1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 ;; Boston, MA 02110-1301, USA.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_EH_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
51 (UNSPEC_ADDRESS_FIRST 100)
55 ;; For MIPS Paired-Singled Floating Point Instructions.
57 (UNSPEC_MOVE_TF_PS 200)
60 ;; MIPS64/MIPS32R2 alnv.ps
63 ;; MIPS-3D instructions
67 (UNSPEC_CVT_PW_PS 205)
68 (UNSPEC_CVT_PS_PW 206)
75 (UNSPEC_SINGLE_CC 212)
77 ;; MIPS DSP ASE Revision 0.98 3/24/2005
85 (UNSPEC_RADDU_W_QB 307)
87 (UNSPEC_PRECRQ_QB_PH 309)
88 (UNSPEC_PRECRQ_PH_W 310)
89 (UNSPEC_PRECRQ_RS_PH_W 311)
90 (UNSPEC_PRECRQU_S_QB_PH 312)
91 (UNSPEC_PRECEQ_W_PHL 313)
92 (UNSPEC_PRECEQ_W_PHR 314)
93 (UNSPEC_PRECEQU_PH_QBL 315)
94 (UNSPEC_PRECEQU_PH_QBR 316)
95 (UNSPEC_PRECEQU_PH_QBLA 317)
96 (UNSPEC_PRECEQU_PH_QBRA 318)
97 (UNSPEC_PRECEU_PH_QBL 319)
98 (UNSPEC_PRECEU_PH_QBR 320)
99 (UNSPEC_PRECEU_PH_QBLA 321)
100 (UNSPEC_PRECEU_PH_QBRA 322)
106 (UNSPEC_MULEU_S_PH_QBL 328)
107 (UNSPEC_MULEU_S_PH_QBR 329)
108 (UNSPEC_MULQ_RS_PH 330)
109 (UNSPEC_MULEQ_S_W_PHL 331)
110 (UNSPEC_MULEQ_S_W_PHR 332)
111 (UNSPEC_DPAU_H_QBL 333)
112 (UNSPEC_DPAU_H_QBR 334)
113 (UNSPEC_DPSU_H_QBL 335)
114 (UNSPEC_DPSU_H_QBR 336)
115 (UNSPEC_DPAQ_S_W_PH 337)
116 (UNSPEC_DPSQ_S_W_PH 338)
117 (UNSPEC_MULSAQ_S_W_PH 339)
118 (UNSPEC_DPAQ_SA_L_W 340)
119 (UNSPEC_DPSQ_SA_L_W 341)
120 (UNSPEC_MAQ_S_W_PHL 342)
121 (UNSPEC_MAQ_S_W_PHR 343)
122 (UNSPEC_MAQ_SA_W_PHL 344)
123 (UNSPEC_MAQ_SA_W_PHR 345)
131 (UNSPEC_CMPGU_EQ_QB 353)
132 (UNSPEC_CMPGU_LT_QB 354)
133 (UNSPEC_CMPGU_LE_QB 355)
135 (UNSPEC_PACKRL_PH 357)
137 (UNSPEC_EXTR_R_W 359)
138 (UNSPEC_EXTR_RS_W 360)
139 (UNSPEC_EXTR_S_H 361)
149 (include "predicates.md")
150 (include "constraints.md")
152 ;; ....................
156 ;; ....................
158 (define_attr "got" "unset,xgot_high,load"
159 (const_string "unset"))
161 ;; For jal instructions, this attribute is DIRECT when the target address
162 ;; is symbolic and INDIRECT when it is a register.
163 (define_attr "jal" "unset,direct,indirect"
164 (const_string "unset"))
166 ;; This attribute is YES if the instruction is a jal macro (not a
167 ;; real jal instruction).
169 ;; jal is always a macro for o32 and o64 abicalls because it includes an
170 ;; instruction to restore $gp. Direct jals are also macros for -mshared
171 ;; abicalls because they first load the target address into $25.
172 (define_attr "jal_macro" "no,yes"
173 (cond [(eq_attr "jal" "direct")
174 (symbol_ref "TARGET_ABICALLS
175 && (TARGET_OLDABI || !TARGET_ABSOLUTE_ABICALLS)")
176 (eq_attr "jal" "indirect")
177 (symbol_ref "TARGET_ABICALLS && TARGET_OLDABI")]
178 (const_string "no")))
180 ;; Classification of each insn.
181 ;; branch conditional branch
182 ;; jump unconditional jump
183 ;; call unconditional call
184 ;; load load instruction(s)
185 ;; fpload floating point load
186 ;; fpidxload floating point indexed load
187 ;; store store instruction(s)
188 ;; fpstore floating point store
189 ;; fpidxstore floating point indexed store
190 ;; prefetch memory prefetch (register + offset)
191 ;; prefetchx memory indexed prefetch (register + register)
192 ;; condmove conditional moves
193 ;; xfer transfer to/from coprocessor
194 ;; mthilo transfer to hi/lo registers
195 ;; mfhilo transfer from hi/lo registers
196 ;; const load constant
197 ;; arith integer arithmetic and logical instructions
198 ;; shift integer shift instructions
199 ;; slt set less than instructions
200 ;; clz the clz and clo instructions
201 ;; trap trap if instructions
202 ;; imul integer multiply 2 operands
203 ;; imul3 integer multiply 3 operands
204 ;; imadd integer multiply-add
205 ;; idiv integer divide
206 ;; fmove floating point register move
207 ;; fadd floating point add/subtract
208 ;; fmul floating point multiply
209 ;; fmadd floating point multiply-add
210 ;; fdiv floating point divide
211 ;; frdiv floating point reciprocal divide
212 ;; frdiv1 floating point reciprocal divide step 1
213 ;; frdiv2 floating point reciprocal divide step 2
214 ;; fabs floating point absolute value
215 ;; fneg floating point negation
216 ;; fcmp floating point compare
217 ;; fcvt floating point convert
218 ;; fsqrt floating point square root
219 ;; frsqrt floating point reciprocal square root
220 ;; frsqrt1 floating point reciprocal square root step1
221 ;; frsqrt2 floating point reciprocal square root step2
222 ;; multi multiword sequence (or user asm statements)
225 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
226 (cond [(eq_attr "jal" "!unset") (const_string "call")
227 (eq_attr "got" "load") (const_string "load")]
228 (const_string "unknown")))
230 ;; Main data type used by the insn
231 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
232 (const_string "unknown"))
234 ;; Mode for conversion types (fcvt)
235 ;; I2S integer to float single (SI/DI to SF)
236 ;; I2D integer to float double (SI/DI to DF)
237 ;; S2I float to integer (SF to SI/DI)
238 ;; D2I float to integer (DF to SI/DI)
239 ;; D2S double to float single
240 ;; S2D float single to double
242 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
243 (const_string "unknown"))
245 ;; Is this an extended instruction in mips16 mode?
246 (define_attr "extended_mips16" "no,yes"
249 ;; Length of instruction in bytes.
250 (define_attr "length" ""
251 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
252 ;; If a branch is outside this range, we have a choice of two
253 ;; sequences. For PIC, an out-of-range branch like:
258 ;; becomes the equivalent of:
267 ;; where the load address can be up to three instructions long
270 ;; The non-PIC case is similar except that we use a direct
271 ;; jump instead of an la/jr pair. Since the target of this
272 ;; jump is an absolute 28-bit bit address (the other bits
273 ;; coming from the address of the delay slot) this form cannot
274 ;; cross a 256MB boundary. We could provide the option of
275 ;; using la/jr in this case too, but we do not do so at
278 ;; Note that this value does not account for the delay slot
279 ;; instruction, whose length is added separately. If the RTL
280 ;; pattern has no explicit delay slot, mips_adjust_insn_length
281 ;; will add the length of the implicit nop. The values for
282 ;; forward and backward branches will be different as well.
283 (eq_attr "type" "branch")
284 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
285 (le (minus (pc) (match_dup 1)) (const_int 131068)))
287 (ne (symbol_ref "flag_pic") (const_int 0))
291 (eq_attr "got" "load")
293 (eq_attr "got" "xgot_high")
296 (eq_attr "type" "const")
297 (symbol_ref "mips_const_insns (operands[1]) * 4")
298 (eq_attr "type" "load,fpload")
299 (symbol_ref "mips_fetch_insns (operands[1]) * 4")
300 (eq_attr "type" "store,fpstore")
301 (symbol_ref "mips_fetch_insns (operands[0]) * 4")
303 ;; In the worst case, a call macro will take 8 instructions:
305 ;; lui $25,%call_hi(FOO)
307 ;; lw $25,%call_lo(FOO)($25)
313 (eq_attr "jal_macro" "yes")
316 (and (eq_attr "extended_mips16" "yes")
317 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
320 ;; Various VR4120 errata require a nop to be inserted after a macc
321 ;; instruction. The assembler does this for us, so account for
322 ;; the worst-case length here.
323 (and (eq_attr "type" "imadd")
324 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
327 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
328 ;; the result of the second one is missed. The assembler should work
329 ;; around this by inserting a nop after the first dmult.
330 (and (eq_attr "type" "imul,imul3")
331 (and (eq_attr "mode" "DI")
332 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
335 (eq_attr "type" "idiv")
336 (symbol_ref "mips_idiv_insns () * 4")
339 ;; Attribute describing the processor. This attribute must match exactly
340 ;; with the processor_type enumeration in mips.h.
342 "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
343 (const (symbol_ref "mips_tune")))
345 ;; The type of hardware hazard associated with this instruction.
346 ;; DELAY means that the next instruction cannot read the result
347 ;; of this one. HILO means that the next two instructions cannot
348 ;; write to HI or LO.
349 (define_attr "hazard" "none,delay,hilo"
350 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
351 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
352 (const_string "delay")
354 (and (eq_attr "type" "xfer")
355 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
356 (const_string "delay")
358 (and (eq_attr "type" "fcmp")
359 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
360 (const_string "delay")
362 ;; The r4000 multiplication patterns include an mflo instruction.
363 (and (eq_attr "type" "imul")
364 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
365 (const_string "hilo")
367 (and (eq_attr "type" "mfhilo")
368 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
369 (const_string "hilo")]
370 (const_string "none")))
372 ;; Is it a single instruction?
373 (define_attr "single_insn" "no,yes"
374 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
376 ;; Can the instruction be put into a delay slot?
377 (define_attr "can_delay" "no,yes"
378 (if_then_else (and (eq_attr "type" "!branch,call,jump")
379 (and (eq_attr "hazard" "none")
380 (eq_attr "single_insn" "yes")))
382 (const_string "no")))
384 ;; Attribute defining whether or not we can use the branch-likely instructions
385 (define_attr "branch_likely" "no,yes"
387 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
389 (const_string "no"))))
391 ;; True if an instruction might assign to hi or lo when reloaded.
392 ;; This is used by the TUNE_MACC_CHAINS code.
393 (define_attr "may_clobber_hilo" "no,yes"
394 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
396 (const_string "no")))
398 ;; Describe a user's asm statement.
399 (define_asm_attributes
400 [(set_attr "type" "multi")
401 (set_attr "can_delay" "no")])
403 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
404 ;; from the same template.
405 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
407 ;; This mode macro allows :P to be used for patterns that operate on
408 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
409 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
411 ;; This mode macro allows :MOVECC to be used anywhere that a
412 ;; conditional-move-type condition is needed.
413 (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
415 ;; This mode macro allows the QI and HI extension patterns to be defined from
416 ;; the same template.
417 (define_mode_macro SHORT [QI HI])
419 ;; This mode macro allows :ANYF to be used wherever a scalar or vector
420 ;; floating-point mode is allowed.
421 (define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
422 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
423 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
425 ;; Like ANYF, but only applies to scalar modes.
426 (define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
427 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
429 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
430 ;; 32-bit version and "dsubu" in the 64-bit version.
431 (define_mode_attr d [(SI "") (DI "d")])
433 ;; This attribute gives the length suffix for a sign- or zero-extension
435 (define_mode_attr size [(QI "b") (HI "h")])
437 ;; This attributes gives the mode mask of a SHORT.
438 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
440 ;; Mode attributes for GPR loads and stores.
441 (define_mode_attr load [(SI "lw") (DI "ld")])
442 (define_mode_attr store [(SI "sw") (DI "sd")])
444 ;; Similarly for MIPS IV indexed FPR loads and stores.
445 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
446 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
448 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
449 ;; are different. Some forms of unextended addiu have an 8-bit immediate
450 ;; field but the equivalent daddiu has only a 5-bit field.
451 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
453 ;; This attribute gives the best constraint to use for registers of
455 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
457 ;; This attribute gives the format suffix for floating-point operations.
458 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
460 ;; This attribute gives the upper-case mode name for one unit of a
461 ;; floating-point mode.
462 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
464 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
466 ;; In certain cases, div.s and div.ps may have a rounding error
467 ;; and/or wrong inexact flag.
469 ;; Therefore, we only allow div.s if not working around SB-1 rev2
470 ;; errata or if a slight loss of precision is OK.
471 (define_mode_attr divide_condition
472 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
473 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
475 ; This attribute gives the condition for which sqrt instructions exist.
476 (define_mode_attr sqrt_condition
477 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
479 ; This attribute gives the condition for which recip and rsqrt instructions
481 (define_mode_attr recip_condition
482 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
484 ;; This code macro allows all branch instructions to be generated from
485 ;; a single define_expand template.
486 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
487 eq ne gt ge lt le gtu geu ltu leu])
489 ;; This code macro allows signed and unsigned widening multiplications
490 ;; to use the same template.
491 (define_code_macro any_extend [sign_extend zero_extend])
493 ;; This code macro allows the three shift instructions to be generated
494 ;; from the same template.
495 (define_code_macro any_shift [ashift ashiftrt lshiftrt])
497 ;; This code macro allows all native floating-point comparisons to be
498 ;; generated from the same template.
499 (define_code_macro fcond [unordered uneq unlt unle eq lt le])
501 ;; This code macro is used for comparisons that can be implemented
502 ;; by swapping the operands.
503 (define_code_macro swapped_fcond [ge gt unge ungt])
505 ;; <u> expands to an empty string when doing a signed operation and
506 ;; "u" when doing an unsigned operation.
507 (define_code_attr u [(sign_extend "") (zero_extend "u")])
509 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
510 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
512 ;; <optab> expands to the name of the optab for a particular code.
513 (define_code_attr optab [(ashift "ashl")
517 ;; <insn> expands to the name of the insn that implements a particular code.
518 (define_code_attr insn [(ashift "sll")
522 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
523 (define_code_attr fcond [(unordered "un")
531 ;; Similar, but for swapped conditions.
532 (define_code_attr swapped_fcond [(ge "le")
537 ;; .........................
539 ;; Branch, call and jump delay slots
541 ;; .........................
543 (define_delay (and (eq_attr "type" "branch")
544 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
545 [(eq_attr "can_delay" "yes")
547 (and (eq_attr "branch_likely" "yes")
548 (eq_attr "can_delay" "yes"))])
550 (define_delay (eq_attr "type" "jump")
551 [(eq_attr "can_delay" "yes")
555 (define_delay (and (eq_attr "type" "call")
556 (eq_attr "jal_macro" "no"))
557 [(eq_attr "can_delay" "yes")
561 ;; Pipeline descriptions.
563 ;; generic.md provides a fallback for processors without a specific
564 ;; pipeline description. It is derived from the old define_function_unit
565 ;; version and uses the "alu" and "imuldiv" units declared below.
567 ;; Some of the processor-specific files are also derived from old
568 ;; define_function_unit descriptions and simply override the parts of
569 ;; generic.md that don't apply. The other processor-specific files
570 ;; are self-contained.
571 (define_automaton "alu,imuldiv")
573 (define_cpu_unit "alu" "alu")
574 (define_cpu_unit "imuldiv" "imuldiv")
593 (include "generic.md")
596 ;; ....................
600 ;; ....................
604 [(trap_if (const_int 1) (const_int 0))]
607 if (ISA_HAS_COND_TRAP)
609 else if (TARGET_MIPS16)
614 [(set_attr "type" "trap")])
616 (define_expand "conditional_trap"
617 [(trap_if (match_operator 0 "comparison_operator"
618 [(match_dup 2) (match_dup 3)])
619 (match_operand 1 "const_int_operand"))]
622 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
623 && operands[1] == const0_rtx)
625 mips_gen_conditional_trap (operands);
632 (define_insn "*conditional_trap<mode>"
633 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
634 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
635 (match_operand:GPR 2 "arith_operand" "dI")])
639 [(set_attr "type" "trap")])
642 ;; ....................
646 ;; ....................
649 (define_insn "add<mode>3"
650 [(set (match_operand:ANYF 0 "register_operand" "=f")
651 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
652 (match_operand:ANYF 2 "register_operand" "f")))]
654 "add.<fmt>\t%0,%1,%2"
655 [(set_attr "type" "fadd")
656 (set_attr "mode" "<UNITMODE>")])
658 (define_expand "add<mode>3"
659 [(set (match_operand:GPR 0 "register_operand")
660 (plus:GPR (match_operand:GPR 1 "register_operand")
661 (match_operand:GPR 2 "arith_operand")))]
664 (define_insn "*add<mode>3"
665 [(set (match_operand:GPR 0 "register_operand" "=d,d")
666 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
667 (match_operand:GPR 2 "arith_operand" "d,Q")))]
672 [(set_attr "type" "arith")
673 (set_attr "mode" "<MODE>")])
675 ;; We need to recognize MIPS16 stack pointer additions explicitly, since
676 ;; we don't have a constraint for $sp. These insns will be generated by
677 ;; the save_restore_insns functions.
679 (define_insn "*add<mode>3_sp1"
681 (plus:GPR (reg:GPR 29)
682 (match_operand:GPR 0 "const_arith_operand" "")))]
685 [(set_attr "type" "arith")
686 (set_attr "mode" "<MODE>")
687 (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")
691 (define_insn "*add<mode>3_sp2"
692 [(set (match_operand:GPR 0 "register_operand" "=d")
693 (plus:GPR (reg:GPR 29)
694 (match_operand:GPR 1 "const_arith_operand" "")))]
697 [(set_attr "type" "arith")
698 (set_attr "mode" "<MODE>")
699 (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4")
703 (define_insn "*add<mode>3_mips16"
704 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
705 (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")
706 (match_operand:GPR 2 "arith_operand" "Q,O,d")))]
712 [(set_attr "type" "arith")
713 (set_attr "mode" "<MODE>")
714 (set_attr_alternative "length"
715 [(if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
718 (if_then_else (match_operand 2 "m16_simm4_1")
724 ;; On the mips16, we can sometimes split an add of a constant which is
725 ;; a 4 byte instruction into two adds which are both 2 byte
726 ;; instructions. There are two cases: one where we are adding a
727 ;; constant plus a register to another register, and one where we are
728 ;; simply adding a constant to a register.
731 [(set (match_operand:SI 0 "register_operand")
732 (plus:SI (match_dup 0)
733 (match_operand:SI 1 "const_int_operand")))]
734 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
735 && REG_P (operands[0])
736 && M16_REG_P (REGNO (operands[0]))
737 && GET_CODE (operands[1]) == CONST_INT
738 && ((INTVAL (operands[1]) > 0x7f
739 && INTVAL (operands[1]) <= 0x7f + 0x7f)
740 || (INTVAL (operands[1]) < - 0x80
741 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
742 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
743 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
745 HOST_WIDE_INT val = INTVAL (operands[1]);
749 operands[1] = GEN_INT (0x7f);
750 operands[2] = GEN_INT (val - 0x7f);
754 operands[1] = GEN_INT (- 0x80);
755 operands[2] = GEN_INT (val + 0x80);
760 [(set (match_operand:SI 0 "register_operand")
761 (plus:SI (match_operand:SI 1 "register_operand")
762 (match_operand:SI 2 "const_int_operand")))]
763 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
764 && REG_P (operands[0])
765 && M16_REG_P (REGNO (operands[0]))
766 && REG_P (operands[1])
767 && M16_REG_P (REGNO (operands[1]))
768 && REGNO (operands[0]) != REGNO (operands[1])
769 && GET_CODE (operands[2]) == CONST_INT
770 && ((INTVAL (operands[2]) > 0x7
771 && INTVAL (operands[2]) <= 0x7 + 0x7f)
772 || (INTVAL (operands[2]) < - 0x8
773 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
774 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
775 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
777 HOST_WIDE_INT val = INTVAL (operands[2]);
781 operands[2] = GEN_INT (0x7);
782 operands[3] = GEN_INT (val - 0x7);
786 operands[2] = GEN_INT (- 0x8);
787 operands[3] = GEN_INT (val + 0x8);
792 [(set (match_operand:DI 0 "register_operand")
793 (plus:DI (match_dup 0)
794 (match_operand:DI 1 "const_int_operand")))]
795 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
796 && REG_P (operands[0])
797 && M16_REG_P (REGNO (operands[0]))
798 && GET_CODE (operands[1]) == CONST_INT
799 && ((INTVAL (operands[1]) > 0xf
800 && INTVAL (operands[1]) <= 0xf + 0xf)
801 || (INTVAL (operands[1]) < - 0x10
802 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
803 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
804 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
806 HOST_WIDE_INT val = INTVAL (operands[1]);
810 operands[1] = GEN_INT (0xf);
811 operands[2] = GEN_INT (val - 0xf);
815 operands[1] = GEN_INT (- 0x10);
816 operands[2] = GEN_INT (val + 0x10);
821 [(set (match_operand:DI 0 "register_operand")
822 (plus:DI (match_operand:DI 1 "register_operand")
823 (match_operand:DI 2 "const_int_operand")))]
824 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
825 && REG_P (operands[0])
826 && M16_REG_P (REGNO (operands[0]))
827 && REG_P (operands[1])
828 && M16_REG_P (REGNO (operands[1]))
829 && REGNO (operands[0]) != REGNO (operands[1])
830 && GET_CODE (operands[2]) == CONST_INT
831 && ((INTVAL (operands[2]) > 0x7
832 && INTVAL (operands[2]) <= 0x7 + 0xf)
833 || (INTVAL (operands[2]) < - 0x8
834 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
835 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
836 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
838 HOST_WIDE_INT val = INTVAL (operands[2]);
842 operands[2] = GEN_INT (0x7);
843 operands[3] = GEN_INT (val - 0x7);
847 operands[2] = GEN_INT (- 0x8);
848 operands[3] = GEN_INT (val + 0x8);
852 (define_insn "*addsi3_extended"
853 [(set (match_operand:DI 0 "register_operand" "=d,d")
855 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
856 (match_operand:SI 2 "arith_operand" "d,Q"))))]
857 "TARGET_64BIT && !TARGET_MIPS16"
861 [(set_attr "type" "arith")
862 (set_attr "mode" "SI")])
864 ;; Split this insn so that the addiu splitters can have a crack at it.
865 ;; Use a conservative length estimate until the split.
866 (define_insn_and_split "*addsi3_extended_mips16"
867 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
869 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
870 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
871 "TARGET_64BIT && TARGET_MIPS16"
873 "&& reload_completed"
874 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
875 { operands[3] = gen_lowpart (SImode, operands[0]); }
876 [(set_attr "type" "arith")
877 (set_attr "mode" "SI")
878 (set_attr "extended_mips16" "yes")])
881 ;; ....................
885 ;; ....................
888 (define_insn "sub<mode>3"
889 [(set (match_operand:ANYF 0 "register_operand" "=f")
890 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
891 (match_operand:ANYF 2 "register_operand" "f")))]
893 "sub.<fmt>\t%0,%1,%2"
894 [(set_attr "type" "fadd")
895 (set_attr "mode" "<UNITMODE>")])
897 (define_insn "sub<mode>3"
898 [(set (match_operand:GPR 0 "register_operand" "=d")
899 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
900 (match_operand:GPR 2 "register_operand" "d")))]
903 [(set_attr "type" "arith")
904 (set_attr "mode" "<MODE>")])
906 (define_insn "*subsi3_extended"
907 [(set (match_operand:DI 0 "register_operand" "=d")
909 (minus:SI (match_operand:SI 1 "register_operand" "d")
910 (match_operand:SI 2 "register_operand" "d"))))]
913 [(set_attr "type" "arith")
914 (set_attr "mode" "DI")])
917 ;; ....................
921 ;; ....................
924 (define_expand "mul<mode>3"
925 [(set (match_operand:SCALARF 0 "register_operand")
926 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
927 (match_operand:SCALARF 2 "register_operand")))]
931 (define_insn "*mul<mode>3"
932 [(set (match_operand:SCALARF 0 "register_operand" "=f")
933 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
934 (match_operand:SCALARF 2 "register_operand" "f")))]
935 "!TARGET_4300_MUL_FIX"
936 "mul.<fmt>\t%0,%1,%2"
937 [(set_attr "type" "fmul")
938 (set_attr "mode" "<MODE>")])
940 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
941 ;; operands may corrupt immediately following multiplies. This is a
942 ;; simple fix to insert NOPs.
944 (define_insn "*mul<mode>3_r4300"
945 [(set (match_operand:SCALARF 0 "register_operand" "=f")
946 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
947 (match_operand:SCALARF 2 "register_operand" "f")))]
948 "TARGET_4300_MUL_FIX"
949 "mul.<fmt>\t%0,%1,%2\;nop"
950 [(set_attr "type" "fmul")
951 (set_attr "mode" "<MODE>")
952 (set_attr "length" "8")])
954 (define_insn "mulv2sf3"
955 [(set (match_operand:V2SF 0 "register_operand" "=f")
956 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
957 (match_operand:V2SF 2 "register_operand" "f")))]
958 "TARGET_PAIRED_SINGLE_FLOAT"
960 [(set_attr "type" "fmul")
961 (set_attr "mode" "SF")])
963 ;; The original R4000 has a cpu bug. If a double-word or a variable
964 ;; shift executes while an integer multiplication is in progress, the
965 ;; shift may give an incorrect result. Avoid this by keeping the mflo
966 ;; with the mult on the R4000.
968 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
969 ;; (also valid for MIPS R4000MC processors):
971 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
972 ;; this errata description.
973 ;; The following code sequence causes the R4000 to incorrectly
974 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
975 ;; instruction. If the dsra32 instruction is executed during an
976 ;; integer multiply, the dsra32 will only shift by the amount in
977 ;; specified in the instruction rather than the amount plus 32
979 ;; instruction 1: mult rs,rt integer multiply
980 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
981 ;; right arithmetic + 32
982 ;; Workaround: A dsra32 instruction placed after an integer
983 ;; multiply should not be one of the 11 instructions after the
984 ;; multiply instruction."
988 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
989 ;; the following description.
990 ;; All extended shifts (shift by n+32) and variable shifts (32 and
991 ;; 64-bit versions) may produce incorrect results under the
992 ;; following conditions:
993 ;; 1) An integer multiply is currently executing
994 ;; 2) These types of shift instructions are executed immediately
995 ;; following an integer divide instruction.
997 ;; 1) Make sure no integer multiply is running wihen these
998 ;; instruction are executed. If this cannot be predicted at
999 ;; compile time, then insert a "mfhi" to R0 instruction
1000 ;; immediately after the integer multiply instruction. This
1001 ;; will cause the integer multiply to complete before the shift
1003 ;; 2) Separate integer divide and these two classes of shift
1004 ;; instructions by another instruction or a noop."
1006 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1009 (define_expand "mul<mode>3"
1010 [(set (match_operand:GPR 0 "register_operand")
1011 (mult:GPR (match_operand:GPR 1 "register_operand")
1012 (match_operand:GPR 2 "register_operand")))]
1015 if (GENERATE_MULT3_<MODE>)
1016 emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2]));
1017 else if (!TARGET_FIX_R4000)
1018 emit_insn (gen_mul<mode>3_internal (operands[0], operands[1],
1021 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1025 (define_insn "mulsi3_mult3"
1026 [(set (match_operand:SI 0 "register_operand" "=d,l")
1027 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1028 (match_operand:SI 2 "register_operand" "d,d")))
1029 (clobber (match_scratch:SI 3 "=h,h"))
1030 (clobber (match_scratch:SI 4 "=l,X"))]
1033 if (which_alternative == 1)
1034 return "mult\t%1,%2";
1043 return "mul\t%0,%1,%2";
1044 return "mult\t%0,%1,%2";
1046 [(set_attr "type" "imul3,imul")
1047 (set_attr "mode" "SI")])
1049 (define_insn "muldi3_mult3"
1050 [(set (match_operand:DI 0 "register_operand" "=d")
1051 (mult:DI (match_operand:DI 1 "register_operand" "d")
1052 (match_operand:DI 2 "register_operand" "d")))
1053 (clobber (match_scratch:DI 3 "=h"))
1054 (clobber (match_scratch:DI 4 "=l"))]
1055 "TARGET_64BIT && GENERATE_MULT3_DI"
1057 [(set_attr "type" "imul3")
1058 (set_attr "mode" "DI")])
1060 ;; If a register gets allocated to LO, and we spill to memory, the reload
1061 ;; will include a move from LO to a GPR. Merge it into the multiplication
1062 ;; if it can set the GPR directly.
1065 ;; Operand 1: GPR (1st multiplication operand)
1066 ;; Operand 2: GPR (2nd multiplication operand)
1068 ;; Operand 4: GPR (destination)
1071 [(set (match_operand:SI 0 "register_operand")
1072 (mult:SI (match_operand:SI 1 "register_operand")
1073 (match_operand:SI 2 "register_operand")))
1074 (clobber (match_operand:SI 3 "register_operand"))
1075 (clobber (scratch:SI))])
1076 (set (match_operand:SI 4 "register_operand")
1077 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1078 "GENERATE_MULT3_SI && peep2_reg_dead_p (2, operands[0])"
1081 (mult:SI (match_dup 1)
1083 (clobber (match_dup 3))
1084 (clobber (match_dup 0))])])
1086 (define_insn "mul<mode>3_internal"
1087 [(set (match_operand:GPR 0 "register_operand" "=l")
1088 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1089 (match_operand:GPR 2 "register_operand" "d")))
1090 (clobber (match_scratch:GPR 3 "=h"))]
1093 [(set_attr "type" "imul")
1094 (set_attr "mode" "<MODE>")])
1096 (define_insn "mul<mode>3_r4000"
1097 [(set (match_operand:GPR 0 "register_operand" "=d")
1098 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1099 (match_operand:GPR 2 "register_operand" "d")))
1100 (clobber (match_scratch:GPR 3 "=h"))
1101 (clobber (match_scratch:GPR 4 "=l"))]
1103 "<d>mult\t%1,%2\;mflo\t%0"
1104 [(set_attr "type" "imul")
1105 (set_attr "mode" "<MODE>")
1106 (set_attr "length" "8")])
1108 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1109 ;; of "mult; mflo". They have the same latency, but the first form gives
1110 ;; us an extra cycle to compute the operands.
1113 ;; Operand 1: GPR (1st multiplication operand)
1114 ;; Operand 2: GPR (2nd multiplication operand)
1116 ;; Operand 4: GPR (destination)
1119 [(set (match_operand:SI 0 "register_operand")
1120 (mult:SI (match_operand:SI 1 "register_operand")
1121 (match_operand:SI 2 "register_operand")))
1122 (clobber (match_operand:SI 3 "register_operand"))])
1123 (set (match_operand:SI 4 "register_operand")
1124 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1125 "ISA_HAS_MACC && !GENERATE_MULT3_SI"
1130 (plus:SI (mult:SI (match_dup 1)
1134 (plus:SI (mult:SI (match_dup 1)
1137 (clobber (match_dup 3))])])
1139 ;; Multiply-accumulate patterns
1141 ;; For processors that can copy the output to a general register:
1143 ;; The all-d alternative is needed because the combiner will find this
1144 ;; pattern and then register alloc/reload will move registers around to
1145 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1147 ;; The last alternative should be made slightly less desirable, but adding
1148 ;; "?" to the constraint is too strong, and causes values to be loaded into
1149 ;; LO even when that's more costly. For now, using "*d" mostly does the
1151 (define_insn "*mul_acc_si"
1152 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1153 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1154 (match_operand:SI 2 "register_operand" "d,d,d"))
1155 (match_operand:SI 3 "register_operand" "0,l,*d")))
1156 (clobber (match_scratch:SI 4 "=h,h,h"))
1157 (clobber (match_scratch:SI 5 "=X,3,l"))
1158 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1160 || ISA_HAS_MADD_MSUB)
1163 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1164 if (which_alternative == 2)
1166 if (ISA_HAS_MADD_MSUB && which_alternative != 0)
1168 return madd[which_alternative];
1170 [(set_attr "type" "imadd,imadd,multi")
1171 (set_attr "mode" "SI")
1172 (set_attr "length" "4,4,8")])
1174 ;; Split the above insn if we failed to get LO allocated.
1176 [(set (match_operand:SI 0 "register_operand")
1177 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1178 (match_operand:SI 2 "register_operand"))
1179 (match_operand:SI 3 "register_operand")))
1180 (clobber (match_scratch:SI 4))
1181 (clobber (match_scratch:SI 5))
1182 (clobber (match_scratch:SI 6))]
1183 "reload_completed && !TARGET_DEBUG_D_MODE
1184 && GP_REG_P (true_regnum (operands[0]))
1185 && GP_REG_P (true_regnum (operands[3]))"
1186 [(parallel [(set (match_dup 6)
1187 (mult:SI (match_dup 1) (match_dup 2)))
1188 (clobber (match_dup 4))
1189 (clobber (match_dup 5))])
1190 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1193 ;; Splitter to copy result of MADD to a general register
1195 [(set (match_operand:SI 0 "register_operand")
1196 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1197 (match_operand:SI 2 "register_operand"))
1198 (match_operand:SI 3 "register_operand")))
1199 (clobber (match_scratch:SI 4))
1200 (clobber (match_scratch:SI 5))
1201 (clobber (match_scratch:SI 6))]
1202 "reload_completed && !TARGET_DEBUG_D_MODE
1203 && GP_REG_P (true_regnum (operands[0]))
1204 && true_regnum (operands[3]) == LO_REGNUM"
1205 [(parallel [(set (match_dup 3)
1206 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1208 (clobber (match_dup 4))
1209 (clobber (match_dup 5))
1210 (clobber (match_dup 6))])
1211 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1214 (define_insn "*macc"
1215 [(set (match_operand:SI 0 "register_operand" "=l,d")
1216 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1217 (match_operand:SI 2 "register_operand" "d,d"))
1218 (match_operand:SI 3 "register_operand" "0,l")))
1219 (clobber (match_scratch:SI 4 "=h,h"))
1220 (clobber (match_scratch:SI 5 "=X,3"))]
1223 if (which_alternative == 1)
1224 return "macc\t%0,%1,%2";
1225 else if (TARGET_MIPS5500)
1226 return "madd\t%1,%2";
1228 /* The VR4130 assumes that there is a two-cycle latency between a macc
1229 that "writes" to $0 and an instruction that reads from it. We avoid
1230 this by assigning to $1 instead. */
1231 return "%[macc\t%@,%1,%2%]";
1233 [(set_attr "type" "imadd")
1234 (set_attr "mode" "SI")])
1236 (define_insn "*msac"
1237 [(set (match_operand:SI 0 "register_operand" "=l,d")
1238 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1239 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1240 (match_operand:SI 3 "register_operand" "d,d"))))
1241 (clobber (match_scratch:SI 4 "=h,h"))
1242 (clobber (match_scratch:SI 5 "=X,1"))]
1245 if (which_alternative == 1)
1246 return "msac\t%0,%2,%3";
1247 else if (TARGET_MIPS5500)
1248 return "msub\t%2,%3";
1250 return "msac\t$0,%2,%3";
1252 [(set_attr "type" "imadd")
1253 (set_attr "mode" "SI")])
1255 ;; An msac-like instruction implemented using negation and a macc.
1256 (define_insn_and_split "*msac_using_macc"
1257 [(set (match_operand:SI 0 "register_operand" "=l,d")
1258 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1259 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1260 (match_operand:SI 3 "register_operand" "d,d"))))
1261 (clobber (match_scratch:SI 4 "=h,h"))
1262 (clobber (match_scratch:SI 5 "=X,1"))
1263 (clobber (match_scratch:SI 6 "=d,d"))]
1264 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1266 "&& reload_completed"
1268 (neg:SI (match_dup 3)))
1271 (plus:SI (mult:SI (match_dup 2)
1274 (clobber (match_dup 4))
1275 (clobber (match_dup 5))])]
1277 [(set_attr "type" "imadd")
1278 (set_attr "length" "8")])
1280 ;; Patterns generated by the define_peephole2 below.
1282 (define_insn "*macc2"
1283 [(set (match_operand:SI 0 "register_operand" "=l")
1284 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1285 (match_operand:SI 2 "register_operand" "d"))
1287 (set (match_operand:SI 3 "register_operand" "=d")
1288 (plus:SI (mult:SI (match_dup 1)
1291 (clobber (match_scratch:SI 4 "=h"))]
1292 "ISA_HAS_MACC && reload_completed"
1294 [(set_attr "type" "imadd")
1295 (set_attr "mode" "SI")])
1297 (define_insn "*msac2"
1298 [(set (match_operand:SI 0 "register_operand" "=l")
1299 (minus:SI (match_dup 0)
1300 (mult:SI (match_operand:SI 1 "register_operand" "d")
1301 (match_operand:SI 2 "register_operand" "d"))))
1302 (set (match_operand:SI 3 "register_operand" "=d")
1303 (minus:SI (match_dup 0)
1304 (mult:SI (match_dup 1)
1306 (clobber (match_scratch:SI 4 "=h"))]
1307 "ISA_HAS_MSAC && reload_completed"
1309 [(set_attr "type" "imadd")
1310 (set_attr "mode" "SI")])
1312 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1316 ;; Operand 1: macc/msac
1318 ;; Operand 3: GPR (destination)
1321 [(set (match_operand:SI 0 "register_operand")
1322 (match_operand:SI 1 "macc_msac_operand"))
1323 (clobber (match_operand:SI 2 "register_operand"))
1324 (clobber (scratch:SI))])
1325 (set (match_operand:SI 3 "register_operand")
1326 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1328 [(parallel [(set (match_dup 0)
1332 (clobber (match_dup 2))])]
1335 ;; When we have a three-address multiplication instruction, it should
1336 ;; be faster to do a separate multiply and add, rather than moving
1337 ;; something into LO in order to use a macc instruction.
1339 ;; This peephole needs a scratch register to cater for the case when one
1340 ;; of the multiplication operands is the same as the destination.
1342 ;; Operand 0: GPR (scratch)
1344 ;; Operand 2: GPR (addend)
1345 ;; Operand 3: GPR (destination)
1346 ;; Operand 4: macc/msac
1348 ;; Operand 6: new multiplication
1349 ;; Operand 7: new addition/subtraction
1351 [(match_scratch:SI 0 "d")
1352 (set (match_operand:SI 1 "register_operand")
1353 (match_operand:SI 2 "register_operand"))
1356 [(set (match_operand:SI 3 "register_operand")
1357 (match_operand:SI 4 "macc_msac_operand"))
1358 (clobber (match_operand:SI 5 "register_operand"))
1359 (clobber (match_dup 1))])]
1361 && true_regnum (operands[1]) == LO_REGNUM
1362 && peep2_reg_dead_p (2, operands[1])
1363 && GP_REG_P (true_regnum (operands[3]))"
1364 [(parallel [(set (match_dup 0)
1366 (clobber (match_dup 5))
1367 (clobber (match_dup 1))])
1371 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1372 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1373 operands[2], operands[0]);
1376 ;; Same as above, except LO is the initial target of the macc.
1378 ;; Operand 0: GPR (scratch)
1380 ;; Operand 2: GPR (addend)
1381 ;; Operand 3: macc/msac
1383 ;; Operand 5: GPR (destination)
1384 ;; Operand 6: new multiplication
1385 ;; Operand 7: new addition/subtraction
1387 [(match_scratch:SI 0 "d")
1388 (set (match_operand:SI 1 "register_operand")
1389 (match_operand:SI 2 "register_operand"))
1393 (match_operand:SI 3 "macc_msac_operand"))
1394 (clobber (match_operand:SI 4 "register_operand"))
1395 (clobber (scratch:SI))])
1397 (set (match_operand:SI 5 "register_operand")
1398 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1399 "GENERATE_MULT3_SI && peep2_reg_dead_p (3, operands[1])"
1400 [(parallel [(set (match_dup 0)
1402 (clobber (match_dup 4))
1403 (clobber (match_dup 1))])
1407 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1408 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1409 operands[2], operands[0]);
1412 (define_insn "*mul_sub_si"
1413 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1414 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1415 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1416 (match_operand:SI 3 "register_operand" "d,d,d"))))
1417 (clobber (match_scratch:SI 4 "=h,h,h"))
1418 (clobber (match_scratch:SI 5 "=X,1,l"))
1419 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1425 [(set_attr "type" "imadd,multi,multi")
1426 (set_attr "mode" "SI")
1427 (set_attr "length" "4,8,8")])
1429 ;; Split the above insn if we failed to get LO allocated.
1431 [(set (match_operand:SI 0 "register_operand")
1432 (minus:SI (match_operand:SI 1 "register_operand")
1433 (mult:SI (match_operand:SI 2 "register_operand")
1434 (match_operand:SI 3 "register_operand"))))
1435 (clobber (match_scratch:SI 4))
1436 (clobber (match_scratch:SI 5))
1437 (clobber (match_scratch:SI 6))]
1438 "reload_completed && !TARGET_DEBUG_D_MODE
1439 && GP_REG_P (true_regnum (operands[0]))
1440 && GP_REG_P (true_regnum (operands[1]))"
1441 [(parallel [(set (match_dup 6)
1442 (mult:SI (match_dup 2) (match_dup 3)))
1443 (clobber (match_dup 4))
1444 (clobber (match_dup 5))])
1445 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1448 ;; Splitter to copy result of MSUB to a general register
1450 [(set (match_operand:SI 0 "register_operand")
1451 (minus:SI (match_operand:SI 1 "register_operand")
1452 (mult:SI (match_operand:SI 2 "register_operand")
1453 (match_operand:SI 3 "register_operand"))))
1454 (clobber (match_scratch:SI 4))
1455 (clobber (match_scratch:SI 5))
1456 (clobber (match_scratch:SI 6))]
1457 "reload_completed && !TARGET_DEBUG_D_MODE
1458 && GP_REG_P (true_regnum (operands[0]))
1459 && true_regnum (operands[1]) == LO_REGNUM"
1460 [(parallel [(set (match_dup 1)
1461 (minus:SI (match_dup 1)
1462 (mult:SI (match_dup 2) (match_dup 3))))
1463 (clobber (match_dup 4))
1464 (clobber (match_dup 5))
1465 (clobber (match_dup 6))])
1466 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1469 (define_insn "*muls"
1470 [(set (match_operand:SI 0 "register_operand" "=l,d")
1471 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1472 (match_operand:SI 2 "register_operand" "d,d"))))
1473 (clobber (match_scratch:SI 3 "=h,h"))
1474 (clobber (match_scratch:SI 4 "=X,l"))]
1479 [(set_attr "type" "imul,imul3")
1480 (set_attr "mode" "SI")])
1482 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1484 (define_expand "<u>mulsidi3"
1486 [(set (match_operand:DI 0 "register_operand")
1487 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1488 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1489 (clobber (scratch:DI))
1490 (clobber (scratch:DI))
1491 (clobber (scratch:DI))])]
1492 "!TARGET_64BIT || !TARGET_FIX_R4000"
1496 if (!TARGET_FIX_R4000)
1497 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1500 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1506 (define_insn "<u>mulsidi3_32bit_internal"
1507 [(set (match_operand:DI 0 "register_operand" "=x")
1508 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1509 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1510 "!TARGET_64BIT && !TARGET_FIX_R4000"
1512 [(set_attr "type" "imul")
1513 (set_attr "mode" "SI")])
1515 (define_insn "<u>mulsidi3_32bit_r4000"
1516 [(set (match_operand:DI 0 "register_operand" "=d")
1517 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1518 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1519 (clobber (match_scratch:DI 3 "=x"))]
1520 "!TARGET_64BIT && TARGET_FIX_R4000"
1521 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1522 [(set_attr "type" "imul")
1523 (set_attr "mode" "SI")
1524 (set_attr "length" "12")])
1526 (define_insn_and_split "*<u>mulsidi3_64bit"
1527 [(set (match_operand:DI 0 "register_operand" "=d")
1528 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1529 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1530 (clobber (match_scratch:DI 3 "=l"))
1531 (clobber (match_scratch:DI 4 "=h"))
1532 (clobber (match_scratch:DI 5 "=d"))]
1533 "TARGET_64BIT && !TARGET_FIX_R4000"
1535 "&& reload_completed"
1539 (mult:SI (match_dup 1)
1543 (mult:DI (any_extend:DI (match_dup 1))
1544 (any_extend:DI (match_dup 2)))
1547 ;; OP5 <- LO, OP0 <- HI
1548 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1549 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1553 (ashift:DI (match_dup 5)
1556 (lshiftrt:DI (match_dup 5)
1559 ;; Shift OP0 into place.
1561 (ashift:DI (match_dup 0)
1564 ;; OR the two halves together
1566 (ior:DI (match_dup 0)
1569 [(set_attr "type" "imul")
1570 (set_attr "mode" "SI")
1571 (set_attr "length" "24")])
1573 (define_insn "*<u>mulsidi3_64bit_parts"
1574 [(set (match_operand:DI 0 "register_operand" "=l")
1576 (mult:SI (match_operand:SI 2 "register_operand" "d")
1577 (match_operand:SI 3 "register_operand" "d"))))
1578 (set (match_operand:DI 1 "register_operand" "=h")
1580 (mult:DI (any_extend:DI (match_dup 2))
1581 (any_extend:DI (match_dup 3)))
1583 "TARGET_64BIT && !TARGET_FIX_R4000"
1585 [(set_attr "type" "imul")
1586 (set_attr "mode" "SI")])
1588 ;; Widening multiply with negation.
1589 (define_insn "*muls<u>_di"
1590 [(set (match_operand:DI 0 "register_operand" "=x")
1593 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1594 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1595 "!TARGET_64BIT && ISA_HAS_MULS"
1597 [(set_attr "type" "imul")
1598 (set_attr "mode" "SI")])
1600 (define_insn "*msac<u>_di"
1601 [(set (match_operand:DI 0 "register_operand" "=x")
1603 (match_operand:DI 3 "register_operand" "0")
1605 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1606 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1607 "!TARGET_64BIT && ISA_HAS_MSAC"
1609 if (TARGET_MIPS5500)
1610 return "msub<u>\t%1,%2";
1612 return "msac<u>\t$0,%1,%2";
1614 [(set_attr "type" "imadd")
1615 (set_attr "mode" "SI")])
1617 ;; _highpart patterns
1619 (define_expand "<su>mulsi3_highpart"
1620 [(set (match_operand:SI 0 "register_operand")
1623 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1624 (any_extend:DI (match_operand:SI 2 "register_operand")))
1626 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1629 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1633 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1638 (define_insn "<su>mulsi3_highpart_internal"
1639 [(set (match_operand:SI 0 "register_operand" "=h")
1642 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1643 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1645 (clobber (match_scratch:SI 3 "=l"))]
1646 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1648 [(set_attr "type" "imul")
1649 (set_attr "mode" "SI")])
1651 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1652 [(set (match_operand:SI 0 "register_operand" "=h,d")
1656 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1657 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1659 (clobber (match_scratch:SI 3 "=l,l"))
1660 (clobber (match_scratch:SI 4 "=X,h"))]
1665 [(set_attr "type" "imul,imul3")
1666 (set_attr "mode" "SI")])
1668 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1669 [(set (match_operand:SI 0 "register_operand" "=h,d")
1674 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1675 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1677 (clobber (match_scratch:SI 3 "=l,l"))
1678 (clobber (match_scratch:SI 4 "=X,h"))]
1682 mulshi<u>\t%0,%1,%2"
1683 [(set_attr "type" "imul,imul3")
1684 (set_attr "mode" "SI")])
1686 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1687 ;; errata MD(0), which says that dmultu does not always produce the
1689 (define_insn "<su>muldi3_highpart"
1690 [(set (match_operand:DI 0 "register_operand" "=h")
1694 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1695 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1697 (clobber (match_scratch:DI 3 "=l"))]
1698 "TARGET_64BIT && !TARGET_FIX_R4000
1699 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1701 [(set_attr "type" "imul")
1702 (set_attr "mode" "DI")])
1704 ;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
1705 ;; instruction. The HI/LO registers are used as a 64 bit accumulator.
1707 (define_insn "madsi"
1708 [(set (match_operand:SI 0 "register_operand" "+l")
1709 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1710 (match_operand:SI 2 "register_operand" "d"))
1712 (clobber (match_scratch:SI 3 "=h"))]
1715 [(set_attr "type" "imadd")
1716 (set_attr "mode" "SI")])
1718 (define_insn "*<su>mul_acc_di"
1719 [(set (match_operand:DI 0 "register_operand" "=x")
1721 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1722 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1723 (match_operand:DI 3 "register_operand" "0")))]
1724 "(TARGET_MAD || ISA_HAS_MACC)
1728 return "mad<u>\t%1,%2";
1729 else if (TARGET_MIPS5500)
1730 return "madd<u>\t%1,%2";
1732 /* See comment in *macc. */
1733 return "%[macc<u>\t%@,%1,%2%]";
1735 [(set_attr "type" "imadd")
1736 (set_attr "mode" "SI")])
1738 ;; Floating point multiply accumulate instructions.
1740 (define_insn "*madd<mode>"
1741 [(set (match_operand:ANYF 0 "register_operand" "=f")
1742 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1743 (match_operand:ANYF 2 "register_operand" "f"))
1744 (match_operand:ANYF 3 "register_operand" "f")))]
1745 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1746 "madd.<fmt>\t%0,%3,%1,%2"
1747 [(set_attr "type" "fmadd")
1748 (set_attr "mode" "<UNITMODE>")])
1750 (define_insn "*msub<mode>"
1751 [(set (match_operand:ANYF 0 "register_operand" "=f")
1752 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1753 (match_operand:ANYF 2 "register_operand" "f"))
1754 (match_operand:ANYF 3 "register_operand" "f")))]
1755 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1756 "msub.<fmt>\t%0,%3,%1,%2"
1757 [(set_attr "type" "fmadd")
1758 (set_attr "mode" "<UNITMODE>")])
1760 (define_insn "*nmadd<mode>"
1761 [(set (match_operand:ANYF 0 "register_operand" "=f")
1762 (neg:ANYF (plus:ANYF
1763 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1764 (match_operand:ANYF 2 "register_operand" "f"))
1765 (match_operand:ANYF 3 "register_operand" "f"))))]
1766 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1767 && HONOR_SIGNED_ZEROS (<MODE>mode)"
1768 "nmadd.<fmt>\t%0,%3,%1,%2"
1769 [(set_attr "type" "fmadd")
1770 (set_attr "mode" "<UNITMODE>")])
1772 (define_insn "*nmadd<mode>_fastmath"
1773 [(set (match_operand:ANYF 0 "register_operand" "=f")
1775 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1776 (match_operand:ANYF 2 "register_operand" "f"))
1777 (match_operand:ANYF 3 "register_operand" "f")))]
1778 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1779 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
1780 "nmadd.<fmt>\t%0,%3,%1,%2"
1781 [(set_attr "type" "fmadd")
1782 (set_attr "mode" "<UNITMODE>")])
1784 (define_insn "*nmsub<mode>"
1785 [(set (match_operand:ANYF 0 "register_operand" "=f")
1786 (neg:ANYF (minus:ANYF
1787 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1788 (match_operand:ANYF 3 "register_operand" "f"))
1789 (match_operand:ANYF 1 "register_operand" "f"))))]
1790 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1791 && HONOR_SIGNED_ZEROS (<MODE>mode)"
1792 "nmsub.<fmt>\t%0,%1,%2,%3"
1793 [(set_attr "type" "fmadd")
1794 (set_attr "mode" "<UNITMODE>")])
1796 (define_insn "*nmsub<mode>_fastmath"
1797 [(set (match_operand:ANYF 0 "register_operand" "=f")
1799 (match_operand:ANYF 1 "register_operand" "f")
1800 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1801 (match_operand:ANYF 3 "register_operand" "f"))))]
1802 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1803 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
1804 "nmsub.<fmt>\t%0,%1,%2,%3"
1805 [(set_attr "type" "fmadd")
1806 (set_attr "mode" "<UNITMODE>")])
1809 ;; ....................
1811 ;; DIVISION and REMAINDER
1813 ;; ....................
1816 (define_expand "div<mode>3"
1817 [(set (match_operand:ANYF 0 "register_operand")
1818 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1819 (match_operand:ANYF 2 "register_operand")))]
1820 "<divide_condition>"
1822 if (const_1_operand (operands[1], <MODE>mode))
1823 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1824 operands[1] = force_reg (<MODE>mode, operands[1]);
1827 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1829 ;; If an mfc1 or dmfc1 happens to access the floating point register
1830 ;; file at the same time a long latency operation (div, sqrt, recip,
1831 ;; sqrt) iterates an intermediate result back through the floating
1832 ;; point register file bypass, then instead returning the correct
1833 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1834 ;; result of the long latency operation.
1836 ;; The workaround is to insert an unconditional 'mov' from/to the
1837 ;; long latency op destination register.
1839 (define_insn "*div<mode>3"
1840 [(set (match_operand:ANYF 0 "register_operand" "=f")
1841 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1842 (match_operand:ANYF 2 "register_operand" "f")))]
1843 "<divide_condition>"
1846 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1848 return "div.<fmt>\t%0,%1,%2";
1850 [(set_attr "type" "fdiv")
1851 (set_attr "mode" "<UNITMODE>")
1852 (set (attr "length")
1853 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1857 (define_insn "*recip<mode>3"
1858 [(set (match_operand:ANYF 0 "register_operand" "=f")
1859 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1860 (match_operand:ANYF 2 "register_operand" "f")))]
1861 "<recip_condition> && flag_unsafe_math_optimizations"
1864 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1866 return "recip.<fmt>\t%0,%2";
1868 [(set_attr "type" "frdiv")
1869 (set_attr "mode" "<UNITMODE>")
1870 (set (attr "length")
1871 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1875 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1876 ;; with negative operands. We use special libgcc functions instead.
1877 (define_insn "divmod<mode>4"
1878 [(set (match_operand:GPR 0 "register_operand" "=l")
1879 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1880 (match_operand:GPR 2 "register_operand" "d")))
1881 (set (match_operand:GPR 3 "register_operand" "=h")
1882 (mod:GPR (match_dup 1)
1884 "!TARGET_FIX_VR4120"
1885 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1886 [(set_attr "type" "idiv")
1887 (set_attr "mode" "<MODE>")])
1889 (define_insn "udivmod<mode>4"
1890 [(set (match_operand:GPR 0 "register_operand" "=l")
1891 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1892 (match_operand:GPR 2 "register_operand" "d")))
1893 (set (match_operand:GPR 3 "register_operand" "=h")
1894 (umod:GPR (match_dup 1)
1897 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1898 [(set_attr "type" "idiv")
1899 (set_attr "mode" "<MODE>")])
1902 ;; ....................
1906 ;; ....................
1908 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1909 ;; "*div[sd]f3" comment for details).
1911 (define_insn "sqrt<mode>2"
1912 [(set (match_operand:ANYF 0 "register_operand" "=f")
1913 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1917 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1919 return "sqrt.<fmt>\t%0,%1";
1921 [(set_attr "type" "fsqrt")
1922 (set_attr "mode" "<UNITMODE>")
1923 (set (attr "length")
1924 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1928 (define_insn "*rsqrt<mode>a"
1929 [(set (match_operand:ANYF 0 "register_operand" "=f")
1930 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1931 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
1932 "<recip_condition> && flag_unsafe_math_optimizations"
1935 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1937 return "rsqrt.<fmt>\t%0,%2";
1939 [(set_attr "type" "frsqrt")
1940 (set_attr "mode" "<UNITMODE>")
1941 (set (attr "length")
1942 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1946 (define_insn "*rsqrt<mode>b"
1947 [(set (match_operand:ANYF 0 "register_operand" "=f")
1948 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1949 (match_operand:ANYF 2 "register_operand" "f"))))]
1950 "<recip_condition> && flag_unsafe_math_optimizations"
1953 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1955 return "rsqrt.<fmt>\t%0,%2";
1957 [(set_attr "type" "frsqrt")
1958 (set_attr "mode" "<UNITMODE>")
1959 (set (attr "length")
1960 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1965 ;; ....................
1969 ;; ....................
1971 ;; Do not use the integer abs macro instruction, since that signals an
1972 ;; exception on -2147483648 (sigh).
1974 (define_insn "abs<mode>2"
1975 [(set (match_operand:ANYF 0 "register_operand" "=f")
1976 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1979 [(set_attr "type" "fabs")
1980 (set_attr "mode" "<UNITMODE>")])
1983 ;; ...................
1985 ;; Count leading zeroes.
1987 ;; ...................
1990 (define_insn "clz<mode>2"
1991 [(set (match_operand:GPR 0 "register_operand" "=d")
1992 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
1995 [(set_attr "type" "clz")
1996 (set_attr "mode" "<MODE>")])
1999 ;; ....................
2001 ;; NEGATION and ONE'S COMPLEMENT
2003 ;; ....................
2005 (define_insn "negsi2"
2006 [(set (match_operand:SI 0 "register_operand" "=d")
2007 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2011 return "neg\t%0,%1";
2013 return "subu\t%0,%.,%1";
2015 [(set_attr "type" "arith")
2016 (set_attr "mode" "SI")])
2018 (define_insn "negdi2"
2019 [(set (match_operand:DI 0 "register_operand" "=d")
2020 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2021 "TARGET_64BIT && !TARGET_MIPS16"
2023 [(set_attr "type" "arith")
2024 (set_attr "mode" "DI")])
2026 (define_insn "neg<mode>2"
2027 [(set (match_operand:ANYF 0 "register_operand" "=f")
2028 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2031 [(set_attr "type" "fneg")
2032 (set_attr "mode" "<UNITMODE>")])
2034 (define_insn "one_cmpl<mode>2"
2035 [(set (match_operand:GPR 0 "register_operand" "=d")
2036 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2040 return "not\t%0,%1";
2042 return "nor\t%0,%.,%1";
2044 [(set_attr "type" "arith")
2045 (set_attr "mode" "<MODE>")])
2048 ;; ....................
2052 ;; ....................
2055 ;; Many of these instructions use trivial define_expands, because we
2056 ;; want to use a different set of constraints when TARGET_MIPS16.
2058 (define_expand "and<mode>3"
2059 [(set (match_operand:GPR 0 "register_operand")
2060 (and:GPR (match_operand:GPR 1 "register_operand")
2061 (match_operand:GPR 2 "uns_arith_operand")))]
2065 operands[2] = force_reg (<MODE>mode, operands[2]);
2068 (define_insn "*and<mode>3"
2069 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2070 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2071 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2076 [(set_attr "type" "arith")
2077 (set_attr "mode" "<MODE>")])
2079 (define_insn "*and<mode>3_mips16"
2080 [(set (match_operand:GPR 0 "register_operand" "=d")
2081 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2082 (match_operand:GPR 2 "register_operand" "d")))]
2085 [(set_attr "type" "arith")
2086 (set_attr "mode" "<MODE>")])
2088 (define_expand "ior<mode>3"
2089 [(set (match_operand:GPR 0 "register_operand")
2090 (ior:GPR (match_operand:GPR 1 "register_operand")
2091 (match_operand:GPR 2 "uns_arith_operand")))]
2095 operands[2] = force_reg (<MODE>mode, operands[2]);
2098 (define_insn "*ior<mode>3"
2099 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2100 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2101 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2106 [(set_attr "type" "arith")
2107 (set_attr "mode" "<MODE>")])
2109 (define_insn "*ior<mode>3_mips16"
2110 [(set (match_operand:GPR 0 "register_operand" "=d")
2111 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2112 (match_operand:GPR 2 "register_operand" "d")))]
2115 [(set_attr "type" "arith")
2116 (set_attr "mode" "<MODE>")])
2118 (define_expand "xor<mode>3"
2119 [(set (match_operand:GPR 0 "register_operand")
2120 (xor:GPR (match_operand:GPR 1 "register_operand")
2121 (match_operand:GPR 2 "uns_arith_operand")))]
2126 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2127 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2128 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2133 [(set_attr "type" "arith")
2134 (set_attr "mode" "<MODE>")])
2137 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2138 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2139 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2145 [(set_attr "type" "arith")
2146 (set_attr "mode" "<MODE>")
2147 (set_attr_alternative "length"
2149 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2154 (define_insn "*nor<mode>3"
2155 [(set (match_operand:GPR 0 "register_operand" "=d")
2156 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2157 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2160 [(set_attr "type" "arith")
2161 (set_attr "mode" "<MODE>")])
2164 ;; ....................
2168 ;; ....................
2172 (define_insn "truncdfsf2"
2173 [(set (match_operand:SF 0 "register_operand" "=f")
2174 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2175 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2177 [(set_attr "type" "fcvt")
2178 (set_attr "cnv_mode" "D2S")
2179 (set_attr "mode" "SF")])
2181 ;; Integer truncation patterns. Truncating SImode values to smaller
2182 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2183 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2184 ;; need to make sure that the lower 32 bits are properly sign-extended
2185 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2186 ;; smaller than SImode is equivalent to two separate truncations:
2189 ;; DI ---> HI == DI ---> SI ---> HI
2190 ;; DI ---> QI == DI ---> SI ---> QI
2192 ;; Step A needs a real instruction but step B does not.
2194 (define_insn "truncdisi2"
2195 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2196 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2201 [(set_attr "type" "shift,store")
2202 (set_attr "mode" "SI")
2203 (set_attr "extended_mips16" "yes,*")])
2205 (define_insn "truncdihi2"
2206 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2207 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2212 [(set_attr "type" "shift,store")
2213 (set_attr "mode" "SI")
2214 (set_attr "extended_mips16" "yes,*")])
2216 (define_insn "truncdiqi2"
2217 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2218 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2223 [(set_attr "type" "shift,store")
2224 (set_attr "mode" "SI")
2225 (set_attr "extended_mips16" "yes,*")])
2227 ;; Combiner patterns to optimize shift/truncate combinations.
2230 [(set (match_operand:SI 0 "register_operand" "=d")
2232 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2233 (match_operand:DI 2 "const_arith_operand" ""))))]
2234 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2236 [(set_attr "type" "shift")
2237 (set_attr "mode" "SI")])
2240 [(set (match_operand:SI 0 "register_operand" "=d")
2241 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2243 "TARGET_64BIT && !TARGET_MIPS16"
2245 [(set_attr "type" "shift")
2246 (set_attr "mode" "SI")])
2249 ;; Combiner patterns for truncate/sign_extend combinations. They use
2250 ;; the shift/truncate patterns above.
2252 (define_insn_and_split ""
2253 [(set (match_operand:SI 0 "register_operand" "=d")
2255 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2256 "TARGET_64BIT && !TARGET_MIPS16"
2258 "&& reload_completed"
2260 (ashift:DI (match_dup 1)
2263 (truncate:SI (ashiftrt:DI (match_dup 2)
2265 { operands[2] = gen_lowpart (DImode, operands[0]); })
2267 (define_insn_and_split ""
2268 [(set (match_operand:SI 0 "register_operand" "=d")
2270 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2271 "TARGET_64BIT && !TARGET_MIPS16"
2273 "&& reload_completed"
2275 (ashift:DI (match_dup 1)
2278 (truncate:SI (ashiftrt:DI (match_dup 2)
2280 { operands[2] = gen_lowpart (DImode, operands[0]); })
2283 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2286 [(set (match_operand:SI 0 "register_operand" "=d")
2287 (zero_extend:SI (truncate:HI
2288 (match_operand:DI 1 "register_operand" "d"))))]
2289 "TARGET_64BIT && !TARGET_MIPS16"
2290 "andi\t%0,%1,0xffff"
2291 [(set_attr "type" "arith")
2292 (set_attr "mode" "SI")])
2295 [(set (match_operand:SI 0 "register_operand" "=d")
2296 (zero_extend:SI (truncate:QI
2297 (match_operand:DI 1 "register_operand" "d"))))]
2298 "TARGET_64BIT && !TARGET_MIPS16"
2300 [(set_attr "type" "arith")
2301 (set_attr "mode" "SI")])
2304 [(set (match_operand:HI 0 "register_operand" "=d")
2305 (zero_extend:HI (truncate:QI
2306 (match_operand:DI 1 "register_operand" "d"))))]
2307 "TARGET_64BIT && !TARGET_MIPS16"
2309 [(set_attr "type" "arith")
2310 (set_attr "mode" "HI")])
2313 ;; ....................
2317 ;; ....................
2321 (define_insn_and_split "zero_extendsidi2"
2322 [(set (match_operand:DI 0 "register_operand" "=d,d")
2323 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2328 "&& reload_completed && REG_P (operands[1])"
2330 (ashift:DI (match_dup 1) (const_int 32)))
2332 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2333 { operands[1] = gen_lowpart (DImode, operands[1]); }
2334 [(set_attr "type" "multi,load")
2335 (set_attr "mode" "DI")
2336 (set_attr "length" "8,*")])
2338 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2339 ;; because of TRULY_NOOP_TRUNCATION.
2341 (define_insn_and_split "*clear_upper32"
2342 [(set (match_operand:DI 0 "register_operand" "=d,d")
2343 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2344 (const_int 4294967295)))]
2347 if (which_alternative == 0)
2350 operands[1] = gen_lowpart (SImode, operands[1]);
2351 return "lwu\t%0,%1";
2353 "&& reload_completed && REG_P (operands[1])"
2355 (ashift:DI (match_dup 1) (const_int 32)))
2357 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2359 [(set_attr "type" "multi,load")
2360 (set_attr "mode" "DI")
2361 (set_attr "length" "8,*")])
2363 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2364 [(set (match_operand:GPR 0 "register_operand")
2365 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2368 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2369 && !memory_operand (operands[1], <SHORT:MODE>mode))
2371 emit_insn (gen_and<GPR:mode>3 (operands[0],
2372 gen_lowpart (<GPR:MODE>mode, operands[1]),
2373 force_reg (<GPR:MODE>mode,
2374 GEN_INT (<SHORT:mask>))));
2379 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2380 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2382 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2385 andi\t%0,%1,<SHORT:mask>
2386 l<SHORT:size>u\t%0,%1"
2387 [(set_attr "type" "arith,load")
2388 (set_attr "mode" "<GPR:MODE>")])
2390 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2391 [(set (match_operand:GPR 0 "register_operand" "=d")
2392 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2394 "ze<SHORT:size>\t%0"
2395 [(set_attr "type" "arith")
2396 (set_attr "mode" "<GPR:MODE>")])
2398 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2399 [(set (match_operand:GPR 0 "register_operand" "=d")
2400 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2402 "l<SHORT:size>u\t%0,%1"
2403 [(set_attr "type" "load")
2404 (set_attr "mode" "<GPR:MODE>")])
2406 (define_expand "zero_extendqihi2"
2407 [(set (match_operand:HI 0 "register_operand")
2408 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2411 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2413 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2419 (define_insn "*zero_extendqihi2"
2420 [(set (match_operand:HI 0 "register_operand" "=d,d")
2421 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2426 [(set_attr "type" "arith,load")
2427 (set_attr "mode" "HI")])
2429 (define_insn "*zero_extendqihi2_mips16"
2430 [(set (match_operand:HI 0 "register_operand" "=d")
2431 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2434 [(set_attr "type" "load")
2435 (set_attr "mode" "HI")])
2438 ;; ....................
2442 ;; ....................
2445 ;; Those for integer source operand are ordered widest source type first.
2447 ;; When TARGET_64BIT, all SImode integer registers should already be in
2448 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2449 ;; therefore get rid of register->register instructions if we constrain
2450 ;; the source to be in the same register as the destination.
2452 ;; The register alternative has type "arith" so that the pre-reload
2453 ;; scheduler will treat it as a move. This reflects what happens if
2454 ;; the register alternative needs a reload.
2455 (define_insn_and_split "extendsidi2"
2456 [(set (match_operand:DI 0 "register_operand" "=d,d")
2457 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2462 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2465 emit_note (NOTE_INSN_DELETED);
2468 [(set_attr "type" "arith,load")
2469 (set_attr "mode" "DI")])
2471 (define_expand "extend<SHORT:mode><GPR:mode>2"
2472 [(set (match_operand:GPR 0 "register_operand")
2473 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2476 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2477 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2478 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2482 l<SHORT:size>\t%0,%1"
2483 [(set_attr "type" "arith,load")
2484 (set_attr "mode" "<GPR:MODE>")])
2486 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2487 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2489 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2490 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2493 l<SHORT:size>\t%0,%1"
2494 "&& reload_completed && REG_P (operands[1])"
2495 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2496 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2498 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2499 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2500 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2502 [(set_attr "type" "arith,load")
2503 (set_attr "mode" "<GPR:MODE>")
2504 (set_attr "length" "8,*")])
2506 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2507 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2509 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2512 se<SHORT:size>\t%0,%1
2513 l<SHORT:size>\t%0,%1"
2514 [(set_attr "type" "arith,load")
2515 (set_attr "mode" "<GPR:MODE>")])
2517 ;; This pattern generates the same code as extendqisi2; split it into
2518 ;; that form after reload.
2519 (define_insn_and_split "extendqihi2"
2520 [(set (match_operand:HI 0 "register_operand" "=d,d")
2521 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2525 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
2526 { operands[0] = gen_lowpart (SImode, operands[0]); }
2527 [(set_attr "type" "arith,load")
2528 (set_attr "mode" "SI")
2529 (set_attr "length" "8,*")])
2531 (define_insn "extendsfdf2"
2532 [(set (match_operand:DF 0 "register_operand" "=f")
2533 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2534 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2536 [(set_attr "type" "fcvt")
2537 (set_attr "cnv_mode" "S2D")
2538 (set_attr "mode" "DF")])
2541 ;; ....................
2545 ;; ....................
2547 (define_expand "fix_truncdfsi2"
2548 [(set (match_operand:SI 0 "register_operand")
2549 (fix:SI (match_operand:DF 1 "register_operand")))]
2550 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2552 if (!ISA_HAS_TRUNC_W)
2554 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2559 (define_insn "fix_truncdfsi2_insn"
2560 [(set (match_operand:SI 0 "register_operand" "=f")
2561 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2562 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2564 [(set_attr "type" "fcvt")
2565 (set_attr "mode" "DF")
2566 (set_attr "cnv_mode" "D2I")
2567 (set_attr "length" "4")])
2569 (define_insn "fix_truncdfsi2_macro"
2570 [(set (match_operand:SI 0 "register_operand" "=f")
2571 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2572 (clobber (match_scratch:DF 2 "=d"))]
2573 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2576 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2578 return "trunc.w.d %0,%1,%2";
2580 [(set_attr "type" "fcvt")
2581 (set_attr "mode" "DF")
2582 (set_attr "cnv_mode" "D2I")
2583 (set_attr "length" "36")])
2585 (define_expand "fix_truncsfsi2"
2586 [(set (match_operand:SI 0 "register_operand")
2587 (fix:SI (match_operand:SF 1 "register_operand")))]
2590 if (!ISA_HAS_TRUNC_W)
2592 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2597 (define_insn "fix_truncsfsi2_insn"
2598 [(set (match_operand:SI 0 "register_operand" "=f")
2599 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2600 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2602 [(set_attr "type" "fcvt")
2603 (set_attr "mode" "SF")
2604 (set_attr "cnv_mode" "S2I")
2605 (set_attr "length" "4")])
2607 (define_insn "fix_truncsfsi2_macro"
2608 [(set (match_operand:SI 0 "register_operand" "=f")
2609 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2610 (clobber (match_scratch:SF 2 "=d"))]
2611 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2614 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2616 return "trunc.w.s %0,%1,%2";
2618 [(set_attr "type" "fcvt")
2619 (set_attr "mode" "SF")
2620 (set_attr "cnv_mode" "S2I")
2621 (set_attr "length" "36")])
2624 (define_insn "fix_truncdfdi2"
2625 [(set (match_operand:DI 0 "register_operand" "=f")
2626 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2627 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2629 [(set_attr "type" "fcvt")
2630 (set_attr "mode" "DF")
2631 (set_attr "cnv_mode" "D2I")
2632 (set_attr "length" "4")])
2635 (define_insn "fix_truncsfdi2"
2636 [(set (match_operand:DI 0 "register_operand" "=f")
2637 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2638 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2640 [(set_attr "type" "fcvt")
2641 (set_attr "mode" "SF")
2642 (set_attr "cnv_mode" "S2I")
2643 (set_attr "length" "4")])
2646 (define_insn "floatsidf2"
2647 [(set (match_operand:DF 0 "register_operand" "=f")
2648 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2649 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2651 [(set_attr "type" "fcvt")
2652 (set_attr "mode" "DF")
2653 (set_attr "cnv_mode" "I2D")
2654 (set_attr "length" "4")])
2657 (define_insn "floatdidf2"
2658 [(set (match_operand:DF 0 "register_operand" "=f")
2659 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2660 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2662 [(set_attr "type" "fcvt")
2663 (set_attr "mode" "DF")
2664 (set_attr "cnv_mode" "I2D")
2665 (set_attr "length" "4")])
2668 (define_insn "floatsisf2"
2669 [(set (match_operand:SF 0 "register_operand" "=f")
2670 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2673 [(set_attr "type" "fcvt")
2674 (set_attr "mode" "SF")
2675 (set_attr "cnv_mode" "I2S")
2676 (set_attr "length" "4")])
2679 (define_insn "floatdisf2"
2680 [(set (match_operand:SF 0 "register_operand" "=f")
2681 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2682 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2684 [(set_attr "type" "fcvt")
2685 (set_attr "mode" "SF")
2686 (set_attr "cnv_mode" "I2S")
2687 (set_attr "length" "4")])
2690 (define_expand "fixuns_truncdfsi2"
2691 [(set (match_operand:SI 0 "register_operand")
2692 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2693 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2695 rtx reg1 = gen_reg_rtx (DFmode);
2696 rtx reg2 = gen_reg_rtx (DFmode);
2697 rtx reg3 = gen_reg_rtx (SImode);
2698 rtx label1 = gen_label_rtx ();
2699 rtx label2 = gen_label_rtx ();
2700 REAL_VALUE_TYPE offset;
2702 real_2expN (&offset, 31);
2704 if (reg1) /* Turn off complaints about unreached code. */
2706 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2707 do_pending_stack_adjust ();
2709 emit_insn (gen_cmpdf (operands[1], reg1));
2710 emit_jump_insn (gen_bge (label1));
2712 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2713 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2714 gen_rtx_LABEL_REF (VOIDmode, label2)));
2717 emit_label (label1);
2718 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2719 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2720 (BITMASK_HIGH, SImode)));
2722 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2723 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2725 emit_label (label2);
2727 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2728 fields, and can't be used for REG_NOTES anyway). */
2729 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2735 (define_expand "fixuns_truncdfdi2"
2736 [(set (match_operand:DI 0 "register_operand")
2737 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2738 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2740 rtx reg1 = gen_reg_rtx (DFmode);
2741 rtx reg2 = gen_reg_rtx (DFmode);
2742 rtx reg3 = gen_reg_rtx (DImode);
2743 rtx label1 = gen_label_rtx ();
2744 rtx label2 = gen_label_rtx ();
2745 REAL_VALUE_TYPE offset;
2747 real_2expN (&offset, 63);
2749 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2750 do_pending_stack_adjust ();
2752 emit_insn (gen_cmpdf (operands[1], reg1));
2753 emit_jump_insn (gen_bge (label1));
2755 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2756 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2757 gen_rtx_LABEL_REF (VOIDmode, label2)));
2760 emit_label (label1);
2761 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2762 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2763 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2765 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2766 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2768 emit_label (label2);
2770 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2771 fields, and can't be used for REG_NOTES anyway). */
2772 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2777 (define_expand "fixuns_truncsfsi2"
2778 [(set (match_operand:SI 0 "register_operand")
2779 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2782 rtx reg1 = gen_reg_rtx (SFmode);
2783 rtx reg2 = gen_reg_rtx (SFmode);
2784 rtx reg3 = gen_reg_rtx (SImode);
2785 rtx label1 = gen_label_rtx ();
2786 rtx label2 = gen_label_rtx ();
2787 REAL_VALUE_TYPE offset;
2789 real_2expN (&offset, 31);
2791 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2792 do_pending_stack_adjust ();
2794 emit_insn (gen_cmpsf (operands[1], reg1));
2795 emit_jump_insn (gen_bge (label1));
2797 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2798 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2799 gen_rtx_LABEL_REF (VOIDmode, label2)));
2802 emit_label (label1);
2803 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2804 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2805 (BITMASK_HIGH, SImode)));
2807 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2808 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2810 emit_label (label2);
2812 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2813 fields, and can't be used for REG_NOTES anyway). */
2814 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2819 (define_expand "fixuns_truncsfdi2"
2820 [(set (match_operand:DI 0 "register_operand")
2821 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2822 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2824 rtx reg1 = gen_reg_rtx (SFmode);
2825 rtx reg2 = gen_reg_rtx (SFmode);
2826 rtx reg3 = gen_reg_rtx (DImode);
2827 rtx label1 = gen_label_rtx ();
2828 rtx label2 = gen_label_rtx ();
2829 REAL_VALUE_TYPE offset;
2831 real_2expN (&offset, 63);
2833 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2834 do_pending_stack_adjust ();
2836 emit_insn (gen_cmpsf (operands[1], reg1));
2837 emit_jump_insn (gen_bge (label1));
2839 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2840 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2841 gen_rtx_LABEL_REF (VOIDmode, label2)));
2844 emit_label (label1);
2845 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2846 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2847 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2849 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2850 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2852 emit_label (label2);
2854 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2855 fields, and can't be used for REG_NOTES anyway). */
2856 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2861 ;; ....................
2865 ;; ....................
2867 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2869 (define_expand "extv"
2870 [(set (match_operand 0 "register_operand")
2871 (sign_extract (match_operand:QI 1 "memory_operand")
2872 (match_operand 2 "immediate_operand")
2873 (match_operand 3 "immediate_operand")))]
2876 if (mips_expand_unaligned_load (operands[0], operands[1],
2877 INTVAL (operands[2]),
2878 INTVAL (operands[3])))
2884 (define_expand "extzv"
2885 [(set (match_operand 0 "register_operand")
2886 (zero_extract (match_operand 1 "nonimmediate_operand")
2887 (match_operand 2 "immediate_operand")
2888 (match_operand 3 "immediate_operand")))]
2891 if (mips_expand_unaligned_load (operands[0], operands[1],
2892 INTVAL (operands[2]),
2893 INTVAL (operands[3])))
2895 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
2897 if (GET_MODE (operands[0]) == DImode)
2898 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
2901 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
2909 (define_insn "extzv<mode>"
2910 [(set (match_operand:GPR 0 "register_operand" "=d")
2911 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
2912 (match_operand:SI 2 "immediate_operand" "I")
2913 (match_operand:SI 3 "immediate_operand" "I")))]
2914 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
2915 "<d>ext\t%0,%1,%3,%2"
2916 [(set_attr "type" "arith")
2917 (set_attr "mode" "<MODE>")])
2920 (define_expand "insv"
2921 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
2922 (match_operand 1 "immediate_operand")
2923 (match_operand 2 "immediate_operand"))
2924 (match_operand 3 "reg_or_0_operand"))]
2927 if (mips_expand_unaligned_store (operands[0], operands[3],
2928 INTVAL (operands[1]),
2929 INTVAL (operands[2])))
2931 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
2933 if (GET_MODE (operands[0]) == DImode)
2934 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
2937 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
2945 (define_insn "insv<mode>"
2946 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
2947 (match_operand:SI 1 "immediate_operand" "I")
2948 (match_operand:SI 2 "immediate_operand" "I"))
2949 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
2950 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
2951 "<d>ins\t%0,%z3,%2,%1"
2952 [(set_attr "type" "arith")
2953 (set_attr "mode" "<MODE>")])
2955 ;; Unaligned word moves generated by the bit field patterns.
2957 ;; As far as the rtl is concerned, both the left-part and right-part
2958 ;; instructions can access the whole field. However, the real operand
2959 ;; refers to just the first or the last byte (depending on endianness).
2960 ;; We therefore use two memory operands to each instruction, one to
2961 ;; describe the rtl effect and one to use in the assembly output.
2963 ;; Operands 0 and 1 are the rtl-level target and source respectively.
2964 ;; This allows us to use the standard length calculations for the "load"
2965 ;; and "store" type attributes.
2967 (define_insn "mov_<load>l"
2968 [(set (match_operand:GPR 0 "register_operand" "=d")
2969 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
2970 (match_operand:QI 2 "memory_operand" "m")]
2974 [(set_attr "type" "load")
2975 (set_attr "mode" "<MODE>")])
2977 (define_insn "mov_<load>r"
2978 [(set (match_operand:GPR 0 "register_operand" "=d")
2979 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
2980 (match_operand:QI 2 "memory_operand" "m")
2981 (match_operand:GPR 3 "register_operand" "0")]
2982 UNSPEC_LOAD_RIGHT))]
2985 [(set_attr "type" "load")
2986 (set_attr "mode" "<MODE>")])
2988 (define_insn "mov_<store>l"
2989 [(set (match_operand:BLK 0 "memory_operand" "=m")
2990 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
2991 (match_operand:QI 2 "memory_operand" "m")]
2992 UNSPEC_STORE_LEFT))]
2995 [(set_attr "type" "store")
2996 (set_attr "mode" "<MODE>")])
2998 (define_insn "mov_<store>r"
2999 [(set (match_operand:BLK 0 "memory_operand" "+m")
3000 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3001 (match_operand:QI 2 "memory_operand" "m")
3003 UNSPEC_STORE_RIGHT))]
3006 [(set_attr "type" "store")
3007 (set_attr "mode" "<MODE>")])
3009 ;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL.
3010 ;; The required value is:
3012 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3014 ;; which translates to:
3016 ;; lui op0,%highest(op1)
3017 ;; daddiu op0,op0,%higher(op1)
3019 ;; daddiu op0,op0,%hi(op1)
3022 ;; The split is deferred until after flow2 to allow the peephole2 below
3024 (define_insn_and_split "*lea_high64"
3025 [(set (match_operand:DI 0 "register_operand" "=d")
3026 (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
3027 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3029 "&& flow2_completed"
3030 [(set (match_dup 0) (high:DI (match_dup 2)))
3031 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3032 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3033 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3034 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3036 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3037 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3039 [(set_attr "length" "20")])
3041 ;; Use a scratch register to reduce the latency of the above pattern
3042 ;; on superscalar machines. The optimized sequence is:
3044 ;; lui op1,%highest(op2)
3046 ;; daddiu op1,op1,%higher(op2)
3048 ;; daddu op1,op1,op0
3050 [(set (match_operand:DI 1 "register_operand")
3051 (high:DI (match_operand:DI 2 "general_symbolic_operand")))
3052 (match_scratch:DI 0 "d")]
3053 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3054 [(set (match_dup 1) (high:DI (match_dup 3)))
3055 (set (match_dup 0) (high:DI (match_dup 4)))
3056 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3057 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3058 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3060 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3061 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3064 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3065 ;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
3066 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3067 ;; used once. We can then use the sequence:
3069 ;; lui op0,%highest(op1)
3071 ;; daddiu op0,op0,%higher(op1)
3072 ;; daddiu op2,op2,%lo(op1)
3074 ;; daddu op0,op0,op2
3076 ;; which takes 4 cycles on most superscalar targets.
3077 (define_insn_and_split "*lea64"
3078 [(set (match_operand:DI 0 "register_operand" "=d")
3079 (match_operand:DI 1 "general_symbolic_operand" ""))
3080 (clobber (match_scratch:DI 2 "=&d"))]
3081 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3083 "&& reload_completed"
3084 [(set (match_dup 0) (high:DI (match_dup 3)))
3085 (set (match_dup 2) (high:DI (match_dup 4)))
3086 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3087 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3088 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3089 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3091 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3092 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3094 [(set_attr "length" "24")])
3096 ;; Insns to fetch a global symbol from a big GOT.
3098 (define_insn_and_split "*xgot_hi<mode>"
3099 [(set (match_operand:P 0 "register_operand" "=d")
3100 (high:P (match_operand:P 1 "global_got_operand" "")))]
3101 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3103 "&& reload_completed"
3104 [(set (match_dup 0) (high:P (match_dup 2)))
3105 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3107 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
3108 operands[3] = pic_offset_table_rtx;
3110 [(set_attr "got" "xgot_high")
3111 (set_attr "mode" "<MODE>")])
3113 (define_insn_and_split "*xgot_lo<mode>"
3114 [(set (match_operand:P 0 "register_operand" "=d")
3115 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3116 (match_operand:P 2 "global_got_operand" "")))]
3117 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3119 "&& reload_completed"
3121 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3122 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_GLOBAL); }
3123 [(set_attr "got" "load")
3124 (set_attr "mode" "<MODE>")])
3126 ;; Insns to fetch a global symbol from a normal GOT.
3128 (define_insn_and_split "*got_disp<mode>"
3129 [(set (match_operand:P 0 "register_operand" "=d")
3130 (match_operand:P 1 "global_got_operand" ""))]
3131 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3133 "&& reload_completed"
3135 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3137 operands[2] = pic_offset_table_rtx;
3138 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
3140 [(set_attr "got" "load")
3141 (set_attr "mode" "<MODE>")])
3143 ;; Insns for loading the high part of a local symbol.
3145 (define_insn_and_split "*got_page<mode>"
3146 [(set (match_operand:P 0 "register_operand" "=d")
3147 (high:P (match_operand:P 1 "local_got_operand" "")))]
3148 "TARGET_EXPLICIT_RELOCS"
3150 "&& reload_completed"
3152 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3154 operands[2] = pic_offset_table_rtx;
3155 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3157 [(set_attr "got" "load")
3158 (set_attr "mode" "<MODE>")])
3160 ;; Lower-level instructions for loading an address from the GOT.
3161 ;; We could use MEMs, but an unspec gives more optimization
3164 (define_insn "load_got<mode>"
3165 [(set (match_operand:P 0 "register_operand" "=d")
3166 (unspec:P [(match_operand:P 1 "register_operand" "d")
3167 (match_operand:P 2 "immediate_operand" "")]
3170 "<load>\t%0,%R2(%1)"
3171 [(set_attr "type" "load")
3172 (set_attr "mode" "<MODE>")
3173 (set_attr "length" "4")])
3175 ;; Instructions for adding the low 16 bits of an address to a register.
3176 ;; Operand 2 is the address: print_operand works out which relocation
3177 ;; should be applied.
3179 (define_insn "*low<mode>"
3180 [(set (match_operand:P 0 "register_operand" "=d")
3181 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3182 (match_operand:P 2 "immediate_operand" "")))]
3184 "<d>addiu\t%0,%1,%R2"
3185 [(set_attr "type" "arith")
3186 (set_attr "mode" "<MODE>")])
3188 (define_insn "*low<mode>_mips16"
3189 [(set (match_operand:P 0 "register_operand" "=d")
3190 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3191 (match_operand:P 2 "immediate_operand" "")))]
3194 [(set_attr "type" "arith")
3195 (set_attr "mode" "<MODE>")
3196 (set_attr "length" "8")])
3198 ;; Allow combine to split complex const_int load sequences, using operand 2
3199 ;; to store the intermediate results. See move_operand for details.
3201 [(set (match_operand:GPR 0 "register_operand")
3202 (match_operand:GPR 1 "splittable_const_int_operand"))
3203 (clobber (match_operand:GPR 2 "register_operand"))]
3207 mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
3211 ;; Likewise, for symbolic operands.
3213 [(set (match_operand:P 0 "register_operand")
3214 (match_operand:P 1 "splittable_symbolic_operand"))
3215 (clobber (match_operand:P 2 "register_operand"))]
3217 [(set (match_dup 0) (match_dup 1))]
3218 { operands[1] = mips_split_symbol (operands[2], operands[1]); })
3220 ;; 64-bit integer moves
3222 ;; Unlike most other insns, the move insns can't be split with
3223 ;; different predicates, because register spilling and other parts of
3224 ;; the compiler, have memoized the insn number already.
3226 (define_expand "movdi"
3227 [(set (match_operand:DI 0 "")
3228 (match_operand:DI 1 ""))]
3231 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3235 ;; For mips16, we need a special case to handle storing $31 into
3236 ;; memory, since we don't have a constraint to match $31. This
3237 ;; instruction can be generated by save_restore_insns.
3239 (define_insn "*mov<mode>_ra"
3240 [(set (match_operand:GPR 0 "stack_operand" "=m")
3244 [(set_attr "type" "store")
3245 (set_attr "mode" "<MODE>")])
3247 (define_insn "*movdi_32bit"
3248 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3249 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3250 "!TARGET_64BIT && !TARGET_MIPS16
3251 && (register_operand (operands[0], DImode)
3252 || reg_or_0_operand (operands[1], DImode))"
3253 { return mips_output_move (operands[0], operands[1]); }
3254 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,xfer,load,xfer,store")
3255 (set_attr "mode" "DI")
3256 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3258 (define_insn "*movdi_32bit_mips16"
3259 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3260 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3261 "!TARGET_64BIT && TARGET_MIPS16
3262 && (register_operand (operands[0], DImode)
3263 || register_operand (operands[1], DImode))"
3264 { return mips_output_move (operands[0], operands[1]); }
3265 [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo")
3266 (set_attr "mode" "DI")
3267 (set_attr "length" "8,8,8,8,12,*,*,8")])
3269 (define_insn "*movdi_64bit"
3270 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3271 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3272 "TARGET_64BIT && !TARGET_MIPS16
3273 && (register_operand (operands[0], DImode)
3274 || reg_or_0_operand (operands[1], DImode))"
3275 { return mips_output_move (operands[0], operands[1]); }
3276 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,xfer,load,xfer,store")
3277 (set_attr "mode" "DI")
3278 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3280 (define_insn "*movdi_64bit_mips16"
3281 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3282 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3283 "TARGET_64BIT && TARGET_MIPS16
3284 && (register_operand (operands[0], DImode)
3285 || register_operand (operands[1], DImode))"
3286 { return mips_output_move (operands[0], operands[1]); }
3287 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3288 (set_attr "mode" "DI")
3289 (set_attr_alternative "length"
3293 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3296 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3301 (const_string "*")])])
3304 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3305 ;; when the original load is a 4 byte instruction but the add and the
3306 ;; load are 2 2 byte instructions.
3309 [(set (match_operand:DI 0 "register_operand")
3310 (mem:DI (plus:DI (match_dup 0)
3311 (match_operand:DI 1 "const_int_operand"))))]
3312 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3313 && !TARGET_DEBUG_D_MODE
3314 && REG_P (operands[0])
3315 && M16_REG_P (REGNO (operands[0]))
3316 && GET_CODE (operands[1]) == CONST_INT
3317 && ((INTVAL (operands[1]) < 0
3318 && INTVAL (operands[1]) >= -0x10)
3319 || (INTVAL (operands[1]) >= 32 * 8
3320 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3321 || (INTVAL (operands[1]) >= 0
3322 && INTVAL (operands[1]) < 32 * 8
3323 && (INTVAL (operands[1]) & 7) != 0))"
3324 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3325 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3327 HOST_WIDE_INT val = INTVAL (operands[1]);
3330 operands[2] = const0_rtx;
3331 else if (val >= 32 * 8)
3335 operands[1] = GEN_INT (0x8 + off);
3336 operands[2] = GEN_INT (val - off - 0x8);
3342 operands[1] = GEN_INT (off);
3343 operands[2] = GEN_INT (val - off);
3347 ;; 32-bit Integer moves
3349 ;; Unlike most other insns, the move insns can't be split with
3350 ;; different predicates, because register spilling and other parts of
3351 ;; the compiler, have memoized the insn number already.
3353 (define_expand "movsi"
3354 [(set (match_operand:SI 0 "")
3355 (match_operand:SI 1 ""))]
3358 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3362 ;; The difference between these two is whether or not ints are allowed
3363 ;; in FP registers (off by default, use -mdebugh to enable).
3365 (define_insn "*movsi_internal"
3366 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3367 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3369 && (register_operand (operands[0], SImode)
3370 || reg_or_0_operand (operands[1], SImode))"
3371 { return mips_output_move (operands[0], operands[1]); }
3372 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,mfhilo,xfer,load,xfer,store")
3373 (set_attr "mode" "SI")
3374 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
3376 (define_insn "*movsi_mips16"
3377 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3378 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3380 && (register_operand (operands[0], SImode)
3381 || register_operand (operands[1], SImode))"
3382 { return mips_output_move (operands[0], operands[1]); }
3383 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3384 (set_attr "mode" "SI")
3385 (set_attr_alternative "length"
3389 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3392 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3397 (const_string "*")])])
3399 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3400 ;; when the original load is a 4 byte instruction but the add and the
3401 ;; load are 2 2 byte instructions.
3404 [(set (match_operand:SI 0 "register_operand")
3405 (mem:SI (plus:SI (match_dup 0)
3406 (match_operand:SI 1 "const_int_operand"))))]
3407 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3408 && REG_P (operands[0])
3409 && M16_REG_P (REGNO (operands[0]))
3410 && GET_CODE (operands[1]) == CONST_INT
3411 && ((INTVAL (operands[1]) < 0
3412 && INTVAL (operands[1]) >= -0x80)
3413 || (INTVAL (operands[1]) >= 32 * 4
3414 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3415 || (INTVAL (operands[1]) >= 0
3416 && INTVAL (operands[1]) < 32 * 4
3417 && (INTVAL (operands[1]) & 3) != 0))"
3418 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3419 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3421 HOST_WIDE_INT val = INTVAL (operands[1]);
3424 operands[2] = const0_rtx;
3425 else if (val >= 32 * 4)
3429 operands[1] = GEN_INT (0x7c + off);
3430 operands[2] = GEN_INT (val - off - 0x7c);
3436 operands[1] = GEN_INT (off);
3437 operands[2] = GEN_INT (val - off);
3441 ;; On the mips16, we can split a load of certain constants into a load
3442 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3446 [(set (match_operand:SI 0 "register_operand")
3447 (match_operand:SI 1 "const_int_operand"))]
3448 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3449 && REG_P (operands[0])
3450 && M16_REG_P (REGNO (operands[0]))
3451 && GET_CODE (operands[1]) == CONST_INT
3452 && INTVAL (operands[1]) >= 0x100
3453 && INTVAL (operands[1]) <= 0xff + 0x7f"
3454 [(set (match_dup 0) (match_dup 1))
3455 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3457 int val = INTVAL (operands[1]);
3459 operands[1] = GEN_INT (0xff);
3460 operands[2] = GEN_INT (val - 0xff);
3463 ;; This insn handles moving CCmode values. It's really just a
3464 ;; slightly simplified copy of movsi_internal2, with additional cases
3465 ;; to move a condition register to a general register and to move
3466 ;; between the general registers and the floating point registers.
3468 (define_insn "movcc"
3469 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3470 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3471 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3472 { return mips_output_move (operands[0], operands[1]); }
3473 [(set_attr "type" "xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore")
3474 (set_attr "mode" "SI")
3475 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3477 ;; Reload condition code registers. reload_incc and reload_outcc
3478 ;; both handle moves from arbitrary operands into condition code
3479 ;; registers. reload_incc handles the more common case in which
3480 ;; a source operand is constrained to be in a condition-code
3481 ;; register, but has not been allocated to one.
3483 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3484 ;; constraints do not include 'z'. reload_outcc handles the case
3485 ;; when such an operand is allocated to a condition-code register.
3487 ;; Note that reloads from a condition code register to some
3488 ;; other location can be done using ordinary moves. Moving
3489 ;; into a GPR takes a single movcc, moving elsewhere takes
3490 ;; two. We can leave these cases to the generic reload code.
3491 (define_expand "reload_incc"
3492 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3493 (match_operand:CC 1 "general_operand" ""))
3494 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3495 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3497 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3501 (define_expand "reload_outcc"
3502 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3503 (match_operand:CC 1 "register_operand" ""))
3504 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3505 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3507 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3511 ;; MIPS4 supports loading and storing a floating point register from
3512 ;; the sum of two general registers. We use two versions for each of
3513 ;; these four instructions: one where the two general registers are
3514 ;; SImode, and one where they are DImode. This is because general
3515 ;; registers will be in SImode when they hold 32 bit values, but,
3516 ;; since the 32 bit values are always sign extended, the [ls][wd]xc1
3517 ;; instructions will still work correctly.
3519 ;; ??? Perhaps it would be better to support these instructions by
3520 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3521 ;; these instructions can only be used to load and store floating
3522 ;; point registers, that would probably cause trouble in reload.
3524 (define_insn "*<ANYF:loadx>_<P:mode>"
3525 [(set (match_operand:ANYF 0 "register_operand" "=f")
3526 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3527 (match_operand:P 2 "register_operand" "d"))))]
3529 "<ANYF:loadx>\t%0,%1(%2)"
3530 [(set_attr "type" "fpidxload")
3531 (set_attr "mode" "<ANYF:UNITMODE>")])
3533 (define_insn "*<ANYF:storex>_<P:mode>"
3534 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3535 (match_operand:P 2 "register_operand" "d")))
3536 (match_operand:ANYF 0 "register_operand" "f"))]
3538 "<ANYF:storex>\t%0,%1(%2)"
3539 [(set_attr "type" "fpidxstore")
3540 (set_attr "mode" "<ANYF:UNITMODE>")])
3542 ;; 16-bit Integer moves
3544 ;; Unlike most other insns, the move insns can't be split with
3545 ;; different predicates, because register spilling and other parts of
3546 ;; the compiler, have memoized the insn number already.
3547 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3549 (define_expand "movhi"
3550 [(set (match_operand:HI 0 "")
3551 (match_operand:HI 1 ""))]
3554 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3558 (define_insn "*movhi_internal"
3559 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3560 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3562 && (register_operand (operands[0], HImode)
3563 || reg_or_0_operand (operands[1], HImode))"
3573 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
3574 (set_attr "mode" "HI")
3575 (set_attr "length" "4,4,*,*,4,4,4,4")])
3577 (define_insn "*movhi_mips16"
3578 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3579 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3581 && (register_operand (operands[0], HImode)
3582 || register_operand (operands[1], HImode))"
3591 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3592 (set_attr "mode" "HI")
3593 (set_attr_alternative "length"
3597 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3600 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3604 (const_string "*")])])
3607 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3608 ;; when the original load is a 4 byte instruction but the add and the
3609 ;; load are 2 2 byte instructions.
3612 [(set (match_operand:HI 0 "register_operand")
3613 (mem:HI (plus:SI (match_dup 0)
3614 (match_operand:SI 1 "const_int_operand"))))]
3615 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3616 && REG_P (operands[0])
3617 && M16_REG_P (REGNO (operands[0]))
3618 && GET_CODE (operands[1]) == CONST_INT
3619 && ((INTVAL (operands[1]) < 0
3620 && INTVAL (operands[1]) >= -0x80)
3621 || (INTVAL (operands[1]) >= 32 * 2
3622 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3623 || (INTVAL (operands[1]) >= 0
3624 && INTVAL (operands[1]) < 32 * 2
3625 && (INTVAL (operands[1]) & 1) != 0))"
3626 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3627 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3629 HOST_WIDE_INT val = INTVAL (operands[1]);
3632 operands[2] = const0_rtx;
3633 else if (val >= 32 * 2)
3637 operands[1] = GEN_INT (0x7e + off);
3638 operands[2] = GEN_INT (val - off - 0x7e);
3644 operands[1] = GEN_INT (off);
3645 operands[2] = GEN_INT (val - off);
3649 ;; 8-bit Integer moves
3651 ;; Unlike most other insns, the move insns can't be split with
3652 ;; different predicates, because register spilling and other parts of
3653 ;; the compiler, have memoized the insn number already.
3654 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3656 (define_expand "movqi"
3657 [(set (match_operand:QI 0 "")
3658 (match_operand:QI 1 ""))]
3661 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3665 (define_insn "*movqi_internal"
3666 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3667 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3669 && (register_operand (operands[0], QImode)
3670 || reg_or_0_operand (operands[1], QImode))"
3680 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
3681 (set_attr "mode" "QI")
3682 (set_attr "length" "4,4,*,*,4,4,4,4")])
3684 (define_insn "*movqi_mips16"
3685 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3686 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3688 && (register_operand (operands[0], QImode)
3689 || register_operand (operands[1], QImode))"
3698 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3699 (set_attr "mode" "QI")
3700 (set_attr "length" "4,4,4,4,8,*,*")])
3702 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3703 ;; when the original load is a 4 byte instruction but the add and the
3704 ;; load are 2 2 byte instructions.
3707 [(set (match_operand:QI 0 "register_operand")
3708 (mem:QI (plus:SI (match_dup 0)
3709 (match_operand:SI 1 "const_int_operand"))))]
3710 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3711 && REG_P (operands[0])
3712 && M16_REG_P (REGNO (operands[0]))
3713 && GET_CODE (operands[1]) == CONST_INT
3714 && ((INTVAL (operands[1]) < 0
3715 && INTVAL (operands[1]) >= -0x80)
3716 || (INTVAL (operands[1]) >= 32
3717 && INTVAL (operands[1]) <= 31 + 0x7f))"
3718 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3719 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3721 HOST_WIDE_INT val = INTVAL (operands[1]);
3724 operands[2] = const0_rtx;
3727 operands[1] = GEN_INT (0x7f);
3728 operands[2] = GEN_INT (val - 0x7f);
3732 ;; 32-bit floating point moves
3734 (define_expand "movsf"
3735 [(set (match_operand:SF 0 "")
3736 (match_operand:SF 1 ""))]
3739 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3743 (define_insn "*movsf_hardfloat"
3744 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3745 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3747 && (register_operand (operands[0], SFmode)
3748 || reg_or_0_operand (operands[1], SFmode))"
3749 { return mips_output_move (operands[0], operands[1]); }
3750 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3751 (set_attr "mode" "SF")
3752 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3754 (define_insn "*movsf_softfloat"
3755 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3756 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3757 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3758 && (register_operand (operands[0], SFmode)
3759 || reg_or_0_operand (operands[1], SFmode))"
3760 { return mips_output_move (operands[0], operands[1]); }
3761 [(set_attr "type" "arith,load,store")
3762 (set_attr "mode" "SF")
3763 (set_attr "length" "4,*,*")])
3765 (define_insn "*movsf_mips16"
3766 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3767 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3769 && (register_operand (operands[0], SFmode)
3770 || register_operand (operands[1], SFmode))"
3771 { return mips_output_move (operands[0], operands[1]); }
3772 [(set_attr "type" "arith,arith,arith,load,store")
3773 (set_attr "mode" "SF")
3774 (set_attr "length" "4,4,4,*,*")])
3777 ;; 64-bit floating point moves
3779 (define_expand "movdf"
3780 [(set (match_operand:DF 0 "")
3781 (match_operand:DF 1 ""))]
3784 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3788 (define_insn "*movdf_hardfloat_64bit"
3789 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3790 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3791 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3792 && (register_operand (operands[0], DFmode)
3793 || reg_or_0_operand (operands[1], DFmode))"
3794 { return mips_output_move (operands[0], operands[1]); }
3795 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3796 (set_attr "mode" "DF")
3797 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3799 (define_insn "*movdf_hardfloat_32bit"
3800 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3801 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3802 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3803 && (register_operand (operands[0], DFmode)
3804 || reg_or_0_operand (operands[1], DFmode))"
3805 { return mips_output_move (operands[0], operands[1]); }
3806 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3807 (set_attr "mode" "DF")
3808 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3810 (define_insn "*movdf_softfloat"
3811 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3812 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3813 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3814 && (register_operand (operands[0], DFmode)
3815 || reg_or_0_operand (operands[1], DFmode))"
3816 { return mips_output_move (operands[0], operands[1]); }
3817 [(set_attr "type" "arith,load,store,xfer,xfer,fmove")
3818 (set_attr "mode" "DF")
3819 (set_attr "length" "8,*,*,4,4,4")])
3821 (define_insn "*movdf_mips16"
3822 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3823 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3825 && (register_operand (operands[0], DFmode)
3826 || register_operand (operands[1], DFmode))"
3827 { return mips_output_move (operands[0], operands[1]); }
3828 [(set_attr "type" "arith,arith,arith,load,store")
3829 (set_attr "mode" "DF")
3830 (set_attr "length" "8,8,8,*,*")])
3833 [(set (match_operand:DI 0 "nonimmediate_operand")
3834 (match_operand:DI 1 "move_operand"))]
3835 "reload_completed && !TARGET_64BIT
3836 && mips_split_64bit_move_p (operands[0], operands[1])"
3839 mips_split_64bit_move (operands[0], operands[1]);
3844 [(set (match_operand:DF 0 "nonimmediate_operand")
3845 (match_operand:DF 1 "move_operand"))]
3846 "reload_completed && !TARGET_64BIT
3847 && mips_split_64bit_move_p (operands[0], operands[1])"
3850 mips_split_64bit_move (operands[0], operands[1]);
3854 ;; When generating mips16 code, split moves of negative constants into
3855 ;; a positive "li" followed by a negation.
3857 [(set (match_operand 0 "register_operand")
3858 (match_operand 1 "const_int_operand"))]
3859 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
3863 (neg:SI (match_dup 2)))]
3865 operands[2] = gen_lowpart (SImode, operands[0]);
3866 operands[3] = GEN_INT (-INTVAL (operands[1]));
3869 ;; 64-bit paired-single floating point moves
3871 (define_expand "movv2sf"
3872 [(set (match_operand:V2SF 0)
3873 (match_operand:V2SF 1))]
3874 "TARGET_PAIRED_SINGLE_FLOAT"
3876 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
3880 (define_insn "movv2sf_hardfloat_64bit"
3881 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3882 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
3883 "TARGET_PAIRED_SINGLE_FLOAT
3885 && (register_operand (operands[0], V2SFmode)
3886 || reg_or_0_operand (operands[1], V2SFmode))"
3887 { return mips_output_move (operands[0], operands[1]); }
3888 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3889 (set_attr "mode" "SF")
3890 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3892 ;; The HI and LO registers are not truly independent. If we move an mthi
3893 ;; instruction before an mflo instruction, it will make the result of the
3894 ;; mflo unpredictable. The same goes for mtlo and mfhi.
3896 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
3897 ;; Operand 1 is the register we want, operand 2 is the other one.
3899 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
3900 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
3901 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
3903 (define_expand "mfhilo_<mode>"
3904 [(set (match_operand:GPR 0 "register_operand")
3905 (unspec:GPR [(match_operand:GPR 1 "register_operand")
3906 (match_operand:GPR 2 "register_operand")]
3909 (define_insn "*mfhilo_<mode>"
3910 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3911 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3912 (match_operand:GPR 2 "register_operand" "l,h")]
3916 [(set_attr "type" "mfhilo")
3917 (set_attr "mode" "<MODE>")])
3919 (define_insn "*mfhilo_<mode>_macc"
3920 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3921 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3922 (match_operand:GPR 2 "register_operand" "l,h")]
3926 if (REGNO (operands[1]) == HI_REGNUM)
3927 return "<d>macchi\t%0,%.,%.";
3929 return "<d>macc\t%0,%.,%.";
3931 [(set_attr "type" "mfhilo")
3932 (set_attr "mode" "<MODE>")])
3934 ;; Patterns for loading or storing part of a paired floating point
3935 ;; register. We need them because odd-numbered floating-point registers
3936 ;; are not fully independent: see mips_split_64bit_move.
3938 ;; Load the low word of operand 0 with operand 1.
3939 (define_insn "load_df_low"
3940 [(set (match_operand:DF 0 "register_operand" "=f,f")
3941 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
3942 UNSPEC_LOAD_DF_LOW))]
3943 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3945 operands[0] = mips_subword (operands[0], 0);
3946 return mips_output_move (operands[0], operands[1]);
3948 [(set_attr "type" "xfer,fpload")
3949 (set_attr "mode" "SF")])
3951 ;; Load the high word of operand 0 from operand 1, preserving the value
3953 (define_insn "load_df_high"
3954 [(set (match_operand:DF 0 "register_operand" "=f,f")
3955 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
3956 (match_operand:DF 2 "register_operand" "0,0")]
3957 UNSPEC_LOAD_DF_HIGH))]
3958 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3960 operands[0] = mips_subword (operands[0], 1);
3961 return mips_output_move (operands[0], operands[1]);
3963 [(set_attr "type" "xfer,fpload")
3964 (set_attr "mode" "SF")])
3966 ;; Store the high word of operand 1 in operand 0. The corresponding
3967 ;; low-word move is done in the normal way.
3968 (define_insn "store_df_high"
3969 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
3970 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
3971 UNSPEC_STORE_DF_HIGH))]
3972 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3974 operands[1] = mips_subword (operands[1], 1);
3975 return mips_output_move (operands[0], operands[1]);
3977 [(set_attr "type" "xfer,fpstore")
3978 (set_attr "mode" "SF")])
3980 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
3981 ;; of _gp from the start of this function. Operand 1 is the incoming
3982 ;; function address.
3983 (define_insn_and_split "loadgp"
3984 [(unspec_volatile [(match_operand 0 "" "")
3985 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
3986 "mips_current_loadgp_style () == LOADGP_NEWABI"
3989 [(set (match_dup 2) (match_dup 3))
3990 (set (match_dup 2) (match_dup 4))
3991 (set (match_dup 2) (match_dup 5))]
3993 operands[2] = pic_offset_table_rtx;
3994 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
3995 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
3996 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
3998 [(set_attr "length" "12")])
4000 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4001 (define_insn_and_split "loadgp_noshared"
4002 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
4003 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4008 emit_move_insn (pic_offset_table_rtx, operands[0]);
4011 [(set_attr "length" "8")])
4013 ;; The use of gp is hidden when not using explicit relocations.
4014 ;; This blockage instruction prevents the gp load from being
4015 ;; scheduled after an implicit use of gp. It also prevents
4016 ;; the load from being deleted as dead.
4017 (define_insn "loadgp_blockage"
4018 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4021 [(set_attr "type" "unknown")
4022 (set_attr "mode" "none")
4023 (set_attr "length" "0")])
4025 ;; Emit a .cprestore directive, which normally expands to a single store
4026 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4027 ;; code so that jals inside inline asms will work correctly.
4028 (define_insn "cprestore"
4029 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
4033 if (set_nomacro && which_alternative == 1)
4034 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4036 return ".cprestore\t%0";
4038 [(set_attr "type" "store")
4039 (set_attr "length" "4,12")])
4041 ;; Block moves, see mips.c for more details.
4042 ;; Argument 0 is the destination
4043 ;; Argument 1 is the source
4044 ;; Argument 2 is the length
4045 ;; Argument 3 is the alignment
4047 (define_expand "movmemsi"
4048 [(parallel [(set (match_operand:BLK 0 "general_operand")
4049 (match_operand:BLK 1 "general_operand"))
4050 (use (match_operand:SI 2 ""))
4051 (use (match_operand:SI 3 "const_int_operand"))])]
4052 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4054 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4061 ;; ....................
4065 ;; ....................
4067 (define_expand "<optab><mode>3"
4068 [(set (match_operand:GPR 0 "register_operand")
4069 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4070 (match_operand:SI 2 "arith_operand")))]
4073 /* On the mips16, a shift of more than 8 is a four byte instruction,
4074 so, for a shift between 8 and 16, it is just as fast to do two
4075 shifts of 8 or less. If there is a lot of shifting going on, we
4076 may win in CSE. Otherwise combine will put the shifts back
4077 together again. This can be called by function_arg, so we must
4078 be careful not to allocate a new register if we've reached the
4082 && GET_CODE (operands[2]) == CONST_INT
4083 && INTVAL (operands[2]) > 8
4084 && INTVAL (operands[2]) <= 16
4085 && !reload_in_progress
4086 && !reload_completed)
4088 rtx temp = gen_reg_rtx (<MODE>mode);
4090 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4091 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4092 GEN_INT (INTVAL (operands[2]) - 8)));
4097 (define_insn "*<optab><mode>3"
4098 [(set (match_operand:GPR 0 "register_operand" "=d")
4099 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4100 (match_operand:SI 2 "arith_operand" "dI")))]
4103 if (GET_CODE (operands[2]) == CONST_INT)
4104 operands[2] = GEN_INT (INTVAL (operands[2])
4105 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4107 return "<d><insn>\t%0,%1,%2";
4109 [(set_attr "type" "shift")
4110 (set_attr "mode" "<MODE>")])
4112 (define_insn "*<optab>si3_extend"
4113 [(set (match_operand:DI 0 "register_operand" "=d")
4115 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4116 (match_operand:SI 2 "arith_operand" "dI"))))]
4117 "TARGET_64BIT && !TARGET_MIPS16"
4119 if (GET_CODE (operands[2]) == CONST_INT)
4120 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4122 return "<insn>\t%0,%1,%2";
4124 [(set_attr "type" "shift")
4125 (set_attr "mode" "SI")])
4127 (define_insn "*<optab>si3_mips16"
4128 [(set (match_operand:SI 0 "register_operand" "=d,d")
4129 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4130 (match_operand:SI 2 "arith_operand" "d,I")))]
4133 if (which_alternative == 0)
4134 return "<insn>\t%0,%2";
4136 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4137 return "<insn>\t%0,%1,%2";
4139 [(set_attr "type" "shift")
4140 (set_attr "mode" "SI")
4141 (set_attr_alternative "length"
4143 (if_then_else (match_operand 2 "m16_uimm3_b")
4147 ;; We need separate DImode MIPS16 patterns because of the irregularity
4149 (define_insn "*ashldi3_mips16"
4150 [(set (match_operand:DI 0 "register_operand" "=d,d")
4151 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4152 (match_operand:SI 2 "arith_operand" "d,I")))]
4153 "TARGET_64BIT && TARGET_MIPS16"
4155 if (which_alternative == 0)
4156 return "dsll\t%0,%2";
4158 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4159 return "dsll\t%0,%1,%2";
4161 [(set_attr "type" "shift")
4162 (set_attr "mode" "DI")
4163 (set_attr_alternative "length"
4165 (if_then_else (match_operand 2 "m16_uimm3_b")
4169 (define_insn "*ashrdi3_mips16"
4170 [(set (match_operand:DI 0 "register_operand" "=d,d")
4171 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4172 (match_operand:SI 2 "arith_operand" "d,I")))]
4173 "TARGET_64BIT && TARGET_MIPS16"
4175 if (GET_CODE (operands[2]) == CONST_INT)
4176 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4178 return "dsra\t%0,%2";
4180 [(set_attr "type" "shift")
4181 (set_attr "mode" "DI")
4182 (set_attr_alternative "length"
4184 (if_then_else (match_operand 2 "m16_uimm3_b")
4188 (define_insn "*lshrdi3_mips16"
4189 [(set (match_operand:DI 0 "register_operand" "=d,d")
4190 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4191 (match_operand:SI 2 "arith_operand" "d,I")))]
4192 "TARGET_64BIT && TARGET_MIPS16"
4194 if (GET_CODE (operands[2]) == CONST_INT)
4195 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4197 return "dsrl\t%0,%2";
4199 [(set_attr "type" "shift")
4200 (set_attr "mode" "DI")
4201 (set_attr_alternative "length"
4203 (if_then_else (match_operand 2 "m16_uimm3_b")
4207 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4210 [(set (match_operand:GPR 0 "register_operand")
4211 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4212 (match_operand:GPR 2 "const_int_operand")))]
4213 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4214 && GET_CODE (operands[2]) == CONST_INT
4215 && INTVAL (operands[2]) > 8
4216 && INTVAL (operands[2]) <= 16"
4217 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4218 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4219 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4221 ;; If we load a byte on the mips16 as a bitfield, the resulting
4222 ;; sequence of instructions is too complicated for combine, because it
4223 ;; involves four instructions: a load, a shift, a constant load into a
4224 ;; register, and an and (the key problem here is that the mips16 does
4225 ;; not have and immediate). We recognize a shift of a load in order
4226 ;; to make it simple enough for combine to understand.
4228 ;; The length here is the worst case: the length of the split version
4229 ;; will be more accurate.
4230 (define_insn_and_split ""
4231 [(set (match_operand:SI 0 "register_operand" "=d")
4232 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4233 (match_operand:SI 2 "immediate_operand" "I")))]
4237 [(set (match_dup 0) (match_dup 1))
4238 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4240 [(set_attr "type" "load")
4241 (set_attr "mode" "SI")
4242 (set_attr "length" "16")])
4244 (define_insn "rotr<mode>3"
4245 [(set (match_operand:GPR 0 "register_operand" "=d")
4246 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4247 (match_operand:SI 2 "arith_operand" "dI")))]
4248 "ISA_HAS_ROTR_<MODE>"
4250 if (GET_CODE (operands[2]) == CONST_INT)
4251 gcc_assert (INTVAL (operands[2]) >= 0
4252 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4254 return "<d>ror\t%0,%1,%2";
4256 [(set_attr "type" "shift")
4257 (set_attr "mode" "<MODE>")])
4260 ;; ....................
4264 ;; ....................
4266 ;; Flow here is rather complex:
4268 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4269 ;; into cmp_operands[] but generates no RTL.
4271 ;; 2) The appropriate branch define_expand is called, which then
4272 ;; creates the appropriate RTL for the comparison and branch.
4273 ;; Different CC modes are used, based on what type of branch is
4274 ;; done, so that we can constrain things appropriately. There
4275 ;; are assumptions in the rest of GCC that break if we fold the
4276 ;; operands into the branches for integer operations, and use cc0
4277 ;; for floating point, so we use the fp status register instead.
4278 ;; If needed, an appropriate temporary is created to hold the
4279 ;; of the integer compare.
4281 (define_expand "cmp<mode>"
4283 (compare:CC (match_operand:GPR 0 "register_operand")
4284 (match_operand:GPR 1 "nonmemory_operand")))]
4287 cmp_operands[0] = operands[0];
4288 cmp_operands[1] = operands[1];
4292 (define_expand "cmp<mode>"
4294 (compare:CC (match_operand:SCALARF 0 "register_operand")
4295 (match_operand:SCALARF 1 "register_operand")))]
4298 cmp_operands[0] = operands[0];
4299 cmp_operands[1] = operands[1];
4304 ;; ....................
4306 ;; CONDITIONAL BRANCHES
4308 ;; ....................
4310 ;; Conditional branches on floating-point equality tests.
4312 (define_insn "*branch_fp"
4315 (match_operator 0 "equality_operator"
4316 [(match_operand:CC 2 "register_operand" "z")
4318 (label_ref (match_operand 1 "" ""))
4322 return mips_output_conditional_branch (insn, operands,
4323 MIPS_BRANCH ("b%F0", "%Z2%1"),
4324 MIPS_BRANCH ("b%W0", "%Z2%1"));
4326 [(set_attr "type" "branch")
4327 (set_attr "mode" "none")])
4329 (define_insn "*branch_fp_inverted"
4332 (match_operator 0 "equality_operator"
4333 [(match_operand:CC 2 "register_operand" "z")
4336 (label_ref (match_operand 1 "" ""))))]
4339 return mips_output_conditional_branch (insn, operands,
4340 MIPS_BRANCH ("b%W0", "%Z2%1"),
4341 MIPS_BRANCH ("b%F0", "%Z2%1"));
4343 [(set_attr "type" "branch")
4344 (set_attr "mode" "none")])
4346 ;; Conditional branches on ordered comparisons with zero.
4348 (define_insn "*branch_order<mode>"
4351 (match_operator 0 "order_operator"
4352 [(match_operand:GPR 2 "register_operand" "d")
4354 (label_ref (match_operand 1 "" ""))
4357 { return mips_output_order_conditional_branch (insn, operands, false); }
4358 [(set_attr "type" "branch")
4359 (set_attr "mode" "none")])
4361 (define_insn "*branch_order<mode>_inverted"
4364 (match_operator 0 "order_operator"
4365 [(match_operand:GPR 2 "register_operand" "d")
4368 (label_ref (match_operand 1 "" ""))))]
4370 { return mips_output_order_conditional_branch (insn, operands, true); }
4371 [(set_attr "type" "branch")
4372 (set_attr "mode" "none")])
4374 ;; Conditional branch on equality comparison.
4376 (define_insn "*branch_equality<mode>"
4379 (match_operator 0 "equality_operator"
4380 [(match_operand:GPR 2 "register_operand" "d")
4381 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4382 (label_ref (match_operand 1 "" ""))
4386 return mips_output_conditional_branch (insn, operands,
4387 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4388 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4390 [(set_attr "type" "branch")
4391 (set_attr "mode" "none")])
4393 (define_insn "*branch_equality<mode>_inverted"
4396 (match_operator 0 "equality_operator"
4397 [(match_operand:GPR 2 "register_operand" "d")
4398 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4400 (label_ref (match_operand 1 "" ""))))]
4403 return mips_output_conditional_branch (insn, operands,
4404 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4405 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4407 [(set_attr "type" "branch")
4408 (set_attr "mode" "none")])
4412 (define_insn "*branch_equality<mode>_mips16"
4415 (match_operator 0 "equality_operator"
4416 [(match_operand:GPR 1 "register_operand" "d,t")
4418 (match_operand 2 "pc_or_label_operand" "")
4419 (match_operand 3 "pc_or_label_operand" "")))]
4422 if (operands[2] != pc_rtx)
4424 if (which_alternative == 0)
4425 return "b%C0z\t%1,%2";
4427 return "bt%C0z\t%2";
4431 if (which_alternative == 0)
4432 return "b%N0z\t%1,%3";
4434 return "bt%N0z\t%3";
4437 [(set_attr "type" "branch")
4438 (set_attr "mode" "none")
4439 (set_attr "length" "8")])
4441 (define_expand "b<code>"
4443 (if_then_else (any_cond:CC (cc0)
4445 (label_ref (match_operand 0 ""))
4449 gen_conditional_branch (operands, <CODE>);
4453 ;; Used to implement built-in functions.
4454 (define_expand "condjump"
4456 (if_then_else (match_operand 0)
4457 (label_ref (match_operand 1))
4461 ;; ....................
4463 ;; SETTING A REGISTER FROM A COMPARISON
4465 ;; ....................
4467 (define_expand "seq"
4468 [(set (match_operand:SI 0 "register_operand")
4469 (eq:SI (match_dup 1)
4472 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4474 (define_insn "*seq_<mode>"
4475 [(set (match_operand:GPR 0 "register_operand" "=d")
4476 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4480 [(set_attr "type" "slt")
4481 (set_attr "mode" "<MODE>")])
4483 (define_insn "*seq_<mode>_mips16"
4484 [(set (match_operand:GPR 0 "register_operand" "=t")
4485 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4489 [(set_attr "type" "slt")
4490 (set_attr "mode" "<MODE>")])
4492 ;; "sne" uses sltu instructions in which the first operand is $0.
4493 ;; This isn't possible in mips16 code.
4495 (define_expand "sne"
4496 [(set (match_operand:SI 0 "register_operand")
4497 (ne:SI (match_dup 1)
4500 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
4502 (define_insn "*sne_<mode>"
4503 [(set (match_operand:GPR 0 "register_operand" "=d")
4504 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
4508 [(set_attr "type" "slt")
4509 (set_attr "mode" "<MODE>")])
4511 (define_expand "sgt"
4512 [(set (match_operand:SI 0 "register_operand")
4513 (gt:SI (match_dup 1)
4516 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
4518 (define_insn "*sgt_<mode>"
4519 [(set (match_operand:GPR 0 "register_operand" "=d")
4520 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4521 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4524 [(set_attr "type" "slt")
4525 (set_attr "mode" "<MODE>")])
4527 (define_insn "*sgt_<mode>_mips16"
4528 [(set (match_operand:GPR 0 "register_operand" "=t")
4529 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4530 (match_operand:GPR 2 "register_operand" "d")))]
4533 [(set_attr "type" "slt")
4534 (set_attr "mode" "<MODE>")])
4536 (define_expand "sge"
4537 [(set (match_operand:SI 0 "register_operand")
4538 (ge:SI (match_dup 1)
4541 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
4543 (define_insn "*sge_<mode>"
4544 [(set (match_operand:GPR 0 "register_operand" "=d")
4545 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
4549 [(set_attr "type" "slt")
4550 (set_attr "mode" "<MODE>")])
4552 (define_expand "slt"
4553 [(set (match_operand:SI 0 "register_operand")
4554 (lt:SI (match_dup 1)
4557 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
4559 (define_insn "*slt_<mode>"
4560 [(set (match_operand:GPR 0 "register_operand" "=d")
4561 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
4562 (match_operand:GPR 2 "arith_operand" "dI")))]
4565 [(set_attr "type" "slt")
4566 (set_attr "mode" "<MODE>")])
4568 (define_insn "*slt_<mode>_mips16"
4569 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4570 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
4571 (match_operand:GPR 2 "arith_operand" "d,I")))]
4574 [(set_attr "type" "slt")
4575 (set_attr "mode" "<MODE>")
4576 (set_attr_alternative "length"
4578 (if_then_else (match_operand 2 "m16_uimm8_1")
4582 (define_expand "sle"
4583 [(set (match_operand:SI 0 "register_operand")
4584 (le:SI (match_dup 1)
4587 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
4589 (define_insn "*sle_<mode>"
4590 [(set (match_operand:GPR 0 "register_operand" "=d")
4591 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4592 (match_operand:GPR 2 "sle_operand" "")))]
4595 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4596 return "slt\t%0,%1,%2";
4598 [(set_attr "type" "slt")
4599 (set_attr "mode" "<MODE>")])
4601 (define_insn "*sle_<mode>_mips16"
4602 [(set (match_operand:GPR 0 "register_operand" "=t")
4603 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4604 (match_operand:GPR 2 "sle_operand" "")))]
4607 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4608 return "slt\t%1,%2";
4610 [(set_attr "type" "slt")
4611 (set_attr "mode" "<MODE>")
4612 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4616 (define_expand "sgtu"
4617 [(set (match_operand:SI 0 "register_operand")
4618 (gtu:SI (match_dup 1)
4621 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
4623 (define_insn "*sgtu_<mode>"
4624 [(set (match_operand:GPR 0 "register_operand" "=d")
4625 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4626 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4629 [(set_attr "type" "slt")
4630 (set_attr "mode" "<MODE>")])
4632 (define_insn "*sgtu_<mode>_mips16"
4633 [(set (match_operand:GPR 0 "register_operand" "=t")
4634 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4635 (match_operand:GPR 2 "register_operand" "d")))]
4638 [(set_attr "type" "slt")
4639 (set_attr "mode" "<MODE>")])
4641 (define_expand "sgeu"
4642 [(set (match_operand:SI 0 "register_operand")
4643 (geu:SI (match_dup 1)
4646 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
4648 (define_insn "*sge_<mode>"
4649 [(set (match_operand:GPR 0 "register_operand" "=d")
4650 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
4654 [(set_attr "type" "slt")
4655 (set_attr "mode" "<MODE>")])
4657 (define_expand "sltu"
4658 [(set (match_operand:SI 0 "register_operand")
4659 (ltu:SI (match_dup 1)
4662 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
4664 (define_insn "*sltu_<mode>"
4665 [(set (match_operand:GPR 0 "register_operand" "=d")
4666 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
4667 (match_operand:GPR 2 "arith_operand" "dI")))]
4670 [(set_attr "type" "slt")
4671 (set_attr "mode" "<MODE>")])
4673 (define_insn "*sltu_<mode>_mips16"
4674 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4675 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
4676 (match_operand:GPR 2 "arith_operand" "d,I")))]
4679 [(set_attr "type" "slt")
4680 (set_attr "mode" "<MODE>")
4681 (set_attr_alternative "length"
4683 (if_then_else (match_operand 2 "m16_uimm8_1")
4687 (define_expand "sleu"
4688 [(set (match_operand:SI 0 "register_operand")
4689 (leu:SI (match_dup 1)
4692 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
4694 (define_insn "*sleu_<mode>"
4695 [(set (match_operand:GPR 0 "register_operand" "=d")
4696 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4697 (match_operand:GPR 2 "sleu_operand" "")))]
4700 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4701 return "sltu\t%0,%1,%2";
4703 [(set_attr "type" "slt")
4704 (set_attr "mode" "<MODE>")])
4706 (define_insn "*sleu_<mode>_mips16"
4707 [(set (match_operand:GPR 0 "register_operand" "=t")
4708 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4709 (match_operand:GPR 2 "sleu_operand" "")))]
4712 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4713 return "sltu\t%1,%2";
4715 [(set_attr "type" "slt")
4716 (set_attr "mode" "<MODE>")
4717 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4722 ;; ....................
4724 ;; FLOATING POINT COMPARISONS
4726 ;; ....................
4728 (define_insn "s<code>_<mode>"
4729 [(set (match_operand:CC 0 "register_operand" "=z")
4730 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4731 (match_operand:SCALARF 2 "register_operand" "f")))]
4733 "c.<fcond>.<fmt>\t%Z0%1,%2"
4734 [(set_attr "type" "fcmp")
4735 (set_attr "mode" "FPSW")])
4737 (define_insn "s<code>_<mode>"
4738 [(set (match_operand:CC 0 "register_operand" "=z")
4739 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4740 (match_operand:SCALARF 2 "register_operand" "f")))]
4742 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
4743 [(set_attr "type" "fcmp")
4744 (set_attr "mode" "FPSW")])
4747 ;; ....................
4749 ;; UNCONDITIONAL BRANCHES
4751 ;; ....................
4753 ;; Unconditional branches.
4757 (label_ref (match_operand 0 "" "")))]
4762 if (get_attr_length (insn) <= 8)
4763 return "%*b\t%l0%/";
4766 output_asm_insn (mips_output_load_label (), operands);
4767 return "%*jr\t%@%/%]";
4771 return "%*j\t%l0%/";
4773 [(set_attr "type" "jump")
4774 (set_attr "mode" "none")
4775 (set (attr "length")
4776 ;; We can't use `j' when emitting PIC. Emit a branch if it's
4777 ;; in range, otherwise load the address of the branch target into
4778 ;; $at and then jump to it.
4780 (ior (eq (symbol_ref "flag_pic") (const_int 0))
4781 (lt (abs (minus (match_dup 0)
4782 (plus (pc) (const_int 4))))
4783 (const_int 131072)))
4784 (const_int 4) (const_int 16)))])
4786 ;; We need a different insn for the mips16, because a mips16 branch
4787 ;; does not have a delay slot.
4791 (label_ref (match_operand 0 "" "")))]
4794 [(set_attr "type" "branch")
4795 (set_attr "mode" "none")
4796 (set_attr "length" "8")])
4798 (define_expand "indirect_jump"
4799 [(set (pc) (match_operand 0 "register_operand"))]
4802 operands[0] = force_reg (Pmode, operands[0]);
4803 if (Pmode == SImode)
4804 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
4806 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
4810 (define_insn "indirect_jump<mode>"
4811 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
4814 [(set_attr "type" "jump")
4815 (set_attr "mode" "none")])
4817 (define_expand "tablejump"
4819 (match_operand 0 "register_operand"))
4820 (use (label_ref (match_operand 1 "")))]
4824 operands[0] = expand_binop (Pmode, add_optab,
4825 convert_to_mode (Pmode, operands[0], false),
4826 gen_rtx_LABEL_REF (Pmode, operands[1]),
4828 else if (TARGET_GPWORD)
4829 operands[0] = expand_binop (Pmode, add_optab, operands[0],
4830 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
4832 if (Pmode == SImode)
4833 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
4835 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
4839 (define_insn "tablejump<mode>"
4841 (match_operand:P 0 "register_operand" "d"))
4842 (use (label_ref (match_operand 1 "" "")))]
4845 [(set_attr "type" "jump")
4846 (set_attr "mode" "none")])
4848 ;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well.
4849 ;; While it is possible to either pull it off the stack (in the
4850 ;; o32 case) or recalculate it given t9 and our target label,
4851 ;; it takes 3 or 4 insns to do so.
4853 (define_expand "builtin_setjmp_setup"
4854 [(use (match_operand 0 "register_operand"))]
4859 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
4860 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
4864 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
4865 ;; that older code did recalculate the gp from $25. Continue to jump through
4866 ;; $25 for compatibility (we lose nothing by doing so).
4868 (define_expand "builtin_longjmp"
4869 [(use (match_operand 0 "register_operand"))]
4872 /* The elements of the buffer are, in order: */
4873 int W = GET_MODE_SIZE (Pmode);
4874 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
4875 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
4876 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
4877 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
4878 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
4879 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
4880 The target is bound to be using $28 as the global pointer
4881 but the current function might not be. */
4882 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
4884 /* This bit is similar to expand_builtin_longjmp except that it
4885 restores $gp as well. */
4886 emit_move_insn (hard_frame_pointer_rtx, fp);
4887 emit_move_insn (pv, lab);
4888 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
4889 emit_move_insn (gp, gpv);
4890 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
4891 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4892 emit_insn (gen_rtx_USE (VOIDmode, gp));
4893 emit_indirect_jump (pv);
4898 ;; ....................
4900 ;; Function prologue/epilogue
4902 ;; ....................
4905 (define_expand "prologue"
4909 mips_expand_prologue ();
4913 ;; Block any insns from being moved before this point, since the
4914 ;; profiling call to mcount can use various registers that aren't
4915 ;; saved or used to pass arguments.
4917 (define_insn "blockage"
4918 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
4921 [(set_attr "type" "unknown")
4922 (set_attr "mode" "none")
4923 (set_attr "length" "0")])
4925 (define_expand "epilogue"
4929 mips_expand_epilogue (false);
4933 (define_expand "sibcall_epilogue"
4937 mips_expand_epilogue (true);
4941 ;; Trivial return. Make it look like a normal return insn as that
4942 ;; allows jump optimizations to work better.
4944 (define_insn "return"
4946 "mips_can_use_return_insn ()"
4948 [(set_attr "type" "jump")
4949 (set_attr "mode" "none")])
4953 (define_insn "return_internal"
4955 (use (match_operand 0 "pmode_register_operand" ""))]
4958 [(set_attr "type" "jump")
4959 (set_attr "mode" "none")])
4961 ;; This is used in compiling the unwind routines.
4962 (define_expand "eh_return"
4963 [(use (match_operand 0 "general_operand"))]
4966 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
4968 if (GET_MODE (operands[0]) != gpr_mode)
4969 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
4971 emit_insn (gen_eh_set_lr_di (operands[0]));
4973 emit_insn (gen_eh_set_lr_si (operands[0]));
4978 ;; Clobber the return address on the stack. We can't expand this
4979 ;; until we know where it will be put in the stack frame.
4981 (define_insn "eh_set_lr_si"
4982 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
4983 (clobber (match_scratch:SI 1 "=&d"))]
4987 (define_insn "eh_set_lr_di"
4988 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
4989 (clobber (match_scratch:DI 1 "=&d"))]
4994 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
4995 (clobber (match_scratch 1))]
4996 "reload_completed && !TARGET_DEBUG_D_MODE"
4999 mips_set_return_address (operands[0], operands[1]);
5003 (define_insn_and_split "exception_receiver"
5005 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
5006 "TARGET_ABICALLS && TARGET_OLDABI"
5008 "&& reload_completed"
5014 [(set_attr "type" "load")
5015 (set_attr "length" "12")])
5018 ;; ....................
5022 ;; ....................
5024 ;; Instructions to load a call address from the GOT. The address might
5025 ;; point to a function or to a lazy binding stub. In the latter case,
5026 ;; the stub will use the dynamic linker to resolve the function, which
5027 ;; in turn will change the GOT entry to point to the function's real
5030 ;; This means that every call, even pure and constant ones, can
5031 ;; potentially modify the GOT entry. And once a stub has been called,
5032 ;; we must not call it again.
5034 ;; We represent this restriction using an imaginary fixed register that
5035 ;; acts like a GOT version number. By making the register call-clobbered,
5036 ;; we tell the target-independent code that the address could be changed
5037 ;; by any call insn.
5038 (define_insn "load_call<mode>"
5039 [(set (match_operand:P 0 "register_operand" "=c")
5040 (unspec:P [(match_operand:P 1 "register_operand" "r")
5041 (match_operand:P 2 "immediate_operand" "")
5042 (reg:P FAKE_CALL_REGNO)]
5045 "<load>\t%0,%R2(%1)"
5046 [(set_attr "type" "load")
5047 (set_attr "mode" "<MODE>")
5048 (set_attr "length" "4")])
5050 ;; Sibling calls. All these patterns use jump instructions.
5052 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5053 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5054 ;; is defined in terms of call_insn_operand, the same is true of the
5057 ;; When we use an indirect jump, we need a register that will be
5058 ;; preserved by the epilogue. Since TARGET_ABICALLS forces us to
5059 ;; use $25 for this purpose -- and $25 is never clobbered by the
5060 ;; epilogue -- we might as well use it for !TARGET_ABICALLS as well.
5062 (define_expand "sibcall"
5063 [(parallel [(call (match_operand 0 "")
5064 (match_operand 1 ""))
5065 (use (match_operand 2 "")) ;; next_arg_reg
5066 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5069 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5073 (define_insn "sibcall_internal"
5074 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5075 (match_operand 1 "" ""))]
5076 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5077 { return MIPS_CALL ("j", operands, 0); }
5078 [(set_attr "type" "call")])
5080 (define_expand "sibcall_value"
5081 [(parallel [(set (match_operand 0 "")
5082 (call (match_operand 1 "")
5083 (match_operand 2 "")))
5084 (use (match_operand 3 ""))])] ;; next_arg_reg
5087 mips_expand_call (operands[0], XEXP (operands[1], 0),
5088 operands[2], operands[3], true);
5092 (define_insn "sibcall_value_internal"
5093 [(set (match_operand 0 "register_operand" "=df,df")
5094 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5095 (match_operand 2 "" "")))]
5096 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5097 { return MIPS_CALL ("j", operands, 1); }
5098 [(set_attr "type" "call")])
5100 (define_insn "sibcall_value_multiple_internal"
5101 [(set (match_operand 0 "register_operand" "=df,df")
5102 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5103 (match_operand 2 "" "")))
5104 (set (match_operand 3 "register_operand" "=df,df")
5105 (call (mem:SI (match_dup 1))
5107 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5108 { return MIPS_CALL ("j", operands, 1); }
5109 [(set_attr "type" "call")])
5111 (define_expand "call"
5112 [(parallel [(call (match_operand 0 "")
5113 (match_operand 1 ""))
5114 (use (match_operand 2 "")) ;; next_arg_reg
5115 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5118 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5122 ;; This instruction directly corresponds to an assembly-language "jal".
5123 ;; There are four cases:
5126 ;; Both symbolic and register destinations are OK. The pattern
5127 ;; always expands to a single mips instruction.
5129 ;; - -mabicalls/-mno-explicit-relocs:
5130 ;; Again, both symbolic and register destinations are OK.
5131 ;; The call is treated as a multi-instruction black box.
5133 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5134 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5137 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5138 ;; Only "jal $25" is allowed. The call is actually two instructions:
5139 ;; "jalr $25" followed by an insn to reload $gp.
5141 ;; In the last case, we can generate the individual instructions with
5142 ;; a define_split. There are several things to be wary of:
5144 ;; - We can't expose the load of $gp before reload. If we did,
5145 ;; it might get removed as dead, but reload can introduce new
5146 ;; uses of $gp by rematerializing constants.
5148 ;; - We shouldn't restore $gp after calls that never return.
5149 ;; It isn't valid to insert instructions between a noreturn
5150 ;; call and the following barrier.
5152 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5153 ;; instruction preserves $gp and so have no effect on its liveness.
5154 ;; But once we generate the separate insns, it becomes obvious that
5155 ;; $gp is not live on entry to the call.
5157 ;; ??? The operands[2] = insn check is a hack to make the original insn
5158 ;; available to the splitter.
5159 (define_insn_and_split "call_internal"
5160 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5161 (match_operand 1 "" ""))
5162 (clobber (reg:SI 31))]
5164 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5165 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5168 emit_call_insn (gen_call_split (operands[0], operands[1]));
5169 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5173 [(set_attr "jal" "indirect,direct")
5174 (set_attr "extended_mips16" "no,yes")])
5176 (define_insn "call_split"
5177 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5178 (match_operand 1 "" ""))
5179 (clobber (reg:SI 31))
5180 (clobber (reg:SI 28))]
5181 "TARGET_SPLIT_CALLS"
5182 { return MIPS_CALL ("jal", operands, 0); }
5183 [(set_attr "type" "call")])
5185 (define_expand "call_value"
5186 [(parallel [(set (match_operand 0 "")
5187 (call (match_operand 1 "")
5188 (match_operand 2 "")))
5189 (use (match_operand 3 ""))])] ;; next_arg_reg
5192 mips_expand_call (operands[0], XEXP (operands[1], 0),
5193 operands[2], operands[3], false);
5197 ;; See comment for call_internal.
5198 (define_insn_and_split "call_value_internal"
5199 [(set (match_operand 0 "register_operand" "=df,df")
5200 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5201 (match_operand 2 "" "")))
5202 (clobber (reg:SI 31))]
5204 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5205 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5208 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5210 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5214 [(set_attr "jal" "indirect,direct")
5215 (set_attr "extended_mips16" "no,yes")])
5217 (define_insn "call_value_split"
5218 [(set (match_operand 0 "register_operand" "=df")
5219 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5220 (match_operand 2 "" "")))
5221 (clobber (reg:SI 31))
5222 (clobber (reg:SI 28))]
5223 "TARGET_SPLIT_CALLS"
5224 { return MIPS_CALL ("jal", operands, 1); }
5225 [(set_attr "type" "call")])
5227 ;; See comment for call_internal.
5228 (define_insn_and_split "call_value_multiple_internal"
5229 [(set (match_operand 0 "register_operand" "=df,df")
5230 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5231 (match_operand 2 "" "")))
5232 (set (match_operand 3 "register_operand" "=df,df")
5233 (call (mem:SI (match_dup 1))
5235 (clobber (reg:SI 31))]
5237 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5238 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5241 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5242 operands[2], operands[3]));
5243 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5247 [(set_attr "jal" "indirect,direct")
5248 (set_attr "extended_mips16" "no,yes")])
5250 (define_insn "call_value_multiple_split"
5251 [(set (match_operand 0 "register_operand" "=df")
5252 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5253 (match_operand 2 "" "")))
5254 (set (match_operand 3 "register_operand" "=df")
5255 (call (mem:SI (match_dup 1))
5257 (clobber (reg:SI 31))
5258 (clobber (reg:SI 28))]
5259 "TARGET_SPLIT_CALLS"
5260 { return MIPS_CALL ("jal", operands, 1); }
5261 [(set_attr "type" "call")])
5263 ;; Call subroutine returning any type.
5265 (define_expand "untyped_call"
5266 [(parallel [(call (match_operand 0 "")
5268 (match_operand 1 "")
5269 (match_operand 2 "")])]
5274 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5276 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5278 rtx set = XVECEXP (operands[2], 0, i);
5279 emit_move_insn (SET_DEST (set), SET_SRC (set));
5282 emit_insn (gen_blockage ());
5287 ;; ....................
5291 ;; ....................
5295 (define_insn "prefetch"
5296 [(prefetch (match_operand:QI 0 "address_operand" "p")
5297 (match_operand 1 "const_int_operand" "n")
5298 (match_operand 2 "const_int_operand" "n"))]
5299 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5301 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5302 return "pref\t%1,%a0";
5304 [(set_attr "type" "prefetch")])
5306 (define_insn "*prefetch_indexed_<mode>"
5307 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5308 (match_operand:P 1 "register_operand" "d"))
5309 (match_operand 2 "const_int_operand" "n")
5310 (match_operand 3 "const_int_operand" "n"))]
5311 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5313 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5314 return "prefx\t%2,%1(%0)";
5316 [(set_attr "type" "prefetchx")])
5322 [(set_attr "type" "nop")
5323 (set_attr "mode" "none")])
5325 ;; Like nop, but commented out when outside a .set noreorder block.
5326 (define_insn "hazard_nop"
5335 [(set_attr "type" "nop")])
5337 ;; MIPS4 Conditional move instructions.
5339 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5340 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5342 (match_operator:MOVECC 4 "equality_operator"
5343 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5345 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5346 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5351 [(set_attr "type" "condmove")
5352 (set_attr "mode" "<GPR:MODE>")])
5354 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5355 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5356 (if_then_else:SCALARF
5357 (match_operator:MOVECC 4 "equality_operator"
5358 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5360 (match_operand:SCALARF 2 "register_operand" "f,0")
5361 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5364 mov%T4.<fmt>\t%0,%2,%1
5365 mov%t4.<fmt>\t%0,%3,%1"
5366 [(set_attr "type" "condmove")
5367 (set_attr "mode" "<SCALARF:MODE>")])
5369 ;; These are the main define_expand's used to make conditional moves.
5371 (define_expand "mov<mode>cc"
5372 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5373 (set (match_operand:GPR 0 "register_operand")
5374 (if_then_else:GPR (match_dup 5)
5375 (match_operand:GPR 2 "reg_or_0_operand")
5376 (match_operand:GPR 3 "reg_or_0_operand")))]
5379 gen_conditional_move (operands);
5383 (define_expand "mov<mode>cc"
5384 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5385 (set (match_operand:SCALARF 0 "register_operand")
5386 (if_then_else:SCALARF (match_dup 5)
5387 (match_operand:SCALARF 2 "register_operand")
5388 (match_operand:SCALARF 3 "register_operand")))]
5391 gen_conditional_move (operands);
5396 ;; ....................
5398 ;; mips16 inline constant tables
5400 ;; ....................
5403 (define_insn "consttable_int"
5404 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5405 (match_operand 1 "const_int_operand" "")]
5406 UNSPEC_CONSTTABLE_INT)]
5409 assemble_integer (operands[0], INTVAL (operands[1]),
5410 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5413 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5415 (define_insn "consttable_float"
5416 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5417 UNSPEC_CONSTTABLE_FLOAT)]
5422 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5423 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5424 assemble_real (d, GET_MODE (operands[0]),
5425 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5428 [(set (attr "length")
5429 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5431 (define_insn "align"
5432 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5435 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5438 [(match_operand 0 "small_data_pattern")]
5441 { operands[0] = mips_rewrite_small_data (operands[0]); })
5443 ; Thread-Local Storage
5445 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
5446 ; MIPS architecture defines this register, and no current
5447 ; implementation provides it; instead, any OS which supports TLS is
5448 ; expected to trap and emulate this instruction. rdhwr is part of the
5449 ; MIPS 32r2 specification, but we use it on any architecture because
5450 ; we expect it to be emulated. Use .set to force the assembler to
5453 (define_insn "tls_get_tp_<mode>"
5454 [(set (match_operand:P 0 "register_operand" "=v")
5455 (unspec:P [(const_int 0)]
5456 UNSPEC_TLS_GET_TP))]
5457 "HAVE_AS_TLS && !TARGET_MIPS16"
5458 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
5459 [(set_attr "type" "unknown")
5460 (set_attr "mode" "<MODE>")])
5462 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
5464 (include "mips-ps-3d.md")
5466 ; The MIPS DSP Instructions.
5468 (include "mips-dsp.md")