1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
24 ;; Boston, MA 02111-1307, USA.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_EH_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_ADDRESS_FIRST 100)
53 ;; For MIPS Paired-Singled Floating Point Instructions.
55 (UNSPEC_MOVE_TF_PS 200)
58 ;; MIPS64/MIPS32R2 alnv.ps
61 ;; MIPS-3D instructions
65 (UNSPEC_CVT_PW_PS 205)
66 (UNSPEC_CVT_PS_PW 206)
76 (include "predicates.md")
78 ;; ....................
82 ;; ....................
84 (define_attr "got" "unset,xgot_high,load"
85 (const_string "unset"))
87 ;; For jal instructions, this attribute is DIRECT when the target address
88 ;; is symbolic and INDIRECT when it is a register.
89 (define_attr "jal" "unset,direct,indirect"
90 (const_string "unset"))
92 ;; This attribute is YES if the instruction is a jal macro (not a
93 ;; real jal instruction).
95 ;; jal is always a macro in SVR4 PIC since it includes an instruction to
96 ;; restore $gp. Direct jals are also macros in NewABI PIC since they
97 ;; load the target address into $25.
98 (define_attr "jal_macro" "no,yes"
99 (cond [(eq_attr "jal" "direct")
100 (symbol_ref "TARGET_ABICALLS != 0")
101 (eq_attr "jal" "indirect")
102 (symbol_ref "(TARGET_ABICALLS && !TARGET_NEWABI) != 0")]
103 (const_string "no")))
105 ;; Classification of each insn.
106 ;; branch conditional branch
107 ;; jump unconditional jump
108 ;; call unconditional call
109 ;; load load instruction(s)
110 ;; fpload floating point load
111 ;; fpidxload floating point indexed load
112 ;; store store instruction(s)
113 ;; fpstore floating point store
114 ;; fpidxstore floating point indexed store
115 ;; prefetch memory prefetch (register + offset)
116 ;; prefetchx memory indexed prefetch (register + register)
117 ;; condmove conditional moves
118 ;; xfer transfer to/from coprocessor
119 ;; mthilo transfer to hi/lo registers
120 ;; mfhilo transfer from hi/lo registers
121 ;; const load constant
122 ;; arith integer arithmetic and logical instructions
123 ;; shift integer shift instructions
124 ;; slt set less than instructions
125 ;; clz the clz and clo instructions
126 ;; trap trap if instructions
127 ;; imul integer multiply
128 ;; imadd integer multiply-add
129 ;; idiv integer divide
130 ;; fmove floating point register move
131 ;; fadd floating point add/subtract
132 ;; fmul floating point multiply
133 ;; fmadd floating point multiply-add
134 ;; fdiv floating point divide
135 ;; frdiv floating point reciprocal divide
136 ;; frdiv1 floating point reciprocal divide step 1
137 ;; frdiv2 floating point reciprocal divide step 2
138 ;; fabs floating point absolute value
139 ;; fneg floating point negation
140 ;; fcmp floating point compare
141 ;; fcvt floating point convert
142 ;; fsqrt floating point square root
143 ;; frsqrt floating point reciprocal square root
144 ;; frsqrt1 floating point reciprocal square root step1
145 ;; frsqrt2 floating point reciprocal square root step2
146 ;; multi multiword sequence (or user asm statements)
149 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
150 (cond [(eq_attr "jal" "!unset") (const_string "call")
151 (eq_attr "got" "load") (const_string "load")]
152 (const_string "unknown")))
154 ;; Main data type used by the insn
155 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
156 (const_string "unknown"))
158 ;; Is this an extended instruction in mips16 mode?
159 (define_attr "extended_mips16" "no,yes"
162 ;; Length of instruction in bytes.
163 (define_attr "length" ""
164 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
165 ;; If a branch is outside this range, we have a choice of two
166 ;; sequences. For PIC, an out-of-range branch like:
171 ;; becomes the equivalent of:
180 ;; where the load address can be up to three instructions long
183 ;; The non-PIC case is similar except that we use a direct
184 ;; jump instead of an la/jr pair. Since the target of this
185 ;; jump is an absolute 28-bit bit address (the other bits
186 ;; coming from the address of the delay slot) this form cannot
187 ;; cross a 256MB boundary. We could provide the option of
188 ;; using la/jr in this case too, but we do not do so at
191 ;; Note that this value does not account for the delay slot
192 ;; instruction, whose length is added separately. If the RTL
193 ;; pattern has no explicit delay slot, mips_adjust_insn_length
194 ;; will add the length of the implicit nop. The values for
195 ;; forward and backward branches will be different as well.
196 (eq_attr "type" "branch")
197 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
198 (le (minus (pc) (match_dup 1)) (const_int 131068)))
200 (ne (symbol_ref "flag_pic") (const_int 0))
204 (eq_attr "got" "load")
206 (eq_attr "got" "xgot_high")
209 (eq_attr "type" "const")
210 (symbol_ref "mips_const_insns (operands[1]) * 4")
211 (eq_attr "type" "load,fpload")
212 (symbol_ref "mips_fetch_insns (operands[1]) * 4")
213 (eq_attr "type" "store,fpstore")
214 (symbol_ref "mips_fetch_insns (operands[0]) * 4")
216 ;; In the worst case, a call macro will take 8 instructions:
218 ;; lui $25,%call_hi(FOO)
220 ;; lw $25,%call_lo(FOO)($25)
226 (eq_attr "jal_macro" "yes")
229 (and (eq_attr "extended_mips16" "yes")
230 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
233 ;; Various VR4120 errata require a nop to be inserted after a macc
234 ;; instruction. The assembler does this for us, so account for
235 ;; the worst-case length here.
236 (and (eq_attr "type" "imadd")
237 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
240 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
241 ;; the result of the second one is missed. The assembler should work
242 ;; around this by inserting a nop after the first dmult.
243 (and (eq_attr "type" "imul")
244 (and (eq_attr "mode" "DI")
245 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
248 (eq_attr "type" "idiv")
249 (symbol_ref "mips_idiv_insns () * 4")
252 ;; Attribute describing the processor. This attribute must match exactly
253 ;; with the processor_type enumeration in mips.h.
255 "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
256 (const (symbol_ref "mips_tune")))
258 ;; The type of hardware hazard associated with this instruction.
259 ;; DELAY means that the next instruction cannot read the result
260 ;; of this one. HILO means that the next two instructions cannot
261 ;; write to HI or LO.
262 (define_attr "hazard" "none,delay,hilo"
263 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
264 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
265 (const_string "delay")
267 (and (eq_attr "type" "xfer")
268 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
269 (const_string "delay")
271 (and (eq_attr "type" "fcmp")
272 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
273 (const_string "delay")
275 ;; The r4000 multiplication patterns include an mflo instruction.
276 (and (eq_attr "type" "imul")
277 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
278 (const_string "hilo")
280 (and (eq_attr "type" "mfhilo")
281 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
282 (const_string "hilo")]
283 (const_string "none")))
285 ;; Is it a single instruction?
286 (define_attr "single_insn" "no,yes"
287 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
289 ;; Can the instruction be put into a delay slot?
290 (define_attr "can_delay" "no,yes"
291 (if_then_else (and (eq_attr "type" "!branch,call,jump")
292 (and (eq_attr "hazard" "none")
293 (eq_attr "single_insn" "yes")))
295 (const_string "no")))
297 ;; Attribute defining whether or not we can use the branch-likely instructions
298 (define_attr "branch_likely" "no,yes"
300 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
302 (const_string "no"))))
304 ;; True if an instruction might assign to hi or lo when reloaded.
305 ;; This is used by the TUNE_MACC_CHAINS code.
306 (define_attr "may_clobber_hilo" "no,yes"
307 (if_then_else (eq_attr "type" "imul,imadd,idiv,mthilo")
309 (const_string "no")))
311 ;; Describe a user's asm statement.
312 (define_asm_attributes
313 [(set_attr "type" "multi")
314 (set_attr "can_delay" "no")])
316 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
317 ;; from the same template.
318 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
320 ;; This mode macro allows :P to be used for patterns that operate on
321 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
322 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
324 ;; This mode macro allows :MOVECC to be used anywhere that a
325 ;; conditional-move-type condition is needed.
326 (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
328 ;; This mode macro allows the QI and HI extension patterns to be defined from
329 ;; the same template.
330 (define_mode_macro SHORT [QI HI])
332 ;; This mode macro allows :ANYF to be used wherever a scalar or vector
333 ;; floating-point mode is allowed.
334 (define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
335 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
336 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
338 ;; Like ANYF, but only applies to scalar modes.
339 (define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
340 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
342 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
343 ;; 32-bit version and "dsubu" in the 64-bit version.
344 (define_mode_attr d [(SI "") (DI "d")])
346 ;; This attribute gives the length suffix for a sign- or zero-extension
348 (define_mode_attr size [(QI "b") (HI "h")])
350 ;; This attributes gives the mode mask of a SHORT.
351 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
353 ;; Mode attributes for GPR loads and stores.
354 (define_mode_attr load [(SI "lw") (DI "ld")])
355 (define_mode_attr store [(SI "sw") (DI "sd")])
357 ;; Similarly for MIPS IV indexed FPR loads and stores.
358 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
359 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
361 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
362 ;; are different. Some forms of unextended addiu have an 8-bit immediate
363 ;; field but the equivalent daddiu has only a 5-bit field.
364 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
366 ;; This attribute gives the best constraint to use for registers of
368 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
370 ;; This attribute gives the format suffix for floating-point operations.
371 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
373 ;; This attribute gives the upper-case mode name for one unit of a
374 ;; floating-point mode.
375 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
377 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
379 ;; In certain cases, div.s and div.ps may have a rounding error
380 ;; and/or wrong inexact flag.
382 ;; Therefore, we only allow div.s if not working around SB-1 rev2
383 ;; errata or if a slight loss of precision is OK.
384 (define_mode_attr divide_condition
385 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
386 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
388 ; This attribute gives the condition for which sqrt instructions exist.
389 (define_mode_attr sqrt_condition
390 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
392 ; This attribute gives the condition for which recip and rsqrt instructions
394 (define_mode_attr recip_condition
395 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
397 ;; This code macro allows all branch instructions to be generated from
398 ;; a single define_expand template.
399 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
400 eq ne gt ge lt le gtu geu ltu leu])
402 ;; This code macro allows signed and unsigned widening multiplications
403 ;; to use the same template.
404 (define_code_macro any_extend [sign_extend zero_extend])
406 ;; This code macro allows the three shift instructions to be generated
407 ;; from the same template.
408 (define_code_macro any_shift [ashift ashiftrt lshiftrt])
410 ;; This code macro allows all native floating-point comparisons to be
411 ;; generated from the same template.
412 (define_code_macro fcond [unordered uneq unlt unle eq lt le])
414 ;; <u> expands to an empty string when doing a signed operation and
415 ;; "u" when doing an unsigned operation.
416 (define_code_attr u [(sign_extend "") (zero_extend "u")])
418 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
419 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
421 ;; <optab> expands to the name of the optab for a particular code.
422 (define_code_attr optab [(ashift "ashl")
426 ;; <insn> expands to the name of the insn that implements a particular code.
427 (define_code_attr insn [(ashift "sll")
431 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
432 (define_code_attr fcond [(unordered "un")
440 ;; .........................
442 ;; Branch, call and jump delay slots
444 ;; .........................
446 (define_delay (and (eq_attr "type" "branch")
447 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
448 [(eq_attr "can_delay" "yes")
450 (and (eq_attr "branch_likely" "yes")
451 (eq_attr "can_delay" "yes"))])
453 (define_delay (eq_attr "type" "jump")
454 [(eq_attr "can_delay" "yes")
458 (define_delay (and (eq_attr "type" "call")
459 (eq_attr "jal_macro" "no"))
460 [(eq_attr "can_delay" "yes")
464 ;; Pipeline descriptions.
466 ;; generic.md provides a fallback for processors without a specific
467 ;; pipeline description. It is derived from the old define_function_unit
468 ;; version and uses the "alu" and "imuldiv" units declared below.
470 ;; Some of the processor-specific files are also derived from old
471 ;; define_function_unit descriptions and simply override the parts of
472 ;; generic.md that don't apply. The other processor-specific files
473 ;; are self-contained.
474 (define_automaton "alu,imuldiv")
476 (define_cpu_unit "alu" "alu")
477 (define_cpu_unit "imuldiv" "imuldiv")
493 (include "generic.md")
496 ;; ....................
500 ;; ....................
504 [(trap_if (const_int 1) (const_int 0))]
507 if (ISA_HAS_COND_TRAP)
509 else if (TARGET_MIPS16)
514 [(set_attr "type" "trap")])
516 (define_expand "conditional_trap"
517 [(trap_if (match_operator 0 "comparison_operator"
518 [(match_dup 2) (match_dup 3)])
519 (match_operand 1 "const_int_operand"))]
522 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
523 && operands[1] == const0_rtx)
525 mips_gen_conditional_trap (operands);
532 (define_insn "*conditional_trap<mode>"
533 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
534 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
535 (match_operand:GPR 2 "arith_operand" "dI")])
539 [(set_attr "type" "trap")])
542 ;; ....................
546 ;; ....................
549 (define_insn "add<mode>3"
550 [(set (match_operand:ANYF 0 "register_operand" "=f")
551 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
552 (match_operand:ANYF 2 "register_operand" "f")))]
554 "add.<fmt>\t%0,%1,%2"
555 [(set_attr "type" "fadd")
556 (set_attr "mode" "<UNITMODE>")])
558 (define_expand "add<mode>3"
559 [(set (match_operand:GPR 0 "register_operand")
560 (plus:GPR (match_operand:GPR 1 "register_operand")
561 (match_operand:GPR 2 "arith_operand")))]
564 (define_insn "*add<mode>3"
565 [(set (match_operand:GPR 0 "register_operand" "=d,d")
566 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
567 (match_operand:GPR 2 "arith_operand" "d,Q")))]
572 [(set_attr "type" "arith")
573 (set_attr "mode" "<MODE>")])
575 ;; We need to recognize MIPS16 stack pointer additions explicitly, since
576 ;; we don't have a constraint for $sp. These insns will be generated by
577 ;; the save_restore_insns functions.
579 (define_insn "*add<mode>3_sp1"
581 (plus:GPR (reg:GPR 29)
582 (match_operand:GPR 0 "const_arith_operand" "")))]
585 [(set_attr "type" "arith")
586 (set_attr "mode" "<MODE>")
587 (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")
591 (define_insn "*add<mode>3_sp2"
592 [(set (match_operand:GPR 0 "register_operand" "=d")
593 (plus:GPR (reg:GPR 29)
594 (match_operand:GPR 1 "const_arith_operand" "")))]
597 [(set_attr "type" "arith")
598 (set_attr "mode" "<MODE>")
599 (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4")
603 (define_insn "*add<mode>3_mips16"
604 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
605 (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")
606 (match_operand:GPR 2 "arith_operand" "Q,O,d")))]
612 [(set_attr "type" "arith")
613 (set_attr "mode" "<MODE>")
614 (set_attr_alternative "length"
615 [(if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
618 (if_then_else (match_operand 2 "m16_simm4_1")
624 ;; On the mips16, we can sometimes split an add of a constant which is
625 ;; a 4 byte instruction into two adds which are both 2 byte
626 ;; instructions. There are two cases: one where we are adding a
627 ;; constant plus a register to another register, and one where we are
628 ;; simply adding a constant to a register.
631 [(set (match_operand:SI 0 "register_operand")
632 (plus:SI (match_dup 0)
633 (match_operand:SI 1 "const_int_operand")))]
634 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
635 && GET_CODE (operands[0]) == REG
636 && M16_REG_P (REGNO (operands[0]))
637 && GET_CODE (operands[1]) == CONST_INT
638 && ((INTVAL (operands[1]) > 0x7f
639 && INTVAL (operands[1]) <= 0x7f + 0x7f)
640 || (INTVAL (operands[1]) < - 0x80
641 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
642 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
643 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
645 HOST_WIDE_INT val = INTVAL (operands[1]);
649 operands[1] = GEN_INT (0x7f);
650 operands[2] = GEN_INT (val - 0x7f);
654 operands[1] = GEN_INT (- 0x80);
655 operands[2] = GEN_INT (val + 0x80);
660 [(set (match_operand:SI 0 "register_operand")
661 (plus:SI (match_operand:SI 1 "register_operand")
662 (match_operand:SI 2 "const_int_operand")))]
663 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
664 && GET_CODE (operands[0]) == REG
665 && M16_REG_P (REGNO (operands[0]))
666 && GET_CODE (operands[1]) == REG
667 && M16_REG_P (REGNO (operands[1]))
668 && REGNO (operands[0]) != REGNO (operands[1])
669 && GET_CODE (operands[2]) == CONST_INT
670 && ((INTVAL (operands[2]) > 0x7
671 && INTVAL (operands[2]) <= 0x7 + 0x7f)
672 || (INTVAL (operands[2]) < - 0x8
673 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
674 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
675 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
677 HOST_WIDE_INT val = INTVAL (operands[2]);
681 operands[2] = GEN_INT (0x7);
682 operands[3] = GEN_INT (val - 0x7);
686 operands[2] = GEN_INT (- 0x8);
687 operands[3] = GEN_INT (val + 0x8);
692 [(set (match_operand:DI 0 "register_operand")
693 (plus:DI (match_dup 0)
694 (match_operand:DI 1 "const_int_operand")))]
695 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
696 && GET_CODE (operands[0]) == REG
697 && M16_REG_P (REGNO (operands[0]))
698 && GET_CODE (operands[1]) == CONST_INT
699 && ((INTVAL (operands[1]) > 0xf
700 && INTVAL (operands[1]) <= 0xf + 0xf)
701 || (INTVAL (operands[1]) < - 0x10
702 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
703 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
704 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
706 HOST_WIDE_INT val = INTVAL (operands[1]);
710 operands[1] = GEN_INT (0xf);
711 operands[2] = GEN_INT (val - 0xf);
715 operands[1] = GEN_INT (- 0x10);
716 operands[2] = GEN_INT (val + 0x10);
721 [(set (match_operand:DI 0 "register_operand")
722 (plus:DI (match_operand:DI 1 "register_operand")
723 (match_operand:DI 2 "const_int_operand")))]
724 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
725 && GET_CODE (operands[0]) == REG
726 && M16_REG_P (REGNO (operands[0]))
727 && GET_CODE (operands[1]) == REG
728 && M16_REG_P (REGNO (operands[1]))
729 && REGNO (operands[0]) != REGNO (operands[1])
730 && GET_CODE (operands[2]) == CONST_INT
731 && ((INTVAL (operands[2]) > 0x7
732 && INTVAL (operands[2]) <= 0x7 + 0xf)
733 || (INTVAL (operands[2]) < - 0x8
734 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
735 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
736 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
738 HOST_WIDE_INT val = INTVAL (operands[2]);
742 operands[2] = GEN_INT (0x7);
743 operands[3] = GEN_INT (val - 0x7);
747 operands[2] = GEN_INT (- 0x8);
748 operands[3] = GEN_INT (val + 0x8);
752 (define_insn "*addsi3_extended"
753 [(set (match_operand:DI 0 "register_operand" "=d,d")
755 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
756 (match_operand:SI 2 "arith_operand" "d,Q"))))]
757 "TARGET_64BIT && !TARGET_MIPS16"
761 [(set_attr "type" "arith")
762 (set_attr "mode" "SI")])
764 ;; Split this insn so that the addiu splitters can have a crack at it.
765 ;; Use a conservative length estimate until the split.
766 (define_insn_and_split "*addsi3_extended_mips16"
767 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
769 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
770 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
771 "TARGET_64BIT && TARGET_MIPS16"
773 "&& reload_completed"
774 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
775 { operands[3] = gen_lowpart (SImode, operands[0]); }
776 [(set_attr "type" "arith")
777 (set_attr "mode" "SI")
778 (set_attr "extended_mips16" "yes")])
781 ;; ....................
785 ;; ....................
788 (define_insn "sub<mode>3"
789 [(set (match_operand:ANYF 0 "register_operand" "=f")
790 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
791 (match_operand:ANYF 2 "register_operand" "f")))]
793 "sub.<fmt>\t%0,%1,%2"
794 [(set_attr "type" "fadd")
795 (set_attr "mode" "<UNITMODE>")])
797 (define_insn "sub<mode>3"
798 [(set (match_operand:GPR 0 "register_operand" "=d")
799 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
800 (match_operand:GPR 2 "register_operand" "d")))]
803 [(set_attr "type" "arith")
804 (set_attr "mode" "<MODE>")])
806 (define_insn "*subsi3_extended"
807 [(set (match_operand:DI 0 "register_operand" "=d")
809 (minus:SI (match_operand:SI 1 "register_operand" "d")
810 (match_operand:SI 2 "register_operand" "d"))))]
813 [(set_attr "type" "arith")
814 (set_attr "mode" "DI")])
817 ;; ....................
821 ;; ....................
824 (define_expand "mul<mode>3"
825 [(set (match_operand:SCALARF 0 "register_operand")
826 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
827 (match_operand:SCALARF 2 "register_operand")))]
831 (define_insn "*mul<mode>3"
832 [(set (match_operand:SCALARF 0 "register_operand" "=f")
833 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
834 (match_operand:SCALARF 2 "register_operand" "f")))]
835 "!TARGET_4300_MUL_FIX"
836 "mul.<fmt>\t%0,%1,%2"
837 [(set_attr "type" "fmul")
838 (set_attr "mode" "<MODE>")])
840 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
841 ;; operands may corrupt immediately following multiplies. This is a
842 ;; simple fix to insert NOPs.
844 (define_insn "*mul<mode>3_r4300"
845 [(set (match_operand:SCALARF 0 "register_operand" "=f")
846 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
847 (match_operand:SCALARF 2 "register_operand" "f")))]
848 "TARGET_4300_MUL_FIX"
849 "mul.<fmt>\t%0,%1,%2\;nop"
850 [(set_attr "type" "fmul")
851 (set_attr "mode" "<MODE>")
852 (set_attr "length" "8")])
854 (define_insn "mulv2sf3"
855 [(set (match_operand:V2SF 0 "register_operand" "=f")
856 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
857 (match_operand:V2SF 2 "register_operand" "f")))]
858 "TARGET_PAIRED_SINGLE_FLOAT"
860 [(set_attr "type" "fmul")
861 (set_attr "mode" "SF")])
863 ;; The original R4000 has a cpu bug. If a double-word or a variable
864 ;; shift executes while an integer multiplication is in progress, the
865 ;; shift may give an incorrect result. Avoid this by keeping the mflo
866 ;; with the mult on the R4000.
868 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
869 ;; (also valid for MIPS R4000MC processors):
871 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
872 ;; this errata description.
873 ;; The following code sequence causes the R4000 to incorrectly
874 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
875 ;; instruction. If the dsra32 instruction is executed during an
876 ;; integer multiply, the dsra32 will only shift by the amount in
877 ;; specified in the instruction rather than the amount plus 32
879 ;; instruction 1: mult rs,rt integer multiply
880 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
881 ;; right arithmetic + 32
882 ;; Workaround: A dsra32 instruction placed after an integer
883 ;; multiply should not be one of the 11 instructions after the
884 ;; multiply instruction."
888 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
889 ;; the following description.
890 ;; All extended shifts (shift by n+32) and variable shifts (32 and
891 ;; 64-bit versions) may produce incorrect results under the
892 ;; following conditions:
893 ;; 1) An integer multiply is currently executing
894 ;; 2) These types of shift instructions are executed immediately
895 ;; following an integer divide instruction.
897 ;; 1) Make sure no integer multiply is running wihen these
898 ;; instruction are executed. If this cannot be predicted at
899 ;; compile time, then insert a "mfhi" to R0 instruction
900 ;; immediately after the integer multiply instruction. This
901 ;; will cause the integer multiply to complete before the shift
903 ;; 2) Separate integer divide and these two classes of shift
904 ;; instructions by another instruction or a noop."
906 ;; These processors have PRId values of 0x00004220 and 0x00004300,
909 (define_expand "mul<mode>3"
910 [(set (match_operand:GPR 0 "register_operand")
911 (mult:GPR (match_operand:GPR 1 "register_operand")
912 (match_operand:GPR 2 "register_operand")))]
915 if (GENERATE_MULT3_<MODE>)
916 emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2]));
917 else if (!TARGET_FIX_R4000)
918 emit_insn (gen_mul<mode>3_internal (operands[0], operands[1],
921 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
925 (define_insn "mulsi3_mult3"
926 [(set (match_operand:SI 0 "register_operand" "=d,l")
927 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
928 (match_operand:SI 2 "register_operand" "d,d")))
929 (clobber (match_scratch:SI 3 "=h,h"))
930 (clobber (match_scratch:SI 4 "=l,X"))]
933 if (which_alternative == 1)
934 return "mult\t%1,%2";
943 return "mul\t%0,%1,%2";
944 return "mult\t%0,%1,%2";
946 [(set_attr "type" "imul")
947 (set_attr "mode" "SI")])
949 (define_insn "muldi3_mult3"
950 [(set (match_operand:DI 0 "register_operand" "=d")
951 (mult:DI (match_operand:DI 1 "register_operand" "d")
952 (match_operand:DI 2 "register_operand" "d")))
953 (clobber (match_scratch:DI 3 "=h"))
954 (clobber (match_scratch:DI 4 "=l"))]
955 "TARGET_64BIT && GENERATE_MULT3_DI"
957 [(set_attr "type" "imul")
958 (set_attr "mode" "DI")])
960 ;; If a register gets allocated to LO, and we spill to memory, the reload
961 ;; will include a move from LO to a GPR. Merge it into the multiplication
962 ;; if it can set the GPR directly.
965 ;; Operand 1: GPR (1st multiplication operand)
966 ;; Operand 2: GPR (2nd multiplication operand)
968 ;; Operand 4: GPR (destination)
971 [(set (match_operand:SI 0 "register_operand")
972 (mult:SI (match_operand:SI 1 "register_operand")
973 (match_operand:SI 2 "register_operand")))
974 (clobber (match_operand:SI 3 "register_operand"))
975 (clobber (scratch:SI))])
976 (set (match_operand:SI 4 "register_operand")
977 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
978 "GENERATE_MULT3_SI && peep2_reg_dead_p (2, operands[0])"
981 (mult:SI (match_dup 1)
983 (clobber (match_dup 3))
984 (clobber (match_dup 0))])])
986 (define_insn "mul<mode>3_internal"
987 [(set (match_operand:GPR 0 "register_operand" "=l")
988 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
989 (match_operand:GPR 2 "register_operand" "d")))
990 (clobber (match_scratch:GPR 3 "=h"))]
993 [(set_attr "type" "imul")
994 (set_attr "mode" "<MODE>")])
996 (define_insn "mul<mode>3_r4000"
997 [(set (match_operand:GPR 0 "register_operand" "=d")
998 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
999 (match_operand:GPR 2 "register_operand" "d")))
1000 (clobber (match_scratch:GPR 3 "=h"))
1001 (clobber (match_scratch:GPR 4 "=l"))]
1003 "<d>mult\t%1,%2\;mflo\t%0"
1004 [(set_attr "type" "imul")
1005 (set_attr "mode" "<MODE>")
1006 (set_attr "length" "8")])
1008 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1009 ;; of "mult; mflo". They have the same latency, but the first form gives
1010 ;; us an extra cycle to compute the operands.
1013 ;; Operand 1: GPR (1st multiplication operand)
1014 ;; Operand 2: GPR (2nd multiplication operand)
1016 ;; Operand 4: GPR (destination)
1019 [(set (match_operand:SI 0 "register_operand")
1020 (mult:SI (match_operand:SI 1 "register_operand")
1021 (match_operand:SI 2 "register_operand")))
1022 (clobber (match_operand:SI 3 "register_operand"))])
1023 (set (match_operand:SI 4 "register_operand")
1024 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1025 "ISA_HAS_MACC && !GENERATE_MULT3_SI"
1030 (plus:SI (mult:SI (match_dup 1)
1034 (plus:SI (mult:SI (match_dup 1)
1037 (clobber (match_dup 3))])])
1039 ;; Multiply-accumulate patterns
1041 ;; For processors that can copy the output to a general register:
1043 ;; The all-d alternative is needed because the combiner will find this
1044 ;; pattern and then register alloc/reload will move registers around to
1045 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1047 ;; The last alternative should be made slightly less desirable, but adding
1048 ;; "?" to the constraint is too strong, and causes values to be loaded into
1049 ;; LO even when that's more costly. For now, using "*d" mostly does the
1051 (define_insn "*mul_acc_si"
1052 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1053 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1054 (match_operand:SI 2 "register_operand" "d,d,d"))
1055 (match_operand:SI 3 "register_operand" "0,l,*d")))
1056 (clobber (match_scratch:SI 4 "=h,h,h"))
1057 (clobber (match_scratch:SI 5 "=X,3,l"))
1058 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1060 || ISA_HAS_MADD_MSUB)
1063 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1064 if (which_alternative == 2)
1066 if (ISA_HAS_MADD_MSUB && which_alternative != 0)
1068 return madd[which_alternative];
1070 [(set_attr "type" "imadd,imadd,multi")
1071 (set_attr "mode" "SI")
1072 (set_attr "length" "4,4,8")])
1074 ;; Split the above insn if we failed to get LO allocated.
1076 [(set (match_operand:SI 0 "register_operand")
1077 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1078 (match_operand:SI 2 "register_operand"))
1079 (match_operand:SI 3 "register_operand")))
1080 (clobber (match_scratch:SI 4))
1081 (clobber (match_scratch:SI 5))
1082 (clobber (match_scratch:SI 6))]
1083 "reload_completed && !TARGET_DEBUG_D_MODE
1084 && GP_REG_P (true_regnum (operands[0]))
1085 && GP_REG_P (true_regnum (operands[3]))"
1086 [(parallel [(set (match_dup 6)
1087 (mult:SI (match_dup 1) (match_dup 2)))
1088 (clobber (match_dup 4))
1089 (clobber (match_dup 5))])
1090 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1093 ;; Splitter to copy result of MADD to a general register
1095 [(set (match_operand:SI 0 "register_operand")
1096 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1097 (match_operand:SI 2 "register_operand"))
1098 (match_operand:SI 3 "register_operand")))
1099 (clobber (match_scratch:SI 4))
1100 (clobber (match_scratch:SI 5))
1101 (clobber (match_scratch:SI 6))]
1102 "reload_completed && !TARGET_DEBUG_D_MODE
1103 && GP_REG_P (true_regnum (operands[0]))
1104 && true_regnum (operands[3]) == LO_REGNUM"
1105 [(parallel [(set (match_dup 3)
1106 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1108 (clobber (match_dup 4))
1109 (clobber (match_dup 5))
1110 (clobber (match_dup 6))])
1111 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1114 (define_insn "*macc"
1115 [(set (match_operand:SI 0 "register_operand" "=l,d")
1116 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1117 (match_operand:SI 2 "register_operand" "d,d"))
1118 (match_operand:SI 3 "register_operand" "0,l")))
1119 (clobber (match_scratch:SI 4 "=h,h"))
1120 (clobber (match_scratch:SI 5 "=X,3"))]
1123 if (which_alternative == 1)
1124 return "macc\t%0,%1,%2";
1125 else if (TARGET_MIPS5500)
1126 return "madd\t%1,%2";
1128 /* The VR4130 assumes that there is a two-cycle latency between a macc
1129 that "writes" to $0 and an instruction that reads from it. We avoid
1130 this by assigning to $1 instead. */
1131 return "%[macc\t%@,%1,%2%]";
1133 [(set_attr "type" "imadd")
1134 (set_attr "mode" "SI")])
1136 (define_insn "*msac"
1137 [(set (match_operand:SI 0 "register_operand" "=l,d")
1138 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1139 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1140 (match_operand:SI 3 "register_operand" "d,d"))))
1141 (clobber (match_scratch:SI 4 "=h,h"))
1142 (clobber (match_scratch:SI 5 "=X,1"))]
1145 if (which_alternative == 1)
1146 return "msac\t%0,%2,%3";
1147 else if (TARGET_MIPS5500)
1148 return "msub\t%2,%3";
1150 return "msac\t$0,%2,%3";
1152 [(set_attr "type" "imadd")
1153 (set_attr "mode" "SI")])
1155 ;; An msac-like instruction implemented using negation and a macc.
1156 (define_insn_and_split "*msac_using_macc"
1157 [(set (match_operand:SI 0 "register_operand" "=l,d")
1158 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1159 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1160 (match_operand:SI 3 "register_operand" "d,d"))))
1161 (clobber (match_scratch:SI 4 "=h,h"))
1162 (clobber (match_scratch:SI 5 "=X,1"))
1163 (clobber (match_scratch:SI 6 "=d,d"))]
1164 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1166 "&& reload_completed"
1168 (neg:SI (match_dup 3)))
1171 (plus:SI (mult:SI (match_dup 2)
1174 (clobber (match_dup 4))
1175 (clobber (match_dup 5))])]
1177 [(set_attr "type" "imadd")
1178 (set_attr "length" "8")])
1180 ;; Patterns generated by the define_peephole2 below.
1182 (define_insn "*macc2"
1183 [(set (match_operand:SI 0 "register_operand" "=l")
1184 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1185 (match_operand:SI 2 "register_operand" "d"))
1187 (set (match_operand:SI 3 "register_operand" "=d")
1188 (plus:SI (mult:SI (match_dup 1)
1191 (clobber (match_scratch:SI 4 "=h"))]
1192 "ISA_HAS_MACC && reload_completed"
1194 [(set_attr "type" "imadd")
1195 (set_attr "mode" "SI")])
1197 (define_insn "*msac2"
1198 [(set (match_operand:SI 0 "register_operand" "=l")
1199 (minus:SI (match_dup 0)
1200 (mult:SI (match_operand:SI 1 "register_operand" "d")
1201 (match_operand:SI 2 "register_operand" "d"))))
1202 (set (match_operand:SI 3 "register_operand" "=d")
1203 (minus:SI (match_dup 0)
1204 (mult:SI (match_dup 1)
1206 (clobber (match_scratch:SI 4 "=h"))]
1207 "ISA_HAS_MSAC && reload_completed"
1209 [(set_attr "type" "imadd")
1210 (set_attr "mode" "SI")])
1212 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1216 ;; Operand 1: macc/msac
1218 ;; Operand 3: GPR (destination)
1221 [(set (match_operand:SI 0 "register_operand")
1222 (match_operand:SI 1 "macc_msac_operand"))
1223 (clobber (match_operand:SI 2 "register_operand"))
1224 (clobber (scratch:SI))])
1225 (set (match_operand:SI 3 "register_operand")
1226 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1228 [(parallel [(set (match_dup 0)
1232 (clobber (match_dup 2))])]
1235 ;; When we have a three-address multiplication instruction, it should
1236 ;; be faster to do a separate multiply and add, rather than moving
1237 ;; something into LO in order to use a macc instruction.
1239 ;; This peephole needs a scratch register to cater for the case when one
1240 ;; of the multiplication operands is the same as the destination.
1242 ;; Operand 0: GPR (scratch)
1244 ;; Operand 2: GPR (addend)
1245 ;; Operand 3: GPR (destination)
1246 ;; Operand 4: macc/msac
1248 ;; Operand 6: new multiplication
1249 ;; Operand 7: new addition/subtraction
1251 [(match_scratch:SI 0 "d")
1252 (set (match_operand:SI 1 "register_operand")
1253 (match_operand:SI 2 "register_operand"))
1256 [(set (match_operand:SI 3 "register_operand")
1257 (match_operand:SI 4 "macc_msac_operand"))
1258 (clobber (match_operand:SI 5 "register_operand"))
1259 (clobber (match_dup 1))])]
1261 && true_regnum (operands[1]) == LO_REGNUM
1262 && peep2_reg_dead_p (2, operands[1])
1263 && GP_REG_P (true_regnum (operands[3]))"
1264 [(parallel [(set (match_dup 0)
1266 (clobber (match_dup 5))
1267 (clobber (match_dup 1))])
1271 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1272 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1273 operands[2], operands[0]);
1276 ;; Same as above, except LO is the initial target of the macc.
1278 ;; Operand 0: GPR (scratch)
1280 ;; Operand 2: GPR (addend)
1281 ;; Operand 3: macc/msac
1283 ;; Operand 5: GPR (destination)
1284 ;; Operand 6: new multiplication
1285 ;; Operand 7: new addition/subtraction
1287 [(match_scratch:SI 0 "d")
1288 (set (match_operand:SI 1 "register_operand")
1289 (match_operand:SI 2 "register_operand"))
1293 (match_operand:SI 3 "macc_msac_operand"))
1294 (clobber (match_operand:SI 4 "register_operand"))
1295 (clobber (scratch:SI))])
1297 (set (match_operand:SI 5 "register_operand")
1298 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1299 "GENERATE_MULT3_SI && peep2_reg_dead_p (3, operands[1])"
1300 [(parallel [(set (match_dup 0)
1302 (clobber (match_dup 4))
1303 (clobber (match_dup 1))])
1307 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1308 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1309 operands[2], operands[0]);
1312 (define_insn "*mul_sub_si"
1313 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1314 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1315 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1316 (match_operand:SI 3 "register_operand" "d,d,d"))))
1317 (clobber (match_scratch:SI 4 "=h,h,h"))
1318 (clobber (match_scratch:SI 5 "=X,1,l"))
1319 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1325 [(set_attr "type" "imadd,multi,multi")
1326 (set_attr "mode" "SI")
1327 (set_attr "length" "4,8,8")])
1329 ;; Split the above insn if we failed to get LO allocated.
1331 [(set (match_operand:SI 0 "register_operand")
1332 (minus:SI (match_operand:SI 1 "register_operand")
1333 (mult:SI (match_operand:SI 2 "register_operand")
1334 (match_operand:SI 3 "register_operand"))))
1335 (clobber (match_scratch:SI 4))
1336 (clobber (match_scratch:SI 5))
1337 (clobber (match_scratch:SI 6))]
1338 "reload_completed && !TARGET_DEBUG_D_MODE
1339 && GP_REG_P (true_regnum (operands[0]))
1340 && GP_REG_P (true_regnum (operands[1]))"
1341 [(parallel [(set (match_dup 6)
1342 (mult:SI (match_dup 2) (match_dup 3)))
1343 (clobber (match_dup 4))
1344 (clobber (match_dup 5))])
1345 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1348 ;; Splitter to copy result of MSUB to a general register
1350 [(set (match_operand:SI 0 "register_operand")
1351 (minus:SI (match_operand:SI 1 "register_operand")
1352 (mult:SI (match_operand:SI 2 "register_operand")
1353 (match_operand:SI 3 "register_operand"))))
1354 (clobber (match_scratch:SI 4))
1355 (clobber (match_scratch:SI 5))
1356 (clobber (match_scratch:SI 6))]
1357 "reload_completed && !TARGET_DEBUG_D_MODE
1358 && GP_REG_P (true_regnum (operands[0]))
1359 && true_regnum (operands[1]) == LO_REGNUM"
1360 [(parallel [(set (match_dup 1)
1361 (minus:SI (match_dup 1)
1362 (mult:SI (match_dup 2) (match_dup 3))))
1363 (clobber (match_dup 4))
1364 (clobber (match_dup 5))
1365 (clobber (match_dup 6))])
1366 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1369 (define_insn "*muls"
1370 [(set (match_operand:SI 0 "register_operand" "=l,d")
1371 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1372 (match_operand:SI 2 "register_operand" "d,d"))))
1373 (clobber (match_scratch:SI 3 "=h,h"))
1374 (clobber (match_scratch:SI 4 "=X,l"))]
1379 [(set_attr "type" "imul")
1380 (set_attr "mode" "SI")])
1382 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1384 (define_expand "<u>mulsidi3"
1386 [(set (match_operand:DI 0 "register_operand")
1387 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1388 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1389 (clobber (scratch:DI))
1390 (clobber (scratch:DI))
1391 (clobber (scratch:DI))])]
1392 "!TARGET_64BIT || !TARGET_FIX_R4000"
1396 if (!TARGET_FIX_R4000)
1397 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1400 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1406 (define_insn "<u>mulsidi3_32bit_internal"
1407 [(set (match_operand:DI 0 "register_operand" "=x")
1408 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1409 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1410 "!TARGET_64BIT && !TARGET_FIX_R4000"
1412 [(set_attr "type" "imul")
1413 (set_attr "mode" "SI")])
1415 (define_insn "<u>mulsidi3_32bit_r4000"
1416 [(set (match_operand:DI 0 "register_operand" "=d")
1417 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1418 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1419 (clobber (match_scratch:DI 3 "=x"))]
1420 "!TARGET_64BIT && TARGET_FIX_R4000"
1421 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1422 [(set_attr "type" "imul")
1423 (set_attr "mode" "SI")
1424 (set_attr "length" "12")])
1426 (define_insn_and_split "*<u>mulsidi3_64bit"
1427 [(set (match_operand:DI 0 "register_operand" "=d")
1428 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1429 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1430 (clobber (match_scratch:DI 3 "=l"))
1431 (clobber (match_scratch:DI 4 "=h"))
1432 (clobber (match_scratch:DI 5 "=d"))]
1433 "TARGET_64BIT && !TARGET_FIX_R4000"
1435 "&& reload_completed"
1439 (mult:SI (match_dup 1)
1443 (mult:DI (any_extend:DI (match_dup 1))
1444 (any_extend:DI (match_dup 2)))
1447 ;; OP5 <- LO, OP0 <- HI
1448 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1449 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1453 (ashift:DI (match_dup 5)
1456 (lshiftrt:DI (match_dup 5)
1459 ;; Shift OP0 into place.
1461 (ashift:DI (match_dup 0)
1464 ;; OR the two halves together
1466 (ior:DI (match_dup 0)
1469 [(set_attr "type" "imul")
1470 (set_attr "mode" "SI")
1471 (set_attr "length" "24")])
1473 (define_insn "*<u>mulsidi3_64bit_parts"
1474 [(set (match_operand:DI 0 "register_operand" "=l")
1476 (mult:SI (match_operand:SI 2 "register_operand" "d")
1477 (match_operand:SI 3 "register_operand" "d"))))
1478 (set (match_operand:DI 1 "register_operand" "=h")
1480 (mult:DI (any_extend:DI (match_dup 2))
1481 (any_extend:DI (match_dup 3)))
1483 "TARGET_64BIT && !TARGET_FIX_R4000"
1485 [(set_attr "type" "imul")
1486 (set_attr "mode" "SI")])
1488 ;; Widening multiply with negation.
1489 (define_insn "*muls<u>_di"
1490 [(set (match_operand:DI 0 "register_operand" "=x")
1493 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1494 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1495 "!TARGET_64BIT && ISA_HAS_MULS"
1497 [(set_attr "type" "imul")
1498 (set_attr "mode" "SI")])
1500 (define_insn "*msac<u>_di"
1501 [(set (match_operand:DI 0 "register_operand" "=x")
1503 (match_operand:DI 3 "register_operand" "0")
1505 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1506 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1507 "!TARGET_64BIT && ISA_HAS_MSAC"
1509 if (TARGET_MIPS5500)
1510 return "msub<u>\t%1,%2";
1512 return "msac<u>\t$0,%1,%2";
1514 [(set_attr "type" "imadd")
1515 (set_attr "mode" "SI")])
1517 ;; _highpart patterns
1519 (define_expand "<su>mulsi3_highpart"
1520 [(set (match_operand:SI 0 "register_operand")
1523 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1524 (any_extend:DI (match_operand:SI 2 "register_operand")))
1526 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1529 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1533 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1538 (define_insn "<su>mulsi3_highpart_internal"
1539 [(set (match_operand:SI 0 "register_operand" "=h")
1542 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1543 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1545 (clobber (match_scratch:SI 3 "=l"))]
1546 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1548 [(set_attr "type" "imul")
1549 (set_attr "mode" "SI")])
1551 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1552 [(set (match_operand:SI 0 "register_operand" "=h,d")
1556 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1557 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1559 (clobber (match_scratch:SI 3 "=l,l"))
1560 (clobber (match_scratch:SI 4 "=X,h"))]
1565 [(set_attr "type" "imul")
1566 (set_attr "mode" "SI")])
1568 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1569 [(set (match_operand:SI 0 "register_operand" "=h,d")
1574 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1575 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1577 (clobber (match_scratch:SI 3 "=l,l"))
1578 (clobber (match_scratch:SI 4 "=X,h"))]
1582 mulshi<u>\t%0,%1,%2"
1583 [(set_attr "type" "imul")
1584 (set_attr "mode" "SI")])
1586 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1587 ;; errata MD(0), which says that dmultu does not always produce the
1589 (define_insn "<su>muldi3_highpart"
1590 [(set (match_operand:DI 0 "register_operand" "=h")
1594 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1595 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1597 (clobber (match_scratch:DI 3 "=l"))]
1598 "TARGET_64BIT && !TARGET_FIX_R4000
1599 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1601 [(set_attr "type" "imul")
1602 (set_attr "mode" "DI")])
1604 ;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
1605 ;; instruction. The HI/LO registers are used as a 64 bit accumulator.
1607 (define_insn "madsi"
1608 [(set (match_operand:SI 0 "register_operand" "+l")
1609 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1610 (match_operand:SI 2 "register_operand" "d"))
1612 (clobber (match_scratch:SI 3 "=h"))]
1615 [(set_attr "type" "imadd")
1616 (set_attr "mode" "SI")])
1618 (define_insn "*<su>mul_acc_di"
1619 [(set (match_operand:DI 0 "register_operand" "=x")
1621 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1622 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1623 (match_operand:DI 3 "register_operand" "0")))]
1624 "(TARGET_MAD || ISA_HAS_MACC)
1628 return "mad<u>\t%1,%2";
1629 else if (TARGET_MIPS5500)
1630 return "madd<u>\t%1,%2";
1632 /* See comment in *macc. */
1633 return "%[macc<u>\t%@,%1,%2%]";
1635 [(set_attr "type" "imadd")
1636 (set_attr "mode" "SI")])
1638 ;; Floating point multiply accumulate instructions.
1640 (define_insn "*madd<mode>"
1641 [(set (match_operand:ANYF 0 "register_operand" "=f")
1642 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1643 (match_operand:ANYF 2 "register_operand" "f"))
1644 (match_operand:ANYF 3 "register_operand" "f")))]
1645 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1646 "madd.<fmt>\t%0,%3,%1,%2"
1647 [(set_attr "type" "fmadd")
1648 (set_attr "mode" "<UNITMODE>")])
1650 (define_insn "*msub<mode>"
1651 [(set (match_operand:ANYF 0 "register_operand" "=f")
1652 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1653 (match_operand:ANYF 2 "register_operand" "f"))
1654 (match_operand:ANYF 3 "register_operand" "f")))]
1655 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1656 "msub.<fmt>\t%0,%3,%1,%2"
1657 [(set_attr "type" "fmadd")
1658 (set_attr "mode" "<UNITMODE>")])
1660 (define_insn "*nmadd<mode>"
1661 [(set (match_operand:ANYF 0 "register_operand" "=f")
1662 (neg:ANYF (plus:ANYF
1663 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1664 (match_operand:ANYF 2 "register_operand" "f"))
1665 (match_operand:ANYF 3 "register_operand" "f"))))]
1666 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1667 && HONOR_SIGNED_ZEROS (<MODE>mode)"
1668 "nmadd.<fmt>\t%0,%3,%1,%2"
1669 [(set_attr "type" "fmadd")
1670 (set_attr "mode" "<UNITMODE>")])
1672 (define_insn "*nmadd<mode>_fastmath"
1673 [(set (match_operand:ANYF 0 "register_operand" "=f")
1675 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1676 (match_operand:ANYF 2 "register_operand" "f"))
1677 (match_operand:ANYF 3 "register_operand" "f")))]
1678 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1679 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
1680 "nmadd.<fmt>\t%0,%3,%1,%2"
1681 [(set_attr "type" "fmadd")
1682 (set_attr "mode" "<UNITMODE>")])
1684 (define_insn "*nmsub<mode>"
1685 [(set (match_operand:ANYF 0 "register_operand" "=f")
1686 (neg:ANYF (minus:ANYF
1687 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1688 (match_operand:ANYF 3 "register_operand" "f"))
1689 (match_operand:ANYF 1 "register_operand" "f"))))]
1690 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1691 && HONOR_SIGNED_ZEROS (<MODE>mode)"
1692 "nmsub.<fmt>\t%0,%1,%2,%3"
1693 [(set_attr "type" "fmadd")
1694 (set_attr "mode" "<UNITMODE>")])
1696 (define_insn "*nmsub<mode>_fastmath"
1697 [(set (match_operand:ANYF 0 "register_operand" "=f")
1699 (match_operand:ANYF 1 "register_operand" "f")
1700 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1701 (match_operand:ANYF 3 "register_operand" "f"))))]
1702 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1703 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
1704 "nmsub.<fmt>\t%0,%1,%2,%3"
1705 [(set_attr "type" "fmadd")
1706 (set_attr "mode" "<UNITMODE>")])
1709 ;; ....................
1711 ;; DIVISION and REMAINDER
1713 ;; ....................
1716 (define_expand "div<mode>3"
1717 [(set (match_operand:ANYF 0 "register_operand")
1718 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1719 (match_operand:ANYF 2 "register_operand")))]
1720 "<divide_condition>"
1722 if (const_1_operand (operands[1], <MODE>mode))
1723 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1724 operands[1] = force_reg (<MODE>mode, operands[1]);
1727 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1729 ;; If an mfc1 or dmfc1 happens to access the floating point register
1730 ;; file at the same time a long latency operation (div, sqrt, recip,
1731 ;; sqrt) iterates an intermediate result back through the floating
1732 ;; point register file bypass, then instead returning the correct
1733 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1734 ;; result of the long latency operation.
1736 ;; The workaround is to insert an unconditional 'mov' from/to the
1737 ;; long latency op destination register.
1739 (define_insn "*div<mode>3"
1740 [(set (match_operand:ANYF 0 "register_operand" "=f")
1741 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1742 (match_operand:ANYF 2 "register_operand" "f")))]
1743 "<divide_condition>"
1746 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1748 return "div.<fmt>\t%0,%1,%2";
1750 [(set_attr "type" "fdiv")
1751 (set_attr "mode" "<UNITMODE>")
1752 (set (attr "length")
1753 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1757 (define_insn "*recip<mode>3"
1758 [(set (match_operand:ANYF 0 "register_operand" "=f")
1759 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1760 (match_operand:ANYF 2 "register_operand" "f")))]
1761 "<recip_condition> && flag_unsafe_math_optimizations"
1764 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1766 return "recip.<fmt>\t%0,%2";
1768 [(set_attr "type" "frdiv")
1769 (set_attr "mode" "<UNITMODE>")
1770 (set (attr "length")
1771 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1775 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1776 ;; with negative operands. We use special libgcc functions instead.
1777 (define_insn "divmod<mode>4"
1778 [(set (match_operand:GPR 0 "register_operand" "=l")
1779 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1780 (match_operand:GPR 2 "register_operand" "d")))
1781 (set (match_operand:GPR 3 "register_operand" "=h")
1782 (mod:GPR (match_dup 1)
1784 "!TARGET_FIX_VR4120"
1785 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1786 [(set_attr "type" "idiv")
1787 (set_attr "mode" "<MODE>")])
1789 (define_insn "udivmod<mode>4"
1790 [(set (match_operand:GPR 0 "register_operand" "=l")
1791 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1792 (match_operand:GPR 2 "register_operand" "d")))
1793 (set (match_operand:GPR 3 "register_operand" "=h")
1794 (umod:GPR (match_dup 1)
1797 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1798 [(set_attr "type" "idiv")
1799 (set_attr "mode" "<MODE>")])
1802 ;; ....................
1806 ;; ....................
1808 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1809 ;; "*div[sd]f3" comment for details).
1811 (define_insn "sqrt<mode>2"
1812 [(set (match_operand:ANYF 0 "register_operand" "=f")
1813 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1817 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1819 return "sqrt.<fmt>\t%0,%1";
1821 [(set_attr "type" "fsqrt")
1822 (set_attr "mode" "<UNITMODE>")
1823 (set (attr "length")
1824 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1828 (define_insn "*rsqrt<mode>a"
1829 [(set (match_operand:ANYF 0 "register_operand" "=f")
1830 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1831 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
1832 "<recip_condition> && flag_unsafe_math_optimizations"
1835 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1837 return "rsqrt.<fmt>\t%0,%2";
1839 [(set_attr "type" "frsqrt")
1840 (set_attr "mode" "<UNITMODE>")
1841 (set (attr "length")
1842 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1846 (define_insn "*rsqrt<mode>b"
1847 [(set (match_operand:ANYF 0 "register_operand" "=f")
1848 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1849 (match_operand:ANYF 2 "register_operand" "f"))))]
1850 "<recip_condition> && flag_unsafe_math_optimizations"
1853 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1855 return "rsqrt.<fmt>\t%0,%2";
1857 [(set_attr "type" "frsqrt")
1858 (set_attr "mode" "<UNITMODE>")
1859 (set (attr "length")
1860 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1865 ;; ....................
1869 ;; ....................
1871 ;; Do not use the integer abs macro instruction, since that signals an
1872 ;; exception on -2147483648 (sigh).
1874 (define_insn "abs<mode>2"
1875 [(set (match_operand:GPR 0 "register_operand" "=d")
1876 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))]
1879 if (REGNO (operands[0]) == REGNO (operands[1]) && GENERATE_BRANCHLIKELY)
1880 return "%(bltzl\t%1,1f\;<d>subu\t%0,%.,%0\n%~1:%)";
1882 return "%(bgez\t%1,1f\;move\t%0,%1\;<d>subu\t%0,%.,%0\n%~1:%)";
1884 [(set_attr "type" "multi")
1885 (set_attr "mode" "<MODE>")
1886 (set_attr "length" "12")])
1888 (define_insn "abs<mode>2"
1889 [(set (match_operand:ANYF 0 "register_operand" "=f")
1890 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1893 [(set_attr "type" "fabs")
1894 (set_attr "mode" "<UNITMODE>")])
1897 ;; ....................
1899 ;; FIND FIRST BIT INSTRUCTION
1901 ;; ....................
1904 (define_insn "ffs<mode>2"
1905 [(set (match_operand:GPR 0 "register_operand" "=&d")
1906 (ffs:GPR (match_operand:GPR 1 "register_operand" "d")))
1907 (clobber (match_scratch:GPR 2 "=&d"))
1908 (clobber (match_scratch:GPR 3 "=&d"))]
1911 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
1915 %~1:\tand\t%2,%1,0x0001\;\
1925 %~1:\tand\t%2,%3,0x0001\;\
1931 [(set_attr "type" "multi")
1932 (set_attr "mode" "<MODE>")
1933 (set_attr "length" "28")])
1936 ;; ...................
1938 ;; Count leading zeroes.
1940 ;; ...................
1943 (define_insn "clz<mode>2"
1944 [(set (match_operand:GPR 0 "register_operand" "=d")
1945 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
1948 [(set_attr "type" "clz")
1949 (set_attr "mode" "<MODE>")])
1952 ;; ....................
1954 ;; NEGATION and ONE'S COMPLEMENT
1956 ;; ....................
1958 (define_insn "negsi2"
1959 [(set (match_operand:SI 0 "register_operand" "=d")
1960 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1964 return "neg\t%0,%1";
1966 return "subu\t%0,%.,%1";
1968 [(set_attr "type" "arith")
1969 (set_attr "mode" "SI")])
1971 (define_insn "negdi2"
1972 [(set (match_operand:DI 0 "register_operand" "=d")
1973 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
1974 "TARGET_64BIT && !TARGET_MIPS16"
1976 [(set_attr "type" "arith")
1977 (set_attr "mode" "DI")])
1979 (define_insn "neg<mode>2"
1980 [(set (match_operand:ANYF 0 "register_operand" "=f")
1981 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1984 [(set_attr "type" "fneg")
1985 (set_attr "mode" "<UNITMODE>")])
1987 (define_insn "one_cmpl<mode>2"
1988 [(set (match_operand:GPR 0 "register_operand" "=d")
1989 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
1993 return "not\t%0,%1";
1995 return "nor\t%0,%.,%1";
1997 [(set_attr "type" "arith")
1998 (set_attr "mode" "<MODE>")])
2001 ;; ....................
2005 ;; ....................
2008 ;; Many of these instructions use trivial define_expands, because we
2009 ;; want to use a different set of constraints when TARGET_MIPS16.
2011 (define_expand "and<mode>3"
2012 [(set (match_operand:GPR 0 "register_operand")
2013 (and:GPR (match_operand:GPR 1 "register_operand")
2014 (match_operand:GPR 2 "uns_arith_operand")))]
2018 operands[2] = force_reg (<MODE>mode, operands[2]);
2021 (define_insn "*and<mode>3"
2022 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2023 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2024 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2029 [(set_attr "type" "arith")
2030 (set_attr "mode" "<MODE>")])
2032 (define_insn "*and<mode>3_mips16"
2033 [(set (match_operand:GPR 0 "register_operand" "=d")
2034 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2035 (match_operand:GPR 2 "register_operand" "d")))]
2038 [(set_attr "type" "arith")
2039 (set_attr "mode" "<MODE>")])
2041 (define_expand "ior<mode>3"
2042 [(set (match_operand:GPR 0 "register_operand")
2043 (ior:GPR (match_operand:GPR 1 "register_operand")
2044 (match_operand:GPR 2 "uns_arith_operand")))]
2048 operands[2] = force_reg (<MODE>mode, operands[2]);
2051 (define_insn "*ior<mode>3"
2052 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2053 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2054 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2059 [(set_attr "type" "arith")
2060 (set_attr "mode" "<MODE>")])
2062 (define_insn "*ior<mode>3_mips16"
2063 [(set (match_operand:GPR 0 "register_operand" "=d")
2064 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2065 (match_operand:GPR 2 "register_operand" "d")))]
2068 [(set_attr "type" "arith")
2069 (set_attr "mode" "<MODE>")])
2071 (define_expand "xor<mode>3"
2072 [(set (match_operand:GPR 0 "register_operand")
2073 (xor:GPR (match_operand:GPR 1 "register_operand")
2074 (match_operand:GPR 2 "uns_arith_operand")))]
2079 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2080 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2081 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2086 [(set_attr "type" "arith")
2087 (set_attr "mode" "<MODE>")])
2090 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2091 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2092 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2098 [(set_attr "type" "arith")
2099 (set_attr "mode" "<MODE>")
2100 (set_attr_alternative "length"
2102 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2107 (define_insn "*nor<mode>3"
2108 [(set (match_operand:GPR 0 "register_operand" "=d")
2109 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2110 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2113 [(set_attr "type" "arith")
2114 (set_attr "mode" "<MODE>")])
2117 ;; ....................
2121 ;; ....................
2125 (define_insn "truncdfsf2"
2126 [(set (match_operand:SF 0 "register_operand" "=f")
2127 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2128 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2130 [(set_attr "type" "fcvt")
2131 (set_attr "mode" "SF")])
2133 ;; Integer truncation patterns. Truncating SImode values to smaller
2134 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2135 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2136 ;; need to make sure that the lower 32 bits are properly sign-extended
2137 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2138 ;; smaller than SImode is equivalent to two separate truncations:
2141 ;; DI ---> HI == DI ---> SI ---> HI
2142 ;; DI ---> QI == DI ---> SI ---> QI
2144 ;; Step A needs a real instruction but step B does not.
2146 (define_insn "truncdisi2"
2147 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2148 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2153 [(set_attr "type" "shift,store")
2154 (set_attr "mode" "SI")
2155 (set_attr "extended_mips16" "yes,*")])
2157 (define_insn "truncdihi2"
2158 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2159 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2164 [(set_attr "type" "shift,store")
2165 (set_attr "mode" "SI")
2166 (set_attr "extended_mips16" "yes,*")])
2168 (define_insn "truncdiqi2"
2169 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2170 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2175 [(set_attr "type" "shift,store")
2176 (set_attr "mode" "SI")
2177 (set_attr "extended_mips16" "yes,*")])
2179 ;; Combiner patterns to optimize shift/truncate combinations.
2182 [(set (match_operand:SI 0 "register_operand" "=d")
2184 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2185 (match_operand:DI 2 "const_arith_operand" ""))))]
2186 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2188 [(set_attr "type" "shift")
2189 (set_attr "mode" "SI")])
2192 [(set (match_operand:SI 0 "register_operand" "=d")
2193 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2195 "TARGET_64BIT && !TARGET_MIPS16"
2197 [(set_attr "type" "shift")
2198 (set_attr "mode" "SI")])
2201 ;; Combiner patterns for truncate/sign_extend combinations. They use
2202 ;; the shift/truncate patterns above.
2204 (define_insn_and_split ""
2205 [(set (match_operand:SI 0 "register_operand" "=d")
2207 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2208 "TARGET_64BIT && !TARGET_MIPS16"
2210 "&& reload_completed"
2212 (ashift:DI (match_dup 1)
2215 (truncate:SI (ashiftrt:DI (match_dup 2)
2217 { operands[2] = gen_lowpart (DImode, operands[0]); })
2219 (define_insn_and_split ""
2220 [(set (match_operand:SI 0 "register_operand" "=d")
2222 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2223 "TARGET_64BIT && !TARGET_MIPS16"
2225 "&& reload_completed"
2227 (ashift:DI (match_dup 1)
2230 (truncate:SI (ashiftrt:DI (match_dup 2)
2232 { operands[2] = gen_lowpart (DImode, operands[0]); })
2235 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2238 [(set (match_operand:SI 0 "register_operand" "=d")
2239 (zero_extend:SI (truncate:HI
2240 (match_operand:DI 1 "register_operand" "d"))))]
2241 "TARGET_64BIT && !TARGET_MIPS16"
2242 "andi\t%0,%1,0xffff"
2243 [(set_attr "type" "arith")
2244 (set_attr "mode" "SI")])
2247 [(set (match_operand:SI 0 "register_operand" "=d")
2248 (zero_extend:SI (truncate:QI
2249 (match_operand:DI 1 "register_operand" "d"))))]
2250 "TARGET_64BIT && !TARGET_MIPS16"
2252 [(set_attr "type" "arith")
2253 (set_attr "mode" "SI")])
2256 [(set (match_operand:HI 0 "register_operand" "=d")
2257 (zero_extend:HI (truncate:QI
2258 (match_operand:DI 1 "register_operand" "d"))))]
2259 "TARGET_64BIT && !TARGET_MIPS16"
2261 [(set_attr "type" "arith")
2262 (set_attr "mode" "HI")])
2265 ;; ....................
2269 ;; ....................
2273 (define_insn_and_split "zero_extendsidi2"
2274 [(set (match_operand:DI 0 "register_operand" "=d,d")
2275 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2280 "&& reload_completed && REG_P (operands[1])"
2282 (ashift:DI (match_dup 1) (const_int 32)))
2284 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2285 { operands[1] = gen_lowpart (DImode, operands[1]); }
2286 [(set_attr "type" "multi,load")
2287 (set_attr "mode" "DI")
2288 (set_attr "length" "8,*")])
2290 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2291 [(set (match_operand:GPR 0 "register_operand")
2292 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2295 if (TARGET_MIPS16 && !memory_operand (operands[1], <SHORT:MODE>mode))
2297 emit_insn (gen_and<GPR:mode>3 (operands[0],
2298 gen_lowpart (<GPR:MODE>mode, operands[1]),
2299 force_reg (<GPR:MODE>mode,
2300 GEN_INT (<SHORT:mask>))));
2305 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2306 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2308 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2311 andi\t%0,%1,<SHORT:mask>
2312 l<SHORT:size>u\t%0,%1"
2313 [(set_attr "type" "arith,load")
2314 (set_attr "mode" "<GPR:MODE>")])
2316 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2317 [(set (match_operand:GPR 0 "register_operand" "=d")
2318 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2320 "l<SHORT:size>u\t%0,%1"
2321 [(set_attr "type" "load")
2322 (set_attr "mode" "<GPR:MODE>")])
2324 (define_expand "zero_extendqihi2"
2325 [(set (match_operand:HI 0 "register_operand")
2326 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2329 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2331 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2337 (define_insn "*zero_extendqihi2"
2338 [(set (match_operand:HI 0 "register_operand" "=d,d")
2339 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2344 [(set_attr "type" "arith,load")
2345 (set_attr "mode" "HI")])
2347 (define_insn "*zero_extendqihi2_mips16"
2348 [(set (match_operand:HI 0 "register_operand" "=d")
2349 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2352 [(set_attr "type" "load")
2353 (set_attr "mode" "HI")])
2356 ;; ....................
2360 ;; ....................
2363 ;; Those for integer source operand are ordered widest source type first.
2365 ;; When TARGET_64BIT, all SImode integer registers should already be in
2366 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2367 ;; therefore get rid of register->register instructions if we constrain
2368 ;; the source to be in the same register as the destination.
2370 ;; The register alternative has type "arith" so that the pre-reload
2371 ;; scheduler will treat it as a move. This reflects what happens if
2372 ;; the register alternative needs a reload.
2373 (define_insn_and_split "extendsidi2"
2374 [(set (match_operand:DI 0 "register_operand" "=d,d")
2375 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2380 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2383 emit_note (NOTE_INSN_DELETED);
2386 [(set_attr "type" "arith,load")
2387 (set_attr "mode" "DI")])
2389 (define_expand "extend<SHORT:mode><GPR:mode>2"
2390 [(set (match_operand:GPR 0 "register_operand")
2391 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2394 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2395 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2397 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2401 l<SHORT:size>\t%0,%1"
2402 "&& reload_completed && REG_P (operands[1])"
2403 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2404 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2406 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2407 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2408 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2410 [(set_attr "type" "arith,load")
2411 (set_attr "mode" "<GPR:MODE>")
2412 (set_attr "length" "8,*")])
2414 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2415 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2417 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2420 se<SHORT:size>\t%0,%1
2421 l<SHORT:size>\t%0,%1"
2422 [(set_attr "type" "arith,load")
2423 (set_attr "mode" "<GPR:MODE>")])
2425 ;; This pattern generates the same code as extendqisi2; split it into
2426 ;; that form after reload.
2427 (define_insn_and_split "extendqihi2"
2428 [(set (match_operand:HI 0 "register_operand" "=d,d")
2429 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2433 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
2434 { operands[0] = gen_lowpart (SImode, operands[0]); }
2435 [(set_attr "type" "arith,load")
2436 (set_attr "mode" "SI")
2437 (set_attr "length" "8,*")])
2439 (define_insn "extendsfdf2"
2440 [(set (match_operand:DF 0 "register_operand" "=f")
2441 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2442 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2444 [(set_attr "type" "fcvt")
2445 (set_attr "mode" "DF")])
2448 ;; ....................
2452 ;; ....................
2454 (define_expand "fix_truncdfsi2"
2455 [(set (match_operand:SI 0 "register_operand")
2456 (fix:SI (match_operand:DF 1 "register_operand")))]
2457 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2459 if (!ISA_HAS_TRUNC_W)
2461 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2466 (define_insn "fix_truncdfsi2_insn"
2467 [(set (match_operand:SI 0 "register_operand" "=f")
2468 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2469 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2471 [(set_attr "type" "fcvt")
2472 (set_attr "mode" "DF")
2473 (set_attr "length" "4")])
2475 (define_insn "fix_truncdfsi2_macro"
2476 [(set (match_operand:SI 0 "register_operand" "=f")
2477 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2478 (clobber (match_scratch:DF 2 "=d"))]
2479 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2482 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2484 return "trunc.w.d %0,%1,%2";
2486 [(set_attr "type" "fcvt")
2487 (set_attr "mode" "DF")
2488 (set_attr "length" "36")])
2490 (define_expand "fix_truncsfsi2"
2491 [(set (match_operand:SI 0 "register_operand")
2492 (fix:SI (match_operand:SF 1 "register_operand")))]
2495 if (!ISA_HAS_TRUNC_W)
2497 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2502 (define_insn "fix_truncsfsi2_insn"
2503 [(set (match_operand:SI 0 "register_operand" "=f")
2504 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2505 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2507 [(set_attr "type" "fcvt")
2508 (set_attr "mode" "DF")
2509 (set_attr "length" "4")])
2511 (define_insn "fix_truncsfsi2_macro"
2512 [(set (match_operand:SI 0 "register_operand" "=f")
2513 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2514 (clobber (match_scratch:SF 2 "=d"))]
2515 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2518 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2520 return "trunc.w.s %0,%1,%2";
2522 [(set_attr "type" "fcvt")
2523 (set_attr "mode" "DF")
2524 (set_attr "length" "36")])
2527 (define_insn "fix_truncdfdi2"
2528 [(set (match_operand:DI 0 "register_operand" "=f")
2529 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2530 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2532 [(set_attr "type" "fcvt")
2533 (set_attr "mode" "DF")
2534 (set_attr "length" "4")])
2537 (define_insn "fix_truncsfdi2"
2538 [(set (match_operand:DI 0 "register_operand" "=f")
2539 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2540 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2542 [(set_attr "type" "fcvt")
2543 (set_attr "mode" "SF")
2544 (set_attr "length" "4")])
2547 (define_insn "floatsidf2"
2548 [(set (match_operand:DF 0 "register_operand" "=f")
2549 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2550 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2552 [(set_attr "type" "fcvt")
2553 (set_attr "mode" "DF")
2554 (set_attr "length" "4")])
2557 (define_insn "floatdidf2"
2558 [(set (match_operand:DF 0 "register_operand" "=f")
2559 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2560 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2562 [(set_attr "type" "fcvt")
2563 (set_attr "mode" "DF")
2564 (set_attr "length" "4")])
2567 (define_insn "floatsisf2"
2568 [(set (match_operand:SF 0 "register_operand" "=f")
2569 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2572 [(set_attr "type" "fcvt")
2573 (set_attr "mode" "SF")
2574 (set_attr "length" "4")])
2577 (define_insn "floatdisf2"
2578 [(set (match_operand:SF 0 "register_operand" "=f")
2579 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2580 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2582 [(set_attr "type" "fcvt")
2583 (set_attr "mode" "SF")
2584 (set_attr "length" "4")])
2587 (define_expand "fixuns_truncdfsi2"
2588 [(set (match_operand:SI 0 "register_operand")
2589 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2590 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2592 rtx reg1 = gen_reg_rtx (DFmode);
2593 rtx reg2 = gen_reg_rtx (DFmode);
2594 rtx reg3 = gen_reg_rtx (SImode);
2595 rtx label1 = gen_label_rtx ();
2596 rtx label2 = gen_label_rtx ();
2597 REAL_VALUE_TYPE offset;
2599 real_2expN (&offset, 31);
2601 if (reg1) /* Turn off complaints about unreached code. */
2603 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2604 do_pending_stack_adjust ();
2606 emit_insn (gen_cmpdf (operands[1], reg1));
2607 emit_jump_insn (gen_bge (label1));
2609 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2610 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2611 gen_rtx_LABEL_REF (VOIDmode, label2)));
2614 emit_label (label1);
2615 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2616 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2617 (BITMASK_HIGH, SImode)));
2619 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2620 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2622 emit_label (label2);
2624 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2625 fields, and can't be used for REG_NOTES anyway). */
2626 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2632 (define_expand "fixuns_truncdfdi2"
2633 [(set (match_operand:DI 0 "register_operand")
2634 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2635 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2637 rtx reg1 = gen_reg_rtx (DFmode);
2638 rtx reg2 = gen_reg_rtx (DFmode);
2639 rtx reg3 = gen_reg_rtx (DImode);
2640 rtx label1 = gen_label_rtx ();
2641 rtx label2 = gen_label_rtx ();
2642 REAL_VALUE_TYPE offset;
2644 real_2expN (&offset, 63);
2646 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2647 do_pending_stack_adjust ();
2649 emit_insn (gen_cmpdf (operands[1], reg1));
2650 emit_jump_insn (gen_bge (label1));
2652 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2653 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2654 gen_rtx_LABEL_REF (VOIDmode, label2)));
2657 emit_label (label1);
2658 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2659 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2660 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2662 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2663 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2665 emit_label (label2);
2667 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2668 fields, and can't be used for REG_NOTES anyway). */
2669 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2674 (define_expand "fixuns_truncsfsi2"
2675 [(set (match_operand:SI 0 "register_operand")
2676 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2679 rtx reg1 = gen_reg_rtx (SFmode);
2680 rtx reg2 = gen_reg_rtx (SFmode);
2681 rtx reg3 = gen_reg_rtx (SImode);
2682 rtx label1 = gen_label_rtx ();
2683 rtx label2 = gen_label_rtx ();
2684 REAL_VALUE_TYPE offset;
2686 real_2expN (&offset, 31);
2688 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2689 do_pending_stack_adjust ();
2691 emit_insn (gen_cmpsf (operands[1], reg1));
2692 emit_jump_insn (gen_bge (label1));
2694 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2695 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2696 gen_rtx_LABEL_REF (VOIDmode, label2)));
2699 emit_label (label1);
2700 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2701 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2702 (BITMASK_HIGH, SImode)));
2704 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2705 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2707 emit_label (label2);
2709 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2710 fields, and can't be used for REG_NOTES anyway). */
2711 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2716 (define_expand "fixuns_truncsfdi2"
2717 [(set (match_operand:DI 0 "register_operand")
2718 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2719 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2721 rtx reg1 = gen_reg_rtx (SFmode);
2722 rtx reg2 = gen_reg_rtx (SFmode);
2723 rtx reg3 = gen_reg_rtx (DImode);
2724 rtx label1 = gen_label_rtx ();
2725 rtx label2 = gen_label_rtx ();
2726 REAL_VALUE_TYPE offset;
2728 real_2expN (&offset, 63);
2730 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2731 do_pending_stack_adjust ();
2733 emit_insn (gen_cmpsf (operands[1], reg1));
2734 emit_jump_insn (gen_bge (label1));
2736 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2737 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2738 gen_rtx_LABEL_REF (VOIDmode, label2)));
2741 emit_label (label1);
2742 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2743 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2744 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2746 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2747 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2749 emit_label (label2);
2751 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2752 fields, and can't be used for REG_NOTES anyway). */
2753 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2758 ;; ....................
2762 ;; ....................
2764 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2766 (define_expand "extv"
2767 [(set (match_operand 0 "register_operand")
2768 (sign_extract (match_operand:QI 1 "memory_operand")
2769 (match_operand 2 "immediate_operand")
2770 (match_operand 3 "immediate_operand")))]
2773 if (mips_expand_unaligned_load (operands[0], operands[1],
2774 INTVAL (operands[2]),
2775 INTVAL (operands[3])))
2781 (define_expand "extzv"
2782 [(set (match_operand 0 "register_operand")
2783 (zero_extract (match_operand:QI 1 "memory_operand")
2784 (match_operand 2 "immediate_operand")
2785 (match_operand 3 "immediate_operand")))]
2788 if (mips_expand_unaligned_load (operands[0], operands[1],
2789 INTVAL (operands[2]),
2790 INTVAL (operands[3])))
2796 (define_expand "insv"
2797 [(set (zero_extract (match_operand:QI 0 "memory_operand")
2798 (match_operand 1 "immediate_operand")
2799 (match_operand 2 "immediate_operand"))
2800 (match_operand 3 "reg_or_0_operand"))]
2803 if (mips_expand_unaligned_store (operands[0], operands[3],
2804 INTVAL (operands[1]),
2805 INTVAL (operands[2])))
2811 ;; Unaligned word moves generated by the bit field patterns.
2813 ;; As far as the rtl is concerned, both the left-part and right-part
2814 ;; instructions can access the whole field. However, the real operand
2815 ;; refers to just the first or the last byte (depending on endianness).
2816 ;; We therefore use two memory operands to each instruction, one to
2817 ;; describe the rtl effect and one to use in the assembly output.
2819 ;; Operands 0 and 1 are the rtl-level target and source respectively.
2820 ;; This allows us to use the standard length calculations for the "load"
2821 ;; and "store" type attributes.
2823 (define_insn "mov_<load>l"
2824 [(set (match_operand:GPR 0 "register_operand" "=d")
2825 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
2826 (match_operand:QI 2 "memory_operand" "m")]
2830 [(set_attr "type" "load")
2831 (set_attr "mode" "<MODE>")])
2833 (define_insn "mov_<load>r"
2834 [(set (match_operand:GPR 0 "register_operand" "=d")
2835 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
2836 (match_operand:QI 2 "memory_operand" "m")
2837 (match_operand:GPR 3 "register_operand" "0")]
2838 UNSPEC_LOAD_RIGHT))]
2841 [(set_attr "type" "load")
2842 (set_attr "mode" "<MODE>")])
2844 (define_insn "mov_<store>l"
2845 [(set (match_operand:BLK 0 "memory_operand" "=m")
2846 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
2847 (match_operand:QI 2 "memory_operand" "m")]
2848 UNSPEC_STORE_LEFT))]
2851 [(set_attr "type" "store")
2852 (set_attr "mode" "<MODE>")])
2854 (define_insn "mov_<store>r"
2855 [(set (match_operand:BLK 0 "memory_operand" "+m")
2856 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
2857 (match_operand:QI 2 "memory_operand" "m")
2859 UNSPEC_STORE_RIGHT))]
2862 [(set_attr "type" "store")
2863 (set_attr "mode" "<MODE>")])
2865 ;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL.
2866 ;; The required value is:
2868 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
2870 ;; which translates to:
2872 ;; lui op0,%highest(op1)
2873 ;; daddiu op0,op0,%higher(op1)
2875 ;; daddiu op0,op0,%hi(op1)
2878 ;; The split is deferred until after flow2 to allow the peephole2 below
2880 (define_insn_and_split "*lea_high64"
2881 [(set (match_operand:DI 0 "register_operand" "=d")
2882 (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
2883 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
2885 "&& flow2_completed"
2886 [(set (match_dup 0) (high:DI (match_dup 2)))
2887 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
2888 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
2889 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
2890 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
2892 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
2893 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
2895 [(set_attr "length" "20")])
2897 ;; Use a scratch register to reduce the latency of the above pattern
2898 ;; on superscalar machines. The optimized sequence is:
2900 ;; lui op1,%highest(op2)
2902 ;; daddiu op1,op1,%higher(op2)
2904 ;; daddu op1,op1,op0
2906 [(match_scratch:DI 0 "d")
2907 (set (match_operand:DI 1 "register_operand")
2908 (high:DI (match_operand:DI 2 "general_symbolic_operand")))]
2909 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
2910 [(set (match_dup 1) (high:DI (match_dup 3)))
2911 (set (match_dup 0) (high:DI (match_dup 4)))
2912 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
2913 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
2914 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
2916 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
2917 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
2920 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
2921 ;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
2922 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
2923 ;; used once. We can then use the sequence:
2925 ;; lui op0,%highest(op1)
2927 ;; daddiu op0,op0,%higher(op1)
2928 ;; daddiu op2,op2,%lo(op1)
2930 ;; daddu op0,op0,op2
2932 ;; which takes 4 cycles on most superscalar targets.
2933 (define_insn_and_split "*lea64"
2934 [(set (match_operand:DI 0 "register_operand" "=d")
2935 (match_operand:DI 1 "general_symbolic_operand" ""))
2936 (clobber (match_scratch:DI 2 "=&d"))]
2937 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
2939 "&& reload_completed"
2940 [(set (match_dup 0) (high:DI (match_dup 3)))
2941 (set (match_dup 2) (high:DI (match_dup 4)))
2942 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
2943 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
2944 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
2945 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
2947 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
2948 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
2950 [(set_attr "length" "24")])
2952 ;; Insns to fetch a global symbol from a big GOT.
2954 (define_insn_and_split "*xgot_hi<mode>"
2955 [(set (match_operand:P 0 "register_operand" "=d")
2956 (high:P (match_operand:P 1 "global_got_operand" "")))]
2957 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
2959 "&& reload_completed"
2960 [(set (match_dup 0) (high:P (match_dup 2)))
2961 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
2963 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
2964 operands[3] = pic_offset_table_rtx;
2966 [(set_attr "got" "xgot_high")
2967 (set_attr "mode" "<MODE>")])
2969 (define_insn_and_split "*xgot_lo<mode>"
2970 [(set (match_operand:P 0 "register_operand" "=d")
2971 (lo_sum:P (match_operand:P 1 "register_operand" "d")
2972 (match_operand:P 2 "global_got_operand" "")))]
2973 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
2975 "&& reload_completed"
2977 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
2978 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_GLOBAL); }
2979 [(set_attr "got" "load")
2980 (set_attr "mode" "<MODE>")])
2982 ;; Insns to fetch a global symbol from a normal GOT.
2984 (define_insn_and_split "*got_disp<mode>"
2985 [(set (match_operand:P 0 "register_operand" "=d")
2986 (match_operand:P 1 "global_got_operand" ""))]
2987 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
2989 "&& reload_completed"
2991 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
2993 operands[2] = pic_offset_table_rtx;
2994 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
2996 [(set_attr "got" "load")
2997 (set_attr "mode" "<MODE>")])
2999 ;; Insns for loading the high part of a local symbol.
3001 (define_insn_and_split "*got_page<mode>"
3002 [(set (match_operand:P 0 "register_operand" "=d")
3003 (high:P (match_operand:P 1 "local_got_operand" "")))]
3004 "TARGET_EXPLICIT_RELOCS"
3006 "&& reload_completed"
3008 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3010 operands[2] = pic_offset_table_rtx;
3011 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3013 [(set_attr "got" "load")
3014 (set_attr "mode" "<MODE>")])
3016 ;; Lower-level instructions for loading an address from the GOT.
3017 ;; We could use MEMs, but an unspec gives more optimization
3020 (define_insn "*load_got<mode>"
3021 [(set (match_operand:P 0 "register_operand" "=d")
3022 (unspec:P [(match_operand:P 1 "register_operand" "d")
3023 (match_operand:P 2 "immediate_operand" "")]
3026 "<load>\t%0,%R2(%1)"
3027 [(set_attr "type" "load")
3028 (set_attr "mode" "<MODE>")
3029 (set_attr "length" "4")])
3031 ;; Instructions for adding the low 16 bits of an address to a register.
3032 ;; Operand 2 is the address: print_operand works out which relocation
3033 ;; should be applied.
3035 (define_insn "*low<mode>"
3036 [(set (match_operand:P 0 "register_operand" "=d")
3037 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3038 (match_operand:P 2 "immediate_operand" "")))]
3040 "<d>addiu\t%0,%1,%R2"
3041 [(set_attr "type" "arith")
3042 (set_attr "mode" "<MODE>")])
3044 (define_insn "*low<mode>_mips16"
3045 [(set (match_operand:P 0 "register_operand" "=d")
3046 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3047 (match_operand:P 2 "immediate_operand" "")))]
3050 [(set_attr "type" "arith")
3051 (set_attr "mode" "<MODE>")
3052 (set_attr "length" "8")])
3054 ;; 64-bit integer moves
3056 ;; Unlike most other insns, the move insns can't be split with
3057 ;; different predicates, because register spilling and other parts of
3058 ;; the compiler, have memoized the insn number already.
3060 (define_expand "movdi"
3061 [(set (match_operand:DI 0 "")
3062 (match_operand:DI 1 ""))]
3065 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3069 ;; For mips16, we need a special case to handle storing $31 into
3070 ;; memory, since we don't have a constraint to match $31. This
3071 ;; instruction can be generated by save_restore_insns.
3073 (define_insn "*mov<mode>_ra"
3074 [(set (match_operand:GPR 0 "stack_operand" "=m")
3078 [(set_attr "type" "store")
3079 (set_attr "mode" "<MODE>")])
3081 (define_insn "*movdi_32bit"
3082 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*x,*d,*B*C*D,*B*C*D,*d,*m")
3083 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*x,*d,*m,*B*C*D,*B*C*D"))]
3084 "!TARGET_64BIT && !TARGET_MIPS16
3085 && (register_operand (operands[0], DImode)
3086 || reg_or_0_operand (operands[1], DImode))"
3087 { return mips_output_move (operands[0], operands[1]); }
3088 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,xfer,load,xfer,store")
3089 (set_attr "mode" "DI")
3090 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3092 (define_insn "*movdi_32bit_mips16"
3093 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3094 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3095 "!TARGET_64BIT && TARGET_MIPS16
3096 && (register_operand (operands[0], DImode)
3097 || register_operand (operands[1], DImode))"
3098 { return mips_output_move (operands[0], operands[1]); }
3099 [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo")
3100 (set_attr "mode" "DI")
3101 (set_attr "length" "8,8,8,8,12,*,*,8")])
3103 (define_insn "*movdi_64bit"
3104 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3105 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3106 "TARGET_64BIT && !TARGET_MIPS16
3107 && (register_operand (operands[0], DImode)
3108 || reg_or_0_operand (operands[1], DImode))"
3109 { return mips_output_move (operands[0], operands[1]); }
3110 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,xfer,load,xfer,store")
3111 (set_attr "mode" "DI")
3112 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3114 (define_insn "*movdi_64bit_mips16"
3115 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3116 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3117 "TARGET_64BIT && TARGET_MIPS16
3118 && (register_operand (operands[0], DImode)
3119 || register_operand (operands[1], DImode))"
3120 { return mips_output_move (operands[0], operands[1]); }
3121 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3122 (set_attr "mode" "DI")
3123 (set_attr_alternative "length"
3127 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3130 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3135 (const_string "*")])])
3138 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3139 ;; when the original load is a 4 byte instruction but the add and the
3140 ;; load are 2 2 byte instructions.
3143 [(set (match_operand:DI 0 "register_operand")
3144 (mem:DI (plus:DI (match_dup 0)
3145 (match_operand:DI 1 "const_int_operand"))))]
3146 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3147 && !TARGET_DEBUG_D_MODE
3148 && GET_CODE (operands[0]) == REG
3149 && M16_REG_P (REGNO (operands[0]))
3150 && GET_CODE (operands[1]) == CONST_INT
3151 && ((INTVAL (operands[1]) < 0
3152 && INTVAL (operands[1]) >= -0x10)
3153 || (INTVAL (operands[1]) >= 32 * 8
3154 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3155 || (INTVAL (operands[1]) >= 0
3156 && INTVAL (operands[1]) < 32 * 8
3157 && (INTVAL (operands[1]) & 7) != 0))"
3158 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3159 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3161 HOST_WIDE_INT val = INTVAL (operands[1]);
3164 operands[2] = const0_rtx;
3165 else if (val >= 32 * 8)
3169 operands[1] = GEN_INT (0x8 + off);
3170 operands[2] = GEN_INT (val - off - 0x8);
3176 operands[1] = GEN_INT (off);
3177 operands[2] = GEN_INT (val - off);
3181 ;; 32-bit Integer moves
3183 ;; Unlike most other insns, the move insns can't be split with
3184 ;; different predicates, because register spilling and other parts of
3185 ;; the compiler, have memoized the insn number already.
3187 (define_expand "movsi"
3188 [(set (match_operand:SI 0 "")
3189 (match_operand:SI 1 ""))]
3192 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3196 ;; The difference between these two is whether or not ints are allowed
3197 ;; in FP registers (off by default, use -mdebugh to enable).
3199 (define_insn "*movsi_internal"
3200 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*x,*B*C*D,*B*C*D,*d,*m")
3201 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3203 && (register_operand (operands[0], SImode)
3204 || reg_or_0_operand (operands[1], SImode))"
3205 { return mips_output_move (operands[0], operands[1]); }
3206 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,xfer,load,xfer,store")
3207 (set_attr "mode" "SI")
3208 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,*,4,*")])
3210 (define_insn "*movsi_mips16"
3211 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3212 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3214 && (register_operand (operands[0], SImode)
3215 || register_operand (operands[1], SImode))"
3216 { return mips_output_move (operands[0], operands[1]); }
3217 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3218 (set_attr "mode" "SI")
3219 (set_attr_alternative "length"
3223 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3226 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3231 (const_string "*")])])
3233 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3234 ;; when the original load is a 4 byte instruction but the add and the
3235 ;; load are 2 2 byte instructions.
3238 [(set (match_operand:SI 0 "register_operand")
3239 (mem:SI (plus:SI (match_dup 0)
3240 (match_operand:SI 1 "const_int_operand"))))]
3241 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3242 && GET_CODE (operands[0]) == REG
3243 && M16_REG_P (REGNO (operands[0]))
3244 && GET_CODE (operands[1]) == CONST_INT
3245 && ((INTVAL (operands[1]) < 0
3246 && INTVAL (operands[1]) >= -0x80)
3247 || (INTVAL (operands[1]) >= 32 * 4
3248 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3249 || (INTVAL (operands[1]) >= 0
3250 && INTVAL (operands[1]) < 32 * 4
3251 && (INTVAL (operands[1]) & 3) != 0))"
3252 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3253 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3255 HOST_WIDE_INT val = INTVAL (operands[1]);
3258 operands[2] = const0_rtx;
3259 else if (val >= 32 * 4)
3263 operands[1] = GEN_INT (0x7c + off);
3264 operands[2] = GEN_INT (val - off - 0x7c);
3270 operands[1] = GEN_INT (off);
3271 operands[2] = GEN_INT (val - off);
3275 ;; On the mips16, we can split a load of certain constants into a load
3276 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3280 [(set (match_operand:SI 0 "register_operand")
3281 (match_operand:SI 1 "const_int_operand"))]
3282 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3283 && GET_CODE (operands[0]) == REG
3284 && M16_REG_P (REGNO (operands[0]))
3285 && GET_CODE (operands[1]) == CONST_INT
3286 && INTVAL (operands[1]) >= 0x100
3287 && INTVAL (operands[1]) <= 0xff + 0x7f"
3288 [(set (match_dup 0) (match_dup 1))
3289 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3291 int val = INTVAL (operands[1]);
3293 operands[1] = GEN_INT (0xff);
3294 operands[2] = GEN_INT (val - 0xff);
3297 ;; This insn handles moving CCmode values. It's really just a
3298 ;; slightly simplified copy of movsi_internal2, with additional cases
3299 ;; to move a condition register to a general register and to move
3300 ;; between the general registers and the floating point registers.
3302 (define_insn "movcc"
3303 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3304 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3305 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3306 { return mips_output_move (operands[0], operands[1]); }
3307 [(set_attr "type" "xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore")
3308 (set_attr "mode" "SI")
3309 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3311 ;; Reload condition code registers. reload_incc and reload_outcc
3312 ;; both handle moves from arbitrary operands into condition code
3313 ;; registers. reload_incc handles the more common case in which
3314 ;; a source operand is constrained to be in a condition-code
3315 ;; register, but has not been allocated to one.
3317 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3318 ;; constraints do not include 'z'. reload_outcc handles the case
3319 ;; when such an operand is allocated to a condition-code register.
3321 ;; Note that reloads from a condition code register to some
3322 ;; other location can be done using ordinary moves. Moving
3323 ;; into a GPR takes a single movcc, moving elsewhere takes
3324 ;; two. We can leave these cases to the generic reload code.
3325 (define_expand "reload_incc"
3326 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3327 (match_operand:CC 1 "general_operand" ""))
3328 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3329 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3331 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3335 (define_expand "reload_outcc"
3336 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3337 (match_operand:CC 1 "register_operand" ""))
3338 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3339 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3341 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3345 ;; MIPS4 supports loading and storing a floating point register from
3346 ;; the sum of two general registers. We use two versions for each of
3347 ;; these four instructions: one where the two general registers are
3348 ;; SImode, and one where they are DImode. This is because general
3349 ;; registers will be in SImode when they hold 32 bit values, but,
3350 ;; since the 32 bit values are always sign extended, the [ls][wd]xc1
3351 ;; instructions will still work correctly.
3353 ;; ??? Perhaps it would be better to support these instructions by
3354 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3355 ;; these instructions can only be used to load and store floating
3356 ;; point registers, that would probably cause trouble in reload.
3358 (define_insn "*<ANYF:loadx>_<P:mode>"
3359 [(set (match_operand:ANYF 0 "register_operand" "=f")
3360 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3361 (match_operand:P 2 "register_operand" "d"))))]
3363 "<ANYF:loadx>\t%0,%1(%2)"
3364 [(set_attr "type" "fpidxload")
3365 (set_attr "mode" "<ANYF:UNITMODE>")])
3367 (define_insn "*<ANYF:storex>_<P:mode>"
3368 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3369 (match_operand:P 2 "register_operand" "d")))
3370 (match_operand:ANYF 0 "register_operand" "f"))]
3372 "<ANYF:storex>\t%0,%1(%2)"
3373 [(set_attr "type" "fpidxstore")
3374 (set_attr "mode" "<ANYF:UNITMODE>")])
3376 ;; 16-bit Integer moves
3378 ;; Unlike most other insns, the move insns can't be split with
3379 ;; different predicates, because register spilling and other parts of
3380 ;; the compiler, have memoized the insn number already.
3381 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3383 (define_expand "movhi"
3384 [(set (match_operand:HI 0 "")
3385 (match_operand:HI 1 ""))]
3388 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3392 (define_insn "*movhi_internal"
3393 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3394 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3396 && (register_operand (operands[0], HImode)
3397 || reg_or_0_operand (operands[1], HImode))"
3407 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
3408 (set_attr "mode" "HI")
3409 (set_attr "length" "4,4,*,*,4,4,4,4")])
3411 (define_insn "*movhi_mips16"
3412 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3413 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3415 && (register_operand (operands[0], HImode)
3416 || register_operand (operands[1], HImode))"
3425 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3426 (set_attr "mode" "HI")
3427 (set_attr_alternative "length"
3431 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3434 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3438 (const_string "*")])])
3441 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3442 ;; when the original load is a 4 byte instruction but the add and the
3443 ;; load are 2 2 byte instructions.
3446 [(set (match_operand:HI 0 "register_operand")
3447 (mem:HI (plus:SI (match_dup 0)
3448 (match_operand:SI 1 "const_int_operand"))))]
3449 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3450 && GET_CODE (operands[0]) == REG
3451 && M16_REG_P (REGNO (operands[0]))
3452 && GET_CODE (operands[1]) == CONST_INT
3453 && ((INTVAL (operands[1]) < 0
3454 && INTVAL (operands[1]) >= -0x80)
3455 || (INTVAL (operands[1]) >= 32 * 2
3456 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3457 || (INTVAL (operands[1]) >= 0
3458 && INTVAL (operands[1]) < 32 * 2
3459 && (INTVAL (operands[1]) & 1) != 0))"
3460 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3461 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3463 HOST_WIDE_INT val = INTVAL (operands[1]);
3466 operands[2] = const0_rtx;
3467 else if (val >= 32 * 2)
3471 operands[1] = GEN_INT (0x7e + off);
3472 operands[2] = GEN_INT (val - off - 0x7e);
3478 operands[1] = GEN_INT (off);
3479 operands[2] = GEN_INT (val - off);
3483 ;; 8-bit Integer moves
3485 ;; Unlike most other insns, the move insns can't be split with
3486 ;; different predicates, because register spilling and other parts of
3487 ;; the compiler, have memoized the insn number already.
3488 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3490 (define_expand "movqi"
3491 [(set (match_operand:QI 0 "")
3492 (match_operand:QI 1 ""))]
3495 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3499 (define_insn "*movqi_internal"
3500 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3501 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3503 && (register_operand (operands[0], QImode)
3504 || reg_or_0_operand (operands[1], QImode))"
3514 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
3515 (set_attr "mode" "QI")
3516 (set_attr "length" "4,4,*,*,4,4,4,4")])
3518 (define_insn "*movqi_mips16"
3519 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3520 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3522 && (register_operand (operands[0], QImode)
3523 || register_operand (operands[1], QImode))"
3532 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3533 (set_attr "mode" "QI")
3534 (set_attr "length" "4,4,4,4,8,*,*")])
3536 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3537 ;; when the original load is a 4 byte instruction but the add and the
3538 ;; load are 2 2 byte instructions.
3541 [(set (match_operand:QI 0 "register_operand")
3542 (mem:QI (plus:SI (match_dup 0)
3543 (match_operand:SI 1 "const_int_operand"))))]
3544 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3545 && GET_CODE (operands[0]) == REG
3546 && M16_REG_P (REGNO (operands[0]))
3547 && GET_CODE (operands[1]) == CONST_INT
3548 && ((INTVAL (operands[1]) < 0
3549 && INTVAL (operands[1]) >= -0x80)
3550 || (INTVAL (operands[1]) >= 32
3551 && INTVAL (operands[1]) <= 31 + 0x7f))"
3552 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3553 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3555 HOST_WIDE_INT val = INTVAL (operands[1]);
3558 operands[2] = const0_rtx;
3561 operands[1] = GEN_INT (0x7f);
3562 operands[2] = GEN_INT (val - 0x7f);
3566 ;; 32-bit floating point moves
3568 (define_expand "movsf"
3569 [(set (match_operand:SF 0 "")
3570 (match_operand:SF 1 ""))]
3573 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3577 (define_insn "*movsf_hardfloat"
3578 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3579 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3581 && (register_operand (operands[0], SFmode)
3582 || reg_or_0_operand (operands[1], SFmode))"
3583 { return mips_output_move (operands[0], operands[1]); }
3584 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3585 (set_attr "mode" "SF")
3586 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3588 (define_insn "*movsf_softfloat"
3589 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3590 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3591 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3592 && (register_operand (operands[0], SFmode)
3593 || reg_or_0_operand (operands[1], SFmode))"
3594 { return mips_output_move (operands[0], operands[1]); }
3595 [(set_attr "type" "arith,load,store")
3596 (set_attr "mode" "SF")
3597 (set_attr "length" "4,*,*")])
3599 (define_insn "*movsf_mips16"
3600 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3601 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3603 && (register_operand (operands[0], SFmode)
3604 || register_operand (operands[1], SFmode))"
3605 { return mips_output_move (operands[0], operands[1]); }
3606 [(set_attr "type" "arith,arith,arith,load,store")
3607 (set_attr "mode" "SF")
3608 (set_attr "length" "4,4,4,*,*")])
3611 ;; 64-bit floating point moves
3613 (define_expand "movdf"
3614 [(set (match_operand:DF 0 "")
3615 (match_operand:DF 1 ""))]
3618 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3622 (define_insn "*movdf_hardfloat_64bit"
3623 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3624 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3625 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3626 && (register_operand (operands[0], DFmode)
3627 || reg_or_0_operand (operands[1], DFmode))"
3628 { return mips_output_move (operands[0], operands[1]); }
3629 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3630 (set_attr "mode" "DF")
3631 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3633 (define_insn "*movdf_hardfloat_32bit"
3634 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3635 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3636 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3637 && (register_operand (operands[0], DFmode)
3638 || reg_or_0_operand (operands[1], DFmode))"
3639 { return mips_output_move (operands[0], operands[1]); }
3640 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3641 (set_attr "mode" "DF")
3642 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3644 (define_insn "*movdf_softfloat"
3645 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3646 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3647 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3648 && (register_operand (operands[0], DFmode)
3649 || reg_or_0_operand (operands[1], DFmode))"
3650 { return mips_output_move (operands[0], operands[1]); }
3651 [(set_attr "type" "arith,load,store,xfer,xfer,fmove")
3652 (set_attr "mode" "DF")
3653 (set_attr "length" "8,*,*,4,4,4")])
3655 (define_insn "*movdf_mips16"
3656 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3657 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3659 && (register_operand (operands[0], DFmode)
3660 || register_operand (operands[1], DFmode))"
3661 { return mips_output_move (operands[0], operands[1]); }
3662 [(set_attr "type" "arith,arith,arith,load,store")
3663 (set_attr "mode" "DF")
3664 (set_attr "length" "8,8,8,*,*")])
3667 [(set (match_operand:DI 0 "nonimmediate_operand")
3668 (match_operand:DI 1 "move_operand"))]
3669 "reload_completed && !TARGET_64BIT
3670 && mips_split_64bit_move_p (operands[0], operands[1])"
3673 mips_split_64bit_move (operands[0], operands[1]);
3678 [(set (match_operand:DF 0 "nonimmediate_operand")
3679 (match_operand:DF 1 "move_operand"))]
3680 "reload_completed && !TARGET_64BIT
3681 && mips_split_64bit_move_p (operands[0], operands[1])"
3684 mips_split_64bit_move (operands[0], operands[1]);
3688 ;; When generating mips16 code, split moves of negative constants into
3689 ;; a positive "li" followed by a negation.
3691 [(set (match_operand 0 "register_operand")
3692 (match_operand 1 "const_int_operand"))]
3693 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
3697 (neg:SI (match_dup 2)))]
3699 operands[2] = gen_lowpart (SImode, operands[0]);
3700 operands[3] = GEN_INT (-INTVAL (operands[1]));
3703 ;; 64-bit paired-single floating point moves
3705 (define_expand "movv2sf"
3706 [(set (match_operand:V2SF 0)
3707 (match_operand:V2SF 1))]
3708 "TARGET_PAIRED_SINGLE_FLOAT"
3710 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
3714 (define_insn "movv2sf_hardfloat_64bit"
3715 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3716 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
3717 "TARGET_PAIRED_SINGLE_FLOAT
3719 && (register_operand (operands[0], V2SFmode)
3720 || reg_or_0_operand (operands[1], V2SFmode))"
3721 { return mips_output_move (operands[0], operands[1]); }
3722 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3723 (set_attr "mode" "SF")
3724 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3726 ;; The HI and LO registers are not truly independent. If we move an mthi
3727 ;; instruction before an mflo instruction, it will make the result of the
3728 ;; mflo unpredictable. The same goes for mtlo and mfhi.
3730 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
3731 ;; Operand 1 is the register we want, operand 2 is the other one.
3733 (define_insn "mfhilo_<mode>"
3734 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3735 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3736 (match_operand:GPR 2 "register_operand" "l,h")]
3740 [(set_attr "type" "mfhilo")
3741 (set_attr "mode" "<MODE>")])
3743 ;; Patterns for loading or storing part of a paired floating point
3744 ;; register. We need them because odd-numbered floating-point registers
3745 ;; are not fully independent: see mips_split_64bit_move.
3747 ;; Load the low word of operand 0 with operand 1.
3748 (define_insn "load_df_low"
3749 [(set (match_operand:DF 0 "register_operand" "=f,f")
3750 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
3751 UNSPEC_LOAD_DF_LOW))]
3752 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3754 operands[0] = mips_subword (operands[0], 0);
3755 return mips_output_move (operands[0], operands[1]);
3757 [(set_attr "type" "xfer,fpload")
3758 (set_attr "mode" "SF")])
3760 ;; Load the high word of operand 0 from operand 1, preserving the value
3762 (define_insn "load_df_high"
3763 [(set (match_operand:DF 0 "register_operand" "=f,f")
3764 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
3765 (match_operand:DF 2 "register_operand" "0,0")]
3766 UNSPEC_LOAD_DF_HIGH))]
3767 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3769 operands[0] = mips_subword (operands[0], 1);
3770 return mips_output_move (operands[0], operands[1]);
3772 [(set_attr "type" "xfer,fpload")
3773 (set_attr "mode" "SF")])
3775 ;; Store the high word of operand 1 in operand 0. The corresponding
3776 ;; low-word move is done in the normal way.
3777 (define_insn "store_df_high"
3778 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
3779 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
3780 UNSPEC_STORE_DF_HIGH))]
3781 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3783 operands[1] = mips_subword (operands[1], 1);
3784 return mips_output_move (operands[0], operands[1]);
3786 [(set_attr "type" "xfer,fpstore")
3787 (set_attr "mode" "SF")])
3789 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
3790 ;; of _gp from the start of this function. Operand 1 is the incoming
3791 ;; function address.
3792 (define_insn_and_split "loadgp"
3793 [(unspec_volatile [(match_operand 0 "" "")
3794 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
3795 "TARGET_ABICALLS && TARGET_NEWABI"
3798 [(set (match_dup 2) (match_dup 3))
3799 (set (match_dup 2) (match_dup 4))
3800 (set (match_dup 2) (match_dup 5))]
3802 operands[2] = pic_offset_table_rtx;
3803 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
3804 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
3805 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
3807 [(set_attr "length" "12")])
3809 ;; The use of gp is hidden when not using explicit relocations.
3810 ;; This blockage instruction prevents the gp load from being
3811 ;; scheduled after an implicit use of gp. It also prevents
3812 ;; the load from being deleted as dead.
3813 (define_insn "loadgp_blockage"
3814 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
3817 [(set_attr "type" "unknown")
3818 (set_attr "mode" "none")
3819 (set_attr "length" "0")])
3821 ;; Emit a .cprestore directive, which normally expands to a single store
3822 ;; instruction. Note that we continue to use .cprestore for explicit reloc
3823 ;; code so that jals inside inline asms will work correctly.
3824 (define_insn "cprestore"
3825 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
3829 if (set_nomacro && which_alternative == 1)
3830 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
3832 return ".cprestore\t%0";
3834 [(set_attr "type" "store")
3835 (set_attr "length" "4,12")])
3837 ;; Block moves, see mips.c for more details.
3838 ;; Argument 0 is the destination
3839 ;; Argument 1 is the source
3840 ;; Argument 2 is the length
3841 ;; Argument 3 is the alignment
3843 (define_expand "movmemsi"
3844 [(parallel [(set (match_operand:BLK 0 "general_operand")
3845 (match_operand:BLK 1 "general_operand"))
3846 (use (match_operand:SI 2 ""))
3847 (use (match_operand:SI 3 "const_int_operand"))])]
3848 "!TARGET_MIPS16 && !TARGET_MEMCPY"
3850 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
3857 ;; ....................
3861 ;; ....................
3863 (define_expand "<optab><mode>3"
3864 [(set (match_operand:GPR 0 "register_operand")
3865 (any_shift:GPR (match_operand:GPR 1 "register_operand")
3866 (match_operand:SI 2 "arith_operand")))]
3869 /* On the mips16, a shift of more than 8 is a four byte instruction,
3870 so, for a shift between 8 and 16, it is just as fast to do two
3871 shifts of 8 or less. If there is a lot of shifting going on, we
3872 may win in CSE. Otherwise combine will put the shifts back
3873 together again. This can be called by function_arg, so we must
3874 be careful not to allocate a new register if we've reached the
3878 && GET_CODE (operands[2]) == CONST_INT
3879 && INTVAL (operands[2]) > 8
3880 && INTVAL (operands[2]) <= 16
3881 && !reload_in_progress
3882 && !reload_completed)
3884 rtx temp = gen_reg_rtx (<MODE>mode);
3886 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
3887 emit_insn (gen_<optab><mode>3 (operands[0], temp,
3888 GEN_INT (INTVAL (operands[2]) - 8)));
3893 (define_insn "*<optab><mode>3"
3894 [(set (match_operand:GPR 0 "register_operand" "=d")
3895 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
3896 (match_operand:SI 2 "arith_operand" "dI")))]
3899 if (GET_CODE (operands[2]) == CONST_INT)
3900 operands[2] = GEN_INT (INTVAL (operands[2])
3901 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
3903 return "<d><insn>\t%0,%1,%2";
3905 [(set_attr "type" "shift")
3906 (set_attr "mode" "<MODE>")])
3908 (define_insn "*<optab>si3_extend"
3909 [(set (match_operand:DI 0 "register_operand" "=d")
3911 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
3912 (match_operand:SI 2 "arith_operand" "dI"))))]
3913 "TARGET_64BIT && !TARGET_MIPS16"
3915 if (GET_CODE (operands[2]) == CONST_INT)
3916 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
3918 return "<insn>\t%0,%1,%2";
3920 [(set_attr "type" "shift")
3921 (set_attr "mode" "SI")])
3923 (define_insn "*<optab>si3_mips16"
3924 [(set (match_operand:SI 0 "register_operand" "=d,d")
3925 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
3926 (match_operand:SI 2 "arith_operand" "d,I")))]
3929 if (which_alternative == 0)
3930 return "<insn>\t%0,%2";
3932 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
3933 return "<insn>\t%0,%1,%2";
3935 [(set_attr "type" "shift")
3936 (set_attr "mode" "SI")
3937 (set_attr_alternative "length"
3939 (if_then_else (match_operand 2 "m16_uimm3_b")
3943 ;; We need separate DImode MIPS16 patterns because of the irregularity
3945 (define_insn "*ashldi3_mips16"
3946 [(set (match_operand:DI 0 "register_operand" "=d,d")
3947 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
3948 (match_operand:SI 2 "arith_operand" "d,I")))]
3949 "TARGET_64BIT && TARGET_MIPS16"
3951 if (which_alternative == 0)
3952 return "dsll\t%0,%2";
3954 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
3955 return "dsll\t%0,%1,%2";
3957 [(set_attr "type" "shift")
3958 (set_attr "mode" "DI")
3959 (set_attr_alternative "length"
3961 (if_then_else (match_operand 2 "m16_uimm3_b")
3965 (define_insn "*ashrdi3_mips16"
3966 [(set (match_operand:DI 0 "register_operand" "=d,d")
3967 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
3968 (match_operand:SI 2 "arith_operand" "d,I")))]
3969 "TARGET_64BIT && TARGET_MIPS16"
3971 if (GET_CODE (operands[2]) == CONST_INT)
3972 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
3974 return "dsra\t%0,%2";
3976 [(set_attr "type" "shift")
3977 (set_attr "mode" "DI")
3978 (set_attr_alternative "length"
3980 (if_then_else (match_operand 2 "m16_uimm3_b")
3984 (define_insn "*lshrdi3_mips16"
3985 [(set (match_operand:DI 0 "register_operand" "=d,d")
3986 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
3987 (match_operand:SI 2 "arith_operand" "d,I")))]
3988 "TARGET_64BIT && TARGET_MIPS16"
3990 if (GET_CODE (operands[2]) == CONST_INT)
3991 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
3993 return "dsrl\t%0,%2";
3995 [(set_attr "type" "shift")
3996 (set_attr "mode" "DI")
3997 (set_attr_alternative "length"
3999 (if_then_else (match_operand 2 "m16_uimm3_b")
4003 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4006 [(set (match_operand:GPR 0 "register_operand")
4007 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4008 (match_operand:GPR 2 "const_int_operand")))]
4009 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4010 && GET_CODE (operands[2]) == CONST_INT
4011 && INTVAL (operands[2]) > 8
4012 && INTVAL (operands[2]) <= 16"
4013 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4014 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4015 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4017 ;; If we load a byte on the mips16 as a bitfield, the resulting
4018 ;; sequence of instructions is too complicated for combine, because it
4019 ;; involves four instructions: a load, a shift, a constant load into a
4020 ;; register, and an and (the key problem here is that the mips16 does
4021 ;; not have and immediate). We recognize a shift of a load in order
4022 ;; to make it simple enough for combine to understand.
4024 ;; The length here is the worst case: the length of the split version
4025 ;; will be more accurate.
4026 (define_insn_and_split ""
4027 [(set (match_operand:SI 0 "register_operand" "=d")
4028 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4029 (match_operand:SI 2 "immediate_operand" "I")))]
4033 [(set (match_dup 0) (match_dup 1))
4034 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4036 [(set_attr "type" "load")
4037 (set_attr "mode" "SI")
4038 (set_attr "length" "16")])
4040 (define_insn "rotr<mode>3"
4041 [(set (match_operand:GPR 0 "register_operand" "=d")
4042 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4043 (match_operand:SI 2 "arith_operand" "dI")))]
4044 "ISA_HAS_ROTR_<MODE>"
4046 if (GET_CODE (operands[2]) == CONST_INT)
4047 gcc_assert (INTVAL (operands[2]) >= 0
4048 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4050 return "<d>ror\t%0,%1,%2";
4052 [(set_attr "type" "shift")
4053 (set_attr "mode" "<MODE>")])
4056 ;; ....................
4060 ;; ....................
4062 ;; Flow here is rather complex:
4064 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4065 ;; into cmp_operands[] but generates no RTL.
4067 ;; 2) The appropriate branch define_expand is called, which then
4068 ;; creates the appropriate RTL for the comparison and branch.
4069 ;; Different CC modes are used, based on what type of branch is
4070 ;; done, so that we can constrain things appropriately. There
4071 ;; are assumptions in the rest of GCC that break if we fold the
4072 ;; operands into the branches for integer operations, and use cc0
4073 ;; for floating point, so we use the fp status register instead.
4074 ;; If needed, an appropriate temporary is created to hold the
4075 ;; of the integer compare.
4077 (define_expand "cmp<mode>"
4079 (compare:CC (match_operand:GPR 0 "register_operand")
4080 (match_operand:GPR 1 "nonmemory_operand")))]
4083 cmp_operands[0] = operands[0];
4084 cmp_operands[1] = operands[1];
4088 (define_expand "cmp<mode>"
4090 (compare:CC (match_operand:SCALARF 0 "register_operand")
4091 (match_operand:SCALARF 1 "register_operand")))]
4094 cmp_operands[0] = operands[0];
4095 cmp_operands[1] = operands[1];
4100 ;; ....................
4102 ;; CONDITIONAL BRANCHES
4104 ;; ....................
4106 ;; Conditional branches on floating-point equality tests.
4108 (define_insn "branch_fp"
4111 (match_operator:CC 0 "comparison_operator"
4112 [(match_operand:CC 2 "register_operand" "z")
4114 (label_ref (match_operand 1 "" ""))
4118 return mips_output_conditional_branch (insn,
4120 /*two_operands_p=*/0,
4123 get_attr_length (insn));
4125 [(set_attr "type" "branch")
4126 (set_attr "mode" "none")])
4128 (define_insn "branch_fp_inverted"
4131 (match_operator:CC 0 "comparison_operator"
4132 [(match_operand:CC 2 "register_operand" "z")
4135 (label_ref (match_operand 1 "" ""))))]
4138 return mips_output_conditional_branch (insn,
4140 /*two_operands_p=*/0,
4143 get_attr_length (insn));
4145 [(set_attr "type" "branch")
4146 (set_attr "mode" "none")])
4148 ;; Conditional branches on comparisons with zero.
4150 (define_insn "*branch_zero<mode>"
4153 (match_operator:GPR 0 "comparison_operator"
4154 [(match_operand:GPR 2 "register_operand" "d")
4156 (label_ref (match_operand 1 "" ""))
4160 return mips_output_conditional_branch (insn,
4162 /*two_operands_p=*/0,
4165 get_attr_length (insn));
4167 [(set_attr "type" "branch")
4168 (set_attr "mode" "none")])
4170 (define_insn "*branch_zero<mode>_inverted"
4173 (match_operator:GPR 0 "comparison_operator"
4174 [(match_operand:GPR 2 "register_operand" "d")
4177 (label_ref (match_operand 1 "" ""))))]
4180 return mips_output_conditional_branch (insn,
4182 /*two_operands_p=*/0,
4185 get_attr_length (insn));
4187 [(set_attr "type" "branch")
4188 (set_attr "mode" "none")])
4190 ;; Conditional branch on equality comparison.
4192 (define_insn "*branch_equality<mode>"
4195 (match_operator:GPR 0 "equality_operator"
4196 [(match_operand:GPR 2 "register_operand" "d")
4197 (match_operand:GPR 3 "register_operand" "d")])
4198 (label_ref (match_operand 1 "" ""))
4202 return mips_output_conditional_branch (insn,
4204 /*two_operands_p=*/1,
4207 get_attr_length (insn));
4209 [(set_attr "type" "branch")
4210 (set_attr "mode" "none")])
4212 (define_insn "*branch_equality<mode>_inverted"
4215 (match_operator:GPR 0 "equality_operator"
4216 [(match_operand:GPR 2 "register_operand" "d")
4217 (match_operand:GPR 3 "register_operand" "d")])
4219 (label_ref (match_operand 1 "" ""))))]
4222 return mips_output_conditional_branch (insn,
4224 /*two_operands_p=*/1,
4227 get_attr_length (insn));
4229 [(set_attr "type" "branch")
4230 (set_attr "mode" "none")])
4234 (define_insn "*branch_equality<mode>_mips16"
4237 (match_operator:GPR 0 "equality_operator"
4238 [(match_operand:GPR 1 "register_operand" "d,t")
4240 (match_operand 2 "pc_or_label_operand" "")
4241 (match_operand 3 "pc_or_label_operand" "")))]
4244 if (operands[2] != pc_rtx)
4246 if (which_alternative == 0)
4247 return "b%C0z\t%1,%2";
4249 return "bt%C0z\t%2";
4253 if (which_alternative == 0)
4254 return "b%N0z\t%1,%3";
4256 return "bt%N0z\t%3";
4259 [(set_attr "type" "branch")
4260 (set_attr "mode" "none")
4261 (set_attr "length" "8")])
4263 (define_expand "b<code>"
4265 (if_then_else (any_cond:CC (cc0)
4267 (label_ref (match_operand 0 ""))
4271 gen_conditional_branch (operands, <CODE>);
4276 ;; ....................
4278 ;; SETTING A REGISTER FROM A COMPARISON
4280 ;; ....................
4282 (define_expand "seq"
4283 [(set (match_operand:SI 0 "register_operand")
4284 (eq:SI (match_dup 1)
4287 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4289 (define_insn "*seq_<mode>"
4290 [(set (match_operand:GPR 0 "register_operand" "=d")
4291 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4295 [(set_attr "type" "slt")
4296 (set_attr "mode" "<MODE>")])
4298 (define_insn "*seq_<mode>_mips16"
4299 [(set (match_operand:GPR 0 "register_operand" "=t")
4300 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4304 [(set_attr "type" "slt")
4305 (set_attr "mode" "<MODE>")])
4307 ;; "sne" uses sltu instructions in which the first operand is $0.
4308 ;; This isn't possible in mips16 code.
4310 (define_expand "sne"
4311 [(set (match_operand:SI 0 "register_operand")
4312 (ne:SI (match_dup 1)
4315 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
4317 (define_insn "*sne_<mode>"
4318 [(set (match_operand:GPR 0 "register_operand" "=d")
4319 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
4323 [(set_attr "type" "slt")
4324 (set_attr "mode" "<MODE>")])
4326 (define_expand "sgt"
4327 [(set (match_operand:SI 0 "register_operand")
4328 (gt:SI (match_dup 1)
4331 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
4333 (define_insn "*sgt_<mode>"
4334 [(set (match_operand:GPR 0 "register_operand" "=d")
4335 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4336 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4339 [(set_attr "type" "slt")
4340 (set_attr "mode" "<MODE>")])
4342 (define_insn "*sgt_<mode>_mips16"
4343 [(set (match_operand:GPR 0 "register_operand" "=t")
4344 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4345 (match_operand:GPR 2 "register_operand" "d")))]
4348 [(set_attr "type" "slt")
4349 (set_attr "mode" "<MODE>")])
4351 (define_expand "sge"
4352 [(set (match_operand:SI 0 "register_operand")
4353 (ge:SI (match_dup 1)
4356 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
4358 (define_insn "*sge_<mode>"
4359 [(set (match_operand:GPR 0 "register_operand" "=d")
4360 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
4364 [(set_attr "type" "slt")
4365 (set_attr "mode" "<MODE>")])
4367 (define_expand "slt"
4368 [(set (match_operand:SI 0 "register_operand")
4369 (lt:SI (match_dup 1)
4372 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
4374 (define_insn "*slt_<mode>"
4375 [(set (match_operand:GPR 0 "register_operand" "=d")
4376 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
4377 (match_operand:GPR 2 "arith_operand" "dI")))]
4380 [(set_attr "type" "slt")
4381 (set_attr "mode" "<MODE>")])
4383 (define_insn "*slt_<mode>_mips16"
4384 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4385 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
4386 (match_operand:GPR 2 "arith_operand" "d,I")))]
4389 [(set_attr "type" "slt")
4390 (set_attr "mode" "<MODE>")
4391 (set_attr_alternative "length"
4393 (if_then_else (match_operand 2 "m16_uimm8_1")
4397 (define_expand "sle"
4398 [(set (match_operand:SI 0 "register_operand")
4399 (le:SI (match_dup 1)
4402 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
4404 (define_insn "*sle_<mode>"
4405 [(set (match_operand:GPR 0 "register_operand" "=d")
4406 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4407 (match_operand:GPR 2 "sle_operand" "")))]
4410 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4411 return "slt\t%0,%1,%2";
4413 [(set_attr "type" "slt")
4414 (set_attr "mode" "<MODE>")])
4416 (define_insn "*sle_<mode>_mips16"
4417 [(set (match_operand:GPR 0 "register_operand" "=t")
4418 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4419 (match_operand:GPR 2 "sle_operand" "")))]
4422 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4423 return "slt\t%1,%2";
4425 [(set_attr "type" "slt")
4426 (set_attr "mode" "<MODE>")
4427 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4431 (define_expand "sgtu"
4432 [(set (match_operand:SI 0 "register_operand")
4433 (gtu:SI (match_dup 1)
4436 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
4438 (define_insn "*sgtu_<mode>"
4439 [(set (match_operand:GPR 0 "register_operand" "=d")
4440 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4441 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4444 [(set_attr "type" "slt")
4445 (set_attr "mode" "<MODE>")])
4447 (define_insn "*sgtu_<mode>_mips16"
4448 [(set (match_operand:GPR 0 "register_operand" "=t")
4449 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4450 (match_operand:GPR 2 "register_operand" "d")))]
4453 [(set_attr "type" "slt")
4454 (set_attr "mode" "<MODE>")])
4456 (define_expand "sgeu"
4457 [(set (match_operand:SI 0 "register_operand")
4458 (geu:SI (match_dup 1)
4461 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
4463 (define_insn "*sge_<mode>"
4464 [(set (match_operand:GPR 0 "register_operand" "=d")
4465 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
4469 [(set_attr "type" "slt")
4470 (set_attr "mode" "<MODE>")])
4472 (define_expand "sltu"
4473 [(set (match_operand:SI 0 "register_operand")
4474 (ltu:SI (match_dup 1)
4477 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
4479 (define_insn "*sltu_<mode>"
4480 [(set (match_operand:GPR 0 "register_operand" "=d")
4481 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
4482 (match_operand:GPR 2 "arith_operand" "dI")))]
4485 [(set_attr "type" "slt")
4486 (set_attr "mode" "<MODE>")])
4488 (define_insn "*sltu_<mode>_mips16"
4489 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4490 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
4491 (match_operand:GPR 2 "arith_operand" "d,I")))]
4494 [(set_attr "type" "slt")
4495 (set_attr "mode" "<MODE>")
4496 (set_attr_alternative "length"
4498 (if_then_else (match_operand 2 "m16_uimm8_1")
4502 (define_expand "sleu"
4503 [(set (match_operand:SI 0 "register_operand")
4504 (leu:SI (match_dup 1)
4507 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
4509 (define_insn "*sleu_<mode>"
4510 [(set (match_operand:GPR 0 "register_operand" "=d")
4511 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4512 (match_operand:GPR 2 "sleu_operand" "")))]
4515 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4516 return "sltu\t%0,%1,%2";
4518 [(set_attr "type" "slt")
4519 (set_attr "mode" "<MODE>")])
4521 (define_insn "*sleu_<mode>_mips16"
4522 [(set (match_operand:GPR 0 "register_operand" "=t")
4523 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4524 (match_operand:GPR 2 "sleu_operand" "")))]
4527 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4528 return "sltu\t%1,%2";
4530 [(set_attr "type" "slt")
4531 (set_attr "mode" "<MODE>")
4532 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4537 ;; ....................
4539 ;; FLOATING POINT COMPARISONS
4541 ;; ....................
4543 (define_insn "s<code>_<mode>"
4544 [(set (match_operand:CC 0 "register_operand" "=z")
4545 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4546 (match_operand:SCALARF 2 "register_operand" "f")))]
4548 "c.<fcond>.<fmt>\t%Z0%1,%2"
4549 [(set_attr "type" "fcmp")
4550 (set_attr "mode" "FPSW")])
4552 (define_insn "sgt_<mode>"
4553 [(set (match_operand:CC 0 "register_operand" "=z")
4554 (gt:CC (match_operand:SCALARF 1 "register_operand" "f")
4555 (match_operand:SCALARF 2 "register_operand" "f")))]
4557 "c.lt.<fmt>\t%Z0%2,%1"
4558 [(set_attr "type" "fcmp")
4559 (set_attr "mode" "FPSW")])
4561 (define_insn "sge_<mode>"
4562 [(set (match_operand:CC 0 "register_operand" "=z")
4563 (ge:CC (match_operand:SCALARF 1 "register_operand" "f")
4564 (match_operand:SCALARF 2 "register_operand" "f")))]
4566 "c.le.<fmt>\t%Z0%2,%1"
4567 [(set_attr "type" "fcmp")
4568 (set_attr "mode" "FPSW")])
4571 ;; ....................
4573 ;; UNCONDITIONAL BRANCHES
4575 ;; ....................
4577 ;; Unconditional branches.
4581 (label_ref (match_operand 0 "" "")))]
4586 if (get_attr_length (insn) <= 8)
4587 return "%*b\t%l0%/";
4590 output_asm_insn (mips_output_load_label (), operands);
4591 return "%*jr\t%@%/%]";
4595 return "%*j\t%l0%/";
4597 [(set_attr "type" "jump")
4598 (set_attr "mode" "none")
4599 (set (attr "length")
4600 ;; We can't use `j' when emitting PIC. Emit a branch if it's
4601 ;; in range, otherwise load the address of the branch target into
4602 ;; $at and then jump to it.
4604 (ior (eq (symbol_ref "flag_pic") (const_int 0))
4605 (lt (abs (minus (match_dup 0)
4606 (plus (pc) (const_int 4))))
4607 (const_int 131072)))
4608 (const_int 4) (const_int 16)))])
4610 ;; We need a different insn for the mips16, because a mips16 branch
4611 ;; does not have a delay slot.
4615 (label_ref (match_operand 0 "" "")))]
4618 [(set_attr "type" "branch")
4619 (set_attr "mode" "none")
4620 (set_attr "length" "8")])
4622 (define_expand "indirect_jump"
4623 [(set (pc) (match_operand 0 "register_operand"))]
4626 operands[0] = force_reg (Pmode, operands[0]);
4627 if (Pmode == SImode)
4628 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
4630 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
4634 (define_insn "indirect_jump<mode>"
4635 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
4638 [(set_attr "type" "jump")
4639 (set_attr "mode" "none")])
4641 (define_expand "tablejump"
4643 (match_operand 0 "register_operand"))
4644 (use (label_ref (match_operand 1 "")))]
4648 operands[0] = expand_binop (Pmode, add_optab,
4649 convert_to_mode (Pmode, operands[0], false),
4650 gen_rtx_LABEL_REF (Pmode, operands[1]),
4652 else if (TARGET_GPWORD)
4653 operands[0] = expand_binop (Pmode, add_optab, operands[0],
4654 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
4656 if (Pmode == SImode)
4657 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
4659 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
4663 (define_insn "tablejump<mode>"
4665 (match_operand:P 0 "register_operand" "d"))
4666 (use (label_ref (match_operand 1 "" "")))]
4669 [(set_attr "type" "jump")
4670 (set_attr "mode" "none")])
4672 ;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well.
4673 ;; While it is possible to either pull it off the stack (in the
4674 ;; o32 case) or recalculate it given t9 and our target label,
4675 ;; it takes 3 or 4 insns to do so.
4677 (define_expand "builtin_setjmp_setup"
4678 [(use (match_operand 0 "register_operand"))]
4683 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
4684 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
4688 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
4689 ;; that older code did recalculate the gp from $25. Continue to jump through
4690 ;; $25 for compatibility (we lose nothing by doing so).
4692 (define_expand "builtin_longjmp"
4693 [(use (match_operand 0 "register_operand"))]
4696 /* The elements of the buffer are, in order: */
4697 int W = GET_MODE_SIZE (Pmode);
4698 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
4699 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
4700 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
4701 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
4702 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
4703 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
4704 The target is bound to be using $28 as the global pointer
4705 but the current function might not be. */
4706 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
4708 /* This bit is similar to expand_builtin_longjmp except that it
4709 restores $gp as well. */
4710 emit_move_insn (hard_frame_pointer_rtx, fp);
4711 emit_move_insn (pv, lab);
4712 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
4713 emit_move_insn (gp, gpv);
4714 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
4715 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4716 emit_insn (gen_rtx_USE (VOIDmode, gp));
4717 emit_indirect_jump (pv);
4722 ;; ....................
4724 ;; Function prologue/epilogue
4726 ;; ....................
4729 (define_expand "prologue"
4733 mips_expand_prologue ();
4737 ;; Block any insns from being moved before this point, since the
4738 ;; profiling call to mcount can use various registers that aren't
4739 ;; saved or used to pass arguments.
4741 (define_insn "blockage"
4742 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
4745 [(set_attr "type" "unknown")
4746 (set_attr "mode" "none")
4747 (set_attr "length" "0")])
4749 (define_expand "epilogue"
4753 mips_expand_epilogue (false);
4757 (define_expand "sibcall_epilogue"
4761 mips_expand_epilogue (true);
4765 ;; Trivial return. Make it look like a normal return insn as that
4766 ;; allows jump optimizations to work better.
4768 (define_insn "return"
4770 "mips_can_use_return_insn ()"
4772 [(set_attr "type" "jump")
4773 (set_attr "mode" "none")])
4777 (define_insn "return_internal"
4779 (use (match_operand 0 "pmode_register_operand" ""))]
4782 [(set_attr "type" "jump")
4783 (set_attr "mode" "none")])
4785 ;; This is used in compiling the unwind routines.
4786 (define_expand "eh_return"
4787 [(use (match_operand 0 "general_operand"))]
4790 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
4792 if (GET_MODE (operands[0]) != gpr_mode)
4793 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
4795 emit_insn (gen_eh_set_lr_di (operands[0]));
4797 emit_insn (gen_eh_set_lr_si (operands[0]));
4802 ;; Clobber the return address on the stack. We can't expand this
4803 ;; until we know where it will be put in the stack frame.
4805 (define_insn "eh_set_lr_si"
4806 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
4807 (clobber (match_scratch:SI 1 "=&d"))]
4811 (define_insn "eh_set_lr_di"
4812 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
4813 (clobber (match_scratch:DI 1 "=&d"))]
4818 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
4819 (clobber (match_scratch 1))]
4820 "reload_completed && !TARGET_DEBUG_D_MODE"
4823 mips_set_return_address (operands[0], operands[1]);
4827 (define_insn_and_split "exception_receiver"
4829 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
4830 "TARGET_ABICALLS && TARGET_OLDABI"
4832 "&& reload_completed"
4838 [(set_attr "type" "load")
4839 (set_attr "length" "12")])
4842 ;; ....................
4846 ;; ....................
4848 ;; Instructions to load a call address from the GOT. The address might
4849 ;; point to a function or to a lazy binding stub. In the latter case,
4850 ;; the stub will use the dynamic linker to resolve the function, which
4851 ;; in turn will change the GOT entry to point to the function's real
4854 ;; This means that every call, even pure and constant ones, can
4855 ;; potentially modify the GOT entry. And once a stub has been called,
4856 ;; we must not call it again.
4858 ;; We represent this restriction using an imaginary fixed register that
4859 ;; acts like a GOT version number. By making the register call-clobbered,
4860 ;; we tell the target-independent code that the address could be changed
4861 ;; by any call insn.
4862 (define_insn "load_call<mode>"
4863 [(set (match_operand:P 0 "register_operand" "=c")
4864 (unspec:P [(match_operand:P 1 "register_operand" "r")
4865 (match_operand:P 2 "immediate_operand" "")
4866 (reg:P FAKE_CALL_REGNO)]
4869 "<load>\t%0,%R2(%1)"
4870 [(set_attr "type" "load")
4871 (set_attr "mode" "<MODE>")
4872 (set_attr "length" "4")])
4874 ;; Sibling calls. All these patterns use jump instructions.
4876 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
4877 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
4878 ;; is defined in terms of call_insn_operand, the same is true of the
4881 ;; When we use an indirect jump, we need a register that will be
4882 ;; preserved by the epilogue. Since TARGET_ABICALLS forces us to
4883 ;; use $25 for this purpose -- and $25 is never clobbered by the
4884 ;; epilogue -- we might as well use it for !TARGET_ABICALLS as well.
4886 (define_expand "sibcall"
4887 [(parallel [(call (match_operand 0 "")
4888 (match_operand 1 ""))
4889 (use (match_operand 2 "")) ;; next_arg_reg
4890 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
4893 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
4897 (define_insn "sibcall_internal"
4898 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
4899 (match_operand 1 "" ""))]
4900 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
4904 [(set_attr "type" "call")])
4906 (define_expand "sibcall_value"
4907 [(parallel [(set (match_operand 0 "")
4908 (call (match_operand 1 "")
4909 (match_operand 2 "")))
4910 (use (match_operand 3 ""))])] ;; next_arg_reg
4913 mips_expand_call (operands[0], XEXP (operands[1], 0),
4914 operands[2], operands[3], true);
4918 (define_insn "sibcall_value_internal"
4919 [(set (match_operand 0 "register_operand" "=df,df")
4920 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
4921 (match_operand 2 "" "")))]
4922 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
4926 [(set_attr "type" "call")])
4928 (define_insn "sibcall_value_multiple_internal"
4929 [(set (match_operand 0 "register_operand" "=df,df")
4930 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
4931 (match_operand 2 "" "")))
4932 (set (match_operand 3 "register_operand" "=df,df")
4933 (call (mem:SI (match_dup 1))
4935 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
4939 [(set_attr "type" "call")])
4941 (define_expand "call"
4942 [(parallel [(call (match_operand 0 "")
4943 (match_operand 1 ""))
4944 (use (match_operand 2 "")) ;; next_arg_reg
4945 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
4948 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
4952 ;; This instruction directly corresponds to an assembly-language "jal".
4953 ;; There are four cases:
4956 ;; Both symbolic and register destinations are OK. The pattern
4957 ;; always expands to a single mips instruction.
4959 ;; - -mabicalls/-mno-explicit-relocs:
4960 ;; Again, both symbolic and register destinations are OK.
4961 ;; The call is treated as a multi-instruction black box.
4963 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
4964 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
4967 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
4968 ;; Only "jal $25" is allowed. The call is actually two instructions:
4969 ;; "jalr $25" followed by an insn to reload $gp.
4971 ;; In the last case, we can generate the individual instructions with
4972 ;; a define_split. There are several things to be wary of:
4974 ;; - We can't expose the load of $gp before reload. If we did,
4975 ;; it might get removed as dead, but reload can introduce new
4976 ;; uses of $gp by rematerializing constants.
4978 ;; - We shouldn't restore $gp after calls that never return.
4979 ;; It isn't valid to insert instructions between a noreturn
4980 ;; call and the following barrier.
4982 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
4983 ;; instruction preserves $gp and so have no effect on its liveness.
4984 ;; But once we generate the separate insns, it becomes obvious that
4985 ;; $gp is not live on entry to the call.
4987 ;; ??? The operands[2] = insn check is a hack to make the original insn
4988 ;; available to the splitter.
4989 (define_insn_and_split "call_internal"
4990 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
4991 (match_operand 1 "" ""))
4992 (clobber (reg:SI 31))]
4994 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%0%/"; }
4995 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
4998 emit_call_insn (gen_call_split (operands[0], operands[1]));
4999 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5003 [(set_attr "jal" "indirect,direct")
5004 (set_attr "extended_mips16" "no,yes")])
5006 (define_insn "call_split"
5007 [(call (mem:SI (match_operand 0 "call_insn_operand" "c"))
5008 (match_operand 1 "" ""))
5009 (clobber (reg:SI 31))
5010 (clobber (reg:SI 28))]
5011 "TARGET_SPLIT_CALLS"
5013 [(set_attr "type" "call")])
5015 (define_expand "call_value"
5016 [(parallel [(set (match_operand 0 "")
5017 (call (match_operand 1 "")
5018 (match_operand 2 "")))
5019 (use (match_operand 3 ""))])] ;; next_arg_reg
5022 mips_expand_call (operands[0], XEXP (operands[1], 0),
5023 operands[2], operands[3], false);
5027 ;; See comment for call_internal.
5028 (define_insn_and_split "call_value_internal"
5029 [(set (match_operand 0 "register_operand" "=df,df")
5030 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5031 (match_operand 2 "" "")))
5032 (clobber (reg:SI 31))]
5034 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
5035 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5038 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5040 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5044 [(set_attr "jal" "indirect,direct")
5045 (set_attr "extended_mips16" "no,yes")])
5047 (define_insn "call_value_split"
5048 [(set (match_operand 0 "register_operand" "=df")
5049 (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
5050 (match_operand 2 "" "")))
5051 (clobber (reg:SI 31))
5052 (clobber (reg:SI 28))]
5053 "TARGET_SPLIT_CALLS"
5055 [(set_attr "type" "call")])
5057 ;; See comment for call_internal.
5058 (define_insn_and_split "call_value_multiple_internal"
5059 [(set (match_operand 0 "register_operand" "=df,df")
5060 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5061 (match_operand 2 "" "")))
5062 (set (match_operand 3 "register_operand" "=df,df")
5063 (call (mem:SI (match_dup 1))
5065 (clobber (reg:SI 31))]
5067 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
5068 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5071 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5072 operands[2], operands[3]));
5073 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5077 [(set_attr "jal" "indirect,direct")
5078 (set_attr "extended_mips16" "no,yes")])
5080 (define_insn "call_value_multiple_split"
5081 [(set (match_operand 0 "register_operand" "=df")
5082 (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
5083 (match_operand 2 "" "")))
5084 (set (match_operand 3 "register_operand" "=df")
5085 (call (mem:SI (match_dup 1))
5087 (clobber (reg:SI 31))
5088 (clobber (reg:SI 28))]
5089 "TARGET_SPLIT_CALLS"
5091 [(set_attr "type" "call")])
5093 ;; Call subroutine returning any type.
5095 (define_expand "untyped_call"
5096 [(parallel [(call (match_operand 0 "")
5098 (match_operand 1 "")
5099 (match_operand 2 "")])]
5104 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5106 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5108 rtx set = XVECEXP (operands[2], 0, i);
5109 emit_move_insn (SET_DEST (set), SET_SRC (set));
5112 emit_insn (gen_blockage ());
5117 ;; ....................
5121 ;; ....................
5125 (define_insn "prefetch"
5126 [(prefetch (match_operand:QI 0 "address_operand" "p")
5127 (match_operand 1 "const_int_operand" "n")
5128 (match_operand 2 "const_int_operand" "n"))]
5129 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5131 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5132 return "pref\t%1,%a0";
5134 [(set_attr "type" "prefetch")])
5136 (define_insn "*prefetch_indexed_<mode>"
5137 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5138 (match_operand:P 1 "register_operand" "d"))
5139 (match_operand 2 "const_int_operand" "n")
5140 (match_operand 3 "const_int_operand" "n"))]
5141 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5143 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5144 return "prefx\t%2,%1(%0)";
5146 [(set_attr "type" "prefetchx")])
5152 [(set_attr "type" "nop")
5153 (set_attr "mode" "none")])
5155 ;; Like nop, but commented out when outside a .set noreorder block.
5156 (define_insn "hazard_nop"
5165 [(set_attr "type" "nop")])
5167 ;; MIPS4 Conditional move instructions.
5169 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5170 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5172 (match_operator:MOVECC 4 "equality_operator"
5173 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5175 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5176 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5181 [(set_attr "type" "condmove")
5182 (set_attr "mode" "<GPR:MODE>")])
5184 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5185 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5186 (if_then_else:SCALARF
5187 (match_operator:MOVECC 4 "equality_operator"
5188 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5190 (match_operand:SCALARF 2 "register_operand" "f,0")
5191 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5194 mov%T4.<fmt>\t%0,%2,%1
5195 mov%t4.<fmt>\t%0,%3,%1"
5196 [(set_attr "type" "condmove")
5197 (set_attr "mode" "<SCALARF:MODE>")])
5199 ;; These are the main define_expand's used to make conditional moves.
5201 (define_expand "mov<mode>cc"
5202 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5203 (set (match_operand:GPR 0 "register_operand")
5204 (if_then_else:GPR (match_dup 5)
5205 (match_operand:GPR 2 "reg_or_0_operand")
5206 (match_operand:GPR 3 "reg_or_0_operand")))]
5209 gen_conditional_move (operands);
5213 (define_expand "mov<mode>cc"
5214 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5215 (set (match_operand:SCALARF 0 "register_operand")
5216 (if_then_else:SCALARF (match_dup 5)
5217 (match_operand:SCALARF 2 "register_operand")
5218 (match_operand:SCALARF 3 "register_operand")))]
5221 gen_conditional_move (operands);
5226 ;; ....................
5228 ;; mips16 inline constant tables
5230 ;; ....................
5233 (define_insn "consttable_int"
5234 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5235 (match_operand 1 "const_int_operand" "")]
5236 UNSPEC_CONSTTABLE_INT)]
5239 assemble_integer (operands[0], INTVAL (operands[1]),
5240 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5243 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5245 (define_insn "consttable_float"
5246 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5247 UNSPEC_CONSTTABLE_FLOAT)]
5252 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5253 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5254 assemble_real (d, GET_MODE (operands[0]),
5255 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5258 [(set (attr "length")
5259 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5261 (define_insn "align"
5262 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5265 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5268 [(match_operand 0 "small_data_pattern")]
5271 { operands[0] = mips_rewrite_small_data (operands[0]); })
5273 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
5275 (include "mips-ps-3d.md")