1 ;; Machine description for GNU compiler, Vax Version
2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;;- Instruction patterns. When multiple patterns apply,
24 ;;- the first one in the file is chosen.
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29 ;;- updates for most instructions.
31 ;; We don't want to allow a constant operand for test insns because
32 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
33 ;; be folded while optimizing anyway.
37 (match_operand:SI 0 "nonimmediate_operand" "g"))]
43 (match_operand:HI 0 "nonimmediate_operand" "g"))]
49 (match_operand:QI 0 "nonimmediate_operand" "g"))]
55 (match_operand:DF 0 "general_operand" "gF"))]
61 (match_operand:SF 0 "general_operand" "gF"))]
67 (compare (match_operand:SI 0 "nonimmediate_operand" "g")
68 (match_operand:SI 1 "general_operand" "g")))]
74 (compare (match_operand:HI 0 "nonimmediate_operand" "g")
75 (match_operand:HI 1 "general_operand" "g")))]
81 (compare (match_operand:QI 0 "nonimmediate_operand" "g")
82 (match_operand:QI 1 "general_operand" "g")))]
88 (compare (match_operand:DF 0 "general_operand" "gF,gF")
89 (match_operand:DF 1 "general_operand" "G,gF")))]
97 (compare (match_operand:SF 0 "general_operand" "gF,gF")
98 (match_operand:SF 1 "general_operand" "G,gF")))]
106 (and:SI (match_operand:SI 0 "general_operand" "g")
107 (match_operand:SI 1 "general_operand" "g")))]
113 (and:HI (match_operand:HI 0 "general_operand" "g")
114 (match_operand:HI 1 "general_operand" "g")))]
120 (and:QI (match_operand:QI 0 "general_operand" "g")
121 (match_operand:QI 1 "general_operand" "g")))]
125 ;; The vax has no sCOND insns. It does have add/subtract with carry
126 ;; which could be used to implement the sltu and sgeu patterns. However,
127 ;; to do this properly requires a complete rewrite of the compare insns
128 ;; to keep them together with the sltu/sgeu insns until after the
129 ;; reload pass is complete. The previous implementation didn't do this
130 ;; and has been deleted.
134 [(set (match_operand:DF 0 "general_operand" "=g,g")
135 (match_operand:DF 1 "general_operand" "G,gF"))]
142 [(set (match_operand:SF 0 "general_operand" "=g,g")
143 (match_operand:SF 1 "general_operand" "G,gF"))]
149 ;; Some vaxes don't support this instruction.
150 ;;(define_insn "movti"
151 ;; [(set (match_operand:TI 0 "general_operand" "=g")
152 ;; (match_operand:TI 1 "general_operand" "g"))]
157 [(set (match_operand:DI 0 "general_operand" "=g,g")
158 (match_operand:DI 1 "general_operand" "I,g"))]
164 ;; The VAX move instructions have space-time tradeoffs. On a microVAX
165 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
166 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
167 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
168 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
169 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
170 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description
171 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
174 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
175 ;; but on a VAX 9000 most move and add instructions with one constant
176 ;; operand take 1 cycle).
178 ;; Loads of constants between 64 and 128 used to be done with
179 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
182 [(set (match_operand:SI 0 "general_operand" "=g")
183 (match_operand:SI 1 "general_operand" "g"))]
188 if (operands[1] == const1_rtx
189 && (link = find_reg_note (insn, REG_WAS_0, 0))
190 /* Make sure the insn that stored the 0 is still present. */
191 && ! INSN_DELETED_P (XEXP (link, 0))
192 && GET_CODE (XEXP (link, 0)) != NOTE
193 /* Make sure cross jumping didn't happen here. */
194 && no_labels_between_p (XEXP (link, 0), insn)
195 /* Make sure the reg hasn't been clobbered. */
196 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
198 if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
200 if (push_operand (operands[0], SImode))
201 return \"pushab %a1\";
202 return \"movab %a1,%0\";
204 if (operands[1] == const0_rtx)
206 if (GET_CODE (operands[1]) == CONST_INT
207 && (unsigned) INTVAL (operands[1]) >= 64)
209 int i = INTVAL (operands[1]);
210 if ((unsigned)(~i) < 64)
211 return \"mcoml %N1,%0\";
212 if ((unsigned)i < 0x100)
213 return \"movzbl %1,%0\";
214 if (i >= -0x80 && i < 0)
215 return \"cvtbl %1,%0\";
216 if ((unsigned)i < 0x10000)
217 return \"movzwl %1,%0\";
218 if (i >= -0x8000 && i < 0)
219 return \"cvtwl %1,%0\";
221 if (push_operand (operands[0], SImode))
223 return \"movl %1,%0\";
227 [(set (match_operand:HI 0 "general_operand" "=g")
228 (match_operand:HI 1 "general_operand" "g"))]
233 if (operands[1] == const1_rtx
234 && (link = find_reg_note (insn, REG_WAS_0, 0))
235 /* Make sure the insn that stored the 0 is still present. */
236 && ! INSN_DELETED_P (XEXP (link, 0))
237 && GET_CODE (XEXP (link, 0)) != NOTE
238 /* Make sure cross jumping didn't happen here. */
239 && no_labels_between_p (XEXP (link, 0), insn)
240 /* Make sure the reg hasn't been clobbered. */
241 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
244 if (GET_CODE (operands[1]) == CONST_INT)
246 int i = INTVAL (operands[1]);
249 else if ((unsigned int)i < 64)
250 return \"movw %1,%0\";
251 else if ((unsigned int)~i < 64)
252 return \"mcomw %H1,%0\";
253 else if ((unsigned int)i < 256)
254 return \"movzbw %1,%0\";
256 return \"movw %1,%0\";
259 (define_insn "movstricthi"
260 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
261 (match_operand:HI 1 "general_operand" "g"))]
265 if (GET_CODE (operands[1]) == CONST_INT)
267 int i = INTVAL (operands[1]);
270 else if ((unsigned int)i < 64)
271 return \"movw %1,%0\";
272 else if ((unsigned int)~i < 64)
273 return \"mcomw %H1,%0\";
274 else if ((unsigned int)i < 256)
275 return \"movzbw %1,%0\";
277 return \"movw %1,%0\";
281 [(set (match_operand:QI 0 "general_operand" "=g")
282 (match_operand:QI 1 "general_operand" "g"))]
287 if (operands[1] == const1_rtx
288 && (link = find_reg_note (insn, REG_WAS_0, 0))
289 /* Make sure the insn that stored the 0 is still present. */
290 && ! INSN_DELETED_P (XEXP (link, 0))
291 && GET_CODE (XEXP (link, 0)) != NOTE
292 /* Make sure cross jumping didn't happen here. */
293 && no_labels_between_p (XEXP (link, 0), insn)
294 /* Make sure the reg hasn't been clobbered. */
295 && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
298 if (GET_CODE (operands[1]) == CONST_INT)
300 int i = INTVAL (operands[1]);
303 else if ((unsigned int)~i < 64)
304 return \"mcomb %B1,%0\";
306 return \"movb %1,%0\";
309 (define_insn "movstrictqi"
310 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
311 (match_operand:QI 1 "general_operand" "g"))]
315 if (GET_CODE (operands[1]) == CONST_INT)
317 int i = INTVAL (operands[1]);
320 else if ((unsigned int)~i < 64)
321 return \"mcomb %B1,%0\";
323 return \"movb %1,%0\";
326 ;; This is here to accept 4 arguments and pass the first 3 along
327 ;; to the movstrhi1 pattern that really does the work.
328 (define_expand "movstrhi"
329 [(set (match_operand:BLK 0 "general_operand" "=g")
330 (match_operand:BLK 1 "general_operand" "g"))
331 (use (match_operand:HI 2 "general_operand" "g"))
332 (match_operand 3 "" "")]
335 emit_insn (gen_movstrhi1 (operands[0], operands[1], operands[2]));
339 ;; The definition of this insn does not really explain what it does,
340 ;; but it should suffice
341 ;; that anything generated as this insn will be recognized as one
342 ;; and that it won't successfully combine with anything.
343 (define_insn "movstrhi1"
344 [(set (match_operand:BLK 0 "general_operand" "=g")
345 (match_operand:BLK 1 "general_operand" "g"))
346 (use (match_operand:HI 2 "general_operand" "g"))
352 (clobber (reg:SI 5))]
356 ;; Extension and truncation insns.
358 (define_insn "truncsiqi2"
359 [(set (match_operand:QI 0 "general_operand" "=g")
360 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
364 (define_insn "truncsihi2"
365 [(set (match_operand:HI 0 "general_operand" "=g")
366 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
370 (define_insn "trunchiqi2"
371 [(set (match_operand:QI 0 "general_operand" "=g")
372 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
376 (define_insn "extendhisi2"
377 [(set (match_operand:SI 0 "general_operand" "=g")
378 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
382 (define_insn "extendqihi2"
383 [(set (match_operand:HI 0 "general_operand" "=g")
384 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
388 (define_insn "extendqisi2"
389 [(set (match_operand:SI 0 "general_operand" "=g")
390 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
394 (define_insn "extendsfdf2"
395 [(set (match_operand:DF 0 "general_operand" "=g")
396 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
400 (define_insn "truncdfsf2"
401 [(set (match_operand:SF 0 "general_operand" "=g")
402 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
406 (define_insn "zero_extendhisi2"
407 [(set (match_operand:SI 0 "general_operand" "=g")
408 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
412 (define_insn "zero_extendqihi2"
413 [(set (match_operand:HI 0 "general_operand" "=g")
414 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
418 (define_insn "zero_extendqisi2"
419 [(set (match_operand:SI 0 "general_operand" "=g")
420 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
424 ;; Fix-to-float conversion insns.
426 (define_insn "floatsisf2"
427 [(set (match_operand:SF 0 "general_operand" "=g")
428 (float:SF (match_operand:SI 1 "nonimmediate_operand" "g")))]
432 (define_insn "floatsidf2"
433 [(set (match_operand:DF 0 "general_operand" "=g")
434 (float:DF (match_operand:SI 1 "nonimmediate_operand" "g")))]
438 (define_insn "floathisf2"
439 [(set (match_operand:SF 0 "general_operand" "=g")
440 (float:SF (match_operand:HI 1 "nonimmediate_operand" "g")))]
444 (define_insn "floathidf2"
445 [(set (match_operand:DF 0 "general_operand" "=g")
446 (float:DF (match_operand:HI 1 "nonimmediate_operand" "g")))]
450 (define_insn "floatqisf2"
451 [(set (match_operand:SF 0 "general_operand" "=g")
452 (float:SF (match_operand:QI 1 "nonimmediate_operand" "g")))]
456 (define_insn "floatqidf2"
457 [(set (match_operand:DF 0 "general_operand" "=g")
458 (float:DF (match_operand:QI 1 "nonimmediate_operand" "g")))]
462 ;; Float-to-fix conversion insns.
464 (define_insn "fix_truncsfqi2"
465 [(set (match_operand:QI 0 "general_operand" "=g")
466 (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
470 (define_insn "fix_truncsfhi2"
471 [(set (match_operand:HI 0 "general_operand" "=g")
472 (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
476 (define_insn "fix_truncsfsi2"
477 [(set (match_operand:SI 0 "general_operand" "=g")
478 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
482 (define_insn "fix_truncdfqi2"
483 [(set (match_operand:QI 0 "general_operand" "=g")
484 (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
488 (define_insn "fix_truncdfhi2"
489 [(set (match_operand:HI 0 "general_operand" "=g")
490 (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
494 (define_insn "fix_truncdfsi2"
495 [(set (match_operand:SI 0 "general_operand" "=g")
496 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
500 ;;- All kinds of add instructions.
502 (define_insn "adddf3"
503 [(set (match_operand:DF 0 "general_operand" "=g,g,g")
504 (plus:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
505 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
512 (define_insn "addsf3"
513 [(set (match_operand:SF 0 "general_operand" "=g,g,g")
514 (plus:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
515 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
522 /* The space-time-opcode tradeoffs for addition vary by model of VAX.
524 On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
525 but it not faster on other models.
527 "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
528 faster on a VAX 3, but some VAXes (e.g. VAX 9000) will stall if
529 a register is used in an address too soon after it is set.
530 Compromise by using movab only when it is shorter than the add
531 or the base register in the address is one of sp, ap, and fp,
532 which are not modified very often. */
535 (define_insn "addsi3"
536 [(set (match_operand:SI 0 "general_operand" "=g")
537 (plus:SI (match_operand:SI 1 "general_operand" "g")
538 (match_operand:SI 2 "general_operand" "g")))]
542 if (rtx_equal_p (operands[0], operands[1]))
544 if (operands[2] == const1_rtx)
546 if (operands[2] == constm1_rtx)
548 if (GET_CODE (operands[2]) == CONST_INT
549 && (unsigned) (- INTVAL (operands[2])) < 64)
550 return \"subl2 $%n2,%0\";
551 if (GET_CODE (operands[2]) == CONST_INT
552 && (unsigned) INTVAL (operands[2]) >= 64
553 && GET_CODE (operands[1]) == REG
554 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
555 || REGNO (operands[1]) > 11))
556 return \"movab %c2(%1),%0\";
557 return \"addl2 %2,%0\";
559 if (rtx_equal_p (operands[0], operands[2]))
560 return \"addl2 %1,%0\";
562 if (GET_CODE (operands[2]) == CONST_INT
563 && INTVAL (operands[2]) < 32767
564 && INTVAL (operands[2]) > -32768
565 && GET_CODE (operands[1]) == REG
566 && push_operand (operands[0], SImode))
567 return \"pushab %c2(%1)\";
569 if (GET_CODE (operands[2]) == CONST_INT
570 && (unsigned) (- INTVAL (operands[2])) < 64)
571 return \"subl3 $%n2,%1,%0\";
573 if (GET_CODE (operands[2]) == CONST_INT
574 && (unsigned) INTVAL (operands[2]) >= 64
575 && GET_CODE (operands[1]) == REG
576 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
577 || REGNO (operands[1]) > 11))
578 return \"movab %c2(%1),%0\";
580 /* Add this if using gcc on a VAX 3xxx:
581 if (REG_P (operands[1]) && REG_P (operands[2]))
582 return \"movab (%1)[%2],%0\";
584 return \"addl3 %1,%2,%0\";
587 (define_insn "addhi3"
588 [(set (match_operand:HI 0 "general_operand" "=g")
589 (plus:HI (match_operand:HI 1 "general_operand" "g")
590 (match_operand:HI 2 "general_operand" "g")))]
594 if (rtx_equal_p (operands[0], operands[1]))
596 if (operands[2] == const1_rtx)
598 if (operands[2] == constm1_rtx)
600 if (GET_CODE (operands[2]) == CONST_INT
601 && (unsigned) (- INTVAL (operands[2])) < 64)
602 return \"subw2 $%n2,%0\";
603 return \"addw2 %2,%0\";
605 if (rtx_equal_p (operands[0], operands[2]))
606 return \"addw2 %1,%0\";
607 if (GET_CODE (operands[2]) == CONST_INT
608 && (unsigned) (- INTVAL (operands[2])) < 64)
609 return \"subw3 $%n2,%1,%0\";
610 return \"addw3 %1,%2,%0\";
613 (define_insn "addqi3"
614 [(set (match_operand:QI 0 "general_operand" "=g")
615 (plus:QI (match_operand:QI 1 "general_operand" "g")
616 (match_operand:QI 2 "general_operand" "g")))]
620 if (rtx_equal_p (operands[0], operands[1]))
622 if (operands[2] == const1_rtx)
624 if (operands[2] == constm1_rtx)
626 if (GET_CODE (operands[2]) == CONST_INT
627 && (unsigned) (- INTVAL (operands[2])) < 64)
628 return \"subb2 $%n2,%0\";
629 return \"addb2 %2,%0\";
631 if (rtx_equal_p (operands[0], operands[2]))
632 return \"addb2 %1,%0\";
633 if (GET_CODE (operands[2]) == CONST_INT
634 && (unsigned) (- INTVAL (operands[2])) < 64)
635 return \"subb3 $%n2,%1,%0\";
636 return \"addb3 %1,%2,%0\";
639 ;; The add-with-carry (adwc) instruction only accepts two operands.
640 (define_insn "adddi3"
641 [(set (match_operand:DI 0 "general_operand" "=ro>,ro>")
642 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
643 (match_operand:DI 2 "general_operand" "Fro,F")))]
651 split_quadword_operands (operands, low, 3);
653 if (rtx_equal_p (operands[0], operands[1]))
655 if (low[2] == const0_rtx)
656 /* Should examine operand, punt if not POST_INC. */
657 pattern = \"tstl %0\", carry = 0;
658 else if (low[2] == const1_rtx)
659 pattern = \"incl %0\";
661 pattern = \"addl2 %2,%0\";
665 if (low[2] == const0_rtx)
666 pattern = \"movl %1,%0\", carry = 0;
668 pattern = \"addl3 %2,%1,%0\";
671 output_asm_insn (pattern, low);
673 /* If CARRY is 0, we don't have any carry value to worry about. */
674 return get_insn_template (CODE_FOR_addsi3, insn);
675 /* %0 = C + %1 + %2 */
676 if (!rtx_equal_p (operands[0], operands[1]))
677 output_asm_insn ((operands[1] == const0_rtx
679 : \"movl %1,%0\"), operands);
680 return \"adwc %2,%0\";
683 ;;- All kinds of subtract instructions.
685 (define_insn "subdf3"
686 [(set (match_operand:DF 0 "general_operand" "=g,g")
687 (minus:DF (match_operand:DF 1 "general_operand" "0,gF")
688 (match_operand:DF 2 "general_operand" "gF,gF")))]
694 (define_insn "subsf3"
695 [(set (match_operand:SF 0 "general_operand" "=g,g")
696 (minus:SF (match_operand:SF 1 "general_operand" "0,gF")
697 (match_operand:SF 2 "general_operand" "gF,gF")))]
703 (define_insn "subsi3"
704 [(set (match_operand:SI 0 "general_operand" "=g,g")
705 (minus:SI (match_operand:SI 1 "general_operand" "0,g")
706 (match_operand:SI 2 "general_operand" "g,g")))]
712 (define_insn "subhi3"
713 [(set (match_operand:HI 0 "general_operand" "=g,g")
714 (minus:HI (match_operand:HI 1 "general_operand" "0,g")
715 (match_operand:HI 2 "general_operand" "g,g")))]
721 (define_insn "subqi3"
722 [(set (match_operand:QI 0 "general_operand" "=g,g")
723 (minus:QI (match_operand:QI 1 "general_operand" "0,g")
724 (match_operand:QI 2 "general_operand" "g,g")))]
730 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
731 (define_insn "subdi3"
732 [(set (match_operand:DI 0 "general_operand" "=or>,or>")
733 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
734 (match_operand:DI 2 "general_operand" "For,F")))]
742 split_quadword_operands (operands, low, 3);
743 /* Subtract low parts. */
744 if (rtx_equal_p (operands[0], operands[1]))
746 if (low[2] == const0_rtx)
747 pattern = 0, carry = 0;
748 else if (low[2] == constm1_rtx)
749 pattern = \"decl %0\";
751 pattern = \"subl2 %2,%0\";
755 if (low[2] == constm1_rtx)
756 pattern = \"decl %0\";
757 else if (low[2] == const0_rtx)
758 pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0;
760 pattern = \"subl3 %2,%1,%0\";
763 output_asm_insn (pattern, low);
766 if (!rtx_equal_p (operands[0], operands[1]))
767 return \"movl %1,%0\;sbwc %2,%0\";
768 return \"sbwc %2,%0\";
769 /* %0 = %2 - %1 - C */
771 return get_insn_template (CODE_FOR_subsi3, insn);
774 ;;- Multiply instructions.
776 (define_insn "muldf3"
777 [(set (match_operand:DF 0 "general_operand" "=g,g,g")
778 (mult:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
779 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
786 (define_insn "mulsf3"
787 [(set (match_operand:SF 0 "general_operand" "=g,g,g")
788 (mult:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
789 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
796 (define_insn "mulsi3"
797 [(set (match_operand:SI 0 "general_operand" "=g,g,g")
798 (mult:SI (match_operand:SI 1 "general_operand" "0,g,g")
799 (match_operand:SI 2 "general_operand" "g,0,g")))]
806 (define_insn "mulhi3"
807 [(set (match_operand:HI 0 "general_operand" "=g,g,")
808 (mult:HI (match_operand:HI 1 "general_operand" "0,g,g")
809 (match_operand:HI 2 "general_operand" "g,0,g")))]
816 (define_insn "mulqi3"
817 [(set (match_operand:QI 0 "general_operand" "=g,g,g")
818 (mult:QI (match_operand:QI 1 "general_operand" "0,g,g")
819 (match_operand:QI 2 "general_operand" "g,0,g")))]
826 (define_insn "mulsidi3"
827 [(set (match_operand:DI 0 "general_operand" "=g")
828 (mult:DI (sign_extend:DI
829 (match_operand:SI 1 "nonimmediate_operand" "g"))
831 (match_operand:SI 2 "nonimmediate_operand" "g"))))]
836 [(set (match_operand:DI 0 "general_operand" "=g")
838 (mult:DI (sign_extend:DI
839 (match_operand:SI 1 "nonimmediate_operand" "g"))
841 (match_operand:SI 2 "nonimmediate_operand" "g")))
842 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
846 ;; 'F' constraint means type CONST_DOUBLE
848 [(set (match_operand:DI 0 "general_operand" "=g")
850 (mult:DI (sign_extend:DI
851 (match_operand:SI 1 "nonimmediate_operand" "g"))
853 (match_operand:SI 2 "nonimmediate_operand" "g")))
854 (match_operand:DI 3 "immediate_operand" "F")))]
855 "GET_CODE (operands[3]) == CONST_DOUBLE
856 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
859 if (CONST_DOUBLE_HIGH (operands[3]))
860 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
861 return \"emul %1,%2,%3,%0\";
864 ;;- Divide instructions.
866 (define_insn "divdf3"
867 [(set (match_operand:DF 0 "general_operand" "=g,g")
868 (div:DF (match_operand:DF 1 "general_operand" "0,gF")
869 (match_operand:DF 2 "general_operand" "gF,gF")))]
875 (define_insn "divsf3"
876 [(set (match_operand:SF 0 "general_operand" "=g,g")
877 (div:SF (match_operand:SF 1 "general_operand" "0,gF")
878 (match_operand:SF 2 "general_operand" "gF,gF")))]
884 (define_insn "divsi3"
885 [(set (match_operand:SI 0 "general_operand" "=g,g")
886 (div:SI (match_operand:SI 1 "general_operand" "0,g")
887 (match_operand:SI 2 "general_operand" "g,g")))]
893 (define_insn "divhi3"
894 [(set (match_operand:HI 0 "general_operand" "=g,g")
895 (div:HI (match_operand:HI 1 "general_operand" "0,g")
896 (match_operand:HI 2 "general_operand" "g,g")))]
902 (define_insn "divqi3"
903 [(set (match_operand:QI 0 "general_operand" "=g,g")
904 (div:QI (match_operand:QI 1 "general_operand" "0,g")
905 (match_operand:QI 2 "general_operand" "g,g")))]
911 ;This is left out because it is very slow;
912 ;we are better off programming around the "lack" of this insn.
913 ;(define_insn "divmoddisi4"
914 ; [(set (match_operand:SI 0 "general_operand" "=g")
915 ; (div:SI (match_operand:DI 1 "general_operand" "g")
916 ; (match_operand:SI 2 "general_operand" "g")))
917 ; (set (match_operand:SI 3 "general_operand" "=g")
918 ; (mod:SI (match_operand:DI 1 "general_operand" "g")
919 ; (match_operand:SI 2 "general_operand" "g")))]
921 ; "ediv %2,%1,%0,%3")
923 ;; Bit-and on the vax is done with a clear-bits insn.
924 (define_expand "andsi3"
925 [(set (match_operand:SI 0 "general_operand" "=g")
926 (and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
927 (match_operand:SI 2 "general_operand" "g")))]
931 rtx op1 = operands[1];
933 /* If there is a constant argument, complement that one. */
934 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
936 operands[1] = operands[2];
941 if (GET_CODE (op1) == CONST_INT)
942 operands[1] = GEN_INT (~INTVAL (op1));
944 operands[1] = expand_unop (SImode, one_cmpl_optab, op1, 0, 1);
947 (define_expand "andhi3"
948 [(set (match_operand:HI 0 "general_operand" "=g")
949 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
950 (match_operand:HI 2 "general_operand" "g")))]
954 rtx op1 = operands[1];
956 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
958 operands[1] = operands[2];
963 if (GET_CODE (op1) == CONST_INT)
964 operands[1] = GEN_INT (65535 & ~INTVAL (op1));
966 operands[1] = expand_unop (HImode, one_cmpl_optab, op1, 0, 1);
969 (define_expand "andqi3"
970 [(set (match_operand:QI 0 "general_operand" "=g")
971 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
972 (match_operand:QI 2 "general_operand" "g")))]
976 rtx op1 = operands[1];
978 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
980 operands[1] = operands[2];
985 if (GET_CODE (op1) == CONST_INT)
986 operands[1] = GEN_INT (255 & ~INTVAL (op1));
988 operands[1] = expand_unop (QImode, one_cmpl_optab, op1, 0, 1);
992 [(set (match_operand:SI 0 "general_operand" "=g,g")
993 (and:SI (not:SI (match_operand:SI 1 "general_operand" "g,g"))
994 (match_operand:SI 2 "general_operand" "0,g")))]
1001 [(set (match_operand:HI 0 "general_operand" "=g,g")
1002 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g,g"))
1003 (match_operand:HI 2 "general_operand" "0,g")))]
1010 [(set (match_operand:QI 0 "general_operand" "=g,g")
1011 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g,g"))
1012 (match_operand:QI 2 "general_operand" "0,g")))]
1018 ;; The following used to be needed because constant propagation can
1019 ;; create them starting from the bic insn patterns above. This is no
1020 ;; longer a problem. However, having these patterns allows optimization
1021 ;; opportunities in combine.c.
1024 [(set (match_operand:SI 0 "general_operand" "=g,g")
1025 (and:SI (match_operand:SI 1 "general_operand" "0,g")
1026 (match_operand:SI 2 "const_int_operand" "n,n")))]
1033 [(set (match_operand:HI 0 "general_operand" "=g,g")
1034 (and:HI (match_operand:HI 1 "general_operand" "0,g")
1035 (match_operand:HI 2 "const_int_operand" "n,n")))]
1042 [(set (match_operand:QI 0 "general_operand" "=g,g")
1043 (and:QI (match_operand:QI 1 "general_operand" "0,g")
1044 (match_operand:QI 2 "const_int_operand" "n,n")))]
1050 ;;- Bit set instructions.
1052 (define_insn "iorsi3"
1053 [(set (match_operand:SI 0 "general_operand" "=g,g,g")
1054 (ior:SI (match_operand:SI 1 "general_operand" "0,g,g")
1055 (match_operand:SI 2 "general_operand" "g,0,g")))]
1062 (define_insn "iorhi3"
1063 [(set (match_operand:HI 0 "general_operand" "=g,g,g")
1064 (ior:HI (match_operand:HI 1 "general_operand" "0,g,g")
1065 (match_operand:HI 2 "general_operand" "g,0,g")))]
1072 (define_insn "iorqi3"
1073 [(set (match_operand:QI 0 "general_operand" "=g,g,g")
1074 (ior:QI (match_operand:QI 1 "general_operand" "0,g,g")
1075 (match_operand:QI 2 "general_operand" "g,0,g")))]
1082 ;;- xor instructions.
1084 (define_insn "xorsi3"
1085 [(set (match_operand:SI 0 "general_operand" "=g,g,g")
1086 (xor:SI (match_operand:SI 1 "general_operand" "0,g,g")
1087 (match_operand:SI 2 "general_operand" "g,0,g")))]
1094 (define_insn "xorhi3"
1095 [(set (match_operand:HI 0 "general_operand" "=g,g,g")
1096 (xor:HI (match_operand:HI 1 "general_operand" "0,g,g")
1097 (match_operand:HI 2 "general_operand" "g,0,g")))]
1104 (define_insn "xorqi3"
1105 [(set (match_operand:QI 0 "general_operand" "=g,g,g")
1106 (xor:QI (match_operand:QI 1 "general_operand" "0,g,g")
1107 (match_operand:QI 2 "general_operand" "g,0,g")))]
1114 (define_insn "negdf2"
1115 [(set (match_operand:DF 0 "general_operand" "=g")
1116 (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1120 (define_insn "negsf2"
1121 [(set (match_operand:SF 0 "general_operand" "=g")
1122 (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1126 (define_insn "negsi2"
1127 [(set (match_operand:SI 0 "general_operand" "=g")
1128 (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1132 (define_insn "neghi2"
1133 [(set (match_operand:HI 0 "general_operand" "=g")
1134 (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1138 (define_insn "negqi2"
1139 [(set (match_operand:QI 0 "general_operand" "=g")
1140 (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1144 (define_insn "one_cmplsi2"
1145 [(set (match_operand:SI 0 "general_operand" "=g")
1146 (not:SI (match_operand:SI 1 "general_operand" "g")))]
1150 (define_insn "one_cmplhi2"
1151 [(set (match_operand:HI 0 "general_operand" "=g")
1152 (not:HI (match_operand:HI 1 "general_operand" "g")))]
1156 (define_insn "one_cmplqi2"
1157 [(set (match_operand:QI 0 "general_operand" "=g")
1158 (not:QI (match_operand:QI 1 "general_operand" "g")))]
1162 ;; Arithmetic right shift on the vax works by negating the shift count,
1163 ;; then emitting a right shift with the shift count negated. This means
1164 ;; that all actual shift counts in the RTL will be positive. This
1165 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1166 ;; which isn't valid.
1167 (define_expand "ashrsi3"
1168 [(set (match_operand:SI 0 "general_operand" "=g")
1169 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1170 (match_operand:QI 2 "general_operand" "g")))]
1174 if (GET_CODE (operands[2]) != CONST_INT)
1175 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1179 [(set (match_operand:SI 0 "general_operand" "=g")
1180 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1181 (match_operand:QI 2 "const_int_operand" "n")))]
1186 [(set (match_operand:SI 0 "general_operand" "=g")
1187 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1188 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1192 (define_insn "ashlsi3"
1193 [(set (match_operand:SI 0 "general_operand" "=g")
1194 (ashift:SI (match_operand:SI 1 "general_operand" "g")
1195 (match_operand:QI 2 "general_operand" "g")))]
1199 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1200 return \"addl2 %0,%0\";
1201 if (GET_CODE (operands[1]) == REG
1202 && GET_CODE (operands[2]) == CONST_INT)
1204 int i = INTVAL (operands[2]);
1206 return \"addl3 %1,%1,%0\";
1208 return \"moval 0[%1],%0\";
1210 return \"movad 0[%1],%0\";
1212 return \"ashl %2,%1,%0\";
1215 ;; Arithmetic right shift on the vax works by negating the shift count.
1216 (define_expand "ashrdi3"
1217 [(set (match_operand:DI 0 "general_operand" "=g")
1218 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1219 (match_operand:QI 2 "general_operand" "g")))]
1223 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1226 (define_insn "ashldi3"
1227 [(set (match_operand:DI 0 "general_operand" "=g")
1228 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1229 (match_operand:QI 2 "general_operand" "g")))]
1234 [(set (match_operand:DI 0 "general_operand" "=g")
1235 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1236 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1240 ;; We used to have expand_shift handle logical right shifts by using extzv,
1241 ;; but this make it very difficult to do lshrdi3. Since the VAX is the
1242 ;; only machine with this kludge, it's better to just do this with a
1243 ;; define_expand and remove that case from expand_shift.
1245 (define_expand "lshrsi3"
1247 (minus:QI (const_int 32)
1249 (set (match_operand:SI 0 "general_operand" "=g")
1250 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1252 (match_operand:SI 2 "register_operand" "g")))]
1256 operands[3] = gen_reg_rtx (QImode);
1257 operands[4] = gen_lowpart (QImode, operands[2]);
1260 ;; Rotate right on the vax works by negating the shift count.
1261 (define_expand "rotrsi3"
1262 [(set (match_operand:SI 0 "general_operand" "=g")
1263 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1264 (match_operand:QI 2 "general_operand" "g")))]
1268 if (GET_CODE (operands[2]) != CONST_INT)
1269 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1272 (define_insn "rotlsi3"
1273 [(set (match_operand:SI 0 "general_operand" "=g")
1274 (rotate:SI (match_operand:SI 1 "general_operand" "g")
1275 (match_operand:QI 2 "general_operand" "g")))]
1280 [(set (match_operand:SI 0 "general_operand" "=g")
1281 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1282 (match_operand:QI 2 "const_int_operand" "n")))]
1287 [(set (match_operand:SI 0 "general_operand" "=g")
1288 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1289 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1293 ;This insn is probably slower than a multiply and an add.
1295 ; [(set (match_operand:SI 0 "general_operand" "=g")
1296 ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1297 ; (match_operand:SI 2 "general_operand" "g"))
1298 ; (match_operand:SI 3 "general_operand" "g")))]
1300 ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1302 ;; Special cases of bit-field insns which we should
1303 ;; recognize in preference to the general case.
1304 ;; These handle aligned 8-bit and 16-bit fields,
1305 ;; which can usually be done with move instructions.
1308 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
1309 (match_operand:QI 1 "const_int_operand" "n")
1310 (match_operand:SI 2 "const_int_operand" "n"))
1311 (match_operand:SI 3 "general_operand" "g"))]
1312 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1313 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1314 && (GET_CODE (operands[0]) == REG
1315 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1318 if (REG_P (operands[0]))
1320 if (INTVAL (operands[2]) != 0)
1321 return \"insv %3,%2,%1,%0\";
1325 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
1328 if (INTVAL (operands[1]) == 8)
1329 return \"movb %3,%0\";
1330 return \"movw %3,%0\";
1334 [(set (match_operand:SI 0 "general_operand" "=&g")
1335 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1336 (match_operand:QI 2 "const_int_operand" "n")
1337 (match_operand:SI 3 "const_int_operand" "n")))]
1338 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1339 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1340 && (GET_CODE (operands[1]) == REG
1341 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1344 if (REG_P (operands[1]))
1346 if (INTVAL (operands[3]) != 0)
1347 return \"extzv %3,%2,%1,%0\";
1351 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1353 if (INTVAL (operands[2]) == 8)
1354 return \"movzbl %1,%0\";
1355 return \"movzwl %1,%0\";
1359 [(set (match_operand:SI 0 "general_operand" "=g")
1360 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1361 (match_operand:QI 2 "const_int_operand" "n")
1362 (match_operand:SI 3 "const_int_operand" "n")))]
1363 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1364 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1365 && (GET_CODE (operands[1]) == REG
1366 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1369 if (REG_P (operands[1]))
1371 if (INTVAL (operands[3]) != 0)
1372 return \"extv %3,%2,%1,%0\";
1376 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1378 if (INTVAL (operands[2]) == 8)
1379 return \"cvtbl %1,%0\";
1380 return \"cvtwl %1,%0\";
1383 ;; Register-only SImode cases of bit-field insns.
1388 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1389 (match_operand:QI 1 "general_operand" "g")
1390 (match_operand:SI 2 "general_operand" "g"))
1391 (match_operand:SI 3 "general_operand" "g")))]
1398 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1399 (match_operand:QI 1 "general_operand" "g")
1400 (match_operand:SI 2 "general_operand" "g"))
1401 (match_operand:SI 3 "general_operand" "g")))]
1403 "cmpzv %2,%1,%0,%3")
1405 ;; When the field position and size are constant and the destination
1406 ;; is a register, extv and extzv are much slower than a rotate followed
1407 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v
1408 ;; anyway, we can't allow immediate values for the primary source operand.
1411 [(set (match_operand:SI 0 "general_operand" "=g")
1412 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1413 (match_operand:QI 2 "general_operand" "g")
1414 (match_operand:SI 3 "general_operand" "g")))]
1418 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1419 || GET_CODE (operands[0]) != REG
1420 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
1421 return \"extv %3,%2,%1,%0\";
1422 if (INTVAL (operands[2]) == 8)
1423 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1424 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1428 [(set (match_operand:SI 0 "general_operand" "=g")
1429 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1430 (match_operand:QI 2 "general_operand" "g")
1431 (match_operand:SI 3 "general_operand" "g")))]
1435 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1436 || GET_CODE (operands[0]) != REG)
1437 return \"extzv %3,%2,%1,%0\";
1438 if (INTVAL (operands[2]) == 8)
1439 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1440 if (INTVAL (operands[2]) == 16)
1441 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1442 if (INTVAL (operands[3]) & 31)
1443 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1444 if (rtx_equal_p (operands[0], operands[1]))
1445 return \"bicl2 %M2,%0\";
1446 return \"bicl3 %M2,%1,%0\";
1449 ;; Non-register cases.
1450 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1451 ;; don't match these (and therefore match the cases above instead).
1456 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
1457 (match_operand:QI 1 "general_operand" "g")
1458 (match_operand:SI 2 "general_operand" "g"))
1459 (match_operand:SI 3 "general_operand" "g")))]
1466 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1467 (match_operand:QI 1 "general_operand" "g")
1468 (match_operand:SI 2 "general_operand" "g"))
1469 (match_operand:SI 3 "general_operand" "g")))]
1471 "cmpzv %2,%1,%0,%3")
1474 [(set (match_operand:SI 0 "general_operand" "=g")
1475 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
1476 (match_operand:QI 2 "general_operand" "g")
1477 (match_operand:SI 3 "general_operand" "g")))]
1481 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1482 || GET_CODE (operands[3]) != CONST_INT
1483 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
1484 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1485 || side_effects_p (operands[1])
1486 || (GET_CODE (operands[1]) == MEM
1487 && mode_dependent_address_p (XEXP (operands[1], 0))))
1488 return \"extv %3,%2,%1,%0\";
1489 if (INTVAL (operands[2]) == 8)
1490 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1491 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1494 (define_expand "extzv"
1495 [(set (match_operand:SI 0 "general_operand" "")
1496 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
1497 (match_operand:QI 2 "general_operand" "")
1498 (match_operand:SI 3 "general_operand" "")))]
1503 [(set (match_operand:SI 0 "general_operand" "=g")
1504 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
1505 (match_operand:QI 2 "general_operand" "g")
1506 (match_operand:SI 3 "general_operand" "g")))]
1510 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1511 || GET_CODE (operands[3]) != CONST_INT
1512 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1513 || side_effects_p (operands[1])
1514 || (GET_CODE (operands[1]) == MEM
1515 && mode_dependent_address_p (XEXP (operands[1], 0))))
1516 return \"extzv %3,%2,%1,%0\";
1517 if (INTVAL (operands[2]) == 8)
1518 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1519 if (INTVAL (operands[2]) == 16)
1520 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1521 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1524 (define_expand "insv"
1525 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
1526 (match_operand:QI 1 "general_operand" "")
1527 (match_operand:SI 2 "general_operand" ""))
1528 (match_operand:SI 3 "general_operand" ""))]
1533 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
1534 (match_operand:QI 1 "general_operand" "g")
1535 (match_operand:SI 2 "general_operand" "g"))
1536 (match_operand:SI 3 "general_operand" "g"))]
1541 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1542 (match_operand:QI 1 "general_operand" "g")
1543 (match_operand:SI 2 "general_operand" "g"))
1544 (match_operand:SI 3 "general_operand" "g"))]
1550 (label_ref (match_operand 0 "" "")))]
1556 (if_then_else (eq (cc0)
1558 (label_ref (match_operand 0 "" ""))
1565 (if_then_else (ne (cc0)
1567 (label_ref (match_operand 0 "" ""))
1574 (if_then_else (gt (cc0)
1576 (label_ref (match_operand 0 "" ""))
1583 (if_then_else (gtu (cc0)
1585 (label_ref (match_operand 0 "" ""))
1592 (if_then_else (lt (cc0)
1594 (label_ref (match_operand 0 "" ""))
1601 (if_then_else (ltu (cc0)
1603 (label_ref (match_operand 0 "" ""))
1610 (if_then_else (ge (cc0)
1612 (label_ref (match_operand 0 "" ""))
1619 (if_then_else (geu (cc0)
1621 (label_ref (match_operand 0 "" ""))
1628 (if_then_else (le (cc0)
1630 (label_ref (match_operand 0 "" ""))
1637 (if_then_else (leu (cc0)
1639 (label_ref (match_operand 0 "" ""))
1644 ;; Recognize reversed jumps.
1647 (if_then_else (match_operator 0 "comparison_operator"
1651 (label_ref (match_operand 1 "" ""))))]
1653 "j%C0 %l1") ; %C0 negates condition
1655 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
1656 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
1657 ;; memory, we use QImode in the insn. So we can't use those instructions
1658 ;; for mode-dependent addresses.
1663 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1665 (match_operand:SI 1 "general_operand" "I,g"))
1667 (label_ref (match_operand 2 "" ""))
1677 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1679 (match_operand:SI 1 "general_operand" "I,g"))
1681 (label_ref (match_operand 2 "" ""))
1691 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1693 (match_operand:SI 1 "general_operand" "I,g"))
1695 (label_ref (match_operand 2 "" ""))
1705 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1707 (match_operand:SI 1 "general_operand" "I,g"))
1709 (label_ref (match_operand 2 "" ""))
1716 ;; Subtract-and-jump and Add-and-jump insns.
1717 ;; These are not used when output is for the Unix assembler
1718 ;; because it does not know how to modify them to reach far.
1720 ;; Normal sob insns.
1725 (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1728 (label_ref (match_operand 1 "" ""))
1731 (plus:SI (match_dup 0)
1739 (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
1742 (label_ref (match_operand 1 "" ""))
1745 (plus:SI (match_dup 0)
1750 ;; Normal aob insns. Define a version for when operands[1] is a constant.
1754 (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1756 (match_operand:SI 1 "general_operand" "g"))
1757 (label_ref (match_operand 2 "" ""))
1760 (plus:SI (match_dup 0)
1763 "jaoblss %1,%0,%l2")
1768 (lt (match_operand:SI 0 "general_operand" "+g")
1769 (match_operand:SI 1 "general_operand" "g"))
1770 (label_ref (match_operand 2 "" ""))
1773 (plus:SI (match_dup 0)
1775 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1776 "jaoblss %P1,%0,%l2")
1781 (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
1783 (match_operand:SI 1 "general_operand" "g"))
1784 (label_ref (match_operand 2 "" ""))
1787 (plus:SI (match_dup 0)
1790 "jaobleq %1,%0,%l2")
1795 (le (match_operand:SI 0 "general_operand" "+g")
1796 (match_operand:SI 1 "general_operand" "g"))
1797 (label_ref (match_operand 2 "" ""))
1800 (plus:SI (match_dup 0)
1802 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1803 "jaobleq %P1,%0,%l2")
1805 ;; Something like a sob insn, but compares against -1.
1806 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1811 (ne (match_operand:SI 0 "general_operand" "+g")
1813 (label_ref (match_operand 1 "" ""))
1816 (plus:SI (match_dup 0)
1819 "decl %0\;jgequ %l1")
1821 ;; Note that operand 1 is total size of args, in bytes,
1822 ;; and what the call insn wants is the number of words.
1823 ;; It is used in the call instruction as a byte, but in the addl2 as
1824 ;; a word. Since the only time we actually use it in the call instruction
1825 ;; is when it is a constant, SImode (for addl2) is the proper mode.
1826 (define_insn "call_pop"
1827 [(call (match_operand:QI 0 "memory_operand" "m")
1828 (match_operand:SI 1 "const_int_operand" "n"))
1829 (set (reg:SI 14) (plus:SI (reg:SI 14)
1830 (match_operand:SI 3 "immediate_operand" "i")))]
1833 if (INTVAL (operands[1]) > 255 * 4)
1834 /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1835 return \"calls $0,%0\;addl2 %1,sp\";
1836 operands[1] = GEN_INT ((INTVAL (operands[1]) + 3)/ 4);
1837 return \"calls %1,%0\";
1840 (define_insn "call_value_pop"
1841 [(set (match_operand 0 "" "=g")
1842 (call (match_operand:QI 1 "memory_operand" "m")
1843 (match_operand:SI 2 "const_int_operand" "n")))
1844 (set (reg:SI 14) (plus:SI (reg:SI 14)
1845 (match_operand:SI 4 "immediate_operand" "i")))]
1848 if (INTVAL (operands[2]) > 255 * 4)
1849 /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1850 return \"calls $0,%1\;addl2 %2,sp\";
1851 operands[2] = GEN_INT ((INTVAL (operands[2]) + 3)/ 4);
1852 return \"calls %2,%1\";
1855 ;; Define another set of these for the case of functions with no
1856 ;; operands. In that case, combine may simplify the adjustment of sp.
1858 [(call (match_operand:QI 0 "memory_operand" "m")
1859 (match_operand:SI 1 "const_int_operand" "n"))
1860 (set (reg:SI 14) (reg:SI 14))]
1863 if (INTVAL (operands[1]) > 255 * 4)
1864 /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1865 return \"calls $0,%0\;addl2 %1,sp\";
1866 operands[1] = GEN_INT ((INTVAL (operands[1]) + 3)/ 4);
1867 return \"calls %1,%0\";
1871 [(set (match_operand 0 "" "=g")
1872 (call (match_operand:QI 1 "memory_operand" "m")
1873 (match_operand:SI 2 "const_int_operand" "n")))
1874 (set (reg:SI 14) (reg:SI 14))]
1877 if (INTVAL (operands[2]) > 255 * 4)
1878 /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1879 return \"calls $0,%1\;addl2 %2,sp\";
1880 operands[2] = GEN_INT ((INTVAL (operands[2]) + 3)/ 4);
1881 return \"calls %2,%1\";
1884 ;; Call subroutine returning any type.
1886 (define_expand "untyped_call"
1887 [(parallel [(call (match_operand 0 "" "")
1889 (match_operand 1 "" "")
1890 (match_operand 2 "" "")])]
1896 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1898 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1900 rtx set = XVECEXP (operands[2], 0, i);
1901 emit_move_insn (SET_DEST (set), SET_SRC (set));
1904 /* The optimizer does not know that the call sets the function value
1905 registers we stored in the result block. We avoid problems by
1906 claiming that all hard registers are used and clobbered at this
1908 emit_insn (gen_blockage ());
1913 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1914 ;; all of memory. This blocks insns from being moved across this point.
1916 (define_insn "blockage"
1917 [(unspec_volatile [(const_int 0)] 0)]
1921 (define_insn "return"
1931 ;; This had a wider constraint once, and it had trouble.
1932 ;; If you are tempted to try `g', please don't--it's not worth
1933 ;; the risk we will reopen the same bug.
1934 (define_insn "indirect_jump"
1935 [(set (pc) (match_operand:SI 0 "general_operand" "r"))]
1939 ;; This is here to accept 5 arguments (as passed by expand_end_case)
1940 ;; and pass the first 4 along to the casesi1 pattern that really does the work.
1941 (define_expand "casesi"
1943 (if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
1944 (match_operand:SI 1 "general_operand" "g"))
1945 (match_operand:SI 2 "general_operand" "g"))
1946 (plus:SI (sign_extend:SI
1949 (mult:SI (minus:SI (match_dup 0)
1952 (label_ref:SI (match_operand 3 "" "")))
1954 (match_operand 4 "" "")]
1957 emit_insn (gen_casesi1 (operands[0], operands[1], operands[2], operands[3]));
1961 (define_insn "casesi1"
1963 (if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
1964 (match_operand:SI 1 "general_operand" "g"))
1965 (match_operand:SI 2 "general_operand" "g"))
1966 (plus:SI (sign_extend:SI
1969 (mult:SI (minus:SI (match_dup 0)
1972 (label_ref:SI (match_operand 3 "" "")))
1977 ;; This used to arise from the preceding by simplification
1978 ;; if operand 1 is zero. Perhaps it is no longer necessary.
1981 (if_then_else (leu (match_operand:SI 0 "general_operand" "g")
1982 (match_operand:SI 1 "general_operand" "g"))
1983 (plus:SI (sign_extend:SI
1986 (mult:SI (minus:SI (match_dup 0)
1989 (label_ref:SI (match_operand 3 "" "")))
1994 ;;- load or push effective address
1995 ;; These come after the move and add/sub patterns
1996 ;; because we don't want pushl $1 turned into pushad 1.
1997 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1999 ;; It does not work to use constraints to distinguish pushes from moves,
2000 ;; because < matches any autodecrement, not just a push.
2003 [(set (match_operand:SI 0 "general_operand" "=g")
2004 (match_operand:QI 1 "address_operand" "p"))]
2008 if (push_operand (operands[0], SImode))
2009 return \"pushab %a1\";
2011 return \"movab %a1,%0\";
2015 [(set (match_operand:SI 0 "general_operand" "=g")
2016 (match_operand:HI 1 "address_operand" "p"))]
2020 if (push_operand (operands[0], SImode))
2021 return \"pushaw %a1\";
2023 return \"movaw %a1,%0\";
2027 [(set (match_operand:SI 0 "general_operand" "=g")
2028 (match_operand:SI 1 "address_operand" "p"))]
2032 if (push_operand (operands[0], SImode))
2033 return \"pushal %a1\";
2035 return \"moval %a1,%0\";
2039 [(set (match_operand:SI 0 "general_operand" "=g")
2040 (match_operand:DI 1 "address_operand" "p"))]
2044 if (push_operand (operands[0], SImode))
2045 return \"pushaq %a1\";
2047 return \"movaq %a1,%0\";
2051 [(set (match_operand:SI 0 "general_operand" "=g")
2052 (match_operand:SF 1 "address_operand" "p"))]
2056 if (push_operand (operands[0], SImode))
2057 return \"pushaf %a1\";
2059 return \"movaf %a1,%0\";
2063 [(set (match_operand:SI 0 "general_operand" "=g")
2064 (match_operand:DF 1 "address_operand" "p"))]
2068 if (push_operand (operands[0], SImode))
2069 return \"pushad %a1\";
2071 return \"movad %a1,%0\";
2074 ;; These used to be peepholes, but it is more straightforward to do them
2075 ;; as single insns. However, we must force the output to be a register
2076 ;; if it is not an offsettable address so that we know that we can assign
2079 ;; If we had a good way of evaluating the relative costs, these could be
2080 ;; machine-independent.
2082 ;; Optimize extzv ...,z; andl2 ...,z
2083 ;; or ashl ...,z; andl2 ...,z
2084 ;; with other operands constant. This is what the combiner converts the
2085 ;; above sequences to before attempting to recognize the new insn.
2088 [(set (match_operand:SI 0 "general_operand" "=ro")
2089 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
2090 (match_operand:QI 2 "const_int_operand" "n"))
2091 (match_operand:SI 3 "const_int_operand" "n")))]
2092 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
2095 unsigned long mask1 = INTVAL (operands[3]);
2096 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
2098 if ((mask1 & mask2) != mask1)
2099 operands[3] = GEN_INT (mask1 & mask2);
2101 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
2104 ;; left-shift and mask
2105 ;; The only case where `ashl' is better is if the mask only turns off
2106 ;; bits that the ashl would anyways, in which case it should have been
2110 [(set (match_operand:SI 0 "general_operand" "=ro")
2111 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
2112 (match_operand:QI 2 "const_int_operand" "n"))
2113 (match_operand:SI 3 "const_int_operand" "n")))]
2118 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
2119 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";