1 ;;- Machine description for GNU compiler -- System/370 version.
2 ;; Copyright (C) 1989, 1993, 1994, 1995, 1997, 1998, 1999, 2000
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Jan Stein (jan@cd.chalmers.se).
5 ;; Modified for OS/390 LanguageEnvironment C by Dave Pitts (dpitts@cozx.com)
6 ;; Lots of Bug Fixes & Enhancements by Linas Vepstas (linas@linas.org)
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; =======================================================================
26 ;; Condition codes for some of the instructions (in particular, for
27 ;; add, sub, shift, abs, etc. are handled with the cpp macro NOTICE_UPDATE_CC
29 ;; Special constraints for 370 machine description:
31 ;; a -- Any address register from 1 to 15.
32 ;; d -- Any register from 0 to 15.
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; R -- a valid S operand in an RS, SI or SS instruction, or register
37 ;; S -- a valid S operand in an RS, SI or SS instruction
40 ;; When defining an instruction, e.g. the movsi pattern:
43 ;; [(set (match_operand:SI 0 "r_or_s_operand" "=dm,d,dm")
44 ;; (match_operand:SI 1 "r_or_s_operand" "diR,dim,*fF"))]
46 ;; The "r_or_s_operand" predicate is used to recognize the instruction;
47 ;; however, it is not further used to enforce a constraint at later stages.
48 ;; Thus, for example, although "r_or_s_operand" bars operands of the form
49 ;; base+index+displacement, such operands can none-the-less show up during
50 ;; post-instruction-recog processing: thus, for example, garbage like
51 ;; MVC 152(4,r13),0(r5,r13) might be generated if both op0 and op1 are
52 ;; mem operands. To avoid this, use the S constraint.
55 ;; Special formats used for outputting 370 instructions.
57 ;; %B -- Print a constant byte integer.
58 ;; %H -- Print a signed 16-bit constant.
59 ;; %K -- Print a signed 16-bit constant signed-extended to 32-bits.
60 ;; %L -- Print least significant word of a CONST_DOUBLE.
61 ;; %M -- Print most significant word of a CONST_DOUBLE.
62 ;; %N -- Print next register (second word of a DImode reg).
63 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
64 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
65 ;; %X -- Print a constant byte integer in hex.
66 ;; %W -- Print a signed 32-bit int sign-extended to 64-bits.
68 ;; We have a special constraint for pattern matching.
70 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
72 ;; r_or_s_operand -- Matches a register or a valid S operand in a RS, SI
73 ;; or SS type instruction or a register
75 ;; For MVS C/370 we use the following stack locations for:
77 ;; 136 - internal function result buffer
78 ;; 140 - numeric conversion buffer
79 ;; 144 - pointer to internal function result buffer
80 ;; 148 - start of automatic variables and function arguments
82 ;; To support programs larger than a page, 4096 bytes, PAGE_REGISTER points
83 ;; to a page origin table, all internal labels are generated to reload the
84 ;; BASE_REGISTER knowing what page it is on and all branch instructions go
85 ;; directly to the target if it is known that the target is on the current
86 ;; page (essentially backward references). All forward references and off
87 ;; page references are handled by loading the address of target into a
88 ;; register and branching indirectly.
90 ;; Some *di patterns have been commented out per advice from RMS, as gcc
91 ;; will generate the right things to do.
93 ;; See the note in i370.h about register 14, clobbering it, and optimization.
94 ;; Basically, using clobber in egcs-1.1.1 will ruin ability to optimize around
95 ;; branches, so don't do it.
97 ;; We use the "length" attirbute to store the max possible code size of an
98 ;; insn. We use this length to estimate the length of forward branches, to
99 ;; determine if they're on page or off.
101 (define_attr "length" "" (const_int 0))
104 ;;- Test instructions.
108 ; tstdi instruction pattern(s).
113 (match_operand:DI 0 "register_operand" "d"))]
118 mvs_check_page (0, 4, 0);
119 return \"SRDA %0,0\";
121 [(set_attr "length" "4")]
125 ; tstsi instruction pattern(s).
130 (match_operand:SI 0 "register_operand" "d"))]
135 mvs_check_page (0, 2, 0);
136 return \"LTR %0,%0\";
138 [(set_attr "length" "2")]
142 ; tsthi instruction pattern(s).
147 (match_operand:HI 0 "register_operand" "d"))]
152 mvs_check_page (0, 4, 2);
153 return \"CH %0,=H'0'\";
155 [(set_attr "length" "4")]
159 ; tstqi instruction pattern(s).
164 (match_operand:QI 0 "r_or_s_operand" "dm"))]
165 "unsigned_jump_follows_p (insn)"
169 if (REG_P (operands[0]))
171 /* an unsigned compare to zero is always zero/not-zero... */
172 mvs_check_page (0, 4, 4);
173 return \"N %0,=XL4'000000FF'\";
175 mvs_check_page (0, 4, 0);
178 [(set_attr "length" "4")]
183 (match_operand:QI 0 "register_operand" "d"))]
188 if (unsigned_jump_follows_p (insn))
190 /* an unsigned compare to zero is always zero/not-zero... */
191 mvs_check_page (0, 4, 4);
192 return \"N %0,=XL4'000000FF'\";
194 mvs_check_page (0, 8, 0);
195 return \"SLL %0,24\;SRA %0,24\";
197 [(set_attr "length" "8")]
201 ; tstdf instruction pattern(s).
206 (match_operand:DF 0 "general_operand" "f"))]
211 mvs_check_page (0, 2, 0);
212 return \"LTDR %0,%0\";
214 [(set_attr "length" "2")]
218 ; tstsf instruction pattern(s).
223 (match_operand:SF 0 "general_operand" "f"))]
228 mvs_check_page (0, 2, 0);
229 return \"LTER %0,%0\";
231 [(set_attr "length" "2")]
235 ;;- Compare instructions.
239 ; cmpdi instruction pattern(s).
242 ;(define_insn "cmpdi"
244 ; (compare (match_operand:DI 0 "register_operand" "d")
245 ; (match_operand:DI 1 "general_operand" "")))]
249 ; check_label_emit ();
250 ; if (REG_P (operands[1]))
252 ; mvs_check_page (0, 8, 0);
253 ; if (unsigned_jump_follows_p (insn))
254 ; return \"CLR %0,%1\;BNE *+6\;CLR %N0,%N1\";
255 ; return \"CR %0,%1\;BNE *+6\;CLR %N0,%N1\";
257 ; mvs_check_page (0, 12, 0);
258 ; if (unsigned_jump_follows_p (insn))
259 ; return \"CL %0,%M1\;BNE *+8\;CL %N0,%L1\";
260 ; return \"C %0,%M1\;BNE *+8\;CL %N0,%L1\";
264 ; cmpsi instruction pattern(s).
269 (compare (match_operand:SI 0 "register_operand" "d")
270 (match_operand:SI 1 "general_operand" "md")))]
275 if (REG_P (operands[1]))
277 mvs_check_page (0, 2, 0);
278 if (unsigned_jump_follows_p (insn))
279 return \"CLR %0,%1\";
282 if (GET_CODE (operands[1]) == CONST_INT)
284 mvs_check_page (0, 4, 4);
285 if (unsigned_jump_follows_p (insn))
286 return \"CL %0,=F'%c1'\";
287 return \"C %0,=F'%c1'\";
289 mvs_check_page (0, 4, 0);
290 if (unsigned_jump_follows_p (insn))
294 [(set_attr "length" "4")]
298 ; cmphi instruction pattern(s).
301 ; depricate constraint d because it takes multiple instructions
302 ; and a memeory access ...
305 (compare (match_operand:HI 0 "register_operand" "d")
306 (match_operand:HI 1 "general_operand" "???dim")))]
311 if (REG_P (operands[1]))
313 mvs_check_page (0, 8, 0);
314 if (unsigned_jump_follows_p (insn))
315 return \"STH %1,140(,13)\;CLM %0,3,140(13)\";
316 return \"STH %1,140(,13)\;CH %0,140(,13)\";
318 if (GET_CODE (operands[1]) == CONST_INT)
320 mvs_check_page (0, 4, 0);
321 return \"CH %0,%H1\";
323 mvs_check_page (0, 4, 0);
326 [(set_attr "length" "8")]
330 ; cmpqi instruction pattern(s).
335 (compare (match_operand:QI 0 "r_or_s_operand" "dS")
336 (match_operand:QI 1 "r_or_s_operand" "diS")))]
337 "unsigned_jump_follows_p (insn)"
341 if (REG_P (operands[0]))
343 if (REG_P (operands[1]))
345 mvs_check_page (0, 8, 0);
346 return \"STC %1,140(,13)\;CLM %0,1,140(13)\";
348 if (GET_CODE (operands[1]) == CONST_INT)
350 mvs_check_page (0, 4, 1);
351 return \"CLM %0,1,=XL1'%X1'\";
353 mvs_check_page (0, 4, 0);
354 return \"CLM %0,1,%1\";
356 else if (GET_CODE (operands[0]) == CONST_INT)
358 cc_status.flags |= CC_REVERSED;
359 if (REG_P (operands[1]))
361 mvs_check_page (0, 4, 1);
362 return \"CLM %1,1,=XL1'%X0'\";
364 mvs_check_page (0, 4, 0);
365 return \"CLI %1,%B0\";
367 if (GET_CODE (operands[1]) == CONST_INT)
369 mvs_check_page (0, 4, 0);
370 return \"CLI %0,%B1\";
372 if (GET_CODE (operands[1]) == MEM)
374 mvs_check_page (0, 6, 0);
375 return \"CLC %O0(1,%R0),%1\";
377 cc_status.flags |= CC_REVERSED;
378 mvs_check_page (0, 4, 0);
379 return \"CLM %1,1,%0\";
381 [(set_attr "length" "8")]
386 (compare (match_operand:QI 0 "register_operand" "d")
387 (match_operand:QI 1 "general_operand" "di")))]
392 if (unsigned_jump_follows_p (insn))
394 if (GET_CODE (operands[1]) == CONST_INT)
396 mvs_check_page (0, 4, 1);
397 return \"CLM %0,1,=XL1'%X1'\";
399 if (!(REG_P (operands[1])))
401 mvs_check_page (0, 4, 0);
402 return \"CLM %0,1,%1\";
404 mvs_check_page (0, 8, 0);
405 return \"STC %1,140(,13)\;CLM %0,1,140(13)\";
407 if (REG_P (operands[1]))
409 mvs_check_page (0, 18, 0);
410 return \"SLL %0,24\;SRA %0,24\;SLL %1,24\;SRA %1,24\;CR %0,%1\";
412 mvs_check_page (0, 12, 0);
413 return \"SLL %0,24\;SRA %0,24\;C %0,%1\";
415 [(set_attr "length" "18")]
419 ; cmpdf instruction pattern(s).
424 (compare (match_operand:DF 0 "general_operand" "f,mF")
425 (match_operand:DF 1 "general_operand" "fmF,f")))]
430 if (FP_REG_P (operands[0]))
432 if (FP_REG_P (operands[1]))
434 mvs_check_page (0, 2, 0);
435 return \"CDR %0,%1\";
437 mvs_check_page (0, 4, 0);
440 cc_status.flags |= CC_REVERSED;
441 mvs_check_page (0, 4, 0);
444 [(set_attr "length" "4")]
448 ; cmpsf instruction pattern(s).
453 (compare (match_operand:SF 0 "general_operand" "f,mF")
454 (match_operand:SF 1 "general_operand" "fmF,f")))]
459 if (FP_REG_P (operands[0]))
461 if (FP_REG_P (operands[1]))
463 mvs_check_page (0, 2, 0);
464 return \"CER %0,%1\";
466 mvs_check_page (0, 4, 0);
469 cc_status.flags |= CC_REVERSED;
470 mvs_check_page (0, 4, 0);
473 [(set_attr "length" "4")]
477 ; cmpstrsi instruction pattern(s).
480 (define_expand "cmpstrsi"
481 [(set (match_operand:SI 0 "general_operand" "")
482 (compare (match_operand:BLK 1 "general_operand" "")
483 (match_operand:BLK 2 "general_operand" "")))
484 (use (match_operand:SI 3 "general_operand" ""))
485 (use (match_operand:SI 4 "" ""))]
491 op1 = XEXP (operands[1], 0);
492 if (GET_CODE (op1) == REG
493 || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG
494 && GET_CODE (XEXP (op1, 1)) == CONST_INT
495 && (unsigned) INTVAL (XEXP (op1, 1)) < 4096))
501 op1 = gen_rtx_MEM (BLKmode, copy_to_mode_reg (SImode, op1));
504 op2 = XEXP (operands[2], 0);
505 if (GET_CODE (op2) == REG
506 || (GET_CODE (op2) == PLUS && GET_CODE (XEXP (op2, 0)) == REG
507 && GET_CODE (XEXP (op2, 1)) == CONST_INT
508 && (unsigned) INTVAL (XEXP (op2, 1)) < 4096))
514 op2 = gen_rtx_MEM (BLKmode, copy_to_mode_reg (SImode, op2));
517 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
519 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
520 gen_rtx_SET (VOIDmode, operands[0],
521 gen_rtx_COMPARE (VOIDmode, op1, op2)),
522 gen_rtx_USE (VOIDmode, operands[3]))));
526 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
527 rtx reg1 = gen_reg_rtx (DImode);
528 rtx reg2 = gen_reg_rtx (DImode);
529 rtx result = operands[0];
530 rtx mem1 = operands[1];
531 rtx mem2 = operands[2];
532 rtx len = operands[3];
533 if (!CONSTANT_P (len))
534 len = force_reg (SImode, len);
536 /* Load up the address+length pairs. */
537 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
538 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0),
539 force_operand (XEXP (mem1, 0), NULL_RTX));
540 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 1), len);
542 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2));
543 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0),
544 force_operand (XEXP (mem2, 0), NULL_RTX));
545 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 1), len);
548 emit_insn (gen_cmpstrsi_1 (result, reg1, reg2));
553 ; Compare a block that is less than 256 bytes in length.
556 [(set (match_operand:SI 0 "register_operand" "=d")
557 (compare (match_operand:BLK 1 "s_operand" "m")
558 (match_operand:BLK 2 "s_operand" "m")))
559 (use (match_operand:QI 3 "immediate_operand" "I"))]
560 "((unsigned) INTVAL (operands[3]) < 256)"
564 mvs_check_page (0, 22, 0);
565 return \"LA %0,%1\;CLC %O1(%c3,%R1),%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\";
567 [(set_attr "length" "22")]
570 ; Compare a block that is larger than 255 bytes in length.
572 (define_insn "cmpstrsi_1"
573 [(set (match_operand:SI 0 "register_operand" "+d")
575 (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "+d") 0))
576 (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "+d") 0))))
579 (clobber (match_dup 1))
580 (clobber (match_dup 2))]
585 mvs_check_page (0, 18, 0);
586 return \"LA %0,1(0,0)\;CLCL %1,%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\";
588 [(set_attr "length" "18")]
592 ;;- Move instructions.
596 ; movdi instruction pattern(s).
600 ;; [(set (match_operand:DI 0 "r_or_s_operand" "=dm")
601 ;; (match_operand:DI 1 "r_or_s_operand" "dim*fF"))]
602 [(set (match_operand:DI 0 "r_or_s_operand" "=dS,m")
603 (match_operand:DI 1 "r_or_s_operand" "diS*fF,d*fF"))]
605 "TARGET_CHAR_INSTRUCTIONS"
609 if (REG_P (operands[0]))
611 if (FP_REG_P (operands[1]))
613 mvs_check_page (0, 8, 0);
614 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
616 if (REG_P (operands[1]))
618 mvs_check_page (0, 4, 0);
619 return \"LR %0,%1\;LR %N0,%N1\";
621 if (operands[1] == const0_rtx)
624 mvs_check_page (0, 4, 0);
625 return \"SLR %0,%0\;SLR %N0,%N0\";
627 if (GET_CODE (operands[1]) == CONST_INT
628 && (unsigned) INTVAL (operands[1]) < 4096)
631 mvs_check_page (0, 6, 0);
632 return \"SLR %0,%0\;LA %N0,%c1(0,0)\";
634 if (GET_CODE (operands[1]) == CONST_INT)
636 CC_STATUS_SET (operands[0], operands[1]);
637 mvs_check_page (0, 8, 0);
638 return \"L %0,%1\;SRDA %0,32\";
640 mvs_check_page (0, 4, 0);
641 return \"LM %0,%N0,%1\";
643 else if (FP_REG_P (operands[1]))
645 mvs_check_page (0, 4, 0);
646 return \"STD %1,%0\";
648 else if (REG_P (operands[1]))
650 mvs_check_page (0, 4, 0);
651 return \"STM %1,%N1,%0\";
653 mvs_check_page (0, 6, 0);
654 return \"MVC %O0(8,%R0),%W1\";
656 [(set_attr "length" "8")]
660 ;; [(set (match_operand:DI 0 "general_operand" "=d,dm")
661 ;; (match_operand:DI 1 "general_operand" "dimF,*fd"))]
662 [(set (match_operand:DI 0 "general_operand" "=d,dm")
663 (match_operand:DI 1 "r_or_s_operand" "diSF,*fd"))]
668 if (REG_P (operands[0]))
670 if (FP_REG_P (operands[1]))
672 mvs_check_page (0, 8, 0);
673 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
675 if (REG_P (operands[1]))
677 mvs_check_page (0, 4, 0);
678 return \"LR %0,%1\;LR %N0,%N1\";
680 if (operands[1] == const0_rtx)
683 mvs_check_page (0, 4, 0);
684 return \"SLR %0,%0\;SLR %N0,%N0\";
686 if (GET_CODE (operands[1]) == CONST_INT
687 && (unsigned) INTVAL (operands[1]) < 4096)
690 mvs_check_page (0, 6, 0);
691 return \"SLR %0,%0\;LA %N0,%c1(0,0)\";
693 if (GET_CODE (operands[1]) == CONST_INT)
695 CC_STATUS_SET (operands[0], operands[1]);
696 mvs_check_page (0, 8, 0);
697 return \"L %0,%1\;SRDA %0,32\";
699 mvs_check_page (0, 4, 0);
700 return \"LM %0,%N0,%1\";
702 else if (FP_REG_P (operands[1]))
704 mvs_check_page (0, 4, 0);
705 return \"STD %1,%0\";
707 mvs_check_page (0, 4, 0);
708 return \"STM %1,%N1,%0\";
710 [(set_attr "length" "8")]
713 ;; we have got to provide a movdi alternative that will go from
714 ;; register to memory & back in its full glory. However, we try to
715 ;; discourage its use by listing this alternative last.
716 ;; The problem is that the instructions above only provide
717 ;; S-form style (base + displacement) mem access, while the
718 ;; below provvides the full (base+index+displacement) RX-form.
719 ;; These are rarely needed, but when needed they're needed.
722 [(set (match_operand:DI 0 "general_operand" "=d,???m")
723 (match_operand:DI 1 "general_operand" "???m,d"))]
729 if (REG_P (operands[0]))
731 mvs_check_page (0, 8, 0);
732 return \"LM %0,%N0,%1\";
734 else if (REG_P (operands[1]))
736 mvs_check_page (0, 8, 0);
737 return \"STM %1,%N1,%0\";
739 mvs_check_page (0, 6, 0);
740 return \"MVC %O0(8,%R0),%1\";
742 [(set_attr "length" "8")]
746 ; movsi instruction pattern(s).
750 ;; [(set (match_operand:SI 0 "r_or_s_operand" "=dm,d,dm")
751 ;; (match_operand:SI 1 "r_or_s_operand" "diR,dim,*fF"))]
752 [(set (match_operand:SI 0 "r_or_s_operand" "=d,dS,dm")
753 (match_operand:SI 1 "general_operand" "dim,diS,di*fF"))]
755 "TARGET_CHAR_INSTRUCTIONS"
759 if (REG_P (operands[0]))
761 if (FP_REG_P (operands[1]))
763 mvs_check_page (0, 8, 0);
764 return \"STE %1,140(,13)\;L %0,140(,13)\";
766 if (REG_P (operands[1]))
768 mvs_check_page (0, 2, 0);
771 if (operands[1] == const0_rtx)
774 mvs_check_page (0, 2, 0);
775 return \"SLR %0,%0\";
777 if (GET_CODE (operands[1]) == CONST_INT
778 && (unsigned) INTVAL (operands[1]) < 4096)
780 mvs_check_page (0, 4, 0);
781 return \"LA %0,%c1(0,0)\";
783 mvs_check_page (0, 4, 0);
786 else if (FP_REG_P (operands[1]))
788 mvs_check_page (0, 4, 0);
789 return \"STE %1,%0\";
791 else if (REG_P (operands[1]))
793 mvs_check_page (0, 4, 0);
796 mvs_check_page (0, 6, 0);
797 return \"MVC %O0(4,%R0),%1\";
799 [(set_attr "length" "8")]
803 [(set (match_operand:SI 0 "general_operand" "=d,dm")
804 (match_operand:SI 1 "general_operand" "dimF,*fd"))]
809 if (REG_P (operands[0]))
811 if (FP_REG_P (operands[1]))
813 mvs_check_page (0, 8, 0);
814 return \"STE %1,140(,13)\;L %0,140(,13)\";
816 if (REG_P (operands[1]))
818 mvs_check_page (0, 2, 0);
821 if (operands[1] == const0_rtx)
824 mvs_check_page (0, 2, 0);
825 return \"SLR %0,%0\";
827 if (GET_CODE (operands[1]) == CONST_INT
828 && (unsigned) INTVAL (operands[1]) < 4096)
830 mvs_check_page (0, 4, 0);
831 return \"LA %0,%c1(0,0)\";
833 mvs_check_page (0, 4, 0);
836 else if (FP_REG_P (operands[1]))
838 mvs_check_page (0, 4, 0);
839 return \"STE %1,%0\";
841 mvs_check_page (0, 4, 0);
844 [(set_attr "length" "8")]
847 ;(define_expand "movsi"
848 ; [(set (match_operand:SI 0 "general_operand" "=d,dm")
849 ; (match_operand:SI 1 "general_operand" "dimF,*fd"))]
856 ; if (GET_CODE (op0) == CONST
857 ; && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SYMBOL_REF
858 ; && SYMBOL_REF_FLAG (XEXP (XEXP (op0, 0), 0)))
860 ; op0 = gen_rtx_MEM (SImode, copy_to_mode_reg (SImode, XEXP (op0, 0)));
864 ; if (GET_CODE (op1) == CONST
865 ; && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF
866 ; && SYMBOL_REF_FLAG (XEXP (XEXP (op1, 0), 0)))
868 ; op1 = gen_rtx_MEM (SImode, copy_to_mode_reg (SImode, XEXP (op1, 0)));
871 ; emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
876 ; movhi instruction pattern(s).
880 [(set (match_operand:HI 0 "r_or_s_operand" "=g")
881 (match_operand:HI 1 "r_or_s_operand" "g"))]
882 "TARGET_CHAR_INSTRUCTIONS"
886 if (REG_P (operands[0]))
888 if (REG_P (operands[1]))
890 mvs_check_page (0, 2, 0);
893 if (operands[1] == const0_rtx)
896 mvs_check_page (0, 2, 0);
897 return \"SLR %0,%0\";
899 if (GET_CODE (operands[1]) == CONST_INT
900 && (unsigned) INTVAL (operands[1]) < 4096)
902 mvs_check_page (0, 4, 0);
903 return \"LA %0,%c1(0,0)\";
905 if (GET_CODE (operands[1]) == CONST_INT)
907 mvs_check_page (0, 4, 0);
908 return \"LH %0,%H1\";
910 mvs_check_page (0, 4, 0);
913 else if (REG_P (operands[1]))
915 mvs_check_page (0, 4, 0);
916 return \"STH %1,%0\";
918 if (GET_CODE (operands[1]) == CONST_INT)
920 mvs_check_page (0, 6, 0);
921 return \"MVC %O0(2,%R0),%H1\";
923 mvs_check_page (0, 6, 0);
924 return \"MVC %O0(2,%R0),%1\";
926 [(set_attr "length" "6")]
930 [(set (match_operand:HI 0 "general_operand" "=d,m")
931 (match_operand:HI 1 "general_operand" "g,d"))]
936 if (REG_P (operands[0]))
938 if (REG_P (operands[1]))
940 mvs_check_page (0, 2, 0);
943 if (operands[1] == const0_rtx)
946 mvs_check_page (0, 2, 0);
947 return \"SLR %0,%0\";
949 if (GET_CODE (operands[1]) == CONST_INT
950 && (unsigned) INTVAL (operands[1]) < 4096)
952 mvs_check_page (0, 4, 0);
953 return \"LA %0,%c1(0,0)\";
955 if (GET_CODE (operands[1]) == CONST_INT)
957 mvs_check_page (0, 4, 0);
958 return \"LH %0,%H1\";
960 mvs_check_page (0, 4, 0);
963 mvs_check_page (0, 4, 0);
964 return \"STH %1,%0\";
966 [(set_attr "length" "4")]
970 ; movqi instruction pattern(s).
974 [(set (match_operand:QI 0 "r_or_s_operand" "=g")
975 (match_operand:QI 1 "r_or_s_operand" "g"))]
976 "TARGET_CHAR_INSTRUCTIONS"
980 if (REG_P (operands[0]))
982 if (REG_P (operands[1]))
984 mvs_check_page (0, 2, 0);
987 if (operands[1] == const0_rtx)
990 mvs_check_page (0, 2, 0);
991 return \"SLR %0,%0\";
993 if (GET_CODE (operands[1]) == CONST_INT)
995 if ((INTVAL (operands[1]) >= 0)
996 && (unsigned) INTVAL (operands[1]) < 4096)
998 mvs_check_page (0, 4, 0);
999 return \"LA %0,%c1(0,0)\";
1001 mvs_check_page (0, 4, 0);
1002 return \"L %0,=F'%c1'\";
1004 mvs_check_page (0, 4, 0);
1005 return \"IC %0,%1\";
1007 else if (REG_P (operands[1]))
1009 mvs_check_page (0, 4, 0);
1010 return \"STC %1,%0\";
1012 else if (GET_CODE (operands[1]) == CONST_INT)
1014 mvs_check_page (0, 4, 0);
1015 return \"MVI %0,%B1\";
1017 mvs_check_page (0, 6, 0);
1018 return \"MVC %O0(1,%R0),%1\";
1020 [(set_attr "length" "6")]
1023 (define_insn "movqi"
1024 [(set (match_operand:QI 0 "general_operand" "=d,m")
1025 (match_operand:QI 1 "general_operand" "g,d"))]
1029 check_label_emit ();
1030 if (REG_P (operands[0]))
1032 if (REG_P (operands[1]))
1034 mvs_check_page (0, 2, 0);
1035 return \"LR %0,%1\";
1037 if (operands[1] == const0_rtx)
1040 mvs_check_page (0, 2, 0);
1041 return \"SLR %0,%0\";
1043 if (GET_CODE (operands[1]) == CONST_INT)
1045 if ((INTVAL (operands[1]) >= 0)
1046 && (unsigned) INTVAL (operands[1]) < 4096)
1048 mvs_check_page (0, 4, 0);
1049 return \"LA %0,%c1(0,0)\";
1051 mvs_check_page (0, 4, 0);
1052 return \"L %0,=F'%c1'\";
1054 mvs_check_page (0, 4, 0);
1055 return \"IC %0,%1\";
1057 mvs_check_page (0, 4, 0);
1058 return \"STC %1,%0\";
1060 [(set_attr "length" "4")]
1064 ; movstrictqi instruction pattern(s).
1067 (define_insn "movstrictqi"
1068 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d"))
1069 (match_operand:QI 1 "general_operand" "g"))]
1073 check_label_emit ();
1074 if (REG_P (operands[1]))
1076 mvs_check_page (0, 8, 0);
1077 return \"STC %1,140(,13)\;IC %0,140(,13)\";
1079 mvs_check_page (0, 4, 0);
1080 return \"IC %0,%1\";
1082 [(set_attr "length" "8")]
1086 ; movstricthi instruction pattern(s).
1090 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1091 (match_operand:HI 1 "r_or_s_operand" "g"))]
1095 check_label_emit ();
1096 if (REG_P (operands[1]))
1098 mvs_check_page (0, 8, 0);
1099 return \"STH %1,140(,13)\;ICM %0,3,140(13)\";
1101 else if (GET_CODE (operands[1]) == CONST_INT)
1103 mvs_check_page (0, 4, 0);
1104 return \"ICM %0,3,%H1\";
1106 mvs_check_page (0, 4, 0);
1107 return \"ICM %0,3,%1\";
1109 [(set_attr "length" "8")]
1112 (define_insn "movstricthi"
1113 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1114 (match_operand:HI 1 "general_operand" "d"))]
1118 check_label_emit ();
1119 if (REG_P (operands[0]))
1121 mvs_check_page (0, 8, 0);
1122 return \"STH %1,140(,13)\;ICM %0,3,140(13)\";
1124 mvs_check_page (0, 4, 0);
1125 return \"STH %1,%0\";
1127 [(set_attr "length" "8")]
1131 ; movdf instruction pattern(s).
1135 ;; [(set (match_operand:DF 0 "r_or_s_operand" "=fm,fm,*dm")
1136 ;; (match_operand:DF 1 "r_or_s_operand" "fmF,*dm,fmF"))]
1137 [(set (match_operand:DF 0 "general_operand" "=f,m,fS,*dS,???d")
1138 (match_operand:DF 1 "general_operand" "fmF,fF,*dS,fSF,???d"))]
1140 "TARGET_CHAR_INSTRUCTIONS"
1143 check_label_emit ();
1144 if (FP_REG_P (operands[0]))
1146 if (FP_REG_P (operands[1]))
1148 mvs_check_page (0, 2, 0);
1149 return \"LDR %0,%1\";
1151 if (REG_P (operands[1]))
1153 mvs_check_page (0, 8, 0);
1154 return \"STM %1,%N1,140(13)\;LD %0,140(,13)\";
1156 if (operands[1] == const0_rtx)
1158 CC_STATUS_SET (operands[0], operands[1]);
1159 mvs_check_page (0, 2, 0);
1160 return \"SDR %0,%0\";
1162 mvs_check_page (0, 4, 0);
1163 return \"LD %0,%1\";
1165 if (REG_P (operands[0]))
1167 if (FP_REG_P (operands[1]))
1169 mvs_check_page (0, 12, 0);
1170 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
1172 if (REG_P (operands[1]))
1174 mvs_check_page (0, 4, 0);
1175 return \"LR %0,%1\;LR %N0,%N1\";
1177 mvs_check_page (0, 4, 0);
1178 return \"LM %0,%N0,%1\";
1180 else if (FP_REG_P (operands[1]))
1182 mvs_check_page (0, 4, 0);
1183 return \"STD %1,%0\";
1185 else if (REG_P (operands[1]))
1187 mvs_check_page (0, 4, 0);
1188 return \"STM %1,%N1,%0\";
1190 mvs_check_page (0, 6, 0);
1191 return \"MVC %O0(8,%R0),%1\";
1193 [(set_attr "length" "12")]
1196 (define_insn "movdf"
1197 ;; [(set (match_operand:DF 0 "general_operand" "=f,fm,m,*d")
1198 ;; (match_operand:DF 1 "general_operand" "fmF,*d,f,fmF"))]
1199 [(set (match_operand:DF 0 "general_operand" "=f,m,fS,*d,???d")
1200 (match_operand:DF 1 "general_operand" "fmF,f,*d,SfF,???d"))]
1205 check_label_emit ();
1206 if (FP_REG_P (operands[0]))
1208 if (FP_REG_P (operands[1]))
1210 mvs_check_page (0, 2, 0);
1211 return \"LDR %0,%1\";
1213 if (REG_P (operands[1]))
1215 mvs_check_page (0, 8, 0);
1216 return \"STM %1,%N1,140(13)\;LD %0,140(,13)\";
1218 if (operands[1] == const0_rtx)
1220 CC_STATUS_SET (operands[0], operands[1]);
1221 mvs_check_page (0, 2, 0);
1222 return \"SDR %0,%0\";
1224 mvs_check_page (0, 4, 0);
1225 return \"LD %0,%1\";
1227 else if (REG_P (operands[0]))
1229 if (FP_REG_P (operands[1]))
1231 mvs_check_page (0, 12, 0);
1232 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
1234 if (REG_P (operands[1]))
1236 mvs_check_page (0, 4, 0);
1237 return \"LR %0,%1\;LR %N0,%N1\";
1239 mvs_check_page (0, 4, 0);
1240 return \"LM %0,%N0,%1\";
1242 else if (FP_REG_P (operands[1]))
1244 mvs_check_page (0, 4, 0);
1245 return \"STD %1,%0\";
1247 mvs_check_page (0, 4, 0);
1248 return \"STM %1,%N1,%0\";
1250 [(set_attr "length" "12")]
1254 ; movsf instruction pattern(s).
1258 ;; [(set (match_operand:SF 0 "r_or_s_operand" "=fm,fm,*dm")
1259 ;; (match_operand:SF 1 "r_or_s_operand" "fmF,*dm,fmF"))]
1260 ;; [(set (match_operand:SF 0 "general_operand" "=f,m,fm,*d,S")
1261 ;; (match_operand:SF 1 "general_operand" "fmF,fF,*d,fmF,S"))]
1262 [(set (match_operand:SF 0 "general_operand" "=f*d,fm,S,???d")
1263 (match_operand:SF 1 "general_operand" "fmF,fF*d,S,???d"))]
1265 "TARGET_CHAR_INSTRUCTIONS"
1268 check_label_emit ();
1269 if (FP_REG_P (operands[0]))
1271 if (FP_REG_P (operands[1]))
1273 mvs_check_page (0, 2, 0);
1274 return \"LER %0,%1\";
1276 if (REG_P (operands[1]))
1278 mvs_check_page (0, 8, 0);
1279 return \"ST %1,140(,13)\;LE %0,140(,13)\";
1281 if (operands[1] == const0_rtx)
1283 CC_STATUS_SET (operands[0], operands[1]);
1284 mvs_check_page (0, 2, 0);
1285 return \"SER %0,%0\";
1287 mvs_check_page (0, 4, 0);
1288 return \"LE %0,%1\";
1290 else if (REG_P (operands[0]))
1292 if (FP_REG_P (operands[1]))
1294 mvs_check_page (0, 8, 0);
1295 return \"STE %1,140(,13)\;L %0,140(,13)\";
1297 if (REG_P (operands[1]))
1299 mvs_check_page (0, 2, 0);
1300 return \"LR %0,%1\";
1302 mvs_check_page (0, 4, 0);
1305 else if (FP_REG_P (operands[1]))
1307 mvs_check_page (0, 4, 0);
1308 return \"STE %1,%0\";
1310 else if (REG_P (operands[1]))
1312 mvs_check_page (0, 4, 0);
1313 return \"ST %1,%0\";
1315 mvs_check_page (0, 6, 0);
1316 return \"MVC %O0(4,%R0),%1\";
1318 [(set_attr "length" "8")]
1321 (define_insn "movsf"
1322 [(set (match_operand:SF 0 "general_operand" "=f,fm,m,*d")
1323 (match_operand:SF 1 "general_operand" "fmF,*d,f,fmF"))]
1327 check_label_emit ();
1328 if (FP_REG_P (operands[0]))
1330 if (FP_REG_P (operands[1]))
1332 mvs_check_page (0, 2, 0);
1333 return \"LER %0,%1\";
1335 if (REG_P (operands[1]))
1337 mvs_check_page (0, 8, 0);
1338 return \"ST %1,140(,13)\;LE %0,140(,13)\";
1340 if (operands[1] == const0_rtx)
1342 CC_STATUS_SET (operands[0], operands[1]);
1343 mvs_check_page (0, 2, 0);
1344 return \"SER %0,%0\";
1346 mvs_check_page (0, 4, 0);
1347 return \"LE %0,%1\";
1349 else if (REG_P (operands[0]))
1351 if (FP_REG_P (operands[1]))
1353 mvs_check_page (0, 8, 0);
1354 return \"STE %1,140(,13)\;L %0,140(,13)\";
1356 mvs_check_page (0, 4, 0);
1359 else if (FP_REG_P (operands[1]))
1361 mvs_check_page (0, 4, 0);
1362 return \"STE %1,%0\";
1364 mvs_check_page (0, 4, 0);
1365 return \"ST %1,%0\";
1367 [(set_attr "length" "8")]
1371 ; clrstrsi instruction pattern(s).
1372 ; memset a block of bytes to zero.
1373 ; block must be less than 16M (24 bits) in length
1375 (define_expand "clrstrsi"
1376 [(set (match_operand:BLK 0 "general_operand" "g")
1378 (use (match_operand:SI 1 "general_operand" ""))
1379 (match_operand 2 "" "")]
1384 XXX bogus, i think, unless change_address has a side effet we need
1387 op0 = XEXP (operands[0], 0);
1388 if (GET_CODE (op0) == REG
1389 || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == REG
1390 && GET_CODE (XEXP (op0, 1)) == CONST_INT
1391 && (unsigned) INTVAL (XEXP (op0, 1)) < 4096))
1394 op0 = change_address (operands[0], VOIDmode,
1395 copy_to_mode_reg (SImode, op0));
1399 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1400 rtx reg1 = gen_reg_rtx (DImode);
1401 rtx reg2 = gen_reg_rtx (DImode);
1402 rtx mem1 = operands[0];
1403 rtx zippo = gen_rtx_CONST_INT (SImode, 0);
1404 rtx len = operands[1];
1405 if (!CONSTANT_P (len))
1406 len = force_reg (SImode, len);
1408 /* Load up the address+length pairs. */
1409 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1410 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0),
1411 force_operand (XEXP (mem1, 0), NULL_RTX));
1412 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 1), len);
1414 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2));
1415 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0), zippo);
1416 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 1), zippo);
1419 emit_insn (gen_movstrsi_1 (reg1, reg2));
1425 ; movstrsi instruction pattern(s).
1426 ; block must be less than 16M (24 bits) in length
1428 (define_expand "movstrsi"
1429 [(set (match_operand:BLK 0 "general_operand" "")
1430 (match_operand:BLK 1 "general_operand" ""))
1431 (use (match_operand:SI 2 "general_operand" ""))
1432 (match_operand 3 "" "")]
1438 op0 = XEXP (operands[0], 0);
1439 if (GET_CODE (op0) == REG
1440 || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == REG
1441 && GET_CODE (XEXP (op0, 1)) == CONST_INT
1442 && (unsigned) INTVAL (XEXP (op0, 1)) < 4096))
1445 op0 = change_address (operands[0], VOIDmode,
1446 copy_to_mode_reg (SImode, op0));
1448 op1 = XEXP (operands[1], 0);
1449 if (GET_CODE (op1) == REG
1450 || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG
1451 && GET_CODE (XEXP (op1, 1)) == CONST_INT
1452 && (unsigned) INTVAL (XEXP (op1, 1)) < 4096))
1455 op1 = change_address (operands[1], VOIDmode,
1456 copy_to_mode_reg (SImode, op1));
1458 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 256)
1459 emit_insn (gen_rtx_PARALLEL (VOIDmode,
1461 gen_rtx_SET (VOIDmode, op0, op1),
1462 gen_rtx_USE (VOIDmode, operands[2]))));
1466 /* implementation provided by Richard Henderson <rth@cygnus.com> */
1467 rtx reg1 = gen_reg_rtx (DImode);
1468 rtx reg2 = gen_reg_rtx (DImode);
1469 rtx mem1 = operands[0];
1470 rtx mem2 = operands[1];
1471 rtx len = operands[2];
1472 if (!CONSTANT_P (len))
1473 len = force_reg (SImode, len);
1475 /* Load up the address+length pairs. */
1476 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1477 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0),
1478 force_operand (XEXP (mem1, 0), NULL_RTX));
1479 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 1), len);
1481 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2));
1482 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0),
1483 force_operand (XEXP (mem2, 0), NULL_RTX));
1484 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 1), len);
1487 emit_insn (gen_movstrsi_1 (reg1, reg2));
1492 ; Move a block that is less than 256 bytes in length.
1495 [(set (match_operand:BLK 0 "s_operand" "=m")
1496 (match_operand:BLK 1 "s_operand" "m"))
1497 (use (match_operand 2 "immediate_operand" "I"))]
1498 "((unsigned) INTVAL (operands[2]) < 256)"
1501 check_label_emit ();
1502 mvs_check_page (0, 6, 0);
1503 return \"MVC %O0(%c2,%R0),%1\";
1505 [(set_attr "length" "6")]
1508 ; Move a block that is larger than 255 bytes in length.
1510 (define_insn "movstrsi_1"
1511 [(set (mem:BLK (subreg:SI (match_operand:DI 0 "register_operand" "+d") 0))
1512 (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "+d") 0)))
1515 (clobber (match_dup 0))
1516 (clobber (match_dup 1))]
1520 check_label_emit ();
1521 mvs_check_page (0, 2, 0);
1522 return \"MVCL %0,%1\";
1524 [(set_attr "length" "2")]
1528 ;;- Conversion instructions.
1532 ; extendsidi2 instruction pattern(s).
1535 (define_expand "extendsidi2"
1536 [(set (match_operand:DI 0 "register_operand" "=d")
1537 (sign_extend:DI (match_operand:SI 1 "general_operand" "")))]
1541 if (GET_CODE (operands[1]) != CONST_INT)
1543 emit_insn (gen_rtx_SET (VOIDmode,
1544 operand_subword (operands[0], 0, 1, DImode), operands[1]));
1545 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1546 gen_rtx_ASHIFTRT (DImode, operands[0],
1547 gen_rtx_CONST_INT (SImode, 32))));
1551 if (INTVAL (operands[1]) < 0)
1553 emit_insn (gen_rtx_SET (VOIDmode,
1554 operand_subword (operands[0], 0, 1, DImode),
1555 gen_rtx_CONST_INT (SImode, -1)));
1559 emit_insn (gen_rtx_SET (VOIDmode,
1560 operand_subword (operands[0], 0, 1, DImode),
1561 gen_rtx_CONST_INT (SImode, 0)));
1563 emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (SImode, operands[0]),
1570 ; extendhisi2 instruction pattern(s).
1573 (define_insn "extendhisi2"
1574 [(set (match_operand:SI 0 "general_operand" "=d,m")
1575 (sign_extend:SI (match_operand:HI 1 "general_operand" "g,d")))]
1579 check_label_emit ();
1580 if (REG_P (operands[0]))
1582 if (REG_P (operands[1]))
1584 if (REGNO (operands[0]) != REGNO (operands[1]))
1586 mvs_check_page (0, 10, 0);
1587 return \"LR %0,%1\;SLL %0,16\;SRA %0,16\";
1590 return \"\"; /* Should be empty. 16-bits regs are always 32-bits. */
1592 if (operands[1] == const0_rtx)
1595 mvs_check_page (0, 2, 0);
1596 return \"SLR %0,%0\";
1598 if (GET_CODE (operands[1]) == CONST_INT
1599 && (unsigned) INTVAL (operands[1]) < 4096)
1601 mvs_check_page (0, 4, 0);
1602 return \"LA %0,%c1(0,0)\";
1604 if (GET_CODE (operands[1]) == CONST_INT)
1606 mvs_check_page (0, 4, 0);
1607 return \"LH %0,%H1\";
1609 mvs_check_page (0, 4, 0);
1610 return \"LH %0,%1\";
1612 mvs_check_page (0, 12, 0);
1613 return \"SLL %1,16\;SRA %1,16\;ST %1,%0\";
1615 [(set_attr "length" "12")]
1619 ; extendqisi2 instruction pattern(s).
1622 (define_insn "extendqisi2"
1623 [(set (match_operand:SI 0 "general_operand" "=d")
1624 (sign_extend:SI (match_operand:QI 1 "general_operand" "0mi")))]
1628 check_label_emit ();
1629 CC_STATUS_SET (operands[0], operands[1]);
1630 if (REG_P (operands[1]))
1632 mvs_check_page (0, 8, 0);
1633 return \"SLL %0,24\;SRA %0,24\";
1635 if (s_operand (operands[1], GET_MODE (operands[1])))
1637 mvs_check_page (0, 8, 0);
1638 return \"ICM %0,8,%1\;SRA %0,24\";
1640 mvs_check_page (0, 12, 0);
1641 return \"IC %0,%1\;SLL %0,24\;SRA %0,24\";
1643 [(set_attr "length" "12")]
1647 ; extendqihi2 instruction pattern(s).
1650 (define_insn "extendqihi2"
1651 [(set (match_operand:HI 0 "general_operand" "=d")
1652 (sign_extend:HI (match_operand:QI 1 "general_operand" "0m")))]
1656 check_label_emit ();
1657 CC_STATUS_SET (operands[0], operands[1]);
1658 if (REG_P (operands[1]))
1660 mvs_check_page (0, 8, 0);
1661 return \"SLL %0,24\;SRA %0,24\";
1663 if (s_operand (operands[1], GET_MODE (operands[1])))
1665 mvs_check_page (0, 8, 0);
1666 return \"ICM %0,8,%1\;SRA %0,24\";
1668 mvs_check_page (0, 12, 0);
1669 return \"IC %0,%1\;SLL %0,24\;SRA %0,24\";
1671 [(set_attr "length" "12")]
1675 ; zero_extendsidi2 instruction pattern(s).
1678 (define_expand "zero_extendsidi2"
1679 [(set (match_operand:DI 0 "register_operand" "=d")
1680 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
1684 emit_insn (gen_rtx_SET (VOIDmode,
1685 operand_subword (operands[0], 0, 1, DImode), operands[1]));
1686 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1687 gen_rtx_LSHIFTRT (DImode, operands[0],
1688 gen_rtx_CONST_INT (SImode, 32))));
1693 ; zero_extendhisi2 instruction pattern(s).
1696 (define_insn "zero_extendhisi2"
1697 [(set (match_operand:SI 0 "general_operand" "=d")
1698 (zero_extend:SI (match_operand:HI 1 "general_operand" "0")))]
1702 check_label_emit ();
1703 /* AND only sets zero/not-zero bits not the arithmetic bits ... */
1705 mvs_check_page (0, 4, 4);
1706 return \"N %1,=XL4'0000FFFF'\";
1708 [(set_attr "length" "4")]
1712 ; zero_extendqisi2 instruction pattern(s).
1715 (define_insn "zero_extendqisi2"
1716 [(set (match_operand:SI 0 "general_operand" "=d,&d")
1717 (zero_extend:SI (match_operand:QI 1 "general_operand" "0i,m")))]
1721 check_label_emit ();
1722 if (REG_P (operands[1]))
1724 /* AND only sets zero/not-zero bits not the arithmetic bits ... */
1726 mvs_check_page (0, 4, 4);
1727 return \"N %0,=XL4'000000FF'\";
1729 if (GET_CODE (operands[1]) == CONST_INT)
1731 mvs_check_page (0, 4, 0);
1732 return \"LA %0,%c1(0,0)\";
1735 mvs_check_page (0, 8, 0);
1736 return \"SLR %0,%0\;IC %0,%1\";
1738 [(set_attr "length" "8")]
1742 ; zero_extendqihi2 instruction pattern(s).
1745 (define_insn "zero_extendqihi2"
1746 [(set (match_operand:HI 0 "general_operand" "=d,&d")
1747 (zero_extend:HI (match_operand:QI 1 "general_operand" "0i,m")))]
1751 check_label_emit ();
1752 if (REG_P (operands[1]))
1754 /* AND only sets zero/not-zero bits not the arithmetic bits ... */
1756 mvs_check_page (0, 4, 4);
1757 return \"N %0,=XL4'000000FF'\";
1759 if (GET_CODE (operands[1]) == CONST_INT)
1761 mvs_check_page (0, 4, 0);
1762 return \"LA %0,%c1(0,0)\";
1765 mvs_check_page (0, 8, 0);
1766 return \"SLR %0,%0\;IC %0,%1\";
1768 [(set_attr "length" "8")]
1772 ; truncsihi2 instruction pattern(s).
1775 (define_insn "truncsihi2"
1776 [(set (match_operand:HI 0 "general_operand" "=d,m")
1777 (truncate:HI (match_operand:SI 1 "general_operand" "0,d")))]
1781 check_label_emit ();
1782 if (REG_P (operands[0]))
1784 CC_STATUS_SET (operands[0], operands[1]);
1785 mvs_check_page (0, 8, 0);
1786 return \"SLL %0,16\;SRA %0,16\";
1788 mvs_check_page (0, 4, 0);
1789 return \"STH %1,%0\";
1791 [(set_attr "length" "8")]
1795 ; fix_truncdfsi2 instruction pattern(s).
1798 (define_insn "fix_truncdfsi2"
1799 [(set (match_operand:SI 0 "general_operand" "=d")
1800 (fix:SI (truncate:DF (match_operand:DF 1 "general_operand" "+f"))))
1801 (clobber (reg:DF 16))]
1805 check_label_emit ();
1807 if (REGNO (operands[1]) == 16)
1809 mvs_check_page (0, 12, 8);
1810 return \"AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\";
1812 mvs_check_page (0, 14, 8);
1813 return \"LDR 0,%1\;AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\";
1815 [(set_attr "length" "14")]
1819 ; floatsidf2 instruction pattern(s).
1821 ; LE/370 mode uses the float field of the TCA.
1824 (define_insn "floatsidf2"
1825 [(set (match_operand:DF 0 "general_operand" "=f")
1826 (float:DF (match_operand:SI 1 "general_operand" "d")))]
1830 check_label_emit ();
1832 #ifdef TARGET_ELF_ABI
1833 mvs_check_page (0, 22, 12);
1834 return \"MVC 140(4,13),=XL4'4E000000'\;ST %1,144(,13)\;XI 144(13),128\;LD %0,140(,13)\;SD %0,=XL8'4E00000080000000'\";
1836 mvs_check_page (0, 16, 8);
1837 return \"ST %1,508(,12)\;XI 508(12),128\;LD %0,504(,12)\;SD %0,=XL8'4E00000080000000'\";
1840 [(set_attr "length" "22")]
1844 ; truncdfsf2 instruction pattern(s).
1847 (define_insn "truncdfsf2"
1848 [(set (match_operand:SF 0 "general_operand" "=f")
1849 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
1853 check_label_emit ();
1854 mvs_check_page (0, 2, 0);
1855 return \"LRER %0,%1\";
1857 [(set_attr "length" "2")]
1861 ; extendsfdf2 instruction pattern(s).
1864 (define_insn "extendsfdf2"
1865 [(set (match_operand:DF 0 "general_operand" "=f")
1866 (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
1870 check_label_emit ();
1871 CC_STATUS_SET (0, const0_rtx);
1872 if (FP_REG_P (operands[1]))
1874 if (REGNO (operands[0]) == REGNO (operands[1]))
1876 mvs_check_page (0, 10, 0);
1877 return \"STE %1,140(,13)\;SDR %0,%0\;LE %0,140(,13)\";
1879 mvs_check_page (0, 4, 0);
1880 return \"SDR %0,%0\;LER %0,%1\";
1882 mvs_check_page (0, 6, 0);
1883 return \"SDR %0,%0\;LE %0,%1\";
1885 [(set_attr "length" "10")]
1889 ;;- Add instructions.
1893 ; adddi3 instruction pattern(s).
1896 ;(define_expand "adddi3"
1897 ; [(set (match_operand:DI 0 "general_operand" "")
1898 ; (plus:DI (match_operand:DI 1 "general_operand" "")
1899 ; (match_operand:DI 2 "general_operand" "")))]
1903 ; rtx label = gen_label_rtx ();
1904 ; rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
1905 ; rtx op0_low = gen_lowpart (SImode, operands[0]);
1907 ; emit_insn (gen_rtx_SET (VOIDmode, op0_high,
1908 ; gen_rtx_PLUS (SImode,
1909 ; operand_subword (operands[1], 0, 1, DImode),
1910 ; operand_subword (operands[2], 0, 1, DImode))));
1911 ; emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1912 ; gen_rtx_SET (VOIDmode, op0_low,
1913 ; gen_rtx_PLUS (SImode, gen_lowpart (SImode, operands[1]),
1914 ; gen_lowpart (SImode, operands[2]))),
1915 ; gen_rtx_USE (VOIDmode, gen_rtx_LABEL_REF (VOIDmode, label)))));
1916 ; emit_insn (gen_rtx_SET (VOIDmode, op0_high,
1917 ; gen_rtx_PLUS (SImode, op0_high,
1918 ; gen_rtx_CONST_INT (SImode, 1))));
1919 ; emit_label (label);
1924 [(set (match_operand:SI 0 "general_operand" "=d")
1925 (plus:SI (match_operand:SI 1 "general_operand" "%0")
1926 (match_operand:SI 2 "general_operand" "g")))
1927 (use (label_ref (match_operand 3 "" "")))
1928 ; (clobber (reg:SI 14))
1935 check_label_emit ();
1936 onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3]));
1937 if (REG_P (operands[2]))
1941 mvs_check_page (0, 8, 4);
1942 return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1944 if (mvs_check_page (0, 6, 0))
1946 mvs_check_page (0, 2, 4);
1947 return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1949 return \"ALR %0,%2\;BC 12,%l3\";
1953 mvs_check_page (0, 10, 4);
1954 return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1956 if (mvs_check_page (0, 8 ,0))
1958 mvs_check_page (0, 2, 4);
1959 return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1961 return \"AL %0,%2\;BC 12,%l3\";
1963 [(set_attr "length" "10")]
1967 ; addsi3 instruction pattern(s).
1969 ; The following insn is used when it is known that operand one is an address,
1970 ; frame, stack or argument pointer, and operand two is a constant that is
1971 ; small enough to fit in the displacement field.
1972 ; Notice that we can't allow the frame pointer to used as a normal register
1973 ; because of this insn.
1977 [(set (match_operand:SI 0 "register_operand" "=d")
1978 (plus:SI (match_operand:SI 1 "general_operand" "%a")
1979 (match_operand:SI 2 "immediate_operand" "J")))]
1980 "((REGNO (operands[1]) == FRAME_POINTER_REGNUM || REGNO (operands[1]) == ARG_POINTER_REGNUM || REGNO (operands[1]) == STACK_POINTER_REGNUM) && (unsigned) INTVAL (operands[2]) < 4096)"
1983 check_label_emit ();
1984 CC_STATUS_INIT; /* add assumes CC but LA doesnt set CC */
1985 mvs_check_page (0, 4, 0);
1986 return \"LA %0,%c2(,%1)\";
1988 [(set_attr "length" "4")]
1991 ; This insn handles additions that are relative to the frame pointer.
1994 [(set (match_operand:SI 0 "register_operand" "=d")
1995 (plus:SI (match_operand:SI 1 "register_operand" "%a")
1996 (match_operand:SI 2 "immediate_operand" "i")))]
1997 "REGNO (operands[1]) == FRAME_POINTER_REGNUM"
2000 check_label_emit ();
2001 if ((unsigned) INTVAL (operands[2]) < 4096)
2003 CC_STATUS_INIT; /* add assumes CC but LA doesnt set CC */
2004 mvs_check_page (0, 4, 0);
2005 return \"LA %0,%c2(,%1)\";
2007 if (REGNO (operands[1]) == REGNO (operands[0]))
2010 mvs_check_page (0, 4, 0);
2013 mvs_check_page (0, 6, 0);
2014 return \"L %0,%2\;AR %0,%1\";
2016 [(set_attr "length" "6")]
2020 ;; The CC status bits for the arithmetic instructions are handled
2021 ;; in the NOTICE_UPDATE_CC macro (yeah???) and so they do not need
2022 ;; to be set below. They only need to be invalidated if *not* set
2023 ;; (e.g. by BCTR) ... yeah I think that's right ...
2026 (define_insn "addsi3"
2027 [(set (match_operand:SI 0 "general_operand" "=d")
2028 (plus:SI (match_operand:SI 1 "general_operand" "%0")
2029 (match_operand:SI 2 "general_operand" "g")))]
2033 check_label_emit ();
2034 if (REG_P (operands[2]))
2036 mvs_check_page (0, 2, 0);
2037 return \"AR %0,%2\";
2039 if (GET_CODE (operands[2]) == CONST_INT)
2041 if (INTVAL (operands[2]) == -1)
2043 CC_STATUS_INIT; /* add assumes CC but BCTR doesnt set CC */
2044 mvs_check_page (0, 2, 0);
2045 return \"BCTR %0,0\";
2048 mvs_check_page (0, 4, 0);
2051 [(set_attr "length" "4")]
2055 ; addhi3 instruction pattern(s).
2058 (define_insn "addhi3"
2059 [(set (match_operand:HI 0 "general_operand" "=d")
2060 (plus:HI (match_operand:HI 1 "general_operand" "%0")
2061 (match_operand:HI 2 "general_operand" "dmi")))]
2065 check_label_emit ();
2066 if (REG_P (operands[2]))
2068 mvs_check_page (0, 8, 0);
2069 return \"STH %2,140(,13)\;AH %0,140(,13)\";
2071 if (GET_CODE (operands[2]) == CONST_INT)
2073 if (INTVAL (operands[2]) == -1)
2075 CC_STATUS_INIT; /* add assumes CC but BCTR doesnt set CC */
2076 mvs_check_page (0, 2, 0);
2077 return \"BCTR %0,0\";
2079 mvs_check_page (0, 4, 0);
2080 return \"AH %0,%H2\";
2082 mvs_check_page (0, 4, 0);
2083 return \"AH %0,%2\";
2085 [(set_attr "length" "8")]
2089 ; addqi3 instruction pattern(s).
2092 (define_insn "addqi3"
2093 [(set (match_operand:QI 0 "general_operand" "=d")
2094 (plus:QI (match_operand:QI 1 "general_operand" "%a")
2095 (match_operand:QI 2 "general_operand" "ai")))]
2099 check_label_emit ();
2100 CC_STATUS_INIT; /* add assumes CC but LA doesnt set CC */
2101 mvs_check_page (0, 4, 0);
2102 if (REG_P (operands[2]))
2103 return \"LA %0,0(%1,%2)\";
2104 return \"LA %0,%B2(,%1)\";
2106 [(set_attr "length" "4")]
2110 ; adddf3 instruction pattern(s).
2113 (define_insn "adddf3"
2114 [(set (match_operand:DF 0 "general_operand" "=f")
2115 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2116 (match_operand:DF 2 "general_operand" "fmF")))]
2120 check_label_emit ();
2121 if (FP_REG_P (operands[2]))
2123 mvs_check_page (0, 2, 0);
2124 return \"ADR %0,%2\";
2126 mvs_check_page (0, 4, 0);
2127 return \"AD %0,%2\";
2129 [(set_attr "length" "4")]
2133 ; addsf3 instruction pattern(s).
2136 (define_insn "addsf3"
2137 [(set (match_operand:SF 0 "general_operand" "=f")
2138 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2139 (match_operand:SF 2 "general_operand" "fmF")))]
2143 check_label_emit ();
2144 if (FP_REG_P (operands[2]))
2146 mvs_check_page (0, 2, 0);
2147 return \"AER %0,%2\";
2149 mvs_check_page (0, 4, 0);
2150 return \"AE %0,%2\";
2152 [(set_attr "length" "4")]
2156 ;;- Subtract instructions.
2160 ; subdi3 instruction pattern(s).
2163 ;(define_expand "subdi3"
2164 ; [(set (match_operand:DI 0 "general_operand" "")
2165 ; (minus:DI (match_operand:DI 1 "general_operand" "")
2166 ; (match_operand:DI 2 "general_operand" "")))]
2170 ; rtx label = gen_label_rtx ();
2171 ; rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
2172 ; rtx op0_low = gen_lowpart (SImode, operands[0]);
2174 ; emit_insn (gen_rtx_SET (VOIDmode, op0_high,
2175 ; gen_rtx_MINUS (SImode,
2176 ; operand_subword (operands[1], 0, 1, DImode),
2177 ; operand_subword (operands[2], 0, 1, DImode))));
2178 ; emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
2179 ; gen_rtx_SET (VOIDmode, op0_low,
2180 ; gen_rtx_MINUS (SImode,
2181 ; gen_lowpart (SImode, operands[1]),
2182 ; gen_lowpart (SImode, operands[2]))),
2183 ; gen_rtx_USE (VOIDmode,
2184 ; gen_rtx_LABEL_REF (VOIDmode, label)))));
2185 ; emit_insn (gen_rtx_SET (VOIDmode, op0_high,
2186 ; gen_rtx_MINUS (SImode, op0_high,
2187 ; gen_rtx_CONST_INT (SImode, 1))));
2188 ; emit_label (label);
2193 [(set (match_operand:SI 0 "general_operand" "=d")
2194 (minus:SI (match_operand:SI 1 "general_operand" "0")
2195 (match_operand:SI 2 "general_operand" "g")))
2196 (use (label_ref (match_operand 3 "" "")))
2197 ; (clobber (reg:SI 14))
2204 check_label_emit ();
2206 onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3]));
2207 if (REG_P (operands[2]))
2211 mvs_check_page (0, 8, 4);
2212 return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
2214 if (mvs_check_page (0, 6, 0))
2216 mvs_check_page (0, 2, 4);
2217 return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
2219 return \"SLR %0,%2\;BC 12,%l3\";
2223 mvs_check_page (0, 10, 4);
2224 return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
2226 if (mvs_check_page (0, 8, 0))
2228 mvs_check_page (0, 2, 4);
2229 return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
2231 return \"SL %0,%2\;BC 12,%l3\";
2233 [(set_attr "length" "10")]
2237 ; subsi3 instruction pattern(s).
2240 (define_insn "subsi3"
2241 [(set (match_operand:SI 0 "general_operand" "=d")
2242 (minus:SI (match_operand:SI 1 "general_operand" "0")
2243 (match_operand:SI 2 "general_operand" "g")))]
2247 check_label_emit ();
2248 if (REG_P (operands[2]))
2250 mvs_check_page (0, 2, 0);
2251 return \"SR %0,%2\";
2253 if (operands[2] == const1_rtx)
2255 CC_STATUS_INIT; /* subtract assumes CC but BCTR doesnt set CC */
2256 mvs_check_page (0, 2, 0);
2257 return \"BCTR %0,0\";
2259 mvs_check_page (0, 4, 0);
2262 [(set_attr "length" "4")]
2266 ; subhi3 instruction pattern(s).
2269 (define_insn "subhi3"
2270 [(set (match_operand:HI 0 "general_operand" "=d")
2271 (minus:HI (match_operand:HI 1 "general_operand" "0")
2272 (match_operand:HI 2 "general_operand" "g")))]
2276 check_label_emit ();
2277 if (REG_P (operands[2]))
2279 mvs_check_page (0, 8, 0);
2280 return \"STH %2,140(,13)\;SH %0,140(,13)\";
2282 if (operands[2] == const1_rtx)
2284 CC_STATUS_INIT; /* subtract assumes CC but BCTR doesnt set CC */
2285 mvs_check_page (0, 2, 0);
2286 return \"BCTR %0,0\";
2288 if (GET_CODE (operands[2]) == CONST_INT)
2290 mvs_check_page (0, 4, 0);
2291 return \"SH %0,%H2\";
2293 mvs_check_page (0, 4, 0);
2294 return \"SH %0,%2\";
2296 [(set_attr "length" "8")]
2300 ; subqi3 instruction pattern(s).
2303 (define_expand "subqi3"
2304 [(set (match_operand:QI 0 "general_operand" "=d")
2305 (minus:QI (match_operand:QI 1 "general_operand" "0")
2306 (match_operand:QI 2 "general_operand" "di")))]
2310 if (REG_P (operands[2]))
2312 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2313 gen_rtx_MINUS (QImode, operands[1], operands[2])));
2317 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2318 gen_rtx_PLUS (QImode, operands[1],
2319 negate_rtx (QImode, operands[2]))));
2325 [(set (match_operand:QI 0 "register_operand" "=d")
2326 (minus:QI (match_operand:QI 1 "register_operand" "0")
2327 (match_operand:QI 2 "register_operand" "d")))]
2331 check_label_emit ();
2332 mvs_check_page (0, 2, 0);
2333 return \"SR %0,%2\";
2335 [(set_attr "length" "2")]
2339 ; subdf3 instruction pattern(s).
2342 (define_insn "subdf3"
2343 [(set (match_operand:DF 0 "general_operand" "=f")
2344 (minus:DF (match_operand:DF 1 "general_operand" "0")
2345 (match_operand:DF 2 "general_operand" "fmF")))]
2349 check_label_emit ();
2350 if (FP_REG_P (operands[2]))
2352 mvs_check_page (0, 2, 0);
2353 return \"SDR %0,%2\";
2355 mvs_check_page (0, 4, 0);
2356 return \"SD %0,%2\";
2358 [(set_attr "length" "4")]
2362 ; subsf3 instruction pattern(s).
2365 (define_insn "subsf3"
2366 [(set (match_operand:SF 0 "general_operand" "=f")
2367 (minus:SF (match_operand:SF 1 "general_operand" "0")
2368 (match_operand:SF 2 "general_operand" "fmF")))]
2372 check_label_emit ();
2373 if (FP_REG_P (operands[2]))
2375 mvs_check_page (0, 2, 0);
2376 return \"SER %0,%2\";
2378 mvs_check_page (0, 4, 0);
2379 return \"SE %0,%2\";
2381 [(set_attr "length" "4")]
2385 ;;- Multiply instructions.
2389 ; mulsi3 instruction pattern(s).
2392 (define_expand "mulsi3"
2393 [(set (match_operand:SI 0 "general_operand" "")
2394 (mult:SI (match_operand:SI 1 "general_operand" "")
2395 (match_operand:SI 2 "general_operand" "")))]
2399 if (GET_CODE (operands[1]) == CONST_INT
2400 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
2402 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2403 gen_rtx_MULT (SImode, operands[2], operands[1])));
2405 else if (GET_CODE (operands[2]) == CONST_INT
2406 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
2408 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2409 gen_rtx_MULT (SImode, operands[1], operands[2])));
2413 rtx r = gen_reg_rtx (DImode);
2415 /* XXX trouble. Below we generate some rtx's that model what
2416 * is really supposed to happen with multiply on the 370/390
2417 * hardware, and that is all well & good. However, during optimization
2418 * it can happen that the two operands are exchanged (after all,
2419 * multiplication is commutitive), in which case the doubleword
2420 * ends up in memory and everything is hosed. The gen_reg_rtx
2421 * should have kept it in a reg ... We hack around this
2422 * below, in the M/MR isntruction pattern, and constrain it to
2423 * \"di\" instead of \"g\". But this still ends up with lots & lots of
2424 * movement between registers & memory and is an awful waste.
2425 * Dunno how to untwist it elegantly; but it seems to work for now.
2427 emit_insn (gen_rtx_SET (VOIDmode,
2428 gen_rtx_SUBREG (SImode, r, 1), operands[1]));
2429 emit_insn (gen_rtx_SET (VOIDmode, r,
2430 gen_rtx_MULT (DImode, r, operands[2])));
2431 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2432 gen_rtx_SUBREG (SImode, r, 1)));
2438 [(set (match_operand:SI 0 "general_operand" "=d")
2439 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2440 (match_operand:SI 2 "immediate_operand" "K")))]
2444 check_label_emit ();
2445 mvs_check_page (0, 4, 0);
2446 return \"MH %0,%H2\";
2448 [(set_attr "length" "4")]
2452 [(set (match_operand:DI 0 "register_operand" "=d")
2453 (mult:DI (match_operand:DI 1 "general_operand" "%0")
2454 (match_operand:SI 2 "general_operand" "di")))]
2458 check_label_emit ();
2459 if (REG_P (operands[2]))
2461 mvs_check_page (0, 2, 0);
2462 return \"MR %0,%2\";
2464 mvs_check_page (0, 4, 0);
2467 [(set_attr "length" "4")]
2471 ; muldf3 instruction pattern(s).
2474 (define_insn "muldf3"
2475 [(set (match_operand:DF 0 "general_operand" "=f")
2476 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2477 (match_operand:DF 2 "general_operand" "fmF")))]
2481 check_label_emit ();
2482 if (FP_REG_P (operands[2]))
2484 mvs_check_page (0, 2, 0);
2485 return \"MDR %0,%2\";
2487 mvs_check_page (0, 4, 0);
2488 return \"MD %0,%2\";
2490 [(set_attr "length" "4")]
2494 ; mulsf3 instruction pattern(s).
2497 (define_insn "mulsf3"
2498 [(set (match_operand:SF 0 "general_operand" "=f")
2499 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2500 (match_operand:SF 2 "general_operand" "fmF")))]
2504 check_label_emit ();
2505 if (FP_REG_P (operands[2]))
2507 mvs_check_page (0, 2, 0);
2508 return \"MER %0,%2\";
2510 mvs_check_page (0, 4, 0);
2511 return \"ME %0,%2\";
2513 [(set_attr "length" "4")]
2517 ;;- Divide instructions.
2521 ; divsi3 instruction pattern(s).
2524 (define_expand "divsi3"
2525 [(set (match_operand:SI 0 "general_operand" "")
2526 (div:SI (match_operand:SI 1 "general_operand" "")
2527 (match_operand:SI 2 "general_operand" "")))]
2531 rtx r = gen_reg_rtx (DImode);
2533 emit_insn (gen_extendsidi2 (r, operands[1]));
2534 emit_insn (gen_rtx_SET (VOIDmode, r,
2535 gen_rtx_DIV (DImode, r, operands[2])));
2536 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2537 gen_rtx_SUBREG (SImode, r, 1)));
2543 ; udivsi3 instruction pattern(s).
2546 (define_expand "udivsi3"
2547 [(set (match_operand:SI 0 "general_operand" "")
2548 (udiv:SI (match_operand:SI 1 "general_operand" "")
2549 (match_operand:SI 2 "general_operand" "")))]
2553 rtx dr = gen_reg_rtx (DImode);
2554 rtx dr_0 = gen_rtx_SUBREG (SImode, dr, 0);
2555 rtx dr_1 = gen_rtx_SUBREG (SImode, dr, 1);
2558 if (GET_CODE (operands[2]) == CONST_INT)
2560 if (INTVAL (operands[2]) > 0)
2562 emit_insn (gen_zero_extendsidi2 (dr, operands[1]));
2563 emit_insn (gen_rtx_SET (VOIDmode, dr,
2564 gen_rtx_DIV (DImode, dr, operands[2])));
2568 rtx label1 = gen_label_rtx ();
2570 emit_insn (gen_rtx_SET (VOIDmode, dr_0, operands[1]));
2571 emit_insn (gen_rtx_SET (VOIDmode, dr_1, const0_rtx));
2572 emit_insn (gen_cmpsi (dr_0, operands[2]));
2573 emit_jump_insn (gen_bltu (label1));
2574 emit_insn (gen_rtx_SET (VOIDmode, dr_1, const1_rtx));
2575 emit_label (label1);
2580 rtx label1 = gen_label_rtx ();
2581 rtx label2 = gen_label_rtx ();
2582 rtx label3 = gen_label_rtx ();
2583 rtx sr = gen_reg_rtx (SImode);
2585 emit_insn (gen_rtx_SET (VOIDmode, dr_0, operands[1]));
2586 emit_insn (gen_rtx_SET (VOIDmode, sr, operands[2]));
2587 emit_insn (gen_rtx_SET (VOIDmode, dr_1, const0_rtx));
2588 emit_insn (gen_cmpsi (sr, dr_0));
2589 emit_jump_insn (gen_bgtu (label3));
2590 emit_insn (gen_cmpsi (sr, const1_rtx));
2591 emit_jump_insn (gen_blt (label2));
2592 emit_insn (gen_cmpsi (sr, const1_rtx));
2593 emit_jump_insn (gen_beq (label1));
2594 emit_insn (gen_rtx_SET (VOIDmode, dr,
2595 gen_rtx_LSHIFTRT (DImode, dr,
2596 gen_rtx_CONST_INT (SImode, 32))));
2597 emit_insn (gen_rtx_SET (VOIDmode, dr,
2598 gen_rtx_DIV (DImode, dr, sr)));
2599 emit_jump_insn (gen_jump (label3));
2600 emit_label (label1);
2601 emit_insn (gen_rtx_SET (VOIDmode, dr_1, dr_0));
2602 emit_jump_insn (gen_jump (label3));
2603 emit_label (label2);
2604 emit_insn (gen_rtx_SET (VOIDmode, dr_1, const1_rtx));
2605 emit_label (label3);
2607 emit_insn (gen_rtx_SET (VOIDmode, operands[0], dr_1));
2612 ; This is used by divsi3 & udivsi3.
2615 [(set (match_operand:DI 0 "register_operand" "=d")
2616 (div:DI (match_operand:DI 1 "register_operand" "0")
2617 (match_operand:SI 2 "general_operand" "dm")))]
2621 check_label_emit ();
2622 if (REG_P (operands[2]))
2624 mvs_check_page (0, 2, 0);
2625 return \"DR %0,%2\";
2627 mvs_check_page (0, 4, 0);
2630 [(set_attr "length" "4")]
2634 ; divdf3 instruction pattern(s).
2637 (define_insn "divdf3"
2638 [(set (match_operand:DF 0 "general_operand" "=f")
2639 (div:DF (match_operand:DF 1 "general_operand" "0")
2640 (match_operand:DF 2 "general_operand" "fmF")))]
2644 check_label_emit ();
2645 if (FP_REG_P (operands[2]))
2647 mvs_check_page (0, 2, 0);
2648 return \"DDR %0,%2\";
2650 mvs_check_page (0, 4, 0);
2651 return \"DD %0,%2\";
2653 [(set_attr "length" "4")]
2657 ; divsf3 instruction pattern(s).
2660 (define_insn "divsf3"
2661 [(set (match_operand:SF 0 "general_operand" "=f")
2662 (div:SF (match_operand:SF 1 "general_operand" "0")
2663 (match_operand:SF 2 "general_operand" "fmF")))]
2667 check_label_emit ();
2668 if (FP_REG_P (operands[2]))
2670 mvs_check_page (0, 2, 0);
2671 return \"DER %0,%2\";
2673 mvs_check_page (0, 4, 0);
2674 return \"DE %0,%2\";
2676 [(set_attr "length" "4")]
2680 ;;- Modulo instructions.
2684 ; modsi3 instruction pattern(s).
2687 (define_expand "modsi3"
2688 [(set (match_operand:SI 0 "general_operand" "")
2689 (mod:SI (match_operand:SI 1 "general_operand" "")
2690 (match_operand:SI 2 "general_operand" "")))]
2694 rtx r = gen_reg_rtx (DImode);
2696 emit_insn (gen_extendsidi2 (r, operands[1]));
2697 emit_insn (gen_rtx_SET (VOIDmode, r,
2698 gen_rtx_MOD (DImode, r, operands[2])));
2699 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2700 gen_rtx_SUBREG (SImode, r, 0)));
2705 ; umodsi3 instruction pattern(s).
2708 (define_expand "umodsi3"
2709 [(set (match_operand:SI 0 "general_operand" "")
2710 (umod:SI (match_operand:SI 1 "general_operand" "")
2711 (match_operand:SI 2 "general_operand" "")))]
2715 rtx dr = gen_reg_rtx (DImode);
2716 rtx dr_0 = gen_rtx_SUBREG (SImode, dr, 0);
2718 emit_insn (gen_rtx_SET (VOIDmode, dr_0, operands[1]));
2720 if (GET_CODE (operands[2]) == CONST_INT)
2722 if (INTVAL (operands[2]) > 0)
2724 emit_insn (gen_rtx_SET (VOIDmode, dr,
2725 gen_rtx_LSHIFTRT (DImode, dr,
2726 gen_rtx_CONST_INT (SImode, 32))));
2727 emit_insn (gen_rtx_SET (VOIDmode, dr,
2728 gen_rtx_MOD (DImode, dr, operands[2])));
2732 rtx label1 = gen_label_rtx ();
2733 rtx sr = gen_reg_rtx (SImode);
2735 emit_insn (gen_rtx_SET (VOIDmode, sr, operands[2]));
2736 emit_insn (gen_cmpsi (dr_0, sr));
2737 emit_jump_insn (gen_bltu (label1));
2738 emit_insn (gen_rtx_SET (VOIDmode, sr, gen_rtx_ABS (SImode, sr)));
2739 emit_insn (gen_rtx_SET (VOIDmode, dr_0,
2740 gen_rtx_PLUS (SImode, dr_0, sr)));
2741 emit_label (label1);
2746 rtx label1 = gen_label_rtx ();
2747 rtx label2 = gen_label_rtx ();
2748 rtx label3 = gen_label_rtx ();
2749 rtx sr = gen_reg_rtx (SImode);
2751 emit_insn (gen_rtx_SET (VOIDmode, dr_0, operands[1]));
2752 emit_insn (gen_rtx_SET (VOIDmode, sr, operands[2]));
2753 emit_insn (gen_cmpsi (sr, dr_0));
2754 emit_jump_insn (gen_bgtu (label3));
2755 emit_insn (gen_cmpsi (sr, const1_rtx));
2756 emit_jump_insn (gen_blt (label2));
2757 emit_jump_insn (gen_beq (label1));
2758 emit_insn (gen_rtx_SET (VOIDmode, dr,
2759 gen_rtx_LSHIFTRT (DImode, dr,
2760 gen_rtx_CONST_INT (SImode, 32))));
2761 emit_insn (gen_rtx_SET (VOIDmode, dr, gen_rtx_MOD (DImode, dr, sr)));
2762 emit_jump_insn (gen_jump (label3));
2763 emit_label (label1);
2764 emit_insn (gen_rtx_SET (VOIDmode, dr_0, const0_rtx));
2765 emit_jump_insn (gen_jump (label3));
2766 emit_label (label2);
2767 emit_insn (gen_rtx_SET (VOIDmode, dr_0,
2768 gen_rtx_MINUS (SImode, dr_0, sr)));
2769 emit_label (label3);
2772 emit_insn (gen_rtx_SET (VOIDmode, operands[0], dr_0));
2777 ; This is used by modsi3 & umodsi3.
2780 [(set (match_operand:DI 0 "register_operand" "=d")
2781 (mod:DI (match_operand:DI 1 "register_operand" "0")
2782 (match_operand:SI 2 "general_operand" "dm")))]
2786 check_label_emit ();
2787 if (REG_P (operands[2]))
2789 mvs_check_page (0, 2, 0);
2790 return \"DR %0,%2\";
2792 mvs_check_page (0, 4, 0);
2795 [(set_attr "length" "4")]
2799 ;;- And instructions.
2803 ; anddi3 instruction pattern(s).
2806 ;(define_expand "anddi3"
2807 ; [(set (match_operand:DI 0 "general_operand" "")
2808 ; (and:DI (match_operand:DI 1 "general_operand" "")
2809 ; (match_operand:DI 2 "general_operand" "")))]
2815 ; emit_insn (gen_andsi3 (operand_subword (operands[0], 0, 1, DImode),
2816 ; operand_subword (operands[1], 0, 1, DImode),
2817 ; operand_subword (operands[2], 0, 1, DImode)));
2818 ; emit_insn (gen_andsi3 (gen_lowpart (SImode, operands[0]),
2819 ; gen_lowpart (SImode, operands[1]),
2820 ; gen_lowpart (SImode, operands[2])));
2825 ; andsi3 instruction pattern(s).
2829 [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
2830 (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
2831 (match_operand:SI 2 "r_or_s_operand" "g,mi")))]
2832 "TARGET_CHAR_INSTRUCTIONS"
2835 check_label_emit ();
2836 CC_STATUS_INIT; /* and sets CC but not how we want it */
2837 if (REG_P (operands[2]))
2839 mvs_check_page (0, 2, 0);
2840 return \"NR %0,%2\";
2842 if (REG_P (operands[0]))
2844 mvs_check_page (0, 4, 0);
2847 mvs_check_page (0, 6, 0);
2848 return \"NC %O0(4,%R0),%2\";
2850 [(set_attr "length" "6")]
2853 (define_insn "andsi3"
2854 [(set (match_operand:SI 0 "general_operand" "=d")
2855 (and:SI (match_operand:SI 1 "general_operand" "%0")
2856 (match_operand:SI 2 "general_operand" "g")))]
2860 check_label_emit ();
2861 CC_STATUS_INIT; /* and sets CC but not how we want it */
2862 if (REG_P (operands[2]))
2864 mvs_check_page (0, 2, 0);
2865 return \"NR %0,%2\";
2867 mvs_check_page (0, 4, 0);
2870 [(set_attr "length" "4")]
2874 ; andhi3 instruction pattern(s).
2878 [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
2879 (and:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
2880 (match_operand:HI 2 "r_or_s_operand" "di,mi")))]
2881 "TARGET_CHAR_INSTRUCTIONS"
2884 check_label_emit ();
2885 CC_STATUS_INIT; /* and sets CC but not how we want it */
2886 if (REG_P (operands[2]))
2888 mvs_check_page (0, 2, 0);
2889 return \"NR %0,%2\";
2891 if (REG_P (operands[0]))
2893 /* %K2 == sign extend operand to 32 bits so that CH works */
2894 mvs_check_page (0, 4, 0);
2895 if (GET_CODE (operands[2]) == CONST_INT)
2896 return \"N %0,%K2\";
2899 if (GET_CODE (operands[2]) == CONST_INT)
2901 mvs_check_page (0, 6, 0);
2902 return \"NC %O0(2,%R0),%H2\";
2904 mvs_check_page (0, 6, 0);
2905 return \"NC %O0(2,%R0),%2\";
2907 [(set_attr "length" "6")]
2910 (define_insn "andhi3"
2911 [(set (match_operand:HI 0 "general_operand" "=d")
2912 (and:HI (match_operand:HI 1 "general_operand" "%0")
2913 (match_operand:HI 2 "general_operand" "di")))]
2917 check_label_emit ();
2918 CC_STATUS_INIT; /* and sets CC but not how we want it */
2919 if (GET_CODE (operands[2]) == CONST_INT)
2921 /* %K2 == sign extend operand to 32 bits so that CH works */
2922 mvs_check_page (0, 4, 0);
2923 return \"N %0,%K2\";
2925 mvs_check_page (0, 2, 0);
2926 return \"NR %0,%2\";
2928 [(set_attr "length" "4")]
2932 ; andqi3 instruction pattern(s).
2936 [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
2937 (and:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
2938 (match_operand:QI 2 "r_or_s_operand" "di,mi")))]
2939 "TARGET_CHAR_INSTRUCTIONS"
2942 check_label_emit ();
2943 CC_STATUS_INIT; /* and sets CC but not how we want it */
2944 if (REG_P (operands[2]))
2946 mvs_check_page (0, 2, 0);
2947 return \"NR %0,%2\";
2949 if (REG_P (operands[0]))
2951 mvs_check_page (0, 4, 0);
2954 if (GET_CODE (operands[2]) == CONST_INT)
2956 mvs_check_page (0, 4, 0);
2957 return \"NI %0,%B2\";
2959 mvs_check_page (0, 6, 0);
2960 return \"NC %O0(1,%R0),%2\";
2962 [(set_attr "length" "6")]
2965 (define_insn "andqi3"
2966 [(set (match_operand:QI 0 "general_operand" "=d")
2967 (and:QI (match_operand:QI 1 "general_operand" "%0")
2968 (match_operand:QI 2 "general_operand" "di")))]
2972 check_label_emit ();
2973 CC_STATUS_INIT; /* and sets CC but not how we want it */
2974 if (GET_CODE (operands[2]) == CONST_INT)
2976 mvs_check_page (0, 4, 0);
2979 mvs_check_page (0, 2, 0);
2980 return \"NR %0,%2\";
2982 [(set_attr "length" "4")]
2986 ;;- Bit set (inclusive or) instructions.
2990 ; iordi3 instruction pattern(s).
2993 ;(define_expand "iordi3"
2994 ; [(set (match_operand:DI 0 "general_operand" "")
2995 ; (ior:DI (match_operand:DI 1 "general_operand" "")
2996 ; (match_operand:DI 2 "general_operand" "")))]
3002 ; emit_insn (gen_iorsi3 (operand_subword (operands[0], 0, 1, DImode),
3003 ; operand_subword (operands[1], 0, 1, DImode),
3004 ; operand_subword (operands[2], 0, 1, DImode)));
3005 ; emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]),
3006 ; gen_lowpart (SImode, operands[1]),
3007 ; gen_lowpart (SImode, operands[2])));
3012 ; iorsi3 instruction pattern(s).
3016 [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
3017 (ior:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
3018 (match_operand:SI 2 "r_or_s_operand" "g,Si")))]
3019 "TARGET_CHAR_INSTRUCTIONS"
3022 check_label_emit ();
3023 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3024 if (REG_P (operands[2]))
3026 mvs_check_page (0, 2, 0);
3027 return \"OR %0,%2\";
3029 if (REG_P (operands[0]))
3031 mvs_check_page (0, 4, 0);
3034 mvs_check_page (0, 6, 0);
3035 return \"OC %O0(4,%R0),%2\";
3037 [(set_attr "length" "6")]
3040 (define_insn "iorsi3"
3041 [(set (match_operand:SI 0 "general_operand" "=d")
3042 (ior:SI (match_operand:SI 1 "general_operand" "%0")
3043 (match_operand:SI 2 "general_operand" "g")))]
3047 check_label_emit ();
3048 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3049 if (REG_P (operands[2]))
3051 mvs_check_page (0, 2, 0);
3052 return \"OR %0,%2\";
3054 mvs_check_page (0, 4, 0);
3057 [(set_attr "length" "4")]
3061 ; iorhi3 instruction pattern(s).
3065 [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
3066 (ior:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
3067 (match_operand:HI 2 "r_or_s_operand" "di,mi")))]
3068 "TARGET_CHAR_INSTRUCTIONS"
3071 check_label_emit ();
3072 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3073 if (REG_P (operands[2]))
3075 mvs_check_page (0, 2, 0);
3076 return \"OR %0,%2\";
3078 if (REG_P (operands[0]))
3080 mvs_check_page (0, 4, 0);
3083 if (GET_CODE (operands[2]) == CONST_INT)
3085 mvs_check_page (0, 6, 2);
3086 return \"OC %O0(2,%R0),%H2\";
3088 mvs_check_page (0, 6, 0);
3089 return \"OC %O0(2,%R0),%2\";
3091 [(set_attr "length" "6")]
3094 (define_insn "iorhi3"
3095 [(set (match_operand:HI 0 "general_operand" "=d")
3096 (ior:HI (match_operand:HI 1 "general_operand" "%0")
3097 (match_operand:HI 2 "general_operand" "di")))]
3101 check_label_emit ();
3102 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3103 if (GET_CODE (operands[2]) == CONST_INT)
3105 mvs_check_page (0, 4, 0);
3108 mvs_check_page (0, 2, 0);
3109 return \"OR %0,%2\";
3111 [(set_attr "length" "4")]
3115 ; iorqi3 instruction pattern(s).
3119 [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
3120 (ior:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
3121 (match_operand:QI 2 "r_or_s_operand" "di,mi")))]
3122 "TARGET_CHAR_INSTRUCTIONS"
3125 check_label_emit ();
3126 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3127 if (REG_P (operands[2]))
3129 mvs_check_page (0, 2, 0);
3130 return \"OR %0,%2\";
3132 if (REG_P (operands[0]))
3134 mvs_check_page (0, 4, 0);
3137 if (GET_CODE (operands[2]) == CONST_INT)
3139 mvs_check_page (0, 4, 0);
3140 return \"OI %0,%B2\";
3142 mvs_check_page (0, 6, 0);
3143 return \"OC %O0(1,%R0),%2\";
3145 [(set_attr "length" "6")]
3148 (define_insn "iorqi3"
3149 [(set (match_operand:QI 0 "general_operand" "=d")
3150 (ior:QI (match_operand:QI 1 "general_operand" "%0")
3151 (match_operand:QI 2 "general_operand" "di")))]
3155 check_label_emit ();
3156 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3157 if (GET_CODE (operands[2]) == CONST_INT)
3159 mvs_check_page (0, 4, 0);
3162 mvs_check_page (0, 2, 0);
3163 return \"OR %0,%2\";
3165 [(set_attr "length" "4")]
3169 ;;- Xor instructions.
3173 ; xordi3 instruction pattern(s).
3176 ;(define_expand "xordi3"
3177 ; [(set (match_operand:DI 0 "general_operand" "")
3178 ; (xor:DI (match_operand:DI 1 "general_operand" "")
3179 ; (match_operand:DI 2 "general_operand" "")))]
3185 ; emit_insn (gen_xorsi3 (operand_subword (operands[0], 0, 1, DImode),
3186 ; operand_subword (operands[1], 0, 1, DImode),
3187 ; operand_subword (operands[2], 0, 1, DImode)));
3188 ; emit_insn (gen_xorsi3 (gen_lowpart (SImode, operands[0]),
3189 ; gen_lowpart (SImode, operands[1]),
3190 ; gen_lowpart (SImode, operands[2])));
3195 ; xorsi3 instruction pattern(s).
3199 [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
3200 (xor:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
3201 (match_operand:SI 2 "r_or_s_operand" "g,mi")))]
3202 "TARGET_CHAR_INSTRUCTIONS"
3205 check_label_emit ();
3206 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3207 if (REG_P (operands[2]))
3209 mvs_check_page (0, 2, 0);
3210 return \"XR %0,%2\";
3212 if (REG_P (operands[0]))
3214 mvs_check_page (0, 4, 0);
3217 mvs_check_page (0, 6, 0);
3218 return \"XC %O0(4,%R0),%2\";
3220 [(set_attr "length" "6")]
3223 (define_insn "xorsi3"
3224 [(set (match_operand:SI 0 "general_operand" "=d")
3225 (xor:SI (match_operand:SI 1 "general_operand" "%0")
3226 (match_operand:SI 2 "general_operand" "g")))]
3230 check_label_emit ();
3231 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3232 if (REG_P (operands[2]))
3234 mvs_check_page (0, 2, 0);
3235 return \"XR %0,%2\";
3237 mvs_check_page (0, 4, 0);
3240 [(set_attr "length" "4")]
3244 ; xorhi3 instruction pattern(s).
3248 [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
3249 (xor:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
3250 (match_operand:HI 2 "r_or_s_operand" "di,mi")))]
3251 "TARGET_CHAR_INSTRUCTIONS"
3254 check_label_emit ();
3255 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3256 if (REG_P (operands[2]))
3258 mvs_check_page (0, 2, 0);
3259 return \"XR %0,%2\";
3261 if (REG_P (operands[0]))
3263 mvs_check_page (0, 4, 0);
3264 return \"X %0,%H2\";
3266 if (GET_CODE (operands[2]) == CONST_INT)
3268 mvs_check_page (0, 6, 0);
3269 return \"XC %O0(2,%R0),%H2\";
3271 mvs_check_page (0, 6, 0);
3272 return \"XC %O0(2,%R0),%2\";
3274 [(set_attr "length" "6")]
3277 (define_insn "xorhi3"
3278 [(set (match_operand:HI 0 "general_operand" "=d")
3279 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3280 (match_operand:HI 2 "general_operand" "di")))]
3284 check_label_emit ();
3285 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3286 if (GET_CODE (operands[2]) == CONST_INT)
3288 mvs_check_page (0, 4, 0);
3289 return \"X %0,%H2\";
3291 mvs_check_page (0, 2, 0);
3292 return \"XR %0,%2\";
3294 [(set_attr "length" "4")]
3298 ; xorqi3 instruction pattern(s).
3302 [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
3303 (xor:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
3304 (match_operand:QI 2 "r_or_s_operand" "di,mi")))]
3305 "TARGET_CHAR_INSTRUCTIONS"
3308 check_label_emit ();
3309 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3310 if (REG_P (operands[2]))
3312 mvs_check_page (0, 2, 0);
3313 return \"XR %0,%2\";
3315 if (REG_P (operands[0]))
3317 mvs_check_page (0, 4, 0);
3320 if (GET_CODE (operands[2]) == CONST_INT)
3322 mvs_check_page (0, 4, 0);
3323 return \"XI %0,%B2\";
3325 mvs_check_page (0, 6, 0);
3326 return \"XC %O0(1,%R0),%2\";
3328 [(set_attr "length" "6")]
3331 (define_insn "xorqi3"
3332 [(set (match_operand:QI 0 "general_operand" "=d")
3333 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3334 (match_operand:QI 2 "general_operand" "di")))]
3338 check_label_emit ();
3339 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3340 if (GET_CODE (operands[2]) == CONST_INT)
3342 mvs_check_page (0, 4, 0);
3345 mvs_check_page (0, 2, 0);
3346 return \"XR %0,%2\";
3348 [(set_attr "length" "4")]
3352 ;;- Negate instructions.
3356 ; negsi2 instruction pattern(s).
3359 (define_insn "negsi2"
3360 [(set (match_operand:SI 0 "general_operand" "=d")
3361 (neg:SI (match_operand:SI 1 "general_operand" "d")))]
3365 check_label_emit ();
3366 mvs_check_page (0, 2, 0);
3367 return \"LCR %0,%1\";
3369 [(set_attr "length" "2")]
3373 ; neghi2 instruction pattern(s).
3376 (define_insn "neghi2"
3377 [(set (match_operand:HI 0 "general_operand" "=d")
3378 (neg:HI (match_operand:HI 1 "general_operand" "d")))]
3382 check_label_emit ();
3383 mvs_check_page (0, 10, 0);
3384 return \"SLL %1,16\;SRA %1,16\;LCR %0,%1\";
3386 [(set_attr "length" "10")]
3390 ; negdf2 instruction pattern(s).
3393 (define_insn "negdf2"
3394 [(set (match_operand:DF 0 "general_operand" "=f")
3395 (neg:DF (match_operand:DF 1 "general_operand" "f")))]
3399 check_label_emit ();
3400 mvs_check_page (0, 2, 0);
3401 return \"LCDR %0,%1\";
3403 [(set_attr "length" "2")]
3407 ; negsf2 instruction pattern(s).
3410 (define_insn "negsf2"
3411 [(set (match_operand:SF 0 "general_operand" "=f")
3412 (neg:SF (match_operand:SF 1 "general_operand" "f")))]
3416 check_label_emit ();
3417 mvs_check_page (0, 2, 0);
3418 return \"LCER %0,%1\";
3420 [(set_attr "length" "2")]
3424 ;;- Absolute value instructions.
3428 ; abssi2 instruction pattern(s).
3431 (define_insn "abssi2"
3432 [(set (match_operand:SI 0 "general_operand" "=d")
3433 (abs:SI (match_operand:SI 1 "general_operand" "d")))]
3437 check_label_emit ();
3438 mvs_check_page (0, 2, 0);
3439 return \"LPR %0,%1\";
3441 [(set_attr "length" "2")]
3445 ; abshi2 instruction pattern(s).
3448 (define_insn "abshi2"
3449 [(set (match_operand:HI 0 "general_operand" "=d")
3450 (abs:HI (match_operand:HI 1 "general_operand" "d")))]
3454 check_label_emit ();
3455 mvs_check_page (0, 10, 0);
3456 return \"SLL %1,16\;SRA %1,16\;LPR %0,%1\";
3458 [(set_attr "length" "10")]
3462 ; absdf2 instruction pattern(s).
3465 (define_insn "absdf2"
3466 [(set (match_operand:DF 0 "general_operand" "=f")
3467 (abs:DF (match_operand:DF 1 "general_operand" "f")))]
3471 check_label_emit ();
3472 mvs_check_page (0, 2, 0);
3473 return \"LPDR %0,%1\";
3475 [(set_attr "length" "2")]
3479 ; abssf2 instruction pattern(s).
3482 (define_insn "abssf2"
3483 [(set (match_operand:SF 0 "general_operand" "=f")
3484 (abs:SF (match_operand:SF 1 "general_operand" "f")))]
3488 check_label_emit ();
3489 mvs_check_page (0, 2, 0);
3490 return \"LPER %0,%1\";
3492 [(set_attr "length" "2")]
3496 ;;- One complement instructions.
3500 ; one_cmpldi2 instruction pattern(s).
3503 ;(define_expand "one_cmpldi2"
3504 ; [(set (match_operand:DI 0 "general_operand" "")
3505 ; (not:DI (match_operand:DI 1 "general_operand" "")))]
3509 ; rtx gen_one_cmplsi2();
3511 ; emit_insn (gen_one_cmplsi2 (operand_subword (operands[0], 0, 1, DImode),
3512 ; operand_subword (operands[1], 0, 1, DImode)));
3513 ; emit_insn (gen_one_cmplsi2 (gen_lowpart (SImode, operands[0]),
3514 ; gen_lowpart (SImode, operands[1])));
3519 ; one_cmplsi2 instruction pattern(s).
3523 [(set (match_operand:SI 0 "r_or_s_operand" "=dm")
3524 (not:SI (match_operand:SI 1 "r_or_s_operand" "0")))]
3525 "TARGET_CHAR_INSTRUCTIONS"
3528 check_label_emit ();
3529 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3530 if (REG_P (operands[0]))
3532 mvs_check_page (0, 4, 4);
3533 return \"X %0,=F'-1'\";
3536 mvs_check_page (0, 6, 4);
3537 return \"XC %O0(4,%R0),=F'-1'\";
3539 [(set_attr "length" "6")]
3542 (define_insn "one_cmplsi2"
3543 [(set (match_operand:SI 0 "general_operand" "=d")
3544 (not:SI (match_operand:SI 1 "general_operand" "0")))]
3548 check_label_emit ();
3549 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3550 mvs_check_page (0, 4, 4);
3551 return \"X %0,=F'-1'\";
3553 [(set_attr "length" "4")]
3557 ; one_cmplhi2 instruction pattern(s).
3561 [(set (match_operand:HI 0 "r_or_s_operand" "=dm")
3562 (not:HI (match_operand:HI 1 "r_or_s_operand" "0")))]
3563 "TARGET_CHAR_INSTRUCTIONS"
3566 check_label_emit ();
3567 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3568 if (REG_P (operands[0]))
3570 mvs_check_page (0, 4, 4);
3571 return \"X %0,=F'-1'\";
3573 mvs_check_page (0, 6, 4);
3574 return \"XC %O0(2,%R0),=XL4'FFFF'\";
3576 [(set_attr "length" "6")]
3579 (define_insn "one_cmplhi2"
3580 [(set (match_operand:HI 0 "general_operand" "=d")
3581 (not:HI (match_operand:HI 1 "general_operand" "0")))]
3585 check_label_emit ();
3586 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3587 mvs_check_page (0, 4, 4);
3588 return \"X %0,=F'-1'\";
3590 [(set_attr "length" "4")]
3594 ; one_cmplqi2 instruction pattern(s).
3598 [(set (match_operand:QI 0 "r_or_s_operand" "=dm")
3599 (not:QI (match_operand:QI 1 "r_or_s_operand" "0")))]
3600 "TARGET_CHAR_INSTRUCTIONS"
3603 check_label_emit ();
3604 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3605 if (REG_P (operands[0]))
3607 mvs_check_page (0, 4, 4);
3608 return \"X %0,=F'-1'\";
3610 mvs_check_page (0, 4, 0);
3611 return \"XI %0,255\";
3613 [(set_attr "length" "4")]
3616 (define_insn "one_cmplqi2"
3617 [(set (match_operand:QI 0 "general_operand" "=d")
3618 (not:QI (match_operand:QI 1 "general_operand" "0")))]
3622 check_label_emit ();
3623 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3624 mvs_check_page (0, 4, 4);
3625 return \"X %0,=F'-1'\";
3627 [(set_attr "length" "4")]
3631 ;;- Arithmetic shift instructions.
3635 ; ashldi3 instruction pattern(s).
3638 (define_insn "ashldi3"
3639 [(set (match_operand:DI 0 "general_operand" "=d")
3640 (ashift:DI (match_operand:DI 1 "general_operand" "0")
3641 (match_operand:SI 2 "general_operand" "Ja")))]
3645 check_label_emit ();
3646 /* this status set seems not have the desired effect,
3647 * proably because the 64-bit long-long test is emulated ?! */
3648 CC_STATUS_SET (operands[0], operands[1]);
3649 mvs_check_page (0, 4, 0);
3650 if (REG_P (operands[2]))
3651 return \"SLDA %0,0(%2)\";
3652 return \"SLDA %0,%c2\";
3654 [(set_attr "length" "4")]
3658 ; ashrdi3 instruction pattern(s).
3661 (define_insn "ashrdi3"
3662 [(set (match_operand:DI 0 "register_operand" "=d")
3663 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
3664 (match_operand:SI 2 "general_operand" "Ja")))]
3668 check_label_emit ();
3669 /* this status set seems not have the desired effect,
3670 * proably because the 64-bit long-long test is emulated ?! */
3671 CC_STATUS_SET (operands[0], operands[1]);
3672 mvs_check_page (0, 4, 0);
3673 if (REG_P (operands[2]))
3674 return \"SRDA %0,0(%2)\";
3675 return \"SRDA %0,%c2\";
3677 [(set_attr "length" "4")]
3681 ; ashlsi3 instruction pattern(s).
3684 (define_insn "ashlsi3"
3685 [(set (match_operand:SI 0 "general_operand" "=d")
3686 (ashift:SI (match_operand:SI 1 "general_operand" "0")
3687 (match_operand:SI 2 "general_operand" "Ja")))]
3691 check_label_emit ();
3692 mvs_check_page (0, 4, 0);
3693 if (REG_P (operands[2]))
3694 return \"SLL %0,0(%2)\";
3695 return \"SLL %0,%c2\";
3697 [(set_attr "length" "4")]
3701 ; ashrsi3 instruction pattern(s).
3704 (define_insn "ashrsi3"
3705 [(set (match_operand:SI 0 "general_operand" "=d")
3706 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
3707 (match_operand:SI 2 "general_operand" "Ja")))]
3711 check_label_emit ();
3712 CC_STATUS_SET (operands[0], operands[1]);
3713 mvs_check_page (0, 4, 0);
3714 if (REG_P (operands[2]))
3715 return \"SRA %0,0(%2)\";
3716 return \"SRA %0,%c2\";
3718 [(set_attr "length" "4")]
3722 ; ashlhi3 instruction pattern(s).
3725 (define_insn "ashlhi3"
3726 [(set (match_operand:HI 0 "general_operand" "=d")
3727 (ashift:HI (match_operand:HI 1 "general_operand" "0")
3728 (match_operand:SI 2 "general_operand" "Ja")))]
3732 check_label_emit ();
3733 mvs_check_page (0, 8, 0);
3734 if (REG_P (operands[2]))
3735 return \"SLL %0,16(%2)\;SRA %0,16\";
3736 return \"SLL %0,16+%c2\;SRA %0,16\";
3738 [(set_attr "length" "8")]
3742 ; ashrhi3 instruction pattern(s).
3745 (define_insn "ashrhi3"
3746 [(set (match_operand:HI 0 "general_operand" "=d")
3747 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
3748 (match_operand:SI 2 "general_operand" "Ja")))]
3752 check_label_emit ();
3753 mvs_check_page (0, 8, 0);
3754 if (REG_P (operands[2]))
3755 return \"SLL %0,16\;SRA %0,16(%2)\";
3756 return \"SLL %0,16\;SRA %0,16+%c2\";
3758 [(set_attr "length" "8")]
3762 ; ashlqi3 instruction pattern(s).
3765 (define_insn "ashlqi3"
3766 [(set (match_operand:QI 0 "general_operand" "=d")
3767 (ashift:QI (match_operand:QI 1 "general_operand" "0")
3768 (match_operand:SI 2 "general_operand" "Ja")))]
3772 check_label_emit ();
3773 mvs_check_page (0, 4, 0);
3774 if (REG_P (operands[2]))
3775 return \"SLL %0,0(%2)\";
3776 return \"SLL %0,%c2\";
3778 [(set_attr "length" "4")]
3782 ; ashrqi3 instruction pattern(s).
3785 (define_insn "ashrqi3"
3786 [(set (match_operand:QI 0 "general_operand" "=d")
3787 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
3788 (match_operand:SI 2 "general_operand" "Ja")))]
3792 check_label_emit ();
3793 mvs_check_page (0, 8, 0);
3794 if (REG_P (operands[2]))
3795 return \"SLL %0,24\;SRA %0,24(%2)\";
3796 return \"SLL %0,24\;SRA %0,24+%c2\";
3798 [(set_attr "length" "8")]
3802 ;;- Logical shift instructions.
3806 ; lshrdi3 instruction pattern(s).
3809 (define_insn "lshrdi3"
3810 [(set (match_operand:DI 0 "general_operand" "=d")
3811 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
3812 (match_operand:SI 2 "general_operand" "Ja")))]
3816 check_label_emit ();
3817 mvs_check_page (0, 4, 0);
3818 if (REG_P (operands[2]))
3819 return \"SRDL %0,0(%2)\";
3820 return \"SRDL %0,%c2\";
3822 [(set_attr "length" "4")]
3827 ; lshrsi3 instruction pattern(s).
3830 (define_insn "lshrsi3"
3831 [(set (match_operand:SI 0 "general_operand" "=d")
3832 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
3833 (match_operand:SI 2 "general_operand" "Ja")))]
3837 check_label_emit ();
3838 mvs_check_page (0, 4, 0);
3839 if (REG_P (operands[2]))
3840 return \"SRL %0,0(%2)\";
3841 return \"SRL %0,%c2\";
3843 [(set_attr "length" "4")]
3847 ; lshrhi3 instruction pattern(s).
3850 (define_insn "lshrhi3"
3851 [(set (match_operand:HI 0 "general_operand" "=d")
3852 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
3853 (match_operand:SI 2 "general_operand" "Ja")))]
3857 check_label_emit ();
3858 CC_STATUS_INIT; /* AND sets the CC but not how we want it */
3859 if (REG_P (operands[2]))
3861 mvs_check_page (0, 8, 4);
3862 return \"N %0,=XL4'0000FFFF'\;SRL %0,0(%2)\";
3864 mvs_check_page (0, 8, 4);
3865 return \"N %0,=XL4'0000FFFF'\;SRL %0,%c2\";
3867 [(set_attr "length" "8")]
3871 ; lshrqi3 instruction pattern(s).
3874 (define_insn "lshrqi3"
3875 [(set (match_operand:QI 0 "general_operand" "=d")
3876 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
3877 (match_operand:SI 2 "general_operand" "Ja")))]
3881 check_label_emit ();
3882 CC_STATUS_INIT; /* AND sets the CC but not how we want it */
3883 mvs_check_page (0, 8, 4);
3884 if (REG_P (operands[2]))
3885 return \"N %0,=XL4'000000FF'\;SRL %0,0(%2)\";
3886 return \"N %0,=XL4'000000FF'\;SRL %0,%c2\";
3888 [(set_attr "length" "8")]
3891 ;; =======================================================================
3892 ;;- Conditional jump instructions.
3893 ;; =======================================================================
3896 ; beq instruction pattern(s).
3901 (if_then_else (eq (cc0)
3903 (label_ref (match_operand 0 "" ""))
3905 ; (clobber (reg:SI 14))
3910 check_label_emit ();
3911 mvs_check_page (0, 4, 0);
3912 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3916 mvs_check_page (0, 2, 4);
3917 return \"L 14,=A(%l0)\;BER 14\";
3919 [(set_attr "length" "6")]
3923 ; bne instruction pattern(s).
3928 (if_then_else (ne (cc0)
3930 (label_ref (match_operand 0 "" ""))
3932 ; (clobber (reg:SI 14))
3937 check_label_emit ();
3938 mvs_check_page (0, 4, 0);
3939 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3943 mvs_check_page (0, 2, 4);
3944 return \"L 14,=A(%l0)\;BNER 14\";
3946 [(set_attr "length" "6")]
3950 ; bgt instruction pattern(s).
3955 (if_then_else (gt (cc0)
3957 (label_ref (match_operand 0 "" ""))
3959 ; (clobber (reg:SI 14))
3964 check_label_emit ();
3965 mvs_check_page (0, 4, 0);
3966 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3970 mvs_check_page (0, 2, 4);
3971 return \"L 14,=A(%l0)\;BHR 14\";
3973 [(set_attr "length" "6")]
3977 ; bgtu instruction pattern(s).
3982 (if_then_else (gtu (cc0)
3984 (label_ref (match_operand 0 "" ""))
3986 ; (clobber (reg:SI 14))
3991 check_label_emit ();
3992 mvs_check_page (0, 4, 0);
3993 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3997 mvs_check_page (0, 2, 4);
3998 return \"L 14,=A(%l0)\;BHR 14\";
4000 [(set_attr "length" "6")]
4004 ; blt instruction pattern(s).
4009 (if_then_else (lt (cc0)
4011 (label_ref (match_operand 0 "" ""))
4013 ; (clobber (reg:SI 14))
4018 check_label_emit ();
4019 mvs_check_page (0, 4, 0);
4020 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4024 mvs_check_page (0, 2, 4);
4025 return \"L 14,=A(%l0)\;BLR 14\";
4027 [(set_attr "length" "6")]
4031 ; bltu instruction pattern(s).
4036 (if_then_else (ltu (cc0)
4038 (label_ref (match_operand 0 "" ""))
4040 ; (clobber (reg:SI 14))
4045 check_label_emit ();
4046 mvs_check_page (0, 4, 0);
4047 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4051 mvs_check_page (0, 2, 4);
4052 return \"L 14,=A(%l0)\;BLR 14\";
4054 [(set_attr "length" "6")]
4058 ; bge instruction pattern(s).
4063 (if_then_else (ge (cc0)
4065 (label_ref (match_operand 0 "" ""))
4067 ; (clobber (reg:SI 14))
4072 check_label_emit ();
4073 mvs_check_page (0, 4, 0);
4074 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4078 mvs_check_page (0, 2, 4);
4079 return \"L 14,=A(%l0)\;BNLR 14\";
4081 [(set_attr "length" "6")]
4085 ; bgeu instruction pattern(s).
4090 (if_then_else (geu (cc0)
4092 (label_ref (match_operand 0 "" ""))
4094 ; (clobber (reg:SI 14))
4099 check_label_emit ();
4100 mvs_check_page (0, 4, 0);
4101 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4105 mvs_check_page (0, 2, 4);
4106 return \"L 14,=A(%l0)\;BNLR 14\";
4108 [(set_attr "length" "6")]
4112 ; ble instruction pattern(s).
4117 (if_then_else (le (cc0)
4119 (label_ref (match_operand 0 "" ""))
4121 ; (clobber (reg:SI 14))
4126 check_label_emit ();
4127 mvs_check_page (0, 4, 0);
4128 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4132 mvs_check_page (0, 2, 4);
4133 return \"L 14,=A(%l0)\;BNHR 14\";
4135 [(set_attr "length" "6")]
4139 ; bleu instruction pattern(s).
4144 (if_then_else (leu (cc0)
4146 (label_ref (match_operand 0 "" ""))
4148 ; (clobber (reg:SI 14))
4153 check_label_emit ();
4154 mvs_check_page (0, 4, 0);
4155 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4159 mvs_check_page (0, 2, 4);
4160 return \"L 14,=A(%l0)\;BNHR 14\";
4162 [(set_attr "length" "6")]
4166 ;;- Negated conditional jump instructions.
4171 (if_then_else (eq (cc0)
4174 (label_ref (match_operand 0 "" ""))))
4175 ; (clobber (reg:SI 14))
4180 check_label_emit ();
4181 mvs_check_page (0, 4, 0);
4182 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4186 mvs_check_page (0, 2, 4);
4187 return \"L 14,=A(%l0)\;BNER 14\";
4189 [(set_attr "length" "6")]
4194 (if_then_else (ne (cc0)
4197 (label_ref (match_operand 0 "" ""))))
4198 ; (clobber (reg:SI 14))
4203 check_label_emit ();
4204 mvs_check_page (0, 4, 0);
4205 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4209 mvs_check_page (0, 2, 4);
4210 return \"L 14,=A(%l0)\;BER 14\";
4212 [(set_attr "length" "6")]
4217 (if_then_else (gt (cc0)
4220 (label_ref (match_operand 0 "" ""))))
4221 ; (clobber (reg:SI 14))
4226 check_label_emit ();
4227 mvs_check_page (0, 4, 0);
4228 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4232 mvs_check_page (0, 2, 4);
4233 return \"L 14,=A(%l0)\;BNHR 14\";
4235 [(set_attr "length" "6")]
4240 (if_then_else (gtu (cc0)
4243 (label_ref (match_operand 0 "" ""))))
4244 ; (clobber (reg:SI 14))
4249 check_label_emit ();
4250 mvs_check_page (0, 4, 0);
4251 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4255 mvs_check_page (0, 2, 4);
4256 return \"L 14,=A(%l0)\;BNHR 14\";
4258 [(set_attr "length" "6")]
4263 (if_then_else (lt (cc0)
4266 (label_ref (match_operand 0 "" ""))))
4267 ; (clobber (reg:SI 14))
4272 check_label_emit ();
4273 mvs_check_page (0, 4, 0);
4274 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4278 mvs_check_page (0, 2, 4);
4279 return \"L 14,=A(%l0)\;BNLR 14\";
4281 [(set_attr "length" "6")]
4286 (if_then_else (ltu (cc0)
4289 (label_ref (match_operand 0 "" ""))))
4290 ; (clobber (reg:SI 14))
4295 check_label_emit ();
4296 mvs_check_page (0, 4, 0);
4297 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4301 mvs_check_page (0, 2, 4);
4302 return \"L 14,=A(%l0)\;BNLR 14\";
4304 [(set_attr "length" "6")]
4309 (if_then_else (ge (cc0)
4312 (label_ref (match_operand 0 "" ""))))
4313 ; (clobber (reg:SI 14))
4318 check_label_emit ();
4319 mvs_check_page (0, 4, 0);
4320 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4324 mvs_check_page (0, 2, 4);
4325 return \"L 14,=A(%l0)\;BLR 14\";
4327 [(set_attr "length" "6")]
4332 (if_then_else (geu (cc0)
4335 (label_ref (match_operand 0 "" ""))))
4336 ; (clobber (reg:SI 14))
4341 check_label_emit ();
4342 mvs_check_page (0, 4, 0);
4343 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4347 mvs_check_page (0, 2, 4);
4348 return \"L 14,=A(%l0)\;BLR 14\";
4350 [(set_attr "length" "6")]
4355 (if_then_else (le (cc0)
4358 (label_ref (match_operand 0 "" ""))))
4359 ; (clobber (reg:SI 14))
4364 check_label_emit ();
4365 mvs_check_page (0, 4, 0);
4366 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4370 mvs_check_page (0, 2, 4);
4371 return \"L 14,=A(%l0)\;BHR 14\";
4373 [(set_attr "length" "6")]
4378 (if_then_else (leu (cc0)
4381 (label_ref (match_operand 0 "" ""))))
4382 ; (clobber (reg:SI 14))
4387 check_label_emit ();
4388 mvs_check_page (0, 4, 0);
4389 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4393 mvs_check_page (0, 2, 4);
4394 return \"L 14,=A(%l0)\;BHR 14\";
4396 [(set_attr "length" "6")]
4399 ;; ==============================================================
4400 ;;- Subtract one and jump if not zero.
4401 ;; These insns seem to not be getting matched ...
4402 ;; XXX should fix this, as it would improve for loops
4407 (ne (plus:SI (match_operand:SI 0 "register_operand" "+d")
4410 (label_ref (match_operand 1 "" ""))
4413 (plus:SI (match_dup 0)
4415 ; (clobber (reg:SI 14))
4420 check_label_emit ();
4421 mvs_check_page (0, 4, 0);
4422 if (mvs_check_label (CODE_LABEL_NUMBER (operands[1])))
4424 return \"BCT %0,%l1\";
4426 mvs_check_page (0, 2, 4);
4427 return \"L 14,=A(%l1)\;BCTR %0,14\";
4429 [(set_attr "length" "6")]
4435 (eq (plus:SI (match_operand:SI 0 "register_operand" "+d")
4439 (label_ref (match_operand 1 "" ""))))
4441 (plus:SI (match_dup 0)
4443 ; (clobber (reg:SI 14))
4448 check_label_emit ();
4449 mvs_check_page (0, 4, 0);
4450 if (mvs_check_label (CODE_LABEL_NUMBER (operands[1])))
4452 return \"BCT %0,%l1\";
4454 mvs_check_page (0, 2, 4);
4455 return \"L 14,=A(%l1)\;BCTR %0,14\";
4457 [(set_attr "length" "6")]
4460 ;; =============================================================
4461 ;;- Unconditional jump instructions.
4465 ; jump instruction pattern(s).
4470 (label_ref (match_operand 0 "" "")))
4471 ; (clobber (reg:SI 14))
4476 check_label_emit ();
4477 mvs_check_page (0, 4, 0);
4478 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4482 mvs_check_page (0, 2, 4);
4483 return \"L 14,=A(%l0)\;BR 14\";
4485 [(set_attr "length" "6")]
4489 ; indirect-jump instruction pattern(s).
4490 ; hack alert -- should check that displacement is < 4096
4492 (define_insn "indirect_jump"
4493 [(set (pc) (match_operand:SI 0 "general_operand" "rm"))]
4497 check_label_emit ();
4498 if (REG_P (operands[0]))
4500 mvs_check_page (0, 2, 0);
4503 mvs_check_page (0, 4, 0);
4506 [(set_attr "length" "4")]
4510 ; tablejump instruction pattern(s).
4513 (define_insn "tablejump"
4515 (match_operand:SI 0 "general_operand" "am"))
4516 (use (label_ref (match_operand 1 "" "")))
4517 ; (clobber (reg:SI 14))
4522 check_label_emit ();
4523 if (REG_P (operands[0]))
4525 mvs_check_page (0, 6, 0);
4526 return \"BR %0\;DS 0F\";
4528 mvs_check_page (0, 10, 0);
4529 return \"L 14,%0\;BR 14\;DS 0F\";
4531 [(set_attr "length" "10")]
4535 ;;- Jump to subroutine.
4537 ;; For the C/370 environment the internal functions, ie. sqrt, are called with
4538 ;; a non-standard form. So, we must fix it here. There's no BM like IBM.
4540 ;; The ELF ABI is different from the C/370 ABI because we have a simpler,
4541 ;; more powerful way of dealing with structure-value returns. Basically,
4542 ;; we use R1 to point at structure returns (64-bit and larger returns)
4543 ;; and R11 to point at the args. Note that this handles double-precision
4544 ;; (64-bit) values just fine, in a less-kludged manner than the C/370 ABI.
4545 ;; Since R1 is used, we use R2 to pass the argument pointer to the routine.
4548 ; call instruction pattern(s).
4550 ; We define four call instruction patterns below. The first two patterns,
4551 ; although general, end up matching (only?) calls through function pointers.
4552 ; The last two, which require a symbol-ref to match, get used for all
4553 ; ordinary subroutine calls.
4556 [(call (match_operand:QI 0 "memory_operand" "m")
4557 (match_operand:SI 1 "immediate_operand" "i"))
4558 (clobber (reg:SI 2))
4563 static char temp[128];
4564 int i = STACK_POINTER_OFFSET;
4567 check_label_emit ();
4568 #ifdef TARGET_ELF_ABI
4569 mvs_check_page (0, 10, 4);
4570 sprintf ( temp, \"LA r2,%d(,sp)\;LA 15,%%0\;BASR 14,15\", i );
4573 if (mvs_function_check (XSTR (operands[0], 0)))
4575 mvs_check_page (0, 22, 4);
4576 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;LA 15,%%0\;BALR 14,15\;LD 0,136(,13)\",
4581 mvs_check_page (0, 10, 4);
4582 sprintf ( temp, \"LA 1,%d(,13)\;LA 15,%%0\;BALR 14,15\", i );
4587 [(set_attr "length" "22")]
4591 ; call_value instruction pattern(s).
4594 (define_insn "call_value"
4595 [(set (match_operand 0 "" "=rf")
4596 (call (match_operand:QI 1 "memory_operand" "m")
4597 (match_operand:SI 2 "general_operand" "i")))
4598 (clobber (reg:SI 2))
4603 static char temp[128];
4604 int i = STACK_POINTER_OFFSET;
4607 check_label_emit ();
4608 #ifdef TARGET_ELF_ABI
4609 mvs_check_page (0, 10, 4);
4610 sprintf ( temp, \"LA r2,%d(,sp)\;LA 15,%%1\;BASR 14,15\", i );
4613 if (mvs_function_check (XSTR (operands[1], 0)))
4615 mvs_check_page (0, 22, 4);
4616 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;LA 15,%%1\;BALR 14,15\;LD 0,136(,13)\",
4621 mvs_check_page (0, 10, 4);
4622 sprintf ( temp, \"LA 1,%d(,13)\;LA 15,%%1\;BALR 14,15\", i );
4627 [(set_attr "length" "22")]
4631 [(call (mem:QI (match_operand:SI 0 "" "i"))
4632 (match_operand:SI 1 "general_operand" "g"))
4633 (clobber (reg:SI 2))
4635 "GET_CODE (operands[0]) == SYMBOL_REF"
4638 static char temp[128];
4639 int i = STACK_POINTER_OFFSET;
4642 check_label_emit ();
4643 #ifdef TARGET_ELF_ABI
4644 mvs_check_page (0, 10, 4);
4645 sprintf ( temp, \"LA r2,%d(,sp)\;L 15,%%0\;BASR 14,15\", i );
4648 if (mvs_function_check (XSTR (operands[0], 0)))
4650 mvs_check_page (0, 22, 4);
4651 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\",
4656 mvs_check_page (0, 10, 4);
4657 sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i );
4662 [(set_attr "length" "22")]
4666 [(set (match_operand 0 "" "=rf")
4667 (call (mem:QI (match_operand:SI 1 "" "i"))
4668 (match_operand:SI 2 "general_operand" "g")))
4669 (clobber (reg:SI 2))
4671 "GET_CODE (operands[1]) == SYMBOL_REF"
4674 static char temp[128];
4675 int i = STACK_POINTER_OFFSET;
4678 check_label_emit ();
4679 #ifdef TARGET_ELF_ABI
4680 mvs_check_page (0, 10, 4);
4681 sprintf ( temp, \"LA r2,%d(,sp)\;L 15,%%1\;BASR 14,15\", i );
4684 if (mvs_function_check (XSTR (operands[1], 0)))
4686 mvs_check_page (0, 22, 4);
4687 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\",
4692 mvs_check_page (0, 10, 4);
4693 sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i );
4698 [(set_attr "length" "22")]
4702 ;; Call subroutine returning any type.
4703 ;; This instruction pattern appears to be used only by the
4704 ;; expand_builtin_apply definition for __builtin_apply. It is needed
4705 ;; since call_value might return an in in r15 or a float in fpr0 (r16)
4706 ;; and the builtin code calla abort since the reg is ambiguous. Well,
4707 ;; the below is probably broken anyway, we just want to go for now.
4709 (define_expand "untyped_call"
4710 [(parallel [(call (match_operand 0 "" "")
4712 (match_operand 1 "" "")
4713 (match_operand 2 "" "")])]
4719 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
4721 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4723 rtx set = XVECEXP (operands[2], 0, i);
4724 emit_move_insn (SET_DEST (set), SET_SRC (set));
4727 /* The optimizer does not know that the call sets the function value
4728 registers we stored in the result block. We avoid problems by
4729 claiming that all hard registers are used and clobbered at this
4731 /* emit_insn (gen_blockage ()); */
4738 ;;- Miscellaneous instructions.
4742 ; nop instruction pattern(s).
4750 check_label_emit ();
4751 mvs_check_page (0, 2, 0);
4754 [(set_attr "length" "2")]