1 @c Copyright (C) 1988-2015 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 A @code{define_insn} expression is used to define instruction patterns
109 to which insns may be matched. A @code{define_insn} expression contains
110 an incomplete RTL expression, with pieces to be filled in later, operand
111 constraints that restrict how the pieces can be filled in, and an output
112 template or C code to generate the assembler output.
114 A @code{define_insn} is an RTL expression containing four or five operands:
118 An optional name. The presence of a name indicate that this instruction
119 pattern can perform a certain standard job for the RTL-generation
120 pass of the compiler. This pass knows certain names and will use
121 the instruction patterns with those names, if the names are defined
122 in the machine description.
124 The absence of a name is indicated by writing an empty string
125 where the name should go. Nameless instruction patterns are never
126 used for generating RTL code, but they may permit several simpler insns
127 to be combined later on.
129 Names that are not thus known and used in RTL-generation have no
130 effect; they are equivalent to no name at all.
132 For the purpose of debugging the compiler, you may also specify a
133 name beginning with the @samp{*} character. Such a name is used only
134 for identifying the instruction in RTL dumps; it is equivalent to having
135 a nameless pattern for all other purposes. Names beginning with the
136 @samp{*} character are not required to be unique.
139 The @dfn{RTL template}: This is a vector of incomplete RTL expressions
140 which describe the semantics of the instruction (@pxref{RTL Template}).
141 It is incomplete because it may contain @code{match_operand},
142 @code{match_operator}, and @code{match_dup} expressions that stand for
143 operands of the instruction.
145 If the vector has multiple elements, the RTL template is treated as a
146 @code{parallel} expression.
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 The condition: This is a string which contains a C expression. When the
152 compiler attempts to match RTL against a pattern, the condition is
153 evaluated. If the condition evaluates to @code{true}, the match is
154 permitted. The condition may be an empty string, which is treated
155 as always @code{true}.
157 @cindex named patterns and conditions
158 For a named pattern, the condition may not depend on the data in the
159 insn being matched, but only the target-machine-type flags. The compiler
160 needs to test these conditions during initialization in order to learn
161 exactly which named instructions are available in a particular run.
164 For nameless patterns, the condition is applied only when matching an
165 individual insn, and only after the insn has matched the pattern's
166 recognition template. The insn's operands may be found in the vector
169 For an insn where the condition has once matched, it
170 cannot later be used to control register allocation by excluding
171 certain register or value combinations.
174 The @dfn{output template} or @dfn{output statement}: This is either
175 a string, or a fragment of C code which returns a string.
177 When simple substitution isn't general enough, you can specify a piece
178 of C code to compute the output. @xref{Output Statement}.
181 The @dfn{insn attributes}: This is an optional vector containing the values of
182 attributes for insns matching this pattern (@pxref{Insn Attributes}).
186 @section Example of @code{define_insn}
187 @cindex @code{define_insn} example
189 Here is an example of an instruction pattern, taken from the machine
190 description for the 68000/68020.
195 (match_operand:SI 0 "general_operand" "rm"))]
199 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
201 return \"cmpl #0,%0\";
206 This can also be written using braced strings:
211 (match_operand:SI 0 "general_operand" "rm"))]
214 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
220 This describes an instruction which sets the condition codes based on the
221 value of a general operand. It has no condition, so any insn with an RTL
222 description of the form shown may be matched to this pattern. The name
223 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL
224 generation pass that, when it is necessary to test such a value, an insn
225 to do so can be constructed using this pattern.
227 The output control string is a piece of C code which chooses which
228 output template to return based on the kind of operand and the specific
229 type of CPU for which code is being generated.
231 @samp{"rm"} is an operand constraint. Its meaning is explained below.
234 @section RTL Template
235 @cindex RTL insn template
236 @cindex generating insns
237 @cindex insns, generating
238 @cindex recognizing insns
239 @cindex insns, recognizing
241 The RTL template is used to define which insns match the particular pattern
242 and how to find their operands. For named patterns, the RTL template also
243 says how to construct an insn from specified operands.
245 Construction involves substituting specified operands into a copy of the
246 template. Matching involves determining the values that serve as the
247 operands in the insn being matched. Both of these activities are
248 controlled by special expression types that direct matching and
249 substitution of the operands.
252 @findex match_operand
253 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
254 This expression is a placeholder for operand number @var{n} of
255 the insn. When constructing an insn, operand number @var{n}
256 will be substituted at this point. When matching an insn, whatever
257 appears at this position in the insn will be taken as operand
258 number @var{n}; but it must satisfy @var{predicate} or this instruction
259 pattern will not match at all.
261 Operand numbers must be chosen consecutively counting from zero in
262 each instruction pattern. There may be only one @code{match_operand}
263 expression in the pattern for each operand number. Usually operands
264 are numbered in the order of appearance in @code{match_operand}
265 expressions. In the case of a @code{define_expand}, any operand numbers
266 used only in @code{match_dup} expressions have higher values than all
267 other operand numbers.
269 @var{predicate} is a string that is the name of a function that
270 accepts two arguments, an expression and a machine mode.
271 @xref{Predicates}. During matching, the function will be called with
272 the putative operand as the expression and @var{m} as the mode
273 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
274 which normally causes @var{predicate} to accept any mode). If it
275 returns zero, this instruction pattern fails to match.
276 @var{predicate} may be an empty string; then it means no test is to be
277 done on the operand, so anything which occurs in this position is
280 Most of the time, @var{predicate} will reject modes other than @var{m}---but
281 not always. For example, the predicate @code{address_operand} uses
282 @var{m} as the mode of memory ref that the address should be valid for.
283 Many predicates accept @code{const_int} nodes even though their mode is
286 @var{constraint} controls reloading and the choice of the best register
287 class to use for a value, as explained later (@pxref{Constraints}).
288 If the constraint would be an empty string, it can be omitted.
290 People are often unclear on the difference between the constraint and the
291 predicate. The predicate helps decide whether a given insn matches the
292 pattern. The constraint plays no role in this decision; instead, it
293 controls various decisions in the case of an insn which does match.
295 @findex match_scratch
296 @item (match_scratch:@var{m} @var{n} @var{constraint})
297 This expression is also a placeholder for operand number @var{n}
298 and indicates that operand must be a @code{scratch} or @code{reg}
301 When matching patterns, this is equivalent to
304 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
307 but, when generating RTL, it produces a (@code{scratch}:@var{m})
310 If the last few expressions in a @code{parallel} are @code{clobber}
311 expressions whose operands are either a hard register or
312 @code{match_scratch}, the combiner can add or delete them when
313 necessary. @xref{Side Effects}.
316 @item (match_dup @var{n})
317 This expression is also a placeholder for operand number @var{n}.
318 It is used when the operand needs to appear more than once in the
321 In construction, @code{match_dup} acts just like @code{match_operand}:
322 the operand is substituted into the insn being constructed. But in
323 matching, @code{match_dup} behaves differently. It assumes that operand
324 number @var{n} has already been determined by a @code{match_operand}
325 appearing earlier in the recognition template, and it matches only an
326 identical-looking expression.
328 Note that @code{match_dup} should not be used to tell the compiler that
329 a particular register is being used for two operands (example:
330 @code{add} that adds one register to another; the second register is
331 both an input operand and the output operand). Use a matching
332 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
333 operand is used in two places in the template, such as an instruction
334 that computes both a quotient and a remainder, where the opcode takes
335 two input operands but the RTL template has to refer to each of those
336 twice; once for the quotient pattern and once for the remainder pattern.
338 @findex match_operator
339 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
340 This pattern is a kind of placeholder for a variable RTL expression
343 When constructing an insn, it stands for an RTL expression whose
344 expression code is taken from that of operand @var{n}, and whose
345 operands are constructed from the patterns @var{operands}.
347 When matching an expression, it matches an expression if the function
348 @var{predicate} returns nonzero on that expression @emph{and} the
349 patterns @var{operands} match the operands of the expression.
351 Suppose that the function @code{commutative_operator} is defined as
352 follows, to match any expression whose operator is one of the
353 commutative arithmetic operators of RTL and whose mode is @var{mode}:
357 commutative_integer_operator (x, mode)
361 enum rtx_code code = GET_CODE (x);
362 if (GET_MODE (x) != mode)
364 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
365 || code == EQ || code == NE);
369 Then the following pattern will match any RTL expression consisting
370 of a commutative operator applied to two general operands:
373 (match_operator:SI 3 "commutative_operator"
374 [(match_operand:SI 1 "general_operand" "g")
375 (match_operand:SI 2 "general_operand" "g")])
378 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
379 because the expressions to be matched all contain two operands.
381 When this pattern does match, the two operands of the commutative
382 operator are recorded as operands 1 and 2 of the insn. (This is done
383 by the two instances of @code{match_operand}.) Operand 3 of the insn
384 will be the entire commutative expression: use @code{GET_CODE
385 (operands[3])} to see which commutative operator was used.
387 The machine mode @var{m} of @code{match_operator} works like that of
388 @code{match_operand}: it is passed as the second argument to the
389 predicate function, and that function is solely responsible for
390 deciding whether the expression to be matched ``has'' that mode.
392 When constructing an insn, argument 3 of the gen-function will specify
393 the operation (i.e.@: the expression code) for the expression to be
394 made. It should be an RTL expression, whose expression code is copied
395 into a new expression whose operands are arguments 1 and 2 of the
396 gen-function. The subexpressions of argument 3 are not used;
397 only its expression code matters.
399 When @code{match_operator} is used in a pattern for matching an insn,
400 it usually best if the operand number of the @code{match_operator}
401 is higher than that of the actual operands of the insn. This improves
402 register allocation because the register allocator often looks at
403 operands 1 and 2 of insns to see if it can do register tying.
405 There is no way to specify constraints in @code{match_operator}. The
406 operand of the insn which corresponds to the @code{match_operator}
407 never has any constraints because it is never reloaded as a whole.
408 However, if parts of its @var{operands} are matched by
409 @code{match_operand} patterns, those parts may have constraints of
413 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
414 Like @code{match_dup}, except that it applies to operators instead of
415 operands. When constructing an insn, operand number @var{n} will be
416 substituted at this point. But in matching, @code{match_op_dup} behaves
417 differently. It assumes that operand number @var{n} has already been
418 determined by a @code{match_operator} appearing earlier in the
419 recognition template, and it matches only an identical-looking
422 @findex match_parallel
423 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
424 This pattern is a placeholder for an insn that consists of a
425 @code{parallel} expression with a variable number of elements. This
426 expression should only appear at the top level of an insn pattern.
428 When constructing an insn, operand number @var{n} will be substituted at
429 this point. When matching an insn, it matches if the body of the insn
430 is a @code{parallel} expression with at least as many elements as the
431 vector of @var{subpat} expressions in the @code{match_parallel}, if each
432 @var{subpat} matches the corresponding element of the @code{parallel},
433 @emph{and} the function @var{predicate} returns nonzero on the
434 @code{parallel} that is the body of the insn. It is the responsibility
435 of the predicate to validate elements of the @code{parallel} beyond
436 those listed in the @code{match_parallel}.
438 A typical use of @code{match_parallel} is to match load and store
439 multiple expressions, which can contain a variable number of elements
440 in a @code{parallel}. For example,
444 [(match_parallel 0 "load_multiple_operation"
445 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
446 (match_operand:SI 2 "memory_operand" "m"))
448 (clobber (reg:SI 179))])]
453 This example comes from @file{a29k.md}. The function
454 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
455 that subsequent elements in the @code{parallel} are the same as the
456 @code{set} in the pattern, except that they are referencing subsequent
457 registers and memory locations.
459 An insn that matches this pattern might look like:
463 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
465 (clobber (reg:SI 179))
467 (mem:SI (plus:SI (reg:SI 100)
470 (mem:SI (plus:SI (reg:SI 100)
474 @findex match_par_dup
475 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
476 Like @code{match_op_dup}, but for @code{match_parallel} instead of
477 @code{match_operator}.
481 @node Output Template
482 @section Output Templates and Operand Substitution
483 @cindex output templates
484 @cindex operand substitution
486 @cindex @samp{%} in template
488 The @dfn{output template} is a string which specifies how to output the
489 assembler code for an instruction pattern. Most of the template is a
490 fixed string which is output literally. The character @samp{%} is used
491 to specify where to substitute an operand; it can also be used to
492 identify places where different variants of the assembler require
495 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
496 operand @var{n} at that point in the string.
498 @samp{%} followed by a letter and a digit says to output an operand in an
499 alternate fashion. Four letters have standard, built-in meanings described
500 below. The machine description macro @code{PRINT_OPERAND} can define
501 additional letters with nonstandard meanings.
503 @samp{%c@var{digit}} can be used to substitute an operand that is a
504 constant value without the syntax that normally indicates an immediate
507 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
508 the constant is negated before printing.
510 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
511 memory reference, with the actual operand treated as the address. This may
512 be useful when outputting a ``load address'' instruction, because often the
513 assembler syntax for such an instruction requires you to write the operand
514 as if it were a memory reference.
516 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
519 @samp{%=} outputs a number which is unique to each instruction in the
520 entire compilation. This is useful for making local labels to be
521 referred to more than once in a single template that generates multiple
522 assembler instructions.
524 @samp{%} followed by a punctuation character specifies a substitution that
525 does not use an operand. Only one case is standard: @samp{%%} outputs a
526 @samp{%} into the assembler code. Other nonstandard cases can be
527 defined in the @code{PRINT_OPERAND} macro. You must also define
528 which punctuation characters are valid with the
529 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
533 The template may generate multiple assembler instructions. Write the text
534 for the instructions, with @samp{\;} between them.
536 @cindex matching operands
537 When the RTL contains two operands which are required by constraint to match
538 each other, the output template must refer only to the lower-numbered operand.
539 Matching operands are not always identical, and the rest of the compiler
540 arranges to put the proper RTL expression for printing into the lower-numbered
543 One use of nonstandard letters or punctuation following @samp{%} is to
544 distinguish between different assembler languages for the same machine; for
545 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
546 requires periods in most opcode names, while MIT syntax does not. For
547 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
548 syntax. The same file of patterns is used for both kinds of output syntax,
549 but the character sequence @samp{%.} is used in each place where Motorola
550 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
551 defines the sequence to output a period; the macro for MIT syntax defines
554 @cindex @code{#} in template
555 As a special case, a template consisting of the single character @code{#}
556 instructs the compiler to first split the insn, and then output the
557 resulting instructions separately. This helps eliminate redundancy in the
558 output templates. If you have a @code{define_insn} that needs to emit
559 multiple assembler instructions, and there is a matching @code{define_split}
560 already defined, then you can simply use @code{#} as the output template
561 instead of writing an output template that emits the multiple assembler
564 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
565 of the form @samp{@{option0|option1|option2@}} in the templates. These
566 describe multiple variants of assembler language syntax.
567 @xref{Instruction Output}.
569 @node Output Statement
570 @section C Statements for Assembler Output
571 @cindex output statements
572 @cindex C statements for assembler output
573 @cindex generating assembler output
575 Often a single fixed template string cannot produce correct and efficient
576 assembler code for all the cases that are recognized by a single
577 instruction pattern. For example, the opcodes may depend on the kinds of
578 operands; or some unfortunate combinations of operands may require extra
579 machine instructions.
581 If the output control string starts with a @samp{@@}, then it is actually
582 a series of templates, each on a separate line. (Blank lines and
583 leading spaces and tabs are ignored.) The templates correspond to the
584 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
585 if a target machine has a two-address add instruction @samp{addr} to add
586 into a register and another @samp{addm} to add a register to memory, you
587 might write this pattern:
590 (define_insn "addsi3"
591 [(set (match_operand:SI 0 "general_operand" "=r,m")
592 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
593 (match_operand:SI 2 "general_operand" "g,r")))]
600 @cindex @code{*} in template
601 @cindex asterisk in template
602 If the output control string starts with a @samp{*}, then it is not an
603 output template but rather a piece of C program that should compute a
604 template. It should execute a @code{return} statement to return the
605 template-string you want. Most such templates use C string literals, which
606 require doublequote characters to delimit them. To include these
607 doublequote characters in the string, prefix each one with @samp{\}.
609 If the output control string is written as a brace block instead of a
610 double-quoted string, it is automatically assumed to be C code. In that
611 case, it is not necessary to put in a leading asterisk, or to escape the
612 doublequotes surrounding C string literals.
614 The operands may be found in the array @code{operands}, whose C data type
617 It is very common to select different ways of generating assembler code
618 based on whether an immediate operand is within a certain range. Be
619 careful when doing this, because the result of @code{INTVAL} is an
620 integer on the host machine. If the host machine has more bits in an
621 @code{int} than the target machine has in the mode in which the constant
622 will be used, then some of the bits you get from @code{INTVAL} will be
623 superfluous. For proper results, you must carefully disregard the
624 values of those bits.
626 @findex output_asm_insn
627 It is possible to output an assembler instruction and then go on to output
628 or compute more of them, using the subroutine @code{output_asm_insn}. This
629 receives two arguments: a template-string and a vector of operands. The
630 vector may be @code{operands}, or it may be another array of @code{rtx}
631 that you declare locally and initialize yourself.
633 @findex which_alternative
634 When an insn pattern has multiple alternatives in its constraints, often
635 the appearance of the assembler code is determined mostly by which alternative
636 was matched. When this is so, the C code can test the variable
637 @code{which_alternative}, which is the ordinal number of the alternative
638 that was actually satisfied (0 for the first, 1 for the second alternative,
641 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
642 for registers and @samp{clrmem} for memory locations. Here is how
643 a pattern could use @code{which_alternative} to choose between them:
647 [(set (match_operand:SI 0 "general_operand" "=r,m")
651 return (which_alternative == 0
652 ? "clrreg %0" : "clrmem %0");
656 The example above, where the assembler code to generate was
657 @emph{solely} determined by the alternative, could also have been specified
658 as follows, having the output control string start with a @samp{@@}:
663 [(set (match_operand:SI 0 "general_operand" "=r,m")
672 If you just need a little bit of C code in one (or a few) alternatives,
673 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
678 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
683 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
691 @cindex operand predicates
692 @cindex operator predicates
694 A predicate determines whether a @code{match_operand} or
695 @code{match_operator} expression matches, and therefore whether the
696 surrounding instruction pattern will be used for that combination of
697 operands. GCC has a number of machine-independent predicates, and you
698 can define machine-specific predicates as needed. By convention,
699 predicates used with @code{match_operand} have names that end in
700 @samp{_operand}, and those used with @code{match_operator} have names
701 that end in @samp{_operator}.
703 All predicates are Boolean functions (in the mathematical sense) of
704 two arguments: the RTL expression that is being considered at that
705 position in the instruction pattern, and the machine mode that the
706 @code{match_operand} or @code{match_operator} specifies. In this
707 section, the first argument is called @var{op} and the second argument
708 @var{mode}. Predicates can be called from C as ordinary two-argument
709 functions; this can be useful in output templates or other
710 machine-specific code.
712 Operand predicates can allow operands that are not actually acceptable
713 to the hardware, as long as the constraints give reload the ability to
714 fix them up (@pxref{Constraints}). However, GCC will usually generate
715 better code if the predicates specify the requirements of the machine
716 instructions as closely as possible. Reload cannot fix up operands
717 that must be constants (``immediate operands''); you must use a
718 predicate that allows only constants, or else enforce the requirement
719 in the extra condition.
721 @cindex predicates and machine modes
722 @cindex normal predicates
723 @cindex special predicates
724 Most predicates handle their @var{mode} argument in a uniform manner.
725 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
726 any mode. If @var{mode} is anything else, then @var{op} must have the
727 same mode, unless @var{op} is a @code{CONST_INT} or integer
728 @code{CONST_DOUBLE}. These RTL expressions always have
729 @code{VOIDmode}, so it would be counterproductive to check that their
730 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
731 integer @code{CONST_DOUBLE} check that the value stored in the
732 constant will fit in the requested mode.
734 Predicates with this behavior are called @dfn{normal}.
735 @command{genrecog} can optimize the instruction recognizer based on
736 knowledge of how normal predicates treat modes. It can also diagnose
737 certain kinds of common errors in the use of normal predicates; for
738 instance, it is almost always an error to use a normal predicate
739 without specifying a mode.
741 Predicates that do something different with their @var{mode} argument
742 are called @dfn{special}. The generic predicates
743 @code{address_operand} and @code{pmode_register_operand} are special
744 predicates. @command{genrecog} does not do any optimizations or
745 diagnosis when special predicates are used.
748 * Machine-Independent Predicates:: Predicates available to all back ends.
749 * Defining Predicates:: How to write machine-specific predicate
753 @node Machine-Independent Predicates
754 @subsection Machine-Independent Predicates
755 @cindex machine-independent predicates
756 @cindex generic predicates
758 These are the generic predicates available to all back ends. They are
759 defined in @file{recog.c}. The first category of predicates allow
760 only constant, or @dfn{immediate}, operands.
762 @defun immediate_operand
763 This predicate allows any sort of constant that fits in @var{mode}.
764 It is an appropriate choice for instructions that take operands that
768 @defun const_int_operand
769 This predicate allows any @code{CONST_INT} expression that fits in
770 @var{mode}. It is an appropriate choice for an immediate operand that
771 does not allow a symbol or label.
774 @defun const_double_operand
775 This predicate accepts any @code{CONST_DOUBLE} expression that has
776 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
777 accept @code{CONST_INT}. It is intended for immediate floating point
782 The second category of predicates allow only some kind of machine
785 @defun register_operand
786 This predicate allows any @code{REG} or @code{SUBREG} expression that
787 is valid for @var{mode}. It is often suitable for arithmetic
788 instruction operands on a RISC machine.
791 @defun pmode_register_operand
792 This is a slight variant on @code{register_operand} which works around
793 a limitation in the machine-description reader.
796 (match_operand @var{n} "pmode_register_operand" @var{constraint})
803 (match_operand:P @var{n} "register_operand" @var{constraint})
807 would mean, if the machine-description reader accepted @samp{:P}
808 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
809 alias for some other mode, and might vary with machine-specific
810 options. @xref{Misc}.
813 @defun scratch_operand
814 This predicate allows hard registers and @code{SCRATCH} expressions,
815 but not pseudo-registers. It is used internally by @code{match_scratch};
816 it should not be used directly.
820 The third category of predicates allow only some kind of memory reference.
822 @defun memory_operand
823 This predicate allows any valid reference to a quantity of mode
824 @var{mode} in memory, as determined by the weak form of
825 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
828 @defun address_operand
829 This predicate is a little unusual; it allows any operand that is a
830 valid expression for the @emph{address} of a quantity of mode
831 @var{mode}, again determined by the weak form of
832 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
833 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
834 @code{memory_operand}, then @var{exp} is acceptable to
835 @code{address_operand}. Note that @var{exp} does not necessarily have
839 @defun indirect_operand
840 This is a stricter form of @code{memory_operand} which allows only
841 memory references with a @code{general_operand} as the address
842 expression. New uses of this predicate are discouraged, because
843 @code{general_operand} is very permissive, so it's hard to tell what
844 an @code{indirect_operand} does or does not allow. If a target has
845 different requirements for memory operands for different instructions,
846 it is better to define target-specific predicates which enforce the
847 hardware's requirements explicitly.
851 This predicate allows a memory reference suitable for pushing a value
852 onto the stack. This will be a @code{MEM} which refers to
853 @code{stack_pointer_rtx}, with a side-effect in its address expression
854 (@pxref{Incdec}); which one is determined by the
855 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
859 This predicate allows a memory reference suitable for popping a value
860 off the stack. Again, this will be a @code{MEM} referring to
861 @code{stack_pointer_rtx}, with a side-effect in its address
862 expression. However, this time @code{STACK_POP_CODE} is expected.
866 The fourth category of predicates allow some combination of the above
869 @defun nonmemory_operand
870 This predicate allows any immediate or register operand valid for @var{mode}.
873 @defun nonimmediate_operand
874 This predicate allows any register or memory operand valid for @var{mode}.
877 @defun general_operand
878 This predicate allows any immediate, register, or memory operand
879 valid for @var{mode}.
883 Finally, there are two generic operator predicates.
885 @defun comparison_operator
886 This predicate matches any expression which performs an arithmetic
887 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
891 @defun ordered_comparison_operator
892 This predicate matches any expression which performs an arithmetic
893 comparison in @var{mode} and whose expression code is valid for integer
894 modes; that is, the expression code will be one of @code{eq}, @code{ne},
895 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
896 @code{ge}, @code{geu}.
899 @node Defining Predicates
900 @subsection Defining Machine-Specific Predicates
901 @cindex defining predicates
902 @findex define_predicate
903 @findex define_special_predicate
905 Many machines have requirements for their operands that cannot be
906 expressed precisely using the generic predicates. You can define
907 additional predicates using @code{define_predicate} and
908 @code{define_special_predicate} expressions. These expressions have
913 The name of the predicate, as it will be referred to in
914 @code{match_operand} or @code{match_operator} expressions.
917 An RTL expression which evaluates to true if the predicate allows the
918 operand @var{op}, false if it does not. This expression can only use
919 the following RTL codes:
923 When written inside a predicate expression, a @code{MATCH_OPERAND}
924 expression evaluates to true if the predicate it names would allow
925 @var{op}. The operand number and constraint are ignored. Due to
926 limitations in @command{genrecog}, you can only refer to generic
927 predicates and predicates that have already been defined.
930 This expression evaluates to true if @var{op} or a specified
931 subexpression of @var{op} has one of a given list of RTX codes.
933 The first operand of this expression is a string constant containing a
934 comma-separated list of RTX code names (in lower case). These are the
935 codes for which the @code{MATCH_CODE} will be true.
937 The second operand is a string constant which indicates what
938 subexpression of @var{op} to examine. If it is absent or the empty
939 string, @var{op} itself is examined. Otherwise, the string constant
940 must be a sequence of digits and/or lowercase letters. Each character
941 indicates a subexpression to extract from the current expression; for
942 the first character this is @var{op}, for the second and subsequent
943 characters it is the result of the previous character. A digit
944 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
945 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
946 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
947 @code{MATCH_CODE} then examines the RTX code of the subexpression
948 extracted by the complete string. It is not possible to extract
949 components of an @code{rtvec} that is not at position 0 within its RTX
953 This expression has one operand, a string constant containing a C
954 expression. The predicate's arguments, @var{op} and @var{mode}, are
955 available with those names in the C expression. The @code{MATCH_TEST}
956 evaluates to true if the C expression evaluates to a nonzero value.
957 @code{MATCH_TEST} expressions must not have side effects.
963 The basic @samp{MATCH_} expressions can be combined using these
964 logical operators, which have the semantics of the C operators
965 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
966 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
967 arbitrary number of arguments; this has exactly the same effect as
968 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
972 An optional block of C code, which should execute
973 @samp{@w{return true}} if the predicate is found to match and
974 @samp{@w{return false}} if it does not. It must not have any side
975 effects. The predicate arguments, @var{op} and @var{mode}, are
976 available with those names.
978 If a code block is present in a predicate definition, then the RTL
979 expression must evaluate to true @emph{and} the code block must
980 execute @samp{@w{return true}} for the predicate to allow the operand.
981 The RTL expression is evaluated first; do not re-check anything in the
982 code block that was checked in the RTL expression.
985 The program @command{genrecog} scans @code{define_predicate} and
986 @code{define_special_predicate} expressions to determine which RTX
987 codes are possibly allowed. You should always make this explicit in
988 the RTL predicate expression, using @code{MATCH_OPERAND} and
991 Here is an example of a simple predicate definition, from the IA64
996 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
997 (define_predicate "small_addr_symbolic_operand"
998 (and (match_code "symbol_ref")
999 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1004 And here is another, showing the use of the C block.
1008 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1009 (define_predicate "gr_register_operand"
1010 (match_operand 0 "register_operand")
1013 if (GET_CODE (op) == SUBREG)
1014 op = SUBREG_REG (op);
1017 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1022 Predicates written with @code{define_predicate} automatically include
1023 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1024 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1025 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1026 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1027 kind of constant fits in the requested mode. This is because
1028 target-specific predicates that take constants usually have to do more
1029 stringent value checks anyway. If you need the exact same treatment
1030 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1031 provide, use a @code{MATCH_OPERAND} subexpression to call
1032 @code{const_int_operand}, @code{const_double_operand}, or
1033 @code{immediate_operand}.
1035 Predicates written with @code{define_special_predicate} do not get any
1036 automatic mode checks, and are treated as having special mode handling
1037 by @command{genrecog}.
1039 The program @command{genpreds} is responsible for generating code to
1040 test predicates. It also writes a header file containing function
1041 declarations for all machine-specific predicates. It is not necessary
1042 to declare these predicates in @file{@var{cpu}-protos.h}.
1045 @c Most of this node appears by itself (in a different place) even
1046 @c when the INTERNALS flag is clear. Passages that require the internals
1047 @c manual's context are conditionalized to appear only in the internals manual.
1050 @section Operand Constraints
1051 @cindex operand constraints
1054 Each @code{match_operand} in an instruction pattern can specify
1055 constraints for the operands allowed. The constraints allow you to
1056 fine-tune matching within the set of operands allowed by the
1062 @section Constraints for @code{asm} Operands
1063 @cindex operand constraints, @code{asm}
1064 @cindex constraints, @code{asm}
1065 @cindex @code{asm} constraints
1067 Here are specific details on what constraint letters you can use with
1068 @code{asm} operands.
1070 Constraints can say whether
1071 an operand may be in a register, and which kinds of register; whether the
1072 operand can be a memory reference, and which kinds of address; whether the
1073 operand may be an immediate constant, and which possible values it may
1074 have. Constraints can also require two operands to match.
1075 Side-effects aren't allowed in operands of inline @code{asm}, unless
1076 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1077 that the side-effects will happen exactly once in an instruction that can update
1078 the addressing register.
1082 * Simple Constraints:: Basic use of constraints.
1083 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1084 * Class Preferences:: Constraints guide which hard register to put things in.
1085 * Modifiers:: More precise control over effects of constraints.
1086 * Machine Constraints:: Existing constraints for some particular machines.
1087 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1088 * Define Constraints:: How to define machine-specific constraints.
1089 * C Constraint Interface:: How to test constraints from C code.
1095 * Simple Constraints:: Basic use of constraints.
1096 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1097 * Modifiers:: More precise control over effects of constraints.
1098 * Machine Constraints:: Special constraints for some particular machines.
1102 @node Simple Constraints
1103 @subsection Simple Constraints
1104 @cindex simple constraints
1106 The simplest kind of constraint is a string full of letters, each of
1107 which describes one kind of operand that is permitted. Here are
1108 the letters that are allowed:
1112 Whitespace characters are ignored and can be inserted at any position
1113 except the first. This enables each alternative for different operands to
1114 be visually aligned in the machine description even if they have different
1115 number of constraints and modifiers.
1117 @cindex @samp{m} in constraint
1118 @cindex memory references in constraints
1120 A memory operand is allowed, with any kind of address that the machine
1121 supports in general.
1122 Note that the letter used for the general memory constraint can be
1123 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1125 @cindex offsettable address
1126 @cindex @samp{o} in constraint
1128 A memory operand is allowed, but only if the address is
1129 @dfn{offsettable}. This means that adding a small integer (actually,
1130 the width in bytes of the operand, as determined by its machine mode)
1131 may be added to the address and the result is also a valid memory
1134 @cindex autoincrement/decrement addressing
1135 For example, an address which is constant is offsettable; so is an
1136 address that is the sum of a register and a constant (as long as a
1137 slightly larger constant is also within the range of address-offsets
1138 supported by the machine); but an autoincrement or autodecrement
1139 address is not offsettable. More complicated indirect/indexed
1140 addresses may or may not be offsettable depending on the other
1141 addressing modes that the machine supports.
1143 Note that in an output operand which can be matched by another
1144 operand, the constraint letter @samp{o} is valid only when accompanied
1145 by both @samp{<} (if the target machine has predecrement addressing)
1146 and @samp{>} (if the target machine has preincrement addressing).
1148 @cindex @samp{V} in constraint
1150 A memory operand that is not offsettable. In other words, anything that
1151 would fit the @samp{m} constraint but not the @samp{o} constraint.
1153 @cindex @samp{<} in constraint
1155 A memory operand with autodecrement addressing (either predecrement or
1156 postdecrement) is allowed. In inline @code{asm} this constraint is only
1157 allowed if the operand is used exactly once in an instruction that can
1158 handle the side-effects. Not using an operand with @samp{<} in constraint
1159 string in the inline @code{asm} pattern at all or using it in multiple
1160 instructions isn't valid, because the side-effects wouldn't be performed
1161 or would be performed more than once. Furthermore, on some targets
1162 the operand with @samp{<} in constraint string must be accompanied by
1163 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1164 or @code{%P0} on IA-64.
1166 @cindex @samp{>} in constraint
1168 A memory operand with autoincrement addressing (either preincrement or
1169 postincrement) is allowed. In inline @code{asm} the same restrictions
1170 as for @samp{<} apply.
1172 @cindex @samp{r} in constraint
1173 @cindex registers in constraints
1175 A register operand is allowed provided that it is in a general
1178 @cindex constants in constraints
1179 @cindex @samp{i} in constraint
1181 An immediate integer operand (one with constant value) is allowed.
1182 This includes symbolic constants whose values will be known only at
1183 assembly time or later.
1185 @cindex @samp{n} in constraint
1187 An immediate integer operand with a known numeric value is allowed.
1188 Many systems cannot support assembly-time constants for operands less
1189 than a word wide. Constraints for these operands should use @samp{n}
1190 rather than @samp{i}.
1192 @cindex @samp{I} in constraint
1193 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1194 Other letters in the range @samp{I} through @samp{P} may be defined in
1195 a machine-dependent fashion to permit immediate integer operands with
1196 explicit integer values in specified ranges. For example, on the
1197 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1198 This is the range permitted as a shift count in the shift
1201 @cindex @samp{E} in constraint
1203 An immediate floating operand (expression code @code{const_double}) is
1204 allowed, but only if the target floating point format is the same as
1205 that of the host machine (on which the compiler is running).
1207 @cindex @samp{F} in constraint
1209 An immediate floating operand (expression code @code{const_double} or
1210 @code{const_vector}) is allowed.
1212 @cindex @samp{G} in constraint
1213 @cindex @samp{H} in constraint
1214 @item @samp{G}, @samp{H}
1215 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1216 permit immediate floating operands in particular ranges of values.
1218 @cindex @samp{s} in constraint
1220 An immediate integer operand whose value is not an explicit integer is
1223 This might appear strange; if an insn allows a constant operand with a
1224 value not known at compile time, it certainly must allow any known
1225 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1226 better code to be generated.
1228 For example, on the 68000 in a fullword instruction it is possible to
1229 use an immediate operand; but if the immediate value is between @minus{}128
1230 and 127, better code results from loading the value into a register and
1231 using the register. This is because the load into the register can be
1232 done with a @samp{moveq} instruction. We arrange for this to happen
1233 by defining the letter @samp{K} to mean ``any integer outside the
1234 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1237 @cindex @samp{g} in constraint
1239 Any register, memory or immediate integer operand is allowed, except for
1240 registers that are not general registers.
1242 @cindex @samp{X} in constraint
1245 Any operand whatsoever is allowed, even if it does not satisfy
1246 @code{general_operand}. This is normally used in the constraint of
1247 a @code{match_scratch} when certain alternatives will not actually
1248 require a scratch register.
1251 Any operand whatsoever is allowed.
1254 @cindex @samp{0} in constraint
1255 @cindex digits in constraint
1256 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1257 An operand that matches the specified operand number is allowed. If a
1258 digit is used together with letters within the same alternative, the
1259 digit should come last.
1261 This number is allowed to be more than a single digit. If multiple
1262 digits are encountered consecutively, they are interpreted as a single
1263 decimal integer. There is scant chance for ambiguity, since to-date
1264 it has never been desirable that @samp{10} be interpreted as matching
1265 either operand 1 @emph{or} operand 0. Should this be desired, one
1266 can use multiple alternatives instead.
1268 @cindex matching constraint
1269 @cindex constraint, matching
1270 This is called a @dfn{matching constraint} and what it really means is
1271 that the assembler has only a single operand that fills two roles
1273 considered separate in the RTL insn. For example, an add insn has two
1274 input operands and one output operand in the RTL, but on most CISC
1277 which @code{asm} distinguishes. For example, an add instruction uses
1278 two input operands and an output operand, but on most CISC
1280 machines an add instruction really has only two operands, one of them an
1281 input-output operand:
1287 Matching constraints are used in these circumstances.
1288 More precisely, the two operands that match must include one input-only
1289 operand and one output-only operand. Moreover, the digit must be a
1290 smaller number than the number of the operand that uses it in the
1294 For operands to match in a particular case usually means that they
1295 are identical-looking RTL expressions. But in a few special cases
1296 specific kinds of dissimilarity are allowed. For example, @code{*x}
1297 as an input operand will match @code{*x++} as an output operand.
1298 For proper results in such cases, the output template should always
1299 use the output-operand's number when printing the operand.
1302 @cindex load address instruction
1303 @cindex push address instruction
1304 @cindex address constraints
1305 @cindex @samp{p} in constraint
1307 An operand that is a valid memory address is allowed. This is
1308 for ``load address'' and ``push address'' instructions.
1310 @findex address_operand
1311 @samp{p} in the constraint must be accompanied by @code{address_operand}
1312 as the predicate in the @code{match_operand}. This predicate interprets
1313 the mode specified in the @code{match_operand} as the mode of the memory
1314 reference for which the address would be valid.
1316 @cindex other register constraints
1317 @cindex extensible constraints
1318 @item @var{other-letters}
1319 Other letters can be defined in machine-dependent fashion to stand for
1320 particular classes of registers or other arbitrary operand types.
1321 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1322 for data, address and floating point registers.
1326 In order to have valid assembler code, each operand must satisfy
1327 its constraint. But a failure to do so does not prevent the pattern
1328 from applying to an insn. Instead, it directs the compiler to modify
1329 the code so that the constraint will be satisfied. Usually this is
1330 done by copying an operand into a register.
1332 Contrast, therefore, the two instruction patterns that follow:
1336 [(set (match_operand:SI 0 "general_operand" "=r")
1337 (plus:SI (match_dup 0)
1338 (match_operand:SI 1 "general_operand" "r")))]
1344 which has two operands, one of which must appear in two places, and
1348 [(set (match_operand:SI 0 "general_operand" "=r")
1349 (plus:SI (match_operand:SI 1 "general_operand" "0")
1350 (match_operand:SI 2 "general_operand" "r")))]
1356 which has three operands, two of which are required by a constraint to be
1357 identical. If we are considering an insn of the form
1360 (insn @var{n} @var{prev} @var{next}
1362 (plus:SI (reg:SI 6) (reg:SI 109)))
1367 the first pattern would not apply at all, because this insn does not
1368 contain two identical subexpressions in the right place. The pattern would
1369 say, ``That does not look like an add instruction; try other patterns''.
1370 The second pattern would say, ``Yes, that's an add instruction, but there
1371 is something wrong with it''. It would direct the reload pass of the
1372 compiler to generate additional insns to make the constraint true. The
1373 results might look like this:
1376 (insn @var{n2} @var{prev} @var{n}
1377 (set (reg:SI 3) (reg:SI 6))
1380 (insn @var{n} @var{n2} @var{next}
1382 (plus:SI (reg:SI 3) (reg:SI 109)))
1386 It is up to you to make sure that each operand, in each pattern, has
1387 constraints that can handle any RTL expression that could be present for
1388 that operand. (When multiple alternatives are in use, each pattern must,
1389 for each possible combination of operand expressions, have at least one
1390 alternative which can handle that combination of operands.) The
1391 constraints don't need to @emph{allow} any possible operand---when this is
1392 the case, they do not constrain---but they must at least point the way to
1393 reloading any possible operand so that it will fit.
1397 If the constraint accepts whatever operands the predicate permits,
1398 there is no problem: reloading is never necessary for this operand.
1400 For example, an operand whose constraints permit everything except
1401 registers is safe provided its predicate rejects registers.
1403 An operand whose predicate accepts only constant values is safe
1404 provided its constraints include the letter @samp{i}. If any possible
1405 constant value is accepted, then nothing less than @samp{i} will do;
1406 if the predicate is more selective, then the constraints may also be
1410 Any operand expression can be reloaded by copying it into a register.
1411 So if an operand's constraints allow some kind of register, it is
1412 certain to be safe. It need not permit all classes of registers; the
1413 compiler knows how to copy a register into another register of the
1414 proper class in order to make an instruction valid.
1416 @cindex nonoffsettable memory reference
1417 @cindex memory reference, nonoffsettable
1419 A nonoffsettable memory reference can be reloaded by copying the
1420 address into a register. So if the constraint uses the letter
1421 @samp{o}, all memory references are taken care of.
1424 A constant operand can be reloaded by allocating space in memory to
1425 hold it as preinitialized data. Then the memory reference can be used
1426 in place of the constant. So if the constraint uses the letters
1427 @samp{o} or @samp{m}, constant operands are not a problem.
1430 If the constraint permits a constant and a pseudo register used in an insn
1431 was not allocated to a hard register and is equivalent to a constant,
1432 the register will be replaced with the constant. If the predicate does
1433 not permit a constant and the insn is re-recognized for some reason, the
1434 compiler will crash. Thus the predicate must always recognize any
1435 objects allowed by the constraint.
1438 If the operand's predicate can recognize registers, but the constraint does
1439 not permit them, it can make the compiler crash. When this operand happens
1440 to be a register, the reload pass will be stymied, because it does not know
1441 how to copy a register temporarily into memory.
1443 If the predicate accepts a unary operator, the constraint applies to the
1444 operand. For example, the MIPS processor at ISA level 3 supports an
1445 instruction which adds two registers in @code{SImode} to produce a
1446 @code{DImode} result, but only if the registers are correctly sign
1447 extended. This predicate for the input operands accepts a
1448 @code{sign_extend} of an @code{SImode} register. Write the constraint
1449 to indicate the type of register that is required for the operand of the
1453 @node Multi-Alternative
1454 @subsection Multiple Alternative Constraints
1455 @cindex multiple alternative constraints
1457 Sometimes a single instruction has multiple alternative sets of possible
1458 operands. For example, on the 68000, a logical-or instruction can combine
1459 register or an immediate value into memory, or it can combine any kind of
1460 operand into a register; but it cannot combine one memory location into
1463 These constraints are represented as multiple alternatives. An alternative
1464 can be described by a series of letters for each operand. The overall
1465 constraint for an operand is made from the letters for this operand
1466 from the first alternative, a comma, the letters for this operand from
1467 the second alternative, a comma, and so on until the last alternative.
1469 Here is how it is done for fullword logical-or on the 68000:
1472 (define_insn "iorsi3"
1473 [(set (match_operand:SI 0 "general_operand" "=m,d")
1474 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1475 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1479 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1480 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1481 2. The second alternative has @samp{d} (data register) for operand 0,
1482 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1483 @samp{%} in the constraints apply to all the alternatives; their
1484 meaning is explained in the next section (@pxref{Class Preferences}).
1487 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1488 If all the operands fit any one alternative, the instruction is valid.
1489 Otherwise, for each alternative, the compiler counts how many instructions
1490 must be added to copy the operands so that that alternative applies.
1491 The alternative requiring the least copying is chosen. If two alternatives
1492 need the same amount of copying, the one that comes first is chosen.
1493 These choices can be altered with the @samp{?} and @samp{!} characters:
1496 @cindex @samp{?} in constraint
1497 @cindex question mark
1499 Disparage slightly the alternative that the @samp{?} appears in,
1500 as a choice when no alternative applies exactly. The compiler regards
1501 this alternative as one unit more costly for each @samp{?} that appears
1504 @cindex @samp{!} in constraint
1505 @cindex exclamation point
1507 Disparage severely the alternative that the @samp{!} appears in.
1508 This alternative can still be used if it fits without reloading,
1509 but if reloading is needed, some other alternative will be used.
1511 @cindex @samp{^} in constraint
1514 This constraint is analogous to @samp{?} but it disparages slightly
1515 the alternative only if the operand with the @samp{^} needs a reload.
1517 @cindex @samp{$} in constraint
1520 This constraint is analogous to @samp{!} but it disparages severely
1521 the alternative only if the operand with the @samp{$} needs a reload.
1525 When an insn pattern has multiple alternatives in its constraints, often
1526 the appearance of the assembler code is determined mostly by which
1527 alternative was matched. When this is so, the C code for writing the
1528 assembler code can use the variable @code{which_alternative}, which is
1529 the ordinal number of the alternative that was actually satisfied (0 for
1530 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1534 @node Class Preferences
1535 @subsection Register Class Preferences
1536 @cindex class preference constraints
1537 @cindex register class preference constraints
1539 @cindex voting between constraint alternatives
1540 The operand constraints have another function: they enable the compiler
1541 to decide which kind of hardware register a pseudo register is best
1542 allocated to. The compiler examines the constraints that apply to the
1543 insns that use the pseudo register, looking for the machine-dependent
1544 letters such as @samp{d} and @samp{a} that specify classes of registers.
1545 The pseudo register is put in whichever class gets the most ``votes''.
1546 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1547 favor of a general register. The machine description says which registers
1548 are considered general.
1550 Of course, on some machines all registers are equivalent, and no register
1551 classes are defined. Then none of this complexity is relevant.
1555 @subsection Constraint Modifier Characters
1556 @cindex modifiers in constraints
1557 @cindex constraint modifier characters
1559 @c prevent bad page break with this line
1560 Here are constraint modifier characters.
1563 @cindex @samp{=} in constraint
1565 Means that this operand is written to by this instruction:
1566 the previous value is discarded and replaced by new data.
1568 @cindex @samp{+} in constraint
1570 Means that this operand is both read and written by the instruction.
1572 When the compiler fixes up the operands to satisfy the constraints,
1573 it needs to know which operands are read by the instruction and
1574 which are written by it. @samp{=} identifies an operand which is only
1575 written; @samp{+} identifies an operand that is both read and written; all
1576 other operands are assumed to only be read.
1578 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1579 first character of the constraint string.
1581 @cindex @samp{&} in constraint
1582 @cindex earlyclobber operand
1584 Means (in a particular alternative) that this operand is an
1585 @dfn{earlyclobber} operand, which is written before the instruction is
1586 finished using the input operands. Therefore, this operand may not lie
1587 in a register that is read by the instruction or as part of any memory
1590 @samp{&} applies only to the alternative in which it is written. In
1591 constraints with multiple alternatives, sometimes one alternative
1592 requires @samp{&} while others do not. See, for example, the
1593 @samp{movdf} insn of the 68000.
1595 A operand which is read by the instruction can be tied to an earlyclobber
1596 operand if its only use as an input occurs before the early result is
1597 written. Adding alternatives of this form often allows GCC to produce
1598 better code when only some of the read operands can be affected by the
1599 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1601 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1602 operand, then that operand is written only after it's used.
1604 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1605 @dfn{earlyclobber} operands are always written, a read-only
1606 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1609 @cindex @samp{%} in constraint
1611 Declares the instruction to be commutative for this operand and the
1612 following operand. This means that the compiler may interchange the
1613 two operands if that is the cheapest way to make all operands fit the
1614 constraints. @samp{%} applies to all alternatives and must appear as
1615 the first character in the constraint. Only read-only operands can use
1619 This is often used in patterns for addition instructions
1620 that really have only two operands: the result must go in one of the
1621 arguments. Here for example, is how the 68000 halfword-add
1622 instruction is defined:
1625 (define_insn "addhi3"
1626 [(set (match_operand:HI 0 "general_operand" "=m,r")
1627 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1628 (match_operand:HI 2 "general_operand" "di,g")))]
1632 GCC can only handle one commutative pair in an asm; if you use more,
1633 the compiler may fail. Note that you need not use the modifier if
1634 the two alternatives are strictly identical; this would only waste
1635 time in the reload pass. The modifier is not operational after
1636 register allocation, so the result of @code{define_peephole2}
1637 and @code{define_split}s performed after reload cannot rely on
1638 @samp{%} to make the intended insn match.
1640 @cindex @samp{#} in constraint
1642 Says that all following characters, up to the next comma, are to be
1643 ignored as a constraint. They are significant only for choosing
1644 register preferences.
1646 @cindex @samp{*} in constraint
1648 Says that the following character should be ignored when choosing
1649 register preferences. @samp{*} has no effect on the meaning of the
1650 constraint as a constraint, and no effect on reloading. For LRA
1651 @samp{*} additionally disparages slightly the alternative if the
1652 following character matches the operand.
1655 Here is an example: the 68000 has an instruction to sign-extend a
1656 halfword in a data register, and can also sign-extend a value by
1657 copying it into an address register. While either kind of register is
1658 acceptable, the constraints on an address-register destination are
1659 less strict, so it is best if register allocation makes an address
1660 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1661 constraint letter (for data register) is ignored when computing
1662 register preferences.
1665 (define_insn "extendhisi2"
1666 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1668 (match_operand:HI 1 "general_operand" "0,g")))]
1674 @node Machine Constraints
1675 @subsection Constraints for Particular Machines
1676 @cindex machine specific constraints
1677 @cindex constraints, machine specific
1679 Whenever possible, you should use the general-purpose constraint letters
1680 in @code{asm} arguments, since they will convey meaning more readily to
1681 people reading your code. Failing that, use the constraint letters
1682 that usually have very similar meanings across architectures. The most
1683 commonly used constraints are @samp{m} and @samp{r} (for memory and
1684 general-purpose registers respectively; @pxref{Simple Constraints}), and
1685 @samp{I}, usually the letter indicating the most common
1686 immediate-constant format.
1688 Each architecture defines additional constraints. These constraints
1689 are used by the compiler itself for instruction generation, as well as
1690 for @code{asm} statements; therefore, some of the constraints are not
1691 particularly useful for @code{asm}. Here is a summary of some of the
1692 machine-dependent constraints available on some particular machines;
1693 it includes both constraints that are useful for @code{asm} and
1694 constraints that aren't. The compiler source file mentioned in the
1695 table heading for each architecture is the definitive reference for
1696 the meanings of that architecture's constraints.
1698 @c Please keep this table alphabetized by target!
1700 @item AArch64 family---@file{config/aarch64/constraints.md}
1703 The stack pointer register (@code{SP})
1706 Floating point or SIMD vector register
1709 Integer constant that is valid as an immediate operand in an @code{ADD}
1713 Integer constant that is valid as an immediate operand in a @code{SUB}
1714 instruction (once negated)
1717 Integer constant that can be used with a 32-bit logical instruction
1720 Integer constant that can be used with a 64-bit logical instruction
1723 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1724 pseudo instruction. The @code{MOV} may be assembled to one of several different
1725 machine instructions depending on the value
1728 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1732 An absolute symbolic address or a label reference
1735 Floating point constant zero
1738 Integer constant zero
1741 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1742 within 4GB of the instruction
1745 A memory address which uses a single base register with no offset
1748 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1754 @item ARC ---@file{config/arc/constraints.md}
1757 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1758 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1759 option is in effect.
1762 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1763 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1764 This constraint can only match when the @option{-mq}
1765 option is in effect.
1767 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1770 A signed 12-bit integer constant.
1773 constant for arithmetic/logical operations. This might be any constant
1774 that can be put into a long immediate by the assmbler or linker without
1775 involving a PIC relocation.
1778 A 3-bit unsigned integer constant.
1781 A 6-bit unsigned integer constant.
1784 One's complement of a 6-bit unsigned integer constant.
1787 Two's complement of a 6-bit unsigned integer constant.
1790 A 5-bit unsigned integer constant.
1793 A 7-bit unsigned integer constant.
1796 A 8-bit unsigned integer constant.
1799 Any const_double value.
1802 @item ARM family---@file{config/arm/constraints.md}
1806 In Thumb state, the core registers @code{r8}-@code{r15}.
1809 The stack pointer register.
1812 In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this
1813 is an alias for the @code{r} constraint.
1816 VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values.
1819 VFP floating-point registers @code{d0}-@code{d31} and the appropriate
1820 subset @code{d0}-@code{d15} based on command line options.
1821 Used for 64 bit values only. Not valid for Thumb1.
1824 The iWMMX co-processor registers.
1827 The iWMMX GR registers.
1830 The floating-point constant 0.0
1833 Integer that is valid as an immediate operand in a data processing
1834 instruction. That is, an integer in the range 0 to 255 rotated by a
1838 Integer in the range @minus{}4095 to 4095
1841 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1844 Integer that satisfies constraint @samp{I} when negated (twos complement)
1847 Integer in the range 0 to 32
1850 A memory reference where the exact address is in a single register
1851 (`@samp{m}' is preferable for @code{asm} statements)
1854 An item in the constant pool
1857 A symbol in the text segment of the current file
1860 A memory reference suitable for VFP load/store insns (reg+constant offset)
1863 A memory reference suitable for iWMMXt load/store instructions.
1866 A memory reference suitable for the ARMv4 ldrsb instruction.
1869 @item AVR family---@file{config/avr/constraints.md}
1872 Registers from r0 to r15
1875 Registers from r16 to r23
1878 Registers from r16 to r31
1881 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1884 Pointer register (r26--r31)
1887 Base pointer register (r28--r31)
1890 Stack pointer register (SPH:SPL)
1893 Temporary register r0
1896 Register pair X (r27:r26)
1899 Register pair Y (r29:r28)
1902 Register pair Z (r31:r30)
1905 Constant greater than @minus{}1, less than 64
1908 Constant greater than @minus{}64, less than 1
1917 Constant that fits in 8 bits
1920 Constant integer @minus{}1
1923 Constant integer 8, 16, or 24
1929 A floating point constant 0.0
1932 A memory address based on Y or Z pointer with displacement.
1935 @item Blackfin family---@file{config/bfin/constraints.md}
1944 A call clobbered P register.
1947 A single register. If @var{n} is in the range 0 to 7, the corresponding D
1948 register. If it is @code{A}, then the register P0.
1951 Even-numbered D register
1954 Odd-numbered D register
1957 Accumulator register.
1960 Even-numbered accumulator register.
1963 Odd-numbered accumulator register.
1975 Registers used for circular buffering, i.e. I, B, or L registers.
1990 Any D, P, B, M, I or L register.
1993 Additional registers typically used only in prologues and epilogues: RETS,
1994 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
1997 Any register except accumulators or CC.
2000 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2003 Unsigned 16 bit integer (in the range 0 to 65535)
2006 Signed 7 bit integer (in the range @minus{}64 to 63)
2009 Unsigned 7 bit integer (in the range 0 to 127)
2012 Unsigned 5 bit integer (in the range 0 to 31)
2015 Signed 4 bit integer (in the range @minus{}8 to 7)
2018 Signed 3 bit integer (in the range @minus{}3 to 4)
2021 Unsigned 3 bit integer (in the range 0 to 7)
2024 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2027 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2028 use with either accumulator.
2031 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2032 use only with accumulator A1.
2041 An integer constant with exactly a single bit set.
2044 An integer constant with all bits set except exactly one.
2052 @item CR16 Architecture---@file{config/cr16/cr16.h}
2056 Registers from r0 to r14 (registers without stack pointer)
2059 Register from r0 to r11 (all 16-bit registers)
2062 Register from r12 to r15 (all 32-bit registers)
2065 Signed constant that fits in 4 bits
2068 Signed constant that fits in 5 bits
2071 Signed constant that fits in 6 bits
2074 Unsigned constant that fits in 4 bits
2077 Signed constant that fits in 32 bits
2080 Check for 64 bits wide constants for add/sub instructions
2083 Floating point constant that is legal for store immediate
2086 @item Epiphany---@file{config/epiphany/constraints.md}
2089 An unsigned 16-bit constant.
2092 An unsigned 5-bit constant.
2095 A signed 11-bit constant.
2098 A signed 11-bit constant added to @minus{}1.
2099 Can only match when the @option{-m1reg-@var{reg}} option is active.
2102 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
2103 being a block of trailing zeroes.
2104 Can only match when the @option{-m1reg-@var{reg}} option is active.
2107 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
2108 rest being zeroes. Or to put it another way, one less than a power of two.
2109 Can only match when the @option{-m1reg-@var{reg}} option is active.
2112 Constant for arithmetic/logical operations.
2113 This is like @code{i}, except that for position independent code,
2114 no symbols / expressions needing relocations are allowed.
2117 Symbolic constant for call/jump instruction.
2120 The register class usable in short insns. This is a register class
2121 constraint, and can thus drive register allocation.
2122 This constraint won't match unless @option{-mprefer-short-insn-regs} is
2126 The the register class of registers that can be used to hold a
2127 sibcall call address. I.e., a caller-saved register.
2130 Core control register class.
2133 The register group usable in short insns.
2134 This constraint does not use a register class, so that it only
2135 passively matches suitable registers, and doesn't drive register allocation.
2139 Constant suitable for the addsi3_r pattern. This is a valid offset
2140 For byte, halfword, or word addressing.
2144 Matches the return address if it can be replaced with the link register.
2147 Matches the integer condition code register.
2150 Matches the return address if it is in a stack slot.
2153 Matches control register values to switch fp mode, which are encapsulated in
2154 @code{UNSPEC_FP_MODE}.
2157 @item FRV---@file{config/frv/frv.h}
2160 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2163 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2166 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2167 @code{icc0} to @code{icc3}).
2170 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2173 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2174 Odd registers are excluded not in the class but through the use of a machine
2175 mode larger than 4 bytes.
2178 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2181 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2182 Odd registers are excluded not in the class but through the use of a machine
2183 mode larger than 4 bytes.
2186 Register in the class @code{LR_REG} (the @code{lr} register).
2189 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2190 Register numbers not divisible by 4 are excluded not in the class but through
2191 the use of a machine mode larger than 8 bytes.
2194 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2197 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2200 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2203 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2206 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2207 Register numbers not divisible by 4 are excluded not in the class but through
2208 the use of a machine mode larger than 8 bytes.
2211 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2214 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2217 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2220 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2223 Floating point constant zero
2226 6-bit signed integer constant
2229 10-bit signed integer constant
2232 16-bit signed integer constant
2235 16-bit unsigned integer constant
2238 12-bit signed integer constant that is negative---i.e.@: in the
2239 range of @minus{}2048 to @minus{}1
2245 12-bit signed integer constant that is greater than zero---i.e.@: in the
2250 @item FT32---@file{config/ft32/constraints.md}
2259 A register indirect memory operand
2268 The constant zero or one
2271 A 16-bit signed constant (@minus{}32768 @dots{} 32767)
2274 A bitfield mask suitable for bext or bins
2277 An inverted bitfield mask suitable for bext or bins
2280 A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532)
2283 A 20-bit signed constant (@minus{}524288 @dots{} 524287)
2286 A constant for a bitfield width (1 @dots{} 16)
2289 A 10-bit signed constant (@minus{}512 @dots{} 511)
2293 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2299 Floating point register
2302 Shift amount register
2305 Floating point register (deprecated)
2308 Upper floating point register (32-bit), floating point register (64-bit)
2314 Signed 11-bit integer constant
2317 Signed 14-bit integer constant
2320 Integer constant that can be deposited with a @code{zdepi} instruction
2323 Signed 5-bit integer constant
2329 Integer constant that can be loaded with a @code{ldil} instruction
2332 Integer constant whose value plus one is a power of 2
2335 Integer constant that can be used for @code{and} operations in @code{depi}
2336 and @code{extru} instructions
2345 Floating-point constant 0.0
2348 A @code{lo_sum} data-linkage-table memory operand
2351 A memory operand that can be used as the destination operand of an
2352 integer store instruction
2355 A scaled or unscaled indexed memory operand
2358 A memory operand for floating-point loads and stores
2361 A register indirect memory operand
2364 @item Intel IA-64---@file{config/ia64/ia64.h}
2367 General register @code{r0} to @code{r3} for @code{addl} instruction
2373 Predicate register (@samp{c} as in ``conditional'')
2376 Application register residing in M-unit
2379 Application register residing in I-unit
2382 Floating-point register
2385 Memory operand. If used together with @samp{<} or @samp{>},
2386 the operand can have postincrement and postdecrement which
2387 require printing with @samp{%Pn} on IA-64.
2390 Floating-point constant 0.0 or 1.0
2393 14-bit signed integer constant
2396 22-bit signed integer constant
2399 8-bit signed integer constant for logical instructions
2402 8-bit adjusted signed integer constant for compare pseudo-ops
2405 6-bit unsigned integer constant for shift counts
2408 9-bit signed integer constant for load and store postincrements
2414 0 or @minus{}1 for @code{dep} instruction
2417 Non-volatile memory for floating-point loads and stores
2420 Integer constant in the range 1 to 4 for @code{shladd} instruction
2423 Memory operand except postincrement and postdecrement. This is
2424 now roughly the same as @samp{m} when not used together with @samp{<}
2428 @item M32C---@file{config/m32c/m32c.c}
2433 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2436 Any control register, when they're 16 bits wide (nothing if control
2437 registers are 24 bits wide)
2440 Any control register, when they're 24 bits wide.
2449 $r0 or $r2, or $r2r0 for 32 bit values.
2452 $r1 or $r3, or $r3r1 for 32 bit values.
2455 A register that can hold a 64 bit value.
2458 $r0 or $r1 (registers with addressable high/low bytes)
2467 Address registers when they're 16 bits wide.
2470 Address registers when they're 24 bits wide.
2473 Registers that can hold QI values.
2476 Registers that can be used with displacements ($a0, $a1, $sb).
2479 Registers that can hold 32 bit values.
2482 Registers that can hold 16 bit values.
2485 Registers chat can hold 16 bit values, including all control
2489 $r0 through R1, plus $a0 and $a1.
2495 The memory-based pseudo-registers $mem0 through $mem15.
2498 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2499 bit registers for m32cm, m32c).
2502 Matches multiple registers in a PARALLEL to form a larger register.
2503 Used to match function return values.
2509 @minus{}128 @dots{} 127
2512 @minus{}32768 @dots{} 32767
2518 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2521 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2524 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2527 @minus{}65536 @dots{} @minus{}1
2530 An 8 bit value with exactly one bit set.
2533 A 16 bit value with exactly one bit set.
2536 The common src/dest memory addressing modes.
2539 Memory addressed using $a0 or $a1.
2542 Memory addressed with immediate addresses.
2545 Memory addressed using the stack pointer ($sp).
2548 Memory addressed using the frame base register ($fb).
2551 Memory addressed using the small base register ($sb).
2557 @item MeP---@file{config/mep/constraints.md}
2567 Any control register.
2570 Either the $hi or the $lo register.
2573 Coprocessor registers that can be directly loaded ($c0-$c15).
2576 Coprocessor registers that can be moved to each other.
2579 Coprocessor registers that can be moved to core registers.
2591 Registers which can be used in $tp-relative addressing.
2597 The coprocessor registers.
2600 The coprocessor control registers.
2606 User-defined register set A.
2609 User-defined register set B.
2612 User-defined register set C.
2615 User-defined register set D.
2618 Offsets for $gp-rel addressing.
2621 Constants that can be used directly with boolean insns.
2624 Constants that can be moved directly to registers.
2627 Small constants that can be added to registers.
2633 Small constants that can be compared to registers.
2636 Constants that can be loaded into the top half of registers.
2639 Signed 8-bit immediates.
2642 Symbols encoded for $tp-rel or $gp-rel addressing.
2645 Non-constant addresses for loading/saving coprocessor registers.
2648 The top half of a symbol's value.
2651 A register indirect address without offset.
2654 Symbolic references to the control bus.
2658 @item MicroBlaze---@file{config/microblaze/constraints.md}
2661 A general register (@code{r0} to @code{r31}).
2664 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2668 @item MIPS---@file{config/mips/constraints.md}
2671 An address register. This is equivalent to @code{r} unless
2672 generating MIPS16 code.
2675 A floating-point register (if available).
2678 Formerly the @code{hi} register. This constraint is no longer supported.
2681 The @code{lo} register. Use this register to store values that are
2682 no bigger than a word.
2685 The concatenated @code{hi} and @code{lo} registers. Use this register
2686 to store doubleword values.
2689 A register suitable for use in an indirect jump. This will always be
2690 @code{$25} for @option{-mabicalls}.
2693 Register @code{$3}. Do not use this constraint in new code;
2694 it is retained only for compatibility with glibc.
2697 Equivalent to @code{r}; retained for backwards compatibility.
2700 A floating-point condition code register.
2703 A signed 16-bit constant (for arithmetic instructions).
2709 An unsigned 16-bit constant (for logic instructions).
2712 A signed 32-bit constant in which the lower 16 bits are zero.
2713 Such constants can be loaded using @code{lui}.
2716 A constant that cannot be loaded using @code{lui}, @code{addiu}
2720 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2723 A signed 15-bit constant.
2726 A constant in the range 1 to 65535 (inclusive).
2729 Floating-point zero.
2732 An address that can be used in a non-macro load or store.
2735 A memory operand whose address is formed by a base register and offset
2736 that is suitable for use in instructions with the same addressing mode
2737 as @code{ll} and @code{sc}.
2740 An address suitable for a @code{prefetch} instruction, or for any other
2741 instruction with the same addressing mode as @code{prefetch}.
2744 @item Motorola 680x0---@file{config/m68k/constraints.md}
2753 68881 floating-point register, if available
2756 Integer in the range 1 to 8
2759 16-bit signed number
2762 Signed number whose magnitude is greater than 0x80
2765 Integer in the range @minus{}8 to @minus{}1
2768 Signed number whose magnitude is greater than 0x100
2771 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2774 16 (for rotate using swap)
2777 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2780 Numbers that mov3q can handle
2783 Floating point constant that is not a 68881 constant
2786 Operands that satisfy 'm' when -mpcrel is in effect
2789 Operands that satisfy 's' when -mpcrel is not in effect
2792 Address register indirect addressing mode
2795 Register offset addressing
2810 Range of signed numbers that don't fit in 16 bits
2813 Integers valid for mvq
2816 Integers valid for a moveq followed by a swap
2819 Integers valid for mvz
2822 Integers valid for mvs
2828 Non-register operands allowed in clr
2832 @item Moxie---@file{config/moxie/constraints.md}
2841 A register indirect memory operand
2844 A constant in the range of 0 to 255.
2847 A constant in the range of 0 to @minus{}255.
2851 @item MSP430--@file{config/msp430/constraints.md}
2864 Integer constant -1^20..1^19.
2867 Integer constant 1-4.
2870 Memory references which do not require an extended MOVX instruction.
2873 Memory reference, labels only.
2876 Memory reference, stack only.
2880 @item NDS32---@file{config/nds32/constraints.md}
2883 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
2885 LOW register class $r0 to $r7.
2887 MIDDLE register class $r0 to $r11, $r16 to $r19.
2889 HIGH register class $r12 to $r14, $r20 to $r31.
2891 Temporary assist register $ta (i.e.@: $r15).
2895 Unsigned immediate 3-bit value.
2897 Negative immediate 3-bit value in the range of @minus{}7--0.
2899 Unsigned immediate 4-bit value.
2901 Signed immediate 5-bit value.
2903 Unsigned immediate 5-bit value.
2905 Negative immediate 5-bit value in the range of @minus{}31--0.
2907 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
2909 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
2911 Unsigned immediate 8-bit value.
2913 Unsigned immediate 9-bit value.
2915 Signed immediate 10-bit value.
2917 Signed immediate 11-bit value.
2919 Signed immediate 15-bit value.
2921 Unsigned immediate 15-bit value.
2923 A constant which is not in the range of imm15u but ok for bclr instruction.
2925 A constant which is not in the range of imm15u but ok for bset instruction.
2927 A constant which is not in the range of imm15u but ok for btgl instruction.
2929 A constant whose compliment value is in the range of imm15u
2930 and ok for bitci instruction.
2932 Signed immediate 16-bit value.
2934 Signed immediate 17-bit value.
2936 Signed immediate 19-bit value.
2938 Signed immediate 20-bit value.
2940 The immediate value that can be simply set high 20-bit.
2942 The immediate value 0xff.
2944 The immediate value 0xffff.
2946 The immediate value 0x01.
2948 The immediate value 0x7ff.
2950 The immediate value with power of 2.
2952 The immediate value with power of 2 minus 1.
2954 Memory constraint for 333 format.
2956 Memory constraint for 45 format.
2958 Memory constraint for 37 format.
2961 @item Nios II family---@file{config/nios2/constraints.md}
2965 Integer that is valid as an immediate operand in an
2966 instruction taking a signed 16-bit number. Range
2967 @minus{}32768 to 32767.
2970 Integer that is valid as an immediate operand in an
2971 instruction taking an unsigned 16-bit number. Range
2975 Integer that is valid as an immediate operand in an
2976 instruction taking only the upper 16-bits of a
2977 32-bit number. Range 32-bit numbers with the lower
2981 Integer that is valid as an immediate operand for a
2982 shift instruction. Range 0 to 31.
2985 Integer that is valid as an immediate operand for
2986 only the value 0. Can be used in conjunction with
2987 the format modifier @code{z} to use @code{r0}
2988 instead of @code{0} in the assembly output.
2991 Integer that is valid as an immediate operand for
2992 a custom instruction opcode. Range 0 to 255.
2995 An immediate operand for R2 andchi/andci instructions.
2998 Matches immediates which are addresses in the small
2999 data section and therefore can be added to @code{gp}
3000 as a 16-bit immediate to re-create their 32-bit value.
3003 Matches constants suitable as an operand for the rdprs and
3007 A memory operand suitable for Nios II R2 load/store
3008 exclusive instructions.
3011 A memory operand suitable for load/store IO and cache
3016 A @code{const} wrapped @code{UNSPEC} expression,
3017 representing a supported PIC or TLS relocation.
3022 @item PDP-11---@file{config/pdp11/constraints.md}
3025 Floating point registers AC0 through AC3. These can be loaded from/to
3026 memory with a single instruction.
3029 Odd numbered general registers (R1, R3, R5). These are used for
3030 16-bit multiply operations.
3033 Any of the floating point registers (AC0 through AC5).
3036 Floating point constant 0.
3039 An integer constant that fits in 16 bits.
3042 An integer constant whose low order 16 bits are zero.
3045 An integer constant that does not meet the constraints for codes
3046 @samp{I} or @samp{J}.
3049 The integer constant 1.
3052 The integer constant @minus{}1.
3055 The integer constant 0.
3058 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
3059 amounts are handled as multiple single-bit shifts rather than a single
3060 variable-length shift.
3063 A memory reference which requires an additional word (address or
3064 offset) after the opcode.
3067 A memory reference that is encoded within the opcode.
3071 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
3074 Address base register
3077 Floating point register (containing 64-bit value)
3080 Floating point register (containing 32-bit value)
3083 Altivec vector register
3086 Any VSX register if the -mvsx option was used or NO_REGS.
3088 When using any of the register constraints (@code{wa}, @code{wd},
3089 @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
3090 @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, @code{wt},
3091 @code{wu}, @code{wv}, @code{ww}, or @code{wy})
3092 that take VSX registers, you must use @code{%x<n>} in the template so
3093 that the correct register is used. Otherwise the register number
3094 output in the assembly file will be incorrect if an Altivec register
3095 is an operand of a VSX instruction that expects VSX register
3099 asm ("xvadddp %x0,%x1,%x2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
3105 asm ("xvadddp %0,%1,%2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
3111 VSX vector register to hold vector double data or NO_REGS.
3114 VSX vector register to hold vector float data or NO_REGS.
3117 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
3120 Floating point register if direct moves are available, or NO_REGS.
3123 FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
3126 FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
3129 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
3132 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
3135 VSX register if direct move instructions are enabled, or NO_REGS.
3138 No register (NO_REGS).
3141 VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
3144 VSX register to use for IEEE 128-bit floating point, or NO_REGS.
3147 General purpose register if 64-bit instructions are enabled or NO_REGS.
3150 VSX vector register to hold scalar double values or NO_REGS.
3153 VSX vector register to hold 128 bit integer or NO_REGS.
3156 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
3159 Altivec register to use for double loads/stores or NO_REGS.
3162 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
3165 Floating point register if the STFIWX instruction is enabled or NO_REGS.
3168 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
3171 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
3174 Int constant that is the element number of the 64-bit scalar in a vector.
3177 A memory address that will work with the @code{lq} and @code{stq}
3181 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
3187 @samp{LINK} register
3190 @samp{CR} register (condition register) number 0
3193 @samp{CR} register (condition register)
3196 @samp{XER[CA]} carry bit (part of the XER register)
3199 Signed 16-bit constant
3202 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
3203 @code{SImode} constants)
3206 Unsigned 16-bit constant
3209 Signed 16-bit constant shifted left 16 bits
3212 Constant larger than 31
3221 Constant whose negation is a signed 16-bit constant
3224 Floating point constant that can be loaded into a register with one
3225 instruction per word
3228 Integer/Floating point constant that can be loaded into a register using
3233 Normally, @code{m} does not allow addresses that update the base register.
3234 If @samp{<} or @samp{>} constraint is also used, they are allowed and
3235 therefore on PowerPC targets in that case it is only safe
3236 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
3237 accesses the operand exactly once. The @code{asm} statement must also
3238 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
3239 corresponding load or store instruction. For example:
3242 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
3248 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
3254 A ``stable'' memory operand; that is, one which does not include any
3255 automodification of the base register. This used to be useful when
3256 @samp{m} allowed automodification of the base register, but as those are now only
3257 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
3258 as @samp{m} without @samp{<} and @samp{>}.
3261 Memory operand that is an offset from a register (it is usually better
3262 to use @samp{m} or @samp{es} in @code{asm} statements)
3265 Memory operand that is an indexed or indirect from a register (it is
3266 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
3272 Address operand that is an indexed or indirect from a register (@samp{p} is
3273 preferable for @code{asm} statements)
3276 System V Release 4 small data area reference
3279 Vector constant that does not require memory
3282 Vector constant that is all zeros.
3286 @item RL78---@file{config/rl78/constraints.md}
3290 An integer constant in the range 1 @dots{} 7.
3292 An integer constant in the range 0 @dots{} 255.
3294 An integer constant in the range @minus{}255 @dots{} 0
3296 The integer constant 1.
3298 The integer constant -1.
3300 The integer constant 0.
3302 The integer constant 2.
3304 The integer constant -2.
3306 An integer constant in the range 1 @dots{} 15.
3308 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3310 The synthetic compare types--gt, lt, ge, and le.
3312 A memory reference with an absolute address.
3314 A memory reference using @code{BC} as a base register, with an optional offset.
3316 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3318 A memory reference using any 16-bit register pair for the address, for calls.
3320 A memory reference using @code{DE} as a base register, with an optional offset.
3322 A memory reference using @code{DE} as a base register, without any offset.
3324 Any memory reference to an address in the far address space.
3326 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3328 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3330 A memory reference using @code{HL} as a base register, without any offset.
3332 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3334 Any memory reference to an address in the near address space.
3336 The @code{AX} register.
3338 The @code{BC} register.
3340 The @code{DE} register.
3342 @code{A} through @code{L} registers.
3344 The @code{SP} register.
3346 The @code{HL} register.
3348 The 16-bit @code{R8} register.
3350 The 16-bit @code{R10} register.
3352 The registers reserved for interrupts (@code{R24} to @code{R31}).
3354 The @code{A} register.
3356 The @code{B} register.
3358 The @code{C} register.
3360 The @code{D} register.
3362 The @code{E} register.
3364 The @code{H} register.
3366 The @code{L} register.
3368 The virtual registers.
3370 The @code{PSW} register.
3372 The @code{X} register.
3376 @item RX---@file{config/rx/constraints.md}
3379 An address which does not involve register indirect addressing or
3380 pre/post increment/decrement addressing.
3386 A constant in the range @minus{}256 to 255, inclusive.
3389 A constant in the range @minus{}128 to 127, inclusive.
3392 A constant in the range @minus{}32768 to 32767, inclusive.
3395 A constant in the range @minus{}8388608 to 8388607, inclusive.
3398 A constant in the range 0 to 15, inclusive.
3402 @item S/390 and zSeries---@file{config/s390/s390.h}
3405 Address register (general purpose register except r0)
3408 Condition code register
3411 Data register (arbitrary general purpose register)
3414 Floating-point register
3417 Unsigned 8-bit constant (0--255)
3420 Unsigned 12-bit constant (0--4095)
3423 Signed 16-bit constant (@minus{}32768--32767)
3426 Value appropriate as displacement.
3429 for short displacement
3430 @item (@minus{}524288..524287)
3431 for long displacement
3435 Constant integer with a value of 0x7fffffff.
3438 Multiple letter constraint followed by 4 parameter letters.
3441 number of the part counting from most to least significant
3445 mode of the containing operand
3447 value of the other parts (F---all bits set)
3449 The constraint matches if the specified part of a constant
3450 has a value different from its other parts.
3453 Memory reference without index register and with short displacement.
3456 Memory reference with index register and short displacement.
3459 Memory reference without index register but with long displacement.
3462 Memory reference with index register and long displacement.
3465 Pointer with short displacement.
3468 Pointer with long displacement.
3471 Shift count operand.
3476 @item SPARC---@file{config/sparc/sparc.h}
3479 Floating-point register on the SPARC-V8 architecture and
3480 lower floating-point register on the SPARC-V9 architecture.
3483 Floating-point register. It is equivalent to @samp{f} on the
3484 SPARC-V8 architecture and contains both lower and upper
3485 floating-point registers on the SPARC-V9 architecture.
3488 Floating-point condition code register.
3491 Lower floating-point register. It is only valid on the SPARC-V9
3492 architecture when the Visual Instruction Set is available.
3495 Floating-point register. It is only valid on the SPARC-V9 architecture
3496 when the Visual Instruction Set is available.
3499 64-bit global or out register for the SPARC-V8+ architecture.
3502 The constant all-ones, for floating-point.
3505 Signed 5-bit constant
3511 Signed 13-bit constant
3517 32-bit constant with the low 12 bits clear (a constant that can be
3518 loaded with the @code{sethi} instruction)
3521 A constant in the range supported by @code{movcc} instructions (11-bit
3525 A constant in the range supported by @code{movrcc} instructions (10-bit
3529 Same as @samp{K}, except that it verifies that bits that are not in the
3530 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3531 modes wider than @code{SImode}
3540 Signed 13-bit constant, sign-extended to 32 or 64 bits
3546 Floating-point constant whose integral representation can
3547 be moved into an integer register using a single sethi
3551 Floating-point constant whose integral representation can
3552 be moved into an integer register using a single mov
3556 Floating-point constant whose integral representation can
3557 be moved into an integer register using a high/lo_sum
3558 instruction sequence
3561 Memory address aligned to an 8-byte boundary
3567 Memory address for @samp{e} constraint registers
3570 Memory address with only a base register
3577 @item SPU---@file{config/spu/spu.h}
3580 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3583 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3586 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3589 An immediate which can be loaded with @code{fsmbi}.
3592 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3595 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3598 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3601 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3604 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3607 An unsigned 7-bit constant for conversion/nop/channel instructions.
3610 A signed 10-bit constant for most arithmetic instructions.
3613 A signed 16 bit immediate for @code{stop}.
3616 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3619 An unsigned 7-bit constant whose 3 least significant bits are 0.
3622 An unsigned 3-bit constant for 16-byte rotates and shifts
3625 Call operand, reg, for indirect calls
3628 Call operand, symbol, for relative calls.
3631 Call operand, const_int, for absolute calls.
3634 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3637 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3640 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3643 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3647 @item TI C6X family---@file{config/c6x/constraints.md}
3650 Register file A (A0--A31).
3653 Register file B (B0--B31).
3656 Predicate registers in register file A (A0--A2 on C64X and
3657 higher, A1 and A2 otherwise).
3660 Predicate registers in register file B (B0--B2).
3663 A call-used register in register file B (B0--B9, B16--B31).
3666 Register file A, excluding predicate registers (A3--A31,
3667 plus A0 if not C64X or higher).
3670 Register file B, excluding predicate registers (B3--B31).
3673 Integer constant in the range 0 @dots{} 15.
3676 Integer constant in the range 0 @dots{} 31.
3679 Integer constant in the range @minus{}31 @dots{} 0.
3682 Integer constant in the range @minus{}16 @dots{} 15.
3685 Integer constant that can be the operand of an ADDA or a SUBA insn.
3688 Integer constant in the range 0 @dots{} 65535.
3691 Integer constant in the range @minus{}32768 @dots{} 32767.
3694 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3697 Integer constant that is a valid mask for the clr instruction.
3700 Integer constant that is a valid mask for the set instruction.
3703 Memory location with A base register.
3706 Memory location with B base register.
3710 On C64x+ targets, a GP-relative small data reference.
3713 Any kind of @code{SYMBOL_REF}, for use in a call address.
3716 Any kind of immediate operand, unless it matches the S0 constraint.
3719 Memory location with B base register, but not using a long offset.
3722 A memory operand with an address that can't be used in an unaligned access.
3726 Register B14 (aka DP).
3730 @item TILE-Gx---@file{config/tilegx/constraints.md}
3743 Each of these represents a register constraint for an individual
3744 register, from r0 to r10.
3747 Signed 8-bit integer constant.
3750 Signed 16-bit integer constant.
3753 Unsigned 16-bit integer constant.
3756 Integer constant that fits in one signed byte when incremented by one
3757 (@minus{}129 @dots{} 126).
3760 Memory operand. If used together with @samp{<} or @samp{>}, the
3761 operand can have postincrement which requires printing with @samp{%In}
3762 and @samp{%in} on TILE-Gx. For example:
3765 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3769 A bit mask suitable for the BFINS instruction.
3772 Integer constant that is a byte tiled out eight times.
3775 The integer zero constant.
3778 Integer constant that is a sign-extended byte tiled out as four shorts.
3781 Integer constant that fits in one signed byte when incremented
3782 (@minus{}129 @dots{} 126), but excluding -1.
3785 Integer constant that has all 1 bits consecutive and starting at bit 0.
3788 A 16-bit fragment of a got, tls, or pc-relative reference.
3791 Memory operand except postincrement. This is roughly the same as
3792 @samp{m} when not used together with @samp{<} or @samp{>}.
3795 An 8-element vector constant with identical elements.
3798 A 4-element vector constant with identical elements.
3801 The integer constant 0xffffffff.
3804 The integer constant 0xffffffff00000000.
3808 @item TILEPro---@file{config/tilepro/constraints.md}
3821 Each of these represents a register constraint for an individual
3822 register, from r0 to r10.
3825 Signed 8-bit integer constant.
3828 Signed 16-bit integer constant.
3831 Nonzero integer constant with low 16 bits zero.
3834 Integer constant that fits in one signed byte when incremented by one
3835 (@minus{}129 @dots{} 126).
3838 Memory operand. If used together with @samp{<} or @samp{>}, the
3839 operand can have postincrement which requires printing with @samp{%In}
3840 and @samp{%in} on TILEPro. For example:
3843 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3847 A bit mask suitable for the MM instruction.
3850 Integer constant that is a byte tiled out four times.
3853 The integer zero constant.
3856 Integer constant that is a sign-extended byte tiled out as two shorts.
3859 Integer constant that fits in one signed byte when incremented
3860 (@minus{}129 @dots{} 126), but excluding -1.
3863 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3867 Memory operand except postincrement. This is roughly the same as
3868 @samp{m} when not used together with @samp{<} or @samp{>}.
3871 A 4-element vector constant with identical elements.
3874 A 2-element vector constant with identical elements.
3878 @item Visium---@file{config/visium/constraints.md}
3881 EAM register @code{mdb}
3884 EAM register @code{mdc}
3887 Floating point register
3891 Register for sibcall optimization
3895 General register, but not @code{r29}, @code{r30} and @code{r31}
3907 Floating-point constant 0.0
3910 Integer constant in the range 0 .. 65535 (16-bit immediate)
3913 Integer constant in the range 1 .. 31 (5-bit immediate)
3916 Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
3919 Integer constant @minus{}1
3928 @item x86 family---@file{config/i386/constraints.md}
3931 Legacy register---the eight integer registers available on all
3932 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
3933 @code{si}, @code{di}, @code{bp}, @code{sp}).
3936 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
3937 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
3940 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
3941 @code{c}, and @code{d}.
3945 Any register that can be used as the index in a base+index memory
3946 access: that is, any general register except the stack pointer.
3950 The @code{a} register.
3953 The @code{b} register.
3956 The @code{c} register.
3959 The @code{d} register.
3962 The @code{si} register.
3965 The @code{di} register.
3968 The @code{a} and @code{d} registers. This class is used for instructions
3969 that return double word results in the @code{ax:dx} register pair. Single
3970 word values will be allocated either in @code{ax} or @code{dx}.
3971 For example on i386 the following implements @code{rdtsc}:
3974 unsigned long long rdtsc (void)
3976 unsigned long long tick;
3977 __asm__ __volatile__("rdtsc":"=A"(tick));
3982 This is not correct on x86-64 as it would allocate tick in either @code{ax}
3983 or @code{dx}. You have to use the following variant instead:
3986 unsigned long long rdtsc (void)
3988 unsigned int tickl, tickh;
3989 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
3990 return ((unsigned long long)tickh << 32)|tickl;
3996 Any 80387 floating-point (stack) register.
3999 Top of 80387 floating-point stack (@code{%st(0)}).
4002 Second from top of 80387 floating-point stack (@code{%st(1)}).
4011 First SSE register (@code{%xmm0}).
4015 Any SSE register, when SSE2 is enabled.
4018 Any SSE register, when SSE2 and inter-unit moves are enabled.
4021 Any MMX register, when inter-unit moves are enabled.
4025 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
4028 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
4031 Signed 8-bit integer constant.
4034 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
4037 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
4040 Unsigned 8-bit integer constant (for @code{in} and @code{out}
4045 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
4049 Standard 80387 floating point constant.
4052 Standard SSE floating point constant.
4055 32-bit signed integer constant, or a symbolic reference known
4056 to fit that range (for immediate operands in sign-extending x86-64
4060 32-bit unsigned integer constant, or a symbolic reference known
4061 to fit that range (for immediate operands in zero-extending x86-64
4066 @item Xstormy16---@file{config/stormy16/stormy16.h}
4081 Registers r0 through r7.
4084 Registers r0 and r1.
4090 Registers r8 and r9.
4093 A constant between 0 and 3 inclusive.
4096 A constant that has exactly one bit set.
4099 A constant that has exactly one bit clear.
4102 A constant between 0 and 255 inclusive.
4105 A constant between @minus{}255 and 0 inclusive.
4108 A constant between @minus{}3 and 0 inclusive.
4111 A constant between 1 and 4 inclusive.
4114 A constant between @minus{}4 and @minus{}1 inclusive.
4117 A memory reference that is a stack push.
4120 A memory reference that is a stack pop.
4123 A memory reference that refers to a constant address of known value.
4126 The register indicated by Rx (not implemented yet).
4129 A constant that is not between 2 and 15 inclusive.
4136 @item Xtensa---@file{config/xtensa/constraints.md}
4139 General-purpose 32-bit register
4142 One-bit boolean register
4145 MAC16 40-bit accumulator register
4148 Signed 12-bit integer constant, for use in MOVI instructions
4151 Signed 8-bit integer constant, for use in ADDI instructions
4154 Integer constant valid for BccI instructions
4157 Unsigned constant valid for BccUI instructions
4164 @node Disable Insn Alternatives
4165 @subsection Disable insn alternatives using the @code{enabled} attribute
4168 There are three insn attributes that may be used to selectively disable
4169 instruction alternatives:
4173 Says whether an alternative is available on the current subtarget.
4175 @item preferred_for_size
4176 Says whether an enabled alternative should be used in code that is
4179 @item preferred_for_speed
4180 Says whether an enabled alternative should be used in code that is
4181 optimized for speed.
4184 All these attributes should use @code{(const_int 1)} to allow an alternative
4185 or @code{(const_int 0)} to disallow it. The attributes must be a static
4186 property of the subtarget; they cannot for example depend on the
4187 current operands, on the current optimization level, on the location
4188 of the insn within the body of a loop, on whether register allocation
4189 has finished, or on the current compiler pass.
4191 The @code{enabled} attribute is a correctness property. It tells GCC to act
4192 as though the disabled alternatives were never defined in the first place.
4193 This is useful when adding new instructions to an existing pattern in
4194 cases where the new instructions are only available for certain cpu
4195 architecture levels (typically mapped to the @code{-march=} command-line
4198 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4199 attributes are strong optimization hints rather than correctness properties.
4200 @code{preferred_for_size} tells GCC which alternatives to consider when
4201 adding or modifying an instruction that GCC wants to optimize for size.
4202 @code{preferred_for_speed} does the same thing for speed. Note that things
4203 like code motion can lead to cases where code optimized for size uses
4204 alternatives that are not preferred for size, and similarly for speed.
4206 Although @code{define_insn}s can in principle specify the @code{enabled}
4207 attribute directly, it is often clearer to have subsiduary attributes
4208 for each architectural feature of interest. The @code{define_insn}s
4209 can then use these subsiduary attributes to say which alternatives
4210 require which features. The example below does this for @code{cpu_facility}.
4212 E.g. the following two patterns could easily be merged using the @code{enabled}
4217 (define_insn "*movdi_old"
4218 [(set (match_operand:DI 0 "register_operand" "=d")
4219 (match_operand:DI 1 "register_operand" " d"))]
4223 (define_insn "*movdi_new"
4224 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4225 (match_operand:DI 1 "register_operand" " d,d,f"))]
4238 (define_insn "*movdi_combined"
4239 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4240 (match_operand:DI 1 "register_operand" " d,d,f"))]
4246 [(set_attr "cpu_facility" "*,new,new")])
4250 with the @code{enabled} attribute defined like this:
4254 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4256 (define_attr "enabled" ""
4257 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4258 (and (eq_attr "cpu_facility" "new")
4259 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4268 @node Define Constraints
4269 @subsection Defining Machine-Specific Constraints
4270 @cindex defining constraints
4271 @cindex constraints, defining
4273 Machine-specific constraints fall into two categories: register and
4274 non-register constraints. Within the latter category, constraints
4275 which allow subsets of all possible memory or address operands should
4276 be specially marked, to give @code{reload} more information.
4278 Machine-specific constraints can be given names of arbitrary length,
4279 but they must be entirely composed of letters, digits, underscores
4280 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4281 must begin with a letter or underscore.
4283 In order to avoid ambiguity in operand constraint strings, no
4284 constraint can have a name that begins with any other constraint's
4285 name. For example, if @code{x} is defined as a constraint name,
4286 @code{xy} may not be, and vice versa. As a consequence of this rule,
4287 no constraint may begin with one of the generic constraint letters:
4288 @samp{E F V X g i m n o p r s}.
4290 Register constraints correspond directly to register classes.
4291 @xref{Register Classes}. There is thus not much flexibility in their
4294 @deffn {MD Expression} define_register_constraint name regclass docstring
4295 All three arguments are string constants.
4296 @var{name} is the name of the constraint, as it will appear in
4297 @code{match_operand} expressions. If @var{name} is a multi-letter
4298 constraint its length shall be the same for all constraints starting
4299 with the same letter. @var{regclass} can be either the
4300 name of the corresponding register class (@pxref{Register Classes}),
4301 or a C expression which evaluates to the appropriate register class.
4302 If it is an expression, it must have no side effects, and it cannot
4303 look at the operand. The usual use of expressions is to map some
4304 register constraints to @code{NO_REGS} when the register class
4305 is not available on a given subarchitecture.
4307 @var{docstring} is a sentence documenting the meaning of the
4308 constraint. Docstrings are explained further below.
4311 Non-register constraints are more like predicates: the constraint
4312 definition gives a Boolean expression which indicates whether the
4315 @deffn {MD Expression} define_constraint name docstring exp
4316 The @var{name} and @var{docstring} arguments are the same as for
4317 @code{define_register_constraint}, but note that the docstring comes
4318 immediately after the name for these expressions. @var{exp} is an RTL
4319 expression, obeying the same rules as the RTL expressions in predicate
4320 definitions. @xref{Defining Predicates}, for details. If it
4321 evaluates true, the constraint matches; if it evaluates false, it
4322 doesn't. Constraint expressions should indicate which RTL codes they
4323 might match, just like predicate expressions.
4325 @code{match_test} C expressions have access to the
4326 following variables:
4330 The RTL object defining the operand.
4332 The machine mode of @var{op}.
4334 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4336 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4337 @code{const_double}.
4339 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4340 @code{const_double}.
4342 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4343 @code{const_double}.
4346 The @var{*val} variables should only be used once another piece of the
4347 expression has verified that @var{op} is the appropriate kind of RTL
4351 Most non-register constraints should be defined with
4352 @code{define_constraint}. The remaining two definition expressions
4353 are only appropriate for constraints that should be handled specially
4354 by @code{reload} if they fail to match.
4356 @deffn {MD Expression} define_memory_constraint name docstring exp
4357 Use this expression for constraints that match a subset of all memory
4358 operands: that is, @code{reload} can make them match by converting the
4359 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4360 base register (from the register class specified by
4361 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4363 For example, on the S/390, some instructions do not accept arbitrary
4364 memory references, but only those that do not make use of an index
4365 register. The constraint letter @samp{Q} is defined to represent a
4366 memory address of this type. If @samp{Q} is defined with
4367 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4368 memory operand, because @code{reload} knows it can simply copy the
4369 memory address into a base register if required. This is analogous to
4370 the way an @samp{o} constraint can handle any memory operand.
4372 The syntax and semantics are otherwise identical to
4373 @code{define_constraint}.
4376 @deffn {MD Expression} define_address_constraint name docstring exp
4377 Use this expression for constraints that match a subset of all address
4378 operands: that is, @code{reload} can make the constraint match by
4379 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4380 with @var{X} a base register.
4382 Constraints defined with @code{define_address_constraint} can only be
4383 used with the @code{address_operand} predicate, or machine-specific
4384 predicates that work the same way. They are treated analogously to
4385 the generic @samp{p} constraint.
4387 The syntax and semantics are otherwise identical to
4388 @code{define_constraint}.
4391 For historical reasons, names beginning with the letters @samp{G H}
4392 are reserved for constraints that match only @code{const_double}s, and
4393 names beginning with the letters @samp{I J K L M N O P} are reserved
4394 for constraints that match only @code{const_int}s. This may change in
4395 the future. For the time being, constraints with these names must be
4396 written in a stylized form, so that @code{genpreds} can tell you did
4401 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4403 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4404 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4407 @c the semicolons line up in the formatted manual
4409 It is fine to use names beginning with other letters for constraints
4410 that match @code{const_double}s or @code{const_int}s.
4412 Each docstring in a constraint definition should be one or more complete
4413 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4414 In the future they will be copied into the GCC manual, in @ref{Machine
4415 Constraints}, replacing the hand-maintained tables currently found in
4416 that section. Also, in the future the compiler may use this to give
4417 more helpful diagnostics when poor choice of @code{asm} constraints
4418 causes a reload failure.
4420 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4421 beginning of a docstring, then (in the future) it will appear only in
4422 the internals manual's version of the machine-specific constraint tables.
4423 Use this for constraints that should not appear in @code{asm} statements.
4425 @node C Constraint Interface
4426 @subsection Testing constraints from C
4427 @cindex testing constraints
4428 @cindex constraints, testing
4430 It is occasionally useful to test a constraint from C code rather than
4431 implicitly via the constraint string in a @code{match_operand}. The
4432 generated file @file{tm_p.h} declares a few interfaces for working
4433 with constraints. At present these are defined for all constraints
4434 except @code{g} (which is equivalent to @code{general_operand}).
4436 Some valid constraint names are not valid C identifiers, so there is a
4437 mangling scheme for referring to them from C@. Constraint names that
4438 do not contain angle brackets or underscores are left unchanged.
4439 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4440 each @samp{>} with @samp{_g}. Here are some examples:
4442 @c the @c's prevent double blank lines in the printed manual.
4444 @multitable {Original} {Mangled}
4445 @item @strong{Original} @tab @strong{Mangled} @c
4446 @item @code{x} @tab @code{x} @c
4447 @item @code{P42x} @tab @code{P42x} @c
4448 @item @code{P4_x} @tab @code{P4__x} @c
4449 @item @code{P4>x} @tab @code{P4_gx} @c
4450 @item @code{P4>>} @tab @code{P4_g_g} @c
4451 @item @code{P4_g>} @tab @code{P4__g_g} @c
4455 Throughout this section, the variable @var{c} is either a constraint
4456 in the abstract sense, or a constant from @code{enum constraint_num};
4457 the variable @var{m} is a mangled constraint name (usually as part of
4458 a larger identifier).
4460 @deftp Enum constraint_num
4461 For each constraint except @code{g}, there is a corresponding
4462 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4463 constraint. Functions that take an @code{enum constraint_num} as an
4464 argument expect one of these constants.
4467 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4468 For each non-register constraint @var{m} except @code{g}, there is
4469 one of these functions; it returns @code{true} if @var{exp} satisfies the
4470 constraint. These functions are only visible if @file{rtl.h} was included
4471 before @file{tm_p.h}.
4474 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4475 Like the @code{satisfies_constraint_@var{m}} functions, but the
4476 constraint to test is given as an argument, @var{c}. If @var{c}
4477 specifies a register constraint, this function will always return
4481 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4482 Returns the register class associated with @var{c}. If @var{c} is not
4483 a register constraint, or those registers are not available for the
4484 currently selected subtarget, returns @code{NO_REGS}.
4487 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4488 peephole optimizations (@pxref{Peephole Definitions}), operand
4489 constraint strings are ignored, so if there are relevant constraints,
4490 they must be tested in the C condition. In the example, the
4491 optimization is applied if operand 2 does @emph{not} satisfy the
4492 @samp{K} constraint. (This is a simplified version of a peephole
4493 definition from the i386 machine description.)
4497 [(match_scratch:SI 3 "r")
4498 (set (match_operand:SI 0 "register_operand" "")
4499 (mult:SI (match_operand:SI 1 "memory_operand" "")
4500 (match_operand:SI 2 "immediate_operand" "")))]
4502 "!satisfies_constraint_K (operands[2])"
4504 [(set (match_dup 3) (match_dup 1))
4505 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4510 @node Standard Names
4511 @section Standard Pattern Names For Generation
4512 @cindex standard pattern names
4513 @cindex pattern names
4514 @cindex names, pattern
4516 Here is a table of the instruction names that are meaningful in the RTL
4517 generation pass of the compiler. Giving one of these names to an
4518 instruction pattern tells the RTL generation pass that it can use the
4519 pattern to accomplish a certain task.
4522 @cindex @code{mov@var{m}} instruction pattern
4523 @item @samp{mov@var{m}}
4524 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4525 This instruction pattern moves data with that machine mode from operand
4526 1 to operand 0. For example, @samp{movsi} moves full-word data.
4528 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4529 own mode is wider than @var{m}, the effect of this instruction is
4530 to store the specified value in the part of the register that corresponds
4531 to mode @var{m}. Bits outside of @var{m}, but which are within the
4532 same target word as the @code{subreg} are undefined. Bits which are
4533 outside the target word are left unchanged.
4535 This class of patterns is special in several ways. First of all, each
4536 of these names up to and including full word size @emph{must} be defined,
4537 because there is no other way to copy a datum from one place to another.
4538 If there are patterns accepting operands in larger modes,
4539 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4541 Second, these patterns are not used solely in the RTL generation pass.
4542 Even the reload pass can generate move insns to copy values from stack
4543 slots into temporary registers. When it does so, one of the operands is
4544 a hard register and the other is an operand that can need to be reloaded
4548 Therefore, when given such a pair of operands, the pattern must generate
4549 RTL which needs no reloading and needs no temporary registers---no
4550 registers other than the operands. For example, if you support the
4551 pattern with a @code{define_expand}, then in such a case the
4552 @code{define_expand} mustn't call @code{force_reg} or any other such
4553 function which might generate new pseudo registers.
4555 This requirement exists even for subword modes on a RISC machine where
4556 fetching those modes from memory normally requires several insns and
4557 some temporary registers.
4559 @findex change_address
4560 During reload a memory reference with an invalid address may be passed
4561 as an operand. Such an address will be replaced with a valid address
4562 later in the reload pass. In this case, nothing may be done with the
4563 address except to use it as it stands. If it is copied, it will not be
4564 replaced with a valid address. No attempt should be made to make such
4565 an address into a valid address and no routine (such as
4566 @code{change_address}) that will do so may be called. Note that
4567 @code{general_operand} will fail when applied to such an address.
4569 @findex reload_in_progress
4570 The global variable @code{reload_in_progress} (which must be explicitly
4571 declared if required) can be used to determine whether such special
4572 handling is required.
4574 The variety of operands that have reloads depends on the rest of the
4575 machine description, but typically on a RISC machine these can only be
4576 pseudo registers that did not get hard registers, while on other
4577 machines explicit memory references will get optional reloads.
4579 If a scratch register is required to move an object to or from memory,
4580 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4582 If there are cases which need scratch registers during or after reload,
4583 you must provide an appropriate secondary_reload target hook.
4585 @findex can_create_pseudo_p
4586 The macro @code{can_create_pseudo_p} can be used to determine if it
4587 is unsafe to create new pseudo registers. If this variable is nonzero, then
4588 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4590 The constraints on a @samp{mov@var{m}} must permit moving any hard
4591 register to any other hard register provided that
4592 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4593 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4596 It is obligatory to support floating point @samp{mov@var{m}}
4597 instructions into and out of any registers that can hold fixed point
4598 values, because unions and structures (which have modes @code{SImode} or
4599 @code{DImode}) can be in those registers and they may have floating
4602 There may also be a need to support fixed point @samp{mov@var{m}}
4603 instructions in and out of floating point registers. Unfortunately, I
4604 have forgotten why this was so, and I don't know whether it is still
4605 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
4606 floating point registers, then the constraints of the fixed point
4607 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4608 reload into a floating point register.
4610 @cindex @code{reload_in} instruction pattern
4611 @cindex @code{reload_out} instruction pattern
4612 @item @samp{reload_in@var{m}}
4613 @itemx @samp{reload_out@var{m}}
4614 These named patterns have been obsoleted by the target hook
4615 @code{secondary_reload}.
4617 Like @samp{mov@var{m}}, but used when a scratch register is required to
4618 move between operand 0 and operand 1. Operand 2 describes the scratch
4619 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4620 macro in @pxref{Register Classes}.
4622 There are special restrictions on the form of the @code{match_operand}s
4623 used in these patterns. First, only the predicate for the reload
4624 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4625 the predicates for operand 0 or 2. Second, there may be only one
4626 alternative in the constraints. Third, only a single register class
4627 letter may be used for the constraint; subsequent constraint letters
4628 are ignored. As a special exception, an empty constraint string
4629 matches the @code{ALL_REGS} register class. This may relieve ports
4630 of the burden of defining an @code{ALL_REGS} constraint letter just
4633 @cindex @code{movstrict@var{m}} instruction pattern
4634 @item @samp{movstrict@var{m}}
4635 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4636 with mode @var{m} of a register whose natural mode is wider,
4637 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4638 any of the register except the part which belongs to mode @var{m}.
4640 @cindex @code{movmisalign@var{m}} instruction pattern
4641 @item @samp{movmisalign@var{m}}
4642 This variant of a move pattern is designed to load or store a value
4643 from a memory address that is not naturally aligned for its mode.
4644 For a store, the memory will be in operand 0; for a load, the memory
4645 will be in operand 1. The other operand is guaranteed not to be a
4646 memory, so that it's easy to tell whether this is a load or store.
4648 This pattern is used by the autovectorizer, and when expanding a
4649 @code{MISALIGNED_INDIRECT_REF} expression.
4651 @cindex @code{load_multiple} instruction pattern
4652 @item @samp{load_multiple}
4653 Load several consecutive memory locations into consecutive registers.
4654 Operand 0 is the first of the consecutive registers, operand 1
4655 is the first memory location, and operand 2 is a constant: the
4656 number of consecutive registers.
4658 Define this only if the target machine really has such an instruction;
4659 do not define this if the most efficient way of loading consecutive
4660 registers from memory is to do them one at a time.
4662 On some machines, there are restrictions as to which consecutive
4663 registers can be stored into memory, such as particular starting or
4664 ending register numbers or only a range of valid counts. For those
4665 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4666 and make the pattern fail if the restrictions are not met.
4668 Write the generated insn as a @code{parallel} with elements being a
4669 @code{set} of one register from the appropriate memory location (you may
4670 also need @code{use} or @code{clobber} elements). Use a
4671 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4672 @file{rs6000.md} for examples of the use of this insn pattern.
4674 @cindex @samp{store_multiple} instruction pattern
4675 @item @samp{store_multiple}
4676 Similar to @samp{load_multiple}, but store several consecutive registers
4677 into consecutive memory locations. Operand 0 is the first of the
4678 consecutive memory locations, operand 1 is the first register, and
4679 operand 2 is a constant: the number of consecutive registers.
4681 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4682 @item @samp{vec_load_lanes@var{m}@var{n}}
4683 Perform an interleaved load of several vectors from memory operand 1
4684 into register operand 0. Both operands have mode @var{m}. The register
4685 operand is viewed as holding consecutive vectors of mode @var{n},
4686 while the memory operand is a flat array that contains the same number
4687 of elements. The operation is equivalent to:
4690 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4691 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4692 for (i = 0; i < c; i++)
4693 operand0[i][j] = operand1[j * c + i];
4696 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4697 from memory into a register of mode @samp{TI}@. The register
4698 contains two consecutive vectors of mode @samp{V4HI}@.
4700 This pattern can only be used if:
4702 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4704 is true. GCC assumes that, if a target supports this kind of
4705 instruction for some mode @var{n}, it also supports unaligned
4706 loads for vectors of mode @var{n}.
4708 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4709 @item @samp{vec_store_lanes@var{m}@var{n}}
4710 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4711 and register operands reversed. That is, the instruction is
4715 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4716 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4717 for (i = 0; i < c; i++)
4718 operand0[j * c + i] = operand1[i][j];
4721 for a memory operand 0 and register operand 1.
4723 @cindex @code{vec_set@var{m}} instruction pattern
4724 @item @samp{vec_set@var{m}}
4725 Set given field in the vector value. Operand 0 is the vector to modify,
4726 operand 1 is new value of field and operand 2 specify the field index.
4728 @cindex @code{vec_extract@var{m}} instruction pattern
4729 @item @samp{vec_extract@var{m}}
4730 Extract given field from the vector value. Operand 1 is the vector, operand 2
4731 specify field index and operand 0 place to store value into.
4733 @cindex @code{vec_init@var{m}} instruction pattern
4734 @item @samp{vec_init@var{m}}
4735 Initialize the vector to given values. Operand 0 is the vector to initialize
4736 and operand 1 is parallel containing values for individual fields.
4738 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4739 @item @samp{vcond@var{m}@var{n}}
4740 Output a conditional vector move. Operand 0 is the destination to
4741 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4742 dependent on the outcome of the predicate in operand 3 which is a
4743 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4744 modes @var{m} and @var{n} should have the same size. Operand 0
4745 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4746 where @var{msk} is computed by element-wise evaluation of the vector
4747 comparison with a truth value of all-ones and a false value of all-zeros.
4749 @cindex @code{vec_perm@var{m}} instruction pattern
4750 @item @samp{vec_perm@var{m}}
4751 Output a (variable) vector permutation. Operand 0 is the destination
4752 to receive elements from operand 1 and operand 2, which are of mode
4753 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4754 vector of the same width and number of elements as mode @var{m}.
4756 The input elements are numbered from 0 in operand 1 through
4757 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4758 be computed modulo @math{2*@var{N}}. Note that if
4759 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4760 with just operand 1 and selector elements modulo @var{N}.
4762 In order to make things easy for a number of targets, if there is no
4763 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4764 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4765 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4768 @cindex @code{vec_perm_const@var{m}} instruction pattern
4769 @item @samp{vec_perm_const@var{m}}
4770 Like @samp{vec_perm} except that the permutation is a compile-time
4771 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4773 Some targets cannot perform a permutation with a variable selector,
4774 but can efficiently perform a constant permutation. Further, the
4775 target hook @code{vec_perm_ok} is queried to determine if the
4776 specific constant permutation is available efficiently; the named
4777 pattern is never expanded without @code{vec_perm_ok} returning true.
4779 There is no need for a target to supply both @samp{vec_perm@var{m}}
4780 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4781 the operation with, say, the vector constant loaded into a register.
4783 @cindex @code{push@var{m}1} instruction pattern
4784 @item @samp{push@var{m}1}
4785 Output a push instruction. Operand 0 is value to push. Used only when
4786 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4787 missing and in such case an @code{mov} expander is used instead, with a
4788 @code{MEM} expression forming the push operation. The @code{mov} expander
4789 method is deprecated.
4791 @cindex @code{add@var{m}3} instruction pattern
4792 @item @samp{add@var{m}3}
4793 Add operand 2 and operand 1, storing the result in operand 0. All operands
4794 must have mode @var{m}. This can be used even on two-address machines, by
4795 means of constraints requiring operands 1 and 0 to be the same location.
4797 @cindex @code{addptr@var{m}3} instruction pattern
4798 @item @samp{addptr@var{m}3}
4799 Like @code{add@var{m}3} but is guaranteed to only be used for address
4800 calculations. The expanded code is not allowed to clobber the
4801 condition code. It only needs to be defined if @code{add@var{m}3}
4802 sets the condition code. If adds used for address calculations and
4803 normal adds are not compatible it is required to expand a distinct
4804 pattern (e.g. using an unspec). The pattern is used by LRA to emit
4805 address calculations. @code{add@var{m}3} is used if
4806 @code{addptr@var{m}3} is not defined.
4808 @cindex @code{ssadd@var{m}3} instruction pattern
4809 @cindex @code{usadd@var{m}3} instruction pattern
4810 @cindex @code{sub@var{m}3} instruction pattern
4811 @cindex @code{sssub@var{m}3} instruction pattern
4812 @cindex @code{ussub@var{m}3} instruction pattern
4813 @cindex @code{mul@var{m}3} instruction pattern
4814 @cindex @code{ssmul@var{m}3} instruction pattern
4815 @cindex @code{usmul@var{m}3} instruction pattern
4816 @cindex @code{div@var{m}3} instruction pattern
4817 @cindex @code{ssdiv@var{m}3} instruction pattern
4818 @cindex @code{udiv@var{m}3} instruction pattern
4819 @cindex @code{usdiv@var{m}3} instruction pattern
4820 @cindex @code{mod@var{m}3} instruction pattern
4821 @cindex @code{umod@var{m}3} instruction pattern
4822 @cindex @code{umin@var{m}3} instruction pattern
4823 @cindex @code{umax@var{m}3} instruction pattern
4824 @cindex @code{and@var{m}3} instruction pattern
4825 @cindex @code{ior@var{m}3} instruction pattern
4826 @cindex @code{xor@var{m}3} instruction pattern
4827 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4828 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4829 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4830 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4831 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4832 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4833 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4834 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4835 Similar, for other arithmetic operations.
4837 @cindex @code{fma@var{m}4} instruction pattern
4838 @item @samp{fma@var{m}4}
4839 Multiply operand 2 and operand 1, then add operand 3, storing the
4840 result in operand 0 without doing an intermediate rounding step. All
4841 operands must have mode @var{m}. This pattern is used to implement
4842 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
4843 the ISO C99 standard.
4845 @cindex @code{fms@var{m}4} instruction pattern
4846 @item @samp{fms@var{m}4}
4847 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4848 product instead of added to the product. This is represented
4852 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4855 @cindex @code{fnma@var{m}4} instruction pattern
4856 @item @samp{fnma@var{m}4}
4857 Like @code{fma@var{m}4} except that the intermediate product
4858 is negated before being added to operand 3. This is represented
4862 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4865 @cindex @code{fnms@var{m}4} instruction pattern
4866 @item @samp{fnms@var{m}4}
4867 Like @code{fms@var{m}4} except that the intermediate product
4868 is negated before subtracting operand 3. This is represented
4872 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
4875 @cindex @code{min@var{m}3} instruction pattern
4876 @cindex @code{max@var{m}3} instruction pattern
4877 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
4878 Signed minimum and maximum operations. When used with floating point,
4879 if both operands are zeros, or if either operand is @code{NaN}, then
4880 it is unspecified which of the two operands is returned as the result.
4882 @cindex @code{reduc_smin_@var{m}} instruction pattern
4883 @cindex @code{reduc_smax_@var{m}} instruction pattern
4884 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4885 Find the signed minimum/maximum of the elements of a vector. The vector is
4886 operand 1, and the result is stored in the least significant bits of
4887 operand 0 (also a vector). The output and input vector should have the same
4888 modes. These are legacy optabs, and platforms should prefer to implement
4889 @samp{reduc_smin_scal_@var{m}} and @samp{reduc_smax_scal_@var{m}}.
4891 @cindex @code{reduc_umin_@var{m}} instruction pattern
4892 @cindex @code{reduc_umax_@var{m}} instruction pattern
4893 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4894 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4895 operand 1, and the result is stored in the least significant bits of
4896 operand 0 (also a vector). The output and input vector should have the same
4897 modes. These are legacy optabs, and platforms should prefer to implement
4898 @samp{reduc_umin_scal_@var{m}} and @samp{reduc_umax_scal_@var{m}}.
4900 @cindex @code{reduc_splus_@var{m}} instruction pattern
4901 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4902 @item @samp{reduc_splus_@var{m}}, @samp{reduc_uplus_@var{m}}
4903 Compute the sum of the signed/unsigned elements of a vector. The vector is
4904 operand 1, and the result is stored in the least significant bits of operand 0
4905 (also a vector). The output and input vector should have the same modes.
4906 These are legacy optabs, and platforms should prefer to implement
4907 @samp{reduc_plus_scal_@var{m}}.
4909 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
4910 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
4911 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
4912 Find the signed minimum/maximum of the elements of a vector. The vector is
4913 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
4914 the elements of the input vector.
4916 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
4917 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
4918 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
4919 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4920 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
4921 the elements of the input vector.
4923 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
4924 @item @samp{reduc_plus_scal_@var{m}}
4925 Compute the sum of the elements of a vector. The vector is operand 1, and
4926 operand 0 is the scalar result, with mode equal to the mode of the elements of
4929 @cindex @code{sdot_prod@var{m}} instruction pattern
4930 @item @samp{sdot_prod@var{m}}
4931 @cindex @code{udot_prod@var{m}} instruction pattern
4932 @itemx @samp{udot_prod@var{m}}
4933 Compute the sum of the products of two signed/unsigned elements.
4934 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4935 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4936 wider than the mode of the product. The result is placed in operand 0, which
4937 is of the same mode as operand 3.
4939 @cindex @code{ssad@var{m}} instruction pattern
4940 @item @samp{ssad@var{m}}
4941 @cindex @code{usad@var{m}} instruction pattern
4942 @item @samp{usad@var{m}}
4943 Compute the sum of absolute differences of two signed/unsigned elements.
4944 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
4945 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
4946 equal or wider than the mode of the absolute difference. The result is placed
4947 in operand 0, which is of the same mode as operand 3.
4949 @cindex @code{ssum_widen@var{m3}} instruction pattern
4950 @item @samp{ssum_widen@var{m3}}
4951 @cindex @code{usum_widen@var{m3}} instruction pattern
4952 @itemx @samp{usum_widen@var{m3}}
4953 Operands 0 and 2 are of the same mode, which is wider than the mode of
4954 operand 1. Add operand 1 to operand 2 and place the widened result in
4955 operand 0. (This is used express accumulation of elements into an accumulator
4958 @cindex @code{vec_shr_@var{m}} instruction pattern
4959 @item @samp{vec_shr_@var{m}}
4960 Whole vector right shift in bits, i.e. towards element 0.
4961 Operand 1 is a vector to be shifted.
4962 Operand 2 is an integer shift amount in bits.
4963 Operand 0 is where the resulting shifted vector is stored.
4964 The output and input vectors should have the same modes.
4966 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4967 @item @samp{vec_pack_trunc_@var{m}}
4968 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4969 are vectors of the same mode having N integral or floating point elements
4970 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4971 size N/2 are concatenated after narrowing them down using truncation.
4973 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4974 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4975 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4976 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4977 are vectors of the same mode having N integral elements of size S.
4978 Operand 0 is the resulting vector in which the elements of the two input
4979 vectors are concatenated after narrowing them down using signed/unsigned
4980 saturating arithmetic.
4982 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4983 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4984 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4985 Narrow, convert to signed/unsigned integral type and merge the elements
4986 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4987 floating point elements of size S@. Operand 0 is the resulting vector
4988 in which 2*N elements of size N/2 are concatenated.
4990 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4991 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4992 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4993 Extract and widen (promote) the high/low part of a vector of signed
4994 integral or floating point elements. The input vector (operand 1) has N
4995 elements of size S@. Widen (promote) the high/low elements of the vector
4996 using signed or floating point extension and place the resulting N/2
4997 values of size 2*S in the output vector (operand 0).
4999 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
5000 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
5001 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
5002 Extract and widen (promote) the high/low part of a vector of unsigned
5003 integral elements. The input vector (operand 1) has N elements of size S.
5004 Widen (promote) the high/low elements of the vector using zero extension and
5005 place the resulting N/2 values of size 2*S in the output vector (operand 0).
5007 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
5008 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
5009 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
5010 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
5011 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
5012 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
5013 Extract, convert to floating point type and widen the high/low part of a
5014 vector of signed/unsigned integral elements. The input vector (operand 1)
5015 has N elements of size S@. Convert the high/low elements of the vector using
5016 floating point conversion and place the resulting N/2 values of size 2*S in
5017 the output vector (operand 0).
5019 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
5020 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
5021 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
5022 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
5023 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
5024 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
5025 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
5026 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
5027 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
5028 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
5029 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
5030 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
5031 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
5032 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
5033 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
5034 in the output vector (operand 0). A target shouldn't implement even/odd pattern
5035 pair if it is less efficient than lo/hi one.
5037 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
5038 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
5039 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
5040 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
5041 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
5042 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
5043 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
5044 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
5045 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
5046 output vector (operand 0).
5048 @cindex @code{mulhisi3} instruction pattern
5049 @item @samp{mulhisi3}
5050 Multiply operands 1 and 2, which have mode @code{HImode}, and store
5051 a @code{SImode} product in operand 0.
5053 @cindex @code{mulqihi3} instruction pattern
5054 @cindex @code{mulsidi3} instruction pattern
5055 @item @samp{mulqihi3}, @samp{mulsidi3}
5056 Similar widening-multiplication instructions of other widths.
5058 @cindex @code{umulqihi3} instruction pattern
5059 @cindex @code{umulhisi3} instruction pattern
5060 @cindex @code{umulsidi3} instruction pattern
5061 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
5062 Similar widening-multiplication instructions that do unsigned
5065 @cindex @code{usmulqihi3} instruction pattern
5066 @cindex @code{usmulhisi3} instruction pattern
5067 @cindex @code{usmulsidi3} instruction pattern
5068 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
5069 Similar widening-multiplication instructions that interpret the first
5070 operand as unsigned and the second operand as signed, then do a signed
5073 @cindex @code{smul@var{m}3_highpart} instruction pattern
5074 @item @samp{smul@var{m}3_highpart}
5075 Perform a signed multiplication of operands 1 and 2, which have mode
5076 @var{m}, and store the most significant half of the product in operand 0.
5077 The least significant half of the product is discarded.
5079 @cindex @code{umul@var{m}3_highpart} instruction pattern
5080 @item @samp{umul@var{m}3_highpart}
5081 Similar, but the multiplication is unsigned.
5083 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5084 @item @samp{madd@var{m}@var{n}4}
5085 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5086 operand 3, and store the result in operand 0. Operands 1 and 2
5087 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5088 Both modes must be integer or fixed-point modes and @var{n} must be twice
5089 the size of @var{m}.
5091 In other words, @code{madd@var{m}@var{n}4} is like
5092 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5094 These instructions are not allowed to @code{FAIL}.
5096 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5097 @item @samp{umadd@var{m}@var{n}4}
5098 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5099 operands instead of sign-extending them.
5101 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5102 @item @samp{ssmadd@var{m}@var{n}4}
5103 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5106 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5107 @item @samp{usmadd@var{m}@var{n}4}
5108 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5109 unsigned-saturating.
5111 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5112 @item @samp{msub@var{m}@var{n}4}
5113 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5114 result from operand 3, and store the result in operand 0. Operands 1 and 2
5115 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5116 Both modes must be integer or fixed-point modes and @var{n} must be twice
5117 the size of @var{m}.
5119 In other words, @code{msub@var{m}@var{n}4} is like
5120 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5123 These instructions are not allowed to @code{FAIL}.
5125 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5126 @item @samp{umsub@var{m}@var{n}4}
5127 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5128 operands instead of sign-extending them.
5130 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5131 @item @samp{ssmsub@var{m}@var{n}4}
5132 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5135 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5136 @item @samp{usmsub@var{m}@var{n}4}
5137 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5138 unsigned-saturating.
5140 @cindex @code{divmod@var{m}4} instruction pattern
5141 @item @samp{divmod@var{m}4}
5142 Signed division that produces both a quotient and a remainder.
5143 Operand 1 is divided by operand 2 to produce a quotient stored
5144 in operand 0 and a remainder stored in operand 3.
5146 For machines with an instruction that produces both a quotient and a
5147 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5148 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5149 allows optimization in the relatively common case when both the quotient
5150 and remainder are computed.
5152 If an instruction that just produces a quotient or just a remainder
5153 exists and is more efficient than the instruction that produces both,
5154 write the output routine of @samp{divmod@var{m}4} to call
5155 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5156 quotient or remainder and generate the appropriate instruction.
5158 @cindex @code{udivmod@var{m}4} instruction pattern
5159 @item @samp{udivmod@var{m}4}
5160 Similar, but does unsigned division.
5162 @anchor{shift patterns}
5163 @cindex @code{ashl@var{m}3} instruction pattern
5164 @cindex @code{ssashl@var{m}3} instruction pattern
5165 @cindex @code{usashl@var{m}3} instruction pattern
5166 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5167 Arithmetic-shift operand 1 left by a number of bits specified by operand
5168 2, and store the result in operand 0. Here @var{m} is the mode of
5169 operand 0 and operand 1; operand 2's mode is specified by the
5170 instruction pattern, and the compiler will convert the operand to that
5171 mode before generating the instruction. The meaning of out-of-range shift
5172 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5173 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5175 @cindex @code{ashr@var{m}3} instruction pattern
5176 @cindex @code{lshr@var{m}3} instruction pattern
5177 @cindex @code{rotl@var{m}3} instruction pattern
5178 @cindex @code{rotr@var{m}3} instruction pattern
5179 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5180 Other shift and rotate instructions, analogous to the
5181 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5183 @cindex @code{vashl@var{m}3} instruction pattern
5184 @cindex @code{vashr@var{m}3} instruction pattern
5185 @cindex @code{vlshr@var{m}3} instruction pattern
5186 @cindex @code{vrotl@var{m}3} instruction pattern
5187 @cindex @code{vrotr@var{m}3} instruction pattern
5188 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5189 Vector shift and rotate instructions that take vectors as operand 2
5190 instead of a scalar type.
5192 @cindex @code{bswap@var{m}2} instruction pattern
5193 @item @samp{bswap@var{m}2}
5194 Reverse the order of bytes of operand 1 and store the result in operand 0.
5196 @cindex @code{neg@var{m}2} instruction pattern
5197 @cindex @code{ssneg@var{m}2} instruction pattern
5198 @cindex @code{usneg@var{m}2} instruction pattern
5199 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5200 Negate operand 1 and store the result in operand 0.
5202 @cindex @code{abs@var{m}2} instruction pattern
5203 @item @samp{abs@var{m}2}
5204 Store the absolute value of operand 1 into operand 0.
5206 @cindex @code{sqrt@var{m}2} instruction pattern
5207 @item @samp{sqrt@var{m}2}
5208 Store the square root of operand 1 into operand 0.
5210 The @code{sqrt} built-in function of C always uses the mode which
5211 corresponds to the C data type @code{double} and the @code{sqrtf}
5212 built-in function uses the mode which corresponds to the C data
5215 @cindex @code{fmod@var{m}3} instruction pattern
5216 @item @samp{fmod@var{m}3}
5217 Store the remainder of dividing operand 1 by operand 2 into
5218 operand 0, rounded towards zero to an integer.
5220 The @code{fmod} built-in function of C always uses the mode which
5221 corresponds to the C data type @code{double} and the @code{fmodf}
5222 built-in function uses the mode which corresponds to the C data
5225 @cindex @code{remainder@var{m}3} instruction pattern
5226 @item @samp{remainder@var{m}3}
5227 Store the remainder of dividing operand 1 by operand 2 into
5228 operand 0, rounded to the nearest integer.
5230 The @code{remainder} built-in function of C always uses the mode
5231 which corresponds to the C data type @code{double} and the
5232 @code{remainderf} built-in function uses the mode which corresponds
5233 to the C data type @code{float}.
5235 @cindex @code{cos@var{m}2} instruction pattern
5236 @item @samp{cos@var{m}2}
5237 Store the cosine of operand 1 into operand 0.
5239 The @code{cos} built-in function of C always uses the mode which
5240 corresponds to the C data type @code{double} and the @code{cosf}
5241 built-in function uses the mode which corresponds to the C data
5244 @cindex @code{sin@var{m}2} instruction pattern
5245 @item @samp{sin@var{m}2}
5246 Store the sine of operand 1 into operand 0.
5248 The @code{sin} built-in function of C always uses the mode which
5249 corresponds to the C data type @code{double} and the @code{sinf}
5250 built-in function uses the mode which corresponds to the C data
5253 @cindex @code{sincos@var{m}3} instruction pattern
5254 @item @samp{sincos@var{m}3}
5255 Store the cosine of operand 2 into operand 0 and the sine of
5256 operand 2 into operand 1.
5258 The @code{sin} and @code{cos} built-in functions of C always use the
5259 mode which corresponds to the C data type @code{double} and the
5260 @code{sinf} and @code{cosf} built-in function use the mode which
5261 corresponds to the C data type @code{float}.
5262 Targets that can calculate the sine and cosine simultaneously can
5263 implement this pattern as opposed to implementing individual
5264 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5265 and @code{cos} built-in functions will then be expanded to the
5266 @code{sincos@var{m}3} pattern, with one of the output values
5269 @cindex @code{exp@var{m}2} instruction pattern
5270 @item @samp{exp@var{m}2}
5271 Store the exponential of operand 1 into operand 0.
5273 The @code{exp} built-in function of C always uses the mode which
5274 corresponds to the C data type @code{double} and the @code{expf}
5275 built-in function uses the mode which corresponds to the C data
5278 @cindex @code{log@var{m}2} instruction pattern
5279 @item @samp{log@var{m}2}
5280 Store the natural logarithm of operand 1 into operand 0.
5282 The @code{log} built-in function of C always uses the mode which
5283 corresponds to the C data type @code{double} and the @code{logf}
5284 built-in function uses the mode which corresponds to the C data
5287 @cindex @code{pow@var{m}3} instruction pattern
5288 @item @samp{pow@var{m}3}
5289 Store the value of operand 1 raised to the exponent operand 2
5292 The @code{pow} built-in function of C always uses the mode which
5293 corresponds to the C data type @code{double} and the @code{powf}
5294 built-in function uses the mode which corresponds to the C data
5297 @cindex @code{atan2@var{m}3} instruction pattern
5298 @item @samp{atan2@var{m}3}
5299 Store the arc tangent (inverse tangent) of operand 1 divided by
5300 operand 2 into operand 0, using the signs of both arguments to
5301 determine the quadrant of the result.
5303 The @code{atan2} built-in function of C always uses the mode which
5304 corresponds to the C data type @code{double} and the @code{atan2f}
5305 built-in function uses the mode which corresponds to the C data
5308 @cindex @code{floor@var{m}2} instruction pattern
5309 @item @samp{floor@var{m}2}
5310 Store the largest integral value not greater than argument.
5312 The @code{floor} built-in function of C always uses the mode which
5313 corresponds to the C data type @code{double} and the @code{floorf}
5314 built-in function uses the mode which corresponds to the C data
5317 @cindex @code{btrunc@var{m}2} instruction pattern
5318 @item @samp{btrunc@var{m}2}
5319 Store the argument rounded to integer towards zero.
5321 The @code{trunc} built-in function of C always uses the mode which
5322 corresponds to the C data type @code{double} and the @code{truncf}
5323 built-in function uses the mode which corresponds to the C data
5326 @cindex @code{round@var{m}2} instruction pattern
5327 @item @samp{round@var{m}2}
5328 Store the argument rounded to integer away from zero.
5330 The @code{round} built-in function of C always uses the mode which
5331 corresponds to the C data type @code{double} and the @code{roundf}
5332 built-in function uses the mode which corresponds to the C data
5335 @cindex @code{ceil@var{m}2} instruction pattern
5336 @item @samp{ceil@var{m}2}
5337 Store the argument rounded to integer away from zero.
5339 The @code{ceil} built-in function of C always uses the mode which
5340 corresponds to the C data type @code{double} and the @code{ceilf}
5341 built-in function uses the mode which corresponds to the C data
5344 @cindex @code{nearbyint@var{m}2} instruction pattern
5345 @item @samp{nearbyint@var{m}2}
5346 Store the argument rounded according to the default rounding mode
5348 The @code{nearbyint} built-in function of C always uses the mode which
5349 corresponds to the C data type @code{double} and the @code{nearbyintf}
5350 built-in function uses the mode which corresponds to the C data
5353 @cindex @code{rint@var{m}2} instruction pattern
5354 @item @samp{rint@var{m}2}
5355 Store the argument rounded according to the default rounding mode and
5356 raise the inexact exception when the result differs in value from
5359 The @code{rint} built-in function of C always uses the mode which
5360 corresponds to the C data type @code{double} and the @code{rintf}
5361 built-in function uses the mode which corresponds to the C data
5364 @cindex @code{lrint@var{m}@var{n}2}
5365 @item @samp{lrint@var{m}@var{n}2}
5366 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5367 point mode @var{n} as a signed number according to the current
5368 rounding mode and store in operand 0 (which has mode @var{n}).
5370 @cindex @code{lround@var{m}@var{n}2}
5371 @item @samp{lround@var{m}@var{n}2}
5372 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5373 point mode @var{n} as a signed number rounding to nearest and away
5374 from zero and store in operand 0 (which has mode @var{n}).
5376 @cindex @code{lfloor@var{m}@var{n}2}
5377 @item @samp{lfloor@var{m}@var{n}2}
5378 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5379 point mode @var{n} as a signed number rounding down and store in
5380 operand 0 (which has mode @var{n}).
5382 @cindex @code{lceil@var{m}@var{n}2}
5383 @item @samp{lceil@var{m}@var{n}2}
5384 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5385 point mode @var{n} as a signed number rounding up and store in
5386 operand 0 (which has mode @var{n}).
5388 @cindex @code{copysign@var{m}3} instruction pattern
5389 @item @samp{copysign@var{m}3}
5390 Store a value with the magnitude of operand 1 and the sign of operand
5393 The @code{copysign} built-in function of C always uses the mode which
5394 corresponds to the C data type @code{double} and the @code{copysignf}
5395 built-in function uses the mode which corresponds to the C data
5398 @cindex @code{ffs@var{m}2} instruction pattern
5399 @item @samp{ffs@var{m}2}
5400 Store into operand 0 one plus the index of the least significant 1-bit
5401 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
5402 of operand 0; operand 1's mode is specified by the instruction
5403 pattern, and the compiler will convert the operand to that mode before
5404 generating the instruction.
5406 The @code{ffs} built-in function of C always uses the mode which
5407 corresponds to the C data type @code{int}.
5409 @cindex @code{clrsb@var{m}2} instruction pattern
5410 @item @samp{clrsb@var{m}2}
5411 Count leading redundant sign bits.
5412 Store into operand 0 the number of redundant sign bits in operand 1, starting
5413 at the most significant bit position.
5414 A redundant sign bit is defined as any sign bit after the first. As such,
5415 this count will be one less than the count of leading sign bits.
5417 @cindex @code{clz@var{m}2} instruction pattern
5418 @item @samp{clz@var{m}2}
5419 Store into operand 0 the number of leading 0-bits in operand 1, starting
5420 at the most significant bit position. If operand 1 is 0, the
5421 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5422 the result is undefined or has a useful value.
5423 @var{m} is the mode of operand 0; operand 1's mode is
5424 specified by the instruction pattern, and the compiler will convert the
5425 operand to that mode before generating the instruction.
5427 @cindex @code{ctz@var{m}2} instruction pattern
5428 @item @samp{ctz@var{m}2}
5429 Store into operand 0 the number of trailing 0-bits in operand 1, starting
5430 at the least significant bit position. If operand 1 is 0, the
5431 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5432 the result is undefined or has a useful value.
5433 @var{m} is the mode of operand 0; operand 1's mode is
5434 specified by the instruction pattern, and the compiler will convert the
5435 operand to that mode before generating the instruction.
5437 @cindex @code{popcount@var{m}2} instruction pattern
5438 @item @samp{popcount@var{m}2}
5439 Store into operand 0 the number of 1-bits in operand 1. @var{m} is the
5440 mode of operand 0; operand 1's mode is specified by the instruction
5441 pattern, and the compiler will convert the operand to that mode before
5442 generating the instruction.
5444 @cindex @code{parity@var{m}2} instruction pattern
5445 @item @samp{parity@var{m}2}
5446 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
5447 in operand 1 modulo 2. @var{m} is the mode of operand 0; operand 1's mode
5448 is specified by the instruction pattern, and the compiler will convert
5449 the operand to that mode before generating the instruction.
5451 @cindex @code{one_cmpl@var{m}2} instruction pattern
5452 @item @samp{one_cmpl@var{m}2}
5453 Store the bitwise-complement of operand 1 into operand 0.
5455 @cindex @code{movmem@var{m}} instruction pattern
5456 @item @samp{movmem@var{m}}
5457 Block move instruction. The destination and source blocks of memory
5458 are the first two operands, and both are @code{mem:BLK}s with an
5459 address in mode @code{Pmode}.
5461 The number of bytes to move is the third operand, in mode @var{m}.
5462 Usually, you specify @code{Pmode} for @var{m}. However, if you can
5463 generate better code knowing the range of valid lengths is smaller than
5464 those representable in a full Pmode pointer, you should provide
5466 mode corresponding to the range of values you can handle efficiently
5467 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
5468 that appear negative) and also a pattern with @code{Pmode}.
5470 The fourth operand is the known shared alignment of the source and
5471 destination, in the form of a @code{const_int} rtx. Thus, if the
5472 compiler knows that both source and destination are word-aligned,
5473 it may provide the value 4 for this operand.
5475 Optional operands 5 and 6 specify expected alignment and size of block
5476 respectively. The expected alignment differs from alignment in operand 4
5477 in a way that the blocks are not required to be aligned according to it in
5478 all cases. This expected alignment is also in bytes, just like operand 4.
5479 Expected size, when unknown, is set to @code{(const_int -1)}.
5481 Descriptions of multiple @code{movmem@var{m}} patterns can only be
5482 beneficial if the patterns for smaller modes have fewer restrictions
5483 on their first, second and fourth operands. Note that the mode @var{m}
5484 in @code{movmem@var{m}} does not impose any restriction on the mode of
5485 individually moved data units in the block.
5487 These patterns need not give special consideration to the possibility
5488 that the source and destination strings might overlap.
5490 @cindex @code{movstr} instruction pattern
5492 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5493 an output operand in mode @code{Pmode}. The addresses of the
5494 destination and source strings are operands 1 and 2, and both are
5495 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5496 the expansion of this pattern should store in operand 0 the address in
5497 which the @code{NUL} terminator was stored in the destination string.
5499 This patern has also several optional operands that are same as in
5502 @cindex @code{setmem@var{m}} instruction pattern
5503 @item @samp{setmem@var{m}}
5504 Block set instruction. The destination string is the first operand,
5505 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5506 number of bytes to set is the second operand, in mode @var{m}. The value to
5507 initialize the memory with is the third operand. Targets that only support the
5508 clearing of memory should reject any value that is not the constant 0. See
5509 @samp{movmem@var{m}} for a discussion of the choice of mode.
5511 The fourth operand is the known alignment of the destination, in the form
5512 of a @code{const_int} rtx. Thus, if the compiler knows that the
5513 destination is word-aligned, it may provide the value 4 for this
5516 Optional operands 5 and 6 specify expected alignment and size of block
5517 respectively. The expected alignment differs from alignment in operand 4
5518 in a way that the blocks are not required to be aligned according to it in
5519 all cases. This expected alignment is also in bytes, just like operand 4.
5520 Expected size, when unknown, is set to @code{(const_int -1)}.
5521 Operand 7 is the minimal size of the block and operand 8 is the
5522 maximal size of the block (NULL if it can not be represented as CONST_INT).
5523 Operand 9 is the probable maximal size (i.e. we can not rely on it for correctness,
5524 but it can be used for choosing proper code sequence for a given size).
5526 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
5528 @cindex @code{cmpstrn@var{m}} instruction pattern
5529 @item @samp{cmpstrn@var{m}}
5530 String compare instruction, with five operands. Operand 0 is the output;
5531 it has mode @var{m}. The remaining four operands are like the operands
5532 of @samp{movmem@var{m}}. The two memory blocks specified are compared
5533 byte by byte in lexicographic order starting at the beginning of each
5534 string. The instruction is not allowed to prefetch more than one byte
5535 at a time since either string may end in the first byte and reading past
5536 that may access an invalid page or segment and cause a fault. The
5537 comparison terminates early if the fetched bytes are different or if
5538 they are equal to zero. The effect of the instruction is to store a
5539 value in operand 0 whose sign indicates the result of the comparison.
5541 @cindex @code{cmpstr@var{m}} instruction pattern
5542 @item @samp{cmpstr@var{m}}
5543 String compare instruction, without known maximum length. Operand 0 is the
5544 output; it has mode @var{m}. The second and third operand are the blocks of
5545 memory to be compared; both are @code{mem:BLK} with an address in mode
5548 The fourth operand is the known shared alignment of the source and
5549 destination, in the form of a @code{const_int} rtx. Thus, if the
5550 compiler knows that both source and destination are word-aligned,
5551 it may provide the value 4 for this operand.
5553 The two memory blocks specified are compared byte by byte in lexicographic
5554 order starting at the beginning of each string. The instruction is not allowed
5555 to prefetch more than one byte at a time since either string may end in the
5556 first byte and reading past that may access an invalid page or segment and
5557 cause a fault. The comparison will terminate when the fetched bytes
5558 are different or if they are equal to zero. The effect of the
5559 instruction is to store a value in operand 0 whose sign indicates the
5560 result of the comparison.
5562 @cindex @code{cmpmem@var{m}} instruction pattern
5563 @item @samp{cmpmem@var{m}}
5564 Block compare instruction, with five operands like the operands
5565 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
5566 byte by byte in lexicographic order starting at the beginning of each
5567 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
5568 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
5569 the comparison will not stop if both bytes are zero. The effect of
5570 the instruction is to store a value in operand 0 whose sign indicates
5571 the result of the comparison.
5573 @cindex @code{strlen@var{m}} instruction pattern
5574 @item @samp{strlen@var{m}}
5575 Compute the length of a string, with three operands.
5576 Operand 0 is the result (of mode @var{m}), operand 1 is
5577 a @code{mem} referring to the first character of the string,
5578 operand 2 is the character to search for (normally zero),
5579 and operand 3 is a constant describing the known alignment
5580 of the beginning of the string.
5582 @cindex @code{float@var{m}@var{n}2} instruction pattern
5583 @item @samp{float@var{m}@var{n}2}
5584 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
5585 floating point mode @var{n} and store in operand 0 (which has mode
5588 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
5589 @item @samp{floatuns@var{m}@var{n}2}
5590 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
5591 to floating point mode @var{n} and store in operand 0 (which has mode
5594 @cindex @code{fix@var{m}@var{n}2} instruction pattern
5595 @item @samp{fix@var{m}@var{n}2}
5596 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5597 point mode @var{n} as a signed number and store in operand 0 (which
5598 has mode @var{n}). This instruction's result is defined only when
5599 the value of operand 1 is an integer.
5601 If the machine description defines this pattern, it also needs to
5602 define the @code{ftrunc} pattern.
5604 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
5605 @item @samp{fixuns@var{m}@var{n}2}
5606 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5607 point mode @var{n} as an unsigned number and store in operand 0 (which
5608 has mode @var{n}). This instruction's result is defined only when the
5609 value of operand 1 is an integer.
5611 @cindex @code{ftrunc@var{m}2} instruction pattern
5612 @item @samp{ftrunc@var{m}2}
5613 Convert operand 1 (valid for floating point mode @var{m}) to an
5614 integer value, still represented in floating point mode @var{m}, and
5615 store it in operand 0 (valid for floating point mode @var{m}).
5617 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
5618 @item @samp{fix_trunc@var{m}@var{n}2}
5619 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
5620 of mode @var{m} by converting the value to an integer.
5622 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
5623 @item @samp{fixuns_trunc@var{m}@var{n}2}
5624 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
5625 value of mode @var{m} by converting the value to an integer.
5627 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
5628 @item @samp{trunc@var{m}@var{n}2}
5629 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
5630 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5631 point or both floating point.
5633 @cindex @code{extend@var{m}@var{n}2} instruction pattern
5634 @item @samp{extend@var{m}@var{n}2}
5635 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5636 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5637 point or both floating point.
5639 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
5640 @item @samp{zero_extend@var{m}@var{n}2}
5641 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5642 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5645 @cindex @code{fract@var{m}@var{n}2} instruction pattern
5646 @item @samp{fract@var{m}@var{n}2}
5647 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5648 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5649 could be fixed-point to fixed-point, signed integer to fixed-point,
5650 fixed-point to signed integer, floating-point to fixed-point,
5651 or fixed-point to floating-point.
5652 When overflows or underflows happen, the results are undefined.
5654 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
5655 @item @samp{satfract@var{m}@var{n}2}
5656 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5657 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5658 could be fixed-point to fixed-point, signed integer to fixed-point,
5659 or floating-point to fixed-point.
5660 When overflows or underflows happen, the instruction saturates the
5661 results to the maximum or the minimum.
5663 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
5664 @item @samp{fractuns@var{m}@var{n}2}
5665 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5666 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5667 could be unsigned integer to fixed-point, or
5668 fixed-point to unsigned integer.
5669 When overflows or underflows happen, the results are undefined.
5671 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
5672 @item @samp{satfractuns@var{m}@var{n}2}
5673 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
5674 @var{n} and store in operand 0 (which has mode @var{n}).
5675 When overflows or underflows happen, the instruction saturates the
5676 results to the maximum or the minimum.
5678 @cindex @code{extv@var{m}} instruction pattern
5679 @item @samp{extv@var{m}}
5680 Extract a bit-field from register operand 1, sign-extend it, and store
5681 it in operand 0. Operand 2 specifies the width of the field in bits
5682 and operand 3 the starting bit, which counts from the most significant
5683 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
5686 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
5687 target-specific mode.
5689 @cindex @code{extvmisalign@var{m}} instruction pattern
5690 @item @samp{extvmisalign@var{m}}
5691 Extract a bit-field from memory operand 1, sign extend it, and store
5692 it in operand 0. Operand 2 specifies the width in bits and operand 3
5693 the starting bit. The starting bit is always somewhere in the first byte of
5694 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5695 is true and from the least significant bit otherwise.
5697 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
5698 Operands 2 and 3 have a target-specific mode.
5700 The instruction must not read beyond the last byte of the bit-field.
5702 @cindex @code{extzv@var{m}} instruction pattern
5703 @item @samp{extzv@var{m}}
5704 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
5706 @cindex @code{extzvmisalign@var{m}} instruction pattern
5707 @item @samp{extzvmisalign@var{m}}
5708 Like @samp{extvmisalign@var{m}} except that the bit-field value is
5711 @cindex @code{insv@var{m}} instruction pattern
5712 @item @samp{insv@var{m}}
5713 Insert operand 3 into a bit-field of register operand 0. Operand 1
5714 specifies the width of the field in bits and operand 2 the starting bit,
5715 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5716 is true and from the least significant bit otherwise.
5718 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
5719 target-specific mode.
5721 @cindex @code{insvmisalign@var{m}} instruction pattern
5722 @item @samp{insvmisalign@var{m}}
5723 Insert operand 3 into a bit-field of memory operand 0. Operand 1
5724 specifies the width of the field in bits and operand 2 the starting bit.
5725 The starting bit is always somewhere in the first byte of operand 0;
5726 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5727 is true and from the least significant bit otherwise.
5729 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
5730 Operands 1 and 2 have a target-specific mode.
5732 The instruction must not read or write beyond the last byte of the bit-field.
5734 @cindex @code{extv} instruction pattern
5736 Extract a bit-field from operand 1 (a register or memory operand), where
5737 operand 2 specifies the width in bits and operand 3 the starting bit,
5738 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
5739 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
5740 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
5741 be valid for @code{word_mode}.
5743 The RTL generation pass generates this instruction only with constants
5744 for operands 2 and 3 and the constant is never zero for operand 2.
5746 The bit-field value is sign-extended to a full word integer
5747 before it is stored in operand 0.
5749 This pattern is deprecated; please use @samp{extv@var{m}} and
5750 @code{extvmisalign@var{m}} instead.
5752 @cindex @code{extzv} instruction pattern
5754 Like @samp{extv} except that the bit-field value is zero-extended.
5756 This pattern is deprecated; please use @samp{extzv@var{m}} and
5757 @code{extzvmisalign@var{m}} instead.
5759 @cindex @code{insv} instruction pattern
5761 Store operand 3 (which must be valid for @code{word_mode}) into a
5762 bit-field in operand 0, where operand 1 specifies the width in bits and
5763 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
5764 @code{word_mode}; often @code{word_mode} is allowed only for registers.
5765 Operands 1 and 2 must be valid for @code{word_mode}.
5767 The RTL generation pass generates this instruction only with constants
5768 for operands 1 and 2 and the constant is never zero for operand 1.
5770 This pattern is deprecated; please use @samp{insv@var{m}} and
5771 @code{insvmisalign@var{m}} instead.
5773 @cindex @code{mov@var{mode}cc} instruction pattern
5774 @item @samp{mov@var{mode}cc}
5775 Conditionally move operand 2 or operand 3 into operand 0 according to the
5776 comparison in operand 1. If the comparison is true, operand 2 is moved
5777 into operand 0, otherwise operand 3 is moved.
5779 The mode of the operands being compared need not be the same as the operands
5780 being moved. Some machines, sparc64 for example, have instructions that
5781 conditionally move an integer value based on the floating point condition
5782 codes and vice versa.
5784 If the machine does not have conditional move instructions, do not
5785 define these patterns.
5787 @cindex @code{add@var{mode}cc} instruction pattern
5788 @item @samp{add@var{mode}cc}
5789 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
5790 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
5791 comparison in operand 1. If the comparison is false, operand 2 is moved into
5792 operand 0, otherwise (operand 2 + operand 3) is moved.
5794 @cindex @code{cstore@var{mode}4} instruction pattern
5795 @item @samp{cstore@var{mode}4}
5796 Store zero or nonzero in operand 0 according to whether a comparison
5797 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
5798 are the first and second operand of the comparison, respectively.
5799 You specify the mode that operand 0 must have when you write the
5800 @code{match_operand} expression. The compiler automatically sees which
5801 mode you have used and supplies an operand of that mode.
5803 The value stored for a true condition must have 1 as its low bit, or
5804 else must be negative. Otherwise the instruction is not suitable and
5805 you should omit it from the machine description. You describe to the
5806 compiler exactly which value is stored by defining the macro
5807 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
5808 found that can be used for all the possible comparison operators, you
5809 should pick one and use a @code{define_expand} to map all results
5810 onto the one you chose.
5812 These operations may @code{FAIL}, but should do so only in relatively
5813 uncommon cases; if they would @code{FAIL} for common cases involving
5814 integer comparisons, it is best to restrict the predicates to not
5815 allow these operands. Likewise if a given comparison operator will
5816 always fail, independent of the operands (for floating-point modes, the
5817 @code{ordered_comparison_operator} predicate is often useful in this case).
5819 If this pattern is omitted, the compiler will generate a conditional
5820 branch---for example, it may copy a constant one to the target and branching
5821 around an assignment of zero to the target---or a libcall. If the predicate
5822 for operand 1 only rejects some operators, it will also try reordering the
5823 operands and/or inverting the result value (e.g.@: by an exclusive OR).
5824 These possibilities could be cheaper or equivalent to the instructions
5825 used for the @samp{cstore@var{mode}4} pattern followed by those required
5826 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
5827 case, you can and should make operand 1's predicate reject some operators
5828 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
5829 from the machine description.
5831 @cindex @code{cbranch@var{mode}4} instruction pattern
5832 @item @samp{cbranch@var{mode}4}
5833 Conditional branch instruction combined with a compare instruction.
5834 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
5835 first and second operands of the comparison, respectively. Operand 3
5836 is a @code{label_ref} that refers to the label to jump to.
5838 @cindex @code{jump} instruction pattern
5840 A jump inside a function; an unconditional branch. Operand 0 is the
5841 @code{label_ref} of the label to jump to. This pattern name is mandatory
5844 @cindex @code{call} instruction pattern
5846 Subroutine call instruction returning no value. Operand 0 is the
5847 function to call; operand 1 is the number of bytes of arguments pushed
5848 as a @code{const_int}; operand 2 is the number of registers used as
5851 On most machines, operand 2 is not actually stored into the RTL
5852 pattern. It is supplied for the sake of some RISC machines which need
5853 to put this information into the assembler code; they can put it in
5854 the RTL instead of operand 1.
5856 Operand 0 should be a @code{mem} RTX whose address is the address of the
5857 function. Note, however, that this address can be a @code{symbol_ref}
5858 expression even if it would not be a legitimate memory address on the
5859 target machine. If it is also not a valid argument for a call
5860 instruction, the pattern for this operation should be a
5861 @code{define_expand} (@pxref{Expander Definitions}) that places the
5862 address into a register and uses that register in the call instruction.
5864 @cindex @code{call_value} instruction pattern
5865 @item @samp{call_value}
5866 Subroutine call instruction returning a value. Operand 0 is the hard
5867 register in which the value is returned. There are three more
5868 operands, the same as the three operands of the @samp{call}
5869 instruction (but with numbers increased by one).
5871 Subroutines that return @code{BLKmode} objects use the @samp{call}
5874 @cindex @code{call_pop} instruction pattern
5875 @cindex @code{call_value_pop} instruction pattern
5876 @item @samp{call_pop}, @samp{call_value_pop}
5877 Similar to @samp{call} and @samp{call_value}, except used if defined and
5878 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5879 that contains both the function call and a @code{set} to indicate the
5880 adjustment made to the frame pointer.
5882 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
5883 patterns increases the number of functions for which the frame pointer
5884 can be eliminated, if desired.
5886 @cindex @code{untyped_call} instruction pattern
5887 @item @samp{untyped_call}
5888 Subroutine call instruction returning a value of any type. Operand 0 is
5889 the function to call; operand 1 is a memory location where the result of
5890 calling the function is to be stored; operand 2 is a @code{parallel}
5891 expression where each element is a @code{set} expression that indicates
5892 the saving of a function return value into the result block.
5894 This instruction pattern should be defined to support
5895 @code{__builtin_apply} on machines where special instructions are needed
5896 to call a subroutine with arbitrary arguments or to save the value
5897 returned. This instruction pattern is required on machines that have
5898 multiple registers that can hold a return value
5899 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5901 @cindex @code{return} instruction pattern
5903 Subroutine return instruction. This instruction pattern name should be
5904 defined only if a single instruction can do all the work of returning
5907 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
5908 RTL generation phase. In this case it is to support machines where
5909 multiple instructions are usually needed to return from a function, but
5910 some class of functions only requires one instruction to implement a
5911 return. Normally, the applicable functions are those which do not need
5912 to save any registers or allocate stack space.
5914 It is valid for this pattern to expand to an instruction using
5915 @code{simple_return} if no epilogue is required.
5917 @cindex @code{simple_return} instruction pattern
5918 @item @samp{simple_return}
5919 Subroutine return instruction. This instruction pattern name should be
5920 defined only if a single instruction can do all the work of returning
5921 from a function on a path where no epilogue is required. This pattern
5922 is very similar to the @code{return} instruction pattern, but it is emitted
5923 only by the shrink-wrapping optimization on paths where the function
5924 prologue has not been executed, and a function return should occur without
5925 any of the effects of the epilogue. Additional uses may be introduced on
5926 paths where both the prologue and the epilogue have executed.
5928 @findex reload_completed
5929 @findex leaf_function_p
5930 For such machines, the condition specified in this pattern should only
5931 be true when @code{reload_completed} is nonzero and the function's
5932 epilogue would only be a single instruction. For machines with register
5933 windows, the routine @code{leaf_function_p} may be used to determine if
5934 a register window push is required.
5936 Machines that have conditional return instructions should define patterns
5942 (if_then_else (match_operator
5943 0 "comparison_operator"
5944 [(cc0) (const_int 0)])
5951 where @var{condition} would normally be the same condition specified on the
5952 named @samp{return} pattern.
5954 @cindex @code{untyped_return} instruction pattern
5955 @item @samp{untyped_return}
5956 Untyped subroutine return instruction. This instruction pattern should
5957 be defined to support @code{__builtin_return} on machines where special
5958 instructions are needed to return a value of any type.
5960 Operand 0 is a memory location where the result of calling a function
5961 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
5962 expression where each element is a @code{set} expression that indicates
5963 the restoring of a function return value from the result block.
5965 @cindex @code{nop} instruction pattern
5967 No-op instruction. This instruction pattern name should always be defined
5968 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5971 @cindex @code{indirect_jump} instruction pattern
5972 @item @samp{indirect_jump}
5973 An instruction to jump to an address which is operand zero.
5974 This pattern name is mandatory on all machines.
5976 @cindex @code{casesi} instruction pattern
5978 Instruction to jump through a dispatch table, including bounds checking.
5979 This instruction takes five operands:
5983 The index to dispatch on, which has mode @code{SImode}.
5986 The lower bound for indices in the table, an integer constant.
5989 The total range of indices in the table---the largest index
5990 minus the smallest one (both inclusive).
5993 A label that precedes the table itself.
5996 A label to jump to if the index has a value outside the bounds.
5999 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
6000 @code{jump_table_data}. The number of elements in the table is one plus the
6001 difference between the upper bound and the lower bound.
6003 @cindex @code{tablejump} instruction pattern
6004 @item @samp{tablejump}
6005 Instruction to jump to a variable address. This is a low-level
6006 capability which can be used to implement a dispatch table when there
6007 is no @samp{casesi} pattern.
6009 This pattern requires two operands: the address or offset, and a label
6010 which should immediately precede the jump table. If the macro
6011 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
6012 operand is an offset which counts from the address of the table; otherwise,
6013 it is an absolute address to jump to. In either case, the first operand has
6016 The @samp{tablejump} insn is always the last insn before the jump
6017 table it uses. Its assembler code normally has no need to use the
6018 second operand, but you should incorporate it in the RTL pattern so
6019 that the jump optimizer will not delete the table as unreachable code.
6022 @cindex @code{decrement_and_branch_until_zero} instruction pattern
6023 @item @samp{decrement_and_branch_until_zero}
6024 Conditional branch instruction that decrements a register and
6025 jumps if the register is nonzero. Operand 0 is the register to
6026 decrement and test; operand 1 is the label to jump to if the
6027 register is nonzero. @xref{Looping Patterns}.
6029 This optional instruction pattern is only used by the combiner,
6030 typically for loops reversed by the loop optimizer when strength
6031 reduction is enabled.
6033 @cindex @code{doloop_end} instruction pattern
6034 @item @samp{doloop_end}
6035 Conditional branch instruction that decrements a register and
6036 jumps if the register is nonzero. Operand 0 is the register to
6037 decrement and test; operand 1 is the label to jump to if the
6038 register is nonzero.
6039 @xref{Looping Patterns}.
6041 This optional instruction pattern should be defined for machines with
6042 low-overhead looping instructions as the loop optimizer will try to
6043 modify suitable loops to utilize it. The target hook
6044 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
6045 low-overhead loops can be used.
6047 @cindex @code{doloop_begin} instruction pattern
6048 @item @samp{doloop_begin}
6049 Companion instruction to @code{doloop_end} required for machines that
6050 need to perform some initialization, such as loading a special counter
6051 register. Operand 1 is the associated @code{doloop_end} pattern and
6052 operand 0 is the register that it decrements.
6054 If initialization insns do not always need to be emitted, use a
6055 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
6057 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
6058 @item @samp{canonicalize_funcptr_for_compare}
6059 Canonicalize the function pointer in operand 1 and store the result
6062 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
6063 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
6064 and also has mode @code{Pmode}.
6066 Canonicalization of a function pointer usually involves computing
6067 the address of the function which would be called if the function
6068 pointer were used in an indirect call.
6070 Only define this pattern if function pointers on the target machine
6071 can have different values but still call the same function when
6072 used in an indirect call.
6074 @cindex @code{save_stack_block} instruction pattern
6075 @cindex @code{save_stack_function} instruction pattern
6076 @cindex @code{save_stack_nonlocal} instruction pattern
6077 @cindex @code{restore_stack_block} instruction pattern
6078 @cindex @code{restore_stack_function} instruction pattern
6079 @cindex @code{restore_stack_nonlocal} instruction pattern
6080 @item @samp{save_stack_block}
6081 @itemx @samp{save_stack_function}
6082 @itemx @samp{save_stack_nonlocal}
6083 @itemx @samp{restore_stack_block}
6084 @itemx @samp{restore_stack_function}
6085 @itemx @samp{restore_stack_nonlocal}
6086 Most machines save and restore the stack pointer by copying it to or
6087 from an object of mode @code{Pmode}. Do not define these patterns on
6090 Some machines require special handling for stack pointer saves and
6091 restores. On those machines, define the patterns corresponding to the
6092 non-standard cases by using a @code{define_expand} (@pxref{Expander
6093 Definitions}) that produces the required insns. The three types of
6094 saves and restores are:
6098 @samp{save_stack_block} saves the stack pointer at the start of a block
6099 that allocates a variable-sized object, and @samp{restore_stack_block}
6100 restores the stack pointer when the block is exited.
6103 @samp{save_stack_function} and @samp{restore_stack_function} do a
6104 similar job for the outermost block of a function and are used when the
6105 function allocates variable-sized objects or calls @code{alloca}. Only
6106 the epilogue uses the restored stack pointer, allowing a simpler save or
6107 restore sequence on some machines.
6110 @samp{save_stack_nonlocal} is used in functions that contain labels
6111 branched to by nested functions. It saves the stack pointer in such a
6112 way that the inner function can use @samp{restore_stack_nonlocal} to
6113 restore the stack pointer. The compiler generates code to restore the
6114 frame and argument pointer registers, but some machines require saving
6115 and restoring additional data such as register window information or
6116 stack backchains. Place insns in these patterns to save and restore any
6120 When saving the stack pointer, operand 0 is the save area and operand 1
6121 is the stack pointer. The mode used to allocate the save area defaults
6122 to @code{Pmode} but you can override that choice by defining the
6123 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6124 specify an integral mode, or @code{VOIDmode} if no save area is needed
6125 for a particular type of save (either because no save is needed or
6126 because a machine-specific save area can be used). Operand 0 is the
6127 stack pointer and operand 1 is the save area for restore operations. If
6128 @samp{save_stack_block} is defined, operand 0 must not be
6129 @code{VOIDmode} since these saves can be arbitrarily nested.
6131 A save area is a @code{mem} that is at a constant offset from
6132 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6133 nonlocal gotos and a @code{reg} in the other two cases.
6135 @cindex @code{allocate_stack} instruction pattern
6136 @item @samp{allocate_stack}
6137 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6138 the stack pointer to create space for dynamically allocated data.
6140 Store the resultant pointer to this space into operand 0. If you
6141 are allocating space from the main stack, do this by emitting a
6142 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6143 If you are allocating the space elsewhere, generate code to copy the
6144 location of the space to operand 0. In the latter case, you must
6145 ensure this space gets freed when the corresponding space on the main
6148 Do not define this pattern if all that must be done is the subtraction.
6149 Some machines require other operations such as stack probes or
6150 maintaining the back chain. Define this pattern to emit those
6151 operations in addition to updating the stack pointer.
6153 @cindex @code{check_stack} instruction pattern
6154 @item @samp{check_stack}
6155 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
6156 probing the stack, define this pattern to perform the needed check and signal
6157 an error if the stack has overflowed. The single operand is the address in
6158 the stack farthest from the current stack pointer that you need to validate.
6159 Normally, on platforms where this pattern is needed, you would obtain the
6160 stack limit from a global or thread-specific variable or register.
6162 @cindex @code{probe_stack_address} instruction pattern
6163 @item @samp{probe_stack_address}
6164 If stack checking (@pxref{Stack Checking}) can be done on your system by
6165 probing the stack but without the need to actually access it, define this
6166 pattern and signal an error if the stack has overflowed. The single operand
6167 is the memory address in the stack that needs to be probed.
6169 @cindex @code{probe_stack} instruction pattern
6170 @item @samp{probe_stack}
6171 If stack checking (@pxref{Stack Checking}) can be done on your system by
6172 probing the stack but doing it with a ``store zero'' instruction is not valid
6173 or optimal, define this pattern to do the probing differently and signal an
6174 error if the stack has overflowed. The single operand is the memory reference
6175 in the stack that needs to be probed.
6177 @cindex @code{nonlocal_goto} instruction pattern
6178 @item @samp{nonlocal_goto}
6179 Emit code to generate a non-local goto, e.g., a jump from one function
6180 to a label in an outer function. This pattern has four arguments,
6181 each representing a value to be used in the jump. The first
6182 argument is to be loaded into the frame pointer, the second is
6183 the address to branch to (code to dispatch to the actual label),
6184 the third is the address of a location where the stack is saved,
6185 and the last is the address of the label, to be placed in the
6186 location for the incoming static chain.
6188 On most machines you need not define this pattern, since GCC will
6189 already generate the correct code, which is to load the frame pointer
6190 and static chain, restore the stack (using the
6191 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
6192 to the dispatcher. You need only define this pattern if this code will
6193 not work on your machine.
6195 @cindex @code{nonlocal_goto_receiver} instruction pattern
6196 @item @samp{nonlocal_goto_receiver}
6197 This pattern, if defined, contains code needed at the target of a
6198 nonlocal goto after the code already generated by GCC@. You will not
6199 normally need to define this pattern. A typical reason why you might
6200 need this pattern is if some value, such as a pointer to a global table,
6201 must be restored when the frame pointer is restored. Note that a nonlocal
6202 goto only occurs within a unit-of-translation, so a global table pointer
6203 that is shared by all functions of a given module need not be restored.
6204 There are no arguments.
6206 @cindex @code{exception_receiver} instruction pattern
6207 @item @samp{exception_receiver}
6208 This pattern, if defined, contains code needed at the site of an
6209 exception handler that isn't needed at the site of a nonlocal goto. You
6210 will not normally need to define this pattern. A typical reason why you
6211 might need this pattern is if some value, such as a pointer to a global
6212 table, must be restored after control flow is branched to the handler of
6213 an exception. There are no arguments.
6215 @cindex @code{builtin_setjmp_setup} instruction pattern
6216 @item @samp{builtin_setjmp_setup}
6217 This pattern, if defined, contains additional code needed to initialize
6218 the @code{jmp_buf}. You will not normally need to define this pattern.
6219 A typical reason why you might need this pattern is if some value, such
6220 as a pointer to a global table, must be restored. Though it is
6221 preferred that the pointer value be recalculated if possible (given the
6222 address of a label for instance). The single argument is a pointer to
6223 the @code{jmp_buf}. Note that the buffer is five words long and that
6224 the first three are normally used by the generic mechanism.
6226 @cindex @code{builtin_setjmp_receiver} instruction pattern
6227 @item @samp{builtin_setjmp_receiver}
6228 This pattern, if defined, contains code needed at the site of a
6229 built-in setjmp that isn't needed at the site of a nonlocal goto. You
6230 will not normally need to define this pattern. A typical reason why you
6231 might need this pattern is if some value, such as a pointer to a global
6232 table, must be restored. It takes one argument, which is the label
6233 to which builtin_longjmp transferred control; this pattern may be emitted
6234 at a small offset from that label.
6236 @cindex @code{builtin_longjmp} instruction pattern
6237 @item @samp{builtin_longjmp}
6238 This pattern, if defined, performs the entire action of the longjmp.
6239 You will not normally need to define this pattern unless you also define
6240 @code{builtin_setjmp_setup}. The single argument is a pointer to the
6243 @cindex @code{eh_return} instruction pattern
6244 @item @samp{eh_return}
6245 This pattern, if defined, affects the way @code{__builtin_eh_return},
6246 and thence the call frame exception handling library routines, are
6247 built. It is intended to handle non-trivial actions needed along
6248 the abnormal return path.
6250 The address of the exception handler to which the function should return
6251 is passed as operand to this pattern. It will normally need to copied by
6252 the pattern to some special register or memory location.
6253 If the pattern needs to determine the location of the target call
6254 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6255 if defined; it will have already been assigned.
6257 If this pattern is not defined, the default action will be to simply
6258 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
6259 that macro or this pattern needs to be defined if call frame exception
6260 handling is to be used.
6262 @cindex @code{prologue} instruction pattern
6263 @anchor{prologue instruction pattern}
6264 @item @samp{prologue}
6265 This pattern, if defined, emits RTL for entry to a function. The function
6266 entry is responsible for setting up the stack frame, initializing the frame
6267 pointer register, saving callee saved registers, etc.
6269 Using a prologue pattern is generally preferred over defining
6270 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
6272 The @code{prologue} pattern is particularly useful for targets which perform
6273 instruction scheduling.
6275 @cindex @code{window_save} instruction pattern
6276 @anchor{window_save instruction pattern}
6277 @item @samp{window_save}
6278 This pattern, if defined, emits RTL for a register window save. It should
6279 be defined if the target machine has register windows but the window events
6280 are decoupled from calls to subroutines. The canonical example is the SPARC
6283 @cindex @code{epilogue} instruction pattern
6284 @anchor{epilogue instruction pattern}
6285 @item @samp{epilogue}
6286 This pattern emits RTL for exit from a function. The function
6287 exit is responsible for deallocating the stack frame, restoring callee saved
6288 registers and emitting the return instruction.
6290 Using an epilogue pattern is generally preferred over defining
6291 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
6293 The @code{epilogue} pattern is particularly useful for targets which perform
6294 instruction scheduling or which have delay slots for their return instruction.
6296 @cindex @code{sibcall_epilogue} instruction pattern
6297 @item @samp{sibcall_epilogue}
6298 This pattern, if defined, emits RTL for exit from a function without the final
6299 branch back to the calling function. This pattern will be emitted before any
6300 sibling call (aka tail call) sites.
6302 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
6303 parameter passing or any stack slots for arguments passed to the current
6306 @cindex @code{trap} instruction pattern
6308 This pattern, if defined, signals an error, typically by causing some
6309 kind of signal to be raised. Among other places, it is used by the Java
6310 front end to signal `invalid array index' exceptions.
6312 @cindex @code{ctrap@var{MM}4} instruction pattern
6313 @item @samp{ctrap@var{MM}4}
6314 Conditional trap instruction. Operand 0 is a piece of RTL which
6315 performs a comparison, and operands 1 and 2 are the arms of the
6316 comparison. Operand 3 is the trap code, an integer.
6318 A typical @code{ctrap} pattern looks like
6321 (define_insn "ctrapsi4"
6322 [(trap_if (match_operator 0 "trap_operator"
6323 [(match_operand 1 "register_operand")
6324 (match_operand 2 "immediate_operand")])
6325 (match_operand 3 "const_int_operand" "i"))]
6330 @cindex @code{prefetch} instruction pattern
6331 @item @samp{prefetch}
6332 This pattern, if defined, emits code for a non-faulting data prefetch
6333 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
6334 is a constant 1 if the prefetch is preparing for a write to the memory
6335 address, or a constant 0 otherwise. Operand 2 is the expected degree of
6336 temporal locality of the data and is a value between 0 and 3, inclusive; 0
6337 means that the data has no temporal locality, so it need not be left in the
6338 cache after the access; 3 means that the data has a high degree of temporal
6339 locality and should be left in all levels of cache possible; 1 and 2 mean,
6340 respectively, a low or moderate degree of temporal locality.
6342 Targets that do not support write prefetches or locality hints can ignore
6343 the values of operands 1 and 2.
6345 @cindex @code{blockage} instruction pattern
6346 @item @samp{blockage}
6347 This pattern defines a pseudo insn that prevents the instruction
6348 scheduler and other passes from moving instructions and using register
6349 equivalences across the boundary defined by the blockage insn.
6350 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
6352 @cindex @code{memory_barrier} instruction pattern
6353 @item @samp{memory_barrier}
6354 If the target memory model is not fully synchronous, then this pattern
6355 should be defined to an instruction that orders both loads and stores
6356 before the instruction with respect to loads and stores after the instruction.
6357 This pattern has no operands.
6359 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
6360 @item @samp{sync_compare_and_swap@var{mode}}
6361 This pattern, if defined, emits code for an atomic compare-and-swap
6362 operation. Operand 1 is the memory on which the atomic operation is
6363 performed. Operand 2 is the ``old'' value to be compared against the
6364 current contents of the memory location. Operand 3 is the ``new'' value
6365 to store in the memory if the compare succeeds. Operand 0 is the result
6366 of the operation; it should contain the contents of the memory
6367 before the operation. If the compare succeeds, this should obviously be
6368 a copy of operand 2.
6370 This pattern must show that both operand 0 and operand 1 are modified.
6372 This pattern must issue any memory barrier instructions such that all
6373 memory operations before the atomic operation occur before the atomic
6374 operation and all memory operations after the atomic operation occur
6375 after the atomic operation.
6377 For targets where the success or failure of the compare-and-swap
6378 operation is available via the status flags, it is possible to
6379 avoid a separate compare operation and issue the subsequent
6380 branch or store-flag operation immediately after the compare-and-swap.
6381 To this end, GCC will look for a @code{MODE_CC} set in the
6382 output of @code{sync_compare_and_swap@var{mode}}; if the machine
6383 description includes such a set, the target should also define special
6384 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
6385 be able to take the destination of the @code{MODE_CC} set and pass it
6386 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
6387 operand of the comparison (the second will be @code{(const_int 0)}).
6389 For targets where the operating system may provide support for this
6390 operation via library calls, the @code{sync_compare_and_swap_optab}
6391 may be initialized to a function with the same interface as the
6392 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
6393 set of @var{__sync} builtins are supported via library calls, the
6394 target can initialize all of the optabs at once with
6395 @code{init_sync_libfuncs}.
6396 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
6397 assumed that these library calls do @emph{not} use any kind of
6398 interruptable locking.
6400 @cindex @code{sync_add@var{mode}} instruction pattern
6401 @cindex @code{sync_sub@var{mode}} instruction pattern
6402 @cindex @code{sync_ior@var{mode}} instruction pattern
6403 @cindex @code{sync_and@var{mode}} instruction pattern
6404 @cindex @code{sync_xor@var{mode}} instruction pattern
6405 @cindex @code{sync_nand@var{mode}} instruction pattern
6406 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
6407 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
6408 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
6409 These patterns emit code for an atomic operation on memory.
6410 Operand 0 is the memory on which the atomic operation is performed.
6411 Operand 1 is the second operand to the binary operator.
6413 This pattern must issue any memory barrier instructions such that all
6414 memory operations before the atomic operation occur before the atomic
6415 operation and all memory operations after the atomic operation occur
6416 after the atomic operation.
6418 If these patterns are not defined, the operation will be constructed
6419 from a compare-and-swap operation, if defined.
6421 @cindex @code{sync_old_add@var{mode}} instruction pattern
6422 @cindex @code{sync_old_sub@var{mode}} instruction pattern
6423 @cindex @code{sync_old_ior@var{mode}} instruction pattern
6424 @cindex @code{sync_old_and@var{mode}} instruction pattern
6425 @cindex @code{sync_old_xor@var{mode}} instruction pattern
6426 @cindex @code{sync_old_nand@var{mode}} instruction pattern
6427 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
6428 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
6429 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
6430 These patterns emit code for an atomic operation on memory,
6431 and return the value that the memory contained before the operation.
6432 Operand 0 is the result value, operand 1 is the memory on which the
6433 atomic operation is performed, and operand 2 is the second operand
6434 to the binary operator.
6436 This pattern must issue any memory barrier instructions such that all
6437 memory operations before the atomic operation occur before the atomic
6438 operation and all memory operations after the atomic operation occur
6439 after the atomic operation.
6441 If these patterns are not defined, the operation will be constructed
6442 from a compare-and-swap operation, if defined.
6444 @cindex @code{sync_new_add@var{mode}} instruction pattern
6445 @cindex @code{sync_new_sub@var{mode}} instruction pattern
6446 @cindex @code{sync_new_ior@var{mode}} instruction pattern
6447 @cindex @code{sync_new_and@var{mode}} instruction pattern
6448 @cindex @code{sync_new_xor@var{mode}} instruction pattern
6449 @cindex @code{sync_new_nand@var{mode}} instruction pattern
6450 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
6451 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
6452 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
6453 These patterns are like their @code{sync_old_@var{op}} counterparts,
6454 except that they return the value that exists in the memory location
6455 after the operation, rather than before the operation.
6457 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
6458 @item @samp{sync_lock_test_and_set@var{mode}}
6459 This pattern takes two forms, based on the capabilities of the target.
6460 In either case, operand 0 is the result of the operand, operand 1 is
6461 the memory on which the atomic operation is performed, and operand 2
6462 is the value to set in the lock.
6464 In the ideal case, this operation is an atomic exchange operation, in
6465 which the previous value in memory operand is copied into the result
6466 operand, and the value operand is stored in the memory operand.
6468 For less capable targets, any value operand that is not the constant 1
6469 should be rejected with @code{FAIL}. In this case the target may use
6470 an atomic test-and-set bit operation. The result operand should contain
6471 1 if the bit was previously set and 0 if the bit was previously clear.
6472 The true contents of the memory operand are implementation defined.
6474 This pattern must issue any memory barrier instructions such that the
6475 pattern as a whole acts as an acquire barrier, that is all memory
6476 operations after the pattern do not occur until the lock is acquired.
6478 If this pattern is not defined, the operation will be constructed from
6479 a compare-and-swap operation, if defined.
6481 @cindex @code{sync_lock_release@var{mode}} instruction pattern
6482 @item @samp{sync_lock_release@var{mode}}
6483 This pattern, if defined, releases a lock set by
6484 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
6485 that contains the lock; operand 1 is the value to store in the lock.
6487 If the target doesn't implement full semantics for
6488 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
6489 the constant 0 should be rejected with @code{FAIL}, and the true contents
6490 of the memory operand are implementation defined.
6492 This pattern must issue any memory barrier instructions such that the
6493 pattern as a whole acts as a release barrier, that is the lock is
6494 released only after all previous memory operations have completed.
6496 If this pattern is not defined, then a @code{memory_barrier} pattern
6497 will be emitted, followed by a store of the value to the memory operand.
6499 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
6500 @item @samp{atomic_compare_and_swap@var{mode}}
6501 This pattern, if defined, emits code for an atomic compare-and-swap
6502 operation with memory model semantics. Operand 2 is the memory on which
6503 the atomic operation is performed. Operand 0 is an output operand which
6504 is set to true or false based on whether the operation succeeded. Operand
6505 1 is an output operand which is set to the contents of the memory before
6506 the operation was attempted. Operand 3 is the value that is expected to
6507 be in memory. Operand 4 is the value to put in memory if the expected
6508 value is found there. Operand 5 is set to 1 if this compare and swap is to
6509 be treated as a weak operation. Operand 6 is the memory model to be used
6510 if the operation is a success. Operand 7 is the memory model to be used
6511 if the operation fails.
6513 If memory referred to in operand 2 contains the value in operand 3, then
6514 operand 4 is stored in memory pointed to by operand 2 and fencing based on
6515 the memory model in operand 6 is issued.
6517 If memory referred to in operand 2 does not contain the value in operand 3,
6518 then fencing based on the memory model in operand 7 is issued.
6520 If a target does not support weak compare-and-swap operations, or the port
6521 elects not to implement weak operations, the argument in operand 5 can be
6522 ignored. Note a strong implementation must be provided.
6524 If this pattern is not provided, the @code{__atomic_compare_exchange}
6525 built-in functions will utilize the legacy @code{sync_compare_and_swap}
6526 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
6528 @cindex @code{atomic_load@var{mode}} instruction pattern
6529 @item @samp{atomic_load@var{mode}}
6530 This pattern implements an atomic load operation with memory model
6531 semantics. Operand 1 is the memory address being loaded from. Operand 0
6532 is the result of the load. Operand 2 is the memory model to be used for
6535 If not present, the @code{__atomic_load} built-in function will either
6536 resort to a normal load with memory barriers, or a compare-and-swap
6537 operation if a normal load would not be atomic.
6539 @cindex @code{atomic_store@var{mode}} instruction pattern
6540 @item @samp{atomic_store@var{mode}}
6541 This pattern implements an atomic store operation with memory model
6542 semantics. Operand 0 is the memory address being stored to. Operand 1
6543 is the value to be written. Operand 2 is the memory model to be used for
6546 If not present, the @code{__atomic_store} built-in function will attempt to
6547 perform a normal store and surround it with any required memory fences. If
6548 the store would not be atomic, then an @code{__atomic_exchange} is
6549 attempted with the result being ignored.
6551 @cindex @code{atomic_exchange@var{mode}} instruction pattern
6552 @item @samp{atomic_exchange@var{mode}}
6553 This pattern implements an atomic exchange operation with memory model
6554 semantics. Operand 1 is the memory location the operation is performed on.
6555 Operand 0 is an output operand which is set to the original value contained
6556 in the memory pointed to by operand 1. Operand 2 is the value to be
6557 stored. Operand 3 is the memory model to be used.
6559 If this pattern is not present, the built-in function
6560 @code{__atomic_exchange} will attempt to preform the operation with a
6561 compare and swap loop.
6563 @cindex @code{atomic_add@var{mode}} instruction pattern
6564 @cindex @code{atomic_sub@var{mode}} instruction pattern
6565 @cindex @code{atomic_or@var{mode}} instruction pattern
6566 @cindex @code{atomic_and@var{mode}} instruction pattern
6567 @cindex @code{atomic_xor@var{mode}} instruction pattern
6568 @cindex @code{atomic_nand@var{mode}} instruction pattern
6569 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
6570 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
6571 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
6572 These patterns emit code for an atomic operation on memory with memory
6573 model semantics. Operand 0 is the memory on which the atomic operation is
6574 performed. Operand 1 is the second operand to the binary operator.
6575 Operand 2 is the memory model to be used by the operation.
6577 If these patterns are not defined, attempts will be made to use legacy
6578 @code{sync} patterns, or equivalent patterns which return a result. If
6579 none of these are available a compare-and-swap loop will be used.
6581 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
6582 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
6583 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
6584 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
6585 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
6586 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
6587 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
6588 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
6589 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
6590 These patterns emit code for an atomic operation on memory with memory
6591 model semantics, and return the original value. Operand 0 is an output
6592 operand which contains the value of the memory location before the
6593 operation was performed. Operand 1 is the memory on which the atomic
6594 operation is performed. Operand 2 is the second operand to the binary
6595 operator. Operand 3 is the memory model to be used by the operation.
6597 If these patterns are not defined, attempts will be made to use legacy
6598 @code{sync} patterns. If none of these are available a compare-and-swap
6601 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
6602 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
6603 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
6604 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
6605 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
6606 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
6607 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
6608 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
6609 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
6610 These patterns emit code for an atomic operation on memory with memory
6611 model semantics and return the result after the operation is performed.
6612 Operand 0 is an output operand which contains the value after the
6613 operation. Operand 1 is the memory on which the atomic operation is
6614 performed. Operand 2 is the second operand to the binary operator.
6615 Operand 3 is the memory model to be used by the operation.
6617 If these patterns are not defined, attempts will be made to use legacy
6618 @code{sync} patterns, or equivalent patterns which return the result before
6619 the operation followed by the arithmetic operation required to produce the
6620 result. If none of these are available a compare-and-swap loop will be
6623 @cindex @code{atomic_test_and_set} instruction pattern
6624 @item @samp{atomic_test_and_set}
6625 This pattern emits code for @code{__builtin_atomic_test_and_set}.
6626 Operand 0 is an output operand which is set to true if the previous
6627 previous contents of the byte was "set", and false otherwise. Operand 1
6628 is the @code{QImode} memory to be modified. Operand 2 is the memory
6631 The specific value that defines "set" is implementation defined, and
6632 is normally based on what is performed by the native atomic test and set
6635 @cindex @code{mem_thread_fence@var{mode}} instruction pattern
6636 @item @samp{mem_thread_fence@var{mode}}
6637 This pattern emits code required to implement a thread fence with
6638 memory model semantics. Operand 0 is the memory model to be used.
6640 If this pattern is not specified, all memory models except
6641 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6644 @cindex @code{mem_signal_fence@var{mode}} instruction pattern
6645 @item @samp{mem_signal_fence@var{mode}}
6646 This pattern emits code required to implement a signal fence with
6647 memory model semantics. Operand 0 is the memory model to be used.
6649 This pattern should impact the compiler optimizers the same way that
6650 mem_signal_fence does, but it does not need to issue any barrier
6653 If this pattern is not specified, all memory models except
6654 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6657 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
6658 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
6659 @item @samp{get_thread_pointer@var{mode}}
6660 @itemx @samp{set_thread_pointer@var{mode}}
6661 These patterns emit code that reads/sets the TLS thread pointer. Currently,
6662 these are only needed if the target needs to support the
6663 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
6666 The get/set patterns have a single output/input operand respectively,
6667 with @var{mode} intended to be @code{Pmode}.
6669 @cindex @code{stack_protect_set} instruction pattern
6670 @item @samp{stack_protect_set}
6671 This pattern, if defined, moves a @code{ptr_mode} value from the memory
6672 in operand 1 to the memory in operand 0 without leaving the value in
6673 a register afterward. This is to avoid leaking the value some place
6674 that an attacker might use to rewrite the stack guard slot after
6675 having clobbered it.
6677 If this pattern is not defined, then a plain move pattern is generated.
6679 @cindex @code{stack_protect_test} instruction pattern
6680 @item @samp{stack_protect_test}
6681 This pattern, if defined, compares a @code{ptr_mode} value from the
6682 memory in operand 1 with the memory in operand 0 without leaving the
6683 value in a register afterward and branches to operand 2 if the values
6686 If this pattern is not defined, then a plain compare pattern and
6687 conditional branch pattern is used.
6689 @cindex @code{clear_cache} instruction pattern
6690 @item @samp{clear_cache}
6691 This pattern, if defined, flushes the instruction cache for a region of
6692 memory. The region is bounded to by the Pmode pointers in operand 0
6693 inclusive and operand 1 exclusive.
6695 If this pattern is not defined, a call to the library function
6696 @code{__clear_cache} is used.
6701 @c Each of the following nodes are wrapped in separate
6702 @c "@ifset INTERNALS" to work around memory limits for the default
6703 @c configuration in older tetex distributions. Known to not work:
6704 @c tetex-1.0.7, known to work: tetex-2.0.2.
6706 @node Pattern Ordering
6707 @section When the Order of Patterns Matters
6708 @cindex Pattern Ordering
6709 @cindex Ordering of Patterns
6711 Sometimes an insn can match more than one instruction pattern. Then the
6712 pattern that appears first in the machine description is the one used.
6713 Therefore, more specific patterns (patterns that will match fewer things)
6714 and faster instructions (those that will produce better code when they
6715 do match) should usually go first in the description.
6717 In some cases the effect of ordering the patterns can be used to hide
6718 a pattern when it is not valid. For example, the 68000 has an
6719 instruction for converting a fullword to floating point and another
6720 for converting a byte to floating point. An instruction converting
6721 an integer to floating point could match either one. We put the
6722 pattern to convert the fullword first to make sure that one will
6723 be used rather than the other. (Otherwise a large integer might
6724 be generated as a single-byte immediate quantity, which would not work.)
6725 Instead of using this pattern ordering it would be possible to make the
6726 pattern for convert-a-byte smart enough to deal properly with any
6731 @node Dependent Patterns
6732 @section Interdependence of Patterns
6733 @cindex Dependent Patterns
6734 @cindex Interdependence of Patterns
6736 In some cases machines support instructions identical except for the
6737 machine mode of one or more operands. For example, there may be
6738 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
6742 (set (match_operand:SI 0 @dots{})
6743 (extend:SI (match_operand:HI 1 @dots{})))
6745 (set (match_operand:SI 0 @dots{})
6746 (extend:SI (match_operand:QI 1 @dots{})))
6750 Constant integers do not specify a machine mode, so an instruction to
6751 extend a constant value could match either pattern. The pattern it
6752 actually will match is the one that appears first in the file. For correct
6753 results, this must be the one for the widest possible mode (@code{HImode},
6754 here). If the pattern matches the @code{QImode} instruction, the results
6755 will be incorrect if the constant value does not actually fit that mode.
6757 Such instructions to extend constants are rarely generated because they are
6758 optimized away, but they do occasionally happen in nonoptimized
6761 If a constraint in a pattern allows a constant, the reload pass may
6762 replace a register with a constant permitted by the constraint in some
6763 cases. Similarly for memory references. Because of this substitution,
6764 you should not provide separate patterns for increment and decrement
6765 instructions. Instead, they should be generated from the same pattern
6766 that supports register-register add insns by examining the operands and
6767 generating the appropriate machine instruction.
6772 @section Defining Jump Instruction Patterns
6773 @cindex jump instruction patterns
6774 @cindex defining jump instruction patterns
6776 GCC does not assume anything about how the machine realizes jumps.
6777 The machine description should define a single pattern, usually
6778 a @code{define_expand}, which expands to all the required insns.
6780 Usually, this would be a comparison insn to set the condition code
6781 and a separate branch insn testing the condition code and branching
6782 or not according to its value. For many machines, however,
6783 separating compares and branches is limiting, which is why the
6784 more flexible approach with one @code{define_expand} is used in GCC.
6785 The machine description becomes clearer for architectures that
6786 have compare-and-branch instructions but no condition code. It also
6787 works better when different sets of comparison operators are supported
6788 by different kinds of conditional branches (e.g. integer vs. floating-point),
6789 or by conditional branches with respect to conditional stores.
6791 Two separate insns are always used if the machine description represents
6792 a condition code register using the legacy RTL expression @code{(cc0)},
6793 and on most machines that use a separate condition code register
6794 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
6795 fact, the set and use of the condition code must be separate and
6796 adjacent@footnote{@code{note} insns can separate them, though.}, thus
6797 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
6798 so that the comparison and branch insns could be located from each other
6799 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
6801 Even in this case having a single entry point for conditional branches
6802 is advantageous, because it handles equally well the case where a single
6803 comparison instruction records the results of both signed and unsigned
6804 comparison of the given operands (with the branch insns coming in distinct
6805 signed and unsigned flavors) as in the x86 or SPARC, and the case where
6806 there are distinct signed and unsigned compare instructions and only
6807 one set of conditional branch instructions as in the PowerPC.
6811 @node Looping Patterns
6812 @section Defining Looping Instruction Patterns
6813 @cindex looping instruction patterns
6814 @cindex defining looping instruction patterns
6816 Some machines have special jump instructions that can be utilized to
6817 make loops more efficient. A common example is the 68000 @samp{dbra}
6818 instruction which performs a decrement of a register and a branch if the
6819 result was greater than zero. Other machines, in particular digital
6820 signal processors (DSPs), have special block repeat instructions to
6821 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
6822 DSPs have a block repeat instruction that loads special registers to
6823 mark the top and end of a loop and to count the number of loop
6824 iterations. This avoids the need for fetching and executing a
6825 @samp{dbra}-like instruction and avoids pipeline stalls associated with
6828 GCC has three special named patterns to support low overhead looping.
6829 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
6830 and @samp{doloop_end}. The first pattern,
6831 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
6832 generation but may be emitted during the instruction combination phase.
6833 This requires the assistance of the loop optimizer, using information
6834 collected during strength reduction, to reverse a loop to count down to
6835 zero. Some targets also require the loop optimizer to add a
6836 @code{REG_NONNEG} note to indicate that the iteration count is always
6837 positive. This is needed if the target performs a signed loop
6838 termination test. For example, the 68000 uses a pattern similar to the
6839 following for its @code{dbra} instruction:
6843 (define_insn "decrement_and_branch_until_zero"
6846 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6849 (label_ref (match_operand 1 "" ""))
6852 (plus:SI (match_dup 0)
6854 "find_reg_note (insn, REG_NONNEG, 0)"
6859 Note that since the insn is both a jump insn and has an output, it must
6860 deal with its own reloads, hence the `m' constraints. Also note that
6861 since this insn is generated by the instruction combination phase
6862 combining two sequential insns together into an implicit parallel insn,
6863 the iteration counter needs to be biased by the same amount as the
6864 decrement operation, in this case @minus{}1. Note that the following similar
6865 pattern will not be matched by the combiner.
6869 (define_insn "decrement_and_branch_until_zero"
6872 (ge (match_operand:SI 0 "general_operand" "+d*am")
6874 (label_ref (match_operand 1 "" ""))
6877 (plus:SI (match_dup 0)
6879 "find_reg_note (insn, REG_NONNEG, 0)"
6884 The other two special looping patterns, @samp{doloop_begin} and
6885 @samp{doloop_end}, are emitted by the loop optimizer for certain
6886 well-behaved loops with a finite number of loop iterations using
6887 information collected during strength reduction.
6889 The @samp{doloop_end} pattern describes the actual looping instruction
6890 (or the implicit looping operation) and the @samp{doloop_begin} pattern
6891 is an optional companion pattern that can be used for initialization
6892 needed for some low-overhead looping instructions.
6894 Note that some machines require the actual looping instruction to be
6895 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
6896 the true RTL for a looping instruction at the top of the loop can cause
6897 problems with flow analysis. So instead, a dummy @code{doloop} insn is
6898 emitted at the end of the loop. The machine dependent reorg pass checks
6899 for the presence of this @code{doloop} insn and then searches back to
6900 the top of the loop, where it inserts the true looping insn (provided
6901 there are no instructions in the loop which would cause problems). Any
6902 additional labels can be emitted at this point. In addition, if the
6903 desired special iteration counter register was not allocated, this
6904 machine dependent reorg pass could emit a traditional compare and jump
6907 The essential difference between the
6908 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
6909 patterns is that the loop optimizer allocates an additional pseudo
6910 register for the latter as an iteration counter. This pseudo register
6911 cannot be used within the loop (i.e., general induction variables cannot
6912 be derived from it), however, in many cases the loop induction variable
6913 may become redundant and removed by the flow pass.
6918 @node Insn Canonicalizations
6919 @section Canonicalization of Instructions
6920 @cindex canonicalization of instructions
6921 @cindex insn canonicalization
6923 There are often cases where multiple RTL expressions could represent an
6924 operation performed by a single machine instruction. This situation is
6925 most commonly encountered with logical, branch, and multiply-accumulate
6926 instructions. In such cases, the compiler attempts to convert these
6927 multiple RTL expressions into a single canonical form to reduce the
6928 number of insn patterns required.
6930 In addition to algebraic simplifications, following canonicalizations
6935 For commutative and comparison operators, a constant is always made the
6936 second operand. If a machine only supports a constant as the second
6937 operand, only patterns that match a constant in the second operand need
6941 For associative operators, a sequence of operators will always chain
6942 to the left; for instance, only the left operand of an integer @code{plus}
6943 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
6944 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
6945 @code{umax} are associative when applied to integers, and sometimes to
6949 @cindex @code{neg}, canonicalization of
6950 @cindex @code{not}, canonicalization of
6951 @cindex @code{mult}, canonicalization of
6952 @cindex @code{plus}, canonicalization of
6953 @cindex @code{minus}, canonicalization of
6954 For these operators, if only one operand is a @code{neg}, @code{not},
6955 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
6959 In combinations of @code{neg}, @code{mult}, @code{plus}, and
6960 @code{minus}, the @code{neg} operations (if any) will be moved inside
6961 the operations as far as possible. For instance,
6962 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
6963 @code{(plus (mult (neg B) C) A)} is canonicalized as
6964 @code{(minus A (mult B C))}.
6966 @cindex @code{compare}, canonicalization of
6968 For the @code{compare} operator, a constant is always the second operand
6969 if the first argument is a condition code register or @code{(cc0)}.
6972 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
6973 @code{minus} is made the first operand under the same conditions as
6977 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
6978 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
6982 @code{(minus @var{x} (const_int @var{n}))} is converted to
6983 @code{(plus @var{x} (const_int @var{-n}))}.
6986 Within address computations (i.e., inside @code{mem}), a left shift is
6987 converted into the appropriate multiplication by a power of two.
6989 @cindex @code{ior}, canonicalization of
6990 @cindex @code{and}, canonicalization of
6991 @cindex De Morgan's law
6993 De Morgan's Law is used to move bitwise negation inside a bitwise
6994 logical-and or logical-or operation. If this results in only one
6995 operand being a @code{not} expression, it will be the first one.
6997 A machine that has an instruction that performs a bitwise logical-and of one
6998 operand with the bitwise negation of the other should specify the pattern
6999 for that instruction as
7003 [(set (match_operand:@var{m} 0 @dots{})
7004 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7005 (match_operand:@var{m} 2 @dots{})))]
7011 Similarly, a pattern for a ``NAND'' instruction should be written
7015 [(set (match_operand:@var{m} 0 @dots{})
7016 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7017 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
7022 In both cases, it is not necessary to include patterns for the many
7023 logically equivalent RTL expressions.
7025 @cindex @code{xor}, canonicalization of
7027 The only possible RTL expressions involving both bitwise exclusive-or
7028 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
7029 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
7032 The sum of three items, one of which is a constant, will only appear in
7036 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
7039 @cindex @code{zero_extract}, canonicalization of
7040 @cindex @code{sign_extract}, canonicalization of
7042 Equality comparisons of a group of bits (usually a single bit) with zero
7043 will be written using @code{zero_extract} rather than the equivalent
7044 @code{and} or @code{sign_extract} operations.
7046 @cindex @code{mult}, canonicalization of
7048 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
7049 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
7050 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
7051 for @code{zero_extend}.
7054 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
7055 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
7056 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
7057 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
7058 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
7059 operand of @code{mult} is also a shift, then that is extended also.
7060 This transformation is only applied when it can be proven that the
7061 original operation had sufficient precision to prevent overflow.
7065 Further canonicalization rules are defined in the function
7066 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
7070 @node Expander Definitions
7071 @section Defining RTL Sequences for Code Generation
7072 @cindex expander definitions
7073 @cindex code generation RTL sequences
7074 @cindex defining RTL sequences for code generation
7076 On some target machines, some standard pattern names for RTL generation
7077 cannot be handled with single insn, but a sequence of RTL insns can
7078 represent them. For these target machines, you can write a
7079 @code{define_expand} to specify how to generate the sequence of RTL@.
7081 @findex define_expand
7082 A @code{define_expand} is an RTL expression that looks almost like a
7083 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
7084 only for RTL generation and it can produce more than one RTL insn.
7086 A @code{define_expand} RTX has four operands:
7090 The name. Each @code{define_expand} must have a name, since the only
7091 use for it is to refer to it by name.
7094 The RTL template. This is a vector of RTL expressions representing
7095 a sequence of separate instructions. Unlike @code{define_insn}, there
7096 is no implicit surrounding @code{PARALLEL}.
7099 The condition, a string containing a C expression. This expression is
7100 used to express how the availability of this pattern depends on
7101 subclasses of target machine, selected by command-line options when GCC
7102 is run. This is just like the condition of a @code{define_insn} that
7103 has a standard name. Therefore, the condition (if present) may not
7104 depend on the data in the insn being matched, but only the
7105 target-machine-type flags. The compiler needs to test these conditions
7106 during initialization in order to learn exactly which named instructions
7107 are available in a particular run.
7110 The preparation statements, a string containing zero or more C
7111 statements which are to be executed before RTL code is generated from
7114 Usually these statements prepare temporary registers for use as
7115 internal operands in the RTL template, but they can also generate RTL
7116 insns directly by calling routines such as @code{emit_insn}, etc.
7117 Any such insns precede the ones that come from the RTL template.
7120 Optionally, a vector containing the values of attributes. @xref{Insn
7124 Every RTL insn emitted by a @code{define_expand} must match some
7125 @code{define_insn} in the machine description. Otherwise, the compiler
7126 will crash when trying to generate code for the insn or trying to optimize
7129 The RTL template, in addition to controlling generation of RTL insns,
7130 also describes the operands that need to be specified when this pattern
7131 is used. In particular, it gives a predicate for each operand.
7133 A true operand, which needs to be specified in order to generate RTL from
7134 the pattern, should be described with a @code{match_operand} in its first
7135 occurrence in the RTL template. This enters information on the operand's
7136 predicate into the tables that record such things. GCC uses the
7137 information to preload the operand into a register if that is required for
7138 valid RTL code. If the operand is referred to more than once, subsequent
7139 references should use @code{match_dup}.
7141 The RTL template may also refer to internal ``operands'' which are
7142 temporary registers or labels used only within the sequence made by the
7143 @code{define_expand}. Internal operands are substituted into the RTL
7144 template with @code{match_dup}, never with @code{match_operand}. The
7145 values of the internal operands are not passed in as arguments by the
7146 compiler when it requests use of this pattern. Instead, they are computed
7147 within the pattern, in the preparation statements. These statements
7148 compute the values and store them into the appropriate elements of
7149 @code{operands} so that @code{match_dup} can find them.
7151 There are two special macros defined for use in the preparation statements:
7152 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
7159 Use the @code{DONE} macro to end RTL generation for the pattern. The
7160 only RTL insns resulting from the pattern on this occasion will be
7161 those already emitted by explicit calls to @code{emit_insn} within the
7162 preparation statements; the RTL template will not be generated.
7166 Make the pattern fail on this occasion. When a pattern fails, it means
7167 that the pattern was not truly available. The calling routines in the
7168 compiler will try other strategies for code generation using other patterns.
7170 Failure is currently supported only for binary (addition, multiplication,
7171 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
7175 If the preparation falls through (invokes neither @code{DONE} nor
7176 @code{FAIL}), then the @code{define_expand} acts like a
7177 @code{define_insn} in that the RTL template is used to generate the
7180 The RTL template is not used for matching, only for generating the
7181 initial insn list. If the preparation statement always invokes
7182 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
7183 list of operands, such as this example:
7187 (define_expand "addsi3"
7188 [(match_operand:SI 0 "register_operand" "")
7189 (match_operand:SI 1 "register_operand" "")
7190 (match_operand:SI 2 "register_operand" "")]
7196 handle_add (operands[0], operands[1], operands[2]);
7202 Here is an example, the definition of left-shift for the SPUR chip:
7206 (define_expand "ashlsi3"
7207 [(set (match_operand:SI 0 "register_operand" "")
7211 (match_operand:SI 1 "register_operand" "")
7212 (match_operand:SI 2 "nonmemory_operand" "")))]
7221 if (GET_CODE (operands[2]) != CONST_INT
7222 || (unsigned) INTVAL (operands[2]) > 3)
7229 This example uses @code{define_expand} so that it can generate an RTL insn
7230 for shifting when the shift-count is in the supported range of 0 to 3 but
7231 fail in other cases where machine insns aren't available. When it fails,
7232 the compiler tries another strategy using different patterns (such as, a
7235 If the compiler were able to handle nontrivial condition-strings in
7236 patterns with names, then it would be possible to use a
7237 @code{define_insn} in that case. Here is another case (zero-extension
7238 on the 68000) which makes more use of the power of @code{define_expand}:
7241 (define_expand "zero_extendhisi2"
7242 [(set (match_operand:SI 0 "general_operand" "")
7244 (set (strict_low_part
7248 (match_operand:HI 1 "general_operand" ""))]
7250 "operands[1] = make_safe_from (operands[1], operands[0]);")
7254 @findex make_safe_from
7255 Here two RTL insns are generated, one to clear the entire output operand
7256 and the other to copy the input operand into its low half. This sequence
7257 is incorrect if the input operand refers to [the old value of] the output
7258 operand, so the preparation statement makes sure this isn't so. The
7259 function @code{make_safe_from} copies the @code{operands[1]} into a
7260 temporary register if it refers to @code{operands[0]}. It does this
7261 by emitting another RTL insn.
7263 Finally, a third example shows the use of an internal operand.
7264 Zero-extension on the SPUR chip is done by @code{and}-ing the result
7265 against a halfword mask. But this mask cannot be represented by a
7266 @code{const_int} because the constant value is too large to be legitimate
7267 on this machine. So it must be copied into a register with
7268 @code{force_reg} and then the register used in the @code{and}.
7271 (define_expand "zero_extendhisi2"
7272 [(set (match_operand:SI 0 "register_operand" "")
7274 (match_operand:HI 1 "register_operand" "")
7279 = force_reg (SImode, GEN_INT (65535)); ")
7282 @emph{Note:} If the @code{define_expand} is used to serve a
7283 standard binary or unary arithmetic operation or a bit-field operation,
7284 then the last insn it generates must not be a @code{code_label},
7285 @code{barrier} or @code{note}. It must be an @code{insn},
7286 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
7287 at the end, emit an insn to copy the result of the operation into
7288 itself. Such an insn will generate no code, but it can avoid problems
7293 @node Insn Splitting
7294 @section Defining How to Split Instructions
7295 @cindex insn splitting
7296 @cindex instruction splitting
7297 @cindex splitting instructions
7299 There are two cases where you should specify how to split a pattern
7300 into multiple insns. On machines that have instructions requiring
7301 delay slots (@pxref{Delay Slots}) or that have instructions whose
7302 output is not available for multiple cycles (@pxref{Processor pipeline
7303 description}), the compiler phases that optimize these cases need to
7304 be able to move insns into one-instruction delay slots. However, some
7305 insns may generate more than one machine instruction. These insns
7306 cannot be placed into a delay slot.
7308 Often you can rewrite the single insn as a list of individual insns,
7309 each corresponding to one machine instruction. The disadvantage of
7310 doing so is that it will cause the compilation to be slower and require
7311 more space. If the resulting insns are too complex, it may also
7312 suppress some optimizations. The compiler splits the insn if there is a
7313 reason to believe that it might improve instruction or delay slot
7316 The insn combiner phase also splits putative insns. If three insns are
7317 merged into one insn with a complex expression that cannot be matched by
7318 some @code{define_insn} pattern, the combiner phase attempts to split
7319 the complex pattern into two insns that are recognized. Usually it can
7320 break the complex pattern into two patterns by splitting out some
7321 subexpression. However, in some other cases, such as performing an
7322 addition of a large constant in two insns on a RISC machine, the way to
7323 split the addition into two insns is machine-dependent.
7325 @findex define_split
7326 The @code{define_split} definition tells the compiler how to split a
7327 complex insn into several simpler insns. It looks like this:
7331 [@var{insn-pattern}]
7333 [@var{new-insn-pattern-1}
7334 @var{new-insn-pattern-2}
7336 "@var{preparation-statements}")
7339 @var{insn-pattern} is a pattern that needs to be split and
7340 @var{condition} is the final condition to be tested, as in a
7341 @code{define_insn}. When an insn matching @var{insn-pattern} and
7342 satisfying @var{condition} is found, it is replaced in the insn list
7343 with the insns given by @var{new-insn-pattern-1},
7344 @var{new-insn-pattern-2}, etc.
7346 The @var{preparation-statements} are similar to those statements that
7347 are specified for @code{define_expand} (@pxref{Expander Definitions})
7348 and are executed before the new RTL is generated to prepare for the
7349 generated code or emit some insns whose pattern is not fixed. Unlike
7350 those in @code{define_expand}, however, these statements must not
7351 generate any new pseudo-registers. Once reload has completed, they also
7352 must not allocate any space in the stack frame.
7354 Patterns are matched against @var{insn-pattern} in two different
7355 circumstances. If an insn needs to be split for delay slot scheduling
7356 or insn scheduling, the insn is already known to be valid, which means
7357 that it must have been matched by some @code{define_insn} and, if
7358 @code{reload_completed} is nonzero, is known to satisfy the constraints
7359 of that @code{define_insn}. In that case, the new insn patterns must
7360 also be insns that are matched by some @code{define_insn} and, if
7361 @code{reload_completed} is nonzero, must also satisfy the constraints
7362 of those definitions.
7364 As an example of this usage of @code{define_split}, consider the following
7365 example from @file{a29k.md}, which splits a @code{sign_extend} from
7366 @code{HImode} to @code{SImode} into a pair of shift insns:
7370 [(set (match_operand:SI 0 "gen_reg_operand" "")
7371 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
7374 (ashift:SI (match_dup 1)
7377 (ashiftrt:SI (match_dup 0)
7380 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
7383 When the combiner phase tries to split an insn pattern, it is always the
7384 case that the pattern is @emph{not} matched by any @code{define_insn}.
7385 The combiner pass first tries to split a single @code{set} expression
7386 and then the same @code{set} expression inside a @code{parallel}, but
7387 followed by a @code{clobber} of a pseudo-reg to use as a scratch
7388 register. In these cases, the combiner expects exactly two new insn
7389 patterns to be generated. It will verify that these patterns match some
7390 @code{define_insn} definitions, so you need not do this test in the
7391 @code{define_split} (of course, there is no point in writing a
7392 @code{define_split} that will never produce insns that match).
7394 Here is an example of this use of @code{define_split}, taken from
7399 [(set (match_operand:SI 0 "gen_reg_operand" "")
7400 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
7401 (match_operand:SI 2 "non_add_cint_operand" "")))]
7403 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
7404 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
7407 int low = INTVAL (operands[2]) & 0xffff;
7408 int high = (unsigned) INTVAL (operands[2]) >> 16;
7411 high++, low |= 0xffff0000;
7413 operands[3] = GEN_INT (high << 16);
7414 operands[4] = GEN_INT (low);
7418 Here the predicate @code{non_add_cint_operand} matches any
7419 @code{const_int} that is @emph{not} a valid operand of a single add
7420 insn. The add with the smaller displacement is written so that it
7421 can be substituted into the address of a subsequent operation.
7423 An example that uses a scratch register, from the same file, generates
7424 an equality comparison of a register and a large constant:
7428 [(set (match_operand:CC 0 "cc_reg_operand" "")
7429 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
7430 (match_operand:SI 2 "non_short_cint_operand" "")))
7431 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
7432 "find_single_use (operands[0], insn, 0)
7433 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
7434 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
7435 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
7436 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
7439 /* @r{Get the constant we are comparing against, C, and see what it
7440 looks like sign-extended to 16 bits. Then see what constant
7441 could be XOR'ed with C to get the sign-extended value.} */
7443 int c = INTVAL (operands[2]);
7444 int sextc = (c << 16) >> 16;
7445 int xorv = c ^ sextc;
7447 operands[4] = GEN_INT (xorv);
7448 operands[5] = GEN_INT (sextc);
7452 To avoid confusion, don't write a single @code{define_split} that
7453 accepts some insns that match some @code{define_insn} as well as some
7454 insns that don't. Instead, write two separate @code{define_split}
7455 definitions, one for the insns that are valid and one for the insns that
7458 The splitter is allowed to split jump instructions into sequence of
7459 jumps or create new jumps in while splitting non-jump instructions. As
7460 the central flowgraph and branch prediction information needs to be updated,
7461 several restriction apply.
7463 Splitting of jump instruction into sequence that over by another jump
7464 instruction is always valid, as compiler expect identical behavior of new
7465 jump. When new sequence contains multiple jump instructions or new labels,
7466 more assistance is needed. Splitter is required to create only unconditional
7467 jumps, or simple conditional jump instructions. Additionally it must attach a
7468 @code{REG_BR_PROB} note to each conditional jump. A global variable
7469 @code{split_branch_probability} holds the probability of the original branch in case
7470 it was a simple conditional jump, @minus{}1 otherwise. To simplify
7471 recomputing of edge frequencies, the new sequence is required to have only
7472 forward jumps to the newly created labels.
7474 @findex define_insn_and_split
7475 For the common case where the pattern of a define_split exactly matches the
7476 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
7480 (define_insn_and_split
7481 [@var{insn-pattern}]
7483 "@var{output-template}"
7484 "@var{split-condition}"
7485 [@var{new-insn-pattern-1}
7486 @var{new-insn-pattern-2}
7488 "@var{preparation-statements}"
7489 [@var{insn-attributes}])
7493 @var{insn-pattern}, @var{condition}, @var{output-template}, and
7494 @var{insn-attributes} are used as in @code{define_insn}. The
7495 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
7496 in a @code{define_split}. The @var{split-condition} is also used as in
7497 @code{define_split}, with the additional behavior that if the condition starts
7498 with @samp{&&}, the condition used for the split will be the constructed as a
7499 logical ``and'' of the split condition with the insn condition. For example,
7503 (define_insn_and_split "zero_extendhisi2_and"
7504 [(set (match_operand:SI 0 "register_operand" "=r")
7505 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
7506 (clobber (reg:CC 17))]
7507 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
7509 "&& reload_completed"
7510 [(parallel [(set (match_dup 0)
7511 (and:SI (match_dup 0) (const_int 65535)))
7512 (clobber (reg:CC 17))])]
7514 [(set_attr "type" "alu1")])
7518 In this case, the actual split condition will be
7519 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
7521 The @code{define_insn_and_split} construction provides exactly the same
7522 functionality as two separate @code{define_insn} and @code{define_split}
7523 patterns. It exists for compactness, and as a maintenance tool to prevent
7524 having to ensure the two patterns' templates match.
7528 @node Including Patterns
7529 @section Including Patterns in Machine Descriptions.
7530 @cindex insn includes
7533 The @code{include} pattern tells the compiler tools where to
7534 look for patterns that are in files other than in the file
7535 @file{.md}. This is used only at build time and there is no preprocessing allowed.
7549 (include "filestuff")
7553 Where @var{pathname} is a string that specifies the location of the file,
7554 specifies the include file to be in @file{gcc/config/target/filestuff}. The
7555 directory @file{gcc/config/target} is regarded as the default directory.
7558 Machine descriptions may be split up into smaller more manageable subsections
7559 and placed into subdirectories.
7565 (include "BOGUS/filestuff")
7569 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
7571 Specifying an absolute path for the include file such as;
7574 (include "/u2/BOGUS/filestuff")
7577 is permitted but is not encouraged.
7579 @subsection RTL Generation Tool Options for Directory Search
7580 @cindex directory options .md
7581 @cindex options, directory search
7582 @cindex search options
7584 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
7589 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
7594 Add the directory @var{dir} to the head of the list of directories to be
7595 searched for header files. This can be used to override a system machine definition
7596 file, substituting your own version, since these directories are
7597 searched before the default machine description file directories. If you use more than
7598 one @option{-I} option, the directories are scanned in left-to-right
7599 order; the standard default directory come after.
7604 @node Peephole Definitions
7605 @section Machine-Specific Peephole Optimizers
7606 @cindex peephole optimizer definitions
7607 @cindex defining peephole optimizers
7609 In addition to instruction patterns the @file{md} file may contain
7610 definitions of machine-specific peephole optimizations.
7612 The combiner does not notice certain peephole optimizations when the data
7613 flow in the program does not suggest that it should try them. For example,
7614 sometimes two consecutive insns related in purpose can be combined even
7615 though the second one does not appear to use a register computed in the
7616 first one. A machine-specific peephole optimizer can detect such
7619 There are two forms of peephole definitions that may be used. The
7620 original @code{define_peephole} is run at assembly output time to
7621 match insns and substitute assembly text. Use of @code{define_peephole}
7624 A newer @code{define_peephole2} matches insns and substitutes new
7625 insns. The @code{peephole2} pass is run after register allocation
7626 but before scheduling, which may result in much better code for
7627 targets that do scheduling.
7630 * define_peephole:: RTL to Text Peephole Optimizers
7631 * define_peephole2:: RTL to RTL Peephole Optimizers
7636 @node define_peephole
7637 @subsection RTL to Text Peephole Optimizers
7638 @findex define_peephole
7641 A definition looks like this:
7645 [@var{insn-pattern-1}
7646 @var{insn-pattern-2}
7650 "@var{optional-insn-attributes}")
7654 The last string operand may be omitted if you are not using any
7655 machine-specific information in this machine description. If present,
7656 it must obey the same rules as in a @code{define_insn}.
7658 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
7659 consecutive insns. The optimization applies to a sequence of insns when
7660 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
7661 the next, and so on.
7663 Each of the insns matched by a peephole must also match a
7664 @code{define_insn}. Peepholes are checked only at the last stage just
7665 before code generation, and only optionally. Therefore, any insn which
7666 would match a peephole but no @code{define_insn} will cause a crash in code
7667 generation in an unoptimized compilation, or at various optimization
7670 The operands of the insns are matched with @code{match_operands},
7671 @code{match_operator}, and @code{match_dup}, as usual. What is not
7672 usual is that the operand numbers apply to all the insn patterns in the
7673 definition. So, you can check for identical operands in two insns by
7674 using @code{match_operand} in one insn and @code{match_dup} in the
7677 The operand constraints used in @code{match_operand} patterns do not have
7678 any direct effect on the applicability of the peephole, but they will
7679 be validated afterward, so make sure your constraints are general enough
7680 to apply whenever the peephole matches. If the peephole matches
7681 but the constraints are not satisfied, the compiler will crash.
7683 It is safe to omit constraints in all the operands of the peephole; or
7684 you can write constraints which serve as a double-check on the criteria
7687 Once a sequence of insns matches the patterns, the @var{condition} is
7688 checked. This is a C expression which makes the final decision whether to
7689 perform the optimization (we do so if the expression is nonzero). If
7690 @var{condition} is omitted (in other words, the string is empty) then the
7691 optimization is applied to every sequence of insns that matches the
7694 The defined peephole optimizations are applied after register allocation
7695 is complete. Therefore, the peephole definition can check which
7696 operands have ended up in which kinds of registers, just by looking at
7699 @findex prev_active_insn
7700 The way to refer to the operands in @var{condition} is to write
7701 @code{operands[@var{i}]} for operand number @var{i} (as matched by
7702 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
7703 to refer to the last of the insns being matched; use
7704 @code{prev_active_insn} to find the preceding insns.
7706 @findex dead_or_set_p
7707 When optimizing computations with intermediate results, you can use
7708 @var{condition} to match only when the intermediate results are not used
7709 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
7710 @var{op})}, where @var{insn} is the insn in which you expect the value
7711 to be used for the last time (from the value of @code{insn}, together
7712 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
7713 value (from @code{operands[@var{i}]}).
7715 Applying the optimization means replacing the sequence of insns with one
7716 new insn. The @var{template} controls ultimate output of assembler code
7717 for this combined insn. It works exactly like the template of a
7718 @code{define_insn}. Operand numbers in this template are the same ones
7719 used in matching the original sequence of insns.
7721 The result of a defined peephole optimizer does not need to match any of
7722 the insn patterns in the machine description; it does not even have an
7723 opportunity to match them. The peephole optimizer definition itself serves
7724 as the insn pattern to control how the insn is output.
7726 Defined peephole optimizers are run as assembler code is being output,
7727 so the insns they produce are never combined or rearranged in any way.
7729 Here is an example, taken from the 68000 machine description:
7733 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7734 (set (match_operand:DF 0 "register_operand" "=f")
7735 (match_operand:DF 1 "register_operand" "ad"))]
7736 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7739 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7741 output_asm_insn ("move.l %1,(sp)", xoperands);
7742 output_asm_insn ("move.l %1,-(sp)", operands);
7743 return "fmove.d (sp)+,%0";
7745 output_asm_insn ("movel %1,sp@@", xoperands);
7746 output_asm_insn ("movel %1,sp@@-", operands);
7747 return "fmoved sp@@+,%0";
7753 The effect of this optimization is to change
7779 If a peephole matches a sequence including one or more jump insns, you must
7780 take account of the flags such as @code{CC_REVERSED} which specify that the
7781 condition codes are represented in an unusual manner. The compiler
7782 automatically alters any ordinary conditional jumps which occur in such
7783 situations, but the compiler cannot alter jumps which have been replaced by
7784 peephole optimizations. So it is up to you to alter the assembler code
7785 that the peephole produces. Supply C code to write the assembler output,
7786 and in this C code check the condition code status flags and change the
7787 assembler code as appropriate.
7790 @var{insn-pattern-1} and so on look @emph{almost} like the second
7791 operand of @code{define_insn}. There is one important difference: the
7792 second operand of @code{define_insn} consists of one or more RTX's
7793 enclosed in square brackets. Usually, there is only one: then the same
7794 action can be written as an element of a @code{define_peephole}. But
7795 when there are multiple actions in a @code{define_insn}, they are
7796 implicitly enclosed in a @code{parallel}. Then you must explicitly
7797 write the @code{parallel}, and the square brackets within it, in the
7798 @code{define_peephole}. Thus, if an insn pattern looks like this,
7801 (define_insn "divmodsi4"
7802 [(set (match_operand:SI 0 "general_operand" "=d")
7803 (div:SI (match_operand:SI 1 "general_operand" "0")
7804 (match_operand:SI 2 "general_operand" "dmsK")))
7805 (set (match_operand:SI 3 "general_operand" "=d")
7806 (mod:SI (match_dup 1) (match_dup 2)))]
7808 "divsl%.l %2,%3:%0")
7812 then the way to mention this insn in a peephole is as follows:
7818 [(set (match_operand:SI 0 "general_operand" "=d")
7819 (div:SI (match_operand:SI 1 "general_operand" "0")
7820 (match_operand:SI 2 "general_operand" "dmsK")))
7821 (set (match_operand:SI 3 "general_operand" "=d")
7822 (mod:SI (match_dup 1) (match_dup 2)))])
7829 @node define_peephole2
7830 @subsection RTL to RTL Peephole Optimizers
7831 @findex define_peephole2
7833 The @code{define_peephole2} definition tells the compiler how to
7834 substitute one sequence of instructions for another sequence,
7835 what additional scratch registers may be needed and what their
7840 [@var{insn-pattern-1}
7841 @var{insn-pattern-2}
7844 [@var{new-insn-pattern-1}
7845 @var{new-insn-pattern-2}
7847 "@var{preparation-statements}")
7850 The definition is almost identical to @code{define_split}
7851 (@pxref{Insn Splitting}) except that the pattern to match is not a
7852 single instruction, but a sequence of instructions.
7854 It is possible to request additional scratch registers for use in the
7855 output template. If appropriate registers are not free, the pattern
7856 will simply not match.
7858 @findex match_scratch
7860 Scratch registers are requested with a @code{match_scratch} pattern at
7861 the top level of the input pattern. The allocated register (initially) will
7862 be dead at the point requested within the original sequence. If the scratch
7863 is used at more than a single point, a @code{match_dup} pattern at the
7864 top level of the input pattern marks the last position in the input sequence
7865 at which the register must be available.
7867 Here is an example from the IA-32 machine description:
7871 [(match_scratch:SI 2 "r")
7872 (parallel [(set (match_operand:SI 0 "register_operand" "")
7873 (match_operator:SI 3 "arith_or_logical_operator"
7875 (match_operand:SI 1 "memory_operand" "")]))
7876 (clobber (reg:CC 17))])]
7877 "! optimize_size && ! TARGET_READ_MODIFY"
7878 [(set (match_dup 2) (match_dup 1))
7879 (parallel [(set (match_dup 0)
7880 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
7881 (clobber (reg:CC 17))])]
7886 This pattern tries to split a load from its use in the hopes that we'll be
7887 able to schedule around the memory load latency. It allocates a single
7888 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
7889 to be live only at the point just before the arithmetic.
7891 A real example requiring extended scratch lifetimes is harder to come by,
7892 so here's a silly made-up example:
7896 [(match_scratch:SI 4 "r")
7897 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7898 (set (match_operand:SI 2 "" "") (match_dup 1))
7900 (set (match_operand:SI 3 "" "") (match_dup 1))]
7901 "/* @r{determine 1 does not overlap 0 and 2} */"
7902 [(set (match_dup 4) (match_dup 1))
7903 (set (match_dup 0) (match_dup 4))
7904 (set (match_dup 2) (match_dup 4))
7905 (set (match_dup 3) (match_dup 4))]
7910 If we had not added the @code{(match_dup 4)} in the middle of the input
7911 sequence, it might have been the case that the register we chose at the
7912 beginning of the sequence is killed by the first or second @code{set}.
7916 @node Insn Attributes
7917 @section Instruction Attributes
7918 @cindex insn attributes
7919 @cindex instruction attributes
7921 In addition to describing the instruction supported by the target machine,
7922 the @file{md} file also defines a group of @dfn{attributes} and a set of
7923 values for each. Every generated insn is assigned a value for each attribute.
7924 One possible attribute would be the effect that the insn has on the machine's
7925 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
7926 to track the condition codes.
7929 * Defining Attributes:: Specifying attributes and their values.
7930 * Expressions:: Valid expressions for attribute values.
7931 * Tagging Insns:: Assigning attribute values to insns.
7932 * Attr Example:: An example of assigning attributes.
7933 * Insn Lengths:: Computing the length of insns.
7934 * Constant Attributes:: Defining attributes that are constant.
7935 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
7936 * Delay Slots:: Defining delay slots required for a machine.
7937 * Processor pipeline description:: Specifying information for insn scheduling.
7942 @node Defining Attributes
7943 @subsection Defining Attributes and their Values
7944 @cindex defining attributes and their values
7945 @cindex attributes, defining
7948 The @code{define_attr} expression is used to define each attribute required
7949 by the target machine. It looks like:
7952 (define_attr @var{name} @var{list-of-values} @var{default})
7955 @var{name} is a string specifying the name of the attribute being
7956 defined. Some attributes are used in a special way by the rest of the
7957 compiler. The @code{enabled} attribute can be used to conditionally
7958 enable or disable insn alternatives (@pxref{Disable Insn
7959 Alternatives}). The @code{predicable} attribute, together with a
7960 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
7961 be used to automatically generate conditional variants of instruction
7962 patterns. The @code{mnemonic} attribute can be used to check for the
7963 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
7964 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
7965 so they should not be used elsewhere as alternative names.
7967 @var{list-of-values} is either a string that specifies a comma-separated
7968 list of values that can be assigned to the attribute, or a null string to
7969 indicate that the attribute takes numeric values.
7971 @var{default} is an attribute expression that gives the value of this
7972 attribute for insns that match patterns whose definition does not include
7973 an explicit value for this attribute. @xref{Attr Example}, for more
7974 information on the handling of defaults. @xref{Constant Attributes},
7975 for information on attributes that do not depend on any particular insn.
7978 For each defined attribute, a number of definitions are written to the
7979 @file{insn-attr.h} file. For cases where an explicit set of values is
7980 specified for an attribute, the following are defined:
7984 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
7987 An enumerated class is defined for @samp{attr_@var{name}} with
7988 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
7989 the attribute name and value are first converted to uppercase.
7992 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
7993 returns the attribute value for that insn.
7996 For example, if the following is present in the @file{md} file:
7999 (define_attr "type" "branch,fp,load,store,arith" @dots{})
8003 the following lines will be written to the file @file{insn-attr.h}.
8006 #define HAVE_ATTR_type 1
8007 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
8008 TYPE_STORE, TYPE_ARITH@};
8009 extern enum attr_type get_attr_type ();
8012 If the attribute takes numeric values, no @code{enum} type will be
8013 defined and the function to obtain the attribute's value will return
8016 There are attributes which are tied to a specific meaning. These
8017 attributes are not free to use for other purposes:
8021 The @code{length} attribute is used to calculate the length of emitted
8022 code chunks. This is especially important when verifying branch
8023 distances. @xref{Insn Lengths}.
8026 The @code{enabled} attribute can be defined to prevent certain
8027 alternatives of an insn definition from being used during code
8028 generation. @xref{Disable Insn Alternatives}.
8031 The @code{mnemonic} attribute can be defined to implement instruction
8032 specific checks in e.g. the pipeline description.
8033 @xref{Mnemonic Attribute}.
8036 For each of these special attributes, the corresponding
8037 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
8038 attribute is not defined; in that case, it is defined as @samp{0}.
8040 @findex define_enum_attr
8041 @anchor{define_enum_attr}
8042 Another way of defining an attribute is to use:
8045 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
8048 This works in just the same way as @code{define_attr}, except that
8049 the list of values is taken from a separate enumeration called
8050 @var{enum} (@pxref{define_enum}). This form allows you to use
8051 the same list of values for several attributes without having to
8052 repeat the list each time. For example:
8055 (define_enum "processor" [
8060 (define_enum_attr "arch" "processor"
8061 (const (symbol_ref "target_arch")))
8062 (define_enum_attr "tune" "processor"
8063 (const (symbol_ref "target_tune")))
8066 defines the same attributes as:
8069 (define_attr "arch" "model_a,model_b,@dots{}"
8070 (const (symbol_ref "target_arch")))
8071 (define_attr "tune" "model_a,model_b,@dots{}"
8072 (const (symbol_ref "target_tune")))
8075 but without duplicating the processor list. The second example defines two
8076 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
8077 defines a single C enum (@code{processor}).
8081 @subsection Attribute Expressions
8082 @cindex attribute expressions
8084 RTL expressions used to define attributes use the codes described above
8085 plus a few specific to attribute definitions, to be discussed below.
8086 Attribute value expressions must have one of the following forms:
8089 @cindex @code{const_int} and attributes
8090 @item (const_int @var{i})
8091 The integer @var{i} specifies the value of a numeric attribute. @var{i}
8092 must be non-negative.
8094 The value of a numeric attribute can be specified either with a
8095 @code{const_int}, or as an integer represented as a string in
8096 @code{const_string}, @code{eq_attr} (see below), @code{attr},
8097 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
8098 overrides on specific instructions (@pxref{Tagging Insns}).
8100 @cindex @code{const_string} and attributes
8101 @item (const_string @var{value})
8102 The string @var{value} specifies a constant attribute value.
8103 If @var{value} is specified as @samp{"*"}, it means that the default value of
8104 the attribute is to be used for the insn containing this expression.
8105 @samp{"*"} obviously cannot be used in the @var{default} expression
8106 of a @code{define_attr}.
8108 If the attribute whose value is being specified is numeric, @var{value}
8109 must be a string containing a non-negative integer (normally
8110 @code{const_int} would be used in this case). Otherwise, it must
8111 contain one of the valid values for the attribute.
8113 @cindex @code{if_then_else} and attributes
8114 @item (if_then_else @var{test} @var{true-value} @var{false-value})
8115 @var{test} specifies an attribute test, whose format is defined below.
8116 The value of this expression is @var{true-value} if @var{test} is true,
8117 otherwise it is @var{false-value}.
8119 @cindex @code{cond} and attributes
8120 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
8121 The first operand of this expression is a vector containing an even
8122 number of expressions and consisting of pairs of @var{test} and @var{value}
8123 expressions. The value of the @code{cond} expression is that of the
8124 @var{value} corresponding to the first true @var{test} expression. If
8125 none of the @var{test} expressions are true, the value of the @code{cond}
8126 expression is that of the @var{default} expression.
8129 @var{test} expressions can have one of the following forms:
8132 @cindex @code{const_int} and attribute tests
8133 @item (const_int @var{i})
8134 This test is true if @var{i} is nonzero and false otherwise.
8136 @cindex @code{not} and attributes
8137 @cindex @code{ior} and attributes
8138 @cindex @code{and} and attributes
8139 @item (not @var{test})
8140 @itemx (ior @var{test1} @var{test2})
8141 @itemx (and @var{test1} @var{test2})
8142 These tests are true if the indicated logical function is true.
8144 @cindex @code{match_operand} and attributes
8145 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
8146 This test is true if operand @var{n} of the insn whose attribute value
8147 is being determined has mode @var{m} (this part of the test is ignored
8148 if @var{m} is @code{VOIDmode}) and the function specified by the string
8149 @var{pred} returns a nonzero value when passed operand @var{n} and mode
8150 @var{m} (this part of the test is ignored if @var{pred} is the null
8153 The @var{constraints} operand is ignored and should be the null string.
8155 @cindex @code{match_test} and attributes
8156 @item (match_test @var{c-expr})
8157 The test is true if C expression @var{c-expr} is true. In non-constant
8158 attributes, @var{c-expr} has access to the following variables:
8162 The rtl instruction under test.
8163 @item which_alternative
8164 The @code{define_insn} alternative that @var{insn} matches.
8165 @xref{Output Statement}.
8167 An array of @var{insn}'s rtl operands.
8170 @var{c-expr} behaves like the condition in a C @code{if} statement,
8171 so there is no need to explicitly convert the expression into a boolean
8172 0 or 1 value. For example, the following two tests are equivalent:
8175 (match_test "x & 2")
8176 (match_test "(x & 2) != 0")
8179 @cindex @code{le} and attributes
8180 @cindex @code{leu} and attributes
8181 @cindex @code{lt} and attributes
8182 @cindex @code{gt} and attributes
8183 @cindex @code{gtu} and attributes
8184 @cindex @code{ge} and attributes
8185 @cindex @code{geu} and attributes
8186 @cindex @code{ne} and attributes
8187 @cindex @code{eq} and attributes
8188 @cindex @code{plus} and attributes
8189 @cindex @code{minus} and attributes
8190 @cindex @code{mult} and attributes
8191 @cindex @code{div} and attributes
8192 @cindex @code{mod} and attributes
8193 @cindex @code{abs} and attributes
8194 @cindex @code{neg} and attributes
8195 @cindex @code{ashift} and attributes
8196 @cindex @code{lshiftrt} and attributes
8197 @cindex @code{ashiftrt} and attributes
8198 @item (le @var{arith1} @var{arith2})
8199 @itemx (leu @var{arith1} @var{arith2})
8200 @itemx (lt @var{arith1} @var{arith2})
8201 @itemx (ltu @var{arith1} @var{arith2})
8202 @itemx (gt @var{arith1} @var{arith2})
8203 @itemx (gtu @var{arith1} @var{arith2})
8204 @itemx (ge @var{arith1} @var{arith2})
8205 @itemx (geu @var{arith1} @var{arith2})
8206 @itemx (ne @var{arith1} @var{arith2})
8207 @itemx (eq @var{arith1} @var{arith2})
8208 These tests are true if the indicated comparison of the two arithmetic
8209 expressions is true. Arithmetic expressions are formed with
8210 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
8211 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
8212 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
8215 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
8216 Lengths},for additional forms). @code{symbol_ref} is a string
8217 denoting a C expression that yields an @code{int} when evaluated by the
8218 @samp{get_attr_@dots{}} routine. It should normally be a global
8222 @item (eq_attr @var{name} @var{value})
8223 @var{name} is a string specifying the name of an attribute.
8225 @var{value} is a string that is either a valid value for attribute
8226 @var{name}, a comma-separated list of values, or @samp{!} followed by a
8227 value or list. If @var{value} does not begin with a @samp{!}, this
8228 test is true if the value of the @var{name} attribute of the current
8229 insn is in the list specified by @var{value}. If @var{value} begins
8230 with a @samp{!}, this test is true if the attribute's value is
8231 @emph{not} in the specified list.
8236 (eq_attr "type" "load,store")
8243 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
8246 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
8247 value of the compiler variable @code{which_alternative}
8248 (@pxref{Output Statement}) and the values must be small integers. For
8252 (eq_attr "alternative" "2,3")
8259 (ior (eq (symbol_ref "which_alternative") (const_int 2))
8260 (eq (symbol_ref "which_alternative") (const_int 3)))
8263 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
8264 where the value of the attribute being tested is known for all insns matching
8265 a particular pattern. This is by far the most common case.
8268 @item (attr_flag @var{name})
8269 The value of an @code{attr_flag} expression is true if the flag
8270 specified by @var{name} is true for the @code{insn} currently being
8273 @var{name} is a string specifying one of a fixed set of flags to test.
8274 Test the flags @code{forward} and @code{backward} to determine the
8275 direction of a conditional branch.
8277 This example describes a conditional branch delay slot which
8278 can be nullified for forward branches that are taken (annul-true) or
8279 for backward branches which are not taken (annul-false).
8282 (define_delay (eq_attr "type" "cbranch")
8283 [(eq_attr "in_branch_delay" "true")
8284 (and (eq_attr "in_branch_delay" "true")
8285 (attr_flag "forward"))
8286 (and (eq_attr "in_branch_delay" "true")
8287 (attr_flag "backward"))])
8290 The @code{forward} and @code{backward} flags are false if the current
8291 @code{insn} being scheduled is not a conditional branch.
8293 @code{attr_flag} is only used during delay slot scheduling and has no
8294 meaning to other passes of the compiler.
8297 @item (attr @var{name})
8298 The value of another attribute is returned. This is most useful
8299 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
8300 produce more efficient code for non-numeric attributes.
8306 @subsection Assigning Attribute Values to Insns
8307 @cindex tagging insns
8308 @cindex assigning attribute values to insns
8310 The value assigned to an attribute of an insn is primarily determined by
8311 which pattern is matched by that insn (or which @code{define_peephole}
8312 generated it). Every @code{define_insn} and @code{define_peephole} can
8313 have an optional last argument to specify the values of attributes for
8314 matching insns. The value of any attribute not specified in a particular
8315 insn is set to the default value for that attribute, as specified in its
8316 @code{define_attr}. Extensive use of default values for attributes
8317 permits the specification of the values for only one or two attributes
8318 in the definition of most insn patterns, as seen in the example in the
8321 The optional last argument of @code{define_insn} and
8322 @code{define_peephole} is a vector of expressions, each of which defines
8323 the value for a single attribute. The most general way of assigning an
8324 attribute's value is to use a @code{set} expression whose first operand is an
8325 @code{attr} expression giving the name of the attribute being set. The
8326 second operand of the @code{set} is an attribute expression
8327 (@pxref{Expressions}) giving the value of the attribute.
8329 When the attribute value depends on the @samp{alternative} attribute
8330 (i.e., which is the applicable alternative in the constraint of the
8331 insn), the @code{set_attr_alternative} expression can be used. It
8332 allows the specification of a vector of attribute expressions, one for
8336 When the generality of arbitrary attribute expressions is not required,
8337 the simpler @code{set_attr} expression can be used, which allows
8338 specifying a string giving either a single attribute value or a list
8339 of attribute values, one for each alternative.
8341 The form of each of the above specifications is shown below. In each case,
8342 @var{name} is a string specifying the attribute to be set.
8345 @item (set_attr @var{name} @var{value-string})
8346 @var{value-string} is either a string giving the desired attribute value,
8347 or a string containing a comma-separated list giving the values for
8348 succeeding alternatives. The number of elements must match the number
8349 of alternatives in the constraint of the insn pattern.
8351 Note that it may be useful to specify @samp{*} for some alternative, in
8352 which case the attribute will assume its default value for insns matching
8355 @findex set_attr_alternative
8356 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
8357 Depending on the alternative of the insn, the value will be one of the
8358 specified values. This is a shorthand for using a @code{cond} with
8359 tests on the @samp{alternative} attribute.
8362 @item (set (attr @var{name}) @var{value})
8363 The first operand of this @code{set} must be the special RTL expression
8364 @code{attr}, whose sole operand is a string giving the name of the
8365 attribute being set. @var{value} is the value of the attribute.
8368 The following shows three different ways of representing the same
8369 attribute value specification:
8372 (set_attr "type" "load,store,arith")
8374 (set_attr_alternative "type"
8375 [(const_string "load") (const_string "store")
8376 (const_string "arith")])
8379 (cond [(eq_attr "alternative" "1") (const_string "load")
8380 (eq_attr "alternative" "2") (const_string "store")]
8381 (const_string "arith")))
8385 @findex define_asm_attributes
8386 The @code{define_asm_attributes} expression provides a mechanism to
8387 specify the attributes assigned to insns produced from an @code{asm}
8388 statement. It has the form:
8391 (define_asm_attributes [@var{attr-sets}])
8395 where @var{attr-sets} is specified the same as for both the
8396 @code{define_insn} and the @code{define_peephole} expressions.
8398 These values will typically be the ``worst case'' attribute values. For
8399 example, they might indicate that the condition code will be clobbered.
8401 A specification for a @code{length} attribute is handled specially. The
8402 way to compute the length of an @code{asm} insn is to multiply the
8403 length specified in the expression @code{define_asm_attributes} by the
8404 number of machine instructions specified in the @code{asm} statement,
8405 determined by counting the number of semicolons and newlines in the
8406 string. Therefore, the value of the @code{length} attribute specified
8407 in a @code{define_asm_attributes} should be the maximum possible length
8408 of a single machine instruction.
8413 @subsection Example of Attribute Specifications
8414 @cindex attribute specifications example
8415 @cindex attribute specifications
8417 The judicious use of defaulting is important in the efficient use of
8418 insn attributes. Typically, insns are divided into @dfn{types} and an
8419 attribute, customarily called @code{type}, is used to represent this
8420 value. This attribute is normally used only to define the default value
8421 for other attributes. An example will clarify this usage.
8423 Assume we have a RISC machine with a condition code and in which only
8424 full-word operations are performed in registers. Let us assume that we
8425 can divide all insns into loads, stores, (integer) arithmetic
8426 operations, floating point operations, and branches.
8428 Here we will concern ourselves with determining the effect of an insn on
8429 the condition code and will limit ourselves to the following possible
8430 effects: The condition code can be set unpredictably (clobbered), not
8431 be changed, be set to agree with the results of the operation, or only
8432 changed if the item previously set into the condition code has been
8435 Here is part of a sample @file{md} file for such a machine:
8438 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
8440 (define_attr "cc" "clobber,unchanged,set,change0"
8441 (cond [(eq_attr "type" "load")
8442 (const_string "change0")
8443 (eq_attr "type" "store,branch")
8444 (const_string "unchanged")
8445 (eq_attr "type" "arith")
8446 (if_then_else (match_operand:SI 0 "" "")
8447 (const_string "set")
8448 (const_string "clobber"))]
8449 (const_string "clobber")))
8452 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
8453 (match_operand:SI 1 "general_operand" "r,m,r"))]
8459 [(set_attr "type" "arith,load,store")])
8462 Note that we assume in the above example that arithmetic operations
8463 performed on quantities smaller than a machine word clobber the condition
8464 code since they will set the condition code to a value corresponding to the
8470 @subsection Computing the Length of an Insn
8471 @cindex insn lengths, computing
8472 @cindex computing the length of an insn
8474 For many machines, multiple types of branch instructions are provided, each
8475 for different length branch displacements. In most cases, the assembler
8476 will choose the correct instruction to use. However, when the assembler
8477 cannot do so, GCC can when a special attribute, the @code{length}
8478 attribute, is defined. This attribute must be defined to have numeric
8479 values by specifying a null string in its @code{define_attr}.
8481 In the case of the @code{length} attribute, two additional forms of
8482 arithmetic terms are allowed in test expressions:
8485 @cindex @code{match_dup} and attributes
8486 @item (match_dup @var{n})
8487 This refers to the address of operand @var{n} of the current insn, which
8488 must be a @code{label_ref}.
8490 @cindex @code{pc} and attributes
8492 For non-branch instructions and backward branch instructions, this refers
8493 to the address of the current insn. But for forward branch instructions,
8494 this refers to the address of the next insn, because the length of the
8495 current insn is to be computed.
8498 @cindex @code{addr_vec}, length of
8499 @cindex @code{addr_diff_vec}, length of
8500 For normal insns, the length will be determined by value of the
8501 @code{length} attribute. In the case of @code{addr_vec} and
8502 @code{addr_diff_vec} insn patterns, the length is computed as
8503 the number of vectors multiplied by the size of each vector.
8505 Lengths are measured in addressable storage units (bytes).
8507 Note that it is possible to call functions via the @code{symbol_ref}
8508 mechanism to compute the length of an insn. However, if you use this
8509 mechanism you must provide dummy clauses to express the maximum length
8510 without using the function call. You can an example of this in the
8511 @code{pa} machine description for the @code{call_symref} pattern.
8513 The following macros can be used to refine the length computation:
8516 @findex ADJUST_INSN_LENGTH
8517 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
8518 If defined, modifies the length assigned to instruction @var{insn} as a
8519 function of the context in which it is used. @var{length} is an lvalue
8520 that contains the initially computed length of the insn and should be
8521 updated with the correct length of the insn.
8523 This macro will normally not be required. A case in which it is
8524 required is the ROMP@. On this machine, the size of an @code{addr_vec}
8525 insn must be increased by two to compensate for the fact that alignment
8529 @findex get_attr_length
8530 The routine that returns @code{get_attr_length} (the value of the
8531 @code{length} attribute) can be used by the output routine to
8532 determine the form of the branch instruction to be written, as the
8533 example below illustrates.
8535 As an example of the specification of variable-length branches, consider
8536 the IBM 360. If we adopt the convention that a register will be set to
8537 the starting address of a function, we can jump to labels within 4k of
8538 the start using a four-byte instruction. Otherwise, we need a six-byte
8539 sequence to load the address from memory and then branch to it.
8541 On such a machine, a pattern for a branch instruction might be specified
8547 (label_ref (match_operand 0 "" "")))]
8550 return (get_attr_length (insn) == 4
8551 ? "b %l0" : "l r15,=a(%l0); br r15");
8553 [(set (attr "length")
8554 (if_then_else (lt (match_dup 0) (const_int 4096))
8561 @node Constant Attributes
8562 @subsection Constant Attributes
8563 @cindex constant attributes
8565 A special form of @code{define_attr}, where the expression for the
8566 default value is a @code{const} expression, indicates an attribute that
8567 is constant for a given run of the compiler. Constant attributes may be
8568 used to specify which variety of processor is used. For example,
8571 (define_attr "cpu" "m88100,m88110,m88000"
8573 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
8574 (symbol_ref "TARGET_88110") (const_string "m88110")]
8575 (const_string "m88000"))))
8577 (define_attr "memory" "fast,slow"
8579 (if_then_else (symbol_ref "TARGET_FAST_MEM")
8580 (const_string "fast")
8581 (const_string "slow"))))
8584 The routine generated for constant attributes has no parameters as it
8585 does not depend on any particular insn. RTL expressions used to define
8586 the value of a constant attribute may use the @code{symbol_ref} form,
8587 but may not use either the @code{match_operand} form or @code{eq_attr}
8588 forms involving insn attributes.
8592 @node Mnemonic Attribute
8593 @subsection Mnemonic Attribute
8594 @cindex mnemonic attribute
8596 The @code{mnemonic} attribute is a string type attribute holding the
8597 instruction mnemonic for an insn alternative. The attribute values
8598 will automatically be generated by the machine description parser if
8599 there is an attribute definition in the md file:
8602 (define_attr "mnemonic" "unknown" (const_string "unknown"))
8605 The default value can be freely chosen as long as it does not collide
8606 with any of the instruction mnemonics. This value will be used
8607 whenever the machine description parser is not able to determine the
8608 mnemonic string. This might be the case for output templates
8609 containing more than a single instruction as in
8610 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
8612 The @code{mnemonic} attribute set is not generated automatically if the
8613 instruction string is generated via C code.
8615 An existing @code{mnemonic} attribute set in an insn definition will not
8616 be overriden by the md file parser. That way it is possible to
8617 manually set the instruction mnemonics for the cases where the md file
8618 parser fails to determine it automatically.
8620 The @code{mnemonic} attribute is useful for dealing with instruction
8621 specific properties in the pipeline description without defining
8622 additional insn attributes.
8625 (define_attr "ooo_expanded" ""
8626 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
8634 @subsection Delay Slot Scheduling
8635 @cindex delay slots, defining
8637 The insn attribute mechanism can be used to specify the requirements for
8638 delay slots, if any, on a target machine. An instruction is said to
8639 require a @dfn{delay slot} if some instructions that are physically
8640 after the instruction are executed as if they were located before it.
8641 Classic examples are branch and call instructions, which often execute
8642 the following instruction before the branch or call is performed.
8644 On some machines, conditional branch instructions can optionally
8645 @dfn{annul} instructions in the delay slot. This means that the
8646 instruction will not be executed for certain branch outcomes. Both
8647 instructions that annul if the branch is true and instructions that
8648 annul if the branch is false are supported.
8650 Delay slot scheduling differs from instruction scheduling in that
8651 determining whether an instruction needs a delay slot is dependent only
8652 on the type of instruction being generated, not on data flow between the
8653 instructions. See the next section for a discussion of data-dependent
8654 instruction scheduling.
8656 @findex define_delay
8657 The requirement of an insn needing one or more delay slots is indicated
8658 via the @code{define_delay} expression. It has the following form:
8661 (define_delay @var{test}
8662 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
8663 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
8667 @var{test} is an attribute test that indicates whether this
8668 @code{define_delay} applies to a particular insn. If so, the number of
8669 required delay slots is determined by the length of the vector specified
8670 as the second argument. An insn placed in delay slot @var{n} must
8671 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
8672 attribute test that specifies which insns may be annulled if the branch
8673 is true. Similarly, @var{annul-false-n} specifies which insns in the
8674 delay slot may be annulled if the branch is false. If annulling is not
8675 supported for that delay slot, @code{(nil)} should be coded.
8677 For example, in the common case where branch and call insns require
8678 a single delay slot, which may contain any insn other than a branch or
8679 call, the following would be placed in the @file{md} file:
8682 (define_delay (eq_attr "type" "branch,call")
8683 [(eq_attr "type" "!branch,call") (nil) (nil)])
8686 Multiple @code{define_delay} expressions may be specified. In this
8687 case, each such expression specifies different delay slot requirements
8688 and there must be no insn for which tests in two @code{define_delay}
8689 expressions are both true.
8691 For example, if we have a machine that requires one delay slot for branches
8692 but two for calls, no delay slot can contain a branch or call insn,
8693 and any valid insn in the delay slot for the branch can be annulled if the
8694 branch is true, we might represent this as follows:
8697 (define_delay (eq_attr "type" "branch")
8698 [(eq_attr "type" "!branch,call")
8699 (eq_attr "type" "!branch,call")
8702 (define_delay (eq_attr "type" "call")
8703 [(eq_attr "type" "!branch,call") (nil) (nil)
8704 (eq_attr "type" "!branch,call") (nil) (nil)])
8706 @c the above is *still* too long. --mew 4feb93
8710 @node Processor pipeline description
8711 @subsection Specifying processor pipeline description
8712 @cindex processor pipeline description
8713 @cindex processor functional units
8714 @cindex instruction latency time
8715 @cindex interlock delays
8716 @cindex data dependence delays
8717 @cindex reservation delays
8718 @cindex pipeline hazard recognizer
8719 @cindex automaton based pipeline description
8720 @cindex regular expressions
8721 @cindex deterministic finite state automaton
8722 @cindex automaton based scheduler
8726 To achieve better performance, most modern processors
8727 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
8728 processors) have many @dfn{functional units} on which several
8729 instructions can be executed simultaneously. An instruction starts
8730 execution if its issue conditions are satisfied. If not, the
8731 instruction is stalled until its conditions are satisfied. Such
8732 @dfn{interlock (pipeline) delay} causes interruption of the fetching
8733 of successor instructions (or demands nop instructions, e.g.@: for some
8736 There are two major kinds of interlock delays in modern processors.
8737 The first one is a data dependence delay determining @dfn{instruction
8738 latency time}. The instruction execution is not started until all
8739 source data have been evaluated by prior instructions (there are more
8740 complex cases when the instruction execution starts even when the data
8741 are not available but will be ready in given time after the
8742 instruction execution start). Taking the data dependence delays into
8743 account is simple. The data dependence (true, output, and
8744 anti-dependence) delay between two instructions is given by a
8745 constant. In most cases this approach is adequate. The second kind
8746 of interlock delays is a reservation delay. The reservation delay
8747 means that two instructions under execution will be in need of shared
8748 processors resources, i.e.@: buses, internal registers, and/or
8749 functional units, which are reserved for some time. Taking this kind
8750 of delay into account is complex especially for modern @acronym{RISC}
8753 The task of exploiting more processor parallelism is solved by an
8754 instruction scheduler. For a better solution to this problem, the
8755 instruction scheduler has to have an adequate description of the
8756 processor parallelism (or @dfn{pipeline description}). GCC
8757 machine descriptions describe processor parallelism and functional
8758 unit reservations for groups of instructions with the aid of
8759 @dfn{regular expressions}.
8761 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
8762 figure out the possibility of the instruction issue by the processor
8763 on a given simulated processor cycle. The pipeline hazard recognizer is
8764 automatically generated from the processor pipeline description. The
8765 pipeline hazard recognizer generated from the machine description
8766 is based on a deterministic finite state automaton (@acronym{DFA}):
8767 the instruction issue is possible if there is a transition from one
8768 automaton state to another one. This algorithm is very fast, and
8769 furthermore, its speed is not dependent on processor
8770 complexity@footnote{However, the size of the automaton depends on
8771 processor complexity. To limit this effect, machine descriptions
8772 can split orthogonal parts of the machine description among several
8773 automata: but then, since each of these must be stepped independently,
8774 this does cause a small decrease in the algorithm's performance.}.
8776 @cindex automaton based pipeline description
8777 The rest of this section describes the directives that constitute
8778 an automaton-based processor pipeline description. The order of
8779 these constructions within the machine description file is not
8782 @findex define_automaton
8783 @cindex pipeline hazard recognizer
8784 The following optional construction describes names of automata
8785 generated and used for the pipeline hazards recognition. Sometimes
8786 the generated finite state automaton used by the pipeline hazard
8787 recognizer is large. If we use more than one automaton and bind functional
8788 units to the automata, the total size of the automata is usually
8789 less than the size of the single automaton. If there is no one such
8790 construction, only one finite state automaton is generated.
8793 (define_automaton @var{automata-names})
8796 @var{automata-names} is a string giving names of the automata. The
8797 names are separated by commas. All the automata should have unique names.
8798 The automaton name is used in the constructions @code{define_cpu_unit} and
8799 @code{define_query_cpu_unit}.
8801 @findex define_cpu_unit
8802 @cindex processor functional units
8803 Each processor functional unit used in the description of instruction
8804 reservations should be described by the following construction.
8807 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
8810 @var{unit-names} is a string giving the names of the functional units
8811 separated by commas. Don't use name @samp{nothing}, it is reserved
8814 @var{automaton-name} is a string giving the name of the automaton with
8815 which the unit is bound. The automaton should be described in
8816 construction @code{define_automaton}. You should give
8817 @dfn{automaton-name}, if there is a defined automaton.
8819 The assignment of units to automata are constrained by the uses of the
8820 units in insn reservations. The most important constraint is: if a
8821 unit reservation is present on a particular cycle of an alternative
8822 for an insn reservation, then some unit from the same automaton must
8823 be present on the same cycle for the other alternatives of the insn
8824 reservation. The rest of the constraints are mentioned in the
8825 description of the subsequent constructions.
8827 @findex define_query_cpu_unit
8828 @cindex querying function unit reservations
8829 The following construction describes CPU functional units analogously
8830 to @code{define_cpu_unit}. The reservation of such units can be
8831 queried for an automaton state. The instruction scheduler never
8832 queries reservation of functional units for given automaton state. So
8833 as a rule, you don't need this construction. This construction could
8834 be used for future code generation goals (e.g.@: to generate
8835 @acronym{VLIW} insn templates).
8838 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
8841 @var{unit-names} is a string giving names of the functional units
8842 separated by commas.
8844 @var{automaton-name} is a string giving the name of the automaton with
8845 which the unit is bound.
8847 @findex define_insn_reservation
8848 @cindex instruction latency time
8849 @cindex regular expressions
8851 The following construction is the major one to describe pipeline
8852 characteristics of an instruction.
8855 (define_insn_reservation @var{insn-name} @var{default_latency}
8856 @var{condition} @var{regexp})
8859 @var{default_latency} is a number giving latency time of the
8860 instruction. There is an important difference between the old
8861 description and the automaton based pipeline description. The latency
8862 time is used for all dependencies when we use the old description. In
8863 the automaton based pipeline description, the given latency time is only
8864 used for true dependencies. The cost of anti-dependencies is always
8865 zero and the cost of output dependencies is the difference between
8866 latency times of the producing and consuming insns (if the difference
8867 is negative, the cost is considered to be zero). You can always
8868 change the default costs for any description by using the target hook
8869 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
8871 @var{insn-name} is a string giving the internal name of the insn. The
8872 internal names are used in constructions @code{define_bypass} and in
8873 the automaton description file generated for debugging. The internal
8874 name has nothing in common with the names in @code{define_insn}. It is a
8875 good practice to use insn classes described in the processor manual.
8877 @var{condition} defines what RTL insns are described by this
8878 construction. You should remember that you will be in trouble if
8879 @var{condition} for two or more different
8880 @code{define_insn_reservation} constructions is TRUE for an insn. In
8881 this case what reservation will be used for the insn is not defined.
8882 Such cases are not checked during generation of the pipeline hazards
8883 recognizer because in general recognizing that two conditions may have
8884 the same value is quite difficult (especially if the conditions
8885 contain @code{symbol_ref}). It is also not checked during the
8886 pipeline hazard recognizer work because it would slow down the
8887 recognizer considerably.
8889 @var{regexp} is a string describing the reservation of the cpu's functional
8890 units by the instruction. The reservations are described by a regular
8891 expression according to the following syntax:
8894 regexp = regexp "," oneof
8897 oneof = oneof "|" allof
8900 allof = allof "+" repeat
8903 repeat = element "*" number
8906 element = cpu_function_unit_name
8915 @samp{,} is used for describing the start of the next cycle in
8919 @samp{|} is used for describing a reservation described by the first
8920 regular expression @strong{or} a reservation described by the second
8921 regular expression @strong{or} etc.
8924 @samp{+} is used for describing a reservation described by the first
8925 regular expression @strong{and} a reservation described by the
8926 second regular expression @strong{and} etc.
8929 @samp{*} is used for convenience and simply means a sequence in which
8930 the regular expression are repeated @var{number} times with cycle
8931 advancing (see @samp{,}).
8934 @samp{cpu_function_unit_name} denotes reservation of the named
8938 @samp{reservation_name} --- see description of construction
8939 @samp{define_reservation}.
8942 @samp{nothing} denotes no unit reservations.
8945 @findex define_reservation
8946 Sometimes unit reservations for different insns contain common parts.
8947 In such case, you can simplify the pipeline description by describing
8948 the common part by the following construction
8951 (define_reservation @var{reservation-name} @var{regexp})
8954 @var{reservation-name} is a string giving name of @var{regexp}.
8955 Functional unit names and reservation names are in the same name
8956 space. So the reservation names should be different from the
8957 functional unit names and can not be the reserved name @samp{nothing}.
8959 @findex define_bypass
8960 @cindex instruction latency time
8962 The following construction is used to describe exceptions in the
8963 latency time for given instruction pair. This is so called bypasses.
8966 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
8970 @var{number} defines when the result generated by the instructions
8971 given in string @var{out_insn_names} will be ready for the
8972 instructions given in string @var{in_insn_names}. Each of these
8973 strings is a comma-separated list of filename-style globs and
8974 they refer to the names of @code{define_insn_reservation}s.
8977 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
8979 defines a bypass between instructions that start with
8980 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
8983 @var{guard} is an optional string giving the name of a C function which
8984 defines an additional guard for the bypass. The function will get the
8985 two insns as parameters. If the function returns zero the bypass will
8986 be ignored for this case. The additional guard is necessary to
8987 recognize complicated bypasses, e.g.@: when the consumer is only an address
8988 of insn @samp{store} (not a stored value).
8990 If there are more one bypass with the same output and input insns, the
8991 chosen bypass is the first bypass with a guard in description whose
8992 guard function returns nonzero. If there is no such bypass, then
8993 bypass without the guard function is chosen.
8995 @findex exclusion_set
8996 @findex presence_set
8997 @findex final_presence_set
8999 @findex final_absence_set
9002 The following five constructions are usually used to describe
9003 @acronym{VLIW} processors, or more precisely, to describe a placement
9004 of small instructions into @acronym{VLIW} instruction slots. They
9005 can be used for @acronym{RISC} processors, too.
9008 (exclusion_set @var{unit-names} @var{unit-names})
9009 (presence_set @var{unit-names} @var{patterns})
9010 (final_presence_set @var{unit-names} @var{patterns})
9011 (absence_set @var{unit-names} @var{patterns})
9012 (final_absence_set @var{unit-names} @var{patterns})
9015 @var{unit-names} is a string giving names of functional units
9016 separated by commas.
9018 @var{patterns} is a string giving patterns of functional units
9019 separated by comma. Currently pattern is one unit or units
9020 separated by white-spaces.
9022 The first construction (@samp{exclusion_set}) means that each
9023 functional unit in the first string can not be reserved simultaneously
9024 with a unit whose name is in the second string and vice versa. For
9025 example, the construction is useful for describing processors
9026 (e.g.@: some SPARC processors) with a fully pipelined floating point
9027 functional unit which can execute simultaneously only single floating
9028 point insns or only double floating point insns.
9030 The second construction (@samp{presence_set}) means that each
9031 functional unit in the first string can not be reserved unless at
9032 least one of pattern of units whose names are in the second string is
9033 reserved. This is an asymmetric relation. For example, it is useful
9034 for description that @acronym{VLIW} @samp{slot1} is reserved after
9035 @samp{slot0} reservation. We could describe it by the following
9039 (presence_set "slot1" "slot0")
9042 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
9043 reservation. In this case we could write
9046 (presence_set "slot1" "slot0 b0")
9049 The third construction (@samp{final_presence_set}) is analogous to
9050 @samp{presence_set}. The difference between them is when checking is
9051 done. When an instruction is issued in given automaton state
9052 reflecting all current and planned unit reservations, the automaton
9053 state is changed. The first state is a source state, the second one
9054 is a result state. Checking for @samp{presence_set} is done on the
9055 source state reservation, checking for @samp{final_presence_set} is
9056 done on the result reservation. This construction is useful to
9057 describe a reservation which is actually two subsequent reservations.
9058 For example, if we use
9061 (presence_set "slot1" "slot0")
9064 the following insn will be never issued (because @samp{slot1} requires
9065 @samp{slot0} which is absent in the source state).
9068 (define_reservation "insn_and_nop" "slot0 + slot1")
9071 but it can be issued if we use analogous @samp{final_presence_set}.
9073 The forth construction (@samp{absence_set}) means that each functional
9074 unit in the first string can be reserved only if each pattern of units
9075 whose names are in the second string is not reserved. This is an
9076 asymmetric relation (actually @samp{exclusion_set} is analogous to
9077 this one but it is symmetric). For example it might be useful in a
9078 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
9079 after either @samp{slot1} or @samp{slot2} have been reserved. This
9080 can be described as:
9083 (absence_set "slot0" "slot1, slot2")
9086 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
9087 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
9088 this case we could write
9091 (absence_set "slot2" "slot0 b0, slot1 b1")
9094 All functional units mentioned in a set should belong to the same
9097 The last construction (@samp{final_absence_set}) is analogous to
9098 @samp{absence_set} but checking is done on the result (state)
9099 reservation. See comments for @samp{final_presence_set}.
9101 @findex automata_option
9102 @cindex deterministic finite state automaton
9103 @cindex nondeterministic finite state automaton
9104 @cindex finite state automaton minimization
9105 You can control the generator of the pipeline hazard recognizer with
9106 the following construction.
9109 (automata_option @var{options})
9112 @var{options} is a string giving options which affect the generated
9113 code. Currently there are the following options:
9117 @dfn{no-minimization} makes no minimization of the automaton. This is
9118 only worth to do when we are debugging the description and need to
9119 look more accurately at reservations of states.
9122 @dfn{time} means printing time statistics about the generation of
9126 @dfn{stats} means printing statistics about the generated automata
9127 such as the number of DFA states, NDFA states and arcs.
9130 @dfn{v} means a generation of the file describing the result automata.
9131 The file has suffix @samp{.dfa} and can be used for the description
9132 verification and debugging.
9135 @dfn{w} means a generation of warning instead of error for
9136 non-critical errors.
9139 @dfn{no-comb-vect} prevents the automaton generator from generating
9140 two data structures and comparing them for space efficiency. Using
9141 a comb vector to represent transitions may be better, but it can be
9142 very expensive to construct. This option is useful if the build
9143 process spends an unacceptably long time in genautomata.
9146 @dfn{ndfa} makes nondeterministic finite state automata. This affects
9147 the treatment of operator @samp{|} in the regular expressions. The
9148 usual treatment of the operator is to try the first alternative and,
9149 if the reservation is not possible, the second alternative. The
9150 nondeterministic treatment means trying all alternatives, some of them
9151 may be rejected by reservations in the subsequent insns.
9154 @dfn{collapse-ndfa} modifies the behaviour of the generator when
9155 producing an automaton. An additional state transition to collapse a
9156 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
9157 state is generated. It can be triggered by passing @code{const0_rtx} to
9158 state_transition. In such an automaton, cycle advance transitions are
9159 available only for these collapsed states. This option is useful for
9160 ports that want to use the @code{ndfa} option, but also want to use
9161 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
9164 @dfn{progress} means output of a progress bar showing how many states
9165 were generated so far for automaton being processed. This is useful
9166 during debugging a @acronym{DFA} description. If you see too many
9167 generated states, you could interrupt the generator of the pipeline
9168 hazard recognizer and try to figure out a reason for generation of the
9172 As an example, consider a superscalar @acronym{RISC} machine which can
9173 issue three insns (two integer insns and one floating point insn) on
9174 the cycle but can finish only two insns. To describe this, we define
9175 the following functional units.
9178 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
9179 (define_cpu_unit "port0, port1")
9182 All simple integer insns can be executed in any integer pipeline and
9183 their result is ready in two cycles. The simple integer insns are
9184 issued into the first pipeline unless it is reserved, otherwise they
9185 are issued into the second pipeline. Integer division and
9186 multiplication insns can be executed only in the second integer
9187 pipeline and their results are ready correspondingly in 8 and 4
9188 cycles. The integer division is not pipelined, i.e.@: the subsequent
9189 integer division insn can not be issued until the current division
9190 insn finished. Floating point insns are fully pipelined and their
9191 results are ready in 3 cycles. Where the result of a floating point
9192 insn is used by an integer insn, an additional delay of one cycle is
9193 incurred. To describe all of this we could specify
9196 (define_cpu_unit "div")
9198 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9199 "(i0_pipeline | i1_pipeline), (port0 | port1)")
9201 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
9202 "i1_pipeline, nothing*2, (port0 | port1)")
9204 (define_insn_reservation "div" 8 (eq_attr "type" "div")
9205 "i1_pipeline, div*7, div + (port0 | port1)")
9207 (define_insn_reservation "float" 3 (eq_attr "type" "float")
9208 "f_pipeline, nothing, (port0 | port1))
9210 (define_bypass 4 "float" "simple,mult,div")
9213 To simplify the description we could describe the following reservation
9216 (define_reservation "finish" "port0|port1")
9219 and use it in all @code{define_insn_reservation} as in the following
9223 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9224 "(i0_pipeline | i1_pipeline), finish")
9230 @node Conditional Execution
9231 @section Conditional Execution
9232 @cindex conditional execution
9235 A number of architectures provide for some form of conditional
9236 execution, or predication. The hallmark of this feature is the
9237 ability to nullify most of the instructions in the instruction set.
9238 When the instruction set is large and not entirely symmetric, it
9239 can be quite tedious to describe these forms directly in the
9240 @file{.md} file. An alternative is the @code{define_cond_exec} template.
9242 @findex define_cond_exec
9245 [@var{predicate-pattern}]
9247 "@var{output-template}"
9248 "@var{optional-insn-attribues}")
9251 @var{predicate-pattern} is the condition that must be true for the
9252 insn to be executed at runtime and should match a relational operator.
9253 One can use @code{match_operator} to match several relational operators
9254 at once. Any @code{match_operand} operands must have no more than one
9257 @var{condition} is a C expression that must be true for the generated
9260 @findex current_insn_predicate
9261 @var{output-template} is a string similar to the @code{define_insn}
9262 output template (@pxref{Output Template}), except that the @samp{*}
9263 and @samp{@@} special cases do not apply. This is only useful if the
9264 assembly text for the predicate is a simple prefix to the main insn.
9265 In order to handle the general case, there is a global variable
9266 @code{current_insn_predicate} that will contain the entire predicate
9267 if the current insn is predicated, and will otherwise be @code{NULL}.
9269 @var{optional-insn-attributes} is an optional vector of attributes that gets
9270 appended to the insn attributes of the produced cond_exec rtx. It can
9271 be used to add some distinguishing attribute to cond_exec rtxs produced
9272 that way. An example usage would be to use this attribute in conjunction
9273 with attributes on the main pattern to disable particular alternatives under
9276 When @code{define_cond_exec} is used, an implicit reference to
9277 the @code{predicable} instruction attribute is made.
9278 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
9279 exactly two elements in its @var{list-of-values}), with the possible
9280 values being @code{no} and @code{yes}. The default and all uses in
9281 the insns must be a simple constant, not a complex expressions. It
9282 may, however, depend on the alternative, by using a comma-separated
9283 list of values. If that is the case, the port should also define an
9284 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
9285 should also allow only @code{no} and @code{yes} as its values.
9287 For each @code{define_insn} for which the @code{predicable}
9288 attribute is true, a new @code{define_insn} pattern will be
9289 generated that matches a predicated version of the instruction.
9293 (define_insn "addsi"
9294 [(set (match_operand:SI 0 "register_operand" "r")
9295 (plus:SI (match_operand:SI 1 "register_operand" "r")
9296 (match_operand:SI 2 "register_operand" "r")))]
9301 [(ne (match_operand:CC 0 "register_operand" "c")
9308 generates a new pattern
9313 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
9314 (set (match_operand:SI 0 "register_operand" "r")
9315 (plus:SI (match_operand:SI 1 "register_operand" "r")
9316 (match_operand:SI 2 "register_operand" "r"))))]
9317 "(@var{test2}) && (@var{test1})"
9318 "(%3) add %2,%1,%0")
9324 @section RTL Templates Transformations
9325 @cindex define_subst
9327 For some hardware architectures there are common cases when the RTL
9328 templates for the instructions can be derived from the other RTL
9329 templates using simple transformations. E.g., @file{i386.md} contains
9330 an RTL template for the ordinary @code{sub} instruction---
9331 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
9332 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
9333 implemented by a single meta-template capable of generating a modified
9334 case based on the initial one:
9336 @findex define_subst
9338 (define_subst "@var{name}"
9339 [@var{input-template}]
9341 [@var{output-template}])
9343 @var{input-template} is a pattern describing the source RTL template,
9344 which will be transformed.
9346 @var{condition} is a C expression that is conjunct with the condition
9347 from the input-template to generate a condition to be used in the
9350 @var{output-template} is a pattern that will be used in the resulting
9353 @code{define_subst} mechanism is tightly coupled with the notion of the
9354 subst attribute (@pxref{Subst Iterators}). The use of
9355 @code{define_subst} is triggered by a reference to a subst attribute in
9356 the transforming RTL template. This reference initiates duplication of
9357 the source RTL template and substitution of the attributes with their
9358 values. The source RTL template is left unchanged, while the copy is
9359 transformed by @code{define_subst}. This transformation can fail in the
9360 case when the source RTL template is not matched against the
9361 input-template of the @code{define_subst}. In such case the copy is
9364 @code{define_subst} can be used only in @code{define_insn} and
9365 @code{define_expand}, it cannot be used in other expressions (e.g. in
9366 @code{define_insn_and_split}).
9369 * Define Subst Example:: Example of @code{define_subst} work.
9370 * Define Subst Pattern Matching:: Process of template comparison.
9371 * Define Subst Output Template:: Generation of output template.
9374 @node Define Subst Example
9375 @subsection @code{define_subst} Example
9376 @cindex define_subst
9378 To illustrate how @code{define_subst} works, let us examine a simple
9379 template transformation.
9381 Suppose there are two kinds of instructions: one that touches flags and
9382 the other that does not. The instructions of the second type could be
9383 generated with the following @code{define_subst}:
9386 (define_subst "add_clobber_subst"
9387 [(set (match_operand:SI 0 "" "")
9388 (match_operand:SI 1 "" ""))]
9392 (clobber (reg:CC FLAGS_REG))]
9395 This @code{define_subst} can be applied to any RTL pattern containing
9396 @code{set} of mode SI and generates a copy with clobber when it is
9399 Assume there is an RTL template for a @code{max} instruction to be used
9400 in @code{define_subst} mentioned above:
9403 (define_insn "maxsi"
9404 [(set (match_operand:SI 0 "register_operand" "=r")
9406 (match_operand:SI 1 "register_operand" "r")
9407 (match_operand:SI 2 "register_operand" "r")))]
9409 "max\t@{%2, %1, %0|%0, %1, %2@}"
9413 To mark the RTL template for @code{define_subst} application,
9414 subst-attributes are used. They should be declared in advance:
9417 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
9420 Here @samp{add_clobber_name} is the attribute name,
9421 @samp{add_clobber_subst} is the name of the corresponding
9422 @code{define_subst}, the third argument (@samp{_noclobber}) is the
9423 attribute value that would be substituted into the unchanged version of
9424 the source RTL template, and the last argument (@samp{_clobber}) is the
9425 value that would be substituted into the second, transformed,
9426 version of the RTL template.
9428 Once the subst-attribute has been defined, it should be used in RTL
9429 templates which need to be processed by the @code{define_subst}. So,
9430 the original RTL template should be changed:
9433 (define_insn "maxsi<add_clobber_name>"
9434 [(set (match_operand:SI 0 "register_operand" "=r")
9436 (match_operand:SI 1 "register_operand" "r")
9437 (match_operand:SI 2 "register_operand" "r")))]
9439 "max\t@{%2, %1, %0|%0, %1, %2@}"
9443 The result of the @code{define_subst} usage would look like the following:
9446 (define_insn "maxsi_noclobber"
9447 [(set (match_operand:SI 0 "register_operand" "=r")
9449 (match_operand:SI 1 "register_operand" "r")
9450 (match_operand:SI 2 "register_operand" "r")))]
9452 "max\t@{%2, %1, %0|%0, %1, %2@}"
9454 (define_insn "maxsi_clobber"
9455 [(set (match_operand:SI 0 "register_operand" "=r")
9457 (match_operand:SI 1 "register_operand" "r")
9458 (match_operand:SI 2 "register_operand" "r")))
9459 (clobber (reg:CC FLAGS_REG))]
9461 "max\t@{%2, %1, %0|%0, %1, %2@}"
9465 @node Define Subst Pattern Matching
9466 @subsection Pattern Matching in @code{define_subst}
9467 @cindex define_subst
9469 All expressions, allowed in @code{define_insn} or @code{define_expand},
9470 are allowed in the input-template of @code{define_subst}, except
9471 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
9472 meanings of expressions in the input-template were changed:
9474 @code{match_operand} matches any expression (possibly, a subtree in
9475 RTL-template), if modes of the @code{match_operand} and this expression
9476 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
9477 this expression is @code{match_dup}, @code{match_op_dup}. If the
9478 expression is @code{match_operand} too, and predicate of
9479 @code{match_operand} from the input pattern is not empty, then the
9480 predicates are compared. That can be used for more accurate filtering
9481 of accepted RTL-templates.
9483 @code{match_operator} matches common operators (like @code{plus},
9484 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
9485 @code{match_operator}s from the original pattern if the modes match and
9486 @code{match_operator} from the input pattern has the same number of
9487 operands as the operator from the original pattern.
9489 @node Define Subst Output Template
9490 @subsection Generation of output template in @code{define_subst}
9491 @cindex define_subst
9493 If all necessary checks for @code{define_subst} application pass, a new
9494 RTL-pattern, based on the output-template, is created to replace the old
9495 template. Like in input-patterns, meanings of some RTL expressions are
9496 changed when they are used in output-patterns of a @code{define_subst}.
9497 Thus, @code{match_dup} is used for copying the whole expression from the
9498 original pattern, which matched corresponding @code{match_operand} from
9501 @code{match_dup N} is used in the output template to be replaced with
9502 the expression from the original pattern, which matched
9503 @code{match_operand N} from the input pattern. As a consequence,
9504 @code{match_dup} cannot be used to point to @code{match_operand}s from
9505 the output pattern, it should always refer to a @code{match_operand}
9506 from the input pattern.
9508 In the output template one can refer to the expressions from the
9509 original pattern and create new ones. For instance, some operands could
9510 be added by means of standard @code{match_operand}.
9512 After replacing @code{match_dup} with some RTL-subtree from the original
9513 pattern, it could happen that several @code{match_operand}s in the
9514 output pattern have the same indexes. It is unknown, how many and what
9515 indexes would be used in the expression which would replace
9516 @code{match_dup}, so such conflicts in indexes are inevitable. To
9517 overcome this issue, @code{match_operands} and @code{match_operators},
9518 which were introduced into the output pattern, are renumerated when all
9519 @code{match_dup}s are replaced.
9521 Number of alternatives in @code{match_operand}s introduced into the
9522 output template @code{M} could differ from the number of alternatives in
9523 the original pattern @code{N}, so in the resultant pattern there would
9524 be @code{N*M} alternatives. Thus, constraints from the original pattern
9525 would be duplicated @code{N} times, constraints from the output pattern
9526 would be duplicated @code{M} times, producing all possible combinations.
9530 @node Constant Definitions
9531 @section Constant Definitions
9532 @cindex constant definitions
9533 @findex define_constants
9535 Using literal constants inside instruction patterns reduces legibility and
9536 can be a maintenance problem.
9538 To overcome this problem, you may use the @code{define_constants}
9539 expression. It contains a vector of name-value pairs. From that
9540 point on, wherever any of the names appears in the MD file, it is as
9541 if the corresponding value had been written instead. You may use
9542 @code{define_constants} multiple times; each appearance adds more
9543 constants to the table. It is an error to redefine a constant with
9546 To come back to the a29k load multiple example, instead of
9550 [(match_parallel 0 "load_multiple_operation"
9551 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9552 (match_operand:SI 2 "memory_operand" "m"))
9554 (clobber (reg:SI 179))])]
9570 [(match_parallel 0 "load_multiple_operation"
9571 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9572 (match_operand:SI 2 "memory_operand" "m"))
9574 (clobber (reg:SI R_CR))])]
9579 The constants that are defined with a define_constant are also output
9580 in the insn-codes.h header file as #defines.
9582 @cindex enumerations
9583 @findex define_c_enum
9584 You can also use the machine description file to define enumerations.
9585 Like the constants defined by @code{define_constant}, these enumerations
9586 are visible to both the machine description file and the main C code.
9588 The syntax is as follows:
9591 (define_c_enum "@var{name}" [
9599 This definition causes the equivalent of the following C code to appear
9600 in @file{insn-constants.h}:
9607 @var{valuen} = @var{n}
9609 #define NUM_@var{cname}_VALUES (@var{n} + 1)
9612 where @var{cname} is the capitalized form of @var{name}.
9613 It also makes each @var{valuei} available in the machine description
9614 file, just as if it had been declared with:
9617 (define_constants [(@var{valuei} @var{i})])
9620 Each @var{valuei} is usually an upper-case identifier and usually
9621 begins with @var{cname}.
9623 You can split the enumeration definition into as many statements as
9624 you like. The above example is directly equivalent to:
9627 (define_c_enum "@var{name}" [@var{value0}])
9628 (define_c_enum "@var{name}" [@var{value1}])
9630 (define_c_enum "@var{name}" [@var{valuen}])
9633 Splitting the enumeration helps to improve the modularity of each
9634 individual @code{.md} file. For example, if a port defines its
9635 synchronization instructions in a separate @file{sync.md} file,
9636 it is convenient to define all synchronization-specific enumeration
9637 values in @file{sync.md} rather than in the main @file{.md} file.
9639 Some enumeration names have special significance to GCC:
9643 @findex unspec_volatile
9644 If an enumeration called @code{unspecv} is defined, GCC will use it
9645 when printing out @code{unspec_volatile} expressions. For example:
9648 (define_c_enum "unspecv" [
9653 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
9656 (unspec_volatile ... UNSPECV_BLOCKAGE)
9661 If an enumeration called @code{unspec} is defined, GCC will use
9662 it when printing out @code{unspec} expressions. GCC will also use
9663 it when printing out @code{unspec_volatile} expressions unless an
9664 @code{unspecv} enumeration is also defined. You can therefore
9665 decide whether to keep separate enumerations for volatile and
9666 non-volatile expressions or whether to use the same enumeration
9671 @anchor{define_enum}
9672 Another way of defining an enumeration is to use @code{define_enum}:
9675 (define_enum "@var{name}" [
9683 This directive implies:
9686 (define_c_enum "@var{name}" [
9687 @var{cname}_@var{cvalue0}
9688 @var{cname}_@var{cvalue1}
9690 @var{cname}_@var{cvaluen}
9694 @findex define_enum_attr
9695 where @var{cvaluei} is the capitalized form of @var{valuei}.
9696 However, unlike @code{define_c_enum}, the enumerations defined
9697 by @code{define_enum} can be used in attribute specifications
9698 (@pxref{define_enum_attr}).
9703 @cindex iterators in @file{.md} files
9705 Ports often need to define similar patterns for more than one machine
9706 mode or for more than one rtx code. GCC provides some simple iterator
9707 facilities to make this process easier.
9710 * Mode Iterators:: Generating variations of patterns for different modes.
9711 * Code Iterators:: Doing the same for codes.
9712 * Int Iterators:: Doing the same for integers.
9713 * Subst Iterators:: Generating variations of patterns for define_subst.
9716 @node Mode Iterators
9717 @subsection Mode Iterators
9718 @cindex mode iterators in @file{.md} files
9720 Ports often need to define similar patterns for two or more different modes.
9725 If a processor has hardware support for both single and double
9726 floating-point arithmetic, the @code{SFmode} patterns tend to be
9727 very similar to the @code{DFmode} ones.
9730 If a port uses @code{SImode} pointers in one configuration and
9731 @code{DImode} pointers in another, it will usually have very similar
9732 @code{SImode} and @code{DImode} patterns for manipulating pointers.
9735 Mode iterators allow several patterns to be instantiated from one
9736 @file{.md} file template. They can be used with any type of
9737 rtx-based construct, such as a @code{define_insn},
9738 @code{define_split}, or @code{define_peephole2}.
9741 * Defining Mode Iterators:: Defining a new mode iterator.
9742 * Substitutions:: Combining mode iterators with substitutions
9743 * Examples:: Examples
9746 @node Defining Mode Iterators
9747 @subsubsection Defining Mode Iterators
9748 @findex define_mode_iterator
9750 The syntax for defining a mode iterator is:
9753 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
9756 This allows subsequent @file{.md} file constructs to use the mode suffix
9757 @code{:@var{name}}. Every construct that does so will be expanded
9758 @var{n} times, once with every use of @code{:@var{name}} replaced by
9759 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
9760 and so on. In the expansion for a particular @var{modei}, every
9761 C condition will also require that @var{condi} be true.
9766 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9769 defines a new mode suffix @code{:P}. Every construct that uses
9770 @code{:P} will be expanded twice, once with every @code{:P} replaced
9771 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
9772 The @code{:SI} version will only apply if @code{Pmode == SImode} and
9773 the @code{:DI} version will only apply if @code{Pmode == DImode}.
9775 As with other @file{.md} conditions, an empty string is treated
9776 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
9777 to @code{@var{mode}}. For example:
9780 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9783 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
9784 but that the @code{:SI} expansion has no such constraint.
9786 Iterators are applied in the order they are defined. This can be
9787 significant if two iterators are used in a construct that requires
9788 substitutions. @xref{Substitutions}.
9791 @subsubsection Substitution in Mode Iterators
9792 @findex define_mode_attr
9794 If an @file{.md} file construct uses mode iterators, each version of the
9795 construct will often need slightly different strings or modes. For
9800 When a @code{define_expand} defines several @code{add@var{m}3} patterns
9801 (@pxref{Standard Names}), each expander will need to use the
9802 appropriate mode name for @var{m}.
9805 When a @code{define_insn} defines several instruction patterns,
9806 each instruction will often use a different assembler mnemonic.
9809 When a @code{define_insn} requires operands with different modes,
9810 using an iterator for one of the operand modes usually requires a specific
9811 mode for the other operand(s).
9814 GCC supports such variations through a system of ``mode attributes''.
9815 There are two standard attributes: @code{mode}, which is the name of
9816 the mode in lower case, and @code{MODE}, which is the same thing in
9817 upper case. You can define other attributes using:
9820 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
9823 where @var{name} is the name of the attribute and @var{valuei}
9824 is the value associated with @var{modei}.
9826 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
9827 each string and mode in the pattern for sequences of the form
9828 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
9829 mode attribute. If the attribute is defined for @var{mode}, the whole
9830 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
9833 For example, suppose an @file{.md} file has:
9836 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9837 (define_mode_attr load [(SI "lw") (DI "ld")])
9840 If one of the patterns that uses @code{:P} contains the string
9841 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
9842 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
9845 Here is an example of using an attribute for a mode:
9848 (define_mode_iterator LONG [SI DI])
9849 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
9850 (define_insn @dots{}
9851 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
9854 The @code{@var{iterator}:} prefix may be omitted, in which case the
9855 substitution will be attempted for every iterator expansion.
9858 @subsubsection Mode Iterator Examples
9860 Here is an example from the MIPS port. It defines the following
9861 modes and attributes (among others):
9864 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9865 (define_mode_attr d [(SI "") (DI "d")])
9868 and uses the following template to define both @code{subsi3}
9872 (define_insn "sub<mode>3"
9873 [(set (match_operand:GPR 0 "register_operand" "=d")
9874 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
9875 (match_operand:GPR 2 "register_operand" "d")))]
9878 [(set_attr "type" "arith")
9879 (set_attr "mode" "<MODE>")])
9882 This is exactly equivalent to:
9885 (define_insn "subsi3"
9886 [(set (match_operand:SI 0 "register_operand" "=d")
9887 (minus:SI (match_operand:SI 1 "register_operand" "d")
9888 (match_operand:SI 2 "register_operand" "d")))]
9891 [(set_attr "type" "arith")
9892 (set_attr "mode" "SI")])
9894 (define_insn "subdi3"
9895 [(set (match_operand:DI 0 "register_operand" "=d")
9896 (minus:DI (match_operand:DI 1 "register_operand" "d")
9897 (match_operand:DI 2 "register_operand" "d")))]
9900 [(set_attr "type" "arith")
9901 (set_attr "mode" "DI")])
9904 @node Code Iterators
9905 @subsection Code Iterators
9906 @cindex code iterators in @file{.md} files
9907 @findex define_code_iterator
9908 @findex define_code_attr
9910 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
9915 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
9918 defines a pseudo rtx code @var{name} that can be instantiated as
9919 @var{codei} if condition @var{condi} is true. Each @var{codei}
9920 must have the same rtx format. @xref{RTL Classes}.
9922 As with mode iterators, each pattern that uses @var{name} will be
9923 expanded @var{n} times, once with all uses of @var{name} replaced by
9924 @var{code1}, once with all uses replaced by @var{code2}, and so on.
9925 @xref{Defining Mode Iterators}.
9927 It is possible to define attributes for codes as well as for modes.
9928 There are two standard code attributes: @code{code}, the name of the
9929 code in lower case, and @code{CODE}, the name of the code in upper case.
9930 Other attributes are defined using:
9933 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
9936 Here's an example of code iterators in action, taken from the MIPS port:
9939 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
9940 eq ne gt ge lt le gtu geu ltu leu])
9942 (define_expand "b<code>"
9944 (if_then_else (any_cond:CC (cc0)
9946 (label_ref (match_operand 0 ""))
9950 gen_conditional_branch (operands, <CODE>);
9955 This is equivalent to:
9958 (define_expand "bunordered"
9960 (if_then_else (unordered:CC (cc0)
9962 (label_ref (match_operand 0 ""))
9966 gen_conditional_branch (operands, UNORDERED);
9970 (define_expand "bordered"
9972 (if_then_else (ordered:CC (cc0)
9974 (label_ref (match_operand 0 ""))
9978 gen_conditional_branch (operands, ORDERED);
9986 @subsection Int Iterators
9987 @cindex int iterators in @file{.md} files
9988 @findex define_int_iterator
9989 @findex define_int_attr
9991 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
9996 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
9999 defines a pseudo integer constant @var{name} that can be instantiated as
10000 @var{inti} if condition @var{condi} is true. Each @var{int}
10001 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
10002 in only those rtx fields that have 'i' as the specifier. This means that
10003 each @var{int} has to be a constant defined using define_constant or
10006 As with mode and code iterators, each pattern that uses @var{name} will be
10007 expanded @var{n} times, once with all uses of @var{name} replaced by
10008 @var{int1}, once with all uses replaced by @var{int2}, and so on.
10009 @xref{Defining Mode Iterators}.
10011 It is possible to define attributes for ints as well as for codes and modes.
10012 Attributes are defined using:
10015 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
10018 Here's an example of int iterators in action, taken from the ARM port:
10021 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
10023 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
10025 (define_insn "neon_vq<absneg><mode>"
10026 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10027 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10028 (match_operand:SI 2 "immediate_operand" "i")]
10031 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10032 [(set_attr "type" "neon_vqneg_vqabs")]
10037 This is equivalent to:
10040 (define_insn "neon_vqabs<mode>"
10041 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10042 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10043 (match_operand:SI 2 "immediate_operand" "i")]
10046 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10047 [(set_attr "type" "neon_vqneg_vqabs")]
10050 (define_insn "neon_vqneg<mode>"
10051 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10052 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10053 (match_operand:SI 2 "immediate_operand" "i")]
10056 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10057 [(set_attr "type" "neon_vqneg_vqabs")]
10062 @node Subst Iterators
10063 @subsection Subst Iterators
10064 @cindex subst iterators in @file{.md} files
10065 @findex define_subst
10066 @findex define_subst_attr
10068 Subst iterators are special type of iterators with the following
10069 restrictions: they could not be declared explicitly, they always have
10070 only two values, and they do not have explicit dedicated name.
10071 Subst-iterators are triggered only when corresponding subst-attribute is
10072 used in RTL-pattern.
10074 Subst iterators transform templates in the following way: the templates
10075 are duplicated, the subst-attributes in these templates are replaced
10076 with the corresponding values, and a new attribute is implicitly added
10077 to the given @code{define_insn}/@code{define_expand}. The name of the
10078 added attribute matches the name of @code{define_subst}. Such
10079 attributes are declared implicitly, and it is not allowed to have a
10080 @code{define_attr} named as a @code{define_subst}.
10082 Each subst iterator is linked to a @code{define_subst}. It is declared
10083 implicitly by the first appearance of the corresponding
10084 @code{define_subst_attr}, and it is not allowed to define it explicitly.
10086 Declarations of subst-attributes have the following syntax:
10088 @findex define_subst_attr
10090 (define_subst_attr "@var{name}"
10092 "@var{no-subst-value}"
10093 "@var{subst-applied-value}")
10096 @var{name} is a string with which the given subst-attribute could be
10099 @var{subst-name} shows which @code{define_subst} should be applied to an
10100 RTL-template if the given subst-attribute is present in the
10103 @var{no-subst-value} is a value with which subst-attribute would be
10104 replaced in the first copy of the original RTL-template.
10106 @var{subst-applied-value} is a value with which subst-attribute would be
10107 replaced in the second copy of the original RTL-template.