1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93, 94, 1995 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "insn-attr.h"
38 #include "insn-codes.h"
42 #undef MAX /* sys/param.h may also define these */
47 #include <sys/types.h>
60 #if defined(USG) || defined(NO_STAB_H)
61 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
63 #include <stab.h> /* On BSD, use the system's stab.h. */
67 #define STAB_CODE_TYPE enum __stab_debug_code
69 #define STAB_CODE_TYPE int
74 extern char *getenv ();
75 extern char *mktemp ();
77 extern rtx
adj_offsettable_operand ();
78 extern rtx
copy_to_reg ();
81 extern tree
lookup_name ();
82 extern void pfatal_with_name ();
83 extern void warning ();
85 extern FILE *asm_out_file
;
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
105 /* Global variables for machine-dependent things. */
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold
= -1;
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames
= 0;
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count
= 0;
120 /* Next label # for each statement for Silicon Graphics IRIS systems. */
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function
= 0;
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file
;
131 FILE *asm_out_text_file
;
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
138 struct extern_list
*next
; /* next external */
139 char *name
; /* name of the external */
140 int size
; /* size in bytes */
143 /* Name of the file containing the current function. */
144 char *current_function_file
= "";
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning
= FALSE
;
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number
= FALSE
;
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely
;
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total
;
165 int dslots_load_filled
;
166 int dslots_jump_total
;
167 int dslots_jump_filled
;
169 /* # of nops needed by previous insn */
170 int dslots_number_nops
;
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
175 /* registers to check for load delay */
176 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
178 /* Cached operands, and operator to compare for use in set/branch on
182 /* what type of branch to use */
183 enum cmp_type branch_type
;
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs
= 0;
187 static int prev_half_pic_refs
= 0;
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu
;
192 /* which instruction set architecture to use. */
195 /* Strings to hold which cpu and instruction set architecture to use. */
196 char *mips_cpu_string
; /* for -mcpu=<xxx> */
197 char *mips_isa_string
; /* for -mips{1,2,3,4} */
199 /* Generating calls to position independent functions? */
200 enum mips_abicalls_type mips_abicalls
;
202 /* High and low marks for floating point values which we will accept
203 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
204 initialized in override_options. */
205 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
207 /* Array giving truth value on whether or not a given hard register
208 can support a given mode. */
209 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
211 /* Current frame information calculated by compute_frame_size. */
212 struct mips_frame_info current_frame_info
;
214 /* Zero structure to initialize current_frame_info. */
215 struct mips_frame_info zero_frame_info
;
217 /* Temporary filename used to buffer .text until end of program
219 static char *temp_filename
;
221 /* Pseudo-reg holding the address of the current function when
222 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
223 by mips_finalize_pic if it was created. */
224 rtx embedded_pic_fnaddr_rtx
;
226 /* List of all MIPS punctuation characters used by print_operand. */
227 char mips_print_operand_punct
[256];
229 /* Map GCC register number to debugger register number. */
230 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
232 /* Buffer to use to enclose a load/store operation with %{ %} to
233 turn on .set volatile. */
234 static char volatile_buffer
[60];
236 /* Hardware names for the registers. If -mrnames is used, this
237 will be overwritten with mips_sw_reg_names. */
239 char mips_reg_names
[][8] =
241 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
242 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
243 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
244 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
245 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
246 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
247 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
248 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
249 "hi", "lo", "accum","$fcr31","$rap"
252 /* Mips software names for the registers, used to overwrite the
253 mips_reg_names array. */
255 char mips_sw_reg_names
[][8] =
257 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
258 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
259 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
260 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
261 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
262 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
263 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
264 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
265 "hi", "lo", "accum","$fcr31","$rap"
268 /* Map hard register number to register class */
269 enum reg_class mips_regno_to_class
[] =
271 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
272 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
273 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
274 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
275 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
276 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
277 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
278 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
279 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
280 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
281 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
282 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
283 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
284 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
285 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
286 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
287 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
291 /* Map register constraint character to register class. */
292 enum reg_class mips_char_to_class
[256] =
294 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
295 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
296 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
297 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
298 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
299 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
300 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
301 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
302 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
303 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
304 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
305 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
306 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
307 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
361 /* Return truth value of whether OP can be used as an operands
362 where a register or 16 bit unsigned integer is needed. */
365 uns_arith_operand (op
, mode
)
367 enum machine_mode mode
;
369 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
372 return register_operand (op
, mode
);
375 /* Return truth value of whether OP can be used as an operands
376 where a 16 bit integer is needed */
379 arith_operand (op
, mode
)
381 enum machine_mode mode
;
383 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
386 return register_operand (op
, mode
);
389 /* Return truth value of whether OP can be used as an operand in a two
390 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
393 arith32_operand (op
, mode
)
395 enum machine_mode mode
;
397 if (GET_CODE (op
) == CONST_INT
)
400 return register_operand (op
, mode
);
403 /* Return truth value of whether OP is a integer which fits in 16 bits */
408 enum machine_mode mode
;
410 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
413 /* Return truth value of whether OP is a 32 bit integer which is too big to
414 be loaded with one instruction. */
419 enum machine_mode mode
;
423 if (GET_CODE (op
) != CONST_INT
)
427 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
430 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
433 if ((value
& 0x0000ffff) == 0) /* lui reg,value>>16 */
439 /* Return truth value of whether OP is a register or the constant 0. */
442 reg_or_0_operand (op
, mode
)
444 enum machine_mode mode
;
446 switch (GET_CODE (op
))
452 return (INTVAL (op
) == 0);
455 if (op
!= CONST0_RTX (mode
))
462 return register_operand (op
, mode
);
468 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
471 mips_const_double_ok (op
, mode
)
473 enum machine_mode mode
;
477 if (GET_CODE (op
) != CONST_DOUBLE
)
480 if (mode
== VOIDmode
)
483 if (mode
!= SFmode
&& mode
!= DFmode
)
486 if (op
== CONST0_RTX (mode
))
489 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
493 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
495 if (REAL_VALUE_ISNAN (d
))
498 if (REAL_VALUE_NEGATIVE (d
))
499 d
= REAL_VALUE_NEGATE (d
);
503 if (REAL_VALUES_LESS (d
, dfhigh
)
504 && REAL_VALUES_LESS (dflow
, d
))
509 if (REAL_VALUES_LESS (d
, sfhigh
)
510 && REAL_VALUES_LESS (sflow
, d
))
517 /* Return truth value if a memory operand fits in a single instruction
518 (ie, register + small offset). */
521 simple_memory_operand (op
, mode
)
523 enum machine_mode mode
;
525 rtx addr
, plus0
, plus1
;
527 /* Eliminate non-memory operations */
528 if (GET_CODE (op
) != MEM
)
531 /* dword operations really put out 2 instructions, so eliminate them. */
532 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
535 /* Decode the address now. */
537 switch (GET_CODE (addr
))
546 return SMALL_INT (op
);
549 plus0
= XEXP (addr
, 0);
550 plus1
= XEXP (addr
, 1);
551 if (GET_CODE (plus0
) == REG
552 && GET_CODE (plus1
) == CONST_INT
553 && SMALL_INT (plus1
))
556 else if (GET_CODE (plus1
) == REG
557 && GET_CODE (plus0
) == CONST_INT
558 && SMALL_INT (plus0
))
565 /* We used to allow small symbol refs here (ie, stuff in .sdata
566 or .sbss), but this causes some bugs in G++. Also, it won't
567 interfere if the MIPS linker rewrites the store instruction
568 because the function is PIC. */
570 case LABEL_REF
: /* never gp relative */
574 /* If -G 0, we can never have a GP relative memory operation.
575 Also, save some time if not optimizing. */
580 rtx offset
= const0_rtx
;
581 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
582 if (GET_CODE (op
) != SYMBOL_REF
)
585 /* let's be paranoid.... */
586 if (! SMALL_INT (offset
))
592 return SYMBOL_REF_FLAG (addr
);
599 /* Return true if the code of this rtx pattern is EQ or NE. */
602 equality_op (op
, mode
)
604 enum machine_mode mode
;
606 if (mode
!= GET_MODE (op
))
609 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
612 /* Return true if the code is a relational operations (EQ, LE, etc.) */
617 enum machine_mode mode
;
619 if (mode
!= GET_MODE (op
))
622 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
625 /* Return true if the operand is either the PC or a label_ref. */
628 pc_or_label_operand (op
, mode
)
630 enum machine_mode mode
;
635 if (GET_CODE (op
) == LABEL_REF
)
641 /* Test for a valid operand for a call instruction.
642 Don't allow the arg pointer register or virtual regs
643 since they may change into reg + const, which the patterns
647 call_insn_operand (op
, mode
)
649 enum machine_mode mode
;
651 if (GET_CODE (op
) == MEM
652 && (CONSTANT_ADDRESS_P (XEXP (op
, 0))
653 || (GET_CODE (XEXP (op
, 0)) == REG
654 && XEXP (op
, 0) != arg_pointer_rtx
655 && !(REGNO (XEXP (op
, 0)) >= FIRST_PSEUDO_REGISTER
656 && REGNO (XEXP (op
, 0)) <= LAST_VIRTUAL_REGISTER
))))
661 /* Returns an operand string for the given instruction's delay slot,
662 after updating filled delay slot statistics.
664 We assume that operands[0] is the target register that is set.
666 In order to check the next insn, most of this functionality is moved
667 to FINAL_PRESCAN_INSN, and we just set the global variables that
670 /* ??? This function no longer does anything useful, because final_prescan_insn
671 now will never emit a nop. */
674 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
675 char *ret
; /* normal string to return */
676 enum delay_type type
; /* type of delay */
677 rtx operands
[]; /* operands to use */
678 rtx cur_insn
; /* current insn */
680 register rtx set_reg
;
681 register enum machine_mode mode
;
682 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
683 register int num_nops
;
685 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
688 else if (type
== DELAY_HILO
)
694 /* Make sure that we don't put nop's after labels. */
695 next_insn
= NEXT_INSN (cur_insn
);
696 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
697 next_insn
= NEXT_INSN (next_insn
);
699 dslots_load_total
+= num_nops
;
700 if (TARGET_DEBUG_F_MODE
702 || type
== DELAY_NONE
703 || operands
== (rtx
*)0
704 || cur_insn
== (rtx
)0
705 || next_insn
== (rtx
)0
706 || GET_CODE (next_insn
) == CODE_LABEL
707 || (set_reg
= operands
[0]) == (rtx
)0)
709 dslots_number_nops
= 0;
710 mips_load_reg
= (rtx
)0;
711 mips_load_reg2
= (rtx
)0;
712 mips_load_reg3
= (rtx
)0;
713 mips_load_reg4
= (rtx
)0;
717 set_reg
= operands
[0];
718 if (set_reg
== (rtx
)0)
721 while (GET_CODE (set_reg
) == SUBREG
)
722 set_reg
= SUBREG_REG (set_reg
);
724 mode
= GET_MODE (set_reg
);
725 dslots_number_nops
= num_nops
;
726 mips_load_reg
= set_reg
;
727 if (GET_MODE_SIZE (mode
)
728 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
729 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
733 if (type
== DELAY_HILO
)
735 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
736 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
748 /* Determine whether a memory reference takes one (based off of the GP pointer),
749 two (normal), or three (label + reg) instructions, and bump the appropriate
750 counter for -mstats. */
753 mips_count_memory_refs (op
, num
)
759 rtx addr
, plus0
, plus1
;
760 enum rtx_code code0
, code1
;
763 if (TARGET_DEBUG_B_MODE
)
765 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
769 /* Skip MEM if passed, otherwise handle movsi of address. */
770 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
772 /* Loop, going through the address RTL */
776 switch (GET_CODE (addr
))
786 plus0
= XEXP (addr
, 0);
787 plus1
= XEXP (addr
, 1);
788 code0
= GET_CODE (plus0
);
789 code1
= GET_CODE (plus1
);
799 if (code0
== CONST_INT
)
814 if (code1
== CONST_INT
)
821 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
828 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
838 n_words
= 2; /* always 2 words */
842 addr
= XEXP (addr
, 0);
847 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
856 n_words
+= additional
;
860 num_refs
[n_words
-1] += num
;
864 /* Return RTL for the offset from the current function to the
868 embedded_pic_offset (x
)
871 if (embedded_pic_fnaddr_rtx
== NULL
)
875 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
877 /* Output code at function start to initialize the pseudo-reg. */
878 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
879 inline functions, because it is called after RTL for the function
880 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
881 does not get copied, and ends up not matching the rest of the RTL.
882 This solution works, but means that we get unnecessary code to
883 initialize this value every time a function is inlined into another
886 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
887 XEXP (DECL_RTL (current_function_decl
), 0)));
888 seq
= gen_sequence ();
890 push_topmost_sequence ();
891 emit_insn_after (seq
, get_insns ());
892 pop_topmost_sequence ();
895 return gen_rtx (CONST
, Pmode
,
896 gen_rtx (MINUS
, Pmode
, x
,
897 XEXP (DECL_RTL (current_function_decl
), 0)));
900 /* Return the appropriate instructions to move one operand to another. */
903 mips_move_1word (operands
, insn
, unsignedp
)
909 rtx op0
= operands
[0];
910 rtx op1
= operands
[1];
911 enum rtx_code code0
= GET_CODE (op0
);
912 enum rtx_code code1
= GET_CODE (op1
);
913 enum machine_mode mode
= GET_MODE (op0
);
914 int subreg_word0
= 0;
915 int subreg_word1
= 0;
916 enum delay_type delay
= DELAY_NONE
;
918 while (code0
== SUBREG
)
920 subreg_word0
+= SUBREG_WORD (op0
);
921 op0
= SUBREG_REG (op0
);
922 code0
= GET_CODE (op0
);
925 while (code1
== SUBREG
)
927 subreg_word1
+= SUBREG_WORD (op1
);
928 op1
= SUBREG_REG (op1
);
929 code1
= GET_CODE (op1
);
934 int regno0
= REGNO (op0
) + subreg_word0
;
938 int regno1
= REGNO (op1
) + subreg_word1
;
940 /* Just in case, don't do anything for assigning a register
941 to itself, unless we are filling a delay slot. */
942 if (regno0
== regno1
&& set_nomacro
== 0)
945 else if (GP_REG_P (regno0
))
947 if (GP_REG_P (regno1
))
950 else if (MD_REG_P (regno1
))
953 if (regno1
!= HILO_REGNUM
)
962 if (FP_REG_P (regno1
))
965 else if (regno1
== FPSW_REGNUM
)
966 ret
= "cfc1\t%0,$31";
970 else if (FP_REG_P (regno0
))
972 if (GP_REG_P (regno1
))
978 if (FP_REG_P (regno1
))
979 ret
= "mov.s\t%0,%1";
982 else if (MD_REG_P (regno0
))
984 if (GP_REG_P (regno1
))
987 if (regno0
!= HILO_REGNUM
)
992 else if (regno0
== FPSW_REGNUM
)
994 if (GP_REG_P (regno1
))
997 ret
= "ctc1\t%0,$31";
1002 else if (code1
== MEM
)
1007 mips_count_memory_refs (op1
, 1);
1009 if (GP_REG_P (regno0
))
1011 /* For loads, use the mode of the memory item, instead of the
1012 target, so zero/sign extend can use this code as well. */
1013 switch (GET_MODE (op1
))
1021 ret
= ((unsignedp
&& TARGET_64BIT
)
1026 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1029 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1034 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1037 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1039 int i
= strlen (ret
);
1040 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1043 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1044 ret
= volatile_buffer
;
1048 else if (code1
== CONST_INT
1049 || (code1
== CONST_DOUBLE
1050 && GET_MODE (op1
) == VOIDmode
))
1052 if (code1
== CONST_DOUBLE
)
1054 /* This can happen when storing constants into long long
1055 bitfields. Just store the least significant word of
1057 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1060 if (INTVAL (op1
) == 0)
1062 if (GP_REG_P (regno0
))
1063 ret
= "move\t%0,%z1";
1065 else if (FP_REG_P (regno0
))
1068 ret
= "mtc1\t%z1,%0";
1071 else if (MD_REG_P (regno0
))
1078 else if (GP_REG_P (regno0
))
1079 ret
= (INTVAL (op1
) < 0) ? "li\t%0,%1\t\t\t# %X1" : "li\t%0,%X1\t\t# %1";
1082 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1084 if (op1
== CONST0_RTX (SFmode
))
1086 if (GP_REG_P (regno0
))
1087 ret
= "move\t%0,%.";
1089 else if (FP_REG_P (regno0
))
1092 ret
= "mtc1\t%.,%0";
1099 ret
= "li.s\t%0,%1";
1103 else if (code1
== LABEL_REF
)
1106 mips_count_memory_refs (op1
, 1);
1111 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1113 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1115 rtx offset
= const0_rtx
;
1117 if (GET_CODE (op1
) == CONST
)
1118 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1120 if (GET_CODE (op1
) == SYMBOL_REF
)
1122 operands
[2] = HALF_PIC_PTR (op1
);
1125 mips_count_memory_refs (operands
[2], 1);
1127 if (INTVAL (offset
) == 0)
1130 ret
= (unsignedp
&& TARGET_64BIT
1136 dslots_load_total
++;
1137 operands
[3] = offset
;
1138 if (unsignedp
&& TARGET_64BIT
)
1139 ret
= (SMALL_INT (offset
))
1140 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1141 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1143 ret
= (SMALL_INT (offset
))
1144 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1145 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1152 mips_count_memory_refs (op1
, 1);
1158 else if (code1
== PLUS
)
1160 rtx add_op0
= XEXP (op1
, 0);
1161 rtx add_op1
= XEXP (op1
, 1);
1163 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1165 add_op0
= XEXP (op1
, 1); /* reverse operands */
1166 add_op1
= XEXP (op1
, 0);
1169 operands
[2] = add_op0
;
1170 operands
[3] = add_op1
;
1171 ret
= "add%:\t%0,%2,%3";
1175 else if (code0
== MEM
)
1178 mips_count_memory_refs (op0
, 1);
1182 int regno1
= REGNO (op1
) + subreg_word1
;
1184 if (GP_REG_P (regno1
))
1189 case SFmode
: ret
= "sw\t%1,%0"; break;
1190 case SImode
: ret
= "sw\t%1,%0"; break;
1191 case HImode
: ret
= "sh\t%1,%0"; break;
1192 case QImode
: ret
= "sb\t%1,%0"; break;
1196 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1200 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1205 case SFmode
: ret
= "sw\t%z1,%0"; break;
1206 case SImode
: ret
= "sw\t%z1,%0"; break;
1207 case HImode
: ret
= "sh\t%z1,%0"; break;
1208 case QImode
: ret
= "sb\t%z1,%0"; break;
1212 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1217 case SFmode
: ret
= "sw\t%.,%0"; break;
1218 case SImode
: ret
= "sw\t%.,%0"; break;
1219 case HImode
: ret
= "sh\t%.,%0"; break;
1220 case QImode
: ret
= "sb\t%.,%0"; break;
1224 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1226 int i
= strlen (ret
);
1227 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1230 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1231 ret
= volatile_buffer
;
1235 if (ret
== (char *)0)
1237 abort_with_insn (insn
, "Bad move");
1241 if (delay
!= DELAY_NONE
)
1242 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1248 /* Return the appropriate instructions to move 2 words */
1251 mips_move_2words (operands
, insn
)
1256 rtx op0
= operands
[0];
1257 rtx op1
= operands
[1];
1258 enum rtx_code code0
= GET_CODE (operands
[0]);
1259 enum rtx_code code1
= GET_CODE (operands
[1]);
1260 int subreg_word0
= 0;
1261 int subreg_word1
= 0;
1262 enum delay_type delay
= DELAY_NONE
;
1264 while (code0
== SUBREG
)
1266 subreg_word0
+= SUBREG_WORD (op0
);
1267 op0
= SUBREG_REG (op0
);
1268 code0
= GET_CODE (op0
);
1271 while (code1
== SUBREG
)
1273 subreg_word1
+= SUBREG_WORD (op1
);
1274 op1
= SUBREG_REG (op1
);
1275 code1
= GET_CODE (op1
);
1280 int regno0
= REGNO (op0
) + subreg_word0
;
1284 int regno1
= REGNO (op1
) + subreg_word1
;
1286 /* Just in case, don't do anything for assigning a register
1287 to itself, unless we are filling a delay slot. */
1288 if (regno0
== regno1
&& set_nomacro
== 0)
1291 else if (FP_REG_P (regno0
))
1293 if (FP_REG_P (regno1
))
1294 ret
= "mov.d\t%0,%1";
1302 abort_with_insn (insn
, "Bad move");
1303 #ifdef TARGET_FP_CALL_32
1304 if (FP_CALL_GP_REG_P (regno1
))
1305 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1308 ret
= "dmtc1\t%1,%0";
1311 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1315 else if (FP_REG_P (regno1
))
1321 abort_with_insn (insn
, "Bad move");
1322 #ifdef TARGET_FP_CALL_32
1323 if (FP_CALL_GP_REG_P (regno0
))
1324 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1327 ret
= "dmfc1\t%0,%1";
1330 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1333 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1338 if (regno0
!= HILO_REGNUM
)
1340 else if (regno1
== 0)
1341 ret
= "mtlo\t%.\n\tmthi\t%.";
1344 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1347 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1352 if (regno1
!= HILO_REGNUM
)
1356 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1359 else if (TARGET_64BIT
)
1360 ret
= "move\t%0,%1";
1362 else if (regno0
!= (regno1
+1))
1363 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1366 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1369 else if (code1
== CONST_DOUBLE
)
1371 /* Move zero from $0 unless !TARGET_64BIT and recipient
1372 is 64-bit fp reg, in which case generate a constant. */
1373 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1374 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1376 if (GET_MODE (op1
) == DFmode
)
1379 #ifdef TARGET_FP_CALL_32
1380 if (FP_CALL_GP_REG_P (regno0
))
1382 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1384 split_double (op1
, operands
+ 2, operands
+ 3);
1385 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1388 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1392 ret
= "li.d\t%0,%1";
1395 else if (TARGET_64BIT
)
1400 split_double (op1
, operands
+ 2, operands
+ 3);
1401 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1407 if (GP_REG_P (regno0
))
1409 #ifdef TARGET_FP_CALL_32
1410 && ! FP_CALL_GP_REG_P (regno0
)
1414 : "move\t%0,%.\n\tmove\t%D0,%.";
1416 else if (FP_REG_P (regno0
))
1419 ret
= (TARGET_64BIT
)
1421 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1426 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1428 if (GP_REG_P (regno0
))
1429 ret
= (TARGET_64BIT
)
1431 : "move\t%0,%.\n\tmove\t%D0,%.";
1433 else if (FP_REG_P (regno0
))
1436 ret
= (TARGET_64BIT
)
1440 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1442 else if (MD_REG_P (regno0
))
1445 if (regno0
!= HILO_REGNUM
)
1448 ret
= "mtlo\t%.\n\tmthi\t%.";
1452 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1456 if (HOST_BITS_PER_WIDE_INT
< 64)
1457 /* We can't use 'X' for negative numbers, because then we won't
1458 get the right value for the upper 32 bits. */
1459 ret
= ((INTVAL (op1
) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1460 : "dli\t%0,%X1\t\t# %1");
1462 /* We must use 'X', because otherwise LONG_MIN will print as
1463 a number that the assembler won't accept. */
1464 ret
= "dli\t%0,%X1\t\t# %1";
1468 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1469 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1473 else if (code1
== MEM
)
1478 mips_count_memory_refs (op1
, 2);
1480 if (FP_REG_P (regno0
))
1483 else if (TARGET_64BIT
)
1485 #ifdef TARGET_FP_CALL_32
1486 if (FP_CALL_GP_REG_P (regno0
))
1488 if (offsettable_address_p (FALSE
, SImode
, op1
))
1489 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1491 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1498 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1500 operands
[2] = adj_offsettable_operand (op1
, 4);
1501 if (reg_mentioned_p (op0
, op1
))
1502 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1504 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1507 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1509 int i
= strlen (ret
);
1510 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1513 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1514 ret
= volatile_buffer
;
1518 else if (code1
== LABEL_REF
1519 || code1
== SYMBOL_REF
1523 mips_count_memory_refs (op1
, 2);
1525 ret
= "dla\t%0,%a1";
1529 else if (code0
== MEM
)
1533 int regno1
= REGNO (op1
) + subreg_word1
;
1535 if (FP_REG_P (regno1
))
1538 else if (TARGET_64BIT
)
1540 #ifdef TARGET_FP_CALL_32
1541 if (FP_CALL_GP_REG_P (regno1
))
1542 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1548 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1550 operands
[2] = adj_offsettable_operand (op0
, 4);
1551 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1555 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1556 || (code1
== CONST_DOUBLE
1557 && op1
== CONST0_RTX (GET_MODE (op1
))))
1559 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1565 operands
[2] = adj_offsettable_operand (op0
, 4);
1566 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1571 mips_count_memory_refs (op0
, 2);
1573 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1575 int i
= strlen (ret
);
1576 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1579 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1580 ret
= volatile_buffer
;
1584 if (ret
== (char *)0)
1586 abort_with_insn (insn
, "Bad move");
1590 if (delay
!= DELAY_NONE
)
1591 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1597 /* Provide the costs of an addressing mode that contains ADDR.
1598 If ADDR is not a valid address, its cost is irrelevant. */
1601 mips_address_cost (addr
)
1604 switch (GET_CODE (addr
))
1618 rtx offset
= const0_rtx
;
1619 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1620 if (GET_CODE (addr
) == LABEL_REF
)
1623 if (GET_CODE (addr
) != SYMBOL_REF
)
1626 if (! SMALL_INT (offset
))
1632 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1636 register rtx plus0
= XEXP (addr
, 0);
1637 register rtx plus1
= XEXP (addr
, 1);
1639 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1641 plus0
= XEXP (addr
, 1);
1642 plus1
= XEXP (addr
, 0);
1645 if (GET_CODE (plus0
) != REG
)
1648 switch (GET_CODE (plus1
))
1654 return (SMALL_INT (plus1
) ? 1 : 2);
1661 return mips_address_cost (plus1
) + 1;
1669 /* Return true if X is an address which needs a temporary register when
1670 reloaded while generating PIC code. */
1673 pic_address_needs_scratch (x
)
1676 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1677 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1678 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1679 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1680 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1686 /* Make normal rtx_code into something we can index from an array */
1688 static enum internal_test
1689 map_test_to_internal_test (test_code
)
1690 enum rtx_code test_code
;
1692 enum internal_test test
= ITEST_MAX
;
1697 case EQ
: test
= ITEST_EQ
; break;
1698 case NE
: test
= ITEST_NE
; break;
1699 case GT
: test
= ITEST_GT
; break;
1700 case GE
: test
= ITEST_GE
; break;
1701 case LT
: test
= ITEST_LT
; break;
1702 case LE
: test
= ITEST_LE
; break;
1703 case GTU
: test
= ITEST_GTU
; break;
1704 case GEU
: test
= ITEST_GEU
; break;
1705 case LTU
: test
= ITEST_LTU
; break;
1706 case LEU
: test
= ITEST_LEU
; break;
1713 /* Generate the code to compare two integer values. The return value is:
1714 (reg:SI xx) The pseudo register the comparison is in
1715 (rtx)0 No register, generate a simple branch.
1717 ??? This is called with result nonzero by the Scond patterns in
1718 mips.md. These patterns are called with a target in the mode of
1719 the Scond instruction pattern. Since this must be a constant, we
1720 must use SImode. This means that if RESULT is non-zero, it will
1721 always be an SImode register, even if TARGET_64BIT is true. We
1722 cope with this by calling convert_move rather than emit_move_insn.
1723 This will sometimes lead to an unnecessary extension of the result;
1735 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
1736 enum rtx_code test_code
; /* relational test (EQ, etc) */
1737 rtx result
; /* result to store comp. or 0 if branch */
1738 rtx cmp0
; /* first operand to compare */
1739 rtx cmp1
; /* second operand to compare */
1740 int *p_invert
; /* NULL or ptr to hold whether branch needs */
1741 /* to reverse its test */
1744 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
1745 int const_low
; /* low bound of constant we can accept */
1746 int const_high
; /* high bound of constant we can accept */
1747 int const_add
; /* constant to add (convert LE -> LT) */
1748 int reverse_regs
; /* reverse registers in test */
1749 int invert_const
; /* != 0 if invert value if cmp1 is constant */
1750 int invert_reg
; /* != 0 if invert value if cmp1 is register */
1751 int unsignedp
; /* != 0 for unsigned comparisons. */
1754 static struct cmp_info info
[ (int)ITEST_MAX
] = {
1756 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
1757 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
1758 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
1759 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
1760 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
1761 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
1762 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
1763 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
1764 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
1765 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
1768 enum internal_test test
;
1769 enum machine_mode mode
;
1770 struct cmp_info
*p_info
;
1777 test
= map_test_to_internal_test (test_code
);
1778 if (test
== ITEST_MAX
)
1781 p_info
= &info
[ (int)test
];
1782 eqne_p
= (p_info
->test_code
== XOR
);
1784 mode
= GET_MODE (cmp0
);
1785 if (mode
== VOIDmode
)
1786 mode
= GET_MODE (cmp1
);
1788 /* Eliminate simple branches */
1789 branch_p
= (result
== (rtx
)0);
1792 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
1794 /* Comparisons against zero are simple branches */
1795 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1798 /* Test for beq/bne. */
1803 /* allocate a pseudo to calculate the value in. */
1804 result
= gen_reg_rtx (mode
);
1807 /* Make sure we can handle any constants given to us. */
1808 if (GET_CODE (cmp0
) == CONST_INT
)
1809 cmp0
= force_reg (mode
, cmp0
);
1811 if (GET_CODE (cmp1
) == CONST_INT
)
1813 HOST_WIDE_INT value
= INTVAL (cmp1
);
1814 if (value
< p_info
->const_low
1815 || value
> p_info
->const_high
1816 /* ??? Why? And why wasn't the similar code below modified too? */
1818 && HOST_BITS_PER_WIDE_INT
< 64
1819 && p_info
->const_add
!= 0
1820 && ((p_info
->unsignedp
1821 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
1823 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
1824 != (p_info
->const_add
> 0))))
1825 cmp1
= force_reg (mode
, cmp1
);
1828 /* See if we need to invert the result. */
1829 invert
= (GET_CODE (cmp1
) == CONST_INT
)
1830 ? p_info
->invert_const
1831 : p_info
->invert_reg
;
1833 if (p_invert
!= (int *)0)
1839 /* Comparison to constants, may involve adding 1 to change a LT into LE.
1840 Comparison between two registers, may involve switching operands. */
1841 if (GET_CODE (cmp1
) == CONST_INT
)
1843 if (p_info
->const_add
!= 0)
1845 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
1846 /* If modification of cmp1 caused overflow,
1847 we would get the wrong answer if we follow the usual path;
1848 thus, x > 0xffffffffU would turn into x > 0U. */
1849 if ((p_info
->unsignedp
1850 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
1851 : new > INTVAL (cmp1
))
1852 != (p_info
->const_add
> 0))
1854 /* This test is always true, but if INVERT is true then
1855 the result of the test needs to be inverted so 0 should
1856 be returned instead. */
1857 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
1861 cmp1
= GEN_INT (new);
1864 else if (p_info
->reverse_regs
)
1871 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1875 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
1876 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
1879 if (test
== ITEST_NE
)
1881 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
1885 else if (test
== ITEST_EQ
)
1887 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
1888 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
1893 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
1899 /* Emit the common code for doing conditional branches.
1900 operand[0] is the label to jump to.
1901 The comparison operands are saved away by cmp{si,di,sf,df}. */
1904 gen_conditional_branch (operands
, test_code
)
1906 enum rtx_code test_code
;
1908 static enum machine_mode mode_map
[(int)CMP_MAX
][(int)ITEST_MAX
] = {
1935 CC_REV_FPmode
, /* ne */
1947 CC_REV_FPmode
, /* ne */
1959 enum machine_mode mode
;
1960 enum cmp_type type
= branch_type
;
1961 rtx cmp0
= branch_cmp
[0];
1962 rtx cmp1
= branch_cmp
[1];
1963 rtx label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
1964 rtx label2
= pc_rtx
;
1967 enum internal_test test
= map_test_to_internal_test (test_code
);
1969 if (test
== ITEST_MAX
)
1975 /* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */
1976 mode
= mode_map
[(int)type
][(int)test
];
1977 if (mode
== VOIDmode
)
1987 reg
= gen_int_relational (test_code
, (rtx
)0, cmp0
, cmp1
, &invert
);
1995 /* Make sure not non-zero constant if ==/!= */
1996 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
1997 cmp1
= force_reg (mode
, cmp1
);
2004 rtx reg
= gen_rtx (REG
, mode
, FPSW_REGNUM
);
2005 emit_insn (gen_rtx (SET
, VOIDmode
, reg
, gen_rtx (test_code
, mode
, cmp0
, cmp1
)));
2013 /* Generate the jump */
2020 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
2022 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2023 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
2030 abort_with_insn (gen_rtx (test_code
, mode
, cmp0
, cmp1
), "bad test");
2035 /* Internal code to generate the load and store of one word/short/byte.
2036 The load is emitted directly, and the store insn is returned. */
2038 #define UNITS_PER_MIPS_DWORD 8
2039 #define UNITS_PER_MIPS_WORD 4
2040 #define UNITS_PER_MIPS_HWORD 2
2043 block_move_load_store (dest_reg
, src_reg
, p_bytes
, p_offset
, align
, orig_src
)
2044 rtx src_reg
; /* register holding source memory address */
2045 rtx dest_reg
; /* register holding dest. memory address */
2046 int *p_bytes
; /* pointer to # bytes remaining */
2047 int *p_offset
; /* pointer to current offset */
2048 int align
; /* alignment */
2049 rtx orig_src
; /* original source for making a reg note */
2051 int bytes
; /* # bytes remaining */
2052 int offset
; /* offset to use */
2053 int size
; /* size in bytes of load/store */
2054 enum machine_mode mode
; /* mode to use for load/store */
2055 rtx reg
; /* temporary register */
2056 rtx src_addr
; /* source address */
2057 rtx dest_addr
; /* destination address */
2058 rtx insn
; /* insn of the load */
2059 rtx orig_src_addr
; /* original source address */
2060 rtx (*load_func
)(); /* function to generate load insn */
2061 rtx (*store_func
)(); /* function to generate destination insn */
2064 if (bytes
<= 0 || align
<= 0)
2067 if (bytes
>= UNITS_PER_MIPS_DWORD
&& align
>= UNIS_PER_MIPS_DWORD
)
2070 size
= UNITS_PER_MIPS_DWORD
;
2071 load_func
= gen_movdi
;
2072 store_func
= gen_movdi
;
2074 else if (bytes
>= UNITS_PER_MIPS_WORD
&& align
>= UNITS_PER_MIPS_WORD
)
2077 size
= UNITS_PER_MIPS_WORD
;
2078 load_func
= gen_movsi
;
2079 store_func
= gen_movsi
;
2083 /* Don't generate unaligned moves here, rather defer those to the
2084 general movestrsi_internal pattern.
2085 If this gets commented back in, then should add the dword equivalent. */
2086 else if (bytes
>= UNITS_PER_MIPS_WORD
)
2089 size
= UNITS_PER_MIPS_WORD
;
2090 load_func
= gen_movsi_ulw
;
2091 store_func
= gen_movsi_usw
;
2095 else if (bytes
>= UNITS_PER_MIPS_SHORT
&& align
>= UNITS_PER_MIPS_SHORT
)
2098 size
= UNITS_PER_MIPS_SHORT
;
2099 load_func
= gen_movhi
;
2100 store_func
= gen_movhi
;
2107 load_func
= gen_movqi
;
2108 store_func
= gen_movqi
;
2112 *p_offset
= offset
+ size
;
2113 *p_bytes
= bytes
- size
;
2118 dest_addr
= dest_reg
;
2122 src_addr
= gen_rtx (PLUS
, Pmode
, src_reg
, GEN_INT (offset
));
2123 dest_addr
= gen_rtx (PLUS
, Pmode
, dest_reg
, GEN_INT (offset
));
2126 reg
= gen_reg_rtx (mode
);
2127 insn
= emit_insn ((*load_func
) (reg
, gen_rtx (MEM
, mode
, src_addr
)));
2128 orig_src_addr
= XEXP (orig_src
, 0);
2129 if (CONSTANT_P (orig_src_addr
))
2130 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_EQUIV
,
2131 plus_constant (orig_src_addr
, offset
),
2134 return (*store_func
) (gen_rtx (MEM
, mode
, dest_addr
), reg
);
2139 /* Write a series of loads/stores to move some bytes. Generate load/stores as follows:
2151 This way, no NOP's are needed, except at the end, and only
2152 two temp registers are needed. Two delay slots are used
2153 in deference to the R4000. */
2157 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2158 rtx dest_reg
; /* register holding destination address */
2159 rtx src_reg
; /* register holding source address */
2160 int bytes
; /* # bytes to move */
2161 int align
; /* max alignment to assume */
2162 rtx orig_src
; /* original source for making a reg note */
2165 rtx prev2_store
= (rtx
)0;
2166 rtx prev_store
= (rtx
)0;
2167 rtx cur_store
= (rtx
)0;
2171 /* Is there a store to do? */
2173 emit_insn (prev2_store
);
2175 prev2_store
= prev_store
;
2176 prev_store
= cur_store
;
2177 cur_store
= block_move_load_store (dest_reg
, src_reg
,
2182 /* Finish up last three stores. */
2184 emit_insn (prev2_store
);
2187 emit_insn (prev_store
);
2190 emit_insn (cur_store
);
2195 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2201 temp<last> = src[MAX_MOVE_REGS-1];
2205 dest[MAX_MOVE_REGS-1] = temp<last>;
2206 src += MAX_MOVE_REGS;
2207 dest += MAX_MOVE_REGS;
2208 } while (src != final);
2210 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2211 registers are needed.
2213 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2214 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2215 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2217 #define MAX_MOVE_REGS 4
2218 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2220 /* ??? Should add code to use DWORD load/stores. */
2223 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2224 rtx dest_reg
; /* register holding destination address */
2225 rtx src_reg
; /* register holding source address */
2226 int bytes
; /* # bytes to move */
2227 int align
; /* alignment */
2228 rtx orig_src
; /* original source for making a reg note */
2230 rtx dest_mem
= gen_rtx (MEM
, BLKmode
, dest_reg
);
2231 rtx src_mem
= gen_rtx (MEM
, BLKmode
, src_reg
);
2232 rtx align_rtx
= GEN_INT (align
);
2238 if (bytes
< 2*MAX_MOVE_BYTES
)
2241 leftover
= bytes
% MAX_MOVE_BYTES
;
2244 label
= gen_label_rtx ();
2245 final_src
= gen_reg_rtx (Pmode
);
2246 bytes_rtx
= GEN_INT (bytes
);
2252 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2253 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2257 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2258 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2264 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2266 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2271 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2272 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2275 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2276 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2277 emit_insn (gen_cmpdi (src_reg
, final_src
));
2281 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2282 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2283 emit_insn (gen_cmpsi (src_reg
, final_src
));
2285 emit_jump_insn (gen_bne (label
));
2288 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2294 /* Use a library function to move some bytes. */
2297 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2302 /* We want to pass the size as Pmode, which will normally be SImode
2303 but will be DImode if we are using 64 bit longs and pointers. */
2304 if (GET_MODE (bytes_rtx
) != VOIDmode
2305 && GET_MODE (bytes_rtx
) != Pmode
)
2306 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2308 #ifdef TARGET_MEM_FUNCTIONS
2309 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2313 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2314 TREE_UNSIGNED (sizetype
)),
2315 TYPE_MODE (sizetype
));
2317 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2321 convert_to_modfe (TYPE_MODE (integer_type_node
),
2323 TREE_UNSIGNED (integer_type_node
)),
2324 TYPE_MODE (integer_type_node
));
2329 /* Expand string/block move operations.
2331 operands[0] is the pointer to the destination.
2332 operands[1] is the pointer to the source.
2333 operands[2] is the number of bytes to move.
2334 operands[3] is the alignment. */
2337 expand_block_move (operands
)
2340 rtx bytes_rtx
= operands
[2];
2341 rtx align_rtx
= operands
[3];
2342 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2343 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2344 int align
= INTVAL (align_rtx
);
2345 rtx orig_src
= operands
[1];
2349 if (constp
&& bytes
<= 0)
2352 if (align
> UNITS_PER_WORD
)
2353 align
= UNITS_PER_WORD
;
2355 /* Move the address into scratch registers. */
2356 dest_reg
= copy_addr_to_reg (XEXP (operands
[0], 0));
2357 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2360 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2363 else if (constp
&& bytes
<= 3*align
)
2364 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2367 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2368 emit_insn (gen_movstrsi_internal (change_address (operands
[0],
2370 change_address (orig_src
, BLKmode
,
2372 bytes_rtx
, align_rtx
));
2374 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2375 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2377 else if (constp
&& optimize
)
2379 /* If the alignment is not word aligned, generate a test at
2380 runtime, to see whether things wound up aligned, and we
2381 can use the faster lw/sw instead ulw/usw. */
2383 rtx temp
= gen_reg_rtx (Pmode
);
2384 rtx aligned_label
= gen_label_rtx ();
2385 rtx join_label
= gen_label_rtx ();
2386 int leftover
= bytes
% MAX_MOVE_BYTES
;
2392 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2393 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2394 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2398 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2399 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2400 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2402 emit_jump_insn (gen_beq (aligned_label
));
2404 /* Unaligned loop. */
2405 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_src
);
2406 emit_jump_insn (gen_jump (join_label
));
2410 emit_label (aligned_label
);
2411 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_src
);
2412 emit_label (join_label
);
2414 /* Bytes at the end of the loop. */
2418 if (leftover
<= 3*align
)
2419 block_move_sequence (dest_reg
, src_reg
, leftover
, align
, orig_src
);
2423 emit_insn (gen_movstrsi_internal (gen_rtx (MEM
, BLKmode
, dest_reg
),
2424 gen_rtx (MEM
, BLKmode
, src_reg
),
2431 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2435 /* Emit load/stores for a small constant block_move.
2437 operands[0] is the memory address of the destination.
2438 operands[1] is the memory address of the source.
2439 operands[2] is the number of bytes to move.
2440 operands[3] is the alignment.
2441 operands[4] is a temp register.
2442 operands[5] is a temp register.
2444 operands[3+num_regs] is the last temp register.
2446 The block move type can be one of the following:
2447 BLOCK_MOVE_NORMAL Do all of the block move.
2448 BLOCK_MOVE_NOT_LAST Do all but the last store.
2449 BLOCK_MOVE_LAST Do just the last store. */
2452 output_block_move (insn
, operands
, num_regs
, move_type
)
2456 enum block_move_type move_type
;
2458 rtx dest_reg
= XEXP (operands
[0], 0);
2459 rtx src_reg
= XEXP (operands
[1], 0);
2460 int bytes
= INTVAL (operands
[2]);
2461 int align
= INTVAL (operands
[3]);
2464 int use_lwl_lwr
= FALSE
;
2465 int last_operand
= num_regs
+4;
2471 char *load
; /* load insn without nop */
2472 char *load_nop
; /* load insn with trailing nop */
2473 char *store
; /* store insn */
2474 char *final
; /* if last_store used: NULL or swr */
2475 char *last_store
; /* last store instruction */
2476 int offset
; /* current offset */
2477 enum machine_mode mode
; /* mode to use on (MEM) */
2480 /* Detect a bug in GCC, where it can give us a register
2481 the same as one of the addressing registers and reduce
2482 the number of registers available. */
2484 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2487 if (!reg_mentioned_p (operands
[i
], operands
[0])
2488 && !reg_mentioned_p (operands
[i
], operands
[1]))
2490 xoperands
[safe_regs
++] = operands
[i
];
2493 if (safe_regs
< last_operand
)
2495 xoperands
[0] = operands
[0];
2496 xoperands
[1] = operands
[1];
2497 xoperands
[2] = operands
[2];
2498 xoperands
[3] = operands
[3];
2499 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2502 /* If we are given global or static addresses, and we would be
2503 emitting a few instructions, try to save time by using a
2504 temporary register for the pointer. */
2505 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
))
2507 if (CONSTANT_P (src_reg
))
2510 mips_count_memory_refs (operands
[1], 1);
2512 src_reg
= operands
[ 3 + num_regs
-- ];
2513 if (move_type
!= BLOCK_MOVE_LAST
)
2515 xoperands
[1] = operands
[1];
2516 xoperands
[0] = src_reg
;
2517 if (Pmode
== DImode
)
2518 output_asm_insn ("dla\t%0,%1", xoperands
);
2520 output_asm_insn ("la\t%0,%1", xoperands
);
2524 if (CONSTANT_P (dest_reg
))
2527 mips_count_memory_refs (operands
[0], 1);
2529 dest_reg
= operands
[ 3 + num_regs
-- ];
2530 if (move_type
!= BLOCK_MOVE_LAST
)
2532 xoperands
[1] = operands
[0];
2533 xoperands
[0] = dest_reg
;
2534 if (Pmode
== DImode
)
2535 output_asm_insn ("dla\t%0,%1", xoperands
);
2537 output_asm_insn ("la\t%0,%1", xoperands
);
2542 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2543 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2545 else if (num_regs
< 1)
2546 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2550 load_store
[num
].offset
= offset
;
2552 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2554 load_store
[num
].load
= "ld\t%0,%1";
2555 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2556 load_store
[num
].store
= "sd\t%0,%1";
2557 load_store
[num
].last_store
= "sd\t%0,%1";
2558 load_store
[num
].final
= (char *)0;
2559 load_store
[num
].mode
= DImode
;
2564 /* ??? Fails because of a MIPS assembler bug? */
2565 else if (TARGET_64BIT
&& bytes
>= 8)
2567 if (BYTES_BIG_ENDIAN
)
2569 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2570 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2571 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2572 load_store
[num
].last_store
= "sdr\t%0,%2";
2573 load_store
[num
].final
= "sdl\t%0,%1";
2577 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2578 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2579 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2580 load_store
[num
].last_store
= "sdr\t%0,%1";
2581 load_store
[num
].final
= "sdl\t%0,%2";
2583 load_store
[num
].mode
= DImode
;
2589 else if (bytes
>= 4 && align
>= 4)
2591 load_store
[num
].load
= "lw\t%0,%1";
2592 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2593 load_store
[num
].store
= "sw\t%0,%1";
2594 load_store
[num
].last_store
= "sw\t%0,%1";
2595 load_store
[num
].final
= (char *)0;
2596 load_store
[num
].mode
= SImode
;
2601 else if (bytes
>= 4)
2603 if (BYTES_BIG_ENDIAN
)
2605 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2606 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2607 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2608 load_store
[num
].last_store
= "swr\t%0,%2";
2609 load_store
[num
].final
= "swl\t%0,%1";
2613 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2614 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2615 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2616 load_store
[num
].last_store
= "swr\t%0,%1";
2617 load_store
[num
].final
= "swl\t%0,%2";
2619 load_store
[num
].mode
= SImode
;
2625 else if (bytes
>= 2 && align
>= 2)
2627 load_store
[num
].load
= "lh\t%0,%1";
2628 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2629 load_store
[num
].store
= "sh\t%0,%1";
2630 load_store
[num
].last_store
= "sh\t%0,%1";
2631 load_store
[num
].final
= (char *)0;
2632 load_store
[num
].mode
= HImode
;
2639 load_store
[num
].load
= "lb\t%0,%1";
2640 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2641 load_store
[num
].store
= "sb\t%0,%1";
2642 load_store
[num
].last_store
= "sb\t%0,%1";
2643 load_store
[num
].final
= (char *)0;
2644 load_store
[num
].mode
= QImode
;
2649 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2651 dslots_load_total
++;
2652 dslots_load_filled
++;
2654 if (CONSTANT_P (src_reg
))
2655 mips_count_memory_refs (src_reg
, 1);
2657 if (CONSTANT_P (dest_reg
))
2658 mips_count_memory_refs (dest_reg
, 1);
2661 /* Emit load/stores now if we have run out of registers or are
2662 at the end of the move. */
2664 if (++num
== num_regs
|| bytes
== 0)
2666 /* If only load/store, we need a NOP after the load. */
2669 load_store
[0].load
= load_store
[0].load_nop
;
2670 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2671 dslots_load_filled
--;
2674 if (move_type
!= BLOCK_MOVE_LAST
)
2676 for (i
= 0; i
< num
; i
++)
2683 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2684 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2686 offset
= load_store
[i
].offset
;
2687 xoperands
[0] = operands
[i
+4];
2688 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2689 plus_constant (src_reg
, offset
));
2694 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2695 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2696 plus_constant (src_reg
,
2701 output_asm_insn (load_store
[i
].load
, xoperands
);
2705 for (i
= 0; i
< num
; i
++)
2707 int last_p
= (i
== num
-1 && bytes
== 0);
2708 int offset
= load_store
[i
].offset
;
2710 xoperands
[0] = operands
[i
+4];
2711 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2712 plus_constant (dest_reg
, offset
));
2718 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2719 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2720 plus_constant (dest_reg
,
2725 if (move_type
== BLOCK_MOVE_NORMAL
)
2726 output_asm_insn (load_store
[i
].store
, xoperands
);
2728 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2731 output_asm_insn (load_store
[i
].store
, xoperands
);
2733 else if (load_store
[i
].final
!= (char *)0)
2734 output_asm_insn (load_store
[i
].final
, xoperands
);
2738 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2741 num
= 0; /* reset load_store */
2742 use_lwl_lwr
= FALSE
;
2750 /* Argument support functions. */
2752 /* Initialize CUMULATIVE_ARGS for a function. */
2755 init_cumulative_args (cum
, fntype
, libname
)
2756 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2757 tree fntype
; /* tree ptr for function decl */
2758 rtx libname
; /* SYMBOL_REF of library name or 0 */
2760 static CUMULATIVE_ARGS zero_cum
;
2761 tree param
, next_param
;
2763 if (TARGET_DEBUG_E_MODE
)
2765 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2767 fputc ('\n', stderr
);
2771 tree ret_type
= TREE_TYPE (fntype
);
2772 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2773 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2774 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2780 /* Determine if this function has variable arguments. This is
2781 indicated by the last argument being 'void_type_mode' if there
2782 are no variable arguments. The standard MIPS calling sequence
2783 passes all arguments in the general purpose registers in this
2786 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
2790 next_param
= TREE_CHAIN (param
);
2791 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
2792 cum
->gp_reg_found
= 1;
2796 /* Advance the argument to the next argument position. */
2799 function_arg_advance (cum
, mode
, type
, named
)
2800 CUMULATIVE_ARGS
*cum
; /* current arg information */
2801 enum machine_mode mode
; /* current arg mode */
2802 tree type
; /* type of the argument or 0 if lib support */
2803 int named
; /* whether or not the argument was named */
2805 if (TARGET_DEBUG_E_MODE
)
2807 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
2808 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
2818 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
2819 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
2821 cum
->gp_reg_found
= 1;
2822 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
2827 cum
->gp_reg_found
= 1;
2828 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
2837 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
2841 cum
->gp_reg_found
= 1;
2842 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
2848 cum
->gp_reg_found
= 1;
2854 /* Return an RTL expression containing the register for the given mode,
2855 or 0 if the argument is to be passed on the stack. */
2858 function_arg (cum
, mode
, type
, named
)
2859 CUMULATIVE_ARGS
*cum
; /* current arg information */
2860 enum machine_mode mode
; /* current arg mode */
2861 tree type
; /* type of the argument or 0 if lib support */
2862 int named
; /* != 0 for normal args, == 0 for ... args */
2867 int struct_p
= ((type
!= (tree
)0)
2868 && (TREE_CODE (type
) == RECORD_TYPE
2869 || TREE_CODE (type
) == UNION_TYPE
));
2871 if (TARGET_DEBUG_E_MODE
)
2873 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
2874 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
2880 if (! ABI_64BIT
|| mips_isa
< 3)
2882 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
2883 regbase
= GP_ARG_FIRST
;
2886 regbase
= FP_ARG_FIRST
;
2887 /* If the first arg was a float in a floating point register,
2888 then set bias to align this float arg properly. */
2889 if (cum
->arg_words
== 1)
2894 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
2899 cum
->arg_words
+= (cum
->arg_words
& 1);
2900 if (! ABI_64BIT
|| mips_isa
< 3)
2901 regbase
= ((cum
->gp_reg_found
2902 || TARGET_SOFT_FLOAT
2903 || TARGET_SINGLE_FLOAT
2904 || cum
->arg_number
>= 2)
2908 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
2909 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
2913 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
2914 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
2917 /* Drops through. */
2919 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
2921 cum
->arg_words
+= (cum
->arg_words
& 1);
2923 regbase
= GP_ARG_FIRST
;
2930 regbase
= GP_ARG_FIRST
;
2935 cum
->arg_words
+= (cum
->arg_words
& 1);
2936 regbase
= GP_ARG_FIRST
;
2939 if (cum
->arg_words
>= MAX_ARGS_IN_REGISTERS
)
2941 if (TARGET_DEBUG_E_MODE
)
2942 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
2951 ret
= gen_rtx (REG
, mode
, regbase
+ cum
->arg_words
+ bias
);
2953 if (TARGET_DEBUG_E_MODE
)
2954 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ cum
->arg_words
+ bias
],
2955 struct_p
? ", [struct]" : "");
2957 /* The following is a hack in order to pass 1 byte structures
2958 the same way that the MIPS compiler does (namely by passing
2959 the structure in the high byte or half word of the register).
2960 This also makes varargs work. If we have such a structure,
2961 we save the adjustment RTL, and the call define expands will
2962 emit them. For the VOIDmode argument (argument after the
2963 last real argument), pass back a parallel vector holding each
2964 of the adjustments. */
2966 /* ??? function_arg can be called more than once for each argument.
2967 As a result, we compute more adjustments than we need here.
2968 See the CUMULATIVE_ARGS definition in mips.h. */
2970 /* ??? This scheme requires everything smaller than the word size to
2971 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
2972 that would mean every int needs to be shifted left, which is very
2973 inefficient. Let's not carry this compatibility to the 64 bit
2974 calling convention for now. */
2976 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
2979 rtx amount
= GEN_INT (BITS_PER_WORD
2980 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
2981 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ cum
->arg_words
+ bias
);
2983 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
2985 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
2989 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
2990 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
2997 function_arg_partial_nregs (cum
, mode
, type
, named
)
2998 CUMULATIVE_ARGS
*cum
; /* current arg information */
2999 enum machine_mode mode
; /* current arg mode */
3000 tree type
; /* type of the argument or 0 if lib support */
3001 int named
; /* != 0 for normal args, == 0 for ... args */
3003 if ((mode
== BLKmode
3004 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3005 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3006 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
)
3009 if (mode
== BLKmode
)
3010 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3013 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3015 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3016 return 0; /* structure fits in registers */
3018 if (TARGET_DEBUG_E_MODE
)
3019 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3020 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3022 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3025 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3028 if (TARGET_DEBUG_E_MODE
)
3029 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3038 /* Print the options used in the assembly file. */
3040 static struct {char *name
; int value
;} target_switches
[]
3051 int mask
= TARGET_DEFAULT
;
3053 /* Allow assembly language comparisons with -mdebug eliminating the
3054 compiler version number and switch lists. */
3056 if (TARGET_DEBUG_MODE
)
3059 fprintf (out
, "\n # %s %s", language_string
, version_string
);
3060 #ifdef TARGET_VERSION_INTERNAL
3061 TARGET_VERSION_INTERNAL (out
);
3064 fprintf (out
, " compiled by GNU C\n\n");
3066 fprintf (out
, " compiled by CC\n\n");
3069 fprintf (out
, " # Cc1 defaults:");
3071 for (j
= 0; j
< sizeof target_switches
/ sizeof target_switches
[0]; j
++)
3073 if (target_switches
[j
].name
[0] != '\0'
3074 && target_switches
[j
].value
> 0
3075 && (target_switches
[j
].value
& mask
) == target_switches
[j
].value
)
3077 mask
&= ~ target_switches
[j
].value
;
3078 len
= strlen (target_switches
[j
].name
) + 1;
3079 if (len
+ line_len
> 79)
3082 fputs ("\n #", out
);
3084 fprintf (out
, " -m%s", target_switches
[j
].name
);
3089 fprintf (out
, "\n\n # Cc1 arguments (-G value = %d, Cpu = %s, ISA = %d):",
3090 mips_section_threshold
, mips_cpu_string
, mips_isa
);
3093 for (p
= &save_argv
[1]; *p
!= (char *)0; p
++)
3098 len
= strlen (arg
) + 1;
3099 if (len
+ line_len
> 79)
3102 fputs ("\n #", out
);
3104 fprintf (out
, " %s", *p
);
3109 fputs ("\n\n", out
);
3113 /* Abort after printing out a specific insn. */
3116 abort_with_insn (insn
, reason
)
3125 /* Write a message to stderr (for use in macros expanded in files that do not
3126 include stdio.h). */
3132 fprintf (stderr
, s
, s1
, s2
);
3142 fprintf (stderr
, "compiling '%s' in '%s'\n",
3143 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3144 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3147 #endif /* SIGINFO */
3150 /* Set up the threshold for data to go into the small data area, instead
3151 of the normal data area, and detect any conflicts in the switches. */
3156 register int i
, start
;
3158 register enum machine_mode mode
;
3160 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3162 if (mips_section_threshold
<= 0)
3163 target_flags
&= ~MASK_GPOPT
;
3165 target_flags
|= MASK_GPOPT
;
3167 /* Get the architectural level. */
3168 if (mips_isa_string
== (char *)0)
3170 #ifdef MIPS_ISA_DEFAULT
3171 mips_isa
= MIPS_ISA_DEFAULT
;
3177 else if (isdigit (*mips_isa_string
))
3179 mips_isa
= atoi (mips_isa_string
);
3180 if (mips_isa
< 1 || mips_isa
> 4)
3182 error ("-mips%d not supported", mips_isa
);
3189 error ("bad value (%s) for -mips switch", mips_isa_string
);
3193 #ifdef MIPS_CPU_STRING_DEFAULT
3194 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3195 greater than that supported by the default processor, then the user gets
3196 an error. Normally, the compiler will just default to the base level cpu
3197 for the indicated isa. */
3198 if (mips_cpu_string
== (char *)0)
3199 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3202 /* Identify the processor type */
3203 if (mips_cpu_string
== (char *)0
3204 || !strcmp (mips_cpu_string
, "default")
3205 || !strcmp (mips_cpu_string
, "DEFAULT"))
3210 mips_cpu_string
= "3000";
3211 mips_cpu
= PROCESSOR_R3000
;
3214 mips_cpu_string
= "6000";
3215 mips_cpu
= PROCESSOR_R6000
;
3218 mips_cpu_string
= "4000";
3219 mips_cpu
= PROCESSOR_R4000
;
3222 mips_cpu_string
= "8000";
3223 mips_cpu
= PROCESSOR_R8000
;
3230 char *p
= mips_cpu_string
;
3232 if (*p
== 'r' || *p
== 'R')
3235 /* Since there is no difference between a R2000 and R3000 in
3236 terms of the scheduler, we collapse them into just an R3000. */
3238 mips_cpu
= PROCESSOR_DEFAULT
;
3242 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3243 mips_cpu
= PROCESSOR_R3000
;
3247 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3248 mips_cpu
= PROCESSOR_R3000
;
3252 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3253 mips_cpu
= PROCESSOR_R4000
;
3254 /* The r4400 is exactly the same as the r4000 from the compiler's
3256 else if (!strcmp (p
, "4400"))
3257 mips_cpu
= PROCESSOR_R4000
;
3258 else if (!strcmp (p
, "4600"))
3259 mips_cpu
= PROCESSOR_R4600
;
3260 else if (!strcmp (p
, "4650"))
3261 mips_cpu
= PROCESSOR_R4650
;
3265 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3266 mips_cpu
= PROCESSOR_R6000
;
3270 if (!strcmp (p
, "8000"))
3271 mips_cpu
= PROCESSOR_R8000
;
3275 if (!strcmp (p
, "orion"))
3276 mips_cpu
= PROCESSOR_R4600
;
3280 if (mips_cpu
== PROCESSOR_DEFAULT
)
3282 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3283 mips_cpu_string
= "default";
3287 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3288 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3289 || ((mips_cpu
== PROCESSOR_R4000
3290 || mips_cpu
== PROCESSOR_R4600
3291 || mips_cpu
== PROCESSOR_R4650
)
3293 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3295 /* make sure sizes of ints/longs/etc. are ok */
3299 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3301 else if (TARGET_LONG64
)
3302 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3304 else if (TARGET_FLOAT64
)
3305 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3307 else if (TARGET_64BIT
)
3308 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3311 if (ABI_64BIT
&& mips_isa
>= 3)
3312 flag_pcc_struct_return
= 0;
3314 /* Tell halfpic.c that we have half-pic code if we do. */
3315 if (TARGET_HALF_PIC
)
3318 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3319 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3320 /* ??? -non_shared turns off pic code generation, but this is not
3322 if (TARGET_ABICALLS
)
3324 mips_abicalls
= MIPS_ABICALLS_YES
;
3326 if (mips_section_threshold
> 0)
3327 warning ("-G is incompatible with PIC code which is the default");
3330 mips_abicalls
= MIPS_ABICALLS_NO
;
3332 /* -membedded-pic is a form of PIC code suitable for embedded
3333 systems. All calls are made using PC relative addressing, and
3334 all data is addressed using the $gp register. This requires gas,
3335 which does most of the work, and GNU ld, which automatically
3336 expands PC relative calls which are out of range into a longer
3337 instruction sequence. All gcc really does differently is
3338 generate a different sequence for a switch. */
3339 if (TARGET_EMBEDDED_PIC
)
3342 if (TARGET_ABICALLS
)
3343 warning ("-membedded-pic and -mabicalls are incompatible");
3345 warning ("-G and -membedded-pic are incompatible");
3346 /* Setting mips_section_threshold is not required, because gas
3347 will force everything to be GP addressable anyhow, but
3348 setting it will cause gcc to make better estimates of the
3349 number of instructions required to access a particular data
3351 mips_section_threshold
= 0x7fffffff;
3354 /* -mrnames says to use the MIPS software convention for register
3355 names instead of the hardware names (ie, $a0 instead of $4).
3356 We do this by switching the names in mips_reg_names, which the
3357 reg_names points into via the REGISTER_NAMES macro. */
3359 if (TARGET_NAME_REGS
)
3360 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3362 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3363 is currently being compiled. */
3365 if (getenv ("GCC_SIGINFO") != (char *)0)
3367 struct sigaction action
;
3368 action
.sa_handler
= siginfo
;
3370 action
.sa_flags
= SA_RESTART
;
3371 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3376 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3377 /* If -mstats and -quiet, make stderr line buffered. */
3378 if (quiet_flag
&& TARGET_STATS
)
3379 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3383 /* Initialize the high and low values for legitimate floating point
3384 constants. Rather than trying to get the accuracy down to the
3385 last bit, just use approximate ranges. */
3386 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3387 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3388 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3389 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3391 mips_print_operand_punct
['?'] = TRUE
;
3392 mips_print_operand_punct
['#'] = TRUE
;
3393 mips_print_operand_punct
['&'] = TRUE
;
3394 mips_print_operand_punct
['!'] = TRUE
;
3395 mips_print_operand_punct
['*'] = TRUE
;
3396 mips_print_operand_punct
['@'] = TRUE
;
3397 mips_print_operand_punct
['.'] = TRUE
;
3398 mips_print_operand_punct
['('] = TRUE
;
3399 mips_print_operand_punct
[')'] = TRUE
;
3400 mips_print_operand_punct
['['] = TRUE
;
3401 mips_print_operand_punct
[']'] = TRUE
;
3402 mips_print_operand_punct
['<'] = TRUE
;
3403 mips_print_operand_punct
['>'] = TRUE
;
3404 mips_print_operand_punct
['{'] = TRUE
;
3405 mips_print_operand_punct
['}'] = TRUE
;
3406 mips_print_operand_punct
['^'] = TRUE
;
3408 mips_char_to_class
['d'] = GR_REGS
;
3409 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3410 mips_char_to_class
['h'] = HI_REG
;
3411 mips_char_to_class
['l'] = LO_REG
;
3412 mips_char_to_class
['a'] = HILO_REG
;
3413 mips_char_to_class
['x'] = MD_REGS
;
3414 mips_char_to_class
['b'] = ALL_REGS
;
3415 mips_char_to_class
['y'] = GR_REGS
;
3416 mips_char_to_class
['z'] = ST_REGS
;
3418 /* Set up array to map GCC register number to debug register number.
3419 Ignore the special purpose register numbers. */
3421 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3422 mips_dbx_regno
[i
] = -1;
3424 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3425 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3426 mips_dbx_regno
[i
] = i
+ start
;
3428 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3429 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3430 mips_dbx_regno
[i
] = i
+ start
;
3432 /* Set up array giving whether a given register can hold a given mode.
3433 At present, restrict ints from being in FP registers, because reload
3434 is a little enthusiastic about storing extra values in FP registers,
3435 and this is not good for things like OS kernels. Also, due to the
3436 mandatory delay, it is as fast to load from cached memory as to move
3437 from the FP register. */
3439 for (mode
= VOIDmode
;
3440 mode
!= MAX_MACHINE_MODE
;
3441 mode
= (enum machine_mode
)((int)mode
+ 1))
3443 register int size
= GET_MODE_SIZE (mode
);
3444 register enum mode_class
class = GET_MODE_CLASS (mode
);
3446 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3450 if (mode
== CC_FPmode
|| mode
== CC_REV_FPmode
)
3451 temp
= (regno
== FPSW_REGNUM
);
3453 else if (GP_REG_P (regno
))
3454 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3456 else if (FP_REG_P (regno
))
3457 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3458 && (class == MODE_FLOAT
3459 || class == MODE_COMPLEX_FLOAT
3460 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3461 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3463 else if (MD_REG_P (regno
))
3464 temp
= (class == MODE_INT
3465 && (size
<= UNITS_PER_WORD
3466 || (regno
== MD_REG_FIRST
&& size
== 2 * UNITS_PER_WORD
)));
3471 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3478 * The MIPS debug format wants all automatic variables and arguments
3479 * to be in terms of the virtual frame pointer (stack pointer before
3480 * any adjustment in the function), while the MIPS 3.0 linker wants
3481 * the frame pointer to be the stack pointer after the initial
3482 * adjustment. So, we do the adjustment here. The arg pointer (which
3483 * is eliminated) points to the virtual frame pointer, while the frame
3484 * pointer (which may be eliminated) points to the stack pointer after
3485 * the initial adjustments.
3489 mips_debugger_offset (addr
, offset
)
3493 rtx offset2
= const0_rtx
;
3494 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3497 offset
= INTVAL (offset2
);
3499 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3501 int frame_size
= (!current_frame_info
.initialized
)
3502 ? compute_frame_size (get_frame_size ())
3503 : current_frame_info
.total_size
;
3505 offset
= offset
- frame_size
;
3507 /* sdbout_parms does not want this to crash for unrecognized cases. */
3509 else if (reg
!= arg_pointer_rtx
)
3510 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3517 /* A C compound statement to output to stdio stream STREAM the
3518 assembler syntax for an instruction operand X. X is an RTL
3521 CODE is a value that can be used to specify one of several ways
3522 of printing the operand. It is used when identical operands
3523 must be printed differently depending on the context. CODE
3524 comes from the `%' specification that was used to request
3525 printing of the operand. If the specification was just `%DIGIT'
3526 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3527 is the ASCII code for LTR.
3529 If X is a register, this macro should print the register's name.
3530 The names can be found in an array `reg_names' whose type is
3531 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3533 When the machine description has a specification `%PUNCT' (a `%'
3534 followed by a punctuation character), this macro is called with
3535 a null pointer for X and the punctuation character for CODE.
3537 The MIPS specific codes are:
3539 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3540 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3541 'd' output integer constant in decimal,
3542 'z' if the operand is 0, use $0 instead of normal operand.
3543 'D' print second register of double-word register operand.
3544 'L' print low-order register of double-word register operand.
3545 'M' print high-order register of double-word register operand.
3546 'C' print part of opcode for a branch condition.
3547 'N' print part of opcode for a branch condition, inverted.
3548 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3549 'B' print 'z' for EQ, 'n' for NE
3550 'b' print 'n' for EQ, 'z' for NE
3551 'T' print 'f' for EQ, 't' for NE
3552 't' print 't' for EQ, 'f' for NE
3553 '(' Turn on .set noreorder
3554 ')' Turn on .set reorder
3555 '[' Turn on .set noat
3557 '<' Turn on .set nomacro
3558 '>' Turn on .set macro
3559 '{' Turn on .set volatile (not GAS)
3560 '}' Turn on .set novolatile (not GAS)
3561 '&' Turn on .set noreorder if filling delay slots
3562 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3563 '!' Turn on .set nomacro if filling delay slots
3564 '#' Print nop if in a .set noreorder section.
3565 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3566 '@' Print the name of the assembler temporary register (at or $1).
3567 '.' Print the name of the register with a hard-wired zero (zero or $0).
3568 '^' Print the name of the pic call-through register (t9 or $25). */
3571 print_operand (file
, op
, letter
)
3572 FILE *file
; /* file to write to */
3573 rtx op
; /* operand to print */
3574 int letter
; /* %<letter> or 0 */
3576 register enum rtx_code code
;
3578 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3583 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3587 if (mips_branch_likely
)
3592 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3596 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3600 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3604 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3605 fputs (".set\tnoreorder\n\t", file
);
3609 if (final_sequence
!= 0)
3611 if (set_noreorder
++ == 0)
3612 fputs (".set\tnoreorder\n\t", file
);
3614 if (set_nomacro
++ == 0)
3615 fputs (".set\tnomacro\n\t", file
);
3620 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3621 fputs ("\n\t.set\tnomacro", file
);
3625 if (set_noreorder
!= 0)
3626 fputs ("\n\tnop", file
);
3628 else if (TARGET_STATS
)
3629 fputs ("\n\t#nop", file
);
3634 if (set_noreorder
++ == 0)
3635 fputs (".set\tnoreorder\n\t", file
);
3639 if (set_noreorder
== 0)
3640 error ("internal error: %%) found without a %%( in assembler pattern");
3642 else if (--set_noreorder
== 0)
3643 fputs ("\n\t.set\treorder", file
);
3648 if (set_noat
++ == 0)
3649 fputs (".set\tnoat\n\t", file
);
3654 error ("internal error: %%] found without a %%[ in assembler pattern");
3656 else if (--set_noat
== 0)
3657 fputs ("\n\t.set\tat", file
);
3662 if (set_nomacro
++ == 0)
3663 fputs (".set\tnomacro\n\t", file
);
3667 if (set_nomacro
== 0)
3668 error ("internal error: %%> found without a %%< in assembler pattern");
3670 else if (--set_nomacro
== 0)
3671 fputs ("\n\t.set\tmacro", file
);
3676 if (set_volatile
++ == 0)
3677 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
3681 if (set_volatile
== 0)
3682 error ("internal error: %%} found without a %%{ in assembler pattern");
3684 else if (--set_volatile
== 0)
3685 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
3694 error ("PRINT_OPERAND null pointer");
3698 code
= GET_CODE (op
);
3702 case EQ
: fputs ("eq", file
); break;
3703 case NE
: fputs ("ne", file
); break;
3704 case GT
: fputs ("gt", file
); break;
3705 case GE
: fputs ("ge", file
); break;
3706 case LT
: fputs ("lt", file
); break;
3707 case LE
: fputs ("le", file
); break;
3708 case GTU
: fputs ("gtu", file
); break;
3709 case GEU
: fputs ("geu", file
); break;
3710 case LTU
: fputs ("ltu", file
); break;
3711 case LEU
: fputs ("leu", file
); break;
3714 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
3717 else if (letter
== 'N')
3720 case EQ
: fputs ("ne", file
); break;
3721 case NE
: fputs ("eq", file
); break;
3722 case GT
: fputs ("le", file
); break;
3723 case GE
: fputs ("lt", file
); break;
3724 case LT
: fputs ("ge", file
); break;
3725 case LE
: fputs ("gt", file
); break;
3726 case GTU
: fputs ("leu", file
); break;
3727 case GEU
: fputs ("ltu", file
); break;
3728 case LTU
: fputs ("geu", file
); break;
3729 case LEU
: fputs ("gtu", file
); break;
3732 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
3735 else if (letter
== 'S')
3739 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
3740 assemble_name (file
, buffer
);
3743 else if (code
== REG
)
3745 register int regnum
= REGNO (op
);
3747 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
3748 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
3752 fprintf (file
, "%s", reg_names
[regnum
]);
3755 else if (code
== MEM
)
3756 output_address (XEXP (op
, 0));
3758 else if (code
== CONST_DOUBLE
3759 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
3764 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
3765 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
3769 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
3770 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
3772 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
3773 && HOST_BITS_PER_WIDE_INT
== 32)
3774 fprintf (file
, "0x%08x", INTVAL(op
));
3776 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
3777 && HOST_BITS_PER_WIDE_INT
== 64)
3778 fprintf (file
, "0x%016lx", INTVAL(op
));
3780 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
3781 fprintf (file
, "%d", (INTVAL(op
)));
3783 else if (letter
== 'z'
3784 && (GET_CODE (op
) == CONST_INT
)
3785 && INTVAL (op
) == 0)
3786 fputs (reg_names
[GP_REG_FIRST
], file
);
3788 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
3789 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
3791 else if (letter
== 'B')
3792 fputs (code
== EQ
? "z" : "n", file
);
3793 else if (letter
== 'b')
3794 fputs (code
== EQ
? "n" : "z", file
);
3795 else if (letter
== 'T')
3796 fputs (code
== EQ
? "f" : "t", file
);
3797 else if (letter
== 't')
3798 fputs (code
== EQ
? "t" : "f", file
);
3801 output_addr_const (file
, op
);
3805 /* A C compound statement to output to stdio stream STREAM the
3806 assembler syntax for an instruction operand that is a memory
3807 reference whose address is ADDR. ADDR is an RTL expression.
3809 On some machines, the syntax for a symbolic address depends on
3810 the section that the address refers to. On these machines,
3811 define the macro `ENCODE_SECTION_INFO' to store the information
3812 into the `symbol_ref', and then check for it here. */
3815 print_operand_address (file
, addr
)
3820 error ("PRINT_OPERAND_ADDRESS, null pointer");
3823 switch (GET_CODE (addr
))
3826 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
3830 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
3831 abort_with_insn (addr
, "Arg pointer not eliminated.");
3833 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
3838 register rtx reg
= (rtx
)0;
3839 register rtx offset
= (rtx
)0;
3840 register rtx arg0
= XEXP (addr
, 0);
3841 register rtx arg1
= XEXP (addr
, 1);
3843 if (GET_CODE (arg0
) == REG
)
3847 if (GET_CODE (offset
) == REG
)
3848 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
3850 else if (GET_CODE (arg1
) == REG
)
3855 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
3857 output_addr_const (file
, addr
);
3861 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
3863 if (!CONSTANT_P (offset
))
3864 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
3866 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
3867 abort_with_insn (addr
, "Arg pointer not eliminated.");
3869 output_addr_const (file
, offset
);
3870 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
3878 output_addr_const (file
, addr
);
3884 /* If optimizing for the global pointer, keep track of all of
3885 the externs, so that at the end of the file, we can emit
3886 the appropriate .extern declaration for them, before writing
3887 out the text section. We assume that all names passed to
3888 us are in the permanent obstack, so that they will be valid
3889 at the end of the compilation.
3891 If we have -G 0, or the extern size is unknown, don't bother
3892 emitting the .externs. */
3895 mips_output_external (file
, decl
, name
)
3900 register struct extern_list
*p
;
3904 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
3905 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0))
3907 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
3908 p
->next
= extern_head
;
3914 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
3915 if (TREE_CODE (decl
) == FUNCTION_DECL
3916 /* ??? Don't include alloca, since gcc will always expand it
3917 inline. If we don't do this, libg++ fails to build. */
3918 && strcmp (name
, "alloca")
3919 /* ??? Don't include __builtin_next_arg, because then gcc will not
3920 bootstrap under Irix 5.1. */
3921 && strcmp (name
, "__builtin_next_arg"))
3923 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
3924 p
->next
= extern_head
;
3934 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
3936 mips_output_external_libcall (file
, name
)
3940 register struct extern_list
*p
;
3942 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
3943 p
->next
= extern_head
;
3953 /* Compute a string to use as a temporary file name. */
3955 /* On MSDOS, write temp files in current dir
3956 because there's no place else we can expect to use. */
3959 #define P_tmpdir "./"
3967 char *base
= getenv ("TMPDIR");
3970 if (base
== (char *)0)
3973 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
3977 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
3983 len
= strlen (base
);
3984 /* temp_filename is global, so we must use malloc, not alloca. */
3985 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
3986 strcpy (temp_filename
, base
);
3987 if (len
> 0 && temp_filename
[len
-1] != '/')
3988 temp_filename
[len
++] = '/';
3990 strcpy (temp_filename
+ len
, "ctXXXXXX");
3991 mktemp (temp_filename
);
3993 stream
= fopen (temp_filename
, "w+");
3995 pfatal_with_name (temp_filename
);
3998 /* In MSDOS, we cannot unlink the temporary file until we are finished using
3999 it. Otherwise, we delete it now, so that it will be gone even if the
4000 compiler happens to crash. */
4001 unlink (temp_filename
);
4007 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4008 for .file's that start within a function. If we are smuggling stabs, try to
4009 put out a MIPS ECOFF file and a stab. */
4012 mips_output_filename (stream
, name
)
4016 static int first_time
= TRUE
;
4017 char ltext_label_name
[100];
4023 current_function_file
= name
;
4024 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4025 /* This tells mips-tfile that stabs will follow. */
4026 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4027 fprintf (stream
, "\t#@stabs\n");
4030 else if (write_symbols
== DBX_DEBUG
)
4032 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4033 fprintf (stream
, "%s ", ASM_STABS_OP
);
4034 output_quoted_string (stream
, name
);
4035 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4038 else if (name
!= current_function_file
4039 && strcmp (name
, current_function_file
) != 0)
4041 if (inside_function
&& !TARGET_GAS
)
4043 if (!file_in_function_warning
)
4045 file_in_function_warning
= TRUE
;
4046 ignore_line_number
= TRUE
;
4047 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4053 current_function_file
= name
;
4054 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4060 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4061 as well as a .loc, since it is possible that MIPS ECOFF might not be
4062 able to represent the location for inlines that come from a different
4066 mips_output_lineno (stream
, line
)
4070 if (write_symbols
== DBX_DEBUG
)
4073 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4074 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4075 LOCAL_LABEL_PREFIX
, sym_lineno
);
4080 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4081 (ignore_line_number
) ? "#" : "",
4082 num_source_filenames
, line
);
4084 LABEL_AFTER_LOC (stream
);
4089 /* If defined, a C statement to be executed just prior to the
4090 output of assembler code for INSN, to modify the extracted
4091 operands so they will be output differently.
4093 Here the argument OPVEC is the vector containing the operands
4094 extracted from INSN, and NOPERANDS is the number of elements of
4095 the vector which contain meaningful data for this insn. The
4096 contents of this vector are what will be used to convert the
4097 insn template into assembler code, so you can change the
4098 assembler output by changing the contents of the vector.
4100 We use it to check if the current insn needs a nop in front of it
4101 because of load delays, and also to update the delay slot
4104 /* ??? There is no real need for this function, because it never actually
4105 emits a NOP anymore. */
4108 final_prescan_insn (insn
, opvec
, noperands
)
4113 if (dslots_number_nops
> 0)
4115 rtx pattern
= PATTERN (insn
);
4116 int length
= get_attr_length (insn
);
4118 /* Do we need to emit a NOP? */
4120 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4121 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4122 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4123 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4124 fputs ("\t#nop\n", asm_out_file
);
4127 dslots_load_filled
++;
4129 while (--dslots_number_nops
> 0)
4130 fputs ("\t#nop\n", asm_out_file
);
4132 mips_load_reg
= (rtx
)0;
4133 mips_load_reg2
= (rtx
)0;
4134 mips_load_reg3
= (rtx
)0;
4135 mips_load_reg4
= (rtx
)0;
4140 enum rtx_code code
= GET_CODE (insn
);
4141 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4142 dslots_jump_total
++;
4147 /* Output at beginning of assembler file.
4148 If we are optimizing to use the global pointer, create a temporary
4149 file to hold all of the text stuff, and write it out to the end.
4150 This is needed because the MIPS assembler is evidently one pass,
4151 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4152 declaration when the code is processed, it generates a two
4153 instruction sequence. */
4156 mips_asm_file_start (stream
)
4159 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4161 /* Versions of the MIPS assembler before 2.20 generate errors
4162 if a branch inside of a .set noreorder section jumps to a
4163 label outside of the .set noreorder section. Revision 2.20
4164 just set nobopt silently rather than fixing the bug. */
4166 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4167 fprintf (stream
, "\t.set\tnobopt\n");
4169 /* Generate the pseudo ops that System V.4 wants. */
4170 #ifndef ABICALLS_ASM_OP
4171 #define ABICALLS_ASM_OP ".abicalls"
4173 if (TARGET_ABICALLS
)
4174 /* ??? but do not want this (or want pic0) if -non-shared? */
4175 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4177 /* Start a section, so that the first .popsection directive is guaranteed
4178 to have a previously defined section to pop back to. */
4179 if (ABI_64BIT
&& mips_isa
>= 3)
4180 fprintf (stream
, "\t.section\t.text\n");
4182 /* This code exists so that we can put all externs before all symbol
4183 references. This is necessary for the assembler's global pointer
4184 optimizations to work. */
4185 /* ??? Current versions of gas do not require that externs occur before
4186 symbol references. This means that this code is unnecessary when
4187 gas is being used. This gas feature hasn't been well tested as yet
4191 asm_out_data_file
= stream
;
4192 asm_out_text_file
= make_temp_file ();
4195 asm_out_data_file
= asm_out_text_file
= stream
;
4197 print_options (stream
);
4201 /* If we are optimizing the global pointer, emit the text section now
4202 and any small externs which did not have .comm, etc that are
4203 needed. Also, give a warning if the data area is more than 32K and
4204 -pic because 3 instructions are needed to reference the data
4208 mips_asm_file_end (file
)
4213 struct extern_list
*p
;
4217 HALF_PIC_FINISH (file
);
4223 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4225 name_tree
= get_identifier (p
->name
);
4227 /* Positively ensure only one .extern for any given symbol. */
4228 if (! TREE_ASM_WRITTEN (name_tree
))
4230 TREE_ASM_WRITTEN (name_tree
) = 1;
4231 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4233 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4237 fputs ("\t.extern\t", file
);
4238 assemble_name (file
, p
->name
);
4239 fprintf (file
, ", %d\n", p
->size
);
4247 fprintf (file
, "\n\t.text\n");
4248 rewind (asm_out_text_file
);
4249 if (ferror (asm_out_text_file
))
4250 fatal_io_error (temp_filename
);
4252 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4253 if (fwrite (buffer
, 1, len
, file
) != len
)
4254 pfatal_with_name (asm_file_name
);
4257 pfatal_with_name (temp_filename
);
4259 if (fclose (asm_out_text_file
) != 0)
4260 pfatal_with_name (temp_filename
);
4263 unlink (temp_filename
);
4269 /* Emit either a label, .comm, or .lcomm directive, and mark
4270 that the symbol is used, so that we don't emit an .extern
4271 for it in mips_asm_file_end. */
4274 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4281 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4282 assemble_name (stream
, name
);
4283 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4287 tree name_tree
= get_identifier (name
);
4288 TREE_ASM_WRITTEN (name_tree
) = 1;
4293 /* Output a double precision value to the assembler. If both the
4294 host and target are IEEE, emit the values in hex. */
4297 mips_output_double (stream
, value
)
4299 REAL_VALUE_TYPE value
;
4301 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4303 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4305 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4306 value_long
[0], value
, value_long
[1]);
4308 fprintf (stream
, "\t.double\t%.20g\n", value
);
4313 /* Output a single precision value to the assembler. If both the
4314 host and target are IEEE, emit the values in hex. */
4317 mips_output_float (stream
, value
)
4319 REAL_VALUE_TYPE value
;
4321 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4323 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4325 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4327 fprintf (stream
, "\t.float\t%.12g\n", value
);
4332 /* Return TRUE if any register used in the epilogue is used. This to insure
4333 any insn put into the epilogue delay slots is safe. */
4336 epilogue_reg_mentioned_p (insn
)
4341 register enum rtx_code code
;
4347 if (GET_CODE (insn
) == LABEL_REF
)
4350 code
= GET_CODE (insn
);
4354 regno
= REGNO (insn
);
4355 if (regno
== STACK_POINTER_REGNUM
)
4358 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4361 if (!call_used_regs
[regno
])
4364 if (regno
!= MIPS_TEMP1_REGNUM
&& regno
!= MIPS_TEMP2_REGNUM
)
4367 if (!current_frame_info
.initialized
)
4368 compute_frame_size (get_frame_size ());
4370 return (current_frame_info
.total_size
>= 32768);
4380 fmt
= GET_RTX_FORMAT (code
);
4381 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4386 for (j
= XVECLEN (insn
, i
) - 1; j
>= 0; j
--)
4387 if (epilogue_reg_mentioned_p (XVECEXP (insn
, i
, j
)))
4390 else if (fmt
[i
] == 'e' && epilogue_reg_mentioned_p (XEXP (insn
, i
)))
4397 /* Return the bytes needed to compute the frame pointer from the current
4400 Mips stack frames look like:
4402 Before call After call
4403 +-----------------------+ +-----------------------+
4406 | caller's temps. | | caller's temps. |
4408 +-----------------------+ +-----------------------+
4410 | arguments on stack. | | arguments on stack. |
4412 +-----------------------+ +-----------------------+
4413 | 4 words to save | | 4 words to save |
4414 | arguments passed | | arguments passed |
4415 | in registers, even | | in registers, even |
4416 SP->| if not passed. | VFP->| if not passed. |
4417 +-----------------------+ +-----------------------+
4419 | fp register save |
4421 +-----------------------+
4423 | gp register save |
4425 +-----------------------+
4429 +-----------------------+
4431 | alloca allocations |
4433 +-----------------------+
4435 | GP save for V.4 abi |
4437 +-----------------------+
4439 | arguments on stack |
4441 +-----------------------+
4443 | arguments passed |
4444 | in registers, even |
4445 low SP->| if not passed. |
4446 memory +-----------------------+
4451 compute_frame_size (size
)
4452 int size
; /* # of var. bytes allocated */
4455 long total_size
; /* # bytes that the entire frame takes up */
4456 long var_size
; /* # bytes that variables take up */
4457 long args_size
; /* # bytes that outgoing arguments take up */
4458 long extra_size
; /* # extra bytes */
4459 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4460 long gp_reg_size
; /* # bytes needed to store gp regs */
4461 long fp_reg_size
; /* # bytes needed to store fp regs */
4462 long mask
; /* mask of saved gp registers */
4463 long fmask
; /* mask of saved fp registers */
4464 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4465 long fp_bits
; /* bitmask to use for each fp register */
4471 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4472 var_size
= MIPS_STACK_ALIGN (size
);
4473 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4475 /* The MIPS 3.0 linker does not like functions that dynamically
4476 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4477 looks like we are trying to create a second frame pointer to the
4478 function, so allocate some stack space to make it happy. */
4480 if (args_size
== 0 && current_function_calls_alloca
)
4481 args_size
= 4*UNITS_PER_WORD
;
4483 total_size
= var_size
+ args_size
+ extra_size
;
4485 /* Calculate space needed for gp registers. */
4486 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4488 if (MUST_SAVE_REGISTER (regno
))
4490 gp_reg_size
+= UNITS_PER_WORD
;
4491 mask
|= 1L << (regno
- GP_REG_FIRST
);
4495 /* Calculate space needed for fp registers. */
4496 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4507 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4509 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4511 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4512 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4516 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4517 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4519 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4520 for leaf routines (total_size == extra_size) to save the gp reg.
4521 The gp reg is callee saved in the 64 bit ABI, so all routines must
4523 if (total_size
== extra_size
&& ! (ABI_64BIT
&& mips_isa
>= 3))
4524 total_size
= extra_size
= 0;
4525 else if (TARGET_ABICALLS
)
4527 /* Add the context-pointer to the saved registers. */
4528 gp_reg_size
+= UNITS_PER_WORD
;
4529 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4530 total_size
-= gp_reg_rounded
;
4531 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4532 total_size
+= gp_reg_rounded
;
4535 /* Add in space reserved on the stack by the callee for storing arguments
4536 passed in registers. */
4537 if (ABI_64BIT
&& mips_isa
>= 3)
4538 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4540 /* Save other computed information. */
4541 current_frame_info
.total_size
= total_size
;
4542 current_frame_info
.var_size
= var_size
;
4543 current_frame_info
.args_size
= args_size
;
4544 current_frame_info
.extra_size
= extra_size
;
4545 current_frame_info
.gp_reg_size
= gp_reg_size
;
4546 current_frame_info
.fp_reg_size
= fp_reg_size
;
4547 current_frame_info
.mask
= mask
;
4548 current_frame_info
.fmask
= fmask
;
4549 current_frame_info
.initialized
= reload_completed
;
4550 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4551 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4555 unsigned long offset
= (args_size
+ extra_size
+ var_size
4556 + gp_reg_size
- UNITS_PER_WORD
);
4557 current_frame_info
.gp_sp_offset
= offset
;
4558 current_frame_info
.gp_save_offset
= offset
- total_size
;
4562 current_frame_info
.gp_sp_offset
= 0;
4563 current_frame_info
.gp_save_offset
= 0;
4569 unsigned long offset
= (args_size
+ extra_size
+ var_size
4570 + gp_reg_rounded
+ fp_reg_size
4571 - fp_inc
* UNITS_PER_FPREG
);
4572 current_frame_info
.fp_sp_offset
= offset
;
4573 current_frame_info
.fp_save_offset
= offset
- total_size
+ UNITS_PER_WORD
;
4577 current_frame_info
.fp_sp_offset
= 0;
4578 current_frame_info
.fp_save_offset
= 0;
4581 /* Ok, we're done. */
4586 /* Common code to emit the insns (or to write the instructions to a file)
4587 to save/restore registers.
4589 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4590 is not modified within save_restore_insns. */
4592 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4595 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4596 int store_p
; /* true if this is prologue */
4597 rtx large_reg
; /* register holding large offset constant or NULL */
4598 long large_offset
; /* large constant offset value */
4599 FILE *file
; /* file to write instructions to instead of making RTL */
4601 long mask
= current_frame_info
.mask
;
4602 long fmask
= current_frame_info
.fmask
;
4610 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4613 if (mask
== 0 && fmask
== 0)
4616 /* Save registers starting from high to low. The debuggers prefer
4617 at least the return register be stored at func+4, and also it
4618 allows us not to need a nop in the epilog if at least one
4619 register is reloaded in addition to return address. */
4621 /* Save GP registers if needed. */
4624 /* Pick which pointer to use as a base register. For small
4625 frames, just use the stack pointer. Otherwise, use a
4626 temporary register. Save 2 cycles if the save area is near
4627 the end of a large frame, by reusing the constant created in
4628 the prologue/epilogue to adjust the stack frame. */
4630 gp_offset
= current_frame_info
.gp_sp_offset
;
4631 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
4633 if (gp_offset
< 0 || end_offset
< 0)
4634 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4635 gp_offset
, end_offset
);
4637 else if (gp_offset
< 32768)
4639 base_reg_rtx
= stack_pointer_rtx
;
4643 else if (large_reg
!= (rtx
)0
4644 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
4645 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4647 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4648 base_offset
= large_offset
;
4649 if (file
== (FILE *)0)
4652 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4654 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4657 fprintf (file
, "\t%s\t%s,%s,%s\n",
4658 TARGET_LONG64
? "daddu" : "addu",
4659 reg_names
[MIPS_TEMP2_REGNUM
],
4660 reg_names
[REGNO (large_reg
)],
4661 reg_names
[STACK_POINTER_REGNUM
]);
4666 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4667 base_offset
= gp_offset
;
4668 if (file
== (FILE *)0)
4670 emit_move_insn (base_reg_rtx
, GEN_INT (gp_offset
));
4672 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4674 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4677 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4678 reg_names
[MIPS_TEMP2_REGNUM
],
4681 TARGET_LONG64
? "daddu" : "addu",
4682 reg_names
[MIPS_TEMP2_REGNUM
],
4683 reg_names
[MIPS_TEMP2_REGNUM
],
4684 reg_names
[STACK_POINTER_REGNUM
]);
4687 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
4689 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
4691 if (file
== (FILE *)0)
4693 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
4694 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
4695 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
4696 GEN_INT (gp_offset
- base_offset
)));
4699 emit_move_insn (mem_rtx
, reg_rtx
);
4700 else if (!TARGET_ABICALLS
|| (ABI_64BIT
&& mips_isa
>= 3)
4701 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4702 emit_move_insn (reg_rtx
, mem_rtx
);
4706 if (store_p
|| !TARGET_ABICALLS
|| (ABI_64BIT
&& mips_isa
>= 3)
4707 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4708 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
4710 ? (store_p
) ? "sd" : "ld"
4711 : (store_p
) ? "sw" : "lw"),
4713 gp_offset
- base_offset
,
4714 reg_names
[REGNO(base_reg_rtx
)]);
4717 gp_offset
-= UNITS_PER_WORD
;
4723 base_reg_rtx
= (rtx
)0; /* Make sure these are initialized */
4727 /* Save floating point registers if needed. */
4730 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
4731 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
4733 /* Pick which pointer to use as a base register. */
4734 fp_offset
= current_frame_info
.fp_sp_offset
;
4735 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
4737 if (fp_offset
< 0 || end_offset
< 0)
4738 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
4739 fp_offset
, end_offset
);
4741 else if (fp_offset
< 32768)
4743 base_reg_rtx
= stack_pointer_rtx
;
4747 else if (base_reg_rtx
!= (rtx
)0
4748 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
4749 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
4751 ; /* already set up for gp registers above */
4754 else if (large_reg
!= (rtx
)0
4755 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
4756 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4758 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4759 base_offset
= large_offset
;
4760 if (file
== (FILE *)0)
4763 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4765 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4768 fprintf (file
, "\t%s\t%s,%s,%s\n",
4769 TARGET_LONG64
? "daddu" : "addu",
4770 reg_names
[MIPS_TEMP2_REGNUM
],
4771 reg_names
[REGNO (large_reg
)],
4772 reg_names
[STACK_POINTER_REGNUM
]);
4777 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4778 base_offset
= fp_offset
;
4779 if (file
== (FILE *)0)
4781 emit_move_insn (base_reg_rtx
, GEN_INT (fp_offset
));
4783 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4785 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4788 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4789 reg_names
[MIPS_TEMP2_REGNUM
],
4792 TARGET_LONG64
? "daddu" : "addu",
4793 reg_names
[MIPS_TEMP2_REGNUM
],
4794 reg_names
[MIPS_TEMP2_REGNUM
],
4795 reg_names
[STACK_POINTER_REGNUM
]);
4798 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
4800 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
4802 if (file
== (FILE *)0)
4804 enum machine_mode sz
=
4805 TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
4806 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
4807 rtx mem_rtx
= gen_rtx (MEM
, sz
,
4808 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
4809 GEN_INT (fp_offset
- base_offset
)));
4812 emit_move_insn (mem_rtx
, reg_rtx
);
4814 emit_move_insn (reg_rtx
, mem_rtx
);
4817 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
4818 (TARGET_SINGLE_FLOAT
4819 ? ((store_p
) ? "s.s" : "l.s")
4820 : ((store_p
) ? "s.d" : "l.d")),
4822 fp_offset
- base_offset
,
4823 reg_names
[REGNO(base_reg_rtx
)]);
4826 fp_offset
-= fp_size
;
4833 /* Set up the stack and frame (if desired) for the function. */
4836 function_prologue (file
, size
)
4841 long tsize
= current_frame_info
.total_size
;
4843 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
4845 #ifdef SDB_DEBUGGING_INFO
4846 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
4847 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
4850 /* Get the function name the same way that toplev.c does before calling
4851 assemble_start_function. This is needed so that the name used here
4852 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
4853 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
4855 inside_function
= 1;
4856 fputs ("\t.ent\t", file
);
4857 assemble_name (file
, fnname
);
4860 assemble_name (file
, fnname
);
4861 fputs (":\n", file
);
4863 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
4864 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
4866 reg_names
[31 + GP_REG_FIRST
],
4867 current_frame_info
.var_size
,
4868 current_frame_info
.num_gp
,
4869 current_frame_info
.num_fp
,
4870 current_function_outgoing_args_size
,
4871 current_frame_info
.extra_size
);
4873 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
4874 current_frame_info
.mask
,
4875 current_frame_info
.gp_save_offset
,
4876 current_frame_info
.fmask
,
4877 current_frame_info
.fp_save_offset
);
4879 if (TARGET_ABICALLS
&& ! (ABI_64BIT
&& mips_isa
>= 3))
4881 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
4883 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
4884 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
4887 fprintf (file
, "\t%s\t%s,%s,%d\n",
4888 (TARGET_LONG64
? "dsubu" : "subu"),
4889 sp_str
, sp_str
, tsize
);
4890 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
4896 /* Expand the prologue into a bunch of separate insns. */
4899 mips_expand_prologue ()
4903 rtx tmp_rtx
= (rtx
)0;
4904 char *arg_name
= (char *)0;
4905 tree fndecl
= current_function_decl
;
4906 tree fntype
= TREE_TYPE (fndecl
);
4907 tree fnargs
= (TREE_CODE (fntype
) != METHOD_TYPE
)
4908 ? DECL_ARGUMENTS (fndecl
)
4914 CUMULATIVE_ARGS args_so_far
;
4916 /* If struct value address is treated as the first argument, make it so. */
4917 if (aggregate_value_p (DECL_RESULT (fndecl
))
4918 && ! current_function_returns_pcc_struct
4919 && struct_value_incoming_rtx
== 0)
4921 tree type
= build_pointer_type (fntype
);
4922 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
4923 DECL_ARG_TYPE (function_result_decl
) = type
;
4924 TREE_CHAIN (function_result_decl
) = fnargs
;
4925 fnargs
= function_result_decl
;
4928 /* Determine the last argument, and get its name. */
4930 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0);
4931 regno
= GP_ARG_FIRST
;
4933 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
4935 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
4936 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
4939 if (TYPE_NEEDS_CONSTRUCTING (passed_type
))
4941 passed_type
= build_pointer_type (passed_type
);
4942 passed_mode
= Pmode
;
4945 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
4951 /* passed in a register, so will get homed automatically */
4952 if (GET_MODE (entry_parm
) == BLKmode
)
4953 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
4955 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
4957 regno
= REGNO (entry_parm
) + words
- 1;
4961 regno
= GP_ARG_LAST
+1;
4965 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
4967 next_arg
= TREE_CHAIN (cur_arg
);
4968 if (next_arg
== (tree
)0)
4970 if (DECL_NAME (cur_arg
))
4971 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
4977 /* In order to pass small structures by value in registers
4978 compatibly with the MIPS compiler, we need to shift the value
4979 into the high part of the register. Function_arg has encoded a
4980 PARALLEL rtx, holding a vector of adjustments to be made as the
4981 next_arg_reg variable, so we split up the insns, and emit them
4984 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
4985 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
4987 rtvec adjust
= XVEC (next_arg_reg
, 0);
4988 int num
= GET_NUM_ELEM (adjust
);
4990 for (i
= 0; i
< num
; i
++)
4992 rtx pattern
= RTVEC_ELT (adjust
, i
);
4993 if (GET_CODE (pattern
) != SET
4994 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
4995 abort_with_insn (pattern
, "Insn is not a shift");
4997 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
4998 emit_insn (pattern
);
5002 tsize
= compute_frame_size (get_frame_size ());
5004 /* If this function is a varargs function, store any registers that
5005 would normally hold arguments ($4 - $7) on the stack. */
5006 if ((! ABI_64BIT
|| mips_isa
< 3)
5007 && ((TYPE_ARG_TYPES (fntype
) != 0
5008 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
5009 || (arg_name
!= (char *)0
5010 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
5011 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0)))))
5013 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5014 rtx ptr
= stack_pointer_rtx
;
5016 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5017 if (TARGET_ABICALLS
&& ! (ABI_64BIT
&& mips_isa
>= 3))
5020 for (; regno
<= GP_ARG_LAST
; regno
++)
5023 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
5024 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
5025 gen_rtx (REG
, word_mode
, regno
));
5026 offset
+= UNITS_PER_WORD
;
5032 rtx tsize_rtx
= GEN_INT (tsize
);
5034 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5035 if (!TARGET_ABICALLS
|| (ABI_64BIT
&& mips_isa
>= 3))
5039 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5040 emit_move_insn (tmp_rtx
, tsize_rtx
);
5041 tsize_rtx
= tmp_rtx
;
5045 emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5048 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5052 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5054 if (frame_pointer_needed
)
5057 emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
5059 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
5062 if (TARGET_ABICALLS
&& (ABI_64BIT
&& mips_isa
>= 3))
5063 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0)));
5066 /* If we are profiling, make sure no instructions are scheduled before
5067 the call to mcount. */
5069 if (profile_flag
|| profile_block_flag
)
5070 emit_insn (gen_blockage ());
5074 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5076 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5077 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5080 function_epilogue (file
, size
)
5086 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5087 char *t1_str
= reg_names
[MIPS_TEMP1_REGNUM
];
5088 rtx epilogue_delay
= current_function_epilogue_delay_list
;
5089 int noreorder
= (epilogue_delay
!= 0);
5090 int noepilogue
= FALSE
;
5091 int load_nop
= FALSE
;
5093 rtx tmp_rtx
= (rtx
)0;
5097 /* The epilogue does not depend on any registers, but the stack
5098 registers, so we assume that if we have 1 pending nop, it can be
5099 ignored, and 2 it must be filled (2 nops occur for integer
5100 multiply and divide). */
5102 if (dslots_number_nops
> 0)
5104 if (dslots_number_nops
== 1)
5106 dslots_number_nops
= 0;
5107 dslots_load_filled
++;
5111 while (--dslots_number_nops
> 0)
5112 fputs ("\t#nop\n", asm_out_file
);
5119 fputs ("\t.set\tat\n", file
);
5120 error ("internal gcc error: .set noat left on in epilogue");
5123 if (set_nomacro
!= 0)
5126 fputs ("\t.set\tmacro\n", file
);
5127 error ("internal gcc error: .set nomacro left on in epilogue");
5130 if (set_noreorder
!= 0)
5133 fputs ("\t.set\treorder\n", file
);
5134 error ("internal gcc error: .set noreorder left on in epilogue");
5137 if (set_volatile
!= 0)
5140 fprintf (file
, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS
) ? "" : "#");
5141 error ("internal gcc error: .set volatile left on in epilogue");
5144 size
= MIPS_STACK_ALIGN (size
);
5145 tsize
= (!current_frame_info
.initialized
)
5146 ? compute_frame_size (size
)
5147 : current_frame_info
.total_size
;
5149 if (tsize
== 0 && epilogue_delay
== 0)
5151 rtx insn
= get_last_insn ();
5153 /* If the last insn was a BARRIER, we don't have to write any code
5154 because a jump (aka return) was put there. */
5155 if (GET_CODE (insn
) == NOTE
)
5156 insn
= prev_nonnote_insn (insn
);
5157 if (insn
&& GET_CODE (insn
) == BARRIER
)
5165 /* In the reload sequence, we don't need to fill the load delay
5166 slots for most of the loads, also see if we can fill the final
5167 delay slot if not otherwise filled by the reload sequence. */
5170 fprintf (file
, "\t.set\tnoreorder\n");
5174 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str
, (long)tsize
, (long)tsize
);
5175 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5178 if (frame_pointer_needed
)
5179 fprintf (file
, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5180 sp_str
, reg_names
[FRAME_POINTER_REGNUM
]);
5182 save_restore_insns (FALSE
, tmp_rtx
, tsize
, file
);
5184 load_only_r31
= (((current_frame_info
.mask
5185 & ~ (TARGET_ABICALLS
&& ! (ABI_64BIT
&& mips_isa
>= 3)
5186 ? PIC_OFFSET_TABLE_MASK
: 0))
5188 && current_frame_info
.fmask
== 0);
5192 /* If the only register saved is the return address, we need a
5193 nop, unless we have an instruction to put into it. Otherwise
5194 we don't since reloading multiple registers doesn't reference
5195 the register being loaded. */
5200 final_scan_insn (XEXP (epilogue_delay
, 0),
5204 1); /* nopeepholes */
5207 fprintf (file
, "\tnop\n");
5212 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5215 fprintf (file
, "\t%s\t%s,%s,%s\n",
5216 TARGET_LONG64
? "daddu" : "addu",
5217 sp_str
, sp_str
, t1_str
);
5220 fprintf (file
, "\t%s\t%s,%s,%d\n",
5221 TARGET_LONG64
? "daddu" : "addu",
5222 sp_str
, sp_str
, tsize
);
5224 else if (!load_only_r31
&& epilogue_delay
!= 0)
5225 final_scan_insn (XEXP (epilogue_delay
, 0),
5229 1); /* nopeepholes */
5231 fprintf (file
, "\t.set\treorder\n");
5237 fprintf (file
, "\t%s\t%s,%s,%s\n",
5238 TARGET_LONG64
? "daddu" : "addu",
5239 sp_str
, sp_str
, t1_str
);
5242 fprintf (file
, "\t%s\t%s,%s,%d\n",
5243 TARGET_LONG64
? "daddu" : "addu",
5244 sp_str
, sp_str
, tsize
);
5246 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5250 /* Get the function name the same way that toplev.c does before calling
5251 assemble_start_function. This is needed so that the name used here
5252 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5253 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5255 fputs ("\t.end\t", file
);
5256 assemble_name (file
, fnname
);
5261 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5262 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5263 int num_regs
= num_gp_regs
+ num_fp_regs
;
5264 char *name
= fnname
;
5269 dslots_load_total
+= num_regs
;
5272 dslots_jump_total
++;
5276 dslots_load_filled
+= num_regs
;
5278 /* If the only register saved is the return register, we
5279 can't fill this register's delay slot. */
5281 if (load_only_r31
&& epilogue_delay
== 0)
5282 dslots_load_filled
--;
5284 if (tsize
> 0 || (!load_only_r31
&& epilogue_delay
!= 0))
5285 dslots_jump_filled
++;
5289 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5291 (frame_pointer_needed
) ? 'y' : 'n',
5292 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5293 (current_function_calls_alloca
) ? 'y' : 'n',
5294 (current_function_calls_setjmp
) ? 'y' : 'n',
5295 (long)current_frame_info
.total_size
,
5296 (long)current_function_outgoing_args_size
,
5297 num_gp_regs
, num_fp_regs
,
5298 dslots_load_total
, dslots_load_filled
,
5299 dslots_jump_total
, dslots_jump_filled
,
5300 num_refs
[0], num_refs
[1], num_refs
[2]);
5302 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5304 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5305 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5308 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5310 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5311 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5314 fputc ('\n', stderr
);
5317 /* Reset state info for each function. */
5318 inside_function
= FALSE
;
5319 ignore_line_number
= FALSE
;
5320 dslots_load_total
= 0;
5321 dslots_jump_total
= 0;
5322 dslots_load_filled
= 0;
5323 dslots_jump_filled
= 0;
5327 mips_load_reg
= (rtx
)0;
5328 mips_load_reg2
= (rtx
)0;
5329 current_frame_info
= zero_frame_info
;
5331 /* Restore the output file if optimizing the GP (optimizing the GP causes
5332 the text to be diverted to a tempfile, so that data decls come before
5333 references to the data). */
5336 asm_out_file
= asm_out_data_file
;
5340 /* Expand the epilogue into a bunch of separate insns. */
5343 mips_expand_epilogue ()
5345 long tsize
= current_frame_info
.total_size
;
5346 rtx tsize_rtx
= GEN_INT (tsize
);
5347 rtx tmp_rtx
= (rtx
)0;
5351 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5352 emit_move_insn (tmp_rtx
, tsize_rtx
);
5353 tsize_rtx
= tmp_rtx
;
5358 if (frame_pointer_needed
)
5361 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5363 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5366 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5369 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5372 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5376 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
, GP_REG_FIRST
+31)));
5380 /* Define the number of delay slots needed for the function epilogue.
5382 On the mips, we need a slot if either no stack has been allocated,
5383 or the only register saved is the return register. */
5386 mips_epilogue_delay_slots ()
5388 if (!current_frame_info
.initialized
)
5389 (void) compute_frame_size (get_frame_size ());
5391 if (current_frame_info
.total_size
== 0)
5394 if (current_frame_info
.mask
== RA_MASK
&& current_frame_info
.fmask
== 0)
5401 /* Return true if this function is known to have a null epilogue.
5402 This allows the optimizer to omit jumps to jumps if no stack
5406 simple_epilogue_p ()
5408 if (!reload_completed
)
5411 if (current_frame_info
.initialized
)
5412 return current_frame_info
.total_size
== 0;
5414 return (compute_frame_size (get_frame_size ())) == 0;
5417 /* Choose the section to use for the constant rtx expression X that has
5420 mips_select_rtx_section (mode
, x
)
5421 enum machine_mode mode
;
5424 if (TARGET_EMBEDDED_DATA
)
5426 /* For embedded applications, always put constants in read-only data,
5427 in order to reduce RAM usage. */
5428 READONLY_DATA_SECTION ();
5432 /* For hosted applications, always put constants in small data if
5433 possible, as this gives the best performance. */
5435 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5436 && mips_section_threshold
> 0)
5437 SMALL_DATA_SECTION ();
5439 READONLY_DATA_SECTION ();
5443 /* Choose the section to use for DECL. RELOC is true if its value contains
5444 any relocatable expression. */
5446 mips_select_section (decl
, reloc
)
5450 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5452 if (TARGET_EMBEDDED_PIC
5453 && TREE_CODE (decl
) == STRING_CST
5454 && !flag_writable_strings
)
5456 /* For embedded position independent code, put constant strings
5457 in the text section, because the data section is limited to
5462 else if (TARGET_EMBEDDED_DATA
)
5464 /* For embedded applications, always put an object in read-only data
5465 if possible, in order to reduce RAM usage. */
5467 if (((TREE_CODE (decl
) == VAR_DECL
5468 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5469 && DECL_INITIAL (decl
)
5470 && (DECL_INITIAL (decl
) == error_mark_node
5471 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5472 /* Deal with calls from output_constant_def_contents. */
5473 || (TREE_CODE (decl
) != VAR_DECL
5474 && (TREE_CODE (decl
) != STRING_CST
5475 || !flag_writable_strings
)))
5476 && ! (flag_pic
&& reloc
))
5477 READONLY_DATA_SECTION ();
5478 else if (size
> 0 && size
<= mips_section_threshold
)
5479 SMALL_DATA_SECTION ();
5485 /* For hosted applications, always put an object in small data if
5486 possible, as this gives the best performance. */
5488 if (size
> 0 && size
<= mips_section_threshold
)
5489 SMALL_DATA_SECTION ();
5490 else if (((TREE_CODE (decl
) == VAR_DECL
5491 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5492 && DECL_INITIAL (decl
)
5493 && (DECL_INITIAL (decl
) == error_mark_node
5494 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5495 /* Deal with calls from output_constant_def_contents. */
5496 || (TREE_CODE (decl
) != VAR_DECL
5497 && (TREE_CODE (decl
) != STRING_CST
5498 || !flag_writable_strings
)))
5499 && ! (flag_pic
&& reloc
))
5500 READONLY_DATA_SECTION ();
5507 /* Support functions for the 64 bit ABI. */
5509 /* Return the register to be used for word INDEX of a variable with type TYPE
5510 being passed starting at general purpose reg REGNO.
5512 If the word being passed is a single field of a structure which has type
5513 double, then pass it in a floating point reg instead of a general purpose
5514 reg. Otherwise, we return the default value REGNO + INDEX. */
5517 type_dependent_reg (regno
, index
, type
)
5525 /* If type isn't a structure type, return the default value now. */
5526 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_isa
< 3)
5527 return gen_rtx (REG
, word_mode
, regno
+ index
);
5529 /* Iterate through the structure fields to find which one corresponds to
5531 offset
= size_int (index
* BITS_PER_WORD
);
5532 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5534 if (! tree_int_cst_lt (DECL_FIELD_BITPOS (field
), offset
))
5538 if (field
&& tree_int_cst_equal (DECL_FIELD_BITPOS (field
), offset
)
5539 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
5540 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5541 return gen_rtx (REG
, DFmode
,
5542 regno
+ index
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
5544 return gen_rtx (REG
, word_mode
, regno
+ index
);
5547 /* Return register to use for a function return value with VALTYPE for function
5551 mips_function_value (valtype
, func
)
5555 int reg
= GP_RETURN
;
5556 enum machine_mode mode
= TYPE_MODE (valtype
);
5557 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5559 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5561 else if (TREE_CODE (valtype
) == RECORD_TYPE
&& mips_isa
>= 3)
5563 /* A struct with only one or two floating point fields is returned in
5564 the floating point registers. */
5568 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5569 field
= TREE_CHAIN (field
), i
++)
5571 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5575 /* Must check i, so that we reject structures with no elements. */
5576 if (! field
&& i
> 0)
5580 return gen_rtx (REG
, mode
, reg
);
5584 /* This function returns the register class required for a secondary
5585 register when copying between one of the registers in CLASS, and X,
5586 using MODE. If IN_P is nonzero, the copy is going from X to the
5587 register, otherwise the register is the source. A return value of
5588 NO_REGS means that no secondary register is required. */
5591 mips_secondary_reload_class (class, mode
, x
, in_p
)
5592 enum reg_class
class;
5593 enum machine_mode mode
;
5599 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5600 regno
= true_regnum (x
);
5602 /* We always require a general register when copying anything to
5603 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
5604 to a general register, or when copying from register 0. */
5605 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
5609 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5613 if (regno
== HILO_REGNUM
)
5617 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5622 /* Copying from HI or LO to anywhere other than a general register
5623 requires a general register. */
5624 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
5626 if (GP_REG_P (regno
))
5630 if (MD_REG_P (regno
))
5632 if (class == GR_REGS
)