| blob | 1cc10432b769e4f04810bd664c918927a46f7df9 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
71 /* This file should be included last. */
74 /* Defined for convenience. */
75 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
77 /* Classifies an address.
79 ADDRESS_REG_IMM
80 A simple base register plus immediate offset.
82 ADDRESS_REG_WB
83 A base register indexed by immediate offset with writeback.
85 ADDRESS_REG_REG
86 A base register indexed by (optionally scaled) register.
88 ADDRESS_REG_UXTW
89 A base register indexed by (optionally scaled) zero-extended register.
91 ADDRESS_REG_SXTW
92 A base register indexed by (optionally scaled) sign-extended register.
94 ADDRESS_LO_SUM
95 A LO_SUM rtx with a base register and "LO12" symbol relocation.
97 ADDRESS_SYMBOLIC:
98 A constant symbolic address, in pc-relative literal pool. */
101 ADDRESS_REG_IMM,
102 ADDRESS_REG_WB,
103 ADDRESS_REG_REG,
104 ADDRESS_REG_UXTW,
105 ADDRESS_REG_SXTW,
106 ADDRESS_LO_SUM,
107 ADDRESS_SYMBOLIC
108 };
112 rtx base;
113 rtx offset;
116 };
118 struct simd_immediate_info
119 {
120 rtx value;
125 };
127 /* The current code model. */
130 #ifdef HAVE_AS_TLS
131 #undef TARGET_HAVE_TLS
132 #define TARGET_HAVE_TLS 1
133 #endif
137 const_tree,
145 vec_perm_indices);
148 const_tree type,
151 static machine_mode
154 /* Major revision number of the ARM Architecture implemented by the target. */
157 /* The processor for which instructions should be scheduled. */
160 /* Mask to specify which instruction scheduling options should be used. */
163 /* Global flag for PC relative loads. */
166 /* Support for command line parsing of boolean flags in the tuning
167 structures. */
168 struct aarch64_flag_desc
169 {
172 };
174 #define AARCH64_FUSION_PAIR(name, internal_name) \
175 { name, AARCH64_FUSE_##internal_name },
177 {
182 };
184 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
185 { name, AARCH64_EXTRA_TUNE_##internal_name },
187 {
192 };
194 /* Tuning parameters. */
197 {
198 {
203 },
210 };
213 {
214 {
219 },
226 };
229 {
230 {
235 },
242 };
245 {
246 {
251 },
258 };
261 {
263 /* Avoid the use of slow int<->fp moves for spilling by setting
264 their cost higher than memmov_cost. */
268 };
271 {
273 /* Avoid the use of slow int<->fp moves for spilling by setting
274 their cost higher than memmov_cost. */
278 };
281 {
283 /* Avoid the use of slow int<->fp moves for spilling by setting
284 their cost higher than memmov_cost. */
288 };
291 {
293 /* Avoid the use of slow int<->fp moves for spilling by setting
294 their cost higher than memmov_cost (actual, 4 and 9). */
298 };
301 {
306 };
309 {
311 /* Avoid the use of slow int<->fp moves for spilling by setting
312 their cost higher than memmov_cost. */
316 };
319 {
321 /* Avoid the use of int<->fp moves for spilling. */
325 };
328 {
330 /* Avoid the use of int<->fp moves for spilling. */
334 };
336 /* Generic costs for vector insn classes. */
338 {
354 };
356 /* ThunderX costs for vector insn classes. */
358 {
374 };
376 /* Generic costs for vector insn classes. */
378 {
394 };
397 {
413 };
415 /* Generic costs for vector insn classes. */
417 {
433 };
435 /* Costs for vector insn classes for Vulcan. */
437 {
453 };
455 /* Generic costs for branch instructions. */
457 {
460 };
462 /* Generic approximation modes. */
464 {
467 AARCH64_APPROX_NONE /* recip_sqrt */
468 };
470 /* Approximation modes for Exynos M1. */
472 {
475 AARCH64_APPROX_ALL /* recip_sqrt */
476 };
478 /* Approximation modes for X-Gene 1. */
480 {
483 AARCH64_APPROX_ALL /* recip_sqrt */
484 };
486 /* Generic prefetch settings (which disable prefetch). */
488 {
494 };
497 {
503 };
506 {
512 };
515 {
521 };
524 {
530 };
533 {
539 };
542 {
563 &generic_prefetch_tune
564 };
567 {
589 &generic_prefetch_tune
590 };
593 {
615 &generic_prefetch_tune
616 };
619 {
641 &generic_prefetch_tune
642 };
645 {
667 &generic_prefetch_tune
668 };
671 {
693 &generic_prefetch_tune
694 };
699 {
720 &exynosm1_prefetch_tune
721 };
724 {
745 &thunderxt88_prefetch_tune
746 };
749 {
769 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
771 &thunderx_prefetch_tune
772 };
775 {
796 &generic_prefetch_tune
797 };
800 {
822 &qdf24xx_prefetch_tune
823 };
826 {
848 &thunderx2t99_prefetch_tune
849 };
851 /* Support for fine-grained override of the tuning structures. */
852 struct aarch64_tuning_override_function
853 {
856 };
861 static const struct aarch64_tuning_override_function
862 aarch64_tuning_override_functions[] =
863 {
867 };
869 /* A processor implementing AArch64. */
870 struct processor
871 {
879 };
881 /* Architectures implementing AArch64. */
883 {
884 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
885 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
888 };
890 /* Processor cores implementing AArch64. */
892 {
893 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
894 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
895 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
896 FLAGS, &COSTS##_tunings},
901 };
904 /* Target specification. These are populated by the -march, -mtune, -mcpu
905 handling code or by target attributes. */
910 /* The current tuning set. */
913 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
915 /* An ISA extension in the co-processor and main instruction set space. */
916 struct aarch64_option_extension
917 {
921 };
924 {
928 }
929 aarch64_cc;
931 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
933 /* The condition codes of the processor, and the inverse function. */
935 {
938 };
940 /* Generate code to enable conditional branches in functions over 1 MiB. */
944 {
961 }
963 void
965 {
969 else
971 }
973 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
974 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
975 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
976 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
977 cost (in this case the best class is the lowest cost one). Using ALL_REGS
978 irrespectively of its cost results in bad allocations with many redundant
979 int<->FP moves which are expensive on various cores.
980 To avoid this we don't allow ALL_REGS as the allocno class, but force a
981 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
982 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
983 Otherwise set the allocno class depending on the mode.
984 The result of this is that it is no longer inefficient to have a higher
985 memory move cost than the register move cost.
986 */
988 static reg_class_t
990 reg_class_t best_class)
991 {
992 machine_mode mode;
1002 }
1004 static unsigned int
1006 {
1010 }
1012 static int
1014 machine_mode mode)
1015 {
1023 }
1025 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1026 unsigned
1028 {
1036 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1037 equivalent DWARF register. */
1039 }
1041 /* Return TRUE if MODE is any of the large INT modes. */
1042 static bool
1044 {
1046 }
1048 /* Return TRUE if MODE is any of the vector modes. */
1049 static bool
1051 {
1054 }
1056 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1057 static bool
1060 {
1068 }
1070 /* Implement TARGET_HARD_REGNO_NREGS. */
1072 static unsigned int
1074 {
1076 {
1082 }
1084 }
1086 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1088 static bool
1090 {
1095 /* The purpose of comparing with ptr_mode is to support the
1096 global register variable associated with the stack pointer
1097 register via the syntax of asm ("wsp") in ILP32. */
1107 {
1110 else
1112 }
1115 }
1117 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1118 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1119 clobbers the top 64 bits when restoring the bottom 64 bits. */
1121 static bool
1123 {
1125 }
1127 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1128 machine_mode
1130 machine_mode mode)
1131 {
1132 /* Handle modes that fit within single registers. */
1134 {
1137 else
1139 }
1140 /* Fall back to generic for multi-reg and very large modes. */
1141 else
1143 }
1145 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
1146 that strcpy from constants will be faster. */
1148 static HOST_WIDE_INT
1150 {
1154 }
1156 /* Return true if calls to DECL should be treated as
1157 long-calls (ie called via a register). */
1158 static bool
1160 {
1162 }
1164 /* Return true if calls to symbol-ref SYM should be treated as
1165 long-calls (ie called via a register). */
1166 bool
1168 {
1170 }
1172 /* Return true if calls to symbol-ref SYM should not go through
1173 plt stubs. */
1175 bool
1177 {
1181 && decl
1182 && (!flag_plt
1188 }
1190 /* Return true if the offsets to a zero/sign-extract operation
1191 represent an expression that matches an extend operation. The
1192 operands represent the paramters from
1194 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1195 bool
1197 rtx extract_imm)
1198 {
1215 }
1217 /* Emit an insn that's a simple single-set. Both the operands must be
1218 known to be valid. */
1221 {
1223 }
1225 /* X and Y are two things to compare using CODE. Emit the compare insn and
1226 return the rtx for register 0 in the proper mode. */
1227 rtx
1229 {
1235 }
1237 /* Build the SYMBOL_REF for __tls_get_addr. */
1241 rtx
1243 {
1247 }
1249 /* Return the TLS model to use for ADDR. */
1251 static enum tls_model
1253 {
1258 {
1262 }
1267 }
1269 /* We'll allow lo_sum's in addresses in our legitimate addresses
1270 so that combine would take care of combining addresses where
1271 necessary, but for generation purposes, we'll generate the address
1272 as :
1273 RTL Absolute
1274 tmp = hi (symbol_ref); adrp x1, foo
1275 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1276 nop
1278 PIC TLS
1279 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1280 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1281 bl __tls_get_addr
1282 nop
1284 Load TLS symbol, depending on TLS mechanism and TLS access model.
1286 Global Dynamic - Traditional TLS:
1287 adrp tmp, :tlsgd:imm
1288 add dest, tmp, #:tlsgd_lo12:imm
1289 bl __tls_get_addr
1291 Global Dynamic - TLS Descriptors:
1292 adrp dest, :tlsdesc:imm
1293 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1294 add dest, dest, #:tlsdesc_lo12:imm
1295 blr tmp
1296 mrs tp, tpidr_el0
1297 add dest, dest, tp
1299 Initial Exec:
1300 mrs tp, tpidr_el0
1301 adrp tmp, :gottprel:imm
1302 ldr dest, [tmp, #:gottprel_lo12:imm]
1303 add dest, dest, tp
1305 Local Exec:
1306 mrs tp, tpidr_el0
1307 add t0, tp, #:tprel_hi12:imm, lsl #12
1308 add t0, t0, #:tprel_lo12_nc:imm
1309 */
1311 static void
1314 {
1316 {
1318 {
1319 /* In ILP32, the mode of dest can be either SImode or DImode. */
1331 }
1338 {
1341 rtx insn;
1342 rtx mem;
1344 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1345 here before rtl expand. Tree IVOPT will generate rtl pattern to
1346 decide rtx costs, in which case pic_offset_table_rtx is not
1347 initialized. For that case no need to generate the first adrp
1348 instruction as the final cost for global variable access is
1349 one instruction. */
1351 {
1352 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1353 using the page base as GOT base, the first page may be wasted,
1354 in the worst scenario, there is only 28K space for GOT).
1356 The generate instruction sequence for accessing global variable
1357 is:
1359 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1361 Only one instruction needed. But we must initialize
1362 pic_offset_table_rtx properly. We generate initialize insn for
1363 every global access, and allow CSE to remove all redundant.
1365 The final instruction sequences will look like the following
1366 for multiply global variables access.
1368 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1370 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1371 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1372 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1373 ... */
1382 }
1385 {
1388 else
1392 }
1393 else
1394 {
1399 }
1401 /* The operand is expected to be MEM. Whenever the related insn
1402 pattern changed, above code which calculate mem should be
1403 updated. */
1409 }
1412 {
1413 /* In ILP32, the mode of dest can be either SImode or DImode,
1414 while the got entry is always of SImode size. The mode of
1415 dest depends on how dest is used: if dest is assigned to a
1416 pointer (e.g. in the memory), it has SImode; it may have
1417 DImode if dest is dereferenced to access the memeory.
1418 This is why we have to handle three different ldr_got_small
1419 patterns here (two patterns for ILP32). */
1421 rtx insn;
1422 rtx mem;
1431 {
1434 else
1438 }
1439 else
1440 {
1445 }
1452 }
1455 {
1463 else
1471 }
1474 {
1477 rtx tp;
1481 /* In ILP32, the got entry is always of SImode size. Unlike
1482 small GOT, the dest is fixed at reg 0. */
1485 else
1496 }
1499 {
1500 /* In ILP32, the mode of dest can be either SImode or DImode,
1501 while the got entry is always of SImode size. The mode of
1502 dest depends on how dest is used: if dest is assigned to a
1503 pointer (e.g. in the memory), it has SImode; it may have
1504 DImode if dest is dereferenced to access the memeory.
1505 This is why we have to handle three different tlsie_small
1506 patterns here (two patterns for ILP32). */
1512 {
1515 else
1516 {
1519 }
1520 }
1521 else
1522 {
1525 }
1531 }
1537 {
1545 {
1568 }
1573 }
1580 {
1585 {
1588 else
1589 {
1592 }
1593 }
1594 else
1595 {
1598 }
1603 }
1607 }
1608 }
1610 /* Emit a move from SRC to DEST. Assume that the move expanders can
1611 handle all moves if !can_create_pseudo_p (). The distinction is
1612 important because, unlike emit_move_insn, the move expanders know
1613 how to force Pmode objects into the constant pool even when the
1614 constant pool address is not itself legitimate. */
1615 static rtx
1617 {
1621 }
1623 /* Split a 128-bit move operation into two 64-bit move operations,
1624 taking care to handle partial overlap of register to register
1625 copies. Special cases are needed when moving between GP regs and
1626 FP regs. SRC can be a register, constant or memory; DST a register
1627 or memory. If either operand is memory it must not have any side
1628 effects. */
1629 void
1631 {
1642 {
1646 /* Handle FP <-> GP regs. */
1648 {
1653 {
1656 }
1657 else
1658 {
1661 }
1663 }
1665 {
1670 {
1673 }
1674 else
1675 {
1678 }
1680 }
1681 }
1688 /* At most one pairing may overlap. */
1690 {
1693 }
1694 else
1695 {
1698 }
1699 }
1701 bool
1703 {
1706 }
1708 /* Split a complex SIMD combine. */
1710 void
1712 {
1724 {
1748 }
1752 }
1754 /* Split a complex SIMD move. */
1756 void
1758 {
1765 {
1771 {
1795 }
1799 }
1800 }
1802 bool
1805 {
1809 }
1812 static rtx
1814 {
1817 else
1818 {
1821 }
1822 }
1825 static rtx
1827 HOST_WIDE_INT offset)
1828 {
1830 {
1831 rtx high;
1832 /* Load the full offset into a register. This
1833 might be improvable in the future. */
1839 }
1841 }
1843 static int
1845 scalar_int_mode mode)
1846 {
1855 {
1859 }
1861 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1862 (with XXXX non-zero). In that case check to see if the move can be done in
1863 a smaller mode. */
1868 {
1872 /* Check if we have to emit a second instruction by checking to see
1873 if any of the upper 32 bits of the original DI mode value is set. */
1884 }
1887 {
1889 {
1894 else
1897 }
1899 }
1901 /* Remaining cases are all for DImode. */
1910 {
1911 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1912 For a 64-bit bitmask try whether changing 16 bits to all ones or
1913 zeroes creates a valid bitmask. To check any repeated bitmask,
1914 try using 16 bits from the other 32-bit half of val. */
1917 {
1928 }
1930 {
1932 {
1936 }
1938 }
1939 }
1941 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1942 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1943 otherwise skip zero bits. */
1955 {
1961 num_insns ++;
1962 }
1965 }
1968 void
1970 {
1975 /* Check on what type of symbol it is. */
1976 scalar_int_mode int_mode;
1981 {
1985 /* If we have (const (plus symbol offset)), separate out the offset
1986 before we start classifying the symbol. */
1991 {
1995 {
2002 }
2007 /* If we aren't generating PC relative literals, then
2008 we need to expand the literal pool access carefully.
2009 This is something that needs to be done in a number
2010 of places, so could well live as a separate function. */
2012 {
2019 }
2036 {
2043 }
2044 /* FALLTHRU */
2057 }
2058 }
2061 {
2064 else
2065 {
2069 }
2072 }
2076 }
2078 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
2079 temporary value if necessary. FRAME_RELATED_P should be true if
2080 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
2081 to the generated instructions. If SCRATCHREG is known to hold
2082 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2083 immediate again.
2085 Since this function may be used to adjust the stack pointer, we must
2086 ensure that it cannot cause transient stack deallocation (for example
2087 by first incrementing SP and then decrementing when adjusting by a
2088 large immediate). */
2090 static void
2094 {
2102 /* Single instruction adjustment. */
2104 {
2108 }
2110 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2111 Only do this if mdelta is not a 16-bit move as adjusting using a move
2112 is better. */
2114 {
2123 }
2125 /* Emit a move immediate if required and an addition/subtraction. */
2132 {
2136 }
2137 }
2141 HOST_WIDE_INT delta)
2142 {
2144 }
2148 {
2151 }
2155 {
2158 }
2160 static bool
2162 tree exp ATTRIBUTE_UNUSED)
2163 {
2164 /* Currently, always true. */
2166 }
2168 /* Implement TARGET_PASS_BY_REFERENCE. */
2170 static bool
2172 machine_mode mode,
2173 const_tree type,
2175 {
2176 HOST_WIDE_INT size;
2177 machine_mode dummymode;
2180 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2184 /* Aggregates are passed by reference based on their size. */
2186 {
2188 }
2190 /* Variable sized arguments are always returned by reference. */
2194 /* Can this be a candidate to be passed in fp/simd register(s)? */
2197 NULL))
2200 /* Arguments which are variable sized or larger than 2 registers are
2201 passed by reference unless they are a homogenous floating point
2202 aggregate. */
2204 }
2206 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2207 static bool
2209 {
2210 machine_mode dummy_mode;
2213 /* Never happens in little-endian mode. */
2217 /* Only composite types smaller than or equal to 16 bytes can
2218 be potentially returned in registers. */
2224 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2225 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2226 is always passed/returned in the least significant bits of fp/simd
2227 register(s). */
2233 }
2235 /* Implement TARGET_FUNCTION_VALUE.
2236 Define how to find the value returned by a function. */
2238 static rtx
2241 {
2242 machine_mode mode;
2245 machine_mode ag_mode;
2252 {
2256 {
2259 }
2260 }
2264 {
2266 {
2269 }
2270 else
2271 {
2273 rtx par;
2277 {
2282 }
2284 }
2285 }
2286 else
2288 }
2290 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2291 Return true if REGNO is the number of a hard register in which the values
2292 of called function may come back. */
2294 static bool
2296 {
2297 /* Maximum of 16 bytes can be returned in the general registers. Examples
2298 of 16-byte return values are: 128-bit integers and 16-byte small
2299 structures (excluding homogeneous floating-point aggregates). */
2303 /* Up to four fp/simd registers can return a function value, e.g. a
2304 homogeneous floating-point aggregate having four members. */
2309 }
2311 /* Implement TARGET_RETURN_IN_MEMORY.
2313 If the type T of the result of a function is such that
2314 void func (T arg)
2315 would require that arg be passed as a value in a register (or set of
2316 registers) according to the parameter passing rules, then the result
2317 is returned in the same registers as would be used for such an
2318 argument. */
2320 static bool
2322 {
2323 HOST_WIDE_INT size;
2324 machine_mode ag_mode;
2330 /* Simple scalar types always returned in registers. */
2334 type,
2337 NULL))
2340 /* Types larger than 2 registers returned in memory. */
2343 }
2345 static bool
2348 {
2351 type,
2353 nregs,
2354 NULL);
2355 }
2357 /* Given MODE and TYPE of a function argument, return the alignment in
2358 bits. The idea is to suppress any stronger alignment requested by
2359 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2360 This is a helper function for local use only. */
2362 static unsigned int
2364 {
2385 }
2387 /* Layout a function argument according to the AAPCS64 rules. The rule
2388 numbers refer to the rule numbers in the AAPCS64. */
2390 static void
2392 const_tree type,
2394 {
2398 HOST_WIDE_INT size;
2400 /* We need to do this once per argument. */
2406 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2407 size
2409 UNITS_PER_WORD);
2413 mode,
2414 type,
2417 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2418 The following code thus handles passing by SIMD/FP registers first. */
2422 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2423 and homogenous short-vector aggregates (HVA). */
2425 {
2430 {
2433 {
2436 }
2437 else
2438 {
2439 rtx par;
2443 {
2446 tmp = gen_rtx_EXPR_LIST
2450 }
2452 }
2454 }
2455 else
2456 {
2457 /* C.3 NSRN is set to 8. */
2460 }
2461 }
2466 /* C6 - C9. though the sign and zero extension semantics are
2467 handled elsewhere. This is the case where the argument fits
2468 entirely general registers. */
2470 {
2474 /* C.8 if the argument has an alignment of 16 then the NGRN is
2475 rounded up to the next even number. */
2478 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2479 comparison is there because for > 16 * BITS_PER_UNIT
2480 alignment nregs should be > 2 and therefore it should be
2481 passed by reference rather than value. */
2483 {
2486 }
2488 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2489 A reg is still generated for it, but the caller should be smart
2490 enough not to use it. */
2493 else
2494 {
2495 rtx par;
2500 {
2505 }
2507 }
2511 }
2513 /* C.11 */
2516 /* The argument is passed on stack; record the needed number of words for
2517 this argument and align the total size if necessary. */
2518 on_stack:
2525 }
2527 /* Implement TARGET_FUNCTION_ARG. */
2529 static rtx
2532 {
2541 }
2543 void
2545 const_tree fntype ATTRIBUTE_UNUSED,
2546 rtx libname ATTRIBUTE_UNUSED,
2547 const_tree fndecl ATTRIBUTE_UNUSED,
2549 {
2563 {
2570 }
2572 }
2574 static void
2576 machine_mode mode,
2577 const_tree type,
2579 {
2582 {
2592 }
2593 }
2595 bool
2597 {
2600 }
2602 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2603 PARM_BOUNDARY bits of alignment, but will be given anything up
2604 to STACK_BOUNDARY bits if the type requires it. This makes sure
2605 that both before and after the layout of each argument, the Next
2606 Stacked Argument Address (NSAA) will have a minimum alignment of
2607 8 bytes. */
2609 static unsigned int
2611 {
2614 }
2616 /* Implement TARGET_FUNCTION_ARG_PADDING.
2618 Small aggregate types are placed in the lowest memory address.
2620 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2622 static pad_direction
2624 {
2625 /* On little-endian targets, the least significant byte of every stack
2626 argument is passed at the lowest byte address of the stack slot. */
2630 /* Otherwise, integral, floating-point and pointer types are padded downward:
2631 the least significant byte of a stack argument is passed at the highest
2632 byte address of the stack slot. */
2639 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2641 }
2643 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2645 It specifies padding for the last (may also be the only)
2646 element of a block move between registers and memory. If
2647 assuming the block is in the memory, padding upward means that
2648 the last element is padded after its highest significant byte,
2649 while in downward padding, the last element is padded at the
2650 its least significant byte side.
2652 Small aggregates and small complex types are always padded
2653 upwards.
2655 We don't need to worry about homogeneous floating-point or
2656 short-vector aggregates; their move is not affected by the
2657 padding direction determined here. Regardless of endianness,
2658 each element of such an aggregate is put in the least
2659 significant bits of a fp/simd register.
2661 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2662 register has useful data, and return the opposite if the most
2663 significant byte does. */
2665 bool
2668 {
2670 /* Small composite types are always padded upward. */
2672 {
2677 }
2679 /* Otherwise, use the default padding. */
2681 }
2683 static scalar_int_mode
2685 {
2687 }
2689 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2691 /* We use the 12-bit shifted immediate arithmetic instructions so values
2692 must be multiple of (1 << 12), i.e. 4096. */
2693 #define ARITH_FACTOR 4096
2695 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2696 #error Cannot use simple address calculation for stack probing
2697 #endif
2699 /* The pair of scratch registers used for stack probing. */
2700 #define PROBE_STACK_FIRST_REG 9
2701 #define PROBE_STACK_SECOND_REG 10
2703 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2704 inclusive. These are offsets from the current stack pointer. */
2706 static void
2708 {
2711 /* See the same assertion on PROBE_INTERVAL above. */
2714 /* See if we have a constant small number of probes to generate. If so,
2715 that's the easy case. */
2717 {
2724 }
2726 /* The run-time loop is made up of 8 insns in the generic case while the
2727 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2729 {
2734 stack_pointer_rtx,
2738 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2739 it exceeds SIZE. If only two probes are needed, this will not
2740 generate any code. Then probe at FIRST + SIZE. */
2742 {
2746 }
2750 {
2755 }
2756 else
2758 }
2760 /* Otherwise, do the same as above, but in a loop. Note that we must be
2761 extra careful with variables wrapping around because we might be at
2762 the very top (or the very bottom) of the address space and we have
2763 to be able to handle this case properly; in particular, we use an
2764 equality test for the loop condition. */
2765 else
2766 {
2769 /* Step 1: round SIZE to the previous multiple of the interval. */
2774 /* Step 2: compute initial and final value of the loop counter. */
2776 /* TEST_ADDR = SP + FIRST. */
2780 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2783 {
2787 }
2788 else
2789 {
2792 }
2794 /* Step 3: the loop
2796 do
2797 {
2798 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2799 probe at TEST_ADDR
2800 }
2801 while (TEST_ADDR != LAST_ADDR)
2803 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2804 until it is equal to ROUNDED_SIZE. */
2809 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2810 that SIZE is equal to ROUNDED_SIZE. */
2813 {
2817 {
2822 }
2823 else
2825 }
2826 }
2828 /* Make sure nothing is scheduled before we are done. */
2830 }
2832 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2833 absolute addresses. */
2837 {
2844 /* Loop. */
2847 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2852 /* Probe at TEST_ADDR. */
2855 /* Test if TEST_ADDR == LAST_ADDR. */
2859 /* Branch. */
2865 }
2867 static bool
2869 {
2870 /* Use the frame pointer if enabled and it is not a leaf function, unless
2871 leaf frame pointer omission is disabled. If the frame pointer is enabled,
2872 force the frame pointer in leaf functions which use LR. */
2874 && !(flag_omit_leaf_frame_pointer
2880 }
2882 /* Mark the registers that need to be saved by the callee and calculate
2883 the size of the callee-saved registers area and frame record (both FP
2884 and LR may be omitted). If the function is not a leaf, ensure LR is
2885 saved at the bottom of the callee-save area. */
2886 static void
2888 {
2895 /* Force a frame chain for EH returns so the return address is at FP+8. */
2899 #define SLOT_NOT_REQUIRED (-2)
2900 #define SLOT_REQUIRED (-1)
2905 /* First mark all the registers that really need to be saved... */
2912 /* ... that includes the eh data registers (if needed)... */
2918 /* ... and any callee saved register that dataflow says is live. */
2928 {
2931 }
2934 {
2935 /* FP and LR are placed in the linkage record. */
2941 }
2943 {
2944 /* Ensure LR is saved at the bottom of the callee-saves. */
2948 }
2950 /* Now assign stack slots for them. */
2953 {
2960 }
2968 {
2969 /* If there is an alignment gap between integer and fp callee-saves,
2970 allocate the last fp register to it if possible. */
2972 {
2975 }
2984 }
2990 HOST_WIDE_INT varargs_and_saved_regs_size
3017 {
3018 /* Simple, small frame with no outgoing arguments:
3019 stp reg1, reg2, [sp, -frame_size]!
3020 stp reg3, reg4, [sp, 16] */
3022 }
3027 {
3028 /* Frame with small outgoing arguments:
3029 sub sp, sp, frame_size
3030 stp reg1, reg2, [sp, outgoing_args_size]
3031 stp reg3, reg4, [sp, outgoing_args_size + 16] */
3035 }
3037 {
3038 /* Frame with large outgoing arguments but a small local area:
3039 stp reg1, reg2, [sp, -hard_fp_offset]!
3040 stp reg3, reg4, [sp, 16]
3041 sub sp, sp, outgoing_args_size */
3045 }
3046 else
3047 {
3048 /* Frame with large local area and outgoing arguments using frame pointer:
3049 sub sp, sp, hard_fp_offset
3050 stp x29, x30, [sp, 0]
3051 add x29, sp, 0
3052 stp reg3, reg4, [sp, 16]
3053 sub sp, sp, outgoing_args_size */
3057 }
3060 }
3062 /* Return true if the register REGNO is saved on entry to
3063 the current function. */
3065 static bool
3067 {
3069 }
3071 /* Return the next register up from REGNO up to LIMIT for the callee
3072 to save. */
3074 static unsigned
3076 {
3078 regno ++;
3080 }
3082 /* Push the register number REGNO of mode MODE to the stack with write-back
3083 adjusting the stack by ADJUSTMENT. */
3085 static void
3087 HOST_WIDE_INT adjustment)
3088 {
3099 }
3101 /* Generate and return an instruction to store the pair of registers
3102 REG and REG2 of mode MODE to location BASE with write-back adjusting
3103 the stack location BASE by ADJUSTMENT. */
3105 static rtx
3107 HOST_WIDE_INT adjustment)
3108 {
3110 {
3121 }
3122 }
3124 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3125 stack pointer by ADJUSTMENT. */
3127 static void
3129 {
3144 }
3146 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3147 adjusting it by ADJUSTMENT afterwards. */
3149 static rtx
3151 HOST_WIDE_INT adjustment)
3152 {
3154 {
3163 }
3164 }
3166 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3167 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3168 into CFI_OPS. */
3170 static void
3173 {
3180 {
3184 }
3185 else
3186 {
3191 }
3192 }
3194 /* Generate and return a store pair instruction of mode MODE to store
3195 register REG1 to MEM1 and register REG2 to MEM2. */
3197 static rtx
3199 rtx reg2)
3200 {
3202 {
3211 }
3212 }
3214 /* Generate and regurn a load pair isntruction of mode MODE to load register
3215 REG1 from MEM1 and register REG2 from MEM2. */
3217 static rtx
3219 rtx mem2)
3220 {
3222 {
3231 }
3232 }
3234 /* Return TRUE if return address signing should be enabled for the current
3235 function, otherwise return FALSE. */
3237 bool
3239 {
3240 /* This function should only be called after frame laid out. */
3243 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3244 if it's LR is pushed onto stack. */
3248 }
3250 /* Emit code to save the callee-saved registers from register number START
3251 to LIMIT to the stack at the location starting at offset START_OFFSET,
3252 skipping any write-back candidates if SKIP_WB is true. */
3254 static void
3257 {
3265 {
3267 HOST_WIDE_INT offset;
3280 offset));
3289 {
3291 rtx mem2;
3295 offset));
3297 reg2));
3299 /* The first part of a frame-related parallel insn is
3300 always assumed to be relevant to the frame
3301 calculations; subsequent parts, are only
3302 frame-related if explicitly marked. */
3305 }
3306 else
3310 }
3311 }
3313 /* Emit code to restore the callee registers of mode MODE from register
3314 number START up to and including LIMIT. Restore from the stack offset
3315 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3316 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3318 static void
3322 {
3326 HOST_WIDE_INT offset;
3331 {
3352 {
3354 rtx mem2;
3362 }
3363 else
3366 }
3367 }
3371 HOST_WIDE_INT offset)
3372 {
3374 }
3378 {
3382 }
3384 bool
3386 {
3390 }
3392 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3394 static sbitmap
3396 {
3402 /* The registers we need saved to the frame. */
3405 {
3410 /* Check that we can access the stack slot of the register with one
3411 direct load with no adjustments needed. */
3414 }
3416 /* Don't mess with the hard frame pointer. */
3422 /* If aarch64_layout_frame has chosen registers to store/restore with
3423 writeback don't interfere with them to avoid having to output explicit
3424 stack adjustment instructions. */
3434 }
3436 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3438 static sbitmap
3440 {
3448 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3457 }
3459 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3460 Nothing to do for aarch64. */
3462 static void
3464 {
3465 }
3467 /* Return the next set bit in BMP from START onwards. Return the total number
3468 of bits in BMP if no set bit is found at or after START. */
3470 static unsigned int
3472 {
3483 }
3485 /* Do the work for aarch64_emit_prologue_components and
3486 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3487 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3488 for these components or the epilogue sequence. That is, it determines
3489 whether we should emit stores or loads and what kind of CFA notes to attach
3490 to the insns. Otherwise the logic for the two sequences is very
3491 similar. */
3493 static void
3495 {
3497 ? HARD_FRAME_POINTER_REGNUM
3505 {
3506 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3507 so DFmode for the vector registers is enough. */
3519 /* No more registers to handle after REGNO.
3520 Emit a single save/restore and exit. */
3522 {
3527 else
3530 }
3533 /* The next register is not of the same class or its offset is not
3534 mergeable with the current one into a pair. */
3539 {
3544 else
3549 }
3551 /* REGNO2 can be saved/restored in a pair with REGNO. */
3563 else
3568 {
3571 }
3572 else
3573 {
3576 }
3579 }
3580 }
3582 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3584 static void
3586 {
3588 }
3590 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3592 static void
3594 {
3596 }
3598 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3600 static void
3602 {
3606 }
3608 /* AArch64 stack frames generated by this compiler look like:
3610 +-------------------------------+
3611 | |
3612 | incoming stack arguments |
3613 | |
3614 +-------------------------------+
3615 | | <-- incoming stack pointer (aligned)
3616 | callee-allocated save area |
3617 | for register varargs |
3618 | |
3619 +-------------------------------+
3620 | local variables | <-- frame_pointer_rtx
3621 | |
3622 +-------------------------------+
3623 | padding0 | \
3624 +-------------------------------+ |
3625 | callee-saved registers | | frame.saved_regs_size
3626 +-------------------------------+ |
3627 | LR' | |
3628 +-------------------------------+ |
3629 | FP' | / <- hard_frame_pointer_rtx (aligned)
3630 +-------------------------------+
3631 | dynamic allocation |
3632 +-------------------------------+
3633 | padding |
3634 +-------------------------------+
3635 | outgoing stack arguments | <-- arg_pointer
3636 | |
3637 +-------------------------------+
3638 | | <-- stack_pointer_rtx (aligned)
3640 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3641 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3642 unchanged. */
3644 /* Generate the prologue instructions for entry into a function.
3645 Establish the stack frame by decreasing the stack pointer with a
3646 properly calculated size and, if necessary, create a frame record
3647 filled with the values of LR and previous frame pointer. The
3648 current FP is also set up if it is in use. */
3650 void
3652 {
3665 /* Sign return address for functions. */
3667 {
3671 }
3677 {
3679 {
3683 (frame_size
3685 }
3688 }
3696 {
3701 stack_pointer_rtx,
3705 }
3712 }
3714 /* Return TRUE if we can use a simple_return insn.
3716 This function checks whether the callee saved stack is empty, which
3717 means no restore actions are need. The pro_and_epilogue will use
3718 this to check whether shrink-wrapping opt is feasible. */
3720 bool
3722 {
3732 }
3734 /* Generate the epilogue instructions for returning from a function.
3735 This is almost exactly the reverse of the prolog sequence, except
3736 that we need to insert barriers to avoid scheduling loads that read
3737 from a deallocated stack, and we optimize the unwind records by
3738 emitting them all together if possible. */
3739 void
3741 {
3753 /* We need to add memory barrier to prevent read from deallocated stack. */
3757 /* Emit a barrier to prevent loads from a deallocated stack. */
3760 {
3763 }
3765 /* Restore the stack pointer from the frame pointer if it may not
3766 be the same as the stack pointer. */
3768 {
3770 hard_frame_pointer_rtx,
3772 /* If writeback is used when restoring callee-saves, the CFA
3773 is restored on the instruction doing the writeback. */
3775 }
3776 else
3791 {
3792 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3798 }
3803 {
3804 /* Emit delayed restores and reset the CFA to be SP. */
3809 }
3811 /* We prefer to emit the combined return/authenticate instruction RETAA,
3812 however there are three cases in which we must instead emit an explicit
3813 authentication instruction.
3815 1) Sibcalls don't return in a normal way, so if we're about to call one
3816 we must authenticate.
3818 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3819 generating code for !TARGET_ARMV8_3 we can't use it and must
3820 explicitly authenticate.
3822 3) On an eh_return path we make extra stack adjustments to update the
3823 canonical frame address to be the exception handler's CFA. We want
3824 to authenticate using the CFA of the function which calls eh_return.
3825 */
3828 {
3832 }
3834 /* Stack adjustment for exception handler. */
3836 {
3837 /* We need to unwind the stack by the offset computed by
3838 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3839 to be SP; letting the CFA move during this adjustment
3840 is just as correct as retaining the CFA from the body
3841 of the function. Therefore, do nothing special. */
3843 }
3848 }
3850 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3851 normally or return to a previous frame after unwinding.
3853 An EH return uses a single shared return sequence. The epilogue is
3854 exactly like a normal epilogue except that it has an extra input
3855 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3856 that must be applied after the frame has been destroyed. An extra label
3857 is inserted before the epilogue which initializes this register to zero,
3858 and this is the entry point for a normal return.
3860 An actual EH return updates the return address, initializes the stack
3861 adjustment and jumps directly into the epilogue (bypassing the zeroing
3862 of the adjustment). Since the return address is typically saved on the
3863 stack when a function makes a call, the saved LR must be updated outside
3864 the epilogue.
3866 This poses problems as the store is generated well before the epilogue,
3867 so the offset of LR is not known yet. Also optimizations will remove the
3868 store as it appears dead, even after the epilogue is generated (as the
3869 base or offset for loading LR is different in many cases).
3871 To avoid these problems this implementation forces the frame pointer
3872 in eh_return functions so that the location of LR is fixed and known early.
3873 It also marks the store volatile, so no optimization is permitted to
3874 remove the store. */
3875 rtx
3877 {
3881 /* Mark the store volatile, so no optimization is permitted to remove it. */
3884 }
3886 /* Output code to add DELTA to the first argument, and then jump
3887 to FUNCTION. Used for C++ multiple inheritance. */
3888 static void
3890 HOST_WIDE_INT delta,
3891 HOST_WIDE_INT vcall_offset,
3892 tree function)
3893 {
3894 /* The this pointer is always in x0. Note that this differs from
3895 Arm where the this pointer maybe bumped to r1 if r0 is required
3896 to return a pointer to an aggregate. On AArch64 a result value
3897 pointer will be in x8. */
3907 else
3908 {
3917 {
3921 else
3923 }
3927 else
3934 else
3935 {
3937 Pmode);
3939 }
3943 else
3949 }
3951 /* Generate a tail call to the target function. */
3953 {
3956 }
3968 /* Stop pretending to be a post-reload pass. */
3970 }
3972 static bool
3974 {
3979 {
3983 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3984 TLS offsets, not real symbol references. */
3987 }
3989 }
3992 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3993 a left shift of 0 or 12 bits. */
3994 bool
3996 {
3999 );
4000 }
4003 /* Return true if val is an immediate that can be loaded into a
4004 register by a MOVZ instruction. */
4005 static bool
4007 {
4009 {
4013 }
4014 else
4015 {
4016 /* Ignore sign extension. */
4018 }
4021 }
4023 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4026 {
4032 };
4035 /* Return true if val is a valid bitmask immediate. */
4037 bool
4039 {
4043 /* Check for a single sequence of one bits and return quickly if so.
4044 The special cases of all ones and all zeroes returns false. */
4051 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4055 /* Invert if the immediate doesn't start with a zero bit - this means we
4056 only need to search for sequences of one bits. */
4060 /* Find the first set bit and set tmp to val with the first sequence of one
4061 bits removed. Return success if there is a single sequence of ones. */
4068 /* Find the next set bit and compute the difference in bit position. */
4073 /* Check the bit position difference is a power of 2, and that the first
4074 sequence of one bits fits within 'bits' bits. */
4078 /* Check the sequence of one bits is repeated 64/bits times. */
4080 }
4082 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4083 Assumed precondition: VAL_IN Is not zero. */
4085 unsigned HOST_WIDE_INT
4087 {
4094 }
4096 /* Create constant where bits outside of lowest bit set to highest bit set
4097 are set to 1. */
4099 unsigned HOST_WIDE_INT
4101 {
4103 }
4105 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4107 bool
4109 {
4110 scalar_int_mode int_mode;
4123 }
4125 /* Return true if val is an immediate that can be loaded into a
4126 register in a single instruction. */
4127 bool
4129 {
4130 scalar_int_mode int_mode;
4137 }
4139 static bool
4141 {
4149 {
4153 else
4154 /* Avoid generating a 64-bit relocation in ILP32; leave
4155 to aarch64_expand_mov_immediate to handle it properly. */
4157 }
4160 }
4162 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4163 The expansion for a table switch is quite expensive due to the number
4164 of instructions, the table lookup and hard to predict indirect jump.
4165 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4166 set, otherwise use tables for > 16 cases as a tradeoff between size and
4167 performance. When optimizing for size, use the default setting. */
4169 static unsigned int
4171 {
4172 /* Use the specified limit for the number of cases before using jump
4173 tables at higher optimization levels. */
4177 else
4179 }
4181 /* Return true if register REGNO is a valid index register.
4182 STRICT_P is true if REG_OK_STRICT is in effect. */
4184 bool
4186 {
4188 {
4196 }
4198 }
4200 /* Return true if register REGNO is a valid base register for mode MODE.
4201 STRICT_P is true if REG_OK_STRICT is in effect. */
4203 bool
4205 {
4207 {
4215 }
4217 /* The fake registers will be eliminated to either the stack or
4218 hard frame pointer, both of which are usually valid base registers.
4219 Reload deals with the cases where the eliminated form isn't valid. */
4224 }
4226 /* Return true if X is a valid base register for mode MODE.
4227 STRICT_P is true if REG_OK_STRICT is in effect. */
4229 static bool
4231 {
4238 }
4240 /* Return true if address offset is a valid index. If it is, fill in INFO
4241 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4243 static bool
4246 {
4248 rtx index;
4251 /* (reg:P) */
4254 {
4258 }
4259 /* (sign_extend:DI (reg:SI)) */
4264 {
4269 }
4270 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4277 {
4282 }
4283 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4290 {
4295 }
4296 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4303 {
4311 }
4312 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4313 (const_int 0xffffffff<<shift)) */
4320 {
4326 }
4327 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4334 {
4342 }
4343 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4344 (const_int 0xffffffff<<shift)) */
4351 {
4357 }
4358 /* (mult:P (reg:P) (const_int scale)) */
4363 {
4367 }
4368 /* (ashift:P (reg:P) (const_int shift)) */
4373 {
4377 }
4378 else
4391 {
4396 }
4399 }
4401 /* Return true if MODE is one of the modes for which we
4402 support LDP/STP operations. */
4404 static bool
4406 {
4411 }
4413 /* Return true if REGNO is a virtual pointer register, or an eliminable
4414 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4415 include stack_pointer or hard_frame_pointer. */
4416 static bool
4418 {
4423 }
4425 /* Return true if X is a valid address for machine mode MODE. If it is,
4426 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4427 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4429 static bool
4433 {
4437 /* On BE, we use load/store pair for all large int mode load/stores.
4438 TI/TFmode may also use a load/store pair. */
4442 || (BYTES_BIG_ENDIAN
4446 !load_store_pair_p
4450 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4451 REG addressing. */
4457 {
4473 {
4479 }
4484 {
4491 /* TImode and TFmode values are allowed in both pairs of X
4492 registers and individual Q registers. The available
4493 address modes are:
4494 X,X: 7-bit signed scaled offset
4495 Q: 9-bit signed offset
4496 We conservatively require an offset representable in either mode.
4497 When performing the check for pairs of X registers i.e. LDP/STP
4498 pass down DImode since that is the natural size of the LDP/STP
4499 instruction memory accesses. */
4505 /* A 7bit offset check because OImode will emit a ldp/stp
4506 instruction (only big endian will get here).
4507 For ldp/stp instructions, the offset is scaled for the size of a
4508 single element of the pair. */
4512 /* Three 9/12 bit offsets checks because CImode will emit three
4513 ldr/str instructions (only big endian will get here). */
4520 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4521 instructions (only big endian will get here). */
4530 else
4533 }
4536 {
4537 /* Look for base + (scaled/extended) index register. */
4540 {
4543 }
4546 {
4549 }
4550 }
4571 {
4572 HOST_WIDE_INT offset;
4576 /* TImode and TFmode values are allowed in both pairs of X
4577 registers and individual Q registers. The available
4578 address modes are:
4579 X,X: 7-bit signed scaled offset
4580 Q: 9-bit signed offset
4581 We conservatively require an offset representable in either mode.
4582 */
4590 else
4592 }
4598 /* load literal: pc-relative constant pool entry. Only supported
4599 for SI mode or larger. */
4603 {
4611 }
4620 {
4625 {
4626 /* The symbol and offset must be aligned to the access size. */
4633 {
4637 }
4643 else
4652 }
4653 }
4658 }
4659 }
4661 /* Return true if the address X is valid for a PRFM instruction.
4662 STRICT_P is true if we should do strict checking with
4663 aarch64_classify_address. */
4665 bool
4667 {
4670 /* PRFM accepts the same addresses as DImode... */
4675 /* ... except writeback forms. */
4677 }
4679 bool
4681 {
4682 rtx offset;
4686 }
4688 /* Classify the base of symbolic expression X. */
4690 enum aarch64_symbol_type
4692 {
4693 rtx offset;
4697 }
4700 /* Return TRUE if X is a legitimate address for accessing memory in
4701 mode MODE. */
4702 static bool
4704 {
4708 }
4710 /* Return TRUE if X is a legitimate address for accessing memory in
4711 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4712 pair operation. */
4713 bool
4716 {
4720 }
4722 /* Split an out-of-range address displacement into a base and offset.
4723 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4724 to increase opportunities for sharing the base address of different sizes.
4725 Unaligned accesses use the signed 9-bit range, TImode/TFmode use
4726 the intersection of signed scaled 7-bit and signed 9-bit offset. */
4727 static bool
4729 {
4731 HOST_WIDE_INT base;
4737 else
4743 }
4745 /* Return the binary representation of floating point constant VALUE in INTVAL.
4746 If the value cannot be converted, return false without setting INTVAL.
4747 The conversion is done in the given MODE. */
4748 bool
4750 {
4752 /* We make a general exception for 0. */
4754 {
4757 }
4763 /* Only support up to DF mode. */
4775 {
4779 }
4780 else
4785 }
4787 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4788 single MOV(+MOVK) followed by an FMOV. */
4789 bool
4791 {
4796 /* Determine whether it's cheaper to write float constants as
4797 mov/movk pairs over ldr/adrp pairs. */
4803 {
4805 ? SImode
4810 }
4813 }
4815 /* Return TRUE if rtx X is immediate constant 0.0 */
4816 bool
4818 {
4825 }
4827 /* Return TRUE if rtx X is immediate constant that fits in a single
4828 MOVI immediate operation. */
4829 bool
4831 {
4835 machine_mode vmode;
4836 scalar_int_mode imode;
4841 {
4845 /* We make a general exception for 0. */
4850 }
4854 else
4857 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4858 a 128 bit vector mode. */
4865 }
4868 /* Return the fixed registers used for condition codes. */
4870 static bool
4872 {
4876 }
4878 /* This function is used by the call expanders of the machine description.
4879 RESULT is the register in which the result is returned. It's NULL for
4880 "call" and "sibcall".
4881 MEM is the location of the function call.
4882 SIBCALL indicates whether this function call is normal call or sibling call.
4883 It will generate different pattern accordingly. */
4885 void
4887 {
4889 rtvec vec;
4890 machine_mode mode;
4897 /* Decide if we should generate indirect calls by loading the
4898 address of the callee into a register before performing
4899 the branch-and-link. */
4913 else
4920 }
4922 /* Emit call insn with PAT and do aarch64-specific handling. */
4924 void
4926 {
4932 }
4934 machine_mode
4936 {
4937 /* All floating point compares return CCFP if it is an equality
4938 comparison, and CCFPE otherwise. */
4940 {
4942 {
4963 }
4964 }
4966 /* Equality comparisons of short modes against zero can be performed
4967 using the TST instruction with the appropriate bitmask. */
4973 /* Similarly, comparisons of zero_extends from shorter modes can
4974 be performed using an ANDS with an immediate mask. */
4990 /* A compare with a shifted operand. Because of canonicalization,
4991 the comparison will have to be swapped when we emit the assembly
4992 code. */
5000 /* Similarly for a negated operand, but we can only do this for
5001 equalities. */
5008 /* A test for unsigned overflow. */
5015 /* For everything else, return CCmode. */
5017 }
5019 static int
5022 int
5024 {
5031 }
5033 static int
5035 {
5037 {
5041 {
5055 }
5060 {
5072 }
5077 {
5089 }
5094 {
5100 }
5105 {
5109 }
5114 {
5118 }
5123 }
5126 }
5128 bool
5130 HOST_WIDE_INT minval,
5131 HOST_WIDE_INT maxval)
5132 {
5133 HOST_WIDE_INT firstval;
5150 }
5152 bool
5154 {
5156 }
5159 /* N Z C V. */
5160 #define AARCH64_CC_V 1
5161 #define AARCH64_CC_C (1 << 1)
5162 #define AARCH64_CC_Z (1 << 2)
5163 #define AARCH64_CC_N (1 << 3)
5165 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5167 {
5184 };
5186 /* Print operand X to file F in a target specific manner according to CODE.
5187 The acceptable formatting commands given by CODE are:
5188 'c': An integer or symbol address without a preceding #
5189 sign.
5190 'e': Print the sign/zero-extend size as a character 8->b,
5191 16->h, 32->w.
5192 'p': Prints N such that 2^N == X (X must be power of 2 and
5193 const int).
5194 'P': Print the number of non-zero bits in X (a const_int).
5195 'H': Print the higher numbered register of a pair (TImode)
5196 of regs.
5197 'm': Print a condition (eq, ne, etc).
5198 'M': Same as 'm', but invert condition.
5199 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5200 'S/T/U/V': Print a FP/SIMD register name for a register list.
5201 The register printed is the FP/SIMD register name
5202 of X + 0/1/2/3 for S/T/U/V.
5203 'R': Print a scalar FP/SIMD register name + 1.
5204 'X': Print bottom 16 bits of integer constant in hex.
5205 'w/x': Print a general register name or the zero register
5206 (32-bit or 64-bit).
5207 '0': Print a normal operand, if it's a general register,
5208 then we assume DImode.
5209 'k': Print NZCV for conditional compare instructions.
5210 'A': Output address constant representing the first
5211 argument of X, specifying a relocation offset
5212 if appropriate.
5213 'L': Output constant address specified by X
5214 with a relocation offset if appropriate.
5215 'G': Prints address of X, specifying a PC relative
5216 relocation mode if appropriate. */
5218 static void
5220 {
5222 {
5225 {
5237 {
5240 }
5241 /* Fall through. */
5245 }
5249 {
5254 {
5257 }
5260 {
5273 }
5274 }
5278 {
5282 {
5285 }
5288 }
5293 {
5296 }
5303 {
5306 }
5313 {
5315 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5317 {
5321 }
5324 {
5327 }
5334 }
5343 {
5344 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5346 }
5355 {
5356 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5358 }
5364 {
5365 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5367 }
5373 {
5376 }
5384 {
5387 }
5390 {
5393 }
5396 {
5399 }
5401 /* Fall through */
5405 {
5408 }
5411 {
5418 /* Check all memory references are Pmode - even with ILP32. */
5434 {
5437 HOST_WIDE_INT_MIN,
5438 HOST_WIDE_INT_MAX));
5440 }
5442 {
5444 }
5445 else
5450 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5451 be getting CONST_DOUBLEs holding integers. */
5454 {
5457 }
5459 {
5460 #define buf_size 20
5468 #undef buf_size
5469 }
5475 }
5483 {
5510 }
5516 {
5551 }
5557 {
5563 }
5568 {
5569 HOST_WIDE_INT cond_code;
5572 {
5575 }
5580 }
5586 }
5587 }
5589 static void
5591 {
5596 {
5600 else
5609 else
5618 else
5627 else
5634 {
5661 }
5672 }
5675 }
5677 bool
5679 {
5686 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5687 referencing instruction, but they are constant offsets, not
5688 symbols. */
5694 {
5696 {
5702 }
5705 }
5708 }
5710 /* Implement REGNO_REG_CLASS. */
5712 enum reg_class
5714 {
5729 }
5731 static rtx
5733 {
5734 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5735 where mask is selected by alignment and size of the offset.
5736 We try to pick as large a range for the offset as possible to
5737 maximize the chance of a CSE. However, for aligned addresses
5738 we limit the range to 4k so that structures with different sized
5739 elements are likely to use the same base. We need to be careful
5740 not to split a CONST for some forms of address expression, otherwise
5741 it will generate sub-optimal code. */
5744 {
5750 {
5754 /* Force any scaling into a temp for CSE. */
5758 /* Let the pointer register be in op0. */
5762 /* If the pointer is virtual or frame related, then we know that
5763 virtual register instantiation or register elimination is going
5764 to apply a second constant. We want the two constants folded
5765 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5767 {
5771 }
5773 /* Otherwise, in order to encourage CSE (and thence loop strength
5774 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5778 }
5780 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5781 HOST_WIDE_INT base_offset;
5784 /* For offsets aren't a multiple of the access size, the limit is
5785 -256...255. */
5787 {
5790 /* BLKmode typically uses LDP of X-registers. */
5793 }
5794 /* Small negative offsets are supported. */
5799 /* Use 12-bit offset by access size. */
5800 else
5804 {
5808 }
5809 }
5812 }
5814 /* Return the reload icode required for a constant pool in mode. */
5815 static enum insn_code
5817 {
5819 {
5855 }
5858 }
5859 static reg_class_t
5861 reg_class_t rclass,
5862 machine_mode mode,
5864 {
5866 /* If we have to disable direct literal pool loads and stores because the
5867 function is too big, then we need a scratch register. */
5872 {
5875 }
5877 /* Without the TARGET_SIMD instructions we cannot move a Q register
5878 to a Q register directly. We need a scratch. */
5882 {
5888 }
5890 /* A TFmode or TImode memory access should be handled via an FP_REGS
5891 because AArch64 has richer addressing modes for LDR/STR instructions
5892 than LDP/STP instructions. */
5901 }
5903 static bool
5905 {
5906 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5907 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5910 {
5922 }
5923 else
5924 {
5925 /* If we decided that we didn't need a leaf frame pointer but then used
5926 LR in the function, then we'll want a frame pointer after all, so
5927 prevent this elimination to ensure a frame pointer is used. */
5930 && flag_omit_leaf_frame_pointer
5933 }
5936 }
5938 HOST_WIDE_INT
5940 {
5944 {
5951 }
5954 {
5958 }
5961 }
5963 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5964 previous frame. */
5966 rtx
5968 {
5972 }
5975 static void
5977 {
5979 {
5982 }
5983 else
5984 {
5987 }
5992 }
5994 static void
5996 {
6000 /* Don't need to copy the trailing D-words, we fill those in below. */
6012 /* XXX We should really define a "clear_cache" pattern and use
6013 gen_clear_cache(). */
6018 ptr_mode);
6019 }
6021 static unsigned char
6023 {
6025 {
6033 return
6045 }
6047 }
6049 static reg_class_t
6051 {
6056 {
6062 }
6064 /* Register eliminiation can result in a request for
6065 SP+constant->FP_REGS. We cannot support such operations which
6066 use SP as source and an FP_REG as destination, so reject out
6067 right now. */
6069 {
6072 /* Look through a possible SUBREG introduced by ILP32. */
6078 POINTER_REGS));
6080 }
6083 }
6085 void
6087 {
6089 }
6091 static void
6093 {
6096 else
6097 {
6099 /* While priority is known to be in range [0, 65535], so 18 bytes
6100 would be enough, the compiler might not know that. To avoid
6101 -Wformat-truncation false positive, use a larger size. */
6108 }
6109 }
6111 static void
6113 {
6116 else
6117 {
6119 /* While priority is known to be in range [0, 65535], so 18 bytes
6120 would be enough, the compiler might not know that. To avoid
6121 -Wformat-truncation false positive, use a larger size. */
6128 }
6129 }
6133 {
6139 {
6140 {
6143 },
6144 {
6147 },
6148 {
6151 },
6152 /* We assume that DImode is only generated when not optimizing and
6153 that we don't really need 64-bit address offsets. That would
6154 imply an object file with 8GB of code in a single function! */
6155 {
6158 }
6159 };
6168 /* Need to implement table size reduction, by chaning the code below. */
6178 }
6181 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6182 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6183 operator. */
6185 int
6187 {
6189 {
6192 {
6196 }
6197 }
6199 }
6201 /* Constant pools are per function only when PC relative
6202 literal loads are true or we are in the large memory
6203 model. */
6207 {
6210 }
6212 static bool
6214 {
6215 /* Fixme:: In an ideal world this would work similar
6216 to the logic in aarch64_select_rtx_section but this
6217 breaks bootstrap in gcc go. For now we workaround
6218 this by returning false here. */
6220 }
6222 /* Select appropriate section for constants depending
6223 on where we place literal pools. */
6227 rtx x,
6229 {
6234 }
6236 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6237 void
6239 HOST_WIDE_INT offset)
6240 {
6241 /* When using per-function literal pools, we must ensure that any code
6242 section is aligned to the minimal instruction length, lest we get
6243 errors from the assembler re "unaligned instructions". */
6246 }
6248 /* Costs. */
6250 /* Helper function for rtx cost calculation. Strip a shift expression
6251 from X. Returns the inner operand if successful, or the original
6252 expression on failure. */
6253 static rtx
6255 {
6258 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6259 we can convert both to ROR during final output. */
6274 }
6276 /* Helper function for rtx cost calculation. Strip an extend
6277 expression from X. Returns the inner operand if successful, or the
6278 original expression on failure. We deal with a number of possible
6279 canonicalization variations here. If STRIP_SHIFT is true, then
6280 we can strip off a shift also. */
6281 static rtx
6283 {
6284 scalar_int_mode mode;
6290 /* Zero and sign extraction of a widened value. */
6298 /* It can also be represented (for zero-extend) as an AND with an
6299 immediate. */
6308 /* Now handle extended register, as this may also have an optional
6309 left shift by 1..4. */
6324 }
6326 /* Return true iff CODE is a shift supported in combination
6327 with arithmetic instructions. */
6329 static bool
6331 {
6333 }
6336 /* Return true iff X is a cheap shift without a sign extend. */
6338 static bool
6340 {
6366 }
6368 /* Helper function for rtx cost calculation. Calculate the cost of
6369 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6370 Return the calculated cost of the expression, recursing manually in to
6371 operands where needed. */
6373 static int
6375 {
6391 /* Integer multiply/fma. */
6393 {
6394 /* The multiply will be canonicalized as a shift, cost it as such. */
6398 {
6402 {
6404 {
6405 /* If the shift is considered cheap,
6406 then don't add any cost. */
6408 ;
6410 /* ARITH + shift-by-register. */
6413 /* ARITH + extended register. We don't have a cost field
6414 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6416 else
6417 /* ARITH + shift-by-immediate. */
6419 }
6420 else
6421 /* LSL (immediate). */
6424 }
6425 /* Strip extends as we will have costed them in the case above. */
6432 }
6434 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6435 compound and let the below cases handle it. After all, MNEG is a
6436 special-case alias of MSUB. */
6438 {
6441 }
6443 /* Integer multiplies or FMAs have zero/sign extending variants. */
6448 {
6453 {
6455 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6457 else
6458 /* MUL/SMULL/UMULL. */
6460 }
6463 }
6465 /* This is either an integer multiply or a MADD. In both cases
6466 we want to recurse and cost the operands. */
6471 {
6473 /* MADD/MSUB. */
6475 else
6476 /* MUL. */
6478 }
6481 }
6482 else
6483 {
6485 {
6486 /* Floating-point FMA/FMUL can also support negations of the
6487 operands, unless the rounding mode is upward or downward in
6488 which case FNMUL is different than FMUL with operand negation. */
6492 {
6497 }
6500 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6502 else
6503 /* FMUL/FNMUL. */
6505 }
6510 }
6511 }
6513 static int
6515 machine_mode mode,
6516 addr_space_t as ATTRIBUTE_UNUSED,
6518 {
6526 {
6528 {
6529 /* This is a CONST or SYMBOL ref which will be split
6530 in a different way depending on the code model in use.
6531 Cost it through the generic infrastructure. */
6533 /* Divide through by the cost of one instruction to
6534 bring it to the same units as the address costs. */
6536 /* The cost is then the cost of preparing the address,
6537 followed by an immediate (possibly 0) offset. */
6539 }
6540 else
6541 {
6542 /* This is most likely a jump table from a case
6543 statement. */
6545 }
6546 }
6549 {
6561 else
6580 }
6584 {
6585 /* For the sake of calculating the cost of the shifted register
6586 component, we can treat same sized modes in the same way. */
6588 {
6601 /* We can't tell, or this is a 128-bit vector. */
6605 }
6606 }
6609 }
6611 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6612 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6613 to be taken. */
6615 int
6617 {
6618 /* When optimizing for speed, use the cost of unpredictable branches. */
6624 else
6626 }
6628 /* Return true if the RTX X in mode MODE is a zero or sign extract
6629 usable in an ADD or SUB (extended register) instruction. */
6630 static bool
6632 {
6633 /* Catch add with a sign extract.
6634 This is add_<optab><mode>_multp2. */
6637 {
6648 op1))
6649 {
6651 }
6652 }
6653 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6654 No shift. */
6660 }
6662 static bool
6664 {
6666 {
6678 }
6679 }
6681 /* Return true iff X is an rtx that will match an extr instruction
6682 i.e. as described in the *extr<mode>5_insn family of patterns.
6683 OP0 and OP1 will be set to the operands of the shifts involved
6684 on success and will be NULL_RTX otherwise. */
6686 static bool
6688 {
6690 scalar_int_mode mode;
6705 {
6706 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6718 {
6722 }
6723 }
6726 }
6728 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6729 storing it in *COST. Result is true if the total cost of the operation
6730 has now been calculated. */
6731 static bool
6733 {
6734 rtx inner;
6735 rtx comparator;
6739 {
6743 }
6744 else
6745 {
6749 }
6752 {
6753 /* Conditional branch. */
6756 else
6757 {
6759 {
6761 {
6762 /* TBZ/TBNZ/CBZ/CBNZ. */
6764 /* TBZ/TBNZ. */
6767 else
6768 /* CBZ/CBNZ. */
6772 }
6773 }
6775 {
6776 /* TBZ/TBNZ. */
6779 }
6780 }
6781 }
6783 {
6784 /* CCMP. */
6786 {
6787 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6791 {
6798 else
6800 }
6802 }
6804 /* It's a conditional operation based on the status flags,
6805 so it must be some flavor of CSEL. */
6807 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6813 {
6814 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6817 }
6822 }
6824 /* We don't know what this is, cost all operands. */
6826 }
6828 /* Check whether X is a bitfield operation of the form shift + extend that
6829 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6830 operand to which the bitfield operation is applied. Otherwise return
6831 NULL_RTX. */
6833 static rtx
6835 {
6849 {
6867 }
6870 }
6872 /* Return true if the mask and a shift amount from an RTX of the form
6873 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6874 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6876 bool
6878 rtx shft_amnt)
6879 {
6884 }
6886 /* Calculate the cost of calculating X, storing it in *COST. Result
6887 is true if the total cost of the operation has now been calculated. */
6888 static bool
6891 {
6896 scalar_int_mode int_mode;
6898 /* By default, assume that everything has equivalent cost to the
6899 cheapest instruction. Any additional costs are applied as a delta
6900 above this default. */
6904 {
6906 /* The cost depends entirely on the operands to SET. */
6912 {
6915 {
6929 }
6938 /* Fall through. */
6940 /* The cost is one per vector-register copied. */
6942 {
6946 }
6947 /* const0_rtx is in general free, but we will use an
6948 instruction to set a register to 0. */
6950 {
6951 /* The cost is 1 per register copied. */
6955 }
6956 else
6957 /* Cost is just the cost of the RHS of the set. */
6963 /* Bit-field insertion. Strip any redundant widening of
6964 the RHS to meet the width of the target. */
6975 {
6976 /* MOV immediate is assumed to always be cheap. */
6978 }
6979 else
6980 {
6981 /* BFM. */
6985 }
6990 /* We can't make sense of this, assume default cost. */
6993 }
6997 /* If an instruction can incorporate a constant within the
6998 instruction, the instruction's expression avoids calling
6999 rtx_cost() on the constant. If rtx_cost() is called on a
7000 constant, then it is usually because the constant must be
7001 moved into a register by one or more instructions.
7003 The exception is constant 0, which can be expressed
7004 as XZR/WZR and is therefore free. The exception to this is
7005 if we have (set (reg) (const0_rtx)) in which case we must cost
7006 the move. However, we can catch that when we cost the SET, so
7007 we don't need to consider that here. */
7010 else
7011 {
7012 /* To an approximation, building any other constant is
7013 proportionally expensive to the number of instructions
7014 required to build that constant. This is true whether we
7015 are compiling for SPEED or otherwise. */
7020 }
7025 /* First determine number of instructions to do the move
7026 as an integer constant. */
7030 {
7036 ? SImode
7042 }
7045 {
7046 /* mov[df,sf]_aarch64. */
7048 /* FMOV (scalar immediate). */
7051 {
7052 /* This will be a load from memory. */
7055 else
7057 }
7058 else
7059 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7060 or MOV v0.s[0], wzr - neither of which are modeled by the
7061 cost tables. Just use the default cost. */
7062 {
7063 }
7064 }
7070 {
7071 /* For loads we want the base cost of a load, plus an
7072 approximation for the additional cost of the addressing
7073 mode. */
7087 }
7095 {
7097 {
7098 /* FNEG. */
7100 }
7102 }
7105 {
7108 {
7109 /* CSETM. */
7112 }
7114 /* Cost this as SUB wzr, X. */
7118 }
7121 {
7122 /* Support (neg(fma...)) as a single instruction only if
7123 sign of zeros is unimportant. This matches the decision
7124 making in aarch64.md. */
7126 {
7127 /* FNMADD. */
7130 }
7132 {
7133 /* FNMUL. */
7136 }
7138 /* FNEG. */
7141 }
7148 {
7151 else
7153 }
7163 {
7167 }
7170 {
7171 /* TODO: A write to the CC flags possibly costs extra, this
7172 needs encoding in the cost tables. */
7175 /* ANDS. */
7177 {
7180 }
7183 {
7184 /* ADDS (and CMN alias). */
7187 }
7190 {
7191 /* SUBS. */
7194 }
7199 {
7200 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7201 Handle it here directly rather than going to cost_logic
7202 since we know the immediate generated for the TST is valid
7203 so we can avoid creating an intermediate rtx for it only
7204 for costing purposes. */
7211 }
7214 {
7215 /* CMN. */
7222 }
7224 /* CMP.
7226 Compare can freely swap the order of operands, and
7227 canonicalization puts the more complex operation first.
7228 But the integer MINUS logic expects the shift/extend
7229 operation in op1. */
7232 {
7235 }
7237 }
7240 {
7241 /* FCMP. */
7246 {
7248 /* FCMP supports constant 0.0 for no extra cost. */
7250 }
7252 }
7255 {
7256 /* Vector compare. */
7261 {
7262 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7263 cost. */
7265 }
7267 }
7271 {
7275 cost_minus:
7278 /* Detect valid immediates. */
7284 {
7286 /* SUB(S) (immediate). */
7289 }
7291 /* Look for SUB (extended register). */
7294 {
7302 }
7306 /* Cost this as an FMA-alike operation. */
7310 {
7313 speed);
7315 }
7320 {
7322 {
7323 /* Vector SUB. */
7325 }
7327 {
7328 /* SUB(S). */
7330 }
7332 {
7333 /* FSUB. */
7335 }
7336 }
7338 }
7341 {
7342 rtx new_op0;
7347 cost_plus:
7350 {
7351 /* CSINC. */
7355 }
7360 {
7364 /* ADD (immediate). */
7367 }
7371 /* Look for ADD (extended register). */
7374 {
7382 }
7384 /* Strip any extend, leave shifts behind as we will
7385 cost them through mult_cost. */
7390 {
7392 speed);
7394 }
7399 {
7401 {
7402 /* Vector ADD. */
7404 }
7406 {
7407 /* ADD. */
7409 }
7411 {
7412 /* FADD. */
7414 }
7415 }
7417 }
7423 {
7426 else
7428 }
7433 {
7437 {
7440 else
7442 }
7444 }
7447 {
7454 }
7455 /* Fall through. */
7458 cost_logic:
7463 {
7467 }
7475 {
7476 /* This is a UBFM/SBFM. */
7481 }
7484 {
7486 {
7487 /* We have a mask + shift version of a UBFIZ
7488 i.e. the *andim_ashift<mode>_bfiz pattern. */
7492 {
7499 }
7501 {
7502 /* We possibly get the immediate for free, this is not
7503 modelled. */
7510 }
7511 }
7512 else
7513 {
7516 /* Handle ORN, EON, or BIC. */
7522 /* If we had a shift on op0 then this is a logical-shift-
7523 by-register/immediate operation. Otherwise, this is just
7524 a logical operation. */
7526 {
7528 {
7529 /* Shift by immediate. */
7532 else
7534 }
7535 else
7537 }
7539 /* In both cases we want to cost both operands. */
7546 }
7547 }
7555 {
7556 /* Vector NOT. */
7559 }
7561 /* MVN-shifted-reg. */
7563 {
7570 }
7571 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7572 Handle the second form here taking care that 'a' in the above can
7573 be a shift. */
7575 {
7584 {
7587 else
7589 }
7592 }
7593 /* MVN. */
7602 /* If a value is written in SI mode, then zero extended to DI
7603 mode, the operation will in general be free as a write to
7604 a 'w' register implicitly zeroes the upper bits of an 'x'
7605 register. However, if this is
7607 (set (reg) (zero_extend (reg)))
7609 we must cost the explicit register move. */
7613 {
7616 /* If OP_COST is non-zero, then the cost of the zero extend
7617 is effectively the cost of the inner operation. Otherwise
7618 we have a MOV instruction and we take the cost from the MOV
7619 itself. This is true independently of whether we are
7620 optimizing for space or time. */
7625 }
7627 {
7628 /* All loads can zero extend to any size for free. */
7631 }
7635 {
7640 }
7643 {
7645 {
7646 /* UMOV. */
7648 }
7649 else
7650 {
7651 /* We generate an AND instead of UXTB/UXTH. */
7653 }
7654 }
7659 {
7660 /* LDRSH. */
7662 {
7669 }
7671 }
7675 {
7680 }
7683 {
7686 else
7688 }
7696 {
7698 {
7700 {
7701 /* Vector shift (immediate). */
7703 }
7704 else
7705 {
7706 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7707 aliases. */
7709 }
7710 }
7712 /* We can incorporate zero/sign extend for free. */
7719 }
7720 else
7721 {
7723 {
7725 /* Vector shift (register). */
7727 }
7728 else
7729 {
7731 /* LSLV. */
7737 {
7739 /* We already demanded XEXP (op1, 0) to be REG_P, so
7740 don't recurse into it. */
7742 }
7743 }
7745 }
7755 {
7756 /* ASR (immediate) and friends. */
7758 {
7761 else
7763 }
7767 }
7768 else
7769 {
7771 {
7773 /* Vector shift (register). */
7775 }
7776 else
7777 {
7779 /* ASR (register) and friends. */
7785 {
7787 /* We already demanded XEXP (op1, 0) to be REG_P, so
7788 don't recurse into it. */
7790 }
7791 }
7793 }
7799 {
7800 /* LDR. */
7803 }
7806 {
7807 /* ADRP, followed by ADD. */
7811 }
7814 {
7815 /* ADR. */
7818 }
7821 {
7822 /* One extra load instruction, after accessing the GOT. */
7826 }
7831 /* ADRP/ADD (immediate). */
7838 /* UBFX/SBFX. */
7840 {
7843 else
7845 }
7847 /* We can trust that the immediates used will be correct (there
7848 are no by-register forms), so we need only cost op0. */
7854 /* aarch64_rtx_mult_cost always handles recursion to its
7855 operands. */
7859 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7860 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7861 an unconditional negate. This case should only ever be reached through
7862 the set_smod_pow2_cheap check in expmed.c. */
7866 {
7867 /* We expand to 4 instructions. Reset the baseline. */
7875 }
7877 /* Fall-through. */
7880 {
7881 /* Slighly prefer UMOD over SMOD. */
7888 }
7895 {
7899 /* There is no integer SQRT, so only DIV and UDIV can get
7900 here. */
7902 /* Slighly prefer UDIV over SDIV. */
7904 else
7906 }
7932 {
7935 else
7937 }
7939 /* FMSUB, FNMADD, and FNMSUB are free. */
7946 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7947 and the by-element operand as operand 0. */
7951 /* Catch vector-by-element operations. The by-element operand can
7952 either be (vec_duplicate (vec_select (x))) or just
7953 (vec_select (x)), depending on whether we are multiplying by
7954 a vector or a scalar.
7956 Canonicalization is not very good in these cases, FMA4 will put the
7957 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7968 /* If the remaining parameters are not registers,
7969 get the cost to put them into registers. */
7983 {
7985 {
7986 /*Vector truncate. */
7988 }
7989 else
7991 }
7996 {
7998 {
7999 /*Vector conversion. */
8001 }
8002 else
8004 }
8010 /* Strip the rounding part. They will all be implemented
8011 by the fcvt* family of instructions anyway. */
8013 {
8022 }
8025 {
8028 else
8030 }
8032 /* We can combine fmul by a power of 2 followed by a fcvt into a single
8033 fixed-point fcvt. */
8038 {
8042 }
8049 {
8050 /* ABS (vector). */
8053 }
8055 {
8058 /* FABD, which is analogous to FADD. */
8060 {
8067 }
8068 /* Simple FABS is analogous to FNEG. */
8071 }
8072 else
8073 {
8074 /* Integer ABS will either be split to
8075 two arithmetic instructions, or will be an ABS
8076 (scalar), which we don't model. */
8080 }
8086 {
8089 else
8090 {
8091 /* FMAXNM/FMINNM/FMAX/FMIN.
8092 TODO: This may not be accurate for all implementations, but
8093 we do not model this in the cost tables. */
8095 }
8096 }
8100 /* The floating point round to integer frint* instructions. */
8102 {
8107 }
8110 {
8115 }
8120 /* Decompose <su>muldi3_highpart. */
8122 mode == DImode
8123 /* (lshiftrt:TI */
8126 /* (mult:TI */
8128 /* (ANY_EXTEND:TI (reg:DI))
8129 (ANY_EXTEND:TI (reg:DI))) */
8136 /* (const_int 64) */
8139 {
8140 /* UMULH/SMULH. */
8148 }
8150 /* Fall through. */
8153 }
8161 }
8163 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8164 calculated for X. This cost is stored in *COST. Returns true
8165 if the total cost of X was calculated. */
8166 static bool
8169 {
8174 {
8179 }
8182 }
8184 static int
8187 {
8193 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8200 /* Moving between GPR and stack cost is the same as GP2GP. */
8205 /* To/From the stack register, we move via the gprs. */
8211 {
8212 /* 128-bit operations on general registers require 2 instructions. */
8220 /* When AdvSIMD instructions are disabled it is not possible to move
8221 a 128-bit value directly between Q registers. This is handled in
8222 secondary reload. A general register is used as a scratch to move
8223 the upper DI value and the lower DI value is moved directly,
8224 hence the cost is the sum of three moves. */
8229 }
8239 }
8241 static int
8243 reg_class_t rclass ATTRIBUTE_UNUSED,
8245 {
8247 }
8249 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8250 to optimize 1.0/sqrt. */
8252 static bool
8254 {
8256 && flag_unsafe_math_optimizations
8260 }
8262 /* Function to decide when to use the approximate reciprocal square root
8263 builtin. */
8265 static tree
8267 {
8273 }
8277 /* Select reciprocal square root initial estimate insn depending on machine
8278 mode. */
8280 static rsqrte_type
8282 {
8284 {
8291 }
8292 }
8296 /* Select reciprocal square root series step insn depending on machine mode. */
8298 static rsqrts_type
8300 {
8302 {
8309 }
8310 }
8312 /* Emit instruction sequence to compute either the approximate square root
8313 or its approximate reciprocal, depending on the flag RECP, and return
8314 whether the sequence was emitted or not. */
8316 bool
8318 {
8322 {
8325 }
8328 {
8335 || flag_trapping_math
8336 || !flag_unsafe_math_optimizations
8339 }
8340 else
8341 /* Caller assumes we cannot fail. */
8347 /* When calculating the approximate square root, compare the
8348 argument with 0.0 and create a mask. */
8354 /* Estimate the approximate reciprocal square root. */
8358 /* Iterate over the series twice for SF and thrice for DF. */
8361 /* Optionally iterate over the series once less for faster performance
8362 while sacrificing the accuracy. */
8365 iterations--;
8367 /* Iterate over the series to calculate the approximate reciprocal square
8368 root. */
8371 {
8379 }
8382 {
8383 /* Qualify the approximate reciprocal square root when the argument is
8384 0.0 by squashing the intermediary result to 0.0. */
8390 /* Calculate the approximate square root. */
8392 }
8394 /* Finalize the approximation. */
8398 }
8402 /* Select reciprocal initial estimate insn depending on machine mode. */
8404 static recpe_type
8406 {
8408 {
8415 }
8416 }
8420 /* Select reciprocal series step insn depending on machine mode. */
8422 static recps_type
8424 {
8426 {
8433 }
8434 }
8436 /* Emit the instruction sequence to compute the approximation for the division
8437 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8439 bool
8441 {
8452 || flag_trapping_math
8453 || !flag_unsafe_math_optimizations
8458 /* Estimate the approximate reciprocal. */
8462 /* Iterate over the series twice for SF and thrice for DF. */
8465 /* Optionally iterate over the series once less for faster performance,
8466 while sacrificing the accuracy. */
8468 iterations--;
8470 /* Iterate over the series to calculate the approximate reciprocal. */
8473 {
8478 }
8481 {
8482 /* As the approximate reciprocal of DEN is already calculated, only
8483 calculate the approximate division when NUM is not 1.0. */
8486 }
8488 /* Finalize the approximation. */
8491 }
8493 /* Return the number of instructions that can be issued per cycle. */
8494 static int
8496 {
8498 }
8500 static int
8502 {
8506 }
8509 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8510 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8511 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8513 static int
8516 {
8518 }
8521 /* Vectorizer cost model target hooks. */
8523 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8524 static int
8526 tree vectype,
8528 {
8537 {
8588 }
8589 }
8591 /* Implement targetm.vectorize.add_stmt_cost. */
8592 static unsigned
8596 {
8601 {
8606 /* Statements in an inner loop relative to the loop being
8607 vectorized are weighted more heavily. The value here is
8608 arbitrary and could potentially be improved with analysis. */
8614 }
8617 }
8621 /* Parse the TO_PARSE string and put the architecture struct that it
8622 selects into RES and the architectural features into ISA_FLAGS.
8623 Return an aarch64_parse_opt_result describing the parse result.
8624 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8626 static enum aarch64_parse_opt_result
8629 {
8641 else
8648 /* Loop through the list of supported ARCHes to find a match. */
8650 {
8652 {
8656 {
8657 /* TO_PARSE string contains at least one extension. */
8658 enum aarch64_parse_opt_result ext_res
8663 }
8664 /* Extension parsing was successful. Confirm the result
8665 arch and ISA flags. */
8669 }
8670 }
8672 /* ARCH name not found in list. */
8674 }
8676 /* Parse the TO_PARSE string and put the result tuning in RES and the
8677 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8678 describing the parse result. If there is an error parsing, RES and
8679 ISA_FLAGS are left unchanged. */
8681 static enum aarch64_parse_opt_result
8684 {
8696 else
8703 /* Loop through the list of supported CPUs to find a match. */
8705 {
8707 {
8712 {
8713 /* TO_PARSE string contains at least one extension. */
8714 enum aarch64_parse_opt_result ext_res
8719 }
8720 /* Extension parsing was successfull. Confirm the result
8721 cpu and ISA flags. */
8725 }
8726 }
8728 /* CPU name not found in list. */
8730 }
8732 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8733 Return an aarch64_parse_opt_result describing the parse result.
8734 If the parsing fails the RES does not change. */
8736 static enum aarch64_parse_opt_result
8738 {
8744 /* Loop through the list of supported CPUs to find a match. */
8746 {
8748 {
8751 }
8752 }
8754 /* CPU name not found in list. */
8756 }
8758 /* Parse TOKEN, which has length LENGTH to see if it is an option
8759 described in FLAG. If it is, return the index bit for that fusion type.
8760 If not, error (printing OPTION_NAME) and return zero. */
8762 static unsigned int
8767 {
8769 {
8773 }
8777 }
8779 /* Parse OPTION which is a comma-separated list of flags to enable.
8780 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8781 default state we inherit from the CPU tuning structures. OPTION_NAME
8782 gives the top-level option we are parsing in the -moverride string,
8783 for use in error messages. */
8785 static unsigned int
8790 {
8797 {
8800 token_length,
8801 flags,
8802 option_name);
8803 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8804 in the token stream, reset the supported operations. So:
8806 adrp+add.cmp+branch.none.adrp+add
8808 would have the result of turning on only adrp+add fusion. */
8814 }
8816 /* We ended with a comma, print something. */
8818 {
8821 }
8823 /* We still have one more token to parse. */
8826 token_length,
8827 flags,
8828 option_name);
8834 }
8836 /* Support for overriding instruction fusion. */
8838 static void
8841 {
8843 aarch64_fusible_pairs,
8846 }
8848 /* Support for overriding other tuning flags. */
8850 static void
8853 {
8854 tune->extra_tuning_flags
8856 aarch64_tuning_flags,
8859 }
8861 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8862 we understand. If it is, extract the option string and handoff to
8863 the appropriate function. */
8865 void
8869 {
8875 {
8878 }
8880 /* Get the length of the option name. */
8882 /* Skip the '=' to get to the option string. */
8883 option_part++;
8886 {
8888 {
8891 }
8892 }
8896 }
8898 /* A checking mechanism for the implementation of the tls size. */
8900 static void
8902 {
8907 {
8909 /* Both the default and maximum TLS size allowed under tiny is 1M which
8910 needs two instructions to address, so we clamp the size to 24. */
8915 /* The maximum TLS size allowed under small is 4G. */
8920 /* The maximum TLS size allowed under large is 16E.
8921 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8927 }
8930 }
8932 /* Parse STRING looking for options in the format:
8933 string :: option:string
8934 option :: name=substring
8935 name :: {a-z}
8936 substring :: defined by option. */
8938 static void
8941 {
8952 {
8954 /* Make this substring look like a string. */
8958 }
8960 /* One last option to parse. */
8963 }
8966 static void
8968 {
8969 /* PR 70044: We have to be careful about being called multiple times for the
8970 same function. This means all changes should be repeatable. */
8972 /* If the frame pointer is enabled, set it to a special value that behaves
8973 similar to frame pointer omission. If we don't do this all leaf functions
8974 will get a frame pointer even if flag_omit_leaf_frame_pointer is set.
8975 If flag_omit_frame_pointer has this special value, we must force the
8976 frame pointer if not in a leaf function. We also need to force it in a
8977 leaf function if flag_omit_frame_pointer is not set or if LR is used. */
8981 /* If not optimizing for size, set the default
8982 alignment to what the target wants. */
8984 {
8991 }
8993 /* We default to no pc-relative literal loads. */
8997 /* If -mpc-relative-literal-loads is set on the command line, this
8998 implies that the user asked for PC relative literal loads. */
9002 /* In the tiny memory model it makes no sense to disallow PC relative
9003 literal pool loads. */
9008 /* When enabling the lower precision Newton series for the square root, also
9009 enable it for the reciprocal square root, since the latter is an
9010 intermediary step for the former. */
9013 }
9015 /* 'Unpack' up the internal tuning structs and update the options
9016 in OPTS. The caller must have set up selected_tune and selected_arch
9017 as all the other target-specific codegen decisions are
9018 derived from them. */
9020 void
9022 {
9025 /* Make a copy of the tuning parameters attached to the core, which
9026 we may later overwrite. */
9034 /* This target defaults to strict volatile bitfields. */
9043 {
9055 }
9057 /* We don't mind passing in global_options_set here as we don't use
9058 the *options_set structs anyway. */
9060 queue_depth,
9064 /* Set up parameters to be used in prefetching algorithm. Do not
9065 override the defaults unless we are tuning for a core we have
9066 researched values for. */
9088 /* Enable sw prefetching at specified optimization level for
9089 CPUS that have prefetch. Lower optimization level threshold by 1
9090 when profiling is enabled. */
9098 }
9100 /* Print a hint with a suggestion for a core or architecture name that
9101 most closely resembles what the user passed in STR. ARCH is true if
9102 the user is asking for an architecture name. ARCH is false if the user
9103 is asking for a core name. */
9105 static void
9107 {
9118 }
9120 /* Print a hint with a suggestion for a core name that most closely resembles
9121 what the user passed in STR. */
9125 {
9127 }
9129 /* Print a hint with a suggestion for an architecture name that most closely
9130 resembles what the user passed in STR. */
9134 {
9136 }
9138 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9139 specified in STR and throw errors if appropriate. Put the results if
9140 they are valid in RES and ISA_FLAGS. Return whether the option is
9141 valid. */
9143 static bool
9146 {
9147 enum aarch64_parse_opt_result parse_res
9154 {
9167 }
9170 }
9172 /* Validate a command-line -march option. Parse the arch and extensions
9173 (if any) specified in STR and throw errors if appropriate. Put the
9174 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9175 option is valid. */
9177 static bool
9180 {
9181 enum aarch64_parse_opt_result parse_res
9188 {
9201 }
9204 }
9206 /* Validate a command-line -mtune option. Parse the cpu
9207 specified in STR and throw errors if appropriate. Put the
9208 result, if it is valid, in RES. Return whether the option is
9209 valid. */
9211 static bool
9213 {
9214 enum aarch64_parse_opt_result parse_res
9221 {
9231 }
9233 }
9235 /* Return the CPU corresponding to the enum CPU.
9236 If it doesn't specify a cpu, return the default. */
9240 {
9244 /* The & 0x3f is to extract the bottom 6 bits that encode the
9245 default cpu as selected by the --with-cpu GCC configure option
9246 in config.gcc.
9247 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9248 flags mechanism should be reworked to make it more sane. */
9250 }
9252 /* Return the architecture corresponding to the enum ARCH.
9253 If it doesn't specify a valid architecture, return the default. */
9257 {
9264 }
9266 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9267 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9268 tuning structs. In particular it must set selected_tune and
9269 aarch64_isa_flags that define the available ISA features and tuning
9270 decisions. It must also set selected_arch as this will be used to
9271 output the .arch asm tags for each function. */
9273 static void
9275 {
9288 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9289 If either of -march or -mtune is given, they override their
9290 respective component of -mcpu. */
9302 /* If the user did not specify a processor, choose the default
9303 one for them. This will be the CPU set during configuration using
9304 --with-cpu, otherwise it is "generic". */
9306 {
9308 {
9312 }
9313 else
9314 {
9315 /* Get default configure-time CPU. */
9318 }
9322 }
9323 /* If both -mcpu and -march are specified check that they are architecturally
9324 compatible, warn if they're not and prefer the -march ISA flags. */
9326 {
9328 {
9332 }
9337 }
9338 else
9339 {
9340 /* -mcpu but no -march. */
9347 }
9349 /* Set the arch as well as we will need it when outputing
9350 the .arch directive in assembly. */
9352 {
9355 }
9360 #ifndef HAVE_AS_MABI_OPTION
9361 /* The compiler may have been configured with 2.23.* binutils, which does
9362 not have support for ILP32. */
9365 #endif
9370 /* Make sure we properly set up the explicit options. */
9381 /* Save these options as the default ones in case we push and pop them later
9382 while processing functions with potential target attributes. */
9383 target_option_default_node = target_option_current_node
9385 }
9387 /* Implement targetm.override_options_after_change. */
9389 static void
9391 {
9393 }
9397 {
9401 }
9403 void
9405 {
9407 }
9409 /* A checking mechanism for the implementation of the various code models. */
9410 static void
9412 {
9414 {
9416 {
9421 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9423 ? AARCH64_CMODEL_SMALL_PIC
9425 #else
9427 #endif
9435 }
9436 }
9437 else
9439 }
9441 /* Implement TARGET_OPTION_SAVE. */
9443 static void
9445 {
9447 }
9449 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9450 using the information saved in PTR. */
9452 static void
9454 {
9462 }
9464 /* Implement TARGET_OPTION_PRINT. */
9466 static void
9468 {
9479 }
9483 void
9485 {
9487 }
9489 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9490 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9491 make sure optab availability predicates are recomputed when necessary. */
9493 void
9495 {
9500 else
9502 }
9504 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9505 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9506 of the function, if such exists. This function may be called multiple
9507 times on a single function so use aarch64_previous_fndecl to avoid
9508 setting up identical state. */
9510 static void
9512 {
9516 tree old_tree = (aarch64_previous_fndecl
9522 /* If current function has no attributes but the previous one did,
9523 use the default node. */
9527 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9528 the default have been handled by aarch64_save_restore_target_globals from
9529 aarch64_pragma_target_parse. */
9535 /* First set the target options. */
9539 }
9541 /* Enum describing the various ways we can handle attributes.
9542 In many cases we can reuse the generic option handling machinery. */
9544 enum aarch64_attr_opt_type
9545 {
9549 aarch64_attr_custom /* Attribute requires a custom handling function. */
9550 };
9552 /* All the information needed to handle a target attribute.
9553 NAME is the name of the attribute.
9554 ATTR_TYPE specifies the type of behavior of the attribute as described
9555 in the definition of enum aarch64_attr_opt_type.
9556 ALLOW_NEG is true if the attribute supports a "no-" form.
9557 HANDLER is the function that takes the attribute string and whether
9558 it is a pragma or attribute and handles the option. It is needed only
9559 when the ATTR_TYPE is aarch64_attr_custom.
9560 OPT_NUM is the enum specifying the option that the attribute modifies.
9561 This is needed for attributes that mirror the behavior of a command-line
9562 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9563 aarch64_attr_enum. */
9565 struct aarch64_attribute_info
9566 {
9572 };
9574 /* Handle the ARCH_STR argument to the arch= target attribute.
9575 PRAGMA_OR_ATTR is used in potential error messages. */
9577 static bool
9579 {
9581 enum aarch64_parse_opt_result parse_res
9585 {
9590 }
9593 {
9607 }
9610 }
9612 /* Handle the argument CPU_STR to the cpu= target attribute.
9613 PRAGMA_OR_ATTR is used in potential error messages. */
9615 static bool
9617 {
9619 enum aarch64_parse_opt_result parse_res
9623 {
9631 }
9634 {
9648 }
9651 }
9653 /* Handle the argument STR to the tune= target attribute.
9654 PRAGMA_OR_ATTR is used in potential error messages. */
9656 static bool
9658 {
9660 enum aarch64_parse_opt_result parse_res
9664 {
9669 }
9672 {
9679 }
9682 }
9684 /* Parse an architecture extensions target attribute string specified in STR.
9685 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9686 if successful. Update aarch64_isa_flags to reflect the ISA features
9687 modified.
9688 PRAGMA_OR_ATTR is used in potential error messages. */
9690 static bool
9692 {
9696 /* We allow "+nothing" in the beginning to clear out all architectural
9697 features if the user wants to handpick specific features. */
9699 {
9702 }
9707 {
9710 }
9713 {
9726 }
9729 }
9731 /* The target attributes that we support. On top of these we also support just
9732 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9733 handled explicitly in aarch64_process_one_target_attr. */
9736 {
9738 OPT_mgeneral_regs_only },
9740 OPT_mfix_cortex_a53_835769 },
9742 OPT_mfix_cortex_a53_843419 },
9746 OPT_momit_leaf_frame_pointer },
9749 OPT_march_ },
9752 OPT_mtune_ },
9754 OPT_msign_return_address_ },
9756 };
9758 /* Parse ARG_STR which contains the definition of one target attribute.
9759 Show appropriate errors if any or return true if the attribute is valid.
9760 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9761 we're processing a target attribute or pragma. */
9763 static bool
9765 {
9771 {
9774 }
9779 /* Skip leading whitespace. */
9781 str_to_check++;
9783 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9784 It is easier to detect and handle it explicitly here rather than going
9785 through the machinery for the rest of the target attributes in this
9786 function. */
9791 {
9794 }
9797 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9798 and point ARG to "foo". */
9800 {
9802 arg++;
9803 }
9807 {
9808 /* If the names don't match up, or the user has given an argument
9809 to an attribute that doesn't accept one, or didn't give an argument
9810 to an attribute that expects one, fail to match. */
9819 {
9823 }
9825 /* If the name matches but the attribute does not allow "no-" versions
9826 then we can't match. */
9828 {
9832 }
9835 {
9836 /* Has a custom handler registered.
9837 For example, cpu=, arch=, tune=. */
9844 /* Either set or unset a boolean option. */
9846 {
9854 }
9855 /* Set or unset a bit in the target_flags. aarch64_handle_option
9856 should know what mask to apply given the option number. */
9858 {
9860 /* We only need to specify the option number.
9861 aarch64_handle_option will know which mask to apply. */
9867 }
9868 /* Use the option setting machinery to set an option to an enum. */
9870 {
9877 {
9880 global_dc);
9881 }
9882 else
9883 {
9886 }
9888 }
9891 }
9892 }
9894 /* If we reached here we either have found an attribute and validated
9895 it or didn't match any. If we matched an attribute but its arguments
9896 were malformed we will have returned false already. */
9898 }
9900 /* Count how many times the character C appears in
9901 NULL-terminated string STR. */
9903 static unsigned int
9905 {
9908 {
9910 res++;
9912 str++;
9913 }
9916 }
9918 /* Parse the tree in ARGS that contains the target attribute information
9919 and update the global target options space. PRAGMA_OR_ATTR is a string
9920 to be used in error messages, specifying whether this is processing
9921 a target attribute or a target pragma. */
9923 bool
9925 {
9927 {
9928 do
9929 {
9932 {
9935 }
9940 }
9943 {
9946 }
9953 {
9956 }
9958 /* Used to catch empty spaces between commas i.e.
9959 attribute ((target ("attr1,,attr2"))). */
9962 /* Handle multiple target attributes separated by ','. */
9967 {
9968 num_attrs++;
9970 {
9973 }
9976 }
9979 {
9983 }
9986 }
9988 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9989 process attribute ((target ("..."))). */
9991 static bool
9993 {
9996 tree old_optimize;
10000 /* If what we're processing is the current pragma string then the
10001 target option node is already stored in target_option_current_node
10002 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
10003 having to re-parse the string. This is especially useful to keep
10004 arm_neon.h compile times down since that header contains a lot
10005 of intrinsics enclosed in pragmas. */
10007 {
10010 }
10016 /* If the function changed the optimization levels as well as setting
10017 target options, start with the optimizations specified. */
10022 /* Save the current target options to restore at the end. */
10025 /* If fndecl already has some target attributes applied to it, unpack
10026 them so that we add this attribute on top of them, rather than
10027 overwriting them. */
10029 {
10035 }
10036 else
10043 /* Set up any additional state. */
10045 {
10047 /* Initialize SIMD builtins if we haven't already.
10048 Set current_target_pragma to NULL for the duration so that
10049 the builtin initialization code doesn't try to tag the functions
10050 being built with the attributes specified by any current pragma, thus
10051 going into an infinite recursion. */
10053 {
10058 }
10060 }
10061 else
10067 {
10072 }
10080 }
10082 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10083 tri-bool options (yes, no, don't care) and the default value is
10084 DEF, determine whether to reject inlining. */
10086 static bool
10089 {
10090 /* If the callee doesn't care, always allow inlining. */
10094 /* If the caller doesn't care, always allow inlining. */
10098 /* Otherwise, allow inlining if either the callee and caller values
10099 agree, or if the callee is using the default value. */
10101 }
10103 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10104 to inline CALLEE into CALLER based on target-specific info.
10105 Make sure that the caller and callee have compatible architectural
10106 features. Then go through the other possible target attributes
10107 and see if they can block inlining. Try not to reject always_inline
10108 callees unless they are incompatible architecturally. */
10110 static bool
10112 {
10116 /* If callee has no option attributes, then it is ok to inline. */
10127 /* Callee's ISA flags should be a subset of the caller's. */
10132 /* Allow non-strict aligned functions inlining into strict
10133 aligned ones. */
10143 /* If the architectural features match up and the callee is always_inline
10144 then the other attributes don't matter. */
10156 /* Honour explicit requests to workaround errata. */
10169 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10170 caller and calle and they don't match up, reject inlining. */
10177 /* If the callee has specific tuning overrides, respect them. */
10182 /* If the user specified tuning override strings for the
10183 caller and callee and they don't match up, reject inlining.
10184 We just do a string compare here, we don't analyze the meaning
10185 of the string, as it would be too costly for little gain. */
10193 }
10195 /* Return true if SYMBOL_REF X binds locally. */
10197 static bool
10199 {
10203 }
10205 /* Return true if SYMBOL_REF X is thread local */
10206 static bool
10208 {
10216 }
10218 /* Classify a TLS symbol into one of the TLS kinds. */
10219 enum aarch64_symbol_type
10221 {
10225 {
10232 {
10238 }
10249 else
10258 }
10259 }
10261 /* Return the method that should be used to access SYMBOL_REF or
10262 LABEL_REF X. */
10264 enum aarch64_symbol_type
10266 {
10268 {
10270 {
10285 }
10286 }
10289 {
10294 {
10296 /* When we retrieve symbol + offset address, we have to make sure
10297 the offset does not cause overflow of the final address. But
10298 we have no way of knowing the address of symbol at compile time
10299 so we can't accurately say if the distance between the PC and
10300 symbol + offset is outside the addressible range of +/-1M in the
10301 TINY code model. So we rely on images not being greater than
10302 1M and cap the offset at 1M and anything beyond 1M will have to
10303 be loaded using an alternative mechanism. Furthermore if the
10304 symbol is a weak reference to something that isn't known to
10305 resolve to a symbol in this module, then force to memory. */
10313 /* Same reasoning as the tiny code model, but the offset cap here is
10314 4G. */
10335 /* This is alright even in PIC code as the constant
10336 pool reference is always PC relative and within
10337 the same translation unit. */
10340 else
10345 }
10346 }
10348 /* By default push everything into the constant pool. */
10350 }
10352 bool
10354 {
10356 }
10358 bool
10360 {
10368 }
10370 /* Return true if X holds either a quarter-precision or
10371 floating-point +0.0 constant. */
10372 static bool
10374 {
10378 /* This call determines which constants can be used in mov<mode>
10379 as integer moves instead of constant loads. */
10384 }
10386 static bool
10388 {
10389 /* Do not allow vector struct mode constants. We could support
10390 0 and -1 easily, but they need support in aarch64-simd.md. */
10394 /* For these cases we never want to use a literal load.
10395 As such we have to prevent the compiler from forcing these
10396 to memory. */
10409 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10410 so spilling them is better than rematerialization. */
10415 }
10417 rtx
10419 {
10425 /* Can return in any reg. */
10428 }
10430 /* On AAPCS systems, this is the "struct __va_list". */
10433 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10434 Return the type to use as __builtin_va_list.
10436 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10438 struct __va_list
10439 {
10440 void *__stack;
10441 void *__gr_top;
10442 void *__vr_top;
10443 int __gr_offs;
10444 int __vr_offs;
10445 }; */
10447 static tree
10449 {
10450 tree va_list_name;
10453 /* Create the type. */
10455 /* Give it the required name. */
10457 TYPE_DECL,
10459 va_list_type);
10464 /* Create the fields. */
10467 ptr_type_node);
10470 ptr_type_node);
10473 ptr_type_node);
10476 integer_type_node);
10479 integer_type_node);
10481 /* Tell tree-stdarg pass about our internal offset fields.
10482 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10483 purpose to identify whether the code is updating va_list internal
10484 offset fields through irregular way. */
10506 /* Compute its layout. */
10510 }
10512 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10513 static void
10515 {
10519 tree t;
10533 {
10536 }
10545 NULL_TREE);
10547 NULL_TREE);
10549 NULL_TREE);
10551 NULL_TREE);
10553 NULL_TREE);
10555 /* Emit code to initialize STACK, which points to the next varargs stack
10556 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10557 by named arguments. STACK is 8-byte aligned. */
10564 /* Emit code to initialize GRTOP, the top of the GR save area.
10565 virtual_incoming_args_rtx should have been 16 byte aligned. */
10570 /* Emit code to initialize VRTOP, the top of the VR save area.
10571 This address is gr_save_area_bytes below GRTOP, rounded
10572 down to the next 16-byte boundary. */
10582 /* Emit code to initialize GROFF, the offset from GRTOP of the
10583 next GPR argument. */
10588 /* Likewise emit code to initialize VROFF, the offset from FTOP
10589 of the next VR argument. */
10593 }
10595 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10597 static tree
10600 {
10601 tree addr;
10607 machine_mode mode;
10634 type,
10638 {
10639 /* TYPE passed in fp/simd registers. */
10651 {
10654 }
10657 {
10659 }
10660 }
10661 else
10662 {
10663 /* TYPE passed in general registers. */
10676 {
10678 }
10679 }
10681 /* Get a local temporary for the field value. */
10684 /* Emit code to branch if off >= 0. */
10690 {
10691 /* Emit: offs = (offs + 15) & -16. */
10697 }
10698 else
10701 /* Update ap.__[g|v]r_offs */
10706 /* String up. */
10710 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10715 /* String up: make sure the assignment happens before the use. */
10719 /* Prepare the trees handling the argument that is passed on the stack;
10720 the top level node will store in ON_STACK. */
10723 {
10724 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10732 }
10733 else
10735 /* Advance ap.__stack */
10743 /* String up roundup and advance. */
10746 /* String up with arg */
10748 /* Big-endianness related address adjustment. */
10751 {
10755 }
10760 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10770 {
10771 /* type ha; // treat as "struct {ftype field[n];}"
10772 ... [computing offs]
10773 for (i = 0; i <nregs; ++i, offs += 16)
10774 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10775 return ha; */
10779 /* Declare a local variable. */
10783 /* Establish the base type. */
10785 {
10804 {
10808 }
10812 }
10814 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10822 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10824 {
10834 }
10838 }
10848 }
10850 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10852 static void
10856 {
10858 CUMULATIVE_ARGS local_cum;
10862 /* The caller has advanced CUM up to, but not beyond, the last named
10863 argument. Advance a local copy of CUM past the last "real" named
10864 argument, to find out how many registers are left over. */
10868 /* Found out how many registers we need to save.
10869 Honor tree-stdvar analysis results. */
10878 {
10881 }
10884 {
10886 {
10889 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10897 }
10899 {
10900 /* We can't use move_block_from_reg, because it will use
10901 the wrong mode, storing D regs only. */
10905 /* Set OFF to the offset from virtual_incoming_args_rtx of
10906 the first vector register. The VR save area lies below
10907 the GR one, and is aligned to 16 bytes. */
10914 {
10922 }
10923 }
10924 }
10926 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10927 any complication of having crtl->args.pretend_args_size changed. */
10932 }
10934 static void
10936 {
10939 {
10941 {
10944 }
10945 }
10946 }
10948 /* Walk down the type tree of TYPE counting consecutive base elements.
10949 If *MODEP is VOIDmode, then set it to the first valid floating point
10950 type. If a non-floating point type is found, or if a floating point
10951 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10952 otherwise return the count in the sub-tree. */
10953 static int
10955 {
10956 machine_mode mode;
10957 HOST_WIDE_INT size;
10960 {
10990 /* Use V2SImode and V4SImode as representatives of all 64-bit
10991 and 128-bit vector types. */
10994 {
11003 }
11008 /* Vector modes are considered to be opaque: two vectors are
11009 equivalent for the purposes of being homogeneous aggregates
11010 if they are the same size. */
11017 {
11021 /* Can't handle incomplete types nor sizes that are not
11022 fixed. */
11029 || !index
11040 /* There must be no padding. */
11046 }
11049 {
11052 tree field;
11054 /* Can't handle incomplete types nor sizes that are not
11055 fixed. */
11061 {
11069 }
11071 /* There must be no padding. */
11077 }
11081 {
11082 /* These aren't very interesting except in a degenerate case. */
11085 tree field;
11087 /* Can't handle incomplete types nor sizes that are not
11088 fixed. */
11094 {
11102 }
11104 /* There must be no padding. */
11110 }
11114 }
11117 }
11119 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11120 type as described in AAPCS64 \S 4.1.2.
11122 See the comment above aarch64_composite_type_p for the notes on MODE. */
11124 static bool
11126 machine_mode mode)
11127 {
11137 }
11139 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11140 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11141 array types. The C99 floating-point complex types are also considered
11142 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11143 types, which are GCC extensions and out of the scope of AAPCS64, are
11144 treated as composite types here as well.
11146 Note that MODE itself is not sufficient in determining whether a type
11147 is such a composite type or not. This is because
11148 stor-layout.c:compute_record_mode may have already changed the MODE
11149 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11150 structure with only one field may have its MODE set to the mode of the
11151 field. Also an integer mode whose size matches the size of the
11152 RECORD_TYPE type may be used to substitute the original mode
11153 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11154 solely relied on. */
11156 static bool
11158 machine_mode mode)
11159 {
11172 }
11174 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11175 shall be passed or returned in simd/fp register(s) (providing these
11176 parameter passing registers are available).
11178 Upon successful return, *COUNT returns the number of needed registers,
11179 *BASE_MODE returns the mode of the individual register and when IS_HAF
11180 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11181 floating-point aggregate or a homogeneous short-vector aggregate. */
11183 static bool
11185 const_tree type,
11189 {
11197 {
11200 }
11202 {
11206 }
11208 {
11212 {
11215 }
11216 else
11218 }
11219 else
11224 }
11226 /* Implement TARGET_STRUCT_VALUE_RTX. */
11228 static rtx
11231 {
11233 }
11235 /* Implements target hook vector_mode_supported_p. */
11236 static bool
11238 {
11250 }
11252 /* Return appropriate SIMD container
11253 for MODE within a vector of WIDTH bits. */
11254 static machine_mode
11256 {
11259 {
11262 {
11279 }
11280 else
11282 {
11295 }
11296 }
11298 }
11300 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11301 static machine_mode
11303 {
11305 }
11307 /* Return the bitmask of possible vector sizes for the vectorizer
11308 to iterate over. */
11309 static unsigned int
11311 {
11313 }
11315 /* Implement TARGET_MANGLE_TYPE. */
11319 {
11320 /* The AArch64 ABI documents say that "__va_list" has to be
11321 managled as if it is in the "std" namespace. */
11325 /* Half-precision float. */
11329 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11330 builtin types. */
11334 /* Use the default mangling. */
11336 }
11338 /* Find the first rtx_insn before insn that will generate an assembly
11339 instruction. */
11343 {
11347 do
11348 {
11350 }
11354 }
11356 static bool
11358 {
11360 /* A number of these may be AArch32 only. */
11365 };
11368 {
11371 }
11374 }
11376 /* Check if there is a register dependency between a load and the insn
11377 for which we hold recog_data. */
11379 static bool
11381 {
11382 rtx load_reg;
11392 {
11398 }
11400 }
11403 /* When working around the Cortex-A53 erratum 835769,
11404 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11405 instruction and has a preceding memory instruction such that a NOP
11406 should be inserted between them. */
11408 bool
11410 {
11413 rtx body;
11426 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11427 Restore recog state to INSN to avoid state corruption. */
11435 /* If the previous insn is a memory op and there is no dependency between
11436 it and the DImode madd, emit a NOP between them. If body is NULL then we
11437 have a complex memory operation, probably a load/store pair.
11438 Be conservative for now and emit a NOP. */
11445 }
11448 /* Implement FINAL_PRESCAN_INSN. */
11450 void
11452 {
11455 }
11458 /* Return the equivalent letter for size. */
11459 static char
11461 {
11463 {
11469 }
11470 }
11472 /* Return true iff x is a uniform vector of floating-point
11473 constants, and the constant can be represented in
11474 quarter-precision form. Note, as aarch64_float_const_representable
11475 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11476 static bool
11478 {
11479 rtx elt;
11483 }
11485 /* Return true for valid and false for invalid. */
11486 bool
11490 {
11491 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11492 matches = 1; \
11493 for (i = 0; i < idx; i += (STRIDE)) \
11494 if (!(TEST)) \
11495 matches = 0; \
11496 if (matches) \
11497 { \
11498 immtype = (CLASS); \
11499 elsize = (ELSIZE); \
11500 eshift = (SHIFT); \
11501 emvn = (NEG); \
11502 break; \
11503 }
11513 {
11519 {
11521 scalar_float_mode elt_mode
11528 }
11531 }
11533 /* Splat vector constant out into a byte vector. */
11535 {
11536 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11537 it must be laid out in the vector register in reverse order. */
11545 {
11548 }
11550 }
11552 /* Sanity check. */
11555 do
11556 {
11558 {
11574 }
11577 {
11593 }
11595 /* Shifting ones / 8-bit / 64-bit variants only checked
11596 for 'ALL' (MOVI/MVNI). */
11598 {
11615 }
11616 }
11623 {
11633 /* Un-invert bytes of recognized vector, if necessary. */
11639 {
11640 /* FIXME: Broken on 32-bit H_W_I hosts. */
11649 }
11650 else
11651 {
11655 /* Construct 'abcdefgh' because the assembler cannot handle
11656 generic constants. */
11661 }
11662 }
11665 #undef CHECK
11666 }
11668 /* Check of immediate shift constants are within range. */
11669 bool
11671 {
11675 else
11677 }
11679 /* Return true if X is a uniform vector where all elements
11680 are either the floating-point constant 0.0 or the
11681 integer constant 0. */
11682 bool
11684 {
11686 }
11689 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11690 operation of width WIDTH at bit position POS. */
11692 rtx
11694 {
11698 unsigned HOST_WIDE_INT mask
11701 }
11703 bool
11705 {
11718 }
11720 /* Return a const_int vector of VAL. */
11721 rtx
11723 {
11734 }
11736 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11738 bool
11740 {
11741 machine_mode vmode;
11746 }
11748 /* Construct and return a PARALLEL RTX vector with elements numbering the
11749 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11750 the vector - from the perspective of the architecture. This does not
11751 line up with GCC's perspective on lane numbers, so we end up with
11752 different masks depending on our target endian-ness. The diagram
11753 below may help. We must draw the distinction when building masks
11754 which select one half of the vector. An instruction selecting
11755 architectural low-lanes for a big-endian target, must be described using
11756 a mask selecting GCC high-lanes.
11758 Big-Endian Little-Endian
11760 GCC 0 1 2 3 3 2 1 0
11761 | x | x | x | x | | x | x | x | x |
11762 Architecture 3 2 1 0 3 2 1 0
11764 Low Mask: { 2, 3 } { 0, 1 }
11765 High Mask: { 0, 1 } { 2, 3 }
11766 */
11768 rtx
11770 {
11776 rtx t1;
11781 else
11789 }
11791 /* Check OP for validity as a PARALLEL RTX vector with elements
11792 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11793 from the perspective of the architecture. See the diagram above
11794 aarch64_simd_vect_par_cnst_half for more details. */
11796 bool
11799 {
11812 {
11819 }
11821 }
11823 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11824 HIGH (exclusive). */
11825 void
11827 const_tree exp)
11828 {
11829 HOST_WIDE_INT lane;
11834 {
11837 else
11839 }
11840 }
11842 /* Return TRUE if OP is a valid vector addressing mode. */
11843 bool
11845 {
11848 }
11850 /* Emit a register copy from operand to operand, taking care not to
11851 early-clobber source registers in the process.
11853 COUNT is the number of components into which the copy needs to be
11854 decomposed. */
11855 void
11858 {
11868 else
11872 }
11874 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11875 one of VSTRUCT modes: OI, CI, or XI. */
11876 int
11878 {
11880 }
11882 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11883 alignment of a vector to 128 bits. */
11884 static HOST_WIDE_INT
11886 {
11889 }
11891 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11892 static bool
11894 {
11898 /* We guarantee alignment for vectors up to 128-bits. */
11903 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11905 }
11907 /* Return true if the vector misalignment factor is supported by the
11908 target. */
11909 static bool
11913 {
11915 {
11916 /* Return if movmisalign pattern is not supported for this mode. */
11920 /* Misalignment factor is unknown at compile time. */
11923 }
11925 is_packed);
11926 }
11928 /* If VALS is a vector constant that can be loaded into a register
11929 using DUP, generate instructions to do so and return an RTX to
11930 assign to the register. Otherwise return NULL_RTX. */
11931 static rtx
11933 {
11936 rtx x;
11941 /* We can load this constant by using DUP and a constant in a
11942 single ARM register. This will be cheaper than a vector
11943 load. */
11946 }
11949 /* Generate code to load VALS, which is a PARALLEL containing only
11950 constants (for vec_init) or CONST_VECTOR, efficiently into a
11951 register. Returns an RTX to copy into the register, or NULL_RTX
11952 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11953 static rtx
11955 {
11957 rtx const_dup;
11966 {
11967 /* A CONST_VECTOR must contain only CONST_INTs and
11968 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11969 Only store valid constants in a CONST_VECTOR. */
11971 {
11974 n_const++;
11975 }
11978 }
11979 else
11984 /* Load using MOVI/MVNI. */
11987 /* Loaded using DUP. */
11990 /* Load from constant pool. We can not take advantage of single-cycle
11991 LD1 because we need a PC-relative addressing mode. */
11993 else
11994 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11995 We can not construct an initializer. */
11997 }
11999 /* Expand a vector initialisation sequence, such that TARGET is
12000 initialised to contain VALS. */
12002 void
12004 {
12007 /* The number of vector elements. */
12009 /* The number of vector elements which are not constant. */
12012 /* The first element of vals. */
12016 /* Count the number of variable elements to initialise. */
12018 {
12022 else
12026 }
12028 /* No variable elements, hand off to aarch64_simd_make_constant which knows
12029 how best to handle this. */
12031 {
12034 {
12037 }
12038 }
12040 /* Splat a single non-constant element if we can. */
12042 {
12046 }
12051 /* If there are only variable elements, try to optimize
12052 the insertion using dup for the most common element
12053 followed by insertions. */
12055 /* The algorithm will fill matches[*][0] with the earliest matching element,
12056 and matches[X][1] with the count of duplicate elements (if X is the
12057 earliest element which has duplicates). */
12060 {
12063 {
12065 {
12067 {
12071 }
12072 }
12073 }
12078 {
12081 }
12083 /* Create a duplicate of the most common element. */
12087 /* Insert the rest. */
12089 {
12095 }
12097 }
12099 /* Initialise a vector which is part-variable. We want to first try
12100 to build those lanes which are constant in the most efficient way we
12101 can. */
12103 {
12106 /* Load constant part of vector. We really don't care what goes into the
12107 parts we will overwrite, but we're more likely to be able to load the
12108 constant efficiently if it has fewer, larger, repeating parts
12109 (see aarch64_simd_valid_immediate). */
12111 {
12117 {
12118 /* Look in the copied vector, as more elements are const. */
12121 {
12124 }
12125 }
12127 }
12129 }
12131 /* Insert the variable lanes directly. */
12133 {
12139 }
12140 }
12142 static unsigned HOST_WIDE_INT
12144 {
12145 return
12146 (!SHIFT_COUNT_TRUNCATED
12149 }
12151 /* Select a format to encode pointers in exception handling data. */
12152 int
12154 {
12157 {
12163 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12164 for everything. */
12168 /* No assumptions here. 8-byte relocs required. */
12171 }
12173 }
12175 /* The last .arch and .tune assembly strings that we printed. */
12179 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12180 by the function fndecl. */
12182 void
12184 tree fndecl)
12185 {
12191 else
12202 /* Only update the assembler .arch string if it is distinct from the last
12203 such string we printed. */
12206 {
12209 }
12211 /* Print the cpu name we're tuning for in the comments, might be
12212 useful to readers of the generated asm. Do it only when it changes
12213 from function to function and verbose assembly is requested. */
12218 {
12222 }
12224 /* Don't forget the type directive for ELF. */
12227 }
12229 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12231 static void
12233 {
12250 }
12252 /* Emit load exclusive. */
12254 static void
12257 {
12261 {
12268 }
12271 }
12273 /* Emit store exclusive. */
12275 static void
12278 {
12282 {
12289 }
12292 }
12294 /* Mark the previous jump instruction as unlikely. */
12296 static void
12298 {
12301 }
12303 /* Expand a compare and swap pattern. */
12305 void
12307 {
12312 gen_cas_fn gen;
12314 {
12315 gen_aarch64_compare_and_swapqi,
12316 gen_aarch64_compare_and_swaphi,
12317 gen_aarch64_compare_and_swapsi,
12318 gen_aarch64_compare_and_swapdi
12319 };
12321 {
12322 gen_aarch64_compare_and_swapqi_lse,
12323 gen_aarch64_compare_and_swaphi_lse,
12324 gen_aarch64_compare_and_swapsi_lse,
12325 gen_aarch64_compare_and_swapdi_lse
12326 };
12339 /* Normally the succ memory model must be stronger than fail, but in the
12340 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12341 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12348 {
12351 /* For short modes, we're going to perform the comparison in SImode,
12352 so do the zero-extension now. */
12356 /* Fall through. */
12360 /* Force the value into a register if needed. */
12367 }
12370 {
12377 }
12380 else
12391 }
12393 /* Test whether the target supports using a atomic load-operate instruction.
12394 CODE is the operation and AFTER is TRUE if the data in memory after the
12395 operation should be returned and FALSE if the data before the operation
12396 should be returned. Returns FALSE if the operation isn't supported by the
12397 architecture. */
12399 bool
12401 {
12406 {
12416 }
12417 }
12419 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12420 sequence implementing an atomic operation. */
12422 static void
12424 {
12431 {
12433 }
12434 }
12436 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12437 for the data in memory. EXPECTED is the value expected to be in memory.
12438 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12439 is the memory ordering to use. */
12441 void
12444 rtx model)
12445 {
12447 machine_mode mode;
12452 {
12459 }
12461 /* Move the expected value into the CAS destination register. */
12464 /* Emit the CAS. */
12467 /* Compare the expected value with the value loaded by the CAS, to establish
12468 whether the swap was made. */
12470 }
12472 /* Split a compare and swap pattern. */
12474 void
12476 {
12478 machine_mode mode;
12483 rtx model_rtx;
12495 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12496 loop:
12497 .label1:
12498 LD[A]XR rval, [mem]
12499 CBNZ rval, .label2
12500 ST[L]XR scratch, newval, [mem]
12501 CBNZ scratch, .label1
12502 .label2:
12503 CMP rval, 0. */
12508 {
12511 }
12514 /* The initial load can be relaxed for a __sync operation since a final
12515 barrier will be emitted to stop code hoisting. */
12519 else
12523 {
12528 }
12529 else
12530 {
12536 }
12541 {
12546 }
12547 else
12548 {
12552 }
12555 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12556 to set the condition flags. If this is not used it will be removed by
12557 later passes. */
12559 {
12563 }
12564 /* Emit any final barrier needed for a __sync operation. */
12567 }
12569 /* Emit a BIC instruction. */
12571 static void
12573 {
12578 {
12583 }
12586 }
12588 /* Emit an atomic swap. */
12590 static void
12593 {
12597 {
12604 }
12607 }
12609 /* Operations supported by aarch64_emit_atomic_load_op. */
12611 enum aarch64_atomic_load_op_code
12612 {
12616 AARCH64_LDOP_BIC /* A & ~B */
12617 };
12619 /* Emit an atomic load-operate. */
12621 static void
12625 {
12628 {
12629 gen_aarch64_atomic_loadaddqi,
12630 gen_aarch64_atomic_loadaddhi,
12631 gen_aarch64_atomic_loadaddsi,
12632 gen_aarch64_atomic_loadadddi
12633 };
12635 {
12636 gen_aarch64_atomic_loadeorqi,
12637 gen_aarch64_atomic_loadeorhi,
12638 gen_aarch64_atomic_loadeorsi,
12639 gen_aarch64_atomic_loadeordi
12640 };
12642 {
12643 gen_aarch64_atomic_loadsetqi,
12644 gen_aarch64_atomic_loadsethi,
12645 gen_aarch64_atomic_loadsetsi,
12646 gen_aarch64_atomic_loadsetdi
12647 };
12649 {
12650 gen_aarch64_atomic_loadclrqi,
12651 gen_aarch64_atomic_loadclrhi,
12652 gen_aarch64_atomic_loadclrsi,
12653 gen_aarch64_atomic_loadclrdi
12654 };
12655 aarch64_atomic_load_op_fn gen;
12659 {
12666 }
12669 {
12676 }
12679 }
12681 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12682 location to store the data read from memory. OUT_RESULT is the location to
12683 store the result of the operation. MEM is the memory location to read and
12684 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12685 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12686 be NULL. */
12688 void
12691 {
12695 aarch64_atomic_load_op_code ldop_code;
12696 rtx src;
12697 rtx x;
12705 /* Make sure the value is in a register, putting it into a destination
12706 register if it needs to be manipulated. */
12709 {
12712 }
12713 else
12717 /* Preprocess the data for the operation as necessary. If the operation is
12718 a SET then emit a swap instruction and finish. */
12720 {
12726 /* Negate the value and treat it as a PLUS. */
12727 {
12728 rtx neg_src;
12730 /* Resize the value if necessary. */
12739 }
12740 /* Fall-through. */
12754 {
12755 rtx not_src;
12757 /* Resize the value if necessary. */
12766 }
12771 /* The operation can't be done with atomic instructions. */
12773 }
12777 /* If necessary, calculate the data in memory after the update by redoing the
12778 operation from values in registers. */
12783 {
12787 }
12792 {
12808 }
12813 }
12815 /* Split an atomic operation. */
12817 void
12820 {
12826 rtx x;
12828 /* Split the atomic operation into a sequence. */
12836 else
12840 /* The initial load can be relaxed for a __sync operation since a final
12841 barrier will be emitted to stop code hoisting. */
12845 else
12849 {
12863 {
12866 }
12867 /* Fall through. */
12873 }
12883 /* Emit any final barrier needed for a __sync operation. */
12886 }
12888 static void
12890 {
12891 /* Half-precision float operations. The compiler handles all operations
12892 with NULL libfuncs by converting to SFmode. */
12894 /* Conversions. */
12898 /* Arithmetic. */
12905 /* Comparisons. */
12913 }
12915 /* Target hook for c_mode_for_suffix. */
12916 static machine_mode
12918 {
12923 }
12925 /* We can only represent floating point constants which will fit in
12926 "quarter-precision" values. These values are characterised by
12927 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12928 by:
12930 (-1)^s * (n/16) * 2^r
12932 Where:
12933 's' is the sign bit.
12934 'n' is an integer in the range 16 <= n <= 31.
12935 'r' is an integer in the range -3 <= r <= 4. */
12937 /* Return true iff X can be represented by a quarter-precision
12938 floating point immediate operand X. Note, we cannot represent 0.0. */
12939 bool
12941 {
12942 /* This represents our current view of how many bits
12943 make up the mantissa. */
12953 /* We don't support HFmode constants yet. */
12959 /* We cannot represent infinities, NaNs or +/-zero. We won't
12960 know if we have +zero until we analyse the mantissa, but we
12961 can reject the other invalid values. */
12966 /* Extract exponent. */
12970 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12971 highest (sign) bit, with a fixed binary point at bit point_pos.
12972 m1 holds the low part of the mantissa, m2 the high part.
12973 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12974 bits for the mantissa, this can fail (low bits will be lost). */
12978 /* If the low part of the mantissa has bits set we cannot represent
12979 the value. */
12982 /* We have rejected the lower HOST_WIDE_INT, so update our
12983 understanding of how many bits lie in the mantissa and
12984 look only at the high HOST_WIDE_INT. */
12988 /* We can only represent values with a mantissa of the form 1.xxxx. */
12993 /* Having filtered unrepresentable values, we may now remove all
12994 but the highest 5 bits. */
12997 /* We cannot represent the value 0.0, so reject it. This is handled
12998 elsewhere. */
13002 /* Then, as bit 4 is always set, we can mask it off, leaving
13003 the mantissa in the range [0, 15]. */
13007 /* GCC internally does not use IEEE754-like encoding (where normalized
13008 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
13009 Our mantissa values are shifted 4 places to the left relative to
13010 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
13011 by 5 places to correct for GCC's representation. */
13015 }
13017 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
13018 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
13019 output MOVI/MVNI, ORR or BIC immediate. */
13022 machine_mode mode,
13025 {
13035 /* This will return true to show const_vector is legal for use as either
13036 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
13037 It will also update INFO to show how the immediate should be generated.
13038 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
13048 {
13050 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
13051 move immediate path. */
13054 else
13055 {
13064 else
13068 }
13069 }
13074 {
13084 else
13088 }
13089 else
13090 {
13091 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
13097 else
13101 }
13103 }
13107 {
13109 /* If a floating point number was passed and we desire to use it in an
13110 integer mode do the conversion to integer. */
13112 {
13117 }
13119 machine_mode vmode;
13120 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13121 a 128 bit vector mode. */
13127 }
13129 /* Split operands into moves from op[1] + op[2] into op[0]. */
13131 void
13133 {
13144 {
13145 /* No-op move. Can't split to nothing; emit something. */
13148 }
13150 /* Preserve register attributes for variable tracking. */
13155 /* Special case of reversed high/low parts. */
13158 {
13162 }
13164 {
13165 /* Try to avoid unnecessary moves if part of the result
13166 is in the right place already. */
13171 }
13172 else
13173 {
13178 }
13179 }
13181 /* vec_perm support. */
13183 #define MAX_VECT_LEN 16
13185 struct expand_vec_perm_d
13186 {
13188 auto_vec_perm_indices perm;
13189 machine_mode vmode;
13192 };
13194 /* Generate a variable permutation. */
13196 static void
13198 {
13209 {
13211 {
13212 /* Expand the argument to a V16QI mode by duplicating it. */
13216 }
13217 else
13218 {
13220 }
13221 }
13222 else
13223 {
13224 rtx pair;
13227 {
13231 }
13232 else
13233 {
13237 }
13238 }
13239 }
13241 void
13243 {
13247 rtx mask;
13249 /* The TBL instruction does not use a modulo index, so we must take care
13250 of that ourselves. */
13255 /* For big-endian, we also need to reverse the index within the vector
13256 (but not which vector). */
13258 {
13259 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13264 }
13266 }
13268 /* Recognize patterns suitable for the TRN instructions. */
13269 static bool
13271 {
13280 /* Note that these are little-endian tests.
13281 We correct for big-endian later. */
13286 else
13291 {
13296 }
13298 /* Success! */
13305 {
13308 }
13312 {
13314 {
13329 }
13330 }
13331 else
13332 {
13334 {
13349 }
13350 }
13354 }
13356 /* Recognize patterns suitable for the UZP instructions. */
13357 static bool
13359 {
13368 /* Note that these are little-endian tests.
13369 We correct for big-endian later. */
13374 else
13379 {
13383 }
13385 /* Success! */
13392 {
13395 }
13399 {
13401 {
13416 }
13417 }
13418 else
13419 {
13421 {
13436 }
13437 }
13441 }
13443 /* Recognize patterns suitable for the ZIP instructions. */
13444 static bool
13446 {
13455 /* Note that these are little-endian tests.
13456 We correct for big-endian later. */
13459 /* Do Nothing. */
13460 ;
13463 else
13468 {
13475 }
13477 /* Success! */
13484 {
13487 }
13491 {
13493 {
13508 }
13509 }
13510 else
13511 {
13513 {
13528 }
13529 }
13533 }
13535 /* Recognize patterns for the EXT insn. */
13537 static bool
13539 {
13542 rtx offset;
13546 /* Check if the extracted indices are increasing by one. */
13548 {
13551 {
13552 /* We'll pass the same vector in twice, so allow indices to wrap. */
13554 }
13557 }
13560 {
13575 }
13577 /* Success! */
13581 /* The case where (location == 0) is a no-op for both big- and little-endian,
13582 and is removed by the mid-end at optimization levels -O1 and higher. */
13585 {
13586 /* After setup, we want the high elements of the first vector (stored
13587 at the LSB end of the register), and the low elements of the second
13588 vector (stored at the MSB end of the register). So swap. */
13590 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13592 }
13597 }
13599 /* Recognize patterns for the REV insns. */
13601 static bool
13603 {
13612 {
13615 {
13620 }
13624 {
13631 }
13635 {
13648 }
13652 }
13656 {
13657 /* This is guaranteed to be true as the value of diff
13658 is 7, 3, 1 and we should have enough elements in the
13659 queue to generate this. Getting a vector mask with a
13660 value of diff other than these values implies that
13661 something is wrong by the time we get here. */
13665 }
13667 /* Success! */
13673 }
13675 static bool
13677 {
13680 rtx in0;
13683 rtx lane;
13687 {
13690 }
13692 /* The generic preparation in aarch64_expand_vec_perm_const_1
13693 swaps the operand order and the permute indices if it finds
13694 d->perm[0] to be in the second operand. Thus, we can always
13695 use d->op0 and need not do any extra arithmetic to get the
13696 correct lane number. */
13701 {
13716 }
13720 }
13722 static bool
13724 {
13732 /* Generic code will try constant permutation twice. Once with the
13733 original mode and again with the elements lowered to QImode.
13734 So wait and don't do the selector expansion ourselves. */
13739 {
13742 /* If big-endian and two vectors we end up with a weird mixed-endian
13743 mode on NEON. Reverse the index within each word but not the word
13744 itself. */
13747 }
13753 }
13755 static bool
13757 {
13758 /* The pattern matching functions above are written to look for a small
13759 number to begin the sequence (0, 1, N/2). If we begin with an index
13760 from the second operand, we can swap the operands. */
13763 {
13769 }
13772 {
13786 }
13788 }
13790 /* Expand a vec_perm_const pattern. */
13792 bool
13794 {
13809 {
13814 }
13817 {
13826 /* The elements of PERM do not suggest that only the first operand
13827 is used, but both operands are identical. Allow easier matching
13828 of the permutation by folding the permutation into the single
13829 input vector. */
13830 /* Fall Through. */
13842 }
13845 }
13847 static bool
13849 {
13858 /* Calculate whether all elements are in one vector. */
13861 {
13865 }
13867 /* If all elements are from the second vector, reindex as if from the
13868 first vector. */
13873 /* Check whether the mask can be applied to a single vector. */
13886 }
13888 rtx
13890 {
13891 /* We have to reverse each vector because we dont have
13892 a permuted load that can reverse-load according to ABI rules. */
13893 rtx mask;
13907 }
13909 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
13910 true. However due to issues with register allocation it is preferable
13911 to avoid tieing integer scalar and FP scalar modes. Executing integer
13912 operations in general registers is better than treating them as scalar
13913 vector operations. This reduces latency and avoids redundant int<->FP
13914 moves. So tie modes if they are either the same class, or vector modes
13915 with other vector modes, vector structs or any scalar mode. */
13917 static bool
13919 {
13923 /* We specifically want to allow elements of "structure" modes to
13924 be tieable to the structure. This more general condition allows
13925 other rarer situations too. */
13929 /* Also allow any scalar modes with vectors. */
13935 }
13937 /* Return a new RTX holding the result of moving POINTER forward by
13938 AMOUNT bytes. */
13940 static rtx
13942 {
13947 }
13949 /* Return a new RTX holding the result of moving POINTER forward by the
13950 size of the mode it points to. */
13952 static rtx
13954 {
13958 }
13960 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13961 MODE bytes. */
13963 static void
13965 machine_mode mode)
13966 {
13969 /* "Cast" the pointers to the correct mode. */
13972 /* Emit the memcpy. */
13975 /* Move the pointers forward. */
13978 }
13980 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13981 we succeed, otherwise return false. */
13983 bool
13985 {
13989 rtx base;
13992 /* When optimizing for size, give a better estimate of the length of a
13993 memcpy call, but use the default otherwise. */
13996 /* We can't do anything smart if the amount to copy is not constant. */
14002 /* Try to keep the number of instructions low. For cases below 16 bytes we
14003 need to make at most two moves. For cases above 16 bytes it will be one
14004 move for each 16 byte chunk, then at most two additional moves. */
14014 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
14015 1-byte chunk. */
14017 {
14019 {
14022 }
14028 }
14030 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
14031 4-byte chunk, partially overlapping with the previously copied chunk. */
14033 {
14037 {
14043 }
14045 }
14047 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
14048 them, then (if applicable) an 8-byte chunk. */
14050 {
14052 {
14055 }
14056 else
14057 {
14060 }
14061 }
14063 /* Finish the final bytes of the copy. We can always do this in one
14064 instruction. We either copy the exact amount we need, or partially
14065 overlap with the previous chunk we copied and copy 8-bytes. */
14074 else
14075 {
14077 {
14081 }
14082 else
14083 {
14089 }
14090 }
14093 }
14095 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
14096 SImode stores. Handle the case when the constant has identical
14097 bottom and top halves. This is beneficial when the two stores can be
14098 merged into an STP and we avoid synthesising potentially expensive
14099 immediates twice. Return true if such a split is possible. */
14101 bool
14103 {
14112 unsigned int orig_cost
14114 unsigned int lo_cost
14117 /* We want to transform:
14118 MOV x1, 49370
14119 MOVK x1, 0x140, lsl 16
14120 MOVK x1, 0xc0da, lsl 32
14121 MOVK x1, 0x140, lsl 48
14122 STR x1, [x0]
14123 into:
14124 MOV w1, 49370
14125 MOVK w1, 0x140, lsl 16
14126 STP w1, w1, [x0]
14127 So we want to perform this only when we save two instructions
14128 or more. When optimizing for size, however, accept any code size
14129 savings we can. */
14144 /* Don't emit an explicit store pair as this may not be always profitable.
14145 Let the sched-fusion logic decide whether to merge them. */
14150 }
14152 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
14154 static unsigned HOST_WIDE_INT
14156 {
14158 }
14160 static bool
14165 {
14166 /* STORE_BY_PIECES can be used when copying a constant string, but
14167 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
14168 For now we always fail this and let the move_by_pieces code copy
14169 the string from read-only memory. */
14174 }
14176 static rtx
14179 {
14183 insn_code icode;
14194 {
14222 }
14227 {
14230 }
14239 {
14242 }
14248 }
14250 static rtx
14253 {
14257 insn_code icode;
14269 {
14297 }
14302 {
14305 }
14313 {
14318 }
14329 {
14332 }
14338 }
14340 #undef TARGET_GEN_CCMP_FIRST
14341 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14343 #undef TARGET_GEN_CCMP_NEXT
14344 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14346 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14347 instruction fusion of some sort. */
14349 static bool
14351 {
14353 }
14356 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14357 should be kept together during scheduling. */
14359 static bool
14361 {
14362 rtx set_dest;
14365 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14372 {
14373 /* We are trying to match:
14374 prev (mov) == (set (reg r0) (const_int imm16))
14375 curr (movk) == (set (zero_extract (reg r0)
14376 (const_int 16)
14377 (const_int 16))
14378 (const_int imm16_1)) */
14390 {
14392 }
14393 }
14396 {
14398 /* We're trying to match:
14399 prev (adrp) == (set (reg r1)
14400 (high (symbol_ref ("SYM"))))
14401 curr (add) == (set (reg r0)
14402 (lo_sum (reg r1)
14403 (symbol_ref ("SYM"))))
14404 Note that r0 need not necessarily be the same as r1, especially
14405 during pre-regalloc scheduling. */
14409 {
14417 }
14418 }
14421 {
14423 /* We're trying to match:
14424 prev (movk) == (set (zero_extract (reg r0)
14425 (const_int 16)
14426 (const_int 32))
14427 (const_int imm16_1))
14428 curr (movk) == (set (zero_extract (reg r0)
14429 (const_int 16)
14430 (const_int 48))
14431 (const_int imm16_2)) */
14447 }
14449 {
14450 /* We're trying to match:
14451 prev (adrp) == (set (reg r0)
14452 (high (symbol_ref ("SYM"))))
14453 curr (ldr) == (set (reg r1)
14454 (mem (lo_sum (reg r0)
14455 (symbol_ref ("SYM")))))
14456 or
14457 curr (ldr) == (set (reg r1)
14458 (zero_extend (mem
14459 (lo_sum (reg r0)
14460 (symbol_ref ("SYM")))))) */
14463 {
14476 }
14477 }
14485 {
14489 rtx cc_reg_1;
14494 && prev
14496 {
14497 /* FIXME: this misses some which is considered simple arthematic
14498 instructions for ThunderX. Simple shifts are missed here. */
14504 }
14505 }
14508 && curr_set
14511 {
14512 /* We're trying to match:
14513 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14514 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14515 (const_int 0))
14516 (label_ref ("SYM"))
14517 (pc)) */
14524 {
14525 /* Fuse ALU operations followed by conditional branch instruction. */
14527 {
14548 }
14549 }
14550 }
14553 }
14555 /* Return true iff the instruction fusion described by OP is enabled. */
14557 bool
14559 {
14561 }
14563 /* If MEM is in the form of [base+offset], extract the two parts
14564 of address and set to BASE and OFFSET, otherwise return false
14565 after clearing BASE and OFFSET. */
14567 bool
14569 {
14570 rtx addr;
14577 {
14581 }
14585 {
14589 }
14595 }
14597 /* Types for scheduling fusion. */
14598 enum sched_fusion_type
14599 {
14601 SCHED_FUSION_LD_SIGN_EXTEND,
14602 SCHED_FUSION_LD_ZERO_EXTEND,
14603 SCHED_FUSION_LD,
14604 SCHED_FUSION_ST,
14605 SCHED_FUSION_NUM
14606 };
14608 /* If INSN is a load or store of address in the form of [base+offset],
14609 extract the two parts and set to BASE and OFFSET. Return scheduling
14610 fusion type this INSN is. */
14612 static enum sched_fusion_type
14614 {
14632 {
14637 }
14639 {
14644 }
14649 {
14652 }
14653 else
14660 }
14662 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14664 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14665 and PRI are only calculated for these instructions. For other instruction,
14666 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14667 type instruction fusion can be added by returning different priorities.
14669 It's important that irrelevant instructions get the largest FUSION_PRI. */
14671 static void
14674 {
14684 {
14688 }
14690 /* Set FUSION_PRI according to fusion type and base register. */
14693 /* Calculate PRI. */
14696 /* INSN with smaller offset goes first. */
14700 else
14705 }
14707 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14708 Adjust priority of sha1h instructions so they are scheduled before
14709 other SHA1 instructions. */
14711 static int
14713 {
14717 {
14722 }
14725 }
14727 /* Given OPERANDS of consecutive load/store, check if we can merge
14728 them into ldp/stp. LOAD is true if they are load instructions.
14729 MODE is the mode of memory operands. */
14731 bool
14733 machine_mode mode)
14734 {
14740 {
14748 }
14749 else
14750 {
14755 }
14757 /* The mems cannot be volatile. */
14761 /* If we have SImode and slow unaligned ldp,
14762 check the alignment to be at least 8 byte. */
14766 && !optimize_size
14770 /* Check if the addresses are in the form of [base+offset]. */
14778 /* Check if the bases are same. */
14785 /* Check if the offsets are consecutive. */
14789 /* Check if the addresses are clobbered by load. */
14791 {
14795 /* In increasing order, the last load can clobber the address. */
14798 }
14802 else
14807 else
14810 /* Check if the registers are of same class. */
14815 }
14817 /* Given OPERANDS of consecutive load/store, check if we can merge
14818 them into ldp/stp by adjusting the offset. LOAD is true if they
14819 are load instructions. MODE is the mode of memory operands.
14821 Given below consecutive stores:
14823 str w1, [xb, 0x100]
14824 str w1, [xb, 0x104]
14825 str w1, [xb, 0x108]
14826 str w1, [xb, 0x10c]
14828 Though the offsets are out of the range supported by stp, we can
14829 still pair them after adjusting the offset, like:
14831 add scratch, xb, 0x100
14832 stp w1, w1, [scratch]
14833 stp w1, w1, [scratch, 0x8]
14835 The peephole patterns detecting this opportunity should guarantee
14836 the scratch register is avaliable. */
14838 bool
14840 scalar_mode mode)
14841 {
14848 {
14861 }
14862 else
14863 {
14872 }
14873 /* Skip if memory operand is by itslef valid for ldp/stp. */
14877 /* The mems cannot be volatile. */
14882 /* Check if the addresses are in the form of [base+offset]. */
14896 /* Check if the bases are same. */
14907 /* Check if the offsets are consecutive. */
14916 /* Check if the addresses are clobbered by load. */
14918 {
14924 /* In increasing order, the last load can clobber the address. */
14927 }
14929 /* If we have SImode and slow unaligned ldp,
14930 check the alignment to be at least 8 byte. */
14934 && !optimize_size
14940 else
14945 else
14950 else
14955 else
14958 /* Check if the registers are of same class. */
14963 }
14965 /* Given OPERANDS of consecutive load/store, this function pairs them
14966 into ldp/stp after adjusting the offset. It depends on the fact
14967 that addresses of load/store instructions are in increasing order.
14968 MODE is the mode of memory operands. CODE is the rtl operator
14969 which should be applied to all memory operands, it's SIGN_EXTEND,
14970 ZERO_EXTEND or UNKNOWN. */
14972 bool
14975 {
14981 {
14986 }
14987 else
14988 {
14994 }
14999 /* Adjust offset thus it can fit in ldp/stp instruction. */
15007 /* Further adjust to make sure all offsets are OK. */
15009 {
15012 }
15014 /* Make sure the adjustment can be done with ADD/SUB instructions. */
15019 {
15022 }
15024 /* Create new memory references. */
15028 /* Check if the adjusted address is OK for ldp/stp. */
15047 {
15052 }
15054 {
15059 }
15062 {
15067 }
15068 else
15069 {
15074 }
15076 /* Emit adjusting instruction. */
15078 /* Emit ldp/stp instructions. */
15086 }
15088 /* Return 1 if pseudo register should be created and used to hold
15089 GOT address for PIC code. */
15091 bool
15093 {
15095 }
15097 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
15099 static int
15101 {
15103 {
15110 }
15113 }
15116 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
15117 return the log2 of that value. Otherwise return -1. */
15119 int
15121 {
15136 }
15138 /* If X is a vector of equal CONST_DOUBLE values and that value is
15139 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
15141 int
15143 {
15159 }
15161 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
15162 to float.
15164 __fp16 always promotes through this hook.
15165 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
15166 through the generic excess precision logic rather than here. */
15168 static tree
15170 {
15176 }
15178 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
15180 static bool
15182 optimization_type opt_type)
15183 {
15185 {
15191 }
15192 }
15194 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
15195 if MODE is HFmode, and punt to the generic implementation otherwise. */
15197 static bool
15199 {
15203 }
15205 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15206 if MODE is HFmode, and punt to the generic implementation otherwise. */
15208 static bool
15210 {
15214 }
15216 /* Set the value of FLT_EVAL_METHOD.
15217 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15219 0: evaluate all operations and constants, whose semantic type has at
15220 most the range and precision of type float, to the range and
15221 precision of float; evaluate all other operations and constants to
15222 the range and precision of the semantic type;
15224 N, where _FloatN is a supported interchange floating type
15225 evaluate all operations and constants, whose semantic type has at
15226 most the range and precision of _FloatN type, to the range and
15227 precision of the _FloatN type; evaluate all other operations and
15228 constants to the range and precision of the semantic type;
15230 If we have the ARMv8.2-A extensions then we support _Float16 in native
15231 precision, so we should set this to 16. Otherwise, we support the type,
15232 but want to evaluate expressions in float precision, so set this to
15233 0. */
15235 static enum flt_eval_method
15237 {
15239 {
15242 /* We can calculate either in 16-bit range and precision or
15243 32-bit range and precision. Make that decision based on whether
15244 we have native support for the ARMv8.2-A 16-bit floating-point
15245 instructions or not. */
15247 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15253 }
15255 }
15257 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15258 scheduled for speculative execution. Reject the long-running division
15259 and square-root instructions. */
15261 static bool
15263 {
15265 {
15283 }
15284 }
15286 /* Target-specific selftests. */
15288 #if CHECKING_P
15292 /* Selftest for the RTL loader.
15293 Verify that the RTL loader copes with a dump from
15294 print_rtx_function. This is essentially just a test that class
15295 function_reader can handle a real dump, but it also verifies
15296 that lookup_reg_by_dump_name correctly handles hard regs.
15297 The presence of hard reg names in the dump means that the test is
15298 target-specific, hence it is in this file. */
15300 static void
15302 {
15314 /* Verify crtl->return_rtx. */
15318 }
15320 /* Run all target-specific selftests. */
15322 static void
15324 {
15326 }
15332 #undef TARGET_ADDRESS_COST
15333 #define TARGET_ADDRESS_COST aarch64_address_cost
15335 /* This hook will determines whether unnamed bitfields affect the alignment
15336 of the containing structure. The hook returns true if the structure
15337 should inherit the alignment requirements of an unnamed bitfield's
15338 type. */
15339 #undef TARGET_ALIGN_ANON_BITFIELD
15340 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15342 #undef TARGET_ASM_ALIGNED_DI_OP
15345 #undef TARGET_ASM_ALIGNED_HI_OP
15348 #undef TARGET_ASM_ALIGNED_SI_OP
15351 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15352 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15353 hook_bool_const_tree_hwi_hwi_const_tree_true
15355 #undef TARGET_ASM_FILE_START
15356 #define TARGET_ASM_FILE_START aarch64_start_file
15358 #undef TARGET_ASM_OUTPUT_MI_THUNK
15359 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15361 #undef TARGET_ASM_SELECT_RTX_SECTION
15362 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15364 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15365 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15367 #undef TARGET_BUILD_BUILTIN_VA_LIST
15368 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15370 #undef TARGET_CALLEE_COPIES
15371 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15373 #undef TARGET_CAN_ELIMINATE
15374 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15376 #undef TARGET_CAN_INLINE_P
15377 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15379 #undef TARGET_CANNOT_FORCE_CONST_MEM
15380 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15382 #undef TARGET_CASE_VALUES_THRESHOLD
15383 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15385 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15386 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15388 /* Only the least significant bit is used for initialization guard
15389 variables. */
15390 #undef TARGET_CXX_GUARD_MASK_BIT
15391 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15393 #undef TARGET_C_MODE_FOR_SUFFIX
15394 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15396 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15397 #undef TARGET_DEFAULT_TARGET_FLAGS
15398 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15399 #endif
15401 #undef TARGET_CLASS_MAX_NREGS
15402 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15404 #undef TARGET_BUILTIN_DECL
15405 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15407 #undef TARGET_BUILTIN_RECIPROCAL
15408 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15410 #undef TARGET_C_EXCESS_PRECISION
15411 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15413 #undef TARGET_EXPAND_BUILTIN
15414 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15416 #undef TARGET_EXPAND_BUILTIN_VA_START
15417 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15419 #undef TARGET_FOLD_BUILTIN
15420 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15422 #undef TARGET_FUNCTION_ARG
15423 #define TARGET_FUNCTION_ARG aarch64_function_arg
15425 #undef TARGET_FUNCTION_ARG_ADVANCE
15426 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15428 #undef TARGET_FUNCTION_ARG_BOUNDARY
15429 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15431 #undef TARGET_FUNCTION_ARG_PADDING
15432 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
15434 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15435 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15437 #undef TARGET_FUNCTION_VALUE
15438 #define TARGET_FUNCTION_VALUE aarch64_function_value
15440 #undef TARGET_FUNCTION_VALUE_REGNO_P
15441 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15443 #undef TARGET_FRAME_POINTER_REQUIRED
15444 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
15446 #undef TARGET_GIMPLE_FOLD_BUILTIN
15447 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15449 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15450 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15452 #undef TARGET_INIT_BUILTINS
15453 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15455 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15456 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15457 aarch64_ira_change_pseudo_allocno_class
15459 #undef TARGET_LEGITIMATE_ADDRESS_P
15460 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15462 #undef TARGET_LEGITIMATE_CONSTANT_P
15463 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15465 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15466 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15467 aarch64_legitimize_address_displacement
15469 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15470 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15472 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15473 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15474 aarch64_libgcc_floating_mode_supported_p
15476 #undef TARGET_MANGLE_TYPE
15477 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15479 #undef TARGET_MEMORY_MOVE_COST
15480 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15482 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15483 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15485 #undef TARGET_MUST_PASS_IN_STACK
15486 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15488 /* This target hook should return true if accesses to volatile bitfields
15489 should use the narrowest mode possible. It should return false if these
15490 accesses should use the bitfield container type. */
15491 #undef TARGET_NARROW_VOLATILE_BITFIELD
15492 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15494 #undef TARGET_OPTION_OVERRIDE
15495 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15497 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15498 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15499 aarch64_override_options_after_change
15501 #undef TARGET_OPTION_SAVE
15502 #define TARGET_OPTION_SAVE aarch64_option_save
15504 #undef TARGET_OPTION_RESTORE
15505 #define TARGET_OPTION_RESTORE aarch64_option_restore
15507 #undef TARGET_OPTION_PRINT
15508 #define TARGET_OPTION_PRINT aarch64_option_print
15510 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15511 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15513 #undef TARGET_SET_CURRENT_FUNCTION
15514 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15516 #undef TARGET_PASS_BY_REFERENCE
15517 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15519 #undef TARGET_PREFERRED_RELOAD_CLASS
15520 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15522 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15523 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15525 #undef TARGET_PROMOTED_TYPE
15526 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15528 #undef TARGET_SECONDARY_RELOAD
15529 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15531 #undef TARGET_SHIFT_TRUNCATION_MASK
15532 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15534 #undef TARGET_SETUP_INCOMING_VARARGS
15535 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15537 #undef TARGET_STRUCT_VALUE_RTX
15538 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15540 #undef TARGET_REGISTER_MOVE_COST
15541 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15543 #undef TARGET_RETURN_IN_MEMORY
15544 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15546 #undef TARGET_RETURN_IN_MSB
15547 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15549 #undef TARGET_RTX_COSTS
15550 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15552 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15553 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15555 #undef TARGET_SCHED_ISSUE_RATE
15556 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15558 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15559 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15560 aarch64_sched_first_cycle_multipass_dfa_lookahead
15562 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15563 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15564 aarch64_first_cycle_multipass_dfa_lookahead_guard
15566 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15567 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15568 aarch64_get_separate_components
15570 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15571 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15572 aarch64_components_for_bb
15574 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15575 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15576 aarch64_disqualify_components
15578 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15579 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15580 aarch64_emit_prologue_components
15582 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15583 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15584 aarch64_emit_epilogue_components
15586 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15587 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15588 aarch64_set_handled_components
15590 #undef TARGET_TRAMPOLINE_INIT
15591 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15593 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15594 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15596 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15597 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15599 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15600 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15601 aarch64_builtin_support_vector_misalignment
15603 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15604 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15606 #undef TARGET_VECTORIZE_ADD_STMT_COST
15607 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15609 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15610 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15611 aarch64_builtin_vectorization_cost
15613 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15614 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15616 #undef TARGET_VECTORIZE_BUILTINS
15617 #define TARGET_VECTORIZE_BUILTINS
15619 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15620 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15621 aarch64_builtin_vectorized_function
15623 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15624 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15625 aarch64_autovectorize_vector_sizes
15627 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15628 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15629 aarch64_atomic_assign_expand_fenv
15631 /* Section anchor support. */
15633 #undef TARGET_MIN_ANCHOR_OFFSET
15634 #define TARGET_MIN_ANCHOR_OFFSET -256
15636 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15637 byte offset; we can do much more for larger data types, but have no way
15638 to determine the size of the access. We assume accesses are aligned. */
15639 #undef TARGET_MAX_ANCHOR_OFFSET
15640 #define TARGET_MAX_ANCHOR_OFFSET 4095
15642 #undef TARGET_VECTOR_ALIGNMENT
15643 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15645 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15646 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15647 aarch64_simd_vector_alignment_reachable
15649 /* vec_perm support. */
15651 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15652 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15653 aarch64_vectorize_vec_perm_const_ok
15655 #undef TARGET_INIT_LIBFUNCS
15656 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15658 #undef TARGET_FIXED_CONDITION_CODE_REGS
15659 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15661 #undef TARGET_FLAGS_REGNUM
15662 #define TARGET_FLAGS_REGNUM CC_REGNUM
15664 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15665 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15667 #undef TARGET_ASAN_SHADOW_OFFSET
15668 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15670 #undef TARGET_LEGITIMIZE_ADDRESS
15671 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15673 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15674 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15675 aarch64_use_by_pieces_infrastructure_p
15677 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15678 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15680 #undef TARGET_CAN_USE_DOLOOP_P
15681 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15683 #undef TARGET_SCHED_ADJUST_PRIORITY
15684 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15686 #undef TARGET_SCHED_MACRO_FUSION_P
15687 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15689 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15690 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15692 #undef TARGET_SCHED_FUSION_PRIORITY
15693 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15695 #undef TARGET_UNSPEC_MAY_TRAP_P
15696 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15698 #undef TARGET_USE_PSEUDO_PIC_REG
15699 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15701 #undef TARGET_PRINT_OPERAND
15702 #define TARGET_PRINT_OPERAND aarch64_print_operand
15704 #undef TARGET_PRINT_OPERAND_ADDRESS
15705 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15707 #undef TARGET_OPTAB_SUPPORTED_P
15708 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15710 #undef TARGET_OMIT_STRUCT_RETURN_REG
15711 #define TARGET_OMIT_STRUCT_RETURN_REG true
15713 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15714 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15715 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15717 #undef TARGET_HARD_REGNO_NREGS
15718 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
15719 #undef TARGET_HARD_REGNO_MODE_OK
15720 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
15722 #undef TARGET_MODES_TIEABLE_P
15723 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
15725 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
15726 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
15727 aarch64_hard_regno_call_part_clobbered
15729 #undef TARGET_CONSTANT_ALIGNMENT
15730 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
15732 #if CHECKING_P
15733 #undef TARGET_RUN_TARGET_SELFTESTS
15734 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests