gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2 -fdump-tree-dom1-details" } */
   3 /* { dg-additional-options "-mbranch-cost=2" { target s390*-*-* } } */
   4 struct bitmap_head_def;
   5 typedef struct bitmap_head_def *bitmap;
   6 typedef const struct bitmap_head_def *const_bitmap;
   7 typedef unsigned long BITMAP_WORD;
   8 typedef struct bitmap_element_def
   9 {
  10   struct bitmap_element_def *next;
  11   unsigned int indx;
  12 } bitmap_element;
  13
  14
  15
  16
  17
  18
  19
  20
  21
  22 unsigned char
  23 bitmap_ior_and_compl (bitmap dst, const_bitmap a, const_bitmap b,
  24                       const_bitmap kill)
  25 {
  26   unsigned char changed = 0;
  27
  28   bitmap_element *dst_elt;
  29   const bitmap_element *a_elt, *b_elt, *kill_elt, *dst_prev;
  30
  31   while (a_elt || b_elt)
  32     {
  33       unsigned char new_element = 0;
  34
  35       if (b_elt)
  36         while (kill_elt && kill_elt->indx < b_elt->indx)
  37           kill_elt = kill_elt->next;
  38
  39       if (b_elt && kill_elt && kill_elt->indx == b_elt->indx
  40           && (!a_elt || a_elt->indx >= b_elt->indx))
  41         {
  42           bitmap_element tmp_elt;
  43           unsigned ix;
  44
  45           BITMAP_WORD ior = 0;
  46
  47               changed = bitmap_elt_ior (dst, dst_elt, dst_prev,
  48                                         a_elt, &tmp_elt, changed);
  49
  50         }
  51
  52     }
  53
  54
  55   return changed;
  56 }
  57 /* The block starting the second conditional has  3 incoming edges,
  58    we should thread all three, but due to a bug in the threading
  59    code we missed the edge when the first conditional is false
  60    (b_elt is zero, which means the second conditional is always
  61    zero.  */
  62 /* ARM Cortex-M0 defined LOGICAL_OP_NON_SHORT_CIRCUIT to false,
  63    so skip below test.  */
  64 /* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! { { mips*-*-* avr-*-* } || { arm_cortex_m && arm_thumb1 } } } } } } */
  65 /* MIPS defines LOGICAL_OP_NON_SHORT_CIRCUIT to 0, so we split both
  66    "a_elt || b_elt" and "b_elt && kill_elt" into two conditions each,
  67    rather than using "(var1 != 0) op (var2 != 0)".  Also, as on other targets,
  68    we duplicate the header of the inner "while" loop.  There are then
  69    6 threading opportunities:
  70
  71    1x "!a_elt && b_elt" in the outer "while" loop
  72       -> the start of the inner "while" loop,
  73          skipping the known-true "b_elt" in the first condition.
  74    1x "!b_elt" in the first condition
  75       -> the outer "while" loop's continuation point,
  76          skipping the known-false "b_elt" in the second condition.
  77    2x "!kill_elt" in the inner "while" loop
  78       -> the outer "while" loop's continuation point,
  79          skipping the known-false "b_elt && kill_elt" in the second condition
  80    2x "kill_elt->indx < b_elt->indx" in the first "while" loop
  81       -> "kill_elt->indx == b_elt->indx" in the second condition,
  82          skipping the known-true "b_elt && kill_elt" in the second
  83          condition.  */
  84 /* For avr, BRANCH_COST is by default 0, so the default
  85    LOGICAL_OP_NON_SHORT_CIRCUIT definition also computes as 0.  */
  86 /* { dg-final { scan-tree-dump-times "Threaded" 6 "dom1" { target mips*-*-* avr-*-* } } } */
  87 /* { dg-final { cleanup-tree-dump "dom1" } } */
  88