| blob | ab515436fc857fcef354058d0535efb85e3a1887 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* And similarly, for notes. */
309 /* Basic block in which we are performing combines. */
313 \f
314 /* Length of the currently allocated uid_insn_cost array. */
318 /* The following array records the insn_cost for every insn
319 in the instruction stream. */
323 /* The following array records the LOG_LINKS for every insn in the
324 instruction stream as struct insn_link pointers. */
330 };
336 {
340 }
342 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
343 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
345 #define FOR_EACH_LOG_LINK(L, INSN) \
346 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
348 /* Links for LOG_LINKS are allocated from this obstack. */
352 /* Allocate a link. */
356 {
364 }
366 /* Incremented for each basic block. */
370 /* Reset to label_tick for each extended basic block in scanning order. */
374 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
375 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
379 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
380 be safely used. It is zero while computing them and after combine has
381 completed. This former test prevents propagating values based on
382 previously set values, which can be incorrect if a variable is modified
383 in a loop. */
387 \f
388 /* Record one modification to rtl structure
389 to be undone by storing old_contents into *where. */
393 struct undo
394 {
399 };
401 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
402 num_undo says how many are currently recorded.
404 other_insn is nonzero if we have modified some other insn in the process
405 of working on subst_insn. It must be verified too. */
407 struct undobuf
408 {
412 };
416 /* Number of times the pseudo being substituted for
417 was found and replaced. */
422 scalar_int_mode,
425 scalar_int_mode,
498 \f
500 /* It is not safe to use ordinary gen_lowpart in combine.
501 See comments in gen_lowpart_for_combine. */
502 #undef RTL_HOOKS_GEN_LOWPART
503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
505 /* Our implementation of gen_lowpart never emits a new pseudo. */
506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
520 \f
521 /* Convenience wrapper for the canonicalize_comparison target hook.
522 Target hooks cannot use enum rtx_code. */
526 {
530 }
532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
533 PATTERN can not be split. Otherwise, it returns an insn sequence.
534 This is a wrapper around split_insns which ensures that the
535 reg_stat vector is made larger if the splitter creates a new
536 register. */
540 {
549 }
551 /* This is used by find_single_use to locate an rtx in LOC that
552 contains exactly one use of DEST, which is typically either a REG
553 or CC0. It returns a pointer to the innermost rtx expression
554 containing DEST. Appearances of DEST that are being used to
555 totally replace it are not counted. */
559 {
568 {
572 CASE_CONST_ANY:
577 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
578 of a REG that occupies all of the REG, the insn uses DEST if
579 it is mentioned in the destination or the source. Otherwise, we
580 need just check the source. */
597 }
599 /* If it wasn't one of the common cases above, check each expression and
600 vector of this code. Look for a unique usage of DEST. */
604 {
606 {
611 else
617 /* Duplicate usage. */
619 }
621 {
625 {
631 else
638 }
639 }
640 }
643 }
646 /* See if DEST, produced in INSN, is used only a single time in the
647 sequel. If so, return a pointer to the innermost rtx expression in which
648 it is used.
650 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
652 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
653 care about REG_DEAD notes or LOG_LINKS.
655 Otherwise, we find the single use by finding an insn that has a
656 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
657 only referenced once in that insn, we know that it must be the first
658 and last insn referencing DEST. */
662 {
663 basic_block bb;
669 {
679 }
689 {
695 {
700 }
701 }
704 }
705 \f
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
710 the undo table. */
712 static void
714 {
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
728 {
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
744 }
748 else
757 }
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
763 not safe. */
765 static void
767 {
776 else
785 }
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
792 well. */
794 static void
796 {
805 else
814 }
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
818 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 static void
822 {
831 else
840 }
842 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 \f
844 /* Subroutine of try_combine. Determine whether the replacement patterns
845 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
846 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
847 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
848 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
849 of all the instructions can be estimated and the replacements are more
850 expensive than the original sequence. */
852 static bool
855 {
860 /* Lookup the original insn_costs. */
865 {
868 {
872 }
873 else
874 {
878 }
879 }
880 else
881 {
884 }
886 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 correct that. */
892 /* Calculate the replacement insn_costs. */
901 {
911 }
912 else
913 {
916 }
919 {
928 optimize_this_for_speed_p);
932 {
935 }
936 else
938 }
940 /* Disallow this combination if both new_cost and old_cost are greater than
941 zero, and new_cost is greater than old cost. */
945 {
964 else
966 }
971 /* Update the uid_insn_cost array with the replacement costs. */
975 {
979 }
982 }
985 /* Delete any insns that copy a register to itself. */
987 static void
989 {
991 basic_block bb;
994 {
996 {
999 {
1004 }
1005 }
1006 }
1007 }
1009 \f
1010 /* Return false if we do not want to (or cannot) combine DEF. */
1011 static bool
1013 {
1014 /* Do not consider if it is pre/post modification in MEM. */
1020 /* Do not combine frame pointer adjustments. */
1023 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1031 }
1033 /* Return false if we do not want to (or cannot) combine USE. */
1034 static bool
1036 {
1037 /* Do not consider the usage of the stack pointer by function call. */
1042 }
1044 /* Fill in log links field for all insns. */
1046 static void
1048 {
1049 basic_block bb;
1056 /* Pass through each block from the end, recording the uses of each
1057 register and establishing log links when def is encountered.
1058 Note that we do not clear next_use array in order to save time,
1059 so we have to test whether the use is in the same basic block as def.
1061 There are a few cases below when we do not consider the definition or
1062 usage -- these are taken from original flow.c did. Don't ask me why it is
1063 done this way; I don't know and if it works, I don't want to know. */
1066 {
1068 {
1072 /* Log links are created only once. */
1076 {
1092 /* flow.c claimed:
1094 We don't build a LOG_LINK for hard registers contained
1095 in ASM_OPERANDs. If these registers get replaced,
1096 we might wind up changing the semantics of the insn,
1097 even if reload can make what appear to be valid
1098 assignments later. */
1103 /* Don't add duplicate links between instructions. */
1112 }
1117 }
1118 }
1121 }
1123 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1124 true if we found a LOG_LINK that proves that A feeds B. This only works
1125 if there are no instructions between A and B which could have a link
1126 depending on A, since in that case we would not record a link for B.
1127 We also check the implicit dependency created by a cc0 setter/user
1128 pair. */
1130 static bool
1132 {
1140 }
1141 \f
1142 /* Main entry point for combiner. F is the first insn of the function.
1143 NREGS is the first unused pseudo-reg number.
1145 Return nonzero if the combiner has turned an indirect jump
1146 instruction into a direct jump. */
1147 static int
1149 {
1154 basic_block last_bb;
1174 /* Allocate array for insn info. */
1182 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1183 problems when, for example, we have j <<= 1 in a loop. */
1188 /* Scan all SETs and see if we can deduce anything about what
1189 bits are known to be zero for some registers and how many copies
1190 of the sign bit are known to exist for those registers.
1192 Also set any known values so that we can use it while searching
1193 for what bits are known to be set. */
1196 /* Allow the entry block and the first block to fall into the same EBB.
1197 Conceptually the incoming promotions are assigned to the entry block. */
1202 {
1207 label_tick++;
1215 {
1216 rtx links;
1222 insn);
1229 insn);
1231 /* Record the current insn_cost of this instruction. */
1235 {
1238 }
1239 }
1240 }
1244 /* Now scan all the insns in forward order. */
1252 {
1255 /* Ignore instruction combination in basic blocks that are going to
1256 be removed as unreachable anyway. See PR82386. */
1264 label_tick++;
1274 {
1288 /* See if we know about function return values before this
1289 insn based upon SUBREG flags. */
1292 /* See if we can find hardregs and subreg of pseudos in
1293 narrower modes. This could help turning TRUNCATEs
1294 into SUBREGs. */
1297 /* Try this insn with each insn it links back to. */
1303 {
1306 }
1308 /* Try each sequence of three linked insns ending with this one. */
1312 {
1315 /* If the linked insn has been replaced by a note, then there
1316 is no point in pursuing this chain any further. */
1324 {
1327 }
1328 }
1330 /* Try to combine a jump insn that uses CC0
1331 with a preceding insn that sets CC0, and maybe with its
1332 logical predecessor as well.
1333 This is how we make decrement-and-branch insns.
1334 We need this special code because data flow connections
1335 via CC0 do not get entered in LOG_LINKS. */
1342 {
1353 }
1355 /* Do the same for an insn that explicitly references CC0. */
1362 {
1373 }
1375 /* Finally, see if any of the insns that this insn links to
1376 explicitly references CC0. If so, try this insn, that insn,
1377 and its predecessor if it sets CC0. */
1379 {
1391 }
1393 /* Try combining an insn with two different insns whose results it
1394 uses. */
1404 {
1407 }
1409 /* Try four-instruction combinations. */
1412 {
1416 /* If the linked insn has been replaced by a note, then there
1417 is no point in pursuing this chain any further. */
1422 {
1426 /* I0 -> I1 -> I2 -> I3. */
1432 {
1435 }
1436 /* I0, I1 -> I2, I2 -> I3. */
1443 {
1446 }
1447 }
1450 {
1454 /* I0 -> I2; I1, I2 -> I3. */
1460 {
1463 }
1464 /* I0 -> I1; I1, I2 -> I3. */
1470 {
1473 }
1474 }
1475 }
1477 /* Try this insn with each REG_EQUAL note it links back to. */
1479 {
1485 /* Avoid using a register that may already been marked
1486 dead by an earlier instruction. */
1494 {
1495 /* Temporarily replace the set's source with the
1496 contents of the REG_EQUAL note. The insn will
1497 be deleted or recognized by try_combine. */
1508 last_combined_insn);
1511 {
1514 }
1517 }
1518 }
1523 retry:
1524 ;
1525 }
1526 }
1533 /* Clean up. */
1539 {
1542 {
1545 }
1547 }
1557 /* Make recognizer allow volatile MEMs again. */
1561 }
1563 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1565 static void
1567 {
1573 }
1574 \f
1575 /* Set up any promoted values for incoming argument registers. */
1577 static void
1579 {
1580 tree arg;
1585 {
1590 /* Only continue if the incoming argument is in a register. */
1594 /* Determine, if possible, whether all call sites of the current
1595 function lie within the current compilation unit. (This does
1596 take into account the exporting of a function via taking its
1597 address, and so forth.) */
1600 /* The mode and signedness of the argument before any promotions happen
1601 (equal to the mode of the pseudo holding it at that stage). */
1605 /* The mode and signedness of the argument after any source language and
1606 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1610 /* The mode and signedness of the argument as it is actually passed,
1611 see assign_parm_setup_reg in function.c. */
1615 /* The mode of the register in which the argument is being passed. */
1618 /* Eliminate sign extensions in the callee when:
1619 (a) A mode promotion has occurred; */
1622 /* (b) The mode of the register is the same as the mode of
1623 the argument as it is passed; */
1626 /* (c) There's no language level extension; */
1628 ;
1629 /* (c.1) All callers are from the current compilation unit. If that's
1630 the case we don't have to rely on an ABI, we only have to know
1631 what we're generating right now, and we know that we will do the
1632 mode1 to mode2 promotion with the given sign. */
1635 /* (c.2) The combination of the two promotions is useful. This is
1636 true when the signs match, or if the first promotion is unsigned.
1637 In the later case, (sign_extend (zero_extend x)) is the same as
1638 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1644 /* Record that the value was promoted from mode1 to mode3,
1645 so that any sign extension at the head of the current
1646 function may be eliminated. */
1650 }
1651 }
1653 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1654 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1655 because some machines (maybe most) will actually do the sign-extension and
1656 this is the conservative approach.
1658 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1659 kludge. */
1661 static rtx
1663 {
1664 scalar_int_mode int_mode;
1673 }
1675 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1676 and SET. */
1678 static void
1680 rtx x)
1681 {
1691 {
1695 }
1697 /* Don't call nonzero_bits if it cannot change anything. */
1699 {
1704 }
1706 /* Don't call num_sign_bit_copies if it cannot change anything. */
1708 {
1711 {
1715 }
1718 }
1719 }
1721 /* Called via note_stores. If X is a pseudo that is narrower than
1722 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1724 If we are setting only a portion of X and we can't figure out what
1725 portion, assume all bits will be used since we don't know what will
1726 be happening.
1728 Similarly, set how many bits of X are known to be copies of the sign bit
1729 at all locations in the function. This is the smallest number implied
1730 by any set of X. */
1732 static void
1734 {
1736 scalar_int_mode mode;
1740 /* If this register is undefined at the start of the file, we can't
1741 say what its contents were. */
1742 && ! REGNO_REG_SET_P
1746 {
1750 {
1754 }
1756 /* If this register is being initialized using itself, and the
1757 register is uninitialized in this basic block, and there are
1758 no LOG_LINKS which set the register, then part of the
1759 register is uninitialized. In that case we can't assume
1760 anything about the number of nonzero bits.
1762 ??? We could do better if we checked this in
1763 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1764 could avoid making assumptions about the insn which initially
1765 sets the register, while still using the information in other
1766 insns. We would have to be careful to check every insn
1767 involved in the combination. */
1773 {
1780 {
1784 }
1785 }
1787 /* If this is a complex assignment, see if we can convert it into a
1788 simple assignment. */
1791 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1792 set what we know about X. */
1798 else
1799 {
1802 }
1803 }
1804 }
1805 \f
1806 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1807 optionally insns that were previously combined into I3 or that will be
1808 combined into the merger of INSN and I3. The order is PRED, PRED2,
1809 INSN, SUCC, SUCC2, I3.
1811 Return 0 if the combination is not allowed for any reason.
1813 If the combination is allowed, *PDEST will be set to the single
1814 destination of INSN and *PSRC to the single source, and this function
1815 will return 1. */
1817 static int
1821 {
1826 rtx link;
1831 {
1833 {
1838 }
1843 }
1847 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1848 or a PARALLEL consisting of such a SET and CLOBBERs.
1850 If INSN has CLOBBER parallel parts, ignore them for our processing.
1851 By definition, these happen during the execution of the insn. When it
1852 is merged with another insn, all bets are off. If they are, in fact,
1853 needed and aren't also supplied in I3, they may be added by
1854 recog_for_combine. Otherwise, it won't match.
1856 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1857 note.
1859 Get the source and destination of INSN. If more than one, can't
1860 combine. */
1866 {
1868 {
1872 {
1873 /* This is important to combine floating point insns
1874 for the SH4 port. */
1876 /* Combining an isolated USE doesn't make sense.
1877 We depend here on combinable_i3pat to reject them. */
1878 /* The code below this loop only verifies that the inputs of
1879 the SET in INSN do not change. We call reg_set_between_p
1880 to verify that the REG in the USE does not change between
1881 I3 and INSN.
1882 If the USE in INSN was for a pseudo register, the matching
1883 insn pattern will likely match any register; combining this
1884 with any other USE would only be safe if we knew that the
1885 used registers have identical values, or if there was
1886 something to tell them apart, e.g. different modes. For
1887 now, we forgo such complicated tests and simply disallow
1888 combining of USES of pseudo registers with any other USE. */
1891 {
1896 do
1897 {
1907 }
1909 }
1912 /* We can ignore CLOBBERs. */
1917 /* Ignore SETs whose result isn't used but not those that
1918 have side-effects. */
1924 /* If we have already found a SET, this is a second one and
1925 so we cannot combine with this insn. */
1933 /* Anything else means we can't combine. */
1935 }
1936 }
1939 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1940 so don't do anything with it. */
1943 }
1944 else
1950 /* The simplification in expand_field_assignment may call back to
1951 get_last_value, so set safe guard here. */
1957 /* Do not eliminate user-specified register if it is in an
1958 asm input because we may break the register asm usage defined
1959 in GCC manual if allow to do so.
1960 Be aware that this may cover more cases than we expect but this
1961 should be harmless. */
1966 /* Don't eliminate a store in the stack pointer. */
1968 /* Don't combine with an insn that sets a register to itself if it has
1969 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1971 /* Can't merge an ASM_OPERANDS. */
1973 /* Can't merge a function call. */
1975 /* Don't eliminate a function call argument. */
1981 /* Don't substitute into an incremented register. */
1985 /* Don't substitute into a non-local goto, this confuses CFG. */
1987 /* Make sure that DEST is not used after INSN but before SUCC, or
1988 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1989 || (!all_adjacent
1990 && ((succ2
1994 || (succ
1995 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1996 that case SUCC is not in the insn stream, so use SUCC2
1997 instead for this test. */
1999 succ2
2002 /* Make sure that the value that is to be substituted for the register
2003 does not use any registers whose values alter in between. However,
2004 If the insns are adjacent, a use can't cross a set even though we
2005 think it might (this can happen for a sequence of insns each setting
2006 the same destination; last_set of that register might point to
2007 a NOTE). If INSN has a REG_EQUIV note, the register is always
2008 equivalent to the memory so the substitution is valid even if there
2009 are intervening stores. Also, don't move a volatile asm or
2010 UNSPEC_VOLATILE across any other insns. */
2011 || (! all_adjacent
2017 /* Don't combine across a CALL_INSN, because that would possibly
2018 change whether the life span of some REGs crosses calls or not,
2019 and it is a pain to update that information.
2020 Exception: if source is a constant, moving it later can't hurt.
2021 Accept that as a special case. */
2025 /* DEST must either be a REG or CC0. */
2027 {
2028 /* If register alignment is being enforced for multi-word items in all
2029 cases except for parameters, it is possible to have a register copy
2030 insn referencing a hard register that is not allowed to contain the
2031 mode being copied and which would not be valid as an operand of most
2032 insns. Eliminate this problem by not combining with such an insn.
2034 Also, on some machines we don't want to extend the life of a hard
2035 register. */
2040 /* Don't extend the life of a hard register unless it is
2041 user variable (if we have few registers) or it can't
2042 fit into the desired register (meaning something special
2043 is going on).
2044 Also avoid substituting a return register into I3, because
2045 reload can't handle a conflict with constraints of other
2046 inputs. */
2051 }
2059 {
2062 /* If the clobber represents an earlyclobber operand, we must not
2063 substitute an expression containing the clobbered register.
2064 As we do not analyze the constraint strings here, we have to
2065 make the conservative assumption. However, if the register is
2066 a fixed hard reg, the clobber cannot represent any operand;
2067 we leave it up to the machine description to either accept or
2068 reject use-and-clobber patterns. */
2074 }
2076 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2077 or not), reject, unless nothing volatile comes between it and I3 */
2080 {
2081 /* Make sure neither succ nor succ2 contains a volatile reference. */
2086 /* We'll check insns between INSN and I3 below. */
2087 }
2089 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2090 to be an explicit register variable, and was chosen for a reason. */
2096 /* If INSN contains volatile references (specifically volatile MEMs),
2097 we cannot combine across any other volatile references.
2098 Even if INSN doesn't contain volatile references, any intervening
2099 volatile insn might affect machine state. */
2102 ? volatile_refs_p
2109 /* If INSN contains an autoincrement or autodecrement, make sure that
2110 register is not used between there and I3, and not already used in
2111 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2112 Also insist that I3 not be a jump; if it were one
2113 and the incremented register were spilled, we would lose. */
2131 /* Don't combine an insn that follows a CC0-setting insn.
2132 An insn that uses CC0 must not be separated from the one that sets it.
2133 We do, however, allow I2 to follow a CC0-setting insn if that insn
2134 is passed as I1; in that case it will be deleted also.
2135 We also allow combining in this case if all the insns are adjacent
2136 because that would leave the two CC0 insns adjacent as well.
2137 It would be more logical to test whether CC0 occurs inside I1 or I2,
2138 but that would be much slower, and this ought to be equivalent. */
2141 {
2146 }
2148 /* If we get here, we have passed all the tests and the combination is
2149 to be allowed. */
2155 }
2156 \f
2157 /* LOC is the location within I3 that contains its pattern or the component
2158 of a PARALLEL of the pattern. We validate that it is valid for combining.
2160 One problem is if I3 modifies its output, as opposed to replacing it
2161 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2162 doing so would produce an insn that is not equivalent to the original insns.
2164 Consider:
2166 (set (reg:DI 101) (reg:DI 100))
2167 (set (subreg:SI (reg:DI 101) 0) <foo>)
2169 This is NOT equivalent to:
2171 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2172 (set (reg:DI 101) (reg:DI 100))])
2174 Not only does this modify 100 (in which case it might still be valid
2175 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2177 We can also run into a problem if I2 sets a register that I1
2178 uses and I1 gets directly substituted into I3 (not via I2). In that
2179 case, we would be getting the wrong value of I2DEST into I3, so we
2180 must reject the combination. This case occurs when I2 and I1 both
2181 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2182 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2183 of a SET must prevent combination from occurring. The same situation
2184 can occur for I0, in which case I0_NOT_IN_SRC is set.
2186 Before doing the above check, we first try to expand a field assignment
2187 into a set of logical operations.
2189 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2190 we place a register that is both set and used within I3. If more than one
2191 such register is detected, we fail.
2193 Return 1 if the combination is valid, zero otherwise. */
2195 static int
2198 {
2202 {
2207 rtx subdest;
2214 /* Check for the case where I3 modifies its output, as discussed
2215 above. We don't want to prevent pseudos from being combined
2216 into the address of a MEM, so only prevent the combination if
2217 i1 or i2 set the same MEM. */
2227 /* This is the same test done in can_combine_p except we can't test
2228 all_adjacent; we don't have to, since this instruction will stay
2229 in place, thus we are not considering increasing the lifetime of
2230 INNER_DEST.
2232 Also, if this insn sets a function argument, combining it with
2233 something that might need a spill could clobber a previous
2234 function argument; the all_adjacent test in can_combine_p also
2235 checks this; here, we do a more specific test for this case. */
2245 /* If DEST is used in I3, it is being killed in this insn, so
2246 record that for later. We have to consider paradoxical
2247 subregs here, since they kill the whole register, but we
2248 ignore partial subregs, STRICT_LOW_PART, etc.
2249 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2250 STACK_POINTER_REGNUM, since these are always considered to be
2251 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2259 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2265 {
2270 }
2271 }
2274 {
2281 }
2284 }
2285 \f
2286 /* Return 1 if X is an arithmetic expression that contains a multiplication
2287 and division. We don't count multiplications by powers of two here. */
2289 static int
2291 {
2293 {
2309 }
2310 }
2311 \f
2312 /* Determine whether INSN can be used in a combination. Return nonzero if
2313 not. This is used in try_combine to detect early some cases where we
2314 can't perform combinations. */
2316 static int
2318 {
2319 rtx set;
2322 /* If this isn't really an insn, we can't do anything.
2323 This can occur when flow deletes an insn that it has merged into an
2324 auto-increment address. */
2328 /* Never combine loads and stores involving hard regs that are likely
2329 to be spilled. The register allocator can usually handle such
2330 reg-reg moves by tying. If we allow the combiner to make
2331 substitutions of likely-spilled regs, reload might die.
2332 As an exception, we allow combinations involving fixed regs; these are
2333 not available to the register allocator so there's no risk involved. */
2354 }
2356 struct likely_spilled_retval_info
2357 {
2360 };
2362 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2363 hard registers that are known to be written to / clobbered in full. */
2364 static void
2366 {
2383 else
2386 }
2388 /* Return nonzero iff part of the return value is live during INSN, and
2389 it is likely spilled. This can happen when more than one insn is needed
2390 to copy the return value, e.g. when we consider to combine into the
2391 second copy insn for a complex value. */
2393 static int
2395 {
2397 rtx reg;
2400 /* We assume here that no machine mode needs more than
2401 32 hard registers when the value overlaps with a register
2402 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2417 /* Disregard parts of the return value that are set later. */
2426 /* Check if any of the (probably) live return value registers is
2427 likely spilled. */
2428 nregs --;
2429 do
2430 {
2436 }
2438 /* Adjust INSN after we made a change to its destination.
2440 Changing the destination can invalidate notes that say something about
2441 the results of the insn and a LOG_LINK pointing to the insn. */
2443 static void
2445 {
2446 /* For notes, be conservative and simply remove them. */
2449 /* The new insn will have a destination that was previously the destination
2450 of an insn just above it. Call distribute_links to make a LOG_LINK from
2451 the next use of that destination. */
2467 }
2469 /* Return TRUE if combine can reuse reg X in mode MODE.
2470 ADDED_SETS is nonzero if the original set is still required. */
2471 static bool
2473 {
2479 /* Don't change between modes with different underlying register sizes,
2480 since this could lead to invalid subregs. */
2486 /* Allow hard registers if the new mode is legal, and occupies no more
2487 registers than the old mode. */
2492 /* Or a pseudo that is only used once. */
2495 && !added_sets
2497 }
2500 /* Check whether X, the destination of a set, refers to part of
2501 the register specified by REG. */
2503 static bool
2505 {
2506 /* Check that reg is an integer mode register. */
2517 }
2519 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2520 Note that the INSN should be deleted *after* removing dead edges, so
2521 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2522 but not for a (set (pc) (label_ref FOO)). */
2524 static void
2526 {
2534 {
2539 /* Remove barriers from the footer if there are any. */
2542 {
2545 else
2549 }
2552 }
2553 }
2555 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2556 by an arbitrary number of CLOBBERs. */
2557 static bool
2559 {
2578 }
2580 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2581 CLOBBERs), can be split into individual SETs in that order, without
2582 changing semantics. */
2583 static bool
2585 {
2593 {
2602 }
2605 }
2607 /* Try to combine the insns I0, I1 and I2 into I3.
2608 Here I0, I1 and I2 appear earlier than I3.
2609 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2610 I3.
2612 If we are combining more than two insns and the resulting insn is not
2613 recognized, try splitting it into two insns. If that happens, I2 and I3
2614 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2615 Otherwise, I0, I1 and I2 are pseudo-deleted.
2617 Return 0 if the combination does not work. Then nothing is changed.
2618 If we did the combination, return the insn at which combine should
2619 resume scanning.
2621 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2622 new direct jump instruction.
2624 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2625 been I3 passed to an earlier try_combine within the same basic
2626 block. */
2631 {
2632 /* New patterns for I3 and I2, respectively. */
2636 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2637 dead. */
2639 /* Total number of SETs to put into I3. */
2641 /* Nonzero if I2's or I1's body now appears in I3. */
2643 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2645 /* Contains I3 if the destination of I3 is used in its source, which means
2646 that the old life of I3 is being killed. If that usage is placed into
2647 I2 and not in I3, a REG_DEAD note must be made. */
2649 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2651 /* Copy of SET_SRC of I1 and I0, if needed. */
2653 /* Set if I2DEST was reused as a scratch register. */
2655 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2657 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2662 /* Notes that must be added to REG_NOTES in I3 and I2. */
2664 /* Notes that we substituted I3 into I2 instead of the normal case. */
2666 /* Notes that I1, I2 or I3 is a MULT operation. */
2673 rtx temp_expr;
2676 rtx new_other_notes;
2680 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2681 never be). */
2685 /* Only try four-insn combinations when there's high likelihood of
2686 success. Look for simple insns, such as loads of constants or
2687 binary operations involving a constant. */
2689 {
2699 {
2702 rtx src;
2707 {
2710 }
2712 ngood++;
2715 nshift++;
2716 }
2718 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2719 are likely manipulating its value. Ideally we'll be able to combine
2720 all four insns into a bitfield insertion of some kind.
2722 Note the source in I0 might be inside a sign/zero extension and the
2723 memory modes in I0 and I3 might be different. So extract the address
2724 from the destination of I3 and search for it in the source of I0.
2726 In the event that there's a match but the source/dest do not actually
2727 refer to the same memory, the worst that happens is we try some
2728 combinations that we wouldn't have otherwise. */
2730 /* Ensure the source of SET0 is a MEM, possibly buried inside
2731 an extension. */
2737 /* Ensure the destination of SET3 is a MEM. */
2739 /* Would it be better to extract the base address for the MEM
2740 in SET3 and look for that? I don't have cases where it matters
2741 but I could envision such cases. */
2747 }
2749 /* Exit early if one of the insns involved can't be used for
2750 combinations. */
2761 combine_attempts++;
2764 /* Reset the hard register usage information. */
2768 {
2775 else
2785 }
2787 /* If multiple insns feed into one of I2 or I3, they can be in any
2788 order. To simplify the code below, reorder them in sequence. */
2799 /* First check for one important special case that the code below will
2800 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2801 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2802 we may be able to replace that destination with the destination of I3.
2803 This occurs in the common code where we compute both a quotient and
2804 remainder into a structure, in which case we want to do the computation
2805 directly into the structure to avoid register-register copies.
2807 Note that this case handles both multiple sets in I2 and also cases
2808 where I2 has a number of CLOBBERs inside the PARALLEL.
2810 We make very conservative checks below and only try to handle the
2811 most common cases of this. For example, we only handle the case
2812 where I2 and I3 are adjacent to avoid making difficult register
2813 usage tests. */
2821 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2822 below would need to check what is inside (and reg_overlap_mentioned_p
2823 doesn't support those codes anyway). Don't allow those destinations;
2824 the resulting insn isn't likely to be recognized anyway. */
2830 {
2833 /* Make sure that the destination of I3,
2834 which we are going to substitute into one output of I2,
2835 is not used within another output of I2. We must avoid making this:
2836 (parallel [(set (mem (reg 69)) ...)
2837 (set (reg 69) ...)])
2838 which is not well-defined as to order of actions.
2839 (Besides, reload can't handle output reloads for this.)
2841 The problem can also happen if the dest of I3 is a memory ref,
2842 if another dest in I2 is an indirect memory ref.
2844 Neither can this PARALLEL be an asm. We do not allow combining
2845 that usually (see can_combine_p), so do not here either. */
2848 {
2857 }
2863 {
2864 combine_merges++;
2874 /* Replace the dest in I2 with our dest and make the resulting
2875 insn the new pattern for I3. Then skip to where we validate
2876 the pattern. Everything was set up above. */
2881 }
2882 }
2884 /* If I2 is setting a pseudo to a constant and I3 is setting some
2885 sub-part of it to another constant, merge them by making a new
2886 constant. */
2894 {
2901 {
2906 {
2912 }
2913 }
2914 else
2915 {
2919 {
2922 }
2923 }
2926 {
2927 /* If this is the low part, we're done. */
2929 ;
2930 /* Handle the case where inner is twice the size of outer. */
2934 /* Otherwise give up for now. */
2935 else
2937 }
2940 {
2948 combine_merges++;
2955 /* Replace the source in I2 with the new constant and make the
2956 resulting insn the new pattern for I3. Then skip to where we
2957 validate the pattern. Everything was set up above. */
2963 /* The dest of I3 has been replaced with the dest of I2. */
2966 }
2967 }
2969 /* If we have no I1 and I2 looks like:
2970 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2971 (set Y OP)])
2972 make up a dummy I1 that is
2973 (set Y OP)
2974 and change I2 to be
2975 (set (reg:CC X) (compare:CC Y (const_int 0)))
2977 (We can ignore any trailing CLOBBERs.)
2979 This undoes a previous combination and allows us to match a branch-and-
2980 decrement insn. */
2992 {
2993 /* We make I1 with the same INSN_UID as I2. This gives it
2994 the same DF_INSN_LUID for value tracking. Our fake I1 will
2995 never appear in the insn stream so giving it the same INSN_UID
2996 as I2 will not cause a problem. */
3009 }
3011 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3012 make those two SETs separate I1 and I2 insns, and make an I0 that is
3013 the original I1. */
3020 {
3021 /* If there is no I1, there is no I0 either. */
3024 /* We make I1 with the same INSN_UID as I2. This gives it
3025 the same DF_INSN_LUID for value tracking. Our fake I1 will
3026 never appear in the insn stream so giving it the same INSN_UID
3027 as I2 will not cause a problem. */
3035 }
3037 /* Verify that I2 and I1 are valid for combining. */
3043 {
3046 }
3048 /* Record whether I2DEST is used in I2SRC and similarly for the other
3049 cases. Knowing this will help in register status updating below. */
3060 /* For the earlier insns, determine which of the subsequent ones they
3061 feed. */
3068 /* Ensure that I3's pattern can be the destination of combines. */
3074 {
3077 }
3079 /* See if any of the insns is a MULT operation. Unless one is, we will
3080 reject a combination that is, since it must be slower. Be conservative
3081 here. */
3089 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3090 We used to do this EXCEPT in one case: I3 has a post-inc in an
3091 output operand. However, that exception can give rise to insns like
3092 mov r3,(r3)+
3093 which is a famous insn on the PDP-11 where the value of r3 used as the
3094 source was model-dependent. Avoid this sort of thing. */
3096 #if 0
3102 /* It's not the exception. */
3103 #endif
3105 {
3106 rtx link;
3112 {
3115 }
3116 }
3118 /* See if the SETs in I1 or I2 need to be kept around in the merged
3119 instruction: whenever the value set there is still needed past I3.
3120 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3122 For the SET in I1, we have two cases: if I1 and I2 independently feed
3123 into I3, the set in I1 needs to be kept around unless I1DEST dies
3124 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3125 in I1 needs to be kept around unless I1DEST dies or is set in either
3126 I2 or I3. The same considerations apply to I0. */
3133 else
3141 else
3144 /* We are about to copy insns for the case where they need to be kept
3145 around. Check that they can be copied in the merged instruction. */
3151 {
3154 }
3156 /* If the set in I2 needs to be kept around, we must make a copy of
3157 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3158 PATTERN (I2), we are only substituting for the original I1DEST, not into
3159 an already-substituted copy. This also prevents making self-referential
3160 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3161 I2DEST. */
3164 {
3167 else
3169 }
3172 {
3175 else
3177 }
3180 {
3183 else
3185 }
3187 combine_merges++;
3189 /* Substitute in the latest insn for the regs set by the earlier ones. */
3195 /* Many machines that don't use CC0 have insns that can both perform an
3196 arithmetic operation and set the condition code. These operations will
3197 be represented as a PARALLEL with the first element of the vector
3198 being a COMPARE of an arithmetic operation with the constant zero.
3199 The second element of the vector will set some pseudo to the result
3200 of the same arithmetic operation. If we simplify the COMPARE, we won't
3201 match such a pattern and so will generate an extra insn. Here we test
3202 for this case, where both the comparison and the operation result are
3203 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3204 I2SRC. Later we will make the PARALLEL that contains I2. */
3210 {
3211 rtx newpat_dest;
3217 scalar_int_mode mode;
3226 {
3232 }
3234 /* Do the rest only if op1 is const0_rtx, which may be the
3235 result of simplification. */
3237 {
3238 /* If a single use of the CC is found, prepare to modify it
3239 when SELECT_CC_MODE returns a new CC-class mode, or when
3240 the above simplify_compare_const() returned a new comparison
3241 operator. undobuf.other_insn is assigned the CC use insn
3242 when modifying it. */
3244 {
3245 #ifdef SELECT_CC_MODE
3246 machine_mode new_mode
3251 {
3256 else
3257 {
3260 }
3261 }
3262 #endif
3263 /* Cases for modifying the CC-using comparison. */
3265 /* ??? Do we need to verify the zero rtx? */
3267 {
3268 /* Replace cc_use_loc with entire new RTX. */
3273 }
3275 {
3276 /* Just replace the CC reg with a new mode. */
3279 }
3280 }
3282 /* Now we modify the current newpat:
3283 First, SET_DEST(newpat) is updated if the CC mode has been
3284 altered. For targets without SELECT_CC_MODE, this should be
3285 optimized away. */
3288 /* This is always done to propagate i2src into newpat. */
3291 /* Create new version of i2pat if needed; the below PARALLEL
3292 creation needs this to work correctly. */
3296 }
3297 }
3300 {
3301 /* It is possible that the source of I2 or I1 may be performing
3302 an unneeded operation, such as a ZERO_EXTEND of something
3303 that is known to have the high part zero. Handle that case
3304 by letting subst look at the inner insns.
3306 Another way to do this would be to have a function that tries
3307 to simplify a single insn instead of merging two or more
3308 insns. We don't do this because of the potential of infinite
3309 loops and because of the potential extra memory required.
3310 However, doing it the way we are is a bit of a kludge and
3311 doesn't catch all cases.
3313 But only do this if -fexpensive-optimizations since it slows
3314 things down and doesn't usually win.
3316 This is not done in the COMPARE case above because the
3317 unmodified I2PAT is used in the PARALLEL and so a pattern
3318 with a modified I2SRC would not match. */
3321 {
3322 /* Pass pc_rtx so no substitutions are done, just
3323 simplifications. */
3325 {
3328 }
3332 }
3337 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3338 copy of I2SRC each time we substitute it, in order to avoid creating
3339 self-referential RTL when we will be substituting I1SRC for I1DEST
3340 later. Likewise if I0 feeds into I2, either directly or indirectly
3341 through I1, and I0DEST is in I0SRC. */
3348 /* Record whether I2's body now appears within I3's body. */
3350 }
3352 /* If we already got a failure, don't try to do more. Otherwise, try to
3353 substitute I1 if we have it. */
3356 {
3357 /* Check that an autoincrement side-effect on I1 has not been lost.
3358 This happens if I1DEST is mentioned in I2 and dies there, and
3359 has disappeared from the new pattern. */
3361 && i1_feeds_i2_n
3364 /* Before we can do this substitution, we must redo the test done
3365 above (see detailed comments there) that ensures I1DEST isn't
3366 mentioned in any SETs in NEWPAT that are field assignments. */
3369 {
3372 }
3377 /* If the following substitution will modify I1SRC, make a copy of it
3378 for the case where it is substituted for I1DEST in I2PAT later. */
3382 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3383 copy of I1SRC each time we substitute it, in order to avoid creating
3384 self-referential RTL when we will be substituting I0SRC for I0DEST
3385 later. */
3390 /* Record whether I1's body now appears within I3's body. */
3392 }
3394 /* Likewise for I0 if we have it. */
3397 {
3404 {
3407 }
3409 /* If the following substitution will modify I0SRC, make a copy of it
3410 for the case where it is substituted for I0DEST in I1PAT later. */
3413 /* And a copy for I0DEST in I2PAT substitution. */
3422 }
3424 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3425 to count all the ways that I2SRC and I1SRC can be used. */
3436 /* Fail if we tried to make a new register. */
3438 /* Fail if we couldn't do something and have a CLOBBER. */
3440 /* Fail if this new pattern is a MULT and we didn't have one before
3441 at the outer level. */
3444 {
3447 }
3449 /* If the actions of the earlier insns must be kept
3450 in addition to substituting them into the latest one,
3451 we must make a new PARALLEL for the latest insn
3452 to hold additional the SETs. */
3455 {
3457 combine_extras++;
3460 {
3466 }
3467 else
3468 {
3473 }
3479 {
3485 }
3487 {
3496 }
3497 }
3499 validate_replacement:
3501 /* Note which hard regs this insn has as inputs. */
3504 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3505 consider splitting this pattern, we might need these clobbers. */
3508 {
3514 }
3516 /* We have recognized nothing yet. */
3519 /* See if this is a PARALLEL of two SETs where one SET's destination is
3520 a register that is unused and this isn't marked as an instruction that
3521 might trap in an EH region. In that case, we just need the other SET.
3522 We prefer this over the PARALLEL.
3524 This can occur when simplifying a divmod insn. We *must* test for this
3525 case here because the code below that splits two independent SETs doesn't
3526 handle this case correctly when it updates the register status.
3528 It's pointless doing this if we originally had two sets, one from
3529 i3, and one from i2. Combining then splitting the parallel results
3530 in the original i2 again plus an invalid insn (which we delete).
3531 The net effect is only to move instructions around, which makes
3532 debug info less accurate.
3534 If the remaining SET came from I2 its destination should not be used
3535 between I2 and I3. See PR82024. */
3540 {
3551 {
3554 }
3563 {
3568 {
3574 }
3575 }
3579 }
3581 /* Is the result of combination a valid instruction? */
3585 /* If we were combining three insns and the result is a simple SET
3586 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3587 insns. There are two ways to do this. It can be split using a
3588 machine-specific method (like when you have an addition of a large
3589 constant) or by combine in the function find_split_point. */
3593 {
3597 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3598 use I2DEST as a scratch register will help. In the latter case,
3599 convert I2DEST to the mode of the source of NEWPAT if we can. */
3603 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3604 inputs of NEWPAT. */
3606 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3607 possible to try that as a scratch reg. This would require adding
3608 more code to make it work though. */
3611 {
3614 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3615 (temporarily, until we are committed to this instruction
3616 combination) does not work: for example, any call to nonzero_bits
3617 on the register (from a splitter in the MD file, for example)
3618 will get the old information, which is invalid.
3620 Since nowadays we can create registers during combine just fine,
3621 we should just create a new one here, not reuse i2dest. */
3623 /* First try to split using the original register as a
3624 scratch register. */
3628 i2dest)));
3631 /* If that didn't work, try changing the mode of I2DEST if
3632 we can. */
3637 {
3639 rtx ni2dest;
3643 else
3644 {
3647 }
3649 parallel = (gen_rtx_PARALLEL
3653 ni2dest))));
3658 {
3666 }
3667 }
3670 }
3672 /* If recog_for_combine has discarded clobbers, try to use them
3673 again for the split. */
3675 {
3678 }
3681 {
3686 }
3690 {
3700 /* If I2 or I3 has multiple SETs, we won't know how to track
3701 register status, so don't use these insns. If I2's destination
3702 is used between I2 and I3, we also can't use these insns. */
3712 /* It is possible that both insns now set the destination of I3.
3713 If so, we must show an extra use of it. */
3716 {
3735 }
3736 }
3738 /* If we can split it and use I2DEST, go ahead and see if that
3739 helps things be recognized. Verify that none of the registers
3740 are set between I2 and I3. */
3744 /* We need I2DEST in the proper mode. If it is a hard register
3745 or the only use of a pseudo, we can change its mode.
3746 Make sure we don't change a hard register to have a mode that
3747 isn't valid for it, or change the number of registers. */
3754 /* We can't overwrite I2DEST if its value is still used by
3755 NEWPAT. */
3757 {
3766 /* *SPLIT may be part of I2SRC, so make sure we have the
3767 original expression around for later debug processing.
3768 We should not need I2SRC any more in other cases. */
3771 else
3774 /* Get NEWDEST as a register in the proper mode. We have already
3775 validated that we can do this. */
3777 {
3780 else
3781 {
3784 }
3785 }
3787 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3788 an ASHIFT. This can occur if it was inside a PLUS and hence
3789 appeared to be a memory address. This is a kludge. */
3794 {
3797 /* Update split_code because we may not have a multiply
3798 anymore. */
3800 }
3802 /* Similarly for (plus (mult FOO (const_int pow2))). */
3808 {
3812 /* Update split_code because we may not have a multiply
3813 anymore. */
3815 }
3817 #ifdef INSN_SCHEDULING
3818 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3819 be written as a ZERO_EXTEND. */
3821 {
3822 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3823 what it really is. */
3828 else
3831 }
3832 #endif
3834 /* Attempt to split binary operators using arithmetic identities. */
3838 {
3845 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3847 {
3852 }
3853 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3860 {
3866 /* Split both "((X op Y) op X) op Y" and
3867 "((X op Y) op Y) op X" as "T op T" where T is
3868 "X op Y". */
3871 {
3876 }
3877 /* Split "((X op X) op Y) op Y)" as "T op T" where
3878 T is "X op Y". */
3880 {
3886 }
3887 }
3888 }
3891 {
3894 }
3898 /* recog_for_combine might have added CLOBBERs to newi2pat.
3899 Make sure NEWPAT does not depend on the clobbered regs. */
3903 {
3906 {
3909 }
3910 }
3912 /* If the split point was a MULT and we didn't have one before,
3913 don't use one now. */
3916 }
3917 }
3919 /* Check for a case where we loaded from memory in a narrow mode and
3920 then sign extended it, but we need both registers. In that case,
3921 we have a PARALLEL with both loads from the same memory location.
3922 We can split this into a load from memory followed by a register-register
3923 copy. This saves at least one insn, more if register allocation can
3924 eliminate the copy.
3926 We cannot do this if the destination of the first assignment is a
3927 condition code register or cc0. We eliminate this case by making sure
3928 the SET_DEST and SET_SRC have the same mode.
3930 We cannot do this if the destination of the second assignment is
3931 a register that we have already assumed is zero-extended. Similarly
3932 for a SUBREG of such a register. */
3967 {
3968 rtx ni2dest;
3982 }
3984 /* Similarly, check for a case where we have a PARALLEL of two independent
3985 SETs but we started with three insns. In this case, we can do the sets
3986 as two separate insns. This case occurs when some SET allows two
3987 other insns to combine, but the destination of that SET is still live.
3989 Also do this if we started with two insns and (at least) one of the
3990 resulting sets is a noop; this noop will be deleted later. */
4009 {
4013 /* Normally, it doesn't matter which of the two is done first,
4014 but the one that references cc0 can't be the second, and
4015 one which uses any regs/memory set in between i2 and i3 can't
4016 be first. The PARALLEL might also have been pre-existing in i3,
4017 so we need to make sure that we won't wrongly hoist a SET to i2
4018 that would conflict with a death note present in there. */
4026 /* If I3 is a jump, ensure that set0 is a jump so that
4027 we do not create invalid RTL. */
4029 )
4030 {
4033 }
4041 /* If I3 is a jump, ensure that set1 is a jump so that
4042 we do not create invalid RTL. */
4044 )
4045 {
4048 }
4049 else
4050 {
4053 }
4058 {
4059 /* recog_for_combine might have added CLOBBERs to newi2pat.
4060 Make sure NEWPAT does not depend on the clobbered regs. */
4062 {
4065 {
4068 {
4071 }
4072 }
4073 }
4076 }
4077 }
4079 /* If it still isn't recognized, fail and change things back the way they
4080 were. */
4082 /* Is the result a reasonable ASM_OPERANDS? */
4084 {
4087 }
4089 /* If we had to change another insn, make sure it is valid also. */
4091 {
4099 {
4102 }
4103 }
4105 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4106 they are adjacent to each other or not. */
4108 {
4112 {
4115 }
4116 }
4118 /* Only allow this combination if insn_cost reports that the
4119 replacement instructions are cheaper than the originals. */
4121 {
4124 }
4127 {
4132 {
4137 /* Temporarily revert mode back. */
4141 {
4142 /* If we used i2dest as a scratch register with a
4143 different mode, substitute it for the original
4144 i2src while its original mode is temporarily
4145 restored, and then clear i2scratch so that we don't
4146 do it again later. */
4148 this_basic_block);
4150 /* Put back the new mode. */
4152 }
4153 else
4154 {
4159 {
4162 }
4163 else
4164 {
4171 }
4173 /* We're dealing with a reg that changed mode but not
4174 meaning, so we want to turn it into a subreg for
4175 the new mode. However, because of REG sharing and
4176 because its mode had already changed, we have to do
4177 it in two steps. First, replace any debug uses of
4178 reg, with its original mode temporarily restored,
4179 with this copy we have created; then, replace the
4180 copy with the SUBREG of the original shared reg,
4181 once again changed to the new mode. */
4183 this_basic_block);
4187 this_basic_block);
4188 }
4189 }
4190 }
4192 /* If we will be able to accept this, we have made a
4193 change to the destination of I3. This requires us to
4194 do a few adjustments. */
4197 {
4200 }
4202 /* We now know that we can do this combination. Merge the insns and
4203 update the status of registers and LOG_LINKS. */
4206 {
4211 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4212 ensure that they are still valid. Then add any non-duplicate
4213 notes added by recog_for_combine. */
4215 {
4224 /* Simply drop equal note since it may be no longer valid
4225 for other_insn. It may be possible to record that CC
4226 register is changed and only discard those notes, but
4227 in practice it's unnecessary complication and doesn't
4228 give any meaningful improvement.
4230 See PR78559. */
4234 }
4238 NULL_RTX);
4239 }
4242 {
4245 rtx ni2dest;
4247 /* I3 now uses what used to be its destination and which is now
4248 I2's destination. This requires us to do a few adjustments. */
4252 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4253 so we still will.
4255 However, some later insn might be using I2's dest and have
4256 a LOG_LINK pointing at I3. We must remove this link.
4257 The simplest way to remove the link is to point it at I1,
4258 which we know will be a NOTE. */
4260 /* newi2pat is usually a SET here; however, recog_for_combine might
4261 have added some clobbers. */
4264 else
4271 {
4274 {
4280 }
4281 }
4282 }
4284 {
4289 /* Compute which registers we expect to eliminate. newi2pat may be setting
4290 either i3dest or i2dest, so we must check it. */
4293 || !i2dest_killed
4295 /* For i1, we need to compute both local elimination and global
4296 elimination information with respect to newi2pat because i1dest
4297 may be the same as i3dest, in which case newi2pat may be setting
4298 i1dest. Global information is used when distributing REG_DEAD
4299 note for i2 and i3, in which case it does matter if newi2pat sets
4300 i1dest or not.
4302 Local information is used when distributing REG_DEAD note for i1,
4303 in which case it doesn't matter if newi2pat sets i1dest or not.
4304 See PR62151, if we have four insns combination:
4305 i0: r0 <- i0src
4306 i1: r1 <- i1src (using r0)
4307 REG_DEAD (r0)
4308 i2: r0 <- i2src (using r1)
4309 i3: r3 <- i3src (using r0)
4310 ix: using r0
4311 From i1's point of view, r0 is eliminated, no matter if it is set
4312 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4313 should be discarded.
4315 Note local information only affects cases in forms like "I1->I2->I3",
4316 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4317 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4318 i0dest anyway. */
4320 || !i1dest_killed
4325 /* Same case as i1. */
4332 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4333 clear them. */
4341 /* Ensure that we do not have something that should not be shared but
4342 occurs multiple times in the new insns. Check this by first
4343 resetting all the `used' flags and then copying anything is shared. */
4367 {
4370 {
4372 {
4373 /* I2SRC must still be meaningful at this point. Some
4374 splitting operations can invalidate I2SRC, but those
4375 operations do not apply to calls. */
4379 }
4386 }
4387 }
4392 /* We had one special case above where I2 had more than one set and
4393 we replaced a destination of one of those sets with the destination
4394 of I3. In that case, we have to update LOG_LINKS of insns later
4395 in this basic block. Note that this (expensive) case is rare.
4397 Also, in this case, we must pretend that all REG_NOTEs for I2
4398 actually came from I3, so that REG_UNUSED notes from I2 will be
4399 properly handled. */
4402 {
4411 temp_insn
4421 {
4426 }
4427 else
4430 }
4438 {
4441 this_basic_block);
4444 }
4445 else
4446 {
4449 this_basic_block);
4451 }
4454 {
4459 this_basic_block);
4461 }
4464 {
4469 this_basic_block);
4471 }
4473 /* Get death notes for everything that is now used in either I3 or
4474 I2 and used to die in a previous insn. If we built two new
4475 patterns, move from I1 to I2 then I2 to I3 so that we get the
4476 proper movement on registers that I2 modifies. */
4482 else
4488 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4505 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4506 know these are REG_UNUSED and want them to go to the desired insn,
4507 so we always pass it as i3. */
4511 NULL_RTX);
4515 NULL_RTX);
4517 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4518 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4519 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4520 in that case, it might delete I2. Similarly for I2 and I1.
4521 Show an additional death due to the REG_DEAD note we make here. If
4522 we discard it in distribute_notes, we will decrement it again. */
4525 {
4530 else
4533 }
4536 {
4541 else
4544 }
4547 {
4552 else
4555 }
4558 {
4563 else
4566 }
4574 {
4579 /* The insn that used to set this register doesn't exist, and
4580 this life of the register may not exist either. See if one of
4581 I3's links points to an insn that sets I2DEST. If it does,
4582 that is now the last known value for I2DEST. If we don't update
4583 this and I2 set the register to a value that depended on its old
4584 contents, we will get confused. If this insn is used, thing
4585 will be set correctly in combine_instructions. */
4593 /* If the reg formerly set in I2 died only once and that was in I3,
4594 zero its use count so it won't make `reload' do any work. */
4597 && ! i2dest_in_i2src
4600 }
4603 {
4616 && ! i1dest_in_i1src
4619 }
4622 {
4635 && ! i0dest_in_i0src
4638 }
4640 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4641 been made to this insn. The order is important, because newi2pat
4642 can affect nonzero_bits of newpat. */
4646 }
4649 {
4651 {
4654 }
4656 }
4659 {
4661 {
4664 }
4666 }
4669 {
4671 {
4674 }
4676 }
4679 {
4681 {
4684 }
4686 }
4689 {
4691 {
4694 }
4696 }
4698 /* Set new_direct_jump_p if a new return or simple jump instruction
4699 has been created. Adjust the CFG accordingly. */
4701 {
4705 }
4710 {
4713 }
4717 {
4723 }
4728 {
4734 }
4736 /* A noop might also need cleaning up of CFG, if it comes from the
4737 simplification of a jump. */
4742 {
4745 }
4752 {
4755 }
4757 combine_successes++;
4767 }
4768 \f
4769 /* Get a marker for undoing to the current state. */
4773 {
4775 }
4777 /* Undo the modifications up to the marker. */
4779 static void
4781 {
4785 {
4790 {
4805 }
4809 }
4812 }
4814 /* Undo all the modifications recorded in undobuf. */
4816 static void
4818 {
4820 }
4822 /* We've committed to accepting the changes we made. Move all
4823 of the undos to the free list. */
4825 static void
4827 {
4831 {
4835 }
4837 }
4838 \f
4839 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4840 where we have an arithmetic expression and return that point. LOC will
4841 be inside INSN.
4843 try_combine will call this function to see if an insn can be split into
4844 two insns. */
4848 {
4858 /* First special-case some codes. */
4860 {
4862 #ifdef INSN_SCHEDULING
4863 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4864 point. */
4867 #endif
4871 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4872 using LO_SUM and HIGH. */
4875 {
4883 }
4885 /* If we have a PLUS whose second operand is a constant and the
4886 address is not valid, perhaps will can split it up using
4887 the machine-specific way to split large constants. We use
4888 the first pseudo-reg (one of the virtual regs) as a placeholder;
4889 it will not remain in the result. */
4894 {
4897 subst_insn);
4899 /* This should have produced two insns, each of which sets our
4900 placeholder. If the source of the second is a valid address,
4901 we can make put both sources together and make a split point
4902 in the middle. */
4915 && memory_address_addr_space_p
4918 {
4922 /* Replace the placeholder in SRC2 with SRC1. If we can
4923 find where in SRC2 it was placed, that can become our
4924 split point and we can replace this address with SRC2.
4925 Just try two obvious places. */
4936 {
4939 }
4940 }
4942 /* If that didn't work, perhaps the first operand is complex and
4943 needs to be computed separately, so make a split point there.
4944 This will occur on machines that just support REG + CONST
4945 and have a constant moved through some previous computation. */
4951 }
4953 /* If we have a PLUS whose first operand is complex, try computing it
4954 separately by making a split there. */
4965 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4966 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4967 we need to put the operand into a register. So split at that
4968 point. */
4978 /* See if we can split SET_SRC as it stands. */
4983 /* See if we can split SET_DEST as it stands. */
4988 /* See if this is a bitfield assignment with everything constant. If
4989 so, this is an IOR of an AND, so split it into that. */
5001 {
5006 unsigned HOST_WIDE_INT mask
5008 rtx or_mask;
5017 else
5018 {
5024 or_mask));
5025 }
5032 }
5034 /* Otherwise, see if this is an operation that we can split into two.
5035 If so, try to split that. */
5039 {
5041 /* If we are AND'ing with a large constant that is only a single
5042 bit and the result is only being used in a context where we
5043 need to know if it is zero or nonzero, replace it with a bit
5044 extraction. This will avoid the large constant, which might
5045 have taken more than one insn to make. If the constant were
5046 not a valid argument to the AND but took only one insn to make,
5047 this is no worse, but if it took more than one insn, it will
5048 be better. */
5058 {
5063 {
5066 }
5067 }
5071 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5072 is known to be on, this can be converted into a NEG of a shift. */
5078 {
5090 }
5096 /* We can't optimize if either mode is a partial integer
5097 mode as we don't know how many bits are significant
5098 in those modes. */
5114 {
5122 }
5127 }
5132 {
5133 /* For unsigned, we have a choice of a shift followed by an
5134 AND or two shifts. Use two shifts for field sizes where the
5135 constant might be too large. We assume here that we can
5136 always at least get 8-bit constants in an AND insn, which is
5137 true for every current RISC. */
5140 {
5141 unsigned HOST_WIDE_INT mask
5145 gen_rtx_LSHIFTRT
5153 }
5154 else
5155 {
5157 gen_rtx_fmt_ee
5168 }
5169 }
5171 /* See if this is a simple operation with a constant as the second
5172 operand. It might be that this constant is out of range and hence
5173 could be used as a split point. */
5181 /* Finally, see if this is a simple operation with its first operand
5182 not in a register. The operation might require this operand in a
5183 register, so return it as a split point. We can always do this
5184 because if the first operand were another operation, we would have
5185 already found it as a split point. */
5194 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5195 it is better to write this as (not (ior A B)) so we can split it.
5196 Similarly for IOR. */
5198 {
5206 }
5208 /* Many RISC machines have a large set of logical insns. If the
5209 second operand is a NOT, put it first so we will try to split the
5210 other operand first. */
5212 {
5216 }
5221 /* Canonicalization can produce (minus A (mult B C)), where C is a
5222 constant. It may be better to try splitting (plus (mult B -C) A)
5223 instead if this isn't a multiply by a power of two. */
5227 {
5235 mode)),
5238 }
5240 /* Split at a multiply-accumulate instruction. However if this is
5241 the SET_SRC, we likely do not have such an instruction and it's
5242 worthless to try this split. */
5251 }
5253 /* Otherwise, select our actions depending on our rtx class. */
5255 {
5261 /* fall through */
5269 /* fall through */
5271 /* Some machines have (and (shift ...) ...) insns. If X is not
5272 an AND, but XEXP (X, 0) is, use it as our split point. */
5282 /* Otherwise, we don't have a split point. */
5284 }
5285 }
5286 \f
5287 /* Throughout X, replace FROM with TO, and return the result.
5288 The result is TO if X is FROM;
5289 otherwise the result is X, but its contents may have been modified.
5290 If they were modified, a record was made in undobuf so that
5291 undo_all will (among other things) return X to its original state.
5293 If the number of changes necessary is too much to record to undo,
5294 the excess changes are not made, so the result is invalid.
5295 The changes already made can still be undone.
5296 undobuf.num_undo is incremented for such changes, so by testing that
5297 the caller can tell whether the result is valid.
5299 `n_occurrences' is incremented each time FROM is replaced.
5301 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5303 IN_COND is nonzero if we are at the top level of a condition.
5305 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5306 by copying if `n_occurrences' is nonzero. */
5308 static rtx
5310 {
5315 rtx new_rtx;
5317 /* Two expressions are equal if they are identical copies of a shared
5318 RTX or if they are both registers with the same register number
5319 and mode. */
5321 #define COMBINE_RTX_EQUAL_P(X,Y) \
5322 ((X) == (Y) \
5323 || (REG_P (X) && REG_P (Y) \
5324 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5326 /* Do not substitute into clobbers of regs -- this will never result in
5327 valid RTL. */
5332 {
5333 n_occurrences++;
5335 }
5337 /* If X and FROM are the same register but different modes, they
5338 will not have been seen as equal above. However, the log links code
5339 will make a LOG_LINKS entry for that case. If we do nothing, we
5340 will try to rerecognize our original insn and, when it succeeds,
5341 we will delete the feeding insn, which is incorrect.
5343 So force this insn not to match in this (rare) case. */
5348 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5349 of which may contain things that can be combined. */
5353 /* It is possible to have a subexpression appear twice in the insn.
5354 Suppose that FROM is a register that appears within TO.
5355 Then, after that subexpression has been scanned once by `subst',
5356 the second time it is scanned, TO may be found. If we were
5357 to scan TO here, we would find FROM within it and create a
5358 self-referent rtl structure which is completely wrong. */
5362 /* Parallel asm_operands need special attention because all of the
5363 inputs are shared across the arms. Furthermore, unsharing the
5364 rtl results in recognition failures. Failure to handle this case
5365 specially can result in circular rtl.
5367 Solve this by doing a normal pass across the first entry of the
5368 parallel, and only processing the SET_DESTs of the subsequent
5369 entries. Ug. */
5374 {
5377 /* If this substitution failed, this whole thing fails. */
5385 {
5391 {
5394 /* If this substitution failed, this whole thing fails. */
5400 }
5401 }
5402 }
5403 else
5404 {
5408 /* We don't need to process a SET_DEST that is a register, CC0,
5409 or PC, so set up to skip this common case. All other cases
5410 where we want to suppress replacing something inside a
5411 SET_SRC are handled via the IN_DEST operand. */
5418 /* Trying to simplify the operands of a widening MULT is not likely
5419 to create RTL matching a machine insn. */
5431 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5432 constant. */
5437 {
5439 {
5442 {
5444 {
5447 n_occurrences++;
5448 }
5449 else
5450 {
5452 unique_copy);
5454 /* If this substitution failed, this whole thing
5455 fails. */
5459 }
5462 }
5463 }
5465 {
5466 /* If this is a register being set, ignore it. */
5473 ;
5476 {
5477 /* In general, don't install a subreg involving two
5478 modes not tieable. It can worsen register
5479 allocation, and can even make invalid reload
5480 insns, since the reg inside may need to be copied
5481 from in the outside mode, and that may be invalid
5482 if it is an fp reg copied in integer mode.
5484 We allow two exceptions to this: It is valid if
5485 it is inside another SUBREG and the mode of that
5486 SUBREG and the mode of the inside of TO is
5487 tieable and it is valid if X is a SET that copies
5488 FROM to CC0. */
5496 && (!HAVE_cc0
5511 n_occurrences++;
5512 }
5513 else
5514 /* If we are in a SET_DEST, suppress most cases unless we
5515 have gone inside a MEM, in which case we want to
5516 simplify the address. We assume here that things that
5517 are actually part of the destination have their inner
5518 parts in the first expression. This is true for SUBREG,
5519 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5520 things aside from REG and MEM that should appear in a
5521 SET_DEST. */
5523 (((in_dest
5529 unique_copy);
5531 /* If we found that we will have to reject this combination,
5532 indicate that by returning the CLOBBER ourselves, rather than
5533 an expression containing it. This will speed things up as
5534 well as prevent accidents where two CLOBBERs are considered
5535 to be equal, thus producing an incorrect simplification. */
5541 {
5549 }
5552 {
5556 }
5557 else
5559 }
5560 }
5561 }
5563 /* Check if we are loading something from the constant pool via float
5564 extension; in this case we would undo compress_float_constant
5565 optimization and degenerate constant load to an immediate value. */
5569 {
5573 }
5575 /* Try to simplify X. If the simplification changed the code, it is likely
5576 that further simplification will help, so loop, but limit the number
5577 of repetitions that will be performed. */
5580 {
5581 /* If X is sufficiently simple, don't bother trying to do anything
5582 with it. */
5591 /* We no longer know the original mode of operand 0 since we
5592 have changed the form of X) */
5594 }
5597 }
5598 \f
5599 /* If X is a commutative operation whose operands are not in the canonical
5600 order, use substitutions to swap them. */
5602 static void
5604 {
5607 {
5611 }
5612 }
5614 /* Simplify X, a piece of RTL. We just operate on the expression at the
5615 outer level; call `subst' to simplify recursively. Return the new
5616 expression.
5618 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5619 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5620 of a condition. */
5622 static rtx
5625 {
5628 scalar_int_mode int_mode;
5629 rtx temp;
5632 /* If this is a commutative operation, put a constant last and a complex
5633 expression first. We don't need to do this for comparisons here. */
5636 /* Try to fold this expression in case we have constants that weren't
5637 present before. */
5640 {
5648 {
5651 {
5655 }
5658 }
5671 }
5674 {
5679 }
5681 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5682 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5683 things. Check for cases where both arms are testing the same
5684 condition.
5686 Don't do anything if all operands are very simple. */
5699 {
5704 /* If everything is a comparison, what we have is highly unlikely
5705 to be simpler, so don't use it. */
5708 {
5715 /* Simplify the alternative arms; this may collapse the true and
5716 false arms to store-flag values. Be careful to use copy_rtx
5717 here since true_rtx or false_rtx might share RTL with x as a
5718 result of the if_then_else_cond call above. */
5722 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5723 is unlikely to be simpler. */
5726 {
5729 /* Restarting if we generate a store-flag expression will cause
5730 us to loop. Just drop through in this case. */
5732 /* If the result values are STORE_FLAG_VALUE and zero, we can
5733 just make the comparison operation. */
5744 /* Likewise, we can make the negate of a comparison operation
5745 if the result values are - STORE_FLAG_VALUE and zero. */
5753 mode);
5764 mode);
5765 else
5768 mode,
5769 VOIDmode,
5770 cond,
5771 cop1),
5776 }
5777 }
5778 }
5780 /* First see if we can apply the inverse distributive law. */
5783 {
5787 }
5789 /* If CODE is an associative operation not otherwise handled, see if we
5790 can associate some operands. This can win if they are constants or
5791 if they are logically related (i.e. (a & b) & a). */
5797 {
5799 {
5803 rtx inner;
5805 /* Make sure we pass the constant operand if any as the second
5806 one if this is a commutative operation. */
5814 /* For commutative operations, try the other pair if that one
5815 didn't simplify. */
5817 {
5822 }
5826 }
5827 }
5829 /* A little bit of algebraic simplification here. */
5831 {
5833 /* Ensure that our address has any ASHIFTs converted to MULT in case
5834 address-recognizing predicates are called later. */
5843 /* See if this can be moved to simplify_subreg. */
5846 /* Don't call gen_lowpart if the inner mode
5847 is VOIDmode and we cannot simplify it, as SUBREG without
5848 inner mode is invalid. */
5855 {
5856 rtx temp;
5862 /* If op is known to have all lower bits zero, the result is zero. */
5875 }
5877 /* Don't change the mode of the MEM if that would change the meaning
5878 of the address. */
5885 /* Note that we cannot do any narrowing for non-constants since
5886 we might have been counting on using the fact that some bits were
5887 zero. We now do this in the SET. */
5894 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5895 replaced by (lshiftrt X C). This will convert
5896 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5904 /* If X has only a single bit that might be nonzero, say, bit I, convert
5905 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5906 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5907 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5908 or a SUBREG of one since we'd be making the expression more
5909 complex if it was just a register. */
5916 {
5917 rtx temp1 = simplify_shift_const
5923 /* If all we did was surround TEMP with the two shifts, we
5924 haven't improved anything, so don't use it. Otherwise,
5925 we are better off with TEMP1. */
5930 }
5934 /* We can't handle truncation to a partial integer mode here
5935 because we don't know the real bitsize of the partial
5936 integer mode. */
5945 /* We can truncate a constant value and return it. */
5949 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5950 whose value is a comparison can be replaced with a subreg if
5951 STORE_FLAG_VALUE permits. */
5960 /* (const (const X)) can become (const X). Do it this way rather than
5961 returning the inner CONST since CONST can be shared with a
5962 REG_EQUAL note. */
5968 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5969 can add in an offset. find_split_point will split this address up
5970 again if it doesn't match. */
5977 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5978 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5979 bit-field and can be replaced by either a sign_extend or a
5980 sign_extract. The `and' may be a zero_extend and the two
5981 <c>, -<c> constants may be reversed. */
5997 return simplify_shift_const
6004 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6005 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6006 the bitsize of the mode - 1. This allows simplification of
6007 "a = (b & 8) == 0;" */
6014 return simplify_shift_const
6018 const1_rtx),
6022 /* If we are adding two things that have no bits in common, convert
6023 the addition into an IOR. This will often be further simplified,
6024 for example in cases like ((a & 1) + (a & 2)), which can
6025 become a & 3. */
6030 {
6031 /* Try to simplify the expression further. */
6035 /* If we could, great. If not, do not go ahead with the IOR
6036 replacement, since PLUS appears in many special purpose
6037 address arithmetic instructions. */
6045 }
6047 /* Canonicalize x + x into x << 1. */
6056 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6057 (and <foo> (const_int pow2-1)) */
6068 /* If we have (mult (plus A B) C), apply the distributive law and then
6069 the inverse distributive law to see if things simplify. This
6070 occurs mostly in addresses, often when unrolling loops. */
6073 {
6077 }
6079 /* Try simplify a*(b/c) as (a*b)/c. */
6082 {
6088 }
6092 /* If this is a divide by a power of two, treat it as a shift if
6093 its first operand is a shift. */
6113 /* If the first operand is a condition code, we can't do anything
6114 with it. */
6118 {
6126 /* Simplify our comparison, if possible. */
6129 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6130 if only the low-order bit is possibly nonzero in X (such as when
6131 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6132 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6133 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6134 (plus X 1).
6136 Remove any ZERO_EXTRACT we made when thinking this was a
6137 comparison. It may now be simpler to use, e.g., an AND. If a
6138 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6139 the call to make_compound_operation in the SET case.
6141 Don't apply these optimizations if the caller would
6142 prefer a comparison rather than a value.
6143 E.g., for the condition in an IF_THEN_ELSE most targets need
6144 an explicit comparison. */
6147 ;
6165 {
6169 int_mode);
6170 }
6178 {
6182 const1_rtx);
6183 }
6192 {
6195 }
6197 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6198 those above. */
6200 ;
6217 {
6221 int_mode);
6222 }
6231 {
6235 int_mode);
6236 }
6238 /* If X is 0/1, (eq X 0) is X-1. */
6245 {
6248 }
6250 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6251 one bit that might be nonzero, we can convert (ne x 0) to
6252 (ashift x c) where C puts the bit in the sign bit. Remove any
6253 AND with STORE_FLAG_VALUE when we are done, since we are only
6254 going to test the sign bit. */
6262 {
6268 else
6270 }
6272 /* If the code changed, return a whole new comparison.
6273 We also need to avoid using SUBST in cases where
6274 simplify_comparison has widened a comparison with a CONST_INT,
6275 since in that case the wider CONST_INT may fail the sanity
6276 checks in do_SUBST. */
6283 /* Otherwise, keep this operation, but maybe change its operands.
6284 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6287 }
6297 /* If we are processing SET_DEST, we are done. */
6315 /* If this is a shift by a constant amount, simplify it. */
6323 (HOST_WIDE_INT_1U
6332 }
6335 }
6336 \f
6337 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6339 static rtx
6341 {
6348 rtx temp;
6351 rtx reversed;
6354 /* Simplify storing of the truth value. */
6359 /* Also when the truth value has to be reversed. */
6365 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6366 in it is being compared against certain values. Get the true and false
6367 comparisons and see if that says anything about the value of each arm. */
6373 {
6374 HOST_WIDE_INT nzb;
6380 /* If FALSE_CODE is EQ, swap the codes and arms. */
6383 {
6386 }
6388 scalar_int_mode from_mode;
6390 {
6391 /* If we are comparing against zero and the expression being
6392 tested has only a single bit that might be nonzero, that is
6393 its value when it is not equal to zero. Similarly if it is
6394 known to be -1 or 0. */
6398 {
6401 }
6406 {
6409 }
6410 }
6412 /* Now simplify an arm if we know the value of the register in the
6413 branch and it is used in the arm. Be careful due to the potential
6414 of locally-shared RTL. */
6431 }
6433 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6434 reversed, do so to avoid needing two sets of patterns for
6435 subtract-and-branch insns. Similarly if we have a constant in the true
6436 arm, the false arm is the same as the first operand of the comparison, or
6437 the false arm is more complicated than the true arm. */
6450 {
6459 /* It is possible that the conditional has been simplified out. */
6462 }
6464 /* If the two arms are identical, we don't need the comparison. */
6469 /* Convert a == b ? b : a to "a". */
6481 /* Look for cases where we have (abs x) or (neg (abs X)). */
6484 && comparison_p
6491 {
6497 return
6500 mode);
6503 }
6505 /* Look for MIN or MAX. */
6508 && comparison_p
6513 {
6528 }
6530 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6531 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6532 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6533 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6534 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6535 neither 1 or -1, but it isn't worth checking for. */
6538 && comparison_p
6541 {
6557 /* If an identity-zero op is commutative, check whether there
6558 would be a match if we swapped the operands. */
6579 {
6583 }
6596 {
6600 }
6617 {
6621 }
6634 {
6638 }
6641 {
6647 const_true_rtx));
6655 }
6656 }
6658 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6659 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6660 negation of a single bit, we can convert this operation to a shift. We
6661 can actually do this more generally, but it doesn't seem worth it. */
6673 return
6677 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6678 non-zero bit in A is C1. */
6686 {
6692 }
6695 }
6696 \f
6697 /* Simplify X, a SET expression. Return the new expression. */
6699 static rtx
6701 {
6704 machine_mode mode
6708 scalar_int_mode int_mode;
6710 /* (set (pc) (return)) gets written as (return). */
6714 /* Now that we know for sure which bits of SRC we are using, see if we can
6715 simplify the expression for the object knowing that we only need the
6716 low-order bits. */
6719 {
6722 }
6724 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6725 the comparison result and try to simplify it unless we already have used
6726 undobuf.other_insn. */
6734 {
6743 {
6746 {
6749 }
6750 }
6751 else
6759 {
6763 }
6764 else
6765 {
6770 /* Attempt to simplify CC user. */
6772 {
6776 }
6778 /* Convert X into a no-op move. */
6782 }
6784 /* Simplify our comparison, if possible. */
6787 #ifdef SELECT_CC_MODE
6788 /* If this machine has CC modes other than CCmode, check to see if we
6789 need to use a different CC mode here. */
6798 else
6801 /* If the mode changed, we have to change SET_DEST, the mode in the
6802 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6803 a hard register, just build new versions with the proper mode. If it
6804 is a pseudo, we lose unless it is only time we set the pseudo, in
6805 which case we can safely change its mode. */
6807 {
6809 {
6811 rtx new_dest;
6815 else
6816 {
6819 }
6826 }
6827 }
6830 /* If the code changed, we have to build a new comparison in
6831 undobuf.other_insn. */
6833 {
6842 /* If the only change we made was to change an EQ into an NE or
6843 vice versa, OP0 has only one bit that might be nonzero, and OP1
6844 is zero, check if changing the user of the condition code will
6845 produce a valid insn. If it won't, we can keep the original code
6846 in that insn by surrounding our operation with an XOR. */
6853 {
6858 {
6865 }
6866 }
6867 }
6872 /* Don't generate a compare of a CC with 0, just use that CC. */
6874 {
6877 }
6878 /* Otherwise, if we didn't previously have the same COMPARE we
6879 want, create it from scratch. */
6882 {
6885 }
6886 }
6887 else
6888 {
6889 /* Get SET_SRC in a form where we have placed back any
6890 compound expressions. Then do the checks below. */
6893 }
6895 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6896 and X being a REG or (subreg (reg)), we may be able to convert this to
6897 (set (subreg:m2 x) (op)).
6899 We can always do this if M1 is narrower than M2 because that means that
6900 we only care about the low bits of the result.
6902 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6903 perform a narrower operation than requested since the high-order bits will
6904 be undefined. On machine where it is defined, this transformation is safe
6905 as long as M1 and M2 have the same number of words. */
6921 {
6924 dest));
6928 }
6930 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6931 in SRC. */
6935 {
6939 /* Here we make sure that we don't have a sign bit on. */
6942 {
6945 }
6946 }
6948 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6949 would require a paradoxical subreg. Replace the subreg with a
6950 zero_extend to avoid the reload that would otherwise be required. */
6956 {
6961 }
6963 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6964 are comparing an item known to be 0 or -1 against 0, use a logical
6965 operation instead. Check for one of the arms being an IOR of the other
6966 arm with some value. We compute three terms to be IOR'ed together. In
6967 practice, at most two will be nonzero. Then we do the IOR's. */
6975 && (!HAVE_conditional_move
6980 {
7005 int_mode),
7006 false_rtx);
7012 term3));
7015 }
7017 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7018 whole thing fail. */
7023 else
7024 /* Convert this into a field assignment operation, if possible. */
7026 }
7027 \f
7028 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7029 result. */
7031 static rtx
7033 {
7036 scalar_int_mode mode;
7039 {
7041 /* We can call simplify_and_const_int only if we don't lose
7042 any (sign) bits when converting INTVAL (op1) to
7043 "unsigned HOST_WIDE_INT". */
7048 {
7055 }
7057 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7058 apply the distributive law and then the inverse distributive
7059 law to see if things simplify. */
7061 {
7065 }
7067 {
7071 }
7075 /* If we have (ior (and A B) C), apply the distributive law and then
7076 the inverse distributive law to see if things simplify. */
7079 {
7083 }
7086 {
7090 }
7095 }
7098 }
7099 \f
7100 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7101 operations" because they can be replaced with two more basic operations.
7102 ZERO_EXTEND is also considered "compound" because it can be replaced with
7103 an AND operation, which is simpler, though only one operation.
7105 The function expand_compound_operation is called with an rtx expression
7106 and will convert it to the appropriate shifts and AND operations,
7107 simplifying at each stage.
7109 The function make_compound_operation is called to convert an expression
7110 consisting of shifts and ANDs into the equivalent compound expression.
7111 It is the inverse of this function, loosely speaking. */
7113 static rtx
7115 {
7119 rtx tem;
7120 scalar_int_mode inner_mode;
7123 {
7126 /* FALLTHRU */
7128 /* We can't necessarily use a const_int for a multiword mode;
7129 it depends on implicitly extending the value.
7130 Since we don't know the right way to extend it,
7131 we can't tell whether the implicit way is right.
7133 Even for a mode that is no wider than a const_int,
7134 we can't win, because we need to sign extend one of its bits through
7135 the rest of it, and we don't know which bit. */
7139 /* Reject modes that aren't scalar integers because turning vector
7140 or complex modes into shifts causes problems. */
7144 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7145 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7146 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7147 reloaded. If not for that, MEM's would very rarely be safe.
7149 Reject modes bigger than a word, because we might not be able
7150 to reference a two-register group starting with an arbitrary register
7151 (and currently gen_lowpart might crash for a SUBREG). */
7157 /* If the inner object has VOIDmode (the only way this can happen
7158 is if it is an ASM_OPERANDS), we can't do anything since we don't
7159 know how much masking to do. */
7168 /* fall through */
7171 /* If the operand is a CLOBBER, just return it. */
7179 /* Reject modes that aren't scalar integers because turning vector
7180 or complex modes into shifts causes problems. */
7187 /* This should stay within the object being extracted, fail otherwise. */
7198 }
7200 /* We've rejected non-scalar operations by now. */
7203 /* Convert sign extension to zero extension, if we know that the high
7204 bit is not set, as this is easier to optimize. It will be converted
7205 back to cheaper alternative in make_extraction. */
7211 {
7215 /* Make sure this is a profitable operation. */
7222 else
7224 }
7226 /* We can optimize some special cases of ZERO_EXTEND. */
7228 {
7229 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7230 know that the last value didn't have any inappropriate bits
7231 set. */
7239 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7248 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7249 is a comparison and STORE_FLAG_VALUE permits. This is like
7250 the first case, but it works even when MODE is larger
7251 than HOST_WIDE_INT. */
7259 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7268 }
7270 /* If we reach here, we want to return a pair of shifts. The inner
7271 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7272 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7273 logical depending on the value of UNSIGNEDP.
7275 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7276 converted into an AND of a shift.
7278 We must check for the case where the left shift would have a negative
7279 count. This can happen in a case like (x >> 31) & 255 on machines
7280 that can't shift by a constant. On those machines, we would first
7281 combine the shift with the AND to produce a variable-position
7282 extraction. Then the constant of 31 would be substituted in
7283 to produce such a position. */
7287 {
7295 }
7300 pos),
7302 else
7303 /* Any other cases we can't handle. */
7306 /* If we couldn't do this for some reason, return the original
7307 expression. */
7312 }
7313 \f
7314 /* X is a SET which contains an assignment of one object into
7315 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7316 or certain SUBREGS). If possible, convert it into a series of
7317 logical operations.
7319 We half-heartedly support variable positions, but do not at all
7320 support variable lengths. */
7322 static const_rtx
7324 {
7325 rtx inner;
7329 scalar_int_mode compute_mode;
7331 /* Loop until we find something we can't simplify. */
7333 {
7336 {
7340 }
7343 {
7348 /* A constant position should stay within the width of INNER. */
7354 {
7362 /* If position is ADJUST - X, new position is X. */
7364 else
7365 {
7370 pos);
7371 }
7372 }
7373 }
7375 /* If the destination is a subreg that overwrites the whole of the inner
7376 register, we can move the subreg to the source. */
7378 /* We need SUBREGs to compute nonzero_bits properly. */
7379 && nonzero_sign_valid
7381 {
7383 gen_lowpart
7387 }
7388 else
7394 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7396 {
7397 /* Don't do anything for vector or complex integral types. */
7401 /* Try to find an integral mode to pun with. */
7407 }
7409 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7413 /* Don't try to compute in too wide unsupported modes. */
7417 /* Now compute the equivalent expression. Make a copy of INNER
7418 for the SET_DEST in case it is a MEM into which we will substitute;
7419 we don't want shared RTL in that case. */
7421 compute_mode);
7425 compute_mode,
7427 compute_mode),
7428 inner);
7433 mask),
7434 pos);
7439 }
7442 }
7443 \f
7444 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7445 it is an RTX that represents the (variable) starting position; otherwise,
7446 POS is the (constant) starting bit position. Both are counted from the LSB.
7448 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7450 IN_DEST is nonzero if this is a reference in the destination of a SET.
7451 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7452 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7453 be used.
7455 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7456 ZERO_EXTRACT should be built even for bits starting at bit 0.
7458 MODE is the desired mode of the result (if IN_DEST == 0).
7460 The result is an RTX for the extraction or NULL_RTX if the target
7461 can't handle it. */
7463 static rtx
7467 {
7468 /* This mode describes the size of the storage area
7469 to fetch the overall value from. Within that, we
7470 ignore the POS lowest bits, etc. */
7472 machine_mode inner_mode;
7473 scalar_int_mode wanted_inner_mode;
7479 HOST_WIDE_INT orig_pos;
7487 /* If trying or potentionally trying to extract
7488 bits outside of is_mode, don't look through
7489 non-paradoxical SUBREGs. See PR82192. */
7492 {
7493 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7494 consider just the QI as the memory to extract from.
7495 The subreg adds or removes high bits; its mode is
7496 irrelevant to the meaning of this extraction,
7497 since POS and LEN count from the lsb. */
7501 }
7506 {
7507 /* We're extracting the least significant bits of an rtx
7508 (ashift X (const_int C)), where LEN > C. Extract the
7509 least significant (LEN - C) bits of X, giving an rtx
7510 whose mode is MODE, then shift it left C times. */
7516 }
7518 /* If trying or potentionally trying to extract
7519 bits outside of is_mode, don't look through
7520 TRUNCATE. See PR82192. */
7527 /* See if this can be done without an extraction. We never can if the
7528 width of the field is not the same as that of some integer mode. For
7529 registers, we can only avoid the extraction if the position is at the
7530 low-order bit and this is either not in the destination or we have the
7531 appropriate STRICT_LOW_PART operation available.
7533 For MEM, we can avoid an extract if the field starts on an appropriate
7534 boundary and we can change the mode of the memory reference. */
7536 scalar_int_mode tmode;
7545 && (! in_dest
7549 && (pos
7552 /* We can't do this if we are widening INNER_MODE (it
7553 may not be aligned, for one thing). */
7559 {
7560 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7561 field. If the original and current mode are the same, we need not
7562 adjust the offset. Otherwise, we do if bytes big endian.
7564 If INNER is not a MEM, get a piece consisting of just the field
7565 of interest (in this case POS % BITS_PER_WORD must be 0). */
7568 {
7569 HOST_WIDE_INT offset;
7571 /* POS counts from lsb, but make OFFSET count in memory order. */
7574 else
7578 }
7580 {
7582 {
7583 /* We can't call gen_lowpart in a DEST since we
7584 always want a SUBREG (see below) and it would sometimes
7585 return a new hard register. */
7587 {
7588 unsigned int offset
7591 /* Avoid creating invalid subregs, for example when
7592 simplifying (x>>32)&255. */
7597 }
7598 else
7600 }
7601 else
7603 }
7604 else
7606 len >= HOST_BITS_PER_WIDE_INT
7607 ? HOST_WIDE_INT_M1U
7610 /* If this extraction is going into the destination of a SET,
7611 make a STRICT_LOW_PART unless we made a MEM. */
7626 /* If we know that no extraneous bits are set, and that the high
7627 bit is not set, convert the extraction to the cheaper of
7628 sign and zero extension, that are equivalent in these cases. */
7634 {
7638 /* Prefer ZERO_EXTENSION, since it gives more information to
7639 backends. */
7644 }
7646 /* Otherwise, sign- or zero-extend unless we already are in the
7647 proper mode. */
7651 }
7653 /* Unless this is a COMPARE or we have a funny memory reference,
7654 don't do anything with zero-extending field extracts starting at
7655 the low-order bit since they are simple AND operations. */
7660 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7661 if the position is not a constant and the length is not 1. In all
7662 other cases, we would only be going outside our object in cases when
7663 an original shift would have been undefined. */
7672 /* If INNER is not from memory, we want it to have the mode of a register
7673 extraction pattern's structure operand, or word_mode if there is no
7674 such pattern. The same applies to extraction_mode and pos_mode
7675 and their respective operands.
7677 For memory, assume that the desired extraction_mode and pos_mode
7678 are the same as for a register operation, since at present we don't
7679 have named patterns for aligned memory structures. */
7683 {
7687 }
7689 /* Never narrow an object, since that might not be safe. */
7697 else
7698 {
7699 /* Be careful not to go beyond the extracted object and maintain the
7700 natural alignment of the memory. */
7705 }
7710 {
7711 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7712 BITS_BIG_ENDIAN style. If position is constant, compute new
7713 position. Otherwise, build subtraction.
7714 Note that POS is relative to the mode of the original argument.
7715 If it's a MEM we need to recompute POS relative to that.
7716 However, if we're extracting from (or inserting into) a register,
7717 we want to recompute POS relative to wanted_inner_mode. */
7724 else
7725 pos_rtx
7728 pos_rtx);
7729 /* POS may be less than 0 now, but we check for that below.
7730 Note that it can only be less than 0 if !MEM_P (inner). */
7731 }
7733 /* If INNER has a wider mode, and this is a constant extraction, try to
7734 make it smaller and adjust the byte to point to the byte containing
7735 the value. */
7738 && ! pos_rtx
7743 {
7746 /* The computations below will be correct if the machine is big
7747 endian in both bits and bytes or little endian in bits and bytes.
7748 If it is mixed, we must adjust. */
7750 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7751 adjust OFFSET to compensate. */
7756 /* We can now move to the desired byte. */
7767 }
7769 /* If INNER is not memory, get it into the proper mode. If we are changing
7770 its mode, POS must be a constant and smaller than the size of the new
7771 mode. */
7773 {
7774 /* On the LHS, don't create paradoxical subregs implicitely truncating
7775 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7778 wanted_inner_mode))
7790 pos_rtx
7792 ? HOST_WIDE_INT_M1U
7796 }
7798 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7799 have to zero extend. Otherwise, we can just use a SUBREG.
7801 We dealt with constant rtxes earlier, so pos_rtx cannot
7802 have VOIDmode at this point. */
7806 {
7810 /* If we know that no extraneous bits are set, and that the high
7811 bit is not set, convert extraction to cheaper one - either
7812 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7813 cases. */
7821 {
7825 /* Prefer ZERO_EXTENSION, since it gives more information to
7826 backends. */
7830 }
7832 }
7834 /* Make POS_RTX unless we already have it and it is correct. If we don't
7835 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7836 be a CONST_INT. */
7843 /* Make the required operation. See if we can use existing rtx. */
7850 }
7851 \f
7852 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7853 can be commuted with any other operations in X. Return X without
7854 that shift if so. */
7856 static rtx
7858 {
7860 rtx tem;
7863 {
7865 /* This is the shift itself. If it is wide enough, we will return
7866 either the value being shifted if the shift count is equal to
7867 COUNT or a shift for the difference. */
7881 /* If we can safely shift this constant and we find the inner shift,
7882 make a new operation. */
7887 {
7891 }
7896 }
7899 }
7900 \f
7901 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7902 level of the expression and MODE is its mode. IN_CODE is as for
7903 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7904 that should be used when recursing on operands of *X_PTR.
7906 There are two possible actions:
7908 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7909 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7911 - Return a new rtx, which the caller returns directly. */
7913 static rtx
7917 {
7925 rtx tem;
7926 scalar_int_mode inner_mode;
7930 {
7933 }
7935 /* Process depending on the code of this operation. If NEW is set
7936 nonzero, it will be returned. */
7939 {
7941 /* Convert shifts by constants into multiplications if inside
7942 an address. */
7946 {
7952 {
7955 }
7958 }
7967 {
7971 }
7974 {
7978 mode));
7980 }
7981 else
7982 {
7985 }
7995 {
7999 }
8002 {
8006 mode));
8008 }
8009 else
8010 {
8014 }
8017 /* If the second operand is not a constant, we can't do anything
8018 with it. */
8022 /* If the constant is a power of two minus one and the first operand
8023 is a logical right shift, make an extraction. */
8026 {
8030 }
8032 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8039 {
8046 /* If we narrowed the mode when dropping the subreg, then we lose. */
8050 /* If that didn't give anything, see if the AND simplifies on
8051 its own. */
8053 {
8057 }
8058 }
8059 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8065 {
8066 /* Apply the distributive law, and then try to make extractions. */
8073 }
8075 /* If we are have (and (rotate X C) M) and C is larger than the number
8076 of bits in M, this is an extraction. */
8082 {
8088 }
8090 /* On machines without logical shifts, if the operand of the AND is
8091 a logical shift and our mask turns off all the propagated sign
8092 bits, we can replace the logical shift with an arithmetic shift. */
8100 {
8110 next_code),
8112 }
8114 /* If the constant is one less than a power of two, this might be
8115 representable by an extraction even if no shift is present.
8116 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8117 we are in a COMPARE. */
8121 next_code),
8124 /* If we are in a comparison and this is an AND with a power of two,
8125 convert this into the appropriate bit extract. */
8131 next_code),
8134 /* If the one operand is a paradoxical subreg of a register or memory and
8135 the constant (limited to the smaller mode) has only zero bits where
8136 the sub expression has known zero bits, this can be expressed as
8137 a zero_extend. */
8139 {
8140 rtx sub;
8146 {
8150 /* original AND constant with all the known zero bits set */
8153 {
8158 }
8159 }
8160 }
8165 /* If the sign bit is known to be zero, replace this with an
8166 arithmetic shift. */
8171 {
8174 next_code),
8177 }
8179 /* fall through */
8185 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8186 this is a SIGN_EXTRACT. */
8193 {
8200 }
8202 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8203 If so, try to merge the shifts into a SIGN_EXTEND. We could
8204 also do this for some cases of SIGN_EXTRACT, but it doesn't
8205 seem worth the effort; the case checked for occurs on Alpha. */
8216 next_code),
8223 /* Call ourselves recursively on the inner expression. If we are
8224 narrowing the object and it has a different RTL code from
8225 what it originally did, do this SUBREG as a force_to_mode. */
8226 {
8230 /* If the SUBREG is masking of a logical right shift,
8231 make an extraction. */
8238 {
8247 }
8249 /* If in_code is COMPARE, it isn't always safe to pass it through
8250 to the recursive make_compound_operation call. */
8254 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8255 is (const_int 0), rather than
8256 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8257 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8258 for non-equality comparisons against 0 is not equivalent
8259 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8269 simplified
8277 {
8278 rtx newer
8281 /* If we have something other than a SUBREG, we might have
8282 done an expansion, so rerun ourselves. */
8286 /* force_to_mode can expand compounds. If it just re-expanded
8287 the compound, use gen_lowpart to convert to the desired
8288 mode. */
8290 /* Likewise if it re-expanded the compound only partially.
8291 This happens for SUBREG of ZERO_EXTRACT if they extract
8292 the same number of bits. */
8301 }
8305 }
8310 }
8316 }
8318 /* Look at the expression rooted at X. Look for expressions
8319 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8320 Form these expressions.
8322 Return the new rtx, usually just X.
8324 Also, for machines like the VAX that don't have logical shift insns,
8325 try to convert logical to arithmetic shift operations in cases where
8326 they are equivalent. This undoes the canonicalizations to logical
8327 shifts done elsewhere.
8329 We try, as much as possible, to re-use rtl expressions to save memory.
8331 IN_CODE says what kind of expression we are processing. Normally, it is
8332 SET. In a memory address it is MEM. When processing the arguments of
8333 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8334 precisely it is an equality comparison against zero. */
8336 rtx
8338 {
8345 /* Select the code to be used in recursive calls. Once we are inside an
8346 address, we stay there. If we have a comparison, set to COMPARE,
8347 but once inside, go back to our default of SET. */
8354 scalar_int_mode mode;
8356 {
8362 }
8364 /* Now recursively process each operand of this operation. We need to
8365 handle ZERO_EXTEND specially so that we don't lose track of the
8366 inner mode. */
8368 {
8376 }
8381 {
8384 }
8387 {
8390 }
8394 }
8395 \f
8396 /* Given M see if it is a value that would select a field of bits
8397 within an item, but not the entire word. Return -1 if not.
8398 Otherwise, return the starting position of the field, where 0 is the
8399 low-order bit.
8401 *PLEN is set to the length of the field. */
8403 static int
8405 {
8406 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8411 /* Now shift off the low-order zero bits and see if we have a
8412 power of two minus 1. */
8420 }
8421 \f
8422 /* If X refers to a register that equals REG in value, replace these
8423 references with REG. */
8424 static rtx
8426 {
8434 {
8467 /* FALLTHRU */
8471 {
8475 else
8477 }
8479 /* fall through */
8486 {
8489 {
8491 {
8494 }
8496 }
8497 }
8499 {
8502 {
8505 {
8507 {
8510 }
8512 }
8513 }
8514 }
8517 }
8520 }
8522 /* Return X converted to MODE. If the value is already truncated to
8523 MODE we can just return a subreg even though in the general case we
8524 would need an explicit truncation. */
8526 static rtx
8528 {
8533 {
8534 /* Bit-cast X into an integer mode. */
8539 }
8542 }
8544 /* See if X can be simplified knowing that we will only refer to it in
8545 MODE and will only refer to those bits that are nonzero in MASK.
8546 If other bits are being computed or if masking operations are done
8547 that select a superset of the bits in MASK, they can sometimes be
8548 ignored.
8550 Return a possibly simplified expression, but always convert X to
8551 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8553 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8554 are all off in X. This is used when X will be complemented, by either
8555 NOT, NEG, or XOR. */
8557 static rtx
8560 {
8563 machine_mode op_mode;
8566 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8567 code below will do the wrong thing since the mode of such an
8568 expression is VOIDmode.
8570 Also do nothing if X is a CLOBBER; this can happen if X was
8571 the return value from a call to gen_lowpart. */
8575 /* We want to perform the operation in its present mode unless we know
8576 that the operation is valid in MODE, in which case we do the operation
8577 in MODE. */
8582 /* It is not valid to do a right-shift in a narrower mode
8583 than the one it came in with. */
8588 /* Truncate MASK to fit OP_MODE. */
8592 /* Determine what bits of X are guaranteed to be (non)zero. */
8595 /* If none of the bits in X are needed, return a zero. */
8599 /* If X is a CONST_INT, return a new one. Do this here since the
8600 test below will fail. */
8602 {
8605 else
8606 {
8609 }
8610 }
8612 /* If X is narrower than MODE and we want all the bits in X's mode, just
8613 get X in the proper mode. */
8618 /* We can ignore the effect of a SUBREG if it narrows the mode or
8619 if the constant masks to zero all the bits the mode doesn't have. */
8631 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8632 integer too. */
8638 }
8640 /* Subroutine of force_to_mode that handles cases in which both X and
8641 the result are scalar integers. MODE is the mode of the result,
8642 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8643 is preferred for simplified versions of X. The other arguments
8644 are as for force_to_mode. */
8646 static rtx
8650 {
8656 /* When we have an arithmetic operation, or a shift whose count we
8657 do not know, we need to assume that all bits up to the highest-order
8658 bit in MASK will be needed. This is how we form such a mask. */
8661 else
8666 {
8668 /* If X is a (clobber (const_int)), return it since we know we are
8669 generating something that won't match. */
8682 /* Similarly for a truncate. */
8686 /* If this is an AND with a constant, convert it into an AND
8687 whose constant is the AND of that constant with MASK. If it
8688 remains an AND of MASK, delete it since it is redundant. */
8691 {
8696 /* If X is still an AND, see if it is an AND with a mask that
8697 is just some low-order bits. If so, and it is MASK, we don't
8698 need it. */
8704 /* If it remains an AND, try making another AND with the bits
8705 in the mode mask that aren't in MASK turned on. If the
8706 constant in the AND is wide enough, this might make a
8707 cheaper constant. */
8712 {
8713 unsigned HOST_WIDE_INT cval
8715 rtx y;
8722 }
8725 }
8730 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8731 low-order bits (as in an alignment operation) and FOO is already
8732 aligned to that boundary, mask C1 to that boundary as well.
8733 This may eliminate that PLUS and, later, the AND. */
8735 {
8739 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8740 number, sign extend it. */
8753 }
8755 /* fall through */
8758 /* Substituting into the operands of a widening MULT is not likely to
8759 create RTL matching a machine insn. */
8769 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8770 most significant bit in MASK since carries from those bits will
8771 affect the bits we are interested in. */
8776 /* If X is (minus C Y) where C's least set bit is larger than any bit
8777 in the mask, then we may replace with (neg Y). */
8780 {
8783 }
8785 /* Similarly, if C contains every bit in the fuller_mask, then we may
8786 replace with (not Y). */
8789 {
8792 }
8799 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8800 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8801 operation which may be a bitfield extraction. Ensure that the
8802 constant we form is not wider than the mode of X. */
8814 {
8817 xmode);
8823 }
8825 binop:
8826 /* For most binary operations, just propagate into the operation and
8827 change the mode if we have an operation of that mode. */
8832 /* If we ended up truncating both operands, truncate the result of the
8833 operation instead. */
8836 {
8839 }
8845 {
8848 }
8852 /* For left shifts, do the same, but just for the first operand.
8853 However, we cannot do anything with shifts where we cannot
8854 guarantee that the counts are smaller than the size of the mode
8855 because such a count will have a different meaning in a
8856 wider mode. */
8866 /* If the shift count is a constant and we can do arithmetic in
8867 the mode of the shift, refine which bits we need. Otherwise, use the
8868 conservative form of the mask. */
8874 else
8882 {
8885 }
8889 /* Here we can only do something if the shift count is a constant,
8890 this shift constant is valid for the host, and we can do arithmetic
8891 in OP_MODE. */
8897 {
8901 /* Select the mask of the bits we need for the shift operand. */
8904 /* We can only change the mode of the shift if we can do arithmetic
8905 in the mode of the shift and INNER_MASK is no wider than the
8906 width of X's mode. */
8913 {
8916 }
8917 }
8919 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8920 shift and AND produces only copies of the sign bit (C2 is one less
8921 than a power of two), we can do this with just a shift. */
8925 /* The shift puts one of the sign bit copies in the least significant
8926 bit. */
8931 /* Number of bits left after the shift must be more than the mask
8932 needs. */
8935 /* Must be more sign bit copies than the mask needs. */
8945 /* If we are just looking for the sign bit, we don't need this shift at
8946 all, even if it has a variable count. */
8950 /* If this is a shift by a constant, get a mask that contains those bits
8951 that are not copies of the sign bit. We then have two cases: If
8952 MASK only includes those bits, this can be a logical shift, which may
8953 allow simplifications. If MASK is a single-bit field not within
8954 those bits, we are requesting a copy of the sign bit and hence can
8955 shift the sign bit to the appropriate location. */
8959 {
8963 /* If the considered data is wider than HOST_WIDE_INT, we can't
8964 represent a mask for all its bits in a single scalar.
8965 But we only care about the lower bits, so calculate these. */
8968 {
8971 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8972 is the number of bits a full-width mask would have set.
8973 We need only shift if these are fewer than nonzero can
8974 hold. If not, we must keep all bits set in nonzero. */
8979 + HOST_BITS_PER_WIDE_INT
8981 }
8982 else
8983 {
8986 }
8989 {
8994 }
8997 {
8998 x = simplify_shift_const
9004 }
9005 }
9007 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9008 even if the shift count isn't a constant. */
9012 shiftrt:
9014 /* If this is a zero- or sign-extension operation that just affects bits
9015 we don't care about, remove it. Be sure the call above returned
9016 something that is still a shift. */
9026 next_select);
9032 /* If the shift count is constant and we can do computations
9033 in the mode of X, compute where the bits we care about are.
9034 Otherwise, we can't do anything. Don't change the mode of
9035 the shift or propagate MODE into the shift, though. */
9038 {
9047 }
9051 /* If we just want the low-order bit, the NEG isn't needed since it
9052 won't change the low-order bit. */
9056 /* We need any bits less significant than the most significant bit in
9057 MASK since carries from those bits will affect the bits we are
9058 interested in. */
9063 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9064 same as the XOR case above. Ensure that the constant we form is not
9065 wider than the mode of X. */
9073 {
9080 }
9082 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9083 use the full mask inside the NOT. */
9086 unop:
9089 next_select));
9091 {
9094 }
9098 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9099 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9100 which is equal to STORE_FLAG_VALUE. */
9112 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9113 written in a narrower mode. We play it safe and do not do so. */
9129 }
9131 /* Ensure we return a value of the proper mode. */
9133 }
9134 \f
9135 /* Return nonzero if X is an expression that has one of two values depending on
9136 whether some other value is zero or nonzero. In that case, we return the
9137 value that is being tested, *PTRUE is set to the value if the rtx being
9138 returned has a nonzero value, and *PFALSE is set to the other alternative.
9140 If we return zero, we set *PTRUE and *PFALSE to X. */
9142 static rtx
9144 {
9149 scalar_int_mode int_mode;
9151 /* If we are comparing a value against zero, we are done. */
9154 {
9158 }
9160 /* If this is a unary operation whose operand has one of two values, apply
9161 our opcode to compute those values. */
9164 {
9169 }
9171 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9172 make can't possibly match and would suppress other optimizations. */
9174 ;
9176 /* If this is a binary operation, see if either side has only one of two
9177 values. If either one does or if both do and they are conditional on
9178 the same value, compute the new true and false values. */
9180 {
9188 {
9189 /* Try to enable a simplification by undoing work done by
9190 if_then_else_cond if it converted a REG into something more
9191 complex. */
9193 {
9196 }
9197 else
9198 {
9201 }
9202 }
9206 {
9207 /* If if_then_else_cond returned zero, then true/false are the
9208 same rtl. We must copy one of them to prevent invalid rtl
9209 sharing. */
9216 {
9221 }
9222 else
9223 {
9226 }
9229 }
9231 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9232 operands is zero when the other is nonzero, and vice-versa,
9233 and STORE_FLAG_VALUE is 1 or -1. */
9239 {
9256 {
9263 const_true_rtx);
9265 }
9266 }
9268 /* Similarly for MULT, AND and UMIN, except that for these the result
9269 is always zero. */
9273 {
9287 {
9290 }
9291 }
9292 }
9295 {
9296 /* If we have IF_THEN_ELSE already, extract the condition and
9297 canonicalize it if it is NE or EQ. */
9303 {
9306 }
9307 else
9309 }
9311 /* If X is a SUBREG, we can narrow both the true and false values
9312 if the inner expression, if there is a condition. */
9316 {
9322 {
9326 }
9327 }
9329 /* If X is a constant, this isn't special and will cause confusions
9330 if we treat it as such. Likewise if it is equivalent to a constant. */
9333 ;
9335 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9336 will be least confusing to the rest of the compiler. */
9338 {
9341 }
9343 /* If X is known to be either 0 or -1, those are the true and
9344 false values when testing X. */
9349 {
9352 }
9354 /* Likewise for 0 or a single bit. */
9357 {
9360 }
9362 /* Otherwise fail; show no condition with true and false values the same. */
9365 }
9366 \f
9367 /* Return the value of expression X given the fact that condition COND
9368 is known to be true when applied to REG as its first operand and VAL
9369 as its second. X is known to not be shared and so can be modified in
9370 place.
9372 We only handle the simplest cases, and specifically those cases that
9373 arise with IF_THEN_ELSE expressions. */
9375 static rtx
9377 {
9385 /* If either operand of the condition is a floating point value,
9386 then we have to avoid collapsing an EQ comparison. */
9396 /* If X is (abs REG) and we know something about REG's relationship
9397 with zero, we may be able to simplify this. */
9401 {
9410 }
9412 /* The only other cases we handle are MIN, MAX, and comparisons if the
9413 operands are the same as REG and VAL. */
9416 {
9418 {
9421 }
9424 {
9426 {
9434 else
9436 }
9439 {
9442 /* Do not reverse the condition when it is NE or EQ.
9443 This is because we cannot conclude anything about
9444 the value of 'SMAX (x, y)' when x is not equal to y,
9445 but we can when x equals y. */
9451 {
9462 }
9463 }
9464 }
9465 }
9467 {
9472 {
9473 /* We must simplify subreg here, before we lose track of the
9474 original inner_mode. */
9479 else
9481 }
9484 }
9485 /* We don't have to handle SIGN_EXTEND here, because even in the
9486 case of replacing something with a modeless CONST_INT, a
9487 CONST_INT is already (supposed to be) a valid sign extension for
9488 its narrower mode, which implies it's already properly
9489 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9490 story is different. */
9492 {
9497 {
9498 /* We must simplify the zero_extend here, before we lose
9499 track of the original inner_mode. */
9504 else
9506 }
9509 }
9513 {
9520 }
9523 }
9524 \f
9525 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9526 assignment as a field assignment. */
9528 static int
9530 {
9532 {
9540 }
9548 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9549 Note that all SUBREGs of MEM are paradoxical; otherwise they
9550 would have been rewritten. */
9563 /* We used to see if get_last_value of X and Y were the same but that's
9564 not correct. In one direction, we'll cause the assignment to have
9565 the wrong destination and in the case, we'll import a register into this
9566 insn that might have already have been dead. So fail if none of the
9567 above cases are true. */
9569 }
9570 \f
9571 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9572 Return that assignment if so.
9574 We only handle the most common cases. */
9576 static rtx
9578 {
9581 rtx assign;
9583 HOST_WIDE_INT c1;
9584 HOST_WIDE_INT pos;
9586 rtx other;
9588 /* All the rules in this function are specific to scalar integers. */
9589 scalar_int_mode mode;
9593 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9594 a clear of a one-bit field. We will have changed it to
9595 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9596 for a SUBREG. */
9602 {
9608 }
9617 {
9624 }
9626 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9627 one-bit field. */
9631 {
9637 }
9639 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9640 SRC is an AND with all bits of that field set, then we can discard
9641 the AND. */
9646 {
9653 else
9656 /* Complete overlap. We can remove the source AND. */
9660 /* Partial overlap. We can reduce the source AND. */
9662 {
9666 }
9667 }
9669 /* The other case we handle is assignments into a constant-position
9670 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9671 a mask that has all one bits except for a group of zero bits and
9672 OTHER is known to have zeros where C1 has ones, this is such an
9673 assignment. Compute the position and length from C1. Shift OTHER
9674 to the appropriate position, force it to the required mode, and
9675 make the extraction. Check for the AND in both operands. */
9677 /* One or more SUBREGs might obscure the constant-position field
9678 assignment. The first one we are likely to encounter is an outer
9679 narrowing SUBREG, which we can just strip for the purposes of
9680 identifying the constant-field assignment. */
9697 /* The second SUBREG that might get in the way is a paradoxical
9698 SUBREG around the first operand of the AND. We want to
9699 pretend the operand is as wide as the destination here. We
9700 do this by adjusting the MEM to wider mode for the sole
9701 purpose of the call to rtx_equal_for_field_assignment_p. Also
9702 note this trick only works for MEMs. */
9714 /* The second SUBREG that might get in the way is a paradoxical
9715 SUBREG around the first operand of the AND. We want to
9716 pretend the operand is as wide as the destination here. We
9717 do this by adjusting the MEM to wider mode for the sole
9718 purpose of the call to rtx_equal_for_field_assignment_p. Also
9719 note this trick only works for MEMs. */
9727 else
9741 /* The mode to use for the source is the mode of the assignment, or of
9742 what is inside a possible STRICT_LOW_PART. */
9746 /* Shift OTHER right POS places and make it the source, restricting it
9747 to the proper length and mode. */
9751 dest);
9753 len >= HOST_BITS_PER_WIDE_INT
9754 ? HOST_WIDE_INT_M1U
9758 /* If SRC is masked by an AND that does not make a difference in
9759 the value being stored, strip it. */
9770 }
9771 \f
9772 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9773 if so. */
9775 static rtx
9777 {
9781 rtx tem;
9783 /* Distributivity is not true for floating point as it can change the
9784 value. So we don't do it unless -funsafe-math-optimizations. */
9789 /* The outer operation can only be one of the following: */
9797 /* If either operand is a primitive we can't do anything, so get out
9798 fast. */
9808 /* See if the inner and outer operations distribute. */
9810 {
9815 /* These all distribute except over PLUS. */
9826 /* This is also a multiply, so it distributes over everything. */
9829 /* This used to handle SUBREG, but this turned out to be counter-
9830 productive, since (subreg (op ...)) usually is not handled by
9831 insn patterns, and this "optimization" therefore transformed
9832 recognizable patterns into unrecognizable ones. Therefore the
9833 SUBREG case was removed from here.
9835 It is possible that distributing SUBREG over arithmetic operations
9836 leads to an intermediate result than can then be optimized further,
9837 e.g. by moving the outer SUBREG to the other side of a SET as done
9838 in simplify_set. This seems to have been the original intent of
9839 handling SUBREGs here.
9841 However, with current GCC this does not appear to actually happen,
9842 at least on major platforms. If some case is found where removing
9843 the SUBREG case here prevents follow-on optimizations, distributing
9844 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9848 }
9850 /* Set LHS and RHS to the inner operands (A and B in the example
9851 above) and set OTHER to the common operand (C in the example).
9852 There is only one way to do this unless the inner operation is
9853 commutative. */
9865 else
9868 /* Form the new inner operation, seeing if it simplifies first. */
9871 /* There is one exception to the general way of distributing:
9872 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9874 {
9877 }
9879 /* We may be able to continuing distributing the result, so call
9880 ourselves recursively on the inner operation before forming the
9881 outer operation, which we return. */
9884 }
9886 /* See if X is of the form (* (+ A B) C), and if so convert to
9887 (+ (* A C) (* B C)) and try to simplify.
9889 Most of the time, this results in no change. However, if some of
9890 the operands are the same or inverses of each other, simplifications
9891 will result.
9893 For example, (and (ior A B) (not B)) can occur as the result of
9894 expanding a bit field assignment. When we apply the distributive
9895 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9896 which then simplifies to (and (A (not B))).
9898 Note that no checks happen on the validity of applying the inverse
9899 distributive law. This is pointless since we can do it in the
9900 few places where this routine is called.
9902 N is the index of the term that is decomposed (the arithmetic operation,
9903 i.e. (+ A B) in the first example above). !N is the index of the term that
9904 is distributed, i.e. of C in the first example above. */
9905 static rtx
9907 {
9908 machine_mode mode;
9912 /* Distributivity is not true for floating point as it can change the
9913 value. So we don't do it unless -funsafe-math-optimizations. */
9930 /* Special case (and (xor B C) (not A)), which is equivalent to
9931 (xor (ior A B) (ior A C)) */
9933 {
9936 }
9939 {
9940 /* Distribute the second term. */
9943 }
9944 else
9945 {
9946 /* Distribute the first term. */
9949 }
9959 }
9960 \f
9961 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9962 in MODE. Return an equivalent form, if different from (and VAROP
9963 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9965 static rtx
9968 {
9971 rtx orig_varop;
9979 /* Simplify VAROP knowing that we will be only looking at some of the
9980 bits in it.
9982 Note by passing in CONSTOP, we guarantee that the bits not set in
9983 CONSTOP are not significant and will never be examined. We must
9984 ensure that is the case by explicitly masking out those bits
9985 before returning. */
9988 /* If VAROP is a CLOBBER, we will fail so return it. */
9992 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9993 to VAROP and return the new constant. */
9997 /* See what bits may be nonzero in VAROP. Unlike the general case of
9998 a call to nonzero_bits, here we don't care about bits outside
9999 MODE. */
10003 /* Turn off all bits in the constant that are known to already be zero.
10004 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10005 which is tested below. */
10009 /* If we don't have any bits left, return zero. */
10013 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10014 a power of two, we can replace this with an ASHIFT. */
10019 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10020 or XOR, then try to apply the distributive law. This may eliminate
10021 operations if either branch can be simplified because of the AND.
10022 It may also make some cases more complex, but those cases probably
10023 won't match a pattern either with or without this. */
10026 {
10028 return
10029 gen_lowpart
10031 apply_distributive_law
10035 constop),
10038 constop))));
10039 }
10041 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10042 the AND and see if one of the operands simplifies to zero. If so, we
10043 may eliminate it. */
10047 {
10056 }
10058 /* Make a SUBREG if necessary. If we can't make it, fail. */
10063 /* If we are only masking insignificant bits, return VAROP. */
10070 /* Otherwise, return an AND. */
10072 }
10075 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10076 in MODE.
10078 Return an equivalent form, if different from X. Otherwise, return X. If
10079 X is zero, we are to always construct the equivalent form. */
10081 static rtx
10084 {
10095 }
10096 \f
10097 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10098 We don't care about bits outside of those defined in MODE.
10100 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10101 a shift, AND, or zero_extract, we can do better. */
10103 static rtx
10105 scalar_int_mode mode,
10107 {
10108 rtx tem;
10111 /* If X is a register whose nonzero bits value is current, use it.
10112 Otherwise, if X is a register whose value we can find, use that
10113 value. Otherwise, use the previously-computed global nonzero bits
10114 for this register. */
10128 && !REGNO_REG_SET_P
10131 {
10132 /* Note that, even if the precision of last_set_mode is lower than that
10133 of mode, record_value_for_reg invoked nonzero_bits on the register
10134 with nonzero_bits_mode (because last_set_mode is necessarily integral
10135 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10136 are all valid, hence in mode too since nonzero_bits_mode is defined
10137 to the largest HWI_COMPUTABLE_MODE_P mode. */
10140 }
10144 {
10149 }
10152 {
10156 /* We don't know anything about the upper bits. */
10160 }
10163 }
10165 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10166 end of X that are known to be equal to the sign bit. X will be used
10167 in mode MODE; the returned value will always be between 1 and the
10168 number of bits in MODE. */
10170 static rtx
10172 scalar_int_mode mode,
10174 {
10175 rtx tem;
10188 && !REGNO_REG_SET_P
10191 {
10194 }
10205 }
10206 \f
10207 /* Return the number of "extended" bits there are in X, when interpreted
10208 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10209 unsigned quantities, this is the number of high-order zero bits.
10210 For signed quantities, this is the number of copies of the sign bit
10211 minus 1. In both case, this function returns the number of "spare"
10212 bits. For example, if two quantities for which this function returns
10213 at least 1 are added, the addition is known not to overflow.
10215 This function will always return 0 unless called during combine, which
10216 implies that it must be called from a define_split. */
10218 unsigned int
10220 {
10224 scalar_int_mode int_mode;
10232 }
10234 /* This function is called from `simplify_shift_const' to merge two
10235 outer operations. Specifically, we have already found that we need
10236 to perform operation *POP0 with constant *PCONST0 at the outermost
10237 position. We would now like to also perform OP1 with constant CONST1
10238 (with *POP0 being done last).
10240 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10241 the resulting operation. *PCOMP_P is set to 1 if we would need to
10242 complement the innermost operand, otherwise it is unchanged.
10244 MODE is the mode in which the operation will be done. No bits outside
10245 the width of this mode matter. It is assumed that the width of this mode
10246 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10248 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10249 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10250 result is simply *PCONST0.
10252 If the resulting operation cannot be expressed as one operation, we
10253 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10255 static int
10256 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10257 {
10264 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10268 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10269 if OP0 is SET. */
10278 {
10280 {
10298 }
10299 }
10301 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10305 /* If the two constants aren't the same, we can't do anything. The
10306 remaining six cases can all be done. */
10310 else
10312 {
10315 /* (a & b) | b == b */
10318 /* (a ^ b) | b == a | b */
10319 {;}
10324 /* (a & b) ^ b == (~a) & b */
10327 /* (a | b) ^ b == a & ~b */
10333 /* (a | b) & b == b */
10336 /* (a ^ b) & b) == (~a) & b */
10341 }
10343 /* Check for NO-OP cases. */
10356 /* ??? Slightly redundant with the above mask, but not entirely.
10357 Moving this above means we'd have to sign-extend the mode mask
10358 for the final test. */
10363 }
10364 \f
10365 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10366 the shift in. The original shift operation CODE is performed on OP in
10367 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10368 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10369 result of the shift is subject to operation OUTER_CODE with operand
10370 OUTER_CONST. */
10372 static scalar_int_mode
10376 {
10379 /* In general we can't perform in wider mode for right shift and rotate. */
10381 {
10383 /* We can still widen if the bits brought in from the left are identical
10384 to the sign bit of ORIG_MODE. */
10392 /* Similarly here but with zero bits. */
10397 /* We can also widen if the bits brought in will be masked off. This
10398 operation is performed in ORIG_MODE. */
10400 {
10406 }
10407 /* fall through */
10417 }
10418 }
10420 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10421 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10422 if we cannot simplify it. Otherwise, return a simplified value.
10424 The shift is normally computed in the widest mode we find in VAROP, as
10425 long as it isn't a different number of words than RESULT_MODE. Exceptions
10426 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10428 static rtx
10431 {
10436 machine_mode shift_mode;
10438 unsigned int mode_words
10440 /* We form (outer_op (code varop count) (outer_const)). */
10446 /* Make sure and truncate the "natural" shift on the way in. We don't
10447 want to do this inside the loop as it makes it more difficult to
10448 combine shifts. */
10452 /* If we were given an invalid count, don't do anything except exactly
10453 what was requested. */
10460 /* Unless one of the branches of the `if' in this loop does a `continue',
10461 we will `break' the loop after the `if'. */
10464 {
10465 /* If we have an operand of (clobber (const_int 0)), fail. */
10469 /* Convert ROTATERT to ROTATE. */
10471 {
10475 }
10479 {
10480 /* We only change the modes of scalar shifts. */
10486 }
10488 scalar_int_mode shift_unit_mode
10491 /* Handle cases where the count is greater than the size of the mode
10492 minus 1. For ASHIFT, use the size minus one as the count (this can
10493 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10494 take the count modulo the size. For other shifts, the result is
10495 zero.
10497 Since these shifts are being produced by the compiler by combining
10498 multiple operations, each of which are defined, we know what the
10499 result is supposed to be. */
10502 {
10507 else
10508 {
10509 /* We can't simply return zero because there may be an
10510 outer op. */
10514 }
10515 }
10517 /* If we discovered we had to complement VAROP, leave. Making a NOT
10518 here would cause an infinite loop. */
10523 {
10524 /* An arithmetic right shift of a quantity known to be -1 or 0
10525 is a no-op. */
10529 {
10532 }
10534 /* If we are doing an arithmetic right shift and discarding all but
10535 the sign bit copies, this is equivalent to doing a shift by the
10536 bitsize minus one. Convert it into that shift because it will
10537 often allow other simplifications. */
10544 /* We simplify the tests below and elsewhere by converting
10545 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10546 `make_compound_operation' will convert it to an ASHIFTRT for
10547 those machines (such as VAX) that don't have an LSHIFTRT. */
10552 shift_unit_mode)))
10564 }
10567 {
10574 {
10577 }
10581 /* The following rules apply only to scalars. */
10586 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10587 minus the width of a smaller mode, we can do this with a
10588 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10595 {
10604 }
10608 /* The following rules apply only to scalars. */
10614 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10615 the same number of words as what we've seen so far. Then store
10616 the widest mode in MODE. */
10622 == mode_words
10624 {
10629 }
10633 /* Some machines use MULT instead of ASHIFT because MULT
10634 is cheaper. But it is still better on those machines to
10635 merge two shifts into one. */
10638 {
10639 varop
10645 }
10649 /* Similar, for when divides are cheaper. */
10652 {
10653 varop
10659 }
10663 /* If we are extracting just the sign bit of an arithmetic
10664 right shift, that shift is not needed. However, the sign
10665 bit of a wider mode may be different from what would be
10666 interpreted as the sign bit in a narrower mode, so, if
10667 the result is narrower, don't discard the shift. */
10672 {
10675 }
10677 /* fall through */
10682 /* The following rules apply only to scalars. */
10689 /* Here we have two nested shifts. The result is usually the
10690 AND of a new shift with a mask. We compute the result below. */
10696 {
10700 rtx mask_rtx;
10702 /* We have one common special case. We can't do any merging if
10703 the inner code is an ASHIFTRT of a smaller mode. However, if
10704 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10705 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10706 we can convert it to
10707 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10708 This simplifies certain SIGN_EXTEND operations. */
10712 {
10713 /* C3 has the low-order C1 bits zero. */
10725 }
10727 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10728 than C1 high-order bits equal to the sign bit, we can convert
10729 this to either an ASHIFT or an ASHIFTRT depending on the
10730 two counts.
10732 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10738 {
10742 {
10745 }
10748 }
10750 /* There are some cases we can't do. If CODE is ASHIFTRT,
10751 we can only do this if FIRST_CODE is also ASHIFTRT.
10753 We can't do the case when CODE is ROTATE and FIRST_CODE is
10754 ASHIFTRT.
10756 If the mode of this shift is not the mode of the outer shift,
10757 we can't do this if either shift is a right shift or ROTATE.
10759 Finally, we can't do any of these if the mode is too wide
10760 unless the codes are the same.
10762 Handle the case where the shift codes are the same
10763 first. */
10766 {
10775 }
10786 /* To compute the mask to apply after the shift, shift the
10787 nonzero bits of the inner shift the same way the
10788 outer shift will. */
10791 int_result_mode);
10793 mask_rtx
10797 /* Give up if we can't compute an outer operation to use. */
10805 /* If the shifts are in the same direction, we add the
10806 counts. Otherwise, we subtract them. */
10810 else
10813 /* If COUNT is positive, the new shift is usually CODE,
10814 except for the two exceptions below, in which case it is
10815 FIRST_CODE. If the count is negative, FIRST_CODE should
10816 always be used */
10826 }
10828 /* If we have (A << B << C) for any shift, we can convert this to
10829 (A << C << B). This wins if A is a constant. Only try this if
10830 B is not a constant. */
10835 {
10836 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10837 sure the result will be masked. See PR70222. */
10845 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10846 up outer sign extension (often left and right shift) is
10847 hardly more efficient than the original. See PR70429. */
10857 }
10861 /* The following rules apply only to scalars. */
10865 /* Make this fit the case below. */
10872 /* The following rules apply only to scalars. */
10878 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10879 with C the size of VAROP - 1 and the shift is logical if
10880 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10881 we have an (le X 0) operation. If we have an arithmetic shift
10882 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10883 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10891 {
10894 const0_rtx);
10900 }
10902 /* If we have (shift (logical)), move the logical to the outside
10903 to allow it to possibly combine with another logical and the
10904 shift to combine with another shift. This also canonicalizes to
10905 what a ZERO_EXTRACT looks like. Also, some machines have
10906 (and (shift)) insns. */
10909 /* We can't do this if we have (ashiftrt (xor)) and the
10910 constant has its sign bit set in shift_unit_mode with
10911 shift_unit_mode wider than result_mode. */
10915 shift_unit_mode))
10924 {
10927 }
10929 /* If we can't do that, try to simplify the shift in each arm of the
10930 logical expression, make a new logical expression, and apply
10931 the inverse distributive law. This also can't be done for
10932 (ashiftrt (xor)) where we've widened the shift and the constant
10933 changes the sign bit. */
10938 shift_unit_mode)))
10939 {
10951 }
10955 /* The following rules apply only to scalars. */
10960 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10961 says that the sign bit can be tested, FOO has mode MODE, C is
10962 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10963 that may be nonzero. */
10973 {
10977 }
10981 /* The following rules apply only to scalars. */
10986 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10987 than the number of bits in the mode is equivalent to A. */
10991 {
10995 }
10997 /* NEG commutes with ASHIFT since it is multiplication. Move the
10998 NEG outside to allow shifts to combine. */
11002 {
11005 }
11009 /* The following rules apply only to scalars. */
11014 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11015 is one less than the number of bits in the mode is
11016 equivalent to (xor A 1). */
11023 {
11027 }
11029 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11030 that might be nonzero in BAR are those being shifted out and those
11031 bits are known zero in FOO, we can replace the PLUS with FOO.
11032 Similarly in the other operand order. This code occurs when
11033 we are computing the size of a variable-size array. */
11040 {
11043 }
11051 {
11054 }
11056 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11067 {
11070 }
11072 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11073 signbit', and attempt to change the PLUS to an XOR and move it to
11074 the outer operation as is done above in the AND/IOR/XOR case
11075 leg for shift(logical). See details in logical handling above
11076 for reasoning in doing so. */
11088 {
11091 }
11096 /* The following rules apply only to scalars. */
11101 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11102 with C the size of VAROP - 1 and the shift is logical if
11103 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11104 we have a (gt X 0) operation. If the shift is arithmetic with
11105 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11106 we have a (neg (gt X 0)) operation. */
11115 {
11118 const0_rtx);
11124 }
11128 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11129 if the truncate does not affect the value. */
11136 {
11139 varop_inner
11142 GEN_INT
11147 }
11152 }
11155 }
11159 {
11160 /* We only change the modes of scalar shifts. */
11165 }
11167 /* We have now finished analyzing the shift. The result should be
11168 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11169 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11170 to the result of the shift. OUTER_CONST is the relevant constant,
11171 but we must turn off all bits turned off in the shift. */
11179 /* Make a SUBREG if necessary. If we can't make it, fail. */
11184 /* If we have an outer operation and we just made a shift, it is
11185 possible that we could have simplified the shift were it not
11186 for the outer operation. So try to do the simplification
11187 recursively. */
11191 else
11197 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11198 turn off all the bits that the shift would have turned off. */
11200 /* We only change the modes of scalar shifts. */
11204 /* Do the remainder of the processing in RESULT_MODE. */
11207 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11208 operation. */
11213 {
11223 {
11224 /* This means that we have determined that the result is
11225 equivalent to a constant. This should be rare. */
11228 }
11231 else
11234 }
11237 }
11239 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11240 The result of the shift is RESULT_MODE. If we cannot simplify it,
11241 return X or, if it is NULL, synthesize the expression with
11242 simplify_gen_binary. Otherwise, return a simplified value.
11244 The shift is normally computed in the widest mode we find in VAROP, as
11245 long as it isn't a different number of words than RESULT_MODE. Exceptions
11246 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11248 static rtx
11251 {
11261 }
11263 \f
11264 /* A subroutine of recog_for_combine. See there for arguments and
11265 return value. */
11267 static int
11269 {
11271 rtx pat_without_clobbers;
11279 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11280 we use to indicate that something didn't match. If we find such a
11281 thing, force rejection. */
11295 {
11298 else
11301 }
11303 /* If it isn't, there is the possibility that we previously had an insn
11304 that clobbered some register as a side effect, but the combined
11305 insn doesn't need to do that. So try once more without the clobbers
11306 unless this represents an ASM insn. */
11310 {
11315 {
11318 pos++;
11319 }
11329 {
11332 else
11335 }
11336 }
11343 /* Recognize all noop sets, these will be killed by followup pass. */
11347 /* If we had any clobbers to add, make a new pattern than contains
11348 them. Then check to make sure that all of them are dead. */
11350 {
11360 else
11367 {
11372 {
11376 }
11377 }
11379 }
11383 {
11391 /* Allow targets to reject combined insn. */
11393 {
11396 dump_file);
11398 /* Callers expect recog_for_combine to strip
11399 clobbers from the pattern on failure. */
11404 }
11409 }
11415 }
11417 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11418 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11419 Return whether anything was so changed. */
11421 static bool
11423 {
11429 {
11441 {
11450 else
11454 }
11460 {
11466 }
11471 {
11475 }
11476 else
11482 {
11485 }
11489 }
11496 scalar_int_mode mode;
11502 {
11516 else
11524 }
11527 }
11529 /* Like recog, but we receive the address of a pointer to a new pattern.
11530 We try to match the rtx that the pointer points to.
11531 If that fails, we may try to modify or replace the pattern,
11532 storing the replacement into the same pointer object.
11534 Modifications include deletion or addition of CLOBBERs. If the
11535 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11536 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11537 (and undo if that fails).
11539 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11540 the CLOBBERs are placed.
11542 The value is the final insn code from the pattern ultimately matched,
11543 or -1. */
11545 static int
11547 {
11559 {
11562 {
11566 }
11567 }
11570 {
11575 }
11578 }
11579 \f
11580 /* Like gen_lowpart_general but for use by combine. In combine it
11581 is not possible to create any new pseudoregs. However, it is
11582 safe to create invalid memory addresses, because combine will
11583 try to recognize them and all they will do is make the combine
11584 attempt fail.
11586 If for some reason this cannot do its job, an rtx
11587 (clobber (const_int 0)) is returned.
11588 An insn containing that will not be recognized. */
11590 static rtx
11592 {
11596 rtx result;
11601 /* We can only support MODE being wider than a word if X is a
11602 constant integer or has a mode the same size. */
11607 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11608 won't know what to do. So we will strip off the SUBREG here and
11609 process normally. */
11611 {
11614 /* For use in case we fall down into the address adjustments
11615 further below, we need to adjust the known mode and size of
11616 x; imode and isize, since we just adjusted x. */
11623 }
11631 {
11632 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11633 address. */
11638 /* If we want to refer to something bigger than the original memref,
11639 generate a paradoxical subreg instead. That will force a reload
11640 of the original memref X. */
11646 }
11648 /* If X is a comparison operator, rewrite it in a new mode. This
11649 probably won't match, but may allow further simplifications. */
11653 /* If we couldn't simplify X any other way, just enclose it in a
11654 SUBREG. Normally, this SUBREG won't match, but some patterns may
11655 include an explicit SUBREG or we may simplify it further in combine. */
11656 else
11657 {
11658 rtx res;
11661 {
11666 }
11670 }
11672 fail:
11674 }
11675 \f
11676 /* Try to simplify a comparison between OP0 and a constant OP1,
11677 where CODE is the comparison code that will be tested, into a
11678 (CODE OP0 const0_rtx) form.
11680 The result is a possibly different comparison code to use.
11681 *POP1 may be updated. */
11683 static enum rtx_code
11686 {
11687 scalar_int_mode int_mode;
11690 /* Get the constant we are comparing against and turn off all bits
11691 not on in our mode. */
11695 /* If we are comparing against a constant power of two and the value
11696 being compared can only have that single bit nonzero (e.g., it was
11697 `and'ed with that bit), we can replace this with a comparison
11698 with zero. */
11707 {
11710 }
11712 /* Similarly, if we are comparing a value known to be either -1 or
11713 0 with -1, change it to the opposite comparison against zero. */
11719 {
11722 }
11724 /* Do some canonicalizations based on the comparison code. We prefer
11725 comparisons against zero and then prefer equality comparisons.
11726 If we can reduce the size of a constant, we will do that too. */
11728 {
11730 /* < C is equivalent to <= (C - 1) */
11732 {
11735 /* ... fall through to LE case below. */
11737 }
11738 else
11742 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11744 {
11747 }
11749 /* If we are doing a <= 0 comparison on a value known to have
11750 a zero sign bit, we can replace this with == 0. */
11761 /* >= C is equivalent to > (C - 1). */
11763 {
11766 /* ... fall through to GT below. */
11768 }
11769 else
11773 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11775 {
11778 }
11780 /* If we are doing a > 0 comparison on a value known to have
11781 a zero sign bit, we can replace this with != 0. */
11792 /* < C is equivalent to <= (C - 1). */
11794 {
11797 /* ... fall through ... */
11799 }
11800 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11805 {
11809 }
11810 else
11814 /* unsigned <= 0 is equivalent to == 0 */
11817 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11821 == ((HOST_WIDE_INT_1U
11823 {
11826 }
11830 /* >= C is equivalent to > (C - 1). */
11832 {
11835 /* ... fall through ... */
11837 }
11839 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11844 {
11848 }
11849 else
11853 /* unsigned > 0 is equivalent to != 0 */
11856 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11860 == (HOST_WIDE_INT_1U
11862 {
11865 }
11870 }
11874 }
11875 \f
11876 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11877 comparison code that will be tested.
11879 The result is a possibly different comparison code to use. *POP0 and
11880 *POP1 may be updated.
11882 It is possible that we might detect that a comparison is either always
11883 true or always false. However, we do not perform general constant
11884 folding in combine, so this knowledge isn't useful. Such tautologies
11885 should have been detected earlier. Hence we ignore all such cases. */
11887 static enum rtx_code
11889 {
11895 opt_scalar_int_mode tmode_iter;
11897 /* Try a few ways of applying the same transformation to both operands. */
11899 {
11900 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11901 so check specially. */
11920 {
11923 }
11925 /* If both operands are the same constant shift, see if we can ignore the
11926 shift. We can if the shift is a rotate or if the bits shifted out of
11927 this shift are known to be zero for both inputs and if the type of
11928 comparison is compatible with the shift. */
11941 {
11954 else
11956 }
11958 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11959 SUBREGs are of the same mode, and, in both cases, the AND would
11960 be redundant if the comparison was done in the narrower mode,
11961 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11962 and the operand's possibly nonzero bits are 0xffffff01; in that case
11963 if we only care about QImode, we don't need the AND). This case
11964 occurs if the output mode of an scc insn is not SImode and
11965 STORE_FLAG_VALUE == 1 (e.g., the 386).
11967 Similarly, check for a case where the AND's are ZERO_EXTEND
11968 operations from some narrower mode even though a SUBREG is not
11969 present. */
11974 {
11990 {
11994 /* The resulting comparison is always unsigned since we masked
11995 off the original sign bit. */
11999 }
12005 {
12011 }
12015 }
12017 /* If both operands are NOT, we can strip off the outer operation
12018 and adjust the comparison code for swapped operands; similarly for
12019 NEG, except that this must be an equality comparison. */
12025 else
12027 }
12029 /* If the first operand is a constant, swap the operands and adjust the
12030 comparison code appropriately, but don't do this if the second operand
12031 is already a constant integer. */
12033 {
12036 }
12038 /* We now enter a loop during which we will try to simplify the comparison.
12039 For the most part, we only are concerned with comparisons with zero,
12040 but some things may really be comparisons with zero but not start
12041 out looking that way. */
12044 {
12046 scalar_int_mode int_mode;
12050 HOST_WIDE_INT const_op;
12052 /* We only want to handle integral modes. This catches VOIDmode,
12053 CCmode, and the floating-point modes. An exception is that we
12054 can handle VOIDmode if OP0 is a COMPARE or a comparison
12055 operation. */
12062 /* Try to simplify the compare to constant, possibly changing the
12063 comparison op, and/or changing op1 to zero. */
12067 /* Compute some predicates to simplify code below. */
12074 /* If this is a sign bit comparison and we can do arithmetic in
12075 MODE, say that we will only be needing the sign bit of OP0. */
12080 HOST_WIDE_INT_1U
12085 {
12086 /* We can't do anything if OP0 is a condition code value, rather
12087 than an actual data value. */
12093 /* Get the two operands being compared. */
12096 else
12099 /* Check for the cases where we simply want the result of the
12100 earlier test or the opposite of that result. */
12104 {
12108 else
12112 {
12117 }
12118 }
12120 }
12126 /* Now try cases based on the opcode of OP0. If none of the cases
12127 does a "continue", we exit this loop immediately after the
12128 switch. */
12133 {
12135 /* If we are extracting a single bit from a variable position in
12136 a constant that has only a single bit set and are comparing it
12137 with zero, we can convert this into an equality comparison
12138 between the position and the location of the single bit. */
12139 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12140 have already reduced the shift count modulo the word size. */
12146 {
12154 /* Result is nonzero iff shift count is equal to I. */
12157 }
12159 /* fall through */
12164 {
12167 }
12171 /* If testing for equality, we can take the NOT of the constant. */
12174 {
12178 }
12180 /* If just looking at the sign bit, reverse the sense of the
12181 comparison. */
12183 {
12187 }
12191 /* If testing for equality, we can take the NEG of the constant. */
12194 {
12198 }
12200 /* The remaining cases only apply to comparisons with zero. */
12204 /* When X is ABS or is known positive,
12205 (neg X) is < 0 if and only if X != 0. */
12213 {
12217 }
12219 /* If we have NEG of something whose two high-order bits are the
12220 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12222 {
12226 }
12230 /* If we are testing equality and our count is a constant, we
12231 can perform the inverse operation on our RHS. */
12235 {
12239 }
12241 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12242 a particular bit. Convert it to an AND of a constant of that
12243 bit. This will be converted into a ZERO_EXTRACT. */
12247 {
12249 (HOST_WIDE_INT_1U
12254 }
12256 /* Fall through. */
12259 /* ABS is ignorable inside an equality comparison with zero. */
12261 {
12264 }
12268 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12269 (compare FOO CONST) if CONST fits in FOO's mode and we
12270 are either testing inequality or have an unsigned
12271 comparison with ZERO_EXTEND or a signed comparison with
12272 SIGN_EXTEND. But don't do it if we don't have a compare
12273 insn of the given mode, since we'd have to revert it
12274 later on, and then we wouldn't know whether to sign- or
12275 zero-extend. */
12277 && ! unsigned_comparison_p
12281 {
12284 }
12288 /* Check for the case where we are comparing A - C1 with C2, that is
12290 (subreg:MODE (plus (A) (-C1))) op (C2)
12292 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12293 comparison in the wider mode. One of the following two conditions
12294 must be true in order for this to be valid:
12296 1. The mode extension results in the same bit pattern being added
12297 on both sides and the comparison is equality or unsigned. As
12298 C2 has been truncated to fit in MODE, the pattern can only be
12299 all 0s or all 1s.
12301 2. The mode extension results in the sign bit being copied on
12302 each side.
12304 The difficulty here is that we have predicates for A but not for
12305 (A - C1) so we need to check that C1 is within proper bounds so
12306 as to perturbate A as little as possible. */
12315 {
12323 /* (A - C1) zero-extends if it is positive and sign-extends
12324 if it is negative, C2 both zero- and sign-extends. */
12328 /* (A - C1) sign-extends if it is positive and 1-extends
12329 if it is negative, C2 both sign- and 1-extends. */
12336 /* (A - C1) always sign-extends, like C2. */
12340 {
12343 }
12344 }
12346 /* If the inner mode is narrower and we are extracting the low part,
12347 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12349 ;
12358 {
12359 /* Remove outer subregs that don't do anything. */
12364 {
12368 }
12370 }
12371 else
12374 /* FALLTHROUGH */
12383 {
12386 }
12390 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12391 this for equality comparisons due to pathological cases involving
12392 overflows. */
12396 {
12400 }
12402 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12405 {
12409 }
12413 /* We used to optimize signed comparisons against zero, but that
12414 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12415 arrive here as equality comparisons, or (GEU, LTU) are
12416 optimized away. No need to special-case them. */
12418 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12419 (eq B (minus A C)), whichever simplifies. We can only do
12420 this for equality comparisons due to pathological cases involving
12421 overflows. */
12425 {
12429 }
12434 {
12438 }
12440 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12441 of bits in X minus 1, is one iff X > 0. */
12446 {
12450 }
12454 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12455 if C is zero or B is a constant. */
12459 {
12463 }
12468 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12469 iff X <= 0. */
12473 {
12477 }
12481 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12482 will be converted to a ZERO_EXTRACT later. */
12486 {
12491 }
12493 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12494 zero and X is a comparison and C1 and C2 describe only bits set
12495 in STORE_FLAG_VALUE, we can compare with X. */
12503 {
12510 {
12513 }
12514 }
12516 /* If we are doing an equality comparison of an AND of a bit equal
12517 to the sign bit, replace this with a LT or GE comparison of
12518 the underlying value. */
12525 {
12529 }
12531 /* If this AND operation is really a ZERO_EXTEND from a narrower
12532 mode, the constant fits within that mode, and this is either an
12533 equality or unsigned comparison, try to do this comparison in
12534 the narrower mode.
12536 Note that in:
12538 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12539 -> (ne:DI (reg:SI 4) (const_int 0))
12541 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12542 known to hold a value of the required mode the
12543 transformation is invalid. */
12551 {
12554 }
12556 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12557 fits in both M1 and M2 and the SUBREG is either paradoxical
12558 or represents the low part, permute the SUBREG and the AND
12559 and try again. */
12562 {
12564 /* Require an integral mode, to avoid creating something like
12565 (AND:SF ...). */
12568 /* It is unsafe to commute the AND into the SUBREG if the
12569 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12570 not defined. As originally written the upper bits
12571 have a defined value due to the AND operation.
12572 However, if we commute the AND inside the SUBREG then
12573 they no longer have defined values and the meaning of
12574 the code has been changed.
12575 Also C1 should not change value in the smaller mode,
12576 see PR67028 (a positive C1 can become negative in the
12577 smaller mode, so that the AND does no longer mask the
12578 upper bits). */
12579 && ((WORD_REGISTER_OPERATIONS
12591 {
12597 }
12598 }
12600 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12604 {
12609 }
12611 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12612 (eq (and (lshiftrt X) 1) 0).
12613 Also handle the case where (not X) is expressed using xor. */
12617 {
12627 == HOST_WIDE_INT_1U
12629 {
12630 op0
12635 }
12636 }
12640 /* If we have (compare (ashift FOO N) (const_int C)) and
12641 the high order N bits of FOO (N+1 if an inequality comparison)
12642 are known to be zero, we can do this by comparing FOO with C
12643 shifted right N bits so long as the low-order N bits of C are
12644 zero. */
12656 {
12657 /* We must perform a logical shift, not an arithmetic one,
12658 as we want the top N bits of C to be zero. */
12665 }
12667 /* If we are doing a sign bit comparison, it means we are testing
12668 a particular bit. Convert it to the appropriate AND. */
12671 {
12673 (HOST_WIDE_INT_1U
12678 }
12680 /* If this an equality comparison with zero and we are shifting
12681 the low bit to the sign bit, we can convert this to an AND of the
12682 low-order bit. */
12686 {
12689 }
12693 /* If this is an equality comparison with zero, we can do this
12694 as a logical shift, which might be much simpler. */
12697 {
12702 }
12704 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12705 do the comparison in a narrower mode. */
12715 {
12718 }
12720 /* Likewise if OP0 is a PLUS of a sign extension with a
12721 constant, which is usually represented with the PLUS
12722 between the shifts. */
12734 {
12742 new_const);
12744 }
12746 /* FALLTHROUGH */
12748 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12749 the low order N bits of FOO are known to be zero, we can do this
12750 by comparing FOO with C shifted left N bits so long as no
12751 overflow occurs. Even if the low order N bits of FOO aren't known
12752 to be zero, if the comparison is >= or < we can use the same
12753 optimization and for > or <= by setting all the low
12754 order N bits in the comparison constant. */
12765 {
12766 unsigned HOST_WIDE_INT low_bits
12768 & ((HOST_WIDE_INT_1U
12771 {
12772 /* If the shift was logical, then we must make the condition
12773 unsigned. */
12782 const_op
12787 }
12788 }
12790 /* If we are using this shift to extract just the sign bit, we
12791 can replace this with an LT or GE comparison. */
12796 {
12800 }
12805 }
12808 }
12810 /* Now make any compound operations involved in this comparison. Then,
12811 check for an outmost SUBREG on OP0 that is not doing anything or is
12812 paradoxical. The latter transformation must only be performed when
12813 it is known that the "extra" bits will be the same in op0 and op1 or
12814 that they don't matter. There are three cases to consider:
12816 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12817 care bits and we can assume they have any convenient value. So
12818 making the transformation is safe.
12820 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12821 In this case the upper bits of op0 are undefined. We should not make
12822 the simplification in that case as we do not know the contents of
12823 those bits.
12825 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12826 In that case we know those bits are zeros or ones. We must also be
12827 sure that they are the same as the upper bits of op1.
12829 We can never remove a SUBREG for a non-equality comparison because
12830 the sign bit is in a different place in the underlying object. */
12843 {
12845 {
12846 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12847 implemented. */
12849 {
12852 }
12853 }
12857 {
12862 }
12863 }
12865 /* We now do the opposite procedure: Some machines don't have compare
12866 insns in all modes. If OP0's mode is an integer mode smaller than a
12867 word and we can't do a compare in that mode, see if there is a larger
12868 mode for which we can do the compare. There are a number of cases in
12869 which we can use the wider mode. */
12875 {
12880 {
12883 /* If this is a test for negative, we can make an explicit
12884 test of the sign bit. Test this first so we can use
12885 a paradoxical subreg to extend OP0. */
12889 {
12890 unsigned HOST_WIDE_INT sign
12897 }
12899 /* If the only nonzero bits in OP0 and OP1 are those in the
12900 narrower mode and this is an equality or unsigned comparison,
12901 we can use the wider mode. Similarly for sign-extended
12902 values, in which case it is true for all comparisons. */
12919 {
12920 /* If OP0 is an AND and we don't have an AND in MODE either,
12921 make a new AND in the proper mode. */
12929 else
12930 {
12932 {
12937 }
12938 else
12939 {
12944 }
12946 }
12947 }
12948 }
12949 }
12951 /* We may have changed the comparison operands. Re-canonicalize. */
12953 {
12956 }
12958 /* If this machine only supports a subset of valid comparisons, see if we
12959 can convert an unsupported one into a supported one. */
12966 }
12967 \f
12968 /* Utility function for record_value_for_reg. Count number of
12969 rtxs in X. */
12970 static int
12972 {
12979 {
12999 }
13010 }
13011 \f
13012 /* Utility function for following routine. Called when X is part of a value
13013 being stored into last_set_value. Sets last_set_table_tick
13014 for each register mentioned. Similar to mention_regs in cse.c */
13016 static void
13018 {
13024 {
13030 {
13033 }
13036 }
13040 {
13041 /* Check for identical subexpressions. If x contains
13042 identical subexpression we only have to traverse one of
13043 them. */
13045 {
13046 /* Note that at this point x1 has already been
13047 processed. */
13051 /* If x0 and x1 are identical then there is no need to
13052 process x0. */
13056 /* If x0 is identical to a subexpression of x1 then while
13057 processing x1, x0 has already been processed. Thus we
13058 are done with x. */
13063 /* If x1 is identical to a subexpression of x0 then we
13064 still have to process the rest of x0. */
13067 {
13070 }
13071 }
13074 }
13078 }
13080 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13081 are saying that the register is clobbered and we no longer know its
13082 value. If INSN is zero, don't update reg_stat[].last_set; this is
13083 only permitted with VALUE also zero and is used to invalidate the
13084 register. */
13086 static void
13088 {
13094 /* If VALUE contains REG and we have a previous value for REG, substitute
13095 the previous value. */
13097 {
13098 rtx tem;
13100 /* Set things up so get_last_value is allowed to see anything set up to
13101 our insn. */
13105 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13106 it isn't going to be useful and will take a lot of time to process,
13107 so just use the CLOBBER. */
13110 {
13116 {
13117 /* If there are two or more occurrences of REG in VALUE,
13118 prevent the value from growing too much. */
13121 }
13124 }
13125 }
13127 /* For each register modified, show we don't know its value, that
13128 we don't know about its bitwise content, that its value has been
13129 updated, and that we don't know the location of the death of the
13130 register. */
13132 {
13144 }
13146 /* Mark registers that are being referenced in this value. */
13150 /* Now update the status of each register being set.
13151 If someone is using this register in this block, set this register
13152 to invalid since we will get confused between the two lives in this
13153 basic block. This makes using this register always invalid. In cse, we
13154 scan the table to invalidate all entries using this register, but this
13155 is too much work for us. */
13158 {
13164 else
13166 }
13168 /* The value being assigned might refer to X (like in "x++;"). In that
13169 case, we must replace it with (clobber (const_int 0)) to prevent
13170 infinite loops. */
13173 {
13177 }
13179 /* For the main register being modified, update the value, the mode, the
13180 nonzero bits, and the number of sign bit copies. */
13185 {
13193 rsp->last_set_sign_bit_copies
13195 }
13196 }
13198 /* Called via note_stores from record_dead_and_set_regs to handle one
13199 SET or CLOBBER in an insn. DATA is the instruction in which the
13200 set is occurring. */
13202 static void
13204 {
13211 {
13215 }
13218 {
13219 /* If we are setting the whole register, we know its value. Otherwise
13220 show that we don't know the value. We can handle SUBREG in
13221 some cases. */
13232 else
13234 }
13236 /* Ignore pushes, they clobber nothing. */
13239 }
13241 /* Update the records of when each REG was most recently set or killed
13242 for the things done by INSN. This is the last thing done in processing
13243 INSN in the combiner loop.
13245 We update reg_stat[], in particular fields last_set, last_set_value,
13246 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13247 last_death, and also the similar information mem_last_set (which insn
13248 most recently modified memory) and last_call_luid (which insn was the
13249 most recent subroutine call). */
13251 static void
13253 {
13254 rtx link;
13258 {
13261 {
13266 {
13271 }
13272 }
13275 }
13278 {
13279 hard_reg_set_iterator hrsi;
13281 {
13293 }
13297 /* We can't combine into a call pattern. Remember, though, that
13298 the return value register is set at this LUID. We could
13299 still replace a register with the return value from the
13300 wrong subroutine call! */
13302 }
13303 else
13305 }
13307 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13308 register present in the SUBREG, so for each such SUBREG go back and
13309 adjust nonzero and sign bit information of the registers that are
13310 known to have some zero/sign bits set.
13312 This is needed because when combine blows the SUBREGs away, the
13313 information on zero/sign bits is lost and further combines can be
13314 missed because of that. */
13316 static void
13318 {
13320 rtx set;
13328 {
13337 {
13340 }
13344 {
13347 }
13350 {
13353 }
13354 else
13356 }
13357 }
13359 /* Check if X, a register, is known to contain a value already
13360 truncated to MODE. In this case we can use a subreg to refer to
13361 the truncated value even though in the generic case we would need
13362 an explicit truncation. */
13364 static bool
13366 {
13378 }
13380 /* If X is a hard reg or a subreg record the mode that the register is
13381 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13382 able to turn a truncate into a subreg using this information. Return true
13383 if traversing X is complete. */
13385 static bool
13387 {
13388 machine_mode truncated_mode;
13392 {
13404 }
13405 /* ??? For hard-regs we now record everything. We might be able to
13406 optimize this using last_set_mode. */
13409 else
13416 {
13419 }
13422 }
13424 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13425 the modes they are used in. This can help truning TRUNCATEs into
13426 SUBREGs. */
13428 static void
13430 {
13435 }
13437 /* Scan X for promoted SUBREGs. For each one found,
13438 note what it implies to the registers used in it. */
13440 static void
13442 {
13447 else
13448 {
13454 {
13464 }
13465 }
13466 }
13467 \f
13468 /* Verify that all the registers and memory references mentioned in *LOC are
13469 still valid. *LOC was part of a value set in INSN when label_tick was
13470 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13471 the invalid references with (clobber (const_int 0)) and return 1. This
13472 replacement is useful because we often can get useful information about
13473 the form of a value (e.g., if it was produced by a shift that always
13474 produces -1 or 0) even though we don't know exactly what registers it
13475 was produced from. */
13477 static int
13479 {
13486 {
13492 {
13495 /* If this is a pseudo-register that was only set once and not
13496 live at the beginning of the function, it is always valid. */
13500 && (!REGNO_REG_SET_P
13502 regno)))
13504 {
13508 }
13509 }
13512 }
13513 /* If this is a memory reference, make sure that there were no stores after
13514 it that might have clobbered the value. We don't have alias info, so we
13515 assume any store invalidates it. Moreover, we only have local UIDs, so
13516 we also assume that there were stores in the intervening basic blocks. */
13519 {
13523 }
13526 {
13528 {
13529 /* Check for identical subexpressions. If x contains
13530 identical subexpression we only have to traverse one of
13531 them. */
13533 {
13534 /* Note that at this point x0 has already been checked
13535 and found valid. */
13539 /* If x0 and x1 are identical then x is also valid. */
13543 /* If x1 is identical to a subexpression of x0 then
13544 while checking x0, x1 has already been checked. Thus
13545 it is valid and so as x. */
13550 /* If x0 is identical to a subexpression of x1 then x is
13551 valid iff the rest of x1 is valid. */
13554 return
13558 }
13563 }
13569 }
13571 /* If we haven't found a reason for it to be invalid, it is valid. */
13573 }
13575 /* Get the last value assigned to X, if known. Some registers
13576 in the value may be replaced with (clobber (const_int 0)) if their value
13577 is known longer known reliably. */
13579 static rtx
13581 {
13583 rtx value;
13586 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13587 then convert it to the desired mode. If this is a paradoxical SUBREG,
13588 we cannot predict what values the "extra" bits might have. */
13602 /* If we don't have a value, or if it isn't for this basic block and
13603 it's either a hard register, set more than once, or it's a live
13604 at the beginning of the function, return 0.
13606 Because if it's not live at the beginning of the function then the reg
13607 is always set before being used (is never used without being set).
13608 And, if it's set only once, and it's always set before use, then all
13609 uses must have the same last value, even if it's not from this basic
13610 block. */
13617 || REGNO_REG_SET_P
13621 /* If the value was set in a later insn than the ones we are processing,
13622 we can't use it even if the register was only set once. */
13627 /* If fewer bits were set than what we are asked for now, we cannot use
13628 the value. */
13633 /* If the value has all its registers valid, return it. */
13637 /* Otherwise, make a copy and replace any invalid register with
13638 (clobber (const_int 0)). If that fails for some reason, return 0. */
13645 }
13646 \f
13647 /* Return nonzero if expression X refers to a REG or to memory
13648 that is set in an instruction more recent than FROM_LUID. */
13650 static int
13652 {
13658 {
13662 #ifdef PUSH_ROUNDING
13663 /* Don't allow uses of the stack pointer to be moved,
13664 because we don't know whether the move crosses a push insn. */
13667 #endif
13669 {
13675 }
13677 }
13685 {
13687 {
13692 }
13696 }
13698 }
13699 \f
13700 /* Define three variables used for communication between the following
13701 routines. */
13706 /* Function called via note_stores from reg_dead_at_p.
13708 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13709 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13711 static void
13713 {
13723 }
13725 /* Return nonzero if REG is known to be dead at INSN.
13727 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13728 referencing REG, it is dead. If we hit a SET referencing REG, it is
13729 live. Otherwise, see if it is live or dead at the start of the basic
13730 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13731 must be assumed to be always live. */
13733 static int
13735 {
13736 basic_block block;
13739 /* Set variables for reg_dead_at_p_1. */
13745 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13746 we allow the machine description to decide whether use-and-clobber
13747 patterns are OK. */
13749 {
13753 }
13755 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13756 beginning of basic block. */
13759 {
13761 {
13771 }
13777 }
13779 /* Look at live-in sets for the basic block that we were in. */
13785 }
13786 \f
13787 /* Note hard registers in X that are used. */
13789 static void
13791 {
13797 {
13801 CASE_CONST_ANY:
13806 /* CC0 must die in the insn after it is set, so we don't need to take
13807 special note of it here. */
13812 /* If we are clobbering a MEM, mark any hard registers inside the
13813 address as used. */
13820 /* A hard reg in a wide mode may really be multiple registers.
13821 If so, mark all of them just like the first. */
13823 {
13824 /* None of this applies to the stack, frame or arg pointers. */
13826 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13834 }
13838 {
13839 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13840 the address. */
13852 }
13857 }
13859 /* Recursively scan the operands of this expression. */
13861 {
13865 {
13869 {
13874 }
13875 }
13876 }
13877 }
13878 \f
13879 /* Remove register number REGNO from the dead registers list of INSN.
13881 Return the note used to record the death, if there was one. */
13883 rtx
13885 {
13892 }
13894 /* For each register (hardware or pseudo) used within expression X, if its
13895 death is in an instruction with luid between FROM_LUID (inclusive) and
13896 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13897 list headed by PNOTES.
13899 That said, don't move registers killed by maybe_kill_insn.
13901 This is done when X is being merged by combination into TO_INSN. These
13902 notes will then be distributed as needed. */
13904 static void
13907 {
13913 {
13917 /* Don't move the register if it gets killed in between from and to. */
13926 {
13929 /* It is possible for the call above to return 0. This can occur
13930 when last_death points to I2 or I1 that we combined with.
13931 In that case make a new note.
13933 We must also check for the case where X is a hard register
13934 and NOTE is a death note for a range of hard registers
13935 including X. In that case, we must put REG_DEAD notes for
13936 the remaining registers in place of NOTE. */
13940 {
13949 }
13951 /* If we didn't find any note, or if we found a REG_DEAD note that
13952 covers only part of the given reg, and we have a multi-reg hard
13953 register, then to be safe we must check for REG_DEAD notes
13954 for each register other than the first. They could have
13955 their own REG_DEAD notes lying around. */
13962 {
13969 else
13975 }
13978 {
13981 }
13982 else
13984 }
13987 }
13990 {
13995 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13996 that accesses one word of a multi-word item, some
13997 piece of everything register in the expression is used by
13998 this insn, so remove any old death. */
13999 /* ??? So why do we test for equality of the sizes? */
14005 {
14008 }
14010 /* If this is some other SUBREG, we know it replaces the entire
14011 value, so use that as the destination. */
14015 /* If this is a MEM, adjust deaths of anything used in the address.
14016 For a REG (the only other possibility), the entire value is
14017 being replaced so the old value is not used in this insn. */
14023 }
14032 {
14034 {
14039 }
14042 }
14043 }
14044 \f
14045 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14046 pattern of an insn. X must be a REG. */
14048 static int
14050 {
14054 {
14056 rtx target;
14063 else
14080 }
14088 }
14089 \f
14090 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14091 as appropriate. I3 and I2 are the insns resulting from the combination
14092 insns including FROM (I2 may be zero).
14094 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14095 not need REG_DEAD notes because they are being substituted for. This
14096 saves searching in the most common cases.
14098 Each note in the list is either ignored or placed on some insns, depending
14099 on the type of note. */
14101 static void
14104 {
14106 rtx tem_note;
14110 {
14115 {
14118 /* Doesn't matter much where we put this, as long as it's somewhere.
14119 It is preferable to keep these notes on branches, which is most
14120 likely to be i3. */
14127 else
14128 {
14131 }
14135 /* These notes must remain with the call or trapping instruction. */
14140 else
14141 {
14147 /* ??? Otherwise assume we've combined things such that we
14148 can now prove that the instructions can't trap. Drop the
14149 note in this case. */
14150 }
14154 /* ??? How to distribute between i3-i1. Assume i3 contains the
14155 entire adjustment. Assert i3 contains at least some adjust. */
14157 {
14159 /* fixup_args_size_notes looks at REG_NORETURN note,
14160 so ensure the note is placed there first. */
14162 {
14166 {
14172 }
14173 }
14175 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14176 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14179 && !ACCUMULATE_OUTGOING_ARGS
14181 }
14189 /* These notes must remain with the call. It should not be
14190 possible for both I2 and I3 to be a call. */
14193 else
14194 {
14197 }
14201 /* Any clobbers for i3 may still exist, and so we must process
14202 REG_UNUSED notes from that insn.
14204 Any clobbers from i2 or i1 can only exist if they were added by
14205 recog_for_combine. In that case, recog_for_combine created the
14206 necessary REG_UNUSED notes. Trying to keep any original
14207 REG_UNUSED notes from these insns can cause incorrect output
14208 if it is for the same register as the original i3 dest.
14209 In that case, we will notice that the register is set in i3,
14210 and then add a REG_UNUSED note for the destination of i3, which
14211 is wrong. However, it is possible to have REG_UNUSED notes from
14212 i2 or i1 for register which were both used and clobbered, so
14213 we keep notes from i2 or i1 if they will turn into REG_DEAD
14214 notes. */
14216 /* If this register is set or clobbered in I3, put the note there
14217 unless there is one already. */
14219 {
14227 }
14228 /* Otherwise, if this register is used by I3, then this register
14229 now dies here, so we must put a REG_DEAD note here unless there
14230 is one already. */
14236 {
14239 }
14245 /* These notes say something about results of an insn. We can
14246 only support them if they used to be on I3 in which case they
14247 remain on I3. Otherwise they are ignored.
14249 If the note refers to an expression that is not a constant, we
14250 must also ignore the note since we cannot tell whether the
14251 equivalence is still true. It might be possible to do
14252 slightly better than this (we only have a problem if I2DEST
14253 or I1DEST is present in the expression), but it doesn't
14254 seem worth the trouble. */
14262 /* These notes say something about how a register is used. They must
14263 be present on any use of the register in I2 or I3. */
14268 {
14271 else
14273 }
14278 /* This can show up in several ways -- either directly in the
14279 pattern, or hidden off in the constant pool with (or without?)
14280 a REG_EQUAL note. */
14281 /* ??? Ignore the without-reg_equal-note problem for now. */
14293 {
14296 else
14298 }
14300 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14301 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14302 there. */
14307 {
14314 }
14320 {
14328 }
14332 /* This note says something about the value of a register prior
14333 to the execution of an insn. It is too much trouble to see
14334 if the note is still correct in all situations. It is better
14335 to simply delete it. */
14339 /* If we replaced the right hand side of FROM_INSN with a
14340 REG_EQUAL note, the original use of the dying register
14341 will not have been combined into I3 and I2. In such cases,
14342 FROM_INSN is guaranteed to be the first of the combined
14343 instructions, so we simply need to search back before
14344 FROM_INSN for the previous use or set of this register,
14345 then alter the notes there appropriately.
14347 If the register is used as an input in I3, it dies there.
14348 Similarly for I2, if it is nonzero and adjacent to I3.
14350 If the register is not used as an input in either I3 or I2
14351 and it is not one of the registers we were supposed to eliminate,
14352 there are two possibilities. We might have a non-adjacent I2
14353 or we might have somehow eliminated an additional register
14354 from a computation. For example, we might have had A & B where
14355 we discover that B will always be zero. In this case we will
14356 eliminate the reference to A.
14358 In both cases, we must search to see if we can find a previous
14359 use of A and put the death note there. */
14365 else
14366 {
14372 {
14373 /* If the new I2 sets the same register that is marked
14374 dead in the note, we do not in general know where to
14375 put the note. One important case we _can_ handle is
14376 when the note comes from I3. */
14379 else
14381 }
14388 && !(i2mod
14390 i2mod_old_rhs)))
14395 }
14398 {
14402 {
14404 {
14408 }
14410 /* If the register is being set at TEM_INSN, see if that is all
14411 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14412 into a REG_UNUSED note instead. Don't delete sets to
14413 global register vars. */
14417 {
14428 ;
14430 /* Verify that it was the set, and not a clobber that
14431 modified the register.
14433 CC0 targets must be careful to maintain setter/user
14434 pairs. If we cannot delete the setter due to side
14435 effects, mark the user with an UNUSED note instead
14436 of deleting it. */
14440 && (!HAVE_cc0
14444 {
14445 /* Move the notes and links of TEM_INSN elsewhere.
14446 This might delete other dead insns recursively.
14447 First set the pattern to something that won't use
14448 any register. */
14467 /* Delete the setter too. */
14469 {
14482 }
14483 }
14484 else
14485 {
14488 /* If there isn't already a REG_UNUSED note, put one
14489 here. Do not place a REG_DEAD note, even if
14490 the register is also used here; that would not
14491 match the algorithm used in lifetime analysis
14492 and can cause the consistency check in the
14493 scheduler to fail. */
14498 }
14499 }
14503 {
14506 /* If we are doing a 3->2 combination, and we have a
14507 register which formerly died in i3 and was not used
14508 by i2, which now no longer dies in i3 and is used in
14509 i2 but does not die in i2, and place is between i2
14510 and i3, then we may need to move a link from place to
14511 i2. */
14513 && from_insn
14516 {
14520 }
14522 }
14526 }
14528 }
14530 /* If the register is set or already dead at PLACE, we needn't do
14531 anything with this note if it is still a REG_DEAD note.
14532 We check here if it is set at all, not if is it totally replaced,
14533 which is what `dead_or_set_p' checks, so also check for it being
14534 set partially. */
14537 {
14543 {
14544 /* Unless the register previously died in PLACE, clear
14545 last_death. [I no longer understand why this is
14546 being done.] */
14550 }
14551 else
14554 /* If this is a death note for a hard reg that is occupying
14555 multiple registers, ensure that we are still using all
14556 parts of the object. If we find a piece of the object
14557 that is unused, we must arrange for an appropriate REG_DEAD
14558 note to be added for it. However, we can't just emit a USE
14559 and tag the note to it, since the register might actually
14560 be dead; so we recourse, and the recursive call then finds
14561 the previous insn that used this register. */
14564 {
14573 {
14576 }
14579 {
14580 /* Put only REG_DEAD notes for pieces that are
14581 not already dead or set. */
14585 {
14592 {
14594 NULL_RTX);
14598 NULL_RTX);
14599 }
14604 {
14606 {
14610 }
14614 {
14617 }
14618 }
14619 }
14622 }
14623 }
14624 }
14628 /* Any other notes should not be present at this point in the
14629 compilation. */
14631 }
14634 {
14638 /* Set added_notes_insn to the earliest insn we added a note to. */
14642 }
14645 {
14648 /* Set added_notes_insn to the earliest insn we added a note to. */
14652 }
14653 }
14654 }
14655 \f
14656 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14657 I3, I2, and I1 to new locations. This is also called to add a link
14658 pointing at I3 when I3's destination is changed. */
14660 static void
14662 {
14666 {
14673 /* If the insn that this link points to is a NOTE, ignore it. */
14682 {
14685 {
14701 }
14704 }
14705 else
14715 /* A LOG_LINK is defined as being placed on the first insn that uses
14716 a register and points to the insn that sets the register. Start
14717 searching at the next insn after the target of the link and stop
14718 when we reach a set of the register or the end of the basic block.
14720 Note that this correctly handles the link that used to point from
14721 I3 to I2. Also note that not much searching is typically done here
14722 since most links don't point very far away. */
14731 {
14735 }
14738 {
14741 }
14745 /* If we found a place to put the link, place it there unless there
14746 is already a link to the same insn as LINK at that point. */
14749 {
14757 {
14761 /* Set added_links_insn to the earliest insn we added a
14762 link to. */
14766 }
14767 }
14768 }
14769 }
14770 \f
14771 /* Check for any register or memory mentioned in EQUIV that is not
14772 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14773 of EXPR where some registers may have been replaced by constants. */
14775 static bool
14777 {
14780 {
14785 }
14787 }
14788 \f
14789 DEBUG_FUNCTION void
14791 {
14792 fprintf
14794 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14796 }
14798 void
14800 {
14801 fprintf
14803 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14805 }
14806 \f
14807 /* Try combining insns through substitution. */
14808 static unsigned int
14810 {
14820 rebuild_jump_labels_after_combine
14823 /* Combining insns may have turned an indirect jump into a
14824 direct jump. Rebuild the JUMP_LABEL fields of jumping
14825 instructions. */
14827 {
14834 }
14838 }
14843 {
14853 };
14856 {
14860 {}
14862 /* opt_pass methods: */
14865 {
14867 }
14873 rtl_opt_pass *
14875 {
14877 }