1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
124 #include "hash-set.h"
126 #include "machmode.h"
128 #include "function.h"
131 #include "dominance.h"
134 #include "basic-block.h"
139 #include "rtl-error.h"
142 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
143 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
145 static int bb_reload_num
;
147 /* The current insn being processed and corresponding its single set
148 (NULL otherwise), its data (basic block, the insn data, the insn
149 static data, and the mode of each operand). */
150 static rtx_insn
*curr_insn
;
151 static rtx curr_insn_set
;
152 static basic_block curr_bb
;
153 static lra_insn_recog_data_t curr_id
;
154 static struct lra_static_insn_data
*curr_static_id
;
155 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
159 /* Start numbers for new registers and insns at the current constraints
161 static int new_regno_start
;
162 static int new_insn_uid_start
;
164 /* If LOC is nonnull, strip any outer subreg from it. */
166 strip_subreg (rtx
*loc
)
168 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
171 /* Return hard regno of REGNO or if it is was not assigned to a hard
172 register, use a hard register from its allocno class. */
174 get_try_hard_regno (int regno
)
177 enum reg_class rclass
;
179 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
180 hard_regno
= lra_get_regno_hard_regno (regno
);
183 rclass
= lra_get_allocno_class (regno
);
184 if (rclass
== NO_REGS
)
186 return ira_class_hard_regs
[rclass
][0];
189 /* Return final hard regno (plus offset) which will be after
190 elimination. We do this for matching constraints because the final
191 hard regno could have a different class. */
193 get_final_hard_regno (int hard_regno
, int offset
)
197 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
198 return hard_regno
+ offset
;
201 /* Return hard regno of X after removing subreg and making
202 elimination. If X is not a register or subreg of register, return
203 -1. For pseudo use its assignment. */
205 get_hard_regno (rtx x
)
208 int offset
, hard_regno
;
211 if (GET_CODE (x
) == SUBREG
)
212 reg
= SUBREG_REG (x
);
215 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
216 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
220 if (GET_CODE (x
) == SUBREG
)
221 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
222 SUBREG_BYTE (x
), GET_MODE (x
));
223 return get_final_hard_regno (hard_regno
, offset
);
226 /* If REGNO is a hard register or has been allocated a hard register,
227 return the class of that register. If REGNO is a reload pseudo
228 created by the current constraints pass, return its allocno class.
229 Return NO_REGS otherwise. */
230 static enum reg_class
231 get_reg_class (int regno
)
235 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
236 hard_regno
= lra_get_regno_hard_regno (regno
);
239 hard_regno
= get_final_hard_regno (hard_regno
, 0);
240 return REGNO_REG_CLASS (hard_regno
);
242 if (regno
>= new_regno_start
)
243 return lra_get_allocno_class (regno
);
247 /* Return true if REG satisfies (or will satisfy) reg class constraint
248 CL. Use elimination first if REG is a hard register. If REG is a
249 reload pseudo created by this constraints pass, assume that it will
250 be allocated a hard register from its allocno class, but allow that
251 class to be narrowed to CL if it is currently a superset of CL.
253 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
254 REGNO (reg), or NO_REGS if no change in its class was needed. */
256 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
258 enum reg_class rclass
, common_class
;
259 machine_mode reg_mode
;
260 int class_size
, hard_regno
, nregs
, i
, j
;
261 int regno
= REGNO (reg
);
263 if (new_class
!= NULL
)
264 *new_class
= NO_REGS
;
265 if (regno
< FIRST_PSEUDO_REGISTER
)
268 rtx
*final_loc
= &final_reg
;
270 lra_eliminate_reg_if_possible (final_loc
);
271 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
273 reg_mode
= GET_MODE (reg
);
274 rclass
= get_reg_class (regno
);
275 if (regno
< new_regno_start
276 /* Do not allow the constraints for reload instructions to
277 influence the classes of new pseudos. These reloads are
278 typically moves that have many alternatives, and restricting
279 reload pseudos for one alternative may lead to situations
280 where other reload pseudos are no longer allocatable. */
281 || (INSN_UID (curr_insn
) >= new_insn_uid_start
282 && curr_insn_set
!= NULL
283 && ((OBJECT_P (SET_SRC (curr_insn_set
))
284 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
285 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
286 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
287 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
288 /* When we don't know what class will be used finally for reload
289 pseudos, we use ALL_REGS. */
290 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
291 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
292 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
293 lra_no_alloc_regs
)));
296 common_class
= ira_reg_class_subset
[rclass
][cl
];
297 if (new_class
!= NULL
)
298 *new_class
= common_class
;
299 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
302 /* Check that there are enough allocatable regs. */
303 class_size
= ira_class_hard_regs_num
[common_class
];
304 for (i
= 0; i
< class_size
; i
++)
306 hard_regno
= ira_class_hard_regs
[common_class
][i
];
307 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
310 for (j
= 0; j
< nregs
; j
++)
311 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
312 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
322 /* Return true if REGNO satisfies a memory constraint. */
326 return get_reg_class (regno
) == NO_REGS
;
329 /* Return 1 if ADDR is a valid memory address for mode MODE in address
330 space AS, and check that each pseudo has the proper kind of hard
333 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
334 rtx addr
, addr_space_t as
)
336 #ifdef GO_IF_LEGITIMATE_ADDRESS
337 lra_assert (ADDR_SPACE_GENERIC_P (as
));
338 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
344 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
349 /* Temporarily eliminates registers in an address (for the lifetime of
351 class address_eliminator
{
353 address_eliminator (struct address_info
*ad
);
354 ~address_eliminator ();
357 struct address_info
*m_ad
;
365 address_eliminator::address_eliminator (struct address_info
*ad
)
367 m_base_loc (strip_subreg (ad
->base_term
)),
368 m_base_reg (NULL_RTX
),
369 m_index_loc (strip_subreg (ad
->index_term
)),
370 m_index_reg (NULL_RTX
)
372 if (m_base_loc
!= NULL
)
374 m_base_reg
= *m_base_loc
;
375 lra_eliminate_reg_if_possible (m_base_loc
);
376 if (m_ad
->base_term2
!= NULL
)
377 *m_ad
->base_term2
= *m_ad
->base_term
;
379 if (m_index_loc
!= NULL
)
381 m_index_reg
= *m_index_loc
;
382 lra_eliminate_reg_if_possible (m_index_loc
);
386 address_eliminator::~address_eliminator ()
388 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
390 *m_base_loc
= m_base_reg
;
391 if (m_ad
->base_term2
!= NULL
)
392 *m_ad
->base_term2
= *m_ad
->base_term
;
394 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
395 *m_index_loc
= m_index_reg
;
398 /* Return true if the eliminated form of AD is a legitimate target address. */
400 valid_address_p (struct address_info
*ad
)
402 address_eliminator
eliminator (ad
);
403 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
406 /* Return true if the eliminated form of memory reference OP satisfies
407 extra memory constraint CONSTRAINT. */
409 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
411 struct address_info ad
;
413 decompose_mem_address (&ad
, op
);
414 address_eliminator
eliminator (&ad
);
415 return constraint_satisfied_p (op
, constraint
);
418 /* Return true if the eliminated form of address AD satisfies extra
419 address constraint CONSTRAINT. */
421 satisfies_address_constraint_p (struct address_info
*ad
,
422 enum constraint_num constraint
)
424 address_eliminator
eliminator (ad
);
425 return constraint_satisfied_p (*ad
->outer
, constraint
);
428 /* Return true if the eliminated form of address OP satisfies extra
429 address constraint CONSTRAINT. */
431 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
433 struct address_info ad
;
435 decompose_lea_address (&ad
, &op
);
436 return satisfies_address_constraint_p (&ad
, constraint
);
439 /* Initiate equivalences for LRA. As we keep original equivalences
440 before any elimination, we need to make copies otherwise any change
441 in insns might change the equivalences. */
443 lra_init_equiv (void)
445 ira_expand_reg_equiv ();
446 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
450 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
451 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
452 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
453 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
457 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
459 /* Update equivalence for REGNO. We need to this as the equivalence
460 might contain other pseudos which are changed by their
463 update_equiv (int regno
)
467 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
468 ira_reg_equiv
[regno
].memory
469 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
471 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
472 ira_reg_equiv
[regno
].invariant
473 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
477 /* If we have decided to substitute X with another value, return that
478 value, otherwise return X. */
485 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
486 || ! ira_reg_equiv
[regno
].defined_p
487 || ! ira_reg_equiv
[regno
].profitable_p
488 || lra_get_regno_hard_regno (regno
) >= 0)
490 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
492 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
494 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
499 /* If we have decided to substitute X with the equivalent value,
500 return that value after elimination for INSN, otherwise return
503 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
505 rtx res
= get_equiv (x
);
507 if (x
== res
|| CONSTANT_P (res
))
509 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
512 /* Set up curr_operand_mode. */
514 init_curr_operand_mode (void)
516 int nop
= curr_static_id
->n_operands
;
517 for (int i
= 0; i
< nop
; i
++)
519 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
520 if (mode
== VOIDmode
)
522 /* The .md mode for address operands is the mode of the
523 addressed value rather than the mode of the address itself. */
524 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
527 mode
= curr_static_id
->operand
[i
].mode
;
529 curr_operand_mode
[i
] = mode
;
535 /* The page contains code to reuse input reloads. */
537 /* Structure describes input reload of the current insns. */
540 /* Reloaded value. */
542 /* Reload pseudo used. */
546 /* The number of elements in the following array. */
547 static int curr_insn_input_reloads_num
;
548 /* Array containing info about input reloads. It is used to find the
549 same input reload and reuse the reload pseudo in this case. */
550 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
552 /* Initiate data concerning reuse of input reloads for the current
555 init_curr_insn_input_reloads (void)
557 curr_insn_input_reloads_num
= 0;
560 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
561 created input reload pseudo (only if TYPE is not OP_OUT). Don't
562 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
563 wrapped up in SUBREG. The result pseudo is returned through
564 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
565 reused the already created input reload pseudo. Use TITLE to
566 describe new registers for debug purposes. */
568 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
569 enum reg_class rclass
, bool in_subreg_p
,
570 const char *title
, rtx
*result_reg
)
573 enum reg_class new_class
;
578 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
581 /* Prevent reuse value of expression with side effects,
582 e.g. volatile memory. */
583 if (! side_effects_p (original
))
584 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
585 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
586 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
588 rtx reg
= curr_insn_input_reloads
[i
].reg
;
590 /* If input is equal to original and both are VOIDmode,
591 GET_MODE (reg) might be still different from mode.
592 Ensure we don't return *result_reg with wrong mode. */
593 if (GET_MODE (reg
) != mode
)
597 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
599 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
600 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
604 if (lra_dump_file
!= NULL
)
606 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
607 dump_value_slim (lra_dump_file
, original
, 1);
609 if (new_class
!= lra_get_allocno_class (regno
))
610 lra_change_class (regno
, new_class
, ", change to", false);
611 if (lra_dump_file
!= NULL
)
612 fprintf (lra_dump_file
, "\n");
615 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
616 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
617 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
618 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
624 /* The page contains code to extract memory address parts. */
626 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
628 ok_for_index_p_nonstrict (rtx reg
)
630 unsigned regno
= REGNO (reg
);
632 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
635 /* A version of regno_ok_for_base_p for use here, when all pseudos
636 should count as OK. Arguments as for regno_ok_for_base_p. */
638 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
639 enum rtx_code outer_code
, enum rtx_code index_code
)
641 unsigned regno
= REGNO (reg
);
643 if (regno
>= FIRST_PSEUDO_REGISTER
)
645 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
650 /* The page contains major code to choose the current insn alternative
651 and generate reloads for it. */
653 /* Return the offset from REGNO of the least significant register
656 This function is used to tell whether two registers satisfy
657 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
659 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
660 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
662 lra_constraint_offset (int regno
, machine_mode mode
)
664 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
665 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
666 && SCALAR_INT_MODE_P (mode
))
667 return hard_regno_nregs
[regno
][mode
] - 1;
671 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
672 if they are the same hard reg, and has special hacks for
673 auto-increment and auto-decrement. This is specifically intended for
674 process_alt_operands to use in determining whether two operands
675 match. X is the operand whose number is the lower of the two.
677 It is supposed that X is the output operand and Y is the input
678 operand. Y_HARD_REGNO is the final hard regno of register Y or
679 register in subreg Y as we know it now. Otherwise, it is a
682 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
685 RTX_CODE code
= GET_CODE (x
);
690 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
691 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
695 i
= get_hard_regno (x
);
699 if ((j
= y_hard_regno
) < 0)
702 i
+= lra_constraint_offset (i
, GET_MODE (x
));
703 j
+= lra_constraint_offset (j
, GET_MODE (y
));
708 /* If two operands must match, because they are really a single
709 operand of an assembler insn, then two post-increments are invalid
710 because the assembler insn would increment only once. On the
711 other hand, a post-increment matches ordinary indexing if the
712 post-increment is the output operand. */
713 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
714 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
716 /* Two pre-increments are invalid because the assembler insn would
717 increment only once. On the other hand, a pre-increment matches
718 ordinary indexing if the pre-increment is the input operand. */
719 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
720 || GET_CODE (y
) == PRE_MODIFY
)
721 return operands_match_p (x
, XEXP (y
, 0), -1);
725 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
726 && x
== SUBREG_REG (y
))
728 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
729 && SUBREG_REG (x
) == y
)
732 /* Now we have disposed of all the cases in which different rtx
734 if (code
!= GET_CODE (y
))
737 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
738 if (GET_MODE (x
) != GET_MODE (y
))
747 return LABEL_REF_LABEL (x
) == LABEL_REF_LABEL (y
);
749 return XSTR (x
, 0) == XSTR (y
, 0);
755 /* Compare the elements. If any pair of corresponding elements fail
756 to match, return false for the whole things. */
758 fmt
= GET_RTX_FORMAT (code
);
759 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
765 if (XWINT (x
, i
) != XWINT (y
, i
))
770 if (XINT (x
, i
) != XINT (y
, i
))
775 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
784 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
786 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
788 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
794 /* It is believed that rtx's at this level will never
795 contain anything but integers and other rtx's, except for
796 within LABEL_REFs and SYMBOL_REFs. */
804 /* True if X is a constant that can be forced into the constant pool.
805 MODE is the mode of the operand, or VOIDmode if not known. */
806 #define CONST_POOL_OK_P(MODE, X) \
807 ((MODE) != VOIDmode \
809 && GET_CODE (X) != HIGH \
810 && !targetm.cannot_force_const_mem (MODE, X))
812 /* True if C is a non-empty register class that has too few registers
813 to be safely used as a reload target class. */
814 #define SMALL_REGISTER_CLASS_P(C) \
815 (ira_class_hard_regs_num [(C)] == 1 \
816 || (ira_class_hard_regs_num [(C)] >= 1 \
817 && targetm.class_likely_spilled_p (C)))
819 /* If REG is a reload pseudo, try to make its class satisfying CL. */
821 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
823 enum reg_class rclass
;
825 /* Do not make more accurate class from reloads generated. They are
826 mostly moves with a lot of constraints. Making more accurate
827 class may results in very narrow class and impossibility of find
828 registers for several reloads of one insn. */
829 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
831 if (GET_CODE (reg
) == SUBREG
)
832 reg
= SUBREG_REG (reg
);
833 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
835 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
836 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
839 /* Generate reloads for matching OUT and INS (array of input operand
840 numbers with end marker -1) with reg class GOAL_CLASS. Add input
841 and output reloads correspondingly to the lists *BEFORE and *AFTER.
842 OUT might be negative. In this case we generate input reloads for
843 matched input operands INS. */
845 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
846 rtx_insn
**before
, rtx_insn
**after
)
849 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
850 machine_mode inmode
, outmode
;
851 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
852 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
854 inmode
= curr_operand_mode
[ins
[0]];
855 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
856 push_to_sequence (*before
);
857 if (inmode
!= outmode
)
859 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
862 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
864 if (SCALAR_INT_MODE_P (inmode
))
865 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
867 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
868 LRA_SUBREG_P (new_out_reg
) = 1;
869 /* If the input reg is dying here, we can use the same hard
870 register for REG and IN_RTX. We do it only for original
871 pseudos as reload pseudos can die although original
872 pseudos still live where reload pseudos dies. */
873 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
874 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
875 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
880 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
882 if (SCALAR_INT_MODE_P (outmode
))
883 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
885 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
886 /* NEW_IN_REG is non-paradoxical subreg. We don't want
887 NEW_OUT_REG living above. We add clobber clause for
888 this. This is just a temporary clobber. We can remove
889 it at the end of LRA work. */
890 clobber
= emit_clobber (new_out_reg
);
891 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
892 LRA_SUBREG_P (new_in_reg
) = 1;
893 if (GET_CODE (in_rtx
) == SUBREG
)
895 rtx subreg_reg
= SUBREG_REG (in_rtx
);
897 /* If SUBREG_REG is dying here and sub-registers IN_RTX
898 and NEW_IN_REG are similar, we can use the same hard
899 register for REG and SUBREG_REG. */
900 if (REG_P (subreg_reg
)
901 && (int) REGNO (subreg_reg
) < lra_new_regno_start
902 && GET_MODE (subreg_reg
) == outmode
903 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
904 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
905 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
911 /* Pseudos have values -- see comments for lra_reg_info.
912 Different pseudos with the same value do not conflict even if
913 they live in the same place. When we create a pseudo we
914 assign value of original pseudo (if any) from which we
915 created the new pseudo. If we create the pseudo from the
916 input pseudo, the new pseudo will no conflict with the input
917 pseudo which is wrong when the input pseudo lives after the
918 insn and as the new pseudo value is changed by the insn
919 output. Therefore we create the new pseudo from the output.
921 We cannot reuse the current output register because we might
922 have a situation like "a <- a op b", where the constraints
923 force the second input operand ("b") to match the output
924 operand ("a"). "b" must then be copied into a new register
925 so that it doesn't clobber the current value of "a". */
927 new_in_reg
= new_out_reg
928 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
931 /* In operand can be got from transformations before processing insn
932 constraints. One example of such transformations is subreg
933 reloading (see function simplify_operand_subreg). The new
934 pseudos created by the transformations might have inaccurate
935 class (ALL_REGS) and we should make their classes more
937 narrow_reload_pseudo_class (in_rtx
, goal_class
);
938 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
939 *before
= get_insns ();
941 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
944 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
945 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
946 *curr_id
->operand_loc
[in
] = new_in_reg
;
948 lra_update_dups (curr_id
, ins
);
951 /* See a comment for the input operand above. */
952 narrow_reload_pseudo_class (out_rtx
, goal_class
);
953 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
956 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
958 *after
= get_insns ();
961 *curr_id
->operand_loc
[out
] = new_out_reg
;
962 lra_update_dup (curr_id
, out
);
965 /* Return register class which is union of all reg classes in insn
966 constraint alternative string starting with P. */
967 static enum reg_class
968 reg_class_from_constraints (const char *p
)
971 enum reg_class op_class
= NO_REGS
;
974 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
981 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
985 enum constraint_num cn
= lookup_constraint (p
);
986 enum reg_class cl
= reg_class_for_constraint (cn
);
989 if (insn_extra_address_constraint (cn
))
991 = (reg_class_subunion
992 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
997 op_class
= reg_class_subunion
[op_class
][cl
];
1000 while ((p
+= len
), c
);
1004 /* If OP is a register, return the class of the register as per
1005 get_reg_class, otherwise return NO_REGS. */
1006 static inline enum reg_class
1007 get_op_class (rtx op
)
1009 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1012 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1013 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1014 SUBREG for VAL to make them equal. */
1016 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1018 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1020 /* Usually size of mem_pseudo is greater than val size but in
1021 rare cases it can be less as it can be defined by target
1022 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1025 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1026 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1028 LRA_SUBREG_P (val
) = 1;
1032 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1033 LRA_SUBREG_P (mem_pseudo
) = 1;
1036 return as_a
<rtx_insn
*> (to_p
1037 ? gen_move_insn (mem_pseudo
, val
)
1038 : gen_move_insn (val
, mem_pseudo
));
1041 /* Process a special case insn (register move), return true if we
1042 don't need to process it anymore. INSN should be a single set
1043 insn. Set up that RTL was changed through CHANGE_P and macro
1044 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1047 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1050 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, scratch_reg
;
1052 enum reg_class dclass
, sclass
, secondary_class
;
1053 machine_mode sreg_mode
;
1054 secondary_reload_info sri
;
1056 lra_assert (curr_insn_set
!= NULL_RTX
);
1057 dreg
= dest
= SET_DEST (curr_insn_set
);
1058 sreg
= src
= SET_SRC (curr_insn_set
);
1059 if (GET_CODE (dest
) == SUBREG
)
1060 dreg
= SUBREG_REG (dest
);
1061 if (GET_CODE (src
) == SUBREG
)
1062 sreg
= SUBREG_REG (src
);
1063 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1065 sclass
= dclass
= NO_REGS
;
1067 dclass
= get_reg_class (REGNO (dreg
));
1068 if (dclass
== ALL_REGS
)
1069 /* ALL_REGS is used for new pseudos created by transformations
1070 like reload of SUBREG_REG (see function
1071 simplify_operand_subreg). We don't know their class yet. We
1072 should figure out the class from processing the insn
1073 constraints not in this fast path function. Even if ALL_REGS
1074 were a right class for the pseudo, secondary_... hooks usually
1075 are not define for ALL_REGS. */
1077 sreg_mode
= GET_MODE (sreg
);
1080 sclass
= get_reg_class (REGNO (sreg
));
1081 if (sclass
== ALL_REGS
)
1082 /* See comments above. */
1084 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1086 #ifdef SECONDARY_MEMORY_NEEDED
1087 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1088 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1089 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1090 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1098 if (! REG_P (dreg
) || ! REG_P (sreg
))
1100 sri
.prev_sri
= NULL
;
1101 sri
.icode
= CODE_FOR_nothing
;
1103 secondary_class
= NO_REGS
;
1104 /* Set up hard register for a reload pseudo for hook
1105 secondary_reload because some targets just ignore unassigned
1106 pseudos in the hook. */
1107 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1109 dregno
= REGNO (dreg
);
1110 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1114 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1116 sregno
= REGNO (sreg
);
1117 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1121 if (sclass
!= NO_REGS
)
1123 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1124 (reg_class_t
) sclass
,
1125 GET_MODE (src
), &sri
);
1126 if (sclass
== NO_REGS
1127 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1128 && dclass
!= NO_REGS
))
1130 enum reg_class old_sclass
= secondary_class
;
1131 secondary_reload_info old_sri
= sri
;
1133 sri
.prev_sri
= NULL
;
1134 sri
.icode
= CODE_FOR_nothing
;
1137 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1138 (reg_class_t
) dclass
,
1140 /* Check the target hook consistency. */
1142 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1143 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1144 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1147 reg_renumber
[sregno
] = -1;
1149 reg_renumber
[dregno
] = -1;
1150 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1154 if (secondary_class
!= NO_REGS
)
1155 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1159 if (old_sreg
!= sreg
)
1160 sreg
= copy_rtx (sreg
);
1161 if (sri
.icode
== CODE_FOR_nothing
)
1162 lra_emit_move (new_reg
, sreg
);
1165 enum reg_class scratch_class
;
1167 scratch_class
= (reg_class_from_constraints
1168 (insn_data
[sri
.icode
].operand
[2].constraint
));
1169 scratch_reg
= (lra_create_new_reg_with_unique_value
1170 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1171 scratch_class
, "scratch"));
1172 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1173 sreg
, scratch_reg
));
1175 before
= get_insns ();
1177 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1178 if (new_reg
!= NULL_RTX
)
1180 if (GET_CODE (src
) == SUBREG
)
1181 SUBREG_REG (src
) = new_reg
;
1183 SET_SRC (curr_insn_set
) = new_reg
;
1187 if (lra_dump_file
!= NULL
)
1189 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1190 dump_insn_slim (lra_dump_file
, curr_insn
);
1192 lra_set_insn_deleted (curr_insn
);
1198 /* The following data describe the result of process_alt_operands.
1199 The data are used in curr_insn_transform to generate reloads. */
1201 /* The chosen reg classes which should be used for the corresponding
1203 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1204 /* True if the operand should be the same as another operand and that
1205 other operand does not need a reload. */
1206 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1207 /* True if the operand does not need a reload. */
1208 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1209 /* True if the operand can be offsetable memory. */
1210 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1211 /* The number of an operand to which given operand can be matched to. */
1212 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1213 /* The number of elements in the following array. */
1214 static int goal_alt_dont_inherit_ops_num
;
1215 /* Numbers of operands whose reload pseudos should not be inherited. */
1216 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1217 /* True if the insn commutative operands should be swapped. */
1218 static bool goal_alt_swapped
;
1219 /* The chosen insn alternative. */
1220 static int goal_alt_number
;
1222 /* The following five variables are used to choose the best insn
1223 alternative. They reflect final characteristics of the best
1226 /* Number of necessary reloads and overall cost reflecting the
1227 previous value and other unpleasantness of the best alternative. */
1228 static int best_losers
, best_overall
;
1229 /* Overall number hard registers used for reloads. For example, on
1230 some targets we need 2 general registers to reload DFmode and only
1231 one floating point register. */
1232 static int best_reload_nregs
;
1233 /* Overall number reflecting distances of previous reloading the same
1234 value. The distances are counted from the current BB start. It is
1235 used to improve inheritance chances. */
1236 static int best_reload_sum
;
1238 /* True if the current insn should have no correspondingly input or
1240 static bool no_input_reloads_p
, no_output_reloads_p
;
1242 /* True if we swapped the commutative operands in the current
1244 static int curr_swapped
;
1246 /* Arrange for address element *LOC to be a register of class CL.
1247 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1248 automodified value; handle that case by adding the required output
1249 reloads to list AFTER. Return true if the RTL was changed. */
1251 process_addr_reg (rtx
*loc
, rtx_insn
**before
, rtx_insn
**after
,
1255 enum reg_class rclass
, new_class
;
1259 bool subreg_p
, before_p
= false;
1261 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1263 loc
= &SUBREG_REG (*loc
);
1265 mode
= GET_MODE (reg
);
1268 /* Always reload memory in an address even if the target supports
1270 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1275 regno
= REGNO (reg
);
1276 rclass
= get_reg_class (regno
);
1277 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1279 if (lra_dump_file
!= NULL
)
1281 fprintf (lra_dump_file
,
1282 "Changing pseudo %d in address of insn %u on equiv ",
1283 REGNO (reg
), INSN_UID (curr_insn
));
1284 dump_value_slim (lra_dump_file
, *loc
, 1);
1285 fprintf (lra_dump_file
, "\n");
1287 *loc
= copy_rtx (*loc
);
1289 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1292 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1293 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1296 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1298 lra_change_class (regno
, new_class
, " Change to", true);
1306 push_to_sequence (*before
);
1307 lra_emit_move (new_reg
, reg
);
1308 *before
= get_insns ();
1315 lra_emit_move (reg
, new_reg
);
1317 *after
= get_insns ();
1323 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1324 the insn to be inserted before curr insn. AFTER returns the
1325 the insn to be inserted after curr insn. ORIGREG and NEWREG
1326 are the original reg and new reg for reload. */
1328 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1333 push_to_sequence (*before
);
1334 lra_emit_move (newreg
, origreg
);
1335 *before
= get_insns ();
1341 lra_emit_move (origreg
, newreg
);
1343 *after
= get_insns ();
1348 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1350 /* Make reloads for subreg in operand NOP with internal subreg mode
1351 REG_MODE, add new reloads for further processing. Return true if
1352 any reload was generated. */
1354 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1357 rtx_insn
*before
, *after
;
1360 rtx operand
= *curr_id
->operand_loc
[nop
];
1361 enum reg_class regclass
;
1364 before
= after
= NULL
;
1366 if (GET_CODE (operand
) != SUBREG
)
1369 mode
= GET_MODE (operand
);
1370 reg
= SUBREG_REG (operand
);
1371 type
= curr_static_id
->operand
[nop
].type
;
1372 /* If we change address for paradoxical subreg of memory, the
1373 address might violate the necessary alignment or the access might
1374 be slow. So take this into consideration. We should not worry
1375 about access beyond allocated memory for paradoxical memory
1376 subregs as we don't substitute such equiv memory (see processing
1377 equivalences in function lra_constraints) and because for spilled
1378 pseudos we allocate stack memory enough for the biggest
1379 corresponding paradoxical subreg. */
1381 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1382 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1384 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1386 alter_subreg (curr_id
->operand_loc
[nop
], false);
1387 subst
= *curr_id
->operand_loc
[nop
];
1388 lra_assert (MEM_P (subst
));
1389 if (! valid_address_p (GET_MODE (reg
), XEXP (reg
, 0),
1390 MEM_ADDR_SPACE (reg
))
1391 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1392 MEM_ADDR_SPACE (subst
)))
1394 /* If the address was valid and became invalid, prefer to reload
1395 the memory. Typical case is when the index scale should
1396 correspond the memory. */
1397 *curr_id
->operand_loc
[nop
] = old
;
1399 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1401 alter_subreg (curr_id
->operand_loc
[nop
], false);
1404 /* Put constant into memory when we have mixed modes. It generates
1405 a better code in most cases as it does not need a secondary
1406 reload memory. It also prevents LRA looping when LRA is using
1407 secondary reload memory again and again. */
1408 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1409 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1411 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1412 alter_subreg (curr_id
->operand_loc
[nop
], false);
1415 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1416 if there may be a problem accessing OPERAND in the outer
1419 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1420 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1421 /* Don't reload paradoxical subregs because we could be looping
1422 having repeatedly final regno out of hard regs range. */
1423 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1424 >= hard_regno_nregs
[hard_regno
][mode
])
1425 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1426 SUBREG_BYTE (operand
), mode
) < 0
1427 /* Don't reload subreg for matching reload. It is actually
1428 valid subreg in LRA. */
1429 && ! LRA_SUBREG_P (operand
))
1430 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1432 enum reg_class rclass
;
1435 /* There is a big probability that we will get the same class
1436 for the new pseudo and we will get the same insn which
1437 means infinite looping. So spill the new pseudo. */
1440 /* The class will be defined later in curr_insn_transform. */
1442 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1444 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1445 rclass
, TRUE
, "subreg reg", &new_reg
))
1447 bool insert_before
, insert_after
;
1448 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1450 insert_before
= (type
!= OP_OUT
1451 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1452 insert_after
= (type
!= OP_IN
);
1453 insert_move_for_subreg (insert_before
? &before
: NULL
,
1454 insert_after
? &after
: NULL
,
1457 SUBREG_REG (operand
) = new_reg
;
1458 lra_process_new_insns (curr_insn
, before
, after
,
1459 "Inserting subreg reload");
1462 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1463 IRA allocates hardreg to the inner pseudo reg according to its mode
1464 instead of the outermode, so the size of the hardreg may not be enough
1465 to contain the outermode operand, in that case we may need to insert
1466 reload for the reg. For the following two types of paradoxical subreg,
1467 we need to insert reload:
1468 1. If the op_type is OP_IN, and the hardreg could not be paired with
1469 other hardreg to contain the outermode operand
1470 (checked by in_hard_reg_set_p), we need to insert the reload.
1471 2. If the op_type is OP_OUT or OP_INOUT.
1473 Here is a paradoxical subreg example showing how the reload is generated:
1475 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1476 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1478 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1479 here, if reg107 is assigned to hardreg R15, because R15 is the last
1480 hardreg, compiler cannot find another hardreg to pair with R15 to
1481 contain TImode data. So we insert a TImode reload reg180 for it.
1482 After reload is inserted:
1484 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1485 (reg:DI 107 [ __comp ])) -1
1486 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1487 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1489 Two reload hard registers will be allocated to reg180 to save TImode data
1491 else if (REG_P (reg
)
1492 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1493 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1494 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1495 < hard_regno_nregs
[hard_regno
][mode
])
1496 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1498 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1501 /* The class will be defined later in curr_insn_transform. */
1502 enum reg_class rclass
1503 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1505 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1506 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1509 bool insert_before
, insert_after
;
1511 PUT_MODE (new_reg
, mode
);
1512 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1513 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1515 insert_before
= (type
!= OP_OUT
);
1516 insert_after
= (type
!= OP_IN
);
1517 insert_move_for_subreg (insert_before
? &before
: NULL
,
1518 insert_after
? &after
: NULL
,
1521 SUBREG_REG (operand
) = new_reg
;
1522 lra_process_new_insns (curr_insn
, before
, after
,
1523 "Inserting paradoxical subreg reload");
1529 /* Return TRUE if X refers for a hard register from SET. */
1531 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1533 int i
, j
, x_hard_regno
;
1540 code
= GET_CODE (x
);
1541 mode
= GET_MODE (x
);
1545 code
= GET_CODE (x
);
1546 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1547 mode
= GET_MODE (x
);
1552 x_hard_regno
= get_hard_regno (x
);
1553 return (x_hard_regno
>= 0
1554 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1558 struct address_info ad
;
1560 decompose_mem_address (&ad
, x
);
1561 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1563 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1566 fmt
= GET_RTX_FORMAT (code
);
1567 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1571 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1574 else if (fmt
[i
] == 'E')
1576 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1577 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1584 /* Return true if OP is a spilled pseudo. */
1586 spilled_pseudo_p (rtx op
)
1589 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1592 /* Return true if X is a general constant. */
1594 general_constant_p (rtx x
)
1596 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1600 reg_in_class_p (rtx reg
, enum reg_class cl
)
1603 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1604 return in_class_p (reg
, cl
, NULL
);
1607 /* Major function to choose the current insn alternative and what
1608 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1609 negative we should consider only this alternative. Return false if
1610 we can not choose the alternative or find how to reload the
1613 process_alt_operands (int only_alternative
)
1616 int nop
, overall
, nalt
;
1617 int n_alternatives
= curr_static_id
->n_alternatives
;
1618 int n_operands
= curr_static_id
->n_operands
;
1619 /* LOSERS counts the operands that don't fit this alternative and
1620 would require loading. */
1622 /* REJECT is a count of how undesirable this alternative says it is
1623 if any reloading is required. If the alternative matches exactly
1624 then REJECT is ignored, but otherwise it gets this much counted
1625 against it in addition to the reloading needed. */
1627 /* The number of elements in the following array. */
1628 int early_clobbered_regs_num
;
1629 /* Numbers of operands which are early clobber registers. */
1630 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1631 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1632 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1633 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1634 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1635 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1636 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1637 /* The number of elements in the following array. */
1638 int curr_alt_dont_inherit_ops_num
;
1639 /* Numbers of operands whose reload pseudos should not be inherited. */
1640 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1642 /* The register when the operand is a subreg of register, otherwise the
1644 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1645 /* The register if the operand is a register or subreg of register,
1647 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1648 int hard_regno
[MAX_RECOG_OPERANDS
];
1649 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1650 int reload_nregs
, reload_sum
;
1654 /* Calculate some data common for all alternatives to speed up the
1656 for (nop
= 0; nop
< n_operands
; nop
++)
1660 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1661 /* The real hard regno of the operand after the allocation. */
1662 hard_regno
[nop
] = get_hard_regno (op
);
1664 operand_reg
[nop
] = reg
= op
;
1665 biggest_mode
[nop
] = GET_MODE (op
);
1666 if (GET_CODE (op
) == SUBREG
)
1668 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1669 if (GET_MODE_SIZE (biggest_mode
[nop
])
1670 < GET_MODE_SIZE (GET_MODE (reg
)))
1671 biggest_mode
[nop
] = GET_MODE (reg
);
1674 operand_reg
[nop
] = NULL_RTX
;
1675 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1676 || ((int) REGNO (reg
)
1677 == lra_get_elimination_hard_regno (REGNO (reg
))))
1678 no_subreg_reg_operand
[nop
] = reg
;
1680 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1681 /* Just use natural mode for elimination result. It should
1682 be enough for extra constraints hooks. */
1683 = regno_reg_rtx
[hard_regno
[nop
]];
1686 /* The constraints are made of several alternatives. Each operand's
1687 constraint looks like foo,bar,... with commas separating the
1688 alternatives. The first alternatives for all operands go
1689 together, the second alternatives go together, etc.
1691 First loop over alternatives. */
1692 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1693 if (only_alternative
>= 0)
1694 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1696 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1698 /* Loop over operands for one constraint alternative. */
1699 if (!TEST_BIT (preferred
, nalt
))
1702 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1703 for (nop
= 0; nop
< n_operands
; nop
++)
1705 int inc
= (curr_static_id
1706 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1707 if (lra_dump_file
!= NULL
&& inc
!= 0)
1708 fprintf (lra_dump_file
,
1709 " Staticly defined alt reject+=%d\n", inc
);
1712 early_clobbered_regs_num
= 0;
1714 for (nop
= 0; nop
< n_operands
; nop
++)
1718 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1719 bool win
, did_match
, offmemok
, early_clobber_p
;
1720 /* false => this operand can be reloaded somehow for this
1723 /* true => this operand can be reloaded if the alternative
1726 /* True if a constant forced into memory would be OK for
1729 enum reg_class this_alternative
, this_costly_alternative
;
1730 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1731 bool this_alternative_match_win
, this_alternative_win
;
1732 bool this_alternative_offmemok
;
1735 enum constraint_num cn
;
1737 opalt_num
= nalt
* n_operands
+ nop
;
1738 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1740 /* Fast track for no constraints at all. */
1741 curr_alt
[nop
] = NO_REGS
;
1742 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1743 curr_alt_win
[nop
] = true;
1744 curr_alt_match_win
[nop
] = false;
1745 curr_alt_offmemok
[nop
] = false;
1746 curr_alt_matches
[nop
] = -1;
1750 op
= no_subreg_reg_operand
[nop
];
1751 mode
= curr_operand_mode
[nop
];
1753 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1756 early_clobber_p
= false;
1757 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1759 this_costly_alternative
= this_alternative
= NO_REGS
;
1760 /* We update set of possible hard regs besides its class
1761 because reg class might be inaccurate. For example,
1762 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1763 is translated in HI_REGS because classes are merged by
1764 pairs and there is no accurate intermediate class. */
1765 CLEAR_HARD_REG_SET (this_alternative_set
);
1766 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1767 this_alternative_win
= false;
1768 this_alternative_match_win
= false;
1769 this_alternative_offmemok
= false;
1770 this_alternative_matches
= -1;
1772 /* An empty constraint should be excluded by the fast
1774 lra_assert (*p
!= 0 && *p
!= ',');
1776 /* Scan this alternative's specs for this operand; set WIN
1777 if the operand fits any letter in this alternative.
1778 Otherwise, clear BADOP if this operand could fit some
1779 letter after reloads, or set WINREG if this operand could
1780 fit after reloads provided the constraint allows some
1785 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1795 early_clobber_p
= true;
1799 /* Ignore rest of this alternative. */
1803 case '0': case '1': case '2': case '3': case '4':
1804 case '5': case '6': case '7': case '8': case '9':
1809 m
= strtoul (p
, &end
, 10);
1812 lra_assert (nop
> m
);
1814 this_alternative_matches
= m
;
1815 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1816 /* We are supposed to match a previous operand.
1817 If we do, we win if that one did. If we do
1818 not, count both of the operands as losers.
1819 (This is too conservative, since most of the
1820 time only a single reload insn will be needed
1821 to make the two operands win. As a result,
1822 this alternative may be rejected when it is
1823 actually desirable.) */
1825 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1826 *curr_id
->operand_loc
[m
], m_hregno
))
1828 /* We should reject matching of an early
1829 clobber operand if the matching operand is
1830 not dying in the insn. */
1831 if (! curr_static_id
->operand
[m
].early_clobber
1832 || operand_reg
[nop
] == NULL_RTX
1833 || (find_regno_note (curr_insn
, REG_DEAD
,
1835 || REGNO (op
) == REGNO (operand_reg
[m
])))
1840 /* If we are matching a non-offsettable
1841 address where an offsettable address was
1842 expected, then we must reject this
1843 combination, because we can't reload
1845 if (curr_alt_offmemok
[m
]
1846 && MEM_P (*curr_id
->operand_loc
[m
])
1847 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1852 /* Operands don't match. Both operands must
1853 allow a reload register, otherwise we
1854 cannot make them match. */
1855 if (curr_alt
[m
] == NO_REGS
)
1857 /* Retroactively mark the operand we had to
1858 match as a loser, if it wasn't already and
1859 it wasn't matched to a register constraint
1860 (e.g it might be matched by memory). */
1862 && (operand_reg
[m
] == NULL_RTX
1863 || hard_regno
[m
] < 0))
1867 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1868 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1871 /* Prefer matching earlyclobber alternative as
1872 it results in less hard regs required for
1873 the insn than a non-matching earlyclobber
1875 if (curr_static_id
->operand
[m
].early_clobber
)
1877 if (lra_dump_file
!= NULL
)
1880 " %d Matching earlyclobber alt:"
1885 /* Otherwise we prefer no matching
1886 alternatives because it gives more freedom
1888 else if (operand_reg
[nop
] == NULL_RTX
1889 || (find_regno_note (curr_insn
, REG_DEAD
,
1890 REGNO (operand_reg
[nop
]))
1893 if (lra_dump_file
!= NULL
)
1896 " %d Matching alt: reject+=2\n",
1901 /* If we have to reload this operand and some
1902 previous operand also had to match the same
1903 thing as this operand, we don't know how to do
1905 if (!match_p
|| !curr_alt_win
[m
])
1907 for (i
= 0; i
< nop
; i
++)
1908 if (curr_alt_matches
[i
] == m
)
1916 /* This can be fixed with reloads if the operand
1917 we are supposed to match can be fixed with
1920 this_alternative
= curr_alt
[m
];
1921 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1922 winreg
= this_alternative
!= NO_REGS
;
1928 || general_constant_p (op
)
1929 || spilled_pseudo_p (op
))
1935 cn
= lookup_constraint (p
);
1936 switch (get_constraint_type (cn
))
1939 cl
= reg_class_for_constraint (cn
);
1945 if (CONST_INT_P (op
)
1946 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1952 && satisfies_memory_constraint_p (op
, cn
))
1954 else if (spilled_pseudo_p (op
))
1957 /* If we didn't already win, we can reload constants
1958 via force_const_mem or put the pseudo value into
1959 memory, or make other memory by reloading the
1960 address like for 'o'. */
1961 if (CONST_POOL_OK_P (mode
, op
)
1962 || MEM_P (op
) || REG_P (op
))
1969 /* If we didn't already win, we can reload the address
1970 into a base register. */
1971 if (satisfies_address_constraint_p (op
, cn
))
1973 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1979 if (constraint_satisfied_p (op
, cn
))
1986 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1987 IOR_HARD_REG_SET (this_alternative_set
,
1988 reg_class_contents
[cl
]);
1991 this_costly_alternative
1992 = reg_class_subunion
[this_costly_alternative
][cl
];
1993 IOR_HARD_REG_SET (this_costly_alternative_set
,
1994 reg_class_contents
[cl
]);
1996 if (mode
== BLKmode
)
2001 if (hard_regno
[nop
] >= 0
2002 && in_hard_reg_set_p (this_alternative_set
,
2003 mode
, hard_regno
[nop
]))
2005 else if (hard_regno
[nop
] < 0
2006 && in_class_p (op
, this_alternative
, NULL
))
2011 if (c
!= ' ' && c
!= '\t')
2012 costly_p
= c
== '*';
2014 while ((p
+= len
), c
);
2016 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2017 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2018 /* Record which operands fit this alternative. */
2021 this_alternative_win
= true;
2022 if (operand_reg
[nop
] != NULL_RTX
)
2024 if (hard_regno
[nop
] >= 0)
2026 if (in_hard_reg_set_p (this_costly_alternative_set
,
2027 mode
, hard_regno
[nop
]))
2029 if (lra_dump_file
!= NULL
)
2030 fprintf (lra_dump_file
,
2031 " %d Costly set: reject++\n",
2038 /* Prefer won reg to spilled pseudo under other
2039 equal conditions for possibe inheritance. */
2042 if (lra_dump_file
!= NULL
)
2045 " %d Non pseudo reload: reject++\n",
2049 if (in_class_p (operand_reg
[nop
],
2050 this_costly_alternative
, NULL
))
2052 if (lra_dump_file
!= NULL
)
2055 " %d Non pseudo costly reload:"
2061 /* We simulate the behaviour of old reload here.
2062 Although scratches need hard registers and it
2063 might result in spilling other pseudos, no reload
2064 insns are generated for the scratches. So it
2065 might cost something but probably less than old
2066 reload pass believes. */
2069 if (lra_dump_file
!= NULL
)
2070 fprintf (lra_dump_file
,
2071 " %d Scratch win: reject+=2\n",
2078 this_alternative_match_win
= true;
2081 int const_to_mem
= 0;
2084 /* Never do output reload of stack pointer. It makes
2085 impossible to do elimination when SP is changed in
2087 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2088 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2091 /* If this alternative asks for a specific reg class, see if there
2092 is at least one allocatable register in that class. */
2094 = (this_alternative
== NO_REGS
2095 || (hard_reg_set_subset_p
2096 (reg_class_contents
[this_alternative
],
2097 lra_no_alloc_regs
)));
2099 /* For asms, verify that the class for this alternative is possible
2100 for the mode that is specified. */
2101 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2104 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2105 if (HARD_REGNO_MODE_OK (i
, mode
)
2106 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2109 if (i
== FIRST_PSEUDO_REGISTER
)
2113 /* If this operand accepts a register, and if the
2114 register class has at least one allocatable register,
2115 then this operand can be reloaded. */
2116 if (winreg
&& !no_regs_p
)
2121 if (lra_dump_file
!= NULL
)
2122 fprintf (lra_dump_file
,
2123 " alt=%d: Bad operand -- refuse\n",
2128 /* If not assigned pseudo has a class which a subset of
2129 required reg class, it is a less costly alternative
2130 as the pseudo still can get a hard reg of necessary
2132 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2133 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2134 && ira_class_subset_p
[this_alternative
][cl
])
2136 if (lra_dump_file
!= NULL
)
2139 " %d Super set class reg: reject-=3\n", nop
);
2143 this_alternative_offmemok
= offmemok
;
2144 if (this_costly_alternative
!= NO_REGS
)
2146 if (lra_dump_file
!= NULL
)
2147 fprintf (lra_dump_file
,
2148 " %d Costly loser: reject++\n", nop
);
2151 /* If the operand is dying, has a matching constraint,
2152 and satisfies constraints of the matched operand
2153 which failed to satisfy the own constraints, most probably
2154 the reload for this operand will be gone. */
2155 if (this_alternative_matches
>= 0
2156 && !curr_alt_win
[this_alternative_matches
]
2158 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2159 && (hard_regno
[nop
] >= 0
2160 ? in_hard_reg_set_p (this_alternative_set
,
2161 mode
, hard_regno
[nop
])
2162 : in_class_p (op
, this_alternative
, NULL
)))
2164 if (lra_dump_file
!= NULL
)
2167 " %d Dying matched operand reload: reject++\n",
2173 /* Strict_low_part requires to reload the register
2174 not the sub-register. In this case we should
2175 check that a final reload hard reg can hold the
2177 if (curr_static_id
->operand
[nop
].strict_low
2179 && hard_regno
[nop
] < 0
2180 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2181 && ira_class_hard_regs_num
[this_alternative
] > 0
2182 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2183 [this_alternative
][0],
2185 (*curr_id
->operand_loc
[nop
])))
2187 if (lra_dump_file
!= NULL
)
2190 " alt=%d: Strict low subreg reload -- refuse\n",
2196 if (operand_reg
[nop
] != NULL_RTX
2197 /* Output operands and matched input operands are
2198 not inherited. The following conditions do not
2199 exactly describe the previous statement but they
2200 are pretty close. */
2201 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2202 && (this_alternative_matches
< 0
2203 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2205 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2209 /* The value of reload_sum has sense only if we
2210 process insns in their order. It happens only on
2211 the first constraints sub-pass when we do most of
2213 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2214 reload_sum
+= last_reload
- bb_reload_num
;
2216 /* If this is a constant that is reloaded into the
2217 desired class by copying it to memory first, count
2218 that as another reload. This is consistent with
2219 other code and is required to avoid choosing another
2220 alternative when the constant is moved into memory.
2221 Note that the test here is precisely the same as in
2222 the code below that calls force_const_mem. */
2223 if (CONST_POOL_OK_P (mode
, op
)
2224 && ((targetm
.preferred_reload_class
2225 (op
, this_alternative
) == NO_REGS
)
2226 || no_input_reloads_p
))
2233 /* Alternative loses if it requires a type of reload not
2234 permitted for this insn. We can always reload
2235 objects with a REG_UNUSED note. */
2236 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2237 && no_output_reloads_p
2238 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2239 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2240 && no_input_reloads_p
&& ! const_to_mem
)
2241 || (this_alternative_matches
>= 0
2242 && (no_input_reloads_p
2243 || (no_output_reloads_p
2244 && (curr_static_id
->operand
2245 [this_alternative_matches
].type
!= OP_IN
)
2246 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2247 no_subreg_reg_operand
2248 [this_alternative_matches
])))))
2250 if (lra_dump_file
!= NULL
)
2253 " alt=%d: No input/otput reload -- refuse\n",
2258 /* Check strong discouragement of reload of non-constant
2259 into class THIS_ALTERNATIVE. */
2260 if (! CONSTANT_P (op
) && ! no_regs_p
2261 && (targetm
.preferred_reload_class
2262 (op
, this_alternative
) == NO_REGS
2263 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2264 && (targetm
.preferred_output_reload_class
2265 (op
, this_alternative
) == NO_REGS
))))
2267 if (lra_dump_file
!= NULL
)
2268 fprintf (lra_dump_file
,
2269 " %d Non-prefered reload: reject+=%d\n",
2270 nop
, LRA_MAX_REJECT
);
2271 reject
+= LRA_MAX_REJECT
;
2274 if (! (MEM_P (op
) && offmemok
)
2275 && ! (const_to_mem
&& constmemok
))
2277 /* We prefer to reload pseudos over reloading other
2278 things, since such reloads may be able to be
2279 eliminated later. So bump REJECT in other cases.
2280 Don't do this in the case where we are forcing a
2281 constant into memory and it will then win since
2282 we don't want to have a different alternative
2284 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2286 if (lra_dump_file
!= NULL
)
2289 " %d Non-pseudo reload: reject+=2\n",
2296 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2298 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2300 if (lra_dump_file
!= NULL
)
2303 " %d Small class reload: reject+=%d\n",
2304 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2305 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2309 /* We are trying to spill pseudo into memory. It is
2310 usually more costly than moving to a hard register
2311 although it might takes the same number of
2313 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2315 if (lra_dump_file
!= NULL
)
2318 " %d Spill pseudo into memory: reject+=3\n",
2321 if (VECTOR_MODE_P (mode
))
2323 /* Spilling vectors into memory is usually more
2324 costly as they contain big values. */
2325 if (lra_dump_file
!= NULL
)
2328 " %d Spill vector pseudo: reject+=2\n",
2334 #ifdef SECONDARY_MEMORY_NEEDED
2335 /* If reload requires moving value through secondary
2336 memory, it will need one more insn at least. */
2337 if (this_alternative
!= NO_REGS
2338 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2339 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2340 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2342 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2343 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2347 /* Input reloads can be inherited more often than output
2348 reloads can be removed, so penalize output
2350 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2352 if (lra_dump_file
!= NULL
)
2355 " %d Non input pseudo reload: reject++\n",
2361 if (early_clobber_p
&& ! scratch_p
)
2363 if (lra_dump_file
!= NULL
)
2364 fprintf (lra_dump_file
,
2365 " %d Early clobber: reject++\n", nop
);
2368 /* ??? We check early clobbers after processing all operands
2369 (see loop below) and there we update the costs more.
2370 Should we update the cost (may be approximately) here
2371 because of early clobber register reloads or it is a rare
2372 or non-important thing to be worth to do it. */
2373 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2374 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2376 if (lra_dump_file
!= NULL
)
2377 fprintf (lra_dump_file
,
2378 " alt=%d,overall=%d,losers=%d -- refuse\n",
2379 nalt
, overall
, losers
);
2383 curr_alt
[nop
] = this_alternative
;
2384 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2385 curr_alt_win
[nop
] = this_alternative_win
;
2386 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2387 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2388 curr_alt_matches
[nop
] = this_alternative_matches
;
2390 if (this_alternative_matches
>= 0
2391 && !did_match
&& !this_alternative_win
)
2392 curr_alt_win
[this_alternative_matches
] = false;
2394 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2395 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2397 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2398 /* Prevent processing non-move insns. */
2399 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2400 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2401 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2402 && REG_P (no_subreg_reg_operand
[0])
2403 && REG_P (no_subreg_reg_operand
[1])
2404 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2405 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2406 || (! curr_alt_win
[0] && curr_alt_win
[1]
2407 && REG_P (no_subreg_reg_operand
[1])
2408 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2409 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2410 && REG_P (no_subreg_reg_operand
[0])
2411 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2412 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2413 no_subreg_reg_operand
[1])
2414 || (targetm
.preferred_reload_class
2415 (no_subreg_reg_operand
[1],
2416 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2417 /* If it is a result of recent elimination in move
2418 insn we can transform it into an add still by
2419 using this alternative. */
2420 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2422 /* We have a move insn and a new reload insn will be similar
2423 to the current insn. We should avoid such situation as it
2424 results in LRA cycling. */
2425 overall
+= LRA_MAX_REJECT
;
2428 curr_alt_dont_inherit_ops_num
= 0;
2429 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2431 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2432 HARD_REG_SET temp_set
;
2434 i
= early_clobbered_nops
[nop
];
2435 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2436 || hard_regno
[i
] < 0)
2438 lra_assert (operand_reg
[i
] != NULL_RTX
);
2439 clobbered_hard_regno
= hard_regno
[i
];
2440 CLEAR_HARD_REG_SET (temp_set
);
2441 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2442 first_conflict_j
= last_conflict_j
= -1;
2443 for (j
= 0; j
< n_operands
; j
++)
2445 /* We don't want process insides of match_operator and
2446 match_parallel because otherwise we would process
2447 their operands once again generating a wrong
2449 || curr_static_id
->operand
[j
].is_operator
)
2451 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2452 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2454 /* If we don't reload j-th operand, check conflicts. */
2455 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2456 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2458 if (first_conflict_j
< 0)
2459 first_conflict_j
= j
;
2460 last_conflict_j
= j
;
2462 if (last_conflict_j
< 0)
2464 /* If earlyclobber operand conflicts with another
2465 non-matching operand which is actually the same register
2466 as the earlyclobber operand, it is better to reload the
2467 another operand as an operand matching the earlyclobber
2468 operand can be also the same. */
2469 if (first_conflict_j
== last_conflict_j
2470 && operand_reg
[last_conflict_j
]
2471 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2472 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2474 curr_alt_win
[last_conflict_j
] = false;
2475 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2478 /* Early clobber was already reflected in REJECT. */
2479 lra_assert (reject
> 0);
2480 if (lra_dump_file
!= NULL
)
2483 " %d Conflict early clobber reload: reject--\n",
2486 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2490 /* We need to reload early clobbered register and the
2491 matched registers. */
2492 for (j
= 0; j
< n_operands
; j
++)
2493 if (curr_alt_matches
[j
] == i
)
2495 curr_alt_match_win
[j
] = false;
2497 overall
+= LRA_LOSER_COST_FACTOR
;
2499 if (! curr_alt_match_win
[i
])
2500 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2503 /* Remember pseudos used for match reloads are never
2505 lra_assert (curr_alt_matches
[i
] >= 0);
2506 curr_alt_win
[curr_alt_matches
[i
]] = false;
2508 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2510 /* Early clobber was already reflected in REJECT. */
2511 lra_assert (reject
> 0);
2512 if (lra_dump_file
!= NULL
)
2515 " %d Matched conflict early clobber reloads:"
2519 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2522 if (lra_dump_file
!= NULL
)
2523 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2524 nalt
, overall
, losers
, reload_nregs
);
2526 /* If this alternative can be made to work by reloading, and it
2527 needs less reloading than the others checked so far, record
2528 it as the chosen goal for reloading. */
2529 if ((best_losers
!= 0 && losers
== 0)
2530 || (((best_losers
== 0 && losers
== 0)
2531 || (best_losers
!= 0 && losers
!= 0))
2532 && (best_overall
> overall
2533 || (best_overall
== overall
2534 /* If the cost of the reloads is the same,
2535 prefer alternative which requires minimal
2536 number of reload regs. */
2537 && (reload_nregs
< best_reload_nregs
2538 || (reload_nregs
== best_reload_nregs
2539 && (best_reload_sum
< reload_sum
2540 || (best_reload_sum
== reload_sum
2541 && nalt
< goal_alt_number
))))))))
2543 for (nop
= 0; nop
< n_operands
; nop
++)
2545 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2546 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2547 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2548 goal_alt
[nop
] = curr_alt
[nop
];
2549 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2551 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2552 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2553 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2554 goal_alt_swapped
= curr_swapped
;
2555 best_overall
= overall
;
2556 best_losers
= losers
;
2557 best_reload_nregs
= reload_nregs
;
2558 best_reload_sum
= reload_sum
;
2559 goal_alt_number
= nalt
;
2562 /* Everything is satisfied. Do not process alternatives
2571 /* Make reload base reg from address AD. */
2573 base_to_reg (struct address_info
*ad
)
2577 rtx new_inner
= NULL_RTX
;
2578 rtx new_reg
= NULL_RTX
;
2580 rtx_insn
*last_insn
= get_last_insn();
2582 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2583 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2584 get_index_code (ad
));
2585 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2587 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2588 ad
->disp_term
== NULL
2589 ? gen_int_mode (0, ad
->mode
)
2591 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2593 insn
= emit_insn (gen_rtx_SET (ad
->mode
, new_reg
, *ad
->base_term
));
2594 code
= recog_memoized (insn
);
2597 delete_insns_since (last_insn
);
2604 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2606 base_plus_disp_to_reg (struct address_info
*ad
)
2611 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2612 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2613 get_index_code (ad
));
2614 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2616 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2620 /* Make reload of index part of address AD. Return the new
2623 index_part_to_reg (struct address_info
*ad
)
2627 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2628 INDEX_REG_CLASS
, "index term");
2629 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2630 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2634 /* Return true if we can add a displacement to address AD, even if that
2635 makes the address invalid. The fix-up code requires any new address
2636 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2638 can_add_disp_p (struct address_info
*ad
)
2640 return (!ad
->autoinc_p
2641 && ad
->segment
== NULL
2642 && ad
->base
== ad
->base_term
2643 && ad
->disp
== ad
->disp_term
);
2646 /* Make equiv substitution in address AD. Return true if a substitution
2649 equiv_address_substitution (struct address_info
*ad
)
2651 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2652 HOST_WIDE_INT disp
, scale
;
2655 base_term
= strip_subreg (ad
->base_term
);
2656 if (base_term
== NULL
)
2657 base_reg
= new_base_reg
= NULL_RTX
;
2660 base_reg
= *base_term
;
2661 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2663 index_term
= strip_subreg (ad
->index_term
);
2664 if (index_term
== NULL
)
2665 index_reg
= new_index_reg
= NULL_RTX
;
2668 index_reg
= *index_term
;
2669 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2671 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2675 if (lra_dump_file
!= NULL
)
2677 fprintf (lra_dump_file
, "Changing address in insn %d ",
2678 INSN_UID (curr_insn
));
2679 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2681 if (base_reg
!= new_base_reg
)
2683 if (REG_P (new_base_reg
))
2685 *base_term
= new_base_reg
;
2688 else if (GET_CODE (new_base_reg
) == PLUS
2689 && REG_P (XEXP (new_base_reg
, 0))
2690 && CONST_INT_P (XEXP (new_base_reg
, 1))
2691 && can_add_disp_p (ad
))
2693 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2694 *base_term
= XEXP (new_base_reg
, 0);
2697 if (ad
->base_term2
!= NULL
)
2698 *ad
->base_term2
= *ad
->base_term
;
2700 if (index_reg
!= new_index_reg
)
2702 if (REG_P (new_index_reg
))
2704 *index_term
= new_index_reg
;
2707 else if (GET_CODE (new_index_reg
) == PLUS
2708 && REG_P (XEXP (new_index_reg
, 0))
2709 && CONST_INT_P (XEXP (new_index_reg
, 1))
2710 && can_add_disp_p (ad
)
2711 && (scale
= get_index_scale (ad
)))
2713 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2714 *index_term
= XEXP (new_index_reg
, 0);
2720 if (ad
->disp
!= NULL
)
2721 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2724 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2725 update_address (ad
);
2729 if (lra_dump_file
!= NULL
)
2732 fprintf (lra_dump_file
, " -- no change\n");
2735 fprintf (lra_dump_file
, " on equiv ");
2736 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2737 fprintf (lra_dump_file
, "\n");
2743 /* Major function to make reloads for an address in operand NOP.
2744 The supported cases are:
2746 1) an address that existed before LRA started, at which point it
2747 must have been valid. These addresses are subject to elimination
2748 and may have become invalid due to the elimination offset being out
2751 2) an address created by forcing a constant to memory
2752 (force_const_to_mem). The initial form of these addresses might
2753 not be valid, and it is this function's job to make them valid.
2755 3) a frame address formed from a register and a (possibly zero)
2756 constant offset. As above, these addresses might not be valid and
2757 this function must make them so.
2759 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2760 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2761 address. Return true for any RTL change.
2763 The function is a helper function which does not produce all
2764 transformations which can be necessary. It does just basic steps.
2765 To do all necessary transformations use function
2768 process_address_1 (int nop
, rtx_insn
**before
, rtx_insn
**after
)
2770 struct address_info ad
;
2772 rtx op
= *curr_id
->operand_loc
[nop
];
2773 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2774 enum constraint_num cn
= lookup_constraint (constraint
);
2777 if (insn_extra_address_constraint (cn
))
2778 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2779 else if (MEM_P (op
))
2780 decompose_mem_address (&ad
, op
);
2781 else if (GET_CODE (op
) == SUBREG
2782 && MEM_P (SUBREG_REG (op
)))
2783 decompose_mem_address (&ad
, SUBREG_REG (op
));
2786 change_p
= equiv_address_substitution (&ad
);
2787 if (ad
.base_term
!= NULL
2788 && (process_addr_reg
2789 (ad
.base_term
, before
,
2791 && !(REG_P (*ad
.base_term
)
2792 && find_regno_note (curr_insn
, REG_DEAD
,
2793 REGNO (*ad
.base_term
)) != NULL_RTX
)
2795 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2796 get_index_code (&ad
)))))
2799 if (ad
.base_term2
!= NULL
)
2800 *ad
.base_term2
= *ad
.base_term
;
2802 if (ad
.index_term
!= NULL
2803 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2806 /* Target hooks sometimes don't treat extra-constraint addresses as
2807 legitimate address_operands, so handle them specially. */
2808 if (insn_extra_address_constraint (cn
)
2809 && satisfies_address_constraint_p (&ad
, cn
))
2812 /* There are three cases where the shape of *AD.INNER may now be invalid:
2814 1) the original address was valid, but either elimination or
2815 equiv_address_substitution was applied and that made
2816 the address invalid.
2818 2) the address is an invalid symbolic address created by
2821 3) the address is a frame address with an invalid offset.
2823 4) the address is a frame address with an invalid base.
2825 All these cases involve a non-autoinc address, so there is no
2826 point revalidating other types. */
2827 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2830 /* Any index existed before LRA started, so we can assume that the
2831 presence and shape of the index is valid. */
2832 push_to_sequence (*before
);
2833 lra_assert (ad
.disp
== ad
.disp_term
);
2834 if (ad
.base
== NULL
)
2836 if (ad
.index
== NULL
)
2839 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2841 rtx addr
= *ad
.inner
;
2843 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2847 rtx_insn
*last
= get_last_insn ();
2849 /* addr => lo_sum (new_base, addr), case (2) above. */
2850 insn
= emit_insn (gen_rtx_SET
2852 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2853 code
= recog_memoized (insn
);
2856 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2857 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2859 /* Try to put lo_sum into register. */
2860 insn
= emit_insn (gen_rtx_SET
2862 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2863 code
= recog_memoized (insn
);
2866 *ad
.inner
= new_reg
;
2867 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2877 delete_insns_since (last
);
2882 /* addr => new_base, case (2) above. */
2883 lra_emit_move (new_reg
, addr
);
2884 *ad
.inner
= new_reg
;
2889 /* index * scale + disp => new base + index * scale,
2891 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2892 GET_CODE (*ad
.index
));
2894 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2895 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2896 lra_emit_move (new_reg
, *ad
.disp
);
2897 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2898 new_reg
, *ad
.index
);
2901 else if (ad
.index
== NULL
)
2906 rtx_insn
*insns
, *last_insn
;
2907 /* Try to reload base into register only if the base is invalid
2908 for the address but with valid offset, case (4) above. */
2910 new_reg
= base_to_reg (&ad
);
2912 /* base + disp => new base, cases (1) and (3) above. */
2913 /* Another option would be to reload the displacement into an
2914 index register. However, postreload has code to optimize
2915 address reloads that have the same base and different
2916 displacements, so reloading into an index register would
2917 not necessarily be a win. */
2918 if (new_reg
== NULL_RTX
)
2919 new_reg
= base_plus_disp_to_reg (&ad
);
2920 insns
= get_insns ();
2921 last_insn
= get_last_insn ();
2922 /* If we generated at least two insns, try last insn source as
2923 an address. If we succeed, we generate one less insn. */
2924 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2925 && GET_CODE (SET_SRC (set
)) == PLUS
2926 && REG_P (XEXP (SET_SRC (set
), 0))
2927 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2929 *ad
.inner
= SET_SRC (set
);
2930 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2932 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2933 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2934 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2935 get_index_code (&ad
));
2936 regno
= REGNO (*ad
.base_term
);
2937 if (regno
>= FIRST_PSEUDO_REGISTER
2938 && cl
!= lra_get_allocno_class (regno
))
2939 lra_change_class (regno
, cl
, " Change to", true);
2940 new_reg
= SET_SRC (set
);
2941 delete_insns_since (PREV_INSN (last_insn
));
2946 *ad
.inner
= new_reg
;
2948 else if (ad
.disp_term
!= NULL
)
2950 /* base + scale * index + disp => new base + scale * index,
2952 new_reg
= base_plus_disp_to_reg (&ad
);
2953 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2954 new_reg
, *ad
.index
);
2956 else if (get_index_scale (&ad
) == 1)
2958 /* The last transformation to one reg will be made in
2959 curr_insn_transform function. */
2965 /* base + scale * index => base + new_reg,
2967 Index part of address may become invalid. For example, we
2968 changed pseudo on the equivalent memory and a subreg of the
2969 pseudo onto the memory of different mode for which the scale is
2971 new_reg
= index_part_to_reg (&ad
);
2972 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2973 *ad
.base_term
, new_reg
);
2975 *before
= get_insns ();
2980 /* Do address reloads until it is necessary. Use process_address_1 as
2981 a helper function. Return true for any RTL changes. */
2983 process_address (int nop
, rtx_insn
**before
, rtx_insn
**after
)
2987 while (process_address_1 (nop
, before
, after
))
2992 /* Emit insns to reload VALUE into a new register. VALUE is an
2993 auto-increment or auto-decrement RTX whose operand is a register or
2994 memory location; so reloading involves incrementing that location.
2995 IN is either identical to VALUE, or some cheaper place to reload
2996 value being incremented/decremented from.
2998 INC_AMOUNT is the number to increment or decrement by (always
2999 positive and ignored for POST_MODIFY/PRE_MODIFY).
3001 Return pseudo containing the result. */
3003 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3005 /* REG or MEM to be copied and incremented. */
3006 rtx incloc
= XEXP (value
, 0);
3007 /* Nonzero if increment after copying. */
3008 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3009 || GET_CODE (value
) == POST_MODIFY
);
3014 rtx real_in
= in
== value
? incloc
: in
;
3018 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3020 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3021 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3022 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3023 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3024 inc
= XEXP (XEXP (value
, 1), 1);
3028 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3029 inc_amount
= -inc_amount
;
3031 inc
= GEN_INT (inc_amount
);
3034 if (! post
&& REG_P (incloc
))
3037 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3040 if (real_in
!= result
)
3042 /* First copy the location to the result register. */
3043 lra_assert (REG_P (result
));
3044 emit_insn (gen_move_insn (result
, real_in
));
3047 /* We suppose that there are insns to add/sub with the constant
3048 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3049 old reload worked with this assumption. If the assumption
3050 becomes wrong, we should use approach in function
3051 base_plus_disp_to_reg. */
3054 /* See if we can directly increment INCLOC. */
3055 last
= get_last_insn ();
3056 add_insn
= emit_insn (plus_p
3057 ? gen_add2_insn (incloc
, inc
)
3058 : gen_sub2_insn (incloc
, inc
));
3060 code
= recog_memoized (add_insn
);
3063 if (! post
&& result
!= incloc
)
3064 emit_insn (gen_move_insn (result
, incloc
));
3067 delete_insns_since (last
);
3070 /* If couldn't do the increment directly, must increment in RESULT.
3071 The way we do this depends on whether this is pre- or
3072 post-increment. For pre-increment, copy INCLOC to the reload
3073 register, increment it there, then save back. */
3076 if (real_in
!= result
)
3077 emit_insn (gen_move_insn (result
, real_in
));
3079 emit_insn (gen_add2_insn (result
, inc
));
3081 emit_insn (gen_sub2_insn (result
, inc
));
3082 if (result
!= incloc
)
3083 emit_insn (gen_move_insn (incloc
, result
));
3089 Because this might be a jump insn or a compare, and because
3090 RESULT may not be available after the insn in an input
3091 reload, we must do the incrementing before the insn being
3094 We have already copied IN to RESULT. Increment the copy in
3095 RESULT, save that back, then decrement RESULT so it has
3096 the original value. */
3098 emit_insn (gen_add2_insn (result
, inc
));
3100 emit_insn (gen_sub2_insn (result
, inc
));
3101 emit_insn (gen_move_insn (incloc
, result
));
3102 /* Restore non-modified value for the result. We prefer this
3103 way because it does not require an additional hard
3107 if (CONST_INT_P (inc
))
3108 emit_insn (gen_add2_insn (result
,
3109 gen_int_mode (-INTVAL (inc
),
3110 GET_MODE (result
))));
3112 emit_insn (gen_sub2_insn (result
, inc
));
3115 emit_insn (gen_add2_insn (result
, inc
));
3120 /* Return true if the current move insn does not need processing as we
3121 already know that it satisfies its constraints. */
3123 simple_move_p (void)
3126 enum reg_class dclass
, sclass
;
3128 lra_assert (curr_insn_set
!= NULL_RTX
);
3129 dest
= SET_DEST (curr_insn_set
);
3130 src
= SET_SRC (curr_insn_set
);
3131 return ((dclass
= get_op_class (dest
)) != NO_REGS
3132 && (sclass
= get_op_class (src
)) != NO_REGS
3133 /* The backend guarantees that register moves of cost 2
3134 never need reloads. */
3135 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3138 /* Swap operands NOP and NOP + 1. */
3140 swap_operands (int nop
)
3142 machine_mode mode
= curr_operand_mode
[nop
];
3143 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3144 curr_operand_mode
[nop
+ 1] = mode
;
3145 rtx x
= *curr_id
->operand_loc
[nop
];
3146 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3147 *curr_id
->operand_loc
[nop
+ 1] = x
;
3148 /* Swap the duplicates too. */
3149 lra_update_dup (curr_id
, nop
);
3150 lra_update_dup (curr_id
, nop
+ 1);
3153 /* Main entry point of the constraint code: search the body of the
3154 current insn to choose the best alternative. It is mimicking insn
3155 alternative cost calculation model of former reload pass. That is
3156 because machine descriptions were written to use this model. This
3157 model can be changed in future. Make commutative operand exchange
3160 Return true if some RTL changes happened during function call. */
3162 curr_insn_transform (void)
3168 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3169 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3170 rtx_insn
*before
, *after
;
3172 /* Flag that the insn has been changed through a transformation. */
3175 #ifdef SECONDARY_MEMORY_NEEDED
3178 int max_regno_before
;
3179 int reused_alternative_num
;
3181 curr_insn_set
= single_set (curr_insn
);
3182 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3185 no_input_reloads_p
= no_output_reloads_p
= false;
3186 goal_alt_number
= -1;
3187 change_p
= sec_mem_p
= false;
3188 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3189 reloads; neither are insns that SET cc0. Insns that use CC0 are
3190 not allowed to have any input reloads. */
3191 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3192 no_output_reloads_p
= true;
3195 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3196 no_input_reloads_p
= true;
3197 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3198 no_output_reloads_p
= true;
3201 n_operands
= curr_static_id
->n_operands
;
3202 n_alternatives
= curr_static_id
->n_alternatives
;
3204 /* Just return "no reloads" if insn has no operands with
3206 if (n_operands
== 0 || n_alternatives
== 0)
3209 max_regno_before
= max_reg_num ();
3211 for (i
= 0; i
< n_operands
; i
++)
3213 goal_alt_matched
[i
][0] = -1;
3214 goal_alt_matches
[i
] = -1;
3217 commutative
= curr_static_id
->commutative
;
3219 /* Now see what we need for pseudos that didn't get hard regs or got
3220 the wrong kind of hard reg. For this, we must consider all the
3221 operands together against the register constraints. */
3223 best_losers
= best_overall
= INT_MAX
;
3224 best_reload_sum
= 0;
3226 curr_swapped
= false;
3227 goal_alt_swapped
= false;
3229 /* Make equivalence substitution and memory subreg elimination
3230 before address processing because an address legitimacy can
3231 depend on memory mode. */
3232 for (i
= 0; i
< n_operands
; i
++)
3234 rtx op
= *curr_id
->operand_loc
[i
];
3235 rtx subst
, old
= op
;
3236 bool op_change_p
= false;
3238 if (GET_CODE (old
) == SUBREG
)
3239 old
= SUBREG_REG (old
);
3240 subst
= get_equiv_with_elimination (old
, curr_insn
);
3243 subst
= copy_rtx (subst
);
3244 lra_assert (REG_P (old
));
3245 if (GET_CODE (op
) == SUBREG
)
3246 SUBREG_REG (op
) = subst
;
3248 *curr_id
->operand_loc
[i
] = subst
;
3249 if (lra_dump_file
!= NULL
)
3251 fprintf (lra_dump_file
,
3252 "Changing pseudo %d in operand %i of insn %u on equiv ",
3253 REGNO (old
), i
, INSN_UID (curr_insn
));
3254 dump_value_slim (lra_dump_file
, subst
, 1);
3255 fprintf (lra_dump_file
, "\n");
3257 op_change_p
= change_p
= true;
3259 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3262 lra_update_dup (curr_id
, i
);
3266 /* Reload address registers and displacements. We do it before
3267 finding an alternative because of memory constraints. */
3268 before
= after
= NULL
;
3269 for (i
= 0; i
< n_operands
; i
++)
3270 if (! curr_static_id
->operand
[i
].is_operator
3271 && process_address (i
, &before
, &after
))
3274 lra_update_dup (curr_id
, i
);
3278 /* If we've changed the instruction then any alternative that
3279 we chose previously may no longer be valid. */
3280 lra_set_used_insn_alternative (curr_insn
, -1);
3282 if (curr_insn_set
!= NULL_RTX
3283 && check_and_process_move (&change_p
, &sec_mem_p
))
3288 reused_alternative_num
= curr_id
->used_insn_alternative
;
3289 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3290 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3291 reused_alternative_num
, INSN_UID (curr_insn
));
3293 if (process_alt_operands (reused_alternative_num
))
3296 /* If insn is commutative (it's safe to exchange a certain pair of
3297 operands) then we need to try each alternative twice, the second
3298 time matching those two operands as if we had exchanged them. To
3299 do this, really exchange them in operands.
3301 If we have just tried the alternatives the second time, return
3302 operands to normal and drop through. */
3304 if (reused_alternative_num
< 0 && commutative
>= 0)
3306 curr_swapped
= !curr_swapped
;
3309 swap_operands (commutative
);
3313 swap_operands (commutative
);
3316 if (! alt_p
&& ! sec_mem_p
)
3318 /* No alternative works with reloads?? */
3319 if (INSN_CODE (curr_insn
) >= 0)
3320 fatal_insn ("unable to generate reloads for:", curr_insn
);
3321 error_for_asm (curr_insn
,
3322 "inconsistent operand constraints in an %<asm%>");
3323 /* Avoid further trouble with this insn. */
3324 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3325 lra_invalidate_insn_data (curr_insn
);
3329 /* If the best alternative is with operands 1 and 2 swapped, swap
3330 them. Update the operand numbers of any reloads already
3333 if (goal_alt_swapped
)
3335 if (lra_dump_file
!= NULL
)
3336 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3337 INSN_UID (curr_insn
));
3339 /* Swap the duplicates too. */
3340 swap_operands (commutative
);
3344 #ifdef SECONDARY_MEMORY_NEEDED
3345 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3346 too conservatively. So we use the secondary memory only if there
3347 is no any alternative without reloads. */
3348 use_sec_mem_p
= false;
3350 use_sec_mem_p
= true;
3353 for (i
= 0; i
< n_operands
; i
++)
3354 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3356 use_sec_mem_p
= i
< n_operands
;
3361 rtx new_reg
, src
, dest
, rld
;
3362 machine_mode sec_mode
, rld_mode
;
3364 lra_assert (sec_mem_p
);
3365 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3366 && curr_static_id
->operand
[1].type
== OP_IN
);
3367 dest
= *curr_id
->operand_loc
[0];
3368 src
= *curr_id
->operand_loc
[1];
3369 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3371 rld_mode
= GET_MODE (rld
);
3372 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3373 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3375 sec_mode
= rld_mode
;
3377 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3378 NO_REGS
, "secondary");
3379 /* If the mode is changed, it should be wider. */
3380 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3381 if (sec_mode
!= rld_mode
)
3383 /* If the target says specifically to use another mode for
3384 secondary memory moves we can not reuse the original
3386 after
= emit_spill_move (false, new_reg
, dest
);
3387 lra_process_new_insns (curr_insn
, NULL
, after
,
3388 "Inserting the sec. move");
3389 /* We may have non null BEFORE here (e.g. after address
3391 push_to_sequence (before
);
3392 before
= emit_spill_move (true, new_reg
, src
);
3394 before
= get_insns ();
3396 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3397 lra_set_insn_deleted (curr_insn
);
3399 else if (dest
== rld
)
3401 *curr_id
->operand_loc
[0] = new_reg
;
3402 after
= emit_spill_move (false, new_reg
, dest
);
3403 lra_process_new_insns (curr_insn
, NULL
, after
,
3404 "Inserting the sec. move");
3408 *curr_id
->operand_loc
[1] = new_reg
;
3409 /* See comments above. */
3410 push_to_sequence (before
);
3411 before
= emit_spill_move (true, new_reg
, src
);
3413 before
= get_insns ();
3415 lra_process_new_insns (curr_insn
, before
, NULL
,
3416 "Inserting the sec. move");
3418 lra_update_insn_regno_info (curr_insn
);
3423 lra_assert (goal_alt_number
>= 0);
3424 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3426 if (lra_dump_file
!= NULL
)
3430 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3431 goal_alt_number
, INSN_UID (curr_insn
));
3432 for (i
= 0; i
< n_operands
; i
++)
3434 p
= (curr_static_id
->operand_alternative
3435 [goal_alt_number
* n_operands
+ i
].constraint
);
3438 fprintf (lra_dump_file
, " (%d) ", i
);
3439 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3440 fputc (*p
, lra_dump_file
);
3442 if (INSN_CODE (curr_insn
) >= 0
3443 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3444 fprintf (lra_dump_file
, " {%s}", p
);
3445 if (curr_id
->sp_offset
!= 0)
3446 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3447 curr_id
->sp_offset
);
3448 fprintf (lra_dump_file
, "\n");
3451 /* Right now, for any pair of operands I and J that are required to
3452 match, with J < I, goal_alt_matches[I] is J. Add I to
3453 goal_alt_matched[J]. */
3455 for (i
= 0; i
< n_operands
; i
++)
3456 if ((j
= goal_alt_matches
[i
]) >= 0)
3458 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3460 /* We allow matching one output operand and several input
3463 || (curr_static_id
->operand
[j
].type
== OP_OUT
3464 && curr_static_id
->operand
[i
].type
== OP_IN
3465 && (curr_static_id
->operand
3466 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3467 goal_alt_matched
[j
][k
] = i
;
3468 goal_alt_matched
[j
][k
+ 1] = -1;
3471 for (i
= 0; i
< n_operands
; i
++)
3472 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3474 /* Any constants that aren't allowed and can't be reloaded into
3475 registers are here changed into memory references. */
3476 for (i
= 0; i
< n_operands
; i
++)
3477 if (goal_alt_win
[i
])
3480 enum reg_class new_class
;
3481 rtx reg
= *curr_id
->operand_loc
[i
];
3483 if (GET_CODE (reg
) == SUBREG
)
3484 reg
= SUBREG_REG (reg
);
3486 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3488 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3490 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3493 lra_change_class (regno
, new_class
, " Change to", true);
3499 const char *constraint
;
3501 rtx op
= *curr_id
->operand_loc
[i
];
3502 rtx subreg
= NULL_RTX
;
3503 machine_mode mode
= curr_operand_mode
[i
];
3505 if (GET_CODE (op
) == SUBREG
)
3508 op
= SUBREG_REG (op
);
3509 mode
= GET_MODE (op
);
3512 if (CONST_POOL_OK_P (mode
, op
)
3513 && ((targetm
.preferred_reload_class
3514 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3515 || no_input_reloads_p
))
3517 rtx tem
= force_const_mem (mode
, op
);
3520 if (subreg
!= NULL_RTX
)
3521 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3523 *curr_id
->operand_loc
[i
] = tem
;
3524 lra_update_dup (curr_id
, i
);
3525 process_address (i
, &before
, &after
);
3527 /* If the alternative accepts constant pool refs directly
3528 there will be no reload needed at all. */
3529 if (subreg
!= NULL_RTX
)
3531 /* Skip alternatives before the one requested. */
3532 constraint
= (curr_static_id
->operand_alternative
3533 [goal_alt_number
* n_operands
+ i
].constraint
);
3535 (c
= *constraint
) && c
!= ',' && c
!= '#';
3536 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3538 enum constraint_num cn
= lookup_constraint (constraint
);
3539 if (insn_extra_memory_constraint (cn
)
3540 && satisfies_memory_constraint_p (tem
, cn
))
3543 if (c
== '\0' || c
== ',' || c
== '#')
3546 goal_alt_win
[i
] = true;
3550 for (i
= 0; i
< n_operands
; i
++)
3553 bool optional_p
= false;
3555 rtx op
= *curr_id
->operand_loc
[i
];
3557 if (goal_alt_win
[i
])
3559 if (goal_alt
[i
] == NO_REGS
3561 /* When we assign NO_REGS it means that we will not
3562 assign a hard register to the scratch pseudo by
3563 assigment pass and the scratch pseudo will be
3564 spilled. Spilled scratch pseudos are transformed
3565 back to scratches at the LRA end. */
3566 && lra_former_scratch_operand_p (curr_insn
, i
))
3568 int regno
= REGNO (op
);
3569 lra_change_class (regno
, NO_REGS
, " Change to", true);
3570 if (lra_get_regno_hard_regno (regno
) >= 0)
3571 /* We don't have to mark all insn affected by the
3572 spilled pseudo as there is only one such insn, the
3574 reg_renumber
[regno
] = -1;
3576 /* We can do an optional reload. If the pseudo got a hard
3577 reg, we might improve the code through inheritance. If
3578 it does not get a hard register we coalesce memory/memory
3579 moves later. Ignore move insns to avoid cycling. */
3581 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3582 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3583 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3584 && regno
< new_regno_start
3585 && ! lra_former_scratch_p (regno
)
3586 && reg_renumber
[regno
] < 0
3587 && (curr_insn_set
== NULL_RTX
3588 || !((REG_P (SET_SRC (curr_insn_set
))
3589 || MEM_P (SET_SRC (curr_insn_set
))
3590 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3591 && (REG_P (SET_DEST (curr_insn_set
))
3592 || MEM_P (SET_DEST (curr_insn_set
))
3593 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3599 /* Operands that match previous ones have already been handled. */
3600 if (goal_alt_matches
[i
] >= 0)
3603 /* We should not have an operand with a non-offsettable address
3604 appearing where an offsettable address will do. It also may
3605 be a case when the address should be special in other words
3606 not a general one (e.g. it needs no index reg). */
3607 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3609 enum reg_class rclass
;
3610 rtx
*loc
= &XEXP (op
, 0);
3611 enum rtx_code code
= GET_CODE (*loc
);
3613 push_to_sequence (before
);
3614 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3616 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3617 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3618 /* This value does not matter for MODIFY. */
3619 GET_MODE_SIZE (GET_MODE (op
)));
3620 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3621 "offsetable address", &new_reg
))
3622 lra_emit_move (new_reg
, *loc
);
3623 before
= get_insns ();
3626 lra_update_dup (curr_id
, i
);
3628 else if (goal_alt_matched
[i
][0] == -1)
3632 int hard_regno
, byte
;
3633 enum op_type type
= curr_static_id
->operand
[i
].type
;
3635 loc
= curr_id
->operand_loc
[i
];
3636 mode
= curr_operand_mode
[i
];
3637 if (GET_CODE (*loc
) == SUBREG
)
3639 reg
= SUBREG_REG (*loc
);
3640 byte
= SUBREG_BYTE (*loc
);
3642 /* Strict_low_part requires reload the register not
3643 the sub-register. */
3644 && (curr_static_id
->operand
[i
].strict_low
3645 || (GET_MODE_SIZE (mode
)
3646 <= GET_MODE_SIZE (GET_MODE (reg
))
3648 = get_try_hard_regno (REGNO (reg
))) >= 0
3649 && (simplify_subreg_regno
3651 GET_MODE (reg
), byte
, mode
) < 0)
3652 && (goal_alt
[i
] == NO_REGS
3653 || (simplify_subreg_regno
3654 (ira_class_hard_regs
[goal_alt
[i
]][0],
3655 GET_MODE (reg
), byte
, mode
) >= 0)))))
3657 loc
= &SUBREG_REG (*loc
);
3658 mode
= GET_MODE (*loc
);
3662 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3663 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3666 push_to_sequence (before
);
3667 lra_emit_move (new_reg
, old
);
3668 before
= get_insns ();
3673 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3676 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3678 after
= get_insns ();
3682 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3683 if (goal_alt_dont_inherit_ops
[j
] == i
)
3685 lra_set_regno_unique_value (REGNO (new_reg
));
3688 lra_update_dup (curr_id
, i
);
3690 else if (curr_static_id
->operand
[i
].type
== OP_IN
3691 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3694 /* generate reloads for input and matched outputs. */
3695 match_inputs
[0] = i
;
3696 match_inputs
[1] = -1;
3697 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3698 goal_alt
[i
], &before
, &after
);
3700 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3701 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3703 /* Generate reloads for output and matched inputs. */
3704 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3705 else if (curr_static_id
->operand
[i
].type
== OP_IN
3706 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3709 /* Generate reloads for matched inputs. */
3710 match_inputs
[0] = i
;
3711 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3712 match_inputs
[j
+ 1] = k
;
3713 match_inputs
[j
+ 1] = -1;
3714 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3717 /* We must generate code in any case when function
3718 process_alt_operands decides that it is possible. */
3722 lra_assert (REG_P (op
));
3724 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3725 if (GET_CODE (op
) == SUBREG
)
3726 op
= SUBREG_REG (op
);
3727 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3728 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3729 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3730 if (lra_dump_file
!= NULL
)
3731 fprintf (lra_dump_file
,
3732 " Making reload reg %d for reg %d optional\n",
3736 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3737 || max_regno_before
!= max_reg_num ())
3741 lra_update_operator_dups (curr_id
);
3742 /* Something changes -- process the insn. */
3743 lra_update_insn_regno_info (curr_insn
);
3745 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3749 /* Return true if X is in LIST. */
3751 in_list_p (rtx x
, rtx list
)
3753 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3754 if (XEXP (list
, 0) == x
)
3759 /* Return true if X contains an allocatable hard register (if
3760 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3762 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3768 code
= GET_CODE (x
);
3771 int regno
= REGNO (x
);
3772 HARD_REG_SET alloc_regs
;
3776 if (regno
>= FIRST_PSEUDO_REGISTER
)
3777 regno
= lra_get_regno_hard_regno (regno
);
3780 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3781 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3785 if (regno
< FIRST_PSEUDO_REGISTER
)
3789 return lra_get_regno_hard_regno (regno
) < 0;
3792 fmt
= GET_RTX_FORMAT (code
);
3793 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3797 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3800 else if (fmt
[i
] == 'E')
3802 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3803 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3810 /* Return true if X contains a symbol reg. */
3812 contains_symbol_ref_p (rtx x
)
3818 code
= GET_CODE (x
);
3819 if (code
== SYMBOL_REF
)
3821 fmt
= GET_RTX_FORMAT (code
);
3822 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3826 if (contains_symbol_ref_p (XEXP (x
, i
)))
3829 else if (fmt
[i
] == 'E')
3831 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3832 if (contains_symbol_ref_p (XVECEXP (x
, i
, j
)))
3839 /* Process all regs in location *LOC and change them on equivalent
3840 substitution. Return true if any change was done. */
3842 loc_equivalence_change_p (rtx
*loc
)
3844 rtx subst
, reg
, x
= *loc
;
3845 bool result
= false;
3846 enum rtx_code code
= GET_CODE (x
);
3852 reg
= SUBREG_REG (x
);
3853 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3854 && GET_MODE (subst
) == VOIDmode
)
3856 /* We cannot reload debug location. Simplify subreg here
3857 while we know the inner mode. */
3858 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3859 GET_MODE (reg
), SUBREG_BYTE (x
));
3863 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3869 /* Scan all the operand sub-expressions. */
3870 fmt
= GET_RTX_FORMAT (code
);
3871 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3874 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3875 else if (fmt
[i
] == 'E')
3876 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3878 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3883 /* Similar to loc_equivalence_change_p, but for use as
3884 simplify_replace_fn_rtx callback. DATA is insn for which the
3885 elimination is done. If it null we don't do the elimination. */
3887 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3892 rtx subst
= (data
== NULL
3893 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
3900 /* Maximum number of generated reload insns per an insn. It is for
3901 preventing this pass cycling in a bug case. */
3902 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3904 /* The current iteration number of this LRA pass. */
3905 int lra_constraint_iter
;
3907 /* True if we substituted equiv which needs checking register
3908 allocation correctness because the equivalent value contains
3909 allocatable hard registers or when we restore multi-register
3911 bool lra_risky_transformations_p
;
3913 /* Return true if REGNO is referenced in more than one block. */
3915 multi_block_pseudo_p (int regno
)
3917 basic_block bb
= NULL
;
3921 if (regno
< FIRST_PSEUDO_REGISTER
)
3924 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3926 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3927 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3932 /* Return true if LIST contains a deleted insn. */
3934 contains_deleted_insn_p (rtx_insn_list
*list
)
3936 for (; list
!= NULL_RTX
; list
= list
->next ())
3937 if (NOTE_P (list
->insn ())
3938 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
3943 /* Return true if X contains a pseudo dying in INSN. */
3945 dead_pseudo_p (rtx x
, rtx insn
)
3952 return (insn
!= NULL_RTX
3953 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3954 code
= GET_CODE (x
);
3955 fmt
= GET_RTX_FORMAT (code
);
3956 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3960 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3963 else if (fmt
[i
] == 'E')
3965 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3966 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3973 /* Return true if INSN contains a dying pseudo in INSN right hand
3976 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
3978 rtx set
= single_set (insn
);
3980 gcc_assert (set
!= NULL
);
3981 return dead_pseudo_p (SET_SRC (set
), insn
);
3984 /* Return true if any init insn of REGNO contains a dying pseudo in
3985 insn right hand side. */
3987 init_insn_rhs_dead_pseudo_p (int regno
)
3989 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
3993 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
3994 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
3999 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4000 reverse only if we have one init insn with given REGNO as a
4003 reverse_equiv_p (int regno
)
4005 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4010 if (! INSN_P (insns
->insn ())
4011 || insns
->next () != NULL
)
4013 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4015 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4018 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4019 call this function only for non-reverse equivalence. */
4021 contains_reloaded_insn_p (int regno
)
4024 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4026 for (; list
!= NULL
; list
= list
->next ())
4027 if ((set
= single_set (list
->insn ())) == NULL_RTX
4028 || ! REG_P (SET_DEST (set
))
4029 || (int) REGNO (SET_DEST (set
)) != regno
)
4034 /* Entry function of LRA constraint pass. Return true if the
4035 constraint pass did change the code. */
4037 lra_constraints (bool first_p
)
4040 int i
, hard_regno
, new_insns_num
;
4041 unsigned int min_len
, new_min_len
, uid
;
4042 rtx set
, x
, reg
, dest_reg
;
4043 basic_block last_bb
;
4044 bitmap_head equiv_insn_bitmap
;
4047 lra_constraint_iter
++;
4048 if (lra_dump_file
!= NULL
)
4049 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4050 lra_constraint_iter
);
4052 if (pic_offset_table_rtx
4053 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4054 lra_risky_transformations_p
= true;
4056 lra_risky_transformations_p
= false;
4057 new_insn_uid_start
= get_max_uid ();
4058 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4059 /* Mark used hard regs for target stack size calulations. */
4060 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4061 if (lra_reg_info
[i
].nrefs
!= 0
4062 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4066 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4067 for (j
= 0; j
< nregs
; j
++)
4068 df_set_regs_ever_live (hard_regno
+ j
, true);
4070 /* Do elimination before the equivalence processing as we can spill
4071 some pseudos during elimination. */
4072 lra_eliminate (false, first_p
);
4073 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4074 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4075 if (lra_reg_info
[i
].nrefs
!= 0)
4077 ira_reg_equiv
[i
].profitable_p
= true;
4078 reg
= regno_reg_rtx
[i
];
4079 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4081 bool pseudo_p
= contains_reg_p (x
, false, false);
4083 /* After RTL transformation, we can not guarantee that
4084 pseudo in the substitution was not reloaded which might
4085 make equivalence invalid. For example, in reverse
4092 the memory address register was reloaded before the 2nd
4094 if ((! first_p
&& pseudo_p
)
4095 /* We don't use DF for compilation speed sake. So it
4096 is problematic to update live info when we use an
4097 equivalence containing pseudos in more than one
4099 || (pseudo_p
&& multi_block_pseudo_p (i
))
4100 /* If an init insn was deleted for some reason, cancel
4101 the equiv. We could update the equiv insns after
4102 transformations including an equiv insn deletion
4103 but it is not worthy as such cases are extremely
4105 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4106 /* If it is not a reverse equivalence, we check that a
4107 pseudo in rhs of the init insn is not dying in the
4108 insn. Otherwise, the live info at the beginning of
4109 the corresponding BB might be wrong after we
4110 removed the insn. When the equiv can be a
4111 constant, the right hand side of the init insn can
4113 || (! reverse_equiv_p (i
)
4114 && (init_insn_rhs_dead_pseudo_p (i
)
4115 /* If we reloaded the pseudo in an equivalence
4116 init insn, we can not remove the equiv init
4117 insns and the init insns might write into
4118 const memory in this case. */
4119 || contains_reloaded_insn_p (i
)))
4120 /* Prevent access beyond equivalent memory for
4121 paradoxical subregs. */
4123 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4124 > GET_MODE_SIZE (GET_MODE (x
))))
4125 || (pic_offset_table_rtx
4126 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4127 && (targetm
.preferred_reload_class
4128 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4129 || contains_symbol_ref_p (x
))))
4130 ira_reg_equiv
[i
].defined_p
= false;
4131 if (contains_reg_p (x
, false, true))
4132 ira_reg_equiv
[i
].profitable_p
= false;
4133 if (get_equiv (reg
) != reg
)
4134 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4137 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4139 /* We should add all insns containing pseudos which should be
4140 substituted by their equivalences. */
4141 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4142 lra_push_insn_by_uid (uid
);
4143 min_len
= lra_insn_stack_length ();
4147 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4149 curr_insn
= lra_pop_insn ();
4151 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4152 if (curr_bb
!= last_bb
)
4155 bb_reload_num
= lra_curr_reload_num
;
4157 if (min_len
> new_min_len
)
4159 min_len
= new_min_len
;
4162 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4164 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4165 MAX_RELOAD_INSNS_NUMBER
);
4167 if (DEBUG_INSN_P (curr_insn
))
4169 /* We need to check equivalence in debug insn and change
4170 pseudo to the equivalent value if necessary. */
4171 curr_id
= lra_get_insn_recog_data (curr_insn
);
4172 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4174 rtx old
= *curr_id
->operand_loc
[0];
4175 *curr_id
->operand_loc
[0]
4176 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4177 loc_equivalence_callback
, curr_insn
);
4178 if (old
!= *curr_id
->operand_loc
[0])
4180 lra_update_insn_regno_info (curr_insn
);
4185 else if (INSN_P (curr_insn
))
4187 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4189 dest_reg
= SET_DEST (set
);
4190 /* The equivalence pseudo could be set up as SUBREG in a
4191 case when it is a call restore insn in a mode
4192 different from the pseudo mode. */
4193 if (GET_CODE (dest_reg
) == SUBREG
)
4194 dest_reg
= SUBREG_REG (dest_reg
);
4195 if ((REG_P (dest_reg
)
4196 && (x
= get_equiv (dest_reg
)) != dest_reg
4197 /* Remove insns which set up a pseudo whose value
4198 can not be changed. Such insns might be not in
4199 init_insns because we don't update equiv data
4200 during insn transformations.
4202 As an example, let suppose that a pseudo got
4203 hard register and on the 1st pass was not
4204 changed to equivalent constant. We generate an
4205 additional insn setting up the pseudo because of
4206 secondary memory movement. Then the pseudo is
4207 spilled and we use the equiv constant. In this
4208 case we should remove the additional insn and
4209 this insn is not init_insns list. */
4210 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4211 /* Check that this is actually an insn setting
4212 up the equivalence. */
4213 || in_list_p (curr_insn
,
4215 [REGNO (dest_reg
)].init_insns
)))
4216 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4217 && in_list_p (curr_insn
,
4219 [REGNO (SET_SRC (set
))].init_insns
)))
4221 /* This is equiv init insn of pseudo which did not get a
4222 hard register -- remove the insn. */
4223 if (lra_dump_file
!= NULL
)
4225 fprintf (lra_dump_file
,
4226 " Removing equiv init insn %i (freq=%d)\n",
4227 INSN_UID (curr_insn
),
4228 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4229 dump_insn_slim (lra_dump_file
, curr_insn
);
4231 if (contains_reg_p (x
, true, false))
4232 lra_risky_transformations_p
= true;
4233 lra_set_insn_deleted (curr_insn
);
4237 curr_id
= lra_get_insn_recog_data (curr_insn
);
4238 curr_static_id
= curr_id
->insn_static_data
;
4239 init_curr_insn_input_reloads ();
4240 init_curr_operand_mode ();
4241 if (curr_insn_transform ())
4243 /* Check non-transformed insns too for equiv change as USE
4244 or CLOBBER don't need reloads but can contain pseudos
4245 being changed on their equivalences. */
4246 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4247 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4249 lra_update_insn_regno_info (curr_insn
);
4254 bitmap_clear (&equiv_insn_bitmap
);
4255 /* If we used a new hard regno, changed_p should be true because the
4256 hard reg is assigned to a new pseudo. */
4257 #ifdef ENABLE_CHECKING
4260 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4261 if (lra_reg_info
[i
].nrefs
!= 0
4262 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4264 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4266 for (j
= 0; j
< nregs
; j
++)
4267 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4274 /* Initiate the LRA constraint pass. It is done once per
4277 lra_constraints_init (void)
4281 /* Finalize the LRA constraint pass. It is done once per
4284 lra_constraints_finish (void)
4290 /* This page contains code to do inheritance/split
4293 /* Number of reloads passed so far in current EBB. */
4294 static int reloads_num
;
4296 /* Number of calls passed so far in current EBB. */
4297 static int calls_num
;
4299 /* Current reload pseudo check for validity of elements in
4301 static int curr_usage_insns_check
;
4303 /* Info about last usage of registers in EBB to do inheritance/split
4304 transformation. Inheritance transformation is done from a spilled
4305 pseudo and split transformations from a hard register or a pseudo
4306 assigned to a hard register. */
4309 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4310 value INSNS is valid. The insns is chain of optional debug insns
4311 and a finishing non-debug insn using the corresponding reg. The
4312 value is also used to mark the registers which are set up in the
4313 current insn. The negated insn uid is used for this. */
4315 /* Value of global reloads_num at the last insn in INSNS. */
4317 /* Value of global reloads_nums at the last insn in INSNS. */
4319 /* It can be true only for splitting. And it means that the restore
4320 insn should be put after insn given by the following member. */
4322 /* Next insns in the current EBB which use the original reg and the
4323 original reg value is not changed between the current insn and
4324 the next insns. In order words, e.g. for inheritance, if we need
4325 to use the original reg value again in the next insns we can try
4326 to use the value in a hard register from a reload insn of the
4331 /* Map: regno -> corresponding pseudo usage insns. */
4332 static struct usage_insns
*usage_insns
;
4335 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4337 usage_insns
[regno
].check
= curr_usage_insns_check
;
4338 usage_insns
[regno
].insns
= insn
;
4339 usage_insns
[regno
].reloads_num
= reloads_num
;
4340 usage_insns
[regno
].calls_num
= calls_num
;
4341 usage_insns
[regno
].after_p
= after_p
;
4344 /* The function is used to form list REGNO usages which consists of
4345 optional debug insns finished by a non-debug insn using REGNO.
4346 RELOADS_NUM is current number of reload insns processed so far. */
4348 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4350 rtx next_usage_insns
;
4352 if (usage_insns
[regno
].check
== curr_usage_insns_check
4353 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4354 && DEBUG_INSN_P (insn
))
4356 /* Check that we did not add the debug insn yet. */
4357 if (next_usage_insns
!= insn
4358 && (GET_CODE (next_usage_insns
) != INSN_LIST
4359 || XEXP (next_usage_insns
, 0) != insn
))
4360 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4363 else if (NONDEBUG_INSN_P (insn
))
4364 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4366 usage_insns
[regno
].check
= 0;
4369 /* Return first non-debug insn in list USAGE_INSNS. */
4371 skip_usage_debug_insns (rtx usage_insns
)
4375 /* Skip debug insns. */
4376 for (insn
= usage_insns
;
4377 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4378 insn
= XEXP (insn
, 1))
4380 return safe_as_a
<rtx_insn
*> (insn
);
4383 /* Return true if we need secondary memory moves for insn in
4384 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4387 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4388 rtx usage_insns ATTRIBUTE_UNUSED
)
4390 #ifndef SECONDARY_MEMORY_NEEDED
4397 if (inher_cl
== ALL_REGS
4398 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4400 lra_assert (INSN_P (insn
));
4401 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4403 dest
= SET_DEST (set
);
4406 lra_assert (inher_cl
!= NO_REGS
);
4407 cl
= get_reg_class (REGNO (dest
));
4408 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4409 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4413 /* Registers involved in inheritance/split in the current EBB
4414 (inheritance/split pseudos and original registers). */
4415 static bitmap_head check_only_regs
;
4417 /* Do inheritance transformations for insn INSN, which defines (if
4418 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4419 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4420 form as the "insns" field of usage_insns. Return true if we
4421 succeed in such transformation.
4423 The transformations look like:
4426 ... p <- i (new insn)
4428 <- ... p ... <- ... i ...
4430 ... i <- p (new insn)
4431 <- ... p ... <- ... i ...
4433 <- ... p ... <- ... i ...
4434 where p is a spilled original pseudo and i is a new inheritance pseudo.
4437 The inheritance pseudo has the smallest class of two classes CL and
4438 class of ORIGINAL REGNO. */
4440 inherit_reload_reg (bool def_p
, int original_regno
,
4441 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4443 if (optimize_function_for_size_p (cfun
))
4446 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4447 rtx original_reg
= regno_reg_rtx
[original_regno
];
4448 rtx new_reg
, usage_insn
;
4449 rtx_insn
*new_insns
;
4451 lra_assert (! usage_insns
[original_regno
].after_p
);
4452 if (lra_dump_file
!= NULL
)
4453 fprintf (lra_dump_file
,
4454 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4455 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4457 if (lra_dump_file
!= NULL
)
4459 fprintf (lra_dump_file
,
4460 " Rejecting inheritance for %d "
4461 "because of disjoint classes %s and %s\n",
4462 original_regno
, reg_class_names
[cl
],
4463 reg_class_names
[rclass
]);
4464 fprintf (lra_dump_file
,
4465 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4469 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4470 /* We don't use a subset of two classes because it can be
4471 NO_REGS. This transformation is still profitable in most
4472 cases even if the classes are not intersected as register
4473 move is probably cheaper than a memory load. */
4474 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4476 if (lra_dump_file
!= NULL
)
4477 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4478 reg_class_names
[cl
], reg_class_names
[rclass
]);
4482 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4484 /* Reject inheritance resulting in secondary memory moves.
4485 Otherwise, there is a danger in LRA cycling. Also such
4486 transformation will be unprofitable. */
4487 if (lra_dump_file
!= NULL
)
4489 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
4490 rtx set
= single_set (insn
);
4492 lra_assert (set
!= NULL_RTX
);
4494 rtx dest
= SET_DEST (set
);
4496 lra_assert (REG_P (dest
));
4497 fprintf (lra_dump_file
,
4498 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4499 "as secondary mem is needed\n",
4500 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4501 original_regno
, reg_class_names
[rclass
]);
4502 fprintf (lra_dump_file
,
4503 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4507 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4508 rclass
, "inheritance");
4511 lra_emit_move (original_reg
, new_reg
);
4513 lra_emit_move (new_reg
, original_reg
);
4514 new_insns
= get_insns ();
4516 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4518 if (lra_dump_file
!= NULL
)
4520 fprintf (lra_dump_file
,
4521 " Rejecting inheritance %d->%d "
4522 "as it results in 2 or more insns:\n",
4523 original_regno
, REGNO (new_reg
));
4524 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
4525 fprintf (lra_dump_file
,
4526 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4530 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
);
4531 lra_update_insn_regno_info (insn
);
4533 /* We now have a new usage insn for original regno. */
4534 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4535 if (lra_dump_file
!= NULL
)
4536 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4537 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4538 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4539 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4540 bitmap_set_bit (&check_only_regs
, original_regno
);
4541 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4543 lra_process_new_insns (insn
, NULL
, new_insns
,
4544 "Add original<-inheritance");
4546 lra_process_new_insns (insn
, new_insns
, NULL
,
4547 "Add inheritance<-original");
4548 while (next_usage_insns
!= NULL_RTX
)
4550 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4552 usage_insn
= next_usage_insns
;
4553 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4554 next_usage_insns
= NULL
;
4558 usage_insn
= XEXP (next_usage_insns
, 0);
4559 lra_assert (DEBUG_INSN_P (usage_insn
));
4560 next_usage_insns
= XEXP (next_usage_insns
, 1);
4562 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4563 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4564 if (lra_dump_file
!= NULL
)
4566 fprintf (lra_dump_file
,
4567 " Inheritance reuse change %d->%d (bb%d):\n",
4568 original_regno
, REGNO (new_reg
),
4569 BLOCK_FOR_INSN (usage_insn
)->index
);
4570 dump_insn_slim (lra_dump_file
, usage_insn
);
4573 if (lra_dump_file
!= NULL
)
4574 fprintf (lra_dump_file
,
4575 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4579 /* Return true if we need a caller save/restore for pseudo REGNO which
4580 was assigned to a hard register. */
4582 need_for_call_save_p (int regno
)
4584 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4585 return (usage_insns
[regno
].calls_num
< calls_num
4586 && (overlaps_hard_reg_set_p
4587 ((flag_use_caller_save
&&
4588 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4589 ? lra_reg_info
[regno
].actual_call_used_reg_set
4590 : call_used_reg_set
,
4591 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4592 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4593 PSEUDO_REGNO_MODE (regno
))));
4596 /* Global registers occurring in the current EBB. */
4597 static bitmap_head ebb_global_regs
;
4599 /* Return true if we need a split for hard register REGNO or pseudo
4600 REGNO which was assigned to a hard register.
4601 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4602 used for reloads since the EBB end. It is an approximation of the
4603 used hard registers in the split range. The exact value would
4604 require expensive calculations. If we were aggressive with
4605 splitting because of the approximation, the split pseudo will save
4606 the same hard register assignment and will be removed in the undo
4607 pass. We still need the approximation because too aggressive
4608 splitting would result in too inaccurate cost calculation in the
4609 assignment pass because of too many generated moves which will be
4610 probably removed in the undo pass. */
4612 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4614 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4616 lra_assert (hard_regno
>= 0);
4617 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4618 /* Don't split eliminable hard registers, otherwise we can
4619 split hard registers like hard frame pointer, which
4620 lives on BB start/end according to DF-infrastructure,
4621 when there is a pseudo assigned to the register and
4622 living in the same BB. */
4623 && (regno
>= FIRST_PSEUDO_REGISTER
4624 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4625 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4626 /* Don't split call clobbered hard regs living through
4627 calls, otherwise we might have a check problem in the
4628 assign sub-pass as in the most cases (exception is a
4629 situation when lra_risky_transformations_p value is
4630 true) the assign pass assumes that all pseudos living
4631 through calls are assigned to call saved hard regs. */
4632 && (regno
>= FIRST_PSEUDO_REGISTER
4633 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4634 || usage_insns
[regno
].calls_num
== calls_num
)
4635 /* We need at least 2 reloads to make pseudo splitting
4636 profitable. We should provide hard regno splitting in
4637 any case to solve 1st insn scheduling problem when
4638 moving hard register definition up might result in
4639 impossibility to find hard register for reload pseudo of
4640 small register class. */
4641 && (usage_insns
[regno
].reloads_num
4642 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4643 && (regno
< FIRST_PSEUDO_REGISTER
4644 /* For short living pseudos, spilling + inheritance can
4645 be considered a substitution for splitting.
4646 Therefore we do not splitting for local pseudos. It
4647 decreases also aggressiveness of splitting. The
4648 minimal number of references is chosen taking into
4649 account that for 2 references splitting has no sense
4650 as we can just spill the pseudo. */
4651 || (regno
>= FIRST_PSEUDO_REGISTER
4652 && lra_reg_info
[regno
].nrefs
> 3
4653 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4654 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4657 /* Return class for the split pseudo created from original pseudo with
4658 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4659 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4660 results in no secondary memory movements. */
4661 static enum reg_class
4662 choose_split_class (enum reg_class allocno_class
,
4663 int hard_regno ATTRIBUTE_UNUSED
,
4664 machine_mode mode ATTRIBUTE_UNUSED
)
4666 #ifndef SECONDARY_MEMORY_NEEDED
4667 return allocno_class
;
4670 enum reg_class cl
, best_cl
= NO_REGS
;
4671 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4672 = REGNO_REG_CLASS (hard_regno
);
4674 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4675 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4676 return allocno_class
;
4678 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4680 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4681 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4682 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4683 && (best_cl
== NO_REGS
4684 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4690 /* Do split transformations for insn INSN, which defines or uses
4691 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4692 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4693 "insns" field of usage_insns.
4695 The transformations look like:
4698 ... s <- p (new insn -- save)
4700 ... p <- s (new insn -- restore)
4701 <- ... p ... <- ... p ...
4703 <- ... p ... <- ... p ...
4704 ... s <- p (new insn -- save)
4706 ... p <- s (new insn -- restore)
4707 <- ... p ... <- ... p ...
4709 where p is an original pseudo got a hard register or a hard
4710 register and s is a new split pseudo. The save is put before INSN
4711 if BEFORE_P is true. Return true if we succeed in such
4714 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
4715 rtx next_usage_insns
)
4717 enum reg_class rclass
;
4719 int hard_regno
, nregs
;
4720 rtx new_reg
, usage_insn
;
4721 rtx_insn
*restore
, *save
;
4725 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4727 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4728 hard_regno
= original_regno
;
4729 call_save_p
= false;
4734 hard_regno
= reg_renumber
[original_regno
];
4735 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4736 rclass
= lra_get_allocno_class (original_regno
);
4737 original_reg
= regno_reg_rtx
[original_regno
];
4738 call_save_p
= need_for_call_save_p (original_regno
);
4740 original_reg
= regno_reg_rtx
[original_regno
];
4741 lra_assert (hard_regno
>= 0);
4742 if (lra_dump_file
!= NULL
)
4743 fprintf (lra_dump_file
,
4744 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4747 machine_mode mode
= GET_MODE (original_reg
);
4749 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4750 hard_regno_nregs
[hard_regno
][mode
],
4752 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4756 rclass
= choose_split_class (rclass
, hard_regno
,
4757 GET_MODE (original_reg
));
4758 if (rclass
== NO_REGS
)
4760 if (lra_dump_file
!= NULL
)
4762 fprintf (lra_dump_file
,
4763 " Rejecting split of %d(%s): "
4764 "no good reg class for %d(%s)\n",
4766 reg_class_names
[lra_get_allocno_class (original_regno
)],
4768 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4771 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4775 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4777 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4779 save
= emit_spill_move (true, new_reg
, original_reg
);
4780 if (NEXT_INSN (save
) != NULL_RTX
)
4782 lra_assert (! call_save_p
);
4783 if (lra_dump_file
!= NULL
)
4787 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4788 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4789 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
4790 fprintf (lra_dump_file
,
4791 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4795 restore
= emit_spill_move (false, new_reg
, original_reg
);
4796 if (NEXT_INSN (restore
) != NULL_RTX
)
4798 lra_assert (! call_save_p
);
4799 if (lra_dump_file
!= NULL
)
4801 fprintf (lra_dump_file
,
4802 " Rejecting split %d->%d "
4803 "resulting in > 2 %s restore insns:\n",
4804 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4805 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
4806 fprintf (lra_dump_file
,
4807 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4811 after_p
= usage_insns
[original_regno
].after_p
;
4812 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4813 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4814 bitmap_set_bit (&check_only_regs
, original_regno
);
4815 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4818 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4820 usage_insn
= next_usage_insns
;
4823 usage_insn
= XEXP (next_usage_insns
, 0);
4824 lra_assert (DEBUG_INSN_P (usage_insn
));
4825 next_usage_insns
= XEXP (next_usage_insns
, 1);
4826 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4827 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4828 if (lra_dump_file
!= NULL
)
4830 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4831 original_regno
, REGNO (new_reg
));
4832 dump_insn_slim (lra_dump_file
, usage_insn
);
4835 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4836 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4837 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
4838 after_p
? NULL
: restore
,
4839 after_p
? restore
: NULL
,
4841 ? "Add reg<-save" : "Add reg<-split");
4842 lra_process_new_insns (insn
, before_p
? save
: NULL
,
4843 before_p
? NULL
: save
,
4845 ? "Add save<-reg" : "Add split<-reg");
4847 /* If we are trying to split multi-register. We should check
4848 conflicts on the next assignment sub-pass. IRA can allocate on
4849 sub-register levels, LRA do this on pseudos level right now and
4850 this discrepancy may create allocation conflicts after
4852 lra_risky_transformations_p
= true;
4853 if (lra_dump_file
!= NULL
)
4854 fprintf (lra_dump_file
,
4855 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4859 /* Recognize that we need a split transformation for insn INSN, which
4860 defines or uses REGNO in its insn biggest MODE (we use it only if
4861 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4862 hard registers which might be used for reloads since the EBB end.
4863 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4864 uid before starting INSN processing. Return true if we succeed in
4865 such transformation. */
4867 split_if_necessary (int regno
, machine_mode mode
,
4868 HARD_REG_SET potential_reload_hard_regs
,
4869 bool before_p
, rtx_insn
*insn
, int max_uid
)
4873 rtx next_usage_insns
;
4875 if (regno
< FIRST_PSEUDO_REGISTER
)
4876 nregs
= hard_regno_nregs
[regno
][mode
];
4877 for (i
= 0; i
< nregs
; i
++)
4878 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4879 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4880 /* To avoid processing the register twice or more. */
4881 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4882 && INSN_UID (next_usage_insns
) < max_uid
)
4883 || (GET_CODE (next_usage_insns
) == INSN_LIST
4884 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4885 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4886 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4891 /* Check only registers living at the current program point in the
4893 static bitmap_head live_regs
;
4895 /* Update live info in EBB given by its HEAD and TAIL insns after
4896 inheritance/split transformation. The function removes dead moves
4899 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
4904 rtx_insn
*prev_insn
;
4907 basic_block last_bb
, prev_bb
, curr_bb
;
4909 struct lra_insn_reg
*reg
;
4913 last_bb
= BLOCK_FOR_INSN (tail
);
4915 for (curr_insn
= tail
;
4916 curr_insn
!= PREV_INSN (head
);
4917 curr_insn
= prev_insn
)
4919 prev_insn
= PREV_INSN (curr_insn
);
4920 /* We need to process empty blocks too. They contain
4921 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4922 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4924 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4925 if (curr_bb
!= prev_bb
)
4927 if (prev_bb
!= NULL
)
4929 /* Update df_get_live_in (prev_bb): */
4930 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4931 if (bitmap_bit_p (&live_regs
, j
))
4932 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4934 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4936 if (curr_bb
!= last_bb
)
4938 /* Update df_get_live_out (curr_bb): */
4939 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4941 live_p
= bitmap_bit_p (&live_regs
, j
);
4943 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4944 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4950 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4952 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4956 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4958 if (! NONDEBUG_INSN_P (curr_insn
))
4960 curr_id
= lra_get_insn_recog_data (curr_insn
);
4961 curr_static_id
= curr_id
->insn_static_data
;
4963 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4964 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4965 && bitmap_bit_p (&check_only_regs
, regno
)
4966 && ! bitmap_bit_p (&live_regs
, regno
))
4968 /* See which defined values die here. */
4969 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4970 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4971 bitmap_clear_bit (&live_regs
, reg
->regno
);
4972 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
4973 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4974 bitmap_clear_bit (&live_regs
, reg
->regno
);
4975 /* Mark each used value as live. */
4976 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4977 if (reg
->type
!= OP_OUT
4978 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4979 bitmap_set_bit (&live_regs
, reg
->regno
);
4980 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
4981 if (reg
->type
!= OP_OUT
4982 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4983 bitmap_set_bit (&live_regs
, reg
->regno
);
4984 if (curr_id
->arg_hard_regs
!= NULL
)
4985 /* Make argument hard registers live. */
4986 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
4987 if (bitmap_bit_p (&check_only_regs
, regno
))
4988 bitmap_set_bit (&live_regs
, regno
);
4989 /* It is quite important to remove dead move insns because it
4990 means removing dead store. We don't need to process them for
4994 if (lra_dump_file
!= NULL
)
4996 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4997 dump_insn_slim (lra_dump_file
, curr_insn
);
4999 lra_set_insn_deleted (curr_insn
);
5004 /* The structure describes info to do an inheritance for the current
5005 insn. We need to collect such info first before doing the
5006 transformations because the transformations change the insn
5007 internal representation. */
5010 /* Original regno. */
5012 /* Subsequent insns which can inherit original reg value. */
5016 /* Array containing all info for doing inheritance from the current
5018 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5020 /* Number elements in the previous array. */
5021 static int to_inherit_num
;
5023 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5024 structure to_inherit. */
5026 add_to_inherit (int regno
, rtx insns
)
5030 for (i
= 0; i
< to_inherit_num
; i
++)
5031 if (to_inherit
[i
].regno
== regno
)
5033 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5034 to_inherit
[to_inherit_num
].regno
= regno
;
5035 to_inherit
[to_inherit_num
++].insns
= insns
;
5038 /* Return the last non-debug insn in basic block BB, or the block begin
5041 get_last_insertion_point (basic_block bb
)
5045 FOR_BB_INSNS_REVERSE (bb
, insn
)
5046 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5051 /* Set up RES by registers living on edges FROM except the edge (FROM,
5052 TO) or by registers set up in a jump insn in BB FROM. */
5054 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5057 struct lra_insn_reg
*reg
;
5061 lra_assert (to
!= NULL
);
5063 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5065 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5066 last
= get_last_insertion_point (from
);
5067 if (! JUMP_P (last
))
5069 curr_id
= lra_get_insn_recog_data (last
);
5070 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5071 if (reg
->type
!= OP_IN
)
5072 bitmap_set_bit (res
, reg
->regno
);
5075 /* Used as a temporary results of some bitmap calculations. */
5076 static bitmap_head temp_bitmap
;
5078 /* We split for reloads of small class of hard regs. The following
5079 defines how many hard regs the class should have to be qualified as
5080 small. The code is mostly oriented to x86/x86-64 architecture
5081 where some insns need to use only specific register or pair of
5082 registers and these register can live in RTL explicitly, e.g. for
5083 parameter passing. */
5084 static const int max_small_class_regs_num
= 2;
5086 /* Do inheritance/split transformations in EBB starting with HEAD and
5087 finishing on TAIL. We process EBB insns in the reverse order.
5088 Return true if we did any inheritance/split transformation in the
5091 We should avoid excessive splitting which results in worse code
5092 because of inaccurate cost calculations for spilling new split
5093 pseudos in such case. To achieve this we do splitting only if
5094 register pressure is high in given basic block and there are reload
5095 pseudos requiring hard registers. We could do more register
5096 pressure calculations at any given program point to avoid necessary
5097 splitting even more but it is to expensive and the current approach
5098 works well enough. */
5100 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5102 int i
, src_regno
, dst_regno
, nregs
;
5103 bool change_p
, succ_p
, update_reloads_num_p
;
5104 rtx_insn
*prev_insn
, *last_insn
;
5105 rtx next_usage_insns
, set
;
5107 struct lra_insn_reg
*reg
;
5108 basic_block last_processed_bb
, curr_bb
= NULL
;
5109 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5113 bool head_p
, after_p
;
5116 curr_usage_insns_check
++;
5117 reloads_num
= calls_num
= 0;
5118 bitmap_clear (&check_only_regs
);
5119 last_processed_bb
= NULL
;
5120 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5121 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5122 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5123 /* We don't process new insns generated in the loop. */
5124 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5126 prev_insn
= PREV_INSN (curr_insn
);
5127 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5128 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5129 if (last_processed_bb
!= curr_bb
)
5131 /* We are at the end of BB. Add qualified living
5132 pseudos for potential splitting. */
5133 to_process
= df_get_live_out (curr_bb
);
5134 if (last_processed_bb
!= NULL
)
5136 /* We are somewhere in the middle of EBB. */
5137 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5139 to_process
= &temp_bitmap
;
5141 last_processed_bb
= curr_bb
;
5142 last_insn
= get_last_insertion_point (curr_bb
);
5143 after_p
= (! JUMP_P (last_insn
)
5144 && (! CALL_P (last_insn
)
5145 || (find_reg_note (last_insn
,
5146 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5147 && ! SIBLING_CALL_P (last_insn
))));
5148 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5149 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5151 if ((int) j
>= lra_constraint_new_regno_start
)
5153 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5155 if (j
< FIRST_PSEUDO_REGISTER
)
5156 SET_HARD_REG_BIT (live_hard_regs
, j
);
5158 add_to_hard_reg_set (&live_hard_regs
,
5159 PSEUDO_REGNO_MODE (j
),
5161 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5165 src_regno
= dst_regno
= -1;
5166 if (NONDEBUG_INSN_P (curr_insn
)
5167 && (set
= single_set (curr_insn
)) != NULL_RTX
5168 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5170 src_regno
= REGNO (SET_SRC (set
));
5171 dst_regno
= REGNO (SET_DEST (set
));
5173 update_reloads_num_p
= true;
5174 if (src_regno
< lra_constraint_new_regno_start
5175 && src_regno
>= FIRST_PSEUDO_REGISTER
5176 && reg_renumber
[src_regno
] < 0
5177 && dst_regno
>= lra_constraint_new_regno_start
5178 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5180 /* 'reload_pseudo <- original_pseudo'. */
5181 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5183 update_reloads_num_p
= false;
5185 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5186 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5187 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5188 curr_insn
, next_usage_insns
);
5192 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5193 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5194 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5195 reg_class_contents
[cl
]);
5197 else if (src_regno
>= lra_constraint_new_regno_start
5198 && dst_regno
< lra_constraint_new_regno_start
5199 && dst_regno
>= FIRST_PSEUDO_REGISTER
5200 && reg_renumber
[dst_regno
] < 0
5201 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5202 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5203 && (next_usage_insns
5204 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5206 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5208 update_reloads_num_p
= false;
5209 /* 'original_pseudo <- reload_pseudo'. */
5210 if (! JUMP_P (curr_insn
)
5211 && inherit_reload_reg (true, dst_regno
, cl
,
5212 curr_insn
, next_usage_insns
))
5215 usage_insns
[dst_regno
].check
= 0;
5216 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5217 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5218 reg_class_contents
[cl
]);
5220 else if (INSN_P (curr_insn
))
5223 int max_uid
= get_max_uid ();
5225 curr_id
= lra_get_insn_recog_data (curr_insn
);
5226 curr_static_id
= curr_id
->insn_static_data
;
5228 /* Process insn definitions. */
5229 for (iter
= 0; iter
< 2; iter
++)
5230 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5233 if (reg
->type
!= OP_IN
5234 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5236 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5237 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5238 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5239 && (next_usage_insns
5240 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5242 struct lra_insn_reg
*r
;
5244 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5245 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5247 /* Don't do inheritance if the pseudo is also
5248 used in the insn. */
5250 /* We can not do inheritance right now
5251 because the current insn reg info (chain
5252 regs) can change after that. */
5253 add_to_inherit (dst_regno
, next_usage_insns
);
5255 /* We can not process one reg twice here because of
5256 usage_insns invalidation. */
5257 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5258 || reg_renumber
[dst_regno
] >= 0)
5259 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5263 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5264 potential_reload_hard_regs
,
5265 false, curr_insn
, max_uid
))
5267 CLEAR_HARD_REG_SET (s
);
5268 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5269 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5271 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5272 reg_renumber
[dst_regno
]);
5273 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5275 /* We should invalidate potential inheritance or
5276 splitting for the current insn usages to the next
5277 usage insns (see code below) as the output pseudo
5279 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5280 && reg_renumber
[dst_regno
] < 0)
5281 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5282 && (dst_regno
< FIRST_PSEUDO_REGISTER
5283 || reg_renumber
[dst_regno
] >= 0)))
5285 /* Invalidate and mark definitions. */
5286 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5287 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5290 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5291 for (i
= 0; i
< nregs
; i
++)
5292 usage_insns
[dst_regno
+ i
].check
5293 = -(int) INSN_UID (curr_insn
);
5297 if (! JUMP_P (curr_insn
))
5298 for (i
= 0; i
< to_inherit_num
; i
++)
5299 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5300 ALL_REGS
, curr_insn
,
5301 to_inherit
[i
].insns
))
5303 if (CALL_P (curr_insn
))
5305 rtx cheap
, pat
, dest
;
5307 int regno
, hard_regno
;
5310 if ((cheap
= find_reg_note (curr_insn
,
5311 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5312 && ((cheap
= XEXP (cheap
, 0)), true)
5313 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5314 && (hard_regno
= reg_renumber
[regno
]) >= 0
5315 /* If there are pending saves/restores, the
5316 optimization is not worth. */
5317 && usage_insns
[regno
].calls_num
== calls_num
- 1
5318 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5320 /* Restore the pseudo from the call result as
5321 REG_RETURNED note says that the pseudo value is
5322 in the call result and the pseudo is an argument
5324 pat
= PATTERN (curr_insn
);
5325 if (GET_CODE (pat
) == PARALLEL
)
5326 pat
= XVECEXP (pat
, 0, 0);
5327 dest
= SET_DEST (pat
);
5328 /* For multiple return values dest is PARALLEL.
5329 Currently we handle only single return value case. */
5333 emit_move_insn (cheap
, copy_rtx (dest
));
5334 restore
= get_insns ();
5336 lra_process_new_insns (curr_insn
, NULL
, restore
,
5337 "Inserting call parameter restore");
5338 /* We don't need to save/restore of the pseudo from
5340 usage_insns
[regno
].calls_num
= calls_num
;
5341 bitmap_set_bit (&check_only_regs
, regno
);
5346 /* Process insn usages. */
5347 for (iter
= 0; iter
< 2; iter
++)
5348 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5351 if ((reg
->type
!= OP_OUT
5352 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5353 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5355 if (src_regno
>= FIRST_PSEUDO_REGISTER
5356 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5358 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5359 && (next_usage_insns
5360 = usage_insns
[src_regno
].insns
) != NULL_RTX
5361 && NONDEBUG_INSN_P (curr_insn
))
5362 add_to_inherit (src_regno
, next_usage_insns
);
5363 else if (usage_insns
[src_regno
].check
5364 != -(int) INSN_UID (curr_insn
))
5365 /* Add usages but only if the reg is not set up
5366 in the same insn. */
5367 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5369 else if (src_regno
< FIRST_PSEUDO_REGISTER
5370 || reg_renumber
[src_regno
] >= 0)
5373 rtx use_insn
= curr_insn
;
5375 before_p
= (JUMP_P (curr_insn
)
5376 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5377 if (NONDEBUG_INSN_P (curr_insn
)
5378 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5379 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5380 potential_reload_hard_regs
,
5381 before_p
, curr_insn
, max_uid
))
5384 lra_risky_transformations_p
= true;
5387 usage_insns
[src_regno
].check
= 0;
5389 use_insn
= PREV_INSN (curr_insn
);
5391 if (NONDEBUG_INSN_P (curr_insn
))
5393 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5394 add_to_hard_reg_set (&live_hard_regs
,
5395 reg
->biggest_mode
, src_regno
);
5397 add_to_hard_reg_set (&live_hard_regs
,
5398 PSEUDO_REGNO_MODE (src_regno
),
5399 reg_renumber
[src_regno
]);
5401 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5404 /* Process call args. */
5405 if (curr_id
->arg_hard_regs
!= NULL
)
5406 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5407 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5409 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5410 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5412 for (i
= 0; i
< to_inherit_num
; i
++)
5414 src_regno
= to_inherit
[i
].regno
;
5415 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5416 curr_insn
, to_inherit
[i
].insns
))
5419 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5422 if (update_reloads_num_p
5423 && NONDEBUG_INSN_P (curr_insn
)
5424 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5427 if ((REG_P (SET_DEST (set
))
5428 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5429 && reg_renumber
[regno
] < 0
5430 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5431 || (REG_P (SET_SRC (set
))
5432 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5433 && reg_renumber
[regno
] < 0
5434 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5436 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5438 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5439 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5440 reg_class_contents
[cl
]);
5443 /* We reached the start of the current basic block. */
5444 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5445 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5447 /* We reached the beginning of the current block -- do
5448 rest of spliting in the current BB. */
5449 to_process
= df_get_live_in (curr_bb
);
5450 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5452 /* We are somewhere in the middle of EBB. */
5453 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5454 curr_bb
, &temp_bitmap
);
5455 to_process
= &temp_bitmap
;
5458 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5460 if ((int) j
>= lra_constraint_new_regno_start
)
5462 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5463 && usage_insns
[j
].check
== curr_usage_insns_check
5464 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5466 if (need_for_split_p (potential_reload_hard_regs
, j
))
5468 if (lra_dump_file
!= NULL
&& head_p
)
5470 fprintf (lra_dump_file
,
5471 " ----------------------------------\n");
5474 if (split_reg (false, j
, bb_note (curr_bb
),
5478 usage_insns
[j
].check
= 0;
5486 /* This value affects EBB forming. If probability of edge from EBB to
5487 a BB is not greater than the following value, we don't add the BB
5489 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5491 /* Current number of inheritance/split iteration. */
5492 int lra_inheritance_iter
;
5494 /* Entry function for inheritance/split pass. */
5496 lra_inheritance (void)
5499 basic_block bb
, start_bb
;
5502 lra_inheritance_iter
++;
5503 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5505 timevar_push (TV_LRA_INHERITANCE
);
5506 if (lra_dump_file
!= NULL
)
5507 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5508 lra_inheritance_iter
);
5509 curr_usage_insns_check
= 0;
5510 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5511 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5512 usage_insns
[i
].check
= 0;
5513 bitmap_initialize (&check_only_regs
, ®_obstack
);
5514 bitmap_initialize (&live_regs
, ®_obstack
);
5515 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5516 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5517 FOR_EACH_BB_FN (bb
, cfun
)
5520 if (lra_dump_file
!= NULL
)
5521 fprintf (lra_dump_file
, "EBB");
5522 /* Form a EBB starting with BB. */
5523 bitmap_clear (&ebb_global_regs
);
5524 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5527 if (lra_dump_file
!= NULL
)
5528 fprintf (lra_dump_file
, " %d", bb
->index
);
5529 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5530 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5532 e
= find_fallthru_edge (bb
->succs
);
5535 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5539 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5540 if (lra_dump_file
!= NULL
)
5541 fprintf (lra_dump_file
, "\n");
5542 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5543 /* Remember that the EBB head and tail can change in
5545 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5547 bitmap_clear (&ebb_global_regs
);
5548 bitmap_clear (&temp_bitmap
);
5549 bitmap_clear (&live_regs
);
5550 bitmap_clear (&check_only_regs
);
5553 timevar_pop (TV_LRA_INHERITANCE
);
5558 /* This page contains code to undo failed inheritance/split
5561 /* Current number of iteration undoing inheritance/split. */
5562 int lra_undo_inheritance_iter
;
5564 /* Fix BB live info LIVE after removing pseudos created on pass doing
5565 inheritance/split which are REMOVED_PSEUDOS. */
5567 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5572 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5573 if (bitmap_clear_bit (live
, regno
))
5574 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5577 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5582 if (GET_CODE (reg
) == SUBREG
)
5583 reg
= SUBREG_REG (reg
);
5589 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5590 return true if we did any change. The undo transformations for
5591 inheritance looks like
5595 p <- i, i <- p, and i <- i3
5596 where p is original pseudo from which inheritance pseudo i was
5597 created, i and i3 are removed inheritance pseudos, i2 is another
5598 not removed inheritance pseudo. All split pseudos or other
5599 occurrences of removed inheritance pseudos are changed on the
5600 corresponding original pseudos.
5602 The function also schedules insns changed and created during
5603 inheritance/split pass for processing by the subsequent constraint
5606 remove_inheritance_pseudos (bitmap remove_pseudos
)
5609 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5611 rtx_insn
*prev_insn
;
5612 bool change_p
, done_p
;
5614 change_p
= ! bitmap_empty_p (remove_pseudos
);
5615 /* We can not finish the function right away if CHANGE_P is true
5616 because we need to marks insns affected by previous
5617 inheritance/split pass for processing by the subsequent
5619 FOR_EACH_BB_FN (bb
, cfun
)
5621 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5622 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5623 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5625 if (! INSN_P (curr_insn
))
5628 sregno
= dregno
= -1;
5629 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5630 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5632 dregno
= get_regno (SET_DEST (set
));
5633 sregno
= get_regno (SET_SRC (set
));
5636 if (sregno
>= 0 && dregno
>= 0)
5638 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5639 && (lra_reg_info
[sregno
].restore_regno
== dregno
5640 || (bitmap_bit_p (remove_pseudos
, dregno
)
5641 && (lra_reg_info
[sregno
].restore_regno
5642 == lra_reg_info
[dregno
].restore_regno
))))
5643 || (bitmap_bit_p (remove_pseudos
, dregno
)
5644 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5645 /* One of the following cases:
5646 original <- removed inheritance pseudo
5647 removed inherit pseudo <- another removed inherit pseudo
5648 removed inherit pseudo <- original pseudo
5650 removed_split_pseudo <- original_reg
5651 original_reg <- removed_split_pseudo */
5653 if (lra_dump_file
!= NULL
)
5655 fprintf (lra_dump_file
, " Removing %s:\n",
5656 bitmap_bit_p (&lra_split_regs
, sregno
)
5657 || bitmap_bit_p (&lra_split_regs
, dregno
)
5658 ? "split" : "inheritance");
5659 dump_insn_slim (lra_dump_file
, curr_insn
);
5661 lra_set_insn_deleted (curr_insn
);
5664 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5665 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5667 /* Search the following pattern:
5668 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5669 original_pseudo <- inherit_or_split_pseudo1
5670 where the 2nd insn is the current insn and
5671 inherit_or_split_pseudo2 is not removed. If it is found,
5672 change the current insn onto:
5673 original_pseudo <- inherit_or_split_pseudo2. */
5674 for (prev_insn
= PREV_INSN (curr_insn
);
5675 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5676 prev_insn
= PREV_INSN (prev_insn
))
5678 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5679 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5680 /* There should be no subregs in insn we are
5681 searching because only the original reg might
5682 be in subreg when we changed the mode of
5683 load/store for splitting. */
5684 && REG_P (SET_DEST (prev_set
))
5685 && REG_P (SET_SRC (prev_set
))
5686 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5687 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5688 >= FIRST_PSEUDO_REGISTER
)
5689 /* As we consider chain of inheritance or
5690 splitting described in above comment we should
5691 check that sregno and prev_sregno were
5692 inheritance/split pseudos created from the
5693 same original regno. */
5694 && (lra_reg_info
[sregno
].restore_regno
5695 == lra_reg_info
[prev_sregno
].restore_regno
)
5696 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5698 lra_assert (GET_MODE (SET_SRC (prev_set
))
5699 == GET_MODE (regno_reg_rtx
[sregno
]));
5700 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5701 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5703 SET_SRC (set
) = SET_SRC (prev_set
);
5704 /* As we are finishing with processing the insn
5705 here, check the destination too as it might
5706 inheritance pseudo for another pseudo. */
5707 if (bitmap_bit_p (remove_pseudos
, dregno
)
5708 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
5710 = lra_reg_info
[dregno
].restore_regno
) >= 0)
5712 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
5713 SUBREG_REG (SET_DEST (set
))
5714 = regno_reg_rtx
[restore_regno
];
5716 SET_DEST (set
) = regno_reg_rtx
[restore_regno
];
5718 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5719 lra_set_used_insn_alternative_by_uid
5720 (INSN_UID (curr_insn
), -1);
5722 if (lra_dump_file
!= NULL
)
5724 fprintf (lra_dump_file
, " Change reload insn:\n");
5725 dump_insn_slim (lra_dump_file
, curr_insn
);
5732 struct lra_insn_reg
*reg
;
5733 bool restored_regs_p
= false;
5734 bool kept_regs_p
= false;
5736 curr_id
= lra_get_insn_recog_data (curr_insn
);
5737 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5740 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5741 if (restore_regno
>= 0)
5743 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5745 lra_substitute_pseudo_within_insn (
5746 curr_insn
, regno
, regno_reg_rtx
[restore_regno
]);
5747 restored_regs_p
= true;
5753 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5755 /* The instruction has changed since the previous
5756 constraints pass. */
5757 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5758 lra_set_used_insn_alternative_by_uid
5759 (INSN_UID (curr_insn
), -1);
5761 else if (restored_regs_p
)
5762 /* The instruction has been restored to the form that
5763 it had during the previous constraints pass. */
5764 lra_update_insn_regno_info (curr_insn
);
5765 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5767 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5768 dump_insn_slim (lra_dump_file
, curr_insn
);
5776 /* If optional reload pseudos failed to get a hard register or was not
5777 inherited, it is better to remove optional reloads. We do this
5778 transformation after undoing inheritance to figure out necessity to
5779 remove optional reloads easier. Return true if we do any
5782 undo_optional_reloads (void)
5784 bool change_p
, keep_p
;
5785 unsigned int regno
, uid
;
5786 bitmap_iterator bi
, bi2
;
5789 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5791 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5792 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5793 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5796 /* Keep optional reloads from previous subpasses. */
5797 if (lra_reg_info
[regno
].restore_regno
< 0
5798 /* If the original pseudo changed its allocation, just
5799 removing the optional pseudo is dangerous as the original
5800 pseudo will have longer live range. */
5801 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5803 else if (reg_renumber
[regno
] >= 0)
5804 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5806 insn
= lra_insn_recog_data
[uid
]->insn
;
5807 if ((set
= single_set (insn
)) == NULL_RTX
)
5809 src
= SET_SRC (set
);
5810 dest
= SET_DEST (set
);
5811 if (! REG_P (src
) || ! REG_P (dest
))
5813 if (REGNO (dest
) == regno
5814 /* Ignore insn for optional reloads itself. */
5815 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5816 /* Check only inheritance on last inheritance pass. */
5817 && (int) REGNO (src
) >= new_regno_start
5818 /* Check that the optional reload was inherited. */
5819 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5827 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5828 if (lra_dump_file
!= NULL
)
5829 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5832 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5833 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5834 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5836 if (lra_dump_file
!= NULL
)
5837 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5838 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5839 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5841 insn
= lra_insn_recog_data
[uid
]->insn
;
5842 if ((set
= single_set (insn
)) != NULL_RTX
)
5844 src
= SET_SRC (set
);
5845 dest
= SET_DEST (set
);
5846 if (REG_P (src
) && REG_P (dest
)
5847 && ((REGNO (src
) == regno
5848 && (lra_reg_info
[regno
].restore_regno
5849 == (int) REGNO (dest
)))
5850 || (REGNO (dest
) == regno
5851 && (lra_reg_info
[regno
].restore_regno
5852 == (int) REGNO (src
)))))
5854 if (lra_dump_file
!= NULL
)
5856 fprintf (lra_dump_file
, " Deleting move %u\n",
5858 dump_insn_slim (lra_dump_file
, insn
);
5860 lra_set_insn_deleted (insn
);
5863 /* We should not worry about generation memory-memory
5864 moves here as if the corresponding inheritance did
5865 not work (inheritance pseudo did not get a hard reg),
5866 we remove the inheritance pseudo and the optional
5869 lra_substitute_pseudo_within_insn (
5871 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5872 lra_update_insn_regno_info (insn
);
5873 if (lra_dump_file
!= NULL
)
5875 fprintf (lra_dump_file
,
5876 " Restoring original insn:\n");
5877 dump_insn_slim (lra_dump_file
, insn
);
5881 /* Clear restore_regnos. */
5882 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5883 lra_reg_info
[regno
].restore_regno
= -1;
5884 bitmap_clear (&insn_bitmap
);
5885 bitmap_clear (&removed_optional_reload_pseudos
);
5889 /* Entry function for undoing inheritance/split transformation. Return true
5890 if we did any RTL change in this pass. */
5892 lra_undo_inheritance (void)
5895 int restore_regno
, hard_regno
;
5896 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5897 bitmap_head remove_pseudos
;
5901 lra_undo_inheritance_iter
++;
5902 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5904 if (lra_dump_file
!= NULL
)
5905 fprintf (lra_dump_file
,
5906 "\n********** Undoing inheritance #%d: **********\n\n",
5907 lra_undo_inheritance_iter
);
5908 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5909 n_inherit
= n_all_inherit
= 0;
5910 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5911 if (lra_reg_info
[regno
].restore_regno
>= 0)
5914 if (reg_renumber
[regno
] < 0
5915 /* If the original pseudo changed its allocation, just
5916 removing inheritance is dangerous as for changing
5917 allocation we used shorter live-ranges. */
5918 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5919 bitmap_set_bit (&remove_pseudos
, regno
);
5923 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5924 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5925 n_inherit
, n_all_inherit
,
5926 (double) n_inherit
/ n_all_inherit
* 100);
5927 n_split
= n_all_split
= 0;
5928 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5929 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5932 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5933 ? reg_renumber
[restore_regno
] : restore_regno
);
5934 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5935 bitmap_set_bit (&remove_pseudos
, regno
);
5939 if (lra_dump_file
!= NULL
)
5940 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5941 regno
, restore_regno
);
5944 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5945 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5946 n_split
, n_all_split
,
5947 (double) n_split
/ n_all_split
* 100);
5948 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5949 bitmap_clear (&remove_pseudos
);
5950 /* Clear restore_regnos. */
5951 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5952 lra_reg_info
[regno
].restore_regno
= -1;
5953 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5954 lra_reg_info
[regno
].restore_regno
= -1;
5955 change_p
= undo_optional_reloads () || change_p
;