1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
40 #include "basic-block.h"
44 #include "diagnostic-core.h"
48 #include "tree-pass.h"
52 static int reload_cse_noop_set_p (rtx
);
53 static bool reload_cse_simplify (rtx_insn
*, rtx
);
54 static void reload_cse_regs_1 (void);
55 static int reload_cse_simplify_set (rtx
, rtx_insn
*);
56 static int reload_cse_simplify_operands (rtx_insn
*, rtx
);
58 static void reload_combine (void);
59 static void reload_combine_note_use (rtx
*, rtx_insn
*, int, rtx
);
60 static void reload_combine_note_store (rtx
, const_rtx
, void *);
62 static bool reload_cse_move2add (rtx_insn
*);
63 static void move2add_note_store (rtx
, const_rtx
, void *);
65 /* Call cse / combine like post-reload optimization phases.
66 FIRST is the first instruction. */
69 reload_cse_regs (rtx_insn
*first ATTRIBUTE_UNUSED
)
74 moves_converted
= reload_cse_move2add (first
);
75 if (flag_expensive_optimizations
)
83 /* See whether a single set SET is a noop. */
85 reload_cse_noop_set_p (rtx set
)
87 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
90 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
93 /* Try to simplify INSN. Return true if the CFG may have changed. */
95 reload_cse_simplify (rtx_insn
*insn
, rtx testreg
)
97 rtx body
= PATTERN (insn
);
98 basic_block insn_bb
= BLOCK_FOR_INSN (insn
);
99 unsigned insn_bb_succs
= EDGE_COUNT (insn_bb
->succs
);
101 if (GET_CODE (body
) == SET
)
105 /* Simplify even if we may think it is a no-op.
106 We may think a memory load of a value smaller than WORD_SIZE
107 is redundant because we haven't taken into account possible
108 implicit extension. reload_cse_simplify_set() will bring
109 this out, so it's safer to simplify before we delete. */
110 count
+= reload_cse_simplify_set (body
, insn
);
112 if (!count
&& reload_cse_noop_set_p (body
))
114 rtx value
= SET_DEST (body
);
116 && ! REG_FUNCTION_VALUE_P (value
))
118 if (check_for_inc_dec (insn
))
119 delete_insn_and_edges (insn
);
120 /* We're done with this insn. */
125 apply_change_group ();
127 reload_cse_simplify_operands (insn
, testreg
);
129 else if (GET_CODE (body
) == PARALLEL
)
133 rtx value
= NULL_RTX
;
135 /* Registers mentioned in the clobber list for an asm cannot be reused
136 within the body of the asm. Invalidate those registers now so that
137 we don't try to substitute values for them. */
138 if (asm_noperands (body
) >= 0)
140 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
142 rtx part
= XVECEXP (body
, 0, i
);
143 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
144 cselib_invalidate_rtx (XEXP (part
, 0));
148 /* If every action in a PARALLEL is a noop, we can delete
149 the entire PARALLEL. */
150 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
152 rtx part
= XVECEXP (body
, 0, i
);
153 if (GET_CODE (part
) == SET
)
155 if (! reload_cse_noop_set_p (part
))
157 if (REG_P (SET_DEST (part
))
158 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
162 value
= SET_DEST (part
);
165 else if (GET_CODE (part
) != CLOBBER
)
171 if (check_for_inc_dec (insn
))
172 delete_insn_and_edges (insn
);
173 /* We're done with this insn. */
177 /* It's not a no-op, but we can try to simplify it. */
178 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
179 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
180 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
183 apply_change_group ();
185 reload_cse_simplify_operands (insn
, testreg
);
189 return (EDGE_COUNT (insn_bb
->succs
) != insn_bb_succs
);
192 /* Do a very simple CSE pass over the hard registers.
194 This function detects no-op moves where we happened to assign two
195 different pseudo-registers to the same hard register, and then
196 copied one to the other. Reload will generate a useless
197 instruction copying a register to itself.
199 This function also detects cases where we load a value from memory
200 into two different registers, and (if memory is more expensive than
201 registers) changes it to simply copy the first register into the
204 Another optimization is performed that scans the operands of each
205 instruction to see whether the value is already available in a
206 hard register. It then replaces the operand with the hard register
207 if possible, much like an optional reload would. */
210 reload_cse_regs_1 (void)
212 bool cfg_changed
= false;
215 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
217 cselib_init (CSELIB_RECORD_MEMORY
);
218 init_alias_analysis ();
220 FOR_EACH_BB_FN (bb
, cfun
)
221 FOR_BB_INSNS (bb
, insn
)
224 cfg_changed
|= reload_cse_simplify (insn
, testreg
);
226 cselib_process_insn (insn
);
230 end_alias_analysis ();
236 /* Try to simplify a single SET instruction. SET is the set pattern.
237 INSN is the instruction it came from.
238 This function only handles one case: if we set a register to a value
239 which is not a register, we try to find that value in some other register
240 and change the set into a register copy. */
243 reload_cse_simplify_set (rtx set
, rtx_insn
*insn
)
251 struct elt_loc_list
*l
;
252 #ifdef LOAD_EXTEND_OP
253 enum rtx_code extend_op
= UNKNOWN
;
255 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
257 dreg
= true_regnum (SET_DEST (set
));
262 if (side_effects_p (src
) || true_regnum (src
) >= 0)
265 dclass
= REGNO_REG_CLASS (dreg
);
267 #ifdef LOAD_EXTEND_OP
268 /* When replacing a memory with a register, we need to honor assumptions
269 that combine made wrt the contents of sign bits. We'll do this by
270 generating an extend instruction instead of a reg->reg copy. Thus
271 the destination must be a register that we can widen. */
273 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
274 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
275 && !REG_P (SET_DEST (set
)))
279 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0, VOIDmode
);
283 /* If memory loads are cheaper than register copies, don't change them. */
285 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
286 else if (REG_P (src
))
287 old_cost
= register_move_cost (GET_MODE (src
),
288 REGNO_REG_CLASS (REGNO (src
)), dclass
);
290 old_cost
= set_src_cost (src
, speed
);
292 for (l
= val
->locs
; l
; l
= l
->next
)
294 rtx this_rtx
= l
->loc
;
297 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
299 #ifdef LOAD_EXTEND_OP
300 if (extend_op
!= UNKNOWN
)
304 if (!CONST_SCALAR_INT_P (this_rtx
))
310 result
= wide_int::from (std::make_pair (this_rtx
,
312 BITS_PER_WORD
, UNSIGNED
);
315 result
= wide_int::from (std::make_pair (this_rtx
,
317 BITS_PER_WORD
, SIGNED
);
322 this_rtx
= immed_wide_int_const (result
, word_mode
);
325 this_cost
= set_src_cost (this_rtx
, speed
);
327 else if (REG_P (this_rtx
))
329 #ifdef LOAD_EXTEND_OP
330 if (extend_op
!= UNKNOWN
)
332 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
333 this_cost
= set_src_cost (this_rtx
, speed
);
337 this_cost
= register_move_cost (GET_MODE (this_rtx
),
338 REGNO_REG_CLASS (REGNO (this_rtx
)),
344 /* If equal costs, prefer registers over anything else. That
345 tends to lead to smaller instructions on some machines. */
346 if (this_cost
< old_cost
347 || (this_cost
== old_cost
349 && !REG_P (SET_SRC (set
))))
351 #ifdef LOAD_EXTEND_OP
352 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
353 && extend_op
!= UNKNOWN
354 #ifdef CANNOT_CHANGE_MODE_CLASS
355 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
357 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
361 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
362 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
363 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
367 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
368 old_cost
= this_cost
, did_change
= 1;
375 /* Try to replace operands in INSN with equivalent values that are already
376 in registers. This can be viewed as optional reloading.
378 For each non-register operand in the insn, see if any hard regs are
379 known to be equivalent to that operand. Record the alternatives which
380 can accept these hard registers. Among all alternatives, select the
381 ones which are better or equal to the one currently matching, where
382 "better" is in terms of '?' and '!' constraints. Among the remaining
383 alternatives, select the one which replaces most operands with
387 reload_cse_simplify_operands (rtx_insn
*insn
, rtx testreg
)
391 /* For each operand, all registers that are equivalent to it. */
392 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
394 const char *constraints
[MAX_RECOG_OPERANDS
];
396 /* Vector recording how bad an alternative is. */
397 int *alternative_reject
;
398 /* Vector recording how many registers can be introduced by choosing
400 int *alternative_nregs
;
401 /* Array of vectors recording, for each operand and each alternative,
402 which hard register to substitute, or -1 if the operand should be
404 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
405 /* Array of alternatives, sorted in order of decreasing desirability. */
406 int *alternative_order
;
410 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
413 /* Figure out which alternative currently matches. */
414 if (! constrain_operands (1))
415 fatal_insn_not_found (insn
);
417 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
418 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
419 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
420 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
421 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
423 /* For each operand, find out which regs are equivalent. */
424 for (i
= 0; i
< recog_data
.n_operands
; i
++)
427 struct elt_loc_list
*l
;
430 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
432 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
433 right, so avoid the problem here. Likewise if we have a constant
434 and the insn pattern doesn't tell us the mode we need. */
435 if (LABEL_P (recog_data
.operand
[i
])
436 || (CONSTANT_P (recog_data
.operand
[i
])
437 && recog_data
.operand_mode
[i
] == VOIDmode
))
440 op
= recog_data
.operand
[i
];
441 #ifdef LOAD_EXTEND_OP
443 && GET_MODE_BITSIZE (GET_MODE (op
)) < BITS_PER_WORD
444 && LOAD_EXTEND_OP (GET_MODE (op
)) != UNKNOWN
)
446 rtx set
= single_set (insn
);
448 /* We might have multiple sets, some of which do implicit
449 extension. Punt on this for now. */
452 /* If the destination is also a MEM or a STRICT_LOW_PART, no
454 Also, if there is an explicit extension, we don't have to
455 worry about an implicit one. */
456 else if (MEM_P (SET_DEST (set
))
457 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
458 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
459 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
460 ; /* Continue ordinary processing. */
461 #ifdef CANNOT_CHANGE_MODE_CLASS
462 /* If the register cannot change mode to word_mode, it follows that
463 it cannot have been used in word_mode. */
464 else if (REG_P (SET_DEST (set
))
465 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
467 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
468 ; /* Continue ordinary processing. */
470 /* If this is a straight load, make the extension explicit. */
471 else if (REG_P (SET_DEST (set
))
472 && recog_data
.n_operands
== 2
473 && SET_SRC (set
) == op
474 && SET_DEST (set
) == recog_data
.operand
[1-i
])
476 validate_change (insn
, recog_data
.operand_loc
[i
],
477 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op
)),
480 validate_change (insn
, recog_data
.operand_loc
[1-i
],
481 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
483 if (! apply_change_group ())
485 return reload_cse_simplify_operands (insn
, testreg
);
488 /* ??? There might be arithmetic operations with memory that are
489 safe to optimize, but is it worth the trouble? */
492 #endif /* LOAD_EXTEND_OP */
493 if (side_effects_p (op
))
495 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0, VOIDmode
);
499 for (l
= v
->locs
; l
; l
= l
->next
)
501 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
504 for (i
= 0; i
< recog_data
.n_operands
; i
++)
506 enum machine_mode mode
;
510 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
511 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
512 op_alt_regno
[i
][j
] = -1;
514 p
= constraints
[i
] = recog_data
.constraints
[i
];
515 mode
= recog_data
.operand_mode
[i
];
517 /* Add the reject values for each alternative given by the constraints
526 alternative_reject
[j
] += 3;
528 alternative_reject
[j
] += 300;
531 /* We won't change operands which are already registers. We
532 also don't want to modify output operands. */
533 regno
= true_regnum (recog_data
.operand
[i
]);
535 || constraints
[i
][0] == '='
536 || constraints
[i
][0] == '+')
539 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
541 enum reg_class rclass
= NO_REGS
;
543 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
546 SET_REGNO_RAW (testreg
, regno
);
547 PUT_MODE (testreg
, mode
);
549 /* We found a register equal to this operand. Now look for all
550 alternatives that can accept this register and have not been
551 assigned a register they can use yet. */
561 rclass
= reg_class_subunion
[rclass
][GENERAL_REGS
];
566 = (reg_class_subunion
568 [reg_class_for_constraint (lookup_constraint (p
))]);
572 /* See if REGNO fits this alternative, and set it up as the
573 replacement register if we don't have one for this
574 alternative yet and the operand being replaced is not
575 a cheap CONST_INT. */
576 if (op_alt_regno
[i
][j
] == -1
577 && TEST_BIT (recog_data
.enabled_alternatives
, j
)
578 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
579 && (!CONST_INT_P (recog_data
.operand
[i
])
580 || (set_src_cost (recog_data
.operand
[i
],
581 optimize_bb_for_speed_p
582 (BLOCK_FOR_INSN (insn
)))
583 > set_src_cost (testreg
,
584 optimize_bb_for_speed_p
585 (BLOCK_FOR_INSN (insn
))))))
587 alternative_nregs
[j
]++;
588 op_alt_regno
[i
][j
] = regno
;
594 p
+= CONSTRAINT_LEN (c
, p
);
602 /* Record all alternatives which are better or equal to the currently
603 matching one in the alternative_order array. */
604 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
605 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
606 alternative_order
[j
++] = i
;
607 recog_data
.n_alternatives
= j
;
609 /* Sort it. Given a small number of alternatives, a dumb algorithm
610 won't hurt too much. */
611 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
614 int best_reject
= alternative_reject
[alternative_order
[i
]];
615 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
618 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
620 int this_reject
= alternative_reject
[alternative_order
[j
]];
621 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
623 if (this_reject
< best_reject
624 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
627 best_reject
= this_reject
;
628 best_nregs
= this_nregs
;
632 tmp
= alternative_order
[best
];
633 alternative_order
[best
] = alternative_order
[i
];
634 alternative_order
[i
] = tmp
;
637 /* Substitute the operands as determined by op_alt_regno for the best
639 j
= alternative_order
[0];
641 for (i
= 0; i
< recog_data
.n_operands
; i
++)
643 enum machine_mode mode
= recog_data
.operand_mode
[i
];
644 if (op_alt_regno
[i
][j
] == -1)
647 validate_change (insn
, recog_data
.operand_loc
[i
],
648 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
651 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
653 int op
= recog_data
.dup_num
[i
];
654 enum machine_mode mode
= recog_data
.operand_mode
[op
];
656 if (op_alt_regno
[op
][j
] == -1)
659 validate_change (insn
, recog_data
.dup_loc
[i
],
660 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
663 return apply_change_group ();
666 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
668 This code might also be useful when reload gave up on reg+reg addressing
669 because of clashes between the return register and INDEX_REG_CLASS. */
671 /* The maximum number of uses of a register we can keep track of to
672 replace them with reg+reg addressing. */
673 #define RELOAD_COMBINE_MAX_USES 16
675 /* Describes a recorded use of a register. */
678 /* The insn where a register has been used. */
680 /* Points to the memory reference enclosing the use, if any, NULL_RTX
683 /* Location of the register within INSN. */
685 /* The reverse uid of the insn. */
689 /* If the register is used in some unknown fashion, USE_INDEX is negative.
690 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
691 indicates where it is first set or clobbered.
692 Otherwise, USE_INDEX is the index of the last encountered use of the
693 register (which is first among these we have seen since we scan backwards).
694 USE_RUID indicates the first encountered, i.e. last, of these uses.
695 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
696 with a constant offset; OFFSET contains this constant in that case.
697 STORE_RUID is always meaningful if we only want to use a value in a
698 register in a different place: it denotes the next insn in the insn
699 stream (i.e. the last encountered) that sets or clobbers the register.
700 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
703 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
709 bool all_offsets_match
;
710 } reg_state
[FIRST_PSEUDO_REGISTER
];
712 /* Reverse linear uid. This is increased in reload_combine while scanning
713 the instructions from last to first. It is used to set last_label_ruid
714 and the store_ruid / use_ruid fields in reg_state. */
715 static int reload_combine_ruid
;
717 /* The RUID of the last label we encountered in reload_combine. */
718 static int last_label_ruid
;
720 /* The RUID of the last jump we encountered in reload_combine. */
721 static int last_jump_ruid
;
723 /* The register numbers of the first and last index register. A value of
724 -1 in LAST_INDEX_REG indicates that we've previously computed these
725 values and found no suitable index registers. */
726 static int first_index_reg
= -1;
727 static int last_index_reg
;
729 #define LABEL_LIVE(LABEL) \
730 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
732 /* Subroutine of reload_combine_split_ruids, called to fix up a single
733 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
736 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
738 if (*pruid
> split_ruid
)
742 /* Called when we insert a new insn in a position we've already passed in
743 the scan. Examine all our state, increasing all ruids that are higher
744 than SPLIT_RUID by one in order to make room for a new insn. */
747 reload_combine_split_ruids (int split_ruid
)
751 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
752 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
753 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
755 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
757 int j
, idx
= reg_state
[i
].use_index
;
758 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
759 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
760 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
764 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
766 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
772 /* Called when we are about to rescan a previously encountered insn with
773 reload_combine_note_use after modifying some part of it. This clears all
774 information about uses in that particular insn. */
777 reload_combine_purge_insn_uses (rtx_insn
*insn
)
781 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
783 int j
, k
, idx
= reg_state
[i
].use_index
;
786 j
= k
= RELOAD_COMBINE_MAX_USES
;
789 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
793 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
796 reg_state
[i
].use_index
= k
;
800 /* Called when we need to forget about all uses of REGNO after an insn
801 which is identified by RUID. */
804 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
806 int j
, k
, idx
= reg_state
[regno
].use_index
;
809 j
= k
= RELOAD_COMBINE_MAX_USES
;
812 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
816 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
819 reg_state
[regno
].use_index
= k
;
822 /* Find the use of REGNO with the ruid that is highest among those
823 lower than RUID_LIMIT, and return it if it is the only use of this
824 reg in the insn. Return NULL otherwise. */
826 static struct reg_use
*
827 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
829 int i
, best_ruid
= 0;
830 int use_idx
= reg_state
[regno
].use_index
;
831 struct reg_use
*retval
;
836 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
838 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
839 int this_ruid
= use
->ruid
;
840 if (this_ruid
>= ruid_limit
)
842 if (this_ruid
> best_ruid
)
844 best_ruid
= this_ruid
;
847 else if (this_ruid
== best_ruid
)
850 if (last_label_ruid
>= best_ruid
)
855 /* After we've moved an add insn, fix up any debug insns that occur
856 between the old location of the add and the new location. REG is
857 the destination register of the add insn; REPLACEMENT is the
858 SET_SRC of the add. FROM and TO specify the range in which we
859 should make this change on debug insns. */
862 fixup_debug_insns (rtx reg
, rtx replacement
, rtx_insn
*from
, rtx_insn
*to
)
865 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
869 if (!DEBUG_INSN_P (insn
))
872 t
= INSN_VAR_LOCATION_LOC (insn
);
873 t
= simplify_replace_rtx (t
, reg
, replacement
);
874 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
878 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
879 with SRC in the insn described by USE, taking costs into account. Return
880 true if we made the replacement. */
883 try_replace_in_use (struct reg_use
*use
, rtx reg
, rtx src
)
885 rtx_insn
*use_insn
= use
->insn
;
886 rtx mem
= use
->containing_mem
;
887 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
891 addr_space_t as
= MEM_ADDR_SPACE (mem
);
892 rtx oldaddr
= XEXP (mem
, 0);
893 rtx newaddr
= NULL_RTX
;
894 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
897 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
898 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
900 XEXP (mem
, 0) = newaddr
;
901 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
902 XEXP (mem
, 0) = oldaddr
;
903 if (new_cost
<= old_cost
904 && validate_change (use_insn
,
905 &XEXP (mem
, 0), newaddr
, 0))
911 rtx new_set
= single_set (use_insn
);
913 && REG_P (SET_DEST (new_set
))
914 && GET_CODE (SET_SRC (new_set
)) == PLUS
915 && REG_P (XEXP (SET_SRC (new_set
), 0))
916 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
919 int old_cost
= set_src_cost (SET_SRC (new_set
), speed
);
921 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
922 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
924 if (set_src_cost (new_src
, speed
) <= old_cost
925 && validate_change (use_insn
, &SET_SRC (new_set
),
933 /* Called by reload_combine when scanning INSN. This function tries to detect
934 patterns where a constant is added to a register, and the result is used
936 Return true if no further processing is needed on INSN; false if it wasn't
937 recognized and should be handled normally. */
940 reload_combine_recognize_const_pattern (rtx_insn
*insn
)
942 int from_ruid
= reload_combine_ruid
;
943 rtx set
, pat
, reg
, src
, addreg
;
947 rtx_insn
*add_moved_after_insn
= NULL
;
948 int add_moved_after_ruid
= 0;
949 int clobbered_regno
= -1;
951 set
= single_set (insn
);
955 reg
= SET_DEST (set
);
958 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1
959 || GET_MODE (reg
) != Pmode
960 || reg
== stack_pointer_rtx
)
965 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
966 uses of REG1 inside an address, or inside another add insn. If
967 possible and profitable, merge the addition into subsequent
969 if (GET_CODE (src
) != PLUS
970 || !REG_P (XEXP (src
, 0))
971 || !CONSTANT_P (XEXP (src
, 1)))
974 addreg
= XEXP (src
, 0);
975 must_move_add
= rtx_equal_p (reg
, addreg
);
977 pat
= PATTERN (insn
);
978 if (must_move_add
&& set
!= pat
)
980 /* We have to be careful when moving the add; apart from the
981 single_set there may also be clobbers. Recognize one special
982 case, that of one clobber alongside the set (likely a clobber
983 of the CC register). */
984 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
985 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
986 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
987 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
989 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
994 use
= reload_combine_closest_single_use (regno
, from_ruid
);
997 /* Start the search for the next use from here. */
998 from_ruid
= use
->ruid
;
1000 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
1002 bool delete_add
= false;
1003 rtx_insn
*use_insn
= use
->insn
;
1004 int use_ruid
= use
->ruid
;
1006 /* Avoid moving the add insn past a jump. */
1007 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
1010 /* If the add clobbers another hard reg in parallel, don't move
1011 it past a real set of this hard reg. */
1012 if (must_move_add
&& clobbered_regno
>= 0
1013 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
1017 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
1018 if (must_move_add
&& sets_cc0_p (PATTERN (use_insn
)))
1022 gcc_assert (reg_state
[regno
].store_ruid
<= use_ruid
);
1023 /* Avoid moving a use of ADDREG past a point where it is stored. */
1024 if (reg_state
[REGNO (addreg
)].store_ruid
> use_ruid
)
1027 /* We also must not move the addition past an insn that sets
1028 the same register, unless we can combine two add insns. */
1029 if (must_move_add
&& reg_state
[regno
].store_ruid
== use_ruid
)
1031 if (use
->containing_mem
== NULL_RTX
)
1037 if (try_replace_in_use (use
, reg
, src
))
1039 reload_combine_purge_insn_uses (use_insn
);
1040 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
1041 use_ruid
, NULL_RTX
);
1045 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1051 add_moved_after_insn
= use_insn
;
1052 add_moved_after_ruid
= use_ruid
;
1057 /* If we get here, we couldn't handle this use. */
1063 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1064 /* Process the add normally. */
1067 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1069 reorder_insns (insn
, insn
, add_moved_after_insn
);
1070 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1071 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1072 reload_combine_note_use (&PATTERN (insn
), insn
,
1073 add_moved_after_ruid
, NULL_RTX
);
1074 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1079 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1080 can handle and improve. Return true if no further processing is needed on
1081 INSN; false if it wasn't recognized and should be handled normally. */
1084 reload_combine_recognize_pattern (rtx_insn
*insn
)
1089 set
= single_set (insn
);
1090 if (set
== NULL_RTX
)
1093 reg
= SET_DEST (set
);
1094 src
= SET_SRC (set
);
1096 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1)
1099 regno
= REGNO (reg
);
1101 /* Look for (set (REGX) (CONST_INT))
1102 (set (REGX) (PLUS (REGX) (REGY)))
1104 ... (MEM (REGX)) ...
1106 (set (REGZ) (CONST_INT))
1108 ... (MEM (PLUS (REGZ) (REGY)))... .
1110 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1111 and that we know all uses of REGX before it dies.
1112 Also, explicitly check that REGX != REGY; our life information
1113 does not yet show whether REGY changes in this insn. */
1115 if (GET_CODE (src
) == PLUS
1116 && reg_state
[regno
].all_offsets_match
1117 && last_index_reg
!= -1
1118 && REG_P (XEXP (src
, 1))
1119 && rtx_equal_p (XEXP (src
, 0), reg
)
1120 && !rtx_equal_p (XEXP (src
, 1), reg
)
1121 && reg_state
[regno
].use_index
>= 0
1122 && reg_state
[regno
].use_index
< RELOAD_COMBINE_MAX_USES
1123 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1125 rtx base
= XEXP (src
, 1);
1126 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
1127 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1128 rtx index_reg
= NULL_RTX
;
1129 rtx reg_sum
= NULL_RTX
;
1132 /* Now we need to set INDEX_REG to an index register (denoted as
1133 REGZ in the illustration above) and REG_SUM to the expression
1134 register+register that we want to use to substitute uses of REG
1135 (typically in MEMs) with. First check REG and BASE for being
1136 index registers; we can use them even if they are not dead. */
1137 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1138 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1146 /* Otherwise, look for a free index register. Since we have
1147 checked above that neither REG nor BASE are index registers,
1148 if we find anything at all, it will be different from these
1150 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1152 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1153 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1154 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1155 && (call_used_regs
[i
] || df_regs_ever_live_p (i
))
1156 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1157 && !fixed_regs
[i
] && !global_regs
[i
]
1158 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1
1159 && targetm
.hard_regno_scratch_ok (i
))
1161 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1162 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1168 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1169 (REGY), i.e. BASE, is not clobbered before the last use we'll
1173 && CONST_INT_P (SET_SRC (prev_set
))
1174 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1175 && (reg_state
[REGNO (base
)].store_ruid
1176 <= reg_state
[regno
].use_ruid
))
1178 /* Change destination register and, if necessary, the constant
1179 value in PREV, the constant loading instruction. */
1180 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1181 if (reg_state
[regno
].offset
!= const0_rtx
)
1182 validate_change (prev
,
1183 &SET_SRC (prev_set
),
1184 GEN_INT (INTVAL (SET_SRC (prev_set
))
1185 + INTVAL (reg_state
[regno
].offset
)),
1188 /* Now for every use of REG that we have recorded, replace REG
1190 for (i
= reg_state
[regno
].use_index
;
1191 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1192 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1193 reg_state
[regno
].reg_use
[i
].usep
,
1194 /* Each change must have its own
1198 if (apply_change_group ())
1200 struct reg_use
*lowest_ruid
= NULL
;
1202 /* For every new use of REG_SUM, we have to record the use
1203 of BASE therein, i.e. operand 1. */
1204 for (i
= reg_state
[regno
].use_index
;
1205 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1207 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1208 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1209 use
->ruid
, use
->containing_mem
);
1210 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1214 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1216 /* Delete the reg-reg addition. */
1219 if (reg_state
[regno
].offset
!= const0_rtx
)
1220 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1222 remove_reg_equal_equiv_notes (prev
);
1224 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1233 reload_combine (void)
1235 rtx_insn
*insn
, *prev
;
1238 int min_labelno
, n_labels
;
1239 HARD_REG_SET ever_live_at_start
, *label_live
;
1241 /* To avoid wasting too much time later searching for an index register,
1242 determine the minimum and maximum index register numbers. */
1243 if (INDEX_REG_CLASS
== NO_REGS
)
1244 last_index_reg
= -1;
1245 else if (first_index_reg
== -1 && last_index_reg
== 0)
1247 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1248 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1250 if (first_index_reg
== -1)
1251 first_index_reg
= r
;
1256 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1257 to -1 so we'll know to quit early the next time we get here. */
1258 if (first_index_reg
== -1)
1260 last_index_reg
= -1;
1265 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1266 information is a bit fuzzy immediately after reload, but it's
1267 still good enough to determine which registers are live at a jump
1269 min_labelno
= get_first_label_num ();
1270 n_labels
= max_label_num () - min_labelno
;
1271 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1272 CLEAR_HARD_REG_SET (ever_live_at_start
);
1274 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
1276 insn
= BB_HEAD (bb
);
1280 bitmap live_in
= df_get_live_in (bb
);
1282 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1283 compute_use_by_pseudos (&live
, live_in
);
1284 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
1285 IOR_HARD_REG_SET (ever_live_at_start
, live
);
1289 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1290 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1291 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1293 reg_state
[r
].store_ruid
= 0;
1294 reg_state
[r
].real_store_ruid
= 0;
1296 reg_state
[r
].use_index
= -1;
1298 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1301 for (insn
= get_last_insn (); insn
; insn
= prev
)
1303 bool control_flow_insn
;
1306 prev
= PREV_INSN (insn
);
1308 /* We cannot do our optimization across labels. Invalidating all the use
1309 information we have would be costly, so we just note where the label
1310 is and then later disable any optimization that would cross it. */
1312 last_label_ruid
= reload_combine_ruid
;
1313 else if (BARRIER_P (insn
))
1315 /* Crossing a barrier resets all the use information. */
1316 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1317 if (! fixed_regs
[r
])
1318 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1320 else if (INSN_P (insn
) && volatile_insn_p (PATTERN (insn
)))
1321 /* Optimizations across insns being marked as volatile must be
1322 prevented. All the usage information is invalidated
1324 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1326 && reg_state
[r
].use_index
!= RELOAD_COMBINE_MAX_USES
)
1327 reg_state
[r
].use_index
= -1;
1329 if (! NONDEBUG_INSN_P (insn
))
1332 reload_combine_ruid
++;
1334 control_flow_insn
= control_flow_insn_p (insn
);
1335 if (control_flow_insn
)
1336 last_jump_ruid
= reload_combine_ruid
;
1338 if (reload_combine_recognize_const_pattern (insn
)
1339 || reload_combine_recognize_pattern (insn
))
1342 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
1348 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1349 if (call_used_regs
[r
])
1351 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1352 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1355 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1356 link
= XEXP (link
, 1))
1358 rtx setuse
= XEXP (link
, 0);
1359 rtx usage_rtx
= XEXP (setuse
, 0);
1360 if ((GET_CODE (setuse
) == USE
|| GET_CODE (setuse
) == CLOBBER
)
1361 && REG_P (usage_rtx
))
1364 unsigned int start_reg
= REGNO (usage_rtx
);
1365 unsigned int num_regs
1366 = hard_regno_nregs
[start_reg
][GET_MODE (usage_rtx
)];
1367 unsigned int end_reg
= start_reg
+ num_regs
- 1;
1368 for (i
= start_reg
; i
<= end_reg
; i
++)
1369 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1371 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1372 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1375 reg_state
[i
].use_index
= -1;
1380 if (control_flow_insn
&& !ANY_RETURN_P (PATTERN (insn
)))
1382 /* Non-spill registers might be used at the call destination in
1383 some unknown fashion, so we have to mark the unknown use. */
1386 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1387 && JUMP_LABEL (insn
))
1389 if (ANY_RETURN_P (JUMP_LABEL (insn
)))
1392 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1395 live
= &ever_live_at_start
;
1398 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1399 if (TEST_HARD_REG_BIT (*live
, r
))
1400 reg_state
[r
].use_index
= -1;
1403 reload_combine_note_use (&PATTERN (insn
), insn
, reload_combine_ruid
,
1406 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1408 if (REG_NOTE_KIND (note
) == REG_INC
&& REG_P (XEXP (note
, 0)))
1410 int regno
= REGNO (XEXP (note
, 0));
1411 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1412 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1413 reg_state
[regno
].use_index
= -1;
1421 /* Check if DST is a register or a subreg of a register; if it is,
1422 update store_ruid, real_store_ruid and use_index in the reg_state
1423 structure accordingly. Called via note_stores from reload_combine. */
1426 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1430 enum machine_mode mode
= GET_MODE (dst
);
1432 if (GET_CODE (dst
) == SUBREG
)
1434 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1435 GET_MODE (SUBREG_REG (dst
)),
1438 dst
= SUBREG_REG (dst
);
1441 /* Some targets do argument pushes without adding REG_INC notes. */
1445 dst
= XEXP (dst
, 0);
1446 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1447 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
1448 || GET_CODE (dst
) == PRE_MODIFY
|| GET_CODE (dst
) == POST_MODIFY
)
1450 regno
= REGNO (XEXP (dst
, 0));
1451 mode
= GET_MODE (XEXP (dst
, 0));
1452 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1454 /* We could probably do better, but for now mark the register
1455 as used in an unknown fashion and set/clobbered at this
1457 reg_state
[i
].use_index
= -1;
1458 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1459 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1468 regno
+= REGNO (dst
);
1470 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1471 careful with registers / register parts that are not full words.
1472 Similarly for ZERO_EXTRACT. */
1473 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1474 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1476 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1478 reg_state
[i
].use_index
= -1;
1479 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1480 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1485 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1487 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1488 if (GET_CODE (set
) == SET
)
1489 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1490 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1495 /* XP points to a piece of rtl that has to be checked for any uses of
1497 *XP is the pattern of INSN, or a part of it.
1498 Called from reload_combine, and recursively by itself. */
1500 reload_combine_note_use (rtx
*xp
, rtx_insn
*insn
, int ruid
, rtx containing_mem
)
1503 enum rtx_code code
= x
->code
;
1506 rtx offset
= const0_rtx
; /* For the REG case below. */
1511 if (REG_P (SET_DEST (x
)))
1513 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1519 /* If this is the USE of a return value, we can't change it. */
1520 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1522 /* Mark the return register as used in an unknown fashion. */
1523 rtx reg
= XEXP (x
, 0);
1524 int regno
= REGNO (reg
);
1525 int nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1527 while (--nregs
>= 0)
1528 reg_state
[regno
+ nregs
].use_index
= -1;
1534 if (REG_P (SET_DEST (x
)))
1536 /* No spurious CLOBBERs of pseudo registers may remain. */
1537 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1543 /* We are interested in (plus (reg) (const_int)) . */
1544 if (!REG_P (XEXP (x
, 0))
1545 || !CONST_INT_P (XEXP (x
, 1)))
1547 offset
= XEXP (x
, 1);
1552 int regno
= REGNO (x
);
1556 /* No spurious USEs of pseudo registers may remain. */
1557 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1559 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1561 /* We can't substitute into multi-hard-reg uses. */
1564 while (--nregs
>= 0)
1565 reg_state
[regno
+ nregs
].use_index
= -1;
1569 /* We may be called to update uses in previously seen insns.
1570 Don't add uses beyond the last store we saw. */
1571 if (ruid
< reg_state
[regno
].store_ruid
)
1574 /* If this register is already used in some unknown fashion, we
1576 If we decrement the index from zero to -1, we can't store more
1577 uses, so this register becomes used in an unknown fashion. */
1578 use_index
= --reg_state
[regno
].use_index
;
1582 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1584 /* This is the first use of this register we have seen since we
1585 marked it as dead. */
1586 reg_state
[regno
].offset
= offset
;
1587 reg_state
[regno
].all_offsets_match
= true;
1588 reg_state
[regno
].use_ruid
= ruid
;
1592 if (reg_state
[regno
].use_ruid
> ruid
)
1593 reg_state
[regno
].use_ruid
= ruid
;
1595 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1596 reg_state
[regno
].all_offsets_match
= false;
1599 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1600 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1601 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1602 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1614 /* Recursively process the components of X. */
1615 fmt
= GET_RTX_FORMAT (code
);
1616 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1619 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1620 else if (fmt
[i
] == 'E')
1622 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1623 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1629 /* See if we can reduce the cost of a constant by replacing a move
1630 with an add. We track situations in which a register is set to a
1631 constant or to a register plus a constant. */
1632 /* We cannot do our optimization across labels. Invalidating all the
1633 information about register contents we have would be costly, so we
1634 use move2add_last_label_luid to note where the label is and then
1635 later disable any optimization that would cross it.
1636 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1637 are only valid if reg_set_luid[n] is greater than
1638 move2add_last_label_luid.
1639 For a set that established a new (potential) base register with
1640 non-constant value, we use move2add_luid from the place where the
1641 setting insn is encountered; registers based off that base then
1642 get the same reg_set_luid. Constants all get
1643 move2add_last_label_luid + 1 as their reg_set_luid. */
1644 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1646 /* If reg_base_reg[n] is negative, register n has been set to
1647 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1648 If reg_base_reg[n] is non-negative, register n has been set to the
1649 sum of reg_offset[n] and the value of register reg_base_reg[n]
1650 before reg_set_luid[n], calculated in mode reg_mode[n] .
1651 For multi-hard-register registers, all but the first one are
1652 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1653 marks it as invalid. */
1654 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1655 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1656 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1657 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1659 /* move2add_luid is linearly increased while scanning the instructions
1660 from first to last. It is used to set reg_set_luid in
1661 reload_cse_move2add and move2add_note_store. */
1662 static int move2add_luid
;
1664 /* move2add_last_label_luid is set whenever a label is found. Labels
1665 invalidate all previously collected reg_offset data. */
1666 static int move2add_last_label_luid
;
1668 /* ??? We don't know how zero / sign extension is handled, hence we
1669 can't go from a narrower to a wider mode. */
1670 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1671 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1672 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1673 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1675 /* Record that REG is being set to a value with the mode of REG. */
1678 move2add_record_mode (rtx reg
)
1681 enum machine_mode mode
= GET_MODE (reg
);
1683 if (GET_CODE (reg
) == SUBREG
)
1685 regno
= subreg_regno (reg
);
1686 nregs
= subreg_nregs (reg
);
1688 else if (REG_P (reg
))
1690 regno
= REGNO (reg
);
1691 nregs
= hard_regno_nregs
[regno
][mode
];
1695 for (int i
= nregs
- 1; i
> 0; i
--)
1696 reg_mode
[regno
+ i
] = BLKmode
;
1697 reg_mode
[regno
] = mode
;
1700 /* Record that REG is being set to the sum of SYM and OFF. */
1703 move2add_record_sym_value (rtx reg
, rtx sym
, rtx off
)
1705 int regno
= REGNO (reg
);
1707 move2add_record_mode (reg
);
1708 reg_set_luid
[regno
] = move2add_luid
;
1709 reg_base_reg
[regno
] = -1;
1710 reg_symbol_ref
[regno
] = sym
;
1711 reg_offset
[regno
] = INTVAL (off
);
1714 /* Check if REGNO contains a valid value in MODE. */
1717 move2add_valid_value_p (int regno
, enum machine_mode mode
)
1719 if (reg_set_luid
[regno
] <= move2add_last_label_luid
)
1722 if (mode
!= reg_mode
[regno
])
1724 if (!MODES_OK_FOR_MOVE2ADD (mode
, reg_mode
[regno
]))
1726 /* The value loaded into regno in reg_mode[regno] is also valid in
1727 mode after truncation only if (REG:mode regno) is the lowpart of
1728 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1729 regno of the lowpart might be different. */
1730 int s_off
= subreg_lowpart_offset (mode
, reg_mode
[regno
]);
1731 s_off
= subreg_regno_offset (regno
, reg_mode
[regno
], s_off
, mode
);
1733 /* We could in principle adjust regno, check reg_mode[regno] to be
1734 BLKmode, and return s_off to the caller (vs. -1 for failure),
1735 but we currently have no callers that could make use of this
1740 for (int i
= hard_regno_nregs
[regno
][mode
] - 1; i
> 0; i
--)
1741 if (reg_mode
[regno
+ i
] != BLKmode
)
1746 /* This function is called with INSN that sets REG to (SYM + OFF),
1747 while REG is known to already have value (SYM + offset).
1748 This function tries to change INSN into an add instruction
1749 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1750 It also updates the information about REG's known value.
1751 Return true if we made a change. */
1754 move2add_use_add2_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1756 rtx pat
= PATTERN (insn
);
1757 rtx src
= SET_SRC (pat
);
1758 int regno
= REGNO (reg
);
1759 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[regno
],
1761 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1762 bool changed
= false;
1764 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1765 use (set (reg) (reg)) instead.
1766 We don't delete this insn, nor do we convert it into a
1767 note, to avoid losing register notes or the return
1768 value flag. jump2 already knows how to get rid of
1770 if (new_src
== const0_rtx
)
1772 /* If the constants are different, this is a
1773 truncation, that, if turned into (set (reg)
1774 (reg)), would be discarded. Maybe we should
1775 try a truncMN pattern? */
1776 if (INTVAL (off
) == reg_offset
[regno
])
1777 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1781 struct full_rtx_costs oldcst
, newcst
;
1782 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1784 get_full_set_rtx_cost (pat
, &oldcst
);
1785 SET_SRC (pat
) = tem
;
1786 get_full_set_rtx_cost (pat
, &newcst
);
1787 SET_SRC (pat
) = src
;
1789 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1790 && have_add2_insn (reg
, new_src
))
1791 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1792 else if (sym
== NULL_RTX
&& GET_MODE (reg
) != BImode
)
1794 enum machine_mode narrow_mode
;
1795 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1796 narrow_mode
!= VOIDmode
1797 && narrow_mode
!= GET_MODE (reg
);
1798 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1800 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1801 && ((reg_offset
[regno
] & ~GET_MODE_MASK (narrow_mode
))
1802 == (INTVAL (off
) & ~GET_MODE_MASK (narrow_mode
))))
1804 rtx narrow_reg
= gen_lowpart_common (narrow_mode
, reg
);
1805 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1808 = gen_rtx_SET (VOIDmode
,
1809 gen_rtx_STRICT_LOW_PART (VOIDmode
,
1812 get_full_set_rtx_cost (new_set
, &newcst
);
1813 if (costs_lt_p (&newcst
, &oldcst
, speed
))
1815 changed
= validate_change (insn
, &PATTERN (insn
),
1824 move2add_record_sym_value (reg
, sym
, off
);
1829 /* This function is called with INSN that sets REG to (SYM + OFF),
1830 but REG doesn't have known value (SYM + offset). This function
1831 tries to find another register which is known to already have
1832 value (SYM + offset) and change INSN into an add instruction
1833 (set (REG) (plus (the found register) (OFF - offset))) if such
1834 a register is found. It also updates the information about
1836 Return true iff we made a change. */
1839 move2add_use_add3_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1841 rtx pat
= PATTERN (insn
);
1842 rtx src
= SET_SRC (pat
);
1843 int regno
= REGNO (reg
);
1845 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1847 bool changed
= false;
1848 struct full_rtx_costs oldcst
, newcst
, mincst
;
1851 init_costs_to_max (&mincst
);
1852 get_full_set_rtx_cost (pat
, &oldcst
);
1854 plus_expr
= gen_rtx_PLUS (GET_MODE (reg
), reg
, const0_rtx
);
1855 SET_SRC (pat
) = plus_expr
;
1857 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1858 if (move2add_valid_value_p (i
, GET_MODE (reg
))
1859 && reg_base_reg
[i
] < 0
1860 && reg_symbol_ref
[i
] != NULL_RTX
1861 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1863 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[i
],
1865 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1866 use (set (reg) (reg)) instead.
1867 We don't delete this insn, nor do we convert it into a
1868 note, to avoid losing register notes or the return
1869 value flag. jump2 already knows how to get rid of
1871 if (new_src
== const0_rtx
)
1873 init_costs_to_zero (&mincst
);
1879 XEXP (plus_expr
, 1) = new_src
;
1880 get_full_set_rtx_cost (pat
, &newcst
);
1882 if (costs_lt_p (&newcst
, &mincst
, speed
))
1889 SET_SRC (pat
) = src
;
1891 if (costs_lt_p (&mincst
, &oldcst
, speed
))
1895 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1898 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[min_regno
],
1900 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1902 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1905 reg_set_luid
[regno
] = move2add_luid
;
1906 move2add_record_sym_value (reg
, sym
, off
);
1910 /* Convert move insns with constant inputs to additions if they are cheaper.
1911 Return true if any changes were made. */
1913 reload_cse_move2add (rtx_insn
*first
)
1917 bool changed
= false;
1919 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1921 reg_set_luid
[i
] = 0;
1923 reg_base_reg
[i
] = 0;
1924 reg_symbol_ref
[i
] = NULL_RTX
;
1925 reg_mode
[i
] = VOIDmode
;
1928 move2add_last_label_luid
= 0;
1930 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1936 move2add_last_label_luid
= move2add_luid
;
1937 /* We're going to increment move2add_luid twice after a
1938 label, so that we can use move2add_last_label_luid + 1 as
1939 the luid for constants. */
1943 if (! INSN_P (insn
))
1945 pat
= PATTERN (insn
);
1946 /* For simplicity, we only perform this optimization on
1947 straightforward SETs. */
1948 if (GET_CODE (pat
) == SET
1949 && REG_P (SET_DEST (pat
)))
1951 rtx reg
= SET_DEST (pat
);
1952 int regno
= REGNO (reg
);
1953 rtx src
= SET_SRC (pat
);
1955 /* Check if we have valid information on the contents of this
1956 register in the mode of REG. */
1957 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
1958 && dbg_cnt (cse2_move2add
))
1960 /* Try to transform (set (REGX) (CONST_INT A))
1962 (set (REGX) (CONST_INT B))
1964 (set (REGX) (CONST_INT A))
1966 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1968 (set (REGX) (CONST_INT A))
1970 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1973 if (CONST_INT_P (src
)
1974 && reg_base_reg
[regno
] < 0
1975 && reg_symbol_ref
[regno
] == NULL_RTX
)
1977 changed
|= move2add_use_add2_insn (reg
, NULL_RTX
, src
, insn
);
1981 /* Try to transform (set (REGX) (REGY))
1982 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1985 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1988 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1990 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1991 else if (REG_P (src
)
1992 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1993 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1994 && move2add_valid_value_p (REGNO (src
), GET_MODE (reg
)))
1996 rtx_insn
*next
= next_nonnote_nondebug_insn (insn
);
1999 set
= single_set (next
);
2001 && SET_DEST (set
) == reg
2002 && GET_CODE (SET_SRC (set
)) == PLUS
2003 && XEXP (SET_SRC (set
), 0) == reg
2004 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
2006 rtx src3
= XEXP (SET_SRC (set
), 1);
2007 unsigned HOST_WIDE_INT added_offset
= UINTVAL (src3
);
2008 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
2009 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
2011 gen_int_mode (added_offset
2015 bool success
= false;
2016 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
2018 if (new_src
== const0_rtx
)
2019 /* See above why we create (set (reg) (reg)) here. */
2021 = validate_change (next
, &SET_SRC (set
), reg
, 0);
2024 rtx old_src
= SET_SRC (set
);
2025 struct full_rtx_costs oldcst
, newcst
;
2026 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
2028 get_full_set_rtx_cost (set
, &oldcst
);
2029 SET_SRC (set
) = tem
;
2030 get_full_set_src_cost (tem
, &newcst
);
2031 SET_SRC (set
) = old_src
;
2032 costs_add_n_insns (&oldcst
, 1);
2034 if (costs_lt_p (&newcst
, &oldcst
, speed
)
2035 && have_add2_insn (reg
, new_src
))
2037 rtx newpat
= gen_rtx_SET (VOIDmode
, reg
, tem
);
2039 = validate_change (next
, &PATTERN (next
),
2047 move2add_record_mode (reg
);
2049 = trunc_int_for_mode (added_offset
+ base_offset
,
2057 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2059 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2061 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2063 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2064 if ((GET_CODE (src
) == SYMBOL_REF
2065 || (GET_CODE (src
) == CONST
2066 && GET_CODE (XEXP (src
, 0)) == PLUS
2067 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
2068 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
2069 && dbg_cnt (cse2_move2add
))
2073 if (GET_CODE (src
) == SYMBOL_REF
)
2080 sym
= XEXP (XEXP (src
, 0), 0);
2081 off
= XEXP (XEXP (src
, 0), 1);
2084 /* If the reg already contains the value which is sum of
2085 sym and some constant value, we can use an add2 insn. */
2086 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
2087 && reg_base_reg
[regno
] < 0
2088 && reg_symbol_ref
[regno
] != NULL_RTX
2089 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
2090 changed
|= move2add_use_add2_insn (reg
, sym
, off
, insn
);
2092 /* Otherwise, we have to find a register whose value is sum
2093 of sym and some constant value. */
2095 changed
|= move2add_use_add3_insn (reg
, sym
, off
, insn
);
2101 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2103 if (REG_NOTE_KIND (note
) == REG_INC
2104 && REG_P (XEXP (note
, 0)))
2106 /* Reset the information about this register. */
2107 int regno
= REGNO (XEXP (note
, 0));
2108 if (regno
< FIRST_PSEUDO_REGISTER
)
2110 move2add_record_mode (XEXP (note
, 0));
2111 reg_mode
[regno
] = VOIDmode
;
2115 note_stores (PATTERN (insn
), move2add_note_store
, insn
);
2117 /* If INSN is a conditional branch, we try to extract an
2118 implicit set out of it. */
2119 if (any_condjump_p (insn
))
2121 rtx cnd
= fis_get_condition (insn
);
2124 && GET_CODE (cnd
) == NE
2125 && REG_P (XEXP (cnd
, 0))
2126 && !reg_set_p (XEXP (cnd
, 0), insn
)
2127 /* The following two checks, which are also in
2128 move2add_note_store, are intended to reduce the
2129 number of calls to gen_rtx_SET to avoid memory
2130 allocation if possible. */
2131 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
2132 && hard_regno_nregs
[REGNO (XEXP (cnd
, 0))][GET_MODE (XEXP (cnd
, 0))] == 1
2133 && CONST_INT_P (XEXP (cnd
, 1)))
2136 gen_rtx_SET (VOIDmode
, XEXP (cnd
, 0), XEXP (cnd
, 1));
2137 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
2141 /* If this is a CALL_INSN, all call used registers are stored with
2145 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
2147 if (call_used_regs
[i
])
2148 /* Reset the information about this register. */
2149 reg_mode
[i
] = VOIDmode
;
2156 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2158 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2159 Called from reload_cse_move2add via note_stores. */
2162 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2164 rtx_insn
*insn
= (rtx_insn
*) data
;
2165 unsigned int regno
= 0;
2166 enum machine_mode mode
= GET_MODE (dst
);
2168 /* Some targets do argument pushes without adding REG_INC notes. */
2172 dst
= XEXP (dst
, 0);
2173 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2174 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2175 reg_mode
[REGNO (XEXP (dst
, 0))] = VOIDmode
;
2179 if (GET_CODE (dst
) == SUBREG
)
2180 regno
= subreg_regno (dst
);
2181 else if (REG_P (dst
))
2182 regno
= REGNO (dst
);
2186 if (SCALAR_INT_MODE_P (mode
)
2187 && GET_CODE (set
) == SET
)
2189 rtx note
, sym
= NULL_RTX
;
2192 note
= find_reg_equal_equiv_note (insn
);
2193 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2195 sym
= XEXP (note
, 0);
2198 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2199 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2200 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2201 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2203 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2204 off
= XEXP (XEXP (XEXP (note
, 0), 0), 1);
2207 if (sym
!= NULL_RTX
)
2209 move2add_record_sym_value (dst
, sym
, off
);
2214 if (SCALAR_INT_MODE_P (mode
)
2215 && GET_CODE (set
) == SET
2216 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2217 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2219 rtx src
= SET_SRC (set
);
2221 unsigned HOST_WIDE_INT offset
;
2224 switch (GET_CODE (src
))
2227 if (REG_P (XEXP (src
, 0)))
2229 base_reg
= XEXP (src
, 0);
2231 if (CONST_INT_P (XEXP (src
, 1)))
2232 offset
= UINTVAL (XEXP (src
, 1));
2233 else if (REG_P (XEXP (src
, 1))
2234 && move2add_valid_value_p (REGNO (XEXP (src
, 1)), mode
))
2236 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0
2237 && reg_symbol_ref
[REGNO (XEXP (src
, 1))] == NULL_RTX
)
2238 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2239 /* Maybe the first register is known to be a
2241 else if (move2add_valid_value_p (REGNO (base_reg
), mode
)
2242 && reg_base_reg
[REGNO (base_reg
)] < 0
2243 && reg_symbol_ref
[REGNO (base_reg
)] == NULL_RTX
)
2245 offset
= reg_offset
[REGNO (base_reg
)];
2246 base_reg
= XEXP (src
, 1);
2265 /* Start tracking the register as a constant. */
2266 reg_base_reg
[regno
] = -1;
2267 reg_symbol_ref
[regno
] = NULL_RTX
;
2268 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2269 /* We assign the same luid to all registers set to constants. */
2270 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2271 move2add_record_mode (dst
);
2278 base_regno
= REGNO (base_reg
);
2279 /* If information about the base register is not valid, set it
2280 up as a new base register, pretending its value is known
2281 starting from the current insn. */
2282 if (!move2add_valid_value_p (base_regno
, mode
))
2284 reg_base_reg
[base_regno
] = base_regno
;
2285 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2286 reg_offset
[base_regno
] = 0;
2287 reg_set_luid
[base_regno
] = move2add_luid
;
2288 gcc_assert (GET_MODE (base_reg
) == mode
);
2289 move2add_record_mode (base_reg
);
2292 /* Copy base information from our base register. */
2293 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2294 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2295 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2297 /* Compute the sum of the offsets or constants. */
2299 = trunc_int_for_mode (offset
+ reg_offset
[base_regno
], mode
);
2301 move2add_record_mode (dst
);
2306 /* Invalidate the contents of the register. */
2307 move2add_record_mode (dst
);
2308 reg_mode
[regno
] = VOIDmode
;
2314 const pass_data pass_data_postreload_cse
=
2316 RTL_PASS
, /* type */
2317 "postreload", /* name */
2318 OPTGROUP_NONE
, /* optinfo_flags */
2319 TV_RELOAD_CSE_REGS
, /* tv_id */
2320 0, /* properties_required */
2321 0, /* properties_provided */
2322 0, /* properties_destroyed */
2323 0, /* todo_flags_start */
2324 TODO_df_finish
, /* todo_flags_finish */
2327 class pass_postreload_cse
: public rtl_opt_pass
2330 pass_postreload_cse (gcc::context
*ctxt
)
2331 : rtl_opt_pass (pass_data_postreload_cse
, ctxt
)
2334 /* opt_pass methods: */
2335 virtual bool gate (function
*) { return (optimize
> 0 && reload_completed
); }
2337 virtual unsigned int execute (function
*);
2339 }; // class pass_postreload_cse
2342 pass_postreload_cse::execute (function
*fun
)
2344 if (!dbg_cnt (postreload_cse
))
2347 /* Do a very simple CSE pass over just the hard registers. */
2348 reload_cse_regs (get_insns ());
2349 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2350 Remove any EH edges associated with them. */
2351 if (fun
->can_throw_non_call_exceptions
2352 && purge_all_dead_edges ())
2361 make_pass_postreload_cse (gcc::context
*ctxt
)
2363 return new pass_postreload_cse (ctxt
);