1 ;; Predicate definitions for Renesas H8/300.
2 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return true if OP is a valid source operand for an integer move
23 (define_predicate "general_operand_src"
24 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
26 if (GET_MODE (op) == mode
27 && GET_CODE (op) == MEM
28 && GET_CODE (XEXP (op, 0)) == POST_INC)
30 return general_operand (op, mode);
33 ;; Return true if OP is a valid destination operand for an integer
36 (define_predicate "general_operand_dst"
37 (match_code "subreg,reg,mem")
39 if (GET_MODE (op) == mode
40 && GET_CODE (op) == MEM
41 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
43 return general_operand (op, mode);
46 ;; Likewise the second operand.
48 (define_predicate "h8300_src_operand"
49 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
52 return general_operand (op, mode);
53 return nonmemory_operand (op, mode);
56 ;; Return true if OP is a suitable first operand for a general
57 ;; arithmetic insn such as "add".
59 (define_predicate "h8300_dst_operand"
60 (match_code "subreg,reg,mem")
63 return nonimmediate_operand (op, mode);
64 return register_operand (op, mode);
67 ;; Check that an operand is either a register or an unsigned 4-bit
70 (define_predicate "nibble_operand"
71 (match_code "const_int")
73 return (GET_CODE (op) == CONST_INT && TARGET_H8300SX
74 && INTVAL (op) >= 0 && INTVAL (op) <= 15);
77 ;; Check that an operand is either a register or an unsigned 4-bit
80 (define_predicate "reg_or_nibble_operand"
81 (match_code "const_int,subreg,reg")
83 return (nibble_operand (op, mode) || register_operand (op, mode));
86 ;; Return true if X is a shift operation of type H8SX_SHIFT_UNARY.
88 (define_predicate "h8sx_unary_shift_operator"
89 (match_code "ashiftrt,lshiftrt,ashift,rotate")
91 return (BINARY_P (op) && NON_COMMUTATIVE_P (op)
92 && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1))
93 == H8SX_SHIFT_UNARY));
96 ;; Likewise H8SX_SHIFT_BINARY.
98 (define_predicate "h8sx_binary_shift_operator"
99 (match_code "ashiftrt,lshiftrt,ashift")
101 return (BINARY_P (op) && NON_COMMUTATIVE_P (op)
102 && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1))
103 == H8SX_SHIFT_BINARY));
106 ;; Return true if OP is a binary operator in which it would be safe to
107 ;; replace register operands with memory operands.
109 (define_predicate "h8sx_binary_memory_operator"
110 (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt,rotate")
115 if (GET_MODE (op) != QImode
116 && GET_MODE (op) != HImode
117 && GET_MODE (op) != SImode)
120 switch (GET_CODE (op))
130 return h8sx_unary_shift_operator (op, mode);
134 ;; Like h8sx_binary_memory_operator, but applies to unary operators.
136 (define_predicate "h8sx_unary_memory_operator"
137 (match_code "neg,not")
142 if (GET_MODE (op) != QImode
143 && GET_MODE (op) != HImode
144 && GET_MODE (op) != SImode)
147 switch (GET_CODE (op))
158 ;; Return true if X is an ldm.l pattern. X is known to be parallel.
160 (define_predicate "h8300_ldm_parallel"
161 (match_code "parallel")
163 return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 0);
168 (define_predicate "h8300_stm_parallel"
169 (match_code "parallel")
171 return h8300_ldm_stm_parallel (XVEC (op, 0), 0, 0);
174 ;; Likewise rts/l and rte/l. Note that the .md pattern will check for
175 ;; the return so there's no need to do that here.
177 (define_predicate "h8300_return_parallel"
178 (match_code "parallel")
180 return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 1);
183 ;; Return true if OP is a constant that contains only one 1 in its
184 ;; binary representation.
186 (define_predicate "single_one_operand"
187 (match_code "const_int")
189 if (GET_CODE (op) == CONST_INT)
191 /* We really need to do this masking because 0x80 in QImode is
192 represented as -128 for example. */
193 if (exact_log2 (INTVAL (op) & GET_MODE_MASK (mode)) >= 0)
200 ;; Return true if OP is a constant that contains only one 0 in its
201 ;; binary representation.
203 (define_predicate "single_zero_operand"
204 (match_code "const_int")
206 if (GET_CODE (op) == CONST_INT)
208 /* We really need to do this masking because 0x80 in QImode is
209 represented as -128 for example. */
210 if (exact_log2 (~INTVAL (op) & GET_MODE_MASK (mode)) >= 0)
217 ;; Return true if OP is a valid call operand.
219 (define_predicate "call_insn_operand"
222 if (GET_CODE (op) == MEM)
224 rtx inside = XEXP (op, 0);
225 if (register_operand (inside, Pmode))
227 if (CONSTANT_ADDRESS_P (inside))
233 ;; Return true if OP is a valid call operand, and OP represents an
234 ;; operand for a small call (4 bytes instead of 6 bytes).
236 (define_predicate "small_call_insn_operand"
239 if (GET_CODE (op) == MEM)
241 rtx inside = XEXP (op, 0);
243 /* Register indirect is a small call. */
244 if (register_operand (inside, Pmode))
247 /* A call through the function vector is a small call too. */
248 if (GET_CODE (inside) == SYMBOL_REF
249 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
252 /* Otherwise it's a large call. */
256 ;; Return true if OP is a valid jump operand.
258 (define_predicate "jump_address_operand"
259 (match_code "reg,mem")
261 if (GET_CODE (op) == REG)
262 return GET_MODE (op) == Pmode;
264 if (GET_CODE (op) == MEM)
266 rtx inside = XEXP (op, 0);
267 if (register_operand (inside, Pmode))
269 if (CONSTANT_ADDRESS_P (inside))
275 ;; Return 1 if an addition/subtraction of a constant integer can be
276 ;; transformed into two consecutive adds/subs that are faster than the
277 ;; straightforward way. Otherwise, return 0.
279 (define_predicate "two_insn_adds_subs_operand"
280 (match_code "const_int")
285 if (GET_CODE (op) == CONST_INT)
287 HOST_WIDE_INT value = INTVAL (op);
289 /* Force VALUE to be positive so that we do not have to consider
290 the negative case. */
293 if (TARGET_H8300H || TARGET_H8300S)
295 /* A constant addition/subtraction takes 2 states in QImode,
296 4 states in HImode, and 6 states in SImode. Thus, the
297 only case we can win is when SImode is used, in which
298 case, two adds/subs are used, taking 4 states. */
308 /* We do not profit directly by splitting addition or
309 subtraction of 3 and 4. However, since these are
310 implemented as a sequence of adds or subs, they do not
311 clobber (cc0) unlike a sequence of add.b and add.x. */
322 ;; Recognize valid operands for bit-field instructions.
324 (define_predicate "bit_operand"
325 (match_code "reg,subreg,mem")
327 /* We can accept any nonimmediate operand, except that MEM operands must
328 be limited to those that use addresses valid for the 'U' constraint. */
329 if (!nonimmediate_operand (op, mode) && !satisfies_constraint_U (op))
332 /* H8SX accepts pretty much anything here. */
336 /* Accept any mem during RTL generation. Otherwise, the code that does
337 insv and extzv will think that we cannot handle memory. However,
338 to avoid reload problems, we only accept 'U' MEM operands after RTL
339 generation. This means that any named pattern which uses this predicate
340 must force its operands to match 'U' before emitting RTL. */
342 if (GET_CODE (op) == REG)
344 if (GET_CODE (op) == SUBREG)
346 return (GET_CODE (op) == MEM
347 && satisfies_constraint_U (op));
350 ;; Return nonzero if OP is a MEM suitable for bit manipulation insns.
352 (define_predicate "bit_memory_operand"
355 return (GET_CODE (op) == MEM
356 && satisfies_constraint_U (op));
359 ;; Return nonzero if OP is indirect register or constant memory
360 ;; suitable for bit manipulation insns.
362 (define_predicate "bit_register_indirect_operand"
365 return (GET_CODE (op) == MEM
366 && (GET_CODE (XEXP (op, 0)) == REG
367 || GET_CODE (XEXP (op, 0)) == CONST_INT));
370 ;; Return nonzero if X is a stack pointer.
372 (define_predicate "stack_pointer_operand"
375 return op == stack_pointer_rtx;
378 ;; False if X is anything that might eliminate to the stack pointer.
380 (define_predicate "register_no_sp_elim_operand"
381 (match_operand 0 "register_operand")
383 if (GET_CODE (op) == SUBREG)
384 op = SUBREG_REG (op);
385 return !(op == stack_pointer_rtx
386 || op == arg_pointer_rtx
387 || op == frame_pointer_rtx
388 || IN_RANGE (REGNO (op),
389 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
392 ;; Return nonzero if X is a constant whose absolute value is greater
395 (define_predicate "const_int_gt_2_operand"
396 (match_code "const_int")
398 return (GET_CODE (op) == CONST_INT
399 && abs (INTVAL (op)) > 2);
402 ;; Return nonzero if X is a constant whose absolute value is no
405 (define_predicate "const_int_ge_8_operand"
406 (match_code "const_int")
408 return (GET_CODE (op) == CONST_INT
409 && abs (INTVAL (op)) >= 8);
412 ;; Return nonzero if X is a constant expressible in QImode.
414 (define_predicate "const_int_qi_operand"
415 (match_code "const_int")
417 return (GET_CODE (op) == CONST_INT
418 && (INTVAL (op) & 0xff) == INTVAL (op));
421 ;; Return nonzero if X is a constant expressible in HImode.
423 (define_predicate "const_int_hi_operand"
424 (match_code "const_int")
426 return (GET_CODE (op) == CONST_INT
427 && (INTVAL (op) & 0xffff) == INTVAL (op));
430 ;; Return nonzero if X is a constant suitable for inc/dec.
432 (define_predicate "incdec_operand"
433 (and (match_code "const_int")
434 (ior (match_test "satisfies_constraint_M (op)")
435 (match_test "satisfies_constraint_O (op)"))))
437 ;; Recognize valid operators for bit instructions.
439 (define_predicate "bit_operator"
440 (match_code "xor,and,ior")
442 enum rtx_code code = GET_CODE (op);
449 ;; Return nonzero if OP is a shift operator.
451 (define_predicate "nshift_operator"
452 (match_code "ashiftrt,lshiftrt,ashift")
454 switch (GET_CODE (op))
466 ;; Return nonzero if X is either EQ or NE.
468 (define_predicate "eqne_operator"
471 enum rtx_code code = GET_CODE (op);
473 return (code == EQ || code == NE);
476 ;; Return nonzero if X is either GT or LE.
478 (define_predicate "gtle_operator"
479 (match_code "gt,le,gtu,leu")
481 enum rtx_code code = GET_CODE (op);
483 return (code == GT || code == LE);
486 ;; Return nonzero if X is either GTU or LEU.
488 (define_predicate "gtuleu_operator"
489 (match_code "gtu,leu")
491 enum rtx_code code = GET_CODE (op);
493 return (code == GTU || code == LEU);
496 ;; Return nonzero if X is either IOR or XOR.
498 (define_predicate "iorxor_operator"
499 (match_code "ior,xor")
501 enum rtx_code code = GET_CODE (op);
503 return (code == IOR || code == XOR);