1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2017 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
32 #include "stringpool.h"
37 #include "diagnostic-core.h"
39 #include "stor-layout.h"
42 #include "conditions.h"
44 #include "insn-attr.h"
48 #include "tm-constrs.h"
51 /* This file should be included last. */
52 #include "target-def.h"
54 /* Classifies a h8300_src_operand or h8300_dst_operand.
57 A constant operand of some sort.
63 A memory reference with a constant address.
66 A memory reference with a register as its address.
69 Some other kind of memory reference. */
70 enum h8300_operand_class
80 /* For a general two-operand instruction, element [X][Y] gives
81 the length of the opcode fields when the first operand has class
82 (X + 1) and the second has class Y. */
83 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
85 /* Forward declarations. */
86 static const char *byte_reg (rtx
, int);
87 static int h8300_interrupt_function_p (tree
);
88 static int h8300_saveall_function_p (tree
);
89 static int h8300_monitor_function_p (tree
);
90 static int h8300_os_task_function_p (tree
);
91 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
92 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
93 static unsigned int compute_saved_regs (void);
94 static const char *cond_string (enum rtx_code
);
95 static unsigned int h8300_asm_insn_count (const char *);
96 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
97 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
98 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
99 static void h8300_print_operand_address (FILE *, machine_mode
, rtx
);
100 static void h8300_print_operand (FILE *, rtx
, int);
101 static bool h8300_print_operand_punct_valid_p (unsigned char code
);
102 #ifndef OBJECT_FORMAT_ELF
103 static void h8300_asm_named_section (const char *, unsigned int, tree
);
105 static int h8300_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
106 static int h8300_and_costs (rtx
);
107 static int h8300_shift_costs (rtx
);
108 static void h8300_push_pop (int, int, bool, bool);
109 static int h8300_stack_offset_p (rtx
, int);
110 static int h8300_ldm_stm_regno (rtx
, int, int, int);
111 static void h8300_reorg (void);
112 static unsigned int h8300_constant_length (rtx
);
113 static unsigned int h8300_displacement_length (rtx
, int);
114 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
115 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
116 static unsigned int h8300_unary_length (rtx
);
117 static unsigned int h8300_short_immediate_length (rtx
);
118 static unsigned int h8300_bitfield_length (rtx
, rtx
);
119 static unsigned int h8300_binary_length (rtx_insn
*, const h8300_length_table
*);
120 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
121 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
122 static bool h8300_hard_regno_scratch_ok (unsigned int);
123 static rtx
h8300_get_index (rtx
, machine_mode mode
, int *);
125 /* CPU_TYPE, says what cpu we're compiling for. */
128 /* True if a #pragma interrupt has been seen for the current function. */
129 static int pragma_interrupt
;
131 /* True if a #pragma saveall has been seen for the current function. */
132 static int pragma_saveall
;
134 static const char *const names_big
[] =
135 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
137 static const char *const names_extended
[] =
138 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
140 static const char *const names_upper_extended
[] =
141 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
143 /* Points to one of the above. */
144 /* ??? The above could be put in an array indexed by CPU_TYPE. */
145 const char * const *h8_reg_names
;
147 /* Various operations needed by the following, indexed by CPU_TYPE. */
149 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
151 /* Value of MOVE_RATIO. */
152 int h8300_move_ratio
;
154 /* See below where shifts are handled for explanation of this enum. */
164 /* Symbols of the various shifts which can be used as indices. */
168 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
171 /* Macros to keep the shift algorithm tables small. */
172 #define INL SHIFT_INLINE
173 #define ROT SHIFT_ROT_AND
174 #define LOP SHIFT_LOOP
175 #define SPC SHIFT_SPECIAL
177 /* The shift algorithms for each machine, mode, shift type, and shift
178 count are defined below. The three tables below correspond to
179 QImode, HImode, and SImode, respectively. Each table is organized
180 by, in the order of indices, machine, shift type, and shift count. */
182 static enum shift_alg shift_alg_qi
[3][3][8] = {
185 /* 0 1 2 3 4 5 6 7 */
186 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
187 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
188 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
192 /* 0 1 2 3 4 5 6 7 */
193 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
194 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
195 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
199 /* 0 1 2 3 4 5 6 7 */
200 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
201 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
202 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
206 static enum shift_alg shift_alg_hi
[3][3][16] = {
209 /* 0 1 2 3 4 5 6 7 */
210 /* 8 9 10 11 12 13 14 15 */
211 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
212 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
213 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
214 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
215 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
216 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
220 /* 0 1 2 3 4 5 6 7 */
221 /* 8 9 10 11 12 13 14 15 */
222 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
223 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
224 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
225 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
226 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
227 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
234 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
235 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
236 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
237 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
238 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
242 static enum shift_alg shift_alg_si
[3][3][32] = {
245 /* 0 1 2 3 4 5 6 7 */
246 /* 8 9 10 11 12 13 14 15 */
247 /* 16 17 18 19 20 21 22 23 */
248 /* 24 25 26 27 28 29 30 31 */
249 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
250 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
251 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
252 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
253 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
254 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
255 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
256 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
257 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
258 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
259 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
260 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
264 /* 0 1 2 3 4 5 6 7 */
265 /* 8 9 10 11 12 13 14 15 */
266 /* 16 17 18 19 20 21 22 23 */
267 /* 24 25 26 27 28 29 30 31 */
268 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
269 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
270 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
271 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
272 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
273 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
274 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
275 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
276 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
277 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
278 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
279 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
283 /* 0 1 2 3 4 5 6 7 */
284 /* 8 9 10 11 12 13 14 15 */
285 /* 16 17 18 19 20 21 22 23 */
286 /* 24 25 26 27 28 29 30 31 */
287 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
288 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
289 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
290 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
291 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
292 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
293 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
294 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
295 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
296 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
297 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
298 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
314 /* Initialize various cpu specific globals at start up. */
317 h8300_option_override (void)
319 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
320 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
321 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
323 #ifndef OBJECT_FORMAT_ELF
326 error ("-msx is not supported in coff");
327 target_flags
|= MASK_H8300S
;
333 cpu_type
= (int) CPU_H8300
;
334 h8_reg_names
= names_big
;
338 /* For this we treat the H8/300H and H8S the same. */
339 cpu_type
= (int) CPU_H8300H
;
340 h8_reg_names
= names_extended
;
342 h8_push_op
= h8_push_ops
[cpu_type
];
343 h8_pop_op
= h8_pop_ops
[cpu_type
];
344 h8_mov_op
= h8_mov_ops
[cpu_type
];
346 if (!TARGET_H8300S
&& TARGET_MAC
)
348 error ("-ms2600 is used without -ms");
349 target_flags
|= MASK_H8300S_1
;
352 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
354 error ("-mn is used without -mh or -ms or -msx");
355 target_flags
^= MASK_NORMAL_MODE
;
358 if (! TARGET_H8300S
&& TARGET_EXR
)
360 error ("-mexr is used without -ms");
361 target_flags
|= MASK_H8300S_1
;
364 if (TARGET_H8300
&& TARGET_INT32
)
366 error ("-mint32 is not supported for H8300 and H8300L targets");
367 target_flags
^= MASK_INT32
;
370 if ((!TARGET_H8300S
&& TARGET_EXR
) && (!TARGET_H8300SX
&& TARGET_EXR
))
372 error ("-mexr is used without -ms or -msx");
373 target_flags
|= MASK_H8300S_1
;
376 if ((!TARGET_H8300S
&& TARGET_NEXR
) && (!TARGET_H8300SX
&& TARGET_NEXR
))
378 warning (OPT_mno_exr
, "-mno-exr valid only with -ms or -msx \
383 if ((TARGET_NORMAL_MODE
))
385 error ("-mn is not supported for linux targets");
386 target_flags
^= MASK_NORMAL_MODE
;
390 /* Some of the shifts are optimized for speed by default.
391 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
392 If optimizing for size, change shift_alg for those shift to
397 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
398 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
399 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
400 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
402 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
403 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
405 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
406 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
409 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
410 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
412 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
413 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
415 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
416 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
417 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
418 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
421 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
424 /* Work out a value for MOVE_RATIO. */
427 /* Memory-memory moves are quite expensive without the
428 h8sx instructions. */
429 h8300_move_ratio
= 3;
431 else if (flag_omit_frame_pointer
)
433 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
434 sometimes be as short as two individual memory-to-memory moves,
435 but since they use all the call-saved registers, it seems better
436 to allow up to three moves here. */
437 h8300_move_ratio
= 4;
439 else if (optimize_size
)
441 /* In this case we don't use movmd sequences since they tend
442 to be longer than calls to memcpy(). Memory-to-memory
443 moves are cheaper than for !TARGET_H8300SX, so it makes
444 sense to have a slightly higher threshold. */
445 h8300_move_ratio
= 4;
449 /* We use movmd sequences for some moves since it can be quicker
450 than calling memcpy(). The sequences will need to save and
451 restore er6 though, so bump up the cost. */
452 h8300_move_ratio
= 6;
455 /* This target defaults to strict volatile bitfields. */
456 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
457 flag_strict_volatile_bitfields
= 1;
460 /* Return the byte register name for a register rtx X. B should be 0
461 if you want a lower byte register. B should be 1 if you want an
462 upper byte register. */
465 byte_reg (rtx x
, int b
)
467 static const char *const names_small
[] = {
468 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
469 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
472 gcc_assert (REG_P (x
));
474 return names_small
[REGNO (x
) * 2 + b
];
477 /* REGNO must be saved/restored across calls if this macro is true. */
479 #define WORD_REG_USED(regno) \
481 /* No need to save registers if this function will not return. */ \
482 && ! TREE_THIS_VOLATILE (current_function_decl) \
483 && (h8300_saveall_function_p (current_function_decl) \
484 /* Save any call saved register that was used. */ \
485 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
486 /* Save the frame pointer if it was used. */ \
487 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
488 /* Save any register used in an interrupt handler. */ \
489 || (h8300_current_function_interrupt_function_p () \
490 && df_regs_ever_live_p (regno)) \
491 /* Save call clobbered registers in non-leaf interrupt \
493 || (h8300_current_function_interrupt_function_p () \
494 && call_used_regs[regno] \
497 /* We use this to wrap all emitted insns in the prologue. */
499 F (rtx_insn
*x
, bool set_it
)
502 RTX_FRAME_RELATED_P (x
) = 1;
506 /* Mark all the subexpressions of the PARALLEL rtx PAR as
507 frame-related. Return PAR.
509 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
510 PARALLEL rtx other than the first if they do not have the
511 FRAME_RELATED flag set on them. */
515 int len
= XVECLEN (par
, 0);
518 for (i
= 0; i
< len
; i
++)
519 RTX_FRAME_RELATED_P (XVECEXP (par
, 0, i
)) = 1;
524 /* Output assembly language to FILE for the operation OP with operand size
525 SIZE to adjust the stack pointer. */
528 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
530 /* If the frame size is 0, we don't have anything to do. */
534 /* H8/300 cannot add/subtract a large constant with a single
535 instruction. If a temporary register is available, load the
536 constant to it and then do the addition. */
539 && !h8300_current_function_interrupt_function_p ()
540 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
542 rtx r3
= gen_rtx_REG (Pmode
, 3);
543 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
544 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
545 stack_pointer_rtx
, r3
)), in_prologue
);
549 /* The stack adjustment made here is further optimized by the
550 splitter. In case of H8/300, the splitter always splits the
551 addition emitted here to make the adjustment interrupt-safe.
552 FIXME: We don't always tag those, because we don't know what
553 the splitter will do. */
556 rtx_insn
*x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
558 GEN_INT (sign
* size
)));
563 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
564 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
568 /* Round up frame size SIZE. */
571 round_frame_size (HOST_WIDE_INT size
)
573 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
574 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
577 /* Compute which registers to push/pop.
578 Return a bit vector of registers. */
581 compute_saved_regs (void)
583 unsigned int saved_regs
= 0;
586 /* Construct a bit vector of registers to be pushed/popped. */
587 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
589 if (WORD_REG_USED (regno
))
590 saved_regs
|= 1 << regno
;
593 /* Don't push/pop the frame pointer as it is treated separately. */
594 if (frame_pointer_needed
)
595 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
600 /* Emit an insn to push register RN. */
603 push (int rn
, bool in_prologue
)
605 rtx reg
= gen_rtx_REG (word_mode
, rn
);
609 x
= gen_push_h8300 (reg
);
610 else if (!TARGET_NORMAL_MODE
)
611 x
= gen_push_h8300hs_advanced (reg
);
613 x
= gen_push_h8300hs_normal (reg
);
614 x
= F (emit_insn (x
), in_prologue
);
615 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
619 /* Emit an insn to pop register RN. */
624 rtx reg
= gen_rtx_REG (word_mode
, rn
);
628 x
= gen_pop_h8300 (reg
);
629 else if (!TARGET_NORMAL_MODE
)
630 x
= gen_pop_h8300hs_advanced (reg
);
632 x
= gen_pop_h8300hs_normal (reg
);
634 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
638 /* Emit an instruction to push or pop NREGS consecutive registers
639 starting at register REGNO. POP_P selects a pop rather than a
640 push and RETURN_P is true if the instruction should return.
642 It must be possible to do the requested operation in a single
643 instruction. If NREGS == 1 && !RETURN_P, use a normal push
644 or pop insn. Otherwise emit a parallel of the form:
647 [(return) ;; if RETURN_P
648 (save or restore REGNO)
649 (save or restore REGNO + 1)
651 (save or restore REGNO + NREGS - 1)
652 (set sp (plus sp (const_int adjust)))] */
655 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
661 /* See whether we can use a simple push or pop. */
662 if (!return_p
&& nregs
== 1)
671 /* We need one element for the return insn, if present, one for each
672 register, and one for stack adjustment. */
673 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
674 sp
= stack_pointer_rtx
;
677 /* Add the return instruction. */
680 RTVEC_ELT (vec
, i
) = ret_rtx
;
684 /* Add the register moves. */
685 for (j
= 0; j
< nregs
; j
++)
691 /* Register REGNO + NREGS - 1 is popped first. Before the
692 stack adjustment, its slot is at address @sp. */
693 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
694 rhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
,
695 (nregs
- j
- 1) * 4));
699 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
700 lhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
, (j
+ 1) * -4));
701 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
703 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (lhs
, rhs
);
706 /* Add the stack adjustment. */
707 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
708 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, offset
));
710 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
720 /* Return true if X has the value sp + OFFSET. */
723 h8300_stack_offset_p (rtx x
, int offset
)
726 return x
== stack_pointer_rtx
;
728 return (GET_CODE (x
) == PLUS
729 && XEXP (x
, 0) == stack_pointer_rtx
730 && GET_CODE (XEXP (x
, 1)) == CONST_INT
731 && INTVAL (XEXP (x
, 1)) == offset
);
734 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
735 something that may be an ldm or stm instruction. If it fits
736 the required template, return the register it loads or stores,
739 LOAD_P is true if X should be a load, false if it should be a store.
740 NREGS is the number of registers that the whole instruction is expected
741 to load or store. INDEX is the index of the register that X should
742 load or store, relative to the lowest-numbered register. */
745 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
747 int regindex
, memindex
, offset
;
750 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
752 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
754 if (GET_CODE (x
) == SET
755 && GET_CODE (XEXP (x
, regindex
)) == REG
756 && GET_CODE (XEXP (x
, memindex
)) == MEM
757 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
758 return REGNO (XEXP (x
, regindex
));
763 /* Return true if the elements of VEC starting at FIRST describe an
764 ldm or stm instruction (LOAD_P says which). */
767 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
770 int nregs
, i
, regno
, adjust
;
772 /* There must be a stack adjustment, a register move, and at least one
773 other operation (a return or another register move). */
774 if (GET_NUM_ELEM (vec
) < 3)
777 /* Get the range of registers to be pushed or popped. */
778 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
779 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
781 /* Check that the call to h8300_ldm_stm_regno succeeded and
782 that we're only dealing with GPRs. */
783 if (regno
< 0 || regno
+ nregs
> 8)
786 /* 2-register h8s instructions must start with an even-numbered register.
787 3- and 4-register instructions must start with er0 or er4. */
790 if ((regno
& 1) != 0)
792 if (nregs
> 2 && (regno
& 3) != 0)
796 /* Check the other loads or stores. */
797 for (i
= 1; i
< nregs
; i
++)
798 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
802 /* Check the stack adjustment. */
803 last
= RTVEC_ELT (vec
, first
+ nregs
);
804 adjust
= (load_p
? nregs
: -nregs
) * 4;
805 return (GET_CODE (last
) == SET
806 && SET_DEST (last
) == stack_pointer_rtx
807 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
810 /* This is what the stack looks like after the prolog of
811 a function with a frame has been set up:
817 <saved registers> <- sp
819 This is what the stack looks like after the prolog of
820 a function which doesn't have a frame:
825 <saved registers> <- sp
828 /* Generate RTL code for the function prologue. */
831 h8300_expand_prologue (void)
837 /* If the current function has the OS_Task attribute set, then
838 we have a naked prologue. */
839 if (h8300_os_task_function_p (current_function_decl
))
842 if (h8300_monitor_function_p (current_function_decl
))
843 /* The monitor function act as normal functions, which means it
844 can accept parameters and return values. In addition to this,
845 interrupts are masked in prologue and return with "rte" in epilogue. */
846 emit_insn (gen_monitor_prologue ());
848 if (frame_pointer_needed
)
851 push (HARD_FRAME_POINTER_REGNUM
, true);
852 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
855 /* Push the rest of the registers in ascending order. */
856 saved_regs
= compute_saved_regs ();
857 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
860 if (saved_regs
& (1 << regno
))
864 /* See how many registers we can push at the same time. */
865 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
866 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
869 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
870 && ((saved_regs
>> regno
) & 0x07) == 0x07)
873 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
874 && ((saved_regs
>> regno
) & 0x03) == 0x03)
878 h8300_push_pop (regno
, n_regs
, false, false);
882 /* Leave room for locals. */
883 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
885 if (flag_stack_usage_info
)
886 current_function_static_stack_size
887 = round_frame_size (get_frame_size ())
888 + (__builtin_popcount (saved_regs
) * UNITS_PER_WORD
)
889 + (frame_pointer_needed
? UNITS_PER_WORD
: 0);
892 /* Return nonzero if we can use "rts" for the function currently being
896 h8300_can_use_return_insn_p (void)
898 return (reload_completed
899 && !frame_pointer_needed
900 && get_frame_size () == 0
901 && compute_saved_regs () == 0);
904 /* Generate RTL code for the function epilogue. */
907 h8300_expand_epilogue (void)
912 HOST_WIDE_INT frame_size
;
915 if (h8300_os_task_function_p (current_function_decl
))
916 /* OS_Task epilogues are nearly naked -- they just have an
920 frame_size
= round_frame_size (get_frame_size ());
923 /* Deallocate locals. */
924 h8300_emit_stack_adjustment (1, frame_size
, false);
926 /* Pop the saved registers in descending order. */
927 saved_regs
= compute_saved_regs ();
928 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
931 if (saved_regs
& (1 << regno
))
935 /* See how many registers we can pop at the same time. */
936 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
937 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
940 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
941 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
944 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
945 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
949 /* See if this pop would be the last insn before the return.
950 If so, use rte/l or rts/l instead of pop or ldm.l. */
952 && !frame_pointer_needed
954 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
957 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
961 /* Pop frame pointer if we had one. */
962 if (frame_pointer_needed
)
966 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
970 emit_jump_insn (ret_rtx
);
973 /* Return nonzero if the current function is an interrupt
977 h8300_current_function_interrupt_function_p (void)
979 return (h8300_interrupt_function_p (current_function_decl
));
983 h8300_current_function_monitor_function_p ()
985 return (h8300_monitor_function_p (current_function_decl
));
988 /* Output assembly code for the start of the file. */
991 h8300_file_start (void)
993 default_file_start ();
996 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
997 else if (TARGET_H8300S
)
998 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
999 else if (TARGET_H8300H
)
1000 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1003 /* Output assembly language code for the end of file. */
1006 h8300_file_end (void)
1008 fputs ("\t.end\n", asm_out_file
);
1011 /* Split an add of a small constant into two adds/subs insns.
1013 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1014 instead of adds/subs. */
1017 split_adds_subs (machine_mode mode
, rtx
*operands
)
1019 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1020 rtx reg
= operands
[0];
1021 HOST_WIDE_INT sign
= 1;
1022 HOST_WIDE_INT amount
;
1023 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1025 /* Force VAL to be positive so that we do not have to consider the
1036 gen_add
= gen_addhi3
;
1040 gen_add
= gen_addsi3
;
1047 /* Try different amounts in descending order. */
1048 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1052 for (; val
>= amount
; val
-= amount
)
1053 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1059 /* Handle machine specific pragmas for compatibility with existing
1060 compilers for the H8/300.
1062 pragma saveall generates prologue/epilogue code which saves and
1063 restores all the registers on function entry.
1065 pragma interrupt saves and restores all registers, and exits with
1066 an rte instruction rather than an rts. A pointer to a function
1067 with this attribute may be safely used in an interrupt vector. */
1070 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1072 pragma_interrupt
= 1;
1076 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1081 /* If the next function argument with MODE and TYPE is to be passed in
1082 a register, return a reg RTX for the hard register in which to pass
1083 the argument. CUM represents the state after the last argument.
1084 If the argument is to be pushed, NULL_RTX is returned.
1086 On the H8/300 all normal args are pushed, unless -mquickcall in which
1087 case the first 3 arguments are passed in registers. */
1090 h8300_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1091 const_tree type
, bool named
)
1093 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1095 static const char *const hand_list
[] = {
1114 rtx result
= NULL_RTX
;
1118 /* Never pass unnamed arguments in registers. */
1122 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1123 if (TARGET_QUICKCALL
)
1126 /* If calling hand written assembler, use 4 regs of args. */
1129 const char * const *p
;
1131 fname
= XSTR (cum
->libcall
, 0);
1133 /* See if this libcall is one of the hand coded ones. */
1134 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1145 if (mode
== BLKmode
)
1146 size
= int_size_in_bytes (type
);
1148 size
= GET_MODE_SIZE (mode
);
1150 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1151 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1152 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1158 /* Update the data in CUM to advance over an argument
1159 of mode MODE and data type TYPE.
1160 (TYPE is null for libcalls where that information may not be available.) */
1163 h8300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1164 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1166 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1168 cum
->nbytes
+= (mode
!= BLKmode
1169 ? (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
1170 : (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
);
1174 /* Implements TARGET_REGISTER_MOVE_COST.
1176 Any SI register-to-register move may need to be reloaded,
1177 so inmplement h8300_register_move_cost to return > 2 so that reload never
1181 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1182 reg_class_t from
, reg_class_t to
)
1184 if (from
== MAC_REGS
|| to
== MAC_REG
)
1190 /* Compute the cost of an and insn. */
1193 h8300_and_costs (rtx x
)
1197 if (GET_MODE (x
) == QImode
)
1200 if (GET_MODE (x
) != HImode
1201 && GET_MODE (x
) != SImode
)
1205 operands
[1] = XEXP (x
, 0);
1206 operands
[2] = XEXP (x
, 1);
1208 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1211 /* Compute the cost of a shift insn. */
1214 h8300_shift_costs (rtx x
)
1218 if (GET_MODE (x
) != QImode
1219 && GET_MODE (x
) != HImode
1220 && GET_MODE (x
) != SImode
)
1225 operands
[2] = XEXP (x
, 1);
1227 return compute_a_shift_length (NULL
, operands
) / 2;
1230 /* Worker function for TARGET_RTX_COSTS. */
1233 h8300_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
1234 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
1236 int code
= GET_CODE (x
);
1238 if (TARGET_H8300SX
&& outer_code
== MEM
)
1240 /* Estimate the number of execution states needed to calculate
1242 if (register_operand (x
, VOIDmode
)
1243 || GET_CODE (x
) == POST_INC
1244 || GET_CODE (x
) == POST_DEC
1248 *total
= COSTS_N_INSNS (1);
1256 HOST_WIDE_INT n
= INTVAL (x
);
1260 /* Constant operands need the same number of processor
1261 states as register operands. Although we could try to
1262 use a size-based cost for !speed, the lack of
1263 of a mode makes the results very unpredictable. */
1267 if (-4 <= n
&& n
<= 4)
1278 *total
= 0 + (outer_code
== SET
);
1282 if (TARGET_H8300H
|| TARGET_H8300S
)
1283 *total
= 0 + (outer_code
== SET
);
1298 /* See comment for CONST_INT. */
1310 if (XEXP (x
, 1) == const0_rtx
)
1315 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1316 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1318 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1321 /* We say that MOD and DIV are so expensive because otherwise we'll
1322 generate some really horrible code for division of a power of two. */
1328 switch (GET_MODE (x
))
1332 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1336 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1342 *total
= COSTS_N_INSNS (12);
1347 switch (GET_MODE (x
))
1351 *total
= COSTS_N_INSNS (2);
1355 *total
= COSTS_N_INSNS (5);
1361 *total
= COSTS_N_INSNS (4);
1367 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1369 *total
= COSTS_N_INSNS (2);
1372 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1374 *total
= COSTS_N_INSNS (1);
1377 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1382 if (GET_MODE (x
) == HImode
)
1389 *total
= COSTS_N_INSNS (1);
1394 /* Documentation for the machine specific operand escapes:
1396 'E' like s but negative.
1397 'F' like t but negative.
1398 'G' constant just the negative
1399 'R' print operand as a byte:8 address if appropriate, else fall back to
1401 'S' print operand as a long word
1402 'T' print operand as a word
1403 'V' find the set bit, and print its number.
1404 'W' find the clear bit, and print its number.
1405 'X' print operand as a byte
1406 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1407 If this operand isn't a register, fall back to 'R' handling.
1409 'c' print the opcode corresponding to rtl
1410 'e' first word of 32-bit value - if reg, then least reg. if mem
1411 then least. if const then most sig word
1412 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1413 then +2. if const then least sig word
1414 'j' print operand as condition code.
1415 'k' print operand as reverse condition code.
1416 'm' convert an integer operand to a size suffix (.b, .w or .l)
1417 'o' print an integer without a leading '#'
1418 's' print as low byte of 16-bit value
1419 't' print as high byte of 16-bit value
1420 'w' print as low byte of 32-bit value
1421 'x' print as 2nd byte of 32-bit value
1422 'y' print as 3rd byte of 32-bit value
1423 'z' print as msb of 32-bit value
1426 /* Return assembly language string which identifies a comparison type. */
1429 cond_string (enum rtx_code code
)
1458 /* Print operand X using operand code CODE to assembly language output file
1462 h8300_print_operand (FILE *file
, rtx x
, int code
)
1464 /* This is used for communication between codes V,W,Z and Y. */
1470 if (h8300_constant_length (x
) == 2)
1471 fprintf (file
, ":16");
1473 fprintf (file
, ":32");
1476 switch (GET_CODE (x
))
1479 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1482 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1489 switch (GET_CODE (x
))
1492 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1495 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1502 gcc_assert (GET_CODE (x
) == CONST_INT
);
1503 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1506 if (GET_CODE (x
) == REG
)
1507 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1512 if (GET_CODE (x
) == REG
)
1513 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1518 bitint
= (INTVAL (x
) & 0xffff);
1519 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1520 bitint
= exact_log2 (bitint
& 0xff);
1522 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1523 gcc_assert (bitint
>= 0);
1524 fprintf (file
, "#%d", bitint
);
1527 bitint
= ((~INTVAL (x
)) & 0xffff);
1528 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1529 bitint
= exact_log2 (bitint
& 0xff);
1531 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1532 gcc_assert (bitint
>= 0);
1533 fprintf (file
, "#%d", bitint
);
1537 if (GET_CODE (x
) == REG
)
1538 fprintf (file
, "%s", byte_reg (x
, 0));
1543 gcc_assert (bitint
>= 0);
1544 if (GET_CODE (x
) == REG
)
1545 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1547 h8300_print_operand (file
, x
, 'R');
1551 bitint
= INTVAL (x
);
1552 fprintf (file
, "#%d", bitint
& 7);
1555 switch (GET_CODE (x
))
1558 fprintf (file
, "or");
1561 fprintf (file
, "xor");
1564 fprintf (file
, "and");
1571 switch (GET_CODE (x
))
1575 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1577 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1580 h8300_print_operand (file
, x
, 0);
1583 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1588 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1589 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1598 switch (GET_CODE (x
))
1602 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1604 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1607 x
= adjust_address (x
, HImode
, 2);
1608 h8300_print_operand (file
, x
, 0);
1611 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1616 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1617 fprintf (file
, "#%ld", (val
& 0xffff));
1625 fputs (cond_string (GET_CODE (x
)), file
);
1628 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1631 gcc_assert (GET_CODE (x
) == CONST_INT
);
1651 h8300_print_operand_address (file
, VOIDmode
, x
);
1654 if (GET_CODE (x
) == CONST_INT
)
1655 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1657 fprintf (file
, "%s", byte_reg (x
, 0));
1660 if (GET_CODE (x
) == CONST_INT
)
1661 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1663 fprintf (file
, "%s", byte_reg (x
, 1));
1666 if (GET_CODE (x
) == CONST_INT
)
1667 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1669 fprintf (file
, "%s",
1670 byte_reg (x
, TARGET_H8300
? 2 : 0));
1673 if (GET_CODE (x
) == CONST_INT
)
1674 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1676 fprintf (file
, "%s",
1677 byte_reg (x
, TARGET_H8300
? 3 : 1));
1680 if (GET_CODE (x
) == CONST_INT
)
1681 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1683 fprintf (file
, "%s", byte_reg (x
, 0));
1686 if (GET_CODE (x
) == CONST_INT
)
1687 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1689 fprintf (file
, "%s", byte_reg (x
, 1));
1694 switch (GET_CODE (x
))
1697 switch (GET_MODE (x
))
1700 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1701 fprintf (file
, "%s", byte_reg (x
, 0));
1702 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1703 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1707 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1711 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1720 rtx addr
= XEXP (x
, 0);
1722 fprintf (file
, "@");
1723 output_address (GET_MODE (x
), addr
);
1725 /* Add a length suffix to constant addresses. Although this
1726 is often unnecessary, it helps to avoid ambiguity in the
1727 syntax of mova. If we wrote an insn like:
1729 mova/w.l @(1,@foo.b),er0
1731 then .b would be considered part of the symbol name.
1732 Adding a length after foo will avoid this. */
1733 if (CONSTANT_P (addr
))
1737 /* Used for mov.b and bit operations. */
1738 if (h8300_eightbit_constant_address_p (addr
))
1740 fprintf (file
, ":8");
1746 /* We should not get here if we are processing bit
1747 operations on H8/300 or H8/300H because 'U'
1748 constraint does not allow bit operations on the
1749 tiny area on these machines. */
1754 if (h8300_constant_length (addr
) == 2)
1755 fprintf (file
, ":16");
1757 fprintf (file
, ":32");
1769 fprintf (file
, "#");
1770 h8300_print_operand_address (file
, VOIDmode
, x
);
1775 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1776 fprintf (file
, "#%ld", val
);
1785 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1788 h8300_print_operand_punct_valid_p (unsigned char code
)
1790 return (code
== '#');
1793 /* Output assembly language output for the address ADDR to FILE. */
1796 h8300_print_operand_address (FILE *file
, machine_mode mode
, rtx addr
)
1801 switch (GET_CODE (addr
))
1804 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1808 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1812 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1816 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1820 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1824 fprintf (file
, "(");
1826 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1827 if (GET_CODE (index
) == REG
)
1830 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1831 fprintf (file
, ",");
1835 h8300_print_operand_address (file
, mode
, index
);
1839 h8300_print_operand (file
, index
, 'X');
1844 h8300_print_operand (file
, index
, 'T');
1849 h8300_print_operand (file
, index
, 'S');
1853 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1858 h8300_print_operand_address (file
, mode
, XEXP (addr
, 0));
1859 fprintf (file
, "+");
1860 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1862 fprintf (file
, ")");
1867 /* Since the H8/300 only has 16-bit pointers, negative values are also
1868 those >= 32768. This happens for example with pointer minus a
1869 constant. We don't want to turn (char *p - 2) into
1870 (char *p + 65534) because loop unrolling can build upon this
1871 (IE: char *p + 131068). */
1872 int n
= INTVAL (addr
);
1874 n
= (int) (short) n
;
1875 fprintf (file
, "%d", n
);
1880 output_addr_const (file
, addr
);
1885 /* Output all insn addresses and their sizes into the assembly language
1886 output file. This is helpful for debugging whether the length attributes
1887 in the md file are correct. This is not meant to be a user selectable
1891 final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1892 int num_operands ATTRIBUTE_UNUSED
)
1894 /* This holds the last insn address. */
1895 static int last_insn_address
= 0;
1897 const int uid
= INSN_UID (insn
);
1899 if (TARGET_ADDRESSES
)
1901 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1902 INSN_ADDRESSES (uid
) - last_insn_address
);
1903 last_insn_address
= INSN_ADDRESSES (uid
);
1907 /* Prepare for an SI sized move. */
1910 h8300_expand_movsi (rtx operands
[])
1912 rtx src
= operands
[1];
1913 rtx dst
= operands
[0];
1914 if (!reload_in_progress
&& !reload_completed
)
1916 if (!register_operand (dst
, GET_MODE (dst
)))
1918 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1919 emit_move_insn (tmp
, src
);
1926 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1927 Frame pointer elimination is automatically handled.
1929 For the h8300, if frame pointer elimination is being done, we would like to
1930 convert ap and rp into sp, not fp.
1932 All other eliminations are valid. */
1935 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1937 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1940 /* Conditionally modify register usage based on target flags. */
1943 h8300_conditional_register_usage (void)
1946 fixed_regs
[MAC_REG
] = call_used_regs
[MAC_REG
] = 1;
1949 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1950 Define the offset between two registers, one to be eliminated, and
1951 the other its replacement, at the start of a routine. */
1954 h8300_initial_elimination_offset (int from
, int to
)
1956 /* The number of bytes that the return address takes on the stack. */
1957 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1959 /* The number of bytes that the saved frame pointer takes on the stack. */
1960 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1962 /* The number of bytes that the saved registers, excluding the frame
1963 pointer, take on the stack. */
1964 int saved_regs_size
= 0;
1966 /* The number of bytes that the locals takes on the stack. */
1967 int frame_size
= round_frame_size (get_frame_size ());
1971 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1972 if (WORD_REG_USED (regno
))
1973 saved_regs_size
+= UNITS_PER_WORD
;
1975 /* Adjust saved_regs_size because the above loop took the frame
1976 pointer int account. */
1977 saved_regs_size
-= fp_size
;
1981 case HARD_FRAME_POINTER_REGNUM
:
1984 case ARG_POINTER_REGNUM
:
1985 return pc_size
+ fp_size
;
1986 case RETURN_ADDRESS_POINTER_REGNUM
:
1988 case FRAME_POINTER_REGNUM
:
1989 return -saved_regs_size
;
1994 case STACK_POINTER_REGNUM
:
1997 case ARG_POINTER_REGNUM
:
1998 return pc_size
+ saved_regs_size
+ frame_size
;
1999 case RETURN_ADDRESS_POINTER_REGNUM
:
2000 return saved_regs_size
+ frame_size
;
2001 case FRAME_POINTER_REGNUM
:
2013 /* Worker function for RETURN_ADDR_RTX. */
2016 h8300_return_addr_rtx (int count
, rtx frame
)
2021 ret
= gen_rtx_MEM (Pmode
,
2022 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
2023 else if (flag_omit_frame_pointer
)
2026 ret
= gen_rtx_MEM (Pmode
,
2027 memory_address (Pmode
,
2028 plus_constant (Pmode
, frame
,
2030 set_mem_alias_set (ret
, get_frame_alias_set ());
2034 /* Update the condition code from the insn. */
2037 notice_update_cc (rtx body
, rtx_insn
*insn
)
2041 switch (get_attr_cc (insn
))
2044 /* Insn does not affect CC at all. */
2048 /* Insn does not change CC, but the 0'th operand has been changed. */
2049 if (cc_status
.value1
!= 0
2050 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2051 cc_status
.value1
= 0;
2052 if (cc_status
.value2
!= 0
2053 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2054 cc_status
.value2
= 0;
2058 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2059 The V flag is unusable. The C flag may or may not be known but
2060 that's ok because alter_cond will change tests to use EQ/NE. */
2062 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2063 set
= single_set (insn
);
2064 cc_status
.value1
= SET_SRC (set
);
2065 if (SET_DEST (set
) != cc0_rtx
)
2066 cc_status
.value2
= SET_DEST (set
);
2070 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2071 The C flag may or may not be known but that's ok because
2072 alter_cond will change tests to use EQ/NE. */
2074 cc_status
.flags
|= CC_NO_CARRY
;
2075 set
= single_set (insn
);
2076 cc_status
.value1
= SET_SRC (set
);
2077 if (SET_DEST (set
) != cc0_rtx
)
2079 /* If the destination is STRICT_LOW_PART, strip off
2081 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2082 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2084 cc_status
.value2
= SET_DEST (set
);
2089 /* The insn is a compare instruction. */
2091 cc_status
.value1
= SET_SRC (body
);
2095 /* Insn doesn't leave CC in a usable state. */
2101 /* Given that X occurs in an address of the form (plus X constant),
2102 return the part of X that is expected to be a register. There are
2103 four kinds of addressing mode to recognize:
2110 If SIZE is nonnull, and the address is one of the last three forms,
2111 set *SIZE to the index multiplication factor. Set it to 0 for
2112 plain @(dd,Rn) addresses.
2114 MODE is the mode of the value being accessed. It can be VOIDmode
2115 if the address is known to be valid, but its mode is unknown. */
2118 h8300_get_index (rtx x
, machine_mode mode
, int *size
)
2125 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2128 && (mode
== VOIDmode
2129 || GET_MODE_CLASS (mode
) == MODE_INT
2130 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2132 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2134 /* When accessing byte-sized values, the index can be
2135 a zero-extended QImode or HImode register. */
2136 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2141 /* We're looking for addresses of the form:
2144 or (mult (zero_extend X) I)
2146 where I is the size of the operand being accessed.
2147 The canonical form of the second expression is:
2149 (and (mult (subreg X) I) J)
2151 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2154 if (GET_CODE (x
) == AND
2155 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2157 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2158 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2160 index
= XEXP (x
, 0);
2161 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2169 if (GET_CODE (index
) == MULT
2170 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2171 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2172 return XEXP (index
, 0);
2179 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2181 On the H8/300, the predecrement and postincrement address depend thus
2182 (the amount of decrement or increment being the length of the operand). */
2185 h8300_mode_dependent_address_p (const_rtx addr
,
2186 addr_space_t as ATTRIBUTE_UNUSED
)
2188 if (GET_CODE (addr
) == PLUS
2189 && h8300_get_index (XEXP (addr
, 0), VOIDmode
, 0) != XEXP (addr
, 0))
2195 static const h8300_length_table addb_length_table
=
2197 /* #xx Rs @aa @Rs @xx */
2198 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2199 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2200 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2201 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2204 static const h8300_length_table addw_length_table
=
2206 /* #xx Rs @aa @Rs @xx */
2207 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2208 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2209 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2210 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2213 static const h8300_length_table addl_length_table
=
2215 /* #xx Rs @aa @Rs @xx */
2216 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2217 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2218 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2219 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2222 #define logicb_length_table addb_length_table
2223 #define logicw_length_table addw_length_table
2225 static const h8300_length_table logicl_length_table
=
2227 /* #xx Rs @aa @Rs @xx */
2228 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2229 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2230 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2231 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2234 static const h8300_length_table movb_length_table
=
2236 /* #xx Rs @aa @Rs @xx */
2237 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2238 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2239 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2240 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2243 #define movw_length_table movb_length_table
2245 static const h8300_length_table movl_length_table
=
2247 /* #xx Rs @aa @Rs @xx */
2248 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2249 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2250 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2251 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2254 /* Return the size of the given address or displacement constant. */
2257 h8300_constant_length (rtx constant
)
2259 /* Check for (@d:16,Reg). */
2260 if (GET_CODE (constant
) == CONST_INT
2261 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2264 /* Check for (@d:16,Reg) in cases where the displacement is
2265 an absolute address. */
2266 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2272 /* Return the size of a displacement field in address ADDR, which should
2273 have the form (plus X constant). SIZE is the number of bytes being
2277 h8300_displacement_length (rtx addr
, int size
)
2281 offset
= XEXP (addr
, 1);
2283 /* Check for @(d:2,Reg). */
2284 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2285 && GET_CODE (offset
) == CONST_INT
2286 && (INTVAL (offset
) == size
2287 || INTVAL (offset
) == size
* 2
2288 || INTVAL (offset
) == size
* 3))
2291 return h8300_constant_length (offset
);
2294 /* Store the class of operand OP in *OPCLASS and return the length of any
2295 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2296 can be null if only the length is needed. */
2299 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2301 enum h8300_operand_class dummy
;
2306 if (CONSTANT_P (op
))
2308 *opclass
= H8OP_IMMEDIATE
;
2310 /* Byte-sized immediates are stored in the opcode fields. */
2314 /* If this is a 32-bit instruction, see whether the constant
2315 will fit into a 16-bit immediate field. */
2318 && GET_CODE (op
) == CONST_INT
2319 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2324 else if (GET_CODE (op
) == MEM
)
2327 if (CONSTANT_P (op
))
2329 *opclass
= H8OP_MEM_ABSOLUTE
;
2330 return h8300_constant_length (op
);
2332 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2334 *opclass
= H8OP_MEM_COMPLEX
;
2335 return h8300_displacement_length (op
, size
);
2337 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2339 *opclass
= H8OP_MEM_COMPLEX
;
2342 else if (register_operand (op
, VOIDmode
))
2344 *opclass
= H8OP_MEM_BASE
;
2348 gcc_assert (register_operand (op
, VOIDmode
));
2349 *opclass
= H8OP_REGISTER
;
2353 /* Return the length of the instruction described by TABLE given that
2354 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2355 and OP2 must be an h8300_src_operand. */
2358 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2360 enum h8300_operand_class op1_class
, op2_class
;
2361 unsigned int size
, immediate_length
;
2363 size
= GET_MODE_SIZE (GET_MODE (op1
));
2364 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2365 + h8300_classify_operand (op2
, size
, &op2_class
));
2366 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2369 /* Return the length of a unary instruction such as neg or not given that
2370 its operand is OP. */
2373 h8300_unary_length (rtx op
)
2375 enum h8300_operand_class opclass
;
2376 unsigned int size
, operand_length
;
2378 size
= GET_MODE_SIZE (GET_MODE (op
));
2379 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2386 return (size
== 4 ? 6 : 4);
2388 case H8OP_MEM_ABSOLUTE
:
2389 return operand_length
+ (size
== 4 ? 6 : 4);
2391 case H8OP_MEM_COMPLEX
:
2392 return operand_length
+ 6;
2399 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2402 h8300_short_immediate_length (rtx op
)
2404 enum h8300_operand_class opclass
;
2405 unsigned int size
, operand_length
;
2407 size
= GET_MODE_SIZE (GET_MODE (op
));
2408 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2416 case H8OP_MEM_ABSOLUTE
:
2417 case H8OP_MEM_COMPLEX
:
2418 return 4 + operand_length
;
2425 /* Likewise bitfield load and store instructions. */
2428 h8300_bitfield_length (rtx op
, rtx op2
)
2430 enum h8300_operand_class opclass
;
2431 unsigned int size
, operand_length
;
2433 if (GET_CODE (op
) == REG
)
2435 gcc_assert (GET_CODE (op
) != REG
);
2437 size
= GET_MODE_SIZE (GET_MODE (op
));
2438 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2443 case H8OP_MEM_ABSOLUTE
:
2444 case H8OP_MEM_COMPLEX
:
2445 return 4 + operand_length
;
2452 /* Calculate the length of general binary instruction INSN using TABLE. */
2455 h8300_binary_length (rtx_insn
*insn
, const h8300_length_table
*table
)
2459 set
= single_set (insn
);
2462 if (BINARY_P (SET_SRC (set
)))
2463 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2464 XEXP (SET_SRC (set
), 1), table
);
2467 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2468 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2469 XEXP (XEXP (SET_SRC (set
), 1), 1),
2474 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2475 memory reference and either (1) it has the form @(d:16,Rn) or
2476 (2) its address has the code given by INC_CODE. */
2479 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2484 if (GET_CODE (op
) != MEM
)
2487 addr
= XEXP (op
, 0);
2488 size
= GET_MODE_SIZE (GET_MODE (op
));
2489 if (size
!= 1 && size
!= 2)
2492 return (GET_CODE (addr
) == inc_code
2493 || (GET_CODE (addr
) == PLUS
2494 && GET_CODE (XEXP (addr
, 0)) == REG
2495 && h8300_displacement_length (addr
, size
) == 2));
2498 /* Calculate the length of move instruction INSN using the given length
2499 table. Although the tables are correct for most cases, there is some
2500 irregularity in the length of mov.b and mov.w. The following forms:
2507 are two bytes shorter than most other "mov Rs, @complex" or
2508 "mov @complex,Rd" combinations. */
2511 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2515 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2516 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2518 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2523 /* Return the length of a mova instruction with the given operands.
2524 DEST is the register destination, SRC is the source address and
2525 OFFSET is the 16-bit or 32-bit displacement. */
2528 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2533 + h8300_constant_length (offset
)
2534 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2535 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2540 /* Compute the length of INSN based on its length_table attribute.
2541 OPERANDS is the array of its operands. */
2544 h8300_insn_length_from_table (rtx_insn
*insn
, rtx
* operands
)
2546 switch (get_attr_length_table (insn
))
2548 case LENGTH_TABLE_NONE
:
2551 case LENGTH_TABLE_ADDB
:
2552 return h8300_binary_length (insn
, &addb_length_table
);
2554 case LENGTH_TABLE_ADDW
:
2555 return h8300_binary_length (insn
, &addw_length_table
);
2557 case LENGTH_TABLE_ADDL
:
2558 return h8300_binary_length (insn
, &addl_length_table
);
2560 case LENGTH_TABLE_LOGICB
:
2561 return h8300_binary_length (insn
, &logicb_length_table
);
2563 case LENGTH_TABLE_MOVB
:
2564 return h8300_move_length (operands
, &movb_length_table
);
2566 case LENGTH_TABLE_MOVW
:
2567 return h8300_move_length (operands
, &movw_length_table
);
2569 case LENGTH_TABLE_MOVL
:
2570 return h8300_move_length (operands
, &movl_length_table
);
2572 case LENGTH_TABLE_MOVA
:
2573 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2575 case LENGTH_TABLE_MOVA_ZERO
:
2576 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2578 case LENGTH_TABLE_UNARY
:
2579 return h8300_unary_length (operands
[0]);
2581 case LENGTH_TABLE_MOV_IMM4
:
2582 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2584 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2585 return h8300_short_immediate_length (operands
[0]);
2587 case LENGTH_TABLE_BITFIELD
:
2588 return h8300_bitfield_length (operands
[0], operands
[1]);
2590 case LENGTH_TABLE_BITBRANCH
:
2591 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2598 /* Return true if LHS and RHS are memory references that can be mapped
2599 to the same h8sx assembly operand. LHS appears as the destination of
2600 an instruction and RHS appears as a source.
2602 Three cases are allowed:
2604 - RHS is @+Rn or @-Rn, LHS is @Rn
2605 - RHS is @Rn, LHS is @Rn+ or @Rn-
2606 - RHS and LHS have the same address and neither has side effects. */
2609 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2611 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2613 rhs
= XEXP (rhs
, 0);
2614 lhs
= XEXP (lhs
, 0);
2616 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2617 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2619 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2620 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2622 if (rtx_equal_p (rhs
, lhs
))
2628 /* Return true if OPERANDS[1] can be mapped to the same assembly
2629 operand as OPERANDS[0]. */
2632 h8300_operands_match_p (rtx
*operands
)
2634 if (register_operand (operands
[0], VOIDmode
)
2635 && register_operand (operands
[1], VOIDmode
))
2638 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2644 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2645 region DEST. The two regions do not overlap and have the common
2646 alignment given by ALIGNMENT. Return true on success.
2648 Using movmd for variable-length moves seems to involve some
2649 complex trade-offs. For instance:
2651 - Preparing for a movmd instruction is similar to preparing
2652 for a memcpy. The main difference is that the arguments
2653 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2655 - Since movmd clobbers the frame pointer, we need to save
2656 and restore it somehow when frame_pointer_needed. This can
2657 sometimes make movmd sequences longer than calls to memcpy().
2659 - The counter register is 16 bits, so the instruction is only
2660 suitable for variable-length moves when sizeof (size_t) == 2.
2661 That's only true in normal mode.
2663 - We will often lack static alignment information. Falling back
2664 on movmd.b would likely be slower than calling memcpy(), at least
2667 This function therefore only uses movmd when the length is a
2668 known constant, and only then if -fomit-frame-pointer is in
2669 effect or if we're not optimizing for size.
2671 At the moment the function uses movmd for all in-range constants,
2672 but it might be better to fall back on memcpy() for large moves
2673 if ALIGNMENT == 1. */
2676 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2677 HOST_WIDE_INT alignment
)
2679 if (!flag_omit_frame_pointer
&& optimize_size
)
2682 if (GET_CODE (length
) == CONST_INT
)
2684 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2688 /* Use movmd.l if the alignment allows it, otherwise fall back
2690 factor
= (alignment
>= 2 ? 4 : 1);
2692 /* Make sure the length is within range. We can handle counter
2693 values up to 65536, although HImode truncation will make
2694 the count appear negative in rtl dumps. */
2695 n
= INTVAL (length
);
2696 if (n
<= 0 || n
/ factor
> 65536)
2699 /* Create temporary registers for the source and destination
2700 pointers. Initialize them to the start of each region. */
2701 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2702 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2704 /* Create references to the movmd source and destination blocks. */
2705 first_dest
= replace_equiv_address (dest
, dest_reg
);
2706 first_src
= replace_equiv_address (src
, src_reg
);
2708 set_mem_size (first_dest
, n
& -factor
);
2709 set_mem_size (first_src
, n
& -factor
);
2711 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2712 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2714 if ((n
& -factor
) != n
)
2716 /* Move SRC and DEST past the region we just copied.
2717 This is done to update the memory attributes. */
2718 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2719 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2721 /* Replace the addresses with the source and destination
2722 registers, which movmd has left with the right values. */
2723 dest
= replace_equiv_address (dest
, dest_reg
);
2724 src
= replace_equiv_address (src
, src_reg
);
2726 /* Mop up the left-over bytes. */
2728 emit_move_insn (adjust_address (dest
, HImode
, 0),
2729 adjust_address (src
, HImode
, 0));
2731 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2732 adjust_address (src
, QImode
, n
& 2));
2739 /* Move ADDR into er6 after pushing its old value onto the stack. */
2742 h8300_swap_into_er6 (rtx addr
)
2744 rtx insn
= push (HARD_FRAME_POINTER_REGNUM
, false);
2745 if (frame_pointer_needed
)
2746 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2747 plus_constant (Pmode
, gen_rtx_MEM (Pmode
, stack_pointer_rtx
),
2748 2 * UNITS_PER_WORD
));
2750 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2751 gen_rtx_SET (stack_pointer_rtx
,
2752 plus_constant (Pmode
, stack_pointer_rtx
, 4)));
2754 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2755 if (REGNO (addr
) == SP_REG
)
2756 emit_move_insn (hard_frame_pointer_rtx
,
2757 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2758 GET_MODE_SIZE (word_mode
)));
2761 /* Move the current value of er6 into ADDR and pop its old value
2765 h8300_swap_out_of_er6 (rtx addr
)
2769 if (REGNO (addr
) != SP_REG
)
2770 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2772 insn
= pop (HARD_FRAME_POINTER_REGNUM
);
2773 if (frame_pointer_needed
)
2774 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2775 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2776 2 * UNITS_PER_WORD
));
2778 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2779 gen_rtx_SET (stack_pointer_rtx
,
2780 plus_constant (Pmode
, stack_pointer_rtx
, -4)));
2783 /* Return the length of mov instruction. */
2786 compute_mov_length (rtx
*operands
)
2788 /* If the mov instruction involves a memory operand, we compute the
2789 length, assuming the largest addressing mode is used, and then
2790 adjust later in the function. Otherwise, we compute and return
2791 the exact length in one step. */
2792 machine_mode mode
= GET_MODE (operands
[0]);
2793 rtx dest
= operands
[0];
2794 rtx src
= operands
[1];
2797 if (GET_CODE (src
) == MEM
)
2798 addr
= XEXP (src
, 0);
2799 else if (GET_CODE (dest
) == MEM
)
2800 addr
= XEXP (dest
, 0);
2806 unsigned int base_length
;
2811 if (addr
== NULL_RTX
)
2814 /* The eightbit addressing is available only in QImode, so
2815 go ahead and take care of it. */
2816 if (h8300_eightbit_constant_address_p (addr
))
2823 if (addr
== NULL_RTX
)
2828 if (src
== const0_rtx
)
2838 if (addr
== NULL_RTX
)
2843 if (GET_CODE (src
) == CONST_INT
)
2845 if (src
== const0_rtx
)
2848 if ((INTVAL (src
) & 0xffff) == 0)
2851 if ((INTVAL (src
) & 0xffff) == 0)
2854 if ((INTVAL (src
) & 0xffff)
2855 == ((INTVAL (src
) >> 16) & 0xffff))
2865 if (addr
== NULL_RTX
)
2870 if (satisfies_constraint_G (src
))
2883 /* Adjust the length based on the addressing mode used.
2884 Specifically, we subtract the difference between the actual
2885 length and the longest one, which is @(d:16,Rs). For SImode
2886 and SFmode, we double the adjustment because two mov.w are
2887 used to do the job. */
2889 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2890 if (GET_CODE (addr
) == PRE_DEC
2891 || GET_CODE (addr
) == POST_INC
)
2893 if (mode
== QImode
|| mode
== HImode
)
2894 return base_length
- 2;
2896 /* In SImode and SFmode, we use two mov.w instructions, so
2897 double the adjustment. */
2898 return base_length
- 4;
2901 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2902 in SImode and SFmode, the second mov.w involves an address
2903 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2905 if (GET_CODE (addr
) == REG
)
2906 return base_length
- 2;
2912 unsigned int base_length
;
2917 if (addr
== NULL_RTX
)
2920 /* The eightbit addressing is available only in QImode, so
2921 go ahead and take care of it. */
2922 if (h8300_eightbit_constant_address_p (addr
))
2929 if (addr
== NULL_RTX
)
2934 if (src
== const0_rtx
)
2944 if (addr
== NULL_RTX
)
2948 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2954 if (GET_CODE (src
) == CONST_INT
)
2956 int val
= INTVAL (src
);
2961 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2964 switch (val
& 0xffffffff)
2985 if (addr
== NULL_RTX
)
2990 if (satisfies_constraint_G (src
))
3003 /* Adjust the length based on the addressing mode used.
3004 Specifically, we subtract the difference between the actual
3005 length and the longest one, which is @(d:24,ERs). */
3007 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3008 if (GET_CODE (addr
) == PRE_DEC
3009 || GET_CODE (addr
) == POST_INC
)
3010 return base_length
- 6;
3012 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3013 if (GET_CODE (addr
) == REG
)
3014 return base_length
- 6;
3016 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3018 if (GET_CODE (addr
) == PLUS
3019 && GET_CODE (XEXP (addr
, 0)) == REG
3020 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
3021 && INTVAL (XEXP (addr
, 1)) > -32768
3022 && INTVAL (XEXP (addr
, 1)) < 32767)
3023 return base_length
- 4;
3025 /* @aa:16 is 4 bytes shorter than the longest. */
3026 if (h8300_tiny_constant_address_p (addr
))
3027 return base_length
- 4;
3029 /* @aa:24 is 2 bytes shorter than the longest. */
3030 if (CONSTANT_P (addr
))
3031 return base_length
- 2;
3037 /* Output an addition insn. */
3040 output_plussi (rtx
*operands
)
3042 machine_mode mode
= GET_MODE (operands
[0]);
3044 gcc_assert (mode
== SImode
);
3048 if (GET_CODE (operands
[2]) == REG
)
3049 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3051 if (GET_CODE (operands
[2]) == CONST_INT
)
3053 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3055 if ((n
& 0xffffff) == 0)
3056 return "add\t%z2,%z0";
3057 if ((n
& 0xffff) == 0)
3058 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3059 if ((n
& 0xff) == 0)
3060 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3063 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3067 if (GET_CODE (operands
[2]) == CONST_INT
3068 && register_operand (operands
[1], VOIDmode
))
3070 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3072 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3073 return "add.l\t%S2,%S0";
3074 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3075 return "sub.l\t%G2,%S0";
3077 /* See if we can finish with 2 bytes. */
3079 switch ((unsigned int) intval
& 0xffffffff)
3084 return "adds\t%2,%S0";
3089 return "subs\t%G2,%S0";
3093 operands
[2] = GEN_INT (intval
>> 16);
3094 return "inc.w\t%2,%e0";
3098 operands
[2] = GEN_INT (intval
>> 16);
3099 return "dec.w\t%G2,%e0";
3102 /* See if we can finish with 4 bytes. */
3103 if ((intval
& 0xffff) == 0)
3105 operands
[2] = GEN_INT (intval
>> 16);
3106 return "add.w\t%2,%e0";
3110 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3112 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3113 return "sub.l\t%S2,%S0";
3115 return "add.l\t%S2,%S0";
3119 /* ??? It would be much easier to add the h8sx stuff if a single function
3120 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3121 /* Compute the length of an addition insn. */
3124 compute_plussi_length (rtx
*operands
)
3126 machine_mode mode
= GET_MODE (operands
[0]);
3128 gcc_assert (mode
== SImode
);
3132 if (GET_CODE (operands
[2]) == REG
)
3135 if (GET_CODE (operands
[2]) == CONST_INT
)
3137 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3139 if ((n
& 0xffffff) == 0)
3141 if ((n
& 0xffff) == 0)
3143 if ((n
& 0xff) == 0)
3151 if (GET_CODE (operands
[2]) == CONST_INT
3152 && register_operand (operands
[1], VOIDmode
))
3154 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3156 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3158 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3161 /* See if we can finish with 2 bytes. */
3163 switch ((unsigned int) intval
& 0xffffffff)
3184 /* See if we can finish with 4 bytes. */
3185 if ((intval
& 0xffff) == 0)
3189 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3190 return h8300_length_from_table (operands
[0],
3191 GEN_INT (-INTVAL (operands
[2])),
3192 &addl_length_table
);
3194 return h8300_length_from_table (operands
[0], operands
[2],
3195 &addl_length_table
);
3200 /* Compute which flag bits are valid after an addition insn. */
3203 compute_plussi_cc (rtx
*operands
)
3205 machine_mode mode
= GET_MODE (operands
[0]);
3207 gcc_assert (mode
== SImode
);
3215 if (GET_CODE (operands
[2]) == CONST_INT
3216 && register_operand (operands
[1], VOIDmode
))
3218 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3220 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3222 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3225 /* See if we can finish with 2 bytes. */
3227 switch ((unsigned int) intval
& 0xffffffff)
3232 return CC_NONE_0HIT
;
3237 return CC_NONE_0HIT
;
3248 /* See if we can finish with 4 bytes. */
3249 if ((intval
& 0xffff) == 0)
3257 /* Output a logical insn. */
3260 output_logical_op (machine_mode mode
, rtx
*operands
)
3262 /* Figure out the logical op that we need to perform. */
3263 enum rtx_code code
= GET_CODE (operands
[3]);
3264 /* Pretend that every byte is affected if both operands are registers. */
3265 const unsigned HOST_WIDE_INT intval
=
3266 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3267 /* Always use the full instruction if the
3268 first operand is in memory. It is better
3269 to use define_splits to generate the shorter
3270 sequence where valid. */
3271 && register_operand (operands
[1], VOIDmode
)
3272 ? INTVAL (operands
[2]) : 0x55555555);
3273 /* The determinant of the algorithm. If we perform an AND, 0
3274 affects a bit. Otherwise, 1 affects a bit. */
3275 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3276 /* Break up DET into pieces. */
3277 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3278 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3279 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3280 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3281 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3282 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3283 int lower_half_easy_p
= 0;
3284 int upper_half_easy_p
= 0;
3285 /* The name of an insn. */
3307 /* First, see if we can finish with one insn. */
3308 if ((TARGET_H8300H
|| TARGET_H8300S
)
3312 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3313 output_asm_insn (insn_buf
, operands
);
3317 /* Take care of the lower byte. */
3320 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3321 output_asm_insn (insn_buf
, operands
);
3323 /* Take care of the upper byte. */
3326 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3327 output_asm_insn (insn_buf
, operands
);
3332 if (TARGET_H8300H
|| TARGET_H8300S
)
3334 /* Determine if the lower half can be taken care of in no more
3336 lower_half_easy_p
= (b0
== 0
3338 || (code
!= IOR
&& w0
== 0xffff));
3340 /* Determine if the upper half can be taken care of in no more
3342 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3343 || (code
== AND
&& w1
== 0xff00));
3346 /* Check if doing everything with one insn is no worse than
3347 using multiple insns. */
3348 if ((TARGET_H8300H
|| TARGET_H8300S
)
3349 && w0
!= 0 && w1
!= 0
3350 && !(lower_half_easy_p
&& upper_half_easy_p
)
3351 && !(code
== IOR
&& w1
== 0xffff
3352 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3354 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3355 output_asm_insn (insn_buf
, operands
);
3359 /* Take care of the lower and upper words individually. For
3360 each word, we try different methods in the order of
3362 1) the special insn (in case of AND or XOR),
3363 2) the word-wise insn, and
3364 3) The byte-wise insn. */
3366 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3367 output_asm_insn ((code
== AND
)
3368 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3370 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3374 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3375 output_asm_insn (insn_buf
, operands
);
3381 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3382 output_asm_insn (insn_buf
, operands
);
3386 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3387 output_asm_insn (insn_buf
, operands
);
3392 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3393 output_asm_insn ((code
== AND
)
3394 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3396 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3399 && (w0
& 0x8000) != 0)
3401 output_asm_insn ("exts.l\t%S0", operands
);
3403 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3407 output_asm_insn ("extu.w\t%e0", operands
);
3409 else if (TARGET_H8300H
|| TARGET_H8300S
)
3413 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3414 output_asm_insn (insn_buf
, operands
);
3421 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3422 output_asm_insn (insn_buf
, operands
);
3426 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3427 output_asm_insn (insn_buf
, operands
);
3438 /* Compute the length of a logical insn. */
3441 compute_logical_op_length (machine_mode mode
, rtx
*operands
)
3443 /* Figure out the logical op that we need to perform. */
3444 enum rtx_code code
= GET_CODE (operands
[3]);
3445 /* Pretend that every byte is affected if both operands are registers. */
3446 const unsigned HOST_WIDE_INT intval
=
3447 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3448 /* Always use the full instruction if the
3449 first operand is in memory. It is better
3450 to use define_splits to generate the shorter
3451 sequence where valid. */
3452 && register_operand (operands
[1], VOIDmode
)
3453 ? INTVAL (operands
[2]) : 0x55555555);
3454 /* The determinant of the algorithm. If we perform an AND, 0
3455 affects a bit. Otherwise, 1 affects a bit. */
3456 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3457 /* Break up DET into pieces. */
3458 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3459 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3460 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3461 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3462 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3463 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3464 int lower_half_easy_p
= 0;
3465 int upper_half_easy_p
= 0;
3467 unsigned int length
= 0;
3472 /* First, see if we can finish with one insn. */
3473 if ((TARGET_H8300H
|| TARGET_H8300S
)
3477 length
= h8300_length_from_table (operands
[1], operands
[2],
3478 &logicw_length_table
);
3482 /* Take care of the lower byte. */
3486 /* Take care of the upper byte. */
3492 if (TARGET_H8300H
|| TARGET_H8300S
)
3494 /* Determine if the lower half can be taken care of in no more
3496 lower_half_easy_p
= (b0
== 0
3498 || (code
!= IOR
&& w0
== 0xffff));
3500 /* Determine if the upper half can be taken care of in no more
3502 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3503 || (code
== AND
&& w1
== 0xff00));
3506 /* Check if doing everything with one insn is no worse than
3507 using multiple insns. */
3508 if ((TARGET_H8300H
|| TARGET_H8300S
)
3509 && w0
!= 0 && w1
!= 0
3510 && !(lower_half_easy_p
&& upper_half_easy_p
)
3511 && !(code
== IOR
&& w1
== 0xffff
3512 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3514 length
= h8300_length_from_table (operands
[1], operands
[2],
3515 &logicl_length_table
);
3519 /* Take care of the lower and upper words individually. For
3520 each word, we try different methods in the order of
3522 1) the special insn (in case of AND or XOR),
3523 2) the word-wise insn, and
3524 3) The byte-wise insn. */
3526 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3530 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3546 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3550 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3553 && (w0
& 0x8000) != 0)
3557 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3563 else if (TARGET_H8300H
|| TARGET_H8300S
)
3584 /* Compute which flag bits are valid after a logical insn. */
3587 compute_logical_op_cc (machine_mode mode
, rtx
*operands
)
3589 /* Figure out the logical op that we need to perform. */
3590 enum rtx_code code
= GET_CODE (operands
[3]);
3591 /* Pretend that every byte is affected if both operands are registers. */
3592 const unsigned HOST_WIDE_INT intval
=
3593 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3594 /* Always use the full instruction if the
3595 first operand is in memory. It is better
3596 to use define_splits to generate the shorter
3597 sequence where valid. */
3598 && register_operand (operands
[1], VOIDmode
)
3599 ? INTVAL (operands
[2]) : 0x55555555);
3600 /* The determinant of the algorithm. If we perform an AND, 0
3601 affects a bit. Otherwise, 1 affects a bit. */
3602 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3603 /* Break up DET into pieces. */
3604 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3605 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3606 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3607 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3608 int lower_half_easy_p
= 0;
3609 int upper_half_easy_p
= 0;
3610 /* Condition code. */
3611 enum attr_cc cc
= CC_CLOBBER
;
3616 /* First, see if we can finish with one insn. */
3617 if ((TARGET_H8300H
|| TARGET_H8300S
)
3625 if (TARGET_H8300H
|| TARGET_H8300S
)
3627 /* Determine if the lower half can be taken care of in no more
3629 lower_half_easy_p
= (b0
== 0
3631 || (code
!= IOR
&& w0
== 0xffff));
3633 /* Determine if the upper half can be taken care of in no more
3635 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3636 || (code
== AND
&& w1
== 0xff00));
3639 /* Check if doing everything with one insn is no worse than
3640 using multiple insns. */
3641 if ((TARGET_H8300H
|| TARGET_H8300S
)
3642 && w0
!= 0 && w1
!= 0
3643 && !(lower_half_easy_p
&& upper_half_easy_p
)
3644 && !(code
== IOR
&& w1
== 0xffff
3645 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3651 if ((TARGET_H8300H
|| TARGET_H8300S
)
3654 && (w0
& 0x8000) != 0)
3666 /* Expand a conditional branch. */
3669 h8300_expand_branch (rtx operands
[])
3671 enum rtx_code code
= GET_CODE (operands
[0]);
3672 rtx op0
= operands
[1];
3673 rtx op1
= operands
[2];
3674 rtx label
= operands
[3];
3677 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3678 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3680 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3681 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3682 gen_rtx_LABEL_REF (VOIDmode
, label
),
3684 emit_jump_insn (gen_rtx_SET (pc_rtx
, tmp
));
3688 /* Expand a conditional store. */
3691 h8300_expand_store (rtx operands
[])
3693 rtx dest
= operands
[0];
3694 enum rtx_code code
= GET_CODE (operands
[1]);
3695 rtx op0
= operands
[2];
3696 rtx op1
= operands
[3];
3699 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3700 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3702 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3703 emit_insn (gen_rtx_SET (dest
, tmp
));
3708 We devote a fair bit of code to getting efficient shifts since we
3709 can only shift one bit at a time on the H8/300 and H8/300H and only
3710 one or two bits at a time on the H8S.
3712 All shift code falls into one of the following ways of
3715 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3716 when a straight line shift is about the same size or smaller than
3719 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3720 off the bits we don't need. This is used when only a few of the
3721 bits in the original value will survive in the shifted value.
3723 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3724 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3725 shifts can be added if the shift count is slightly more than 8 or
3726 16. This case also includes other oddballs that are not worth
3729 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3731 For each shift count, we try to use code that has no trade-off
3732 between code size and speed whenever possible.
3734 If the trade-off is unavoidable, we try to be reasonable.
3735 Specifically, the fastest version is one instruction longer than
3736 the shortest version, we take the fastest version. We also provide
3737 the use a way to switch back to the shortest version with -Os.
3739 For the details of the shift algorithms for various shift counts,
3740 refer to shift_alg_[qhs]i. */
3742 /* Classify a shift with the given mode and code. OP is the shift amount. */
3744 enum h8sx_shift_type
3745 h8sx_classify_shift (machine_mode mode
, enum rtx_code code
, rtx op
)
3747 if (!TARGET_H8300SX
)
3748 return H8SX_SHIFT_NONE
;
3754 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3755 if (GET_CODE (op
) != CONST_INT
)
3756 return H8SX_SHIFT_BINARY
;
3758 /* Reject out-of-range shift amounts. */
3759 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3760 return H8SX_SHIFT_NONE
;
3762 /* Power-of-2 shifts are effectively unary operations. */
3763 if (exact_log2 (INTVAL (op
)) >= 0)
3764 return H8SX_SHIFT_UNARY
;
3766 return H8SX_SHIFT_BINARY
;
3769 if (op
== const1_rtx
|| op
== const2_rtx
)
3770 return H8SX_SHIFT_UNARY
;
3771 return H8SX_SHIFT_NONE
;
3774 if (GET_CODE (op
) == CONST_INT
3775 && (INTVAL (op
) == 1
3777 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3778 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3779 return H8SX_SHIFT_UNARY
;
3780 return H8SX_SHIFT_NONE
;
3783 return H8SX_SHIFT_NONE
;
3787 /* Return the asm template for a single h8sx shift instruction.
3788 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3789 is the source and OPERANDS[3] is the shift. SUFFIX is the
3790 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3791 prefix for the destination operand. */
3794 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3796 static char buffer
[16];
3799 switch (GET_CODE (operands
[3]))
3815 if (INTVAL (operands
[2]) > 2)
3817 /* This is really a right rotate. */
3818 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3819 - INTVAL (operands
[2]));
3827 if (operands
[2] == const1_rtx
)
3828 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3830 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3834 /* Emit code to do shifts. */
3837 expand_a_shift (machine_mode mode
, enum rtx_code code
, rtx operands
[])
3839 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3841 case H8SX_SHIFT_BINARY
:
3842 operands
[1] = force_reg (mode
, operands
[1]);
3845 case H8SX_SHIFT_UNARY
:
3848 case H8SX_SHIFT_NONE
:
3852 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3854 /* Need a loop to get all the bits we want - we generate the
3855 code at emit time, but need to allocate a scratch reg now. */
3857 emit_insn (gen_rtx_PARALLEL
3860 gen_rtx_SET (copy_rtx (operands
[0]),
3861 gen_rtx_fmt_ee (code
, mode
,
3862 copy_rtx (operands
[0]), operands
[2])),
3863 gen_rtx_CLOBBER (VOIDmode
,
3864 gen_rtx_SCRATCH (QImode
)))));
3868 /* Symbols of the various modes which can be used as indices. */
3872 QIshift
, HIshift
, SIshift
3875 /* For single bit shift insns, record assembler and what bits of the
3876 condition code are valid afterwards (represented as various CC_FOO
3877 bits, 0 means CC isn't left in a usable state). */
3881 const char *const assembler
;
3882 const enum attr_cc cc_valid
;
3885 /* Assembler instruction shift table.
3887 These tables are used to look up the basic shifts.
3888 They are indexed by cpu, shift_type, and mode. */
3890 static const struct shift_insn shift_one
[2][3][3] =
3896 { "shll\t%X0", CC_SET_ZNV
},
3897 { "add.w\t%T0,%T0", CC_SET_ZN
},
3898 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3900 /* SHIFT_LSHIFTRT */
3902 { "shlr\t%X0", CC_SET_ZNV
},
3903 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3904 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3906 /* SHIFT_ASHIFTRT */
3908 { "shar\t%X0", CC_SET_ZNV
},
3909 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3910 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3917 { "shll.b\t%X0", CC_SET_ZNV
},
3918 { "shll.w\t%T0", CC_SET_ZNV
},
3919 { "shll.l\t%S0", CC_SET_ZNV
}
3921 /* SHIFT_LSHIFTRT */
3923 { "shlr.b\t%X0", CC_SET_ZNV
},
3924 { "shlr.w\t%T0", CC_SET_ZNV
},
3925 { "shlr.l\t%S0", CC_SET_ZNV
}
3927 /* SHIFT_ASHIFTRT */
3929 { "shar.b\t%X0", CC_SET_ZNV
},
3930 { "shar.w\t%T0", CC_SET_ZNV
},
3931 { "shar.l\t%S0", CC_SET_ZNV
}
3936 static const struct shift_insn shift_two
[3][3] =
3940 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3941 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3942 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3944 /* SHIFT_LSHIFTRT */
3946 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3947 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3948 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3950 /* SHIFT_ASHIFTRT */
3952 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3953 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3954 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3958 /* Rotates are organized by which shift they'll be used in implementing.
3959 There's no need to record whether the cc is valid afterwards because
3960 it is the AND insn that will decide this. */
3962 static const char *const rotate_one
[2][3][3] =
3969 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3972 /* SHIFT_LSHIFTRT */
3975 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3978 /* SHIFT_ASHIFTRT */
3981 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3993 /* SHIFT_LSHIFTRT */
3999 /* SHIFT_ASHIFTRT */
4008 static const char *const rotate_two
[3][3] =
4016 /* SHIFT_LSHIFTRT */
4022 /* SHIFT_ASHIFTRT */
4031 /* Shift algorithm. */
4034 /* The number of bits to be shifted by shift1 and shift2. Valid
4035 when ALG is SHIFT_SPECIAL. */
4036 unsigned int remainder
;
4038 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4039 const char *special
;
4041 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4042 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4045 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4046 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4049 /* CC status for SHIFT_INLINE. */
4050 enum attr_cc cc_inline
;
4052 /* CC status for SHIFT_SPECIAL. */
4053 enum attr_cc cc_special
;
4056 static void get_shift_alg (enum shift_type
,
4057 enum shift_mode
, unsigned int,
4058 struct shift_info
*);
4060 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4061 best algorithm for doing the shift. The assembler code is stored
4062 in the pointers in INFO. We achieve the maximum efficiency in most
4063 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4064 SImode in particular have a lot of room to optimize.
4066 We first determine the strategy of the shift algorithm by a table
4067 lookup. If that tells us to use a hand crafted assembly code, we
4068 go into the big switch statement to find what that is. Otherwise,
4069 we resort to a generic way, such as inlining. In either case, the
4070 result is returned through INFO. */
4073 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4074 unsigned int count
, struct shift_info
*info
)
4078 /* Find the target CPU. */
4081 else if (TARGET_H8300S
)
4086 /* Find the shift algorithm. */
4087 info
->alg
= SHIFT_LOOP
;
4091 if (count
< GET_MODE_BITSIZE (QImode
))
4092 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4096 if (count
< GET_MODE_BITSIZE (HImode
))
4097 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4101 if (count
< GET_MODE_BITSIZE (SImode
))
4102 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4109 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4113 info
->remainder
= count
;
4117 /* It is up to the caller to know that looping clobbers cc. */
4118 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4119 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4120 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4124 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4125 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4126 info
->cc_inline
= CC_CLOBBER
;
4130 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4131 info
->remainder
= 0;
4132 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4133 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4134 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4135 info
->cc_special
= CC_CLOBBER
;
4139 /* Here we only deal with SHIFT_SPECIAL. */
4143 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4144 through the entire value. */
4145 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4146 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4156 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4158 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4160 case SHIFT_LSHIFTRT
:
4162 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4164 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4166 case SHIFT_ASHIFTRT
:
4167 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4171 else if ((8 <= count
&& count
<= 13)
4172 || (TARGET_H8300S
&& count
== 14))
4174 info
->remainder
= count
- 8;
4179 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4181 case SHIFT_LSHIFTRT
:
4184 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4185 info
->shift1
= "shlr.b\t%s0";
4186 info
->cc_inline
= CC_SET_ZNV
;
4190 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4191 info
->cc_special
= CC_SET_ZNV
;
4194 case SHIFT_ASHIFTRT
:
4197 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4198 info
->shift1
= "shar.b\t%s0";
4202 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4203 info
->cc_special
= CC_SET_ZNV
;
4208 else if (count
== 14)
4214 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4216 case SHIFT_LSHIFTRT
:
4218 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4220 case SHIFT_ASHIFTRT
:
4222 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4223 else if (TARGET_H8300H
)
4225 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4226 info
->cc_special
= CC_SET_ZNV
;
4228 else /* TARGET_H8300S */
4233 else if (count
== 15)
4238 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4240 case SHIFT_LSHIFTRT
:
4241 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4243 case SHIFT_ASHIFTRT
:
4244 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4251 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4253 info
->remainder
= count
- 8;
4258 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4260 case SHIFT_LSHIFTRT
:
4261 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4262 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4264 case SHIFT_ASHIFTRT
:
4265 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4269 else if (count
== 8 && !TARGET_H8300
)
4274 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4276 case SHIFT_LSHIFTRT
:
4277 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4279 case SHIFT_ASHIFTRT
:
4280 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4284 else if (count
== 15 && TARGET_H8300
)
4290 case SHIFT_LSHIFTRT
:
4291 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4293 case SHIFT_ASHIFTRT
:
4294 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4298 else if (count
== 15 && !TARGET_H8300
)
4303 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4304 info
->cc_special
= CC_SET_ZNV
;
4306 case SHIFT_LSHIFTRT
:
4307 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4308 info
->cc_special
= CC_SET_ZNV
;
4310 case SHIFT_ASHIFTRT
:
4314 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4315 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4316 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4318 info
->remainder
= count
- 16;
4323 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4325 info
->shift1
= "add.w\t%e0,%e0";
4327 case SHIFT_LSHIFTRT
:
4330 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4331 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4335 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4336 info
->cc_special
= CC_SET_ZNV
;
4339 case SHIFT_ASHIFTRT
:
4342 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4343 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4347 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4348 info
->cc_special
= CC_SET_ZNV
;
4353 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4355 info
->remainder
= count
- 24;
4360 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4361 info
->shift1
= "shll.b\t%z0";
4362 info
->cc_inline
= CC_SET_ZNV
;
4364 case SHIFT_LSHIFTRT
:
4365 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4366 info
->shift1
= "shlr.b\t%w0";
4367 info
->cc_inline
= CC_SET_ZNV
;
4369 case SHIFT_ASHIFTRT
:
4370 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4371 info
->shift1
= "shar.b\t%w0";
4372 info
->cc_inline
= CC_SET_ZNV
;
4376 else if ((TARGET_H8300H
&& count
== 24)
4377 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4379 info
->remainder
= count
- 24;
4384 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4386 case SHIFT_LSHIFTRT
:
4387 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4388 info
->cc_special
= CC_SET_ZNV
;
4390 case SHIFT_ASHIFTRT
:
4391 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4392 info
->cc_special
= CC_SET_ZNV
;
4396 else if (!TARGET_H8300
&& count
== 28)
4402 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4404 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4406 case SHIFT_LSHIFTRT
:
4409 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4410 info
->cc_special
= CC_SET_ZNV
;
4413 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4415 case SHIFT_ASHIFTRT
:
4419 else if (!TARGET_H8300
&& count
== 29)
4425 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4427 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4429 case SHIFT_LSHIFTRT
:
4432 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4433 info
->cc_special
= CC_SET_ZNV
;
4437 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4438 info
->cc_special
= CC_SET_ZNV
;
4441 case SHIFT_ASHIFTRT
:
4445 else if (!TARGET_H8300
&& count
== 30)
4451 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4453 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4455 case SHIFT_LSHIFTRT
:
4457 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4459 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4461 case SHIFT_ASHIFTRT
:
4465 else if (count
== 31)
4472 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4474 case SHIFT_LSHIFTRT
:
4475 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4477 case SHIFT_ASHIFTRT
:
4478 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4487 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4488 info
->cc_special
= CC_SET_ZNV
;
4490 case SHIFT_LSHIFTRT
:
4491 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4492 info
->cc_special
= CC_SET_ZNV
;
4494 case SHIFT_ASHIFTRT
:
4495 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4496 info
->cc_special
= CC_SET_ZNV
;
4509 info
->shift2
= NULL
;
4512 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4513 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4516 h8300_shift_needs_scratch_p (int count
, machine_mode mode
)
4521 if (GET_MODE_BITSIZE (mode
) <= count
)
4524 /* Find out the target CPU. */
4527 else if (TARGET_H8300S
)
4532 /* Find the shift algorithm. */
4536 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4537 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4538 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4542 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4543 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4544 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4548 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4549 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4550 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4557 /* On H8/300H, count == 8 uses a scratch register. */
4558 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4559 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4562 /* Output the assembler code for doing shifts. */
4565 output_a_shift (rtx
*operands
)
4567 static int loopend_lab
;
4568 rtx shift
= operands
[3];
4569 machine_mode mode
= GET_MODE (shift
);
4570 enum rtx_code code
= GET_CODE (shift
);
4571 enum shift_type shift_type
;
4572 enum shift_mode shift_mode
;
4573 struct shift_info info
;
4581 shift_mode
= QIshift
;
4584 shift_mode
= HIshift
;
4587 shift_mode
= SIshift
;
4596 shift_type
= SHIFT_ASHIFTRT
;
4599 shift_type
= SHIFT_LSHIFTRT
;
4602 shift_type
= SHIFT_ASHIFT
;
4608 /* This case must be taken care of by one of the two splitters
4609 that convert a variable shift into a loop. */
4610 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4612 n
= INTVAL (operands
[2]);
4614 /* If the count is negative, make it 0. */
4617 /* If the count is too big, truncate it.
4618 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4619 do the intuitive thing. */
4620 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4621 n
= GET_MODE_BITSIZE (mode
);
4623 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4628 output_asm_insn (info
.special
, operands
);
4634 /* Emit two bit shifts first. */
4635 if (info
.shift2
!= NULL
)
4637 for (; n
> 1; n
-= 2)
4638 output_asm_insn (info
.shift2
, operands
);
4641 /* Now emit one bit shifts for any residual. */
4643 output_asm_insn (info
.shift1
, operands
);
4648 int m
= GET_MODE_BITSIZE (mode
) - n
;
4649 const int mask
= (shift_type
== SHIFT_ASHIFT
4650 ? ((1 << m
) - 1) << n
4654 /* Not all possibilities of rotate are supported. They shouldn't
4655 be generated, but let's watch for 'em. */
4656 gcc_assert (info
.shift1
);
4658 /* Emit two bit rotates first. */
4659 if (info
.shift2
!= NULL
)
4661 for (; m
> 1; m
-= 2)
4662 output_asm_insn (info
.shift2
, operands
);
4665 /* Now single bit rotates for any residual. */
4667 output_asm_insn (info
.shift1
, operands
);
4669 /* Now mask off the high bits. */
4673 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4677 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4678 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4685 output_asm_insn (insn_buf
, operands
);
4690 /* A loop to shift by a "large" constant value.
4691 If we have shift-by-2 insns, use them. */
4692 if (info
.shift2
!= NULL
)
4694 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4695 names_big
[REGNO (operands
[4])]);
4696 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4697 output_asm_insn (info
.shift2
, operands
);
4698 output_asm_insn ("add #0xff,%X4", operands
);
4699 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4701 output_asm_insn (info
.shift1
, operands
);
4705 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4706 names_big
[REGNO (operands
[4])]);
4707 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4708 output_asm_insn (info
.shift1
, operands
);
4709 output_asm_insn ("add #0xff,%X4", operands
);
4710 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4719 /* Count the number of assembly instructions in a string TEMPL. */
4722 h8300_asm_insn_count (const char *templ
)
4724 unsigned int count
= 1;
4726 for (; *templ
; templ
++)
4733 /* Compute the length of a shift insn. */
4736 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4738 rtx shift
= operands
[3];
4739 machine_mode mode
= GET_MODE (shift
);
4740 enum rtx_code code
= GET_CODE (shift
);
4741 enum shift_type shift_type
;
4742 enum shift_mode shift_mode
;
4743 struct shift_info info
;
4744 unsigned int wlength
= 0;
4749 shift_mode
= QIshift
;
4752 shift_mode
= HIshift
;
4755 shift_mode
= SIshift
;
4764 shift_type
= SHIFT_ASHIFTRT
;
4767 shift_type
= SHIFT_LSHIFTRT
;
4770 shift_type
= SHIFT_ASHIFT
;
4776 if (GET_CODE (operands
[2]) != CONST_INT
)
4778 /* Get the assembler code to do one shift. */
4779 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4781 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4785 int n
= INTVAL (operands
[2]);
4787 /* If the count is negative, make it 0. */
4790 /* If the count is too big, truncate it.
4791 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4792 do the intuitive thing. */
4793 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4794 n
= GET_MODE_BITSIZE (mode
);
4796 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4801 wlength
+= h8300_asm_insn_count (info
.special
);
4803 /* Every assembly instruction used in SHIFT_SPECIAL case
4804 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4805 see xor.l, we just pretend that xor.l counts as two insns
4806 so that the insn length will be computed correctly. */
4807 if (strstr (info
.special
, "xor.l") != NULL
)
4815 if (info
.shift2
!= NULL
)
4817 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4821 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4827 int m
= GET_MODE_BITSIZE (mode
) - n
;
4829 /* Not all possibilities of rotate are supported. They shouldn't
4830 be generated, but let's watch for 'em. */
4831 gcc_assert (info
.shift1
);
4833 if (info
.shift2
!= NULL
)
4835 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4839 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4841 /* Now mask off the high bits. */
4851 gcc_assert (!TARGET_H8300
);
4861 /* A loop to shift by a "large" constant value.
4862 If we have shift-by-2 insns, use them. */
4863 if (info
.shift2
!= NULL
)
4865 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4867 wlength
+= h8300_asm_insn_count (info
.shift1
);
4871 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4881 /* Compute which flag bits are valid after a shift insn. */
4884 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4886 rtx shift
= operands
[3];
4887 machine_mode mode
= GET_MODE (shift
);
4888 enum rtx_code code
= GET_CODE (shift
);
4889 enum shift_type shift_type
;
4890 enum shift_mode shift_mode
;
4891 struct shift_info info
;
4897 shift_mode
= QIshift
;
4900 shift_mode
= HIshift
;
4903 shift_mode
= SIshift
;
4912 shift_type
= SHIFT_ASHIFTRT
;
4915 shift_type
= SHIFT_LSHIFTRT
;
4918 shift_type
= SHIFT_ASHIFT
;
4924 /* This case must be taken care of by one of the two splitters
4925 that convert a variable shift into a loop. */
4926 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4928 n
= INTVAL (operands
[2]);
4930 /* If the count is negative, make it 0. */
4933 /* If the count is too big, truncate it.
4934 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4935 do the intuitive thing. */
4936 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4937 n
= GET_MODE_BITSIZE (mode
);
4939 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4944 if (info
.remainder
== 0)
4945 return info
.cc_special
;
4950 return info
.cc_inline
;
4953 /* This case always ends with an and instruction. */
4957 /* A loop to shift by a "large" constant value.
4958 If we have shift-by-2 insns, use them. */
4959 if (info
.shift2
!= NULL
)
4962 return info
.cc_inline
;
4971 /* A rotation by a non-constant will cause a loop to be generated, in
4972 which a rotation by one bit is used. A rotation by a constant,
4973 including the one in the loop, will be taken care of by
4974 output_a_rotate () at the insn emit time. */
4977 expand_a_rotate (rtx operands
[])
4979 rtx dst
= operands
[0];
4980 rtx src
= operands
[1];
4981 rtx rotate_amount
= operands
[2];
4982 machine_mode mode
= GET_MODE (dst
);
4984 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4987 /* We rotate in place. */
4988 emit_move_insn (dst
, src
);
4990 if (GET_CODE (rotate_amount
) != CONST_INT
)
4992 rtx counter
= gen_reg_rtx (QImode
);
4993 rtx_code_label
*start_label
= gen_label_rtx ();
4994 rtx_code_label
*end_label
= gen_label_rtx ();
4996 /* If the rotate amount is less than or equal to 0,
4997 we go out of the loop. */
4998 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4999 QImode
, 0, end_label
);
5001 /* Initialize the loop counter. */
5002 emit_move_insn (counter
, rotate_amount
);
5004 emit_label (start_label
);
5006 /* Rotate by one bit. */
5010 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
5013 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
5016 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
5022 /* Decrement the counter by 1. */
5023 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
5025 /* If the loop counter is nonzero, we go back to the beginning
5027 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
5030 emit_label (end_label
);
5034 /* Rotate by AMOUNT bits. */
5038 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
5041 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
5044 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
5054 /* Output a rotate insn. */
5057 output_a_rotate (enum rtx_code code
, rtx
*operands
)
5059 rtx dst
= operands
[0];
5060 rtx rotate_amount
= operands
[2];
5061 enum shift_mode rotate_mode
;
5062 enum shift_type rotate_type
;
5063 const char *insn_buf
;
5066 machine_mode mode
= GET_MODE (dst
);
5068 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
5073 rotate_mode
= QIshift
;
5076 rotate_mode
= HIshift
;
5079 rotate_mode
= SIshift
;
5088 rotate_type
= SHIFT_ASHIFT
;
5091 rotate_type
= SHIFT_LSHIFTRT
;
5097 amount
= INTVAL (rotate_amount
);
5099 /* Clean up AMOUNT. */
5102 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5103 amount
= GET_MODE_BITSIZE (mode
);
5105 /* Determine the faster direction. After this phase, amount will be
5106 at most a half of GET_MODE_BITSIZE (mode). */
5107 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5109 /* Flip the direction. */
5110 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5112 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5115 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5116 boost up the rotation. */
5117 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5118 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5119 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5120 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5121 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5126 /* This code works on any family. */
5127 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5128 output_asm_insn (insn_buf
, operands
);
5132 /* This code works on the H8/300H and H8S. */
5133 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5134 output_asm_insn (insn_buf
, operands
);
5141 /* Adjust AMOUNT and flip the direction. */
5142 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5144 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5147 /* Output rotate insns. */
5148 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5151 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5153 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5155 for (; amount
>= bits
; amount
-= bits
)
5156 output_asm_insn (insn_buf
, operands
);
5162 /* Compute the length of a rotate insn. */
5165 compute_a_rotate_length (rtx
*operands
)
5167 rtx src
= operands
[1];
5168 rtx amount_rtx
= operands
[2];
5169 machine_mode mode
= GET_MODE (src
);
5171 unsigned int length
= 0;
5173 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5175 amount
= INTVAL (amount_rtx
);
5177 /* Clean up AMOUNT. */
5180 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5181 amount
= GET_MODE_BITSIZE (mode
);
5183 /* Determine the faster direction. After this phase, amount
5184 will be at most a half of GET_MODE_BITSIZE (mode). */
5185 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5186 /* Flip the direction. */
5187 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5189 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5190 boost up the rotation. */
5191 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5192 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5193 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5194 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5195 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5197 /* Adjust AMOUNT and flip the direction. */
5198 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5202 /* We use 2-bit rotations on the H8S. */
5204 amount
= amount
/ 2 + amount
% 2;
5206 /* The H8/300 uses three insns to rotate one bit, taking 6
5208 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5213 /* Fix the operands of a gen_xxx so that it could become a bit
5217 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5219 /* The bit_operand predicate accepts any memory during RTL generation, but
5220 only 'U' memory afterwards, so if this is a MEM operand, we must force
5221 it to be valid for 'U' by reloading the address. */
5224 ? single_zero_operand (operands
[2], QImode
)
5225 : single_one_operand (operands
[2], QImode
))
5227 /* OK to have a memory dest. */
5228 if (GET_CODE (operands
[0]) == MEM
5229 && !satisfies_constraint_U (operands
[0]))
5231 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5232 copy_to_mode_reg (Pmode
,
5233 XEXP (operands
[0], 0)));
5234 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5238 if (GET_CODE (operands
[1]) == MEM
5239 && !satisfies_constraint_U (operands
[1]))
5241 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5242 copy_to_mode_reg (Pmode
,
5243 XEXP (operands
[1], 0)));
5244 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5250 /* Dest and src op must be register. */
5252 operands
[1] = force_reg (QImode
, operands
[1]);
5254 rtx res
= gen_reg_rtx (QImode
);
5258 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5261 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5264 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5269 emit_insn (gen_movqi (operands
[0], res
));
5274 /* Return nonzero if FUNC is an interrupt function as specified
5275 by the "interrupt" attribute. */
5278 h8300_interrupt_function_p (tree func
)
5282 if (TREE_CODE (func
) != FUNCTION_DECL
)
5285 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5286 return a
!= NULL_TREE
;
5289 /* Return nonzero if FUNC is a saveall function as specified by the
5290 "saveall" attribute. */
5293 h8300_saveall_function_p (tree func
)
5297 if (TREE_CODE (func
) != FUNCTION_DECL
)
5300 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5301 return a
!= NULL_TREE
;
5304 /* Return nonzero if FUNC is an OS_Task function as specified
5305 by the "OS_Task" attribute. */
5308 h8300_os_task_function_p (tree func
)
5312 if (TREE_CODE (func
) != FUNCTION_DECL
)
5315 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5316 return a
!= NULL_TREE
;
5319 /* Return nonzero if FUNC is a monitor function as specified
5320 by the "monitor" attribute. */
5323 h8300_monitor_function_p (tree func
)
5327 if (TREE_CODE (func
) != FUNCTION_DECL
)
5330 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5331 return a
!= NULL_TREE
;
5334 /* Return nonzero if FUNC is a function that should be called
5335 through the function vector. */
5338 h8300_funcvec_function_p (tree func
)
5342 if (TREE_CODE (func
) != FUNCTION_DECL
)
5345 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5346 return a
!= NULL_TREE
;
5349 /* Return nonzero if DECL is a variable that's in the eight bit
5353 h8300_eightbit_data_p (tree decl
)
5357 if (TREE_CODE (decl
) != VAR_DECL
)
5360 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5361 return a
!= NULL_TREE
;
5364 /* Return nonzero if DECL is a variable that's in the tiny
5368 h8300_tiny_data_p (tree decl
)
5372 if (TREE_CODE (decl
) != VAR_DECL
)
5375 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5376 return a
!= NULL_TREE
;
5379 /* Generate an 'interrupt_handler' attribute for decls. We convert
5380 all the pragmas to corresponding attributes. */
5383 h8300_insert_attributes (tree node
, tree
*attributes
)
5385 if (TREE_CODE (node
) == FUNCTION_DECL
)
5387 if (pragma_interrupt
)
5389 pragma_interrupt
= 0;
5391 /* Add an 'interrupt_handler' attribute. */
5392 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5400 /* Add an 'saveall' attribute. */
5401 *attributes
= tree_cons (get_identifier ("saveall"),
5407 /* Supported attributes:
5409 interrupt_handler: output a prologue and epilogue suitable for an
5412 saveall: output a prologue and epilogue that saves and restores
5413 all registers except the stack pointer.
5415 function_vector: This function should be called through the
5418 eightbit_data: This variable lives in the 8-bit data area and can
5419 be referenced with 8-bit absolute memory addresses.
5421 tiny_data: This variable lives in the tiny data area and can be
5422 referenced with 16-bit absolute memory references. */
5424 static const struct attribute_spec h8300_attribute_table
[] =
5426 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5427 affects_type_identity } */
5428 { "interrupt_handler", 0, 0, true, false, false,
5429 h8300_handle_fndecl_attribute
, false },
5430 { "saveall", 0, 0, true, false, false,
5431 h8300_handle_fndecl_attribute
, false },
5432 { "OS_Task", 0, 0, true, false, false,
5433 h8300_handle_fndecl_attribute
, false },
5434 { "monitor", 0, 0, true, false, false,
5435 h8300_handle_fndecl_attribute
, false },
5436 { "function_vector", 0, 0, true, false, false,
5437 h8300_handle_fndecl_attribute
, false },
5438 { "eightbit_data", 0, 0, true, false, false,
5439 h8300_handle_eightbit_data_attribute
, false },
5440 { "tiny_data", 0, 0, true, false, false,
5441 h8300_handle_tiny_data_attribute
, false },
5442 { NULL
, 0, 0, false, false, false, NULL
, false }
5446 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5447 struct attribute_spec.handler. */
5449 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5450 tree args ATTRIBUTE_UNUSED
,
5451 int flags ATTRIBUTE_UNUSED
,
5454 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5456 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5458 *no_add_attrs
= true;
5464 /* Handle an "eightbit_data" attribute; arguments as in
5465 struct attribute_spec.handler. */
5467 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5468 tree args ATTRIBUTE_UNUSED
,
5469 int flags ATTRIBUTE_UNUSED
,
5474 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5476 set_decl_section_name (decl
, ".eight");
5480 warning (OPT_Wattributes
, "%qE attribute ignored",
5482 *no_add_attrs
= true;
5488 /* Handle an "tiny_data" attribute; arguments as in
5489 struct attribute_spec.handler. */
5491 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5492 tree args ATTRIBUTE_UNUSED
,
5493 int flags ATTRIBUTE_UNUSED
,
5498 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5500 set_decl_section_name (decl
, ".tiny");
5504 warning (OPT_Wattributes
, "%qE attribute ignored",
5506 *no_add_attrs
= true;
5512 /* Mark function vectors, and various small data objects. */
5515 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5517 int extra_flags
= 0;
5519 default_encode_section_info (decl
, rtl
, first
);
5521 if (TREE_CODE (decl
) == FUNCTION_DECL
5522 && h8300_funcvec_function_p (decl
))
5523 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5524 else if (TREE_CODE (decl
) == VAR_DECL
5525 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5527 if (h8300_eightbit_data_p (decl
))
5528 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5529 else if (first
&& h8300_tiny_data_p (decl
))
5530 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5534 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5537 /* Output a single-bit extraction. */
5540 output_simode_bld (int bild
, rtx operands
[])
5544 /* Clear the destination register. */
5545 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5547 /* Now output the bit load or bit inverse load, and store it in
5550 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5552 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5554 output_asm_insn ("bst\t#0,%w0", operands
);
5558 /* Determine if we can clear the destination first. */
5559 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5560 && REGNO (operands
[0]) != REGNO (operands
[1]));
5563 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5565 /* Output the bit load or bit inverse load. */
5567 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5569 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5572 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5574 /* Perform the bit store. */
5575 output_asm_insn ("rotxl.l\t%S0", operands
);
5582 /* Delayed-branch scheduling is more effective if we have some idea
5583 how long each instruction will be. Use a shorten_branches pass
5584 to get an initial estimate. */
5589 if (flag_delayed_branch
)
5590 shorten_branches (get_insns ());
5593 #ifndef OBJECT_FORMAT_ELF
5595 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5598 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5599 fprintf (asm_out_file
, "\t.section %s\n", name
);
5601 #endif /* ! OBJECT_FORMAT_ELF */
5603 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5604 which is a special case of the 'R' operand. */
5607 h8300_eightbit_constant_address_p (rtx x
)
5609 /* The ranges of the 8-bit area. */
5610 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5611 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5612 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5613 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5614 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5615 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5617 unsigned HOST_WIDE_INT addr
;
5619 /* We accept symbols declared with eightbit_data. */
5620 if (GET_CODE (x
) == SYMBOL_REF
)
5621 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5623 if (GET_CODE (x
) == CONST
5624 && GET_CODE (XEXP (x
, 0)) == PLUS
5625 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
5626 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x
, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0)
5629 if (GET_CODE (x
) != CONST_INT
)
5635 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5636 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5637 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5640 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5641 on H8/300H and H8S. */
5644 h8300_tiny_constant_address_p (rtx x
)
5646 /* The ranges of the 16-bit area. */
5647 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5648 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5649 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5650 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5651 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5652 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5653 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5654 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5656 unsigned HOST_WIDE_INT addr
;
5658 switch (GET_CODE (x
))
5661 /* In the normal mode, any symbol fits in the 16-bit absolute
5662 address range. We also accept symbols declared with
5664 return (TARGET_NORMAL_MODE
5665 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5669 return (TARGET_NORMAL_MODE
5671 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5673 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5676 return TARGET_NORMAL_MODE
;
5684 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5685 locations that can be accessed as a 16-bit word. */
5688 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5690 HOST_WIDE_INT offset1
, offset2
;
5698 else if (GET_CODE (addr1
) == PLUS
5699 && REG_P (XEXP (addr1
, 0))
5700 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5702 reg1
= XEXP (addr1
, 0);
5703 offset1
= INTVAL (XEXP (addr1
, 1));
5713 else if (GET_CODE (addr2
) == PLUS
5714 && REG_P (XEXP (addr2
, 0))
5715 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5717 reg2
= XEXP (addr2
, 0);
5718 offset2
= INTVAL (XEXP (addr2
, 1));
5723 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5724 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5726 && offset1
+ 1 == offset2
)
5732 /* Return nonzero if we have the same comparison insn as I3 two insns
5733 before I3. I3 is assumed to be a comparison insn. */
5736 same_cmp_preceding_p (rtx_insn
*i3
)
5740 /* Make sure we have a sequence of three insns. */
5741 i2
= prev_nonnote_insn (i3
);
5744 i1
= prev_nonnote_insn (i2
);
5748 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5749 && any_condjump_p (i2
) && onlyjump_p (i2
));
5752 /* Return nonzero if we have the same comparison insn as I1 two insns
5753 after I1. I1 is assumed to be a comparison insn. */
5756 same_cmp_following_p (rtx_insn
*i1
)
5760 /* Make sure we have a sequence of three insns. */
5761 i2
= next_nonnote_insn (i1
);
5764 i3
= next_nonnote_insn (i2
);
5768 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5769 && any_condjump_p (i2
) && onlyjump_p (i2
));
5772 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5773 (or pops) N registers. OPERANDS are assumed to be an array of
5777 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5782 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5783 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5784 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5786 return ((REGNO (operands
[0]) == 0
5787 && REGNO (operands
[1]) == 1
5788 && REGNO (operands
[2]) == 2)
5789 || (REGNO (operands
[0]) == 4
5790 && REGNO (operands
[1]) == 5
5791 && REGNO (operands
[2]) == 6));
5794 return (REGNO (operands
[0]) == 0
5795 && REGNO (operands
[1]) == 1
5796 && REGNO (operands
[2]) == 2
5797 && REGNO (operands
[3]) == 3);
5803 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5806 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5807 unsigned int new_reg
)
5809 /* Interrupt functions can only use registers that have already been
5810 saved by the prologue, even if they would normally be
5813 if (h8300_current_function_interrupt_function_p ()
5814 && !df_regs_ever_live_p (new_reg
))
5820 /* Returns true if register REGNO is safe to be allocated as a scratch
5821 register in the current function. */
5824 h8300_hard_regno_scratch_ok (unsigned int regno
)
5826 if (h8300_current_function_interrupt_function_p ()
5827 && ! WORD_REG_USED (regno
))
5834 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5837 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5839 /* Strip off SUBREG if any. */
5840 if (GET_CODE (x
) == SUBREG
)
5845 ? REG_OK_FOR_BASE_STRICT_P (x
)
5846 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5849 /* Return nozero if X is a legitimate address. On the H8/300, a
5850 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5851 CONSTANT_ADDRESS. */
5854 h8300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
5856 /* The register indirect addresses like @er0 is always valid. */
5857 if (h8300_rtx_ok_for_base_p (x
, strict
))
5860 if (CONSTANT_ADDRESS_P (x
))
5864 && ( GET_CODE (x
) == PRE_INC
5865 || GET_CODE (x
) == PRE_DEC
5866 || GET_CODE (x
) == POST_INC
5867 || GET_CODE (x
) == POST_DEC
)
5868 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5871 if (GET_CODE (x
) == PLUS
5872 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5873 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5880 /* Worker function for HARD_REGNO_NREGS.
5882 We pretend the MAC register is 32bits -- we don't have any data
5883 types on the H8 series to handle more than 32bits. */
5886 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, machine_mode mode
)
5888 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5891 /* Worker function for HARD_REGNO_MODE_OK. */
5894 h8300_hard_regno_mode_ok (int regno
, machine_mode mode
)
5897 /* If an even reg, then anything goes. Otherwise the mode must be
5899 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5901 /* MAC register can only be of SImode. Otherwise, anything
5903 return regno
== MAC_REG
? mode
== SImode
: 1;
5906 /* Helper function for the move patterns. Make sure a move is legitimate. */
5909 h8300_move_ok (rtx dest
, rtx src
)
5913 /* Validate that at least one operand is a register. */
5916 if (MEM_P (src
) || CONSTANT_P (src
))
5918 addr
= XEXP (dest
, 0);
5921 else if (MEM_P (src
))
5923 addr
= XEXP (src
, 0);
5929 /* Validate that auto-inc doesn't affect OTHER. */
5930 if (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
)
5932 addr
= XEXP (addr
, 0);
5934 if (addr
== stack_pointer_rtx
)
5935 return register_no_sp_elim_operand (other
, VOIDmode
);
5937 return !reg_overlap_mentioned_p(other
, addr
);
5940 /* Perform target dependent optabs initialization. */
5942 h8300_init_libfuncs (void)
5944 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5945 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5946 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5947 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5948 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5951 /* Worker function for TARGET_FUNCTION_VALUE.
5953 On the H8 the return value is in R0/R1. */
5956 h8300_function_value (const_tree ret_type
,
5957 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5958 bool outgoing ATTRIBUTE_UNUSED
)
5960 return gen_rtx_REG (TYPE_MODE (ret_type
), R0_REG
);
5963 /* Worker function for TARGET_LIBCALL_VALUE.
5965 On the H8 the return value is in R0/R1. */
5968 h8300_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5970 return gen_rtx_REG (mode
, R0_REG
);
5973 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5975 On the H8, R0 is the only register thus used. */
5978 h8300_function_value_regno_p (const unsigned int regno
)
5980 return (regno
== R0_REG
);
5983 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5986 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5988 return (TYPE_MODE (type
) == BLKmode
5989 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5992 /* We emit the entire trampoline here. Depending on the pointer size,
5993 we use a different trampoline.
5997 1 0000 7903xxxx mov.w #0x1234,r3
5998 2 0004 5A00xxxx jmp @0x1234
6003 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6004 3 0006 5Axxxxxx jmp @0x123456
6009 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
6011 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6014 if (Pmode
== HImode
)
6016 mem
= adjust_address (m_tramp
, HImode
, 0);
6017 emit_move_insn (mem
, GEN_INT (0x7903));
6018 mem
= adjust_address (m_tramp
, Pmode
, 2);
6019 emit_move_insn (mem
, cxt
);
6020 mem
= adjust_address (m_tramp
, HImode
, 4);
6021 emit_move_insn (mem
, GEN_INT (0x5a00));
6022 mem
= adjust_address (m_tramp
, Pmode
, 6);
6023 emit_move_insn (mem
, fnaddr
);
6029 mem
= adjust_address (m_tramp
, HImode
, 0);
6030 emit_move_insn (mem
, GEN_INT (0x7a03));
6031 mem
= adjust_address (m_tramp
, Pmode
, 2);
6032 emit_move_insn (mem
, cxt
);
6034 tem
= copy_to_reg (fnaddr
);
6035 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
6036 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
6037 mem
= adjust_address (m_tramp
, SImode
, 6);
6038 emit_move_insn (mem
, tem
);
6042 /* Initialize the GCC target structure. */
6043 #undef TARGET_ATTRIBUTE_TABLE
6044 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6046 #undef TARGET_ASM_ALIGNED_HI_OP
6047 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6049 #undef TARGET_ASM_FILE_START
6050 #define TARGET_ASM_FILE_START h8300_file_start
6051 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6052 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6054 #undef TARGET_ASM_FILE_END
6055 #define TARGET_ASM_FILE_END h8300_file_end
6057 #undef TARGET_PRINT_OPERAND
6058 #define TARGET_PRINT_OPERAND h8300_print_operand
6059 #undef TARGET_PRINT_OPERAND_ADDRESS
6060 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6061 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6062 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6064 #undef TARGET_ENCODE_SECTION_INFO
6065 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6067 #undef TARGET_INSERT_ATTRIBUTES
6068 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6070 #undef TARGET_REGISTER_MOVE_COST
6071 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6073 #undef TARGET_RTX_COSTS
6074 #define TARGET_RTX_COSTS h8300_rtx_costs
6076 #undef TARGET_INIT_LIBFUNCS
6077 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6079 #undef TARGET_FUNCTION_VALUE
6080 #define TARGET_FUNCTION_VALUE h8300_function_value
6082 #undef TARGET_LIBCALL_VALUE
6083 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6085 #undef TARGET_FUNCTION_VALUE_REGNO_P
6086 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6088 #undef TARGET_RETURN_IN_MEMORY
6089 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6091 #undef TARGET_FUNCTION_ARG
6092 #define TARGET_FUNCTION_ARG h8300_function_arg
6094 #undef TARGET_FUNCTION_ARG_ADVANCE
6095 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6097 #undef TARGET_MACHINE_DEPENDENT_REORG
6098 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6100 #undef TARGET_HARD_REGNO_SCRATCH_OK
6101 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6104 #define TARGET_LRA_P hook_bool_void_false
6106 #undef TARGET_LEGITIMATE_ADDRESS_P
6107 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6109 #undef TARGET_CAN_ELIMINATE
6110 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6112 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6113 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6115 #undef TARGET_TRAMPOLINE_INIT
6116 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6118 #undef TARGET_OPTION_OVERRIDE
6119 #define TARGET_OPTION_OVERRIDE h8300_option_override
6121 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6122 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6124 struct gcc_target targetm
= TARGET_INITIALIZER
;