| blob | 8595d0e579fb525f68bd9af4df3f565d69b93428 |
1 2020-04-21 John David Anglin <danglin@gcc.gnu.org>
3 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete.
4 (ASM_WEAKEN_DECL): New define.
5 (HAVE_GAS_WEAKREF): Undefine.
7 2020-04-21 Richard Sandiford <richard.sandiford@arm.com>
9 PR tree-optimization/94683
10 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a
11 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured
12 but distinct vector types.
14 2020-04-21 Jakub Jelinek <jakub@redhat.com>
16 PR c/94641
17 * stor-layout.c (place_field, finalize_record_size): Don't emit
18 -Wpadded warning on TYPE_ARTIFICIAL rli->t.
19 * ubsan.c (ubsan_get_type_descriptor_type,
20 ubsan_get_source_location_type, ubsan_create_data): Set
21 TYPE_ARTIFICIAL.
22 * asan.c (asan_global_struct): Likewise.
24 2020-04-21 Duan bo <duanbo3@huawei.com>
26 PR target/94577
27 * config/aarch64/aarch64.c: Add an error message for option conflict.
28 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is
29 incompatible with -fpic, -fPIC and -mabi=ilp32.
31 2020-04-21 Frederik Harwath <frederik@codesourcery.com>
33 PR other/94629
34 * omp-low.c (new_omp_context): Remove assignments to
35 ctx->outer_reduction_clauses and ctx->local_reduction_clauses.
37 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
39 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
40 ("popcountv2di2_vx"): Use simplify_gen_subreg.
42 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
44 PR target/94613
45 * config/s390/s390-builtin-types.def: Add 3 new function modes.
46 * config/s390/s390-builtins.def: Add mode dependent low-level
47 builtin and map the overloaded builtins to these.
48 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
49 ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
51 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
53 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo
54 has a variable VF, prefer new_loop_vinfo if it is cheaper for the
55 estimated VF and is no worse at double the estimated VF.
57 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
59 PR target/94668
60 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix
61 order of arguments to rtx_vector_builder.
62 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise.
63 When extending the trailing constants to a full vector, replace any
64 variables with zeros.
66 2020-04-20 Jan Hubicka <hubicka@ucw.cz>
68 PR ipa/94582
69 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local
70 flag.
72 2020-04-20 Martin Liska <mliska@suse.cz>
74 * symtab.c (symtab_node::dump_references): Add space after
75 one entry.
76 (symtab_node::dump_referring): Likewise.
78 2020-04-18 Jeff Law <law@redhat.com>
80 PR debug/94439
81 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking
82 the chain.
84 2020-04-18 Iain Buclaw <ibuclaw@gdcproject.org>
86 * doc/sourcebuild.texi (Effective-Target Keywords, Environment
87 attributes): Document d_runtime_has_std_library.
89 2020-04-17 Jeff Law <law@redhat.com>
91 PR rtl-optimization/90275
92 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels
93 when the destination has a REG_UNUSED note.
95 2020-04-17 Tobias Burnus <tobias@codesourcery.com>
97 PR middle-end/94635
98 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to
99 MAP_DELETE.
101 2020-04-17 Richard Sandiford <richard.sandiford@arm.com>
103 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function.
104 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the
105 cost of load and store insns if one loop iteration has enough scalar
106 elements to use an Advanced SIMD LDP or STP.
107 (aarch64_add_stmt_cost): Update call accordingly.
109 2020-04-17 Jakub Jelinek <jakub@redhat.com>
110 Jeff Law <law@redhat.com>
112 PR target/94567
113 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than
114 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision,
115 or pos + len >= 32, or pos + len is equal to operands[2] precision
116 and operands[2] is not a register operand. During splitting perform
117 SImode AND if operands[0] doesn't have CCZmode and pos + len is
118 equal to mode precision.
120 2020-04-17 Richard Biener <rguenther@suse.de>
122 PR other/94629
123 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate
124 initialization.
125 * dwarf2out.c (dw_val_equal_p): Fix pasto in
126 dw_val_class_vms_delta comparison.
127 * optabs.c (expand_binop_directly): Fix pasto in commutation
128 check.
129 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in
130 initialization.
132 2020-04-17 Jakub Jelinek <jakub@redhat.com>
134 PR rtl-optimization/94618
135 * cfgrtl.c (delete_insn_and_edges): Set purge not just when
136 insn is the BB_END of its block, but also when it is only followed
137 by DEBUG_INSNs in its block.
139 PR tree-optimization/94621
140 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN.
141 Move id->adjust_array_error_bounds check first in the condition.
143 2020-04-17 Martin Liska <mliska@suse.cz>
144 Jonathan Yong <10walls@gmail.com>
146 PR gcov-profile/94570
147 * coverage.c (coverage_init): Use separator properly.
149 2020-04-16 Peter Bergner <bergner@linux.ibm.com>
151 PR rtl-optimization/93974
152 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
153 (rs6000_cannot_substitute_mem_equiv_p): New function.
155 2020-04-16 Martin Jambor <mjambor@suse.cz>
157 PR ipa/93621
158 * ipa-inline.h (ipa_saved_clone_sources): Declare.
159 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable.
160 (save_inline_function_body): Link the new body holder with the
161 previous one.
162 * cgraph.c: Include ipa-inline.h.
163 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from
164 the statement in ipa_saved_clone_sources.
165 * cgraphunit.c: Include ipa-inline.h.
166 (expand_all_functions): Free ipa_saved_clone_sources.
168 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
170 PR target/94606
171 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
172 the VNx16BI lowpart of the recursively-generated constant.
174 2020-04-16 Martin Liska <mliska@suse.cz>
175 Jakub Jelinek <jakub@redhat.com>
177 PR c++/94314
178 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
179 DECL_IS_REPLACEABLE_OPERATOR during cloning.
180 * tree-ssa-dce.c (valid_new_delete_pair_p): New function.
181 (propagate_necessity): Check operator names.
183 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
185 PR rtl-optimization/94605
186 * early-remat.c (early_remat::process_block): Handle insns that
187 set multiple candidate registers.
188 2020-04-16 Jan Hubicka <hubicka@ucw.cz>
190 PR gcov-profile/93401
191 * common.opt (profile-prefix-path): New option.
192 * coverae.c: Include diagnostics.h.
193 (coverage_init): Strip profile prefix path.
194 * doc/invoke.texi (-fprofile-prefix-path): Document.
196 2020-04-16 Richard Biener <rguenther@suse.de>
198 PR middle-end/94614
199 * expr.c (emit_move_multi_word): Do not generate code when
200 the destination part is undefined_operand_subword_p.
201 * lower-subreg.c (resolve_clobber): Look through a paradoxica
202 subreg.
204 2020-04-16 Martin Jambor <mjambor@suse.cz>
206 PR tree-optimization/94598
207 * tree-sra.c (verify_sra_access_forest): Fix verification of total
208 scalarization accesses under access to one-element arrays.
210 2020-04-16 Jakub Jelinek <jakub@redhat.com>
212 PR bootstrap/89494
213 * function.c (assign_parm_find_data_types): Add workaround for
214 BROKEN_VALUE_INITIALIZATION compilers.
216 2020-04-16 Richard Biener <rguenther@suse.de>
218 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME
219 nodes.
221 2020-04-15 Uroš Bizjak <ubizjak@gmail.com>
223 PR target/94603
224 * config/i386/i386-builtin.def (__builtin_ia32_movq128):
225 Require OPTION_MASK_ISA_SSE2.
227 2020-04-15 Gustavo Romero <gromero@linux.ibm.com>
229 PR bootstrap/89494
230 * dumpfile.c (selftest::temp_dump_context::temp_dump_context):
231 Don't construct a dump_context temporary to call static method.
233 2020-04-15 Andrea Corallo <andrea.corallo@arm.com>
235 * config/aarch64/falkor-tag-collision-avoidance.c
236 (valid_src_p): Check for aarch64_address_info type before
237 accessing base field.
239 2020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
241 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern.
242 (V_sz_elem2): Remove unused mode attribute.
244 2020-04-15 Matthew Malcomson <matthew.malcomson@arm.com>
246 * config/arm/arm.md (arm_movdi): Disallow for MVE.
248 2020-04-15 Richard Biener <rguenther@suse.de>
250 PR middle-end/94539
251 * tree-ssa-alias.c (same_type_for_tbaa): Defer to
252 alias_sets_conflict_p for pointers.
254 2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
256 PR target/94584
257 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
258 (extendhisi2_internal): Add %v1 before the load instructions.
260 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
262 PR target/94542
263 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to
264 use PC-relative addressing for TLS references.
266 2020-04-14 Martin Jambor <mjambor@suse.cz>
268 PR ipa/94434
269 * ipa-sra.c: Include internal-fn.h.
270 (enum isra_scan_context): Update comment.
271 (scan_function): Treat calls to internal_functions like loads or stores.
273 2020-04-14 Yang Yang <yangyang305@huawei.com>
275 PR tree-optimization/94574
276 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
277 whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
279 2020-04-14 H.J. Lu <hongjiu.lu@intel.com>
281 PR target/94561
282 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
284 2020-04-13 Martin Sebor <msebor@redhat.com>
286 * doc/extend.texi (-Wall): Mention -Wformat-overflow and
287 -Wformat-truncation. Move -Wzero-length-bounds last.
288 (-Wrestrict): Document positive form of option enabled by -Wall.
290 2020-04-13 Zachary Spytz <zspytz@gmail.com>
292 * doc/extend.texi: Add realloc to list of built-in functions
293 are recognized by the compiler.
295 2020-04-13 H.J. Lu <hongjiu.lu@intel.com>
297 PR target/94556
298 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
299 pointer in word_mode for eh_return epilogues.
301 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
303 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to
304 memory references in %B, %C and %D operand selectors when the inner
305 operand is a post increment address.
307 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
309 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory
310 reference by 4 bytes, and %D memory reference by 6 bytes.
312 2020-04-11 Uroš Bizjak <ubizjak@gmail.com>
314 PR target/94494
315 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2
316 condition for V4SI, V8HI and V16QI modes.
318 2020-04-11 Jakub Jelinek <jakub@redhat.com>
320 PR debug/94495
321 PR target/94551
322 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on
323 val->val_rtx.
325 2020-04-10 Thomas Schwinge <thomas@codesourcery.com>
327 PR middle-end/89433
328 PR middle-end/93465
329 * omp-general.c (oacc_verify_routine_clauses): Diagnose if
330 "#pragma omp declare target" has also been applied.
332 2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
334 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
335 when to emit the epilogue_helper insn.
336 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the
337 RTL pattern.
339 2020-04-09 Jakub Jelinek <jakub@redhat.com>
341 PR debug/94495
342 * cselib.h (cselib_record_sp_cfa_base_equiv,
343 cselib_sp_derived_value_p): Declare.
344 * cselib.c (cselib_record_sp_cfa_base_equiv,
345 cselib_sp_derived_value_p): New functions.
346 * var-tracking.c (add_stores): Don't record MO_VAL_SET for
347 cselib_sp_derived_value_p values.
348 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
349 start of extended basic blocks other than the first one
350 for !frame_pointer_needed functions.
352 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
354 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
355 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
356 (aarch64_sve2048_hw): Document.
357 * config/aarch64/aarch64-protos.h
358 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
359 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
360 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
361 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
362 function.
363 (find_type_suffix_for_scalar_type): Use it instead of comparing
364 TYPE_MAIN_VARIANTs.
365 (function_resolver::infer_vector_or_tuple_type): Likewise.
366 (function_resolver::require_vector_type): Likewise.
367 (handle_arm_sve_vector_bits_attribute): New function.
368 * config/aarch64/aarch64.c (pure_scalable_type_info): New class.
369 (aarch64_attribute_table): Add arm_sve_vector_bits.
370 (aarch64_return_in_memory_1):
371 (pure_scalable_type_info::piece::get_rtx): New function.
372 (pure_scalable_type_info::num_zr): Likewise.
373 (pure_scalable_type_info::num_pr): Likewise.
374 (pure_scalable_type_info::get_rtx): Likewise.
375 (pure_scalable_type_info::analyze): Likewise.
376 (pure_scalable_type_info::analyze_registers): Likewise.
377 (pure_scalable_type_info::analyze_array): Likewise.
378 (pure_scalable_type_info::analyze_record): Likewise.
379 (pure_scalable_type_info::add_piece): Likewise.
380 (aarch64_some_values_include_pst_objects_p): Likewise.
381 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
382 to analyze whether the type is returned in SVE registers.
383 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
384 is passed in SVE registers.
385 (aarch64_pass_by_reference_1): New function, extracted from...
386 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
387 to analyze whether the type is a pure scalable type and, if so,
388 whether it should be passed by reference.
389 (aarch64_return_in_msb): Return false for pure scalable types.
390 (aarch64_function_value_1): Fold back into...
391 (aarch64_function_value): ...this function. Use
392 pure_scalable_type_info to analyze whether the type is a pure
393 scalable type and, if so, which registers it should use. Handle
394 types that include pure scalable types but are not themselves
395 pure scalable types.
396 (aarch64_return_in_memory_1): New function, split out from...
397 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info
398 to analyze whether the type is a pure scalable type and, if so,
399 whether it should be returned by reference.
400 (aarch64_layout_arg): Remove orig_mode argument. Use
401 pure_scalable_type_info to analyze whether the type is a pure
402 scalable type and, if so, which registers it should use. Handle
403 types that include pure scalable types but are not themselves
404 pure scalable types.
405 (aarch64_function_arg): Update call accordingly.
406 (aarch64_function_arg_advance): Likewise.
407 (aarch64_pad_reg_upward): On big-endian targets, return false for
408 pure scalable types that are smaller than 16 bytes.
409 (aarch64_member_type_forces_blk): New function.
410 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
411 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that
412 correspond to built-in SVE types. Do not rely on a vector mode
413 if the type includes an pure scalable type. When returning true,
414 assert that the mode is not an SVE mode.
415 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
416 built-in types here. When returning true, assert that the type
417 does not have an SVE mode.
418 (aarch64_can_change_mode_class): Don't allow anything to change
419 between a predicate mode and a non-predicate mode. Also don't
420 allow changes between SVE vector modes and other modes that
421 might be bigger than 128 bits.
422 (aarch64_invalid_binary_op): Reject binary operations that mix
423 SVE and GNU vector types.
424 (TARGET_MEMBER_TYPE_FORCES_BLK): Define.
426 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
428 * config/aarch64/aarch64.c (aarch64_attribute_table): Add
429 "SVE sizeless type".
430 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
431 (sizeless_type_p): New functions.
432 (register_builtin_types): Apply make_type_sizeless to the type.
433 (register_tuple_type): Likewise.
434 (verify_type_context): Use sizeless_type_p instead of builin_type_p.
436 2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
438 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for
439 C++.
441 2020-04-09 Martin Jambor <mjambor@suse.cz>
442 Richard Biener <rguenther@suse.de>
444 PR tree-optimization/94482
445 * tree-sra.c (create_access_replacement): Dump new replacement with
446 TDF_UID.
447 (sra_modify_expr): Fix handling of cases when the original EXPR writes
448 to only part of the replacement.
449 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
450 the first operand of combinations into REAL/IMAGPART_EXPR and
451 BIT_FIELD_REF.
453 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
455 * doc/sourcebuild.texi (check-function-bodies): Treat the third
456 parameter as a list of option regexps and require each regexp
457 to match.
459 2020-04-09 Andrea Corallo <andrea.corallo@arm.com>
461 PR target/94530
462 * config/aarch64/falkor-tag-collision-avoidance.c
463 (valid_src_p): Fix missing rtx type check.
465 2020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com>
466 Richard Biener <rguenther@suse.de>
468 PR tree-optimization/93674
469 * tree-ssa-loop-ivopts.c (langhooks.h): New include.
470 (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
471 or non-mode precision type, add candidate in unsigned type with the
472 same precision.
474 2020-04-08 Clement Chigot <clement.chigot@atos.net>
476 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128.
477 * config/rs6000/aix71.h (LIB_SPEC): Likewise.
478 * config/rs6000/aix72.h (LIB_SPEC): Likewise.
480 2020-04-08 Jakub Jelinek <jakub@redhat.com>
482 PR middle-end/94526
483 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
484 with zero offset.
485 * reload1.c (eliminate_regs_1): Avoid creating
486 (plus (reg) (const_int 0)) in DEBUG_INSNs.
488 PR tree-optimization/94524
489 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
490 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
491 op1 rather than op1 itself at the end. Punt for signed modulo by
492 most negative constant.
493 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
494 modulo by most negative constant.
496 2020-04-08 Richard Biener <rguenther@suse.de>
498 PR rtl-optimization/93946
499 * cse.c (cse_insn): Record the tabled expression in
500 src_related. Verify a redundant store removal is valid.
502 2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
504 PR target/94417
505 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert
506 ENDBR at function entry if function will be called indirectly.
508 2020-04-08 Jakub Jelinek <jakub@redhat.com>
510 PR target/94438
511 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
512 1, 2, 4 and 8.
514 2020-04-08 Martin Liska <mliska@suse.cz>
516 PR c++/94314
517 * gimple.c (gimple_call_operator_delete_p): Rename to...
518 (gimple_call_replaceable_operator_delete_p): ... this.
519 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
520 * gimple.h (gimple_call_operator_delete_p): Rename to ...
521 (gimple_call_replaceable_operator_delete_p): ... this.
522 * tree-core.h (tree_function_decl): Add replaceable_operator
523 flag.
524 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
525 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
526 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
527 (eliminate_unnecessary_stmts): Likewise.
528 * tree-streamer-in.c (unpack_ts_function_decl_value_fields):
529 Pack DECL_IS_REPLACEABLE_OPERATOR.
530 * tree-streamer-out.c (pack_ts_function_decl_value_fields):
531 Unpack the field here.
532 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
533 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
534 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
535 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
536 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
537 replaceable operator flags.
539 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
540 Matthew Malcomson <matthew.malcomson@arm.com>
542 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
543 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
544 (CX_TERNARY_QUALIFIERS): Likewise.
545 (ARM_BUILTIN_CDE_PATTERN_START): Likewise.
546 (ARM_BUILTIN_CDE_PATTERN_END): Likewise.
547 (arm_init_acle_builtins): Initialize CDE builtins.
548 (arm_expand_acle_builtin): Check CDE constant operands.
549 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
550 of CDE constant operand.
551 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
552 TARGET_VFP_BASE.
553 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
554 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
555 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
556 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
557 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
558 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
559 * config/arm/arm_cde_builtins.def: New file.
560 * config/arm/iterators.md (V_reg): New attribute of SI.
561 * config/arm/predicates.md (const_int_coproc_operand): New.
562 (const_int_vcde1_operand, const_int_vcde2_operand): New.
563 (const_int_vcde3_operand): New.
564 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
565 * config/arm/vfp.md (arm_vcx1<mode>): New entry.
566 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
567 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
569 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
571 * config.gcc: Add arm_cde.h.
572 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
573 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
574 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
575 * config/arm/arm.c (arm_option_reconfigure_globals): Configure
576 arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
577 * config/arm/arm.h (TARGET_CDE): New macro.
578 * config/arm/arm_cde.h: New file.
579 * doc/invoke.texi: Document CDE options +cdecp[0-7].
580 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
581 supports option.
582 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
584 2020-04-08 Jakub Jelinek <jakub@redhat.com>
586 PR rtl-optimization/94516
587 * postreload.c: Include rtl-iter.h.
588 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
589 looking for all MEMs with RTX_AUTOINC operand.
590 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
592 2020-04-08 Tobias Burnus <tobias@codesourcery.com>
594 * omp-grid.c (grid_eliminate_combined_simd_part): Use
595 OMP_CLAUSE_CODE to access the omp clause code.
597 2020-04-07 Jeff Law <law@redhat.com>
599 PR rtl-optimization/92264
600 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when
601 the destination is the stack pointer.
603 2020-04-07 Jakub Jelinek <jakub@redhat.com>
605 PR rtl-optimization/94291
606 PR rtl-optimization/84169
607 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST
608 must be a REG or SUBREG of REG; if it is not one of these, don't
609 update LOG_LINKs.
611 2020-04-07 Richard Biener <rguenther@suse.de>
613 PR middle-end/94479
614 * gimplify.c (gimplify_addr_expr): Also consider generated
615 MEM_REFs.
617 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
619 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
621 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
623 * config/arm/arm_mve.h: Cast some pointers to expected types.
625 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
627 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
628 same with '__arm_' prefix.
630 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
632 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
634 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
636 * config/arm/arm.c (arm_mve_immediate_check): Removed.
637 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
638 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
639 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
640 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
641 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
642 mve_vqshruntq_m_n_s*): Fixed immediate constraints.
644 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
646 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
648 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
650 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
651 * config/arm/mve/md: Fix v[id]wdup patterns.
653 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
655 * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
656 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
658 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
660 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
661 and remove const_ptr enums.
663 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
665 * config/arm/arm_mve.h (vsubq_n): Merge with...
666 (vsubq): ... this.
667 (vmulq_n): Merge with...
668 (vmulq): ... this.
669 (__ARM_mve_typeid): Simplify scalar and constant detection.
671 2020-04-07 Jakub Jelinek <jakub@redhat.com>
673 PR target/94509
674 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
675 for inter-lane permutation for 64-byte modes.
677 PR target/94488
678 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
679 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
680 Assume it is a REG after that instead of testing it and doing FAIL
681 otherwise. Formatting fix.
683 2020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
685 * config/rs6000/t-rtems: Delete mcpu=8540 multilib.
687 2020-04-07 Jakub Jelinek <jakub@redhat.com>
689 PR target/94500
690 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
691 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
693 2020-04-06 Jakub Jelinek <jakub@redhat.com>
695 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
696 + const0_rtx return the SP_DERIVED_VALUE_P.
698 2020-04-06 Richard Sandiford <richard.sandiford@arm.com>
700 PR rtl-optimization/92989
701 * lra-lives.c (process_bb_lives): Do not treat eh_return data
702 registers as being live at the beginning of the EH receiver.
704 2020-04-05 Zachary Spytz <zspytz@gmail.com>
706 * extend.texi: Add free to list of ISO C90 functions that
707 are recognized by the compiler.
709 2020-04-05 Nagaraju Mekala <nmekala@xilix.com>
711 * config/microblaze/microblaze.c (microblaze_must_save_register): Check
712 for fast_interrupt.
714 * config/microblaze/microblaze.md (trap): Update output pattern.
716 2020-04-04 Hannes Domani <ssbssa@yahoo.de>
717 Jakub Jelinek <jakub@redhat.com>
719 PR debug/94459
720 * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
721 arrays, pointer-to-members, function types and qualifiers when
722 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
723 to emit type again on definition.
725 2020-04-04 Jan Hubicka <hubicka@ucw.cz>
727 PR ipa/93940
728 * ipa-fnsummary.c (vrp_will_run_p): New function.
729 (fre_will_run_p): New function.
730 (evaluate_properties_for_edge): Use it.
731 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
732 !optimize_debug to optimize_debug.
734 2020-04-04 Jakub Jelinek <jakub@redhat.com>
736 PR rtl-optimization/94468
737 * cselib.c (references_value_p): Formatting fix.
738 (cselib_useless_value_p): New function.
739 (discard_useless_locs, discard_useless_values,
740 cselib_invalidate_regno_val, cselib_invalidate_mem,
741 cselib_record_set): Use it instead of
742 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).
744 PR debug/94441
745 * tree-iterator.h (expr_single): Declare.
746 * tree-iterator.c (expr_single): New function.
747 * tree.h (protected_set_expr_location_if_unset): Declare.
748 * tree.c (protected_set_expr_location): Use expr_single.
749 (protected_set_expr_location_if_unset): New function.
751 2020-04-03 Jeff Law <law@redhat.com>
753 PR rtl-optimization/92264
754 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
755 reloading of auto-increment addressing modes.
757 2020-04-03 H.J. Lu <hongjiu.lu@intel.com>
759 PR target/94467
760 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
761 as earlyclobber.
763 2020-04-03 Jeff Law <law@redhat.com>
765 PR rtl-optimization/92264
766 * config/m32r/m32r.c (m32r_output_block_move): Properly account for
767 post-increment addressing of source operands as well as residuals
768 when computing any adjustments to the input pointer.
770 2020-04-03 Jakub Jelinek <jakub@redhat.com>
772 PR target/94460
773 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
774 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
775 second half of first lane from first lane of second operand and
776 first half of second lane from second lane of first operand.
778 2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
780 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.
782 2020-04-03 Tamar Christina <tamar.christina@arm.com>
784 PR target/94396
785 * common/config/aarch64/aarch64-common.c
786 (aarch64_get_extension_string_for_isa_flags): Handle default flags.
788 2020-04-03 Richard Biener <rguenther@suse.de>
790 PR middle-end/94465
791 * tree.c (array_ref_low_bound): Deal with released SSA names
792 in index position.
794 2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>
796 * config/gcn/gcn.c (print_operand): Handle unordered comparison
797 operators.
798 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
799 comparison operators.
801 2020-04-03 Kewen Lin <linkw@gcc.gnu.org>
803 PR tree-optimization/94443
804 * tree-vect-loop.c (vectorizable_live_operation): Use
805 gsi_insert_seq_before to replace gsi_insert_before.
807 2020-04-03 Martin Liska <mliska@suse.cz>
809 PR ipa/94445
810 * ipa-icf-gimple.c (func_checker::compare_gimple_call):
811 Compare type attributes for gimple_call_fntypes.
813 2020-04-02 Sandra Loosemore <sandra@codesourcery.com>
815 * alias.c (get_alias_set): Fix comment typos.
817 2020-04-02 Fritz Reese <foreese@gcc.gnu.org>
819 PR fortran/85982
820 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
821 attribute checking used by TYPE.
823 2020-04-02 Martin Jambor <mjambor@suse.cz>
825 PR ipa/92676
826 * ipa-sra.c (struct caller_issues): New fields candidate and
827 call_from_outside_comdat.
828 (check_for_caller_issues): Check for calls from outsied of
829 candidate's same_comdat_group.
830 (check_all_callers_for_issues): Set up issues.candidate, check result
831 of the new check.
832 (mark_callers_calls_comdat_local): New function.
833 (process_isra_node_results): Set calls_comdat_local of callers if
834 appropriate.
836 2020-04-02 Richard Biener <rguenther@suse.de>
838 PR c/94392
839 * common.opt (ffinite-loops): Initialize to zero.
840 * opts.c (default_options_table): Remove OPT_ffinite_loops
841 entry.
842 * cfgloop.h (loop::finite_p): New member.
843 * cfgloopmanip.c (copy_loop_info): Copy finite_p.
844 * ipa-icf-gimple.c (func_checker::compare_loops): Compare
845 finite_p.
846 * lto-streamer-in.c (input_cfg): Stream finite_p.
847 * lto-streamer-out.c (output_cfg): Likewise.
848 * tree-cfg.c (replace_loop_annotate): Initialize finite_p
849 from flag_finite_loops at CFG build time.
850 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops
851 finite_p flag instead of flag_finite_loops.
852 * doc/invoke.texi (ffinite-loops): Adjust documentation of
853 default setting.
855 2020-04-02 Richard Biener <rguenther@suse.de>
857 PR debug/94450
858 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting
859 DW_TAG_imported_unit.
861 2020-04-02 Maciej W. Rozycki <macro@wdc.com>
863 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
864 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
865 2.30.
867 2020-04-02 Kewen Lin <linkw@gcc.gnu.org>
869 PR tree-optimization/94401
870 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
871 access type when loading halves of vector to avoid peeling for gaps.
873 2020-04-02 Jakub Jelinek <jakub@redhat.com>
875 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
876 between a string literal and MIPS_SYSVERSION_SPEC macro.
878 2020-04-02 Martin Jambor <mjambor@suse.cz>
880 * doc/invoke.texi (Optimize Options): Document sra-max-propagations.
882 2020-04-02 Jakub Jelinek <jakub@redhat.com>
884 PR rtl-optimization/92264
885 * params.opt (-param=max-find-base-term-values=): Decrease default
886 from 2000 to 200.
888 PR rtl-optimization/92264
889 * rtl.h (struct rtx_def): Mention that call bit is used as
890 SP_DERIVED_VALUE_P in cselib.c.
891 * cselib.c (SP_DERIVED_VALUE_P): Define.
892 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
893 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
894 val_rtx and sp based expression where offsets cancel each other.
895 (preserve_constants_and_equivs): Formatting fix.
896 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
897 locs list for cfa_base_preserved_val if needed. Formatting fix.
898 (autoinc_split): If the to be returned value is a REG, MEM or
899 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
900 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
901 (rtx_equal_for_cselib_1): Call autoinc_split even if both
902 expressions are PLUS in Pmode with CONST_INT second operands.
903 Handle SP_DERIVED_VALUE_P cases.
904 (cselib_hash_plus_const_int): New function.
905 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
906 second operand, as well as for PRE_DEC etc. that ought to be
907 hashed the same way.
908 (cselib_subst_to_values): Substitute PLUS with Pmode and
909 CONST_INT operand if the first operand is a VALUE which has
910 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
911 SP_DERIVED_VALUE_P + adjusted offset.
912 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
913 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding
914 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
915 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
916 on the sp value before calling cselib_add_permanent_equiv on the
917 cfa_base value.
918 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
919 in the insn without REG_INC note.
920 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
921 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes.
923 PR target/94435
924 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
925 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
927 2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
929 PR target/94317
930 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
931 (LDRGBWBXU_Z_QUALIFIERS): Likewise.
932 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
933 intrinsic defintion by adding a new builtin call to writeback into base
934 address.
935 (__arm_vldrdq_gather_base_wb_u64): Likewise.
936 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
937 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
938 (__arm_vldrwq_gather_base_wb_s32): Likewise.
939 (__arm_vldrwq_gather_base_wb_u32): Likewise.
940 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
941 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
942 (__arm_vldrwq_gather_base_wb_f32): Likewise.
943 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
944 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
945 builtin's qualifier.
946 (vldrdq_gather_base_wb_z_u): Likewise.
947 (vldrwq_gather_base_wb_u): Likewise.
948 (vldrdq_gather_base_wb_u): Likewise.
949 (vldrwq_gather_base_wb_z_s): Likewise.
950 (vldrwq_gather_base_wb_z_f): Likewise.
951 (vldrdq_gather_base_wb_z_s): Likewise.
952 (vldrwq_gather_base_wb_s): Likewise.
953 (vldrwq_gather_base_wb_f): Likewise.
954 (vldrdq_gather_base_wb_s): Likewise.
955 (vldrwq_gather_base_nowb_z_u): Define builtin.
956 (vldrdq_gather_base_nowb_z_u): Likewise.
957 (vldrwq_gather_base_nowb_u): Likewise.
958 (vldrdq_gather_base_nowb_u): Likewise.
959 (vldrwq_gather_base_nowb_z_s): Likewise.
960 (vldrwq_gather_base_nowb_z_f): Likewise.
961 (vldrdq_gather_base_nowb_z_s): Likewise.
962 (vldrwq_gather_base_nowb_s): Likewise.
963 (vldrwq_gather_base_nowb_f): Likewise.
964 (vldrdq_gather_base_nowb_s): Likewise.
965 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
966 pattern.
967 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
968 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
969 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
970 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
971 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
972 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
973 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
974 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
975 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
976 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
977 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
979 2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
981 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
982 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
983 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
984 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
985 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
986 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
987 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
988 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
989 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
990 modifier.
991 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
992 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
993 Remove constraints from expander.
994 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
995 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
996 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
997 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
998 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
999 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
1001 2020-04-01 Peter Bergner <bergner@linux.ibm.com>
1003 PR rtl-optimization/94123
1004 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for
1005 flag_split_wide_types_early.
1007 2020-04-01 Joerg Sonnenberger <joerg@bec.de>
1009 * doc/extend.texi (Common Function Attributes): Fix typo.
1011 2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
1013 PR target/94420
1014 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
1015 on operands[1].
1017 2020-04-01 Zackery Spytz <zspytz@gmail.com>
1019 * doc/extend.texi: Fix a typo in the documentation of the
1020 copy function attribute.
1022 2020-04-01 Jakub Jelinek <jakub@redhat.com>
1024 PR middle-end/94423
1025 * tree-object-size.c (pass_object_sizes::execute): Don't call
1026 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
1027 call replace_call_with_value.
1029 2020-04-01 Kewen Lin <linkw@gcc.gnu.org>
1031 PR tree-optimization/94043
1032 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
1033 phi for vec_lhs and use it for lane extraction.
1035 2020-03-31 Felix Yang <felix.yang@huawei.com>
1037 PR tree-optimization/94398
1038 * tree-vect-stmts.c (vectorizable_store): Instead of calling
1039 vect_supportable_dr_alignment, set alignment_support_scheme to
1040 dr_unaligned_supported for gather-scatter accesses.
1041 (vectorizable_load): Likewise.
1043 2020-03-31 Andrew Stubbs <ams@codesourcery.com>
1045 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
1046 New mode iterators.
1047 (vnsi, VnSI, vndi, VnDI): New mode attributes.
1048 (mov<mode>): Use <VnDI> in place of V64DI.
1049 (mov<mode>_exec): Likewise.
1050 (mov<mode>_sgprbase): Likewise.
1051 (reload_out<mode>): Likewise.
1052 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
1053 (gather_load<mode>v64si): Rename to ...
1054 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
1055 and <VnDI> in place of V64DI.
1056 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
1057 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
1058 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
1059 (scatter_store<mode>v64si): Rename to ...
1060 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
1061 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
1062 (scatter<mode>_insn_1offset<exec_scatter>): Likewise.
1063 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
1064 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
1065 (ds_bpermute<mode>): Use <VnSI>.
1066 (addv64si3_vcc<exec_vcc>): Rename to ...
1067 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
1068 (addv64si3_vcc_dup<exec_vcc>): Rename to ...
1069 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
1070 (addcv64si3<exec_vcc>): Rename to ...
1071 (addc<mode>3<exec_vcc>): ... this, and use V_SI.
1072 (subv64si3_vcc<exec_vcc>): Rename to ...
1073 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
1074 (subcv64si3<exec_vcc>): Rename to ...
1075 (subc<mode>3<exec_vcc>): ... this, and use V_SI.
1076 (addv64di3): Rename to ...
1077 (add<mode>3): ... this, and use V_DI.
1078 (addv64di3_exec): Rename to ...
1079 (add<mode>3_exec): ... this, and use V_DI.
1080 (subv64di3): Rename to ...
1081 (sub<mode>3): ... this, and use V_DI.
1082 (subv64di3_exec): Rename to ...
1083 (sub<mode>3_exec): ... this, and use V_DI.
1084 (addv64di3_zext): Rename to ...
1085 (add<mode>3_zext): ... this, and use V_DI and <VnSI>.
1086 (addv64di3_zext_exec): Rename to ...
1087 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
1088 (addv64di3_zext_dup): Rename to ...
1089 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
1090 (addv64di3_zext_dup_exec): Rename to ...
1091 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
1092 (addv64di3_zext_dup2): Rename to ...
1093 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
1094 (addv64di3_zext_dup2_exec): Rename to ...
1095 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
1096 (addv64di3_sext_dup2): Rename to ...
1097 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
1098 (addv64di3_sext_dup2_exec): Rename to ...
1099 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
1100 (<su>mulv64si3_highpart<exec>): Rename to ...
1101 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
1102 (mulv64di3): Rename to ...
1103 (mul<mode>3): ... this, and use V_DI and <VnSI>.
1104 (mulv64di3_exec): Rename to ...
1105 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
1106 (mulv64di3_zext): Rename to ...
1107 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
1108 (mulv64di3_zext_exec): Rename to ...
1109 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
1110 (mulv64di3_zext_dup2): Rename to ...
1111 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
1112 (mulv64di3_zext_dup2_exec): Rename to ...
1113 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
1114 (<expander>v64di3): Rename to ...
1115 (<expander><mode>3): ... this, and use V_DI and <VnSI>.
1116 (<expander>v64di3_exec): Rename to ...
1117 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
1118 (<expander>v64si3<exec>): Rename to ...
1119 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
1120 (v<expander>v64si3<exec>): Rename to ...
1121 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
1122 (<expander>v64si3<exec>): Rename to ...
1123 (<expander><vnsi>3<exec>): ... this, and use V_SI.
1124 (subv64df3<exec>): Rename to ...
1125 (sub<mode>3<exec>): ... this, and use V_DF.
1126 (truncv64di<mode>2): Rename to ...
1127 (trunc<vndi><mode>2): ... this, and use <VnDI>.
1128 (truncv64di<mode>2_exec): Rename to ...
1129 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
1130 (<convop><mode>v64di2): Rename to ...
1131 (<convop><mode><vndi>2): ... this, and use <VnDI>.
1132 (<convop><mode>v64di2_exec): Rename to ...
1133 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
1134 (vec_cmp<u>v64qidi): Rename to ...
1135 (vec_cmp<u><mode>di): ... this, and use <VnSI>.
1136 (vec_cmp<u>v64qidi_exec): Rename to ...
1137 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
1138 (vcond_mask_<mode>di): Use <VnDI>.
1139 (maskload<mode>di): Likewise.
1140 (maskstore<mode>di): Likewise.
1141 (mask_gather_load<mode>v64si): Rename to ...
1142 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
1143 (mask_scatter_store<mode>v64si): Rename to ...
1144 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
1145 (*<reduc_op>_dpp_shr_v64di): Rename to ...
1146 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
1147 (*plus_carry_in_dpp_shr_v64si): Rename to ...
1148 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
1149 (*plus_carry_dpp_shr_v64di): Rename to ...
1150 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
1151 (vec_seriesv64si): Rename to ...
1152 (vec_series<mode>): ... this, and use V_SI.
1153 (vec_seriesv64di): Rename to ...
1154 (vec_series<mode>): ... this, and use V_DI.
1156 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
1158 * config/arc/arc.c (arc_print_operand): Use
1159 HOST_WIDE_INT_PRINT_DEC macro.
1161 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
1163 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
1165 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1167 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
1168 variant.
1169 (__arm_vbicq): Likewise.
1171 2020-03-31 Vineet Gupta <vgupta@synopsys.com>
1173 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
1175 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1177 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
1178 common section of both MVE Integer and MVE Floating Point.
1179 (vaddvq): Likewise.
1180 (vaddlvq_p): Likewise.
1181 (vaddvaq): Likewise.
1182 (vaddvq_p): Likewise.
1183 (vcmpcsq): Likewise.
1184 (vmlsdavxq): Likewise.
1185 (vmlsdavq): Likewise.
1186 (vmladavxq): Likewise.
1187 (vmladavq): Likewise.
1188 (vminvq): Likewise.
1189 (vminavq): Likewise.
1190 (vmaxvq): Likewise.
1191 (vmaxavq): Likewise.
1192 (vmlaldavq): Likewise.
1193 (vcmphiq): Likewise.
1194 (vaddlvaq): Likewise.
1195 (vrmlaldavhq): Likewise.
1196 (vrmlaldavhxq): Likewise.
1197 (vrmlsldavhq): Likewise.
1198 (vrmlsldavhxq): Likewise.
1199 (vmlsldavxq): Likewise.
1200 (vmlsldavq): Likewise.
1201 (vabavq): Likewise.
1202 (vrmlaldavhaq): Likewise.
1203 (vcmpgeq_m_n): Likewise.
1204 (vmlsdavxq_p): Likewise.
1205 (vmlsdavq_p): Likewise.
1206 (vmlsdavaxq): Likewise.
1207 (vmlsdavaq): Likewise.
1208 (vaddvaq_p): Likewise.
1209 (vcmpcsq_m_n): Likewise.
1210 (vcmpcsq_m): Likewise.
1211 (vmladavxq_p): Likewise.
1212 (vmladavq_p): Likewise.
1213 (vmladavaxq): Likewise.
1214 (vmladavaq): Likewise.
1215 (vminvq_p): Likewise.
1216 (vminavq_p): Likewise.
1217 (vmaxvq_p): Likewise.
1218 (vmaxavq_p): Likewise.
1219 (vcmphiq_m): Likewise.
1220 (vaddlvaq_p): Likewise.
1221 (vmlaldavaq): Likewise.
1222 (vmlaldavaxq): Likewise.
1223 (vmlaldavq_p): Likewise.
1224 (vmlaldavxq_p): Likewise.
1225 (vmlsldavaq): Likewise.
1226 (vmlsldavaxq): Likewise.
1227 (vmlsldavq_p): Likewise.
1228 (vmlsldavxq_p): Likewise.
1229 (vrmlaldavhaxq): Likewise.
1230 (vrmlaldavhq_p): Likewise.
1231 (vrmlaldavhxq_p): Likewise.
1232 (vrmlsldavhaq): Likewise.
1233 (vrmlsldavhaxq): Likewise.
1234 (vrmlsldavhq_p): Likewise.
1235 (vrmlsldavhxq_p): Likewise.
1236 (vabavq_p): Likewise.
1237 (vmladavaq_p): Likewise.
1238 (vstrbq_scatter_offset): Likewise.
1239 (vstrbq_p): Likewise.
1240 (vstrbq_scatter_offset_p): Likewise.
1241 (vstrdq_scatter_base_p): Likewise.
1242 (vstrdq_scatter_base): Likewise.
1243 (vstrdq_scatter_offset_p): Likewise.
1244 (vstrdq_scatter_offset): Likewise.
1245 (vstrdq_scatter_shifted_offset_p): Likewise.
1246 (vstrdq_scatter_shifted_offset): Likewise.
1247 (vmaxq_x): Likewise.
1248 (vminq_x): Likewise.
1249 (vmovlbq_x): Likewise.
1250 (vmovltq_x): Likewise.
1251 (vmulhq_x): Likewise.
1252 (vmullbq_int_x): Likewise.
1253 (vmullbq_poly_x): Likewise.
1254 (vmulltq_int_x): Likewise.
1255 (vmulltq_poly_x): Likewise.
1256 (vstrbq): Likewise.
1258 2020-03-31 Jakub Jelinek <jakub@redhat.com>
1260 PR target/94368
1261 * config/aarch64/constraints.md (Uph): New constraint.
1262 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
1263 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
1264 constraint.
1266 2020-03-31 Marc Glisse <marc.glisse@inria.fr>
1267 Jakub Jelinek <jakub@redhat.com>
1269 PR middle-end/94412
1270 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
1271 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
1273 2020-03-31 Jakub Jelinek <jakub@redhat.com>
1275 PR tree-optimization/94403
1276 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
1277 ENUMERAL_TYPE lhs_type.
1279 PR rtl-optimization/94344
1280 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
1281 conversions, either on both operands of |^+ or just one. Handle
1282 also extra same precision conversion on RSHIFT_EXPR first operand
1283 provided RSHIFT_EXPR is performed in unsigned type.
1285 2020-03-30 David Malcolm <dmalcolm@redhat.com>
1287 * lra.c (finish_insn_code_data_once): Set the array elements
1288 to NULL after freeing them.
1290 2020-03-30 Andreas Schwab <schwab@suse.de>
1292 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
1293 Define.
1295 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
1297 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
1298 to skip defining builtins based on builtin_mask.
1300 2020-03-30 Jakub Jelinek <jakub@redhat.com>
1302 PR target/94343
1303 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
1304 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
1305 operand is a register. Don't enable masked variants for V*[QH]Imode.
1307 PR target/93069
1308 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
1309 <store_mask_constraint> instead of m in output operand constraint.
1310 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
1311 %{%3%}.
1313 2020-03-30 Alan Modra <amodra@gmail.com>
1315 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
1316 (rs6000_indirect_call_template_1): Adjust to suit.
1317 * config/rs6000/rs6000.md (call_local): Merge call_local32,
1318 call_local64, and call_local_aix.
1319 (call_value_local): Simlarly.
1320 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
1321 and disable pattern when CALL_LONG.
1322 (call_indirect_aix, call_value_indirect_aix): Adjust rtl.
1323 (call_indirect_elfv2, call_indirect_pcrel): Likewise.
1324 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
1326 2020-03-29 H.J. Lu <hongjiu.lu@intel.com>
1328 PR driver/94381
1329 * doc/invoke.texi: Update -falign-functions, -falign-loops and
1330 -falign-jumps documentation.
1332 2020-03-29 Martin Liska <mliska@suse.cz>
1334 PR ipa/94363
1335 * cgraphunit.c (process_function_and_variable_attributes): Remove
1336 double 'attribute' words.
1338 2020-03-29 John David Anglin <dave.anglin@bell.net>
1340 * gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
1341 .align output.
1343 2020-03-28 Jakub Jelinek <jakub@redhat.com>
1345 PR c/93573
1346 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const
1347 to true after setting size to integer_one_node.
1349 PR tree-optimization/94329
1350 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
1351 on the last stmt in a bb, make sure gsi_prev isn't done immediately
1352 after gsi_last_bb.
1354 2020-03-27 Alan Modra <amodra@gmail.com>
1356 PR target/94145
1357 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
1358 for PLT16_LO and PLT_PCREL.
1359 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
1360 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
1361 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
1363 2020-03-27 Martin Sebor <msebor@redhat.com>
1365 PR c++/94098
1366 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes.
1368 2020-03-27 Andrew Stubbs <ams@codesourcery.com>
1370 * config/gcn/gcn-valu.md:
1371 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
1372 (VEC_1REG_MODE): Delete.
1373 (VEC_1REG_ALT): Delete.
1374 (VEC_ALL1REG_MODE): Rename to V_1REG throughout.
1375 (VEC_1REG_INT_MODE): Delete.
1376 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
1377 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
1378 (VEC_2REG_MODE): Rename to V_2REG throughout.
1379 (VEC_REG_MODE): Rename to V_noHI throughout.
1380 (VEC_ALLREG_MODE): Rename to V_ALL throughout.
1381 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout.
1382 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
1383 (VEC_INT_MODE): Delete.
1384 (VEC_FP_MODE): Rename to V_FP throughout and move to top.
1385 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
1386 (FP_MODE): Delete and replace with FP throughout.
1387 (FP_1REG_MODE): Delete and replace with FP_1REG throughout.
1388 (VCMP_MODE): Rename to V_noQI throughout and move to top.
1389 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
1390 * config/gcn/gcn.md (FP): New mode iterator.
1391 (FP_1REG): New mode iterator.
1393 2020-03-27 David Malcolm <dmalcolm@redhat.com>
1395 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this
1396 now emits two .dot files.
1397 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD.
1398 (graphviz_out::end_tr): Only close a TR, not a TD.
1399 (graphviz_out::begin_td): New.
1400 (graphviz_out::end_td): New.
1401 (graphviz_out::begin_trtd): New, replacing the old implementation
1402 of graphviz_out::begin_tr.
1403 (graphviz_out::end_tdtr): New, replacing the old implementation
1404 of graphviz_out::end_tr.
1405 * graphviz.h (graphviz_out::begin_td): New decl.
1406 (graphviz_out::end_td): New decl.
1407 (graphviz_out::begin_trtd): New decl.
1408 (graphviz_out::end_tdtr): New decl.
1410 2020-03-27 Richard Biener <rguenther@suse.de>
1412 PR debug/94273
1413 * dwarf2out.c (should_emit_struct_debug): Return false for
1414 DINFO_LEVEL_TERSE.
1416 2020-03-27 Richard Biener <rguenther@suse.de>
1418 PR tree-optimization/94352
1419 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the
1420 worklist ...
1421 (ssa_propagation_engine::ssa_propagate): ... here after
1422 initializing curr_order.
1424 2020-03-27 Kewen Lin <linkw@gcc.gnu.org>
1426 PR tree-optimization/90332
1427 * tree-vect-stmts.c (vector_vector_composition_type): New function.
1428 (get_group_load_store_type): Adjust to call
1429 vector_vector_composition_type, extend it to construct with scalar
1430 types.
1431 (vectorizable_load): Likewise.
1433 2020-03-27 Roman Zhuykov <zhroma@ispras.ru>
1435 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions.
1436 (create_ddg_dep_no_link): Likewise.
1437 (add_cross_iteration_register_deps): Move debug instruction check.
1438 Other minor refactoring.
1439 (add_intra_loop_mem_dep): Do not check for debug instructions.
1440 (add_inter_loop_mem_dep): Likewise.
1441 (build_intra_loop_deps): Likewise.
1442 (create_ddg): Do not include debug insns into the graph.
1443 * ddg.h (struct ddg): Remove num_debug field.
1444 * modulo-sched.c (doloop_register_get): Adjust condition.
1445 (res_MII): Remove DDG num_debug field usage.
1446 (sms_schedule_by_order): Use assertion against debug insns.
1447 (ps_has_conflicts): Drop debug insn check.
1449 2020-03-26 Jakub Jelinek <jakub@redhat.com>
1451 PR debug/94323
1452 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST
1453 that contains exactly one non-DEBUG_BEGIN_STMT statement.
1455 PR debug/94281
1456 * gimple.h (gimple_seq_first_nondebug_stmt): New function.
1457 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains
1458 a single non-debug stmt followed by one or more debug stmts.
1459 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt
1460 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt
1461 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and
1462 gimple_seq_last to check if outer_stmt gbind could be reused and
1463 if yes and it is surrounded by any debug stmts, move them into the
1464 gbind body.
1466 PR rtl-optimization/92264
1467 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even
1468 for sp based values in !frame_pointer_needed
1469 && !ACCUMULATE_OUTGOING_ARGS functions.
1471 2020-03-26 Felix Yang <felix.yang@huawei.com>
1473 PR tree-optimization/94269
1474 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict
1475 this
1476 operation to single basic block.
1478 2020-03-25 Jeff Law <law@redhat.com>
1480 PR rtl-optimization/90275
1481 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
1482 pattern.
1484 2020-03-25 Jakub Jelinek <jakub@redhat.com>
1486 PR target/94292
1487 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to
1488 mode rather than VOIDmode.
1490 2020-03-25 Martin Sebor <msebor@redhat.com>
1492 PR middle-end/94004
1493 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings
1494 even for alloca calls resulting from system macro expansion.
1495 Include inlining context in all warnings.
1497 2020-03-25 Richard Sandiford <richard.sandiford@arm.com>
1499 PR target/94254
1500 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
1501 FPRs to change between SDmode and DDmode.
1503 2020-03-25 Martin Sebor <msebor@redhat.com>
1505 PR tree-optimization/94131
1506 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length
1507 types and decls.
1508 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming
1509 types have constant sizes.
1511 2020-03-25 Martin Liska <mliska@suse.cz>
1513 PR lto/94259
1514 * configure.ac: Report error only when --with-zstd
1515 is used.
1516 * configure: Regenerate.
1518 2020-03-25 Jakub Jelinek <jakub@redhat.com>
1520 PR target/94308
1521 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
1522 INSN_CODE (insn) to -1 when changing the pattern.
1524 2020-03-25 Martin Liska <mliska@suse.cz>
1526 PR target/93274
1527 PR ipa/94271
1528 * config/i386/i386-features.c (make_resolver_func): Drop
1529 public flag for resolver.
1530 * config/rs6000/rs6000.c (make_resolver_func): Add comdat
1531 group for resolver and drop public flag if possible.
1532 * multiple_target.c (create_dispatcher_calls): Drop unique_name
1533 and resolution as we want to enable LTO privatization of the default
1534 symbol.
1536 2020-03-25 Martin Liska <mliska@suse.cz>
1538 PR lto/94259
1539 * configure.ac: Respect --without-zstd and report
1540 error when we can't find header file with --with-zstd.
1541 * configure: Regenerate.
1543 2020-03-25 Jakub Jelinek <jakub@redhat.com>
1545 PR middle-end/94303
1546 * varasm.c (output_constructor_array_range): If local->index
1547 RANGE_EXPR doesn't start at the current location in the constructor,
1548 skip needed number of bytes using assemble_zeros or assert we don't
1549 go backwards.
1551 PR c++/94223
1552 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong
1553 counter instead of DECL_UID.
1555 PR tree-optimization/94300
1556 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset
1557 is positive, make sure that off + size isn't larger than needed_len.
1559 2020-03-25 Richard Biener <rguenther@suse.de>
1560 Jakub Jelinek <jakub@redhat.com>
1562 PR debug/94283
1563 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
1565 2020-03-24 Christophe Lyon <christophe.lyon@linaro.org>
1567 * doc/sourcebuild.texi (ARM-specific attributes): Add
1568 arm_fp_dp_ok.
1569 (Features for dg-add-options): Add arm_fp_dp.
1571 2020-03-24 John David Anglin <danglin@gcc.gnu.org>
1573 PR lto/94249
1574 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
1576 2020-03-24 Tobias Burnus <tobias@codesourcery.com>
1578 PR libgomp/81689
1579 * omp-offload.c (omp_finish_file): Fix target-link handling if
1580 targetm_common.have_named_sections is false.
1582 2020-03-24 Jakub Jelinek <jakub@redhat.com>
1584 PR target/94286
1585 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
1586 instead of GEN_INT.
1588 PR debug/94285
1589 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
1590 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.
1591 If not after and at *incr_pos is a debug stmt, set stmt location to
1592 location of next non-debug stmt after it if any.
1594 PR debug/94283
1595 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
1596 GF_PLF_2, but don't add them to worklist. Don't add an assigment to
1597 worklist or set GF_PLF_2 just because it is used in a debug stmt in
1598 another bb. Formatting improvements.
1600 PR debug/94277
1601 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and
1602 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC
1603 regardless of whether TREE_NO_WARNING is set on it or whether
1604 warn_unused_function is true or not.
1606 2020-03-23 Jeff Law <law@redhat.com>
1608 PR rtl-optimization/90275
1609 PR target/94238
1610 PR target/94144
1611 * simplify-rtx.c (comparison_code_valid_for_mode): New function.
1612 (simplify_logical_relational_operation): Use it.
1614 2020-03-23 Jakub Jelinek <jakub@redhat.com>
1616 PR c++/91993
1617 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on
1618 ultimate rhs and if returned something different, reconstructing
1619 the COMPOUND_EXPRs.
1621 2020-03-23 Lewis Hyatt <lhyatt@gmail.com>
1623 * opts.c (print_filtered_help): Improve the help text for alias options.
1625 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1626 Andre Vieira <andre.simoesdiasvieira@arm.com>
1627 Mihail Ionescu <mihail.ionescu@arm.com>
1629 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
1630 (vshlcq_m_u8): Likewise.
1631 (vshlcq_m_s16): Likewise.
1632 (vshlcq_m_u16): Likewise.
1633 (vshlcq_m_s32): Likewise.
1634 (vshlcq_m_u32): Likewise.
1635 (__arm_vshlcq_m_s8): Define intrinsic.
1636 (__arm_vshlcq_m_u8): Likewise.
1637 (__arm_vshlcq_m_s16): Likewise.
1638 (__arm_vshlcq_m_u16): Likewise.
1639 (__arm_vshlcq_m_s32): Likewise.
1640 (__arm_vshlcq_m_u32): Likewise.
1641 (vshlcq_m): Define polymorphic variant.
1642 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
1643 Use builtin qualifier.
1644 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
1645 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern.
1646 (mve_vshlcq_m_carry_<supf><mode>): Likewise.
1647 (mve_vshlcq_m_<supf><mode>): Likewise.
1649 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1651 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
1652 (UQSHL_QUALIFIERS): Likewise.
1653 (ASRL_QUALIFIERS): Likewise.
1654 (SQSHL_QUALIFIERS): Likewise.
1655 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
1656 Big-Endian Mode.
1657 (sqrshr): Define macro.
1658 (sqrshrl): Likewise.
1659 (sqrshrl_sat48): Likewise.
1660 (sqshl): Likewise.
1661 (sqshll): Likewise.
1662 (srshr): Likewise.
1663 (srshrl): Likewise.
1664 (uqrshl): Likewise.
1665 (uqrshll): Likewise.
1666 (uqrshll_sat48): Likewise.
1667 (uqshl): Likewise.
1668 (uqshll): Likewise.
1669 (urshr): Likewise.
1670 (urshrl): Likewise.
1671 (lsll): Likewise.
1672 (asrl): Likewise.
1673 (__arm_lsll): Define intrinsic.
1674 (__arm_asrl): Likewise.
1675 (__arm_uqrshll): Likewise.
1676 (__arm_uqrshll_sat48): Likewise.
1677 (__arm_sqrshrl): Likewise.
1678 (__arm_sqrshrl_sat48): Likewise.
1679 (__arm_uqshll): Likewise.
1680 (__arm_urshrl): Likewise.
1681 (__arm_srshrl): Likewise.
1682 (__arm_sqshll): Likewise.
1683 (__arm_uqrshl): Likewise.
1684 (__arm_sqrshr): Likewise.
1685 (__arm_uqshl): Likewise.
1686 (__arm_urshr): Likewise.
1687 (__arm_sqshl): Likewise.
1688 (__arm_srshr): Likewise.
1689 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
1690 qualifier.
1691 (UQSHL_QUALIFIERS): Likewise.
1692 (ASRL_QUALIFIERS): Likewise.
1693 (SQSHL_QUALIFIERS): Likewise.
1694 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
1695 (mve_sqrshrl_sat<supf>_di): Likewise.
1696 (mve_uqrshl_si): Likewise.
1697 (mve_sqrshr_si): Likewise.
1698 (mve_uqshll_di): Likewise.
1699 (mve_urshrl_di): Likewise.
1700 (mve_uqshl_si): Likewise.
1701 (mve_urshr_si): Likewise.
1702 (mve_sqshl_si): Likewise.
1703 (mve_srshr_si): Likewise.
1704 (mve_srshrl_di): Likewise.
1705 (mve_sqshll_di): Likewise.
1707 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1708 Andre Vieira <andre.simoesdiasvieira@arm.com>
1709 Mihail Ionescu <mihail.ionescu@arm.com>
1711 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro.
1712 (vsetq_lane_f32): Likewise.
1713 (vsetq_lane_s16): Likewise.
1714 (vsetq_lane_s32): Likewise.
1715 (vsetq_lane_s8): Likewise.
1716 (vsetq_lane_s64): Likewise.
1717 (vsetq_lane_u8): Likewise.
1718 (vsetq_lane_u16): Likewise.
1719 (vsetq_lane_u32): Likewise.
1720 (vsetq_lane_u64): Likewise.
1721 (vgetq_lane_f16): Likewise.
1722 (vgetq_lane_f32): Likewise.
1723 (vgetq_lane_s16): Likewise.
1724 (vgetq_lane_s32): Likewise.
1725 (vgetq_lane_s8): Likewise.
1726 (vgetq_lane_s64): Likewise.
1727 (vgetq_lane_u8): Likewise.
1728 (vgetq_lane_u16): Likewise.
1729 (vgetq_lane_u32): Likewise.
1730 (vgetq_lane_u64): Likewise.
1731 (__ARM_NUM_LANES): Likewise.
1732 (__ARM_LANEQ): Likewise.
1733 (__ARM_CHECK_LANEQ): Likewise.
1734 (__arm_vsetq_lane_s16): Define intrinsic.
1735 (__arm_vsetq_lane_s32): Likewise.
1736 (__arm_vsetq_lane_s8): Likewise.
1737 (__arm_vsetq_lane_s64): Likewise.
1738 (__arm_vsetq_lane_u8): Likewise.
1739 (__arm_vsetq_lane_u16): Likewise.
1740 (__arm_vsetq_lane_u32): Likewise.
1741 (__arm_vsetq_lane_u64): Likewise.
1742 (__arm_vgetq_lane_s16): Likewise.
1743 (__arm_vgetq_lane_s32): Likewise.
1744 (__arm_vgetq_lane_s8): Likewise.
1745 (__arm_vgetq_lane_s64): Likewise.
1746 (__arm_vgetq_lane_u8): Likewise.
1747 (__arm_vgetq_lane_u16): Likewise.
1748 (__arm_vgetq_lane_u32): Likewise.
1749 (__arm_vgetq_lane_u64): Likewise.
1750 (__arm_vsetq_lane_f16): Likewise.
1751 (__arm_vsetq_lane_f32): Likewise.
1752 (__arm_vgetq_lane_f16): Likewise.
1753 (__arm_vgetq_lane_f32): Likewise.
1754 (vgetq_lane): Define polymorphic variant.
1755 (vsetq_lane): Likewise.
1756 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL
1757 pattern.
1758 (mve_vec_extractv2didi): Likewise.
1759 (mve_vec_extract_sext_internal<mode>): Likewise.
1760 (mve_vec_extract_zext_internal<mode>): Likewise.
1761 (mve_vec_set<mode>_internal): Likewise.
1762 (mve_vec_setv2di_internal): Likewise.
1763 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md
1764 file.
1765 (vec_extract<mode><V_elem_l>): Rename to
1766 "neon_vec_extract<mode><V_elem_l>".
1767 (vec_extractv2didi): Rename to "neon_vec_extractv2didi".
1768 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL
1769 pattern common for MVE and NEON.
1770 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both
1771 MVE and NEON.
1773 2020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
1775 * config/arm/mve.md (earlyclobber_32): New mode attribute.
1776 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
1777 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
1779 2020-03-23 Richard Biener <rguenther@suse.de>
1781 PR tree-optimization/94261
1782 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove
1783 IL operand swapping code.
1784 (vect_slp_rearrange_stmts): Do not arrange isomorphic
1785 nodes that would need operation code adjustments.
1787 2020-03-23 Tobias Burnus <tobias@codesourcery.com>
1789 * doc/install.texi (amdgcn-*-amdhsa): Renamed
1790 from amdgcn-unknown-amdhsa; change
1791 amdgcn-unknown-amdhsa to amdgcn-amdhsa.
1793 2020-03-23 Richard Biener <rguenther@suse.de>
1795 PR ipa/94245
1796 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP
1797 directly rather than also folding it via build_fold_addr_expr.
1799 2020-03-23 Richard Biener <rguenther@suse.de>
1801 PR tree-optimization/94266
1802 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate
1803 addresses of TARGET_MEM_REFs.
1805 2020-03-23 Martin Liska <mliska@suse.cz>
1807 PR ipa/94250
1808 * symtab.c (symtab_node::clone_references): Save speculative_id
1809 as ref may be overwritten by create_reference.
1810 (symtab_node::clone_referring): Likewise.
1811 (symtab_node::clone_reference): Likewise.
1813 2020-03-22 Iain Sandoe <iain@sandoe.co.uk>
1815 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
1816 references to Darwin.
1817 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
1818 unconditionally and comment on why.
1820 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
1822 * config/darwin.c (darwin_mergeable_constant_section): Collect
1823 section anchor checks into the caller.
1824 (machopic_select_section): Collect section anchor checks into
1825 the determination of 'effective zero-size' objects. When the
1826 size is unknown, assume it is non-zero, and thus return the
1827 'generic' section for the DECL.
1829 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
1831 PR target/93694
1832 * gcc/config/darwin.opt: Amend options descriptions.
1834 2020-03-21 Richard Sandiford <richard.sandiford@arm.com>
1836 PR rtl-optimization/94052
1837 * lra-constraints.c (simplify_operand_subreg): Reload the inner
1838 register of a paradoxical subreg if simplify_subreg_regno fails
1839 to give a valid hard register for the outer mode.
1841 2020-03-20 Martin Jambor <mjambor@suse.cz>
1843 PR tree-optimization/93435
1844 * params.opt (sra-max-propagations): New parameter.
1845 * tree-sra.c (propagation_budget): New variable.
1846 (budget_for_propagation_access): New function.
1847 (propagate_subaccesses_from_rhs): Use it.
1848 (propagate_subaccesses_from_lhs): Likewise.
1849 (propagate_all_subaccesses): Set up and destroy propagation_budget.
1851 2020-03-20 Carl Love <cel@us.ibm.com>
1853 PR/target 87583
1854 * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal):
1855 Add check for TARGET_FPRND for Power 7 or newer.
1857 2020-03-20 Jan Hubicka <hubicka@ucw.cz>
1859 PR ipa/93347
1860 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag.
1861 (cgraph_edge::redirect_callee): Move here; likewise.
1862 (cgraph_node::remove_callees): Update calls_comdat_local flag.
1863 (cgraph_node::verify_node): Verify that calls_comdat_local flag match
1864 reality.
1865 (cgraph_node::check_calls_comdat_local_p): New member function.
1866 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare.
1867 (cgraph_edge::redirect_callee): Move offline.
1868 * ipa-fnsummary.c (compute_fn_summary): Do not compute
1869 calls_comdat_local flag here.
1870 * ipa-inline-transform.c (inline_call): Fix updating of
1871 calls_comdat_local flag.
1872 * ipa-split.c (split_function): Use true instead of 1 to set the flag.
1873 * symtab.c (symtab_node::add_to_same_comdat_group): Update
1874 calls_comdat_local flag.
1876 2020-03-20 Richard Biener <rguenther@suse.de>
1878 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree
1879 from the possibly modified root.
1881 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1882 Andre Vieira <andre.simoesdiasvieira@arm.com>
1883 Mihail Ionescu <mihail.ionescu@arm.com>
1885 * config/arm/arm_mve.h (vst1q_p_u8): Define macro.
1886 (vst1q_p_s8): Likewise.
1887 (vst2q_s8): Likewise.
1888 (vst2q_u8): Likewise.
1889 (vld1q_z_u8): Likewise.
1890 (vld1q_z_s8): Likewise.
1891 (vld2q_s8): Likewise.
1892 (vld2q_u8): Likewise.
1893 (vld4q_s8): Likewise.
1894 (vld4q_u8): Likewise.
1895 (vst1q_p_u16): Likewise.
1896 (vst1q_p_s16): Likewise.
1897 (vst2q_s16): Likewise.
1898 (vst2q_u16): Likewise.
1899 (vld1q_z_u16): Likewise.
1900 (vld1q_z_s16): Likewise.
1901 (vld2q_s16): Likewise.
1902 (vld2q_u16): Likewise.
1903 (vld4q_s16): Likewise.
1904 (vld4q_u16): Likewise.
1905 (vst1q_p_u32): Likewise.
1906 (vst1q_p_s32): Likewise.
1907 (vst2q_s32): Likewise.
1908 (vst2q_u32): Likewise.
1909 (vld1q_z_u32): Likewise.
1910 (vld1q_z_s32): Likewise.
1911 (vld2q_s32): Likewise.
1912 (vld2q_u32): Likewise.
1913 (vld4q_s32): Likewise.
1914 (vld4q_u32): Likewise.
1915 (vld4q_f16): Likewise.
1916 (vld2q_f16): Likewise.
1917 (vld1q_z_f16): Likewise.
1918 (vst2q_f16): Likewise.
1919 (vst1q_p_f16): Likewise.
1920 (vld4q_f32): Likewise.
1921 (vld2q_f32): Likewise.
1922 (vld1q_z_f32): Likewise.
1923 (vst2q_f32): Likewise.
1924 (vst1q_p_f32): Likewise.
1925 (__arm_vst1q_p_u8): Define intrinsic.
1926 (__arm_vst1q_p_s8): Likewise.
1927 (__arm_vst2q_s8): Likewise.
1928 (__arm_vst2q_u8): Likewise.
1929 (__arm_vld1q_z_u8): Likewise.
1930 (__arm_vld1q_z_s8): Likewise.
1931 (__arm_vld2q_s8): Likewise.
1932 (__arm_vld2q_u8): Likewise.
1933 (__arm_vld4q_s8): Likewise.
1934 (__arm_vld4q_u8): Likewise.
1935 (__arm_vst1q_p_u16): Likewise.
1936 (__arm_vst1q_p_s16): Likewise.
1937 (__arm_vst2q_s16): Likewise.
1938 (__arm_vst2q_u16): Likewise.
1939 (__arm_vld1q_z_u16): Likewise.
1940 (__arm_vld1q_z_s16): Likewise.
1941 (__arm_vld2q_s16): Likewise.
1942 (__arm_vld2q_u16): Likewise.
1943 (__arm_vld4q_s16): Likewise.
1944 (__arm_vld4q_u16): Likewise.
1945 (__arm_vst1q_p_u32): Likewise.
1946 (__arm_vst1q_p_s32): Likewise.
1947 (__arm_vst2q_s32): Likewise.
1948 (__arm_vst2q_u32): Likewise.
1949 (__arm_vld1q_z_u32): Likewise.
1950 (__arm_vld1q_z_s32): Likewise.
1951 (__arm_vld2q_s32): Likewise.
1952 (__arm_vld2q_u32): Likewise.
1953 (__arm_vld4q_s32): Likewise.
1954 (__arm_vld4q_u32): Likewise.
1955 (__arm_vld4q_f16): Likewise.
1956 (__arm_vld2q_f16): Likewise.
1957 (__arm_vld1q_z_f16): Likewise.
1958 (__arm_vst2q_f16): Likewise.
1959 (__arm_vst1q_p_f16): Likewise.
1960 (__arm_vld4q_f32): Likewise.
1961 (__arm_vld2q_f32): Likewise.
1962 (__arm_vld1q_z_f32): Likewise.
1963 (__arm_vst2q_f32): Likewise.
1964 (__arm_vst1q_p_f32): Likewise.
1965 (vld1q_z): Define polymorphic variant.
1966 (vld2q): Likewise.
1967 (vld4q): Likewise.
1968 (vst1q_p): Likewise.
1969 (vst2q): Likewise.
1970 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier.
1971 (LOAD1): Likewise.
1972 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern.
1973 (mve_vld2q<mode>): Likewise.
1974 (mve_vld4q<mode>): Likewise.
1976 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1977 Andre Vieira <andre.simoesdiasvieira@arm.com>
1978 Mihail Ionescu <mihail.ionescu@arm.com>
1980 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define.
1981 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise.
1982 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and
1983 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array.
1984 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC
1985 and ARM_BUILTIN_SET_FPSCR_NZCVQC.
1986 * config/arm/arm_mve.h (vadciq_s32): Define macro.
1987 (vadciq_u32): Likewise.
1988 (vadciq_m_s32): Likewise.
1989 (vadciq_m_u32): Likewise.
1990 (vadcq_s32): Likewise.
1991 (vadcq_u32): Likewise.
1992 (vadcq_m_s32): Likewise.
1993 (vadcq_m_u32): Likewise.
1994 (vsbciq_s32): Likewise.
1995 (vsbciq_u32): Likewise.
1996 (vsbciq_m_s32): Likewise.
1997 (vsbciq_m_u32): Likewise.
1998 (vsbcq_s32): Likewise.
1999 (vsbcq_u32): Likewise.
2000 (vsbcq_m_s32): Likewise.
2001 (vsbcq_m_u32): Likewise.
2002 (__arm_vadciq_s32): Define intrinsic.
2003 (__arm_vadciq_u32): Likewise.
2004 (__arm_vadciq_m_s32): Likewise.
2005 (__arm_vadciq_m_u32): Likewise.
2006 (__arm_vadcq_s32): Likewise.
2007 (__arm_vadcq_u32): Likewise.
2008 (__arm_vadcq_m_s32): Likewise.
2009 (__arm_vadcq_m_u32): Likewise.
2010 (__arm_vsbciq_s32): Likewise.
2011 (__arm_vsbciq_u32): Likewise.
2012 (__arm_vsbciq_m_s32): Likewise.
2013 (__arm_vsbciq_m_u32): Likewise.
2014 (__arm_vsbcq_s32): Likewise.
2015 (__arm_vsbcq_u32): Likewise.
2016 (__arm_vsbcq_m_s32): Likewise.
2017 (__arm_vsbcq_m_u32): Likewise.
2018 (vadciq_m): Define polymorphic variant.
2019 (vadciq): Likewise.
2020 (vadcq_m): Likewise.
2021 (vadcq): Likewise.
2022 (vsbciq_m): Likewise.
2023 (vsbciq): Likewise.
2024 (vsbcq_m): Likewise.
2025 (vsbcq): Likewise.
2026 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin
2027 qualifier.
2028 (BINOP_UNONE_UNONE_UNONE): Likewise.
2029 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
2030 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
2031 * config/arm/mve.md (VADCIQ): Define iterator.
2032 (VADCIQ_M): Likewise.
2033 (VSBCQ): Likewise.
2034 (VSBCQ_M): Likewise.
2035 (VSBCIQ): Likewise.
2036 (VSBCIQ_M): Likewise.
2037 (VADCQ): Likewise.
2038 (VADCQ_M): Likewise.
2039 (mve_vadciq_m_<supf>v4si): Define RTL pattern.
2040 (mve_vadciq_<supf>v4si): Likewise.
2041 (mve_vadcq_m_<supf>v4si): Likewise.
2042 (mve_vadcq_<supf>v4si): Likewise.
2043 (mve_vsbciq_m_<supf>v4si): Likewise.
2044 (mve_vsbciq_<supf>v4si): Likewise.
2045 (mve_vsbcq_m_<supf>v4si): Likewise.
2046 (mve_vsbcq_<supf>v4si): Likewise.
2047 (get_fpscr_nzcvqc): Define isns.
2048 (set_fpscr_nzcvqc): Define isns.
2049 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define.
2050 (UNSPEC_SET_FPSCR_NZCVQC): Define.
2052 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2054 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
2055 (vddupq_x_n_u16): Likewise.
2056 (vddupq_x_n_u32): Likewise.
2057 (vddupq_x_wb_u8): Likewise.
2058 (vddupq_x_wb_u16): Likewise.
2059 (vddupq_x_wb_u32): Likewise.
2060 (vdwdupq_x_n_u8): Likewise.
2061 (vdwdupq_x_n_u16): Likewise.
2062 (vdwdupq_x_n_u32): Likewise.
2063 (vdwdupq_x_wb_u8): Likewise.
2064 (vdwdupq_x_wb_u16): Likewise.
2065 (vdwdupq_x_wb_u32): Likewise.
2066 (vidupq_x_n_u8): Likewise.
2067 (vidupq_x_n_u16): Likewise.
2068 (vidupq_x_n_u32): Likewise.
2069 (vidupq_x_wb_u8): Likewise.
2070 (vidupq_x_wb_u16): Likewise.
2071 (vidupq_x_wb_u32): Likewise.
2072 (viwdupq_x_n_u8): Likewise.
2073 (viwdupq_x_n_u16): Likewise.
2074 (viwdupq_x_n_u32): Likewise.
2075 (viwdupq_x_wb_u8): Likewise.
2076 (viwdupq_x_wb_u16): Likewise.
2077 (viwdupq_x_wb_u32): Likewise.
2078 (vdupq_x_n_s8): Likewise.
2079 (vdupq_x_n_s16): Likewise.
2080 (vdupq_x_n_s32): Likewise.
2081 (vdupq_x_n_u8): Likewise.
2082 (vdupq_x_n_u16): Likewise.
2083 (vdupq_x_n_u32): Likewise.
2084 (vminq_x_s8): Likewise.
2085 (vminq_x_s16): Likewise.
2086 (vminq_x_s32): Likewise.
2087 (vminq_x_u8): Likewise.
2088 (vminq_x_u16): Likewise.
2089 (vminq_x_u32): Likewise.
2090 (vmaxq_x_s8): Likewise.
2091 (vmaxq_x_s16): Likewise.
2092 (vmaxq_x_s32): Likewise.
2093 (vmaxq_x_u8): Likewise.
2094 (vmaxq_x_u16): Likewise.
2095 (vmaxq_x_u32): Likewise.
2096 (vabdq_x_s8): Likewise.
2097 (vabdq_x_s16): Likewise.
2098 (vabdq_x_s32): Likewise.
2099 (vabdq_x_u8): Likewise.
2100 (vabdq_x_u16): Likewise.
2101 (vabdq_x_u32): Likewise.
2102 (vabsq_x_s8): Likewise.
2103 (vabsq_x_s16): Likewise.
2104 (vabsq_x_s32): Likewise.
2105 (vaddq_x_s8): Likewise.
2106 (vaddq_x_s16): Likewise.
2107 (vaddq_x_s32): Likewise.
2108 (vaddq_x_n_s8): Likewise.
2109 (vaddq_x_n_s16): Likewise.
2110 (vaddq_x_n_s32): Likewise.
2111 (vaddq_x_u8): Likewise.
2112 (vaddq_x_u16): Likewise.
2113 (vaddq_x_u32): Likewise.
2114 (vaddq_x_n_u8): Likewise.
2115 (vaddq_x_n_u16): Likewise.
2116 (vaddq_x_n_u32): Likewise.
2117 (vclsq_x_s8): Likewise.
2118 (vclsq_x_s16): Likewise.
2119 (vclsq_x_s32): Likewise.
2120 (vclzq_x_s8): Likewise.
2121 (vclzq_x_s16): Likewise.
2122 (vclzq_x_s32): Likewise.
2123 (vclzq_x_u8): Likewise.
2124 (vclzq_x_u16): Likewise.
2125 (vclzq_x_u32): Likewise.
2126 (vnegq_x_s8): Likewise.
2127 (vnegq_x_s16): Likewise.
2128 (vnegq_x_s32): Likewise.
2129 (vmulhq_x_s8): Likewise.
2130 (vmulhq_x_s16): Likewise.
2131 (vmulhq_x_s32): Likewise.
2132 (vmulhq_x_u8): Likewise.
2133 (vmulhq_x_u16): Likewise.
2134 (vmulhq_x_u32): Likewise.
2135 (vmullbq_poly_x_p8): Likewise.
2136 (vmullbq_poly_x_p16): Likewise.
2137 (vmullbq_int_x_s8): Likewise.
2138 (vmullbq_int_x_s16): Likewise.
2139 (vmullbq_int_x_s32): Likewise.
2140 (vmullbq_int_x_u8): Likewise.
2141 (vmullbq_int_x_u16): Likewise.
2142 (vmullbq_int_x_u32): Likewise.
2143 (vmulltq_poly_x_p8): Likewise.
2144 (vmulltq_poly_x_p16): Likewise.
2145 (vmulltq_int_x_s8): Likewise.
2146 (vmulltq_int_x_s16): Likewise.
2147 (vmulltq_int_x_s32): Likewise.
2148 (vmulltq_int_x_u8): Likewise.
2149 (vmulltq_int_x_u16): Likewise.
2150 (vmulltq_int_x_u32): Likewise.
2151 (vmulq_x_s8): Likewise.
2152 (vmulq_x_s16): Likewise.
2153 (vmulq_x_s32): Likewise.
2154 (vmulq_x_n_s8): Likewise.
2155 (vmulq_x_n_s16): Likewise.
2156 (vmulq_x_n_s32): Likewise.
2157 (vmulq_x_u8): Likewise.
2158 (vmulq_x_u16): Likewise.
2159 (vmulq_x_u32): Likewise.
2160 (vmulq_x_n_u8): Likewise.
2161 (vmulq_x_n_u16): Likewise.
2162 (vmulq_x_n_u32): Likewise.
2163 (vsubq_x_s8): Likewise.
2164 (vsubq_x_s16): Likewise.
2165 (vsubq_x_s32): Likewise.
2166 (vsubq_x_n_s8): Likewise.
2167 (vsubq_x_n_s16): Likewise.
2168 (vsubq_x_n_s32): Likewise.
2169 (vsubq_x_u8): Likewise.
2170 (vsubq_x_u16): Likewise.
2171 (vsubq_x_u32): Likewise.
2172 (vsubq_x_n_u8): Likewise.
2173 (vsubq_x_n_u16): Likewise.
2174 (vsubq_x_n_u32): Likewise.
2175 (vcaddq_rot90_x_s8): Likewise.
2176 (vcaddq_rot90_x_s16): Likewise.
2177 (vcaddq_rot90_x_s32): Likewise.
2178 (vcaddq_rot90_x_u8): Likewise.
2179 (vcaddq_rot90_x_u16): Likewise.
2180 (vcaddq_rot90_x_u32): Likewise.
2181 (vcaddq_rot270_x_s8): Likewise.
2182 (vcaddq_rot270_x_s16): Likewise.
2183 (vcaddq_rot270_x_s32): Likewise.
2184 (vcaddq_rot270_x_u8): Likewise.
2185 (vcaddq_rot270_x_u16): Likewise.
2186 (vcaddq_rot270_x_u32): Likewise.
2187 (vhaddq_x_n_s8): Likewise.
2188 (vhaddq_x_n_s16): Likewise.
2189 (vhaddq_x_n_s32): Likewise.
2190 (vhaddq_x_n_u8): Likewise.
2191 (vhaddq_x_n_u16): Likewise.
2192 (vhaddq_x_n_u32): Likewise.
2193 (vhaddq_x_s8): Likewise.
2194 (vhaddq_x_s16): Likewise.
2195 (vhaddq_x_s32): Likewise.
2196 (vhaddq_x_u8): Likewise.
2197 (vhaddq_x_u16): Likewise.
2198 (vhaddq_x_u32): Likewise.
2199 (vhcaddq_rot90_x_s8): Likewise.
2200 (vhcaddq_rot90_x_s16): Likewise.
2201 (vhcaddq_rot90_x_s32): Likewise.
2202 (vhcaddq_rot270_x_s8): Likewise.
2203 (vhcaddq_rot270_x_s16): Likewise.
2204 (vhcaddq_rot270_x_s32): Likewise.
2205 (vhsubq_x_n_s8): Likewise.
2206 (vhsubq_x_n_s16): Likewise.
2207 (vhsubq_x_n_s32): Likewise.
2208 (vhsubq_x_n_u8): Likewise.
2209 (vhsubq_x_n_u16): Likewise.
2210 (vhsubq_x_n_u32): Likewise.
2211 (vhsubq_x_s8): Likewise.
2212 (vhsubq_x_s16): Likewise.
2213 (vhsubq_x_s32): Likewise.
2214 (vhsubq_x_u8): Likewise.
2215 (vhsubq_x_u16): Likewise.
2216 (vhsubq_x_u32): Likewise.
2217 (vrhaddq_x_s8): Likewise.
2218 (vrhaddq_x_s16): Likewise.
2219 (vrhaddq_x_s32): Likewise.
2220 (vrhaddq_x_u8): Likewise.
2221 (vrhaddq_x_u16): Likewise.
2222 (vrhaddq_x_u32): Likewise.
2223 (vrmulhq_x_s8): Likewise.
2224 (vrmulhq_x_s16): Likewise.
2225 (vrmulhq_x_s32): Likewise.
2226 (vrmulhq_x_u8): Likewise.
2227 (vrmulhq_x_u16): Likewise.
2228 (vrmulhq_x_u32): Likewise.
2229 (vandq_x_s8): Likewise.
2230 (vandq_x_s16): Likewise.
2231 (vandq_x_s32): Likewise.
2232 (vandq_x_u8): Likewise.
2233 (vandq_x_u16): Likewise.
2234 (vandq_x_u32): Likewise.
2235 (vbicq_x_s8): Likewise.
2236 (vbicq_x_s16): Likewise.
2237 (vbicq_x_s32): Likewise.
2238 (vbicq_x_u8): Likewise.
2239 (vbicq_x_u16): Likewise.
2240 (vbicq_x_u32): Likewise.
2241 (vbrsrq_x_n_s8): Likewise.
2242 (vbrsrq_x_n_s16): Likewise.
2243 (vbrsrq_x_n_s32): Likewise.
2244 (vbrsrq_x_n_u8): Likewise.
2245 (vbrsrq_x_n_u16): Likewise.
2246 (vbrsrq_x_n_u32): Likewise.
2247 (veorq_x_s8): Likewise.
2248 (veorq_x_s16): Likewise.
2249 (veorq_x_s32): Likewise.
2250 (veorq_x_u8): Likewise.
2251 (veorq_x_u16): Likewise.
2252 (veorq_x_u32): Likewise.
2253 (vmovlbq_x_s8): Likewise.
2254 (vmovlbq_x_s16): Likewise.
2255 (vmovlbq_x_u8): Likewise.
2256 (vmovlbq_x_u16): Likewise.
2257 (vmovltq_x_s8): Likewise.
2258 (vmovltq_x_s16): Likewise.
2259 (vmovltq_x_u8): Likewise.
2260 (vmovltq_x_u16): Likewise.
2261 (vmvnq_x_s8): Likewise.
2262 (vmvnq_x_s16): Likewise.
2263 (vmvnq_x_s32): Likewise.
2264 (vmvnq_x_u8): Likewise.
2265 (vmvnq_x_u16): Likewise.
2266 (vmvnq_x_u32): Likewise.
2267 (vmvnq_x_n_s16): Likewise.
2268 (vmvnq_x_n_s32): Likewise.
2269 (vmvnq_x_n_u16): Likewise.
2270 (vmvnq_x_n_u32): Likewise.
2271 (vornq_x_s8): Likewise.
2272 (vornq_x_s16): Likewise.
2273 (vornq_x_s32): Likewise.
2274 (vornq_x_u8): Likewise.
2275 (vornq_x_u16): Likewise.
2276 (vornq_x_u32): Likewise.
2277 (vorrq_x_s8): Likewise.
2278 (vorrq_x_s16): Likewise.
2279 (vorrq_x_s32): Likewise.
2280 (vorrq_x_u8): Likewise.
2281 (vorrq_x_u16): Likewise.
2282 (vorrq_x_u32): Likewise.
2283 (vrev16q_x_s8): Likewise.
2284 (vrev16q_x_u8): Likewise.
2285 (vrev32q_x_s8): Likewise.
2286 (vrev32q_x_s16): Likewise.
2287 (vrev32q_x_u8): Likewise.
2288 (vrev32q_x_u16): Likewise.
2289 (vrev64q_x_s8): Likewise.
2290 (vrev64q_x_s16): Likewise.
2291 (vrev64q_x_s32): Likewise.
2292 (vrev64q_x_u8): Likewise.
2293 (vrev64q_x_u16): Likewise.
2294 (vrev64q_x_u32): Likewise.
2295 (vrshlq_x_s8): Likewise.
2296 (vrshlq_x_s16): Likewise.
2297 (vrshlq_x_s32): Likewise.
2298 (vrshlq_x_u8): Likewise.
2299 (vrshlq_x_u16): Likewise.
2300 (vrshlq_x_u32): Likewise.
2301 (vshllbq_x_n_s8): Likewise.
2302 (vshllbq_x_n_s16): Likewise.
2303 (vshllbq_x_n_u8): Likewise.
2304 (vshllbq_x_n_u16): Likewise.
2305 (vshlltq_x_n_s8): Likewise.
2306 (vshlltq_x_n_s16): Likewise.
2307 (vshlltq_x_n_u8): Likewise.
2308 (vshlltq_x_n_u16): Likewise.
2309 (vshlq_x_s8): Likewise.
2310 (vshlq_x_s16): Likewise.
2311 (vshlq_x_s32): Likewise.
2312 (vshlq_x_u8): Likewise.
2313 (vshlq_x_u16): Likewise.
2314 (vshlq_x_u32): Likewise.
2315 (vshlq_x_n_s8): Likewise.
2316 (vshlq_x_n_s16): Likewise.
2317 (vshlq_x_n_s32): Likewise.
2318 (vshlq_x_n_u8): Likewise.
2319 (vshlq_x_n_u16): Likewise.
2320 (vshlq_x_n_u32): Likewise.
2321 (vrshrq_x_n_s8): Likewise.
2322 (vrshrq_x_n_s16): Likewise.
2323 (vrshrq_x_n_s32): Likewise.
2324 (vrshrq_x_n_u8): Likewise.
2325 (vrshrq_x_n_u16): Likewise.
2326 (vrshrq_x_n_u32): Likewise.
2327 (vshrq_x_n_s8): Likewise.
2328 (vshrq_x_n_s16): Likewise.
2329 (vshrq_x_n_s32): Likewise.
2330 (vshrq_x_n_u8): Likewise.
2331 (vshrq_x_n_u16): Likewise.
2332 (vshrq_x_n_u32): Likewise.
2333 (vdupq_x_n_f16): Likewise.
2334 (vdupq_x_n_f32): Likewise.
2335 (vminnmq_x_f16): Likewise.
2336 (vminnmq_x_f32): Likewise.
2337 (vmaxnmq_x_f16): Likewise.
2338 (vmaxnmq_x_f32): Likewise.
2339 (vabdq_x_f16): Likewise.
2340 (vabdq_x_f32): Likewise.
2341 (vabsq_x_f16): Likewise.
2342 (vabsq_x_f32): Likewise.
2343 (vaddq_x_f16): Likewise.
2344 (vaddq_x_f32): Likewise.
2345 (vaddq_x_n_f16): Likewise.
2346 (vaddq_x_n_f32): Likewise.
2347 (vnegq_x_f16): Likewise.
2348 (vnegq_x_f32): Likewise.
2349 (vmulq_x_f16): Likewise.
2350 (vmulq_x_f32): Likewise.
2351 (vmulq_x_n_f16): Likewise.
2352 (vmulq_x_n_f32): Likewise.
2353 (vsubq_x_f16): Likewise.
2354 (vsubq_x_f32): Likewise.
2355 (vsubq_x_n_f16): Likewise.
2356 (vsubq_x_n_f32): Likewise.
2357 (vcaddq_rot90_x_f16): Likewise.
2358 (vcaddq_rot90_x_f32): Likewise.
2359 (vcaddq_rot270_x_f16): Likewise.
2360 (vcaddq_rot270_x_f32): Likewise.
2361 (vcmulq_x_f16): Likewise.
2362 (vcmulq_x_f32): Likewise.
2363 (vcmulq_rot90_x_f16): Likewise.
2364 (vcmulq_rot90_x_f32): Likewise.
2365 (vcmulq_rot180_x_f16): Likewise.
2366 (vcmulq_rot180_x_f32): Likewise.
2367 (vcmulq_rot270_x_f16): Likewise.
2368 (vcmulq_rot270_x_f32): Likewise.
2369 (vcvtaq_x_s16_f16): Likewise.
2370 (vcvtaq_x_s32_f32): Likewise.
2371 (vcvtaq_x_u16_f16): Likewise.
2372 (vcvtaq_x_u32_f32): Likewise.
2373 (vcvtnq_x_s16_f16): Likewise.
2374 (vcvtnq_x_s32_f32): Likewise.
2375 (vcvtnq_x_u16_f16): Likewise.
2376 (vcvtnq_x_u32_f32): Likewise.
2377 (vcvtpq_x_s16_f16): Likewise.
2378 (vcvtpq_x_s32_f32): Likewise.
2379 (vcvtpq_x_u16_f16): Likewise.
2380 (vcvtpq_x_u32_f32): Likewise.
2381 (vcvtmq_x_s16_f16): Likewise.
2382 (vcvtmq_x_s32_f32): Likewise.
2383 (vcvtmq_x_u16_f16): Likewise.
2384 (vcvtmq_x_u32_f32): Likewise.
2385 (vcvtbq_x_f32_f16): Likewise.
2386 (vcvttq_x_f32_f16): Likewise.
2387 (vcvtq_x_f16_u16): Likewise.
2388 (vcvtq_x_f16_s16): Likewise.
2389 (vcvtq_x_f32_s32): Likewise.
2390 (vcvtq_x_f32_u32): Likewise.
2391 (vcvtq_x_n_f16_s16): Likewise.
2392 (vcvtq_x_n_f16_u16): Likewise.
2393 (vcvtq_x_n_f32_s32): Likewise.
2394 (vcvtq_x_n_f32_u32): Likewise.
2395 (vcvtq_x_s16_f16): Likewise.
2396 (vcvtq_x_s32_f32): Likewise.
2397 (vcvtq_x_u16_f16): Likewise.
2398 (vcvtq_x_u32_f32): Likewise.
2399 (vcvtq_x_n_s16_f16): Likewise.
2400 (vcvtq_x_n_s32_f32): Likewise.
2401 (vcvtq_x_n_u16_f16): Likewise.
2402 (vcvtq_x_n_u32_f32): Likewise.
2403 (vrndq_x_f16): Likewise.
2404 (vrndq_x_f32): Likewise.
2405 (vrndnq_x_f16): Likewise.
2406 (vrndnq_x_f32): Likewise.
2407 (vrndmq_x_f16): Likewise.
2408 (vrndmq_x_f32): Likewise.
2409 (vrndpq_x_f16): Likewise.
2410 (vrndpq_x_f32): Likewise.
2411 (vrndaq_x_f16): Likewise.
2412 (vrndaq_x_f32): Likewise.
2413 (vrndxq_x_f16): Likewise.
2414 (vrndxq_x_f32): Likewise.
2415 (vandq_x_f16): Likewise.
2416 (vandq_x_f32): Likewise.
2417 (vbicq_x_f16): Likewise.
2418 (vbicq_x_f32): Likewise.
2419 (vbrsrq_x_n_f16): Likewise.
2420 (vbrsrq_x_n_f32): Likewise.
2421 (veorq_x_f16): Likewise.
2422 (veorq_x_f32): Likewise.
2423 (vornq_x_f16): Likewise.
2424 (vornq_x_f32): Likewise.
2425 (vorrq_x_f16): Likewise.
2426 (vorrq_x_f32): Likewise.
2427 (vrev32q_x_f16): Likewise.
2428 (vrev64q_x_f16): Likewise.
2429 (vrev64q_x_f32): Likewise.
2430 (__arm_vddupq_x_n_u8): Define intrinsic.
2431 (__arm_vddupq_x_n_u16): Likewise.
2432 (__arm_vddupq_x_n_u32): Likewise.
2433 (__arm_vddupq_x_wb_u8): Likewise.
2434 (__arm_vddupq_x_wb_u16): Likewise.
2435 (__arm_vddupq_x_wb_u32): Likewise.
2436 (__arm_vdwdupq_x_n_u8): Likewise.
2437 (__arm_vdwdupq_x_n_u16): Likewise.
2438 (__arm_vdwdupq_x_n_u32): Likewise.
2439 (__arm_vdwdupq_x_wb_u8): Likewise.
2440 (__arm_vdwdupq_x_wb_u16): Likewise.
2441 (__arm_vdwdupq_x_wb_u32): Likewise.
2442 (__arm_vidupq_x_n_u8): Likewise.
2443 (__arm_vidupq_x_n_u16): Likewise.
2444 (__arm_vidupq_x_n_u32): Likewise.
2445 (__arm_vidupq_x_wb_u8): Likewise.
2446 (__arm_vidupq_x_wb_u16): Likewise.
2447 (__arm_vidupq_x_wb_u32): Likewise.
2448 (__arm_viwdupq_x_n_u8): Likewise.
2449 (__arm_viwdupq_x_n_u16): Likewise.
2450 (__arm_viwdupq_x_n_u32): Likewise.
2451 (__arm_viwdupq_x_wb_u8): Likewise.
2452 (__arm_viwdupq_x_wb_u16): Likewise.
2453 (__arm_viwdupq_x_wb_u32): Likewise.
2454 (__arm_vdupq_x_n_s8): Likewise.
2455 (__arm_vdupq_x_n_s16): Likewise.
2456 (__arm_vdupq_x_n_s32): Likewise.
2457 (__arm_vdupq_x_n_u8): Likewise.
2458 (__arm_vdupq_x_n_u16): Likewise.
2459 (__arm_vdupq_x_n_u32): Likewise.
2460 (__arm_vminq_x_s8): Likewise.
2461 (__arm_vminq_x_s16): Likewise.
2462 (__arm_vminq_x_s32): Likewise.
2463 (__arm_vminq_x_u8): Likewise.
2464 (__arm_vminq_x_u16): Likewise.
2465 (__arm_vminq_x_u32): Likewise.
2466 (__arm_vmaxq_x_s8): Likewise.
2467 (__arm_vmaxq_x_s16): Likewise.
2468 (__arm_vmaxq_x_s32): Likewise.
2469 (__arm_vmaxq_x_u8): Likewise.
2470 (__arm_vmaxq_x_u16): Likewise.
2471 (__arm_vmaxq_x_u32): Likewise.
2472 (__arm_vabdq_x_s8): Likewise.
2473 (__arm_vabdq_x_s16): Likewise.
2474 (__arm_vabdq_x_s32): Likewise.
2475 (__arm_vabdq_x_u8): Likewise.
2476 (__arm_vabdq_x_u16): Likewise.
2477 (__arm_vabdq_x_u32): Likewise.
2478 (__arm_vabsq_x_s8): Likewise.
2479 (__arm_vabsq_x_s16): Likewise.
2480 (__arm_vabsq_x_s32): Likewise.
2481 (__arm_vaddq_x_s8): Likewise.
2482 (__arm_vaddq_x_s16): Likewise.
2483 (__arm_vaddq_x_s32): Likewise.
2484 (__arm_vaddq_x_n_s8): Likewise.
2485 (__arm_vaddq_x_n_s16): Likewise.
2486 (__arm_vaddq_x_n_s32): Likewise.
2487 (__arm_vaddq_x_u8): Likewise.
2488 (__arm_vaddq_x_u16): Likewise.
2489 (__arm_vaddq_x_u32): Likewise.
2490 (__arm_vaddq_x_n_u8): Likewise.
2491 (__arm_vaddq_x_n_u16): Likewise.
2492 (__arm_vaddq_x_n_u32): Likewise.
2493 (__arm_vclsq_x_s8): Likewise.
2494 (__arm_vclsq_x_s16): Likewise.
2495 (__arm_vclsq_x_s32): Likewise.
2496 (__arm_vclzq_x_s8): Likewise.
2497 (__arm_vclzq_x_s16): Likewise.
2498 (__arm_vclzq_x_s32): Likewise.
2499 (__arm_vclzq_x_u8): Likewise.
2500 (__arm_vclzq_x_u16): Likewise.
2501 (__arm_vclzq_x_u32): Likewise.
2502 (__arm_vnegq_x_s8): Likewise.
2503 (__arm_vnegq_x_s16): Likewise.
2504 (__arm_vnegq_x_s32): Likewise.
2505 (__arm_vmulhq_x_s8): Likewise.
2506 (__arm_vmulhq_x_s16): Likewise.
2507 (__arm_vmulhq_x_s32): Likewise.
2508 (__arm_vmulhq_x_u8): Likewise.
2509 (__arm_vmulhq_x_u16): Likewise.
2510 (__arm_vmulhq_x_u32): Likewise.
2511 (__arm_vmullbq_poly_x_p8): Likewise.
2512 (__arm_vmullbq_poly_x_p16): Likewise.
2513 (__arm_vmullbq_int_x_s8): Likewise.
2514 (__arm_vmullbq_int_x_s16): Likewise.
2515 (__arm_vmullbq_int_x_s32): Likewise.
2516 (__arm_vmullbq_int_x_u8): Likewise.
2517 (__arm_vmullbq_int_x_u16): Likewise.
2518 (__arm_vmullbq_int_x_u32): Likewise.
2519 (__arm_vmulltq_poly_x_p8): Likewise.
2520 (__arm_vmulltq_poly_x_p16): Likewise.
2521 (__arm_vmulltq_int_x_s8): Likewise.
2522 (__arm_vmulltq_int_x_s16): Likewise.
2523 (__arm_vmulltq_int_x_s32): Likewise.
2524 (__arm_vmulltq_int_x_u8): Likewise.
2525 (__arm_vmulltq_int_x_u16): Likewise.
2526 (__arm_vmulltq_int_x_u32): Likewise.
2527 (__arm_vmulq_x_s8): Likewise.
2528 (__arm_vmulq_x_s16): Likewise.
2529 (__arm_vmulq_x_s32): Likewise.
2530 (__arm_vmulq_x_n_s8): Likewise.
2531 (__arm_vmulq_x_n_s16): Likewise.
2532 (__arm_vmulq_x_n_s32): Likewise.
2533 (__arm_vmulq_x_u8): Likewise.
2534 (__arm_vmulq_x_u16): Likewise.
2535 (__arm_vmulq_x_u32): Likewise.
2536 (__arm_vmulq_x_n_u8): Likewise.
2537 (__arm_vmulq_x_n_u16): Likewise.
2538 (__arm_vmulq_x_n_u32): Likewise.
2539 (__arm_vsubq_x_s8): Likewise.
2540 (__arm_vsubq_x_s16): Likewise.
2541 (__arm_vsubq_x_s32): Likewise.
2542 (__arm_vsubq_x_n_s8): Likewise.
2543 (__arm_vsubq_x_n_s16): Likewise.
2544 (__arm_vsubq_x_n_s32): Likewise.
2545 (__arm_vsubq_x_u8): Likewise.
2546 (__arm_vsubq_x_u16): Likewise.
2547 (__arm_vsubq_x_u32): Likewise.
2548 (__arm_vsubq_x_n_u8): Likewise.
2549 (__arm_vsubq_x_n_u16): Likewise.
2550 (__arm_vsubq_x_n_u32): Likewise.
2551 (__arm_vcaddq_rot90_x_s8): Likewise.
2552 (__arm_vcaddq_rot90_x_s16): Likewise.
2553 (__arm_vcaddq_rot90_x_s32): Likewise.
2554 (__arm_vcaddq_rot90_x_u8): Likewise.
2555 (__arm_vcaddq_rot90_x_u16): Likewise.
2556 (__arm_vcaddq_rot90_x_u32): Likewise.
2557 (__arm_vcaddq_rot270_x_s8): Likewise.
2558 (__arm_vcaddq_rot270_x_s16): Likewise.
2559 (__arm_vcaddq_rot270_x_s32): Likewise.
2560 (__arm_vcaddq_rot270_x_u8): Likewise.
2561 (__arm_vcaddq_rot270_x_u16): Likewise.
2562 (__arm_vcaddq_rot270_x_u32): Likewise.
2563 (__arm_vhaddq_x_n_s8): Likewise.
2564 (__arm_vhaddq_x_n_s16): Likewise.
2565 (__arm_vhaddq_x_n_s32): Likewise.
2566 (__arm_vhaddq_x_n_u8): Likewise.
2567 (__arm_vhaddq_x_n_u16): Likewise.
2568 (__arm_vhaddq_x_n_u32): Likewise.
2569 (__arm_vhaddq_x_s8): Likewise.
2570 (__arm_vhaddq_x_s16): Likewise.
2571 (__arm_vhaddq_x_s32): Likewise.
2572 (__arm_vhaddq_x_u8): Likewise.
2573 (__arm_vhaddq_x_u16): Likewise.
2574 (__arm_vhaddq_x_u32): Likewise.
2575 (__arm_vhcaddq_rot90_x_s8): Likewise.
2576 (__arm_vhcaddq_rot90_x_s16): Likewise.
2577 (__arm_vhcaddq_rot90_x_s32): Likewise.
2578 (__arm_vhcaddq_rot270_x_s8): Likewise.
2579 (__arm_vhcaddq_rot270_x_s16): Likewise.
2580 (__arm_vhcaddq_rot270_x_s32): Likewise.
2581 (__arm_vhsubq_x_n_s8): Likewise.
2582 (__arm_vhsubq_x_n_s16): Likewise.
2583 (__arm_vhsubq_x_n_s32): Likewise.
2584 (__arm_vhsubq_x_n_u8): Likewise.
2585 (__arm_vhsubq_x_n_u16): Likewise.
2586 (__arm_vhsubq_x_n_u32): Likewise.
2587 (__arm_vhsubq_x_s8): Likewise.
2588 (__arm_vhsubq_x_s16): Likewise.
2589 (__arm_vhsubq_x_s32): Likewise.
2590 (__arm_vhsubq_x_u8): Likewise.
2591 (__arm_vhsubq_x_u16): Likewise.
2592 (__arm_vhsubq_x_u32): Likewise.
2593 (__arm_vrhaddq_x_s8): Likewise.
2594 (__arm_vrhaddq_x_s16): Likewise.
2595 (__arm_vrhaddq_x_s32): Likewise.
2596 (__arm_vrhaddq_x_u8): Likewise.
2597 (__arm_vrhaddq_x_u16): Likewise.
2598 (__arm_vrhaddq_x_u32): Likewise.
2599 (__arm_vrmulhq_x_s8): Likewise.
2600 (__arm_vrmulhq_x_s16): Likewise.
2601 (__arm_vrmulhq_x_s32): Likewise.
2602 (__arm_vrmulhq_x_u8): Likewise.
2603 (__arm_vrmulhq_x_u16): Likewise.
2604 (__arm_vrmulhq_x_u32): Likewise.
2605 (__arm_vandq_x_s8): Likewise.
2606 (__arm_vandq_x_s16): Likewise.
2607 (__arm_vandq_x_s32): Likewise.
2608 (__arm_vandq_x_u8): Likewise.
2609 (__arm_vandq_x_u16): Likewise.
2610 (__arm_vandq_x_u32): Likewise.
2611 (__arm_vbicq_x_s8): Likewise.
2612 (__arm_vbicq_x_s16): Likewise.
2613 (__arm_vbicq_x_s32): Likewise.
2614 (__arm_vbicq_x_u8): Likewise.
2615 (__arm_vbicq_x_u16): Likewise.
2616 (__arm_vbicq_x_u32): Likewise.
2617 (__arm_vbrsrq_x_n_s8): Likewise.
2618 (__arm_vbrsrq_x_n_s16): Likewise.
2619 (__arm_vbrsrq_x_n_s32): Likewise.
2620 (__arm_vbrsrq_x_n_u8): Likewise.
2621 (__arm_vbrsrq_x_n_u16): Likewise.
2622 (__arm_vbrsrq_x_n_u32): Likewise.
2623 (__arm_veorq_x_s8): Likewise.
2624 (__arm_veorq_x_s16): Likewise.
2625 (__arm_veorq_x_s32): Likewise.
2626 (__arm_veorq_x_u8): Likewise.
2627 (__arm_veorq_x_u16): Likewise.
2628 (__arm_veorq_x_u32): Likewise.
2629 (__arm_vmovlbq_x_s8): Likewise.
2630 (__arm_vmovlbq_x_s16): Likewise.
2631 (__arm_vmovlbq_x_u8): Likewise.
2632 (__arm_vmovlbq_x_u16): Likewise.
2633 (__arm_vmovltq_x_s8): Likewise.
2634 (__arm_vmovltq_x_s16): Likewise.
2635 (__arm_vmovltq_x_u8): Likewise.
2636 (__arm_vmovltq_x_u16): Likewise.
2637 (__arm_vmvnq_x_s8): Likewise.
2638 (__arm_vmvnq_x_s16): Likewise.
2639 (__arm_vmvnq_x_s32): Likewise.
2640 (__arm_vmvnq_x_u8): Likewise.
2641 (__arm_vmvnq_x_u16): Likewise.
2642 (__arm_vmvnq_x_u32): Likewise.
2643 (__arm_vmvnq_x_n_s16): Likewise.
2644 (__arm_vmvnq_x_n_s32): Likewise.
2645 (__arm_vmvnq_x_n_u16): Likewise.
2646 (__arm_vmvnq_x_n_u32): Likewise.
2647 (__arm_vornq_x_s8): Likewise.
2648 (__arm_vornq_x_s16): Likewise.
2649 (__arm_vornq_x_s32): Likewise.
2650 (__arm_vornq_x_u8): Likewise.
2651 (__arm_vornq_x_u16): Likewise.
2652 (__arm_vornq_x_u32): Likewise.
2653 (__arm_vorrq_x_s8): Likewise.
2654 (__arm_vorrq_x_s16): Likewise.
2655 (__arm_vorrq_x_s32): Likewise.
2656 (__arm_vorrq_x_u8): Likewise.
2657 (__arm_vorrq_x_u16): Likewise.
2658 (__arm_vorrq_x_u32): Likewise.
2659 (__arm_vrev16q_x_s8): Likewise.
2660 (__arm_vrev16q_x_u8): Likewise.
2661 (__arm_vrev32q_x_s8): Likewise.
2662 (__arm_vrev32q_x_s16): Likewise.
2663 (__arm_vrev32q_x_u8): Likewise.
2664 (__arm_vrev32q_x_u16): Likewise.
2665 (__arm_vrev64q_x_s8): Likewise.
2666 (__arm_vrev64q_x_s16): Likewise.
2667 (__arm_vrev64q_x_s32): Likewise.
2668 (__arm_vrev64q_x_u8): Likewise.
2669 (__arm_vrev64q_x_u16): Likewise.
2670 (__arm_vrev64q_x_u32): Likewise.
2671 (__arm_vrshlq_x_s8): Likewise.
2672 (__arm_vrshlq_x_s16): Likewise.
2673 (__arm_vrshlq_x_s32): Likewise.
2674 (__arm_vrshlq_x_u8): Likewise.
2675 (__arm_vrshlq_x_u16): Likewise.
2676 (__arm_vrshlq_x_u32): Likewise.
2677 (__arm_vshllbq_x_n_s8): Likewise.
2678 (__arm_vshllbq_x_n_s16): Likewise.
2679 (__arm_vshllbq_x_n_u8): Likewise.
2680 (__arm_vshllbq_x_n_u16): Likewise.
2681 (__arm_vshlltq_x_n_s8): Likewise.
2682 (__arm_vshlltq_x_n_s16): Likewise.
2683 (__arm_vshlltq_x_n_u8): Likewise.
2684 (__arm_vshlltq_x_n_u16): Likewise.
2685 (__arm_vshlq_x_s8): Likewise.
2686 (__arm_vshlq_x_s16): Likewise.
2687 (__arm_vshlq_x_s32): Likewise.
2688 (__arm_vshlq_x_u8): Likewise.
2689 (__arm_vshlq_x_u16): Likewise.
2690 (__arm_vshlq_x_u32): Likewise.
2691 (__arm_vshlq_x_n_s8): Likewise.
2692 (__arm_vshlq_x_n_s16): Likewise.
2693 (__arm_vshlq_x_n_s32): Likewise.
2694 (__arm_vshlq_x_n_u8): Likewise.
2695 (__arm_vshlq_x_n_u16): Likewise.
2696 (__arm_vshlq_x_n_u32): Likewise.
2697 (__arm_vrshrq_x_n_s8): Likewise.
2698 (__arm_vrshrq_x_n_s16): Likewise.
2699 (__arm_vrshrq_x_n_s32): Likewise.
2700 (__arm_vrshrq_x_n_u8): Likewise.
2701 (__arm_vrshrq_x_n_u16): Likewise.
2702 (__arm_vrshrq_x_n_u32): Likewise.
2703 (__arm_vshrq_x_n_s8): Likewise.
2704 (__arm_vshrq_x_n_s16): Likewise.
2705 (__arm_vshrq_x_n_s32): Likewise.
2706 (__arm_vshrq_x_n_u8): Likewise.
2707 (__arm_vshrq_x_n_u16): Likewise.
2708 (__arm_vshrq_x_n_u32): Likewise.
2709 (__arm_vdupq_x_n_f16): Likewise.
2710 (__arm_vdupq_x_n_f32): Likewise.
2711 (__arm_vminnmq_x_f16): Likewise.
2712 (__arm_vminnmq_x_f32): Likewise.
2713 (__arm_vmaxnmq_x_f16): Likewise.
2714 (__arm_vmaxnmq_x_f32): Likewise.
2715 (__arm_vabdq_x_f16): Likewise.
2716 (__arm_vabdq_x_f32): Likewise.
2717 (__arm_vabsq_x_f16): Likewise.
2718 (__arm_vabsq_x_f32): Likewise.
2719 (__arm_vaddq_x_f16): Likewise.
2720 (__arm_vaddq_x_f32): Likewise.
2721 (__arm_vaddq_x_n_f16): Likewise.
2722 (__arm_vaddq_x_n_f32): Likewise.
2723 (__arm_vnegq_x_f16): Likewise.
2724 (__arm_vnegq_x_f32): Likewise.
2725 (__arm_vmulq_x_f16): Likewise.
2726 (__arm_vmulq_x_f32): Likewise.
2727 (__arm_vmulq_x_n_f16): Likewise.
2728 (__arm_vmulq_x_n_f32): Likewise.
2729 (__arm_vsubq_x_f16): Likewise.
2730 (__arm_vsubq_x_f32): Likewise.
2731 (__arm_vsubq_x_n_f16): Likewise.
2732 (__arm_vsubq_x_n_f32): Likewise.
2733 (__arm_vcaddq_rot90_x_f16): Likewise.
2734 (__arm_vcaddq_rot90_x_f32): Likewise.
2735 (__arm_vcaddq_rot270_x_f16): Likewise.
2736 (__arm_vcaddq_rot270_x_f32): Likewise.
2737 (__arm_vcmulq_x_f16): Likewise.
2738 (__arm_vcmulq_x_f32): Likewise.
2739 (__arm_vcmulq_rot90_x_f16): Likewise.
2740 (__arm_vcmulq_rot90_x_f32): Likewise.
2741 (__arm_vcmulq_rot180_x_f16): Likewise.
2742 (__arm_vcmulq_rot180_x_f32): Likewise.
2743 (__arm_vcmulq_rot270_x_f16): Likewise.
2744 (__arm_vcmulq_rot270_x_f32): Likewise.
2745 (__arm_vcvtaq_x_s16_f16): Likewise.
2746 (__arm_vcvtaq_x_s32_f32): Likewise.
2747 (__arm_vcvtaq_x_u16_f16): Likewise.
2748 (__arm_vcvtaq_x_u32_f32): Likewise.
2749 (__arm_vcvtnq_x_s16_f16): Likewise.
2750 (__arm_vcvtnq_x_s32_f32): Likewise.
2751 (__arm_vcvtnq_x_u16_f16): Likewise.
2752 (__arm_vcvtnq_x_u32_f32): Likewise.
2753 (__arm_vcvtpq_x_s16_f16): Likewise.
2754 (__arm_vcvtpq_x_s32_f32): Likewise.
2755 (__arm_vcvtpq_x_u16_f16): Likewise.
2756 (__arm_vcvtpq_x_u32_f32): Likewise.
2757 (__arm_vcvtmq_x_s16_f16): Likewise.
2758 (__arm_vcvtmq_x_s32_f32): Likewise.
2759 (__arm_vcvtmq_x_u16_f16): Likewise.
2760 (__arm_vcvtmq_x_u32_f32): Likewise.
2761 (__arm_vcvtbq_x_f32_f16): Likewise.
2762 (__arm_vcvttq_x_f32_f16): Likewise.
2763 (__arm_vcvtq_x_f16_u16): Likewise.
2764 (__arm_vcvtq_x_f16_s16): Likewise.
2765 (__arm_vcvtq_x_f32_s32): Likewise.
2766 (__arm_vcvtq_x_f32_u32): Likewise.
2767 (__arm_vcvtq_x_n_f16_s16): Likewise.
2768 (__arm_vcvtq_x_n_f16_u16): Likewise.
2769 (__arm_vcvtq_x_n_f32_s32): Likewise.
2770 (__arm_vcvtq_x_n_f32_u32): Likewise.
2771 (__arm_vcvtq_x_s16_f16): Likewise.
2772 (__arm_vcvtq_x_s32_f32): Likewise.
2773 (__arm_vcvtq_x_u16_f16): Likewise.
2774 (__arm_vcvtq_x_u32_f32): Likewise.
2775 (__arm_vcvtq_x_n_s16_f16): Likewise.
2776 (__arm_vcvtq_x_n_s32_f32): Likewise.
2777 (__arm_vcvtq_x_n_u16_f16): Likewise.
2778 (__arm_vcvtq_x_n_u32_f32): Likewise.
2779 (__arm_vrndq_x_f16): Likewise.
2780 (__arm_vrndq_x_f32): Likewise.
2781 (__arm_vrndnq_x_f16): Likewise.
2782 (__arm_vrndnq_x_f32): Likewise.
2783 (__arm_vrndmq_x_f16): Likewise.
2784 (__arm_vrndmq_x_f32): Likewise.
2785 (__arm_vrndpq_x_f16): Likewise.
2786 (__arm_vrndpq_x_f32): Likewise.
2787 (__arm_vrndaq_x_f16): Likewise.
2788 (__arm_vrndaq_x_f32): Likewise.
2789 (__arm_vrndxq_x_f16): Likewise.
2790 (__arm_vrndxq_x_f32): Likewise.
2791 (__arm_vandq_x_f16): Likewise.
2792 (__arm_vandq_x_f32): Likewise.
2793 (__arm_vbicq_x_f16): Likewise.
2794 (__arm_vbicq_x_f32): Likewise.
2795 (__arm_vbrsrq_x_n_f16): Likewise.
2796 (__arm_vbrsrq_x_n_f32): Likewise.
2797 (__arm_veorq_x_f16): Likewise.
2798 (__arm_veorq_x_f32): Likewise.
2799 (__arm_vornq_x_f16): Likewise.
2800 (__arm_vornq_x_f32): Likewise.
2801 (__arm_vorrq_x_f16): Likewise.
2802 (__arm_vorrq_x_f32): Likewise.
2803 (__arm_vrev32q_x_f16): Likewise.
2804 (__arm_vrev64q_x_f16): Likewise.
2805 (__arm_vrev64q_x_f32): Likewise.
2806 (vabdq_x): Define polymorphic variant.
2807 (vabsq_x): Likewise.
2808 (vaddq_x): Likewise.
2809 (vandq_x): Likewise.
2810 (vbicq_x): Likewise.
2811 (vbrsrq_x): Likewise.
2812 (vcaddq_rot270_x): Likewise.
2813 (vcaddq_rot90_x): Likewise.
2814 (vcmulq_rot180_x): Likewise.
2815 (vcmulq_rot270_x): Likewise.
2816 (vcmulq_x): Likewise.
2817 (vcvtq_x): Likewise.
2818 (vcvtq_x_n): Likewise.
2819 (vcvtnq_m): Likewise.
2820 (veorq_x): Likewise.
2821 (vmaxnmq_x): Likewise.
2822 (vminnmq_x): Likewise.
2823 (vmulq_x): Likewise.
2824 (vnegq_x): Likewise.
2825 (vornq_x): Likewise.
2826 (vorrq_x): Likewise.
2827 (vrev32q_x): Likewise.
2828 (vrev64q_x): Likewise.
2829 (vrndaq_x): Likewise.
2830 (vrndmq_x): Likewise.
2831 (vrndnq_x): Likewise.
2832 (vrndpq_x): Likewise.
2833 (vrndq_x): Likewise.
2834 (vrndxq_x): Likewise.
2835 (vsubq_x): Likewise.
2836 (vcmulq_rot90_x): Likewise.
2837 (vadciq): Likewise.
2838 (vclsq_x): Likewise.
2839 (vclzq_x): Likewise.
2840 (vhaddq_x): Likewise.
2841 (vhcaddq_rot270_x): Likewise.
2842 (vhcaddq_rot90_x): Likewise.
2843 (vhsubq_x): Likewise.
2844 (vmaxq_x): Likewise.
2845 (vminq_x): Likewise.
2846 (vmovlbq_x): Likewise.
2847 (vmovltq_x): Likewise.
2848 (vmulhq_x): Likewise.
2849 (vmullbq_int_x): Likewise.
2850 (vmullbq_poly_x): Likewise.
2851 (vmulltq_int_x): Likewise.
2852 (vmulltq_poly_x): Likewise.
2853 (vmvnq_x): Likewise.
2854 (vrev16q_x): Likewise.
2855 (vrhaddq_x): Likewise.
2856 (vrmulhq_x): Likewise.
2857 (vrshlq_x): Likewise.
2858 (vrshrq_x): Likewise.
2859 (vshllbq_x): Likewise.
2860 (vshlltq_x): Likewise.
2861 (vshlq_x_n): Likewise.
2862 (vshlq_x): Likewise.
2863 (vdwdupq_x_u8): Likewise.
2864 (vdwdupq_x_u16): Likewise.
2865 (vdwdupq_x_u32): Likewise.
2866 (viwdupq_x_u8): Likewise.
2867 (viwdupq_x_u16): Likewise.
2868 (viwdupq_x_u32): Likewise.
2869 (vidupq_x_u8): Likewise.
2870 (vddupq_x_u8): Likewise.
2871 (vidupq_x_u16): Likewise.
2872 (vddupq_x_u16): Likewise.
2873 (vidupq_x_u32): Likewise.
2874 (vddupq_x_u32): Likewise.
2875 (vshrq_x): Likewise.
2877 2020-03-20 Richard Biener <rguenther@suse.de>
2879 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
2880 to vectorize for CTOR defs.
2882 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2883 Andre Vieira <andre.simoesdiasvieira@arm.com>
2884 Mihail Ionescu <mihail.ionescu@arm.com>
2886 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin
2887 qualifier.
2888 (LDRGBWBU_QUALIFIERS): Likewise.
2889 (LDRGBWBS_Z_QUALIFIERS): Likewise.
2890 (LDRGBWBU_Z_QUALIFIERS): Likewise.
2891 (STRSBWBS_QUALIFIERS): Likewise.
2892 (STRSBWBU_QUALIFIERS): Likewise.
2893 (STRSBWBS_P_QUALIFIERS): Likewise.
2894 (STRSBWBU_P_QUALIFIERS): Likewise.
2895 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro.
2896 (vldrdq_gather_base_wb_u64): Likewise.
2897 (vldrdq_gather_base_wb_z_s64): Likewise.
2898 (vldrdq_gather_base_wb_z_u64): Likewise.
2899 (vldrwq_gather_base_wb_f32): Likewise.
2900 (vldrwq_gather_base_wb_s32): Likewise.
2901 (vldrwq_gather_base_wb_u32): Likewise.
2902 (vldrwq_gather_base_wb_z_f32): Likewise.
2903 (vldrwq_gather_base_wb_z_s32): Likewise.
2904 (vldrwq_gather_base_wb_z_u32): Likewise.
2905 (vstrdq_scatter_base_wb_p_s64): Likewise.
2906 (vstrdq_scatter_base_wb_p_u64): Likewise.
2907 (vstrdq_scatter_base_wb_s64): Likewise.
2908 (vstrdq_scatter_base_wb_u64): Likewise.
2909 (vstrwq_scatter_base_wb_p_s32): Likewise.
2910 (vstrwq_scatter_base_wb_p_f32): Likewise.
2911 (vstrwq_scatter_base_wb_p_u32): Likewise.
2912 (vstrwq_scatter_base_wb_s32): Likewise.
2913 (vstrwq_scatter_base_wb_u32): Likewise.
2914 (vstrwq_scatter_base_wb_f32): Likewise.
2915 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic.
2916 (__arm_vldrdq_gather_base_wb_u64): Likewise.
2917 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
2918 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
2919 (__arm_vldrwq_gather_base_wb_s32): Likewise.
2920 (__arm_vldrwq_gather_base_wb_u32): Likewise.
2921 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
2922 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
2923 (__arm_vstrdq_scatter_base_wb_s64): Likewise.
2924 (__arm_vstrdq_scatter_base_wb_u64): Likewise.
2925 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
2926 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
2927 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
2928 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
2929 (__arm_vstrwq_scatter_base_wb_s32): Likewise.
2930 (__arm_vstrwq_scatter_base_wb_u32): Likewise.
2931 (__arm_vldrwq_gather_base_wb_f32): Likewise.
2932 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
2933 (__arm_vstrwq_scatter_base_wb_f32): Likewise.
2934 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
2935 (vstrwq_scatter_base_wb): Define polymorphic variant.
2936 (vstrwq_scatter_base_wb_p): Likewise.
2937 (vstrdq_scatter_base_wb_p): Likewise.
2938 (vstrdq_scatter_base_wb): Likewise.
2939 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin
2940 qualifier.
2941 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL
2942 pattern.
2943 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
2944 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise.
2945 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
2946 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
2947 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise.
2948 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
2949 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
2950 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise.
2951 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
2952 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
2953 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise.
2954 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
2955 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
2956 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise.
2957 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
2958 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
2959 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise.
2960 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise.
2961 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
2962 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise.
2963 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
2964 (mve_vldrwq_gather_base_wb_fv4sf): Likewise.
2965 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
2966 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise.
2967 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
2968 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise.
2969 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
2970 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise.
2971 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
2973 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2974 Andre Vieira <andre.simoesdiasvieira@arm.com>
2975 Mihail Ionescu <mihail.ionescu@arm.com>
2977 * config/arm/arm-builtins.c
2978 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary
2979 builtin qualifier.
2980 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro.
2981 (vddupq_m_n_u32): Likewise.
2982 (vddupq_m_n_u16): Likewise.
2983 (vddupq_m_wb_u8): Likewise.
2984 (vddupq_m_wb_u16): Likewise.
2985 (vddupq_m_wb_u32): Likewise.
2986 (vddupq_n_u8): Likewise.
2987 (vddupq_n_u32): Likewise.
2988 (vddupq_n_u16): Likewise.
2989 (vddupq_wb_u8): Likewise.
2990 (vddupq_wb_u16): Likewise.
2991 (vddupq_wb_u32): Likewise.
2992 (vdwdupq_m_n_u8): Likewise.
2993 (vdwdupq_m_n_u32): Likewise.
2994 (vdwdupq_m_n_u16): Likewise.
2995 (vdwdupq_m_wb_u8): Likewise.
2996 (vdwdupq_m_wb_u32): Likewise.
2997 (vdwdupq_m_wb_u16): Likewise.
2998 (vdwdupq_n_u8): Likewise.
2999 (vdwdupq_n_u32): Likewise.
3000 (vdwdupq_n_u16): Likewise.
3001 (vdwdupq_wb_u8): Likewise.
3002 (vdwdupq_wb_u32): Likewise.
3003 (vdwdupq_wb_u16): Likewise.
3004 (vidupq_m_n_u8): Likewise.
3005 (vidupq_m_n_u32): Likewise.
3006 (vidupq_m_n_u16): Likewise.
3007 (vidupq_m_wb_u8): Likewise.
3008 (vidupq_m_wb_u16): Likewise.
3009 (vidupq_m_wb_u32): Likewise.
3010 (vidupq_n_u8): Likewise.
3011 (vidupq_n_u32): Likewise.
3012 (vidupq_n_u16): Likewise.
3013 (vidupq_wb_u8): Likewise.
3014 (vidupq_wb_u16): Likewise.
3015 (vidupq_wb_u32): Likewise.
3016 (viwdupq_m_n_u8): Likewise.
3017 (viwdupq_m_n_u32): Likewise.
3018 (viwdupq_m_n_u16): Likewise.
3019 (viwdupq_m_wb_u8): Likewise.
3020 (viwdupq_m_wb_u32): Likewise.
3021 (viwdupq_m_wb_u16): Likewise.
3022 (viwdupq_n_u8): Likewise.
3023 (viwdupq_n_u32): Likewise.
3024 (viwdupq_n_u16): Likewise.
3025 (viwdupq_wb_u8): Likewise.
3026 (viwdupq_wb_u32): Likewise.
3027 (viwdupq_wb_u16): Likewise.
3028 (__arm_vddupq_m_n_u8): Define intrinsic.
3029 (__arm_vddupq_m_n_u32): Likewise.
3030 (__arm_vddupq_m_n_u16): Likewise.
3031 (__arm_vddupq_m_wb_u8): Likewise.
3032 (__arm_vddupq_m_wb_u16): Likewise.
3033 (__arm_vddupq_m_wb_u32): Likewise.
3034 (__arm_vddupq_n_u8): Likewise.
3035 (__arm_vddupq_n_u32): Likewise.
3036 (__arm_vddupq_n_u16): Likewise.
3037 (__arm_vdwdupq_m_n_u8): Likewise.
3038 (__arm_vdwdupq_m_n_u32): Likewise.
3039 (__arm_vdwdupq_m_n_u16): Likewise.
3040 (__arm_vdwdupq_m_wb_u8): Likewise.
3041 (__arm_vdwdupq_m_wb_u32): Likewise.
3042 (__arm_vdwdupq_m_wb_u16): Likewise.
3043 (__arm_vdwdupq_n_u8): Likewise.
3044 (__arm_vdwdupq_n_u32): Likewise.
3045 (__arm_vdwdupq_n_u16): Likewise.
3046 (__arm_vdwdupq_wb_u8): Likewise.
3047 (__arm_vdwdupq_wb_u32): Likewise.
3048 (__arm_vdwdupq_wb_u16): Likewise.
3049 (__arm_vidupq_m_n_u8): Likewise.
3050 (__arm_vidupq_m_n_u32): Likewise.
3051 (__arm_vidupq_m_n_u16): Likewise.
3052 (__arm_vidupq_n_u8): Likewise.
3053 (__arm_vidupq_m_wb_u8): Likewise.
3054 (__arm_vidupq_m_wb_u16): Likewise.
3055 (__arm_vidupq_m_wb_u32): Likewise.
3056 (__arm_vidupq_n_u32): Likewise.
3057 (__arm_vidupq_n_u16): Likewise.
3058 (__arm_vidupq_wb_u8): Likewise.
3059 (__arm_vidupq_wb_u16): Likewise.
3060 (__arm_vidupq_wb_u32): Likewise.
3061 (__arm_vddupq_wb_u8): Likewise.
3062 (__arm_vddupq_wb_u16): Likewise.
3063 (__arm_vddupq_wb_u32): Likewise.
3064 (__arm_viwdupq_m_n_u8): Likewise.
3065 (__arm_viwdupq_m_n_u32): Likewise.
3066 (__arm_viwdupq_m_n_u16): Likewise.
3067 (__arm_viwdupq_m_wb_u8): Likewise.
3068 (__arm_viwdupq_m_wb_u32): Likewise.
3069 (__arm_viwdupq_m_wb_u16): Likewise.
3070 (__arm_viwdupq_n_u8): Likewise.
3071 (__arm_viwdupq_n_u32): Likewise.
3072 (__arm_viwdupq_n_u16): Likewise.
3073 (__arm_viwdupq_wb_u8): Likewise.
3074 (__arm_viwdupq_wb_u32): Likewise.
3075 (__arm_viwdupq_wb_u16): Likewise.
3076 (vidupq_m): Define polymorphic variant.
3077 (vddupq_m): Likewise.
3078 (vidupq_u16): Likewise.
3079 (vidupq_u32): Likewise.
3080 (vidupq_u8): Likewise.
3081 (vddupq_u16): Likewise.
3082 (vddupq_u32): Likewise.
3083 (vddupq_u8): Likewise.
3084 (viwdupq_m): Likewise.
3085 (viwdupq_u16): Likewise.
3086 (viwdupq_u32): Likewise.
3087 (viwdupq_u8): Likewise.
3088 (vdwdupq_m): Likewise.
3089 (vdwdupq_u16): Likewise.
3090 (vdwdupq_u32): Likewise.
3091 (vdwdupq_u8): Likewise.
3092 * config/arm/arm_mve_builtins.def
3093 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin
3094 qualifier.
3095 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern.
3096 (mve_vidupq_u<mode>_insn): Likewise.
3097 (mve_vidupq_m_n_u<mode>): Likewise.
3098 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
3099 (mve_vddupq_n_u<mode>): Likewise.
3100 (mve_vddupq_u<mode>_insn): Likewise.
3101 (mve_vddupq_m_n_u<mode>): Likewise.
3102 (mve_vddupq_m_wb_u<mode>_insn): Likewise.
3103 (mve_vdwdupq_n_u<mode>): Likewise.
3104 (mve_vdwdupq_wb_u<mode>): Likewise.
3105 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
3106 (mve_vdwdupq_m_n_u<mode>): Likewise.
3107 (mve_vdwdupq_m_wb_u<mode>): Likewise.
3108 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
3109 (mve_viwdupq_n_u<mode>): Likewise.
3110 (mve_viwdupq_wb_u<mode>): Likewise.
3111 (mve_viwdupq_wb_u<mode>_insn): Likewise.
3112 (mve_viwdupq_m_n_u<mode>): Likewise.
3113 (mve_viwdupq_m_wb_u<mode>): Likewise.
3114 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
3116 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3118 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro.
3119 (vreinterpretq_s16_s64): Likewise.
3120 (vreinterpretq_s16_s8): Likewise.
3121 (vreinterpretq_s16_u16): Likewise.
3122 (vreinterpretq_s16_u32): Likewise.
3123 (vreinterpretq_s16_u64): Likewise.
3124 (vreinterpretq_s16_u8): Likewise.
3125 (vreinterpretq_s32_s16): Likewise.
3126 (vreinterpretq_s32_s64): Likewise.
3127 (vreinterpretq_s32_s8): Likewise.
3128 (vreinterpretq_s32_u16): Likewise.
3129 (vreinterpretq_s32_u32): Likewise.
3130 (vreinterpretq_s32_u64): Likewise.
3131 (vreinterpretq_s32_u8): Likewise.
3132 (vreinterpretq_s64_s16): Likewise.
3133 (vreinterpretq_s64_s32): Likewise.
3134 (vreinterpretq_s64_s8): Likewise.
3135 (vreinterpretq_s64_u16): Likewise.
3136 (vreinterpretq_s64_u32): Likewise.
3137 (vreinterpretq_s64_u64): Likewise.
3138 (vreinterpretq_s64_u8): Likewise.
3139 (vreinterpretq_s8_s16): Likewise.
3140 (vreinterpretq_s8_s32): Likewise.
3141 (vreinterpretq_s8_s64): Likewise.
3142 (vreinterpretq_s8_u16): Likewise.
3143 (vreinterpretq_s8_u32): Likewise.
3144 (vreinterpretq_s8_u64): Likewise.
3145 (vreinterpretq_s8_u8): Likewise.
3146 (vreinterpretq_u16_s16): Likewise.
3147 (vreinterpretq_u16_s32): Likewise.
3148 (vreinterpretq_u16_s64): Likewise.
3149 (vreinterpretq_u16_s8): Likewise.
3150 (vreinterpretq_u16_u32): Likewise.
3151 (vreinterpretq_u16_u64): Likewise.
3152 (vreinterpretq_u16_u8): Likewise.
3153 (vreinterpretq_u32_s16): Likewise.
3154 (vreinterpretq_u32_s32): Likewise.
3155 (vreinterpretq_u32_s64): Likewise.
3156 (vreinterpretq_u32_s8): Likewise.
3157 (vreinterpretq_u32_u16): Likewise.
3158 (vreinterpretq_u32_u64): Likewise.
3159 (vreinterpretq_u32_u8): Likewise.
3160 (vreinterpretq_u64_s16): Likewise.
3161 (vreinterpretq_u64_s32): Likewise.
3162 (vreinterpretq_u64_s64): Likewise.
3163 (vreinterpretq_u64_s8): Likewise.
3164 (vreinterpretq_u64_u16): Likewise.
3165 (vreinterpretq_u64_u32): Likewise.
3166 (vreinterpretq_u64_u8): Likewise.
3167 (vreinterpretq_u8_s16): Likewise.
3168 (vreinterpretq_u8_s32): Likewise.
3169 (vreinterpretq_u8_s64): Likewise.
3170 (vreinterpretq_u8_s8): Likewise.
3171 (vreinterpretq_u8_u16): Likewise.
3172 (vreinterpretq_u8_u32): Likewise.
3173 (vreinterpretq_u8_u64): Likewise.
3174 (vreinterpretq_s32_f16): Likewise.
3175 (vreinterpretq_s32_f32): Likewise.
3176 (vreinterpretq_u16_f16): Likewise.
3177 (vreinterpretq_u16_f32): Likewise.
3178 (vreinterpretq_u32_f16): Likewise.
3179 (vreinterpretq_u32_f32): Likewise.
3180 (vreinterpretq_u64_f16): Likewise.
3181 (vreinterpretq_u64_f32): Likewise.
3182 (vreinterpretq_u8_f16): Likewise.
3183 (vreinterpretq_u8_f32): Likewise.
3184 (vreinterpretq_f16_f32): Likewise.
3185 (vreinterpretq_f16_s16): Likewise.
3186 (vreinterpretq_f16_s32): Likewise.
3187 (vreinterpretq_f16_s64): Likewise.
3188 (vreinterpretq_f16_s8): Likewise.
3189 (vreinterpretq_f16_u16): Likewise.
3190 (vreinterpretq_f16_u32): Likewise.
3191 (vreinterpretq_f16_u64): Likewise.
3192 (vreinterpretq_f16_u8): Likewise.
3193 (vreinterpretq_f32_f16): Likewise.
3194 (vreinterpretq_f32_s16): Likewise.
3195 (vreinterpretq_f32_s32): Likewise.
3196 (vreinterpretq_f32_s64): Likewise.
3197 (vreinterpretq_f32_s8): Likewise.
3198 (vreinterpretq_f32_u16): Likewise.
3199 (vreinterpretq_f32_u32): Likewise.
3200 (vreinterpretq_f32_u64): Likewise.
3201 (vreinterpretq_f32_u8): Likewise.
3202 (vreinterpretq_s16_f16): Likewise.
3203 (vreinterpretq_s16_f32): Likewise.
3204 (vreinterpretq_s64_f16): Likewise.
3205 (vreinterpretq_s64_f32): Likewise.
3206 (vreinterpretq_s8_f16): Likewise.
3207 (vreinterpretq_s8_f32): Likewise.
3208 (vuninitializedq_u8): Likewise.
3209 (vuninitializedq_u16): Likewise.
3210 (vuninitializedq_u32): Likewise.
3211 (vuninitializedq_u64): Likewise.
3212 (vuninitializedq_s8): Likewise.
3213 (vuninitializedq_s16): Likewise.
3214 (vuninitializedq_s32): Likewise.
3215 (vuninitializedq_s64): Likewise.
3216 (vuninitializedq_f16): Likewise.
3217 (vuninitializedq_f32): Likewise.
3218 (__arm_vuninitializedq_u8): Define intrinsic.
3219 (__arm_vuninitializedq_u16): Likewise.
3220 (__arm_vuninitializedq_u32): Likewise.
3221 (__arm_vuninitializedq_u64): Likewise.
3222 (__arm_vuninitializedq_s8): Likewise.
3223 (__arm_vuninitializedq_s16): Likewise.
3224 (__arm_vuninitializedq_s32): Likewise.
3225 (__arm_vuninitializedq_s64): Likewise.
3226 (__arm_vreinterpretq_s16_s32): Likewise.
3227 (__arm_vreinterpretq_s16_s64): Likewise.
3228 (__arm_vreinterpretq_s16_s8): Likewise.
3229 (__arm_vreinterpretq_s16_u16): Likewise.
3230 (__arm_vreinterpretq_s16_u32): Likewise.
3231 (__arm_vreinterpretq_s16_u64): Likewise.
3232 (__arm_vreinterpretq_s16_u8): Likewise.
3233 (__arm_vreinterpretq_s32_s16): Likewise.
3234 (__arm_vreinterpretq_s32_s64): Likewise.
3235 (__arm_vreinterpretq_s32_s8): Likewise.
3236 (__arm_vreinterpretq_s32_u16): Likewise.
3237 (__arm_vreinterpretq_s32_u32): Likewise.
3238 (__arm_vreinterpretq_s32_u64): Likewise.
3239 (__arm_vreinterpretq_s32_u8): Likewise.
3240 (__arm_vreinterpretq_s64_s16): Likewise.
3241 (__arm_vreinterpretq_s64_s32): Likewise.
3242 (__arm_vreinterpretq_s64_s8): Likewise.
3243 (__arm_vreinterpretq_s64_u16): Likewise.
3244 (__arm_vreinterpretq_s64_u32): Likewise.
3245 (__arm_vreinterpretq_s64_u64): Likewise.
3246 (__arm_vreinterpretq_s64_u8): Likewise.
3247 (__arm_vreinterpretq_s8_s16): Likewise.
3248 (__arm_vreinterpretq_s8_s32): Likewise.
3249 (__arm_vreinterpretq_s8_s64): Likewise.
3250 (__arm_vreinterpretq_s8_u16): Likewise.
3251 (__arm_vreinterpretq_s8_u32): Likewise.
3252 (__arm_vreinterpretq_s8_u64): Likewise.
3253 (__arm_vreinterpretq_s8_u8): Likewise.
3254 (__arm_vreinterpretq_u16_s16): Likewise.
3255 (__arm_vreinterpretq_u16_s32): Likewise.
3256 (__arm_vreinterpretq_u16_s64): Likewise.
3257 (__arm_vreinterpretq_u16_s8): Likewise.
3258 (__arm_vreinterpretq_u16_u32): Likewise.
3259 (__arm_vreinterpretq_u16_u64): Likewise.
3260 (__arm_vreinterpretq_u16_u8): Likewise.
3261 (__arm_vreinterpretq_u32_s16): Likewise.
3262 (__arm_vreinterpretq_u32_s32): Likewise.
3263 (__arm_vreinterpretq_u32_s64): Likewise.
3264 (__arm_vreinterpretq_u32_s8): Likewise.
3265 (__arm_vreinterpretq_u32_u16): Likewise.
3266 (__arm_vreinterpretq_u32_u64): Likewise.
3267 (__arm_vreinterpretq_u32_u8): Likewise.
3268 (__arm_vreinterpretq_u64_s16): Likewise.
3269 (__arm_vreinterpretq_u64_s32): Likewise.
3270 (__arm_vreinterpretq_u64_s64): Likewise.
3271 (__arm_vreinterpretq_u64_s8): Likewise.
3272 (__arm_vreinterpretq_u64_u16): Likewise.
3273 (__arm_vreinterpretq_u64_u32): Likewise.
3274 (__arm_vreinterpretq_u64_u8): Likewise.
3275 (__arm_vreinterpretq_u8_s16): Likewise.
3276 (__arm_vreinterpretq_u8_s32): Likewise.
3277 (__arm_vreinterpretq_u8_s64): Likewise.
3278 (__arm_vreinterpretq_u8_s8): Likewise.
3279 (__arm_vreinterpretq_u8_u16): Likewise.
3280 (__arm_vreinterpretq_u8_u32): Likewise.
3281 (__arm_vreinterpretq_u8_u64): Likewise.
3282 (__arm_vuninitializedq_f16): Likewise.
3283 (__arm_vuninitializedq_f32): Likewise.
3284 (__arm_vreinterpretq_s32_f16): Likewise.
3285 (__arm_vreinterpretq_s32_f32): Likewise.
3286 (__arm_vreinterpretq_s16_f16): Likewise.
3287 (__arm_vreinterpretq_s16_f32): Likewise.
3288 (__arm_vreinterpretq_s64_f16): Likewise.
3289 (__arm_vreinterpretq_s64_f32): Likewise.
3290 (__arm_vreinterpretq_s8_f16): Likewise.
3291 (__arm_vreinterpretq_s8_f32): Likewise.
3292 (__arm_vreinterpretq_u16_f16): Likewise.
3293 (__arm_vreinterpretq_u16_f32): Likewise.
3294 (__arm_vreinterpretq_u32_f16): Likewise.
3295 (__arm_vreinterpretq_u32_f32): Likewise.
3296 (__arm_vreinterpretq_u64_f16): Likewise.
3297 (__arm_vreinterpretq_u64_f32): Likewise.
3298 (__arm_vreinterpretq_u8_f16): Likewise.
3299 (__arm_vreinterpretq_u8_f32): Likewise.
3300 (__arm_vreinterpretq_f16_f32): Likewise.
3301 (__arm_vreinterpretq_f16_s16): Likewise.
3302 (__arm_vreinterpretq_f16_s32): Likewise.
3303 (__arm_vreinterpretq_f16_s64): Likewise.
3304 (__arm_vreinterpretq_f16_s8): Likewise.
3305 (__arm_vreinterpretq_f16_u16): Likewise.
3306 (__arm_vreinterpretq_f16_u32): Likewise.
3307 (__arm_vreinterpretq_f16_u64): Likewise.
3308 (__arm_vreinterpretq_f16_u8): Likewise.
3309 (__arm_vreinterpretq_f32_f16): Likewise.
3310 (__arm_vreinterpretq_f32_s16): Likewise.
3311 (__arm_vreinterpretq_f32_s32): Likewise.
3312 (__arm_vreinterpretq_f32_s64): Likewise.
3313 (__arm_vreinterpretq_f32_s8): Likewise.
3314 (__arm_vreinterpretq_f32_u16): Likewise.
3315 (__arm_vreinterpretq_f32_u32): Likewise.
3316 (__arm_vreinterpretq_f32_u64): Likewise.
3317 (__arm_vreinterpretq_f32_u8): Likewise.
3318 (vuninitializedq): Define polymorphic variant.
3319 (vreinterpretq_f16): Likewise.
3320 (vreinterpretq_f32): Likewise.
3321 (vreinterpretq_s16): Likewise.
3322 (vreinterpretq_s32): Likewise.
3323 (vreinterpretq_s64): Likewise.
3324 (vreinterpretq_s8): Likewise.
3325 (vreinterpretq_u16): Likewise.
3326 (vreinterpretq_u32): Likewise.
3327 (vreinterpretq_u64): Likewise.
3328 (vreinterpretq_u8): Likewise.
3330 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3331 Andre Vieira <andre.simoesdiasvieira@arm.com>
3332 Mihail Ionescu <mihail.ionescu@arm.com>
3334 * config/arm/arm_mve.h (vaddq_s8): Define macro.
3335 (vaddq_s16): Likewise.
3336 (vaddq_s32): Likewise.
3337 (vaddq_u8): Likewise.
3338 (vaddq_u16): Likewise.
3339 (vaddq_u32): Likewise.
3340 (vaddq_f16): Likewise.
3341 (vaddq_f32): Likewise.
3342 (__arm_vaddq_s8): Define intrinsic.
3343 (__arm_vaddq_s16): Likewise.
3344 (__arm_vaddq_s32): Likewise.
3345 (__arm_vaddq_u8): Likewise.
3346 (__arm_vaddq_u16): Likewise.
3347 (__arm_vaddq_u32): Likewise.
3348 (__arm_vaddq_f16): Likewise.
3349 (__arm_vaddq_f32): Likewise.
3350 (vaddq): Define polymorphic variant.
3351 * config/arm/iterators.md (VNIM): Define mode iterator for common types
3352 Neon, IWMMXT and MVE.
3353 (VNINOTM): Likewise.
3354 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
3355 (mve_vaddq_f<mode>): Define RTL pattern.
3356 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
3357 (addv8hf3_neon): Define RTL pattern.
3358 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
3359 to support MVE.
3360 (addv8hf3): Define standard RTL pattern for MVE and Neon.
3361 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.
3363 2020-03-20 Martin Liska <mliska@suse.cz>
3365 PR ipa/94232
3366 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously
3367 build_ref_for_offset function was used and it transforms off to bytes
3368 from bits.
3370 2020-03-20 Richard Biener <rguenther@suse.de>
3372 PR tree-optimization/94266
3373 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the
3374 type of the underlying object to adjust for the containing
3375 field if available.
3377 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
3379 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
3380 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
3381 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
3383 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
3385 * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
3387 2020-03-20 Jakub Jelinek <jakub@redhat.com>
3389 PR tree-optimization/94224
3390 * gimple-ssa-store-merging.c
3391 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping
3392 or adjacent INTEGER_CST rhs_code stores as mergeable if they have
3393 different lp_nr.
3395 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
3397 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve.
3399 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
3401 PR ipa/94202
3402 * cgraph.c (cgraph_node::function_symbol): Fix availability computation.
3403 (cgraph_node::function_or_virtual_thunk_symbol): Likewise.
3405 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
3407 PR ipa/92372
3408 * cgraphunit.c (process_function_and_variable_attributes): warn
3409 for flatten attribute on alias.
3410 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias.
3412 2020-03-19 Martin Liska <mliska@suse.cz>
3414 * lto-section-in.c: Add ext_symtab.
3415 * lto-streamer-out.c (write_symbol_extension_info): New.
3416 (produce_symtab_extension): New.
3417 (produce_asm_for_decls): Stream also produce_symtab_extension.
3418 * lto-streamer.h (enum lto_section_type): New section.
3420 2020-03-19 Jakub Jelinek <jakub@redhat.com>
3422 PR tree-optimization/94211
3423 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
3424 instead of estimate_num_insns for bb_seq (middle_bb). Rename
3425 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
3426 all uses.
3428 2020-03-19 Richard Biener <rguenther@suse.de>
3430 PR ipa/94217
3431 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr
3432 and build_ref_for_offset.
3434 2020-03-19 Richard Biener <rguenther@suse.de>
3436 PR middle-end/94216
3437 * fold-const.c (fold_binary_loc): Avoid using
3438 build_fold_addr_expr when we really want an ADDR_EXPR.
3440 2020-03-18 Segher Boessenkool <segher@kernel.crashing.org>
3442 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented
3443 aliases for "wa".
3445 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
3447 PR rtl-optimization/90275
3448 * cse.c (cse_insn): Delete no-op register moves too.
3450 2020-03-18 Martin Sebor <msebor@redhat.com>
3452 PR ipa/92799
3453 * cgraphunit.c (process_function_and_variable_attributes): Also
3454 complain about weakref function definitions and drop all effects
3455 of the attribute.
3457 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
3458 Mihail Ionescu <mihail.ionescu@arm.com>
3459 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3461 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
3462 (vstrdq_scatter_base_p_u64): Likewise.
3463 (vstrdq_scatter_base_s64): Likewise.
3464 (vstrdq_scatter_base_u64): Likewise.
3465 (vstrdq_scatter_offset_p_s64): Likewise.
3466 (vstrdq_scatter_offset_p_u64): Likewise.
3467 (vstrdq_scatter_offset_s64): Likewise.
3468 (vstrdq_scatter_offset_u64): Likewise.
3469 (vstrdq_scatter_shifted_offset_p_s64): Likewise.
3470 (vstrdq_scatter_shifted_offset_p_u64): Likewise.
3471 (vstrdq_scatter_shifted_offset_s64): Likewise.
3472 (vstrdq_scatter_shifted_offset_u64): Likewise.
3473 (vstrhq_scatter_offset_f16): Likewise.
3474 (vstrhq_scatter_offset_p_f16): Likewise.
3475 (vstrhq_scatter_shifted_offset_f16): Likewise.
3476 (vstrhq_scatter_shifted_offset_p_f16): Likewise.
3477 (vstrwq_scatter_base_f32): Likewise.
3478 (vstrwq_scatter_base_p_f32): Likewise.
3479 (vstrwq_scatter_offset_f32): Likewise.
3480 (vstrwq_scatter_offset_p_f32): Likewise.
3481 (vstrwq_scatter_offset_p_s32): Likewise.
3482 (vstrwq_scatter_offset_p_u32): Likewise.
3483 (vstrwq_scatter_offset_s32): Likewise.
3484 (vstrwq_scatter_offset_u32): Likewise.
3485 (vstrwq_scatter_shifted_offset_f32): Likewise.
3486 (vstrwq_scatter_shifted_offset_p_f32): Likewise.
3487 (vstrwq_scatter_shifted_offset_p_s32): Likewise.
3488 (vstrwq_scatter_shifted_offset_p_u32): Likewise.
3489 (vstrwq_scatter_shifted_offset_s32): Likewise.
3490 (vstrwq_scatter_shifted_offset_u32): Likewise.
3491 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
3492 (__arm_vstrdq_scatter_base_p_u64): Likewise.
3493 (__arm_vstrdq_scatter_base_s64): Likewise.
3494 (__arm_vstrdq_scatter_base_u64): Likewise.
3495 (__arm_vstrdq_scatter_offset_p_s64): Likewise.
3496 (__arm_vstrdq_scatter_offset_p_u64): Likewise.
3497 (__arm_vstrdq_scatter_offset_s64): Likewise.
3498 (__arm_vstrdq_scatter_offset_u64): Likewise.
3499 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
3500 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
3501 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
3502 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
3503 (__arm_vstrwq_scatter_offset_p_s32): Likewise.
3504 (__arm_vstrwq_scatter_offset_p_u32): Likewise.
3505 (__arm_vstrwq_scatter_offset_s32): Likewise.
3506 (__arm_vstrwq_scatter_offset_u32): Likewise.
3507 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
3508 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
3509 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
3510 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
3511 (__arm_vstrhq_scatter_offset_f16): Likewise.
3512 (__arm_vstrhq_scatter_offset_p_f16): Likewise.
3513 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
3514 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
3515 (__arm_vstrwq_scatter_base_f32): Likewise.
3516 (__arm_vstrwq_scatter_base_p_f32): Likewise.
3517 (__arm_vstrwq_scatter_offset_f32): Likewise.
3518 (__arm_vstrwq_scatter_offset_p_f32): Likewise.
3519 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
3520 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
3521 (vstrhq_scatter_offset): Define polymorphic variant.
3522 (vstrhq_scatter_offset_p): Likewise.
3523 (vstrhq_scatter_shifted_offset): Likewise.
3524 (vstrhq_scatter_shifted_offset_p): Likewise.
3525 (vstrwq_scatter_base): Likewise.
3526 (vstrwq_scatter_base_p): Likewise.
3527 (vstrwq_scatter_offset): Likewise.
3528 (vstrwq_scatter_offset_p): Likewise.
3529 (vstrwq_scatter_shifted_offset): Likewise.
3530 (vstrwq_scatter_shifted_offset_p): Likewise.
3531 (vstrdq_scatter_base_p): Likewise.
3532 (vstrdq_scatter_base): Likewise.
3533 (vstrdq_scatter_offset_p): Likewise.
3534 (vstrdq_scatter_offset): Likewise.
3535 (vstrdq_scatter_shifted_offset_p): Likewise.
3536 (vstrdq_scatter_shifted_offset): Likewise.
3537 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
3538 (STRSBS_P): Likewise.
3539 (STRSBU): Likewise.
3540 (STRSBU_P): Likewise.
3541 (STRSS): Likewise.
3542 (STRSS_P): Likewise.
3543 (STRSU): Likewise.
3544 (STRSU_P): Likewise.
3545 * config/arm/constraints.md (Ri): Define.
3546 * config/arm/mve.md (VSTRDSBQ): Define iterator.
3547 (VSTRDSOQ): Likewise.
3548 (VSTRDSSOQ): Likewise.
3549 (VSTRWSOQ): Likewise.
3550 (VSTRWSSOQ): Likewise.
3551 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
3552 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
3553 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
3554 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
3555 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
3556 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
3557 (mve_vstrhq_scatter_offset_fv8hf): Likewise.
3558 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
3559 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
3560 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
3561 (mve_vstrwq_scatter_base_fv4sf): Likewise.
3562 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
3563 (mve_vstrwq_scatter_offset_fv4sf): Likewise.
3564 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
3565 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
3566 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
3567 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
3568 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
3569 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
3570 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
3571 * config/arm/predicates.md (Ri): Define predicate to check immediate
3572 is the range +/-1016 and multiple of 8.
3574 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
3575 Mihail Ionescu <mihail.ionescu@arm.com>
3576 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3578 * config/arm/arm_mve.h (vst1q_f32): Define macro.
3579 (vst1q_f16): Likewise.
3580 (vst1q_s8): Likewise.
3581 (vst1q_s32): Likewise.
3582 (vst1q_s16): Likewise.
3583 (vst1q_u8): Likewise.
3584 (vst1q_u32): Likewise.
3585 (vst1q_u16): Likewise.
3586 (vstrhq_f16): Likewise.
3587 (vstrhq_scatter_offset_s32): Likewise.
3588 (vstrhq_scatter_offset_s16): Likewise.
3589 (vstrhq_scatter_offset_u32): Likewise.
3590 (vstrhq_scatter_offset_u16): Likewise.
3591 (vstrhq_scatter_offset_p_s32): Likewise.
3592 (vstrhq_scatter_offset_p_s16): Likewise.
3593 (vstrhq_scatter_offset_p_u32): Likewise.
3594 (vstrhq_scatter_offset_p_u16): Likewise.
3595 (vstrhq_scatter_shifted_offset_s32): Likewise.
3596 (vstrhq_scatter_shifted_offset_s16): Likewise.
3597 (vstrhq_scatter_shifted_offset_u32): Likewise.
3598 (vstrhq_scatter_shifted_offset_u16): Likewise.
3599 (vstrhq_scatter_shifted_offset_p_s32): Likewise.
3600 (vstrhq_scatter_shifted_offset_p_s16): Likewise.
3601 (vstrhq_scatter_shifted_offset_p_u32): Likewise.
3602 (vstrhq_scatter_shifted_offset_p_u16): Likewise.
3603 (vstrhq_s32): Likewise.
3604 (vstrhq_s16): Likewise.
3605 (vstrhq_u32): Likewise.
3606 (vstrhq_u16): Likewise.
3607 (vstrhq_p_f16): Likewise.
3608 (vstrhq_p_s32): Likewise.
3609 (vstrhq_p_s16): Likewise.
3610 (vstrhq_p_u32): Likewise.
3611 (vstrhq_p_u16): Likewise.
3612 (vstrwq_f32): Likewise.
3613 (vstrwq_s32): Likewise.
3614 (vstrwq_u32): Likewise.
3615 (vstrwq_p_f32): Likewise.
3616 (vstrwq_p_s32): Likewise.
3617 (vstrwq_p_u32): Likewise.
3618 (__arm_vst1q_s8): Define intrinsic.
3619 (__arm_vst1q_s32): Likewise.
3620 (__arm_vst1q_s16): Likewise.
3621 (__arm_vst1q_u8): Likewise.
3622 (__arm_vst1q_u32): Likewise.
3623 (__arm_vst1q_u16): Likewise.
3624 (__arm_vstrhq_scatter_offset_s32): Likewise.
3625 (__arm_vstrhq_scatter_offset_s16): Likewise.
3626 (__arm_vstrhq_scatter_offset_u32): Likewise.
3627 (__arm_vstrhq_scatter_offset_u16): Likewise.
3628 (__arm_vstrhq_scatter_offset_p_s32): Likewise.
3629 (__arm_vstrhq_scatter_offset_p_s16): Likewise.
3630 (__arm_vstrhq_scatter_offset_p_u32): Likewise.
3631 (__arm_vstrhq_scatter_offset_p_u16): Likewise.
3632 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
3633 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
3634 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
3635 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
3636 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
3637 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
3638 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
3639 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
3640 (__arm_vstrhq_s32): Likewise.
3641 (__arm_vstrhq_s16): Likewise.
3642 (__arm_vstrhq_u32): Likewise.
3643 (__arm_vstrhq_u16): Likewise.
3644 (__arm_vstrhq_p_s32): Likewise.
3645 (__arm_vstrhq_p_s16): Likewise.
3646 (__arm_vstrhq_p_u32): Likewise.
3647 (__arm_vstrhq_p_u16): Likewise.
3648 (__arm_vstrwq_s32): Likewise.
3649 (__arm_vstrwq_u32): Likewise.
3650 (__arm_vstrwq_p_s32): Likewise.
3651 (__arm_vstrwq_p_u32): Likewise.
3652 (__arm_vstrwq_p_f32): Likewise.
3653 (__arm_vstrwq_f32): Likewise.
3654 (__arm_vst1q_f32): Likewise.
3655 (__arm_vst1q_f16): Likewise.
3656 (__arm_vstrhq_f16): Likewise.
3657 (__arm_vstrhq_p_f16): Likewise.
3658 (vst1q): Define polymorphic variant.
3659 (vstrhq): Likewise.
3660 (vstrhq_p): Likewise.
3661 (vstrhq_scatter_offset_p): Likewise.
3662 (vstrhq_scatter_offset): Likewise.
3663 (vstrhq_scatter_shifted_offset_p): Likewise.
3664 (vstrhq_scatter_shifted_offset): Likewise.
3665 (vstrwq_p): Likewise.
3666 (vstrwq): Likewise.
3667 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
3668 (STRS_P): Likewise.
3669 (STRSS): Likewise.
3670 (STRSS_P): Likewise.
3671 (STRSU): Likewise.
3672 (STRSU_P): Likewise.
3673 (STRU): Likewise.
3674 (STRU_P): Likewise.
3675 * config/arm/mve.md (VST1Q): Define iterator.
3676 (VSTRHSOQ): Likewise.
3677 (VSTRHSSOQ): Likewise.
3678 (VSTRHQ): Likewise.
3679 (VSTRWQ): Likewise.
3680 (mve_vstrhq_fv8hf): Define RTL pattern.
3681 (mve_vstrhq_p_fv8hf): Likewise.
3682 (mve_vstrhq_p_<supf><mode>): Likewise.
3683 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
3684 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
3685 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
3686 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
3687 (mve_vstrhq_<supf><mode>): Likewise.
3688 (mve_vstrwq_fv4sf): Likewise.
3689 (mve_vstrwq_p_fv4sf): Likewise.
3690 (mve_vstrwq_p_<supf>v4si): Likewise.
3691 (mve_vstrwq_<supf>v4si): Likewise.
3692 (mve_vst1q_f<mode>): Define expand.
3693 (mve_vst1q_<supf><mode>): Likewise.
3695 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
3696 Mihail Ionescu <mihail.ionescu@arm.com>
3697 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3699 * config/arm/arm_mve.h (vld1q_s8): Define macro.
3700 (vld1q_s32): Likewise.
3701 (vld1q_s16): Likewise.
3702 (vld1q_u8): Likewise.
3703 (vld1q_u32): Likewise.
3704 (vld1q_u16): Likewise.
3705 (vldrhq_gather_offset_s32): Likewise.
3706 (vldrhq_gather_offset_s16): Likewise.
3707 (vldrhq_gather_offset_u32): Likewise.
3708 (vldrhq_gather_offset_u16): Likewise.
3709 (vldrhq_gather_offset_z_s32): Likewise.
3710 (vldrhq_gather_offset_z_s16): Likewise.
3711 (vldrhq_gather_offset_z_u32): Likewise.
3712 (vldrhq_gather_offset_z_u16): Likewise.
3713 (vldrhq_gather_shifted_offset_s32): Likewise.
3714 (vldrhq_gather_shifted_offset_s16): Likewise.
3715 (vldrhq_gather_shifted_offset_u32): Likewise.
3716 (vldrhq_gather_shifted_offset_u16): Likewise.
3717 (vldrhq_gather_shifted_offset_z_s32): Likewise.
3718 (vldrhq_gather_shifted_offset_z_s16): Likewise.
3719 (vldrhq_gather_shifted_offset_z_u32): Likewise.
3720 (vldrhq_gather_shifted_offset_z_u16): Likewise.
3721 (vldrhq_s32): Likewise.
3722 (vldrhq_s16): Likewise.
3723 (vldrhq_u32): Likewise.
3724 (vldrhq_u16): Likewise.
3725 (vldrhq_z_s32): Likewise.
3726 (vldrhq_z_s16): Likewise.
3727 (vldrhq_z_u32): Likewise.
3728 (vldrhq_z_u16): Likewise.
3729 (vldrwq_s32): Likewise.
3730 (vldrwq_u32): Likewise.
3731 (vldrwq_z_s32): Likewise.
3732 (vldrwq_z_u32): Likewise.
3733 (vld1q_f32): Likewise.
3734 (vld1q_f16): Likewise.
3735 (vldrhq_f16): Likewise.
3736 (vldrhq_z_f16): Likewise.
3737 (vldrwq_f32): Likewise.
3738 (vldrwq_z_f32): Likewise.
3739 (__arm_vld1q_s8): Define intrinsic.
3740 (__arm_vld1q_s32): Likewise.
3741 (__arm_vld1q_s16): Likewise.
3742 (__arm_vld1q_u8): Likewise.
3743 (__arm_vld1q_u32): Likewise.
3744 (__arm_vld1q_u16): Likewise.
3745 (__arm_vldrhq_gather_offset_s32): Likewise.
3746 (__arm_vldrhq_gather_offset_s16): Likewise.
3747 (__arm_vldrhq_gather_offset_u32): Likewise.
3748 (__arm_vldrhq_gather_offset_u16): Likewise.
3749 (__arm_vldrhq_gather_offset_z_s32): Likewise.
3750 (__arm_vldrhq_gather_offset_z_s16): Likewise.
3751 (__arm_vldrhq_gather_offset_z_u32): Likewise.
3752 (__arm_vldrhq_gather_offset_z_u16): Likewise.
3753 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
3754 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
3755 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
3756 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
3757 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
3758 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
3759 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
3760 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
3761 (__arm_vldrhq_s32): Likewise.
3762 (__arm_vldrhq_s16): Likewise.
3763 (__arm_vldrhq_u32): Likewise.
3764 (__arm_vldrhq_u16): Likewise.
3765 (__arm_vldrhq_z_s32): Likewise.
3766 (__arm_vldrhq_z_s16): Likewise.
3767 (__arm_vldrhq_z_u32): Likewise.
3768 (__arm_vldrhq_z_u16): Likewise.
3769 (__arm_vldrwq_s32): Likewise.
3770 (__arm_vldrwq_u32): Likewise.
3771 (__arm_vldrwq_z_s32): Likewise.
3772 (__arm_vldrwq_z_u32): Likewise.
3773 (__arm_vld1q_f32): Likewise.
3774 (__arm_vld1q_f16): Likewise.
3775 (__arm_vldrwq_f32): Likewise.
3776 (__arm_vldrwq_z_f32): Likewise.
3777 (__arm_vldrhq_z_f16): Likewise.
3778 (__arm_vldrhq_f16): Likewise.
3779 (vld1q): Define polymorphic variant.
3780 (vldrhq_gather_offset): Likewise.
3781 (vldrhq_gather_offset_z): Likewise.
3782 (vldrhq_gather_shifted_offset): Likewise.
3783 (vldrhq_gather_shifted_offset_z): Likewise.
3784 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
3785 (LDRS): Likewise.
3786 (LDRU_Z): Likewise.
3787 (LDRS_Z): Likewise.
3788 (LDRGU_Z): Likewise.
3789 (LDRGU): Likewise.
3790 (LDRGS_Z): Likewise.
3791 (LDRGS): Likewise.
3792 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
3793 (V_sz_elem1): Likewise.
3794 (VLD1Q): Define iterator.
3795 (VLDRHGOQ): Likewise.
3796 (VLDRHGSOQ): Likewise.
3797 (VLDRHQ): Likewise.
3798 (VLDRWQ): Likewise.
3799 (mve_vldrhq_fv8hf): Define RTL pattern.
3800 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
3801 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
3802 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
3803 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
3804 (mve_vldrhq_<supf><mode>): Likewise.
3805 (mve_vldrhq_z_fv8hf): Likewise.
3806 (mve_vldrhq_z_<supf><mode>): Likewise.
3807 (mve_vldrwq_fv4sf): Likewise.
3808 (mve_vldrwq_<supf>v4si): Likewise.
3809 (mve_vldrwq_z_fv4sf): Likewise.
3810 (mve_vldrwq_z_<supf>v4si): Likewise.
3811 (mve_vld1q_f<mode>): Define RTL expand pattern.
3812 (mve_vld1q_<supf><mode>): Likewise.
3814 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
3815 Mihail Ionescu <mihail.ionescu@arm.com>
3816 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3818 * config/arm/arm_mve.h (vld1q_s8): Define macro.
3819 (vld1q_s32): Likewise.
3820 (vld1q_s16): Likewise.
3821 (vld1q_u8): Likewise.
3822 (vld1q_u32): Likewise.
3823 (vld1q_u16): Likewise.
3824 (vldrhq_gather_offset_s32): Likewise.
3825 (vldrhq_gather_offset_s16): Likewise.
3826 (vldrhq_gather_offset_u32): Likewise.
3827 (vldrhq_gather_offset_u16): Likewise.
3828 (vldrhq_gather_offset_z_s32): Likewise.
3829 (vldrhq_gather_offset_z_s16): Likewise.
3830 (vldrhq_gather_offset_z_u32): Likewise.
3831 (vldrhq_gather_offset_z_u16): Likewise.
3832 (vldrhq_gather_shifted_offset_s32): Likewise.
3833 (vldrhq_gather_shifted_offset_s16): Likewise.
3834 (vldrhq_gather_shifted_offset_u32): Likewise.
3835 (vldrhq_gather_shifted_offset_u16): Likewise.
3836 (vldrhq_gather_shifted_offset_z_s32): Likewise.
3837 (vldrhq_gather_shifted_offset_z_s16): Likewise.
3838 (vldrhq_gather_shifted_offset_z_u32): Likewise.
3839 (vldrhq_gather_shifted_offset_z_u16): Likewise.
3840 (vldrhq_s32): Likewise.
3841 (vldrhq_s16): Likewise.
3842 (vldrhq_u32): Likewise.
3843 (vldrhq_u16): Likewise.
3844 (vldrhq_z_s32): Likewise.
3845 (vldrhq_z_s16): Likewise.
3846 (vldrhq_z_u32): Likewise.
3847 (vldrhq_z_u16): Likewise.
3848 (vldrwq_s32): Likewise.
3849 (vldrwq_u32): Likewise.
3850 (vldrwq_z_s32): Likewise.
3851 (vldrwq_z_u32): Likewise.
3852 (vld1q_f32): Likewise.
3853 (vld1q_f16): Likewise.
3854 (vldrhq_f16): Likewise.
3855 (vldrhq_z_f16): Likewise.
3856 (vldrwq_f32): Likewise.
3857 (vldrwq_z_f32): Likewise.
3858 (__arm_vld1q_s8): Define intrinsic.
3859 (__arm_vld1q_s32): Likewise.
3860 (__arm_vld1q_s16): Likewise.
3861 (__arm_vld1q_u8): Likewise.
3862 (__arm_vld1q_u32): Likewise.
3863 (__arm_vld1q_u16): Likewise.
3864 (__arm_vldrhq_gather_offset_s32): Likewise.
3865 (__arm_vldrhq_gather_offset_s16): Likewise.
3866 (__arm_vldrhq_gather_offset_u32): Likewise.
3867 (__arm_vldrhq_gather_offset_u16): Likewise.
3868 (__arm_vldrhq_gather_offset_z_s32): Likewise.
3869 (__arm_vldrhq_gather_offset_z_s16): Likewise.
3870 (__arm_vldrhq_gather_offset_z_u32): Likewise.
3871 (__arm_vldrhq_gather_offset_z_u16): Likewise.
3872 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
3873 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
3874 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
3875 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
3876 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
3877 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
3878 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
3879 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
3880 (__arm_vldrhq_s32): Likewise.
3881 (__arm_vldrhq_s16): Likewise.
3882 (__arm_vldrhq_u32): Likewise.
3883 (__arm_vldrhq_u16): Likewise.
3884 (__arm_vldrhq_z_s32): Likewise.
3885 (__arm_vldrhq_z_s16): Likewise.
3886 (__arm_vldrhq_z_u32): Likewise.
3887 (__arm_vldrhq_z_u16): Likewise.
3888 (__arm_vldrwq_s32): Likewise.
3889 (__arm_vldrwq_u32): Likewise.
3890 (__arm_vldrwq_z_s32): Likewise.
3891 (__arm_vldrwq_z_u32): Likewise.
3892 (__arm_vld1q_f32): Likewise.
3893 (__arm_vld1q_f16): Likewise.
3894 (__arm_vldrwq_f32): Likewise.
3895 (__arm_vldrwq_z_f32): Likewise.
3896 (__arm_vldrhq_z_f16): Likewise.
3897 (__arm_vldrhq_f16): Likewise.
3898 (vld1q): Define polymorphic variant.
3899 (vldrhq_gather_offset): Likewise.
3900 (vldrhq_gather_offset_z): Likewise.
3901 (vldrhq_gather_shifted_offset): Likewise.
3902 (vldrhq_gather_shifted_offset_z): Likewise.
3903 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
3904 (LDRS): Likewise.
3905 (LDRU_Z): Likewise.
3906 (LDRS_Z): Likewise.
3907 (LDRGU_Z): Likewise.
3908 (LDRGU): Likewise.
3909 (LDRGS_Z): Likewise.
3910 (LDRGS): Likewise.
3911 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
3912 (V_sz_elem1): Likewise.
3913 (VLD1Q): Define iterator.
3914 (VLDRHGOQ): Likewise.
3915 (VLDRHGSOQ): Likewise.
3916 (VLDRHQ): Likewise.
3917 (VLDRWQ): Likewise.
3918 (mve_vldrhq_fv8hf): Define RTL pattern.
3919 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
3920 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
3921 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
3922 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
3923 (mve_vldrhq_<supf><mode>): Likewise.
3924 (mve_vldrhq_z_fv8hf): Likewise.
3925 (mve_vldrhq_z_<supf><mode>): Likewise.
3926 (mve_vldrwq_fv4sf): Likewise.
3927 (mve_vldrwq_<supf>v4si): Likewise.
3928 (mve_vldrwq_z_fv4sf): Likewise.
3929 (mve_vldrwq_z_<supf>v4si): Likewise.
3930 (mve_vld1q_f<mode>): Define RTL expand pattern.
3931 (mve_vld1q_<supf><mode>): Likewise.
3933 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
3934 Mihail Ionescu <mihail.ionescu@arm.com>
3935 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3937 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
3938 qualifier.
3939 (LDRGBU_Z_QUALIFIERS): Likewise.
3940 (LDRGS_Z_QUALIFIERS): Likewise.
3941 (LDRGU_Z_QUALIFIERS): Likewise.
3942 (LDRS_Z_QUALIFIERS): Likewise.
3943 (LDRU_Z_QUALIFIERS): Likewise.
3944 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
3945 (vldrbq_gather_offset_z_u8): Likewise.
3946 (vldrbq_gather_offset_z_s32): Likewise.
3947 (vldrbq_gather_offset_z_u16): Likewise.
3948 (vldrbq_gather_offset_z_u32): Likewise.
3949 (vldrbq_gather_offset_z_s8): Likewise.
3950 (vldrbq_z_s16): Likewise.
3951 (vldrbq_z_u8): Likewise.
3952 (vldrbq_z_s8): Likewise.
3953 (vldrbq_z_s32): Likewise.
3954 (vldrbq_z_u16): Likewise.
3955 (vldrbq_z_u32): Likewise.
3956 (vldrwq_gather_base_z_u32): Likewise.
3957 (vldrwq_gather_base_z_s32): Likewise.
3958 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
3959 (__arm_vldrbq_gather_offset_z_s32): Likewise.
3960 (__arm_vldrbq_gather_offset_z_s16): Likewise.
3961 (__arm_vldrbq_gather_offset_z_u8): Likewise.
3962 (__arm_vldrbq_gather_offset_z_u32): Likewise.
3963 (__arm_vldrbq_gather_offset_z_u16): Likewise.
3964 (__arm_vldrbq_z_s8): Likewise.
3965 (__arm_vldrbq_z_s32): Likewise.
3966 (__arm_vldrbq_z_s16): Likewise.
3967 (__arm_vldrbq_z_u8): Likewise.
3968 (__arm_vldrbq_z_u32): Likewise.
3969 (__arm_vldrbq_z_u16): Likewise.
3970 (__arm_vldrwq_gather_base_z_s32): Likewise.
3971 (__arm_vldrwq_gather_base_z_u32): Likewise.
3972 (vldrbq_gather_offset_z): Define polymorphic variant.
3973 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
3974 qualifier.
3975 (LDRGBU_Z_QUALIFIERS): Likewise.
3976 (LDRGS_Z_QUALIFIERS): Likewise.
3977 (LDRGU_Z_QUALIFIERS): Likewise.
3978 (LDRS_Z_QUALIFIERS): Likewise.
3979 (LDRU_Z_QUALIFIERS): Likewise.
3980 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
3981 RTL pattern.
3982 (mve_vldrbq_z_<supf><mode>): Likewise.
3983 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
3985 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
3986 Mihail Ionescu <mihail.ionescu@arm.com>
3987 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3989 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin
3990 qualifier.
3991 (STRU_P_QUALIFIERS): Likewise.
3992 (STRSU_P_QUALIFIERS): Likewise.
3993 (STRSS_P_QUALIFIERS): Likewise.
3994 (STRSBS_P_QUALIFIERS): Likewise.
3995 (STRSBU_P_QUALIFIERS): Likewise.
3996 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro.
3997 (vstrbq_p_s32): Likewise.
3998 (vstrbq_p_s16): Likewise.
3999 (vstrbq_p_u8): Likewise.
4000 (vstrbq_p_u32): Likewise.
4001 (vstrbq_p_u16): Likewise.
4002 (vstrbq_scatter_offset_p_s8): Likewise.
4003 (vstrbq_scatter_offset_p_s32): Likewise.
4004 (vstrbq_scatter_offset_p_s16): Likewise.
4005 (vstrbq_scatter_offset_p_u8): Likewise.
4006 (vstrbq_scatter_offset_p_u32): Likewise.
4007 (vstrbq_scatter_offset_p_u16): Likewise.
4008 (vstrwq_scatter_base_p_s32): Likewise.
4009 (vstrwq_scatter_base_p_u32): Likewise.
4010 (__arm_vstrbq_p_s8): Define intrinsic.
4011 (__arm_vstrbq_p_s32): Likewise.
4012 (__arm_vstrbq_p_s16): Likewise.
4013 (__arm_vstrbq_p_u8): Likewise.
4014 (__arm_vstrbq_p_u32): Likewise.
4015 (__arm_vstrbq_p_u16): Likewise.
4016 (__arm_vstrbq_scatter_offset_p_s8): Likewise.
4017 (__arm_vstrbq_scatter_offset_p_s32): Likewise.
4018 (__arm_vstrbq_scatter_offset_p_s16): Likewise.
4019 (__arm_vstrbq_scatter_offset_p_u8): Likewise.
4020 (__arm_vstrbq_scatter_offset_p_u32): Likewise.
4021 (__arm_vstrbq_scatter_offset_p_u16): Likewise.
4022 (__arm_vstrwq_scatter_base_p_s32): Likewise.
4023 (__arm_vstrwq_scatter_base_p_u32): Likewise.
4024 (vstrbq_p): Define polymorphic variant.
4025 (vstrbq_scatter_offset_p): Likewise.
4026 (vstrwq_scatter_base_p): Likewise.
4027 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin
4028 qualifier.
4029 (STRU_P_QUALIFIERS): Likewise.
4030 (STRSU_P_QUALIFIERS): Likewise.
4031 (STRSS_P_QUALIFIERS): Likewise.
4032 (STRSBS_P_QUALIFIERS): Likewise.
4033 (STRSBU_P_QUALIFIERS): Likewise.
4034 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define
4035 RTL pattern.
4036 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
4037 (mve_vstrbq_p_<supf><mode>): Likewise.
4039 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4040 Mihail Ionescu <mihail.ionescu@arm.com>
4041 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4043 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
4044 qualifier.
4045 (LDRGS_QUALIFIERS): Likewise.
4046 (LDRS_QUALIFIERS): Likewise.
4047 (LDRU_QUALIFIERS): Likewise.
4048 (LDRGBS_QUALIFIERS): Likewise.
4049 (LDRGBU_QUALIFIERS): Likewise.
4050 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
4051 (vldrbq_gather_offset_s8): Likewise.
4052 (vldrbq_s8): Likewise.
4053 (vldrbq_u8): Likewise.
4054 (vldrbq_gather_offset_u16): Likewise.
4055 (vldrbq_gather_offset_s16): Likewise.
4056 (vldrbq_s16): Likewise.
4057 (vldrbq_u16): Likewise.
4058 (vldrbq_gather_offset_u32): Likewise.
4059 (vldrbq_gather_offset_s32): Likewise.
4060 (vldrbq_s32): Likewise.
4061 (vldrbq_u32): Likewise.
4062 (vldrwq_gather_base_s32): Likewise.
4063 (vldrwq_gather_base_u32): Likewise.
4064 (__arm_vldrbq_gather_offset_u8): Define intrinsic.
4065 (__arm_vldrbq_gather_offset_s8): Likewise.
4066 (__arm_vldrbq_s8): Likewise.
4067 (__arm_vldrbq_u8): Likewise.
4068 (__arm_vldrbq_gather_offset_u16): Likewise.
4069 (__arm_vldrbq_gather_offset_s16): Likewise.
4070 (__arm_vldrbq_s16): Likewise.
4071 (__arm_vldrbq_u16): Likewise.
4072 (__arm_vldrbq_gather_offset_u32): Likewise.
4073 (__arm_vldrbq_gather_offset_s32): Likewise.
4074 (__arm_vldrbq_s32): Likewise.
4075 (__arm_vldrbq_u32): Likewise.
4076 (__arm_vldrwq_gather_base_s32): Likewise.
4077 (__arm_vldrwq_gather_base_u32): Likewise.
4078 (vldrbq_gather_offset): Define polymorphic variant.
4079 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin
4080 qualifier.
4081 (LDRGS_QUALIFIERS): Likewise.
4082 (LDRS_QUALIFIERS): Likewise.
4083 (LDRU_QUALIFIERS): Likewise.
4084 (LDRGBS_QUALIFIERS): Likewise.
4085 (LDRGBU_QUALIFIERS): Likewise.
4086 * config/arm/mve.md (VLDRBGOQ): Define iterator.
4087 (VLDRBQ): Likewise.
4088 (VLDRWGBQ): Likewise.
4089 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
4090 (mve_vldrbq_<supf><mode>): Likewise.
4091 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
4093 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4094 Mihail Ionescu <mihail.ionescu@arm.com>
4095 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4097 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier.
4098 (STRU_QUALIFIERS): Likewise.
4099 (STRSS_QUALIFIERS): Likewise.
4100 (STRSU_QUALIFIERS): Likewise.
4101 (STRSBS_QUALIFIERS): Likewise.
4102 (STRSBU_QUALIFIERS): Likewise.
4103 * config/arm/arm_mve.h (vstrbq_s8): Define macro.
4104 (vstrbq_u8): Likewise.
4105 (vstrbq_u16): Likewise.
4106 (vstrbq_scatter_offset_s8): Likewise.
4107 (vstrbq_scatter_offset_u8): Likewise.
4108 (vstrbq_scatter_offset_u16): Likewise.
4109 (vstrbq_s16): Likewise.
4110 (vstrbq_u32): Likewise.
4111 (vstrbq_scatter_offset_s16): Likewise.
4112 (vstrbq_scatter_offset_u32): Likewise.
4113 (vstrbq_s32): Likewise.
4114 (vstrbq_scatter_offset_s32): Likewise.
4115 (vstrwq_scatter_base_s32): Likewise.
4116 (vstrwq_scatter_base_u32): Likewise.
4117 (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
4118 (__arm_vstrbq_scatter_offset_s32): Likewise.
4119 (__arm_vstrbq_scatter_offset_s16): Likewise.
4120 (__arm_vstrbq_scatter_offset_u8): Likewise.
4121 (__arm_vstrbq_scatter_offset_u32): Likewise.
4122 (__arm_vstrbq_scatter_offset_u16): Likewise.
4123 (__arm_vstrbq_s8): Likewise.
4124 (__arm_vstrbq_s32): Likewise.
4125 (__arm_vstrbq_s16): Likewise.
4126 (__arm_vstrbq_u8): Likewise.
4127 (__arm_vstrbq_u32): Likewise.
4128 (__arm_vstrbq_u16): Likewise.
4129 (__arm_vstrwq_scatter_base_s32): Likewise.
4130 (__arm_vstrwq_scatter_base_u32): Likewise.
4131 (vstrbq): Define polymorphic variant.
4132 (vstrbq_scatter_offset): Likewise.
4133 (vstrwq_scatter_base): Likewise.
4134 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
4135 qualifier.
4136 (STRU_QUALIFIERS): Likewise.
4137 (STRSS_QUALIFIERS): Likewise.
4138 (STRSU_QUALIFIERS): Likewise.
4139 (STRSBS_QUALIFIERS): Likewise.
4140 (STRSBU_QUALIFIERS): Likewise.
4141 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator.
4142 (VSTRWSBQ): Define iterators.
4143 (VSTRBSOQ): Likewise.
4144 (VSTRBQ): Likewise.
4145 (mve_vstrbq_<supf><mode>): Define RTL pattern.
4146 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
4147 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
4149 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4150 Mihail Ionescu <mihail.ionescu@arm.com>
4151 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4153 * config/arm/arm_mve.h (vabdq_m_f32): Define macro.
4154 (vabdq_m_f16): Likewise.
4155 (vaddq_m_f32): Likewise.
4156 (vaddq_m_f16): Likewise.
4157 (vaddq_m_n_f32): Likewise.
4158 (vaddq_m_n_f16): Likewise.
4159 (vandq_m_f32): Likewise.
4160 (vandq_m_f16): Likewise.
4161 (vbicq_m_f32): Likewise.
4162 (vbicq_m_f16): Likewise.
4163 (vbrsrq_m_n_f32): Likewise.
4164 (vbrsrq_m_n_f16): Likewise.
4165 (vcaddq_rot270_m_f32): Likewise.
4166 (vcaddq_rot270_m_f16): Likewise.
4167 (vcaddq_rot90_m_f32): Likewise.
4168 (vcaddq_rot90_m_f16): Likewise.
4169 (vcmlaq_m_f32): Likewise.
4170 (vcmlaq_m_f16): Likewise.
4171 (vcmlaq_rot180_m_f32): Likewise.
4172 (vcmlaq_rot180_m_f16): Likewise.
4173 (vcmlaq_rot270_m_f32): Likewise.
4174 (vcmlaq_rot270_m_f16): Likewise.
4175 (vcmlaq_rot90_m_f32): Likewise.
4176 (vcmlaq_rot90_m_f16): Likewise.
4177 (vcmulq_m_f32): Likewise.
4178 (vcmulq_m_f16): Likewise.
4179 (vcmulq_rot180_m_f32): Likewise.
4180 (vcmulq_rot180_m_f16): Likewise.
4181 (vcmulq_rot270_m_f32): Likewise.
4182 (vcmulq_rot270_m_f16): Likewise.
4183 (vcmulq_rot90_m_f32): Likewise.
4184 (vcmulq_rot90_m_f16): Likewise.
4185 (vcvtq_m_n_s32_f32): Likewise.
4186 (vcvtq_m_n_s16_f16): Likewise.
4187 (vcvtq_m_n_u32_f32): Likewise.
4188 (vcvtq_m_n_u16_f16): Likewise.
4189 (veorq_m_f32): Likewise.
4190 (veorq_m_f16): Likewise.
4191 (vfmaq_m_f32): Likewise.
4192 (vfmaq_m_f16): Likewise.
4193 (vfmaq_m_n_f32): Likewise.
4194 (vfmaq_m_n_f16): Likewise.
4195 (vfmasq_m_n_f32): Likewise.
4196 (vfmasq_m_n_f16): Likewise.
4197 (vfmsq_m_f32): Likewise.
4198 (vfmsq_m_f16): Likewise.
4199 (vmaxnmq_m_f32): Likewise.
4200 (vmaxnmq_m_f16): Likewise.
4201 (vminnmq_m_f32): Likewise.
4202 (vminnmq_m_f16): Likewise.
4203 (vmulq_m_f32): Likewise.
4204 (vmulq_m_f16): Likewise.
4205 (vmulq_m_n_f32): Likewise.
4206 (vmulq_m_n_f16): Likewise.
4207 (vornq_m_f32): Likewise.
4208 (vornq_m_f16): Likewise.
4209 (vorrq_m_f32): Likewise.
4210 (vorrq_m_f16): Likewise.
4211 (vsubq_m_f32): Likewise.
4212 (vsubq_m_f16): Likewise.
4213 (vsubq_m_n_f32): Likewise.
4214 (vsubq_m_n_f16): Likewise.
4215 (__attribute__): Likewise.
4216 (__arm_vabdq_m_f32): Likewise.
4217 (__arm_vabdq_m_f16): Likewise.
4218 (__arm_vaddq_m_f32): Likewise.
4219 (__arm_vaddq_m_f16): Likewise.
4220 (__arm_vaddq_m_n_f32): Likewise.
4221 (__arm_vaddq_m_n_f16): Likewise.
4222 (__arm_vandq_m_f32): Likewise.
4223 (__arm_vandq_m_f16): Likewise.
4224 (__arm_vbicq_m_f32): Likewise.
4225 (__arm_vbicq_m_f16): Likewise.
4226 (__arm_vbrsrq_m_n_f32): Likewise.
4227 (__arm_vbrsrq_m_n_f16): Likewise.
4228 (__arm_vcaddq_rot270_m_f32): Likewise.
4229 (__arm_vcaddq_rot270_m_f16): Likewise.
4230 (__arm_vcaddq_rot90_m_f32): Likewise.
4231 (__arm_vcaddq_rot90_m_f16): Likewise.
4232 (__arm_vcmlaq_m_f32): Likewise.
4233 (__arm_vcmlaq_m_f16): Likewise.
4234 (__arm_vcmlaq_rot180_m_f32): Likewise.
4235 (__arm_vcmlaq_rot180_m_f16): Likewise.
4236 (__arm_vcmlaq_rot270_m_f32): Likewise.
4237 (__arm_vcmlaq_rot270_m_f16): Likewise.
4238 (__arm_vcmlaq_rot90_m_f32): Likewise.
4239 (__arm_vcmlaq_rot90_m_f16): Likewise.
4240 (__arm_vcmulq_m_f32): Likewise.
4241 (__arm_vcmulq_m_f16): Likewise.
4242 (__arm_vcmulq_rot180_m_f32): Define intrinsic.
4243 (__arm_vcmulq_rot180_m_f16): Likewise.
4244 (__arm_vcmulq_rot270_m_f32): Likewise.
4245 (__arm_vcmulq_rot270_m_f16): Likewise.
4246 (__arm_vcmulq_rot90_m_f32): Likewise.
4247 (__arm_vcmulq_rot90_m_f16): Likewise.
4248 (__arm_vcvtq_m_n_s32_f32): Likewise.
4249 (__arm_vcvtq_m_n_s16_f16): Likewise.
4250 (__arm_vcvtq_m_n_u32_f32): Likewise.
4251 (__arm_vcvtq_m_n_u16_f16): Likewise.
4252 (__arm_veorq_m_f32): Likewise.
4253 (__arm_veorq_m_f16): Likewise.
4254 (__arm_vfmaq_m_f32): Likewise.
4255 (__arm_vfmaq_m_f16): Likewise.
4256 (__arm_vfmaq_m_n_f32): Likewise.
4257 (__arm_vfmaq_m_n_f16): Likewise.
4258 (__arm_vfmasq_m_n_f32): Likewise.
4259 (__arm_vfmasq_m_n_f16): Likewise.
4260 (__arm_vfmsq_m_f32): Likewise.
4261 (__arm_vfmsq_m_f16): Likewise.
4262 (__arm_vmaxnmq_m_f32): Likewise.
4263 (__arm_vmaxnmq_m_f16): Likewise.
4264 (__arm_vminnmq_m_f32): Likewise.
4265 (__arm_vminnmq_m_f16): Likewise.
4266 (__arm_vmulq_m_f32): Likewise.
4267 (__arm_vmulq_m_f16): Likewise.
4268 (__arm_vmulq_m_n_f32): Likewise.
4269 (__arm_vmulq_m_n_f16): Likewise.
4270 (__arm_vornq_m_f32): Likewise.
4271 (__arm_vornq_m_f16): Likewise.
4272 (__arm_vorrq_m_f32): Likewise.
4273 (__arm_vorrq_m_f16): Likewise.
4274 (__arm_vsubq_m_f32): Likewise.
4275 (__arm_vsubq_m_f16): Likewise.
4276 (__arm_vsubq_m_n_f32): Likewise.
4277 (__arm_vsubq_m_n_f16): Likewise.
4278 (vabdq_m): Define polymorphic variant.
4279 (vaddq_m): Likewise.
4280 (vaddq_m_n): Likewise.
4281 (vandq_m): Likewise.
4282 (vbicq_m): Likewise.
4283 (vbrsrq_m_n): Likewise.
4284 (vcaddq_rot270_m): Likewise.
4285 (vcaddq_rot90_m): Likewise.
4286 (vcmlaq_m): Likewise.
4287 (vcmlaq_rot180_m): Likewise.
4288 (vcmlaq_rot270_m): Likewise.
4289 (vcmlaq_rot90_m): Likewise.
4290 (vcmulq_m): Likewise.
4291 (vcmulq_rot180_m): Likewise.
4292 (vcmulq_rot270_m): Likewise.
4293 (vcmulq_rot90_m): Likewise.
4294 (veorq_m): Likewise.
4295 (vfmaq_m): Likewise.
4296 (vfmaq_m_n): Likewise.
4297 (vfmasq_m_n): Likewise.
4298 (vfmsq_m): Likewise.
4299 (vmaxnmq_m): Likewise.
4300 (vminnmq_m): Likewise.
4301 (vmulq_m): Likewise.
4302 (vmulq_m_n): Likewise.
4303 (vornq_m): Likewise.
4304 (vsubq_m): Likewise.
4305 (vsubq_m_n): Likewise.
4306 (vorrq_m): Likewise.
4307 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
4308 builtin qualifier.
4309 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
4310 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
4311 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
4312 (mve_vaddq_m_f<mode>): Likewise.
4313 (mve_vaddq_m_n_f<mode>): Likewise.
4314 (mve_vandq_m_f<mode>): Likewise.
4315 (mve_vbicq_m_f<mode>): Likewise.
4316 (mve_vbrsrq_m_n_f<mode>): Likewise.
4317 (mve_vcaddq_rot270_m_f<mode>): Likewise.
4318 (mve_vcaddq_rot90_m_f<mode>): Likewise.
4319 (mve_vcmlaq_m_f<mode>): Likewise.
4320 (mve_vcmlaq_rot180_m_f<mode>): Likewise.
4321 (mve_vcmlaq_rot270_m_f<mode>): Likewise.
4322 (mve_vcmlaq_rot90_m_f<mode>): Likewise.
4323 (mve_vcmulq_m_f<mode>): Likewise.
4324 (mve_vcmulq_rot180_m_f<mode>): Likewise.
4325 (mve_vcmulq_rot270_m_f<mode>): Likewise.
4326 (mve_vcmulq_rot90_m_f<mode>): Likewise.
4327 (mve_veorq_m_f<mode>): Likewise.
4328 (mve_vfmaq_m_f<mode>): Likewise.
4329 (mve_vfmaq_m_n_f<mode>): Likewise.
4330 (mve_vfmasq_m_n_f<mode>): Likewise.
4331 (mve_vfmsq_m_f<mode>): Likewise.
4332 (mve_vmaxnmq_m_f<mode>): Likewise.
4333 (mve_vminnmq_m_f<mode>): Likewise.
4334 (mve_vmulq_m_f<mode>): Likewise.
4335 (mve_vmulq_m_n_f<mode>): Likewise.
4336 (mve_vornq_m_f<mode>): Likewise.
4337 (mve_vorrq_m_f<mode>): Likewise.
4338 (mve_vsubq_m_f<mode>): Likewise.
4339 (mve_vsubq_m_n_f<mode>): Likewise.
4341 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4342 Mihail Ionescu <mihail.ionescu@arm.com>
4343 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4345 * config/arm/arm-protos.h (arm_mve_immediate_check):
4346 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check
4347 mode and interger value.
4348 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
4349 (vmlaldavaq_p_s16): Likewise.
4350 (vmlaldavaq_p_u32): Likewise.
4351 (vmlaldavaq_p_u16): Likewise.
4352 (vmlaldavaxq_p_s32): Likewise.
4353 (vmlaldavaxq_p_s16): Likewise.
4354 (vmlaldavaxq_p_u32): Likewise.
4355 (vmlaldavaxq_p_u16): Likewise.
4356 (vmlsldavaq_p_s32): Likewise.
4357 (vmlsldavaq_p_s16): Likewise.
4358 (vmlsldavaxq_p_s32): Likewise.
4359 (vmlsldavaxq_p_s16): Likewise.
4360 (vmullbq_poly_m_p8): Likewise.
4361 (vmullbq_poly_m_p16): Likewise.
4362 (vmulltq_poly_m_p8): Likewise.
4363 (vmulltq_poly_m_p16): Likewise.
4364 (vqdmullbq_m_n_s32): Likewise.
4365 (vqdmullbq_m_n_s16): Likewise.
4366 (vqdmullbq_m_s32): Likewise.
4367 (vqdmullbq_m_s16): Likewise.
4368 (vqdmulltq_m_n_s32): Likewise.
4369 (vqdmulltq_m_n_s16): Likewise.
4370 (vqdmulltq_m_s32): Likewise.
4371 (vqdmulltq_m_s16): Likewise.
4372 (vqrshrnbq_m_n_s32): Likewise.
4373 (vqrshrnbq_m_n_s16): Likewise.
4374 (vqrshrnbq_m_n_u32): Likewise.
4375 (vqrshrnbq_m_n_u16): Likewise.
4376 (vqrshrntq_m_n_s32): Likewise.
4377 (vqrshrntq_m_n_s16): Likewise.
4378 (vqrshrntq_m_n_u32): Likewise.
4379 (vqrshrntq_m_n_u16): Likewise.
4380 (vqrshrunbq_m_n_s32): Likewise.
4381 (vqrshrunbq_m_n_s16): Likewise.
4382 (vqrshruntq_m_n_s32): Likewise.
4383 (vqrshruntq_m_n_s16): Likewise.
4384 (vqshrnbq_m_n_s32): Likewise.
4385 (vqshrnbq_m_n_s16): Likewise.
4386 (vqshrnbq_m_n_u32): Likewise.
4387 (vqshrnbq_m_n_u16): Likewise.
4388 (vqshrntq_m_n_s32): Likewise.
4389 (vqshrntq_m_n_s16): Likewise.
4390 (vqshrntq_m_n_u32): Likewise.
4391 (vqshrntq_m_n_u16): Likewise.
4392 (vqshrunbq_m_n_s32): Likewise.
4393 (vqshrunbq_m_n_s16): Likewise.
4394 (vqshruntq_m_n_s32): Likewise.
4395 (vqshruntq_m_n_s16): Likewise.
4396 (vrmlaldavhaq_p_s32): Likewise.
4397 (vrmlaldavhaq_p_u32): Likewise.
4398 (vrmlaldavhaxq_p_s32): Likewise.
4399 (vrmlsldavhaq_p_s32): Likewise.
4400 (vrmlsldavhaxq_p_s32): Likewise.
4401 (vrshrnbq_m_n_s32): Likewise.
4402 (vrshrnbq_m_n_s16): Likewise.
4403 (vrshrnbq_m_n_u32): Likewise.
4404 (vrshrnbq_m_n_u16): Likewise.
4405 (vrshrntq_m_n_s32): Likewise.
4406 (vrshrntq_m_n_s16): Likewise.
4407 (vrshrntq_m_n_u32): Likewise.
4408 (vrshrntq_m_n_u16): Likewise.
4409 (vshllbq_m_n_s8): Likewise.
4410 (vshllbq_m_n_s16): Likewise.
4411 (vshllbq_m_n_u8): Likewise.
4412 (vshllbq_m_n_u16): Likewise.
4413 (vshlltq_m_n_s8): Likewise.
4414 (vshlltq_m_n_s16): Likewise.
4415 (vshlltq_m_n_u8): Likewise.
4416 (vshlltq_m_n_u16): Likewise.
4417 (vshrnbq_m_n_s32): Likewise.
4418 (vshrnbq_m_n_s16): Likewise.
4419 (vshrnbq_m_n_u32): Likewise.
4420 (vshrnbq_m_n_u16): Likewise.
4421 (vshrntq_m_n_s32): Likewise.
4422 (vshrntq_m_n_s16): Likewise.
4423 (vshrntq_m_n_u32): Likewise.
4424 (vshrntq_m_n_u16): Likewise.
4425 (__arm_vmlaldavaq_p_s32): Define intrinsic.
4426 (__arm_vmlaldavaq_p_s16): Likewise.
4427 (__arm_vmlaldavaq_p_u32): Likewise.
4428 (__arm_vmlaldavaq_p_u16): Likewise.
4429 (__arm_vmlaldavaxq_p_s32): Likewise.
4430 (__arm_vmlaldavaxq_p_s16): Likewise.
4431 (__arm_vmlaldavaxq_p_u32): Likewise.
4432 (__arm_vmlaldavaxq_p_u16): Likewise.
4433 (__arm_vmlsldavaq_p_s32): Likewise.
4434 (__arm_vmlsldavaq_p_s16): Likewise.
4435 (__arm_vmlsldavaxq_p_s32): Likewise.
4436 (__arm_vmlsldavaxq_p_s16): Likewise.
4437 (__arm_vmullbq_poly_m_p8): Likewise.
4438 (__arm_vmullbq_poly_m_p16): Likewise.
4439 (__arm_vmulltq_poly_m_p8): Likewise.
4440 (__arm_vmulltq_poly_m_p16): Likewise.
4441 (__arm_vqdmullbq_m_n_s32): Likewise.
4442 (__arm_vqdmullbq_m_n_s16): Likewise.
4443 (__arm_vqdmullbq_m_s32): Likewise.
4444 (__arm_vqdmullbq_m_s16): Likewise.
4445 (__arm_vqdmulltq_m_n_s32): Likewise.
4446 (__arm_vqdmulltq_m_n_s16): Likewise.
4447 (__arm_vqdmulltq_m_s32): Likewise.
4448 (__arm_vqdmulltq_m_s16): Likewise.
4449 (__arm_vqrshrnbq_m_n_s32): Likewise.
4450 (__arm_vqrshrnbq_m_n_s16): Likewise.
4451 (__arm_vqrshrnbq_m_n_u32): Likewise.
4452 (__arm_vqrshrnbq_m_n_u16): Likewise.
4453 (__arm_vqrshrntq_m_n_s32): Likewise.
4454 (__arm_vqrshrntq_m_n_s16): Likewise.
4455 (__arm_vqrshrntq_m_n_u32): Likewise.
4456 (__arm_vqrshrntq_m_n_u16): Likewise.
4457 (__arm_vqrshrunbq_m_n_s32): Likewise.
4458 (__arm_vqrshrunbq_m_n_s16): Likewise.
4459 (__arm_vqrshruntq_m_n_s32): Likewise.
4460 (__arm_vqrshruntq_m_n_s16): Likewise.
4461 (__arm_vqshrnbq_m_n_s32): Likewise.
4462 (__arm_vqshrnbq_m_n_s16): Likewise.
4463 (__arm_vqshrnbq_m_n_u32): Likewise.
4464 (__arm_vqshrnbq_m_n_u16): Likewise.
4465 (__arm_vqshrntq_m_n_s32): Likewise.
4466 (__arm_vqshrntq_m_n_s16): Likewise.
4467 (__arm_vqshrntq_m_n_u32): Likewise.
4468 (__arm_vqshrntq_m_n_u16): Likewise.
4469 (__arm_vqshrunbq_m_n_s32): Likewise.
4470 (__arm_vqshrunbq_m_n_s16): Likewise.
4471 (__arm_vqshruntq_m_n_s32): Likewise.
4472 (__arm_vqshruntq_m_n_s16): Likewise.
4473 (__arm_vrmlaldavhaq_p_s32): Likewise.
4474 (__arm_vrmlaldavhaq_p_u32): Likewise.
4475 (__arm_vrmlaldavhaxq_p_s32): Likewise.
4476 (__arm_vrmlsldavhaq_p_s32): Likewise.
4477 (__arm_vrmlsldavhaxq_p_s32): Likewise.
4478 (__arm_vrshrnbq_m_n_s32): Likewise.
4479 (__arm_vrshrnbq_m_n_s16): Likewise.
4480 (__arm_vrshrnbq_m_n_u32): Likewise.
4481 (__arm_vrshrnbq_m_n_u16): Likewise.
4482 (__arm_vrshrntq_m_n_s32): Likewise.
4483 (__arm_vrshrntq_m_n_s16): Likewise.
4484 (__arm_vrshrntq_m_n_u32): Likewise.
4485 (__arm_vrshrntq_m_n_u16): Likewise.
4486 (__arm_vshllbq_m_n_s8): Likewise.
4487 (__arm_vshllbq_m_n_s16): Likewise.
4488 (__arm_vshllbq_m_n_u8): Likewise.
4489 (__arm_vshllbq_m_n_u16): Likewise.
4490 (__arm_vshlltq_m_n_s8): Likewise.
4491 (__arm_vshlltq_m_n_s16): Likewise.
4492 (__arm_vshlltq_m_n_u8): Likewise.
4493 (__arm_vshlltq_m_n_u16): Likewise.
4494 (__arm_vshrnbq_m_n_s32): Likewise.
4495 (__arm_vshrnbq_m_n_s16): Likewise.
4496 (__arm_vshrnbq_m_n_u32): Likewise.
4497 (__arm_vshrnbq_m_n_u16): Likewise.
4498 (__arm_vshrntq_m_n_s32): Likewise.
4499 (__arm_vshrntq_m_n_s16): Likewise.
4500 (__arm_vshrntq_m_n_u32): Likewise.
4501 (__arm_vshrntq_m_n_u16): Likewise.
4502 (vmullbq_poly_m): Define polymorphic variant.
4503 (vmulltq_poly_m): Likewise.
4504 (vshllbq_m): Likewise.
4505 (vshrntq_m_n): Likewise.
4506 (vshrnbq_m_n): Likewise.
4507 (vshlltq_m_n): Likewise.
4508 (vshllbq_m_n): Likewise.
4509 (vrshrntq_m_n): Likewise.
4510 (vrshrnbq_m_n): Likewise.
4511 (vqshruntq_m_n): Likewise.
4512 (vqshrunbq_m_n): Likewise.
4513 (vqdmullbq_m_n): Likewise.
4514 (vqdmullbq_m): Likewise.
4515 (vqdmulltq_m_n): Likewise.
4516 (vqdmulltq_m): Likewise.
4517 (vqrshrnbq_m_n): Likewise.
4518 (vqrshrntq_m_n): Likewise.
4519 (vqrshrunbq_m_n): Likewise.
4520 (vqrshruntq_m_n): Likewise.
4521 (vqshrnbq_m_n): Likewise.
4522 (vqshrntq_m_n): Likewise.
4523 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
4524 builtin qualifiers.
4525 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
4526 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
4527 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
4528 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
4529 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
4530 (VMLALDAVAXQ_P): Likewise.
4531 (VQRSHRNBQ_M_N): Likewise.
4532 (VQRSHRNTQ_M_N): Likewise.
4533 (VQSHRNBQ_M_N): Likewise.
4534 (VQSHRNTQ_M_N): Likewise.
4535 (VRSHRNBQ_M_N): Likewise.
4536 (VRSHRNTQ_M_N): Likewise.
4537 (VSHLLBQ_M_N): Likewise.
4538 (VSHLLTQ_M_N): Likewise.
4539 (VSHRNBQ_M_N): Likewise.
4540 (VSHRNTQ_M_N): Likewise.
4541 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
4542 (mve_vmlaldavaxq_p_<supf><mode>): Likewise.
4543 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
4544 (mve_vqrshrntq_m_n_<supf><mode>): Likewise.
4545 (mve_vqshrnbq_m_n_<supf><mode>): Likewise.
4546 (mve_vqshrntq_m_n_<supf><mode>): Likewise.
4547 (mve_vrmlaldavhaq_p_sv4si): Likewise.
4548 (mve_vrshrnbq_m_n_<supf><mode>): Likewise.
4549 (mve_vrshrntq_m_n_<supf><mode>): Likewise.
4550 (mve_vshllbq_m_n_<supf><mode>): Likewise.
4551 (mve_vshlltq_m_n_<supf><mode>): Likewise.
4552 (mve_vshrnbq_m_n_<supf><mode>): Likewise.
4553 (mve_vshrntq_m_n_<supf><mode>): Likewise.
4554 (mve_vmlsldavaq_p_s<mode>): Likewise.
4555 (mve_vmlsldavaxq_p_s<mode>): Likewise.
4556 (mve_vmullbq_poly_m_p<mode>): Likewise.
4557 (mve_vmulltq_poly_m_p<mode>): Likewise.
4558 (mve_vqdmullbq_m_n_s<mode>): Likewise.
4559 (mve_vqdmullbq_m_s<mode>): Likewise.
4560 (mve_vqdmulltq_m_n_s<mode>): Likewise.
4561 (mve_vqdmulltq_m_s<mode>): Likewise.
4562 (mve_vqrshrunbq_m_n_s<mode>): Likewise.
4563 (mve_vqrshruntq_m_n_s<mode>): Likewise.
4564 (mve_vqshrunbq_m_n_s<mode>): Likewise.
4565 (mve_vqshruntq_m_n_s<mode>): Likewise.
4566 (mve_vrmlaldavhaq_p_uv4si): Likewise.
4567 (mve_vrmlaldavhaxq_p_sv4si): Likewise.
4568 (mve_vrmlsldavhaq_p_sv4si): Likewise.
4569 (mve_vrmlsldavhaxq_p_sv4si): Likewise.
4571 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
4572 Mihail Ionescu <mihail.ionescu@arm.com>
4573 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4575 * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
4576 (vabdq_m_s32): Likewise.
4577 (vabdq_m_s16): Likewise.
4578 (vabdq_m_u8): Likewise.
4579 (vabdq_m_u32): Likewise.
4580 (vabdq_m_u16): Likewise.
4581 (vaddq_m_n_s8): Likewise.
4582 (vaddq_m_n_s32): Likewise.
4583 (vaddq_m_n_s16): Likewise.
4584 (vaddq_m_n_u8): Likewise.
4585 (vaddq_m_n_u32): Likewise.
4586 (vaddq_m_n_u16): Likewise.
4587 (vaddq_m_s8): Likewise.
4588 (vaddq_m_s32): Likewise.
4589 (vaddq_m_s16): Likewise.
4590 (vaddq_m_u8): Likewise.
4591 (vaddq_m_u32): Likewise.
4592 (vaddq_m_u16): Likewise.
4593 (vandq_m_s8): Likewise.
4594 (vandq_m_s32): Likewise.
4595 (vandq_m_s16): Likewise.
4596 (vandq_m_u8): Likewise.
4597 (vandq_m_u32): Likewise.
4598 (vandq_m_u16): Likewise.
4599 (vbicq_m_s8): Likewise.
4600 (vbicq_m_s32): Likewise.
4601 (vbicq_m_s16): Likewise.
4602 (vbicq_m_u8): Likewise.
4603 (vbicq_m_u32): Likewise.
4604 (vbicq_m_u16): Likewise.
4605 (vbrsrq_m_n_s8): Likewise.
4606 (vbrsrq_m_n_s32): Likewise.
4607 (vbrsrq_m_n_s16): Likewise.
4608 (vbrsrq_m_n_u8): Likewise.
4609 (vbrsrq_m_n_u32): Likewise.
4610 (vbrsrq_m_n_u16): Likewise.
4611 (vcaddq_rot270_m_s8): Likewise.
4612 (vcaddq_rot270_m_s32): Likewise.
4613 (vcaddq_rot270_m_s16): Likewise.
4614 (vcaddq_rot270_m_u8): Likewise.
4615 (vcaddq_rot270_m_u32): Likewise.
4616 (vcaddq_rot270_m_u16): Likewise.
4617 (vcaddq_rot90_m_s8): Likewise.
4618 (vcaddq_rot90_m_s32): Likewise.
4619 (vcaddq_rot90_m_s16): Likewise.
4620 (vcaddq_rot90_m_u8): Likewise.
4621 (vcaddq_rot90_m_u32): Likewise.
4622 (vcaddq_rot90_m_u16): Likewise.
4623 (veorq_m_s8): Likewise.
4624 (veorq_m_s32): Likewise.
4625 (veorq_m_s16): Likewise.
4626 (veorq_m_u8): Likewise.
4627 (veorq_m_u32): Likewise.
4628 (veorq_m_u16): Likewise.
4629 (vhaddq_m_n_s8): Likewise.
4630 (vhaddq_m_n_s32): Likewise.
4631 (vhaddq_m_n_s16): Likewise.
4632 (vhaddq_m_n_u8): Likewise.
4633 (vhaddq_m_n_u32): Likewise.
4634 (vhaddq_m_n_u16): Likewise.
4635 (vhaddq_m_s8): Likewise.
4636 (vhaddq_m_s32): Likewise.
4637 (vhaddq_m_s16): Likewise.
4638 (vhaddq_m_u8): Likewise.
4639 (vhaddq_m_u32): Likewise.
4640 (vhaddq_m_u16): Likewise.
4641 (vhcaddq_rot270_m_s8): Likewise.
4642 (vhcaddq_rot270_m_s32): Likewise.
4643 (vhcaddq_rot270_m_s16): Likewise.
4644 (vhcaddq_rot90_m_s8): Likewise.
4645 (vhcaddq_rot90_m_s32): Likewise.
4646 (vhcaddq_rot90_m_s16): Likewise.
4647 (vhsubq_m_n_s8): Likewise.
4648 (vhsubq_m_n_s32): Likewise.
4649 (vhsubq_m_n_s16): Likewise.
4650 (vhsubq_m_n_u8): Likewise.
4651 (vhsubq_m_n_u32): Likewise.
4652 (vhsubq_m_n_u16): Likewise.
4653 (vhsubq_m_s8): Likewise.
4654 (vhsubq_m_s32): Likewise.
4655 (vhsubq_m_s16): Likewise.
4656 (vhsubq_m_u8): Likewise.
4657 (vhsubq_m_u32): Likewise.
4658 (vhsubq_m_u16): Likewise.
4659 (vmaxq_m_s8): Likewise.
4660 (vmaxq_m_s32): Likewise.
4661 (vmaxq_m_s16): Likewise.
4662 (vmaxq_m_u8): Likewise.
4663 (vmaxq_m_u32): Likewise.
4664 (vmaxq_m_u16): Likewise.
4665 (vminq_m_s8): Likewise.
4666 (vminq_m_s32): Likewise.
4667 (vminq_m_s16): Likewise.
4668 (vminq_m_u8): Likewise.
4669 (vminq_m_u32): Likewise.
4670 (vminq_m_u16): Likewise.
4671 (vmladavaq_p_s8): Likewise.
4672 (vmladavaq_p_s32): Likewise.
4673 (vmladavaq_p_s16): Likewise.
4674 (vmladavaq_p_u8): Likewise.
4675 (vmladavaq_p_u32): Likewise.
4676 (vmladavaq_p_u16): Likewise.
4677 (vmladavaxq_p_s8): Likewise.
4678 (vmladavaxq_p_s32): Likewise.
4679 (vmladavaxq_p_s16): Likewise.
4680 (vmlaq_m_n_s8): Likewise.
4681 (vmlaq_m_n_s32): Likewise.
4682 (vmlaq_m_n_s16): Likewise.
4683 (vmlaq_m_n_u8): Likewise.
4684 (vmlaq_m_n_u32): Likewise.
4685 (vmlaq_m_n_u16): Likewise.
4686 (vmlasq_m_n_s8): Likewise.
4687 (vmlasq_m_n_s32): Likewise.
4688 (vmlasq_m_n_s16): Likewise.
4689 (vmlasq_m_n_u8): Likewise.
4690 (vmlasq_m_n_u32): Likewise.
4691 (vmlasq_m_n_u16): Likewise.
4692 (vmlsdavaq_p_s8): Likewise.
4693 (vmlsdavaq_p_s32): Likewise.
4694 (vmlsdavaq_p_s16): Likewise.
4695 (vmlsdavaxq_p_s8): Likewise.
4696 (vmlsdavaxq_p_s32): Likewise.
4697 (vmlsdavaxq_p_s16): Likewise.
4698 (vmulhq_m_s8): Likewise.
4699 (vmulhq_m_s32): Likewise.
4700 (vmulhq_m_s16): Likewise.
4701 (vmulhq_m_u8): Likewise.
4702 (vmulhq_m_u32): Likewise.
4703 (vmulhq_m_u16): Likewise.
4704 (vmullbq_int_m_s8): Likewise.
4705 (vmullbq_int_m_s32): Likewise.
4706 (vmullbq_int_m_s16): Likewise.
4707 (vmullbq_int_m_u8): Likewise.
4708 (vmullbq_int_m_u32): Likewise.
4709 (vmullbq_int_m_u16): Likewise.
4710 (vmulltq_int_m_s8): Likewise.
4711 (vmulltq_int_m_s32): Likewise.
4712 (vmulltq_int_m_s16): Likewise.
4713 (vmulltq_int_m_u8): Likewise.
4714 (vmulltq_int_m_u32): Likewise.
4715 (vmulltq_int_m_u16): Likewise.
4716 (vmulq_m_n_s8): Likewise.
4717 (vmulq_m_n_s32): Likewise.
4718 (vmulq_m_n_s16): Likewise.
4719 (vmulq_m_n_u8): Likewise.
4720 (vmulq_m_n_u32): Likewise.
4721 (vmulq_m_n_u16): Likewise.
4722 (vmulq_m_s8): Likewise.
4723 (vmulq_m_s32): Likewise.
4724 (vmulq_m_s16): Likewise.
4725 (vmulq_m_u8): Likewise.
4726 (vmulq_m_u32): Likewise.
4727 (vmulq_m_u16): Likewise.
4728 (vornq_m_s8): Likewise.
4729 (vornq_m_s32): Likewise.
4730 (vornq_m_s16): Likewise.
4731 (vornq_m_u8): Likewise.
4732 (vornq_m_u32): Likewise.
4733 (vornq_m_u16): Likewise.
4734 (vorrq_m_s8): Likewise.
4735 (vorrq_m_s32): Likewise.
4736 (vorrq_m_s16): Likewise.
4737 (vorrq_m_u8): Likewise.
4738 (vorrq_m_u32): Likewise.
4739 (vorrq_m_u16): Likewise.
4740 (vqaddq_m_n_s8): Likewise.
4741 (vqaddq_m_n_s32): Likewise.
4742 (vqaddq_m_n_s16): Likewise.
4743 (vqaddq_m_n_u8): Likewise.
4744 (vqaddq_m_n_u32): Likewise.
4745 (vqaddq_m_n_u16): Likewise.
4746 (vqaddq_m_s8): Likewise.
4747 (vqaddq_m_s32): Likewise.
4748 (vqaddq_m_s16): Likewise.
4749 (vqaddq_m_u8): Likewise.
4750 (vqaddq_m_u32): Likewise.
4751 (vqaddq_m_u16): Likewise.
4752 (vqdmladhq_m_s8): Likewise.
4753 (vqdmladhq_m_s32): Likewise.
4754 (vqdmladhq_m_s16): Likewise.
4755 (vqdmladhxq_m_s8): Likewise.
4756 (vqdmladhxq_m_s32): Likewise.
4757 (vqdmladhxq_m_s16): Likewise.
4758 (vqdmlahq_m_n_s8): Likewise.
4759 (vqdmlahq_m_n_s32): Likewise.
4760 (vqdmlahq_m_n_s16): Likewise.
4761 (vqdmlahq_m_n_u8): Likewise.
4762 (vqdmlahq_m_n_u32): Likewise.
4763 (vqdmlahq_m_n_u16): Likewise.
4764 (vqdmlsdhq_m_s8): Likewise.
4765 (vqdmlsdhq_m_s32): Likewise.
4766 (vqdmlsdhq_m_s16): Likewise.
4767 (vqdmlsdhxq_m_s8): Likewise.
4768 (vqdmlsdhxq_m_s32): Likewise.
4769 (vqdmlsdhxq_m_s16): Likewise.
4770 (vqdmulhq_m_n_s8): Likewise.
4771 (vqdmulhq_m_n_s32): Likewise.
4772 (vqdmulhq_m_n_s16): Likewise.
4773 (vqdmulhq_m_s8): Likewise.
4774 (vqdmulhq_m_s32): Likewise.
4775 (vqdmulhq_m_s16): Likewise.
4776 (vqrdmladhq_m_s8): Likewise.
4777 (vqrdmladhq_m_s32): Likewise.
4778 (vqrdmladhq_m_s16): Likewise.
4779 (vqrdmladhxq_m_s8): Likewise.
4780 (vqrdmladhxq_m_s32): Likewise.
4781 (vqrdmladhxq_m_s16): Likewise.
4782 (vqrdmlahq_m_n_s8): Likewise.
4783 (vqrdmlahq_m_n_s32): Likewise.
4784 (vqrdmlahq_m_n_s16): Likewise.
4785 (vqrdmlahq_m_n_u8): Likewise.
4786 (vqrdmlahq_m_n_u32): Likewise.
4787 (vqrdmlahq_m_n_u16): Likewise.
4788 (vqrdmlashq_m_n_s8): Likewise.
4789 (vqrdmlashq_m_n_s32): Likewise.
4790 (vqrdmlashq_m_n_s16): Likewise.
4791 (vqrdmlashq_m_n_u8): Likewise.
4792 (vqrdmlashq_m_n_u32): Likewise.
4793 (vqrdmlashq_m_n_u16): Likewise.
4794 (vqrdmlsdhq_m_s8): Likewise.
4795 (vqrdmlsdhq_m_s32): Likewise.
4796 (vqrdmlsdhq_m_s16): Likewise.
4797 (vqrdmlsdhxq_m_s8): Likewise.
4798 (vqrdmlsdhxq_m_s32): Likewise.
4799 (vqrdmlsdhxq_m_s16): Likewise.
4800 (vqrdmulhq_m_n_s8): Likewise.
4801 (vqrdmulhq_m_n_s32): Likewise.
4802 (vqrdmulhq_m_n_s16): Likewise.
4803 (vqrdmulhq_m_s8): Likewise.
4804 (vqrdmulhq_m_s32): Likewise.
4805 (vqrdmulhq_m_s16): Likewise.
4806 (vqrshlq_m_s8): Likewise.
4807 (vqrshlq_m_s32): Likewise.
4808 (vqrshlq_m_s16): Likewise.
4809 (vqrshlq_m_u8): Likewise.
4810 (vqrshlq_m_u32): Likewise.
4811 (vqrshlq_m_u16): Likewise.
4812 (vqshlq_m_n_s8): Likewise.
4813 (vqshlq_m_n_s32): Likewise.
4814 (vqshlq_m_n_s16): Likewise.
4815 (vqshlq_m_n_u8): Likewise.
4816 (vqshlq_m_n_u32): Likewise.
4817 (vqshlq_m_n_u16): Likewise.
4818 (vqshlq_m_s8): Likewise.
4819 (vqshlq_m_s32): Likewise.
4820 (vqshlq_m_s16): Likewise.
4821 (vqshlq_m_u8): Likewise.
4822 (vqshlq_m_u32): Likewise.
4823 (vqshlq_m_u16): Likewise.
4824 (vqsubq_m_n_s8): Likewise.
4825 (vqsubq_m_n_s32): Likewise.
4826 (vqsubq_m_n_s16): Likewise.
4827 (vqsubq_m_n_u8): Likewise.
4828 (vqsubq_m_n_u32): Likewise.
4829 (vqsubq_m_n_u16): Likewise.
4830 (vqsubq_m_s8): Likewise.
4831 (vqsubq_m_s32): Likewise.
4832 (vqsubq_m_s16): Likewise.
4833 (vqsubq_m_u8): Likewise.
4834 (vqsubq_m_u32): Likewise.
4835 (vqsubq_m_u16): Likewise.
4836 (vrhaddq_m_s8): Likewise.
4837 (vrhaddq_m_s32): Likewise.
4838 (vrhaddq_m_s16): Likewise.
4839 (vrhaddq_m_u8): Likewise.
4840 (vrhaddq_m_u32): Likewise.
4841 (vrhaddq_m_u16): Likewise.
4842 (vrmulhq_m_s8): Likewise.
4843 (vrmulhq_m_s32): Likewise.
4844 (vrmulhq_m_s16): Likewise.
4845 (vrmulhq_m_u8): Likewise.
4846 (vrmulhq_m_u32): Likewise.
4847 (vrmulhq_m_u16): Likewise.
4848 (vrshlq_m_s8): Likewise.
4849 (vrshlq_m_s32): Likewise.
4850 (vrshlq_m_s16): Likewise.
4851 (vrshlq_m_u8): Likewise.
4852 (vrshlq_m_u32): Likewise.
4853 (vrshlq_m_u16): Likewise.
4854 (vrshrq_m_n_s8): Likewise.
4855 (vrshrq_m_n_s32): Likewise.
4856 (vrshrq_m_n_s16): Likewise.
4857 (vrshrq_m_n_u8): Likewise.
4858 (vrshrq_m_n_u32): Likewise.
4859 (vrshrq_m_n_u16): Likewise.
4860 (vshlq_m_n_s8): Likewise.
4861 (vshlq_m_n_s32): Likewise.
4862 (vshlq_m_n_s16): Likewise.
4863 (vshlq_m_n_u8): Likewise.
4864 (vshlq_m_n_u32): Likewise.
4865 (vshlq_m_n_u16): Likewise.
4866 (vshrq_m_n_s8): Likewise.
4867 (vshrq_m_n_s32): Likewise.
4868 (vshrq_m_n_s16): Likewise.
4869 (vshrq_m_n_u8): Likewise.
4870 (vshrq_m_n_u32): Likewise.
4871 (vshrq_m_n_u16): Likewise.
4872 (vsliq_m_n_s8): Likewise.
4873 (vsliq_m_n_s32): Likewise.
4874 (vsliq_m_n_s16): Likewise.
4875 (vsliq_m_n_u8): Likewise.
4876 (vsliq_m_n_u32): Likewise.
4877 (vsliq_m_n_u16): Likewise.
4878 (vsubq_m_n_s8): Likewise.
4879 (vsubq_m_n_s32): Likewise.
4880 (vsubq_m_n_s16): Likewise.
4881 (vsubq_m_n_u8): Likewise.
4882 (vsubq_m_n_u32): Likewise.
4883 (vsubq_m_n_u16): Likewise.
4884 (__arm_vabdq_m_s8): Define intrinsic.
4885 (__arm_vabdq_m_s32): Likewise.
4886 (__arm_vabdq_m_s16): Likewise.
4887 (__arm_vabdq_m_u8): Likewise.
4888 (__arm_vabdq_m_u32): Likewise.
4889 (__arm_vabdq_m_u16): Likewise.
4890 (__arm_vaddq_m_n_s8): Likewise.
4891 (__arm_vaddq_m_n_s32): Likewise.
4892 (__arm_vaddq_m_n_s16): Likewise.
4893 (__arm_vaddq_m_n_u8): Likewise.
4894 (__arm_vaddq_m_n_u32): Likewise.
4895 (__arm_vaddq_m_n_u16): Likewise.
4896 (__arm_vaddq_m_s8): Likewise.
4897 (__arm_vaddq_m_s32): Likewise.
4898 (__arm_vaddq_m_s16): Likewise.
4899 (__arm_vaddq_m_u8): Likewise.
4900 (__arm_vaddq_m_u32): Likewise.
4901 (__arm_vaddq_m_u16): Likewise.
4902 (__arm_vandq_m_s8): Likewise.
4903 (__arm_vandq_m_s32): Likewise.
4904 (__arm_vandq_m_s16): Likewise.
4905 (__arm_vandq_m_u8): Likewise.
4906 (__arm_vandq_m_u32): Likewise.
4907 (__arm_vandq_m_u16): Likewise.
4908 (__arm_vbicq_m_s8): Likewise.
4909 (__arm_vbicq_m_s32): Likewise.
4910 (__arm_vbicq_m_s16): Likewise.
4911 (__arm_vbicq_m_u8): Likewise.
4912 (__arm_vbicq_m_u32): Likewise.
4913 (__arm_vbicq_m_u16): Likewise.
4914 (__arm_vbrsrq_m_n_s8): Likewise.
4915 (__arm_vbrsrq_m_n_s32): Likewise.
4916 (__arm_vbrsrq_m_n_s16): Likewise.
4917 (__arm_vbrsrq_m_n_u8): Likewise.
4918 (__arm_vbrsrq_m_n_u32): Likewise.
4919 (__arm_vbrsrq_m_n_u16): Likewise.
4920 (__arm_vcaddq_rot270_m_s8): Likewise.
4921 (__arm_vcaddq_rot270_m_s32): Likewise.
4922 (__arm_vcaddq_rot270_m_s16): Likewise.
4923 (__arm_vcaddq_rot270_m_u8): Likewise.
4924 (__arm_vcaddq_rot270_m_u32): Likewise.
4925 (__arm_vcaddq_rot270_m_u16): Likewise.
4926 (__arm_vcaddq_rot90_m_s8): Likewise.
4927 (__arm_vcaddq_rot90_m_s32): Likewise.
4928 (__arm_vcaddq_rot90_m_s16): Likewise.
4929 (__arm_vcaddq_rot90_m_u8): Likewise.
4930 (__arm_vcaddq_rot90_m_u32): Likewise.
4931 (__arm_vcaddq_rot90_m_u16): Likewise.
4932 (__arm_veorq_m_s8): Likewise.
4933 (__arm_veorq_m_s32): Likewise.
4934 (__arm_veorq_m_s16): Likewise.
4935 (__arm_veorq_m_u8): Likewise.
4936 (__arm_veorq_m_u32): Likewise.
4937 (__arm_veorq_m_u16): Likewise.
4938 (__arm_vhaddq_m_n_s8): Likewise.
4939 (__arm_vhaddq_m_n_s32): Likewise.
4940 (__arm_vhaddq_m_n_s16): Likewise.
4941 (__arm_vhaddq_m_n_u8): Likewise.
4942 (__arm_vhaddq_m_n_u32): Likewise.
4943 (__arm_vhaddq_m_n_u16): Likewise.
4944 (__arm_vhaddq_m_s8): Likewise.
4945 (__arm_vhaddq_m_s32): Likewise.
4946 (__arm_vhaddq_m_s16): Likewise.
4947 (__arm_vhaddq_m_u8): Likewise.
4948 (__arm_vhaddq_m_u32): Likewise.
4949 (__arm_vhaddq_m_u16): Likewise.
4950 (__arm_vhcaddq_rot270_m_s8): Likewise.
4951 (__arm_vhcaddq_rot270_m_s32): Likewise.
4952 (__arm_vhcaddq_rot270_m_s16): Likewise.
4953 (__arm_vhcaddq_rot90_m_s8): Likewise.
4954 (__arm_vhcaddq_rot90_m_s32): Likewise.
4955 (__arm_vhcaddq_rot90_m_s16): Likewise.
4956 (__arm_vhsubq_m_n_s8): Likewise.
4957 (__arm_vhsubq_m_n_s32): Likewise.
4958 (__arm_vhsubq_m_n_s16): Likewise.
4959 (__arm_vhsubq_m_n_u8): Likewise.
4960 (__arm_vhsubq_m_n_u32): Likewise.
4961 (__arm_vhsubq_m_n_u16): Likewise.
4962 (__arm_vhsubq_m_s8): Likewise.
4963 (__arm_vhsubq_m_s32): Likewise.
4964 (__arm_vhsubq_m_s16): Likewise.
4965 (__arm_vhsubq_m_u8): Likewise.
4966 (__arm_vhsubq_m_u32): Likewise.
4967 (__arm_vhsubq_m_u16): Likewise.
4968 (__arm_vmaxq_m_s8): Likewise.
4969 (__arm_vmaxq_m_s32): Likewise.
4970 (__arm_vmaxq_m_s16): Likewise.
4971 (__arm_vmaxq_m_u8): Likewise.
4972 (__arm_vmaxq_m_u32): Likewise.
4973 (__arm_vmaxq_m_u16): Likewise.
4974 (__arm_vminq_m_s8): Likewise.
4975 (__arm_vminq_m_s32): Likewise.
4976 (__arm_vminq_m_s16): Likewise.
4977 (__arm_vminq_m_u8): Likewise.
4978 (__arm_vminq_m_u32): Likewise.
4979 (__arm_vminq_m_u16): Likewise.
4980 (__arm_vmladavaq_p_s8): Likewise.
4981 (__arm_vmladavaq_p_s32): Likewise.
4982 (__arm_vmladavaq_p_s16): Likewise.
4983 (__arm_vmladavaq_p_u8): Likewise.
4984 (__arm_vmladavaq_p_u32): Likewise.
4985 (__arm_vmladavaq_p_u16): Likewise.
4986 (__arm_vmladavaxq_p_s8): Likewise.
4987 (__arm_vmladavaxq_p_s32): Likewise.
4988 (__arm_vmladavaxq_p_s16): Likewise.
4989 (__arm_vmlaq_m_n_s8): Likewise.
4990 (__arm_vmlaq_m_n_s32): Likewise.
4991 (__arm_vmlaq_m_n_s16): Likewise.
4992 (__arm_vmlaq_m_n_u8): Likewise.
4993 (__arm_vmlaq_m_n_u32): Likewise.
4994 (__arm_vmlaq_m_n_u16): Likewise.
4995 (__arm_vmlasq_m_n_s8): Likewise.
4996 (__arm_vmlasq_m_n_s32): Likewise.
4997 (__arm_vmlasq_m_n_s16): Likewise.
4998 (__arm_vmlasq_m_n_u8): Likewise.
4999 (__arm_vmlasq_m_n_u32): Likewise.
5000 (__arm_vmlasq_m_n_u16): Likewise.
5001 (__arm_vmlsdavaq_p_s8): Likewise.
5002 (__arm_vmlsdavaq_p_s32): Likewise.
5003 (__arm_vmlsdavaq_p_s16): Likewise.
5004 (__arm_vmlsdavaxq_p_s8): Likewise.
5005 (__arm_vmlsdavaxq_p_s32): Likewise.
5006 (__arm_vmlsdavaxq_p_s16): Likewise.
5007 (__arm_vmulhq_m_s8): Likewise.
5008 (__arm_vmulhq_m_s32): Likewise.
5009 (__arm_vmulhq_m_s16): Likewise.
5010 (__arm_vmulhq_m_u8): Likewise.
5011 (__arm_vmulhq_m_u32): Likewise.
5012 (__arm_vmulhq_m_u16): Likewise.
5013 (__arm_vmullbq_int_m_s8): Likewise.
5014 (__arm_vmullbq_int_m_s32): Likewise.
5015 (__arm_vmullbq_int_m_s16): Likewise.
5016 (__arm_vmullbq_int_m_u8): Likewise.
5017 (__arm_vmullbq_int_m_u32): Likewise.
5018 (__arm_vmullbq_int_m_u16): Likewise.
5019 (__arm_vmulltq_int_m_s8): Likewise.
5020 (__arm_vmulltq_int_m_s32): Likewise.
5021 (__arm_vmulltq_int_m_s16): Likewise.
5022 (__arm_vmulltq_int_m_u8): Likewise.
5023 (__arm_vmulltq_int_m_u32): Likewise.
5024 (__arm_vmulltq_int_m_u16): Likewise.
5025 (__arm_vmulq_m_n_s8): Likewise.
5026 (__arm_vmulq_m_n_s32): Likewise.
5027 (__arm_vmulq_m_n_s16): Likewise.
5028 (__arm_vmulq_m_n_u8): Likewise.
5029 (__arm_vmulq_m_n_u32): Likewise.
5030 (__arm_vmulq_m_n_u16): Likewise.
5031 (__arm_vmulq_m_s8): Likewise.
5032 (__arm_vmulq_m_s32): Likewise.
5033 (__arm_vmulq_m_s16): Likewise.
5034 (__arm_vmulq_m_u8): Likewise.
5035 (__arm_vmulq_m_u32): Likewise.
5036 (__arm_vmulq_m_u16): Likewise.
5037 (__arm_vornq_m_s8): Likewise.
5038 (__arm_vornq_m_s32): Likewise.
5039 (__arm_vornq_m_s16): Likewise.
5040 (__arm_vornq_m_u8): Likewise.
5041 (__arm_vornq_m_u32): Likewise.
5042 (__arm_vornq_m_u16): Likewise.
5043 (__arm_vorrq_m_s8): Likewise.
5044 (__arm_vorrq_m_s32): Likewise.
5045 (__arm_vorrq_m_s16): Likewise.
5046 (__arm_vorrq_m_u8): Likewise.
5047 (__arm_vorrq_m_u32): Likewise.
5048 (__arm_vorrq_m_u16): Likewise.
5049 (__arm_vqaddq_m_n_s8): Likewise.
5050 (__arm_vqaddq_m_n_s32): Likewise.
5051 (__arm_vqaddq_m_n_s16): Likewise.
5052 (__arm_vqaddq_m_n_u8): Likewise.
5053 (__arm_vqaddq_m_n_u32): Likewise.
5054 (__arm_vqaddq_m_n_u16): Likewise.
5055 (__arm_vqaddq_m_s8): Likewise.
5056 (__arm_vqaddq_m_s32): Likewise.
5057 (__arm_vqaddq_m_s16): Likewise.
5058 (__arm_vqaddq_m_u8): Likewise.
5059 (__arm_vqaddq_m_u32): Likewise.
5060 (__arm_vqaddq_m_u16): Likewise.
5061 (__arm_vqdmladhq_m_s8): Likewise.
5062 (__arm_vqdmladhq_m_s32): Likewise.
5063 (__arm_vqdmladhq_m_s16): Likewise.
5064 (__arm_vqdmladhxq_m_s8): Likewise.
5065 (__arm_vqdmladhxq_m_s32): Likewise.
5066 (__arm_vqdmladhxq_m_s16): Likewise.
5067 (__arm_vqdmlahq_m_n_s8): Likewise.
5068 (__arm_vqdmlahq_m_n_s32): Likewise.
5069 (__arm_vqdmlahq_m_n_s16): Likewise.
5070 (__arm_vqdmlahq_m_n_u8): Likewise.
5071 (__arm_vqdmlahq_m_n_u32): Likewise.
5072 (__arm_vqdmlahq_m_n_u16): Likewise.
5073 (__arm_vqdmlsdhq_m_s8): Likewise.
5074 (__arm_vqdmlsdhq_m_s32): Likewise.
5075 (__arm_vqdmlsdhq_m_s16): Likewise.
5076 (__arm_vqdmlsdhxq_m_s8): Likewise.
5077 (__arm_vqdmlsdhxq_m_s32): Likewise.
5078 (__arm_vqdmlsdhxq_m_s16): Likewise.
5079 (__arm_vqdmulhq_m_n_s8): Likewise.
5080 (__arm_vqdmulhq_m_n_s32): Likewise.
5081 (__arm_vqdmulhq_m_n_s16): Likewise.
5082 (__arm_vqdmulhq_m_s8): Likewise.
5083 (__arm_vqdmulhq_m_s32): Likewise.
5084 (__arm_vqdmulhq_m_s16): Likewise.
5085 (__arm_vqrdmladhq_m_s8): Likewise.
5086 (__arm_vqrdmladhq_m_s32): Likewise.
5087 (__arm_vqrdmladhq_m_s16): Likewise.
5088 (__arm_vqrdmladhxq_m_s8): Likewise.
5089 (__arm_vqrdmladhxq_m_s32): Likewise.
5090 (__arm_vqrdmladhxq_m_s16): Likewise.
5091 (__arm_vqrdmlahq_m_n_s8): Likewise.
5092 (__arm_vqrdmlahq_m_n_s32): Likewise.
5093 (__arm_vqrdmlahq_m_n_s16): Likewise.
5094 (__arm_vqrdmlahq_m_n_u8): Likewise.
5095 (__arm_vqrdmlahq_m_n_u32): Likewise.
5096 (__arm_vqrdmlahq_m_n_u16): Likewise.
5097 (__arm_vqrdmlashq_m_n_s8): Likewise.
5098 (__arm_vqrdmlashq_m_n_s32): Likewise.
5099 (__arm_vqrdmlashq_m_n_s16): Likewise.
5100 (__arm_vqrdmlashq_m_n_u8): Likewise.
5101 (__arm_vqrdmlashq_m_n_u32): Likewise.
5102 (__arm_vqrdmlashq_m_n_u16): Likewise.
5103 (__arm_vqrdmlsdhq_m_s8): Likewise.
5104 (__arm_vqrdmlsdhq_m_s32): Likewise.
5105 (__arm_vqrdmlsdhq_m_s16): Likewise.
5106 (__arm_vqrdmlsdhxq_m_s8): Likewise.
5107 (__arm_vqrdmlsdhxq_m_s32): Likewise.
5108 (__arm_vqrdmlsdhxq_m_s16): Likewise.
5109 (__arm_vqrdmulhq_m_n_s8): Likewise.
5110 (__arm_vqrdmulhq_m_n_s32): Likewise.
5111 (__arm_vqrdmulhq_m_n_s16): Likewise.
5112 (__arm_vqrdmulhq_m_s8): Likewise.
5113 (__arm_vqrdmulhq_m_s32): Likewise.
5114 (__arm_vqrdmulhq_m_s16): Likewise.
5115 (__arm_vqrshlq_m_s8): Likewise.
5116 (__arm_vqrshlq_m_s32): Likewise.
5117 (__arm_vqrshlq_m_s16): Likewise.
5118 (__arm_vqrshlq_m_u8): Likewise.
5119 (__arm_vqrshlq_m_u32): Likewise.
5120 (__arm_vqrshlq_m_u16): Likewise.
5121 (__arm_vqshlq_m_n_s8): Likewise.
5122 (__arm_vqshlq_m_n_s32): Likewise.
5123 (__arm_vqshlq_m_n_s16): Likewise.
5124 (__arm_vqshlq_m_n_u8): Likewise.
5125 (__arm_vqshlq_m_n_u32): Likewise.
5126 (__arm_vqshlq_m_n_u16): Likewise.
5127 (__arm_vqshlq_m_s8): Likewise.
5128 (__arm_vqshlq_m_s32): Likewise.
5129 (__arm_vqshlq_m_s16): Likewise.
5130 (__arm_vqshlq_m_u8): Likewise.
5131 (__arm_vqshlq_m_u32): Likewise.
5132 (__arm_vqshlq_m_u16): Likewise.
5133 (__arm_vqsubq_m_n_s8): Likewise.
5134 (__arm_vqsubq_m_n_s32): Likewise.
5135 (__arm_vqsubq_m_n_s16): Likewise.
5136 (__arm_vqsubq_m_n_u8): Likewise.
5137 (__arm_vqsubq_m_n_u32): Likewise.
5138 (__arm_vqsubq_m_n_u16): Likewise.
5139 (__arm_vqsubq_m_s8): Likewise.
5140 (__arm_vqsubq_m_s32): Likewise.
5141 (__arm_vqsubq_m_s16): Likewise.
5142 (__arm_vqsubq_m_u8): Likewise.
5143 (__arm_vqsubq_m_u32): Likewise.
5144 (__arm_vqsubq_m_u16): Likewise.
5145 (__arm_vrhaddq_m_s8): Likewise.
5146 (__arm_vrhaddq_m_s32): Likewise.
5147 (__arm_vrhaddq_m_s16): Likewise.
5148 (__arm_vrhaddq_m_u8): Likewise.
5149 (__arm_vrhaddq_m_u32): Likewise.
5150 (__arm_vrhaddq_m_u16): Likewise.
5151 (__arm_vrmulhq_m_s8): Likewise.
5152 (__arm_vrmulhq_m_s32): Likewise.
5153 (__arm_vrmulhq_m_s16): Likewise.
5154 (__arm_vrmulhq_m_u8): Likewise.
5155 (__arm_vrmulhq_m_u32): Likewise.
5156 (__arm_vrmulhq_m_u16): Likewise.
5157 (__arm_vrshlq_m_s8): Likewise.
5158 (__arm_vrshlq_m_s32): Likewise.
5159 (__arm_vrshlq_m_s16): Likewise.
5160 (__arm_vrshlq_m_u8): Likewise.
5161 (__arm_vrshlq_m_u32): Likewise.
5162 (__arm_vrshlq_m_u16): Likewise.
5163 (__arm_vrshrq_m_n_s8): Likewise.
5164 (__arm_vrshrq_m_n_s32): Likewise.
5165 (__arm_vrshrq_m_n_s16): Likewise.
5166 (__arm_vrshrq_m_n_u8): Likewise.
5167 (__arm_vrshrq_m_n_u32): Likewise.
5168 (__arm_vrshrq_m_n_u16): Likewise.
5169 (__arm_vshlq_m_n_s8): Likewise.
5170 (__arm_vshlq_m_n_s32): Likewise.
5171 (__arm_vshlq_m_n_s16): Likewise.
5172 (__arm_vshlq_m_n_u8): Likewise.
5173 (__arm_vshlq_m_n_u32): Likewise.
5174 (__arm_vshlq_m_n_u16): Likewise.
5175 (__arm_vshrq_m_n_s8): Likewise.
5176 (__arm_vshrq_m_n_s32): Likewise.
5177 (__arm_vshrq_m_n_s16): Likewise.
5178 (__arm_vshrq_m_n_u8): Likewise.
5179 (__arm_vshrq_m_n_u32): Likewise.
5180 (__arm_vshrq_m_n_u16): Likewise.
5181 (__arm_vsliq_m_n_s8): Likewise.
5182 (__arm_vsliq_m_n_s32): Likewise.
5183 (__arm_vsliq_m_n_s16): Likewise.
5184 (__arm_vsliq_m_n_u8): Likewise.
5185 (__arm_vsliq_m_n_u32): Likewise.
5186 (__arm_vsliq_m_n_u16): Likewise.
5187 (__arm_vsubq_m_n_s8): Likewise.
5188 (__arm_vsubq_m_n_s32): Likewise.
5189 (__arm_vsubq_m_n_s16): Likewise.
5190 (__arm_vsubq_m_n_u8): Likewise.
5191 (__arm_vsubq_m_n_u32): Likewise.
5192 (__arm_vsubq_m_n_u16): Likewise.
5193 (vqdmladhq_m): Define polymorphic variant.
5194 (vqdmladhxq_m): Likewise.
5195 (vqdmlsdhq_m): Likewise.
5196 (vqdmlsdhxq_m): Likewise.
5197 (vabdq_m): Likewise.
5198 (vandq_m): Likewise.
5199 (vbicq_m): Likewise.
5200 (vbrsrq_m_n): Likewise.
5201 (vcaddq_rot270_m): Likewise.
5202 (vcaddq_rot90_m): Likewise.
5203 (veorq_m): Likewise.
5204 (vmaxq_m): Likewise.
5205 (vminq_m): Likewise.
5206 (vmladavaq_p): Likewise.
5207 (vmlaq_m_n): Likewise.
5208 (vmlasq_m_n): Likewise.
5209 (vmulhq_m): Likewise.
5210 (vmullbq_int_m): Likewise.
5211 (vmulltq_int_m): Likewise.
5212 (vornq_m): Likewise.
5213 (vorrq_m): Likewise.
5214 (vqdmlahq_m_n): Likewise.
5215 (vqrdmlahq_m_n): Likewise.
5216 (vqrdmlashq_m_n): Likewise.
5217 (vqrshlq_m): Likewise.
5218 (vqshlq_m_n): Likewise.
5219 (vqshlq_m): Likewise.
5220 (vrhaddq_m): Likewise.
5221 (vrmulhq_m): Likewise.
5222 (vrshlq_m): Likewise.
5223 (vrshrq_m_n): Likewise.
5224 (vshlq_m_n): Likewise.
5225 (vshrq_m_n): Likewise.
5226 (vsliq_m): Likewise.
5227 (vaddq_m_n): Likewise.
5228 (vaddq_m): Likewise.
5229 (vhaddq_m_n): Likewise.
5230 (vhaddq_m): Likewise.
5231 (vhcaddq_rot270_m): Likewise.
5232 (vhcaddq_rot90_m): Likewise.
5233 (vhsubq_m): Likewise.
5234 (vhsubq_m_n): Likewise.
5235 (vmulq_m_n): Likewise.
5236 (vmulq_m): Likewise.
5237 (vqaddq_m_n): Likewise.
5238 (vqaddq_m): Likewise.
5239 (vqdmulhq_m_n): Likewise.
5240 (vqdmulhq_m): Likewise.
5241 (vsubq_m_n): Likewise.
5242 (vsliq_m_n): Likewise.
5243 (vqsubq_m_n): Likewise.
5244 (vqsubq_m): Likewise.
5245 (vqrdmulhq_m): Likewise.
5246 (vqrdmulhq_m_n): Likewise.
5247 (vqrdmlsdhxq_m): Likewise.
5248 (vqrdmlsdhq_m): Likewise.
5249 (vqrdmladhq_m): Likewise.
5250 (vqrdmladhxq_m): Likewise.
5251 (vmlsdavaxq_p): Likewise.
5252 (vmlsdavaq_p): Likewise.
5253 (vmladavaxq_p): Likewise.
5254 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
5255 builtin qualifier.
5256 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
5257 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
5258 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
5259 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
5260 * config/arm/mve.md (VHSUBQ_M): Define iterators.
5261 (VSLIQ_M_N): Likewise.
5262 (VQRDMLAHQ_M_N): Likewise.
5263 (VRSHLQ_M): Likewise.
5264 (VMINQ_M): Likewise.
5265 (VMULLBQ_INT_M): Likewise.
5266 (VMULHQ_M): Likewise.
5267 (VMULQ_M): Likewise.
5268 (VHSUBQ_M_N): Likewise.
5269 (VHADDQ_M_N): Likewise.
5270 (VORRQ_M): Likewise.
5271 (VRMULHQ_M): Likewise.
5272 (VQADDQ_M): Likewise.
5273 (VRSHRQ_M_N): Likewise.
5274 (VQSUBQ_M_N): Likewise.
5275 (VADDQ_M): Likewise.
5276 (VORNQ_M): Likewise.
5277 (VQDMLAHQ_M_N): Likewise.
5278 (VRHADDQ_M): Likewise.
5279 (VQSHLQ_M): Likewise.
5280 (VANDQ_M): Likewise.
5281 (VBICQ_M): Likewise.
5282 (VSHLQ_M_N): Likewise.
5283 (VCADDQ_ROT270_M): Likewise.
5284 (VQRSHLQ_M): Likewise.
5285 (VQADDQ_M_N): Likewise.
5286 (VADDQ_M_N): Likewise.
5287 (VMAXQ_M): Likewise.
5288 (VQSUBQ_M): Likewise.
5289 (VMLASQ_M_N): Likewise.
5290 (VMLADAVAQ_P): Likewise.
5291 (VBRSRQ_M_N): Likewise.
5292 (VMULQ_M_N): Likewise.
5293 (VCADDQ_ROT90_M): Likewise.
5294 (VMULLTQ_INT_M): Likewise.
5295 (VEORQ_M): Likewise.
5296 (VSHRQ_M_N): Likewise.
5297 (VSUBQ_M_N): Likewise.
5298 (VHADDQ_M): Likewise.
5299 (VABDQ_M): Likewise.
5300 (VQRDMLASHQ_M_N): Likewise.
5301 (VMLAQ_M_N): Likewise.
5302 (VQSHLQ_M_N): Likewise.
5303 (mve_vabdq_m_<supf><mode>): Define RTL pattern.
5304 (mve_vaddq_m_n_<supf><mode>): Likewise.
5305 (mve_vaddq_m_<supf><mode>): Likewise.
5306 (mve_vandq_m_<supf><mode>): Likewise.
5307 (mve_vbicq_m_<supf><mode>): Likewise.
5308 (mve_vbrsrq_m_n_<supf><mode>): Likewise.
5309 (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
5310 (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
5311 (mve_veorq_m_<supf><mode>): Likewise.
5312 (mve_vhaddq_m_n_<supf><mode>): Likewise.
5313 (mve_vhaddq_m_<supf><mode>): Likewise.
5314 (mve_vhsubq_m_n_<supf><mode>): Likewise.
5315 (mve_vhsubq_m_<supf><mode>): Likewise.
5316 (mve_vmaxq_m_<supf><mode>): Likewise.
5317 (mve_vminq_m_<supf><mode>): Likewise.
5318 (mve_vmladavaq_p_<supf><mode>): Likewise.
5319 (mve_vmlaq_m_n_<supf><mode>): Likewise.
5320 (mve_vmlasq_m_n_<supf><mode>): Likewise.
5321 (mve_vmulhq_m_<supf><mode>): Likewise.
5322 (mve_vmullbq_int_m_<supf><mode>): Likewise.
5323 (mve_vmulltq_int_m_<supf><mode>): Likewise.
5324 (mve_vmulq_m_n_<supf><mode>): Likewise.
5325 (mve_vmulq_m_<supf><mode>): Likewise.
5326 (mve_vornq_m_<supf><mode>): Likewise.
5327 (mve_vorrq_m_<supf><mode>): Likewise.
5328 (mve_vqaddq_m_n_<supf><mode>): Likewise.
5329 (mve_vqaddq_m_<supf><mode>): Likewise.
5330 (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
5331 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
5332 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
5333 (mve_vqrshlq_m_<supf><mode>): Likewise.
5334 (mve_vqshlq_m_n_<supf><mode>): Likewise.
5335 (mve_vqshlq_m_<supf><mode>): Likewise.
5336 (mve_vqsubq_m_n_<supf><mode>): Likewise.
5337 (mve_vqsubq_m_<supf><mode>): Likewise.
5338 (mve_vrhaddq_m_<supf><mode>): Likewise.
5339 (mve_vrmulhq_m_<supf><mode>): Likewise.
5340 (mve_vrshlq_m_<supf><mode>): Likewise.
5341 (mve_vrshrq_m_n_<supf><mode>): Likewise.
5342 (mve_vshlq_m_n_<supf><mode>): Likewise.
5343 (mve_vshrq_m_n_<supf><mode>): Likewise.
5344 (mve_vsliq_m_n_<supf><mode>): Likewise.
5345 (mve_vsubq_m_n_<supf><mode>): Likewise.
5346 (mve_vhcaddq_rot270_m_s<mode>): Likewise.
5347 (mve_vhcaddq_rot90_m_s<mode>): Likewise.
5348 (mve_vmladavaxq_p_s<mode>): Likewise.
5349 (mve_vmlsdavaq_p_s<mode>): Likewise.
5350 (mve_vmlsdavaxq_p_s<mode>): Likewise.
5351 (mve_vqdmladhq_m_s<mode>): Likewise.
5352 (mve_vqdmladhxq_m_s<mode>): Likewise.
5353 (mve_vqdmlsdhq_m_s<mode>): Likewise.
5354 (mve_vqdmlsdhxq_m_s<mode>): Likewise.
5355 (mve_vqdmulhq_m_n_s<mode>): Likewise.
5356 (mve_vqdmulhq_m_s<mode>): Likewise.
5357 (mve_vqrdmladhq_m_s<mode>): Likewise.
5358 (mve_vqrdmladhxq_m_s<mode>): Likewise.
5359 (mve_vqrdmlsdhq_m_s<mode>): Likewise.
5360 (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
5361 (mve_vqrdmulhq_m_n_s<mode>): Likewise.
5362 (mve_vqrdmulhq_m_s<mode>): Likewise.
5364 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5365 Mihail Ionescu <mihail.ionescu@arm.com>
5366 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5368 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
5369 Define builtin qualifier.
5370 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
5371 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
5372 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
5373 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
5374 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
5375 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
5376 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
5377 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
5378 (vsubq_m_s8): Likewise.
5379 (vcvtq_m_n_f16_u16): Likewise.
5380 (vqshluq_m_n_s8): Likewise.
5381 (vabavq_p_s8): Likewise.
5382 (vsriq_m_n_u8): Likewise.
5383 (vshlq_m_u8): Likewise.
5384 (vsubq_m_u8): Likewise.
5385 (vabavq_p_u8): Likewise.
5386 (vshlq_m_s8): Likewise.
5387 (vcvtq_m_n_f16_s16): Likewise.
5388 (vsriq_m_n_s16): Likewise.
5389 (vsubq_m_s16): Likewise.
5390 (vcvtq_m_n_f32_u32): Likewise.
5391 (vqshluq_m_n_s16): Likewise.
5392 (vabavq_p_s16): Likewise.
5393 (vsriq_m_n_u16): Likewise.
5394 (vshlq_m_u16): Likewise.
5395 (vsubq_m_u16): Likewise.
5396 (vabavq_p_u16): Likewise.
5397 (vshlq_m_s16): Likewise.
5398 (vcvtq_m_n_f32_s32): Likewise.
5399 (vsriq_m_n_s32): Likewise.
5400 (vsubq_m_s32): Likewise.
5401 (vqshluq_m_n_s32): Likewise.
5402 (vabavq_p_s32): Likewise.
5403 (vsriq_m_n_u32): Likewise.
5404 (vshlq_m_u32): Likewise.
5405 (vsubq_m_u32): Likewise.
5406 (vabavq_p_u32): Likewise.
5407 (vshlq_m_s32): Likewise.
5408 (__arm_vsriq_m_n_s8): Define intrinsic.
5409 (__arm_vsubq_m_s8): Likewise.
5410 (__arm_vqshluq_m_n_s8): Likewise.
5411 (__arm_vabavq_p_s8): Likewise.
5412 (__arm_vsriq_m_n_u8): Likewise.
5413 (__arm_vshlq_m_u8): Likewise.
5414 (__arm_vsubq_m_u8): Likewise.
5415 (__arm_vabavq_p_u8): Likewise.
5416 (__arm_vshlq_m_s8): Likewise.
5417 (__arm_vsriq_m_n_s16): Likewise.
5418 (__arm_vsubq_m_s16): Likewise.
5419 (__arm_vqshluq_m_n_s16): Likewise.
5420 (__arm_vabavq_p_s16): Likewise.
5421 (__arm_vsriq_m_n_u16): Likewise.
5422 (__arm_vshlq_m_u16): Likewise.
5423 (__arm_vsubq_m_u16): Likewise.
5424 (__arm_vabavq_p_u16): Likewise.
5425 (__arm_vshlq_m_s16): Likewise.
5426 (__arm_vsriq_m_n_s32): Likewise.
5427 (__arm_vsubq_m_s32): Likewise.
5428 (__arm_vqshluq_m_n_s32): Likewise.
5429 (__arm_vabavq_p_s32): Likewise.
5430 (__arm_vsriq_m_n_u32): Likewise.
5431 (__arm_vshlq_m_u32): Likewise.
5432 (__arm_vsubq_m_u32): Likewise.
5433 (__arm_vabavq_p_u32): Likewise.
5434 (__arm_vshlq_m_s32): Likewise.
5435 (__arm_vcvtq_m_n_f16_u16): Likewise.
5436 (__arm_vcvtq_m_n_f16_s16): Likewise.
5437 (__arm_vcvtq_m_n_f32_u32): Likewise.
5438 (__arm_vcvtq_m_n_f32_s32): Likewise.
5439 (vcvtq_m_n): Define polymorphic variant.
5440 (vqshluq_m_n): Likewise.
5441 (vshlq_m): Likewise.
5442 (vsriq_m_n): Likewise.
5443 (vsubq_m): Likewise.
5444 (vabavq_p): Likewise.
5445 * config/arm/arm_mve_builtins.def
5446 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
5447 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
5448 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
5449 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
5450 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
5451 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
5452 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
5453 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
5454 * config/arm/mve.md (VABAVQ_P): Define iterator.
5455 (VSHLQ_M): Likewise.
5456 (VSRIQ_M_N): Likewise.
5457 (VSUBQ_M): Likewise.
5458 (VCVTQ_M_N_TO_F): Likewise.
5459 (mve_vabavq_p_<supf><mode>): Define RTL pattern.
5460 (mve_vqshluq_m_n_s<mode>): Likewise.
5461 (mve_vshlq_m_<supf><mode>): Likewise.
5462 (mve_vsriq_m_n_<supf><mode>): Likewise.
5463 (mve_vsubq_m_<supf><mode>): Likewise.
5464 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
5466 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
5467 Mihail Ionescu <mihail.ionescu@arm.com>
5468 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5470 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
5471 (vrmlsldavhaq_s32): Likewise.
5472 (vrmlsldavhaxq_s32): Likewise.
5473 (vaddlvaq_p_s32): Likewise.
5474 (vcvtbq_m_f16_f32): Likewise.
5475 (vcvtbq_m_f32_f16): Likewise.
5476 (vcvttq_m_f16_f32): Likewise.
5477 (vcvttq_m_f32_f16): Likewise.
5478 (vrev16q_m_s8): Likewise.
5479 (vrev32q_m_f16): Likewise.
5480 (vrmlaldavhq_p_s32): Likewise.
5481 (vrmlaldavhxq_p_s32): Likewise.
5482 (vrmlsldavhq_p_s32): Likewise.
5483 (vrmlsldavhxq_p_s32): Likewise.
5484 (vaddlvaq_p_u32): Likewise.
5485 (vrev16q_m_u8): Likewise.
5486 (vrmlaldavhq_p_u32): Likewise.
5487 (vmvnq_m_n_s16): Likewise.
5488 (vorrq_m_n_s16): Likewise.
5489 (vqrshrntq_n_s16): Likewise.
5490 (vqshrnbq_n_s16): Likewise.
5491 (vqshrntq_n_s16): Likewise.
5492 (vrshrnbq_n_s16): Likewise.
5493 (vrshrntq_n_s16): Likewise.
5494 (vshrnbq_n_s16): Likewise.
5495 (vshrntq_n_s16): Likewise.
5496 (vcmlaq_f16): Likewise.
5497 (vcmlaq_rot180_f16): Likewise.
5498 (vcmlaq_rot270_f16): Likewise.
5499 (vcmlaq_rot90_f16): Likewise.
5500 (vfmaq_f16): Likewise.
5501 (vfmaq_n_f16): Likewise.
5502 (vfmasq_n_f16): Likewise.
5503 (vfmsq_f16): Likewise.
5504 (vmlaldavaq_s16): Likewise.
5505 (vmlaldavaxq_s16): Likewise.
5506 (vmlsldavaq_s16): Likewise.
5507 (vmlsldavaxq_s16): Likewise.
5508 (vabsq_m_f16): Likewise.
5509 (vcvtmq_m_s16_f16): Likewise.
5510 (vcvtnq_m_s16_f16): Likewise.
5511 (vcvtpq_m_s16_f16): Likewise.
5512 (vcvtq_m_s16_f16): Likewise.
5513 (vdupq_m_n_f16): Likewise.
5514 (vmaxnmaq_m_f16): Likewise.
5515 (vmaxnmavq_p_f16): Likewise.
5516 (vmaxnmvq_p_f16): Likewise.
5517 (vminnmaq_m_f16): Likewise.
5518 (vminnmavq_p_f16): Likewise.
5519 (vminnmvq_p_f16): Likewise.
5520 (vmlaldavq_p_s16): Likewise.
5521 (vmlaldavxq_p_s16): Likewise.
5522 (vmlsldavq_p_s16): Likewise.
5523 (vmlsldavxq_p_s16): Likewise.
5524 (vmovlbq_m_s8): Likewise.
5525 (vmovltq_m_s8): Likewise.
5526 (vmovnbq_m_s16): Likewise.
5527 (vmovntq_m_s16): Likewise.
5528 (vnegq_m_f16): Likewise.
5529 (vpselq_f16): Likewise.
5530 (vqmovnbq_m_s16): Likewise.
5531 (vqmovntq_m_s16): Likewise.
5532 (vrev32q_m_s8): Likewise.
5533 (vrev64q_m_f16): Likewise.
5534 (vrndaq_m_f16): Likewise.
5535 (vrndmq_m_f16): Likewise.
5536 (vrndnq_m_f16): Likewise.
5537 (vrndpq_m_f16): Likewise.
5538 (vrndq_m_f16): Likewise.
5539 (vrndxq_m_f16): Likewise.
5540 (vcmpeqq_m_n_f16): Likewise.
5541 (vcmpgeq_m_f16): Likewise.
5542 (vcmpgeq_m_n_f16): Likewise.
5543 (vcmpgtq_m_f16): Likewise.
5544 (vcmpgtq_m_n_f16): Likewise.
5545 (vcmpleq_m_f16): Likewise.
5546 (vcmpleq_m_n_f16): Likewise.
5547 (vcmpltq_m_f16): Likewise.
5548 (vcmpltq_m_n_f16): Likewise.
5549 (vcmpneq_m_f16): Likewise.
5550 (vcmpneq_m_n_f16): Likewise.
5551 (vmvnq_m_n_u16): Likewise.
5552 (vorrq_m_n_u16): Likewise.
5553 (vqrshruntq_n_s16): Likewise.
5554 (vqshrunbq_n_s16): Likewise.
5555 (vqshruntq_n_s16): Likewise.
5556 (vcvtmq_m_u16_f16): Likewise.
5557 (vcvtnq_m_u16_f16): Likewise.
5558 (vcvtpq_m_u16_f16): Likewise.
5559 (vcvtq_m_u16_f16): Likewise.
5560 (vqmovunbq_m_s16): Likewise.
5561 (vqmovuntq_m_s16): Likewise.
5562 (vqrshrntq_n_u16): Likewise.
5563 (vqshrnbq_n_u16): Likewise.
5564 (vqshrntq_n_u16): Likewise.
5565 (vrshrnbq_n_u16): Likewise.
5566 (vrshrntq_n_u16): Likewise.
5567 (vshrnbq_n_u16): Likewise.
5568 (vshrntq_n_u16): Likewise.
5569 (vmlaldavaq_u16): Likewise.
5570 (vmlaldavaxq_u16): Likewise.
5571 (vmlaldavq_p_u16): Likewise.
5572 (vmlaldavxq_p_u16): Likewise.
5573 (vmovlbq_m_u8): Likewise.
5574 (vmovltq_m_u8): Likewise.
5575 (vmovnbq_m_u16): Likewise.
5576 (vmovntq_m_u16): Likewise.
5577 (vqmovnbq_m_u16): Likewise.
5578 (vqmovntq_m_u16): Likewise.
5579 (vrev32q_m_u8): Likewise.
5580 (vmvnq_m_n_s32): Likewise.
5581 (vorrq_m_n_s32): Likewise.
5582 (vqrshrntq_n_s32): Likewise.
5583 (vqshrnbq_n_s32): Likewise.
5584 (vqshrntq_n_s32): Likewise.
5585 (vrshrnbq_n_s32): Likewise.
5586 (vrshrntq_n_s32): Likewise.
5587 (vshrnbq_n_s32): Likewise.
5588 (vshrntq_n_s32): Likewise.
5589 (vcmlaq_f32): Likewise.
5590 (vcmlaq_rot180_f32): Likewise.
5591 (vcmlaq_rot270_f32): Likewise.
5592 (vcmlaq_rot90_f32): Likewise.
5593 (vfmaq_f32): Likewise.
5594 (vfmaq_n_f32): Likewise.
5595 (vfmasq_n_f32): Likewise.
5596 (vfmsq_f32): Likewise.
5597 (vmlaldavaq_s32): Likewise.
5598 (vmlaldavaxq_s32): Likewise.
5599 (vmlsldavaq_s32): Likewise.
5600 (vmlsldavaxq_s32): Likewise.
5601 (vabsq_m_f32): Likewise.
5602 (vcvtmq_m_s32_f32): Likewise.
5603 (vcvtnq_m_s32_f32): Likewise.
5604 (vcvtpq_m_s32_f32): Likewise.
5605 (vcvtq_m_s32_f32): Likewise.
5606 (vdupq_m_n_f32): Likewise.
5607 (vmaxnmaq_m_f32): Likewise.
5608 (vmaxnmavq_p_f32): Likewise.
5609 (vmaxnmvq_p_f32): Likewise.
5610 (vminnmaq_m_f32): Likewise.
5611 (vminnmavq_p_f32): Likewise.
5612 (vminnmvq_p_f32): Likewise.
5613 (vmlaldavq_p_s32): Likewise.
5614 (vmlaldavxq_p_s32): Likewise.
5615 (vmlsldavq_p_s32): Likewise.
5616 (vmlsldavxq_p_s32): Likewise.
5617 (vmovlbq_m_s16): Likewise.
5618 (vmovltq_m_s16): Likewise.
5619 (vmovnbq_m_s32): Likewise.
5620 (vmovntq_m_s32): Likewise.
5621 (vnegq_m_f32): Likewise.
5622 (vpselq_f32): Likewise.
5623 (vqmovnbq_m_s32): Likewise.
5624 (vqmovntq_m_s32): Likewise.
5625 (vrev32q_m_s16): Likewise.
5626 (vrev64q_m_f32): Likewise.
5627 (vrndaq_m_f32): Likewise.
5628 (vrndmq_m_f32): Likewise.
5629 (vrndnq_m_f32): Likewise.
5630 (vrndpq_m_f32): Likewise.
5631 (vrndq_m_f32): Likewise.
5632 (vrndxq_m_f32): Likewise.
5633 (vcmpeqq_m_n_f32): Likewise.
5634 (vcmpgeq_m_f32): Likewise.
5635 (vcmpgeq_m_n_f32): Likewise.
5636 (vcmpgtq_m_f32): Likewise.
5637 (vcmpgtq_m_n_f32): Likewise.
5638 (vcmpleq_m_f32): Likewise.
5639 (vcmpleq_m_n_f32): Likewise.
5640 (vcmpltq_m_f32): Likewise.
5641 (vcmpltq_m_n_f32): Likewise.
5642 (vcmpneq_m_f32): Likewise.
5643 (vcmpneq_m_n_f32): Likewise.
5644 (vmvnq_m_n_u32): Likewise.
5645 (vorrq_m_n_u32): Likewise.
5646 (vqrshruntq_n_s32): Likewise.
5647 (vqshrunbq_n_s32): Likewise.
5648 (vqshruntq_n_s32): Likewise.
5649 (vcvtmq_m_u32_f32): Likewise.
5650 (vcvtnq_m_u32_f32): Likewise.
5651 (vcvtpq_m_u32_f32): Likewise.
5652 (vcvtq_m_u32_f32): Likewise.
5653 (vqmovunbq_m_s32): Likewise.
5654 (vqmovuntq_m_s32): Likewise.
5655 (vqrshrntq_n_u32): Likewise.
5656 (vqshrnbq_n_u32): Likewise.
5657 (vqshrntq_n_u32): Likewise.
5658 (vrshrnbq_n_u32): Likewise.
5659 (vrshrntq_n_u32): Likewise.
5660 (vshrnbq_n_u32): Likewise.
5661 (vshrntq_n_u32): Likewise.
5662 (vmlaldavaq_u32): Likewise.
5663 (vmlaldavaxq_u32): Likewise.
5664 (vmlaldavq_p_u32): Likewise.
5665 (vmlaldavxq_p_u32): Likewise.
5666 (vmovlbq_m_u16): Likewise.
5667 (vmovltq_m_u16): Likewise.
5668 (vmovnbq_m_u32): Likewise.
5669 (vmovntq_m_u32): Likewise.
5670 (vqmovnbq_m_u32): Likewise.
5671 (vqmovntq_m_u32): Likewise.
5672 (vrev32q_m_u16): Likewise.
5673 (__arm_vrmlaldavhaxq_s32): Define intrinsic.
5674 (__arm_vrmlsldavhaq_s32): Likewise.
5675 (__arm_vrmlsldavhaxq_s32): Likewise.
5676 (__arm_vaddlvaq_p_s32): Likewise.
5677 (__arm_vrev16q_m_s8): Likewise.
5678 (__arm_vrmlaldavhq_p_s32): Likewise.
5679 (__arm_vrmlaldavhxq_p_s32): Likewise.
5680 (__arm_vrmlsldavhq_p_s32): Likewise.
5681 (__arm_vrmlsldavhxq_p_s32): Likewise.
5682 (__arm_vaddlvaq_p_u32): Likewise.
5683 (__arm_vrev16q_m_u8): Likewise.
5684 (__arm_vrmlaldavhq_p_u32): Likewise.
5685 (__arm_vmvnq_m_n_s16): Likewise.
5686 (__arm_vorrq_m_n_s16): Likewise.
5687 (__arm_vqrshrntq_n_s16): Likewise.
5688 (__arm_vqshrnbq_n_s16): Likewise.
5689 (__arm_vqshrntq_n_s16): Likewise.
5690 (__arm_vrshrnbq_n_s16): Likewise.
5691 (__arm_vrshrntq_n_s16): Likewise.
5692 (__arm_vshrnbq_n_s16): Likewise.
5693 (__arm_vshrntq_n_s16): Likewise.
5694 (__arm_vmlaldavaq_s16): Likewise.
5695 (__arm_vmlaldavaxq_s16): Likewise.
5696 (__arm_vmlsldavaq_s16): Likewise.
5697 (__arm_vmlsldavaxq_s16): Likewise.
5698 (__arm_vmlaldavq_p_s16): Likewise.
5699 (__arm_vmlaldavxq_p_s16): Likewise.
5700 (__arm_vmlsldavq_p_s16): Likewise.
5701 (__arm_vmlsldavxq_p_s16): Likewise.
5702 (__arm_vmovlbq_m_s8): Likewise.
5703 (__arm_vmovltq_m_s8): Likewise.
5704 (__arm_vmovnbq_m_s16): Likewise.
5705 (__arm_vmovntq_m_s16): Likewise.
5706 (__arm_vqmovnbq_m_s16): Likewise.
5707 (__arm_vqmovntq_m_s16): Likewise.
5708 (__arm_vrev32q_m_s8): Likewise.
5709 (__arm_vmvnq_m_n_u16): Likewise.
5710 (__arm_vorrq_m_n_u16): Likewise.
5711 (__arm_vqrshruntq_n_s16): Likewise.
5712 (__arm_vqshrunbq_n_s16): Likewise.
5713 (__arm_vqshruntq_n_s16): Likewise.
5714 (__arm_vqmovunbq_m_s16): Likewise.
5715 (__arm_vqmovuntq_m_s16): Likewise.
5716 (__arm_vqrshrntq_n_u16): Likewise.
5717 (__arm_vqshrnbq_n_u16): Likewise.
5718 (__arm_vqshrntq_n_u16): Likewise.
5719 (__arm_vrshrnbq_n_u16): Likewise.
5720 (__arm_vrshrntq_n_u16): Likewise.
5721 (__arm_vshrnbq_n_u16): Likewise.
5722 (__arm_vshrntq_n_u16): Likewise.
5723 (__arm_vmlaldavaq_u16): Likewise.
5724 (__arm_vmlaldavaxq_u16): Likewise.
5725 (__arm_vmlaldavq_p_u16): Likewise.
5726 (__arm_vmlaldavxq_p_u16): Likewise.
5727 (__arm_vmovlbq_m_u8): Likewise.
5728 (__arm_vmovltq_m_u8): Likewise.
5729 (__arm_vmovnbq_m_u16): Likewise.
5730 (__arm_vmovntq_m_u16): Likewise.
5731 (__arm_vqmovnbq_m_u16): Likewise.
5732 (__arm_vqmovntq_m_u16): Likewise.
5733 (__arm_vrev32q_m_u8): Likewise.
5734 (__arm_vmvnq_m_n_s32): Likewise.
5735 (__arm_vorrq_m_n_s32): Likewise.
5736 (__arm_vqrshrntq_n_s32): Likewise.
5737 (__arm_vqshrnbq_n_s32): Likewise.
5738 (__arm_vqshrntq_n_s32): Likewise.
5739 (__arm_vrshrnbq_n_s32): Likewise.
5740 (__arm_vrshrntq_n_s32): Likewise.
5741 (__arm_vshrnbq_n_s32): Likewise.
5742 (__arm_vshrntq_n_s32): Likewise.
5743 (__arm_vmlaldavaq_s32): Likewise.
5744 (__arm_vmlaldavaxq_s32): Likewise.
5745 (__arm_vmlsldavaq_s32): Likewise.
5746 (__arm_vmlsldavaxq_s32): Likewise.
5747 (__arm_vmlaldavq_p_s32): Likewise.
5748 (__arm_vmlaldavxq_p_s32): Likewise.
5749 (__arm_vmlsldavq_p_s32): Likewise.
5750 (__arm_vmlsldavxq_p_s32): Likewise.
5751 (__arm_vmovlbq_m_s16): Likewise.
5752 (__arm_vmovltq_m_s16): Likewise.
5753 (__arm_vmovnbq_m_s32): Likewise.
5754 (__arm_vmovntq_m_s32): Likewise.
5755 (__arm_vqmovnbq_m_s32): Likewise.
5756 (__arm_vqmovntq_m_s32): Likewise.
5757 (__arm_vrev32q_m_s16): Likewise.
5758 (__arm_vmvnq_m_n_u32): Likewise.
5759 (__arm_vorrq_m_n_u32): Likewise.
5760 (__arm_vqrshruntq_n_s32): Likewise.
5761 (__arm_vqshrunbq_n_s32): Likewise.
5762 (__arm_vqshruntq_n_s32): Likewise.
5763 (__arm_vqmovunbq_m_s32): Likewise.
5764 (__arm_vqmovuntq_m_s32): Likewise.
5765 (__arm_vqrshrntq_n_u32): Likewise.
5766 (__arm_vqshrnbq_n_u32): Likewise.
5767 (__arm_vqshrntq_n_u32): Likewise.
5768 (__arm_vrshrnbq_n_u32): Likewise.
5769 (__arm_vrshrntq_n_u32): Likewise.
5770 (__arm_vshrnbq_n_u32): Likewise.
5771 (__arm_vshrntq_n_u32): Likewise.
5772 (__arm_vmlaldavaq_u32): Likewise.
5773 (__arm_vmlaldavaxq_u32): Likewise.
5774 (__arm_vmlaldavq_p_u32): Likewise.
5775 (__arm_vmlaldavxq_p_u32): Likewise.
5776 (__arm_vmovlbq_m_u16): Likewise.
5777 (__arm_vmovltq_m_u16): Likewise.
5778 (__arm_vmovnbq_m_u32): Likewise.
5779 (__arm_vmovntq_m_u32): Likewise.
5780 (__arm_vqmovnbq_m_u32): Likewise.
5781 (__arm_vqmovntq_m_u32): Likewise.
5782 (__arm_vrev32q_m_u16): Likewise.
5783 (__arm_vcvtbq_m_f16_f32): Likewise.
5784 (__arm_vcvtbq_m_f32_f16): Likewise.
5785 (__arm_vcvttq_m_f16_f32): Likewise.
5786 (__arm_vcvttq_m_f32_f16): Likewise.
5787 (__arm_vrev32q_m_f16): Likewise.
5788 (__arm_vcmlaq_f16): Likewise.
5789 (__arm_vcmlaq_rot180_f16): Likewise.
5790 (__arm_vcmlaq_rot270_f16): Likewise.
5791 (__arm_vcmlaq_rot90_f16): Likewise.
5792 (__arm_vfmaq_f16): Likewise.
5793 (__arm_vfmaq_n_f16): Likewise.
5794 (__arm_vfmasq_n_f16): Likewise.
5795 (__arm_vfmsq_f16): Likewise.
5796 (__arm_vabsq_m_f16): Likewise.
5797 (__arm_vcvtmq_m_s16_f16): Likewise.
5798 (__arm_vcvtnq_m_s16_f16): Likewise.
5799 (__arm_vcvtpq_m_s16_f16): Likewise.
5800 (__arm_vcvtq_m_s16_f16): Likewise.
5801 (__arm_vdupq_m_n_f16): Likewise.
5802 (__arm_vmaxnmaq_m_f16): Likewise.
5803 (__arm_vmaxnmavq_p_f16): Likewise.
5804 (__arm_vmaxnmvq_p_f16): Likewise.
5805 (__arm_vminnmaq_m_f16): Likewise.
5806 (__arm_vminnmavq_p_f16): Likewise.
5807 (__arm_vminnmvq_p_f16): Likewise.
5808 (__arm_vnegq_m_f16): Likewise.
5809 (__arm_vpselq_f16): Likewise.
5810 (__arm_vrev64q_m_f16): Likewise.
5811 (__arm_vrndaq_m_f16): Likewise.
5812 (__arm_vrndmq_m_f16): Likewise.
5813 (__arm_vrndnq_m_f16): Likewise.
5814 (__arm_vrndpq_m_f16): Likewise.
5815 (__arm_vrndq_m_f16): Likewise.
5816 (__arm_vrndxq_m_f16): Likewise.
5817 (__arm_vcmpeqq_m_n_f16): Likewise.
5818 (__arm_vcmpgeq_m_f16): Likewise.
5819 (__arm_vcmpgeq_m_n_f16): Likewise.
5820 (__arm_vcmpgtq_m_f16): Likewise.
5821 (__arm_vcmpgtq_m_n_f16): Likewise.
5822 (__arm_vcmpleq_m_f16): Likewise.
5823 (__arm_vcmpleq_m_n_f16): Likewise.
5824 (__arm_vcmpltq_m_f16): Likewise.
5825 (__arm_vcmpltq_m_n_f16): Likewise.
5826 (__arm_vcmpneq_m_f16): Likewise.
5827 (__arm_vcmpneq_m_n_f16): Likewise.
5828 (__arm_vcvtmq_m_u16_f16): Likewise.
5829 (__arm_vcvtnq_m_u16_f16): Likewise.
5830 (__arm_vcvtpq_m_u16_f16): Likewise.
5831 (__arm_vcvtq_m_u16_f16): Likewise.
5832 (__arm_vcmlaq_f32): Likewise.
5833 (__arm_vcmlaq_rot180_f32): Likewise.
5834 (__arm_vcmlaq_rot270_f32): Likewise.
5835 (__arm_vcmlaq_rot90_f32): Likewise.
5836 (__arm_vfmaq_f32): Likewise.
5837 (__arm_vfmaq_n_f32): Likewise.
5838 (__arm_vfmasq_n_f32): Likewise.
5839 (__arm_vfmsq_f32): Likewise.
5840 (__arm_vabsq_m_f32): Likewise.
5841 (__arm_vcvtmq_m_s32_f32): Likewise.
5842 (__arm_vcvtnq_m_s32_f32): Likewise.
5843 (__arm_vcvtpq_m_s32_f32): Likewise.
5844 (__arm_vcvtq_m_s32_f32): Likewise.
5845 (__arm_vdupq_m_n_f32): Likewise.
5846 (__arm_vmaxnmaq_m_f32): Likewise.
5847 (__arm_vmaxnmavq_p_f32): Likewise.
5848 (__arm_vmaxnmvq_p_f32): Likewise.
5849 (__arm_vminnmaq_m_f32): Likewise.
5850 (__arm_vminnmavq_p_f32): Likewise.
5851 (__arm_vminnmvq_p_f32): Likewise.
5852 (__arm_vnegq_m_f32): Likewise.
5853 (__arm_vpselq_f32): Likewise.
5854 (__arm_vrev64q_m_f32): Likewise.
5855 (__arm_vrndaq_m_f32): Likewise.
5856 (__arm_vrndmq_m_f32): Likewise.
5857 (__arm_vrndnq_m_f32): Likewise.
5858 (__arm_vrndpq_m_f32): Likewise.
5859 (__arm_vrndq_m_f32): Likewise.
5860 (__arm_vrndxq_m_f32): Likewise.
5861 (__arm_vcmpeqq_m_n_f32): Likewise.
5862 (__arm_vcmpgeq_m_f32): Likewise.
5863 (__arm_vcmpgeq_m_n_f32): Likewise.
5864 (__arm_vcmpgtq_m_f32): Likewise.
5865 (__arm_vcmpgtq_m_n_f32): Likewise.
5866 (__arm_vcmpleq_m_f32): Likewise.
5867 (__arm_vcmpleq_m_n_f32): Likewise.
5868 (__arm_vcmpltq_m_f32): Likewise.
5869 (__arm_vcmpltq_m_n_f32): Likewise.
5870 (__arm_vcmpneq_m_f32): Likewise.
5871 (__arm_vcmpneq_m_n_f32): Likewise.
5872 (__arm_vcvtmq_m_u32_f32): Likewise.
5873 (__arm_vcvtnq_m_u32_f32): Likewise.
5874 (__arm_vcvtpq_m_u32_f32): Likewise.
5875 (__arm_vcvtq_m_u32_f32): Likewise.
5876 (vcvtq_m): Define polymorphic variant.
5877 (vabsq_m): Likewise.
5878 (vcmlaq): Likewise.
5879 (vcmlaq_rot180): Likewise.
5880 (vcmlaq_rot270): Likewise.
5881 (vcmlaq_rot90): Likewise.
5882 (vcmpeqq_m_n): Likewise.
5883 (vcmpgeq_m_n): Likewise.
5884 (vrndxq_m): Likewise.
5885 (vrndq_m): Likewise.
5886 (vrndpq_m): Likewise.
5887 (vcmpgtq_m_n): Likewise.
5888 (vcmpgtq_m): Likewise.
5889 (vcmpleq_m): Likewise.
5890 (vcmpleq_m_n): Likewise.
5891 (vcmpltq_m_n): Likewise.
5892 (vcmpltq_m): Likewise.
5893 (vcmpneq_m): Likewise.
5894 (vcmpneq_m_n): Likewise.
5895 (vcvtbq_m): Likewise.
5896 (vcvttq_m): Likewise.
5897 (vcvtmq_m): Likewise.
5898 (vcvtnq_m): Likewise.
5899 (vcvtpq_m): Likewise.
5900 (vdupq_m_n): Likewise.
5901 (vfmaq_n): Likewise.
5902 (vfmaq): Likewise.
5903 (vfmasq_n): Likewise.
5904 (vfmsq): Likewise.
5905 (vmaxnmaq_m): Likewise.
5906 (vmaxnmavq_m): Likewise.
5907 (vmaxnmvq_m): Likewise.
5908 (vmaxnmavq_p): Likewise.
5909 (vmaxnmvq_p): Likewise.
5910 (vminnmaq_m): Likewise.
5911 (vminnmavq_p): Likewise.
5912 (vminnmvq_p): Likewise.
5913 (vrndnq_m): Likewise.
5914 (vrndaq_m): Likewise.
5915 (vrndmq_m): Likewise.
5916 (vrev64q_m): Likewise.
5917 (vrev32q_m): Likewise.
5918 (vpselq): Likewise.
5919 (vnegq_m): Likewise.
5920 (vcmpgeq_m): Likewise.
5921 (vshrntq_n): Likewise.
5922 (vrshrntq_n): Likewise.
5923 (vmovlbq_m): Likewise.
5924 (vmovnbq_m): Likewise.
5925 (vmovntq_m): Likewise.
5926 (vmvnq_m_n): Likewise.
5927 (vmvnq_m): Likewise.
5928 (vshrnbq_n): Likewise.
5929 (vrshrnbq_n): Likewise.
5930 (vqshruntq_n): Likewise.
5931 (vrev16q_m): Likewise.
5932 (vqshrunbq_n): Likewise.
5933 (vqshrntq_n): Likewise.
5934 (vqrshruntq_n): Likewise.
5935 (vqrshrntq_n): Likewise.
5936 (vqshrnbq_n): Likewise.
5937 (vqmovuntq_m): Likewise.
5938 (vqmovntq_m): Likewise.
5939 (vqmovnbq_m): Likewise.
5940 (vorrq_m_n): Likewise.
5941 (vmovltq_m): Likewise.
5942 (vqmovunbq_m): Likewise.
5943 (vaddlvaq_p): Likewise.
5944 (vmlaldavaq): Likewise.
5945 (vmlaldavaxq): Likewise.
5946 (vmlaldavq_p): Likewise.
5947 (vmlaldavxq_p): Likewise.
5948 (vmlsldavaq): Likewise.
5949 (vmlsldavaxq): Likewise.
5950 (vmlsldavq_p): Likewise.
5951 (vmlsldavxq_p): Likewise.
5952 (vrmlaldavhaxq): Likewise.
5953 (vrmlaldavhq_p): Likewise.
5954 (vrmlaldavhxq_p): Likewise.
5955 (vrmlsldavhaq): Likewise.
5956 (vrmlsldavhaxq): Likewise.
5957 (vrmlsldavhq_p): Likewise.
5958 (vrmlsldavhxq_p): Likewise.
5959 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
5960 builtin qualifier.
5961 (TERNOP_NONE_NONE_NONE_IMM): Likewise.
5962 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
5963 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
5964 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
5965 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
5966 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
5967 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
5968 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
5969 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
5970 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
5971 (MVE_pred3): Likewise.
5972 (MVE_constraint1): Likewise.
5973 (MVE_pred1): Likewise.
5974 (VMLALDAVQ_P): Define iterator.
5975 (VQMOVNBQ_M): Likewise.
5976 (VMOVLTQ_M): Likewise.
5977 (VMOVNBQ_M): Likewise.
5978 (VRSHRNTQ_N): Likewise.
5979 (VORRQ_M_N): Likewise.
5980 (VREV32Q_M): Likewise.
5981 (VREV16Q_M): Likewise.
5982 (VQRSHRNTQ_N): Likewise.
5983 (VMOVNTQ_M): Likewise.
5984 (VMOVLBQ_M): Likewise.
5985 (VMLALDAVAQ): Likewise.
5986 (VQSHRNBQ_N): Likewise.
5987 (VSHRNBQ_N): Likewise.
5988 (VRSHRNBQ_N): Likewise.
5989 (VMLALDAVXQ_P): Likewise.
5990 (VQMOVNTQ_M): Likewise.
5991 (VMVNQ_M_N): Likewise.
5992 (VQSHRNTQ_N): Likewise.
5993 (VMLALDAVAXQ): Likewise.
5994 (VSHRNTQ_N): Likewise.
5995 (VCVTMQ_M): Likewise.
5996 (VCVTNQ_M): Likewise.
5997 (VCVTPQ_M): Likewise.
5998 (VCVTQ_M_N_FROM_F): Likewise.
5999 (VCVTQ_M_FROM_F): Likewise.
6000 (VRMLALDAVHQ_P): Likewise.
6001 (VADDLVAQ_P): Likewise.
6002 (mve_vrndq_m_f<mode>): Define RTL pattern.
6003 (mve_vabsq_m_f<mode>): Likewise.
6004 (mve_vaddlvaq_p_<supf>v4si): Likewise.
6005 (mve_vcmlaq_f<mode>): Likewise.
6006 (mve_vcmlaq_rot180_f<mode>): Likewise.
6007 (mve_vcmlaq_rot270_f<mode>): Likewise.
6008 (mve_vcmlaq_rot90_f<mode>): Likewise.
6009 (mve_vcmpeqq_m_n_f<mode>): Likewise.
6010 (mve_vcmpgeq_m_f<mode>): Likewise.
6011 (mve_vcmpgeq_m_n_f<mode>): Likewise.
6012 (mve_vcmpgtq_m_f<mode>): Likewise.
6013 (mve_vcmpgtq_m_n_f<mode>): Likewise.
6014 (mve_vcmpleq_m_f<mode>): Likewise.
6015 (mve_vcmpleq_m_n_f<mode>): Likewise.
6016 (mve_vcmpltq_m_f<mode>): Likewise.
6017 (mve_vcmpltq_m_n_f<mode>): Likewise.
6018 (mve_vcmpneq_m_f<mode>): Likewise.
6019 (mve_vcmpneq_m_n_f<mode>): Likewise.
6020 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
6021 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
6022 (mve_vcvttq_m_f16_f32v8hf): Likewise.
6023 (mve_vcvttq_m_f32_f16v4sf): Likewise.
6024 (mve_vdupq_m_n_f<mode>): Likewise.
6025 (mve_vfmaq_f<mode>): Likewise.
6026 (mve_vfmaq_n_f<mode>): Likewise.
6027 (mve_vfmasq_n_f<mode>): Likewise.
6028 (mve_vfmsq_f<mode>): Likewise.
6029 (mve_vmaxnmaq_m_f<mode>): Likewise.
6030 (mve_vmaxnmavq_p_f<mode>): Likewise.
6031 (mve_vmaxnmvq_p_f<mode>): Likewise.
6032 (mve_vminnmaq_m_f<mode>): Likewise.
6033 (mve_vminnmavq_p_f<mode>): Likewise.
6034 (mve_vminnmvq_p_f<mode>): Likewise.
6035 (mve_vmlaldavaq_<supf><mode>): Likewise.
6036 (mve_vmlaldavaxq_<supf><mode>): Likewise.
6037 (mve_vmlaldavq_p_<supf><mode>): Likewise.
6038 (mve_vmlaldavxq_p_<supf><mode>): Likewise.
6039 (mve_vmlsldavaq_s<mode>): Likewise.
6040 (mve_vmlsldavaxq_s<mode>): Likewise.
6041 (mve_vmlsldavq_p_s<mode>): Likewise.
6042 (mve_vmlsldavxq_p_s<mode>): Likewise.
6043 (mve_vmovlbq_m_<supf><mode>): Likewise.
6044 (mve_vmovltq_m_<supf><mode>): Likewise.
6045 (mve_vmovnbq_m_<supf><mode>): Likewise.
6046 (mve_vmovntq_m_<supf><mode>): Likewise.
6047 (mve_vmvnq_m_n_<supf><mode>): Likewise.
6048 (mve_vnegq_m_f<mode>): Likewise.
6049 (mve_vorrq_m_n_<supf><mode>): Likewise.
6050 (mve_vpselq_f<mode>): Likewise.
6051 (mve_vqmovnbq_m_<supf><mode>): Likewise.
6052 (mve_vqmovntq_m_<supf><mode>): Likewise.
6053 (mve_vqmovunbq_m_s<mode>): Likewise.
6054 (mve_vqmovuntq_m_s<mode>): Likewise.
6055 (mve_vqrshrntq_n_<supf><mode>): Likewise.
6056 (mve_vqrshruntq_n_s<mode>): Likewise.
6057 (mve_vqshrnbq_n_<supf><mode>): Likewise.
6058 (mve_vqshrntq_n_<supf><mode>): Likewise.
6059 (mve_vqshrunbq_n_s<mode>): Likewise.
6060 (mve_vqshruntq_n_s<mode>): Likewise.
6061 (mve_vrev32q_m_fv8hf): Likewise.
6062 (mve_vrev32q_m_<supf><mode>): Likewise.
6063 (mve_vrev64q_m_f<mode>): Likewise.
6064 (mve_vrmlaldavhaxq_sv4si): Likewise.
6065 (mve_vrmlaldavhxq_p_sv4si): Likewise.
6066 (mve_vrmlsldavhaxq_sv4si): Likewise.
6067 (mve_vrmlsldavhq_p_sv4si): Likewise.
6068 (mve_vrmlsldavhxq_p_sv4si): Likewise.
6069 (mve_vrndaq_m_f<mode>): Likewise.
6070 (mve_vrndmq_m_f<mode>): Likewise.
6071 (mve_vrndnq_m_f<mode>): Likewise.
6072 (mve_vrndpq_m_f<mode>): Likewise.
6073 (mve_vrndxq_m_f<mode>): Likewise.
6074 (mve_vrshrnbq_n_<supf><mode>): Likewise.
6075 (mve_vrshrntq_n_<supf><mode>): Likewise.
6076 (mve_vshrnbq_n_<supf><mode>): Likewise.
6077 (mve_vshrntq_n_<supf><mode>): Likewise.
6078 (mve_vcvtmq_m_<supf><mode>): Likewise.
6079 (mve_vcvtpq_m_<supf><mode>): Likewise.
6080 (mve_vcvtnq_m_<supf><mode>): Likewise.
6081 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
6082 (mve_vrev16q_m_<supf>v16qi): Likewise.
6083 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
6084 (mve_vrmlaldavhq_p_<supf>v4si): Likewise.
6085 (mve_vrmlsldavhaq_sv4si): Likewise.
6087 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6088 Mihail Ionescu <mihail.ionescu@arm.com>
6089 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6091 * config/arm/arm_mve.h (vpselq_u8): Define macro.
6092 (vpselq_s8): Likewise.
6093 (vrev64q_m_u8): Likewise.
6094 (vqrdmlashq_n_u8): Likewise.
6095 (vqrdmlahq_n_u8): Likewise.
6096 (vqdmlahq_n_u8): Likewise.
6097 (vmvnq_m_u8): Likewise.
6098 (vmlasq_n_u8): Likewise.
6099 (vmlaq_n_u8): Likewise.
6100 (vmladavq_p_u8): Likewise.
6101 (vmladavaq_u8): Likewise.
6102 (vminvq_p_u8): Likewise.
6103 (vmaxvq_p_u8): Likewise.
6104 (vdupq_m_n_u8): Likewise.
6105 (vcmpneq_m_u8): Likewise.
6106 (vcmpneq_m_n_u8): Likewise.
6107 (vcmphiq_m_u8): Likewise.
6108 (vcmphiq_m_n_u8): Likewise.
6109 (vcmpeqq_m_u8): Likewise.
6110 (vcmpeqq_m_n_u8): Likewise.
6111 (vcmpcsq_m_u8): Likewise.
6112 (vcmpcsq_m_n_u8): Likewise.
6113 (vclzq_m_u8): Likewise.
6114 (vaddvaq_p_u8): Likewise.
6115 (vsriq_n_u8): Likewise.
6116 (vsliq_n_u8): Likewise.
6117 (vshlq_m_r_u8): Likewise.
6118 (vrshlq_m_n_u8): Likewise.
6119 (vqshlq_m_r_u8): Likewise.
6120 (vqrshlq_m_n_u8): Likewise.
6121 (vminavq_p_s8): Likewise.
6122 (vminaq_m_s8): Likewise.
6123 (vmaxavq_p_s8): Likewise.
6124 (vmaxaq_m_s8): Likewise.
6125 (vcmpneq_m_s8): Likewise.
6126 (vcmpneq_m_n_s8): Likewise.
6127 (vcmpltq_m_s8): Likewise.
6128 (vcmpltq_m_n_s8): Likewise.
6129 (vcmpleq_m_s8): Likewise.
6130 (vcmpleq_m_n_s8): Likewise.
6131 (vcmpgtq_m_s8): Likewise.
6132 (vcmpgtq_m_n_s8): Likewise.
6133 (vcmpgeq_m_s8): Likewise.
6134 (vcmpgeq_m_n_s8): Likewise.
6135 (vcmpeqq_m_s8): Likewise.
6136 (vcmpeqq_m_n_s8): Likewise.
6137 (vshlq_m_r_s8): Likewise.
6138 (vrshlq_m_n_s8): Likewise.
6139 (vrev64q_m_s8): Likewise.
6140 (vqshlq_m_r_s8): Likewise.
6141 (vqrshlq_m_n_s8): Likewise.
6142 (vqnegq_m_s8): Likewise.
6143 (vqabsq_m_s8): Likewise.
6144 (vnegq_m_s8): Likewise.
6145 (vmvnq_m_s8): Likewise.
6146 (vmlsdavxq_p_s8): Likewise.
6147 (vmlsdavq_p_s8): Likewise.
6148 (vmladavxq_p_s8): Likewise.
6149 (vmladavq_p_s8): Likewise.
6150 (vminvq_p_s8): Likewise.
6151 (vmaxvq_p_s8): Likewise.
6152 (vdupq_m_n_s8): Likewise.
6153 (vclzq_m_s8): Likewise.
6154 (vclsq_m_s8): Likewise.
6155 (vaddvaq_p_s8): Likewise.
6156 (vabsq_m_s8): Likewise.
6157 (vqrdmlsdhxq_s8): Likewise.
6158 (vqrdmlsdhq_s8): Likewise.
6159 (vqrdmlashq_n_s8): Likewise.
6160 (vqrdmlahq_n_s8): Likewise.
6161 (vqrdmladhxq_s8): Likewise.
6162 (vqrdmladhq_s8): Likewise.
6163 (vqdmlsdhxq_s8): Likewise.
6164 (vqdmlsdhq_s8): Likewise.
6165 (vqdmlahq_n_s8): Likewise.
6166 (vqdmladhxq_s8): Likewise.
6167 (vqdmladhq_s8): Likewise.
6168 (vmlsdavaxq_s8): Likewise.
6169 (vmlsdavaq_s8): Likewise.
6170 (vmlasq_n_s8): Likewise.
6171 (vmlaq_n_s8): Likewise.
6172 (vmladavaxq_s8): Likewise.
6173 (vmladavaq_s8): Likewise.
6174 (vsriq_n_s8): Likewise.
6175 (vsliq_n_s8): Likewise.
6176 (vpselq_u16): Likewise.
6177 (vpselq_s16): Likewise.
6178 (vrev64q_m_u16): Likewise.
6179 (vqrdmlashq_n_u16): Likewise.
6180 (vqrdmlahq_n_u16): Likewise.
6181 (vqdmlahq_n_u16): Likewise.
6182 (vmvnq_m_u16): Likewise.
6183 (vmlasq_n_u16): Likewise.
6184 (vmlaq_n_u16): Likewise.
6185 (vmladavq_p_u16): Likewise.
6186 (vmladavaq_u16): Likewise.
6187 (vminvq_p_u16): Likewise.
6188 (vmaxvq_p_u16): Likewise.
6189 (vdupq_m_n_u16): Likewise.
6190 (vcmpneq_m_u16): Likewise.
6191 (vcmpneq_m_n_u16): Likewise.
6192 (vcmphiq_m_u16): Likewise.
6193 (vcmphiq_m_n_u16): Likewise.
6194 (vcmpeqq_m_u16): Likewise.
6195 (vcmpeqq_m_n_u16): Likewise.
6196 (vcmpcsq_m_u16): Likewise.
6197 (vcmpcsq_m_n_u16): Likewise.
6198 (vclzq_m_u16): Likewise.
6199 (vaddvaq_p_u16): Likewise.
6200 (vsriq_n_u16): Likewise.
6201 (vsliq_n_u16): Likewise.
6202 (vshlq_m_r_u16): Likewise.
6203 (vrshlq_m_n_u16): Likewise.
6204 (vqshlq_m_r_u16): Likewise.
6205 (vqrshlq_m_n_u16): Likewise.
6206 (vminavq_p_s16): Likewise.
6207 (vminaq_m_s16): Likewise.
6208 (vmaxavq_p_s16): Likewise.
6209 (vmaxaq_m_s16): Likewise.
6210 (vcmpneq_m_s16): Likewise.
6211 (vcmpneq_m_n_s16): Likewise.
6212 (vcmpltq_m_s16): Likewise.
6213 (vcmpltq_m_n_s16): Likewise.
6214 (vcmpleq_m_s16): Likewise.
6215 (vcmpleq_m_n_s16): Likewise.
6216 (vcmpgtq_m_s16): Likewise.
6217 (vcmpgtq_m_n_s16): Likewise.
6218 (vcmpgeq_m_s16): Likewise.
6219 (vcmpgeq_m_n_s16): Likewise.
6220 (vcmpeqq_m_s16): Likewise.
6221 (vcmpeqq_m_n_s16): Likewise.
6222 (vshlq_m_r_s16): Likewise.
6223 (vrshlq_m_n_s16): Likewise.
6224 (vrev64q_m_s16): Likewise.
6225 (vqshlq_m_r_s16): Likewise.
6226 (vqrshlq_m_n_s16): Likewise.
6227 (vqnegq_m_s16): Likewise.
6228 (vqabsq_m_s16): Likewise.
6229 (vnegq_m_s16): Likewise.
6230 (vmvnq_m_s16): Likewise.
6231 (vmlsdavxq_p_s16): Likewise.
6232 (vmlsdavq_p_s16): Likewise.
6233 (vmladavxq_p_s16): Likewise.
6234 (vmladavq_p_s16): Likewise.
6235 (vminvq_p_s16): Likewise.
6236 (vmaxvq_p_s16): Likewise.
6237 (vdupq_m_n_s16): Likewise.
6238 (vclzq_m_s16): Likewise.
6239 (vclsq_m_s16): Likewise.
6240 (vaddvaq_p_s16): Likewise.
6241 (vabsq_m_s16): Likewise.
6242 (vqrdmlsdhxq_s16): Likewise.
6243 (vqrdmlsdhq_s16): Likewise.
6244 (vqrdmlashq_n_s16): Likewise.
6245 (vqrdmlahq_n_s16): Likewise.
6246 (vqrdmladhxq_s16): Likewise.
6247 (vqrdmladhq_s16): Likewise.
6248 (vqdmlsdhxq_s16): Likewise.
6249 (vqdmlsdhq_s16): Likewise.
6250 (vqdmlahq_n_s16): Likewise.
6251 (vqdmladhxq_s16): Likewise.
6252 (vqdmladhq_s16): Likewise.
6253 (vmlsdavaxq_s16): Likewise.
6254 (vmlsdavaq_s16): Likewise.
6255 (vmlasq_n_s16): Likewise.
6256 (vmlaq_n_s16): Likewise.
6257 (vmladavaxq_s16): Likewise.
6258 (vmladavaq_s16): Likewise.
6259 (vsriq_n_s16): Likewise.
6260 (vsliq_n_s16): Likewise.
6261 (vpselq_u32): Likewise.
6262 (vpselq_s32): Likewise.
6263 (vrev64q_m_u32): Likewise.
6264 (vqrdmlashq_n_u32): Likewise.
6265 (vqrdmlahq_n_u32): Likewise.
6266 (vqdmlahq_n_u32): Likewise.
6267 (vmvnq_m_u32): Likewise.
6268 (vmlasq_n_u32): Likewise.
6269 (vmlaq_n_u32): Likewise.
6270 (vmladavq_p_u32): Likewise.
6271 (vmladavaq_u32): Likewise.
6272 (vminvq_p_u32): Likewise.
6273 (vmaxvq_p_u32): Likewise.
6274 (vdupq_m_n_u32): Likewise.
6275 (vcmpneq_m_u32): Likewise.
6276 (vcmpneq_m_n_u32): Likewise.
6277 (vcmphiq_m_u32): Likewise.
6278 (vcmphiq_m_n_u32): Likewise.
6279 (vcmpeqq_m_u32): Likewise.
6280 (vcmpeqq_m_n_u32): Likewise.
6281 (vcmpcsq_m_u32): Likewise.
6282 (vcmpcsq_m_n_u32): Likewise.
6283 (vclzq_m_u32): Likewise.
6284 (vaddvaq_p_u32): Likewise.
6285 (vsriq_n_u32): Likewise.
6286 (vsliq_n_u32): Likewise.
6287 (vshlq_m_r_u32): Likewise.
6288 (vrshlq_m_n_u32): Likewise.
6289 (vqshlq_m_r_u32): Likewise.
6290 (vqrshlq_m_n_u32): Likewise.
6291 (vminavq_p_s32): Likewise.
6292 (vminaq_m_s32): Likewise.
6293 (vmaxavq_p_s32): Likewise.
6294 (vmaxaq_m_s32): Likewise.
6295 (vcmpneq_m_s32): Likewise.
6296 (vcmpneq_m_n_s32): Likewise.
6297 (vcmpltq_m_s32): Likewise.
6298 (vcmpltq_m_n_s32): Likewise.
6299 (vcmpleq_m_s32): Likewise.
6300 (vcmpleq_m_n_s32): Likewise.
6301 (vcmpgtq_m_s32): Likewise.
6302 (vcmpgtq_m_n_s32): Likewise.
6303 (vcmpgeq_m_s32): Likewise.
6304 (vcmpgeq_m_n_s32): Likewise.
6305 (vcmpeqq_m_s32): Likewise.
6306 (vcmpeqq_m_n_s32): Likewise.
6307 (vshlq_m_r_s32): Likewise.
6308 (vrshlq_m_n_s32): Likewise.
6309 (vrev64q_m_s32): Likewise.
6310 (vqshlq_m_r_s32): Likewise.
6311 (vqrshlq_m_n_s32): Likewise.
6312 (vqnegq_m_s32): Likewise.
6313 (vqabsq_m_s32): Likewise.
6314 (vnegq_m_s32): Likewise.
6315 (vmvnq_m_s32): Likewise.
6316 (vmlsdavxq_p_s32): Likewise.
6317 (vmlsdavq_p_s32): Likewise.
6318 (vmladavxq_p_s32): Likewise.
6319 (vmladavq_p_s32): Likewise.
6320 (vminvq_p_s32): Likewise.
6321 (vmaxvq_p_s32): Likewise.
6322 (vdupq_m_n_s32): Likewise.
6323 (vclzq_m_s32): Likewise.
6324 (vclsq_m_s32): Likewise.
6325 (vaddvaq_p_s32): Likewise.
6326 (vabsq_m_s32): Likewise.
6327 (vqrdmlsdhxq_s32): Likewise.
6328 (vqrdmlsdhq_s32): Likewise.
6329 (vqrdmlashq_n_s32): Likewise.
6330 (vqrdmlahq_n_s32): Likewise.
6331 (vqrdmladhxq_s32): Likewise.
6332 (vqrdmladhq_s32): Likewise.
6333 (vqdmlsdhxq_s32): Likewise.
6334 (vqdmlsdhq_s32): Likewise.
6335 (vqdmlahq_n_s32): Likewise.
6336 (vqdmladhxq_s32): Likewise.
6337 (vqdmladhq_s32): Likewise.
6338 (vmlsdavaxq_s32): Likewise.
6339 (vmlsdavaq_s32): Likewise.
6340 (vmlasq_n_s32): Likewise.
6341 (vmlaq_n_s32): Likewise.
6342 (vmladavaxq_s32): Likewise.
6343 (vmladavaq_s32): Likewise.
6344 (vsriq_n_s32): Likewise.
6345 (vsliq_n_s32): Likewise.
6346 (vpselq_u64): Likewise.
6347 (vpselq_s64): Likewise.
6348 (__arm_vpselq_u8): Define intrinsic.
6349 (__arm_vpselq_s8): Likewise.
6350 (__arm_vrev64q_m_u8): Likewise.
6351 (__arm_vqrdmlashq_n_u8): Likewise.
6352 (__arm_vqrdmlahq_n_u8): Likewise.
6353 (__arm_vqdmlahq_n_u8): Likewise.
6354 (__arm_vmvnq_m_u8): Likewise.
6355 (__arm_vmlasq_n_u8): Likewise.
6356 (__arm_vmlaq_n_u8): Likewise.
6357 (__arm_vmladavq_p_u8): Likewise.
6358 (__arm_vmladavaq_u8): Likewise.
6359 (__arm_vminvq_p_u8): Likewise.
6360 (__arm_vmaxvq_p_u8): Likewise.
6361 (__arm_vdupq_m_n_u8): Likewise.
6362 (__arm_vcmpneq_m_u8): Likewise.
6363 (__arm_vcmpneq_m_n_u8): Likewise.
6364 (__arm_vcmphiq_m_u8): Likewise.
6365 (__arm_vcmphiq_m_n_u8): Likewise.
6366 (__arm_vcmpeqq_m_u8): Likewise.
6367 (__arm_vcmpeqq_m_n_u8): Likewise.
6368 (__arm_vcmpcsq_m_u8): Likewise.
6369 (__arm_vcmpcsq_m_n_u8): Likewise.
6370 (__arm_vclzq_m_u8): Likewise.
6371 (__arm_vaddvaq_p_u8): Likewise.
6372 (__arm_vsriq_n_u8): Likewise.
6373 (__arm_vsliq_n_u8): Likewise.
6374 (__arm_vshlq_m_r_u8): Likewise.
6375 (__arm_vrshlq_m_n_u8): Likewise.
6376 (__arm_vqshlq_m_r_u8): Likewise.
6377 (__arm_vqrshlq_m_n_u8): Likewise.
6378 (__arm_vminavq_p_s8): Likewise.
6379 (__arm_vminaq_m_s8): Likewise.
6380 (__arm_vmaxavq_p_s8): Likewise.
6381 (__arm_vmaxaq_m_s8): Likewise.
6382 (__arm_vcmpneq_m_s8): Likewise.
6383 (__arm_vcmpneq_m_n_s8): Likewise.
6384 (__arm_vcmpltq_m_s8): Likewise.
6385 (__arm_vcmpltq_m_n_s8): Likewise.
6386 (__arm_vcmpleq_m_s8): Likewise.
6387 (__arm_vcmpleq_m_n_s8): Likewise.
6388 (__arm_vcmpgtq_m_s8): Likewise.
6389 (__arm_vcmpgtq_m_n_s8): Likewise.
6390 (__arm_vcmpgeq_m_s8): Likewise.
6391 (__arm_vcmpgeq_m_n_s8): Likewise.
6392 (__arm_vcmpeqq_m_s8): Likewise.
6393 (__arm_vcmpeqq_m_n_s8): Likewise.
6394 (__arm_vshlq_m_r_s8): Likewise.
6395 (__arm_vrshlq_m_n_s8): Likewise.
6396 (__arm_vrev64q_m_s8): Likewise.
6397 (__arm_vqshlq_m_r_s8): Likewise.
6398 (__arm_vqrshlq_m_n_s8): Likewise.
6399 (__arm_vqnegq_m_s8): Likewise.
6400 (__arm_vqabsq_m_s8): Likewise.
6401 (__arm_vnegq_m_s8): Likewise.
6402 (__arm_vmvnq_m_s8): Likewise.
6403 (__arm_vmlsdavxq_p_s8): Likewise.
6404 (__arm_vmlsdavq_p_s8): Likewise.
6405 (__arm_vmladavxq_p_s8): Likewise.
6406 (__arm_vmladavq_p_s8): Likewise.
6407 (__arm_vminvq_p_s8): Likewise.
6408 (__arm_vmaxvq_p_s8): Likewise.
6409 (__arm_vdupq_m_n_s8): Likewise.
6410 (__arm_vclzq_m_s8): Likewise.
6411 (__arm_vclsq_m_s8): Likewise.
6412 (__arm_vaddvaq_p_s8): Likewise.
6413 (__arm_vabsq_m_s8): Likewise.
6414 (__arm_vqrdmlsdhxq_s8): Likewise.
6415 (__arm_vqrdmlsdhq_s8): Likewise.
6416 (__arm_vqrdmlashq_n_s8): Likewise.
6417 (__arm_vqrdmlahq_n_s8): Likewise.
6418 (__arm_vqrdmladhxq_s8): Likewise.
6419 (__arm_vqrdmladhq_s8): Likewise.
6420 (__arm_vqdmlsdhxq_s8): Likewise.
6421 (__arm_vqdmlsdhq_s8): Likewise.
6422 (__arm_vqdmlahq_n_s8): Likewise.
6423 (__arm_vqdmladhxq_s8): Likewise.
6424 (__arm_vqdmladhq_s8): Likewise.
6425 (__arm_vmlsdavaxq_s8): Likewise.
6426 (__arm_vmlsdavaq_s8): Likewise.
6427 (__arm_vmlasq_n_s8): Likewise.
6428 (__arm_vmlaq_n_s8): Likewise.
6429 (__arm_vmladavaxq_s8): Likewise.
6430 (__arm_vmladavaq_s8): Likewise.
6431 (__arm_vsriq_n_s8): Likewise.
6432 (__arm_vsliq_n_s8): Likewise.
6433 (__arm_vpselq_u16): Likewise.
6434 (__arm_vpselq_s16): Likewise.
6435 (__arm_vrev64q_m_u16): Likewise.
6436 (__arm_vqrdmlashq_n_u16): Likewise.
6437 (__arm_vqrdmlahq_n_u16): Likewise.
6438 (__arm_vqdmlahq_n_u16): Likewise.
6439 (__arm_vmvnq_m_u16): Likewise.
6440 (__arm_vmlasq_n_u16): Likewise.
6441 (__arm_vmlaq_n_u16): Likewise.
6442 (__arm_vmladavq_p_u16): Likewise.
6443 (__arm_vmladavaq_u16): Likewise.
6444 (__arm_vminvq_p_u16): Likewise.
6445 (__arm_vmaxvq_p_u16): Likewise.
6446 (__arm_vdupq_m_n_u16): Likewise.
6447 (__arm_vcmpneq_m_u16): Likewise.
6448 (__arm_vcmpneq_m_n_u16): Likewise.
6449 (__arm_vcmphiq_m_u16): Likewise.
6450 (__arm_vcmphiq_m_n_u16): Likewise.
6451 (__arm_vcmpeqq_m_u16): Likewise.
6452 (__arm_vcmpeqq_m_n_u16): Likewise.
6453 (__arm_vcmpcsq_m_u16): Likewise.
6454 (__arm_vcmpcsq_m_n_u16): Likewise.
6455 (__arm_vclzq_m_u16): Likewise.
6456 (__arm_vaddvaq_p_u16): Likewise.
6457 (__arm_vsriq_n_u16): Likewise.
6458 (__arm_vsliq_n_u16): Likewise.
6459 (__arm_vshlq_m_r_u16): Likewise.
6460 (__arm_vrshlq_m_n_u16): Likewise.
6461 (__arm_vqshlq_m_r_u16): Likewise.
6462 (__arm_vqrshlq_m_n_u16): Likewise.
6463 (__arm_vminavq_p_s16): Likewise.
6464 (__arm_vminaq_m_s16): Likewise.
6465 (__arm_vmaxavq_p_s16): Likewise.
6466 (__arm_vmaxaq_m_s16): Likewise.
6467 (__arm_vcmpneq_m_s16): Likewise.
6468 (__arm_vcmpneq_m_n_s16): Likewise.
6469 (__arm_vcmpltq_m_s16): Likewise.
6470 (__arm_vcmpltq_m_n_s16): Likewise.
6471 (__arm_vcmpleq_m_s16): Likewise.
6472 (__arm_vcmpleq_m_n_s16): Likewise.
6473 (__arm_vcmpgtq_m_s16): Likewise.
6474 (__arm_vcmpgtq_m_n_s16): Likewise.
6475 (__arm_vcmpgeq_m_s16): Likewise.
6476 (__arm_vcmpgeq_m_n_s16): Likewise.
6477 (__arm_vcmpeqq_m_s16): Likewise.
6478 (__arm_vcmpeqq_m_n_s16): Likewise.
6479 (__arm_vshlq_m_r_s16): Likewise.
6480 (__arm_vrshlq_m_n_s16): Likewise.
6481 (__arm_vrev64q_m_s16): Likewise.
6482 (__arm_vqshlq_m_r_s16): Likewise.
6483 (__arm_vqrshlq_m_n_s16): Likewise.
6484 (__arm_vqnegq_m_s16): Likewise.
6485 (__arm_vqabsq_m_s16): Likewise.
6486 (__arm_vnegq_m_s16): Likewise.
6487 (__arm_vmvnq_m_s16): Likewise.
6488 (__arm_vmlsdavxq_p_s16): Likewise.
6489 (__arm_vmlsdavq_p_s16): Likewise.
6490 (__arm_vmladavxq_p_s16): Likewise.
6491 (__arm_vmladavq_p_s16): Likewise.
6492 (__arm_vminvq_p_s16): Likewise.
6493 (__arm_vmaxvq_p_s16): Likewise.
6494 (__arm_vdupq_m_n_s16): Likewise.
6495 (__arm_vclzq_m_s16): Likewise.
6496 (__arm_vclsq_m_s16): Likewise.
6497 (__arm_vaddvaq_p_s16): Likewise.
6498 (__arm_vabsq_m_s16): Likewise.
6499 (__arm_vqrdmlsdhxq_s16): Likewise.
6500 (__arm_vqrdmlsdhq_s16): Likewise.
6501 (__arm_vqrdmlashq_n_s16): Likewise.
6502 (__arm_vqrdmlahq_n_s16): Likewise.
6503 (__arm_vqrdmladhxq_s16): Likewise.
6504 (__arm_vqrdmladhq_s16): Likewise.
6505 (__arm_vqdmlsdhxq_s16): Likewise.
6506 (__arm_vqdmlsdhq_s16): Likewise.
6507 (__arm_vqdmlahq_n_s16): Likewise.
6508 (__arm_vqdmladhxq_s16): Likewise.
6509 (__arm_vqdmladhq_s16): Likewise.
6510 (__arm_vmlsdavaxq_s16): Likewise.
6511 (__arm_vmlsdavaq_s16): Likewise.
6512 (__arm_vmlasq_n_s16): Likewise.
6513 (__arm_vmlaq_n_s16): Likewise.
6514 (__arm_vmladavaxq_s16): Likewise.
6515 (__arm_vmladavaq_s16): Likewise.
6516 (__arm_vsriq_n_s16): Likewise.
6517 (__arm_vsliq_n_s16): Likewise.
6518 (__arm_vpselq_u32): Likewise.
6519 (__arm_vpselq_s32): Likewise.
6520 (__arm_vrev64q_m_u32): Likewise.
6521 (__arm_vqrdmlashq_n_u32): Likewise.
6522 (__arm_vqrdmlahq_n_u32): Likewise.
6523 (__arm_vqdmlahq_n_u32): Likewise.
6524 (__arm_vmvnq_m_u32): Likewise.
6525 (__arm_vmlasq_n_u32): Likewise.
6526 (__arm_vmlaq_n_u32): Likewise.
6527 (__arm_vmladavq_p_u32): Likewise.
6528 (__arm_vmladavaq_u32): Likewise.
6529 (__arm_vminvq_p_u32): Likewise.
6530 (__arm_vmaxvq_p_u32): Likewise.
6531 (__arm_vdupq_m_n_u32): Likewise.
6532 (__arm_vcmpneq_m_u32): Likewise.
6533 (__arm_vcmpneq_m_n_u32): Likewise.
6534 (__arm_vcmphiq_m_u32): Likewise.
6535 (__arm_vcmphiq_m_n_u32): Likewise.
6536 (__arm_vcmpeqq_m_u32): Likewise.
6537 (__arm_vcmpeqq_m_n_u32): Likewise.
6538 (__arm_vcmpcsq_m_u32): Likewise.
6539 (__arm_vcmpcsq_m_n_u32): Likewise.
6540 (__arm_vclzq_m_u32): Likewise.
6541 (__arm_vaddvaq_p_u32): Likewise.
6542 (__arm_vsriq_n_u32): Likewise.
6543 (__arm_vsliq_n_u32): Likewise.
6544 (__arm_vshlq_m_r_u32): Likewise.
6545 (__arm_vrshlq_m_n_u32): Likewise.
6546 (__arm_vqshlq_m_r_u32): Likewise.
6547 (__arm_vqrshlq_m_n_u32): Likewise.
6548 (__arm_vminavq_p_s32): Likewise.
6549 (__arm_vminaq_m_s32): Likewise.
6550 (__arm_vmaxavq_p_s32): Likewise.
6551 (__arm_vmaxaq_m_s32): Likewise.
6552 (__arm_vcmpneq_m_s32): Likewise.
6553 (__arm_vcmpneq_m_n_s32): Likewise.
6554 (__arm_vcmpltq_m_s32): Likewise.
6555 (__arm_vcmpltq_m_n_s32): Likewise.
6556 (__arm_vcmpleq_m_s32): Likewise.
6557 (__arm_vcmpleq_m_n_s32): Likewise.
6558 (__arm_vcmpgtq_m_s32): Likewise.
6559 (__arm_vcmpgtq_m_n_s32): Likewise.
6560 (__arm_vcmpgeq_m_s32): Likewise.
6561 (__arm_vcmpgeq_m_n_s32): Likewise.
6562 (__arm_vcmpeqq_m_s32): Likewise.
6563 (__arm_vcmpeqq_m_n_s32): Likewise.
6564 (__arm_vshlq_m_r_s32): Likewise.
6565 (__arm_vrshlq_m_n_s32): Likewise.
6566 (__arm_vrev64q_m_s32): Likewise.
6567 (__arm_vqshlq_m_r_s32): Likewise.
6568 (__arm_vqrshlq_m_n_s32): Likewise.
6569 (__arm_vqnegq_m_s32): Likewise.
6570 (__arm_vqabsq_m_s32): Likewise.
6571 (__arm_vnegq_m_s32): Likewise.
6572 (__arm_vmvnq_m_s32): Likewise.
6573 (__arm_vmlsdavxq_p_s32): Likewise.
6574 (__arm_vmlsdavq_p_s32): Likewise.
6575 (__arm_vmladavxq_p_s32): Likewise.
6576 (__arm_vmladavq_p_s32): Likewise.
6577 (__arm_vminvq_p_s32): Likewise.
6578 (__arm_vmaxvq_p_s32): Likewise.
6579 (__arm_vdupq_m_n_s32): Likewise.
6580 (__arm_vclzq_m_s32): Likewise.
6581 (__arm_vclsq_m_s32): Likewise.
6582 (__arm_vaddvaq_p_s32): Likewise.
6583 (__arm_vabsq_m_s32): Likewise.
6584 (__arm_vqrdmlsdhxq_s32): Likewise.
6585 (__arm_vqrdmlsdhq_s32): Likewise.
6586 (__arm_vqrdmlashq_n_s32): Likewise.
6587 (__arm_vqrdmlahq_n_s32): Likewise.
6588 (__arm_vqrdmladhxq_s32): Likewise.
6589 (__arm_vqrdmladhq_s32): Likewise.
6590 (__arm_vqdmlsdhxq_s32): Likewise.
6591 (__arm_vqdmlsdhq_s32): Likewise.
6592 (__arm_vqdmlahq_n_s32): Likewise.
6593 (__arm_vqdmladhxq_s32): Likewise.
6594 (__arm_vqdmladhq_s32): Likewise.
6595 (__arm_vmlsdavaxq_s32): Likewise.
6596 (__arm_vmlsdavaq_s32): Likewise.
6597 (__arm_vmlasq_n_s32): Likewise.
6598 (__arm_vmlaq_n_s32): Likewise.
6599 (__arm_vmladavaxq_s32): Likewise.
6600 (__arm_vmladavaq_s32): Likewise.
6601 (__arm_vsriq_n_s32): Likewise.
6602 (__arm_vsliq_n_s32): Likewise.
6603 (__arm_vpselq_u64): Likewise.
6604 (__arm_vpselq_s64): Likewise.
6605 (vcmpneq_m_n): Define polymorphic variant.
6606 (vcmpneq_m): Likewise.
6607 (vqrdmlsdhq): Likewise.
6608 (vqrdmlsdhxq): Likewise.
6609 (vqrshlq_m_n): Likewise.
6610 (vqshlq_m_r): Likewise.
6611 (vrev64q_m): Likewise.
6612 (vrshlq_m_n): Likewise.
6613 (vshlq_m_r): Likewise.
6614 (vsliq_n): Likewise.
6615 (vsriq_n): Likewise.
6616 (vqrdmlashq_n): Likewise.
6617 (vqrdmlahq): Likewise.
6618 (vqrdmladhxq): Likewise.
6619 (vqrdmladhq): Likewise.
6620 (vqnegq_m): Likewise.
6621 (vqdmlsdhxq): Likewise.
6622 (vabsq_m): Likewise.
6623 (vclsq_m): Likewise.
6624 (vclzq_m): Likewise.
6625 (vcmpgeq_m): Likewise.
6626 (vcmpgeq_m_n): Likewise.
6627 (vdupq_m_n): Likewise.
6628 (vmaxaq_m): Likewise.
6629 (vmlaq_n): Likewise.
6630 (vmlasq_n): Likewise.
6631 (vmvnq_m): Likewise.
6632 (vnegq_m): Likewise.
6633 (vpselq): Likewise.
6634 (vqdmlahq_n): Likewise.
6635 (vqrdmlahq_n): Likewise.
6636 (vqdmlsdhq): Likewise.
6637 (vqdmladhq): Likewise.
6638 (vqabsq_m): Likewise.
6639 (vminaq_m): Likewise.
6640 (vrmlaldavhaq): Likewise.
6641 (vmlsdavxq_p): Likewise.
6642 (vmlsdavq_p): Likewise.
6643 (vmlsdavaxq): Likewise.
6644 (vmlsdavaq): Likewise.
6645 (vaddvaq_p): Likewise.
6646 (vcmpcsq_m_n): Likewise.
6647 (vcmpcsq_m): Likewise.
6648 (vcmpeqq_m_n): Likewise.
6649 (vcmpeqq_m): Likewise.
6650 (vmladavxq_p): Likewise.
6651 (vmladavq_p): Likewise.
6652 (vmladavaxq): Likewise.
6653 (vmladavaq): Likewise.
6654 (vminvq_p): Likewise.
6655 (vminavq_p): Likewise.
6656 (vmaxvq_p): Likewise.
6657 (vmaxavq_p): Likewise.
6658 (vcmpltq_m_n): Likewise.
6659 (vcmpltq_m): Likewise.
6660 (vcmpleq_m): Likewise.
6661 (vcmpleq_m_n): Likewise.
6662 (vcmphiq_m_n): Likewise.
6663 (vcmphiq_m): Likewise.
6664 (vcmpgtq_m_n): Likewise.
6665 (vcmpgtq_m): Likewise.
6666 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
6667 builtin qualifier.
6668 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
6669 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
6670 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
6671 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
6672 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
6673 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
6674 * config/arm/constraints.md (Rc): Define constraint to check constant is
6675 in the range of 0 to 15.
6676 (Re): Define constraint to check constant is in the range of 0 to 31.
6677 * config/arm/mve.md (VADDVAQ_P): Define iterator.
6678 (VCLZQ_M): Likewise.
6679 (VCMPEQQ_M_N): Likewise.
6680 (VCMPEQQ_M): Likewise.
6681 (VCMPNEQ_M_N): Likewise.
6682 (VCMPNEQ_M): Likewise.
6683 (VDUPQ_M_N): Likewise.
6684 (VMAXVQ_P): Likewise.
6685 (VMINVQ_P): Likewise.
6686 (VMLADAVAQ): Likewise.
6687 (VMLADAVQ_P): Likewise.
6688 (VMLAQ_N): Likewise.
6689 (VMLASQ_N): Likewise.
6690 (VMVNQ_M): Likewise.
6691 (VPSELQ): Likewise.
6692 (VQDMLAHQ_N): Likewise.
6693 (VQRDMLAHQ_N): Likewise.
6694 (VQRDMLASHQ_N): Likewise.
6695 (VQRSHLQ_M_N): Likewise.
6696 (VQSHLQ_M_R): Likewise.
6697 (VREV64Q_M): Likewise.
6698 (VRSHLQ_M_N): Likewise.
6699 (VSHLQ_M_R): Likewise.
6700 (VSLIQ_N): Likewise.
6701 (VSRIQ_N): Likewise.
6702 (mve_vabsq_m_s<mode>): Define RTL pattern.
6703 (mve_vaddvaq_p_<supf><mode>): Likewise.
6704 (mve_vclsq_m_s<mode>): Likewise.
6705 (mve_vclzq_m_<supf><mode>): Likewise.
6706 (mve_vcmpcsq_m_n_u<mode>): Likewise.
6707 (mve_vcmpcsq_m_u<mode>): Likewise.
6708 (mve_vcmpeqq_m_n_<supf><mode>): Likewise.
6709 (mve_vcmpeqq_m_<supf><mode>): Likewise.
6710 (mve_vcmpgeq_m_n_s<mode>): Likewise.
6711 (mve_vcmpgeq_m_s<mode>): Likewise.
6712 (mve_vcmpgtq_m_n_s<mode>): Likewise.
6713 (mve_vcmpgtq_m_s<mode>): Likewise.
6714 (mve_vcmphiq_m_n_u<mode>): Likewise.
6715 (mve_vcmphiq_m_u<mode>): Likewise.
6716 (mve_vcmpleq_m_n_s<mode>): Likewise.
6717 (mve_vcmpleq_m_s<mode>): Likewise.
6718 (mve_vcmpltq_m_n_s<mode>): Likewise.
6719 (mve_vcmpltq_m_s<mode>): Likewise.
6720 (mve_vcmpneq_m_n_<supf><mode>): Likewise.
6721 (mve_vcmpneq_m_<supf><mode>): Likewise.
6722 (mve_vdupq_m_n_<supf><mode>): Likewise.
6723 (mve_vmaxaq_m_s<mode>): Likewise.
6724 (mve_vmaxavq_p_s<mode>): Likewise.
6725 (mve_vmaxvq_p_<supf><mode>): Likewise.
6726 (mve_vminaq_m_s<mode>): Likewise.
6727 (mve_vminavq_p_s<mode>): Likewise.
6728 (mve_vminvq_p_<supf><mode>): Likewise.
6729 (mve_vmladavaq_<supf><mode>): Likewise.
6730 (mve_vmladavq_p_<supf><mode>): Likewise.
6731 (mve_vmladavxq_p_s<mode>): Likewise.
6732 (mve_vmlaq_n_<supf><mode>): Likewise.
6733 (mve_vmlasq_n_<supf><mode>): Likewise.
6734 (mve_vmlsdavq_p_s<mode>): Likewise.
6735 (mve_vmlsdavxq_p_s<mode>): Likewise.
6736 (mve_vmvnq_m_<supf><mode>): Likewise.
6737 (mve_vnegq_m_s<mode>): Likewise.
6738 (mve_vpselq_<supf><mode>): Likewise.
6739 (mve_vqabsq_m_s<mode>): Likewise.
6740 (mve_vqdmlahq_n_<supf><mode>): Likewise.
6741 (mve_vqnegq_m_s<mode>): Likewise.
6742 (mve_vqrdmladhq_s<mode>): Likewise.
6743 (mve_vqrdmladhxq_s<mode>): Likewise.
6744 (mve_vqrdmlahq_n_<supf><mode>): Likewise.
6745 (mve_vqrdmlashq_n_<supf><mode>): Likewise.
6746 (mve_vqrdmlsdhq_s<mode>): Likewise.
6747 (mve_vqrdmlsdhxq_s<mode>): Likewise.
6748 (mve_vqrshlq_m_n_<supf><mode>): Likewise.
6749 (mve_vqshlq_m_r_<supf><mode>): Likewise.
6750 (mve_vrev64q_m_<supf><mode>): Likewise.
6751 (mve_vrshlq_m_n_<supf><mode>): Likewise.
6752 (mve_vshlq_m_r_<supf><mode>): Likewise.
6753 (mve_vsliq_n_<supf><mode>): Likewise.
6754 (mve_vsriq_n_<supf><mode>): Likewise.
6755 (mve_vqdmlsdhxq_s<mode>): Likewise.
6756 (mve_vqdmlsdhq_s<mode>): Likewise.
6757 (mve_vqdmladhxq_s<mode>): Likewise.
6758 (mve_vqdmladhq_s<mode>): Likewise.
6759 (mve_vmlsdavaxq_s<mode>): Likewise.
6760 (mve_vmlsdavaq_s<mode>): Likewise.
6761 (mve_vmladavaxq_s<mode>): Likewise.
6762 * config/arm/predicates.md (mve_imm_15):Define predicate to check the
6763 matching constraint Rc.
6764 (mve_imm_31): Define predicate to check the matching constraint Re.
6766 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
6768 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
6769 (vec_cmp<mode>di_dup): Likewise.
6770 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
6772 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
6774 * config/gcn/gcn-valu.md (COND_MODE): Delete.
6775 (COND_INT_MODE): Delete.
6776 (cond_op): Add "mult".
6777 (cond_<expander><mode>): Use VEC_ALLREG_MODE.
6778 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
6780 2020-03-18 Richard Biener <rguenther@suse.de>
6782 PR middle-end/94206
6783 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using
6784 partial int modes or not mode-precision integer types for
6785 the store.
6787 2020-03-18 Jakub Jelinek <jakub@redhat.com>
6789 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
6790 in a comment.
6791 * config/arc/arc.c (frame_stack_add): Likewise.
6792 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
6793 Likewise.
6794 * ipa-predicate.c (predicate::remap_after_inlining): Likewise.
6795 * tree-ssa-strlen.h (handle_printf_call): Likewise.
6796 * tree-ssa-strlen.c (is_strlen_related_p): Likewise.
6797 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
6799 2020-03-18 Duan bo <duanbo3@huawei.com>
6801 PR target/94201
6802 * config/aarch64/aarch64.md (ldr_got_tiny): Delete.
6803 (@ldr_got_tiny_<mode>): New pattern.
6804 (ldr_got_tiny_sidi): Likewise.
6805 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
6806 them to handle SYMBOL_TINY_GOT for ILP32.
6808 2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
6810 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
6811 call-preserved for SVE PCS functions.
6812 (aarch64_layout_frame): Cope with up to 12 predicate save slots.
6813 Optimize the case in which there are no following vector save slots.
6815 2020-03-18 Richard Biener <rguenther@suse.de>
6817 PR middle-end/94188
6818 * fold-const.c (build_fold_addr_expr): Convert address to
6819 correct type.
6820 * asan.c (maybe_create_ssa_name): Strip useless type conversions.
6821 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
6822 to build the ADDR_EXPR which we don't really want to simplify.
6823 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
6824 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
6825 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
6826 (simplify_builtin_call): Strip useless type conversions.
6827 * tree-ssa-strlen.c (new_strinfo): Likewise.
6829 2020-03-17 Alexey Neyman <stilor@att.net>
6831 PR debug/93751
6832 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
6833 the debug level is terse and the declaration is public. Do not
6834 generate type info.
6835 (dwarf2out_decl): Same.
6836 (add_type_attribute): Return immediately if debug level is
6837 terse.
6839 2020-03-17 Richard Sandiford <richard.sandiford@arm.com>
6841 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.
6843 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
6844 Mihail Ionescu <mihail.ionescu@arm.com>
6845 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6847 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
6848 Define qualifier for ternary operands.
6849 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
6850 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
6851 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
6852 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
6853 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
6854 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
6855 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
6856 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
6857 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
6858 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
6859 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
6860 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
6861 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
6862 * config/arm/arm_mve.h (vabavq_s8): Define macro.
6863 (vabavq_s16): Likewise.
6864 (vabavq_s32): Likewise.
6865 (vbicq_m_n_s16): Likewise.
6866 (vbicq_m_n_s32): Likewise.
6867 (vbicq_m_n_u16): Likewise.
6868 (vbicq_m_n_u32): Likewise.
6869 (vcmpeqq_m_f16): Likewise.
6870 (vcmpeqq_m_f32): Likewise.
6871 (vcvtaq_m_s16_f16): Likewise.
6872 (vcvtaq_m_u16_f16): Likewise.
6873 (vcvtaq_m_s32_f32): Likewise.
6874 (vcvtaq_m_u32_f32): Likewise.
6875 (vcvtq_m_f16_s16): Likewise.
6876 (vcvtq_m_f16_u16): Likewise.
6877 (vcvtq_m_f32_s32): Likewise.
6878 (vcvtq_m_f32_u32): Likewise.
6879 (vqrshrnbq_n_s16): Likewise.
6880 (vqrshrnbq_n_u16): Likewise.
6881 (vqrshrnbq_n_s32): Likewise.
6882 (vqrshrnbq_n_u32): Likewise.
6883 (vqrshrunbq_n_s16): Likewise.
6884 (vqrshrunbq_n_s32): Likewise.
6885 (vrmlaldavhaq_s32): Likewise.
6886 (vrmlaldavhaq_u32): Likewise.
6887 (vshlcq_s8): Likewise.
6888 (vshlcq_u8): Likewise.
6889 (vshlcq_s16): Likewise.
6890 (vshlcq_u16): Likewise.
6891 (vshlcq_s32): Likewise.
6892 (vshlcq_u32): Likewise.
6893 (vabavq_u8): Likewise.
6894 (vabavq_u16): Likewise.
6895 (vabavq_u32): Likewise.
6896 (__arm_vabavq_s8): Define intrinsic.
6897 (__arm_vabavq_s16): Likewise.
6898 (__arm_vabavq_s32): Likewise.
6899 (__arm_vabavq_u8): Likewise.
6900 (__arm_vabavq_u16): Likewise.
6901 (__arm_vabavq_u32): Likewise.
6902 (__arm_vbicq_m_n_s16): Likewise.
6903 (__arm_vbicq_m_n_s32): Likewise.
6904 (__arm_vbicq_m_n_u16): Likewise.
6905 (__arm_vbicq_m_n_u32): Likewise.
6906 (__arm_vqrshrnbq_n_s16): Likewise.
6907 (__arm_vqrshrnbq_n_u16): Likewise.
6908 (__arm_vqrshrnbq_n_s32): Likewise.
6909 (__arm_vqrshrnbq_n_u32): Likewise.
6910 (__arm_vqrshrunbq_n_s16): Likewise.
6911 (__arm_vqrshrunbq_n_s32): Likewise.
6912 (__arm_vrmlaldavhaq_s32): Likewise.
6913 (__arm_vrmlaldavhaq_u32): Likewise.
6914 (__arm_vshlcq_s8): Likewise.
6915 (__arm_vshlcq_u8): Likewise.
6916 (__arm_vshlcq_s16): Likewise.
6917 (__arm_vshlcq_u16): Likewise.
6918 (__arm_vshlcq_s32): Likewise.
6919 (__arm_vshlcq_u32): Likewise.
6920 (__arm_vcmpeqq_m_f16): Likewise.
6921 (__arm_vcmpeqq_m_f32): Likewise.
6922 (__arm_vcvtaq_m_s16_f16): Likewise.
6923 (__arm_vcvtaq_m_u16_f16): Likewise.
6924 (__arm_vcvtaq_m_s32_f32): Likewise.
6925 (__arm_vcvtaq_m_u32_f32): Likewise.
6926 (__arm_vcvtq_m_f16_s16): Likewise.
6927 (__arm_vcvtq_m_f16_u16): Likewise.
6928 (__arm_vcvtq_m_f32_s32): Likewise.
6929 (__arm_vcvtq_m_f32_u32): Likewise.
6930 (vcvtaq_m): Define polymorphic variant.
6931 (vcvtq_m): Likewise.
6932 (vabavq): Likewise.
6933 (vshlcq): Likewise.
6934 (vbicq_m_n): Likewise.
6935 (vqrshrnbq_n): Likewise.
6936 (vqrshrunbq_n): Likewise.
6937 * config/arm/arm_mve_builtins.def
6938 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
6939 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
6940 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
6941 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
6942 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
6943 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
6944 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
6945 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
6946 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
6947 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
6948 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
6949 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
6950 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
6951 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
6952 * config/arm/mve.md (VBICQ_M_N): Define iterator.
6953 (VCVTAQ_M): Likewise.
6954 (VCVTQ_M_TO_F): Likewise.
6955 (VQRSHRNBQ_N): Likewise.
6956 (VABAVQ): Likewise.
6957 (VSHLCQ): Likewise.
6958 (VRMLALDAVHAQ): Likewise.
6959 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
6960 (mve_vcmpeqq_m_f<mode>): Likewise.
6961 (mve_vcvtaq_m_<supf><mode>): Likewise.
6962 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
6963 (mve_vqrshrnbq_n_<supf><mode>): Likewise.
6964 (mve_vqrshrunbq_n_s<mode>): Likewise.
6965 (mve_vrmlaldavhaq_<supf>v4si): Likewise.
6966 (mve_vabavq_<supf><mode>): Likewise.
6967 (mve_vshlcq_<supf><mode>): Likewise.
6968 (mve_vshlcq_<supf><mode>): Likewise.
6969 (mve_vshlcq_vec_<supf><mode>): Define RTL expand.
6970 (mve_vshlcq_carry_<supf><mode>): Likewise.
6972 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
6973 Mihail Ionescu <mihail.ionescu@arm.com>
6974 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6976 * config/arm/arm_mve.h (vqmovntq_u16): Define macro.
6977 (vqmovnbq_u16): Likewise.
6978 (vmulltq_poly_p8): Likewise.
6979 (vmullbq_poly_p8): Likewise.
6980 (vmovntq_u16): Likewise.
6981 (vmovnbq_u16): Likewise.
6982 (vmlaldavxq_u16): Likewise.
6983 (vmlaldavq_u16): Likewise.
6984 (vqmovuntq_s16): Likewise.
6985 (vqmovunbq_s16): Likewise.
6986 (vshlltq_n_u8): Likewise.
6987 (vshllbq_n_u8): Likewise.
6988 (vorrq_n_u16): Likewise.
6989 (vbicq_n_u16): Likewise.
6990 (vcmpneq_n_f16): Likewise.
6991 (vcmpneq_f16): Likewise.
6992 (vcmpltq_n_f16): Likewise.
6993 (vcmpltq_f16): Likewise.
6994 (vcmpleq_n_f16): Likewise.
6995 (vcmpleq_f16): Likewise.
6996 (vcmpgtq_n_f16): Likewise.
6997 (vcmpgtq_f16): Likewise.
6998 (vcmpgeq_n_f16): Likewise.
6999 (vcmpgeq_f16): Likewise.
7000 (vcmpeqq_n_f16): Likewise.
7001 (vcmpeqq_f16): Likewise.
7002 (vsubq_f16): Likewise.
7003 (vqmovntq_s16): Likewise.
7004 (vqmovnbq_s16): Likewise.
7005 (vqdmulltq_s16): Likewise.
7006 (vqdmulltq_n_s16): Likewise.
7007 (vqdmullbq_s16): Likewise.
7008 (vqdmullbq_n_s16): Likewise.
7009 (vorrq_f16): Likewise.
7010 (vornq_f16): Likewise.
7011 (vmulq_n_f16): Likewise.
7012 (vmulq_f16): Likewise.
7013 (vmovntq_s16): Likewise.
7014 (vmovnbq_s16): Likewise.
7015 (vmlsldavxq_s16): Likewise.
7016 (vmlsldavq_s16): Likewise.
7017 (vmlaldavxq_s16): Likewise.
7018 (vmlaldavq_s16): Likewise.
7019 (vminnmvq_f16): Likewise.
7020 (vminnmq_f16): Likewise.
7021 (vminnmavq_f16): Likewise.
7022 (vminnmaq_f16): Likewise.
7023 (vmaxnmvq_f16): Likewise.
7024 (vmaxnmq_f16): Likewise.
7025 (vmaxnmavq_f16): Likewise.
7026 (vmaxnmaq_f16): Likewise.
7027 (veorq_f16): Likewise.
7028 (vcmulq_rot90_f16): Likewise.
7029 (vcmulq_rot270_f16): Likewise.
7030 (vcmulq_rot180_f16): Likewise.
7031 (vcmulq_f16): Likewise.
7032 (vcaddq_rot90_f16): Likewise.
7033 (vcaddq_rot270_f16): Likewise.
7034 (vbicq_f16): Likewise.
7035 (vandq_f16): Likewise.
7036 (vaddq_n_f16): Likewise.
7037 (vabdq_f16): Likewise.
7038 (vshlltq_n_s8): Likewise.
7039 (vshllbq_n_s8): Likewise.
7040 (vorrq_n_s16): Likewise.
7041 (vbicq_n_s16): Likewise.
7042 (vqmovntq_u32): Likewise.
7043 (vqmovnbq_u32): Likewise.
7044 (vmulltq_poly_p16): Likewise.
7045 (vmullbq_poly_p16): Likewise.
7046 (vmovntq_u32): Likewise.
7047 (vmovnbq_u32): Likewise.
7048 (vmlaldavxq_u32): Likewise.
7049 (vmlaldavq_u32): Likewise.
7050 (vqmovuntq_s32): Likewise.
7051 (vqmovunbq_s32): Likewise.
7052 (vshlltq_n_u16): Likewise.
7053 (vshllbq_n_u16): Likewise.
7054 (vorrq_n_u32): Likewise.
7055 (vbicq_n_u32): Likewise.
7056 (vcmpneq_n_f32): Likewise.
7057 (vcmpneq_f32): Likewise.
7058 (vcmpltq_n_f32): Likewise.
7059 (vcmpltq_f32): Likewise.
7060 (vcmpleq_n_f32): Likewise.
7061 (vcmpleq_f32): Likewise.
7062 (vcmpgtq_n_f32): Likewise.
7063 (vcmpgtq_f32): Likewise.
7064 (vcmpgeq_n_f32): Likewise.
7065 (vcmpgeq_f32): Likewise.
7066 (vcmpeqq_n_f32): Likewise.
7067 (vcmpeqq_f32): Likewise.
7068 (vsubq_f32): Likewise.
7069 (vqmovntq_s32): Likewise.
7070 (vqmovnbq_s32): Likewise.
7071 (vqdmulltq_s32): Likewise.
7072 (vqdmulltq_n_s32): Likewise.
7073 (vqdmullbq_s32): Likewise.
7074 (vqdmullbq_n_s32): Likewise.
7075 (vorrq_f32): Likewise.
7076 (vornq_f32): Likewise.
7077 (vmulq_n_f32): Likewise.
7078 (vmulq_f32): Likewise.
7079 (vmovntq_s32): Likewise.
7080 (vmovnbq_s32): Likewise.
7081 (vmlsldavxq_s32): Likewise.
7082 (vmlsldavq_s32): Likewise.
7083 (vmlaldavxq_s32): Likewise.
7084 (vmlaldavq_s32): Likewise.
7085 (vminnmvq_f32): Likewise.
7086 (vminnmq_f32): Likewise.
7087 (vminnmavq_f32): Likewise.
7088 (vminnmaq_f32): Likewise.
7089 (vmaxnmvq_f32): Likewise.
7090 (vmaxnmq_f32): Likewise.
7091 (vmaxnmavq_f32): Likewise.
7092 (vmaxnmaq_f32): Likewise.
7093 (veorq_f32): Likewise.
7094 (vcmulq_rot90_f32): Likewise.
7095 (vcmulq_rot270_f32): Likewise.
7096 (vcmulq_rot180_f32): Likewise.
7097 (vcmulq_f32): Likewise.
7098 (vcaddq_rot90_f32): Likewise.
7099 (vcaddq_rot270_f32): Likewise.
7100 (vbicq_f32): Likewise.
7101 (vandq_f32): Likewise.
7102 (vaddq_n_f32): Likewise.
7103 (vabdq_f32): Likewise.
7104 (vshlltq_n_s16): Likewise.
7105 (vshllbq_n_s16): Likewise.
7106 (vorrq_n_s32): Likewise.
7107 (vbicq_n_s32): Likewise.
7108 (vrmlaldavhq_u32): Likewise.
7109 (vctp8q_m): Likewise.
7110 (vctp64q_m): Likewise.
7111 (vctp32q_m): Likewise.
7112 (vctp16q_m): Likewise.
7113 (vaddlvaq_u32): Likewise.
7114 (vrmlsldavhxq_s32): Likewise.
7115 (vrmlsldavhq_s32): Likewise.
7116 (vrmlaldavhxq_s32): Likewise.
7117 (vrmlaldavhq_s32): Likewise.
7118 (vcvttq_f16_f32): Likewise.
7119 (vcvtbq_f16_f32): Likewise.
7120 (vaddlvaq_s32): Likewise.
7121 (__arm_vqmovntq_u16): Define intrinsic.
7122 (__arm_vqmovnbq_u16): Likewise.
7123 (__arm_vmulltq_poly_p8): Likewise.
7124 (__arm_vmullbq_poly_p8): Likewise.
7125 (__arm_vmovntq_u16): Likewise.
7126 (__arm_vmovnbq_u16): Likewise.
7127 (__arm_vmlaldavxq_u16): Likewise.
7128 (__arm_vmlaldavq_u16): Likewise.
7129 (__arm_vqmovuntq_s16): Likewise.
7130 (__arm_vqmovunbq_s16): Likewise.
7131 (__arm_vshlltq_n_u8): Likewise.
7132 (__arm_vshllbq_n_u8): Likewise.
7133 (__arm_vorrq_n_u16): Likewise.
7134 (__arm_vbicq_n_u16): Likewise.
7135 (__arm_vcmpneq_n_f16): Likewise.
7136 (__arm_vcmpneq_f16): Likewise.
7137 (__arm_vcmpltq_n_f16): Likewise.
7138 (__arm_vcmpltq_f16): Likewise.
7139 (__arm_vcmpleq_n_f16): Likewise.
7140 (__arm_vcmpleq_f16): Likewise.
7141 (__arm_vcmpgtq_n_f16): Likewise.
7142 (__arm_vcmpgtq_f16): Likewise.
7143 (__arm_vcmpgeq_n_f16): Likewise.
7144 (__arm_vcmpgeq_f16): Likewise.
7145 (__arm_vcmpeqq_n_f16): Likewise.
7146 (__arm_vcmpeqq_f16): Likewise.
7147 (__arm_vsubq_f16): Likewise.
7148 (__arm_vqmovntq_s16): Likewise.
7149 (__arm_vqmovnbq_s16): Likewise.
7150 (__arm_vqdmulltq_s16): Likewise.
7151 (__arm_vqdmulltq_n_s16): Likewise.
7152 (__arm_vqdmullbq_s16): Likewise.
7153 (__arm_vqdmullbq_n_s16): Likewise.
7154 (__arm_vorrq_f16): Likewise.
7155 (__arm_vornq_f16): Likewise.
7156 (__arm_vmulq_n_f16): Likewise.
7157 (__arm_vmulq_f16): Likewise.
7158 (__arm_vmovntq_s16): Likewise.
7159 (__arm_vmovnbq_s16): Likewise.
7160 (__arm_vmlsldavxq_s16): Likewise.
7161 (__arm_vmlsldavq_s16): Likewise.
7162 (__arm_vmlaldavxq_s16): Likewise.
7163 (__arm_vmlaldavq_s16): Likewise.
7164 (__arm_vminnmvq_f16): Likewise.
7165 (__arm_vminnmq_f16): Likewise.
7166 (__arm_vminnmavq_f16): Likewise.
7167 (__arm_vminnmaq_f16): Likewise.
7168 (__arm_vmaxnmvq_f16): Likewise.
7169 (__arm_vmaxnmq_f16): Likewise.
7170 (__arm_vmaxnmavq_f16): Likewise.
7171 (__arm_vmaxnmaq_f16): Likewise.
7172 (__arm_veorq_f16): Likewise.
7173 (__arm_vcmulq_rot90_f16): Likewise.
7174 (__arm_vcmulq_rot270_f16): Likewise.
7175 (__arm_vcmulq_rot180_f16): Likewise.
7176 (__arm_vcmulq_f16): Likewise.
7177 (__arm_vcaddq_rot90_f16): Likewise.
7178 (__arm_vcaddq_rot270_f16): Likewise.
7179 (__arm_vbicq_f16): Likewise.
7180 (__arm_vandq_f16): Likewise.
7181 (__arm_vaddq_n_f16): Likewise.
7182 (__arm_vabdq_f16): Likewise.
7183 (__arm_vshlltq_n_s8): Likewise.
7184 (__arm_vshllbq_n_s8): Likewise.
7185 (__arm_vorrq_n_s16): Likewise.
7186 (__arm_vbicq_n_s16): Likewise.
7187 (__arm_vqmovntq_u32): Likewise.
7188 (__arm_vqmovnbq_u32): Likewise.
7189 (__arm_vmulltq_poly_p16): Likewise.
7190 (__arm_vmullbq_poly_p16): Likewise.
7191 (__arm_vmovntq_u32): Likewise.
7192 (__arm_vmovnbq_u32): Likewise.
7193 (__arm_vmlaldavxq_u32): Likewise.
7194 (__arm_vmlaldavq_u32): Likewise.
7195 (__arm_vqmovuntq_s32): Likewise.
7196 (__arm_vqmovunbq_s32): Likewise.
7197 (__arm_vshlltq_n_u16): Likewise.
7198 (__arm_vshllbq_n_u16): Likewise.
7199 (__arm_vorrq_n_u32): Likewise.
7200 (__arm_vbicq_n_u32): Likewise.
7201 (__arm_vcmpneq_n_f32): Likewise.
7202 (__arm_vcmpneq_f32): Likewise.
7203 (__arm_vcmpltq_n_f32): Likewise.
7204 (__arm_vcmpltq_f32): Likewise.
7205 (__arm_vcmpleq_n_f32): Likewise.
7206 (__arm_vcmpleq_f32): Likewise.
7207 (__arm_vcmpgtq_n_f32): Likewise.
7208 (__arm_vcmpgtq_f32): Likewise.
7209 (__arm_vcmpgeq_n_f32): Likewise.
7210 (__arm_vcmpgeq_f32): Likewise.
7211 (__arm_vcmpeqq_n_f32): Likewise.
7212 (__arm_vcmpeqq_f32): Likewise.
7213 (__arm_vsubq_f32): Likewise.
7214 (__arm_vqmovntq_s32): Likewise.
7215 (__arm_vqmovnbq_s32): Likewise.
7216 (__arm_vqdmulltq_s32): Likewise.
7217 (__arm_vqdmulltq_n_s32): Likewise.
7218 (__arm_vqdmullbq_s32): Likewise.
7219 (__arm_vqdmullbq_n_s32): Likewise.
7220 (__arm_vorrq_f32): Likewise.
7221 (__arm_vornq_f32): Likewise.
7222 (__arm_vmulq_n_f32): Likewise.
7223 (__arm_vmulq_f32): Likewise.
7224 (__arm_vmovntq_s32): Likewise.
7225 (__arm_vmovnbq_s32): Likewise.
7226 (__arm_vmlsldavxq_s32): Likewise.
7227 (__arm_vmlsldavq_s32): Likewise.
7228 (__arm_vmlaldavxq_s32): Likewise.
7229 (__arm_vmlaldavq_s32): Likewise.
7230 (__arm_vminnmvq_f32): Likewise.
7231 (__arm_vminnmq_f32): Likewise.
7232 (__arm_vminnmavq_f32): Likewise.
7233 (__arm_vminnmaq_f32): Likewise.
7234 (__arm_vmaxnmvq_f32): Likewise.
7235 (__arm_vmaxnmq_f32): Likewise.
7236 (__arm_vmaxnmavq_f32): Likewise.
7237 (__arm_vmaxnmaq_f32): Likewise.
7238 (__arm_veorq_f32): Likewise.
7239 (__arm_vcmulq_rot90_f32): Likewise.
7240 (__arm_vcmulq_rot270_f32): Likewise.
7241 (__arm_vcmulq_rot180_f32): Likewise.
7242 (__arm_vcmulq_f32): Likewise.
7243 (__arm_vcaddq_rot90_f32): Likewise.
7244 (__arm_vcaddq_rot270_f32): Likewise.
7245 (__arm_vbicq_f32): Likewise.
7246 (__arm_vandq_f32): Likewise.
7247 (__arm_vaddq_n_f32): Likewise.
7248 (__arm_vabdq_f32): Likewise.
7249 (__arm_vshlltq_n_s16): Likewise.
7250 (__arm_vshllbq_n_s16): Likewise.
7251 (__arm_vorrq_n_s32): Likewise.
7252 (__arm_vbicq_n_s32): Likewise.
7253 (__arm_vrmlaldavhq_u32): Likewise.
7254 (__arm_vctp8q_m): Likewise.
7255 (__arm_vctp64q_m): Likewise.
7256 (__arm_vctp32q_m): Likewise.
7257 (__arm_vctp16q_m): Likewise.
7258 (__arm_vaddlvaq_u32): Likewise.
7259 (__arm_vrmlsldavhxq_s32): Likewise.
7260 (__arm_vrmlsldavhq_s32): Likewise.
7261 (__arm_vrmlaldavhxq_s32): Likewise.
7262 (__arm_vrmlaldavhq_s32): Likewise.
7263 (__arm_vcvttq_f16_f32): Likewise.
7264 (__arm_vcvtbq_f16_f32): Likewise.
7265 (__arm_vaddlvaq_s32): Likewise.
7266 (vst4q): Define polymorphic variant.
7267 (vrndxq): Likewise.
7268 (vrndq): Likewise.
7269 (vrndpq): Likewise.
7270 (vrndnq): Likewise.
7271 (vrndmq): Likewise.
7272 (vrndaq): Likewise.
7273 (vrev64q): Likewise.
7274 (vnegq): Likewise.
7275 (vdupq_n): Likewise.
7276 (vabsq): Likewise.
7277 (vrev32q): Likewise.
7278 (vcvtbq_f32): Likewise.
7279 (vcvttq_f32): Likewise.
7280 (vcvtq): Likewise.
7281 (vsubq_n): Likewise.
7282 (vbrsrq_n): Likewise.
7283 (vcvtq_n): Likewise.
7284 (vsubq): Likewise.
7285 (vorrq): Likewise.
7286 (vabdq): Likewise.
7287 (vaddq_n): Likewise.
7288 (vandq): Likewise.
7289 (vbicq): Likewise.
7290 (vornq): Likewise.
7291 (vmulq_n): Likewise.
7292 (vmulq): Likewise.
7293 (vcaddq_rot270): Likewise.
7294 (vcmpeqq_n): Likewise.
7295 (vcmpeqq): Likewise.
7296 (vcaddq_rot90): Likewise.
7297 (vcmpgeq_n): Likewise.
7298 (vcmpgeq): Likewise.
7299 (vcmpgtq_n): Likewise.
7300 (vcmpgtq): Likewise.
7301 (vcmpgtq): Likewise.
7302 (vcmpleq_n): Likewise.
7303 (vcmpleq_n): Likewise.
7304 (vcmpleq): Likewise.
7305 (vcmpleq): Likewise.
7306 (vcmpltq_n): Likewise.
7307 (vcmpltq_n): Likewise.
7308 (vcmpltq): Likewise.
7309 (vcmpltq): Likewise.
7310 (vcmpneq_n): Likewise.
7311 (vcmpneq_n): Likewise.
7312 (vcmpneq): Likewise.
7313 (vcmpneq): Likewise.
7314 (vcmulq): Likewise.
7315 (vcmulq): Likewise.
7316 (vcmulq_rot180): Likewise.
7317 (vcmulq_rot180): Likewise.
7318 (vcmulq_rot270): Likewise.
7319 (vcmulq_rot270): Likewise.
7320 (vcmulq_rot90): Likewise.
7321 (vcmulq_rot90): Likewise.
7322 (veorq): Likewise.
7323 (veorq): Likewise.
7324 (vmaxnmaq): Likewise.
7325 (vmaxnmaq): Likewise.
7326 (vmaxnmavq): Likewise.
7327 (vmaxnmavq): Likewise.
7328 (vmaxnmq): Likewise.
7329 (vmaxnmq): Likewise.
7330 (vmaxnmvq): Likewise.
7331 (vmaxnmvq): Likewise.
7332 (vminnmaq): Likewise.
7333 (vminnmaq): Likewise.
7334 (vminnmavq): Likewise.
7335 (vminnmavq): Likewise.
7336 (vminnmq): Likewise.
7337 (vminnmq): Likewise.
7338 (vminnmvq): Likewise.
7339 (vminnmvq): Likewise.
7340 (vbicq_n): Likewise.
7341 (vqmovntq): Likewise.
7342 (vqmovntq): Likewise.
7343 (vqmovnbq): Likewise.
7344 (vqmovnbq): Likewise.
7345 (vmulltq_poly): Likewise.
7346 (vmulltq_poly): Likewise.
7347 (vmullbq_poly): Likewise.
7348 (vmullbq_poly): Likewise.
7349 (vmovntq): Likewise.
7350 (vmovntq): Likewise.
7351 (vmovnbq): Likewise.
7352 (vmovnbq): Likewise.
7353 (vmlaldavxq): Likewise.
7354 (vmlaldavxq): Likewise.
7355 (vqmovuntq): Likewise.
7356 (vqmovuntq): Likewise.
7357 (vshlltq_n): Likewise.
7358 (vshlltq_n): Likewise.
7359 (vshllbq_n): Likewise.
7360 (vshllbq_n): Likewise.
7361 (vorrq_n): Likewise.
7362 (vorrq_n): Likewise.
7363 (vmlaldavq): Likewise.
7364 (vmlaldavq): Likewise.
7365 (vqmovunbq): Likewise.
7366 (vqmovunbq): Likewise.
7367 (vqdmulltq_n): Likewise.
7368 (vqdmulltq_n): Likewise.
7369 (vqdmulltq): Likewise.
7370 (vqdmulltq): Likewise.
7371 (vqdmullbq_n): Likewise.
7372 (vqdmullbq_n): Likewise.
7373 (vqdmullbq): Likewise.
7374 (vqdmullbq): Likewise.
7375 (vaddlvaq): Likewise.
7376 (vaddlvaq): Likewise.
7377 (vrmlaldavhq): Likewise.
7378 (vrmlaldavhq): Likewise.
7379 (vrmlaldavhxq): Likewise.
7380 (vrmlaldavhxq): Likewise.
7381 (vrmlsldavhq): Likewise.
7382 (vrmlsldavhq): Likewise.
7383 (vrmlsldavhxq): Likewise.
7384 (vrmlsldavhxq): Likewise.
7385 (vmlsldavxq): Likewise.
7386 (vmlsldavxq): Likewise.
7387 (vmlsldavq): Likewise.
7388 (vmlsldavq): Likewise.
7389 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
7390 (BINOP_NONE_NONE_NONE): Likewise.
7391 (BINOP_UNONE_NONE_NONE): Likewise.
7392 (BINOP_UNONE_UNONE_IMM): Likewise.
7393 (BINOP_UNONE_UNONE_NONE): Likewise.
7394 (BINOP_UNONE_UNONE_UNONE): Likewise.
7395 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
7396 (mve_vaddlvaq_<supf>v4si): Likewise.
7397 (mve_vaddq_n_f<mode>): Likewise.
7398 (mve_vandq_f<mode>): Likewise.
7399 (mve_vbicq_f<mode>): Likewise.
7400 (mve_vbicq_n_<supf><mode>): Likewise.
7401 (mve_vcaddq_rot270_f<mode>): Likewise.
7402 (mve_vcaddq_rot90_f<mode>): Likewise.
7403 (mve_vcmpeqq_f<mode>): Likewise.
7404 (mve_vcmpeqq_n_f<mode>): Likewise.
7405 (mve_vcmpgeq_f<mode>): Likewise.
7406 (mve_vcmpgeq_n_f<mode>): Likewise.
7407 (mve_vcmpgtq_f<mode>): Likewise.
7408 (mve_vcmpgtq_n_f<mode>): Likewise.
7409 (mve_vcmpleq_f<mode>): Likewise.
7410 (mve_vcmpleq_n_f<mode>): Likewise.
7411 (mve_vcmpltq_f<mode>): Likewise.
7412 (mve_vcmpltq_n_f<mode>): Likewise.
7413 (mve_vcmpneq_f<mode>): Likewise.
7414 (mve_vcmpneq_n_f<mode>): Likewise.
7415 (mve_vcmulq_f<mode>): Likewise.
7416 (mve_vcmulq_rot180_f<mode>): Likewise.
7417 (mve_vcmulq_rot270_f<mode>): Likewise.
7418 (mve_vcmulq_rot90_f<mode>): Likewise.
7419 (mve_vctp<mode1>q_mhi): Likewise.
7420 (mve_vcvtbq_f16_f32v8hf): Likewise.
7421 (mve_vcvttq_f16_f32v8hf): Likewise.
7422 (mve_veorq_f<mode>): Likewise.
7423 (mve_vmaxnmaq_f<mode>): Likewise.
7424 (mve_vmaxnmavq_f<mode>): Likewise.
7425 (mve_vmaxnmq_f<mode>): Likewise.
7426 (mve_vmaxnmvq_f<mode>): Likewise.
7427 (mve_vminnmaq_f<mode>): Likewise.
7428 (mve_vminnmavq_f<mode>): Likewise.
7429 (mve_vminnmq_f<mode>): Likewise.
7430 (mve_vminnmvq_f<mode>): Likewise.
7431 (mve_vmlaldavq_<supf><mode>): Likewise.
7432 (mve_vmlaldavxq_<supf><mode>): Likewise.
7433 (mve_vmlsldavq_s<mode>): Likewise.
7434 (mve_vmlsldavxq_s<mode>): Likewise.
7435 (mve_vmovnbq_<supf><mode>): Likewise.
7436 (mve_vmovntq_<supf><mode>): Likewise.
7437 (mve_vmulq_f<mode>): Likewise.
7438 (mve_vmulq_n_f<mode>): Likewise.
7439 (mve_vornq_f<mode>): Likewise.
7440 (mve_vorrq_f<mode>): Likewise.
7441 (mve_vorrq_n_<supf><mode>): Likewise.
7442 (mve_vqdmullbq_n_s<mode>): Likewise.
7443 (mve_vqdmullbq_s<mode>): Likewise.
7444 (mve_vqdmulltq_n_s<mode>): Likewise.
7445 (mve_vqdmulltq_s<mode>): Likewise.
7446 (mve_vqmovnbq_<supf><mode>): Likewise.
7447 (mve_vqmovntq_<supf><mode>): Likewise.
7448 (mve_vqmovunbq_s<mode>): Likewise.
7449 (mve_vqmovuntq_s<mode>): Likewise.
7450 (mve_vrmlaldavhxq_sv4si): Likewise.
7451 (mve_vrmlsldavhq_sv4si): Likewise.
7452 (mve_vrmlsldavhxq_sv4si): Likewise.
7453 (mve_vshllbq_n_<supf><mode>): Likewise.
7454 (mve_vshlltq_n_<supf><mode>): Likewise.
7455 (mve_vsubq_f<mode>): Likewise.
7456 (mve_vmulltq_poly_p<mode>): Likewise.
7457 (mve_vmullbq_poly_p<mode>): Likewise.
7458 (mve_vrmlaldavhq_<supf>v4si): Likewise.
7460 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
7461 Mihail Ionescu <mihail.ionescu@arm.com>
7462 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7464 * config/arm/arm_mve.h (vsubq_u8): Define macro.
7465 (vsubq_n_u8): Likewise.
7466 (vrmulhq_u8): Likewise.
7467 (vrhaddq_u8): Likewise.
7468 (vqsubq_u8): Likewise.
7469 (vqsubq_n_u8): Likewise.
7470 (vqaddq_u8): Likewise.
7471 (vqaddq_n_u8): Likewise.
7472 (vorrq_u8): Likewise.
7473 (vornq_u8): Likewise.
7474 (vmulq_u8): Likewise.
7475 (vmulq_n_u8): Likewise.
7476 (vmulltq_int_u8): Likewise.
7477 (vmullbq_int_u8): Likewise.
7478 (vmulhq_u8): Likewise.
7479 (vmladavq_u8): Likewise.
7480 (vminvq_u8): Likewise.
7481 (vminq_u8): Likewise.
7482 (vmaxvq_u8): Likewise.
7483 (vmaxq_u8): Likewise.
7484 (vhsubq_u8): Likewise.
7485 (vhsubq_n_u8): Likewise.
7486 (vhaddq_u8): Likewise.
7487 (vhaddq_n_u8): Likewise.
7488 (veorq_u8): Likewise.
7489 (vcmpneq_n_u8): Likewise.
7490 (vcmphiq_u8): Likewise.
7491 (vcmphiq_n_u8): Likewise.
7492 (vcmpeqq_u8): Likewise.
7493 (vcmpeqq_n_u8): Likewise.
7494 (vcmpcsq_u8): Likewise.
7495 (vcmpcsq_n_u8): Likewise.
7496 (vcaddq_rot90_u8): Likewise.
7497 (vcaddq_rot270_u8): Likewise.
7498 (vbicq_u8): Likewise.
7499 (vandq_u8): Likewise.
7500 (vaddvq_p_u8): Likewise.
7501 (vaddvaq_u8): Likewise.
7502 (vaddq_n_u8): Likewise.
7503 (vabdq_u8): Likewise.
7504 (vshlq_r_u8): Likewise.
7505 (vrshlq_u8): Likewise.
7506 (vrshlq_n_u8): Likewise.
7507 (vqshlq_u8): Likewise.
7508 (vqshlq_r_u8): Likewise.
7509 (vqrshlq_u8): Likewise.
7510 (vqrshlq_n_u8): Likewise.
7511 (vminavq_s8): Likewise.
7512 (vminaq_s8): Likewise.
7513 (vmaxavq_s8): Likewise.
7514 (vmaxaq_s8): Likewise.
7515 (vbrsrq_n_u8): Likewise.
7516 (vshlq_n_u8): Likewise.
7517 (vrshrq_n_u8): Likewise.
7518 (vqshlq_n_u8): Likewise.
7519 (vcmpneq_n_s8): Likewise.
7520 (vcmpltq_s8): Likewise.
7521 (vcmpltq_n_s8): Likewise.
7522 (vcmpleq_s8): Likewise.
7523 (vcmpleq_n_s8): Likewise.
7524 (vcmpgtq_s8): Likewise.
7525 (vcmpgtq_n_s8): Likewise.
7526 (vcmpgeq_s8): Likewise.
7527 (vcmpgeq_n_s8): Likewise.
7528 (vcmpeqq_s8): Likewise.
7529 (vcmpeqq_n_s8): Likewise.
7530 (vqshluq_n_s8): Likewise.
7531 (vaddvq_p_s8): Likewise.
7532 (vsubq_s8): Likewise.
7533 (vsubq_n_s8): Likewise.
7534 (vshlq_r_s8): Likewise.
7535 (vrshlq_s8): Likewise.
7536 (vrshlq_n_s8): Likewise.
7537 (vrmulhq_s8): Likewise.
7538 (vrhaddq_s8): Likewise.
7539 (vqsubq_s8): Likewise.
7540 (vqsubq_n_s8): Likewise.
7541 (vqshlq_s8): Likewise.
7542 (vqshlq_r_s8): Likewise.
7543 (vqrshlq_s8): Likewise.
7544 (vqrshlq_n_s8): Likewise.
7545 (vqrdmulhq_s8): Likewise.
7546 (vqrdmulhq_n_s8): Likewise.
7547 (vqdmulhq_s8): Likewise.
7548 (vqdmulhq_n_s8): Likewise.
7549 (vqaddq_s8): Likewise.
7550 (vqaddq_n_s8): Likewise.
7551 (vorrq_s8): Likewise.
7552 (vornq_s8): Likewise.
7553 (vmulq_s8): Likewise.
7554 (vmulq_n_s8): Likewise.
7555 (vmulltq_int_s8): Likewise.
7556 (vmullbq_int_s8): Likewise.
7557 (vmulhq_s8): Likewise.
7558 (vmlsdavxq_s8): Likewise.
7559 (vmlsdavq_s8): Likewise.
7560 (vmladavxq_s8): Likewise.
7561 (vmladavq_s8): Likewise.
7562 (vminvq_s8): Likewise.
7563 (vminq_s8): Likewise.
7564 (vmaxvq_s8): Likewise.
7565 (vmaxq_s8): Likewise.
7566 (vhsubq_s8): Likewise.
7567 (vhsubq_n_s8): Likewise.
7568 (vhcaddq_rot90_s8): Likewise.
7569 (vhcaddq_rot270_s8): Likewise.
7570 (vhaddq_s8): Likewise.
7571 (vhaddq_n_s8): Likewise.
7572 (veorq_s8): Likewise.
7573 (vcaddq_rot90_s8): Likewise.
7574 (vcaddq_rot270_s8): Likewise.
7575 (vbrsrq_n_s8): Likewise.
7576 (vbicq_s8): Likewise.
7577 (vandq_s8): Likewise.
7578 (vaddvaq_s8): Likewise.
7579 (vaddq_n_s8): Likewise.
7580 (vabdq_s8): Likewise.
7581 (vshlq_n_s8): Likewise.
7582 (vrshrq_n_s8): Likewise.
7583 (vqshlq_n_s8): Likewise.
7584 (vsubq_u16): Likewise.
7585 (vsubq_n_u16): Likewise.
7586 (vrmulhq_u16): Likewise.
7587 (vrhaddq_u16): Likewise.
7588 (vqsubq_u16): Likewise.
7589 (vqsubq_n_u16): Likewise.
7590 (vqaddq_u16): Likewise.
7591 (vqaddq_n_u16): Likewise.
7592 (vorrq_u16): Likewise.
7593 (vornq_u16): Likewise.
7594 (vmulq_u16): Likewise.
7595 (vmulq_n_u16): Likewise.
7596 (vmulltq_int_u16): Likewise.
7597 (vmullbq_int_u16): Likewise.
7598 (vmulhq_u16): Likewise.
7599 (vmladavq_u16): Likewise.
7600 (vminvq_u16): Likewise.
7601 (vminq_u16): Likewise.
7602 (vmaxvq_u16): Likewise.
7603 (vmaxq_u16): Likewise.
7604 (vhsubq_u16): Likewise.
7605 (vhsubq_n_u16): Likewise.
7606 (vhaddq_u16): Likewise.
7607 (vhaddq_n_u16): Likewise.
7608 (veorq_u16): Likewise.
7609 (vcmpneq_n_u16): Likewise.
7610 (vcmphiq_u16): Likewise.
7611 (vcmphiq_n_u16): Likewise.
7612 (vcmpeqq_u16): Likewise.
7613 (vcmpeqq_n_u16): Likewise.
7614 (vcmpcsq_u16): Likewise.
7615 (vcmpcsq_n_u16): Likewise.
7616 (vcaddq_rot90_u16): Likewise.
7617 (vcaddq_rot270_u16): Likewise.
7618 (vbicq_u16): Likewise.
7619 (vandq_u16): Likewise.
7620 (vaddvq_p_u16): Likewise.
7621 (vaddvaq_u16): Likewise.
7622 (vaddq_n_u16): Likewise.
7623 (vabdq_u16): Likewise.
7624 (vshlq_r_u16): Likewise.
7625 (vrshlq_u16): Likewise.
7626 (vrshlq_n_u16): Likewise.
7627 (vqshlq_u16): Likewise.
7628 (vqshlq_r_u16): Likewise.
7629 (vqrshlq_u16): Likewise.
7630 (vqrshlq_n_u16): Likewise.
7631 (vminavq_s16): Likewise.
7632 (vminaq_s16): Likewise.
7633 (vmaxavq_s16): Likewise.
7634 (vmaxaq_s16): Likewise.
7635 (vbrsrq_n_u16): Likewise.
7636 (vshlq_n_u16): Likewise.
7637 (vrshrq_n_u16): Likewise.
7638 (vqshlq_n_u16): Likewise.
7639 (vcmpneq_n_s16): Likewise.
7640 (vcmpltq_s16): Likewise.
7641 (vcmpltq_n_s16): Likewise.
7642 (vcmpleq_s16): Likewise.
7643 (vcmpleq_n_s16): Likewise.
7644 (vcmpgtq_s16): Likewise.
7645 (vcmpgtq_n_s16): Likewise.
7646 (vcmpgeq_s16): Likewise.
7647 (vcmpgeq_n_s16): Likewise.
7648 (vcmpeqq_s16): Likewise.
7649 (vcmpeqq_n_s16): Likewise.
7650 (vqshluq_n_s16): Likewise.
7651 (vaddvq_p_s16): Likewise.
7652 (vsubq_s16): Likewise.
7653 (vsubq_n_s16): Likewise.
7654 (vshlq_r_s16): Likewise.
7655 (vrshlq_s16): Likewise.
7656 (vrshlq_n_s16): Likewise.
7657 (vrmulhq_s16): Likewise.
7658 (vrhaddq_s16): Likewise.
7659 (vqsubq_s16): Likewise.
7660 (vqsubq_n_s16): Likewise.
7661 (vqshlq_s16): Likewise.
7662 (vqshlq_r_s16): Likewise.
7663 (vqrshlq_s16): Likewise.
7664 (vqrshlq_n_s16): Likewise.
7665 (vqrdmulhq_s16): Likewise.
7666 (vqrdmulhq_n_s16): Likewise.
7667 (vqdmulhq_s16): Likewise.
7668 (vqdmulhq_n_s16): Likewise.
7669 (vqaddq_s16): Likewise.
7670 (vqaddq_n_s16): Likewise.
7671 (vorrq_s16): Likewise.
7672 (vornq_s16): Likewise.
7673 (vmulq_s16): Likewise.
7674 (vmulq_n_s16): Likewise.
7675 (vmulltq_int_s16): Likewise.
7676 (vmullbq_int_s16): Likewise.
7677 (vmulhq_s16): Likewise.
7678 (vmlsdavxq_s16): Likewise.
7679 (vmlsdavq_s16): Likewise.
7680 (vmladavxq_s16): Likewise.
7681 (vmladavq_s16): Likewise.
7682 (vminvq_s16): Likewise.
7683 (vminq_s16): Likewise.
7684 (vmaxvq_s16): Likewise.
7685 (vmaxq_s16): Likewise.
7686 (vhsubq_s16): Likewise.
7687 (vhsubq_n_s16): Likewise.
7688 (vhcaddq_rot90_s16): Likewise.
7689 (vhcaddq_rot270_s16): Likewise.
7690 (vhaddq_s16): Likewise.
7691 (vhaddq_n_s16): Likewise.
7692 (veorq_s16): Likewise.
7693 (vcaddq_rot90_s16): Likewise.
7694 (vcaddq_rot270_s16): Likewise.
7695 (vbrsrq_n_s16): Likewise.
7696 (vbicq_s16): Likewise.
7697 (vandq_s16): Likewise.
7698 (vaddvaq_s16): Likewise.
7699 (vaddq_n_s16): Likewise.
7700 (vabdq_s16): Likewise.
7701 (vshlq_n_s16): Likewise.
7702 (vrshrq_n_s16): Likewise.
7703 (vqshlq_n_s16): Likewise.
7704 (vsubq_u32): Likewise.
7705 (vsubq_n_u32): Likewise.
7706 (vrmulhq_u32): Likewise.
7707 (vrhaddq_u32): Likewise.
7708 (vqsubq_u32): Likewise.
7709 (vqsubq_n_u32): Likewise.
7710 (vqaddq_u32): Likewise.
7711 (vqaddq_n_u32): Likewise.
7712 (vorrq_u32): Likewise.
7713 (vornq_u32): Likewise.
7714 (vmulq_u32): Likewise.
7715 (vmulq_n_u32): Likewise.
7716 (vmulltq_int_u32): Likewise.
7717 (vmullbq_int_u32): Likewise.
7718 (vmulhq_u32): Likewise.
7719 (vmladavq_u32): Likewise.
7720 (vminvq_u32): Likewise.
7721 (vminq_u32): Likewise.
7722 (vmaxvq_u32): Likewise.
7723 (vmaxq_u32): Likewise.
7724 (vhsubq_u32): Likewise.
7725 (vhsubq_n_u32): Likewise.
7726 (vhaddq_u32): Likewise.
7727 (vhaddq_n_u32): Likewise.
7728 (veorq_u32): Likewise.
7729 (vcmpneq_n_u32): Likewise.
7730 (vcmphiq_u32): Likewise.
7731 (vcmphiq_n_u32): Likewise.
7732 (vcmpeqq_u32): Likewise.
7733 (vcmpeqq_n_u32): Likewise.
7734 (vcmpcsq_u32): Likewise.
7735 (vcmpcsq_n_u32): Likewise.
7736 (vcaddq_rot90_u32): Likewise.
7737 (vcaddq_rot270_u32): Likewise.
7738 (vbicq_u32): Likewise.
7739 (vandq_u32): Likewise.
7740 (vaddvq_p_u32): Likewise.
7741 (vaddvaq_u32): Likewise.
7742 (vaddq_n_u32): Likewise.
7743 (vabdq_u32): Likewise.
7744 (vshlq_r_u32): Likewise.
7745 (vrshlq_u32): Likewise.
7746 (vrshlq_n_u32): Likewise.
7747 (vqshlq_u32): Likewise.
7748 (vqshlq_r_u32): Likewise.
7749 (vqrshlq_u32): Likewise.
7750 (vqrshlq_n_u32): Likewise.
7751 (vminavq_s32): Likewise.
7752 (vminaq_s32): Likewise.
7753 (vmaxavq_s32): Likewise.
7754 (vmaxaq_s32): Likewise.
7755 (vbrsrq_n_u32): Likewise.
7756 (vshlq_n_u32): Likewise.
7757 (vrshrq_n_u32): Likewise.
7758 (vqshlq_n_u32): Likewise.
7759 (vcmpneq_n_s32): Likewise.
7760 (vcmpltq_s32): Likewise.
7761 (vcmpltq_n_s32): Likewise.
7762 (vcmpleq_s32): Likewise.
7763 (vcmpleq_n_s32): Likewise.
7764 (vcmpgtq_s32): Likewise.
7765 (vcmpgtq_n_s32): Likewise.
7766 (vcmpgeq_s32): Likewise.
7767 (vcmpgeq_n_s32): Likewise.
7768 (vcmpeqq_s32): Likewise.
7769 (vcmpeqq_n_s32): Likewise.
7770 (vqshluq_n_s32): Likewise.
7771 (vaddvq_p_s32): Likewise.
7772 (vsubq_s32): Likewise.
7773 (vsubq_n_s32): Likewise.
7774 (vshlq_r_s32): Likewise.
7775 (vrshlq_s32): Likewise.
7776 (vrshlq_n_s32): Likewise.
7777 (vrmulhq_s32): Likewise.
7778 (vrhaddq_s32): Likewise.
7779 (vqsubq_s32): Likewise.
7780 (vqsubq_n_s32): Likewise.
7781 (vqshlq_s32): Likewise.
7782 (vqshlq_r_s32): Likewise.
7783 (vqrshlq_s32): Likewise.
7784 (vqrshlq_n_s32): Likewise.
7785 (vqrdmulhq_s32): Likewise.
7786 (vqrdmulhq_n_s32): Likewise.
7787 (vqdmulhq_s32): Likewise.
7788 (vqdmulhq_n_s32): Likewise.
7789 (vqaddq_s32): Likewise.
7790 (vqaddq_n_s32): Likewise.
7791 (vorrq_s32): Likewise.
7792 (vornq_s32): Likewise.
7793 (vmulq_s32): Likewise.
7794 (vmulq_n_s32): Likewise.
7795 (vmulltq_int_s32): Likewise.
7796 (vmullbq_int_s32): Likewise.
7797 (vmulhq_s32): Likewise.
7798 (vmlsdavxq_s32): Likewise.
7799 (vmlsdavq_s32): Likewise.
7800 (vmladavxq_s32): Likewise.
7801 (vmladavq_s32): Likewise.
7802 (vminvq_s32): Likewise.
7803 (vminq_s32): Likewise.
7804 (vmaxvq_s32): Likewise.
7805 (vmaxq_s32): Likewise.
7806 (vhsubq_s32): Likewise.
7807 (vhsubq_n_s32): Likewise.
7808 (vhcaddq_rot90_s32): Likewise.
7809 (vhcaddq_rot270_s32): Likewise.
7810 (vhaddq_s32): Likewise.
7811 (vhaddq_n_s32): Likewise.
7812 (veorq_s32): Likewise.
7813 (vcaddq_rot90_s32): Likewise.
7814 (vcaddq_rot270_s32): Likewise.
7815 (vbrsrq_n_s32): Likewise.
7816 (vbicq_s32): Likewise.
7817 (vandq_s32): Likewise.
7818 (vaddvaq_s32): Likewise.
7819 (vaddq_n_s32): Likewise.
7820 (vabdq_s32): Likewise.
7821 (vshlq_n_s32): Likewise.
7822 (vrshrq_n_s32): Likewise.
7823 (vqshlq_n_s32): Likewise.
7824 (__arm_vsubq_u8): Define intrinsic.
7825 (__arm_vsubq_n_u8): Likewise.
7826 (__arm_vrmulhq_u8): Likewise.
7827 (__arm_vrhaddq_u8): Likewise.
7828 (__arm_vqsubq_u8): Likewise.
7829 (__arm_vqsubq_n_u8): Likewise.
7830 (__arm_vqaddq_u8): Likewise.
7831 (__arm_vqaddq_n_u8): Likewise.
7832 (__arm_vorrq_u8): Likewise.
7833 (__arm_vornq_u8): Likewise.
7834 (__arm_vmulq_u8): Likewise.
7835 (__arm_vmulq_n_u8): Likewise.
7836 (__arm_vmulltq_int_u8): Likewise.
7837 (__arm_vmullbq_int_u8): Likewise.
7838 (__arm_vmulhq_u8): Likewise.
7839 (__arm_vmladavq_u8): Likewise.
7840 (__arm_vminvq_u8): Likewise.
7841 (__arm_vminq_u8): Likewise.
7842 (__arm_vmaxvq_u8): Likewise.
7843 (__arm_vmaxq_u8): Likewise.
7844 (__arm_vhsubq_u8): Likewise.
7845 (__arm_vhsubq_n_u8): Likewise.
7846 (__arm_vhaddq_u8): Likewise.
7847 (__arm_vhaddq_n_u8): Likewise.
7848 (__arm_veorq_u8): Likewise.
7849 (__arm_vcmpneq_n_u8): Likewise.
7850 (__arm_vcmphiq_u8): Likewise.
7851 (__arm_vcmphiq_n_u8): Likewise.
7852 (__arm_vcmpeqq_u8): Likewise.
7853 (__arm_vcmpeqq_n_u8): Likewise.
7854 (__arm_vcmpcsq_u8): Likewise.
7855 (__arm_vcmpcsq_n_u8): Likewise.
7856 (__arm_vcaddq_rot90_u8): Likewise.
7857 (__arm_vcaddq_rot270_u8): Likewise.
7858 (__arm_vbicq_u8): Likewise.
7859 (__arm_vandq_u8): Likewise.
7860 (__arm_vaddvq_p_u8): Likewise.
7861 (__arm_vaddvaq_u8): Likewise.
7862 (__arm_vaddq_n_u8): Likewise.
7863 (__arm_vabdq_u8): Likewise.
7864 (__arm_vshlq_r_u8): Likewise.
7865 (__arm_vrshlq_u8): Likewise.
7866 (__arm_vrshlq_n_u8): Likewise.
7867 (__arm_vqshlq_u8): Likewise.
7868 (__arm_vqshlq_r_u8): Likewise.
7869 (__arm_vqrshlq_u8): Likewise.
7870 (__arm_vqrshlq_n_u8): Likewise.
7871 (__arm_vminavq_s8): Likewise.
7872 (__arm_vminaq_s8): Likewise.
7873 (__arm_vmaxavq_s8): Likewise.
7874 (__arm_vmaxaq_s8): Likewise.
7875 (__arm_vbrsrq_n_u8): Likewise.
7876 (__arm_vshlq_n_u8): Likewise.
7877 (__arm_vrshrq_n_u8): Likewise.
7878 (__arm_vqshlq_n_u8): Likewise.
7879 (__arm_vcmpneq_n_s8): Likewise.
7880 (__arm_vcmpltq_s8): Likewise.
7881 (__arm_vcmpltq_n_s8): Likewise.
7882 (__arm_vcmpleq_s8): Likewise.
7883 (__arm_vcmpleq_n_s8): Likewise.
7884 (__arm_vcmpgtq_s8): Likewise.
7885 (__arm_vcmpgtq_n_s8): Likewise.
7886 (__arm_vcmpgeq_s8): Likewise.
7887 (__arm_vcmpgeq_n_s8): Likewise.
7888 (__arm_vcmpeqq_s8): Likewise.
7889 (__arm_vcmpeqq_n_s8): Likewise.
7890 (__arm_vqshluq_n_s8): Likewise.
7891 (__arm_vaddvq_p_s8): Likewise.
7892 (__arm_vsubq_s8): Likewise.
7893 (__arm_vsubq_n_s8): Likewise.
7894 (__arm_vshlq_r_s8): Likewise.
7895 (__arm_vrshlq_s8): Likewise.
7896 (__arm_vrshlq_n_s8): Likewise.
7897 (__arm_vrmulhq_s8): Likewise.
7898 (__arm_vrhaddq_s8): Likewise.
7899 (__arm_vqsubq_s8): Likewise.
7900 (__arm_vqsubq_n_s8): Likewise.
7901 (__arm_vqshlq_s8): Likewise.
7902 (__arm_vqshlq_r_s8): Likewise.
7903 (__arm_vqrshlq_s8): Likewise.
7904 (__arm_vqrshlq_n_s8): Likewise.
7905 (__arm_vqrdmulhq_s8): Likewise.
7906 (__arm_vqrdmulhq_n_s8): Likewise.
7907 (__arm_vqdmulhq_s8): Likewise.
7908 (__arm_vqdmulhq_n_s8): Likewise.
7909 (__arm_vqaddq_s8): Likewise.
7910 (__arm_vqaddq_n_s8): Likewise.
7911 (__arm_vorrq_s8): Likewise.
7912 (__arm_vornq_s8): Likewise.
7913 (__arm_vmulq_s8): Likewise.
7914 (__arm_vmulq_n_s8): Likewise.
7915 (__arm_vmulltq_int_s8): Likewise.
7916 (__arm_vmullbq_int_s8): Likewise.
7917 (__arm_vmulhq_s8): Likewise.
7918 (__arm_vmlsdavxq_s8): Likewise.
7919 (__arm_vmlsdavq_s8): Likewise.
7920 (__arm_vmladavxq_s8): Likewise.
7921 (__arm_vmladavq_s8): Likewise.
7922 (__arm_vminvq_s8): Likewise.
7923 (__arm_vminq_s8): Likewise.
7924 (__arm_vmaxvq_s8): Likewise.
7925 (__arm_vmaxq_s8): Likewise.
7926 (__arm_vhsubq_s8): Likewise.
7927 (__arm_vhsubq_n_s8): Likewise.
7928 (__arm_vhcaddq_rot90_s8): Likewise.
7929 (__arm_vhcaddq_rot270_s8): Likewise.
7930 (__arm_vhaddq_s8): Likewise.
7931 (__arm_vhaddq_n_s8): Likewise.
7932 (__arm_veorq_s8): Likewise.
7933 (__arm_vcaddq_rot90_s8): Likewise.
7934 (__arm_vcaddq_rot270_s8): Likewise.
7935 (__arm_vbrsrq_n_s8): Likewise.
7936 (__arm_vbicq_s8): Likewise.
7937 (__arm_vandq_s8): Likewise.
7938 (__arm_vaddvaq_s8): Likewise.
7939 (__arm_vaddq_n_s8): Likewise.
7940 (__arm_vabdq_s8): Likewise.
7941 (__arm_vshlq_n_s8): Likewise.
7942 (__arm_vrshrq_n_s8): Likewise.
7943 (__arm_vqshlq_n_s8): Likewise.
7944 (__arm_vsubq_u16): Likewise.
7945 (__arm_vsubq_n_u16): Likewise.
7946 (__arm_vrmulhq_u16): Likewise.
7947 (__arm_vrhaddq_u16): Likewise.
7948 (__arm_vqsubq_u16): Likewise.
7949 (__arm_vqsubq_n_u16): Likewise.
7950 (__arm_vqaddq_u16): Likewise.
7951 (__arm_vqaddq_n_u16): Likewise.
7952 (__arm_vorrq_u16): Likewise.
7953 (__arm_vornq_u16): Likewise.
7954 (__arm_vmulq_u16): Likewise.
7955 (__arm_vmulq_n_u16): Likewise.
7956 (__arm_vmulltq_int_u16): Likewise.
7957 (__arm_vmullbq_int_u16): Likewise.
7958 (__arm_vmulhq_u16): Likewise.
7959 (__arm_vmladavq_u16): Likewise.
7960 (__arm_vminvq_u16): Likewise.
7961 (__arm_vminq_u16): Likewise.
7962 (__arm_vmaxvq_u16): Likewise.
7963 (__arm_vmaxq_u16): Likewise.
7964 (__arm_vhsubq_u16): Likewise.
7965 (__arm_vhsubq_n_u16): Likewise.
7966 (__arm_vhaddq_u16): Likewise.
7967 (__arm_vhaddq_n_u16): Likewise.
7968 (__arm_veorq_u16): Likewise.
7969 (__arm_vcmpneq_n_u16): Likewise.
7970 (__arm_vcmphiq_u16): Likewise.
7971 (__arm_vcmphiq_n_u16): Likewise.
7972 (__arm_vcmpeqq_u16): Likewise.
7973 (__arm_vcmpeqq_n_u16): Likewise.
7974 (__arm_vcmpcsq_u16): Likewise.
7975 (__arm_vcmpcsq_n_u16): Likewise.
7976 (__arm_vcaddq_rot90_u16): Likewise.
7977 (__arm_vcaddq_rot270_u16): Likewise.
7978 (__arm_vbicq_u16): Likewise.
7979 (__arm_vandq_u16): Likewise.
7980 (__arm_vaddvq_p_u16): Likewise.
7981 (__arm_vaddvaq_u16): Likewise.
7982 (__arm_vaddq_n_u16): Likewise.
7983 (__arm_vabdq_u16): Likewise.
7984 (__arm_vshlq_r_u16): Likewise.
7985 (__arm_vrshlq_u16): Likewise.
7986 (__arm_vrshlq_n_u16): Likewise.
7987 (__arm_vqshlq_u16): Likewise.
7988 (__arm_vqshlq_r_u16): Likewise.
7989 (__arm_vqrshlq_u16): Likewise.
7990 (__arm_vqrshlq_n_u16): Likewise.
7991 (__arm_vminavq_s16): Likewise.
7992 (__arm_vminaq_s16): Likewise.
7993 (__arm_vmaxavq_s16): Likewise.
7994 (__arm_vmaxaq_s16): Likewise.
7995 (__arm_vbrsrq_n_u16): Likewise.
7996 (__arm_vshlq_n_u16): Likewise.
7997 (__arm_vrshrq_n_u16): Likewise.
7998 (__arm_vqshlq_n_u16): Likewise.
7999 (__arm_vcmpneq_n_s16): Likewise.
8000 (__arm_vcmpltq_s16): Likewise.
8001 (__arm_vcmpltq_n_s16): Likewise.
8002 (__arm_vcmpleq_s16): Likewise.
8003 (__arm_vcmpleq_n_s16): Likewise.
8004 (__arm_vcmpgtq_s16): Likewise.
8005 (__arm_vcmpgtq_n_s16): Likewise.
8006 (__arm_vcmpgeq_s16): Likewise.
8007 (__arm_vcmpgeq_n_s16): Likewise.
8008 (__arm_vcmpeqq_s16): Likewise.
8009 (__arm_vcmpeqq_n_s16): Likewise.
8010 (__arm_vqshluq_n_s16): Likewise.
8011 (__arm_vaddvq_p_s16): Likewise.
8012 (__arm_vsubq_s16): Likewise.
8013 (__arm_vsubq_n_s16): Likewise.
8014 (__arm_vshlq_r_s16): Likewise.
8015 (__arm_vrshlq_s16): Likewise.
8016 (__arm_vrshlq_n_s16): Likewise.
8017 (__arm_vrmulhq_s16): Likewise.
8018 (__arm_vrhaddq_s16): Likewise.
8019 (__arm_vqsubq_s16): Likewise.
8020 (__arm_vqsubq_n_s16): Likewise.
8021 (__arm_vqshlq_s16): Likewise.
8022 (__arm_vqshlq_r_s16): Likewise.
8023 (__arm_vqrshlq_s16): Likewise.
8024 (__arm_vqrshlq_n_s16): Likewise.
8025 (__arm_vqrdmulhq_s16): Likewise.
8026 (__arm_vqrdmulhq_n_s16): Likewise.
8027 (__arm_vqdmulhq_s16): Likewise.
8028 (__arm_vqdmulhq_n_s16): Likewise.
8029 (__arm_vqaddq_s16): Likewise.
8030 (__arm_vqaddq_n_s16): Likewise.
8031 (__arm_vorrq_s16): Likewise.
8032 (__arm_vornq_s16): Likewise.
8033 (__arm_vmulq_s16): Likewise.
8034 (__arm_vmulq_n_s16): Likewise.
8035 (__arm_vmulltq_int_s16): Likewise.
8036 (__arm_vmullbq_int_s16): Likewise.
8037 (__arm_vmulhq_s16): Likewise.
8038 (__arm_vmlsdavxq_s16): Likewise.
8039 (__arm_vmlsdavq_s16): Likewise.
8040 (__arm_vmladavxq_s16): Likewise.
8041 (__arm_vmladavq_s16): Likewise.
8042 (__arm_vminvq_s16): Likewise.
8043 (__arm_vminq_s16): Likewise.
8044 (__arm_vmaxvq_s16): Likewise.
8045 (__arm_vmaxq_s16): Likewise.
8046 (__arm_vhsubq_s16): Likewise.
8047 (__arm_vhsubq_n_s16): Likewise.
8048 (__arm_vhcaddq_rot90_s16): Likewise.
8049 (__arm_vhcaddq_rot270_s16): Likewise.
8050 (__arm_vhaddq_s16): Likewise.
8051 (__arm_vhaddq_n_s16): Likewise.
8052 (__arm_veorq_s16): Likewise.
8053 (__arm_vcaddq_rot90_s16): Likewise.
8054 (__arm_vcaddq_rot270_s16): Likewise.
8055 (__arm_vbrsrq_n_s16): Likewise.
8056 (__arm_vbicq_s16): Likewise.
8057 (__arm_vandq_s16): Likewise.
8058 (__arm_vaddvaq_s16): Likewise.
8059 (__arm_vaddq_n_s16): Likewise.
8060 (__arm_vabdq_s16): Likewise.
8061 (__arm_vshlq_n_s16): Likewise.
8062 (__arm_vrshrq_n_s16): Likewise.
8063 (__arm_vqshlq_n_s16): Likewise.
8064 (__arm_vsubq_u32): Likewise.
8065 (__arm_vsubq_n_u32): Likewise.
8066 (__arm_vrmulhq_u32): Likewise.
8067 (__arm_vrhaddq_u32): Likewise.
8068 (__arm_vqsubq_u32): Likewise.
8069 (__arm_vqsubq_n_u32): Likewise.
8070 (__arm_vqaddq_u32): Likewise.
8071 (__arm_vqaddq_n_u32): Likewise.
8072 (__arm_vorrq_u32): Likewise.
8073 (__arm_vornq_u32): Likewise.
8074 (__arm_vmulq_u32): Likewise.
8075 (__arm_vmulq_n_u32): Likewise.
8076 (__arm_vmulltq_int_u32): Likewise.
8077 (__arm_vmullbq_int_u32): Likewise.
8078 (__arm_vmulhq_u32): Likewise.
8079 (__arm_vmladavq_u32): Likewise.
8080 (__arm_vminvq_u32): Likewise.
8081 (__arm_vminq_u32): Likewise.
8082 (__arm_vmaxvq_u32): Likewise.
8083 (__arm_vmaxq_u32): Likewise.
8084 (__arm_vhsubq_u32): Likewise.
8085 (__arm_vhsubq_n_u32): Likewise.
8086 (__arm_vhaddq_u32): Likewise.
8087 (__arm_vhaddq_n_u32): Likewise.
8088 (__arm_veorq_u32): Likewise.
8089 (__arm_vcmpneq_n_u32): Likewise.
8090 (__arm_vcmphiq_u32): Likewise.
8091 (__arm_vcmphiq_n_u32): Likewise.
8092 (__arm_vcmpeqq_u32): Likewise.
8093 (__arm_vcmpeqq_n_u32): Likewise.
8094 (__arm_vcmpcsq_u32): Likewise.
8095 (__arm_vcmpcsq_n_u32): Likewise.
8096 (__arm_vcaddq_rot90_u32): Likewise.
8097 (__arm_vcaddq_rot270_u32): Likewise.
8098 (__arm_vbicq_u32): Likewise.
8099 (__arm_vandq_u32): Likewise.
8100 (__arm_vaddvq_p_u32): Likewise.
8101 (__arm_vaddvaq_u32): Likewise.
8102 (__arm_vaddq_n_u32): Likewise.
8103 (__arm_vabdq_u32): Likewise.
8104 (__arm_vshlq_r_u32): Likewise.
8105 (__arm_vrshlq_u32): Likewise.
8106 (__arm_vrshlq_n_u32): Likewise.
8107 (__arm_vqshlq_u32): Likewise.
8108 (__arm_vqshlq_r_u32): Likewise.
8109 (__arm_vqrshlq_u32): Likewise.
8110 (__arm_vqrshlq_n_u32): Likewise.
8111 (__arm_vminavq_s32): Likewise.
8112 (__arm_vminaq_s32): Likewise.
8113 (__arm_vmaxavq_s32): Likewise.
8114 (__arm_vmaxaq_s32): Likewise.
8115 (__arm_vbrsrq_n_u32): Likewise.
8116 (__arm_vshlq_n_u32): Likewise.
8117 (__arm_vrshrq_n_u32): Likewise.
8118 (__arm_vqshlq_n_u32): Likewise.
8119 (__arm_vcmpneq_n_s32): Likewise.
8120 (__arm_vcmpltq_s32): Likewise.
8121 (__arm_vcmpltq_n_s32): Likewise.
8122 (__arm_vcmpleq_s32): Likewise.
8123 (__arm_vcmpleq_n_s32): Likewise.
8124 (__arm_vcmpgtq_s32): Likewise.
8125 (__arm_vcmpgtq_n_s32): Likewise.
8126 (__arm_vcmpgeq_s32): Likewise.
8127 (__arm_vcmpgeq_n_s32): Likewise.
8128 (__arm_vcmpeqq_s32): Likewise.
8129 (__arm_vcmpeqq_n_s32): Likewise.
8130 (__arm_vqshluq_n_s32): Likewise.
8131 (__arm_vaddvq_p_s32): Likewise.
8132 (__arm_vsubq_s32): Likewise.
8133 (__arm_vsubq_n_s32): Likewise.
8134 (__arm_vshlq_r_s32): Likewise.
8135 (__arm_vrshlq_s32): Likewise.
8136 (__arm_vrshlq_n_s32): Likewise.
8137 (__arm_vrmulhq_s32): Likewise.
8138 (__arm_vrhaddq_s32): Likewise.
8139 (__arm_vqsubq_s32): Likewise.
8140 (__arm_vqsubq_n_s32): Likewise.
8141 (__arm_vqshlq_s32): Likewise.
8142 (__arm_vqshlq_r_s32): Likewise.
8143 (__arm_vqrshlq_s32): Likewise.
8144 (__arm_vqrshlq_n_s32): Likewise.
8145 (__arm_vqrdmulhq_s32): Likewise.
8146 (__arm_vqrdmulhq_n_s32): Likewise.
8147 (__arm_vqdmulhq_s32): Likewise.
8148 (__arm_vqdmulhq_n_s32): Likewise.
8149 (__arm_vqaddq_s32): Likewise.
8150 (__arm_vqaddq_n_s32): Likewise.
8151 (__arm_vorrq_s32): Likewise.
8152 (__arm_vornq_s32): Likewise.
8153 (__arm_vmulq_s32): Likewise.
8154 (__arm_vmulq_n_s32): Likewise.
8155 (__arm_vmulltq_int_s32): Likewise.
8156 (__arm_vmullbq_int_s32): Likewise.
8157 (__arm_vmulhq_s32): Likewise.
8158 (__arm_vmlsdavxq_s32): Likewise.
8159 (__arm_vmlsdavq_s32): Likewise.
8160 (__arm_vmladavxq_s32): Likewise.
8161 (__arm_vmladavq_s32): Likewise.
8162 (__arm_vminvq_s32): Likewise.
8163 (__arm_vminq_s32): Likewise.
8164 (__arm_vmaxvq_s32): Likewise.
8165 (__arm_vmaxq_s32): Likewise.
8166 (__arm_vhsubq_s32): Likewise.
8167 (__arm_vhsubq_n_s32): Likewise.
8168 (__arm_vhcaddq_rot90_s32): Likewise.
8169 (__arm_vhcaddq_rot270_s32): Likewise.
8170 (__arm_vhaddq_s32): Likewise.
8171 (__arm_vhaddq_n_s32): Likewise.
8172 (__arm_veorq_s32): Likewise.
8173 (__arm_vcaddq_rot90_s32): Likewise.
8174 (__arm_vcaddq_rot270_s32): Likewise.
8175 (__arm_vbrsrq_n_s32): Likewise.
8176 (__arm_vbicq_s32): Likewise.
8177 (__arm_vandq_s32): Likewise.
8178 (__arm_vaddvaq_s32): Likewise.
8179 (__arm_vaddq_n_s32): Likewise.
8180 (__arm_vabdq_s32): Likewise.
8181 (__arm_vshlq_n_s32): Likewise.
8182 (__arm_vrshrq_n_s32): Likewise.
8183 (__arm_vqshlq_n_s32): Likewise.
8184 (vsubq): Define polymorphic variant.
8185 (vsubq_n): Likewise.
8186 (vshlq_r): Likewise.
8187 (vrshlq_n): Likewise.
8188 (vrshlq): Likewise.
8189 (vrmulhq): Likewise.
8190 (vrhaddq): Likewise.
8191 (vqsubq_n): Likewise.
8192 (vqsubq): Likewise.
8193 (vqshlq): Likewise.
8194 (vqshlq_r): Likewise.
8195 (vqshluq): Likewise.
8196 (vrshrq_n): Likewise.
8197 (vshlq_n): Likewise.
8198 (vqshluq_n): Likewise.
8199 (vqshlq_n): Likewise.
8200 (vqrshlq_n): Likewise.
8201 (vqrshlq): Likewise.
8202 (vqrdmulhq_n): Likewise.
8203 (vqrdmulhq): Likewise.
8204 (vqdmulhq_n): Likewise.
8205 (vqdmulhq): Likewise.
8206 (vqaddq_n): Likewise.
8207 (vqaddq): Likewise.
8208 (vorrq_n): Likewise.
8209 (vorrq): Likewise.
8210 (vornq): Likewise.
8211 (vmulq_n): Likewise.
8212 (vmulq): Likewise.
8213 (vmulltq_int): Likewise.
8214 (vmullbq_int): Likewise.
8215 (vmulhq): Likewise.
8216 (vminq): Likewise.
8217 (vminaq): Likewise.
8218 (vmaxq): Likewise.
8219 (vmaxaq): Likewise.
8220 (vhsubq_n): Likewise.
8221 (vhsubq): Likewise.
8222 (vhcaddq_rot90): Likewise.
8223 (vhcaddq_rot270): Likewise.
8224 (vhaddq_n): Likewise.
8225 (vhaddq): Likewise.
8226 (veorq): Likewise.
8227 (vcaddq_rot90): Likewise.
8228 (vcaddq_rot270): Likewise.
8229 (vbrsrq_n): Likewise.
8230 (vbicq_n): Likewise.
8231 (vbicq): Likewise.
8232 (vaddq): Likewise.
8233 (vaddq_n): Likewise.
8234 (vandq): Likewise.
8235 (vabdq): Likewise.
8236 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
8237 (BINOP_NONE_NONE_NONE): Likewise.
8238 (BINOP_NONE_NONE_UNONE): Likewise.
8239 (BINOP_UNONE_NONE_IMM): Likewise.
8240 (BINOP_UNONE_NONE_NONE): Likewise.
8241 (BINOP_UNONE_UNONE_IMM): Likewise.
8242 (BINOP_UNONE_UNONE_NONE): Likewise.
8243 (BINOP_UNONE_UNONE_UNONE): Likewise.
8244 * config/arm/constraints.md (Ra): Define constraint to check constant is
8245 in the range of 0 to 7.
8246 (Rg): Define constriant to check the constant is one among 1, 2, 4
8247 and 8.
8248 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
8249 (mve_vaddq_n_<supf>): Likewise.
8250 (mve_vaddvaq_<supf>): Likewise.
8251 (mve_vaddvq_p_<supf>): Likewise.
8252 (mve_vandq_<supf>): Likewise.
8253 (mve_vbicq_<supf>): Likewise.
8254 (mve_vbrsrq_n_<supf>): Likewise.
8255 (mve_vcaddq_rot270_<supf>): Likewise.
8256 (mve_vcaddq_rot90_<supf>): Likewise.
8257 (mve_vcmpcsq_n_u): Likewise.
8258 (mve_vcmpcsq_u): Likewise.
8259 (mve_vcmpeqq_n_<supf>): Likewise.
8260 (mve_vcmpeqq_<supf>): Likewise.
8261 (mve_vcmpgeq_n_s): Likewise.
8262 (mve_vcmpgeq_s): Likewise.
8263 (mve_vcmpgtq_n_s): Likewise.
8264 (mve_vcmpgtq_s): Likewise.
8265 (mve_vcmphiq_n_u): Likewise.
8266 (mve_vcmphiq_u): Likewise.
8267 (mve_vcmpleq_n_s): Likewise.
8268 (mve_vcmpleq_s): Likewise.
8269 (mve_vcmpltq_n_s): Likewise.
8270 (mve_vcmpltq_s): Likewise.
8271 (mve_vcmpneq_n_<supf>): Likewise.
8272 (mve_vddupq_n_u): Likewise.
8273 (mve_veorq_<supf>): Likewise.
8274 (mve_vhaddq_n_<supf>): Likewise.
8275 (mve_vhaddq_<supf>): Likewise.
8276 (mve_vhcaddq_rot270_s): Likewise.
8277 (mve_vhcaddq_rot90_s): Likewise.
8278 (mve_vhsubq_n_<supf>): Likewise.
8279 (mve_vhsubq_<supf>): Likewise.
8280 (mve_vidupq_n_u): Likewise.
8281 (mve_vmaxaq_s): Likewise.
8282 (mve_vmaxavq_s): Likewise.
8283 (mve_vmaxq_<supf>): Likewise.
8284 (mve_vmaxvq_<supf>): Likewise.
8285 (mve_vminaq_s): Likewise.
8286 (mve_vminavq_s): Likewise.
8287 (mve_vminq_<supf>): Likewise.
8288 (mve_vminvq_<supf>): Likewise.
8289 (mve_vmladavq_<supf>): Likewise.
8290 (mve_vmladavxq_s): Likewise.
8291 (mve_vmlsdavq_s): Likewise.
8292 (mve_vmlsdavxq_s): Likewise.
8293 (mve_vmulhq_<supf>): Likewise.
8294 (mve_vmullbq_int_<supf>): Likewise.
8295 (mve_vmulltq_int_<supf>): Likewise.
8296 (mve_vmulq_n_<supf>): Likewise.
8297 (mve_vmulq_<supf>): Likewise.
8298 (mve_vornq_<supf>): Likewise.
8299 (mve_vorrq_<supf>): Likewise.
8300 (mve_vqaddq_n_<supf>): Likewise.
8301 (mve_vqaddq_<supf>): Likewise.
8302 (mve_vqdmulhq_n_s): Likewise.
8303 (mve_vqdmulhq_s): Likewise.
8304 (mve_vqrdmulhq_n_s): Likewise.
8305 (mve_vqrdmulhq_s): Likewise.
8306 (mve_vqrshlq_n_<supf>): Likewise.
8307 (mve_vqrshlq_<supf>): Likewise.
8308 (mve_vqshlq_n_<supf>): Likewise.
8309 (mve_vqshlq_r_<supf>): Likewise.
8310 (mve_vqshlq_<supf>): Likewise.
8311 (mve_vqshluq_n_s): Likewise.
8312 (mve_vqsubq_n_<supf>): Likewise.
8313 (mve_vqsubq_<supf>): Likewise.
8314 (mve_vrhaddq_<supf>): Likewise.
8315 (mve_vrmulhq_<supf>): Likewise.
8316 (mve_vrshlq_n_<supf>): Likewise.
8317 (mve_vrshlq_<supf>): Likewise.
8318 (mve_vrshrq_n_<supf>): Likewise.
8319 (mve_vshlq_n_<supf>): Likewise.
8320 (mve_vshlq_r_<supf>): Likewise.
8321 (mve_vsubq_n_<supf>): Likewise.
8322 (mve_vsubq_<supf>): Likewise.
8323 * config/arm/predicates.md (mve_imm_7): Define predicate to check
8324 the matching constraint Ra.
8325 (mve_imm_selective_upto_8): Define predicate to check the matching
8326 constraint Rg.
8328 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8329 Mihail Ionescu <mihail.ionescu@arm.com>
8330 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8332 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
8333 qualifier for binary operands.
8334 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
8335 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
8336 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
8337 (vaddlvq_p_u32): Likewise.
8338 (vcmpneq_s8): Likewise.
8339 (vcmpneq_s16): Likewise.
8340 (vcmpneq_s32): Likewise.
8341 (vcmpneq_u8): Likewise.
8342 (vcmpneq_u16): Likewise.
8343 (vcmpneq_u32): Likewise.
8344 (vshlq_s8): Likewise.
8345 (vshlq_s16): Likewise.
8346 (vshlq_s32): Likewise.
8347 (vshlq_u8): Likewise.
8348 (vshlq_u16): Likewise.
8349 (vshlq_u32): Likewise.
8350 (__arm_vaddlvq_p_s32): Define intrinsic.
8351 (__arm_vaddlvq_p_u32): Likewise.
8352 (__arm_vcmpneq_s8): Likewise.
8353 (__arm_vcmpneq_s16): Likewise.
8354 (__arm_vcmpneq_s32): Likewise.
8355 (__arm_vcmpneq_u8): Likewise.
8356 (__arm_vcmpneq_u16): Likewise.
8357 (__arm_vcmpneq_u32): Likewise.
8358 (__arm_vshlq_s8): Likewise.
8359 (__arm_vshlq_s16): Likewise.
8360 (__arm_vshlq_s32): Likewise.
8361 (__arm_vshlq_u8): Likewise.
8362 (__arm_vshlq_u16): Likewise.
8363 (__arm_vshlq_u32): Likewise.
8364 (vaddlvq_p): Define polymorphic variant.
8365 (vcmpneq): Likewise.
8366 (vshlq): Likewise.
8367 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
8368 Use it.
8369 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
8370 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
8371 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
8372 (mve_vcmpneq_<supf><mode>): Likewise.
8373 (mve_vshlq_<supf><mode>): Likewise.
8375 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8376 Mihail Ionescu <mihail.ionescu@arm.com>
8377 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8379 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
8380 qualifier for binary operands.
8381 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8382 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
8383 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
8384 (vcvtq_n_s32_f32): Likewise.
8385 (vcvtq_n_u16_f16): Likewise.
8386 (vcvtq_n_u32_f32): Likewise.
8387 (vcreateq_u8): Likewise.
8388 (vcreateq_u16): Likewise.
8389 (vcreateq_u32): Likewise.
8390 (vcreateq_u64): Likewise.
8391 (vcreateq_s8): Likewise.
8392 (vcreateq_s16): Likewise.
8393 (vcreateq_s32): Likewise.
8394 (vcreateq_s64): Likewise.
8395 (vshrq_n_s8): Likewise.
8396 (vshrq_n_s16): Likewise.
8397 (vshrq_n_s32): Likewise.
8398 (vshrq_n_u8): Likewise.
8399 (vshrq_n_u16): Likewise.
8400 (vshrq_n_u32): Likewise.
8401 (__arm_vcreateq_u8): Define intrinsic.
8402 (__arm_vcreateq_u16): Likewise.
8403 (__arm_vcreateq_u32): Likewise.
8404 (__arm_vcreateq_u64): Likewise.
8405 (__arm_vcreateq_s8): Likewise.
8406 (__arm_vcreateq_s16): Likewise.
8407 (__arm_vcreateq_s32): Likewise.
8408 (__arm_vcreateq_s64): Likewise.
8409 (__arm_vshrq_n_s8): Likewise.
8410 (__arm_vshrq_n_s16): Likewise.
8411 (__arm_vshrq_n_s32): Likewise.
8412 (__arm_vshrq_n_u8): Likewise.
8413 (__arm_vshrq_n_u16): Likewise.
8414 (__arm_vshrq_n_u32): Likewise.
8415 (__arm_vcvtq_n_s16_f16): Likewise.
8416 (__arm_vcvtq_n_s32_f32): Likewise.
8417 (__arm_vcvtq_n_u16_f16): Likewise.
8418 (__arm_vcvtq_n_u32_f32): Likewise.
8419 (vshrq_n): Define polymorphic variant.
8420 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
8421 Use it.
8422 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8423 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
8424 * config/arm/constraints.md (Rb): Define constraint to check constant is
8425 in the range of 1 to 8.
8426 (Rf): Define constraint to check constant is in the range of 1 to 32.
8427 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
8428 (mve_vshrq_n_<supf><mode>): Likewise.
8429 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
8430 * config/arm/predicates.md (mve_imm_8): Define predicate to check
8431 the matching constraint Rb.
8432 (mve_imm_32): Define predicate to check the matching constraint Rf.
8434 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8435 Mihail Ionescu <mihail.ionescu@arm.com>
8436 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8438 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
8439 qualifier for binary operands.
8440 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
8441 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
8442 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
8443 * config/arm/arm_mve.h (vsubq_n_f16): Define macro.
8444 (vsubq_n_f32): Likewise.
8445 (vbrsrq_n_f16): Likewise.
8446 (vbrsrq_n_f32): Likewise.
8447 (vcvtq_n_f16_s16): Likewise.
8448 (vcvtq_n_f32_s32): Likewise.
8449 (vcvtq_n_f16_u16): Likewise.
8450 (vcvtq_n_f32_u32): Likewise.
8451 (vcreateq_f16): Likewise.
8452 (vcreateq_f32): Likewise.
8453 (__arm_vsubq_n_f16): Define intrinsic.
8454 (__arm_vsubq_n_f32): Likewise.
8455 (__arm_vbrsrq_n_f16): Likewise.
8456 (__arm_vbrsrq_n_f32): Likewise.
8457 (__arm_vcvtq_n_f16_s16): Likewise.
8458 (__arm_vcvtq_n_f32_s32): Likewise.
8459 (__arm_vcvtq_n_f16_u16): Likewise.
8460 (__arm_vcvtq_n_f32_u32): Likewise.
8461 (__arm_vcreateq_f16): Likewise.
8462 (__arm_vcreateq_f32): Likewise.
8463 (vsubq): Define polymorphic variant.
8464 (vbrsrq): Likewise.
8465 (vcvtq_n): Likewise.
8466 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
8467 it.
8468 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
8469 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
8470 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
8471 * config/arm/constraints.md (Rd): Define constraint to check constant is
8472 in the range of 1 to 16.
8473 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
8474 mve_vbrsrq_n_f<mode>: Likewise.
8475 mve_vcvtq_n_to_f_<supf><mode>: Likewise.
8476 mve_vcreateq_f<mode>: Likewise.
8477 * config/arm/predicates.md (mve_imm_16): Define predicate to check
8478 the matching constraint Rd.
8480 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8481 Mihail Ionescu <mihail.ionescu@arm.com>
8482 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8484 * config/arm/arm-builtins.c (hi_UP): Define mode.
8485 * config/arm/arm.h (IS_VPR_REGNUM): Move.
8486 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
8487 (APSRQ_REGNUM): Modify.
8488 (APSRGE_REGNUM): Modify.
8489 * config/arm/arm_mve.h (vctp16q): Define macro.
8490 (vctp32q): Likewise.
8491 (vctp64q): Likewise.
8492 (vctp8q): Likewise.
8493 (vpnot): Likewise.
8494 (__arm_vctp16q): Define intrinsic.
8495 (__arm_vctp32q): Likewise.
8496 (__arm_vctp64q): Likewise.
8497 (__arm_vctp8q): Likewise.
8498 (__arm_vpnot): Likewise.
8499 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
8500 qualifier.
8501 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
8502 (mve_vpnothi): Likewise.
8504 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8505 Mihail Ionescu <mihail.ionescu@arm.com>
8506 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8508 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
8509 * config/arm/arm_mve.h (vdupq_n_s8): Define macro.
8510 (vdupq_n_s16): Likewise.
8511 (vdupq_n_s32): Likewise.
8512 (vabsq_s8): Likewise.
8513 (vabsq_s16): Likewise.
8514 (vabsq_s32): Likewise.
8515 (vclsq_s8): Likewise.
8516 (vclsq_s16): Likewise.
8517 (vclsq_s32): Likewise.
8518 (vclzq_s8): Likewise.
8519 (vclzq_s16): Likewise.
8520 (vclzq_s32): Likewise.
8521 (vnegq_s8): Likewise.
8522 (vnegq_s16): Likewise.
8523 (vnegq_s32): Likewise.
8524 (vaddlvq_s32): Likewise.
8525 (vaddvq_s8): Likewise.
8526 (vaddvq_s16): Likewise.
8527 (vaddvq_s32): Likewise.
8528 (vmovlbq_s8): Likewise.
8529 (vmovlbq_s16): Likewise.
8530 (vmovltq_s8): Likewise.
8531 (vmovltq_s16): Likewise.
8532 (vmvnq_s8): Likewise.
8533 (vmvnq_s16): Likewise.
8534 (vmvnq_s32): Likewise.
8535 (vrev16q_s8): Likewise.
8536 (vrev32q_s8): Likewise.
8537 (vrev32q_s16): Likewise.
8538 (vqabsq_s8): Likewise.
8539 (vqabsq_s16): Likewise.
8540 (vqabsq_s32): Likewise.
8541 (vqnegq_s8): Likewise.
8542 (vqnegq_s16): Likewise.
8543 (vqnegq_s32): Likewise.
8544 (vcvtaq_s16_f16): Likewise.
8545 (vcvtaq_s32_f32): Likewise.
8546 (vcvtnq_s16_f16): Likewise.
8547 (vcvtnq_s32_f32): Likewise.
8548 (vcvtpq_s16_f16): Likewise.
8549 (vcvtpq_s32_f32): Likewise.
8550 (vcvtmq_s16_f16): Likewise.
8551 (vcvtmq_s32_f32): Likewise.
8552 (vmvnq_u8): Likewise.
8553 (vmvnq_u16): Likewise.
8554 (vmvnq_u32): Likewise.
8555 (vdupq_n_u8): Likewise.
8556 (vdupq_n_u16): Likewise.
8557 (vdupq_n_u32): Likewise.
8558 (vclzq_u8): Likewise.
8559 (vclzq_u16): Likewise.
8560 (vclzq_u32): Likewise.
8561 (vaddvq_u8): Likewise.
8562 (vaddvq_u16): Likewise.
8563 (vaddvq_u32): Likewise.
8564 (vrev32q_u8): Likewise.
8565 (vrev32q_u16): Likewise.
8566 (vmovltq_u8): Likewise.
8567 (vmovltq_u16): Likewise.
8568 (vmovlbq_u8): Likewise.
8569 (vmovlbq_u16): Likewise.
8570 (vrev16q_u8): Likewise.
8571 (vaddlvq_u32): Likewise.
8572 (vcvtpq_u16_f16): Likewise.
8573 (vcvtpq_u32_f32): Likewise.
8574 (vcvtnq_u16_f16): Likewise.
8575 (vcvtmq_u16_f16): Likewise.
8576 (vcvtmq_u32_f32): Likewise.
8577 (vcvtaq_u16_f16): Likewise.
8578 (vcvtaq_u32_f32): Likewise.
8579 (__arm_vdupq_n_s8): Define intrinsic.
8580 (__arm_vdupq_n_s16): Likewise.
8581 (__arm_vdupq_n_s32): Likewise.
8582 (__arm_vabsq_s8): Likewise.
8583 (__arm_vabsq_s16): Likewise.
8584 (__arm_vabsq_s32): Likewise.
8585 (__arm_vclsq_s8): Likewise.
8586 (__arm_vclsq_s16): Likewise.
8587 (__arm_vclsq_s32): Likewise.
8588 (__arm_vclzq_s8): Likewise.
8589 (__arm_vclzq_s16): Likewise.
8590 (__arm_vclzq_s32): Likewise.
8591 (__arm_vnegq_s8): Likewise.
8592 (__arm_vnegq_s16): Likewise.
8593 (__arm_vnegq_s32): Likewise.
8594 (__arm_vaddlvq_s32): Likewise.
8595 (__arm_vaddvq_s8): Likewise.
8596 (__arm_vaddvq_s16): Likewise.
8597 (__arm_vaddvq_s32): Likewise.
8598 (__arm_vmovlbq_s8): Likewise.
8599 (__arm_vmovlbq_s16): Likewise.
8600 (__arm_vmovltq_s8): Likewise.
8601 (__arm_vmovltq_s16): Likewise.
8602 (__arm_vmvnq_s8): Likewise.
8603 (__arm_vmvnq_s16): Likewise.
8604 (__arm_vmvnq_s32): Likewise.
8605 (__arm_vrev16q_s8): Likewise.
8606 (__arm_vrev32q_s8): Likewise.
8607 (__arm_vrev32q_s16): Likewise.
8608 (__arm_vqabsq_s8): Likewise.
8609 (__arm_vqabsq_s16): Likewise.
8610 (__arm_vqabsq_s32): Likewise.
8611 (__arm_vqnegq_s8): Likewise.
8612 (__arm_vqnegq_s16): Likewise.
8613 (__arm_vqnegq_s32): Likewise.
8614 (__arm_vmvnq_u8): Likewise.
8615 (__arm_vmvnq_u16): Likewise.
8616 (__arm_vmvnq_u32): Likewise.
8617 (__arm_vdupq_n_u8): Likewise.
8618 (__arm_vdupq_n_u16): Likewise.
8619 (__arm_vdupq_n_u32): Likewise.
8620 (__arm_vclzq_u8): Likewise.
8621 (__arm_vclzq_u16): Likewise.
8622 (__arm_vclzq_u32): Likewise.
8623 (__arm_vaddvq_u8): Likewise.
8624 (__arm_vaddvq_u16): Likewise.
8625 (__arm_vaddvq_u32): Likewise.
8626 (__arm_vrev32q_u8): Likewise.
8627 (__arm_vrev32q_u16): Likewise.
8628 (__arm_vmovltq_u8): Likewise.
8629 (__arm_vmovltq_u16): Likewise.
8630 (__arm_vmovlbq_u8): Likewise.
8631 (__arm_vmovlbq_u16): Likewise.
8632 (__arm_vrev16q_u8): Likewise.
8633 (__arm_vaddlvq_u32): Likewise.
8634 (__arm_vcvtpq_u16_f16): Likewise.
8635 (__arm_vcvtpq_u32_f32): Likewise.
8636 (__arm_vcvtnq_u16_f16): Likewise.
8637 (__arm_vcvtmq_u16_f16): Likewise.
8638 (__arm_vcvtmq_u32_f32): Likewise.
8639 (__arm_vcvtaq_u16_f16): Likewise.
8640 (__arm_vcvtaq_u32_f32): Likewise.
8641 (__arm_vcvtaq_s16_f16): Likewise.
8642 (__arm_vcvtaq_s32_f32): Likewise.
8643 (__arm_vcvtnq_s16_f16): Likewise.
8644 (__arm_vcvtnq_s32_f32): Likewise.
8645 (__arm_vcvtpq_s16_f16): Likewise.
8646 (__arm_vcvtpq_s32_f32): Likewise.
8647 (__arm_vcvtmq_s16_f16): Likewise.
8648 (__arm_vcvtmq_s32_f32): Likewise.
8649 (vdupq_n): Define polymorphic variant.
8650 (vabsq): Likewise.
8651 (vclsq): Likewise.
8652 (vclzq): Likewise.
8653 (vnegq): Likewise.
8654 (vaddlvq): Likewise.
8655 (vaddvq): Likewise.
8656 (vmovlbq): Likewise.
8657 (vmovltq): Likewise.
8658 (vmvnq): Likewise.
8659 (vrev16q): Likewise.
8660 (vrev32q): Likewise.
8661 (vqabsq): Likewise.
8662 (vqnegq): Likewise.
8663 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
8664 (UNOP_SNONE_NONE): Likewise.
8665 (UNOP_UNONE_UNONE): Likewise.
8666 (UNOP_UNONE_NONE): Likewise.
8667 * config/arm/constraints.md (e): Define new constriant to allow only
8668 even registers.
8669 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
8670 (mve_vnegq_s<mode>): Likewise.
8671 (mve_vmvnq_<supf><mode>): Likewise.
8672 (mve_vdupq_n_<supf><mode>): Likewise.
8673 (mve_vclzq_<supf><mode>): Likewise.
8674 (mve_vclsq_s<mode>): Likewise.
8675 (mve_vaddvq_<supf><mode>): Likewise.
8676 (mve_vabsq_s<mode>): Likewise.
8677 (mve_vrev32q_<supf><mode>): Likewise.
8678 (mve_vmovltq_<supf><mode>): Likewise.
8679 (mve_vmovlbq_<supf><mode>): Likewise.
8680 (mve_vcvtpq_<supf><mode>): Likewise.
8681 (mve_vcvtnq_<supf><mode>): Likewise.
8682 (mve_vcvtmq_<supf><mode>): Likewise.
8683 (mve_vcvtaq_<supf><mode>): Likewise.
8684 (mve_vrev16q_<supf>v16qi): Likewise.
8685 (mve_vaddlvq_<supf>v4si): Likewise.
8687 2020-03-17 Jakub Jelinek <jakub@redhat.com>
8689 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in
8690 a dump message.
8691 * tree-sra.c (create_access_replacement): Fix up duplicated word issue
8692 in a comment.
8693 * read-rtl-function.c (find_param_by_name,
8694 function_reader::parse_enum_value, function_reader::get_insn_by_uid):
8695 Likewise.
8696 * spellcheck.c (get_edit_distance_cutoff): Likewise.
8697 * tree-data-ref.c (create_ifn_alias_checks): Likewise.
8698 * tree.def (SWITCH_EXPR): Likewise.
8699 * selftest.c (assert_str_contains): Likewise.
8700 * ipa-param-manipulation.h (class ipa_param_body_adjustments):
8701 Likewise.
8702 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
8703 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
8704 * langhooks.h (struct lang_hooks_for_decls): Likewise.
8705 * ipa-prop.h (struct ipa_param_descriptor): Likewise.
8706 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
8707 Likewise.
8708 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
8709 * tree-ssa-reassoc.c (reassociate_bb): Likewise.
8710 * tree.c (component_ref_size): Likewise.
8711 * hsa-common.c (hsa_init_compilation_unit_data): Likewise.
8712 * gimple-ssa-sprintf.c (get_string_length, format_string,
8713 format_directive): Likewise.
8714 * omp-grid.c (grid_process_kernel_body_copy): Likewise.
8715 * input.c (string_concat_db::get_string_concatenation,
8716 test_lexer_string_locations_ucn4): Likewise.
8717 * cfgexpand.c (pass_expand::execute): Likewise.
8718 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
8719 maybe_diag_overlap): Likewise.
8720 * rtl.c (RTX_CODE_HWINT_P_1): Likewise.
8721 * shrink-wrap.c (spread_components): Likewise.
8722 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
8723 Likewise.
8724 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
8725 Likewise.
8726 * dwarf2out.c (dwarf2out_early_finish): Likewise.
8727 * gimple-ssa-store-merging.c: Likewise.
8728 * ira-costs.c (record_operand_costs): Likewise.
8729 * tree-vect-loop.c (vectorizable_reduction): Likewise.
8730 * target.def (dispatch): Likewise.
8731 (validate_dims, gen_ccmp_first): Fix up duplicated word issue
8732 in documentation text.
8733 * doc/tm.texi: Regenerated.
8734 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
8735 duplicated word issue in a comment.
8736 * config/i386/i386.c (ix86_test_loading_unspec): Likewise.
8737 * config/i386/i386-features.c (remove_partial_avx_dependency):
8738 Likewise.
8739 * config/msp430/msp430.c (msp430_select_section): Likewise.
8740 * config/gcn/gcn-run.c (load_image): Likewise.
8741 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
8742 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
8743 * config/aarch64/falkor-tag-collision-avoidance.c
8744 (single_dest_per_chain): Likewise.
8745 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
8746 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
8747 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
8748 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
8749 Likewise.
8750 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
8751 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
8752 * config/rs6000/rs6000-logue.c
8753 (rs6000_emit_probe_stack_range_stack_clash): Likewise.
8754 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
8755 Fix various other issues in the comment.
8757 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
8759 * config/arm/t-rmprofile: create new multilib for
8760 armv8.1-m.main+mve hard float and reuse v8-m.main ones for
8761 v8.1-m.main+mve.
8763 2020-03-17 Jakub Jelinek <jakub@redhat.com>
8765 PR tree-optimization/94015
8766 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
8767 function where EXP is address of the bytes being stored rather than
8768 the bytes themselves into count_nonzero_bytes_addr. Punt on zero
8769 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
8770 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before
8771 calling native_encode_expr if host or target doesn't have 8-bit
8772 chars. Formatting fixes.
8773 (count_nonzero_bytes_addr): New function.
8775 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8776 Mihail Ionescu <mihail.ionescu@arm.com>
8777 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8779 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
8780 (UNOP_SNONE_NONE_QUALIFIERS): Likewise.
8781 (UNOP_SNONE_IMM_QUALIFIERS): Likewise.
8782 (UNOP_UNONE_NONE_QUALIFIERS): Likewise.
8783 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
8784 (UNOP_UNONE_IMM_QUALIFIERS): Likewise.
8785 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
8786 (vmvnq_n_s32): Likewise.
8787 (vrev64q_s8): Likewise.
8788 (vrev64q_s16): Likewise.
8789 (vrev64q_s32): Likewise.
8790 (vcvtq_s16_f16): Likewise.
8791 (vcvtq_s32_f32): Likewise.
8792 (vrev64q_u8): Likewise.
8793 (vrev64q_u16): Likewise.
8794 (vrev64q_u32): Likewise.
8795 (vmvnq_n_u16): Likewise.
8796 (vmvnq_n_u32): Likewise.
8797 (vcvtq_u16_f16): Likewise.
8798 (vcvtq_u32_f32): Likewise.
8799 (__arm_vmvnq_n_s16): Define intrinsic.
8800 (__arm_vmvnq_n_s32): Likewise.
8801 (__arm_vrev64q_s8): Likewise.
8802 (__arm_vrev64q_s16): Likewise.
8803 (__arm_vrev64q_s32): Likewise.
8804 (__arm_vrev64q_u8): Likewise.
8805 (__arm_vrev64q_u16): Likewise.
8806 (__arm_vrev64q_u32): Likewise.
8807 (__arm_vmvnq_n_u16): Likewise.
8808 (__arm_vmvnq_n_u32): Likewise.
8809 (__arm_vcvtq_s16_f16): Likewise.
8810 (__arm_vcvtq_s32_f32): Likewise.
8811 (__arm_vcvtq_u16_f16): Likewise.
8812 (__arm_vcvtq_u32_f32): Likewise.
8813 (vrev64q): Define polymorphic variant.
8814 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
8815 (UNOP_SNONE_NONE): Likewise.
8816 (UNOP_SNONE_IMM): Likewise.
8817 (UNOP_UNONE_UNONE): Likewise.
8818 (UNOP_UNONE_NONE): Likewise.
8819 (UNOP_UNONE_IMM): Likewise.
8820 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
8821 (mve_vcvtq_from_f_<supf><mode>): Likewise.
8822 (mve_vmvnq_n_<supf><mode>): Likewise.
8824 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
8825 Mihail Ionescu <mihail.ionescu@arm.com>
8826 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8828 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
8829 (UNOP_NONE_SNONE_QUALIFIERS): Likewise.
8830 (UNOP_NONE_UNONE_QUALIFIERS): Likewise.
8831 * config/arm/arm_mve.h (vrndxq_f16): Define macro.
8832 (vrndxq_f32): Likewise.
8833 (vrndq_f16) Likewise.
8834 (vrndq_f32): Likewise.
8835 (vrndpq_f16): Likewise.
8836 (vrndpq_f32): Likewise.
8837 (vrndnq_f16): Likewise.
8838 (vrndnq_f32): Likewise.
8839 (vrndmq_f16): Likewise.
8840 (vrndmq_f32): Likewise.
8841 (vrndaq_f16): Likewise.
8842 (vrndaq_f32): Likewise.
8843 (vrev64q_f16): Likewise.
8844 (vrev64q_f32): Likewise.
8845 (vnegq_f16): Likewise.
8846 (vnegq_f32): Likewise.
8847 (vdupq_n_f16): Likewise.
8848 (vdupq_n_f32): Likewise.
8849 (vabsq_f16): Likewise.
8850 (vabsq_f32): Likewise.
8851 (vrev32q_f16): Likewise.
8852 (vcvttq_f32_f16): Likewise.
8853 (vcvtbq_f32_f16): Likewise.
8854 (vcvtq_f16_s16): Likewise.
8855 (vcvtq_f32_s32): Likewise.
8856 (vcvtq_f16_u16): Likewise.
8857 (vcvtq_f32_u32): Likewise.
8858 (__arm_vrndxq_f16): Define intrinsic.
8859 (__arm_vrndxq_f32): Likewise.
8860 (__arm_vrndq_f16): Likewise.
8861 (__arm_vrndq_f32): Likewise.
8862 (__arm_vrndpq_f16): Likewise.
8863 (__arm_vrndpq_f32): Likewise.
8864 (__arm_vrndnq_f16): Likewise.
8865 (__arm_vrndnq_f32): Likewise.
8866 (__arm_vrndmq_f16): Likewise.
8867 (__arm_vrndmq_f32): Likewise.
8868 (__arm_vrndaq_f16): Likewise.
8869 (__arm_vrndaq_f32): Likewise.
8870 (__arm_vrev64q_f16): Likewise.
8871 (__arm_vrev64q_f32): Likewise.
8872 (__arm_vnegq_f16): Likewise.
8873 (__arm_vnegq_f32): Likewise.
8874 (__arm_vdupq_n_f16): Likewise.
8875 (__arm_vdupq_n_f32): Likewise.
8876 (__arm_vabsq_f16): Likewise.
8877 (__arm_vabsq_f32): Likewise.
8878 (__arm_vrev32q_f16): Likewise.
8879 (__arm_vcvttq_f32_f16): Likewise.
8880 (__arm_vcvtbq_f32_f16): Likewise.
8881 (__arm_vcvtq_f16_s16): Likewise.
8882 (__arm_vcvtq_f32_s32): Likewise.
8883 (__arm_vcvtq_f16_u16): Likewise.
8884 (__arm_vcvtq_f32_u32): Likewise.
8885 (vrndxq): Define polymorphic variants.
8886 (vrndq): Likewise.
8887 (vrndpq): Likewise.
8888 (vrndnq): Likewise.
8889 (vrndmq): Likewise.
8890 (vrndaq): Likewise.
8891 (vrev64q): Likewise.
8892 (vnegq): Likewise.
8893 (vabsq): Likewise.
8894 (vrev32q): Likewise.
8895 (vcvtbq_f32): Likewise.
8896 (vcvttq_f32): Likewise.
8897 (vcvtq): Likewise.
8898 * config/arm/arm_mve_builtins.def (VAR2): Define.
8899 (VAR1): Define.
8900 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
8901 (mve_vrndq_f<mode>): Likewise.
8902 (mve_vrndpq_f<mode>): Likewise.
8903 (mve_vrndnq_f<mode>): Likewise.
8904 (mve_vrndmq_f<mode>): Likewise.
8905 (mve_vrndaq_f<mode>): Likewise.
8906 (mve_vrev64q_f<mode>): Likewise.
8907 (mve_vnegq_f<mode>): Likewise.
8908 (mve_vdupq_n_f<mode>): Likewise.
8909 (mve_vabsq_f<mode>): Likewise.
8910 (mve_vrev32q_fv8hf): Likewise.
8911 (mve_vcvttq_f32_f16v4sf): Likewise.
8912 (mve_vcvtbq_f32_f16v4sf): Likewise.
8913 (mve_vcvtq_to_f_<supf><mode>): Likewise.
8915 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
8916 Mihail Ionescu <mihail.ionescu@arm.com>
8917 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8919 * config/arm/arm-builtins.c (CF): Define mve_builtin_data.
8920 (VAR1): Define.
8921 (ARM_BUILTIN_MVE_PATTERN_START): Define.
8922 (arm_init_mve_builtins): Define function.
8923 (arm_init_builtins): Add TARGET_HAVE_MVE check.
8924 (arm_expand_builtin_1): Check the range of fcode.
8925 (arm_expand_mve_builtin): Define function to expand MVE builtins.
8926 (arm_expand_builtin): Check the range of fcode.
8927 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
8928 types.
8929 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
8930 (vst4q_s8): Define macro.
8931 (vst4q_s16): Likewise.
8932 (vst4q_s32): Likewise.
8933 (vst4q_u8): Likewise.
8934 (vst4q_u16): Likewise.
8935 (vst4q_u32): Likewise.
8936 (vst4q_f16): Likewise.
8937 (vst4q_f32): Likewise.
8938 (__arm_vst4q_s8): Define inline builtin.
8939 (__arm_vst4q_s16): Likewise.
8940 (__arm_vst4q_s32): Likewise.
8941 (__arm_vst4q_u8): Likewise.
8942 (__arm_vst4q_u16): Likewise.
8943 (__arm_vst4q_u32): Likewise.
8944 (__arm_vst4q_f16): Likewise.
8945 (__arm_vst4q_f32): Likewise.
8946 (__ARM_mve_typeid): Define macro with MVE types.
8947 (__ARM_mve_coerce): Define macro with _Generic feature.
8948 (vst4q): Define polymorphic variant for different vst4q builtins.
8949 * config/arm/arm_mve_builtins.def: New file.
8950 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
8951 modes in MVE.
8952 * config/arm/mve.md (MVE_VLD_ST): Define iterator.
8953 (unspec): Define unspec.
8954 (mve_vst4q<mode>): Define RTL pattern.
8955 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
8956 modes in MVE.
8957 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
8958 in MVE.
8959 (define_split): Allow OI mode split for MVE after reload.
8960 (define_split): Allow XI mode split for MVE after reload.
8961 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
8962 (arm-builtins.o): Likewise.
8964 2020-03-17 Christophe Lyon <christophe.lyon@linaro.org>
8966 * c-typeck.c (process_init_element): Handle constructor_type with
8967 type size represented by POLY_INT_CST.
8969 2020-03-17 Jakub Jelinek <jakub@redhat.com>
8971 PR tree-optimization/94187
8972 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if
8973 nchars - offset < nbytes.
8975 PR middle-end/94189
8976 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
8977 emit a warning if it was enabled and don't depend on TREE_NO_WARNING
8978 for code-generation.
8980 2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
8982 PR target/94185
8983 * lra-spills.c (remove_pseudos): Do not reuse insn alternative
8984 after changing memory subreg.
8986 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
8987 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8989 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
8990 emulator calls for dobule precision arithmetic operations for MVE.
8992 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
8993 Mihail Ionescu <mihail.ionescu@arm.com>
8994 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8996 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
8997 feature bit is on and -mfpu=auto is passed as compiler option, do not
8998 generate error on not finding any matching fpu. Because in this case
8999 fpu is not required.
9000 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
9001 enabled for MVE and also for all VFP extensions.
9002 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
9003 is enabled.
9004 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
9005 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
9006 along with feature bits mve_float.
9007 (mve): Modify add options in armv8.1-m.main arch for MVE.
9008 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with
9009 floating point.
9010 * config/arm/arm.c (use_return_insn): Replace the
9011 check with TARGET_VFP_BASE.
9012 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
9013 TARGET_VFP_BASE.
9014 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
9015 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
9016 well.
9017 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
9018 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
9019 as well.
9020 (arm_compute_frame_layout): Likewise.
9021 (arm_save_coproc_regs): Likewise.
9022 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
9023 in MVE as well.
9024 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
9025 with equivalent macro TARGET_VFP_BASE.
9026 (arm_expand_epilogue_apcs_frame): Likewise.
9027 (arm_expand_epilogue): Likewise.
9028 (arm_conditional_register_usage): Likewise.
9029 (arm_declare_function_name): Add check to skip printing .fpu directive
9030 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
9031 "softvfp".
9032 * config/arm/arm.h (TARGET_VFP_BASE): Define.
9033 * config/arm/arm.md (arch): Add "mve" to arch.
9034 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
9035 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
9036 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
9037 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR
9038 in MVE.
9039 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
9040 to not allow for MVE.
9041 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
9042 enum.
9043 (VUNSPEC_GET_FPSCR): Define.
9044 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
9045 instructions which move to general-purpose Register from Floating-point
9046 Special register and vice-versa.
9047 (thumb2_movhi_fp16): Likewise.
9048 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
9049 with MCR and MRC instructions which set and get Floating-point Status
9050 and Control Register (FPSCR).
9051 (movdi_vfp): Modify pattern to enable Single-precision scalar float move
9052 in MVE.
9053 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
9054 float move patterns in MVE.
9055 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
9056 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
9057 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
9058 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
9059 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
9060 TARGET_VFP_BASE check.
9061 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
9062 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
9063 register.
9064 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
9065 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
9066 register.
9069 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
9070 Mihail Ionescu <mihail.ionescu@arm.com>
9071 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9073 * config.gcc (arm_mve.h): Include mve intrinsics header file.
9074 * config/arm/aout.h (p0): Add new register name for MVE predicated
9075 cases.
9076 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
9077 common to Neon and MVE.
9078 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
9079 (arm_init_simd_builtin_types): Disable poly types for MVE.
9080 (arm_init_neon_builtins): Move a check to arm_init_builtins function.
9081 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
9082 ARM_BUILTIN_NEON_LANE_CHECK.
9083 (mve_dereference_pointer): Add function.
9084 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
9085 enabled.
9086 (arm_expand_neon_builtin): Moved to arm_expand_builtin function.
9087 (arm_expand_builtin): Moved from arm_expand_neon_builtin function.
9088 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
9089 with floating point enabled.
9090 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
9091 simd_immediate_valid_for_move.
9092 (simd_immediate_valid_for_move): Renamed from
9093 neon_immediate_valid_for_move function.
9094 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
9095 error if vfpv2 feature bit is disabled and mve feature bit is also
9096 disabled for HARD_FLOAT_ABI.
9097 (use_return_insn): Check to not push VFP regs for MVE.
9098 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
9099 as Neon.
9100 (aapcs_vfp_allocate_return_reg): Likewise.
9101 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
9102 address operand for MVE.
9103 (arm_rtx_costs_internal): MVE check to determine cost of rtx.
9104 (neon_valid_immediate): Rename to simd_valid_immediate.
9105 (simd_valid_immediate): Rename from neon_valid_immediate.
9106 (simd_valid_immediate): MVE check on size of vector is 128 bits.
9107 (neon_immediate_valid_for_move): Rename to
9108 simd_immediate_valid_for_move.
9109 (simd_immediate_valid_for_move): Rename from
9110 neon_immediate_valid_for_move.
9111 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
9112 function.
9113 (neon_make_constant): Modify call to neon_valid_immediate function.
9114 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
9115 for MVE.
9116 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
9117 (arm_compute_frame_layout): Calculate space for saved VFP registers for
9118 MVE.
9119 (arm_save_coproc_regs): Save coproc registers for MVE.
9120 (arm_print_operand): Add case 'E' to print memory operands for MVE.
9121 (arm_print_operand_address): Check to print register number for MVE.
9122 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
9123 (arm_modes_tieable_p): Check to allow structure mode for MVE.
9124 (arm_regno_class): Add VPR_REGNUM check.
9125 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
9126 for APCS frame.
9127 (arm_expand_epilogue): MVE check for enabling pop instructions in
9128 epilogue.
9129 (arm_print_asm_arch_directives): Modify function to disable print of
9130 .arch_extension "mve" and "fp" for cases where MVE is enabled with
9131 "SOFT FLOAT ABI".
9132 (arm_vector_mode_supported_p): Check for modes available in MVE interger
9133 and MVE floating point.
9134 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
9135 pointer support.
9136 (arm_conditional_register_usage): Enable usage of conditional regsiter
9137 for MVE.
9138 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
9139 (arm_declare_function_name): Modify function to disable print of
9140 .arch_extension "mve" and "fp" for cases where MVE is enabled with
9141 "SOFT FLOAT ABI".
9142 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
9143 when target general registers are required.
9144 (TARGET_HAVE_MVE_FLOAT): Likewise.
9145 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
9146 for MVE.
9147 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
9148 which indicate this is not available for across function calls.
9149 (FIRST_PSEUDO_REGISTER): Modify.
9150 (VALID_MVE_MODE): Define valid MVE mode.
9151 (VALID_MVE_SI_MODE): Define valid MVE SI mode.
9152 (VALID_MVE_SF_MODE): Define valid MVE SF mode.
9153 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
9154 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
9155 for MVE.
9156 (IS_VPR_REGNUM): Macro to check for VPR_REG register.
9157 (REG_ALLOC_ORDER): Add VPR_REGNUM entry.
9158 (enum reg_class): Add VPR_REG entry.
9159 (REG_CLASS_NAMES): Add VPR_REG entry.
9160 * config/arm/arm.md (VPR_REGNUM): Define.
9161 (conds): Check is_mve_type attrbiute to differentiate "conditional" and
9162 "unconditional" instructions.
9163 (arm_movsf_soft_insn): Modify RTL to not allow for MVE.
9164 (movdf_soft_insn): Modify RTL to not allow for MVE.
9165 (vfp_pop_multiple_with_writeback): Enable for MVE.
9166 (include "mve.md"): Include mve.md file.
9167 * config/arm/arm_mve.h: Add MVE intrinsics head file.
9168 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
9169 for vector predicated operands.
9170 * config/arm/iterators.md (VNIM1): Define.
9171 (VNINOTM1): Define.
9172 (VHFBF_split): Define
9173 * config/arm/mve.md: New file.
9174 (mve_mov<mode>): Define RTL for move, store and load in MVE.
9175 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
9176 second operand.
9177 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with
9178 simd_immediate_valid_for_move.
9179 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
9180 is common to MVE and NEON to vec-common.md file.
9181 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
9182 * config/arm/predicates.md (vpr_register_operand): Define.
9183 * config/arm/t-arm: Add mve.md file.
9184 * config/arm/types.md (mve_move): Add MVE instructions mve_move to
9185 attribute "type".
9186 (mve_store): Add MVE instructions mve_store to attribute "type".
9187 (mve_load): Add MVE instructions mve_load to attribute "type".
9188 (is_mve_type): Define attribute.
9189 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
9190 standard move patterns in MVE along with NEON and IWMMXT with mode
9191 iterator VNIM1.
9192 (mov<mode>): Modify RTL expand to support standard move patterns in NEON
9193 and IWMMXT with mode iterator V8HF.
9194 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in
9195 NEON and MVE.
9196 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
9197 simd_immediate_valid_for_move.
9200 2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
9202 PR target/89229
9203 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
9204 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
9205 check.
9206 * config/i386/predicates.md (ext_sse_reg_operand): Removed.
9208 2020-03-16 Jakub Jelinek <jakub@redhat.com>
9210 PR debug/94167
9211 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
9212 DEBUG_STMTs.
9214 PR tree-optimization/94166
9215 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
9216 as secondary comparison key.
9218 2020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com>
9220 PR tree-optimization/94125
9221 * tree-loop-distribution.c
9222 (loop_distribution::break_alias_scc_partitions): Update post order
9223 number for merged scc.
9225 2020-03-15 H.J. Lu <hongjiu.lu@intel.com>
9227 PR target/89229
9228 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
9229 MODE_SF.
9230 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
9231 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
9232 and ext_sse_reg_operand check.
9234 2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
9236 * common.opt: Avoid redundancy in the help text.
9237 * config/arc/arc.opt: Likewise.
9238 * config/cr16/cr16.opt: Likewise.
9240 2020-03-14 Jakub Jelinek <jakub@redhat.com>
9242 PR middle-end/93566
9243 * tree-nested.c (convert_nonlocal_omp_clauses,
9244 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
9245 with C/C++ array sections.
9247 2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
9249 PR target/89229
9250 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
9251 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
9252 check.
9254 2020-03-14 Jakub Jelinek <jakub@redhat.com>
9256 * gimple-fold.c (gimple_fold_builtin_strncpy): Change
9257 "a an" to "an" in a comment.
9258 * hsa-common.h (is_a_helper): Likewise.
9259 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
9260 * config/arc/arc.c (arc600_corereg_hazard): Likewise.
9261 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
9263 2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
9265 PR target/92379
9266 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a
9267 64-bit value by 64 bits (UB).
9269 2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
9271 PR rtl-optimization/92303
9272 * lra-spills.c (remove_pseudos): Try to simplify memory subreg.
9274 2020-03-13 Segher Boessenkool <segher@kernel.crashing.org>
9276 PR rtl-optimization/94148
9277 PR rtl-optimization/94042
9278 * df-core.c (BB_LAST_CHANGE_AGE): Delete.
9279 (df_worklist_propagate_forward): New parameter last_change_age, use
9280 that instead of bb->aux.
9281 (df_worklist_propagate_backward): Ditto.
9282 (df_worklist_dataflow_doublequeue): Use a local array last_change_age.
9284 2020-03-13 Richard Biener <rguenther@suse.de>
9286 PR tree-optimization/94163
9287 * tree-ssa-pre.c (create_expression_by_pieces): Check
9288 whether alignment would be zero.
9290 2020-03-13 Martin Liska <mliska@suse.cz>
9292 PR lto/94157
9293 * lto-wrapper.c (run_gcc): Use concat for appending
9294 to collect_gcc_options.
9296 2020-03-13 Jakub Jelinek <jakub@redhat.com>
9298 PR target/94121
9299 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
9300 instead of GEN_INT.
9302 2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
9304 PR target/89229
9305 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
9306 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
9307 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
9308 TARGET_AVX512VL and ext_sse_reg_operand check.
9310 2020-03-13 Bu Le <bule1@huawei.com>
9312 PR target/94154
9313 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
9314 (-param=aarch64-double-recp-precision=): New options.
9315 * doc/invoke.texi: Document them.
9316 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
9317 instead of hard-coding the choice of 1 for float and 2 for double.
9319 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
9321 PR rtl-optimization/94119
9322 * resource.h (clear_hashed_info_until_next_barrier): Declare.
9323 * resource.c (clear_hashed_info_until_next_barrier): New function.
9324 * reorg.c (add_to_delay_list): Fix formatting.
9325 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
9326 the next instruction after removing a BARRIER.
9328 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
9330 PR middle-end/92071
9331 * expmed.c (store_integral_bit_field): For fields larger than a word,
9332 call extract_bit_field on the value if the mode is BLKmode. Remove
9333 specific path for big-endian targets and tidy things up a little bit.
9335 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
9337 PR rtl-optimization/90275
9338 * cse.c (cse_insn): Delete no-op register moves too.
9340 2020-03-12 Darius Galis <darius.galis@cyberthorstudios.com>
9342 * config/rx/rx.md (CTRLREG_CPEN): Remove.
9343 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
9345 2020-03-12 Richard Biener <rguenther@suse.de>
9347 PR tree-optimization/94103
9348 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
9349 punning when the mode precision is not sufficient.
9351 2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
9353 PR target/89229
9354 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
9355 MODE_V1DF and MODE_V2SF.
9356 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
9357 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
9358 check.
9360 2020-03-12 Jakub Jelinek <jakub@redhat.com>
9362 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
9363 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
9364 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
9365 * doc/tm.texi: Regenerated.
9367 PR tree-optimization/94130
9368 * tree-ssa-dse.c: Include gimplify.h.
9369 (increment_start_addr): If stmt has lhs, drop the lhs from call and
9370 set it after the call to the original value of the first argument.
9371 Formatting fixes.
9372 (decrement_count): Formatting fix.
9374 2020-03-11 Delia Burduv <delia.burduv@arm.com>
9376 * config/arm/arm-builtins.c
9377 (arm_init_simd_builtin_scalar_types): New.
9378 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
9379 (vld2q_bf16): Used new builtin type.
9380 (vld3_bf16): Used new builtin type.
9381 (vld3q_bf16): Used new builtin type.
9382 (vld4_bf16): Used new builtin type.
9383 (vld4q_bf16): Used new builtin type.
9384 (vld2_dup_bf16): Used new builtin type.
9385 (vld2q_dup_bf16): Used new builtin type.
9386 (vld3_dup_bf16): Used new builtin type.
9387 (vld3q_dup_bf16): Used new builtin type.
9388 (vld4_dup_bf16): Used new builtin type.
9389 (vld4q_dup_bf16): Used new builtin type.
9391 2020-03-11 Jakub Jelinek <jakub@redhat.com>
9393 PR target/94134
9394 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
9395 at the start to switch to data section. Don't print extra newline if
9396 .globl directive has not been emitted.
9398 2020-03-11 Richard Biener <rguenther@suse.de>
9400 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
9401 New pattern.
9403 2020-03-11 Eric Botcazou <ebotcazou@adacore.com>
9405 PR middle-end/93961
9406 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields
9407 whose type is a qualified union.
9409 2020-03-11 Jakub Jelinek <jakub@redhat.com>
9411 PR target/94121
9412 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
9413 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
9415 PR bootstrap/93962
9416 * value-prof.c (dump_histogram_value): Use abs_hwi instead of
9417 std::abs.
9418 (get_nth_most_common_value): Use abs_hwi instead of abs.
9420 PR middle-end/94111
9421 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
9422 is rvc_normal, otherwise use real_to_decimal to print the number to
9423 string.
9425 PR tree-optimization/94114
9426 * tree-loop-distribution.c (generate_memset_builtin): Call
9427 rewrite_to_non_trapping_overflow even on mem.
9428 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
9429 on dest and src.
9431 2020-03-10 Jeff Law <law@redhat.com>
9433 * config/bfin/bfin.md (movsi_insv): Add length attribute.
9435 2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
9437 PR target/93709
9438 * gcc/config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
9439 NAN and SIGNED_ZEROR for smax/smin.
9441 2020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
9443 PR target/90763
9444 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
9445 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
9447 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
9449 * loop-iv.c (find_simple_exit): Make it static.
9450 * cfgloop.h: Remove the corresponding prototype.
9452 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
9454 * ddg.c (create_ddg): Fix intendation.
9455 (set_recurrence_length): Likewise.
9456 (create_ddg_all_sccs): Likewise.
9458 2020-03-10 Jakub Jelinek <jakub@redhat.com>
9460 PR target/94088
9461 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with
9462 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len
9463 is 32.
9465 2020-03-09 Jason Merrill <jason@redhat.com>
9467 * gdbinit.in (pgs): Fix typo in documentation.
9469 2020-03-09 Vladimir Makarov <vmakarov@redhat.com>
9471 Revert:
9473 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
9475 PR rtl-optimization/93564
9476 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
9477 do not honor reg alloc order.
9479 2020-03-09 Andrew Pinski <apinski@marvell.com>
9481 PR inline-asm/94095
9482 * doc/extend.texi (x86 Operand Modifiers): Fix column
9483 for 'A' modifier.
9485 2020-03-09 Martin Liska <mliska@suse.cz>
9487 PR target/93800
9488 * config/rs6000/rs6000.c (rs6000_option_override_internal):
9489 Remove set of str_align_loops and str_align_jumps as these
9490 should be set in previous 2 conditions in the function.
9492 2020-03-09 Jakub Jelinek <jakub@redhat.com>
9494 PR rtl-optimization/94045
9495 * params.opt (-param=max-find-base-term-values=): New option.
9496 * alias.c (find_base_term): Add cut-off for number of visited VALUEs
9497 in a single toplevel find_base_term call.
9499 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
9501 PR target/91598
9502 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define.
9503 * config/aarch64/aarch64-simd.md
9504 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul.
9505 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
9506 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
9507 * config/aarch64/arm_neon.h:
9508 (vmlal_lane_s16): Expand using intrinsics rather than inline asm.
9509 (vmlal_lane_u16): Likewise.
9510 (vmlal_lane_s32): Likewise.
9511 (vmlal_lane_u32): Likewise.
9512 (vmlal_laneq_s16): Likewise.
9513 (vmlal_laneq_u16): Likewise.
9514 (vmlal_laneq_s32): Likewise.
9515 (vmlal_laneq_u32): Likewise.
9516 (vmull_lane_s16): Likewise.
9517 (vmull_lane_u16): Likewise.
9518 (vmull_lane_s32): Likewise.
9519 (vmull_lane_u32): Likewise.
9520 (vmull_laneq_s16): Likewise.
9521 (vmull_laneq_u16): Likewise.
9522 (vmull_laneq_s32): Likewise.
9523 (vmull_laneq_u32): Likewise.
9524 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul.
9525 (Qlane): Likewise.
9527 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
9529 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
9530 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
9531 (aarch64_mls_elt<mode>): Likewise.
9532 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
9533 (aarch64_fma4_elt<mode>): Likewise.
9534 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
9535 (aarch64_fma4_elt_to_64v2df): Likewise.
9536 (aarch64_fnma4_elt<mode>): Likewise.
9537 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
9538 (aarch64_fnma4_elt_to_64v2df): Likewise.
9540 2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
9542 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
9543 Specify movprfx attribute.
9544 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
9546 2020-03-06 David Edelsohn <dje.gcc@gmail.com>
9548 PR target/94065
9549 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for
9550 cmodel=large.
9551 (TARGET_NO_FP_IN_TOC): Same.
9552 * config/rs6000/aix71.h: Same.
9553 * config/rs6000/aix72.h: Same.
9555 2020-03-06 Andrew Pinski <apinski@marvell.com>
9556 Jeff Law <law@redhat.com>
9558 PR rtl-optimization/93996
9559 * haifa-sched.c (remove_notes): Be more careful when adding
9560 REG_SAVE_NOTE.
9562 2020-03-06 Delia Burduv <delia.burduv@arm.com>
9564 * config/arm/arm_neon.h (vld2_bf16): New.
9565 (vld2q_bf16): New.
9566 (vld3_bf16): New.
9567 (vld3q_bf16): New.
9568 (vld4_bf16): New.
9569 (vld4q_bf16): New.
9570 (vld2_dup_bf16): New.
9571 (vld2q_dup_bf16): New.
9572 (vld3_dup_bf16): New.
9573 (vld3q_dup_bf16): New.
9574 (vld4_dup_bf16): New.
9575 (vld4q_dup_bf16): New.
9576 * config/arm/arm_neon_builtins.def
9577 (vld2): Changed to VAR13 and added v4bf, v8bf
9578 (vld2_dup): Changed to VAR8 and added v4bf, v8bf
9579 (vld3): Changed to VAR13 and added v4bf, v8bf
9580 (vld3_dup): Changed to VAR8 and added v4bf, v8bf
9581 (vld4): Changed to VAR13 and added v4bf, v8bf
9582 (vld4_dup): Changed to VAR8 and added v4bf, v8bf
9583 * config/arm/iterators.md (VDXBF2): New iterator.
9584 *config/arm/neon.md (neon_vld2): Use new iterators.
9585 (neon_vld2_dup<mode): Use new iterators.
9586 (neon_vld3<mode>): Likewise.
9587 (neon_vld3qa<mode>): Likewise.
9588 (neon_vld3qb<mode>): Likewise.
9589 (neon_vld3_dup<mode>): Likewise.
9590 (neon_vld4<mode>): Likewise.
9591 (neon_vld4qa<mode>): Likewise.
9592 (neon_vld4qb<mode>): Likewise.
9593 (neon_vld4_dup<mode>): Likewise.
9594 (neon_vld2_dupv8bf): New.
9595 (neon_vld3_dupv8bf): Likewise.
9596 (neon_vld4_dupv8bf): Likewise.
9598 2020-03-06 Delia Burduv <delia.burduv@arm.com>
9600 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
9601 (bfloat16x8x2_t): New typedef.
9602 (bfloat16x4x3_t): New typedef.
9603 (bfloat16x8x3_t): New typedef.
9604 (bfloat16x4x4_t): New typedef.
9605 (bfloat16x8x4_t): New typedef.
9606 (vst2_bf16): New.
9607 (vst2q_bf16): New.
9608 (vst3_bf16): New.
9609 (vst3q_bf16): New.
9610 (vst4_bf16): New.
9611 (vst4q_bf16): New.
9612 * config/arm/arm-builtins.c (v2bf_UP): Define.
9613 (VAR13): New.
9614 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype.
9615 * config/arm/arm-modes.def (V2BF): New mode.
9616 * config/arm/arm-simd-builtin-types.def
9617 (Bfloat16x2_t): New entry.
9618 * config/arm/arm_neon_builtins.def
9619 (vst2): Changed to VAR13 and added v4bf, v8bf
9620 (vst3): Changed to VAR13 and added v4bf, v8bf
9621 (vst4): Changed to VAR13 and added v4bf, v8bf
9622 * config/arm/iterators.md (VDXBF): New iterator.
9623 (VQ2BF): New iterator.
9624 *config/arm/neon.md (neon_vst2<mode>): Used new iterators.
9625 (neon_vst2<mode>): Used new iterators.
9626 (neon_vst3<mode>): Used new iterators.
9627 (neon_vst3<mode>): Used new iterators.
9628 (neon_vst3qa<mode>): Used new iterators.
9629 (neon_vst3qb<mode>): Used new iterators.
9630 (neon_vst4<mode>): Used new iterators.
9631 (neon_vst4<mode>): Used new iterators.
9632 (neon_vst4qa<mode>): Used new iterators.
9633 (neon_vst4qb<mode>): Used new iterators.
9635 2020-03-06 Delia Burduv <delia.burduv@arm.com>
9637 * config/aarch64/aarch64-simd-builtins.def
9638 (bfcvtn): New built-in function.
9639 (bfcvtn_q): New built-in function.
9640 (bfcvtn2): New built-in function.
9641 (bfcvt): New built-in function.
9642 * config/aarch64/aarch64-simd.md
9643 (aarch64_bfcvtn<q><mode>): New pattern.
9644 (aarch64_bfcvtn2v8bf): New pattern.
9645 (aarch64_bfcvtbf): New pattern.
9646 * config/aarch64/arm_bf16.h (float32_t): New typedef.
9647 (vcvth_bf16_f32): New intrinsic.
9648 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic.
9649 (vcvtq_low_bf16_f32): New intrinsic.
9650 (vcvtq_high_bf16_f32): New intrinsic.
9651 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator.
9652 (UNSPEC_BFCVTN): New UNSPEC.
9653 (UNSPEC_BFCVTN2): New UNSPEC.
9654 (UNSPEC_BFCVT): New UNSPEC.
9655 * config/arm/types.md (bf_cvt): New type.
9657 2020-03-06 Andreas Krebbel <krebbel@linux.ibm.com>
9659 * config/s390/s390.md ("tabort"): Get rid of two consecutive
9660 blanks in format string.
9662 2020-03-05 H.J. Lu <hongjiu.lu@intel.com>
9664 PR target/89229
9665 PR target/89346
9666 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype.
9667 * config/i386/i386.c (ix86_get_ssemov): New function.
9668 (ix86_output_ssemov): Likewise.
9669 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call
9670 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL
9671 check.
9672 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV.
9673 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV.
9674 Remove ext_sse_reg_operand and TARGET_AVX512VL check.
9675 (*movti_internal): Likewise.
9676 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV.
9678 2020-03-05 Jeff Law <law@redhat.com>
9680 PR tree-optimization/91890
9681 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument.
9682 Use gimple_or_expr_nonartificial_location.
9683 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds.
9684 Use gimple_or_expr_nonartificial_location.
9685 * gimple.c (gimple_or_expr_nonartificial_location): New function.
9686 * gimple.h (gimple_or_expr_nonartificial_location): Declare it.
9687 * tree-ssa-strlen.c (maybe_warn_overflow): Use
9688 gimple_or_expr_nonartificial_location.
9689 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise.
9690 (maybe_warn_pointless_strcmp): Likewise.
9692 2020-03-05 Jakub Jelinek <jakub@redhat.com>
9694 PR target/94046
9695 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
9696 SRC and MASK arguments to __m128 from __m128d.
9697 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
9698 from __m256d.
9699 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
9700 from __m128d.
9701 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
9702 argument to __m128i from __m128d.
9703 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
9704 __m256d.
9705 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
9706 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
9707 __m256.
9709 2020-03-05 Delia Burduv <delia.burduv@arm.com>
9711 * config/arm/arm_neon.h (vbfmmlaq_f32): New.
9712 (vbfmlalbq_f32): New.
9713 (vbfmlaltq_f32): New.
9714 (vbfmlalbq_lane_f32): New.
9715 (vbfmlaltq_lane_f32): New.
9716 (vbfmlalbq_laneq_f32): New.
9717 (vbfmlaltq_laneq_f32): New.
9718 * config/arm/arm_neon_builtins.def (vmmla): New.
9719 (vfmab): New.
9720 (vfmat): New.
9721 (vfmab_lane): New.
9722 (vfmat_lane): New.
9723 (vfmab_laneq): New.
9724 (vfmat_laneq): New.
9725 * config/arm/iterators.md (BF_MA): New int iterator.
9726 (bt): New int attribute.
9727 (VQXBF): Copy of VQX with V8BF.
9728 * config/arm/neon.md (neon_vmmlav8bf): New insn.
9729 (neon_vfma<bt>v8bf): New insn.
9730 (neon_vfma<bt>_lanev8bf): New insn.
9731 (neon_vfma<bt>_laneqv8bf): New expand.
9732 (neon_vget_high<mode>): Changed iterator to VQXBF.
9733 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
9734 (UNSPEC_BFMAB): New UNSPEC.
9735 (UNSPEC_BFMAT): New UNSPEC.
9737 2020-03-05 Jakub Jelinek <jakub@redhat.com>
9739 PR middle-end/93399
9740 * tree-pretty-print.h (pretty_print_string): Declare.
9741 * tree-pretty-print.c (pretty_print_string): Remove forward
9742 declaration, no longer static. Change nbytes parameter type
9743 from unsigned to size_t.
9744 * print-rtl.c (print_value) <case CONST_STRING>: Use
9745 pretty_print_string and for shrink way too long strings.
9747 2020-03-05 Richard Biener <rguenther@suse.de>
9748 Jakub Jelinek <jakub@redhat.com>
9750 PR tree-optimization/93582
9751 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR
9752 last operand as signed when looking for memset offset. Formatting
9753 fix.
9755 2020-03-04 Andrew Pinski <apinski@marvell.com>
9757 PR bootstrap/93962
9758 * value-prof.c (dump_histogram_value): Use std::abs.
9760 2020-03-04 Martin Sebor <msebor@redhat.com>
9762 PR tree-optimization/93986
9763 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int
9764 operands to the same precision widest_int to avoid ICEs.
9766 2020-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
9768 PR target/87560
9769 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define.
9770 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry
9771 for OPTION_MASK_ALTIVEC.
9773 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
9775 * config.gcc: Include the glibc-stdint.h header for zTPF.
9777 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
9779 * config/s390/s390.c (s390_secondary_memory_needed): Disallow
9780 direct FPR-GPR copies.
9781 (s390_register_info_gprtofpr): Disallow GPR content to be saved in
9782 FPRs.
9784 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
9786 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new
9787 operands to the prologue_tpf expander.
9788 (s390_emit_epilogue): Likewise.
9789 (s390_option_override_internal): Do error checking and setup for
9790 the new options.
9791 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK)
9792 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET)
9793 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET)
9794 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions.
9795 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new
9796 operands for the check flag and the branch target.
9797 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check")
9798 ("mtpf-trace-hook-prologue-target")
9799 ("mtpf-trace-hook-epilogue-check")
9800 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New
9801 options.
9802 * doc/invoke.texi: Document -mtpf-trace-skip option. The other
9803 options are for debugging purposes and will not be documented
9804 here.
9806 2020-03-04 Jakub Jelinek <jakub@redhat.com>
9808 PR debug/93888
9809 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
9811 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti
9812 argument. Change pd argument so that it can be modified. Turn
9813 constant non-CONSTRUCTOR store into non-constant if it is too large.
9814 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid
9815 overflows.
9816 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust
9817 callers.
9819 2020-02-04 Richard Biener <rguenther@suse.de>
9821 PR tree-optimization/93964
9822 * graphite-isl-ast-to-gimple.c
9823 (gcc_expression_from_isl_ast_expr_id): Add intermediate
9824 conversion for pointer to integer converts.
9825 * graphite-scop-detection.c (assign_parameter_index_in_region):
9826 Relax assert.
9828 2020-03-04 Martin Liska <mliska@suse.cz>
9830 PR c/93886
9831 PR c/93887
9832 * doc/invoke.texi: Clarify --help=language and --help=common
9833 interaction.
9835 2020-03-04 Jakub Jelinek <jakub@redhat.com>
9837 PR tree-optimization/94001
9838 * tree-tailcall.c (process_assignment): Before comparing op1 to
9839 *ass_var, verify *ass_var is non-NULL.
9841 2020-03-04 Kito Cheng <kito.cheng@sifive.com>
9843 PR target/93995
9844 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
9845 the result of IOR.
9847 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
9849 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
9850 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
9851 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
9852 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
9853 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
9854 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
9855 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
9856 (V_bf_low, V_bf_cvt_m): New mode attributes.
9857 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
9858 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
9859 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
9860 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
9861 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
9863 2020-03-03 Jakub Jelinek <jakub@redhat.com>
9865 PR tree-optimization/93582
9866 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
9867 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
9868 members, initialize them in the constructor and if mask is non-NULL,
9869 artificially push_partial_def {} for the portions of the mask that
9870 contain zeros.
9871 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
9872 val and return (void *)-1. Formatting fix.
9873 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
9874 Formatting fix.
9875 (vn_reference_lookup): Add mask argument. If non-NULL, don't call
9876 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
9877 data.mask_result.
9878 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
9879 mask.
9880 (visit_stmt): Formatting fix.
9882 2020-03-03 Richard Biener <rguenther@suse.de>
9884 PR tree-optimization/93946
9885 * alias.h (refs_same_for_tbaa_p): Declare.
9886 * alias.c (refs_same_for_tbaa_p): New function.
9887 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
9888 zero.
9889 * tree-ssa-scopedtables.h
9890 (avail_exprs_stack::lookup_avail_expr): Add output argument
9891 giving access to the hashtable entry.
9892 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
9893 Likewise.
9894 * tree-ssa-dom.c: Include alias.h.
9895 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
9896 removing redundant store.
9897 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
9898 (ao_ref_init_from_vn_reference): Adjust prototype.
9899 (vn_reference_lookup_pieces): Likewise.
9900 (vn_reference_insert_pieces): Likewise.
9901 * tree-ssa-sccvn.c: Track base alias set in addition to alias
9902 set everywhere.
9903 (eliminate_dom_walker::eliminate_stmt): Also check base alias
9904 set when removing redundant stores.
9905 (visit_reference_op_store): Likewise.
9906 * dse.c (record_store): Adjust valdity check for redundant
9907 store removal.
9909 2020-03-03 Jakub Jelinek <jakub@redhat.com>
9911 PR target/26877
9912 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
9914 PR rtl-optimization/94002
9915 * explow.c (plus_constant): Punt if cst has VOIDmode and
9916 get_pool_mode is different from mode.
9918 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
9920 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
9921 address has an offset which fits the scalling constraint for a
9922 load/store operation.
9923 (legitimate_scaled_address_p): Update use
9924 leigitimate_small_data_address_p.
9925 (arc_print_operand): Likewise.
9926 (arc_legitimate_address_p): Likewise.
9927 (legitimate_small_data_address_p): Likewise.
9929 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
9931 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
9932 (fnmasf4_fpu): Likewise.
9934 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
9936 * config/arc/arc.md (adddi3): Early expand the 64bit operation into
9937 32bit ops.
9938 (subdi3): Likewise.
9939 (adddi3_i): Remove pattern.
9940 (subdi3_i): Likewise.
9942 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
9944 * config/arc/arc.md (eh_return): Add length info.
9946 2020-03-02 David Malcolm <dmalcolm@redhat.com>
9948 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
9950 2020-03-02 David Malcolm <dmalcolm@redhat.com>
9952 * doc/invoke.texi (Static Analyzer Options): Add
9953 -Wanalyzer-stale-setjmp-buffer to the list of options enabled
9954 by -fanalyzer.
9956 2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
9958 PR target/93997
9959 * config/i386/i386.md (movstrict<mode>): Allow only
9960 registers with VALID_INT_MODE_P modes.
9962 2020-03-02 Andrew Stubbs <ams@codesourcery.com>
9964 * config/gcn/gcn-valu.md (dpp_move<mode>): New.
9965 (reduc_insn): Use 'U' and 'B' operand codes.
9966 (reduc_<reduc_op>_scal_<mode>): Allow all types.
9967 (reduc_<reduc_op>_scal_v64di): Delete.
9968 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
9969 (*plus_carry_dpp_shr_v64si): Change to ...
9970 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
9971 (mov_from_lane63_v64di): Change to ...
9972 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
9973 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
9974 Support UNSPEC_MOV_DPP_SHR output formats.
9975 (gcn_expand_reduc_scalar): Add "use_moves" reductions.
9976 Add "use_extends" reductions.
9977 (print_operand_address): Add 'I' and 'U' codes.
9978 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
9980 2020-03-02 Martin Liska <mliska@suse.cz>
9982 * lto-wrapper.c: Fix typo in comment about
9983 C++ standard version.
9985 2020-03-01 Martin Sebor <msebor@redhat.com>
9987 PR c++/92721
9988 * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
9990 2020-03-01 Martin Sebor <msebor@redhat.com>
9992 PR middle-end/93829
9993 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
9994 of a pointer in the outermost ADDR_EXPRs.
9996 2020-02-28 Jeff Law <law@redhat.com>
9998 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
9999 * config/v850/v850.c (v850_asm_trampoline_template): Update
10000 accordingly.
10002 2020-02-28 Michael Meissner <meissner@linux.ibm.com>
10004 PR target/93937
10005 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
10006 Delete insn.
10008 2020-02-28 Martin Liska <mliska@suse.cz>
10010 PR other/93965
10011 * configure.ac: Improve detection of ld_date by requiring
10012 either two dashes or none.
10013 * configure: Regenerate.
10015 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
10017 PR rtl-optimization/93564
10018 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
10019 do not honor reg alloc order.
10021 2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
10023 PR target/87612
10024 * config/aarch64/aarch64.c (aarch64_override_options): Fix
10025 misleading warning string.
10027 2020-02-27 Martin Sebor <msebor@redhat.com>
10029 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
10031 2020-02-27 Michael Meissner <meissner@linux.ibm.com>
10033 PR target/93932
10034 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
10035 Split the insn into two parts. This insn only does variable
10036 extract from a register.
10037 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
10038 variable extract from memory.
10039 (vsx_extract_v4sf_var): Split the insn into two parts. This insn
10040 only does variable extract from a register.
10041 (vsx_extract_v4sf_var_load): New insn, do variable extract from
10042 memory.
10043 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
10044 into two parts. This insn only does variable extract from a
10045 register.
10046 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
10047 do variable extract from memory.
10049 2020-02-27 Martin Jambor <mjambor@suse.cz>
10050 Feng Xue <fxue@os.amperecomputing.com>
10052 PR ipa/93707
10053 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
10054 new function calls_same_node_or_its_all_contexts_clone_p.
10055 (cgraph_edge_brings_value_p): Use it.
10056 (cgraph_edge_brings_value_p): Likewise.
10057 (self_recursive_pass_through_p): Return false if caller is a clone.
10058 (self_recursive_agg_pass_through_p): Likewise.
10060 2020-02-27 Jan Hubicka <hubicka@ucw.cz>
10062 PR middle-end/92152
10063 * alias.c (ends_tbaa_access_path_p): Break out from ...
10064 (component_uses_parent_alias_set_from): ... here.
10065 * alias.h (ends_tbaa_access_path_p): Declare.
10066 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
10067 handle trailing arrays past end of tbaa access path.
10068 (aliasing_component_refs_p): ... here; likewise.
10069 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
10070 path; disambiguate also past end of it.
10071 (nonoverlapping_component_refs_p): Use only TBAA segment of the access
10072 path.
10074 2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
10076 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
10077 beginning of the file.
10078 (vcreate_bf16, vcombine_bf16): New.
10079 (vdup_n_bf16, vdupq_n_bf16): New.
10080 (vdup_lane_bf16, vdup_laneq_bf16): New.
10081 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
10082 (vduph_lane_bf16, vduph_laneq_bf16): New.
10083 (vset_lane_bf16, vsetq_lane_bf16): New.
10084 (vget_lane_bf16, vgetq_lane_bf16): New.
10085 (vget_high_bf16, vget_low_bf16): New.
10086 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
10087 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
10088 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
10089 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
10090 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
10091 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
10092 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
10093 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
10094 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
10095 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
10096 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
10097 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
10098 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
10099 (vreinterpretq_bf16_p128): New.
10100 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
10101 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
10102 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
10103 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
10104 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
10105 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
10106 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
10107 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
10108 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
10109 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
10110 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
10111 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
10112 (vreinterpretq_p128_bf16): New.
10113 * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
10114 (V_elem): Likewise.
10115 (V_elem_l): Likewise.
10116 (VD_LANE): Likewise.
10117 (VQX) Add V8BF.
10118 (V_DOUBLE): Likewise.
10119 (VDQX): Add V4BF and V8BF.
10120 (V_two_elem, V_three_elem, V_four_elem): Likewise.
10121 (V_reg): Likewise.
10122 (V_HALF): Likewise.
10123 (V_double_vector_mode): Likewise.
10124 (V_cmp_result): Likewise.
10125 (V_uf_sclr): Likewise.
10126 (V_sz_elem): Likewise.
10127 (Is_d_reg): Likewise.
10128 (V_mode_nunits): Likewise.
10129 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
10131 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
10133 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
10134 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
10135 (<expander><mode>3<exec>): Likewise.
10136 (<expander><mode>3): New.
10137 (v<expander><mode>3): New.
10138 (<expander><mode>3): New.
10139 (<expander><mode>3<exec>): Rename to ...
10140 (<expander>v64si3<exec>): ... this, and change modes to V64SI.
10141 * config/gcn/gcn.md (mnemonic): Use '%B' for not.
10143 2020-02-27 Alexandre Oliva <oliva@adacore.com>
10145 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
10146 them alone on vx7.
10148 2020-02-27 Richard Biener <rguenther@suse.de>
10150 PR tree-optimization/93508
10151 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
10152 non-_CHK variants. Valueize their length arguments.
10154 2020-02-27 Richard Biener <rguenther@suse.de>
10156 PR tree-optimization/93953
10157 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
10158 to the hash-map entry.
10160 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
10162 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
10164 2020-02-27 Mark Williams <mwilliams@fb.com>
10166 * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
10167 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
10168 -ffile-prefix-map and -fmacro-prefix-map.
10169 * lto-streamer-out.c: Include file-prefix-map.h.
10170 (lto_output_location): Remap the file part of locations.
10172 2020-02-27 Jakub Jelinek <jakub@redhat.com>
10174 PR c/93949
10175 * gimplify.c (gimplify_init_constructor): Don't promote readonly
10176 DECL_REGISTER variables to TREE_STATIC.
10178 PR tree-optimization/93582
10179 PR tree-optimization/93945
10180 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
10181 non-zero INTEGER_CST second argument and ref->offset or ref->size
10182 not a multiple of BITS_PER_UNIT.
10184 2020-02-27 Jonathan Wakely <jwakely@redhat.com>
10186 * doc/install.texi (Binaries): Update description of BullFreeware.
10188 2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
10190 PR c++/90467
10192 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
10193 C++ Language Options, Warning Options, and Static Analyzer
10194 Options lists. Document negative form of options enabled by
10195 default. Move some things around to more accurately sort
10196 warnings by category.
10197 (C++ Dialect Options, Warning Options, Static Analyzer
10198 Options): Document negative form of options when enabled by
10199 default. Move some things around to more accurately sort
10200 warnings by category. Add some missing index entries.
10201 Light copy-editing.
10203 2020-02-26 Carl Love <cel@us.ibm.com>
10205 PR target/91276
10206 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
10207 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
10208 for the vector unsigned short arguments. It is also listed as the
10209 name of the built-in for arguments vector unsigned short,
10210 vector unsigned int and vector unsigned long long built-ins. The
10211 name of the builtins for these arguments should be:
10212 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
10213 __builtin_crypto_vpmsumd respectively.
10215 2020-02-26 Richard Biener <rguenther@suse.de>
10217 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
10218 and load permutation.
10220 2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
10222 PR middle-end/93843
10223 * optabs-tree.c (supportable_convert_operation): Reject types with
10224 scalar modes.
10226 2020-02-26 David Malcolm <dmalcolm@redhat.com>
10228 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
10230 2020-02-26 Jakub Jelinek <jakub@redhat.com>
10232 PR tree-optimization/93820
10233 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
10234 argument to ALL_INTEGER_CST_P boolean.
10235 (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
10236 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
10237 adjacent INTEGER_CST store into merged_store->only_constants like
10238 overlapping one.
10240 2020-02-25 Jakub Jelinek <jakub@redhat.com>
10242 PR other/93912
10243 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
10244 -> probability.
10245 * cfghooks.c (verify_flow_info): Likewise.
10246 * predict.c (combine_predictions_for_bb): Likewise.
10247 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
10248 sucessor -> successor.
10249 (find_traces_1_round): Fix comment typo, destinarion -> destination.
10250 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
10251 successors.
10252 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
10253 message typo, sucessors -> successors.
10255 2020-02-25 Martin Sebor <msebor@redhat.com>
10257 * doc/extend.texi (attribute access): Correct an example.
10259 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
10261 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
10262 Add simd_bf.
10263 (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
10264 (VAR15, VAR16): New.
10265 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
10266 (VD): Enable for V4BF.
10267 (VDC): Likewise.
10268 (VQ): Enable for V8BF.
10269 (VQ2): Likewise.
10270 (VQ_NO2E): Likewise.
10271 (VDBL, Vdbl): Add V4BF.
10272 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
10273 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
10274 (bfloat16x8x2_t): Likewise.
10275 (bfloat16x4x3_t): Likewise.
10276 (bfloat16x8x3_t): Likewise.
10277 (bfloat16x4x4_t): Likewise.
10278 (bfloat16x8x4_t): Likewise.
10279 (vcombine_bf16): New.
10280 (vld1_bf16, vld1_bf16_x2): New.
10281 (vld1_bf16_x3, vld1_bf16_x4): New.
10282 (vld1q_bf16, vld1q_bf16_x2): New.
10283 (vld1q_bf16_x3, vld1q_bf16_x4): New.
10284 (vld1_lane_bf16): New.
10285 (vld1q_lane_bf16): New.
10286 (vld1_dup_bf16): New.
10287 (vld1q_dup_bf16): New.
10288 (vld2_bf16): New.
10289 (vld2q_bf16): New.
10290 (vld2_dup_bf16): New.
10291 (vld2q_dup_bf16): New.
10292 (vld3_bf16): New.
10293 (vld3q_bf16): New.
10294 (vld3_dup_bf16): New.
10295 (vld3q_dup_bf16): New.
10296 (vld4_bf16): New.
10297 (vld4q_bf16): New.
10298 (vld4_dup_bf16): New.
10299 (vld4q_dup_bf16): New.
10300 (vst1_bf16, vst1_bf16_x2): New.
10301 (vst1_bf16_x3, vst1_bf16_x4): New.
10302 (vst1q_bf16, vst1q_bf16_x2): New.
10303 (vst1q_bf16_x3, vst1q_bf16_x4): New.
10304 (vst1_lane_bf16): New.
10305 (vst1q_lane_bf16): New.
10306 (vst2_bf16): New.
10307 (vst2q_bf16): New.
10308 (vst3_bf16): New.
10309 (vst3q_bf16): New.
10310 (vst4_bf16): New.
10311 (vst4q_bf16): New.
10313 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
10315 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
10316 (VALL_F16): Likewise.
10317 (VALLDI_F16): Likewise.
10318 (Vtype): Likewise.
10319 (Vetype): Likewise.
10320 (vswap_width_name): Likewise.
10321 (VSWAP_WIDTH): Likewise.
10322 (Vel): Likewise.
10323 (VEL): Likewise.
10324 (q): Likewise.
10325 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
10326 (vget_lane_bf16, vgetq_lane_bf16): New.
10327 (vcreate_bf16): New.
10328 (vdup_n_bf16, vdupq_n_bf16): New.
10329 (vdup_lane_bf16, vdup_laneq_bf16): New.
10330 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
10331 (vduph_lane_bf16, vduph_laneq_bf16): New.
10332 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
10333 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
10334 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
10335 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
10336 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
10337 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
10338 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
10339 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
10340 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
10341 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
10342 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
10343 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
10344 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
10345 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
10346 (vreinterpretq_bf16_p128): New.
10347 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
10348 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
10349 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
10350 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
10351 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
10352 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
10353 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
10354 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
10355 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
10356 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
10357 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
10358 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
10359 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
10360 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
10361 (vreinterpretq_p128_bf16): New.
10363 2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
10365 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
10366 (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
10367 (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
10368 * config/arm/arm_neon_builtins.def (vbfdot): New entry.
10369 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
10370 * config/arm/iterators.md (VSF2BF): New attribute.
10371 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
10372 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
10373 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
10375 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
10377 * config/arm/arm.md (required_for_purecode): New attribute.
10378 (enabled): Handle required_for_purecode.
10379 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
10380 work with -mpure-code.
10382 2020-02-25 Jakub Jelinek <jakub@redhat.com>
10384 PR rtl-optimization/93908
10385 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
10386 with mask.
10388 2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
10390 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
10392 2020-02-25 Roman Zhuykov <zhroma@ispras.ru>
10394 * doc/install.texi (--enable-checking): Adjust wording.
10396 2020-02-25 Richard Biener <rguenther@suse.de>
10398 PR tree-optimization/93868
10399 * tree-vect-slp.c (slp_copy_subtree): New function.
10400 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before
10401 re-arranging stmts in it.
10403 2020-02-25 Jakub Jelinek <jakub@redhat.com>
10405 PR middle-end/93874
10406 * passes.c (pass_manager::dump_passes): Create a cgraph node for the
10407 dummy function and remove it at the end.
10409 PR translation/93864
10410 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo
10411 paramter -> parameter.
10412 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise.
10413 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise.
10415 2020-02-24 Roman Zhuykov <zhroma@ispras.ru>
10417 * doc/install.texi (--enable-checking): Properly document current
10418 behavior.
10419 (--enable-stage1-checking): Minor clarification about bootstrap.
10421 2020-02-24 David Malcolm <dmalcolm@redhat.com>
10423 PR analyzer/93032
10424 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that
10425 -fanalyzer-checker=taint is also required.
10426 (-fanalyzer-checker=): Note that providing this option enables the
10427 given checker, and doing so may be required for checkers that are
10428 disabled by default.
10430 2020-02-24 David Malcolm <dmalcolm@redhat.com>
10432 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows
10433 significant control flow events; add a "3" which shows all
10434 control flow events; the old "3" becomes "4".
10436 2020-02-24 Jakub Jelinek <jakub@redhat.com>
10438 PR tree-optimization/93582
10439 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider
10440 pd.offset and pd.size to be counted in bits rather than bytes, add
10441 support for maxsizei that is not a multiple of BITS_PER_UNIT and
10442 handle bitfield stores and loads.
10443 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with
10444 uncomparable quantities - bytes vs. bits. Allow push_partial_def
10445 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust
10446 pd.offset/pd.size to be counted in bits rather than bytes.
10447 Formatting fix. Rename shadowed len variable to buflen.
10449 2020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
10450 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org>
10452 PR driver/47785
10453 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function.
10454 (driver::main): Call putenv_COLLECT_AS_OPTIONS.
10455 * opts-common.c (parse_options_from_collect_gcc_options): New function.
10456 (prepend_xassembler_to_collect_as_options): Likewise.
10457 * opts.h (parse_options_from_collect_gcc_options): Declare prototype.
10458 (prepend_xassembler_to_collect_as_options): Likewise.
10459 * lto-opts.c (lto_write_options): Stream assembler options
10460 in COLLECT_AS_OPTIONS.
10461 * lto-wrapper.c (xassembler_options_error): New static variable.
10462 (get_options_from_collect_gcc_options): Move parsing options code to
10463 parse_options_from_collect_gcc_options and call it.
10464 (merge_and_complain): Validate -Xassembler options.
10465 (append_compiler_options): Handle OPT_Xassembler.
10466 (run_gcc): Append command line -Xassembler options to
10467 collect_gcc_options.
10468 * doc/invoke.texi: Add documentation about using Xassembler
10469 options with LTO.
10471 2020-02-24 Kito Cheng <kito.cheng@sifive.com>
10473 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen
10474 for LTGT.
10475 (riscv_rtx_costs): Update cost model for LTGT.
10477 2020-02-23 Vladimir Makarov <vmakarov@redhat.com>
10479 PR rtl-optimization/93564
10480 * ira-color.c (struct update_cost_queue_elem): New member start.
10481 (queue_update_cost, get_next_update_cost): Add new arg start.
10482 (allocnos_conflict_p): New function.
10483 (update_costs_from_allocno): Add new arg conflict_cost_update_p.
10484 Add checking conflicts with allocnos_conflict_p.
10485 (update_costs_from_prefs, restore_costs_from_copies): Adjust
10486 update_costs_from_allocno calls.
10487 (update_conflict_hard_regno_costs): Add checking conflicts with
10488 allocnos_conflict_p. Adjust calls of queue_update_cost and
10489 get_next_update_cost.
10490 (assign_hard_reg): Adjust calls of queue_update_cost. Add
10491 debugging print.
10492 (bucket_allocno_compare_func): Restore previous version.
10494 2020-02-21 John David Anglin <danglin@gcc.gnu.org>
10496 * gcc/config/pa/pa.c (pa_function_value): Fix check for word and
10497 double-word size when handling aggregate return values.
10498 * gcc/config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate
10499 that homogeneous SFmode and DFmode aggregates are passed and returned
10500 in general registers.
10502 2020-02-21 Jakub Jelinek <jakub@redhat.com>
10504 PR translation/93759
10505 * opts.c (print_filtered_help): Translate help before appending
10506 messages to it rather than after that.
10508 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
10510 PR rtl-optimization/PR92989
10511 * lra-lives.c (process_bb_lives): Restore the original order
10512 of the bb liveness update. Call make_hard_regno_dead for each
10513 register clobbered at the start of an EH receiver.
10515 2020-02-18 Feng Xue <fxue@os.amperecomputing.com>
10517 PR ipa/93763
10518 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as
10519 self-recursively generated.
10521 2020-02-21 Iain Sandoe <iain@sandoe.co.uk>
10523 PR target/93860
10524 * config/darwin-c.c (pop_field_alignment): Adjust quoting of
10525 error string.
10527 2020-02-21 Mihail Ionescu <mihail.ionescu@arm.com>
10529 * doc/sourcebuild.texi (arm_v8_1m_mve_ok):
10530 Document new target supports option.
10532 2020-02-21 Dennis Zhang <dennis.zhang@arm.com>
10534 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New.
10535 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New.
10536 * config/arm/iterators.md (MATMUL): New iterator.
10537 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US.
10538 (mmla_sfx): New attribute.
10539 * config/arm/neon.md (neon_<sup>mmlav16qi): New.
10540 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New.
10541 (UNSPEC_MATMUL_US): New.
10543 2020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
10545 * config/arm/arm.md: Prevent scalar shifts from being used when big
10546 endian is enabled.
10548 2020-02-21 Jan Hubicka <hubicka@ucw.cz>
10549 Richard Biener <rguenther@suse.de>
10551 PR tree-optimization/93586
10552 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk
10553 after mismatched array refs; do not sure type size information to
10554 recover from unmatched referneces with !flag_strict_aliasing_p.
10556 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
10558 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
10559 (gather_load<mode>v64si): ... this and set operand 2 to V64SI.
10560 (scatter_store<mode>): Rename to ...
10561 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
10562 (scatter<mode>_exec): Delete. Move contents ...
10563 (mask_scatter_store<mode>): ... here, and rename that to ...
10564 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
10565 Remove mode conversion.
10566 (mask_gather_load<mode>): Rename to ...
10567 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
10568 Remove mode conversion.
10569 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
10571 2020-02-21 Martin Jambor <mjambor@suse.cz>
10573 PR tree-optimization/93845
10574 * tree-sra.c (verify_sra_access_forest): Only test access size of
10575 scalar types.
10577 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
10579 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
10580 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
10581 (addv64di3_exec): Likewise.
10582 (subv64di3): Likewise.
10583 (subv64di3_exec): Likewise.
10584 (addv64di3_zext): Likewise.
10585 (addv64di3_zext_exec): Likewise.
10586 (addv64di3_zext_dup): Likewise.
10587 (addv64di3_zext_dup_exec): Likewise.
10588 (addv64di3_zext_dup2): Likewise.
10589 (addv64di3_zext_dup2_exec): Likewise.
10590 (addv64di3_sext_dup2): Likewise.
10591 (addv64di3_sext_dup2_exec): Likewise.
10592 (<expander>v64di3): Likewise.
10593 (<expander>v64di3_exec): Likewise.
10594 (*<reduc_op>_dpp_shr_v64di): Likewise.
10595 (*plus_carry_dpp_shr_v64di): Likewise.
10596 * config/gcn/gcn.md (adddi3): Likewise.
10597 (addptrdi3): Likewise.
10598 (<expander>di3): Likewise.
10600 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
10602 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
10604 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10606 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
10607 support. Use aarch64_emit_mult instead of emitting multiplication
10608 instructions directly.
10609 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2)
10610 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders.
10612 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10614 * config/aarch64/aarch64.c (aarch64_emit_mult): New function.
10615 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult
10616 instead of emitting multiplication instructions directly.
10617 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator.
10618 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>)
10619 (@aarch64_frecps<mode>): New expanders.
10621 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10623 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate
10624 on and produce uint64_ts rather than ints.
10625 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts.
10626 (cpu_approx_modes): Change the fields from unsigned int to uint64_t.
10628 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10630 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create
10631 an unused xmsk register when handling approximate rsqrt.
10633 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
10635 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted
10636 flag_finite_math_only condition.
10638 2020-02-20 Uroš Bizjak <ubizjak@gmail.com>
10640 PR target/93828
10641 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand
10642 to destination operand for shufps alternative.
10643 (*vec_extractv2si_1): Ditto.
10645 2020-02-20 Peter Bergner <bergner@linux.ibm.com>
10647 PR target/93658
10648 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
10649 vector modes.
10651 2020-02-20 Martin Liska <mliska@suse.cz>
10653 PR translation/93831
10654 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode.
10656 2020-02-20 Martin Liska <mliska@suse.cz>
10658 PR translation/93830
10659 * common/config/avr/avr-common.c: Remote trailing "|".
10661 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
10663 * collect2.c (maybe_run_lto_and_relink): Fix typo in
10664 comment.
10666 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
10668 PR tree-optimization/93767
10669 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the
10670 access-size bias from the offset calculations for negative strides.
10672 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
10674 * collect2.c (c_file, o_file): Make const again.
10675 (ldout,lderrout, dump_ld_file): Remove.
10676 (tool_cleanup): Avoid calling not signal-safe functions.
10677 (maybe_run_lto_and_relink): Avoid possible signal handler
10678 access to unintialzed memory (lto_o_files).
10679 (main): Avoid leaking temp files in $TMPDIR.
10680 Initialize c_file/o_file with concat, which avoids exposing
10681 uninitialized memory to signal handler, which calls unlink(!).
10682 Avoid calling maybe_unlink when the main function returns,
10683 since the atexit handler is already doing this.
10684 * collect2.h (dump_ld_file, ldout, lderrout): Remove.
10686 2020-02-19 Martin Jambor <mjambor@suse.cz>
10688 PR tree-optimization/93776
10689 * tree-sra.c (create_access): Do not create zero size accesses.
10690 (get_access_for_expr): Do not search for zero sized accesses.
10692 2020-02-19 Martin Jambor <mjambor@suse.cz>
10694 PR tree-optimization/93667
10695 * tree-sra.c (scalarizable_type_p): Return false if record fields
10696 do not follow wach other.
10698 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
10700 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
10701 rather than fmv.x.s/fmv.s.x.
10703 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
10705 * config/aarch64/aarch64-simd-builtins.def
10706 (intrinsic_vec_smult_lo_): New.
10707 (intrinsic_vec_umult_lo_): Likewise.
10708 (vec_widen_smult_hi_): Likewise.
10709 (vec_widen_umult_hi_): Likewise.
10710 * config/aarch64/aarch64-simd.md
10711 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New.
10712 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics.
10713 (vmull_high_s16): Likewise.
10714 (vmull_high_s32): Likewise.
10715 (vmull_high_u8): Likewise.
10716 (vmull_high_u16): Likewise.
10717 (vmull_high_u32): Likewise.
10718 (vmull_s8): Likewise.
10719 (vmull_s16): Likewise.
10720 (vmull_s32): Likewise.
10721 (vmull_u8): Likewise.
10722 (vmull_u16): Likewise.
10723 (vmull_u32): Likewise.
10725 2020-02-18 Martin Liska <mliska@suse.cz>
10727 * value-prof.c (stream_out_histogram_value): Restore LTO PGO
10728 bootstrap by missing removal of invalid sanity check.
10730 2020-02-18 Martin Liska <mliska@suse.cz>
10732 PR ipa/92518
10733 * ipa-icf-gimple.c (func_checker::compare_gimple_assign):
10734 Always compare LHS of gimple_assign.
10736 2020-02-18 Martin Liska <mliska@suse.cz>
10738 PR ipa/93583
10739 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute
10740 and return type of functions.
10741 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl):
10742 Drop MALLOC attribute for void functions.
10743 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop
10744 malloc_state for a new VOID clone.
10746 2020-02-18 Martin Liska <mliska@suse.cz>
10748 PR ipa/92924
10749 * common.opt: Add -fprofile-reproducibility.
10750 * doc/invoke.texi: Document it.
10751 * value-prof.c (dump_histogram_value):
10752 Document and support behavior for counters[0]
10753 being a negative value.
10754 (get_nth_most_common_value): Handle negative
10755 counters[0] in respect to flag_profile_reproducible.
10757 2020-02-18 Jakub Jelinek <jakub@redhat.com>
10759 PR ipa/93797
10760 * cgraph.c (verify_speculative_call): Use speculative_id instead of
10761 speculative_uid in messages. Remove trailing whitespace from error
10762 message. Use num_speculative_call_targets instead of
10763 num_speculative_targets in a message.
10764 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in
10765 edge messages and stmt instead of cal_stmt in reference message.
10767 PR tree-optimization/93780
10768 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p
10769 before calling build_vector_type.
10770 (execute_update_addresses_taken): Likewise.
10772 PR driver/93796
10773 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help
10774 typo, functoin -> function.
10775 * tree.c (free_lang_data_in_decl): Fix comment typo,
10776 functoin -> function.
10777 * ipa-visibility.c (cgraph_externally_visible_p): Likewise.
10779 2020-02-17 David Malcolm <dmalcolm@redhat.com>
10781 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs
10782 won't be printed.
10783 (print_option_information): Don't call get_option_url if URLs
10784 won't be printed.
10786 2020-02-17 Alexandre Oliva <oliva@adacore.com>
10788 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete
10789 handling of register_common-less targets.
10791 2020-02-17 Martin Liska <mliska@suse.cz>
10793 PR ipa/93760
10794 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar.
10796 2020-02-17 Martin Liska <mliska@suse.cz>
10798 PR translation/93755
10799 * config/rs6000/rs6000.c (rs6000_option_override_internal):
10800 Fix double quotes.
10802 2020-02-17 Martin Liska <mliska@suse.cz>
10804 PR other/93756
10805 * config/rx/elf.opt: Fix typo.
10807 2020-02-17 Richard Biener <rguenther@suse.de>
10809 PR c/86134
10810 * opts-global.c (print_ignored_options): Use inform and
10811 amend message.
10813 2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
10815 PR target/93047
10816 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
10818 2020-02-16 Uroš Bizjak <ubizjak@gmail.com>
10820 PR target/93743
10821 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2.
10822 (atan2<mode>3): Update operand order in the call to gen_atan2xf3.
10824 2020-02-15 Jason Merrill <jason@redhat.com>
10826 * doc/invoke.texi (C Dialect Options): Add -std=c++20.
10828 2020-02-15 Jakub Jelinek <jakub@redhat.com>
10830 PR tree-optimization/93744
10831 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0,
10832 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A,
10833 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make
10834 sure @2 in the first and @1 in the other patterns has no side-effects.
10836 2020-02-15 David Malcolm <dmalcolm@redhat.com>
10837 Bernd Edlinger <bernd.edlinger@hotmail.de>
10839 PR 87488
10840 PR other/93168
10841 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
10842 * configure.ac (--with-diagnostics-urls): New configuration
10843 option, based on --with-diagnostics-color.
10844 (DIAGNOSTICS_URLS_DEFAULT): New define.
10845 * config.h: Regenerate.
10846 * configure: Regenerate.
10847 * diagnostic.c (diagnostic_urls_init): Handle -1 for
10848 DIAGNOSTICS_URLS_DEFAULT from configure-time
10849 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
10850 and TERM_URLS environment variable.
10851 * diagnostic-url.h (diagnostic_url_format): New enum type.
10852 (diagnostic_urls_enabled_p): rename to...
10853 (determine_url_format): ... this, and change return type.
10854 * diagnostic-color.c (parse_env_vars_for_urls): New helper function.
10855 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
10856 the linux console, and mingw.
10857 (diagnostic_urls_enabled_p): rename to...
10858 (determine_url_format): ... this, and adjust.
10859 * pretty-print.h (pretty_printer::show_urls): rename to...
10860 (pretty_printer::url_format): ... this, and change to enum.
10861 * pretty-print.c (pretty_printer::pretty_printer,
10862 pp_begin_url, pp_end_url, test_urls): Adjust.
10863 * doc/install.texi (--with-diagnostics-urls): Document the new
10864 configuration option.
10865 (--with-diagnostics-color): Document the existing interaction
10866 with GCC_COLORS better.
10867 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
10868 vindex reference. Update description of defaults based on the above.
10869 (-fdiagnostics-color): Update description of how -fdiagnostics-color
10870 interacts with GCC_COLORS.
10872 2020-02-14 Eric Botcazou <ebotcazou@adacore.com>
10874 PR target/93704
10875 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in
10876 conjunction with TARGET_GNU_TLS in early return.
10878 2020-02-14 Alexander Monakov <amonakov@ispras.ru>
10880 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if
10881 the mode is not wider than UNITS_PER_WORD.
10883 2020-02-14 Martin Jambor <mjambor@suse.cz>
10885 PR tree-optimization/93516
10886 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create
10887 access of the same type as the parent.
10888 (propagate_subaccesses_from_lhs): Likewise.
10890 2020-02-14 Hongtao Liu <hongtao.liu@intel.com>
10892 PR target/93724
10893 * config/i386/avx512vbmi2intrin.h
10894 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16,
10895 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32,
10896 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
10897 _m512_shrdi_epi64, _m512_mask_shrdi_epi64,
10898 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16,
10899 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16,
10900 _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
10901 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
10902 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo
10903 of lacking a closing parenthesis.
10904 * config/i386/avx512vbmi2vlintrin.h
10905 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16,
10906 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32,
10907 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32,
10908 _m256_shrdi_epi64, _m256_mask_shrdi_epi64,
10909 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16,
10910 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
10911 _mm256_shldi_epi32, _mm256_mask_shldi_epi32,
10912 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64,
10913 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64,
10914 _mm_shrdi_epi16, _mm_mask_shrdi_epi16,
10915 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32,
10916 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32,
10917 _mm_shrdi_epi64, _mm_mask_shrdi_epi64,
10918 _m_maskz_shrdi_epi64, _mm_shldi_epi16,
10919 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16,
10920 _mm_shldi_epi32, _mm_mask_shldi_epi32,
10921 _mm_maskz_shldi_epi32, _mm_shldi_epi64,
10922 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto.
10924 2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
10926 PR target/93656
10927 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
10928 the target function entry.
10930 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
10932 * common/config/arc/arc-common.c (arc_option_optimization_table):
10933 Disable if-conversion step when optimized for size.
10935 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
10937 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
10938 R12-R15 are always in ARCOMPACT16_REGS register class.
10939 * config/arc/arc.opt (mq-class): Deprecate.
10940 * config/arc/constraint.md ("q"): Remove dependency on mq-class
10941 option.
10942 * doc/invoke.texi (mq-class): Update text.
10943 * common/config/arc/arc-common.c (arc_option_optimization_table):
10944 Update list.
10946 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
10948 * config/arc/arc.c (arc_insn_cost): New function.
10949 (TARGET_INSN_COST): Define.
10950 * config/arc/arc.md (cost): New attribute.
10951 (add_n): Use arc_nonmemory_operand.
10952 (ashlsi3_insn): Likewise, also update constraints.
10953 (ashrsi3_insn): Likewise.
10954 (rotrsi3): Likewise.
10955 (add_shift): Likewise.
10956 * config/arc/predicates.md (arc_nonmemory_operand): New predicate.
10958 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
10960 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
10961 registers.
10962 (umulsidi_600): Likewise.
10964 2020-02-13 Jakub Jelinek <jakub@redhat.com>
10966 PR target/93696
10967 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8,
10968 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8,
10969 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8,
10970 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W,
10971 pass __A to the builtin followed by __W instead of __A followed by
10972 __B.
10973 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32,
10974 _mm512_mask_popcnt_epi64): Likewise.
10975 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32,
10976 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64,
10977 _mm256_mask_popcnt_epi64): Likewise.
10979 PR tree-optimization/93582
10980 * fold-const.h (shift_bytes_in_array_left,
10981 shift_bytes_in_array_right): Declare.
10982 * fold-const.c (shift_bytes_in_array_left,
10983 shift_bytes_in_array_right): New function, moved from
10984 gimple-ssa-store-merging.c, no longer static.
10985 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move
10986 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left.
10987 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c.
10988 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of
10989 shift_bytes_in_array.
10990 (verify_shift_bytes_in_array): Rename to ...
10991 (verify_shift_bytes_in_array_left): ... this. Use
10992 shift_bytes_in_array_left instead of shift_bytes_in_array.
10993 (store_merging_c_tests): Call verify_shift_bytes_in_array_left
10994 instead of verify_shift_bytes_in_array.
10995 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr
10996 / native_interpret_expr where the store covers all needed bits,
10997 punt on PDP-endian, otherwise allow all involved offsets and sizes
10998 not to be byte-aligned.
11000 PR target/93673
11001 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and
11002 use const_0_to_255_operand predicate instead of immediate_operand.
11003 (avx512dq_fpclass<mode><mask_scalar_merge_name>,
11004 avx512dq_vmfpclass<mode><mask_scalar_merge_name>,
11005 vgf2p8affineinvqb_<mode><mask_name>,
11006 vgf2p8affineqb_<mode><mask_name>): Drop mode from
11007 const_0_to_255_operand predicated operands.
11009 2020-02-12 Jeff Law <law@redhat.com>
11011 * config/h8300/h8300.md (comparison shortening peepholes): Use
11012 a mode iterator to merge the HImode and SImode peepholes.
11014 2020-02-12 Jakub Jelinek <jakub@redhat.com>
11016 PR middle-end/93663
11017 * real.c (is_even): Make static. Function comment fix.
11018 (is_halfway_below): Make static, don't assert R is not inf/nan,
11019 instead return false for those. Small formatting fixes.
11021 2020-02-12 Martin Sebor <msebor@redhat.com>
11023 PR middle-end/93646
11024 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename...
11025 (handle_builtin_stxncpy_strncat): ...to this. Change first argument.
11026 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation.
11027 (strlen_check_and_optimize_call): Adjust callee name.
11029 2020-02-12 Jeff Law <law@redhat.com>
11031 * config/h8300/h8300.md (comparison shortening peepholes): Drop
11032 (and (xor)) variant. Combine other two into single peephole.
11034 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
11036 PR rtl-optimization/93565
11037 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs.
11039 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
11041 * config/aarch64/aarch64-simd.md
11042 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
11043 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
11044 generating separate ADDV and zero_extend patterns.
11045 * config/aarch64/iterators.md (VDQV_E): New iterator.
11047 2020-02-12 Jeff Law <law@redhat.com>
11049 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,
11050 expanders, splits, etc.
11051 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise.
11052 (stpcpy_internal_<mode>, stpcpy splitter): Likewise.
11053 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise.
11054 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function.
11055 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise
11056 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused
11057 function prototype.
11058 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
11060 2020-02-12 Jakub Jelinek <jakub@redhat.com>
11062 PR target/93670
11063 * config/i386/sse.md (VI48F_256_DQ): New mode iterator.
11064 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove
11065 TARGET_AVX512DQ from condition.
11066 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition>
11067 instead of <mask_mode512bit_condition> in condition. If
11068 TARGET_AVX512DQ is false, emit vextract*64x4 instead of
11069 vextract*32x8.
11070 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition>
11071 from condition.
11073 2020-02-12 Kewen Lin <linkw@gcc.gnu.org>
11075 PR target/91052
11076 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
11078 2020-02-12 Segher Boessenkool <segher@kernel.crashing.org>
11080 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof
11081 where strlen is more legible.
11082 (rs6000_builtin_vectorized_libmass): Ditto.
11083 (rs6000_print_options_internal): Ditto.
11085 2020-02-11 Martin Sebor <msebor@redhat.com>
11087 PR tree-optimization/93683
11088 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
11090 2020-02-11 Michael Meissner <meissner@linux.ibm.com>
11092 * config/rs6000/predicates.md (cint34_operand): Rename the
11093 -mprefixed-addr option to be -mprefixed.
11094 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
11095 the -mprefixed-addr option to be -mprefixed.
11096 (OTHER_FUTURE_MASKS): Likewise.
11097 (POWERPC_MASKS): Likewise.
11098 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
11099 the -mprefixed-addr option to be -mprefixed. Change error
11100 messages to refer to -mprefixed.
11101 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be
11102 -mprefixed.
11103 (rs6000_legitimate_offset_address_p): Likewise.
11104 (rs6000_mode_dependent_address): Likewise.
11105 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
11106 "-mprefixed" for target attributes and pragmas.
11107 (address_to_insn_form): Rename the -mprefixed-addr option to be
11108 -mprefixed.
11109 (rs6000_adjust_insn_length): Likewise.
11110 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
11111 -mprefixed-addr option to be -mprefixed.
11112 (ASM_OUTPUT_OPCODE): Likewise.
11113 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the
11114 -mprefixed-addr option to be -mprefixed.
11115 * config/rs6000/rs6000.opt (-mprefixed): Rename the
11116 -mprefixed-addr option to be prefixed. Change the option from
11117 being undocumented to being documented.
11118 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the
11119 -mprefixed option. Update the -mpcrel documentation to mention
11120 -mprefixed.
11122 2020-02-11 Hans-Peter Nilsson <hp@axis.com>
11124 * ira-conflicts.c (print_hard_reg_set): Correct output for sets
11125 including FIRST_PSEUDO_REGISTER - 1.
11126 * ira-color.c (print_hard_reg_set): Ditto.
11128 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
11130 * config/arm/arm-builtins.c (enum arm_type_qualifiers):
11131 (USTERNOP_QUALIFIERS): New define.
11132 (USMAC_LANE_QUADTUP_QUALIFIERS): New define.
11133 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
11134 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
11135 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
11136 * config/arm/arm_neon.h (vusdot_s32): New.
11137 (vusdot_lane_s32): New.
11138 (vusdotq_lane_s32): New.
11139 (vsudot_lane_s32): New.
11140 (vsudotq_lane_s32): New.
11141 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
11142 * config/arm/iterators.md (DOTPROD_I8MM): New.
11143 (sup, opsuffix): Add <us/su>.
11144 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
11145 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
11147 2020-02-11 Richard Biener <rguenther@suse.de>
11149 PR tree-optimization/93661
11150 PR tree-optimization/93662
11151 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard
11152 tree_to_poly_int64.
11153 * tree-sra.c (get_access_for_expr): Likewise.
11155 2020-02-10 Jakub Jelinek <jakub@redhat.com>
11157 PR target/93637
11158 * config/i386/sse.md (VI_256_AVX2): New mode iterator.
11159 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256.
11160 Change condition from TARGET_AVX2 to TARGET_AVX.
11162 2020-02-10 Iain Sandoe <iain@sandoe.co.uk>
11164 PR other/93641
11165 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last
11166 argument of strncmp.
11168 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
11170 Try to generate zero-based comparisons.
11171 * config/cris/cris.c (cris_reduce_compare): New function.
11172 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype.
11173 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4")
11174 (cstore<mode>4"): Apply cris_reduce_compare in expanders.
11176 2020-02-10 Richard Earnshaw <rearnsha@arm.com>
11178 PR target/91913
11179 * config/arm/arm.md (movsi_compare0): Allow SP as a source register
11180 in Thumb state and also as a destination in Arm state. Add T16
11181 variants.
11183 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
11185 * md.texi (Define Subst): Match closing paren in example.
11187 2020-02-10 Jakub Jelinek <jakub@redhat.com>
11189 PR target/58218
11190 PR other/93641
11191 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last
11192 arguments of strncmp.
11194 2020-02-10 Feng Xue <fxue@os.amperecomputing.com>
11196 PR ipa/93203
11197 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge
11198 but different source value.
11199 (adjust_callers_for_value_intersection): New function.
11200 (gather_edges_for_value): Adjust order of callers to let a
11201 non-self-recursive caller be the first element.
11202 (self_recursive_pass_through_p): Add a new parameter "simple", and
11203 check generalized self-recursive pass-through jump function.
11204 (self_recursive_agg_pass_through_p): Likewise.
11205 (find_more_scalar_values_for_callers_subset): Compute value from
11206 pass-through jump function for self-recursive.
11207 (intersect_with_plats): Cleanup previous implementation code for value
11208 itersection with self-recursive call edge.
11209 (intersect_with_agg_replacements): Likewise.
11210 (intersect_aggregates_with_edge): Deduce value from pass-through jump
11211 function for self-recursive call edge. Cleanup previous implementation
11212 code for value intersection with self-recursive call edge.
11213 (decide_whether_version_node): Remove dead callers and adjust order
11214 to let a non-self-recursive caller be the first element.
11216 2020-02-09 Uroš Bizjak <ubizjak@gmail.com>
11218 * recog.c: Move pass_split_before_sched2 code in front of
11219 pass_split_before_regstack.
11220 (pass_data_split_before_sched2): Rename pass to split3 from split4.
11221 (pass_data_split_before_regstack): Rename pass to split4 from split3.
11222 (rest_of_handle_split_before_sched2): Remove.
11223 (pass_split_before_sched2::execute): Unconditionally call
11224 split_all_insns.
11225 (enable_split_before_sched2): New function.
11226 (pass_split_before_sched2::gate): Use enable_split_before_sched2.
11227 (pass_split_before_regstack::gate): Ditto.
11228 * config/nds32/nds32.c (nds32_split_double_word_load_store_p):
11229 Update name check for renamed split4 pass.
11230 * config/sh/sh.c (register_sh_passes): Update pass insertion
11231 point for renamed split4 pass.
11233 2020-02-09 Jakub Jelinek <jakub@redhat.com>
11235 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote
11236 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid
11237 copying them around between host and target.
11239 2020-02-08 Andrew Pinski <apinski@marvell.com>
11241 PR target/91927
11242 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
11243 STRICT_ALIGNMENT also.
11245 2020-02-08 Jim Wilson <jimw@sifive.com>
11247 PR target/93532
11248 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
11250 2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
11251 Jakub Jelinek <jakub@redhat.com>
11253 PR target/65782
11254 * config/i386/i386.h (CALL_USED_REGISTERS): Make
11255 xmm16-xmm31 call-used even in 64-bit ms-abi.
11257 2020-02-07 Dennis Zhang <dennis.zhang@arm.com>
11259 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry.
11260 (simd_ummla, simd_usmmla): Likewise.
11261 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New.
11262 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New.
11263 (vusmmlaq_s32): New.
11265 2020-02-07 Richard Biener <rguenther@suse.de>
11267 PR middle-end/93519
11268 * tree-inline.c (fold_marked_statements): Do a PRE walk,
11269 skipping unreachable regions.
11270 (optimize_inline_calls): Skip folding stmts when we didn't
11271 inline.
11273 2020-02-07 H.J. Lu <hongjiu.lu@intel.com>
11275 PR target/85667
11276 * config/i386/i386.c (function_arg_ms_64): Add a type argument.
11277 Don't return aggregates with only SFmode and DFmode in SSE
11278 register.
11279 (ix86_function_arg): Pass arg.type to function_arg_ms_64.
11281 2020-02-07 Jakub Jelinek <jakub@redhat.com>
11283 PR target/93122
11284 * config/rs6000/rs6000-logue.c
11285 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn,
11286 if it fails, move rs into end_addr and retry. Add
11287 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or
11288 the insn pattern doesn't describe well what exactly happens to
11289 dwarf2cfi.c.
11291 PR target/93594
11292 * config/i386/predicates.md (avx_identity_operand): Remove.
11293 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove.
11294 (avx_<castmode><avxsizesuffix>_<castmode>,
11295 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to
11296 a VEC_CONCAT of the operand and UNSPEC_CAST.
11297 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to
11298 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with
11299 UNSPEC_CAST.
11301 PR target/93611
11302 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear
11303 recog_data.insn if distance_non_agu_define changed it.
11305 2020-02-06 Michael Meissner <meissner@linux.ibm.com>
11307 PR target/93569
11308 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
11309 we only had X-FORM (reg+reg) addressing for vectors. Also before
11310 ISA 3.0, we only had X-FORM addressing for scalars in the
11311 traditional Altivec registers.
11313 2020-02-06 <zhongyunde@huawei.com>
11314 Vladimir Makarov <vmakarov@redhat.com>
11316 PR rtl-optimization/93561
11317 * lra-assigns.c (spill_for): Check that tested hard regno is not out of
11318 hard register range.
11320 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
11322 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type
11323 attribute.
11325 2020-02-06 Segher Boessenkool <segher@kernel.crashing.org>
11327 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case
11328 where the low and the high 32 bits are equal to each other specially,
11329 with an rldimi instruction.
11331 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
11333 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main.
11335 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
11337 * config/arm/arm-tables.opt: Regenerate.
11339 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
11341 PR target/87763
11342 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
11343 * config/aarch64/aarch64.c (aarch64_movk_shift): New function.
11344 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
11346 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
11348 PR rtl-optimization/87763
11349 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
11351 2020-02-06 Delia Burduv <delia.burduv@arm.com>
11353 * config/aarch64/aarch64-simd-builtins.def
11354 (bfmlaq): New built-in function.
11355 (bfmlalb): New built-in function.
11356 (bfmlalt): New built-in function.
11357 (bfmlalb_lane): New built-in function.
11358 (bfmlalt_lane): New built-in function.
11359 * config/aarch64/aarch64-simd.md
11360 (aarch64_bfmmlaqv4sf): New pattern.
11361 (aarch64_bfmlal<bt>v4sf): New pattern.
11362 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern.
11363 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic.
11364 (vbfmlalbq_f32): New intrinsic.
11365 (vbfmlaltq_f32): New intrinsic.
11366 (vbfmlalbq_lane_f32): New intrinsic.
11367 (vbfmlaltq_lane_f32): New intrinsic.
11368 (vbfmlalbq_laneq_f32): New intrinsic.
11369 (vbfmlaltq_laneq_f32): New intrinsic.
11370 * config/aarch64/iterators.md (BF_MLA): New int iterator.
11371 (bt): New int attribute.
11373 2020-02-06 Uroš Bizjak <ubizjak@gmail.com>
11375 * config/i386/i386.md (*pushtf): Emit "#" instead of
11376 calling gcc_unreachable in insn output.
11377 (*pushxf): Ditto.
11378 (*pushdf): Ditto.
11379 (*pushsf_rex64): Ditto for alternatives other than 1.
11380 (*pushsf): Ditto for alternatives other than 1.
11382 2020-02-06 Martin Liska <mliska@suse.cz>
11384 PR gcov-profile/91971
11385 PR gcov-profile/93466
11386 * coverage.c (coverage_init): Revert mangling of
11387 path into filename. It can lead to huge filename length.
11388 Creation of subfolders seem more natural.
11390 2020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com>
11392 PR target/93300
11393 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New.
11394 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs.
11395 Use arm_block_arith_comp_libfuncs_for_mode for HFmode.
11397 2020-02-06 Jakub Jelinek <jakub@redhat.com>
11399 PR target/93594
11400 * config/i386/predicates.md (avx_identity_operand): New predicate.
11401 * config/i386/sse.md (*avx_vec_concat<mode>_1): New
11402 define_insn_and_split.
11404 PR libgomp/93515
11405 * omp-low.c (use_pointer_for_field): For nested constructs, also
11406 look for map clauses on target construct.
11407 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily
11408 taskreg_nesting_level.
11410 PR libgomp/93515
11411 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding
11412 shared clause, call omp_notice_variable on outer context if any.
11414 2020-02-05 Jason Merrill <jason@redhat.com>
11416 PR c++/92003
11417 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has
11418 non-zero address even if weak and not yet defined.
11420 2020-02-05 Martin Sebor <msebor@redhat.com>
11422 PR tree-optimization/92765
11423 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL.
11424 * tree-ssa-strlen.c (compute_string_length): Remove.
11425 (determine_min_objsize): Remove.
11426 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic.
11427 Avoid using type size as the upper bound on string length.
11428 (handle_builtin_string_cmp): Add an argument. Adjust.
11429 (strlen_check_and_optimize_call): Pass additional argument to
11430 handle_builtin_string_cmp.
11432 2020-02-05 Uroš Bizjak <ubizjak@gmail.com>
11434 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove.
11435 (*pushdi2_rex64 peephole2): Unconditionally split after
11436 epilogue_completed.
11437 (*ashl<mode>3_doubleword): Ditto.
11438 (*<shift_insn><mode>3_doubleword): Ditto.
11440 2020-02-05 Michael Meissner <meissner@linux.ibm.com>
11442 PR target/93568
11443 * config/rs6000/rs6000.c (get_vector_offset): Fix
11445 2020-02-05 Andrew Stubbs <ams@codesourcery.com>
11447 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
11449 2020-02-05 David Malcolm <dmalcolm@redhat.com>
11451 * doc/analyzer.texi
11452 (Special Functions for Debugging the Analyzer): Update description
11453 of __analyzer_dump_exploded_nodes.
11455 2020-02-05 Jakub Jelinek <jakub@redhat.com>
11457 PR target/92190
11458 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
11459 include sets and not clobbers in the vzeroupper pattern.
11460 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
11461 the parallel has 17 (64-bit) or 9 (32-bit) elts.
11462 (*avx_vzeroupper_1): New define_insn_and_split.
11464 PR target/92190
11465 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets,
11466 don't run when !optimize.
11467 (pass_split_before_regstack::gate): For STACK_REGS targets, run even
11468 when !optimize.
11470 2020-02-05 Richard Biener <rguenther@suse.de>
11472 PR middle-end/90648
11473 * genmatch.c (dt_node::gen_kids_1): Emit number of argument
11474 checks before matching calls.
11476 2020-02-05 Jakub Jelinek <jakub@redhat.com>
11478 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up
11479 function comment typo.
11481 PR middle-end/93555
11482 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or
11483 simd_clone_create failed when i == 0, adjust clone->nargs by
11484 clone->inbranch.
11486 2020-02-05 Martin Liska <mliska@suse.cz>
11488 PR c++/92717
11489 * doc/invoke.texi: Document that one should
11490 not combine ASLR and -fpch.
11492 2020-02-04 Richard Biener <rguenther@suse.de>
11494 PR tree-optimization/93538
11495 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr.
11497 2020-02-04 Richard Biener <rguenther@suse.de>
11499 PR tree-optimization/91123
11500 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
11501 (vn_walk_cb_data::last_vuse): New member.
11502 (vn_walk_cb_data::saved_operands): Likewsie.
11503 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
11504 (vn_walk_cb_data::push_partial_def): Use finish.
11505 (vn_reference_lookup_2): Update last_vuse and use finish if
11506 we've saved operands.
11507 (vn_reference_lookup_3): Use finish and update calls to
11508 push_partial_defs everywhere. When translating through
11509 memcpy or aggregate copies save off operands and alias-set.
11510 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
11511 operation for redundant store removal.
11513 2020-02-04 Richard Biener <rguenther@suse.de>
11515 PR tree-optimization/92819
11516 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
11517 generating more stmts than before.
11519 2020-02-04 Martin Liska <mliska@suse.cz>
11521 * config/arm/arm.c (arm_gen_far_branch): Move the function
11522 outside of selftests.
11524 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
11526 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
11527 function to adjust PC-relative vector addresses.
11528 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
11529 handle vectors with PC-relative addresses.
11531 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
11533 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
11534 reference.
11535 (hard_reg_and_mode_to_addr_mask): Delete.
11536 (rs6000_adjust_vec_address): If the original vector address
11537 was REG+REG or REG+OFFSET and the element is not zero, do the add
11538 of the elements in the original address before adding the offset
11539 for the vector element. Use address_to_insn_form to validate the
11540 address using the register being loaded, rather than guessing
11541 whether the address is a DS-FORM or DQ-FORM address.
11543 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
11545 * config/rs6000/rs6000.c (get_vector_offset): New helper function
11546 to calculate the offset in memory from the start of a vector of a
11547 particular element. Add code to keep the element number in
11548 bounds if the element number is variable.
11549 (rs6000_adjust_vec_address): Move calculation of offset of the
11550 vector element to get_vector_offset.
11551 (rs6000_split_vec_extract_var): Do not do the initial AND of
11552 element here, move the code to get_vector_offset.
11554 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
11556 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
11557 gcc_asserts.
11559 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
11561 * config/rs6000/constraints.md: Improve documentation.
11563 2020-02-03 Richard Earnshaw <rearnsha@arm.com>
11565 PR target/93548
11566 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md)
11567 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
11569 2020-02-03 Andrew Stubbs <ams@codesourcery.com>
11571 * config.gcc: Remove "carrizo" support.
11572 * config/gcn/gcn-opts.h (processor_type): Likewise.
11573 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
11574 * config/gcn/gcn.opt (gpu_type): Likewise.
11575 * config/gcn/t-omp-device: Likewise.
11577 2020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com>
11579 PR target/91816
11580 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
11581 * config/arm/arm.c (arm_gen_far_branch): New function
11582 arm_gen_far_branch.
11583 * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
11585 2020-02-03 Julian Brown <julian@codesourcery.com>
11586 Tobias Burnus <tobias@codesourcery.com>
11588 * doc/invoke.texi: Update mention of OpenACC version to 2.6.
11590 2020-02-03 Jakub Jelinek <jakub@redhat.com>
11592 PR target/93533
11593 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
11594 valid RTL to sum up the lowest and second lowest bytes of the popcnt
11595 result.
11597 2020-02-02 Vladimir Makarov <vmakarov@redhat.com>
11599 PR rtl-optimization/91333
11600 * ira-color.c (struct allocno_color_data): Add member
11601 hard_reg_prefs.
11602 (init_allocno_threads): Set the member up.
11603 (bucket_allocno_compare_func): Add compare hard reg
11604 prefs.
11606 2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
11608 nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
11610 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
11611 * config.in: Regenerated.
11612 * configure: Regenerated.
11613 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
11614 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
11615 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.
11617 2020-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
11619 * configure: Regenerate.
11621 2020-01-31 Vladimir Makarov <vmakarov@redhat.com>
11623 PR rtl-optimization/91333
11624 * ira-color.c (bucket_allocno_compare_func): Move conflict hard
11625 reg preferences comparison up.
11627 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
11629 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
11630 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
11631 aarch64-sve-builtins-base.h.
11632 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
11633 aarch64-sve-builtins-base.cc.
11634 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
11635 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
11636 (svcvtnt): Declare.
11637 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
11638 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
11639 (svcvtnt): New functions.
11640 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
11641 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
11642 (svcvtnt): New functions.
11643 (svcvt): Add a form that converts f32 to bf16.
11644 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
11645 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
11646 Declare.
11647 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
11648 Treat B as bfloat16_t.
11649 (ternary_bfloat_lane_base): New class.
11650 (ternary_bfloat_def): Likewise.
11651 (ternary_bfloat): New shape.
11652 (ternary_bfloat_lane_def): New class.
11653 (ternary_bfloat_lane): New shape.
11654 (ternary_bfloat_lanex2_def): New class.
11655 (ternary_bfloat_lanex2): New shape.
11656 (ternary_bfloat_opt_n_def): New class.
11657 (ternary_bfloat_opt_n): New shape.
11658 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
11659 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
11660 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
11661 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
11662 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
11663 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
11664 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
11665 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
11666 the pattern off the narrow mode instead of the wider one.
11667 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
11668 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
11669 (sve_fp_op): Handle them.
11670 (SVE_BFLOAT_TERNARY_LONG): New int itertor.
11671 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
11673 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
11675 * config/aarch64/arm_sve.h: Include arm_bf16.h.
11676 * config/aarch64/aarch64-modes.def (BF): Move definition before
11677 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF.
11678 (SVE_MODES): Handle BF modes.
11679 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
11680 BF modes.
11681 (aarch64_full_sve_mode): Likewise.
11682 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
11683 and VNx32BF.
11684 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
11685 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
11686 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
11687 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
11688 new SVE BF modes.
11689 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
11690 type_class_index.
11691 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
11692 (TYPES_all_data): Add bf16.
11693 (TYPES_reinterpret1, TYPES_reinterpret): Likewise.
11694 (register_tuple_type): Increase buffer size.
11695 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
11696 (bf16): New type suffix.
11697 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
11698 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
11699 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
11700 Change type from all_data to all_arith.
11701 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
11702 (svminp): Likewise.
11704 2020-01-31 Dennis Zhang <dennis.zhang@arm.com>
11705 Matthew Malcomson <matthew.malcomson@arm.com>
11706 Richard Sandiford <richard.sandiford@arm.com>
11708 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
11709 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
11710 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
11711 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define
11712 __ARM_FEATURE_MATMUL_FP64.
11713 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
11714 (sve): Add AARCH64_FL_F32MM to the list of extensions that should
11715 be disabled at the same time.
11716 (f32mm): New extension.
11717 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
11718 (AARCH64_FL_F64MM): Bump to the next bit up.
11719 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
11720 (TARGET_SVE_F64MM): New macros.
11721 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
11722 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
11723 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
11724 (UNSPEC_ZIP2Q): New unspeccs.
11725 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
11726 (optab, sur, perm_insn): Handle the new unspecs.
11727 (sve_fp_op): Handle UNSPEC_FMMLA. Resort.
11728 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
11729 TARGET_SVE_F64MM instead of separate tests.
11730 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
11731 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
11732 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
11733 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
11734 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
11735 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
11736 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
11737 (TYPES_s_signed): New macro.
11738 (TYPES_s_integer): Use it.
11739 (TYPES_d_float): New macro.
11740 (TYPES_d_data): Use it.
11741 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
11742 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
11743 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
11744 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
11745 (svmmla): New shape.
11746 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
11747 template parameters.
11748 (ternary_resize2_lane_base): Likewise.
11749 (ternary_resize2_base): New class.
11750 (ternary_qq_lane_base): Likewise.
11751 (ternary_intq_uintq_lane_def): Likewise.
11752 (ternary_intq_uintq_lane): New shape.
11753 (ternary_intq_uintq_opt_n_def): New class
11754 (ternary_intq_uintq_opt_n): New shape.
11755 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
11756 (ternary_uintq_intq_def): New class.
11757 (ternary_uintq_intq): New shape.
11758 (ternary_uintq_intq_lane_def): New class.
11759 (ternary_uintq_intq_lane): New shape.
11760 (ternary_uintq_intq_opt_n_def): New class.
11761 (ternary_uintq_intq_opt_n): New shape.
11762 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
11763 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
11764 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
11765 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
11766 Generalize to...
11767 (svdotprod_lane_impl): ...this new class.
11768 (svmmla_impl, svusdot_impl): New classes.
11769 (svdot_lane): Update to use svdotprod_lane_impl.
11770 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
11771 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
11772 functions.
11773 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
11774 function, with no types defined.
11775 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
11776 AARCH64_FL_I8MM functions.
11777 (svmmla): New AARCH64_FL_F32MM function.
11778 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
11779 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
11780 AARCH64_FL_F64MM function.
11781 (REQUIRED_EXTENSIONS):
11783 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
11785 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
11786 alternative only.
11788 2020-01-31 Uroš Bizjak <ubizjak@gmail.com>
11790 * config/i386/i386.md (*movoi_internal_avx): Do not check for
11791 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling.
11792 (*movti_internal): Do not check for
11793 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
11794 (*movtf_internal): Move check for TARGET_SSE2 and size optimization
11795 just after check for TARGET_AVX.
11796 (*movdf_internal): Ditto.
11797 * config/i386/mmx.md (*mov<mode>_internal): Do not check for
11798 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
11799 * config/i386/sse.md (mov<mode>_internal): Only check
11800 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check
11801 for TARGET_SSE2 and size optimization just after check for TARGET_AVX.
11802 (<sse>_andnot<mode>3<mask_name>): Move check for
11803 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX.
11804 (<code><mode>3<mask_name>): Ditto.
11805 (*andnot<mode>3): Ditto.
11806 (*andnottf3): Ditto.
11807 (*<code><mode>3): Ditto.
11808 (*<code>tf3): Ditto.
11809 (*andnot<VI:mode>3): Remove
11810 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling.
11811 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto.
11812 (*<code><VI12_AVX_AVX512F:mode>3): Ditto.
11813 (sse4_1_blendv<ssemodesuffix>): Ditto.
11814 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL):
11815 Explain that tune applies to 128bit instructions only.
11817 2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com>
11819 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count
11820 to definition of hsa_kernel_description. Parse assembly to find SGPR
11821 and VGPR count of kernel and store in hsa_kernel_description.
11823 2020-01-31 Tamar Christina <tamar.christina@arm.com>
11825 PR rtl-optimization/91838
11826 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case
11827 to truncate if allowed or reject combination.
11829 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
11831 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step.
11832 (find_inv_vars_cb): Likewise.
11834 2020-01-31 David Malcolm <dmalcolm@redhat.com>
11836 * calls.c (special_function_p): Split out the check for DECL_NAME
11837 being non-NULL and fndecl being extern at file scope into a
11838 new maybe_special_function_p and call it. Drop check for fndecl
11839 being non-NULL that was after a usage of DECL_NAME (fndecl).
11840 * tree.h (maybe_special_function_p): New inline function.
11842 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
11844 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ...
11845 (mask_gather_load<mode>): ... here, and zero-initialize the
11846 destination.
11847 (maskload<mode>di): Zero-initialize the destination.
11848 * config/gcn/gcn.c:
11850 2020-01-30 David Malcolm <dmalcolm@redhat.com>
11852 PR analyzer/93356
11853 * doc/analyzer.texi (Limitations): Note that constraints on
11854 floating-point values are currently ignored.
11856 2020-01-30 Jakub Jelinek <jakub@redhat.com>
11858 PR lto/93384
11859 * symtab.c (symtab_node::noninterposable_alias): If localalias
11860 already exists, but is not usable, append numbers after it until
11861 a unique name is found. Formatting fix.
11863 PR middle-end/93505
11864 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range
11865 rotate counts.
11867 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
11869 * config/gcn/gcn.c (print_operand): Handle LTGT.
11870 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
11872 2020-01-30 Richard Biener <rguenther@suse.de>
11874 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST
11875 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE.
11877 2020-01-30 John David Anglin <danglin@gcc.gnu.org>
11879 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers
11880 without a DECL in .data.rel.ro.local.
11882 2020-01-30 Jakub Jelinek <jakub@redhat.com>
11884 PR target/93494
11885 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4
11886 returned.
11888 PR target/91824
11889 * config/i386/sse.md
11890 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
11891 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
11892 any_extend code iterator instead of always zero_extend.
11893 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
11894 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
11895 Use any_extend code iterator instead of always zero_extend.
11896 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
11897 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
11898 Use any_extend code iterator instead of always zero_extend.
11899 (*sse2_pmovmskb_ext): New define_insn.
11900 (*sse2_pmovmskb_ext_lt): New define_insn_and_split.
11902 PR target/91824
11903 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
11904 (*popcountsi2_zext_falsedep): New define_insn.
11906 2020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
11908 * config.in: Regenerated.
11909 * configure: Regenerated.
11911 2020-01-29 Tobias Burnus <tobias@codesourcery.com>
11913 PR bootstrap/93409
11914 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as
11915 LLVM's assembler changed the default in version 9.
11917 2020-01-24 Jeff Law <law@redhat.com>
11919 PR tree-optimization/89689
11920 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure.
11922 2020-01-29 Richard Sandiford <richard.sandiford@arm.com>
11924 Revert:
11926 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
11928 PR rtl-optimization/87763
11929 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
11930 simplification to handle subregs as well as bare regs.
11931 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
11933 2020-01-29 Joel Hutton <Joel.Hutton@arm.com>
11935 PR target/93221
11936 * ira.c (ira): Revert use of simplified LRA algorithm.
11938 2020-01-29 Martin Jambor <mjambor@suse.cz>
11940 PR tree-optimization/92706
11941 * tree-sra.c (struct access): Fields first_link, last_link,
11942 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link,
11943 next_rhs_queued and grp_rhs_queued respectively, new fields
11944 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued.
11945 (struct assign_link): Field next renamed to next_rhs, new field
11946 next_lhs. Updated comment.
11947 (work_queue_head): Renamed to rhs_work_queue_head.
11948 (lhs_work_queue_head): New variable.
11949 (add_link_to_lhs): New function.
11950 (relink_to_new_repr): Also relink LHS lists.
11951 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue.
11952 (add_access_to_lhs_work_queue): New function.
11953 (pop_access_from_work_queue): Renamed to
11954 pop_access_from_rhs_work_queue.
11955 (pop_access_from_lhs_work_queue): New function.
11956 (build_accesses_from_assign): Also add links to LHS lists and to LHS
11957 work_queue.
11958 (child_would_conflict_in_lacc): Renamed to
11959 child_would_conflict_in_acc. Adjusted parameter names.
11960 (create_artificial_child_access): New parameter set_grp_read, use it.
11961 (subtree_mark_written_and_enqueue): Renamed to
11962 subtree_mark_written_and_rhs_enqueue.
11963 (propagate_subaccesses_across_link): Renamed to
11964 propagate_subaccesses_from_rhs.
11965 (propagate_subaccesses_from_lhs): New function.
11966 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to
11967 RHSs.
11969 2020-01-29 Martin Jambor <mjambor@suse.cz>
11971 PR tree-optimization/92706
11972 * tree-sra.c (struct access): Adjust comment of
11973 grp_total_scalarization.
11974 (find_access_in_subtree): Look for single children spanning an entire
11975 access.
11976 (scalarizable_type_p): Allow register accesses, adjust callers.
11977 (completely_scalarize): Remove function.
11978 (scalarize_elem): Likewise.
11979 (create_total_scalarization_access): Likewise.
11980 (sort_and_splice_var_accesses): Do not track total scalarization
11981 flags.
11982 (analyze_access_subtree): New parameter totally, adjust to new meaning
11983 of grp_total_scalarization.
11984 (analyze_access_trees): Pass new parameter to analyze_access_subtree.
11985 (can_totally_scalarize_forest_p): New function.
11986 (create_total_scalarization_access): Likewise.
11987 (create_total_access_and_reshape): Likewise.
11988 (total_should_skip_creating_access): Likewise.
11989 (totally_scalarize_subtree): Likewise.
11990 (analyze_all_variable_accesses): Perform total scalarization after
11991 subaccess propagation using the new functions above.
11992 (initialize_constant_pool_replacements): Output initializers by
11993 traversing the access tree.
11995 2020-01-29 Martin Jambor <mjambor@suse.cz>
11997 * tree-sra.c (verify_sra_access_forest): New function.
11998 (verify_all_sra_access_forests): Likewise.
11999 (create_artificial_child_access): Set parent.
12000 (analyze_all_variable_accesses): Call the verifier.
12002 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12004 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge
12005 if called on indirect edge.
12006 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of
12007 speculative call if needed.
12009 2020-01-29 Richard Biener <rguenther@suse.de>
12011 PR tree-optimization/93428
12012 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load
12013 permutation when the load node is created.
12014 (vect_analyze_slp_instance): Re-use it here.
12016 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12018 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning.
12020 2020-01-28 Vladimir Makarov <vmakarov@redhat.com>
12022 PR rtl-optimization/93272
12023 * ira-lives.c (process_out_of_region_eh_regs): New function.
12024 (process_bb_node_lives): Call it.
12026 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12028 * coverage.c (read_counts_file): Make error message lowercase.
12030 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12032 * profile-count.c (profile_quality_display_names): Fix ordering.
12034 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
12036 PR lto/93318
12037 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site
12038 hash only when edge is first within the sequence.
12039 (cgraph_edge::set_call_stmt): Update handling of speculative calls.
12040 (symbol_table::create_edge): Do not set target_prob.
12041 (cgraph_edge::remove_caller): Watch for speculative calls when updating
12042 the call site hash.
12043 (cgraph_edge::make_speculative): Drop target_prob parameter.
12044 (cgraph_edge::speculative_call_info): Remove.
12045 (cgraph_edge::first_speculative_call_target): New member function.
12046 (update_call_stmt_hash_for_removing_direct_edge): New function.
12047 (cgraph_edge::resolve_speculation): Rewrite to new API.
12048 (cgraph_edge::speculative_call_for_target): New member function.
12049 (cgraph_edge::make_direct): Rewrite to new API; fix handling of
12050 multiple speculation targets.
12051 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating
12052 of profile.
12053 (verify_speculative_call): Verify that targets form an interval.
12054 * cgraph.h (cgraph_edge::speculative_call_info): Remove.
12055 (cgraph_edge::first_speculative_call_target): New member function.
12056 (cgraph_edge::next_speculative_call_target): New member function.
12057 (cgraph_edge::speculative_call_target_ref): New member function.
12058 (cgraph_edge;:speculative_call_indirect_edge): New member funtion.
12059 (cgraph_edge): Remove target_prob.
12060 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
12061 Fix handling of speculative calls.
12062 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals.
12063 * ipa-fnsummary.c (analyze_function_body): Likewise.
12064 * ipa-inline.c (speculation_useful_p): Use new speculative call API.
12065 * ipa-profile.c (dump_histogram): Fix formating.
12066 (ipa_profile_generate_summary): Watch for overflows.
12067 (ipa_profile): Do not require probablity to be 1/2; update to new API.
12068 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API.
12069 (update_indirect_edges_after_inlining): Update to new API.
12070 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call
12071 profiles.
12072 * profile-count.h: (profile_probability::adjusted): New.
12073 * tree-inline.c (copy_bb): Update to new speculative call API; fix
12074 updating of profile.
12075 * value-prof.c (gimple_ic_transform): Rename to ...
12076 (dump_ic_profile): ... this one; update dumping.
12077 (stream_in_histogram_value): Fix formating.
12078 (gimple_value_profile_transformations): Update.
12080 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
12082 PR target/91461
12083 * config/i386/i386.md (*movoi_internal_avx): Remove
12084 TARGET_SSE_TYPELESS_STORES check.
12085 (*movti_internal): Prefer TARGET_AVX over
12086 TARGET_SSE_TYPELESS_STORES.
12087 (*movtf_internal): Likewise.
12088 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over
12089 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check
12090 from TARGET_SSE_TYPELESS_STORES.
12092 2020-01-28 David Malcolm <dmalcolm@redhat.com>
12094 * diagnostic-core.h (warning_at): Rename overload to...
12095 (warning_meta): ...this.
12096 (emit_diagnostic_valist): Delete decl of overload taking
12097 diagnostic_metadata.
12098 * diagnostic.c (emit_diagnostic_valist): Likewise for defn.
12099 (warning_at): Rename overload taking diagnostic_metadata to...
12100 (warning_meta): ...this.
12102 2020-01-28 Richard Biener <rguenther@suse.de>
12104 PR tree-optimization/93439
12105 * tree-parloops.c (create_loop_fn): Move clique bookkeeping...
12106 * tree-cfg.c (move_sese_region_to_fn): ... here.
12107 (verify_types_in_gimple_reference): Verify used cliques are
12108 tracked.
12110 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
12112 PR target/91399
12113 * config/i386/i386-options.c (set_ix86_tune_features): Add an
12114 argument of a pointer to struct gcc_options and pass it to
12115 parse_mtune_ctrl_str.
12116 (ix86_function_specific_restore): Pass opts to
12117 set_ix86_tune_features.
12118 (ix86_option_override_internal): Likewise.
12119 (parse_mtune_ctrl_str): Add an argument of a pointer to struct
12120 gcc_options and use it for x_ix86_tune_ctrl_string.
12122 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12124 PR rtl-optimization/87763
12125 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
12126 simplification to handle subregs as well as bare regs.
12127 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
12129 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12131 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully
12132 for reduction chains that (now) include a call.
12134 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12136 PR tree-optimization/92822
12137 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling
12138 out the don't-care elements of a vector whose significant elements
12139 are duplicates, make the don't-care elements duplicates too.
12141 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
12143 PR tree-optimization/93434
12144 * tree-predcom.c (split_data_refs_to_components): Record which
12145 components have had aliasing loads removed. Prevent store-store
12146 commoning for all such components.
12148 2020-01-28 Jakub Jelinek <jakub@redhat.com>
12150 PR target/93418
12151 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not
12152 -1 or is_vshift is true, use new_vector with number of elts npatterns
12153 rather than new_unary_operation.
12155 PR tree-optimization/93454
12156 * gimple-fold.c (fold_array_ctor_reference): Perform
12157 elt_size.to_uhwi () just once, instead of calling it in every
12158 iteration. Punt if that value is above size of the temporary
12159 buffer. Decrease third native_encode_expr argument when
12160 bufoff + elt_sz is above size of buf.
12162 2020-01-27 Joseph Myers <joseph@codesourcery.com>
12164 * config/mips/mips.c (mips_declare_object_name)
12165 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object.
12167 2020-01-27 Martin Liska <mliska@suse.cz>
12169 PR gcov-profile/93403
12170 * tree-profile.c (gimple_init_gcov_profiler): Generate
12171 both __gcov_indirect_call_profiler_v4 and
12172 __gcov_indirect_call_profiler_v4_atomic.
12174 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12176 PR target/92822
12177 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
12178 expander.
12179 (@aarch64_split_simd_mov<mode>): Use it.
12180 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
12181 Leave the vec_extract patterns to handle 2-element vectors.
12182 (aarch64_simd_mov_from_<mode>high): Likewise.
12183 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
12184 (vec_extractv2dfv1df): Likewise.
12186 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12188 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
12189 jump conditions for *compare_condjump<GPI:mode>.
12191 2020-01-27 David Malcolm <dmalcolm@redhat.com>
12193 PR analyzer/93276
12194 * digraph.cc (test_edge::test_edge): Specify template for base
12195 class initializer.
12197 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
12199 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
12201 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
12203 * config/arc/arc-protos.h (gen_mlo): Remove.
12204 (gen_mhi): Likewise.
12205 * config/arc/arc.c (AUX_MULHI): Define.
12206 (arc_must_save_reister): Special handling for r58/59.
12207 (arc_compute_frame_size): Consider mlo/mhi registers.
12208 (arc_save_callee_saves): Emit fp/sp move only when emit_move
12209 paramter is true.
12210 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
12211 mlo/mhi name selection.
12212 (arc_restore_callee_saves): Don't early restore blink when ISR.
12213 (arc_expand_prologue): Add mlo/mhi saving.
12214 (arc_expand_epilogue): Add mlo/mhi restoring.
12215 (gen_mlo): Remove.
12216 (gen_mhi): Remove.
12217 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
12218 numbering when MUL64 option is used.
12219 (DWARF2_FRAME_REG_OUT): Define.
12220 * config/arc/arc.md (arc600_stall): New pattern.
12221 (VUNSPEC_ARC_ARC600_STALL): Define.
12222 (mulsi64): Use correct mlo/mhi registers.
12223 (mulsi_600): Clean it up.
12224 * config/arc/predicates.md (mlo_operand): Remove any dependency on
12225 TARGET_BIG_ENDIAN.
12226 (mhi_operand): Likewise.
12228 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
12229 Petro Karashchenko <petro.karashchenko@ring.com>
12231 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct
12232 attributes if needed.
12233 (prepare_move_operands): Generate special unspec instruction for
12234 direct access.
12235 (arc_isuncached_mem_p): Propagate uncached attribute to each
12236 structure member.
12237 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
12238 (VUNSPEC_ARC_STDI): Likewise.
12239 (ALLI): New mode iterator.
12240 (mALLI): New mode attribute.
12241 (lddi): New instruction pattern.
12242 (stdi): Likewise.
12243 (stdidi_split): Split instruction for architectures which are not
12244 supporting ll64 option.
12245 (lddidi_split): Likewise.
12247 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12249 PR rtl-optimization/92989
12250 * lra-lives.c (process_bb_lives): Update the live-in set before
12251 processing additional clobbers.
12253 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12255 PR rtl-optimization/93170
12256 * cselib.c (cselib_invalidate_regno_val): New function, split out
12257 from...
12258 (cselib_invalidate_regno): ...here.
12259 (cselib_invalidated_by_call_p): New function.
12260 (cselib_process_insn): Iterate over all the hard-register entries in
12261 REG_VALUES and invalidate any that cross call-clobbered registers.
12263 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
12265 * dojump.c (split_comparison): Use HONOR_NANS rather than
12266 HONOR_SNANS when splitting LTGT.
12268 2020-01-27 Martin Liska <mliska@suse.cz>
12270 PR driver/91220
12271 * opts.c (print_filtered_help): Exclude language-specific
12272 options from --help=common unless enabled in all FEs.
12274 2020-01-27 Martin Liska <mliska@suse.cz>
12276 * opts.c (print_help): Exclude params from
12277 all except --help=param.
12279 2020-01-27 Martin Liska <mliska@suse.cz>
12281 PR target/93274
12282 * config/i386/i386-features.c (make_resolver_func):
12283 Align the code with ppc64 target implementation.
12284 Do not generate a unique name for resolver function.
12286 2020-01-27 Richard Biener <rguenther@suse.de>
12288 PR tree-optimization/93397
12289 * tree-vect-slp.c (vect_analyze_slp_instance): Delay
12290 converted reduction chain SLP graph adjustment.
12292 2020-01-26 Marek Polacek <polacek@redhat.com>
12294 PR sanitizer/93436
12295 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
12296 null DECL_NAME.
12298 2020-01-26 Jason Merrill <jason@redhat.com>
12300 PR c++/92601
12301 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
12302 of complete types.
12304 2020-01-26 Darius Galis <darius.galis@cyberthorstudios.com>
12306 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
12307 (rx_setmem): Likewise.
12309 2020-01-26 Jakub Jelinek <jakub@redhat.com>
12311 PR target/93412
12312 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
12313 Use nonimmediate_operand instead of x86_64_hilo_general_operand and
12314 drop <di> from constraint of last operand.
12316 PR target/93430
12317 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
12318 TARGET_AVX2 and V4DFmode not in the split condition, but in the
12319 pattern condition, though allow { 0, 0, 0, 0 } broadcast always.
12321 2020-01-25 Feng Xue <fxue@os.amperecomputing.com>
12323 PR ipa/93166
12324 * ipa-cp.c (get_info_about_necessary_edges): Remove value
12325 check assertion.
12327 2020-01-24 Jeff Law <law@redhat.com>
12329 PR tree-optimization/92788
12330 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX
12331 not EDGE_ABNORMAL.
12333 2020-01-24 Jakub Jelinek <jakub@redhat.com>
12335 PR target/93395
12336 * config/i386/sse.md (*avx_vperm_broadcast_v4sf,
12337 *avx_vperm_broadcast_<mode>,
12338 <sse2_avx_avx512f>_vpermil<mode><mask_name>,
12339 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>):
12340 Move before avx2_perm<mode>/avx512f_perm<mode>.
12342 PR target/93376
12343 * simplify-rtx.c (simplify_const_unary_operation,
12344 simplify_const_binary_operation): Punt for mode precision above
12345 MAX_BITSIZE_MODE_ANY_INT.
12347 2020-01-24 Andrew Pinski <apinski@marvell.com>
12349 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change
12350 alu.shift_reg to 0.
12352 2020-01-24 Jeff Law <law@redhat.com>
12354 PR target/13721
12355 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg
12356 for REGs. Call output_operand_lossage to get more reasonable
12357 diagnostics.
12359 2020-01-24 Andrew Stubbs <ams@codesourcery.com>
12361 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use
12362 gcn_fp_compare_operator.
12363 (vec_cmpu<mode>di): Use gcn_compare_operator.
12364 (vec_cmp<u>v64qidi): Use gcn_compare_operator.
12365 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator.
12366 (vec_cmpu<mode>di_exec): Use gcn_compare_operator.
12367 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator.
12368 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator.
12369 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator.
12370 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use
12371 gcn_fp_compare_operator.
12372 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use
12373 gcn_fp_compare_operator.
12374 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use
12375 gcn_fp_compare_operator.
12376 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use
12377 gcn_fp_compare_operator.
12379 2020-01-24 Maciej W. Rozycki <macro@wdc.com>
12381 * doc/install.texi (Cross-Compiler-Specific Options): Document
12382 `--with-toolexeclibdir' option.
12384 2020-01-24 Hans-Peter Nilsson <hp@axis.com>
12386 * target.def (flags_regnum): Also mention effect on delay slot filling.
12387 * doc/tm.texi: Regenerate.
12389 2020-01-23 Jeff Law <law@redhat.com>
12391 PR translation/90162
12392 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text.
12394 2020-01-23 Mikael Tillenius <mti-1@tillenius.com>
12396 PR target/92269
12397 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of
12398 profiling label
12400 2020-01-23 Jakub Jelinek <jakub@redhat.com>
12402 PR rtl-optimization/93402
12403 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust
12404 USE insns.
12406 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
12408 * config.in: Regenerated.
12409 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
12410 for TARGET_LIBC_GNUSTACK.
12411 * configure: Regenerated.
12412 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
12413 found to be 2.31 or greater.
12415 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
12417 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
12418 TARGET_SOFT_FLOAT.
12419 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
12420 (mips_asm_file_end): New function. Delegate to
12421 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
12422 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
12424 2020-01-23 Jakub Jelinek <jakub@redhat.com>
12426 PR target/93376
12427 * config/i386/i386-modes.def (POImode): New mode.
12428 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160.
12429 * config/i386/i386.md (DPWI): New mode attribute.
12430 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>.
12431 (QWI): Rename to...
12432 (QPWI): ... this. Use POI instead of OI for TImode.
12433 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1,
12434 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI>
12435 instead of <QWI>.
12437 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
12439 PR target/93341
12440 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New
12441 unspec.
12442 (speculation_tracker_rev): New pattern.
12443 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation):
12444 Use speculation_tracker_rev to track the inverse condition.
12446 2020-01-23 Richard Biener <rguenther@suse.de>
12448 PR tree-optimization/93381
12449 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take
12450 alias-set of the def as argument and record the first one.
12451 (vn_walk_cb_data::first_set): New member.
12452 (vn_reference_lookup_3): Pass the alias-set of the current def
12453 to push_partial_def. Fix alias-set used in the aggregate copy
12454 case.
12455 (vn_reference_lookup): Consistently set *last_vuse_ptr.
12456 * real.c (clear_significand_below): Fix out-of-bound access.
12458 2020-01-23 Jakub Jelinek <jakub@redhat.com>
12460 PR target/93346
12461 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3):
12462 New define_insn patterns.
12464 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
12466 * doc/sourcebuild.texi (check-function-bodies): Add an
12467 optional target/xfail selector.
12469 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
12471 PR rtl-optimization/93124
12472 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to
12473 bare USE and CLOBBER insns.
12475 2020-01-22 Andrew Pinski <apinski@marvell.com>
12477 * config/arc/arc.c (output_short_suffix): Check insn for nullness.
12479 2020-01-22 David Malcolm <dmalcolm@redhat.com>
12481 PR analyzer/93307
12482 * gdbinit.in (break-on-saved-diagnostic): Update for move of
12483 diagnostic_manager into "ana" namespace.
12484 * selftest-run-tests.c (selftest::run_tests): Update for move of
12485 selftest::run_analyzer_selftests to
12486 ana::selftest::run_analyzer_selftests.
12488 2020-01-22 Richard Sandiford <richard.sandiford@arm.com>
12490 * cfgexpand.c (union_stack_vars): Update the size.
12492 2020-01-22 Richard Biener <rguenther@suse.de>
12494 PR tree-optimization/93381
12495 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting
12496 throughout, handle all conversions the same.
12498 2020-01-22 Jakub Jelinek <jakub@redhat.com>
12500 PR target/93335
12501 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use
12502 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate
12503 predicate, not whenever it is CONST_INT. Otherwise, force_reg it.
12504 Call force_reg on high_in2 unconditionally.
12506 2020-01-22 Martin Liska <mliska@suse.cz>
12508 PR tree-optimization/92924
12509 * profile.c (compute_value_histograms): Divide
12510 all counter values.
12512 2020-01-22 Jakub Jelinek <jakub@redhat.com>
12514 PR target/91298
12515 * output.h (assemble_name_resolve): Declare.
12516 * varasm.c (assemble_name_resolve): New function.
12517 (assemble_name): Use it.
12518 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define.
12520 2020-01-22 Joseph Myers <joseph@codesourcery.com>
12522 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to
12523 update_web_docs_git instead of update_web_docs_svn.
12525 2020-01-21 Andrew Pinski <apinski@marvell.com>
12527 PR target/9311
12528 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
12529 as PTR mode. Have operand 1 as being modeless, it can be P mode.
12530 (*tlsgd_small_<mode>): Likewise.
12531 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
12532 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
12533 register. Convert that register back to dest using convert_mode.
12535 2020-01-21 Jim Wilson <jimw@sifive.com>
12537 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
12538 instead of XINT.
12540 2020-01-21 H.J. Lu <hongjiu.lu@intel.com>
12541 Uros Bizjak <ubizjak@gmail.com>
12543 PR target/93319
12544 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode
12545 with ptr_mode.
12546 (legitimize_tls_address): Do GNU2 TLS address computation in
12547 ptr_mode and zero-extend result to Pmode.
12548 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
12549 :P with :PTR and Pmode with ptr_mode.
12550 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
12551 (*tls_dynamic_gnu2_call_64_<mode>): Likewise.
12552 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise.
12554 2020-01-21 Jakub Jelinek <jakub@redhat.com>
12556 PR target/93333
12557 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
12558 the last two operands are CONST_INT_P before using them as such.
12560 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
12562 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
12563 to get the integer element types.
12565 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
12567 * config/aarch64/aarch64-sve-builtins.h
12568 (function_expander::convert_to_pmode): Declare.
12569 * config/aarch64/aarch64-sve-builtins.cc
12570 (function_expander::convert_to_pmode): New function.
12571 (function_expander::get_contiguous_base): Use it.
12572 (function_expander::prepare_gather_address_operands): Likewise.
12573 * config/aarch64/aarch64-sve-builtins-sve2.cc
12574 (svwhilerw_svwhilewr_impl::expand): Likewise.
12576 2020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com>
12578 PR target/92424
12579 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set
12580 cfun->machine->label_is_assembled.
12581 (aarch64_print_patchable_function_entry): New.
12582 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
12583 * config/aarch64/aarch64.h (struct machine_function): New field,
12584 label_is_assembled.
12586 2020-01-21 David Malcolm <dmalcolm@redhat.com>
12588 PR ipa/93315
12589 * ipa-profile.c (ipa_profile): Delete call_sums and set it to
12590 NULL on exit.
12592 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
12594 PR lto/93318
12595 * cgraph.c (cgraph_edge::resolve_speculation,
12596 cgraph_edge::redirect_call_stmt_to_callee): Fix update of
12597 call_stmt_site_hash.
12599 2020-01-21 Martin Liska <mliska@suse.cz>
12601 * config/rs6000/rs6000.c (common_mode_defined): Remove
12602 unused variable.
12604 2020-01-21 Richard Biener <rguenther@suse.de>
12606 PR tree-optimization/92328
12607 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
12608 type when value-numbering same-sized store by inserting a
12609 VIEW_CONVERT_EXPR.
12610 (eliminate_dom_walker::eliminate_stmt): When eliminating
12611 a redundant store handle bit-reinterpretation of the same value.
12613 2020-01-21 Andrew Pinski <apinski@marvel.com>
12615 PR tree-opt/93321
12616 * tree-into-ssa.c (prepare_block_for_update_1): Split out
12617 from ...
12618 (prepare_block_for_update): This. Use a worklist instead of
12619 recursing.
12621 2020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
12623 * gcc/config/arm/arm.c (clear_operation_p):
12624 Initialise last_regno, skip first iteration
12625 based on the first_set value and use ints instead
12626 of the unnecessary HOST_WIDE_INTs.
12628 2020-01-21 Jakub Jelinek <jakub@redhat.com>
12630 PR target/93073
12631 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
12632 compare_mode other than SFmode or DFmode.
12634 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
12636 PR target/93304
12637 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
12638 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
12639 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
12641 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
12643 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
12645 2020-01-20 Andrew Pinski <apinski@marvell.com>
12647 PR middle-end/93242
12648 * targhooks.c (default_print_patchable_function_entry): Use
12649 output_asm_insn to emit the nop instruction.
12651 2020-01-20 Fangrui Song <maskray@google.com>
12653 PR middle-end/93194
12654 * targhooks.c (default_print_patchable_function_entry): Align to
12655 POINTER_SIZE.
12657 2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
12659 PR target/93319
12660 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to
12661 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode.
12662 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ...
12663 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P.
12664 (*tls_dynamic_gnu2_lea_64): Renamed to ...
12665 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P.
12666 Remove the {q} suffix from lea.
12667 (*tls_dynamic_gnu2_call_64): Renamed to ...
12668 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P.
12669 (*tls_dynamic_gnu2_combine_64): Renamed to ...
12670 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P.
12671 Pass Pmode to gen_tls_dynamic_gnu2_64.
12673 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
12675 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
12677 2020-01-20 Richard Sandiford <richard.sandiford@arm.com>
12679 * config/aarch64/aarch64-sve-builtins-base.cc
12680 (svld1ro_impl::memory_vector_mode): Remove parameter name.
12682 2020-01-20 Richard Biener <rguenther@suse.de>
12684 PR debug/92763
12685 * dwarf2out.c (prune_unused_types): Unconditionally mark
12686 called function DIEs.
12688 2020-01-20 Martin Liska <mliska@suse.cz>
12690 PR tree-optimization/93199
12691 * tree-eh.c (struct leh_state): Add
12692 new field outer_non_cleanup.
12693 (cleanup_is_dead_in): Pass leh_state instead
12694 of eh_region. Add a checking that state->outer_non_cleanup
12695 points to outer non-clean up region.
12696 (lower_try_finally): Record outer_non_cleanup
12697 for this_state.
12698 (lower_catch): Likewise.
12699 (lower_eh_filter): Likewise.
12700 (lower_eh_must_not_throw): Likewise.
12701 (lower_cleanup): Likewise.
12703 2020-01-20 Richard Biener <rguenther@suse.de>
12705 PR tree-optimization/93094
12706 * tree-vectorizer.h (vect_loop_versioning): Adjust.
12707 (vect_transform_loop): Likewise.
12708 * tree-vectorizer.c (try_vectorize_loop_1): Pass down
12709 loop_vectorized_call to vect_transform_loop.
12710 * tree-vect-loop.c (vect_transform_loop): Pass down
12711 loop_vectorized_call to vect_loop_versioning.
12712 * tree-vect-loop-manip.c (vect_loop_versioning): Use
12713 the earlier discovered loop_vectorized_call.
12715 2020-01-19 Eric S. Raymond <esr@thyrsus.com>
12717 * doc/contribute.texi: Update for SVN -> Git transition.
12718 * doc/install.texi: Likewise.
12720 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
12722 PR lto/93318
12723 * cgraph.c (cgraph_edge::make_speculative): Increase number of
12724 speculative targets.
12725 (verify_speculative_call): New function
12726 (cgraph_node::verify_node): Use it.
12727 * ipa-profile.c (ipa_profile): Fix formating; do not set number of
12728 speculations.
12730 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
12732 PR lto/93318
12733 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting.
12734 (cgraph_edge::make_direct): Remove all indirect targets.
12735 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct..
12736 (cgraph_node::verify_node): Verify that only one call_stmt or
12737 lto_stmt_uid is set.
12738 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or
12739 lto_stmt_uid.
12740 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt.
12741 (lto_output_ref): Simplify streaming of stmt.
12742 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid.
12744 2020-01-18 Tamar Christina <tamar.christina@arm.com>
12746 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode):
12747 Mark parameter unused.
12749 2020-01-18 Hans-Peter Nilsson <hp@axis.com>
12751 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux*
12753 2019-01-18 Gerald Pfeifer <gerald@pfeifer.com>
12755 * varpool.c (ctor_useable_for_folding_p): Fix grammar.
12757 2020-01-18 Iain Sandoe <iain@sandoe.co.uk>
12759 * Makefile.in: Add coroutine-passes.o.
12760 * builtin-types.def (BT_CONST_SIZE): New.
12761 (BT_FN_BOOL_PTR): New.
12762 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New.
12763 * builtins.def (DEF_COROUTINE_BUILTIN): New.
12764 * coroutine-builtins.def: New file.
12765 * coroutine-passes.cc: New file.
12766 * function.h (struct GTY function): Add a bit to indicate that the
12767 function is a coroutine component.
12768 * internal-fn.c (expand_CO_FRAME): New.
12769 (expand_CO_YIELD): New.
12770 (expand_CO_SUSPN): New.
12771 (expand_CO_ACTOR): New.
12772 * internal-fn.def (CO_ACTOR): New.
12773 (CO_YIELD): New.
12774 (CO_SUSPN): New.
12775 (CO_FRAME): New.
12776 * passes.def: Add pass_coroutine_lower_builtins,
12777 pass_coroutine_early_expand_ifns.
12778 * tree-pass.h (make_pass_coroutine_lower_builtins): New.
12779 (make_pass_coroutine_early_expand_ifns): New.
12780 * doc/invoke.texi: Document the fcoroutines command line
12781 switch.
12783 2020-01-18 Jakub Jelinek <jakub@redhat.com>
12785 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable.
12787 PR target/93312
12788 * config/arm/arm.c (clear_operation_p): Don't use REGNO until
12789 after checking the argument is a REG. Don't use REGNO (reg)
12790 again to set last_regno, reuse regno variable instead.
12792 2020-01-17 David Malcolm <dmalcolm@redhat.com>
12794 * doc/analyzer.texi (Limitations): Add note about NaN.
12796 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
12797 Sudakshina Das <sudi.das@arm.com>
12799 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
12800 and valid immediate.
12801 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
12802 (lshrdi3): Generate thumb2_lsrl for valid immediates.
12803 * config/arm/constraints.md (Pg): New.
12804 * config/arm/predicates.md (long_shift_imm): New.
12805 (arm_reg_or_long_shift_imm): Likewise.
12806 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
12807 (thumb2_lsll): Likewise.
12808 (thumb2_lsrl): New.
12810 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
12811 Sudakshina Das <sudi.das@arm.com>
12813 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
12814 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
12815 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
12816 register pairs for doubleword quantities for ARMv8.1M-Mainline.
12817 * config/arm/thumb2.md (thumb2_asrl): New.
12818 (thumb2_lsll): Likewise.
12820 2020-01-17 Jakub Jelinek <jakub@redhat.com>
12822 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
12823 unused variable.
12825 2020-01-17 Alexander Monakov <amonakov@ispras.ru>
12827 * gdbinit.in (help-gcc-hooks): New command.
12828 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
12829 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
12830 documentation.
12832 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
12834 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
12835 correct target macro.
12837 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
12839 * config/aarch64/aarch64-protos.h
12840 (aarch64_sve_ld1ro_operand_p): New.
12841 * config/aarch64/aarch64-sve-builtins-base.cc
12842 (class load_replicate): New.
12843 (class svld1ro_impl): New.
12844 (class svld1rq_impl): Change to inherit from load_replicate.
12845 (svld1ro): New sve intrinsic function base.
12846 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
12847 New DEF_SVE_FUNCTION.
12848 * config/aarch64/aarch64-sve-builtins-base.h
12849 (svld1ro): New decl.
12850 * config/aarch64/aarch64-sve-builtins.cc
12851 (function_expander::add_mem_operand): Modify assert to allow
12852 OImode.
12853 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
12854 pattern.
12855 * config/aarch64/aarch64.c
12856 (aarch64_sve_ld1rq_operand_p): Implement in terms of ...
12857 (aarch64_sve_ld1rq_ld1ro_operand_p): This.
12858 (aarch64_sve_ld1ro_operand_p): New.
12859 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
12860 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
12861 * config/aarch64/predicates.md
12862 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New.
12864 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
12866 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
12867 Introduce this ACLE specified predefined macro.
12868 * config/aarch64/aarch64-option-extensions.def (f64mm): New.
12869 (fp): Disabling this disables f64mm.
12870 (simd): Disabling this disables f64mm.
12871 (fp16): Disabling this disables f64mm.
12872 (sve): Disabling this disables f64mm.
12873 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
12874 (AARCH64_ISA_F64MM): New.
12875 (TARGET_F64MM): New.
12876 * doc/invoke.texi (f64mm): Document new option.
12878 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
12880 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
12881 (neoversen1_tunings): Likewise.
12883 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
12885 PR target/92692
12886 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
12887 Add assert to ensure prolog has been emitted.
12888 (aarch64_split_atomic_op): Likewise.
12889 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
12890 Use epilogue_completed rather than reload_completed.
12891 (aarch64_atomic_exchange<mode>): Likewise.
12892 (aarch64_atomic_<atomic_optab><mode>): Likewise.
12893 (atomic_nand<mode>): Likewise.
12894 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
12895 (atomic_fetch_nand<mode>): Likewise.
12896 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
12897 (atomic_nand_fetch<mode>): Likewise.
12899 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
12901 PR target/93133
12902 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
12903 for FP modes.
12904 (REVERSE_CONDITION): Delete.
12905 * config/aarch64/iterators.md (CC_ONLY): New mode iterator.
12906 (CCFP_CCFPE): Likewise.
12907 (e): New mode attribute.
12908 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
12909 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
12910 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
12911 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
12912 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
12913 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
12914 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
12915 name of generator from gen_ccmpdi to gen_ccmpccdi.
12916 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse
12917 the previous comparison but aren't able to, use the new ccmp_rev
12918 patterns instead.
12920 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
12922 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
12923 than testing directly for INTEGER_CST.
12924 (gimplify_target_expr, gimplify_omp_depend): Likewise.
12926 2020-01-17 Jakub Jelinek <jakub@redhat.com>
12928 PR tree-optimization/93292
12929 * tree-vect-stmts.c (vectorizable_comparison): Punt also if
12930 get_vectype_for_scalar_type returns NULL.
12932 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
12934 * params.opt (-param=max-predicted-iterations): Increase range from 0.
12935 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.
12937 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
12939 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
12940 dump.
12941 * params.opt: (max-predicted-iterations): Set bounds.
12942 * predict.c (real_almost_one, real_br_prob_base,
12943 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
12944 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic
12945 probabilities; do not truncate to reg_br_prob_bases.
12946 (estimate_loops_at_level): Pass max_cyclic_prob.
12947 (estimate_loops): Compute max_cyclic_prob.
12948 (estimate_bb_frequencies): Do not initialize real_*; update calculation
12949 of back edge prob.
12950 * profile-count.c (profile_probability::to_sreal): New.
12951 * profile-count.h (class sreal): Move up in file.
12952 (profile_probability::to_sreal): Declare.
12954 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
12956 * config/arm/arm.c
12957 (arm_invalid_conversion): New function for target hook.
12958 (arm_invalid_unary_op): New function for target hook.
12959 (arm_invalid_binary_op): New function for target hook.
12961 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
12963 * config.gcc: Add arm_bf16.h.
12964 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
12965 (arm_simd_builtin_std_type): Add BFmode.
12966 (arm_init_simd_builtin_types): Define element types for vector types.
12967 (arm_init_bf16_types): New function.
12968 (arm_init_builtins): Add arm_init_bf16_types function call.
12969 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
12970 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
12971 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
12972 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
12973 (arm_vector_mode_supported_p): Add V4BF, V8BF.
12974 (arm_mangle_type): Add __bf16.
12975 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
12976 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
12977 arm_bf16_ptr_type_node.
12978 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
12979 define_split between ARM registers.
12980 * config/arm/arm_bf16.h: New file.
12981 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
12982 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
12983 (VQXMOV): Add V8BF.
12984 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
12985 * config/arm/vfp.md: Add BFmode to movhf patterns.
12987 2020-01-16 Mihail Ionescu <mihail.ionescu@arm.com>
12988 Andre Vieira <andre.simoesdiasvieira@arm.com>
12990 * config/arm/arm-cpus.in (mve, mve_float): New features.
12991 (dsp, mve, mve.fp): New options.
12992 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
12993 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
12994 * doc/invoke.texi: Document the armv8.1-m mve and dps options.
12996 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
12997 Thomas Preud'homme <thomas.preudhomme@arm.com>
12999 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
13000 Armv8-M Mainline.
13001 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
13002 error for using -mcmse when targeting Armv8.1-M Mainline.
13004 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13005 Thomas Preud'homme <thomas.preudhomme@arm.com>
13007 * config/arm/arm.md (nonsecure_call_internal): Do not force memory
13008 address in r4 when targeting Armv8.1-M Mainline.
13009 (nonsecure_call_value_internal): Likewise.
13010 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
13011 a register match_operand again. Emit BLXNS when targeting
13012 Armv8.1-M Mainline.
13013 (nonsecure_call_value_reg_thumb2): Likewise.
13015 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13016 Thomas Preud'homme <thomas.preudhomme@arm.com>
13018 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
13019 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
13020 variable as true when floating-point ABI is not hard. Replace
13021 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
13022 Generate VLSTM and VLLDM instruction respectively before and
13023 after a function call to cmse_nonsecure_call function.
13024 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
13025 (VUNSPEC_VLLDM): Likewise.
13026 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
13027 (lazy_load_multiple_insn): Likewise.
13029 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13030 Thomas Preud'homme <thomas.preudhomme@arm.com>
13032 * config/arm/arm.c (vfp_emit_fstmd): Declare early.
13033 (arm_emit_vfp_multi_reg_pop): Likewise.
13034 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
13035 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and
13036 restore callee-saved VFP registers.
13038 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13039 Thomas Preud'homme <thomas.preudhomme@arm.com>
13041 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
13042 (cmse_nonsecure_call_clear_caller_saved): Rename into ...
13043 (cmse_nonsecure_call_inline_register_clear): This. Save and clear
13044 callee-saved GPRs as well as clear ip register before doing a nonsecure
13045 call then restore callee-saved GPRs after it when targeting
13046 Armv8.1-M Mainline.
13047 (arm_reorg): Adapt to function rename.
13049 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13050 Thomas Preud'homme <thomas.preudhomme@arm.com>
13052 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
13053 * config/arm/arm.c (clear_operation_p): Extend to be able to check a
13054 clear_vfp_multiple pattern based on a new vfp parameter.
13055 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
13056 targeting Armv8.1-M Mainline.
13057 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers
13058 unconditionally when targeting Armv8.1-M Mainline architecture. Check
13059 whether VFP registers are available before looking call_used_regs for a
13060 VFP register.
13061 * config/arm/predicates.md (clear_multiple_operation): Adapt to change
13062 of prototype of clear_operation_p.
13063 (clear_vfp_multiple_operation): New predicate.
13064 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
13065 * config/arm/vfp.md (clear_vfp_multiple): New define_insn.
13067 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13068 Thomas Preud'homme <thomas.preudhomme@arm.com>
13070 * config/arm/arm-protos.h (clear_operation_p): Declare.
13071 * config/arm/arm.c (clear_operation_p): New function.
13072 (cmse_clear_registers): Generate clear_multiple instruction pattern if
13073 targeting Armv8.1-M Mainline or successor.
13074 (output_return_instruction): Only output APSR register clearing if
13075 Armv8.1-M Mainline instructions not available.
13076 (thumb_exit): Likewise.
13077 * config/arm/predicates.md (clear_multiple_operation): New predicate.
13078 * config/arm/thumb2.md (clear_apsr): New define_insn.
13079 (clear_multiple): Likewise.
13080 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.
13082 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13083 Thomas Preud'homme <thomas.preudhomme@arm.com>
13085 * config/arm/arm.c (fp_sysreg_names): Declare and define.
13086 (use_return_insn): Also return false for Armv8.1-M Mainline.
13087 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M
13088 Mainline instructions are available.
13089 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS
13090 when targeting Armv8.1-M Mainline Security Extensions.
13091 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
13092 Mainline entry function.
13093 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
13094 targeting Armv8.1-M Mainline or successor.
13095 (arm_expand_epilogue): Fix indentation of caller-saved register
13096 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline
13097 entry function.
13098 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
13099 (FP_SYSREGS): Likewise.
13100 (enum vfp_sysregs_encoding): Define enum.
13101 (fp_sysreg_names): Declare.
13102 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
13103 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
13104 (pop_fpsysreg_insn): Likewise.
13106 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13107 Thomas Preud'homme <thomas.preudhomme@arm.com>
13109 * config/arm/arm-cpus.in (armv8_1m_main): New feature.
13110 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
13111 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
13112 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
13113 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
13114 (ARMv8_1m_main): New feature group.
13115 (armv8.1-m.main): New architecture.
13116 * config/arm/arm-tables.opt: Regenerate.
13117 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
13118 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
13119 (arm_options_perform_arch_sanity_checks): Error out when targeting
13120 Armv8.1-M Mainline Security Extensions.
13121 * config/arm/arm.h (arm_arch8_1m_main): Declare.
13123 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13125 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
13126 aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
13127 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
13128 aarch64_bfdot_laneq): New.
13129 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
13130 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
13131 vbfdotq_laneq_f32): New.
13132 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
13133 VBFMLA_W, VBF): New.
13134 (isquadop): Add V4BF, V8BF.
13136 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13138 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
13139 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
13140 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
13141 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
13142 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
13143 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
13144 usdot_laneq, sudot_lane,sudot_laneq): New.
13145 * config/aarch64/aarch64-simd.md (aarch64_usdot): New.
13146 (aarch64_<sur>dot_lane): New.
13147 * config/aarch64/arm_neon.h (vusdot_s32): New.
13148 (vusdotq_s32): New.
13149 (vusdot_lane_s32): New.
13150 (vsudot_lane_s32): New.
13151 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
13152 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
13154 2020-01-16 Martin Liska <mliska@suse.cz>
13156 * value-prof.c (dump_histogram_value): Fix
13157 obvious spacing issue.
13159 2020-01-16 Andrew Pinski <apinski@marvell.com>
13161 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
13162 !storage_order_barrier_p.
13164 2020-01-16 Andrew Pinski <apinski@marvell.com>
13166 * sched-int.h (_dep): Add unused bit-field field for the padding.
13167 * sched-deps.c (init_dep_1): Init unused field.
13169 2020-01-16 Andrew Pinski <apinski@marvell.com>
13171 * optabs.h (create_expand_operand): Initialize target field also.
13173 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
13175 PR tree-optimization/92429
13176 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
13177 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
13178 control folding.
13179 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
13180 tree.
13182 2020-01-16 Richard Sandiford <richard.sandiford@arm.com>
13184 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
13185 aarch64_sve_int_mode to each mode.
13187 2020-01-15 David Malcolm <dmalcolm@redhat.com>
13189 * doc/analyzer.texi (Overview): Add note about
13190 -fdump-ipa-analyzer.
13192 2020-01-15 Wilco Dijkstra <wdijkstr@arm.com>
13194 PR tree-optimization/93231
13195 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
13196 input_type is unsigned. Use tree_to_shwi for shift constant.
13197 Check CST_STRING element size is CHAR_TYPE_SIZE bits.
13198 (simplify_count_trailing_zeroes): Add test to handle known non-zero
13199 inputs more efficiently.
13201 2020-01-15 Uroš Bizjak <ubizjak@gmail.com>
13203 * config/i386/i386.md (*movsf_internal): Do not require
13204 SSE2 ISA for alternatives 14 and 15.
13206 2020-01-15 Richard Biener <rguenther@suse.de>
13208 PR middle-end/93273
13209 * tree-eh.c (sink_clobbers): If we already visited the destination
13210 block do not defer insertion.
13211 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
13212 the purpose of defered insertion.
13214 2020-01-15 Jakub Jelinek <jakub@redhat.com>
13216 * BASE-VER: Bump to 10.0.1.
13218 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
13220 PR tree-optimization/93247
13221 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
13222 type of the stmt that we're going to vectorize.
13224 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
13226 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
13227 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
13228 type from the lhs.
13230 2020-01-15 Martin Liska <mliska@suse.cz>
13232 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
13233 2 calls of streamer_read_hwi in a function call.
13235 2020-01-15 Richard Biener <rguenther@suse.de>
13237 * alias.c (record_alias_subset): Avoid redundant work when
13238 subset is already recorded.
13240 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13242 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
13243 the analyzer options provide CWE identifiers.
13245 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13247 * tree-diagnostic-path.cc (path_summary::event_range::print):
13248 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
13249 using get_pure_location.
13251 2020-01-15 Jakub Jelinek <jakub@redhat.com>
13253 PR tree-optimization/93262
13254 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
13255 perform head trimming only if the last argument is constant,
13256 either all ones, or larger or equal to head trim, in the latter
13257 case decrease the last argument by head_trim.
13259 PR tree-optimization/93249
13260 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
13261 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to
13262 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
13263 perform head trim unless we can prove there are no '\0' chars
13264 from the source among the first head_trim chars.
13266 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13268 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.
13270 2020-01-15 Jakub Jelinek <jakub@redhat.com>
13272 PR target/93009
13273 * config/i386/sse.md
13274 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1,
13275 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1,
13276 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1,
13277 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use
13278 just a single alternative instead of two, make operands 1 and 2
13279 commutative.
13281 2020-01-14 Jan Hubicka <hubicka@ucw.cz>
13283 PR lto/91576
13284 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
13285 TYPE_MODE.
13287 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13289 * Makefile.in (lang_opt_files): Add analyzer.opt.
13290 (ANALYZER_OBJS): New.
13291 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o,
13292 tristate.o and ANALYZER_OBJS.
13293 (TEXI_GCCINT_FILES): Add analyzer.texi.
13294 * common.opt (-fanalyzer): New driver option.
13295 * config.in: Regenerate.
13296 * configure: Regenerate.
13297 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option.
13298 (gccdepdir): Also create depdir for "analyzer" subdir.
13299 * digraph.cc: New file.
13300 * digraph.h: New file.
13301 * doc/analyzer.texi: New file.
13302 * doc/gccint.texi ("Static Analyzer") New menu item.
13303 (analyzer.texi): Include it.
13304 * doc/invoke.texi ("Static Analyzer Options"): New list and new section.
13305 ("Warning Options"): Add static analysis warnings to the list.
13306 (-Wno-analyzer-double-fclose): New option.
13307 (-Wno-analyzer-double-free): New option.
13308 (-Wno-analyzer-exposure-through-output-file): New option.
13309 (-Wno-analyzer-file-leak): New option.
13310 (-Wno-analyzer-free-of-non-heap): New option.
13311 (-Wno-analyzer-malloc-leak): New option.
13312 (-Wno-analyzer-possible-null-argument): New option.
13313 (-Wno-analyzer-possible-null-dereference): New option.
13314 (-Wno-analyzer-null-argument): New option.
13315 (-Wno-analyzer-null-dereference): New option.
13316 (-Wno-analyzer-stale-setjmp-buffer): New option.
13317 (-Wno-analyzer-tainted-array-index): New option.
13318 (-Wno-analyzer-use-after-free): New option.
13319 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option.
13320 (-Wno-analyzer-use-of-uninitialized-value): New option.
13321 (-Wanalyzer-too-complex): New option.
13322 (-fanalyzer-call-summaries): New warning.
13323 (-fanalyzer-checker=): New warning.
13324 (-fanalyzer-fine-grained): New warning.
13325 (-fno-analyzer-state-merge): New warning.
13326 (-fno-analyzer-state-purge): New warning.
13327 (-fanalyzer-transitivity): New warning.
13328 (-fanalyzer-verbose-edges): New warning.
13329 (-fanalyzer-verbose-state-changes): New warning.
13330 (-fanalyzer-verbosity=): New warning.
13331 (-fdump-analyzer): New warning.
13332 (-fdump-analyzer-callgraph): New warning.
13333 (-fdump-analyzer-exploded-graph): New warning.
13334 (-fdump-analyzer-exploded-nodes): New warning.
13335 (-fdump-analyzer-exploded-nodes-2): New warning.
13336 (-fdump-analyzer-exploded-nodes-3): New warning.
13337 (-fdump-analyzer-supergraph): New warning.
13338 * doc/sourcebuild.texi (dg-require-dot): New.
13339 (dg-check-dot): New.
13340 * gdbinit.in (break-on-saved-diagnostic): New command.
13341 * graphviz.cc: New file.
13342 * graphviz.h: New file.
13343 * ordered-hash-map-tests.cc: New file.
13344 * ordered-hash-map.h: New file.
13345 * passes.def (pass_analyzer): Add before
13346 pass_ipa_whole_program_visibility.
13347 * selftest-run-tests.c (selftest::run_tests): Call
13348 selftest::ordered_hash_map_tests_cc_tests.
13349 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New
13350 decl.
13351 * shortest-paths.h: New file.
13352 * timevar.def (TV_ANALYZER): New timevar.
13353 (TV_ANALYZER_SUPERGRAPH): Likewise.
13354 (TV_ANALYZER_STATE_PURGE): Likewise.
13355 (TV_ANALYZER_PLAN): Likewise.
13356 (TV_ANALYZER_SCC): Likewise.
13357 (TV_ANALYZER_WORKLIST): Likewise.
13358 (TV_ANALYZER_DUMP): Likewise.
13359 (TV_ANALYZER_DIAGNOSTICS): Likewise.
13360 (TV_ANALYZER_SHORTEST_PATHS): Likewise.
13361 * tree-pass.h (make_pass_analyzer): New decl.
13362 * tristate.cc: New file.
13363 * tristate.h: New file.
13365 2020-01-14 Uroš Bizjak <ubizjak@gmail.com>
13367 PR target/93254
13368 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for
13369 alternatives 9 and 10.
13371 2020-01-14 David Malcolm <dmalcolm@redhat.com>
13373 * attribs.c (excl_hash_traits::empty_zero_p): New static constant.
13374 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise.
13375 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise.
13376 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
13377 (selftest::hash_map_tests_c_tests): Call it.
13378 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p):
13379 New static constant, using the value of = H::empty_zero_p.
13380 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value
13381 from default_hash_traits <Value>.
13382 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value
13383 from Traits.
13384 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise.
13385 * hash-table.h (hash_table::alloc_entries): Guard the loop of
13386 calls to mark_empty with !Descriptor::empty_zero_p.
13387 (hash_table::empty_slow): Conditionalize the memset call with a
13388 check that Descriptor::empty_zero_p; otherwise, loop through the
13389 entries calling mark_empty on them.
13390 * hash-traits.h (int_hash::empty_zero_p): New static constant.
13391 (pointer_hash::empty_zero_p): Likewise.
13392 (pair_hash::empty_zero_p): Likewise.
13393 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p):
13394 Likewise.
13395 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise.
13396 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise.
13397 * profile.c (location_triplet_hash::empty_zero_p): Likewise.
13398 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise.
13399 (sanopt_tree_couple_hash::empty_zero_p): Likewise.
13400 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise.
13401 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise.
13402 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise.
13403 * tree-vectorizer.h
13404 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p):
13405 Likewise.
13407 2020-01-14 Kewen Lin <linkw@gcc.gnu.org>
13409 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return,
13410 fix typo on return value.
13412 2020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
13414 PR ipa/69678
13415 * cgraph.c (symbol_table::create_edge): Init speculative_id and
13416 target_prob.
13417 (cgraph_edge::make_speculative): Add param for setting speculative_id
13418 and target_prob.
13419 (cgraph_edge::speculative_call_info): Update comments and find reference
13420 by speculative_id for multiple indirect targets.
13421 (cgraph_edge::resolve_speculation): Decrease the speculations
13422 for indirect edge, drop it's speculative if not direct target
13423 left. Update comments.
13424 (cgraph_edge::redirect_call_stmt_to_callee): Likewise.
13425 (cgraph_node::dump): Print num_speculative_call_targets.
13426 (cgraph_node::verify_node): Don't report error if speculative
13427 edge not include statement.
13428 (cgraph_edge::num_speculative_call_targets_p): New function.
13429 * cgraph.h (int common_target_id): Remove.
13430 (int common_target_probability): Remove.
13431 (num_speculative_call_targets): New variable.
13432 (make_speculative): Add param for setting speculative_id.
13433 (cgraph_edge::num_speculative_call_targets_p): New declare.
13434 (target_prob): New variable.
13435 (speculative_id): New variable.
13436 * ipa-fnsummary.c (analyze_function_body): Create and duplicate
13437 call summaries for multiple speculative call targets.
13438 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id.
13439 * ipa-profile.c (struct speculative_call_target): New struct.
13440 (class speculative_call_summary): New class.
13441 (class speculative_call_summaries): New class.
13442 (call_sums): New variable.
13443 (ipa_profile_generate_summary): Generate indirect multiple targets summaries.
13444 (ipa_profile_write_edge_summary): New function.
13445 (ipa_profile_write_summary): Stream out indirect multiple targets summaries.
13446 (ipa_profile_dump_all_summaries): New function.
13447 (ipa_profile_read_edge_summary): New function.
13448 (ipa_profile_read_summary_section): New function.
13449 (ipa_profile_read_summary): Stream in indirect multiple targets summaries.
13450 (ipa_profile): Generate num_speculative_call_targets from
13451 profile summaries.
13452 * ipa-ref.h (speculative_id): New variable.
13453 * ipa-utils.c (ipa_merge_profiles): Update with target_prob.
13454 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and
13455 common_target_probability. Stream out speculative_id and
13456 num_speculative_call_targets.
13457 (input_edge): Likewise.
13458 * predict.c (dump_prediction): Remove edges count assert to be
13459 precise.
13460 * symtab.c (symtab_node::create_reference): Init speculative_id.
13461 (symtab_node::clone_references): Clone speculative_id.
13462 (symtab_node::clone_referring): Clone speculative_id.
13463 (symtab_node::clone_reference): Clone speculative_id.
13464 (symtab_node::clear_stmts_in_references): Clear speculative_id.
13465 * tree-inline.c (copy_bb): Duplicate all the speculative edges
13466 if indirect call contains multiple speculative targets.
13467 * value-prof.h (check_ic_target): Remove.
13468 * value-prof.c (gimple_value_profile_transformations):
13469 Use void function gimple_ic_transform.
13470 * value-prof.c (gimple_ic_transform): Handle topn case.
13471 Fix comment typos. Change it to a void function.
13473 2020-01-13 Andrew Pinski <apinski@marvell.com>
13475 * config/aarch64/aarch64-cores.def (octeontx2): New define.
13476 (octeontx2t98): New define.
13477 (octeontx2t96): New define.
13478 (octeontx2t93): New define.
13479 (octeontx2f95): New define.
13480 (octeontx2f95n): New define.
13481 (octeontx2f95mm): New define.
13482 * config/aarch64/aarch64-tune.md: Regenerate.
13483 * doc/invoke.texi (-mcpu=): Document the new cpu types.
13485 2020-01-13 Jason Merrill <jason@redhat.com>
13487 PR c++/33799 - destroy return value if local cleanup throws.
13488 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR.
13490 2020-01-13 Martin Liska <mliska@suse.cz>
13492 * ipa-cp.c (get_max_overall_size): Use newly
13493 renamed param param_ipa_cp_unit_growth.
13494 * params.opt: Remove legacy param name.
13496 2020-01-13 Martin Sebor <msebor@redhat.com>
13498 PR tree-optimization/93213
13499 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul
13500 stores to be eliminated.
13502 2020-01-13 Martin Liska <mliska@suse.cz>
13504 * opts.c (print_help): Do not print CL_PARAM
13505 and CL_WARNING for CL_OPTIMIZATION.
13507 2020-01-13 Jonathan Wakely <jwakely@redhat.com>
13509 PR driver/92757
13510 * doc/invoke.texi (Warning Options): Add caveat about some warnings
13511 depending on optimization settings.
13513 2020-01-13 Jakub Jelinek <jakub@redhat.com>
13515 PR tree-optimization/90838
13516 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
13517 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro
13518 argument rather than to initialize temporary for targets that
13519 don't use the mode argument at all. Initialize ctzval to avoid
13520 warning at -O0.
13522 2020-01-10 Thomas Schwinge <thomas@codesourcery.com>
13524 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition.
13525 * tree-core.h: Document it.
13526 * gimplify.c (gimplify_omp_workshare): Set it.
13527 * omp-low.c (lower_omp_target): Use it.
13528 * tree-pretty-print.c (dump_omp_clause): Print it.
13530 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>:
13531 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'.
13533 2020-01-10 David Malcolm <dmalcolm@redhat.com>
13535 * Makefile.in (OBJS): Add tree-diagnostic-path.o.
13536 * common.opt (fdiagnostics-path-format=): New option.
13537 (diagnostic_path_format): New enum.
13538 (fdiagnostics-show-path-depths): New option.
13539 * coretypes.h (diagnostic_event_id_t): New forward decl.
13540 * diagnostic-color.c (color_dict): Add "path".
13541 * diagnostic-event-id.h: New file.
13542 * diagnostic-format-json.cc (json_from_expanded_location): Make
13543 non-static.
13544 (json_end_diagnostic): Call context->make_json_for_path if it
13545 exists and the diagnostic has a path.
13546 (diagnostic_output_format_init): Clear context->print_path.
13547 * diagnostic-path.h: New file.
13548 * diagnostic-show-locus.c (colorizer::set_range): Special-case
13549 when printing a run of events in a diagnostic_path so that they
13550 all get the same color.
13551 (layout::m_diagnostic_path_p): New field.
13552 (layout::layout): Initialize it.
13553 (layout::print_any_labels): Don't colorize the label text for an
13554 event in a diagnostic_path.
13555 (gcc_rich_location::add_location_if_nearby): Add
13556 "restrict_to_current_line_spans" and "label" params. Pass the
13557 former to layout.maybe_add_location_range; pass the latter
13558 when calling add_range.
13559 * diagnostic.c: Include "diagnostic-path.h".
13560 (diagnostic_initialize): Initialize context->path_format and
13561 context->show_path_depths.
13562 (diagnostic_show_any_path): New function.
13563 (diagnostic_path::interprocedural_p): New function.
13564 (diagnostic_report_diagnostic): Call diagnostic_show_any_path.
13565 (simple_diagnostic_path::num_events): New function.
13566 (simple_diagnostic_path::get_event): New function.
13567 (simple_diagnostic_path::add_event): New function.
13568 (simple_diagnostic_event::simple_diagnostic_event): New ctor.
13569 (simple_diagnostic_event::~simple_diagnostic_event): New dtor.
13570 (debug): New overload taking a diagnostic_path *.
13571 * diagnostic.def (DK_DIAGNOSTIC_PATH): New.
13572 * diagnostic.h (enum diagnostic_path_format): New enum.
13573 (json::value): New forward decl.
13574 (diagnostic_context::path_format): New field.
13575 (diagnostic_context::show_path_depths): New field.
13576 (diagnostic_context::print_path): New callback field.
13577 (diagnostic_context::make_json_for_path): New callback field.
13578 (diagnostic_show_any_path): New decl.
13579 (json_from_expanded_location): New decl.
13580 * doc/invoke.texi (-fdiagnostics-path-format=): New option.
13581 (-fdiagnostics-show-path-depths): New option.
13582 (-fdiagnostics-color): Add "path" to description of default
13583 GCC_COLORS; describe it.
13584 (-fdiagnostics-format=json): Document how diagnostic paths are
13585 represented in the JSON output format.
13586 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
13587 Add optional params "restrict_to_current_line_spans" and "label".
13588 * opts.c (common_handle_option): Handle
13589 OPT_fdiagnostics_path_format_ and
13590 OPT_fdiagnostics_show_path_depths.
13591 * pretty-print.c: Include "diagnostic-event-id.h".
13592 (pp_format): Implement "%@" format code for printing
13593 diagnostic_event_id_t *.
13594 (selftest::test_pp_format): Add tests for "%@".
13595 * selftest-run-tests.c (selftest::run_tests): Call
13596 selftest::tree_diagnostic_path_cc_tests.
13597 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl.
13598 * toplev.c (general_init): Initialize global_dc->path_format and
13599 global_dc->show_path_depths.
13600 * tree-diagnostic-path.cc: New file.
13601 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make
13602 non-static. Drop "diagnostic" param in favor of storing the
13603 original value of "where" and re-using it.
13604 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of
13605 maybe_unwind_expanded_macro_loc.
13606 (tree_diagnostics_defaults): Initialize context->print_path and
13607 context->make_json_for_path.
13608 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New
13609 decl.
13610 (default_tree_make_json_for_path): New decl.
13611 (maybe_unwind_expanded_macro_loc): New decl.
13613 2020-01-10 Jakub Jelinek <jakub@redhat.com>
13615 PR tree-optimization/93210
13616 * fold-const.h (native_encode_initializer,
13617 can_native_interpret_type_p): Declare.
13618 * fold-const.c (native_encode_string): Fix up handling with off != -1,
13619 simplify.
13620 (native_encode_initializer): New function, moved from dwarf2out.c.
13621 Adjust to native_encode_expr compatible arguments, including dry-run
13622 and partial extraction modes. Don't handle STRING_CST.
13623 (can_native_interpret_type_p): No longer static.
13624 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
13625 offset / BITS_PER_UNIT fits into int and don't call it if
13626 can_native_interpret_type_p fails. If suboff is NULL and for
13627 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
13628 native_encode_initializer.
13629 (fold_const_aggregate_ref_1): Formatting fix.
13630 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
13631 (tree_add_const_value_attribute): Adjust caller.
13633 PR tree-optimization/90838
13634 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
13635 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
13636 CTZ_DEFINED_VALUE_AT_ZERO.
13638 2020-01-10 Vladimir Makarov <vmakarov@redhat.com>
13640 PR inline-asm/93027
13641 * lra-constraints.c (match_reload): Permit input operands have the
13642 same mode as output while other input operands have a different
13643 mode.
13645 2020-01-10 Wilco Dijkstra <wdijkstr@arm.com>
13647 PR tree-optimization/90838
13648 * tree-ssa-forwprop.c (check_ctz_array): Add new function.
13649 (check_ctz_string): Likewise.
13650 (optimize_count_trailing_zeroes): Likewise.
13651 (simplify_count_trailing_zeroes): Likewise.
13652 (pass_forwprop::execute): Try ctz simplification.
13653 * match.pd: Add matching for ctz idioms.
13655 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13657 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
13658 for target hook.
13659 (aarch64_invalid_unary_op): New function for target hook.
13660 (aarch64_invalid_binary_op): New function for target hook.
13662 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
13664 * config.gcc: Add arm_bf16.h.
13665 * config/aarch64/aarch64-builtins.c
13666 (aarch64_simd_builtin_std_type): Add BFmode.
13667 (aarch64_init_simd_builtin_types): Define element types for vector
13668 types.
13669 (aarch64_init_bf16_types): New function.
13670 (aarch64_general_init_builtins): Add arm_init_bf16_types function call.
13671 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
13672 modes.
13673 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
13674 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
13675 patterns.
13676 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
13677 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
13678 * config/aarch64/aarch64.c
13679 (aarch64_classify_vector_mode): Add support for BF types.
13680 (aarch64_gimplify_va_arg_expr): Add support for BF types.
13681 (aarch64_vq_mode): Add support for BF types.
13682 (aarch64_simd_container_mode): Add support for BF types.
13683 (aarch64_mangle_type): Add support for BF scalar type.
13684 * config/aarch64/aarch64.md: Add BFmode to movhf pattern.
13685 * config/aarch64/arm_bf16.h: New file.
13686 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
13687 * config/aarch64/iterators.md: Add BF types to mode attributes.
13688 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
13690 2020-01-10 Jason Merrill <jason@redhat.com>
13692 PR c++/93173 - incorrect tree sharing.
13693 * gimplify.c (copy_if_shared): No longer static.
13694 * gimplify.h: Declare it.
13696 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
13698 * doc/invoke.texi (-msve-vector-bits=): Document that
13699 -msve-vector-bits=128 now generates VL-specific code for
13700 little-endian targets.
13701 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
13702 build_vector_type_for_mode to construct the data vector types.
13703 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
13704 VL-specific code for -msve-vector-bits=128 on little-endian targets.
13705 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes
13706 for 128-bit vectors.
13708 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
13710 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
13711 invocation.
13713 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
13715 * config/aarch64/aarch64-builtins.c
13716 (aarch64_builtin_vectorized_function): Check for specific vector modes,
13717 rather than checking the number of elements and the element mode.
13719 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
13721 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use
13722 get_related_vectype_for_scalar_type rather than build_vector_type
13723 to create the index type for a conditional reduction.
13725 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
13727 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
13728 for any type of gather or scatter, including strided accesses.
13730 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
13732 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
13733 comment.
13735 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
13737 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
13738 get_dr_vinfo_offset
13739 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init
13740 parameter and its use to reset DR_OFFSET's.
13741 (vect_transform_loop): Remove orig_drs_init argument.
13742 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
13743 member of dr_vec_info rather than the offset of the associated
13744 data_reference's innermost_loop_behavior.
13745 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
13746 (vect_do_peeling): Remove orig_drs_init parameter and its construction.
13747 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
13748 get_dr_vinfo_offset.
13749 (vectorizable_store): Likewise.
13750 (vectorizable_load): Likewise.
13752 2020-01-10 Richard Biener <rguenther@suse.de>
13754 * gimple-ssa-store-merging
13755 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info.
13757 2020-01-10 Martin Liska <mliska@suse.cz>
13759 PR ipa/93217
13760 * ipa-inline-analysis.c (offline_size): Make proper parenthesis
13761 encapsulation that was there before r280040.
13763 2020-01-10 Richard Biener <rguenther@suse.de>
13765 PR middle-end/93199
13766 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
13767 sequences to avoid walking them again for secondary opportunities.
13768 (pass_lower_eh_dispatch::execute): Instead actually insert
13769 them here.
13771 2020-01-10 Richard Biener <rguenther@suse.de>
13773 PR middle-end/93199
13774 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
13775 (cleanup_all_empty_eh): Walk landing pads in reverse order to
13776 avoid quadraticness.
13778 2020-01-10 Martin Jambor <mjambor@suse.cz>
13780 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
13781 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
13782 to get param_ipa_sra_max_replacements.
13783 (param_splitting_across_edge): Pass the caller to
13784 pull_accesses_from_callee.
13786 2020-01-10 Martin Jambor <mjambor@suse.cz>
13788 * params.opt (param_ipcp_unit_growth): Mark as Optimization.
13789 * ipa-cp.c (max_new_size): Removed.
13790 (orig_overall_size): New variable.
13791 (get_max_overall_size): New function.
13792 (estimate_local_effects): Use it. Adjust dump.
13793 (decide_about_value): Likewise.
13794 (ipcp_propagate_stage): Do not calculate max_new_size, just store
13795 orig_overall_size. Adjust dump.
13796 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.
13798 2020-01-10 Martin Jambor <mjambor@suse.cz>
13800 * params.opt (param_ipa_max_agg_items): Mark as Optimization
13801 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
13802 instead of param_ipa_max_agg_items.
13803 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from
13804 optimization info for the callee.
13806 2020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com>
13808 * lto-streamer-in.c (input_function): Remove streamed-in inline debug
13809 markers if debug_inline_points is false.
13811 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
13813 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
13814 extra_objs.
13815 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
13816 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
13817 aarch64-sve-builtins-sve2.h.
13818 (aarch64-sve-builtins-sve2.o): New rule.
13819 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
13820 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
13821 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
13822 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
13823 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
13824 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
13825 TARGET_SVE2_SM4.
13826 * config/aarch64/aarch64-sve.md: Update comments with SVE2
13827 instructions that are handled here.
13828 (@cond_asrd<mode>): Generalize to...
13829 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
13830 (*cond_asrd<mode>_2): Generalize to...
13831 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
13832 (*cond_asrd<mode>_z): Generalize to...
13833 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
13834 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
13835 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
13836 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
13837 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
13838 pattern.
13839 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
13840 (@aarch64_scatter_stnt<mode>): Likewise.
13841 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
13842 (@aarch64_mul_lane_<mode>): Likewise.
13843 (@aarch64_sve_suqadd<mode>_const): Likewise.
13844 (*<sur>h<addsub><mode>): Generalize to...
13845 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
13846 new pattern.
13847 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
13848 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
13849 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
13850 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
13851 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
13852 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
13853 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
13854 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
13855 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
13856 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
13857 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
13858 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
13859 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
13860 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
13861 (@aarch64_sve_add_mul_lane_<mode>): Likewise.
13862 (@aarch64_sve_sub_mul_lane_<mode>): Likewise.
13863 (@aarch64_sve2_xar<mode>): Likewise.
13864 (@aarch64_sve2_bcax<mode>): Likewise.
13865 (*aarch64_sve2_eor3<mode>): Rename to...
13866 (@aarch64_sve2_eor3<mode>): ...this.
13867 (@aarch64_sve2_bsl<mode>): New expander.
13868 (@aarch64_sve2_nbsl<mode>): Likewise.
13869 (@aarch64_sve2_bsl1n<mode>): Likewise.
13870 (@aarch64_sve2_bsl2n<mode>): Likewise.
13871 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
13872 (*aarch64_sve2_sra<mode>): Add MOVPRFX support.
13873 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
13874 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
13875 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
13876 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
13877 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
13878 (<su>mull<bt><Vwide>): Generalize to...
13879 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
13880 pattern.
13881 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
13882 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
13883 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
13884 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
13885 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
13886 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
13887 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
13888 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
13889 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
13890 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
13891 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
13892 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
13893 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
13894 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
13895 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
13896 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
13897 (<SHRNB:r>shrnb<mode>): Generalize to...
13898 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
13899 new pattern.
13900 (<SHRNT:r>shrnt<mode>): Generalize to...
13901 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
13902 new pattern.
13903 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
13904 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
13905 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
13906 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
13907 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
13908 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
13909 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
13910 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
13911 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
13912 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
13913 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
13914 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
13915 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
13916 (@aarch64_sve2_cvtnt<mode>): Likewise.
13917 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
13918 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
13919 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
13920 (@aarch64_sve2_cvtxnt<mode>): Likewise.
13921 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
13922 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
13923 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
13924 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
13925 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
13926 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
13927 (@aarch64_sve2_pmul<mode>): Likewise.
13928 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
13929 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
13930 (@aarch64_sve2_tbl2<mode>): Likewise.
13931 (@aarch64_sve2_tbx<mode>): Likewise.
13932 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
13933 (@aarch64_sve2_histcnt<mode>): Likewise.
13934 (@aarch64_sve2_histseg<mode>): Likewise.
13935 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
13936 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
13937 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
13938 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
13939 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
13940 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
13941 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
13942 (<su>mulh<r>s<mode>3): Update after above pattern name changes.
13943 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
13944 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
13945 (SVE2_PMULL_PAIR_I): New mode iterators.
13946 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
13947 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
13948 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
13949 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
13950 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
13951 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
13952 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
13953 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
13954 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
13955 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
13956 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
13957 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
13958 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
13959 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
13960 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
13961 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
13962 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
13963 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
13964 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
13965 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
13966 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
13967 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
13968 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
13969 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
13970 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
13971 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
13972 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
13973 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
13974 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
13975 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
13976 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
13977 further down file.
13978 (VNARROW, Ventype): New mode attributes.
13979 (Vewtype): Handle VNx2DI. Fix typo in comment.
13980 (VDOUBLE): New mode attribute.
13981 (sve_lane_con): Handle VNx8HI.
13982 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
13983 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
13984 (sve_int_op, sve_int_op_rev): Handle the above codes.
13985 (sve_pred_int_rhs2_operand): Likewise.
13986 (MULLBT, SHRNB, SHRNT): Delete.
13987 (SVE_INT_SHIFT_IMM): New int iterator.
13988 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
13989 and UNSPEC_WHILEHS for TARGET_SVE2.
13990 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
13991 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
13992 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
13993 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
13994 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
13995 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
13996 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
13997 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
13998 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
13999 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
14000 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
14001 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
14002 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
14003 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
14004 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
14005 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
14006 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
14007 (optab): Handle the new unspecs.
14008 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
14009 and UNSPEC_RSHRNT.
14010 (lr): Handle the new unspecs.
14011 (bt): Delete.
14012 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
14013 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
14014 (sve_int_qsub_op): New int attributes.
14015 (sve_fp_op, rot): Handle the new unspecs.
14016 * config/aarch64/aarch64-sve-builtins.h
14017 (function_resolver::require_matching_pointer_type): Declare.
14018 (function_resolver::resolve_unary): Add an optional boolean argument.
14019 (function_resolver::finish_opt_n_resolution): Add an optional
14020 type_suffix_index argument.
14021 (gimple_folder::redirect_call): Declare.
14022 (gimple_expander::prepare_gather_address_operands): Add an optional
14023 bool parameter.
14024 * config/aarch64/aarch64-sve-builtins.cc: Include
14025 aarch64-sve-builtins-sve2.h.
14026 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
14027 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
14028 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
14029 (TYPES_hsd_integer): Use TYPES_hsd_signed.
14030 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
14031 (TYPES_s_unsigned): Likewise.
14032 (TYPES_s_integer): Use TYPES_s_unsigned.
14033 (TYPES_sd_signed, TYPES_sd_unsigned): New macros.
14034 (TYPES_sd_integer): Use them.
14035 (TYPES_d_unsigned): New macro.
14036 (TYPES_d_integer): Use it.
14037 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
14038 (TYPES_cvt_narrow): Likewise.
14039 (DEF_SVE_TYPES_ARRAY): Include the new types macros above.
14040 (preds_mx): New variable.
14041 (function_builder::add_overloaded_function): Allow the new feature
14042 set to be more restrictive than the original one.
14043 (function_resolver::infer_pointer_type): Remove qualifiers from
14044 the pointer type before printing it.
14045 (function_resolver::require_matching_pointer_type): New function.
14046 (function_resolver::resolve_sv_displacement): Handle functions
14047 that don't support 32-bit vector indices or svint32_t vector offsets.
14048 (function_resolver::finish_opt_n_resolution): Take the inferred type
14049 as a separate argument.
14050 (function_resolver::resolve_unary): Optionally treat all forms in
14051 the same way as normal merging functions.
14052 (gimple_folder::redirect_call): New function.
14053 (function_expander::prepare_gather_address_operands): Add an argument
14054 that says whether scaled forms are available. If they aren't,
14055 handle scaling of vector indices and don't add the extension and
14056 scaling operands.
14057 (function_expander::map_to_unspecs): If aarch64_sve isn't available,
14058 fall back to using cond_* instead.
14059 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
14060 Split out the member variables into...
14061 (rtx_code_function_base): ...this new base class.
14062 (rtx_code_function_rotated): Inherit rtx_code_function_base.
14063 (unspec_based_function): Split out the member variables into...
14064 (unspec_based_function_base): ...this new base class.
14065 (unspec_based_function_rotated): Inherit unspec_based_function_base.
14066 (unspec_based_function_exact_insn): New class.
14067 (unspec_based_add_function, unspec_based_add_lane_function)
14068 (unspec_based_lane_function, unspec_based_pred_function)
14069 (unspec_based_qadd_function, unspec_based_qadd_lane_function)
14070 (unspec_based_qsub_function, unspec_based_qsub_lane_function)
14071 (unspec_based_sub_function, unspec_based_sub_lane_function): New
14072 typedefs.
14073 (unspec_based_fused_function): New class.
14074 (unspec_based_mla_function, unspec_based_mls_function): New typedefs.
14075 (unspec_based_fused_lane_function): New class.
14076 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
14077 typedefs.
14078 (CODE_FOR_MODE1): New macro.
14079 (fixed_insn_function): New class.
14080 (while_comparison): Likewise.
14081 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
14082 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
14083 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
14084 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
14085 (load_gather_sv_restricted, shift_left_imm_long): Declare.
14086 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
14087 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
14088 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
14089 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
14090 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
14091 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
14092 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
14093 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
14094 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
14095 Also add an initial argument for unary_convert_narrowt, regardless
14096 of the predication type.
14097 (build_32_64): Allow loads and stores to specify MODE_none.
14098 (build_sv_index64, build_sv_uint_offset): New functions.
14099 (long_type_suffix): New function.
14100 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
14101 (binary_imm_long_base, load_gather_sv_base): Likewise.
14102 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
14103 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
14104 (unary_narrowb_base, unary_narrowt_base): Likewise.
14105 (binary_long_lane_def, binary_long_lane): New shape.
14106 (binary_long_opt_n_def, binary_long_opt_n): Likewise.
14107 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
14108 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
14109 (binary_to_uint_def, binary_to_uint): Likewise.
14110 (binary_wide_def, binary_wide): Likewise.
14111 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
14112 (compare_def, compare): Likewise.
14113 (compare_ptr_def, compare_ptr): Likewise.
14114 (load_ext_gather_index_restricted_def,
14115 load_ext_gather_index_restricted): Likewise.
14116 (load_ext_gather_offset_restricted_def,
14117 load_ext_gather_offset_restricted): Likewise.
14118 (load_gather_sv_def): Inherit from load_gather_sv_base.
14119 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
14120 (shift_left_imm_def, shift_left_imm): Likewise.
14121 (shift_left_imm_long_def, shift_left_imm_long): Likewise.
14122 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
14123 (store_scatter_index_restricted_def,
14124 store_scatter_index_restricted): Likewise.
14125 (store_scatter_offset_restricted_def,
14126 store_scatter_offset_restricted): Likewise.
14127 (tbl_tuple_def, tbl_tuple): Likewise.
14128 (ternary_long_lane_def, ternary_long_lane): Likewise.
14129 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
14130 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
14131 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
14132 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
14133 (ternary_qq_rotate_def, ternary_qq_rotate): New shape.
14134 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
14135 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
14136 (ternary_uint_def, ternary_uint): Likewise.
14137 (unary_convert): Fix typo in comment.
14138 (unary_convert_narrowt_def, unary_convert_narrowt): New shape.
14139 (unary_long_def, unary_long): Likewise.
14140 (unary_narrowb_def, unary_narrowb): Likewise.
14141 (unary_narrowt_def, unary_narrowt): Likewise.
14142 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
14143 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
14144 (unary_to_int_def, unary_to_int): Likewise.
14145 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
14146 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
14147 (svasrd_impl): Delete.
14148 (svcadd_impl::expand): Handle integer operations too.
14149 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
14150 new functions to derive the unspec numbers.
14151 (svmla_svmls_lane_impl): Replace with...
14152 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
14153 integer operations too.
14154 (svwhile_impl): Rename to...
14155 (svwhilelx_impl): ...this and inherit from while_comparison.
14156 (svasrd): Use unspec_based_function.
14157 (svmla_lane): Use svmla_lane_impl.
14158 (svmls_lane): Use svmls_lane_impl.
14159 (svrecpe, svrsqrte): Handle unsigned integer operations too.
14160 (svwhilele, svwhilelt): Use svwhilelx_impl.
14161 * config/aarch64/aarch64-sve-builtins-sve2.h: New file.
14162 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
14163 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
14164 * config/aarch64/aarch64-sve-builtins.def: Include
14165 aarch64-sve-builtins-sve2.def.
14167 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14169 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
14170 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
14171 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
14172 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar
14173 immediates as well as vector ones.
14174 * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
14175 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
14176 (aarch64_sve_qsub_immediate): Update calls accordingly.
14178 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14180 * config/aarch64/aarch64-sve2.md: Add banner comments.
14181 (<su>mulh<r>s<mode>3): Move further up file.
14182 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
14183 (*aarch64_sve2_sra<mode>): Move further down file.
14184 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
14186 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14188 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
14189 and UNSPEC_WHILEWR.
14190 (while_optab_cmp): Handle them.
14191 * config/aarch64/aarch64-sve.md
14192 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public
14193 and add a "@" marker.
14194 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it
14195 instead of gen_aarch64_sve2_while_ptest.
14196 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete.
14198 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14200 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to...
14201 (UNSPEC_WHILELE): ...this.
14202 (UNSPEC_WHILE_LO): Rename to...
14203 (UNSPEC_WHILELO): ...this.
14204 (UNSPEC_WHILE_LS): Rename to...
14205 (UNSPEC_WHILELS): ...this.
14206 (UNSPEC_WHILE_LT): Rename to...
14207 (UNSPEC_WHILELT): ...this.
14208 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly.
14209 (cmp_op, while_optab_cmp): Likewise.
14210 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise.
14211 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise.
14212 (svwhilelt): Likewise.
14214 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14216 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete.
14217 (unary_to_uint): Define.
14218 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def)
14219 (unary_count): Rename to...
14220 (unary_to_uint_def, unary_to_uint): ...this.
14221 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly.
14223 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14225 * config/aarch64/aarch64-sve-builtins-functions.h
14226 (code_for_mode_function): New class.
14227 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros.
14228 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl)
14229 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete.
14230 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0.
14231 (svmul_lane, svtmad): Use CODE_FOR_MODE0.
14233 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14235 * config/aarch64/iterators.md (addsub): New code attribute.
14236 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
14237 Re-express as...
14238 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
14239 in the asm string and attributes. Fix indentation.
14240 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
14241 Re-express as...
14242 (@aarch64_sve_<optab><mode>): ...this.
14243 * config/aarch64/aarch64-sve-builtins.h
14244 (function_expander::expand_signed_unpred_op): Delete.
14245 * config/aarch64/aarch64-sve-builtins.cc
14246 (function_expander::expand_signed_unpred_op): Likewise.
14247 (function_expander::map_to_rtx_codes): If the optab isn't defined,
14248 try using code_for_aarch64_sve instead.
14249 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
14250 (svqsub_impl): Likewise.
14251 (svqadd, svqsub): Use rtx_code_function instead.
14253 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14255 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete.
14256 (HADDSUB, sur, addsub): Remove them.
14258 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14260 * tree-nrv.c (pass_return_slot::execute): Handle all internal
14261 functions the same way, rather than singling out those that
14262 aren't mapped directly to optabs.
14264 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
14266 * target.def (compatible_vector_types_p): New target hook.
14267 * hooks.h (hook_bool_const_tree_const_tree_true): Declare.
14268 * hooks.c (hook_bool_const_tree_const_tree_true): New function.
14269 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook.
14270 * doc/tm.texi: Regenerate.
14271 * gimple-expr.c: Include target.h.
14272 (useless_type_conversion_p): Use targetm.compatible_vector_types_p.
14273 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New
14274 function.
14275 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define.
14276 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred):
14277 Use the original predicate if it already has a suitable type.
14279 2020-01-09 Martin Jambor <mjambor@suse.cz>
14281 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct,
14282 resolve_speculation and redirect_call_stmt_to_callee static. Change
14283 return type of set_call_stmt to cgraph_edge *.
14284 * auto-profile.c (afdo_indirect_call): Adjust call to
14285 redirect_call_stmt_to_callee.
14286 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *,
14287 make the this pointer explicit, adjust self-recursive calls and the
14288 call top make_direct. Return the resulting edge.
14289 (cgraph_edge::remove): Make this pointer explicit.
14290 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove.
14291 (cgraph_edge::make_direct): Likewise, adjust call to
14292 resolve_speculation.
14293 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust
14294 call to set_call_stmt.
14295 (cgraph_update_edges_for_call_stmt_node): Update call to
14296 set_call_stmt and remove.
14297 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
14298 Renamed edge to master_edge. Adjusted calls to set_call_stmt.
14299 (cgraph_node::create_edge_including_clones): Moved "first" definition
14300 of edge to the block where it was used. Adjusted calls to
14301 set_call_stmt.
14302 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to
14303 cgraph_edge::remove.
14304 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to
14305 make_direct and redirect_call_stmt_to_callee.
14306 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to
14307 resolve_speculation and make_direct.
14308 * ipa-inline-transform.c (inline_transform): Adjust call to
14309 redirect_call_stmt_to_callee.
14310 (check_speculations_1):: Adjust call to resolve_speculation.
14311 * ipa-inline.c (resolve_noninline_speculation): Adjust call to
14312 resolve-speculation.
14313 (inline_small_functions): Adjust call to resolve_speculation.
14314 (ipa_inline): Likewise.
14315 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to
14316 make_direct.
14317 * ipa-visibility.c (function_and_variable_visibility): Make iteration
14318 safe with regards to edge removal, adjust calls to
14319 redirect_call_stmt_to_callee.
14320 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct
14321 and redirect_call_stmt_to_callee.
14322 * multiple_target.c (create_dispatcher_calls): Adjust call to
14323 redirect_call_stmt_to_callee
14324 (redirect_to_specific_clone): Likewise.
14325 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph):
14326 Adjust calls to cgraph_edge::remove.
14327 * tree-inline.c (copy_bb): Adjust call to set_call_stmt.
14328 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee.
14329 (expand_call_inline): Adjust call to cgraph_edge::remove.
14331 2020-01-09 Martin Liska <mliska@suse.cz>
14333 * params.opt: Set Optimization for
14334 param_max_speculative_devirt_maydefs.
14336 2020-01-09 Martin Sebor <msebor@redhat.com>
14338 PR middle-end/93200
14339 PR fortran/92956
14340 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type.
14342 2020-01-09 Martin Liska <mliska@suse.cz>
14344 * auto-profile.c (auto_profile): Use opt_for_fn
14345 for a parameter.
14346 * ipa-cp.c (ipcp_lattice::add_value): Likewise.
14347 (propagate_vals_across_arith_jfunc): Likewise.
14348 (hint_time_bonus): Likewise.
14349 (incorporate_penalties): Likewise.
14350 (good_cloning_opportunity_p): Likewise.
14351 (perform_estimation_of_a_value): Likewise.
14352 (estimate_local_effects): Likewise.
14353 (ipcp_propagate_stage): Likewise.
14354 * ipa-fnsummary.c (decompose_param_expr): Likewise.
14355 (set_switch_stmt_execution_predicate): Likewise.
14356 (analyze_function_body): Likewise.
14357 * ipa-inline-analysis.c (offline_size): Likewise.
14358 * ipa-inline.c (early_inliner): Likewise.
14359 * ipa-prop.c (ipa_analyze_node): Likewise.
14360 (ipcp_transform_function): Likewise.
14361 * ipa-sra.c (process_scan_results): Likewise.
14362 (ipa_sra_summarize_function): Likewise.
14363 * params.opt: Rename ipcp-unit-growth to
14364 ipa-cp-unit-growth. Add Optimization for various
14365 IPA-related parameters.
14367 2020-01-09 Richard Biener <rguenther@suse.de>
14369 PR middle-end/93054
14370 * gimplify.c (gimplify_expr): Deal with NOP definitions.
14372 2020-01-09 Richard Biener <rguenther@suse.de>
14374 PR tree-optimization/93040
14375 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit.
14377 2020-01-09 Georg-Johann Lay <avr@gjlay.de>
14379 * common/config/avr/avr-common.c (avr_option_optimization_table)
14380 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.
14382 2020-01-09 Martin Liska <mliska@suse.cz>
14384 * cgraphclones.c (symbol_table::materialize_all_clones):
14385 Use cgraph_node::dump_name.
14387 2020-01-09 Jakub Jelinek <jakub@redhat.com>
14389 PR inline-asm/93202
14390 * config/riscv/riscv.c (riscv_print_operand_reloc): Use
14391 output_operand_lossage instead of gcc_unreachable.
14392 * doc/md.texi (riscv f constraint): Fix typo.
14394 PR target/93141
14395 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
14396 SWI. Use <general_hilo_operand> instead of <general_operand>. Use
14397 CONST_SCALAR_INT_P instead of CONST_INT_P.
14398 (*subv<mode>4_1): Rename to ...
14399 (subv<mode>4_1): ... this.
14400 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
14401 define_insn_and_split patterns.
14402 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
14403 patterns.
14405 2020-01-08 David Malcolm <dmalcolm@redhat.com>
14407 * vec.c (class selftest::count_dtor): New class.
14408 (selftest::test_auto_delete_vec): New test.
14409 (selftest::vec_c_tests): Call it.
14410 * vec.h (class auto_delete_vec): New class template.
14411 (auto_delete_vec<T>::~auto_delete_vec): New dtor.
14413 2020-01-08 David Malcolm <dmalcolm@redhat.com>
14415 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap.
14417 2020-01-08 Jim Wilson <jimw@sifive.com>
14419 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out
14420 use of TLS_MODEL_LOCAL_EXEC when not pic.
14422 2020-01-08 David Malcolm <dmalcolm@redhat.com>
14424 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix
14425 memory leak.
14427 2020-01-08 Jakub Jelinek <jakub@redhat.com>
14429 PR target/93187
14430 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2,
14431 *stack_protect_set_3 peephole2): Also check that the second
14432 insns source is general_operand.
14434 PR target/93174
14435 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand
14436 predicate for output operand instead of register_operand.
14437 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with
14438 memory destination and non-memory operands[2].
14440 2020-01-08 Martin Liska <mliska@suse.cz>
14442 * cgraph.c (cgraph_node::dump): Use ::dump_name or
14443 ::dump_asm_name instead of (::name or ::asm_name).
14444 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise.
14445 * cgraphunit.c (walk_polymorphic_call_targets): Likewise.
14446 (analyze_functions): Likewise.
14447 (expand_all_functions): Likewise.
14448 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise.
14449 (propagate_bits_across_jump_function): Likewise.
14450 (dump_profile_updates): Likewise.
14451 (ipcp_store_bits_results): Likewise.
14452 (ipcp_store_vr_results): Likewise.
14453 * ipa-devirt.c (dump_targets): Likewise.
14454 * ipa-fnsummary.c (analyze_function_body): Likewise.
14455 * ipa-hsa.c (check_warn_node_versionable): Likewise.
14456 (process_hsa_functions): Likewise.
14457 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise.
14458 (set_alias_uids): Likewise.
14459 * ipa-inline-transform.c (save_inline_function_body): Likewise.
14460 * ipa-inline.c (recursive_inlining): Likewise.
14461 (inline_to_all_callers_1): Likewise.
14462 (ipa_inline): Likewise.
14463 * ipa-profile.c (ipa_propagate_frequency_1): Likewise.
14464 (ipa_propagate_frequency): Likewise.
14465 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
14466 (remove_described_reference): Likewise.
14467 * ipa-pure-const.c (worse_state): Likewise.
14468 (check_retval_uses): Likewise.
14469 (analyze_function): Likewise.
14470 (propagate_pure_const): Likewise.
14471 (propagate_nothrow): Likewise.
14472 (dump_malloc_lattice): Likewise.
14473 (propagate_malloc): Likewise.
14474 (pass_local_pure_const::execute): Likewise.
14475 * ipa-visibility.c (optimize_weakref): Likewise.
14476 (function_and_variable_visibility): Likewise.
14477 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise.
14478 (ipa_discover_variable_flags): Likewise.
14479 * lto-streamer-out.c (output_function): Likewise.
14480 (output_constructor): Likewise.
14481 * tree-inline.c (copy_bb): Likewise.
14482 * tree-ssa-structalias.c (ipa_pta_execute): Likewise.
14483 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise.
14485 2020-01-08 Richard Biener <rguenther@suse.de>
14487 PR middle-end/93199
14488 * tree-eh.c (sink_clobbers): Update virtual operands for
14489 the first and last stmt only. Add a dry-run capability.
14490 (pass_lower_eh_dispatch::execute): Perform clobber sinking
14491 after CFG manipulations and in RPO order to catch all
14492 secondary opportunities reliably.
14494 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
14496 PR target/93182
14497 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
14499 2019-01-08 Richard Biener <rguenther@suse.de>
14501 PR middle-end/93199
14502 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
14503 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
14504 virtual operand, also updating SSA use.
14505 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
14506 Update stmt after resetting virtual operand.
14507 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
14508 * gimple-iterator.c (gsi_remove): When not removing the stmt
14509 permanently do not delink immediate uses or mark the stmt modified.
14511 2020-01-08 Martin Liska <mliska@suse.cz>
14513 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
14514 (ipa_call_context::estimate_size_and_time): Likewise.
14515 (inline_analyze_function): Likewise.
14517 2020-01-08 Martin Liska <mliska@suse.cz>
14519 * cgraph.c (cgraph_node::dump): Use systematically
14520 dump_asm_name.
14522 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
14524 Add -nodevicespecs option for avr.
14526 PR target/93182
14527 * config/avr/avr.opt (-nodevicespecs): New driver option.
14528 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
14529 "-specs=device-specs/..." if that option is not set.
14530 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
14532 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
14534 Implement 64-bit double functions for avr.
14536 PR target/92055
14537 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
14538 --with-double-comparison.
14539 * doc/install.texi: Document them.
14540 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
14541 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
14542 <WITH_DOUBLE_COMPARISON>: New built-in defines.
14543 * doc/invoke.texi (AVR Built-in Macros): Document them.
14544 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
14545 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
14546 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
14548 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
14550 PR target/93188
14551 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
14552 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
14553 when only building rm-profile multilibs.
14555 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
14557 PR ipa/93084
14558 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
14559 lattice for a value to check.
14560 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
14561 finite propagation in self-recursive scc.
14563 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
14565 * ipa-inline.c (caller_growth_limits): Restore the AND.
14567 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
14569 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
14570 (VEC_ALLREG_ALT): New iterator.
14571 (VEC_ALLREG_INT_MODE): New iterator.
14572 (VCMP_MODE): New iterator.
14573 (VCMP_MODE_INT): New iterator.
14574 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
14575 (vec_cmp<u>v64qidi): New define_expand.
14576 (vec_cmp<mode>di_exec): Use VCMP_MODE.
14577 (vec_cmpu<mode>di_exec): New define_expand.
14578 (vec_cmp<u>v64qidi_exec): New define_expand.
14579 (vec_cmp<mode>di_dup): Use VCMP_MODE.
14580 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
14581 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
14582 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
14583 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
14584 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
14585 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
14586 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
14587 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
14588 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
14589 this.
14590 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
14591 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
14593 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
14595 * config/gcn/constraints.md (DA): Update description and match.
14596 (DB): Likewise.
14597 (Db): New constraint.
14598 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
14599 parameter.
14600 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
14601 Implement 'Db' mixed immediate type.
14602 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
14603 (addcv64si3_dup<exec_vcc>): Delete.
14604 (subcv64si3<exec_vcc>): Rework constraints.
14605 (addv64di3): Rework constraints.
14606 (addv64di3_exec): Rework constraints.
14607 (subv64di3): Rework constraints.
14608 (addv64di3_dup): Delete.
14609 (addv64di3_dup_exec): Delete.
14610 (addv64di3_zext): Rework constraints.
14611 (addv64di3_zext_exec): Rework constraints.
14612 (addv64di3_zext_dup): Rework constraints.
14613 (addv64di3_zext_dup_exec): Rework constraints.
14614 (addv64di3_zext_dup2): Rework constraints.
14615 (addv64di3_zext_dup2_exec): Rework constraints.
14616 (addv64di3_sext_dup2): Rework constraints.
14617 (addv64di3_sext_dup2_exec): Rework constraints.
14619 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
14621 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
14622 existing target checks.
14624 2020-01-07 Richard Biener <rguenther@suse.de>
14626 * doc/install.texi: Bump minimal supported MPC version.
14628 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
14630 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
14631 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
14632 * langhooks.c: Include stor-layout.h.
14633 (lhd_simulate_enum_decl): New function.
14634 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
14635 handle_arm_sve_h for the LTO frontend.
14636 (register_vector_type): Cope with null returns from pushdecl.
14638 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
14640 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
14641 (aarch64_sve::nvectors_if_data_type): Replace with...
14642 (aarch64_sve::builtin_type_p): ...this.
14643 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
14644 (find_vector_type): Delete.
14645 (add_sve_type_attribute): New function.
14646 (lookup_sve_type_attribute): Likewise.
14647 (register_builtin_types): Add an "SVE type" attribute to each type.
14648 (register_tuple_type): Likewise.
14649 (svbool_type_p, nvectors_if_data_type): Delete.
14650 (mangle_builtin_type): Use lookup_sve_type_attribute.
14651 (builtin_type_p): Likewise. Add an overload that returns the
14652 number of constituent vector and predicate registers.
14653 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
14654 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
14655 instead of aarch64_sve_argument_p.
14656 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
14657 (aarch64_pass_by_reference): Likewise.
14658 (aarch64_function_value_1): Likewise.
14659 (aarch64_return_in_memory): Likewise.
14660 (aarch64_layout_arg): Likewise.
14662 2020-01-07 Jakub Jelinek <jakub@redhat.com>
14664 PR tree-optimization/93156
14665 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
14666 least significant bit is always clear.
14668 PR tree-optimization/93118
14669 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
14670 simplifier with two intermediate conversions.
14672 2020-01-07 Martin Liska <mliska@suse.cz>
14674 * params.opt: Add Optimization for various parameters.
14676 2020-01-07 Martin Liska <mliska@suse.cz>
14678 PR ipa/83411
14679 * doc/extend.texi: Explain cloning for target_clone
14680 attribute.
14682 2020-01-07 Martin Liska <mliska@suse.cz>
14684 PR tree-optimization/92860
14685 * common.opt: Make in Optimization option
14686 as it is affected by -O0, which is an Optimization
14687 option.
14688 * tree-inline.c (tree_inlinable_function_p):
14689 Use opt_for_fn for warn_inline.
14690 (expand_call_inline): Likewise.
14692 2020-01-07 Martin Liska <mliska@suse.cz>
14694 PR tree-optimization/92860
14695 * common.opt: Make flag_ree as optimization
14696 attribute.
14698 2020-01-07 Martin Liska <mliska@suse.cz>
14700 PR optimization/92860
14701 * params.opt: Mark param_min_crossjump_insns with Optimization
14702 keyword.
14704 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
14706 * ipa-inline-analysis.c (estimate_growth): Fix typo.
14707 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
14709 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
14711 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
14712 helper function to return the valid addressing formats for a given
14713 hard register and mode.
14714 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
14716 * config/rs6000/constraints.md (Q constraint): Update
14717 documentation.
14718 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
14719 documentation.
14721 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
14722 Use 'Q' for doing vector extract from memory.
14723 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
14724 memory.
14725 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
14726 doing vector extract from memory.
14727 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
14728 extract from memory.
14730 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
14731 for the offset being 34-bits when -mcpu=future is used.
14733 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
14735 * config/pa/pa.md: Revert change to use ordered_comparison_operator
14736 instead of cmpib_comparison_operator in cmpib patterns.
14737 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
14738 of cmpib_comparison_operator. Revise comment.
14740 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
14742 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
14743 in an IFN_DIV_POW2 node to be equal.
14745 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
14747 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
14748 (vect_check_scalar_mask): ...this.
14749 (vectorizable_store, vectorizable_load): Update call accordingly.
14750 (vectorizable_call): Use vect_check_scalar_mask to check the mask
14751 argument in calls to conditional internal functions.
14753 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
14755 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
14756 '0' matching inputs.
14757 (subv64di3_exec): Likewise.
14759 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
14761 * config/mips/mips.c (vr4130_align_insns): Fix typo.
14762 * doc/md.texi (movstr): Likewise.
14764 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
14766 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
14767 clobber.
14769 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
14771 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
14772 Depend on...
14773 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
14774 to a temporary file and use move-if-change to update the real
14775 file where necessary.
14777 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
14779 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
14780 rather than Upa for CPY /M.
14782 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
14784 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
14785 immediate.
14787 2020-01-06 Martin Liska <mliska@suse.cz>
14789 PR tree-optimization/92860
14790 * params.opt: Mark param_max_combine_insns with Optimization
14791 keyword.
14793 2020-01-05 Jakub Jelinek <jakub@redhat.com>
14795 PR target/93141
14796 * config/i386/i386.md (SWIDWI): New mode iterator.
14797 (DWI, dwi): Add TImode variants.
14798 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
14799 <general_hilo_operand> instead of <general_operand>. Use
14800 CONST_SCALAR_INT_P instead of CONST_INT_P.
14801 (*addv<mode>4_1): Rename to ...
14802 (addv<mode>4_1): ... this.
14803 (QWI): New mode attribute.
14804 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
14805 define_insn_and_split patterns.
14806 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
14807 patterns.
14808 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
14809 <general_hilo_operand> instead of <general_operand>.
14810 (*addcarry<mode>_1): New define_insn.
14811 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
14813 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
14815 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
14816 Use "call" instead of "set".
14818 2020-01-03 Martin Jambor <mjambor@suse.cz>
14820 PR ipa/92917
14821 * ipa-cp.c (print_all_lattices): Skip functions without info.
14823 2020-01-03 Jakub Jelinek <jakub@redhat.com>
14825 PR target/93089
14826 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
14827 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
14828 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
14829 for 'e' simd clones.
14831 PR target/93089
14832 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
14833 entry.
14834 (mprefer-vector-width=): Add Save.
14835 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
14836 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
14837 (ix86_debug_options, ix86_function_specific_print): Adjust
14838 ix86_target_string callers.
14839 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
14840 (ix86_valid_target_attribute_tree): Likewise.
14841 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
14842 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
14843 ix86_target_string caller.
14845 PR target/93110
14846 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
14847 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
14848 instead of gen_int_shift_amount + convert_modes.
14850 PR rtl-optimization/93088
14851 * loop-iv.c (find_single_def_src): Punt after looking through
14852 128 reg copies for regs with single definitions. Move definitions
14853 to first uses.
14855 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
14857 * config/arm/arm-c.c (arm_cpu_builtins): Define
14858 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
14859 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
14860 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
14861 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
14862 * config/arm/arm-tables.opt: Regenerated.
14863 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
14864 arm_arch_i8mm and arm_arch_bf16 when enabled.
14865 * config/arm/arm.h (TARGET_I8MM): New macro.
14866 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
14867 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
14868 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
14869 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
14870 (v8_6_a_simd_variants): New.
14871 (v8_*_a_simd_variants): Add i8mm and bf16.
14872 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
14874 2020-01-02 Jakub Jelinek <jakub@redhat.com>
14876 PR ipa/93087
14877 * predict.c (compute_function_frequency): Don't call
14878 warn_function_cold on functions that already have cold attribute.
14880 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
14882 PR target/67834
14883 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
14884 COMDAT group function labels in .data.rel.ro.local section.
14885 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
14887 PR target/93111
14888 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
14889 comparison_operator in B and S integer comparisons. Likewise, use
14890 ordered_comparison_operator instead of cmpib_comparison_operator in
14891 cmpib patterns.
14892 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
14894 2020-01-01 Jakub Jelinek <jakub@redhat.com>
14896 Update copyright years.
14898 * gcc.c (process_command): Update copyright notice dates.
14899 * gcov-dump.c (print_version): Ditto.
14900 * gcov.c (print_version): Ditto.
14901 * gcov-tool.c (print_version): Ditto.
14902 * gengtype.c (create_file): Ditto.
14903 * doc/cpp.texi: Bump @copying's copyright year.
14904 * doc/cppinternals.texi: Ditto.
14905 * doc/gcc.texi: Ditto.
14906 * doc/gccint.texi: Ditto.
14907 * doc/gcov.texi: Ditto.
14908 * doc/install.texi: Ditto.
14909 * doc/invoke.texi: Ditto.
14911 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
14913 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
14914 summary.
14916 2020-01-01 Jakub Jelinek <jakub@redhat.com>
14918 PR tree-optimization/93098
14919 * match.pd (popcount): For shift amounts, use integer_onep
14920 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
14921 tests. Make sure that precision is power of two larger than or equal
14922 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
14923 instead of ULL suffixed constants. Formatting fixes.
14924 \f
14925 Copyright (C) 2020 Free Software Foundation, Inc.
14927 Copying and distribution of this file, with or without modification,
14928 are permitted in any medium without royalty provided the copyright
14929 notice and this notice are preserved.