gcc/reload1.c

   1 /* Reload pseudo regs into hard regs for insns that require hard regs.
   2    Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
   4    2011, 2012 Free Software Foundation, Inc.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #include "config.h"
  23 #include "system.h"
  24 #include "coretypes.h"
  25 #include "tm.h"
  26
  27 #include "machmode.h"
  28 #include "hard-reg-set.h"
  29 #include "rtl-error.h"
  30 #include "tm_p.h"
  31 #include "obstack.h"
  32 #include "insn-config.h"
  33 #include "ggc.h"
  34 #include "flags.h"
  35 #include "function.h"
  36 #include "expr.h"
  37 #include "optabs.h"
  38 #include "regs.h"
  39 #include "addresses.h"
  40 #include "basic-block.h"
  41 #include "df.h"
  42 #include "reload.h"
  43 #include "recog.h"
  44 #include "except.h"
  45 #include "tree.h"
  46 #include "ira.h"
  47 #include "target.h"
  48 #include "emit-rtl.h"
  49 #include "dumpfile.h"
  50
  51 /* This file contains the reload pass of the compiler, which is
  52    run after register allocation has been done.  It checks that
  53    each insn is valid (operands required to be in registers really
  54    are in registers of the proper class) and fixes up invalid ones
  55    by copying values temporarily into registers for the insns
  56    that need them.
  57
  58    The results of register allocation are described by the vector
  59    reg_renumber; the insns still contain pseudo regs, but reg_renumber
  60    can be used to find which hard reg, if any, a pseudo reg is in.
  61
  62    The technique we always use is to free up a few hard regs that are
  63    called ``reload regs'', and for each place where a pseudo reg
  64    must be in a hard reg, copy it temporarily into one of the reload regs.
  65
  66    Reload regs are allocated locally for every instruction that needs
  67    reloads.  When there are pseudos which are allocated to a register that
  68    has been chosen as a reload reg, such pseudos must be ``spilled''.
  69    This means that they go to other hard regs, or to stack slots if no other
  70    available hard regs can be found.  Spilling can invalidate more
  71    insns, requiring additional need for reloads, so we must keep checking
  72    until the process stabilizes.
  73
  74    For machines with different classes of registers, we must keep track
  75    of the register class needed for each reload, and make sure that
  76    we allocate enough reload registers of each class.
  77
  78    The file reload.c contains the code that checks one insn for
  79    validity and reports the reloads that it needs.  This file
  80    is in charge of scanning the entire rtl code, accumulating the
  81    reload needs, spilling, assigning reload registers to use for
  82    fixing up each insn, and generating the new insns to copy values
  83    into the reload registers.  */
  84 \f
  85 struct target_reload default_target_reload;
  86 #if SWITCHABLE_TARGET
  87 struct target_reload *this_target_reload = &default_target_reload;
  88 #endif
  89
  90 #define spill_indirect_levels                   \
  91   (this_target_reload->x_spill_indirect_levels)
  92
  93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
  94    into which reg N has been reloaded (perhaps for a previous insn).  */
  95 static rtx *reg_last_reload_reg;
  96
  97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
  98    for an output reload that stores into reg N.  */
  99 static regset_head reg_has_output_reload;
 100
 101 /* Indicates which hard regs are reload-registers for an output reload
 102    in the current insn.  */
 103 static HARD_REG_SET reg_is_output_reload;
 104
 105 /* Widest width in which each pseudo reg is referred to (via subreg).  */
 106 static unsigned int *reg_max_ref_width;
 107
 108 /* Vector to remember old contents of reg_renumber before spilling.  */
 109 static short *reg_old_renumber;
 110
 111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
 112    into hard register N.  If that pseudo reg occupied more than one register,
 113    reg_reloaded_contents points to that pseudo for each spill register in
 114    use; all of these must remain set for an inheritance to occur.  */
 115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
 116
 117 /* During reload_as_needed, element N contains the insn for which
 118    hard register N was last used.   Its contents are significant only
 119    when reg_reloaded_valid is set for this register.  */
 120 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
 121
 122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid.  */
 123 static HARD_REG_SET reg_reloaded_valid;
 124 /* Indicate if the register was dead at the end of the reload.
 125    This is only valid if reg_reloaded_contents is set and valid.  */
 126 static HARD_REG_SET reg_reloaded_dead;
 127
 128 /* Indicate whether the register's current value is one that is not
 129    safe to retain across a call, even for registers that are normally
 130    call-saved.  This is only meaningful for members of reg_reloaded_valid.  */
 131 static HARD_REG_SET reg_reloaded_call_part_clobbered;
 132
 133 /* Number of spill-regs so far; number of valid elements of spill_regs.  */
 134 static int n_spills;
 135
 136 /* In parallel with spill_regs, contains REG rtx's for those regs.
 137    Holds the last rtx used for any given reg, or 0 if it has never
 138    been used for spilling yet.  This rtx is reused, provided it has
 139    the proper mode.  */
 140 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
 141
 142 /* In parallel with spill_regs, contains nonzero for a spill reg
 143    that was stored after the last time it was used.
 144    The precise value is the insn generated to do the store.  */
 145 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
 146
 147 /* This is the register that was stored with spill_reg_store.  This is a
 148    copy of reload_out / reload_out_reg when the value was stored; if
 149    reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg.  */
 150 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
 151
 152 /* This table is the inverse mapping of spill_regs:
 153    indexed by hard reg number,
 154    it contains the position of that reg in spill_regs,
 155    or -1 for something that is not in spill_regs.
 156
 157    ?!?  This is no longer accurate.  */
 158 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
 159
 160 /* This reg set indicates registers that can't be used as spill registers for
 161    the currently processed insn.  These are the hard registers which are live
 162    during the insn, but not allocated to pseudos, as well as fixed
 163    registers.  */
 164 static HARD_REG_SET bad_spill_regs;
 165
 166 /* These are the hard registers that can't be used as spill register for any
 167    insn.  This includes registers used for user variables and registers that
 168    we can't eliminate.  A register that appears in this set also can't be used
 169    to retry register allocation.  */
 170 static HARD_REG_SET bad_spill_regs_global;
 171
 172 /* Describes order of use of registers for reloading
 173    of spilled pseudo-registers.  `n_spills' is the number of
 174    elements that are actually valid; new ones are added at the end.
 175
 176    Both spill_regs and spill_reg_order are used on two occasions:
 177    once during find_reload_regs, where they keep track of the spill registers
 178    for a single insn, but also during reload_as_needed where they show all
 179    the registers ever used by reload.  For the latter case, the information
 180    is calculated during finish_spills.  */
 181 static short spill_regs[FIRST_PSEUDO_REGISTER];
 182
 183 /* This vector of reg sets indicates, for each pseudo, which hard registers
 184    may not be used for retrying global allocation because the register was
 185    formerly spilled from one of them.  If we allowed reallocating a pseudo to
 186    a register that it was already allocated to, reload might not
 187    terminate.  */
 188 static HARD_REG_SET *pseudo_previous_regs;
 189
 190 /* This vector of reg sets indicates, for each pseudo, which hard
 191    registers may not be used for retrying global allocation because they
 192    are used as spill registers during one of the insns in which the
 193    pseudo is live.  */
 194 static HARD_REG_SET *pseudo_forbidden_regs;
 195
 196 /* All hard regs that have been used as spill registers for any insn are
 197    marked in this set.  */
 198 static HARD_REG_SET used_spill_regs;
 199
 200 /* Index of last register assigned as a spill register.  We allocate in
 201    a round-robin fashion.  */
 202 static int last_spill_reg;
 203
 204 /* Record the stack slot for each spilled hard register.  */
 205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
 206
 207 /* Width allocated so far for that stack slot.  */
 208 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
 209
 210 /* Record which pseudos needed to be spilled.  */
 211 static regset_head spilled_pseudos;
 212
 213 /* Record which pseudos changed their allocation in finish_spills.  */
 214 static regset_head changed_allocation_pseudos;
 215
 216 /* Used for communication between order_regs_for_reload and count_pseudo.
 217    Used to avoid counting one pseudo twice.  */
 218 static regset_head pseudos_counted;
 219
 220 /* First uid used by insns created by reload in this function.
 221    Used in find_equiv_reg.  */
 222 int reload_first_uid;
 223
 224 /* Flag set by local-alloc or global-alloc if anything is live in
 225    a call-clobbered reg across calls.  */
 226 int caller_save_needed;
 227
 228 /* Set to 1 while reload_as_needed is operating.
 229    Required by some machines to handle any generated moves differently.  */
 230 int reload_in_progress = 0;
 231
 232 /* This obstack is used for allocation of rtl during register elimination.
 233    The allocated storage can be freed once find_reloads has processed the
 234    insn.  */
 235 static struct obstack reload_obstack;
 236
 237 /* Points to the beginning of the reload_obstack.  All insn_chain structures
 238    are allocated first.  */
 239 static char *reload_startobj;
 240
 241 /* The point after all insn_chain structures.  Used to quickly deallocate
 242    memory allocated in copy_reloads during calculate_needs_all_insns.  */
 243 static char *reload_firstobj;
 244
 245 /* This points before all local rtl generated by register elimination.
 246    Used to quickly free all memory after processing one insn.  */
 247 static char *reload_insn_firstobj;
 248
 249 /* List of insn_chain instructions, one for every insn that reload needs to
 250    examine.  */
 251 struct insn_chain *reload_insn_chain;
 252
 253 /* TRUE if we potentially left dead insns in the insn stream and want to
 254    run DCE immediately after reload, FALSE otherwise.  */
 255 static bool need_dce;
 256
 257 /* List of all insns needing reloads.  */
 258 static struct insn_chain *insns_need_reload;
 259 \f
 260 /* This structure is used to record information about register eliminations.
 261    Each array entry describes one possible way of eliminating a register
 262    in favor of another.   If there is more than one way of eliminating a
 263    particular register, the most preferred should be specified first.  */
 264
 265 struct elim_table
 266 {
 267   int from;                     /* Register number to be eliminated.  */
 268   int to;                       /* Register number used as replacement.  */
 269   HOST_WIDE_INT initial_offset; /* Initial difference between values.  */
 270   int can_eliminate;            /* Nonzero if this elimination can be done.  */
 271   int can_eliminate_previous;   /* Value returned by TARGET_CAN_ELIMINATE
 272                                    target hook in previous scan over insns
 273                                    made by reload.  */
 274   HOST_WIDE_INT offset;         /* Current offset between the two regs.  */
 275   HOST_WIDE_INT previous_offset;/* Offset at end of previous insn.  */
 276   int ref_outside_mem;          /* "to" has been referenced outside a MEM.  */
 277   rtx from_rtx;                 /* REG rtx for the register to be eliminated.
 278                                    We cannot simply compare the number since
 279                                    we might then spuriously replace a hard
 280                                    register corresponding to a pseudo
 281                                    assigned to the reg to be eliminated.  */
 282   rtx to_rtx;                   /* REG rtx for the replacement.  */
 283 };
 284
 285 static struct elim_table *reg_eliminate = 0;
 286
 287 /* This is an intermediate structure to initialize the table.  It has
 288    exactly the members provided by ELIMINABLE_REGS.  */
 289 static const struct elim_table_1
 290 {
 291   const int from;
 292   const int to;
 293 } reg_eliminate_1[] =
 294
 295 /* If a set of eliminable registers was specified, define the table from it.
 296    Otherwise, default to the normal case of the frame pointer being
 297    replaced by the stack pointer.  */
 298
 299 #ifdef ELIMINABLE_REGS
 300   ELIMINABLE_REGS;
 301 #else
 302   {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
 303 #endif
 304
 305 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
 306
 307 /* Record the number of pending eliminations that have an offset not equal
 308    to their initial offset.  If nonzero, we use a new copy of each
 309    replacement result in any insns encountered.  */
 310 int num_not_at_initial_offset;
 311
 312 /* Count the number of registers that we may be able to eliminate.  */
 313 static int num_eliminable;
 314 /* And the number of registers that are equivalent to a constant that
 315    can be eliminated to frame_pointer / arg_pointer + constant.  */
 316 static int num_eliminable_invariants;
 317
 318 /* For each label, we record the offset of each elimination.  If we reach
 319    a label by more than one path and an offset differs, we cannot do the
 320    elimination.  This information is indexed by the difference of the
 321    number of the label and the first label number.  We can't offset the
 322    pointer itself as this can cause problems on machines with segmented
 323    memory.  The first table is an array of flags that records whether we
 324    have yet encountered a label and the second table is an array of arrays,
 325    one entry in the latter array for each elimination.  */
 326
 327 static int first_label_num;
 328 static char *offsets_known_at;
 329 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
 330
 331 vec<reg_equivs_t, va_gc> *reg_equivs;
 332
 333 /* Stack of addresses where an rtx has been changed.  We can undo the
 334    changes by popping items off the stack and restoring the original
 335    value at each location.
 336
 337    We use this simplistic undo capability rather than copy_rtx as copy_rtx
 338    will not make a deep copy of a normally sharable rtx, such as
 339    (const (plus (symbol_ref) (const_int))).  If such an expression appears
 340    as R1 in gen_reload_chain_without_interm_reg_p, then a shared
 341    rtx expression would be changed.  See PR 42431.  */
 342
 343 typedef rtx *rtx_p;
 344 static vec<rtx_p> substitute_stack;
 345
 346 /* Number of labels in the current function.  */
 347
 348 static int num_labels;
 349 \f
 350 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
 351 static void maybe_fix_stack_asms (void);
 352 static void copy_reloads (struct insn_chain *);
 353 static void calculate_needs_all_insns (int);
 354 static int find_reg (struct insn_chain *, int);
 355 static void find_reload_regs (struct insn_chain *);
 356 static void select_reload_regs (void);
 357 static void delete_caller_save_insns (void);
 358
 359 static void spill_failure (rtx, enum reg_class);
 360 static void count_spilled_pseudo (int, int, int);
 361 static void delete_dead_insn (rtx);
 362 static void alter_reg (int, int, bool);
 363 static void set_label_offsets (rtx, rtx, int);
 364 static void check_eliminable_occurrences (rtx);
 365 static void elimination_effects (rtx, enum machine_mode);
 366 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
 367 static int eliminate_regs_in_insn (rtx, int);
 368 static void update_eliminable_offsets (void);
 369 static void mark_not_eliminable (rtx, const_rtx, void *);
 370 static void set_initial_elim_offsets (void);
 371 static bool verify_initial_elim_offsets (void);
 372 static void set_initial_label_offsets (void);
 373 static void set_offsets_for_label (rtx);
 374 static void init_eliminable_invariants (rtx, bool);
 375 static void init_elim_table (void);
 376 static void free_reg_equiv (void);
 377 static void update_eliminables (HARD_REG_SET *);
 378 static void elimination_costs_in_insn (rtx);
 379 static void spill_hard_reg (unsigned int, int);
 380 static int finish_spills (int);
 381 static void scan_paradoxical_subregs (rtx);
 382 static void count_pseudo (int);
 383 static void order_regs_for_reload (struct insn_chain *);
 384 static void reload_as_needed (int);
 385 static void forget_old_reloads_1 (rtx, const_rtx, void *);
 386 static void forget_marked_reloads (regset);
 387 static int reload_reg_class_lower (const void *, const void *);
 388 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
 389                                     enum machine_mode);
 390 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
 391                                      enum machine_mode);
 392 static int reload_reg_free_p (unsigned int, int, enum reload_type);
 393 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
 394                                         rtx, rtx, int, int);
 395 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
 396                              rtx, rtx, int, int);
 397 static int allocate_reload_reg (struct insn_chain *, int, int);
 398 static int conflicts_with_override (rtx);
 399 static void failed_reload (rtx, int);
 400 static int set_reload_reg (int, int);
 401 static void choose_reload_regs_init (struct insn_chain *, rtx *);
 402 static void choose_reload_regs (struct insn_chain *);
 403 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
 404                                      rtx, int);
 405 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
 406                                       int);
 407 static void do_input_reload (struct insn_chain *, struct reload *, int);
 408 static void do_output_reload (struct insn_chain *, struct reload *, int);
 409 static void emit_reload_insns (struct insn_chain *);
 410 static void delete_output_reload (rtx, int, int, rtx);
 411 static void delete_address_reloads (rtx, rtx);
 412 static void delete_address_reloads_1 (rtx, rtx, rtx);
 413 static void inc_for_reload (rtx, rtx, rtx, int);
 414 #ifdef AUTO_INC_DEC
 415 static void add_auto_inc_notes (rtx, rtx);
 416 #endif
 417 static void substitute (rtx *, const_rtx, rtx);
 418 static bool gen_reload_chain_without_interm_reg_p (int, int);
 419 static int reloads_conflict (int, int);
 420 static rtx gen_reload (rtx, rtx, int, enum reload_type);
 421 static rtx emit_insn_if_valid_for_reload (rtx);
 422 \f
 423 /* Initialize the reload pass.  This is called at the beginning of compilation
 424    and may be called again if the target is reinitialized.  */
 425
 426 void
 427 init_reload (void)
 428 {
 429   int i;
 430
 431   /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
 432      Set spill_indirect_levels to the number of levels such addressing is
 433      permitted, zero if it is not permitted at all.  */
 434
 435   rtx tem
 436     = gen_rtx_MEM (Pmode,
 437                    gen_rtx_PLUS (Pmode,
 438                                  gen_rtx_REG (Pmode,
 439                                               LAST_VIRTUAL_REGISTER + 1),
 440                                  GEN_INT (4)));
 441   spill_indirect_levels = 0;
 442
 443   while (memory_address_p (QImode, tem))
 444     {
 445       spill_indirect_levels++;
 446       tem = gen_rtx_MEM (Pmode, tem);
 447     }
 448
 449   /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)).  */
 450
 451   tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
 452   indirect_symref_ok = memory_address_p (QImode, tem);
 453
 454   /* See if reg+reg is a valid (and offsettable) address.  */
 455
 456   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 457     {
 458       tem = gen_rtx_PLUS (Pmode,
 459                           gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
 460                           gen_rtx_REG (Pmode, i));
 461
 462       /* This way, we make sure that reg+reg is an offsettable address.  */
 463       tem = plus_constant (Pmode, tem, 4);
 464
 465       if (memory_address_p (QImode, tem))
 466         {
 467           double_reg_address_ok = 1;
 468           break;
 469         }
 470     }
 471
 472   /* Initialize obstack for our rtl allocation.  */
 473   gcc_obstack_init (&reload_obstack);
 474   reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
 475
 476   INIT_REG_SET (&spilled_pseudos);
 477   INIT_REG_SET (&changed_allocation_pseudos);
 478   INIT_REG_SET (&pseudos_counted);
 479 }
 480
 481 /* List of insn chains that are currently unused.  */
 482 static struct insn_chain *unused_insn_chains = 0;
 483
 484 /* Allocate an empty insn_chain structure.  */
 485 struct insn_chain *
 486 new_insn_chain (void)
 487 {
 488   struct insn_chain *c;
 489
 490   if (unused_insn_chains == 0)
 491     {
 492       c = XOBNEW (&reload_obstack, struct insn_chain);
 493       INIT_REG_SET (&c->live_throughout);
 494       INIT_REG_SET (&c->dead_or_set);
 495     }
 496   else
 497     {
 498       c = unused_insn_chains;
 499       unused_insn_chains = c->next;
 500     }
 501   c->is_caller_save_insn = 0;
 502   c->need_operand_change = 0;
 503   c->need_reload = 0;
 504   c->need_elim = 0;
 505   return c;
 506 }
 507
 508 /* Small utility function to set all regs in hard reg set TO which are
 509    allocated to pseudos in regset FROM.  */
 510
 511 void
 512 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
 513 {
 514   unsigned int regno;
 515   reg_set_iterator rsi;
 516
 517   EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
 518     {
 519       int r = reg_renumber[regno];
 520
 521       if (r < 0)
 522         {
 523           /* reload_combine uses the information from DF_LIVE_IN,
 524              which might still contain registers that have not
 525              actually been allocated since they have an
 526              equivalence.  */
 527           gcc_assert (ira_conflicts_p || reload_completed);
 528         }
 529       else
 530         add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
 531     }
 532 }
 533
 534 /* Replace all pseudos found in LOC with their corresponding
 535    equivalences.  */
 536
 537 static void
 538 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
 539 {
 540   rtx x = *loc;
 541   enum rtx_code code;
 542   const char *fmt;
 543   int i, j;
 544
 545   if (! x)
 546     return;
 547
 548   code = GET_CODE (x);
 549   if (code == REG)
 550     {
 551       unsigned int regno = REGNO (x);
 552
 553       if (regno < FIRST_PSEUDO_REGISTER)
 554         return;
 555
 556       x = eliminate_regs_1 (x, mem_mode, usage, true, false);
 557       if (x != *loc)
 558         {
 559           *loc = x;
 560           replace_pseudos_in (loc, mem_mode, usage);
 561           return;
 562         }
 563
 564       if (reg_equiv_constant (regno))
 565         *loc = reg_equiv_constant (regno);
 566       else if (reg_equiv_invariant (regno))
 567         *loc = reg_equiv_invariant (regno);
 568       else if (reg_equiv_mem (regno))
 569         *loc = reg_equiv_mem (regno);
 570       else if (reg_equiv_address (regno))
 571         *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
 572       else
 573         {
 574           gcc_assert (!REG_P (regno_reg_rtx[regno])
 575                       || REGNO (regno_reg_rtx[regno]) != regno);
 576           *loc = regno_reg_rtx[regno];
 577         }
 578
 579       return;
 580     }
 581   else if (code == MEM)
 582     {
 583       replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
 584       return;
 585     }
 586
 587   /* Process each of our operands recursively.  */
 588   fmt = GET_RTX_FORMAT (code);
 589   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
 590     if (*fmt == 'e')
 591       replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
 592     else if (*fmt == 'E')
 593       for (j = 0; j < XVECLEN (x, i); j++)
 594         replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
 595 }
 596
 597 /* Determine if the current function has an exception receiver block
 598    that reaches the exit block via non-exceptional edges  */
 599
 600 static bool
 601 has_nonexceptional_receiver (void)
 602 {
 603   edge e;
 604   edge_iterator ei;
 605   basic_block *tos, *worklist, bb;
 606
 607   /* If we're not optimizing, then just err on the safe side.  */
 608   if (!optimize)
 609     return true;
 610
 611   /* First determine which blocks can reach exit via normal paths.  */
 612   tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
 613
 614   FOR_EACH_BB (bb)
 615     bb->flags &= ~BB_REACHABLE;
 616
 617   /* Place the exit block on our worklist.  */
 618   EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
 619   *tos++ = EXIT_BLOCK_PTR;
 620
 621   /* Iterate: find everything reachable from what we've already seen.  */
 622   while (tos != worklist)
 623     {
 624       bb = *--tos;
 625
 626       FOR_EACH_EDGE (e, ei, bb->preds)
 627         if (!(e->flags & EDGE_ABNORMAL))
 628           {
 629             basic_block src = e->src;
 630
 631             if (!(src->flags & BB_REACHABLE))
 632               {
 633                 src->flags |= BB_REACHABLE;
 634                 *tos++ = src;
 635               }
 636           }
 637     }
 638   free (worklist);
 639
 640   /* Now see if there's a reachable block with an exceptional incoming
 641      edge.  */
 642   FOR_EACH_BB (bb)
 643     if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
 644       return true;
 645
 646   /* No exceptional block reached exit unexceptionally.  */
 647   return false;
 648 }
 649
 650 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
 651    zero elements) to MAX_REG_NUM elements.
 652
 653    Initialize all new fields to NULL and update REG_EQUIVS_SIZE.  */
 654 void
 655 grow_reg_equivs (void)
 656 {
 657   int old_size = vec_safe_length (reg_equivs);
 658   int max_regno = max_reg_num ();
 659   int i;
 660   reg_equivs_t ze;
 661
 662   memset (&ze, 0, sizeof (reg_equivs_t));
 663   vec_safe_reserve (reg_equivs, max_regno);
 664   for (i = old_size; i < max_regno; i++)
 665     reg_equivs->quick_insert (i, ze);
 666 }
 667
 668 \f
 669 /* Global variables used by reload and its subroutines.  */
 670
 671 /* The current basic block while in calculate_elim_costs_all_insns.  */
 672 static basic_block elim_bb;
 673
 674 /* Set during calculate_needs if an insn needs register elimination.  */
 675 static int something_needs_elimination;
 676 /* Set during calculate_needs if an insn needs an operand changed.  */
 677 static int something_needs_operands_changed;
 678 /* Set by alter_regs if we spilled a register to the stack.  */
 679 static bool something_was_spilled;
 680
 681 /* Nonzero means we couldn't get enough spill regs.  */
 682 static int failure;
 683
 684 /* Temporary array of pseudo-register number.  */
 685 static int *temp_pseudo_reg_arr;
 686
 687 /* Main entry point for the reload pass.
 688
 689    FIRST is the first insn of the function being compiled.
 690
 691    GLOBAL nonzero means we were called from global_alloc
 692    and should attempt to reallocate any pseudoregs that we
 693    displace from hard regs we will use for reloads.
 694    If GLOBAL is zero, we do not have enough information to do that,
 695    so any pseudo reg that is spilled must go to the stack.
 696
 697    Return value is TRUE if reload likely left dead insns in the
 698    stream and a DCE pass should be run to elimiante them.  Else the
 699    return value is FALSE.  */
 700
 701 bool
 702 reload (rtx first, int global)
 703 {
 704   int i, n;
 705   rtx insn;
 706   struct elim_table *ep;
 707   basic_block bb;
 708   bool inserted;
 709
 710   /* Make sure even insns with volatile mem refs are recognizable.  */
 711   init_recog ();
 712
 713   failure = 0;
 714
 715   reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
 716
 717   /* Make sure that the last insn in the chain
 718      is not something that needs reloading.  */
 719   emit_note (NOTE_INSN_DELETED);
 720
 721   /* Enable find_equiv_reg to distinguish insns made by reload.  */
 722   reload_first_uid = get_max_uid ();
 723
 724 #ifdef SECONDARY_MEMORY_NEEDED
 725   /* Initialize the secondary memory table.  */
 726   clear_secondary_mem ();
 727 #endif
 728
 729   /* We don't have a stack slot for any spill reg yet.  */
 730   memset (spill_stack_slot, 0, sizeof spill_stack_slot);
 731   memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
 732
 733   /* Initialize the save area information for caller-save, in case some
 734      are needed.  */
 735   init_save_areas ();
 736
 737   /* Compute which hard registers are now in use
 738      as homes for pseudo registers.
 739      This is done here rather than (eg) in global_alloc
 740      because this point is reached even if not optimizing.  */
 741   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 742     mark_home_live (i);
 743
 744   /* A function that has a nonlocal label that can reach the exit
 745      block via non-exceptional paths must save all call-saved
 746      registers.  */
 747   if (cfun->has_nonlocal_label
 748       && has_nonexceptional_receiver ())
 749     crtl->saves_all_registers = 1;
 750
 751   if (crtl->saves_all_registers)
 752     for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 753       if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
 754         df_set_regs_ever_live (i, true);
 755
 756   /* Find all the pseudo registers that didn't get hard regs
 757      but do have known equivalent constants or memory slots.
 758      These include parameters (known equivalent to parameter slots)
 759      and cse'd or loop-moved constant memory addresses.
 760
 761      Record constant equivalents in reg_equiv_constant
 762      so they will be substituted by find_reloads.
 763      Record memory equivalents in reg_mem_equiv so they can
 764      be substituted eventually by altering the REG-rtx's.  */
 765
 766   grow_reg_equivs ();
 767   reg_old_renumber = XCNEWVEC (short, max_regno);
 768   memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
 769   pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
 770   pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
 771
 772   CLEAR_HARD_REG_SET (bad_spill_regs_global);
 773
 774   init_eliminable_invariants (first, true);
 775   init_elim_table ();
 776
 777   /* Alter each pseudo-reg rtx to contain its hard reg number.  Assign
 778      stack slots to the pseudos that lack hard regs or equivalents.
 779      Do not touch virtual registers.  */
 780
 781   temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
 782   for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
 783     temp_pseudo_reg_arr[n++] = i;
 784
 785   if (ira_conflicts_p)
 786     /* Ask IRA to order pseudo-registers for better stack slot
 787        sharing.  */
 788     ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
 789
 790   for (i = 0; i < n; i++)
 791     alter_reg (temp_pseudo_reg_arr[i], -1, false);
 792
 793   /* If we have some registers we think can be eliminated, scan all insns to
 794      see if there is an insn that sets one of these registers to something
 795      other than itself plus a constant.  If so, the register cannot be
 796      eliminated.  Doing this scan here eliminates an extra pass through the
 797      main reload loop in the most common case where register elimination
 798      cannot be done.  */
 799   for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
 800     if (INSN_P (insn))
 801       note_stores (PATTERN (insn), mark_not_eliminable, NULL);
 802
 803   maybe_fix_stack_asms ();
 804
 805   insns_need_reload = 0;
 806   something_needs_elimination = 0;
 807
 808   /* Initialize to -1, which means take the first spill register.  */
 809   last_spill_reg = -1;
 810
 811   /* Spill any hard regs that we know we can't eliminate.  */
 812   CLEAR_HARD_REG_SET (used_spill_regs);
 813   /* There can be multiple ways to eliminate a register;
 814      they should be listed adjacently.
 815      Elimination for any register fails only if all possible ways fail.  */
 816   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; )
 817     {
 818       int from = ep->from;
 819       int can_eliminate = 0;
 820       do
 821         {
 822           can_eliminate |= ep->can_eliminate;
 823           ep++;
 824         }
 825       while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
 826       if (! can_eliminate)
 827         spill_hard_reg (from, 1);
 828     }
 829
 830 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
 831   if (frame_pointer_needed)
 832     spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
 833 #endif
 834   finish_spills (global);
 835
 836   /* From now on, we may need to generate moves differently.  We may also
 837      allow modifications of insns which cause them to not be recognized.
 838      Any such modifications will be cleaned up during reload itself.  */
 839   reload_in_progress = 1;
 840
 841   /* This loop scans the entire function each go-round
 842      and repeats until one repetition spills no additional hard regs.  */
 843   for (;;)
 844     {
 845       int something_changed;
 846       int did_spill;
 847       HOST_WIDE_INT starting_frame_size;
 848
 849       starting_frame_size = get_frame_size ();
 850       something_was_spilled = false;
 851
 852       set_initial_elim_offsets ();
 853       set_initial_label_offsets ();
 854
 855       /* For each pseudo register that has an equivalent location defined,
 856          try to eliminate any eliminable registers (such as the frame pointer)
 857          assuming initial offsets for the replacement register, which
 858          is the normal case.
 859
 860          If the resulting location is directly addressable, substitute
 861          the MEM we just got directly for the old REG.
 862
 863          If it is not addressable but is a constant or the sum of a hard reg
 864          and constant, it is probably not addressable because the constant is
 865          out of range, in that case record the address; we will generate
 866          hairy code to compute the address in a register each time it is
 867          needed.  Similarly if it is a hard register, but one that is not
 868          valid as an address register.
 869
 870          If the location is not addressable, but does not have one of the
 871          above forms, assign a stack slot.  We have to do this to avoid the
 872          potential of producing lots of reloads if, e.g., a location involves
 873          a pseudo that didn't get a hard register and has an equivalent memory
 874          location that also involves a pseudo that didn't get a hard register.
 875
 876          Perhaps at some point we will improve reload_when_needed handling
 877          so this problem goes away.  But that's very hairy.  */
 878
 879       for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 880         if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
 881           {
 882             rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
 883                                     NULL_RTX);
 884
 885             if (strict_memory_address_addr_space_p
 886                   (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
 887                    MEM_ADDR_SPACE (x)))
 888               reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
 889             else if (CONSTANT_P (XEXP (x, 0))
 890                      || (REG_P (XEXP (x, 0))
 891                          && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
 892                      || (GET_CODE (XEXP (x, 0)) == PLUS
 893                          && REG_P (XEXP (XEXP (x, 0), 0))
 894                          && (REGNO (XEXP (XEXP (x, 0), 0))
 895                              < FIRST_PSEUDO_REGISTER)
 896                          && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
 897               reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
 898             else
 899               {
 900                 /* Make a new stack slot.  Then indicate that something
 901                    changed so we go back and recompute offsets for
 902                    eliminable registers because the allocation of memory
 903                    below might change some offset.  reg_equiv_{mem,address}
 904                    will be set up for this pseudo on the next pass around
 905                    the loop.  */
 906                 reg_equiv_memory_loc (i) = 0;
 907                 reg_equiv_init (i) = 0;
 908                 alter_reg (i, -1, true);
 909               }
 910           }
 911
 912       if (caller_save_needed)
 913         setup_save_areas ();
 914
 915       /* If we allocated another stack slot, redo elimination bookkeeping.  */
 916       if (something_was_spilled || starting_frame_size != get_frame_size ())
 917         continue;
 918       if (starting_frame_size && crtl->stack_alignment_needed)
 919         {
 920           /* If we have a stack frame, we must align it now.  The
 921              stack size may be a part of the offset computation for
 922              register elimination.  So if this changes the stack size,
 923              then repeat the elimination bookkeeping.  We don't
 924              realign when there is no stack, as that will cause a
 925              stack frame when none is needed should
 926              STARTING_FRAME_OFFSET not be already aligned to
 927              STACK_BOUNDARY.  */
 928           assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
 929           if (starting_frame_size != get_frame_size ())
 930             continue;
 931         }
 932
 933       if (caller_save_needed)
 934         {
 935           save_call_clobbered_regs ();
 936           /* That might have allocated new insn_chain structures.  */
 937           reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
 938         }
 939
 940       calculate_needs_all_insns (global);
 941
 942       if (! ira_conflicts_p)
 943         /* Don't do it for IRA.  We need this info because we don't
 944            change live_throughout and dead_or_set for chains when IRA
 945            is used.  */
 946         CLEAR_REG_SET (&spilled_pseudos);
 947
 948       did_spill = 0;
 949
 950       something_changed = 0;
 951
 952       /* If we allocated any new memory locations, make another pass
 953          since it might have changed elimination offsets.  */
 954       if (something_was_spilled || starting_frame_size != get_frame_size ())
 955         something_changed = 1;
 956
 957       /* Even if the frame size remained the same, we might still have
 958          changed elimination offsets, e.g. if find_reloads called
 959          force_const_mem requiring the back end to allocate a constant
 960          pool base register that needs to be saved on the stack.  */
 961       else if (!verify_initial_elim_offsets ())
 962         something_changed = 1;
 963
 964       {
 965         HARD_REG_SET to_spill;
 966         CLEAR_HARD_REG_SET (to_spill);
 967         update_eliminables (&to_spill);
 968         AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
 969
 970         for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 971           if (TEST_HARD_REG_BIT (to_spill, i))
 972             {
 973               spill_hard_reg (i, 1);
 974               did_spill = 1;
 975
 976               /* Regardless of the state of spills, if we previously had
 977                  a register that we thought we could eliminate, but now can
 978                  not eliminate, we must run another pass.
 979
 980                  Consider pseudos which have an entry in reg_equiv_* which
 981                  reference an eliminable register.  We must make another pass
 982                  to update reg_equiv_* so that we do not substitute in the
 983                  old value from when we thought the elimination could be
 984                  performed.  */
 985               something_changed = 1;
 986             }
 987       }
 988
 989       select_reload_regs ();
 990       if (failure)
 991         goto failed;
 992
 993       if (insns_need_reload != 0 || did_spill)
 994         something_changed |= finish_spills (global);
 995
 996       if (! something_changed)
 997         break;
 998
 999       if (caller_save_needed)
1000         delete_caller_save_insns ();
1001
1002       obstack_free (&reload_obstack, reload_firstobj);
1003     }
1004
1005   /* If global-alloc was run, notify it of any register eliminations we have
1006      done.  */
1007   if (global)
1008     for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1009       if (ep->can_eliminate)
1010         mark_elimination (ep->from, ep->to);
1011
1012   /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1013      If that insn didn't set the register (i.e., it copied the register to
1014      memory), just delete that insn instead of the equivalencing insn plus
1015      anything now dead.  If we call delete_dead_insn on that insn, we may
1016      delete the insn that actually sets the register if the register dies
1017      there and that is incorrect.  */
1018
1019   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1020     {
1021       if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1022         {
1023           rtx list;
1024           for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1025             {
1026               rtx equiv_insn = XEXP (list, 0);
1027
1028               /* If we already deleted the insn or if it may trap, we can't
1029                  delete it.  The latter case shouldn't happen, but can
1030                  if an insn has a variable address, gets a REG_EH_REGION
1031                  note added to it, and then gets converted into a load
1032                  from a constant address.  */
1033               if (NOTE_P (equiv_insn)
1034                   || can_throw_internal (equiv_insn))
1035                 ;
1036               else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1037                 delete_dead_insn (equiv_insn);
1038               else
1039                 SET_INSN_DELETED (equiv_insn);
1040             }
1041         }
1042     }
1043
1044   /* Use the reload registers where necessary
1045      by generating move instructions to move the must-be-register
1046      values into or out of the reload registers.  */
1047
1048   if (insns_need_reload != 0 || something_needs_elimination
1049       || something_needs_operands_changed)
1050     {
1051       HOST_WIDE_INT old_frame_size = get_frame_size ();
1052
1053       reload_as_needed (global);
1054
1055       gcc_assert (old_frame_size == get_frame_size ());
1056
1057       gcc_assert (verify_initial_elim_offsets ());
1058     }
1059
1060   /* If we were able to eliminate the frame pointer, show that it is no
1061      longer live at the start of any basic block.  If it ls live by
1062      virtue of being in a pseudo, that pseudo will be marked live
1063      and hence the frame pointer will be known to be live via that
1064      pseudo.  */
1065
1066   if (! frame_pointer_needed)
1067     FOR_EACH_BB (bb)
1068       bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1069
1070   /* Come here (with failure set nonzero) if we can't get enough spill
1071      regs.  */
1072  failed:
1073
1074   CLEAR_REG_SET (&changed_allocation_pseudos);
1075   CLEAR_REG_SET (&spilled_pseudos);
1076   reload_in_progress = 0;
1077
1078   /* Now eliminate all pseudo regs by modifying them into
1079      their equivalent memory references.
1080      The REG-rtx's for the pseudos are modified in place,
1081      so all insns that used to refer to them now refer to memory.
1082
1083      For a reg that has a reg_equiv_address, all those insns
1084      were changed by reloading so that no insns refer to it any longer;
1085      but the DECL_RTL of a variable decl may refer to it,
1086      and if so this causes the debugging info to mention the variable.  */
1087
1088   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1089     {
1090       rtx addr = 0;
1091
1092       if (reg_equiv_mem (i))
1093         addr = XEXP (reg_equiv_mem (i), 0);
1094
1095       if (reg_equiv_address (i))
1096         addr = reg_equiv_address (i);
1097
1098       if (addr)
1099         {
1100           if (reg_renumber[i] < 0)
1101             {
1102               rtx reg = regno_reg_rtx[i];
1103
1104               REG_USERVAR_P (reg) = 0;
1105               PUT_CODE (reg, MEM);
1106               XEXP (reg, 0) = addr;
1107               if (reg_equiv_memory_loc (i))
1108                 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1109               else
1110                 MEM_ATTRS (reg) = 0;
1111               MEM_NOTRAP_P (reg) = 1;
1112             }
1113           else if (reg_equiv_mem (i))
1114             XEXP (reg_equiv_mem (i), 0) = addr;
1115         }
1116
1117       /* We don't want complex addressing modes in debug insns
1118          if simpler ones will do, so delegitimize equivalences
1119          in debug insns.  */
1120       if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1121         {
1122           rtx reg = regno_reg_rtx[i];
1123           rtx equiv = 0;
1124           df_ref use, next;
1125
1126           if (reg_equiv_constant (i))
1127             equiv = reg_equiv_constant (i);
1128           else if (reg_equiv_invariant (i))
1129             equiv = reg_equiv_invariant (i);
1130           else if (reg && MEM_P (reg))
1131             equiv = targetm.delegitimize_address (reg);
1132           else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1133             equiv = reg;
1134
1135           if (equiv == reg)
1136             continue;
1137
1138           for (use = DF_REG_USE_CHAIN (i); use; use = next)
1139             {
1140               insn = DF_REF_INSN (use);
1141
1142               /* Make sure the next ref is for a different instruction,
1143                  so that we're not affected by the rescan.  */
1144               next = DF_REF_NEXT_REG (use);
1145               while (next && DF_REF_INSN (next) == insn)
1146                 next = DF_REF_NEXT_REG (next);
1147
1148               if (DEBUG_INSN_P (insn))
1149                 {
1150                   if (!equiv)
1151                     {
1152                       INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1153                       df_insn_rescan_debug_internal (insn);
1154                     }
1155                   else
1156                     INSN_VAR_LOCATION_LOC (insn)
1157                       = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1158                                               reg, equiv);
1159                 }
1160             }
1161         }
1162     }
1163
1164   /* We must set reload_completed now since the cleanup_subreg_operands call
1165      below will re-recognize each insn and reload may have generated insns
1166      which are only valid during and after reload.  */
1167   reload_completed = 1;
1168
1169   /* Make a pass over all the insns and delete all USEs which we inserted
1170      only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and REG_UNUSED
1171      notes.  Delete all CLOBBER insns, except those that refer to the return
1172      value and the special mem:BLK CLOBBERs added to prevent the scheduler
1173      from misarranging variable-array code, and simplify (subreg (reg))
1174      operands.  Strip and regenerate REG_INC notes that may have been moved
1175      around.  */
1176
1177   for (insn = first; insn; insn = NEXT_INSN (insn))
1178     if (INSN_P (insn))
1179       {
1180         rtx *pnote;
1181
1182         if (CALL_P (insn))
1183           replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1184                               VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1185
1186         if ((GET_CODE (PATTERN (insn)) == USE
1187              /* We mark with QImode USEs introduced by reload itself.  */
1188              && (GET_MODE (insn) == QImode
1189                  || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1190             || (GET_CODE (PATTERN (insn)) == CLOBBER
1191                 && (!MEM_P (XEXP (PATTERN (insn), 0))
1192                     || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1193                     || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1194                         && XEXP (XEXP (PATTERN (insn), 0), 0)
1195                                 != stack_pointer_rtx))
1196                 && (!REG_P (XEXP (PATTERN (insn), 0))
1197                     || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1198           {
1199             delete_insn (insn);
1200             continue;
1201           }
1202
1203         /* Some CLOBBERs may survive until here and still reference unassigned
1204            pseudos with const equivalent, which may in turn cause ICE in later
1205            passes if the reference remains in place.  */
1206         if (GET_CODE (PATTERN (insn)) == CLOBBER)
1207           replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1208                               VOIDmode, PATTERN (insn));
1209
1210         /* Discard obvious no-ops, even without -O.  This optimization
1211            is fast and doesn't interfere with debugging.  */
1212         if (NONJUMP_INSN_P (insn)
1213             && GET_CODE (PATTERN (insn)) == SET
1214             && REG_P (SET_SRC (PATTERN (insn)))
1215             && REG_P (SET_DEST (PATTERN (insn)))
1216             && (REGNO (SET_SRC (PATTERN (insn)))
1217                 == REGNO (SET_DEST (PATTERN (insn)))))
1218           {
1219             delete_insn (insn);
1220             continue;
1221           }
1222
1223         pnote = &REG_NOTES (insn);
1224         while (*pnote != 0)
1225           {
1226             if (REG_NOTE_KIND (*pnote) == REG_DEAD
1227                 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1228                 || REG_NOTE_KIND (*pnote) == REG_INC)
1229               *pnote = XEXP (*pnote, 1);
1230             else
1231               pnote = &XEXP (*pnote, 1);
1232           }
1233
1234 #ifdef AUTO_INC_DEC
1235         add_auto_inc_notes (insn, PATTERN (insn));
1236 #endif
1237
1238         /* Simplify (subreg (reg)) if it appears as an operand.  */
1239         cleanup_subreg_operands (insn);
1240
1241         /* Clean up invalid ASMs so that they don't confuse later passes.
1242            See PR 21299.  */
1243         if (asm_noperands (PATTERN (insn)) >= 0)
1244           {
1245             extract_insn (insn);
1246             if (!constrain_operands (1))
1247               {
1248                 error_for_asm (insn,
1249                                "%<asm%> operand has impossible constraints");
1250                 delete_insn (insn);
1251                 continue;
1252               }
1253           }
1254       }
1255
1256   /* If we are doing generic stack checking, give a warning if this
1257      function's frame size is larger than we expect.  */
1258   if (flag_stack_check == GENERIC_STACK_CHECK)
1259     {
1260       HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1261       static int verbose_warned = 0;
1262
1263       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1264         if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1265           size += UNITS_PER_WORD;
1266
1267       if (size > STACK_CHECK_MAX_FRAME_SIZE)
1268         {
1269           warning (0, "frame size too large for reliable stack checking");
1270           if (! verbose_warned)
1271             {
1272               warning (0, "try reducing the number of local variables");
1273               verbose_warned = 1;
1274             }
1275         }
1276     }
1277
1278   free (temp_pseudo_reg_arr);
1279
1280   /* Indicate that we no longer have known memory locations or constants.  */
1281   free_reg_equiv ();
1282
1283   free (reg_max_ref_width);
1284   free (reg_old_renumber);
1285   free (pseudo_previous_regs);
1286   free (pseudo_forbidden_regs);
1287
1288   CLEAR_HARD_REG_SET (used_spill_regs);
1289   for (i = 0; i < n_spills; i++)
1290     SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1291
1292   /* Free all the insn_chain structures at once.  */
1293   obstack_free (&reload_obstack, reload_startobj);
1294   unused_insn_chains = 0;
1295
1296   inserted = fixup_abnormal_edges ();
1297
1298   /* We've possibly turned single trapping insn into multiple ones.  */
1299   if (cfun->can_throw_non_call_exceptions)
1300     {
1301       sbitmap blocks;
1302       blocks = sbitmap_alloc (last_basic_block);
1303       bitmap_ones (blocks);
1304       find_many_sub_basic_blocks (blocks);
1305       sbitmap_free (blocks);
1306     }
1307
1308   if (inserted)
1309     commit_edge_insertions ();
1310
1311   /* Replacing pseudos with their memory equivalents might have
1312      created shared rtx.  Subsequent passes would get confused
1313      by this, so unshare everything here.  */
1314   unshare_all_rtl_again (first);
1315
1316 #ifdef STACK_BOUNDARY
1317   /* init_emit has set the alignment of the hard frame pointer
1318      to STACK_BOUNDARY.  It is very likely no longer valid if
1319      the hard frame pointer was used for register allocation.  */
1320   if (!frame_pointer_needed)
1321     REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1322 #endif
1323
1324   substitute_stack.release ();
1325
1326   gcc_assert (bitmap_empty_p (&spilled_pseudos));
1327
1328   reload_completed = !failure;
1329
1330   return need_dce;
1331 }
1332
1333 /* Yet another special case.  Unfortunately, reg-stack forces people to
1334    write incorrect clobbers in asm statements.  These clobbers must not
1335    cause the register to appear in bad_spill_regs, otherwise we'll call
1336    fatal_insn later.  We clear the corresponding regnos in the live
1337    register sets to avoid this.
1338    The whole thing is rather sick, I'm afraid.  */
1339
1340 static void
1341 maybe_fix_stack_asms (void)
1342 {
1343 #ifdef STACK_REGS
1344   const char *constraints[MAX_RECOG_OPERANDS];
1345   enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1346   struct insn_chain *chain;
1347
1348   for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1349     {
1350       int i, noperands;
1351       HARD_REG_SET clobbered, allowed;
1352       rtx pat;
1353
1354       if (! INSN_P (chain->insn)
1355           || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1356         continue;
1357       pat = PATTERN (chain->insn);
1358       if (GET_CODE (pat) != PARALLEL)
1359         continue;
1360
1361       CLEAR_HARD_REG_SET (clobbered);
1362       CLEAR_HARD_REG_SET (allowed);
1363
1364       /* First, make a mask of all stack regs that are clobbered.  */
1365       for (i = 0; i < XVECLEN (pat, 0); i++)
1366         {
1367           rtx t = XVECEXP (pat, 0, i);
1368           if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1369             SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1370         }
1371
1372       /* Get the operand values and constraints out of the insn.  */
1373       decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1374                            constraints, operand_mode, NULL);
1375
1376       /* For every operand, see what registers are allowed.  */
1377       for (i = 0; i < noperands; i++)
1378         {
1379           const char *p = constraints[i];
1380           /* For every alternative, we compute the class of registers allowed
1381              for reloading in CLS, and merge its contents into the reg set
1382              ALLOWED.  */
1383           int cls = (int) NO_REGS;
1384
1385           for (;;)
1386             {
1387               char c = *p;
1388
1389               if (c == '\0' || c == ',' || c == '#')
1390                 {
1391                   /* End of one alternative - mark the regs in the current
1392                      class, and reset the class.  */
1393                   IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1394                   cls = NO_REGS;
1395                   p++;
1396                   if (c == '#')
1397                     do {
1398                       c = *p++;
1399                     } while (c != '\0' && c != ',');
1400                   if (c == '\0')
1401                     break;
1402                   continue;
1403                 }
1404
1405               switch (c)
1406                 {
1407                 case '=': case '+': case '*': case '%': case '?': case '!':
1408                 case '0': case '1': case '2': case '3': case '4': case '<':
1409                 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1410                 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1411                 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1412                 case TARGET_MEM_CONSTRAINT:
1413                   break;
1414
1415                 case 'p':
1416                   cls = (int) reg_class_subunion[cls]
1417                       [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1418                                              ADDRESS, SCRATCH)];
1419                   break;
1420
1421                 case 'g':
1422                 case 'r':
1423                   cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1424                   break;
1425
1426                 default:
1427                   if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1428                     cls = (int) reg_class_subunion[cls]
1429                       [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1430                                              ADDRESS, SCRATCH)];
1431                   else
1432                     cls = (int) reg_class_subunion[cls]
1433                       [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1434                 }
1435               p += CONSTRAINT_LEN (c, p);
1436             }
1437         }
1438       /* Those of the registers which are clobbered, but allowed by the
1439          constraints, must be usable as reload registers.  So clear them
1440          out of the life information.  */
1441       AND_HARD_REG_SET (allowed, clobbered);
1442       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1443         if (TEST_HARD_REG_BIT (allowed, i))
1444           {
1445             CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1446             CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1447           }
1448     }
1449
1450 #endif
1451 }
1452 \f
1453 /* Copy the global variables n_reloads and rld into the corresponding elts
1454    of CHAIN.  */
1455 static void
1456 copy_reloads (struct insn_chain *chain)
1457 {
1458   chain->n_reloads = n_reloads;
1459   chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1460   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1461   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1462 }
1463
1464 /* Walk the chain of insns, and determine for each whether it needs reloads
1465    and/or eliminations.  Build the corresponding insns_need_reload list, and
1466    set something_needs_elimination as appropriate.  */
1467 static void
1468 calculate_needs_all_insns (int global)
1469 {
1470   struct insn_chain **pprev_reload = &insns_need_reload;
1471   struct insn_chain *chain, *next = 0;
1472
1473   something_needs_elimination = 0;
1474
1475   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1476   for (chain = reload_insn_chain; chain != 0; chain = next)
1477     {
1478       rtx insn = chain->insn;
1479
1480       next = chain->next;
1481
1482       /* Clear out the shortcuts.  */
1483       chain->n_reloads = 0;
1484       chain->need_elim = 0;
1485       chain->need_reload = 0;
1486       chain->need_operand_change = 0;
1487
1488       /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1489          include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1490          what effects this has on the known offsets at labels.  */
1491
1492       if (LABEL_P (insn) || JUMP_P (insn)
1493           || (INSN_P (insn) && REG_NOTES (insn) != 0))
1494         set_label_offsets (insn, insn, 0);
1495
1496       if (INSN_P (insn))
1497         {
1498           rtx old_body = PATTERN (insn);
1499           int old_code = INSN_CODE (insn);
1500           rtx old_notes = REG_NOTES (insn);
1501           int did_elimination = 0;
1502           int operands_changed = 0;
1503           rtx set = single_set (insn);
1504
1505           /* Skip insns that only set an equivalence.  */
1506           if (set && REG_P (SET_DEST (set))
1507               && reg_renumber[REGNO (SET_DEST (set))] < 0
1508               && (reg_equiv_constant (REGNO (SET_DEST (set)))
1509                   || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1510                       && reg_equiv_init (REGNO (SET_DEST (set))))
1511             continue;
1512
1513           /* If needed, eliminate any eliminable registers.  */
1514           if (num_eliminable || num_eliminable_invariants)
1515             did_elimination = eliminate_regs_in_insn (insn, 0);
1516
1517           /* Analyze the instruction.  */
1518           operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1519                                            global, spill_reg_order);
1520
1521           /* If a no-op set needs more than one reload, this is likely
1522              to be something that needs input address reloads.  We
1523              can't get rid of this cleanly later, and it is of no use
1524              anyway, so discard it now.
1525              We only do this when expensive_optimizations is enabled,
1526              since this complements reload inheritance / output
1527              reload deletion, and it can make debugging harder.  */
1528           if (flag_expensive_optimizations && n_reloads > 1)
1529             {
1530               rtx set = single_set (insn);
1531               if (set
1532                   &&
1533                   ((SET_SRC (set) == SET_DEST (set)
1534                     && REG_P (SET_SRC (set))
1535                     && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1536                    || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1537                        && reg_renumber[REGNO (SET_SRC (set))] < 0
1538                        && reg_renumber[REGNO (SET_DEST (set))] < 0
1539                        && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1540                        && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1541                        && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1542                                        reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1543                 {
1544                   if (ira_conflicts_p)
1545                     /* Inform IRA about the insn deletion.  */
1546                     ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1547                                                    REGNO (SET_SRC (set)));
1548                   delete_insn (insn);
1549                   /* Delete it from the reload chain.  */
1550                   if (chain->prev)
1551                     chain->prev->next = next;
1552                   else
1553                     reload_insn_chain = next;
1554                   if (next)
1555                     next->prev = chain->prev;
1556                   chain->next = unused_insn_chains;
1557                   unused_insn_chains = chain;
1558                   continue;
1559                 }
1560             }
1561           if (num_eliminable)
1562             update_eliminable_offsets ();
1563
1564           /* Remember for later shortcuts which insns had any reloads or
1565              register eliminations.  */
1566           chain->need_elim = did_elimination;
1567           chain->need_reload = n_reloads > 0;
1568           chain->need_operand_change = operands_changed;
1569
1570           /* Discard any register replacements done.  */
1571           if (did_elimination)
1572             {
1573               obstack_free (&reload_obstack, reload_insn_firstobj);
1574               PATTERN (insn) = old_body;
1575               INSN_CODE (insn) = old_code;
1576               REG_NOTES (insn) = old_notes;
1577               something_needs_elimination = 1;
1578             }
1579
1580           something_needs_operands_changed |= operands_changed;
1581
1582           if (n_reloads != 0)
1583             {
1584               copy_reloads (chain);
1585               *pprev_reload = chain;
1586               pprev_reload = &chain->next_need_reload;
1587             }
1588         }
1589     }
1590   *pprev_reload = 0;
1591 }
1592 \f
1593 /* This function is called from the register allocator to set up estimates
1594    for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1595    an invariant.  The structure is similar to calculate_needs_all_insns.  */
1596
1597 void
1598 calculate_elim_costs_all_insns (void)
1599 {
1600   int *reg_equiv_init_cost;
1601   basic_block bb;
1602   int i;
1603
1604   reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1605   init_elim_table ();
1606   init_eliminable_invariants (get_insns (), false);
1607
1608   set_initial_elim_offsets ();
1609   set_initial_label_offsets ();
1610
1611   FOR_EACH_BB (bb)
1612     {
1613       rtx insn;
1614       elim_bb = bb;
1615
1616       FOR_BB_INSNS (bb, insn)
1617         {
1618           /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1619              include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1620              what effects this has on the known offsets at labels.  */
1621
1622           if (LABEL_P (insn) || JUMP_P (insn)
1623               || (INSN_P (insn) && REG_NOTES (insn) != 0))
1624             set_label_offsets (insn, insn, 0);
1625
1626           if (INSN_P (insn))
1627             {
1628               rtx set = single_set (insn);
1629
1630               /* Skip insns that only set an equivalence.  */
1631               if (set && REG_P (SET_DEST (set))
1632                   && reg_renumber[REGNO (SET_DEST (set))] < 0
1633                   && (reg_equiv_constant (REGNO (SET_DEST (set)))
1634                       || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1635                 {
1636                   unsigned regno = REGNO (SET_DEST (set));
1637                   rtx init = reg_equiv_init (regno);
1638                   if (init)
1639                     {
1640                       rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1641                                                 false, true);
1642                       int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1643                       int freq = REG_FREQ_FROM_BB (bb);
1644
1645                       reg_equiv_init_cost[regno] = cost * freq;
1646                       continue;
1647                     }
1648                 }
1649               /* If needed, eliminate any eliminable registers.  */
1650               if (num_eliminable || num_eliminable_invariants)
1651                 elimination_costs_in_insn (insn);
1652
1653               if (num_eliminable)
1654                 update_eliminable_offsets ();
1655             }
1656         }
1657     }
1658   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1659     {
1660       if (reg_equiv_invariant (i))
1661         {
1662           if (reg_equiv_init (i))
1663             {
1664               int cost = reg_equiv_init_cost[i];
1665               if (dump_file)
1666                 fprintf (dump_file,
1667                          "Reg %d has equivalence, initial gains %d\n", i, cost);
1668               if (cost != 0)
1669                 ira_adjust_equiv_reg_cost (i, cost);
1670             }
1671           else
1672             {
1673               if (dump_file)
1674                 fprintf (dump_file,
1675                          "Reg %d had equivalence, but can't be eliminated\n",
1676                          i);
1677               ira_adjust_equiv_reg_cost (i, 0);
1678             }
1679         }
1680     }
1681
1682   free (reg_equiv_init_cost);
1683   free (offsets_known_at);
1684   free (offsets_at);
1685   offsets_at = NULL;
1686   offsets_known_at = NULL;
1687 }
1688 \f
1689 /* Comparison function for qsort to decide which of two reloads
1690    should be handled first.  *P1 and *P2 are the reload numbers.  */
1691
1692 static int
1693 reload_reg_class_lower (const void *r1p, const void *r2p)
1694 {
1695   int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1696   int t;
1697
1698   /* Consider required reloads before optional ones.  */
1699   t = rld[r1].optional - rld[r2].optional;
1700   if (t != 0)
1701     return t;
1702
1703   /* Count all solitary classes before non-solitary ones.  */
1704   t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1705        - (reg_class_size[(int) rld[r1].rclass] == 1));
1706   if (t != 0)
1707     return t;
1708
1709   /* Aside from solitaires, consider all multi-reg groups first.  */
1710   t = rld[r2].nregs - rld[r1].nregs;
1711   if (t != 0)
1712     return t;
1713
1714   /* Consider reloads in order of increasing reg-class number.  */
1715   t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1716   if (t != 0)
1717     return t;
1718
1719   /* If reloads are equally urgent, sort by reload number,
1720      so that the results of qsort leave nothing to chance.  */
1721   return r1 - r2;
1722 }
1723 \f
1724 /* The cost of spilling each hard reg.  */
1725 static int spill_cost[FIRST_PSEUDO_REGISTER];
1726
1727 /* When spilling multiple hard registers, we use SPILL_COST for the first
1728    spilled hard reg and SPILL_ADD_COST for subsequent regs.  SPILL_ADD_COST
1729    only the first hard reg for a multi-reg pseudo.  */
1730 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1731
1732 /* Map of hard regno to pseudo regno currently occupying the hard
1733    reg.  */
1734 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1735
1736 /* Update the spill cost arrays, considering that pseudo REG is live.  */
1737
1738 static void
1739 count_pseudo (int reg)
1740 {
1741   int freq = REG_FREQ (reg);
1742   int r = reg_renumber[reg];
1743   int nregs;
1744
1745   /* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
1746   if (ira_conflicts_p && r < 0)
1747     return;
1748
1749   if (REGNO_REG_SET_P (&pseudos_counted, reg)
1750       || REGNO_REG_SET_P (&spilled_pseudos, reg))
1751     return;
1752
1753   SET_REGNO_REG_SET (&pseudos_counted, reg);
1754
1755   gcc_assert (r >= 0);
1756
1757   spill_add_cost[r] += freq;
1758   nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1759   while (nregs-- > 0)
1760     {
1761       hard_regno_to_pseudo_regno[r + nregs] = reg;
1762       spill_cost[r + nregs] += freq;
1763     }
1764 }
1765
1766 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1767    contents of BAD_SPILL_REGS for the insn described by CHAIN.  */
1768
1769 static void
1770 order_regs_for_reload (struct insn_chain *chain)
1771 {
1772   unsigned i;
1773   HARD_REG_SET used_by_pseudos;
1774   HARD_REG_SET used_by_pseudos2;
1775   reg_set_iterator rsi;
1776
1777   COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1778
1779   memset (spill_cost, 0, sizeof spill_cost);
1780   memset (spill_add_cost, 0, sizeof spill_add_cost);
1781   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1782     hard_regno_to_pseudo_regno[i] = -1;
1783
1784   /* Count number of uses of each hard reg by pseudo regs allocated to it
1785      and then order them by decreasing use.  First exclude hard registers
1786      that are live in or across this insn.  */
1787
1788   REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1789   REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1790   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1791   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1792
1793   /* Now find out which pseudos are allocated to it, and update
1794      hard_reg_n_uses.  */
1795   CLEAR_REG_SET (&pseudos_counted);
1796
1797   EXECUTE_IF_SET_IN_REG_SET
1798     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1799     {
1800       count_pseudo (i);
1801     }
1802   EXECUTE_IF_SET_IN_REG_SET
1803     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1804     {
1805       count_pseudo (i);
1806     }
1807   CLEAR_REG_SET (&pseudos_counted);
1808 }
1809 \f
1810 /* Vector of reload-numbers showing the order in which the reloads should
1811    be processed.  */
1812 static short reload_order[MAX_RELOADS];
1813
1814 /* This is used to keep track of the spill regs used in one insn.  */
1815 static HARD_REG_SET used_spill_regs_local;
1816
1817 /* We decided to spill hard register SPILLED, which has a size of
1818    SPILLED_NREGS.  Determine how pseudo REG, which is live during the insn,
1819    is affected.  We will add it to SPILLED_PSEUDOS if necessary, and we will
1820    update SPILL_COST/SPILL_ADD_COST.  */
1821
1822 static void
1823 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1824 {
1825   int freq = REG_FREQ (reg);
1826   int r = reg_renumber[reg];
1827   int nregs;
1828
1829   /* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
1830   if (ira_conflicts_p && r < 0)
1831     return;
1832
1833   gcc_assert (r >= 0);
1834
1835   nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1836
1837   if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1838       || spilled + spilled_nregs <= r || r + nregs <= spilled)
1839     return;
1840
1841   SET_REGNO_REG_SET (&spilled_pseudos, reg);
1842
1843   spill_add_cost[r] -= freq;
1844   while (nregs-- > 0)
1845     {
1846       hard_regno_to_pseudo_regno[r + nregs] = -1;
1847       spill_cost[r + nregs] -= freq;
1848     }
1849 }
1850
1851 /* Find reload register to use for reload number ORDER.  */
1852
1853 static int
1854 find_reg (struct insn_chain *chain, int order)
1855 {
1856   int rnum = reload_order[order];
1857   struct reload *rl = rld + rnum;
1858   int best_cost = INT_MAX;
1859   int best_reg = -1;
1860   unsigned int i, j, n;
1861   int k;
1862   HARD_REG_SET not_usable;
1863   HARD_REG_SET used_by_other_reload;
1864   reg_set_iterator rsi;
1865   static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1866   static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1867
1868   COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1869   IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1870   IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1871
1872   CLEAR_HARD_REG_SET (used_by_other_reload);
1873   for (k = 0; k < order; k++)
1874     {
1875       int other = reload_order[k];
1876
1877       if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1878         for (j = 0; j < rld[other].nregs; j++)
1879           SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1880     }
1881
1882   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1883     {
1884 #ifdef REG_ALLOC_ORDER
1885       unsigned int regno = reg_alloc_order[i];
1886 #else
1887       unsigned int regno = i;
1888 #endif
1889
1890       if (! TEST_HARD_REG_BIT (not_usable, regno)
1891           && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1892           && HARD_REGNO_MODE_OK (regno, rl->mode))
1893         {
1894           int this_cost = spill_cost[regno];
1895           int ok = 1;
1896           unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1897
1898           for (j = 1; j < this_nregs; j++)
1899             {
1900               this_cost += spill_add_cost[regno + j];
1901               if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1902                   || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1903                 ok = 0;
1904             }
1905           if (! ok)
1906             continue;
1907
1908           if (ira_conflicts_p)
1909             {
1910               /* Ask IRA to find a better pseudo-register for
1911                  spilling.  */
1912               for (n = j = 0; j < this_nregs; j++)
1913                 {
1914                   int r = hard_regno_to_pseudo_regno[regno + j];
1915
1916                   if (r < 0)
1917                     continue;
1918                   if (n == 0 || regno_pseudo_regs[n - 1] != r)
1919                     regno_pseudo_regs[n++] = r;
1920                 }
1921               regno_pseudo_regs[n++] = -1;
1922               if (best_reg < 0
1923                   || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1924                                                       best_regno_pseudo_regs,
1925                                                       rl->in, rl->out,
1926                                                       chain->insn))
1927                 {
1928                   best_reg = regno;
1929                   for (j = 0;; j++)
1930                     {
1931                       best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1932                       if (regno_pseudo_regs[j] < 0)
1933                         break;
1934                     }
1935                 }
1936               continue;
1937             }
1938
1939           if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1940             this_cost--;
1941           if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1942             this_cost--;
1943           if (this_cost < best_cost
1944               /* Among registers with equal cost, prefer caller-saved ones, or
1945                  use REG_ALLOC_ORDER if it is defined.  */
1946               || (this_cost == best_cost
1947 #ifdef REG_ALLOC_ORDER
1948                   && (inv_reg_alloc_order[regno]
1949                       < inv_reg_alloc_order[best_reg])
1950 #else
1951                   && call_used_regs[regno]
1952                   && ! call_used_regs[best_reg]
1953 #endif
1954                   ))
1955             {
1956               best_reg = regno;
1957               best_cost = this_cost;
1958             }
1959         }
1960     }
1961   if (best_reg == -1)
1962     return 0;
1963
1964   if (dump_file)
1965     fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1966
1967   rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1968   rl->regno = best_reg;
1969
1970   EXECUTE_IF_SET_IN_REG_SET
1971     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1972     {
1973       count_spilled_pseudo (best_reg, rl->nregs, j);
1974     }
1975
1976   EXECUTE_IF_SET_IN_REG_SET
1977     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1978     {
1979       count_spilled_pseudo (best_reg, rl->nregs, j);
1980     }
1981
1982   for (i = 0; i < rl->nregs; i++)
1983     {
1984       gcc_assert (spill_cost[best_reg + i] == 0);
1985       gcc_assert (spill_add_cost[best_reg + i] == 0);
1986       gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1987       SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1988     }
1989   return 1;
1990 }
1991
1992 /* Find more reload regs to satisfy the remaining need of an insn, which
1993    is given by CHAIN.
1994    Do it by ascending class number, since otherwise a reg
1995    might be spilled for a big class and might fail to count
1996    for a smaller class even though it belongs to that class.  */
1997
1998 static void
1999 find_reload_regs (struct insn_chain *chain)
2000 {
2001   int i;
2002
2003   /* In order to be certain of getting the registers we need,
2004      we must sort the reloads into order of increasing register class.
2005      Then our grabbing of reload registers will parallel the process
2006      that provided the reload registers.  */
2007   for (i = 0; i < chain->n_reloads; i++)
2008     {
2009       /* Show whether this reload already has a hard reg.  */
2010       if (chain->rld[i].reg_rtx)
2011         {
2012           int regno = REGNO (chain->rld[i].reg_rtx);
2013           chain->rld[i].regno = regno;
2014           chain->rld[i].nregs
2015             = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2016         }
2017       else
2018         chain->rld[i].regno = -1;
2019       reload_order[i] = i;
2020     }
2021
2022   n_reloads = chain->n_reloads;
2023   memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2024
2025   CLEAR_HARD_REG_SET (used_spill_regs_local);
2026
2027   if (dump_file)
2028     fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2029
2030   qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2031
2032   /* Compute the order of preference for hard registers to spill.  */
2033
2034   order_regs_for_reload (chain);
2035
2036   for (i = 0; i < n_reloads; i++)
2037     {
2038       int r = reload_order[i];
2039
2040       /* Ignore reloads that got marked inoperative.  */
2041       if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2042           && ! rld[r].optional
2043           && rld[r].regno == -1)
2044         if (! find_reg (chain, i))
2045           {
2046             if (dump_file)
2047               fprintf (dump_file, "reload failure for reload %d\n", r);
2048             spill_failure (chain->insn, rld[r].rclass);
2049             failure = 1;
2050             return;
2051           }
2052     }
2053
2054   COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2055   IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2056
2057   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2058 }
2059
2060 static void
2061 select_reload_regs (void)
2062 {
2063   struct insn_chain *chain;
2064
2065   /* Try to satisfy the needs for each insn.  */
2066   for (chain = insns_need_reload; chain != 0;
2067        chain = chain->next_need_reload)
2068     find_reload_regs (chain);
2069 }
2070 \f
2071 /* Delete all insns that were inserted by emit_caller_save_insns during
2072    this iteration.  */
2073 static void
2074 delete_caller_save_insns (void)
2075 {
2076   struct insn_chain *c = reload_insn_chain;
2077
2078   while (c != 0)
2079     {
2080       while (c != 0 && c->is_caller_save_insn)
2081         {
2082           struct insn_chain *next = c->next;
2083           rtx insn = c->insn;
2084
2085           if (c == reload_insn_chain)
2086             reload_insn_chain = next;
2087           delete_insn (insn);
2088
2089           if (next)
2090             next->prev = c->prev;
2091           if (c->prev)
2092             c->prev->next = next;
2093           c->next = unused_insn_chains;
2094           unused_insn_chains = c;
2095           c = next;
2096         }
2097       if (c != 0)
2098         c = c->next;
2099     }
2100 }
2101 \f
2102 /* Handle the failure to find a register to spill.
2103    INSN should be one of the insns which needed this particular spill reg.  */
2104
2105 static void
2106 spill_failure (rtx insn, enum reg_class rclass)
2107 {
2108   if (asm_noperands (PATTERN (insn)) >= 0)
2109     error_for_asm (insn, "can%'t find a register in class %qs while "
2110                    "reloading %<asm%>",
2111                    reg_class_names[rclass]);
2112   else
2113     {
2114       error ("unable to find a register to spill in class %qs",
2115              reg_class_names[rclass]);
2116
2117       if (dump_file)
2118         {
2119           fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2120           debug_reload_to_stream (dump_file);
2121         }
2122       fatal_insn ("this is the insn:", insn);
2123     }
2124 }
2125 \f
2126 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2127    data that is dead in INSN.  */
2128
2129 static void
2130 delete_dead_insn (rtx insn)
2131 {
2132   rtx prev = prev_active_insn (insn);
2133   rtx prev_dest;
2134
2135   /* If the previous insn sets a register that dies in our insn make
2136      a note that we want to run DCE immediately after reload.
2137
2138      We used to delete the previous insn & recurse, but that's wrong for
2139      block local equivalences.  Instead of trying to figure out the exact
2140      circumstances where we can delete the potentially dead insns, just
2141      let DCE do the job.  */
2142   if (prev && GET_CODE (PATTERN (prev)) == SET
2143       && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2144       && reg_mentioned_p (prev_dest, PATTERN (insn))
2145       && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2146       && ! side_effects_p (SET_SRC (PATTERN (prev))))
2147     need_dce = 1;
2148
2149   SET_INSN_DELETED (insn);
2150 }
2151
2152 /* Modify the home of pseudo-reg I.
2153    The new home is present in reg_renumber[I].
2154
2155    FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2156    or it may be -1, meaning there is none or it is not relevant.
2157    This is used so that all pseudos spilled from a given hard reg
2158    can share one stack slot.  */
2159
2160 static void
2161 alter_reg (int i, int from_reg, bool dont_share_p)
2162 {
2163   /* When outputting an inline function, this can happen
2164      for a reg that isn't actually used.  */
2165   if (regno_reg_rtx[i] == 0)
2166     return;
2167
2168   /* If the reg got changed to a MEM at rtl-generation time,
2169      ignore it.  */
2170   if (!REG_P (regno_reg_rtx[i]))
2171     return;
2172
2173   /* Modify the reg-rtx to contain the new hard reg
2174      number or else to contain its pseudo reg number.  */
2175   SET_REGNO (regno_reg_rtx[i],
2176              reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2177
2178   /* If we have a pseudo that is needed but has no hard reg or equivalent,
2179      allocate a stack slot for it.  */
2180
2181   if (reg_renumber[i] < 0
2182       && REG_N_REFS (i) > 0
2183       && reg_equiv_constant (i) == 0
2184       && (reg_equiv_invariant (i) == 0
2185           || reg_equiv_init (i) == 0)
2186       && reg_equiv_memory_loc (i) == 0)
2187     {
2188       rtx x = NULL_RTX;
2189       enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2190       unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2191       unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2192       unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2193       unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2194       int adjust = 0;
2195
2196       something_was_spilled = true;
2197
2198       if (ira_conflicts_p)
2199         {
2200           /* Mark the spill for IRA.  */
2201           SET_REGNO_REG_SET (&spilled_pseudos, i);
2202           if (!dont_share_p)
2203             x = ira_reuse_stack_slot (i, inherent_size, total_size);
2204         }
2205
2206       if (x)
2207         ;
2208
2209       /* Each pseudo reg has an inherent size which comes from its own mode,
2210          and a total size which provides room for paradoxical subregs
2211          which refer to the pseudo reg in wider modes.
2212
2213          We can use a slot already allocated if it provides both
2214          enough inherent space and enough total space.
2215          Otherwise, we allocate a new slot, making sure that it has no less
2216          inherent space, and no less total space, then the previous slot.  */
2217       else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2218         {
2219           rtx stack_slot;
2220
2221           /* No known place to spill from => no slot to reuse.  */
2222           x = assign_stack_local (mode, total_size,
2223                                   min_align > inherent_align
2224                                   || total_size > inherent_size ? -1 : 0);
2225
2226           stack_slot = x;
2227
2228           /* Cancel the big-endian correction done in assign_stack_local.
2229              Get the address of the beginning of the slot.  This is so we
2230              can do a big-endian correction unconditionally below.  */
2231           if (BYTES_BIG_ENDIAN)
2232             {
2233               adjust = inherent_size - total_size;
2234               if (adjust)
2235                 stack_slot
2236                   = adjust_address_nv (x, mode_for_size (total_size
2237                                                          * BITS_PER_UNIT,
2238                                                          MODE_INT, 1),
2239                                        adjust);
2240             }
2241
2242           if (! dont_share_p && ira_conflicts_p)
2243             /* Inform IRA about allocation a new stack slot.  */
2244             ira_mark_new_stack_slot (stack_slot, i, total_size);
2245         }
2246
2247       /* Reuse a stack slot if possible.  */
2248       else if (spill_stack_slot[from_reg] != 0
2249                && spill_stack_slot_width[from_reg] >= total_size
2250                && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2251                    >= inherent_size)
2252                && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2253         x = spill_stack_slot[from_reg];
2254
2255       /* Allocate a bigger slot.  */
2256       else
2257         {
2258           /* Compute maximum size needed, both for inherent size
2259              and for total size.  */
2260           rtx stack_slot;
2261
2262           if (spill_stack_slot[from_reg])
2263             {
2264               if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2265                   > inherent_size)
2266                 mode = GET_MODE (spill_stack_slot[from_reg]);
2267               if (spill_stack_slot_width[from_reg] > total_size)
2268                 total_size = spill_stack_slot_width[from_reg];
2269               if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2270                 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2271             }
2272
2273           /* Make a slot with that size.  */
2274           x = assign_stack_local (mode, total_size,
2275                                   min_align > inherent_align
2276                                   || total_size > inherent_size ? -1 : 0);
2277           stack_slot = x;
2278
2279           /* Cancel the  big-endian correction done in assign_stack_local.
2280              Get the address of the beginning of the slot.  This is so we
2281              can do a big-endian correction unconditionally below.  */
2282           if (BYTES_BIG_ENDIAN)
2283             {
2284               adjust = GET_MODE_SIZE (mode) - total_size;
2285               if (adjust)
2286                 stack_slot
2287                   = adjust_address_nv (x, mode_for_size (total_size
2288                                                          * BITS_PER_UNIT,
2289                                                          MODE_INT, 1),
2290                                        adjust);
2291             }
2292
2293           spill_stack_slot[from_reg] = stack_slot;
2294           spill_stack_slot_width[from_reg] = total_size;
2295         }
2296
2297       /* On a big endian machine, the "address" of the slot
2298          is the address of the low part that fits its inherent mode.  */
2299       if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2300         adjust += (total_size - inherent_size);
2301
2302       /* If we have any adjustment to make, or if the stack slot is the
2303          wrong mode, make a new stack slot.  */
2304       x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2305
2306       /* Set all of the memory attributes as appropriate for a spill.  */
2307       set_mem_attrs_for_spill (x);
2308
2309       /* Save the stack slot for later.  */
2310       reg_equiv_memory_loc (i) = x;
2311     }
2312 }
2313
2314 /* Mark the slots in regs_ever_live for the hard regs used by
2315    pseudo-reg number REGNO, accessed in MODE.  */
2316
2317 static void
2318 mark_home_live_1 (int regno, enum machine_mode mode)
2319 {
2320   int i, lim;
2321
2322   i = reg_renumber[regno];
2323   if (i < 0)
2324     return;
2325   lim = end_hard_regno (mode, i);
2326   while (i < lim)
2327     df_set_regs_ever_live(i++, true);
2328 }
2329
2330 /* Mark the slots in regs_ever_live for the hard regs
2331    used by pseudo-reg number REGNO.  */
2332
2333 void
2334 mark_home_live (int regno)
2335 {
2336   if (reg_renumber[regno] >= 0)
2337     mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2338 }
2339 \f
2340 /* This function handles the tracking of elimination offsets around branches.
2341
2342    X is a piece of RTL being scanned.
2343
2344    INSN is the insn that it came from, if any.
2345
2346    INITIAL_P is nonzero if we are to set the offset to be the initial
2347    offset and zero if we are setting the offset of the label to be the
2348    current offset.  */
2349
2350 static void
2351 set_label_offsets (rtx x, rtx insn, int initial_p)
2352 {
2353   enum rtx_code code = GET_CODE (x);
2354   rtx tem;
2355   unsigned int i;
2356   struct elim_table *p;
2357
2358   switch (code)
2359     {
2360     case LABEL_REF:
2361       if (LABEL_REF_NONLOCAL_P (x))
2362         return;
2363
2364       x = XEXP (x, 0);
2365
2366       /* ... fall through ...  */
2367
2368     case CODE_LABEL:
2369       /* If we know nothing about this label, set the desired offsets.  Note
2370          that this sets the offset at a label to be the offset before a label
2371          if we don't know anything about the label.  This is not correct for
2372          the label after a BARRIER, but is the best guess we can make.  If
2373          we guessed wrong, we will suppress an elimination that might have
2374          been possible had we been able to guess correctly.  */
2375
2376       if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2377         {
2378           for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2379             offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2380               = (initial_p ? reg_eliminate[i].initial_offset
2381                  : reg_eliminate[i].offset);
2382           offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2383         }
2384
2385       /* Otherwise, if this is the definition of a label and it is
2386          preceded by a BARRIER, set our offsets to the known offset of
2387          that label.  */
2388
2389       else if (x == insn
2390                && (tem = prev_nonnote_insn (insn)) != 0
2391                && BARRIER_P (tem))
2392         set_offsets_for_label (insn);
2393       else
2394         /* If neither of the above cases is true, compare each offset
2395            with those previously recorded and suppress any eliminations
2396            where the offsets disagree.  */
2397
2398         for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2399           if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2400               != (initial_p ? reg_eliminate[i].initial_offset
2401                   : reg_eliminate[i].offset))
2402             reg_eliminate[i].can_eliminate = 0;
2403
2404       return;
2405
2406     case JUMP_INSN:
2407       set_label_offsets (PATTERN (insn), insn, initial_p);
2408
2409       /* ... fall through ...  */
2410
2411     case INSN:
2412     case CALL_INSN:
2413       /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2414          to indirectly and hence must have all eliminations at their
2415          initial offsets.  */
2416       for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2417         if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2418           set_label_offsets (XEXP (tem, 0), insn, 1);
2419       return;
2420
2421     case PARALLEL:
2422     case ADDR_VEC:
2423     case ADDR_DIFF_VEC:
2424       /* Each of the labels in the parallel or address vector must be
2425          at their initial offsets.  We want the first field for PARALLEL
2426          and ADDR_VEC and the second field for ADDR_DIFF_VEC.  */
2427
2428       for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2429         set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2430                            insn, initial_p);
2431       return;
2432
2433     case SET:
2434       /* We only care about setting PC.  If the source is not RETURN,
2435          IF_THEN_ELSE, or a label, disable any eliminations not at
2436          their initial offsets.  Similarly if any arm of the IF_THEN_ELSE
2437          isn't one of those possibilities.  For branches to a label,
2438          call ourselves recursively.
2439
2440          Note that this can disable elimination unnecessarily when we have
2441          a non-local goto since it will look like a non-constant jump to
2442          someplace in the current function.  This isn't a significant
2443          problem since such jumps will normally be when all elimination
2444          pairs are back to their initial offsets.  */
2445
2446       if (SET_DEST (x) != pc_rtx)
2447         return;
2448
2449       switch (GET_CODE (SET_SRC (x)))
2450         {
2451         case PC:
2452         case RETURN:
2453           return;
2454
2455         case LABEL_REF:
2456           set_label_offsets (SET_SRC (x), insn, initial_p);
2457           return;
2458
2459         case IF_THEN_ELSE:
2460           tem = XEXP (SET_SRC (x), 1);
2461           if (GET_CODE (tem) == LABEL_REF)
2462             set_label_offsets (XEXP (tem, 0), insn, initial_p);
2463           else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2464             break;
2465
2466           tem = XEXP (SET_SRC (x), 2);
2467           if (GET_CODE (tem) == LABEL_REF)
2468             set_label_offsets (XEXP (tem, 0), insn, initial_p);
2469           else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2470             break;
2471           return;
2472
2473         default:
2474           break;
2475         }
2476
2477       /* If we reach here, all eliminations must be at their initial
2478          offset because we are doing a jump to a variable address.  */
2479       for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
2480         if (p->offset != p->initial_offset)
2481           p->can_eliminate = 0;
2482       break;
2483
2484     default:
2485       break;
2486     }
2487 }
2488 \f
2489 /* Called through for_each_rtx, this function examines every reg that occurs
2490    in PX and adjusts the costs for its elimination which are gathered by IRA.
2491    DATA is the insn in which PX occurs.  We do not recurse into MEM
2492    expressions.  */
2493
2494 static int
2495 note_reg_elim_costly (rtx *px, void *data)
2496 {
2497   rtx insn = (rtx)data;
2498   rtx x = *px;
2499
2500   if (MEM_P (x))
2501     return -1;
2502
2503   if (REG_P (x)
2504       && REGNO (x) >= FIRST_PSEUDO_REGISTER
2505       && reg_equiv_init (REGNO (x))
2506       && reg_equiv_invariant (REGNO (x)))
2507     {
2508       rtx t = reg_equiv_invariant (REGNO (x));
2509       rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2510       int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2511       int freq = REG_FREQ_FROM_BB (elim_bb);
2512
2513       if (cost != 0)
2514         ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2515     }
2516   return 0;
2517 }
2518
2519 /* Scan X and replace any eliminable registers (such as fp) with a
2520    replacement (such as sp), plus an offset.
2521
2522    MEM_MODE is the mode of an enclosing MEM.  We need this to know how
2523    much to adjust a register for, e.g., PRE_DEC.  Also, if we are inside a
2524    MEM, we are allowed to replace a sum of a register and the constant zero
2525    with the register, which we cannot do outside a MEM.  In addition, we need
2526    to record the fact that a register is referenced outside a MEM.
2527
2528    If INSN is an insn, it is the insn containing X.  If we replace a REG
2529    in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2530    CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2531    the REG is being modified.
2532
2533    Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2534    That's used when we eliminate in expressions stored in notes.
2535    This means, do not set ref_outside_mem even if the reference
2536    is outside of MEMs.
2537
2538    If FOR_COSTS is true, we are being called before reload in order to
2539    estimate the costs of keeping registers with an equivalence unallocated.
2540
2541    REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2542    replacements done assuming all offsets are at their initial values.  If
2543    they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2544    encounter, return the actual location so that find_reloads will do
2545    the proper thing.  */
2546
2547 static rtx
2548 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2549                   bool may_use_invariant, bool for_costs)
2550 {
2551   enum rtx_code code = GET_CODE (x);
2552   struct elim_table *ep;
2553   int regno;
2554   rtx new_rtx;
2555   int i, j;
2556   const char *fmt;
2557   int copied = 0;
2558
2559   if (! current_function_decl)
2560     return x;
2561
2562   switch (code)
2563     {
2564     CASE_CONST_ANY:
2565     case CONST:
2566     case SYMBOL_REF:
2567     case CODE_LABEL:
2568     case PC:
2569     case CC0:
2570     case ASM_INPUT:
2571     case ADDR_VEC:
2572     case ADDR_DIFF_VEC:
2573     case RETURN:
2574       return x;
2575
2576     case REG:
2577       regno = REGNO (x);
2578
2579       /* First handle the case where we encounter a bare register that
2580          is eliminable.  Replace it with a PLUS.  */
2581       if (regno < FIRST_PSEUDO_REGISTER)
2582         {
2583           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2584                ep++)
2585             if (ep->from_rtx == x && ep->can_eliminate)
2586               return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2587
2588         }
2589       else if (reg_renumber && reg_renumber[regno] < 0
2590                && reg_equivs
2591                && reg_equiv_invariant (regno))
2592         {
2593           if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2594             return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2595                                      mem_mode, insn, true, for_costs);
2596           /* There exists at least one use of REGNO that cannot be
2597              eliminated.  Prevent the defining insn from being deleted.  */
2598           reg_equiv_init (regno) = NULL_RTX;
2599           if (!for_costs)
2600             alter_reg (regno, -1, true);
2601         }
2602       return x;
2603
2604     /* You might think handling MINUS in a manner similar to PLUS is a
2605        good idea.  It is not.  It has been tried multiple times and every
2606        time the change has had to have been reverted.
2607
2608        Other parts of reload know a PLUS is special (gen_reload for example)
2609        and require special code to handle code a reloaded PLUS operand.
2610
2611        Also consider backends where the flags register is clobbered by a
2612        MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2613        lea instruction comes to mind).  If we try to reload a MINUS, we
2614        may kill the flags register that was holding a useful value.
2615
2616        So, please before trying to handle MINUS, consider reload as a
2617        whole instead of this little section as well as the backend issues.  */
2618     case PLUS:
2619       /* If this is the sum of an eliminable register and a constant, rework
2620          the sum.  */
2621       if (REG_P (XEXP (x, 0))
2622           && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2623           && CONSTANT_P (XEXP (x, 1)))
2624         {
2625           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2626                ep++)
2627             if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2628               {
2629                 /* The only time we want to replace a PLUS with a REG (this
2630                    occurs when the constant operand of the PLUS is the negative
2631                    of the offset) is when we are inside a MEM.  We won't want
2632                    to do so at other times because that would change the
2633                    structure of the insn in a way that reload can't handle.
2634                    We special-case the commonest situation in
2635                    eliminate_regs_in_insn, so just replace a PLUS with a
2636                    PLUS here, unless inside a MEM.  */
2637                 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2638                     && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2639                   return ep->to_rtx;
2640                 else
2641                   return gen_rtx_PLUS (Pmode, ep->to_rtx,
2642                                        plus_constant (Pmode, XEXP (x, 1),
2643                                                       ep->previous_offset));
2644               }
2645
2646           /* If the register is not eliminable, we are done since the other
2647              operand is a constant.  */
2648           return x;
2649         }
2650
2651       /* If this is part of an address, we want to bring any constant to the
2652          outermost PLUS.  We will do this by doing register replacement in
2653          our operands and seeing if a constant shows up in one of them.
2654
2655          Note that there is no risk of modifying the structure of the insn,
2656          since we only get called for its operands, thus we are either
2657          modifying the address inside a MEM, or something like an address
2658          operand of a load-address insn.  */
2659
2660       {
2661         rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2662                                      for_costs);
2663         rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2664                                      for_costs);
2665
2666         if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2667           {
2668             /* If one side is a PLUS and the other side is a pseudo that
2669                didn't get a hard register but has a reg_equiv_constant,
2670                we must replace the constant here since it may no longer
2671                be in the position of any operand.  */
2672             if (GET_CODE (new0) == PLUS && REG_P (new1)
2673                 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2674                 && reg_renumber[REGNO (new1)] < 0
2675                 && reg_equivs
2676                 && reg_equiv_constant (REGNO (new1)) != 0)
2677               new1 = reg_equiv_constant (REGNO (new1));
2678             else if (GET_CODE (new1) == PLUS && REG_P (new0)
2679                      && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2680                      && reg_renumber[REGNO (new0)] < 0
2681                      && reg_equiv_constant (REGNO (new0)) != 0)
2682               new0 = reg_equiv_constant (REGNO (new0));
2683
2684             new_rtx = form_sum (GET_MODE (x), new0, new1);
2685
2686             /* As above, if we are not inside a MEM we do not want to
2687                turn a PLUS into something else.  We might try to do so here
2688                for an addition of 0 if we aren't optimizing.  */
2689             if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2690               return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2691             else
2692               return new_rtx;
2693           }
2694       }
2695       return x;
2696
2697     case MULT:
2698       /* If this is the product of an eliminable register and a
2699          constant, apply the distribute law and move the constant out
2700          so that we have (plus (mult ..) ..).  This is needed in order
2701          to keep load-address insns valid.   This case is pathological.
2702          We ignore the possibility of overflow here.  */
2703       if (REG_P (XEXP (x, 0))
2704           && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2705           && CONST_INT_P (XEXP (x, 1)))
2706         for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2707              ep++)
2708           if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2709             {
2710               if (! mem_mode
2711                   /* Refs inside notes or in DEBUG_INSNs don't count for
2712                      this purpose.  */
2713                   && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2714                                       || GET_CODE (insn) == INSN_LIST
2715                                       || DEBUG_INSN_P (insn))))
2716                 ep->ref_outside_mem = 1;
2717
2718               return
2719                 plus_constant (Pmode,
2720                                gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2721                                ep->previous_offset * INTVAL (XEXP (x, 1)));
2722             }
2723
2724       /* ... fall through ...  */
2725
2726     case CALL:
2727     case COMPARE:
2728     /* See comments before PLUS about handling MINUS.  */
2729     case MINUS:
2730     case DIV:      case UDIV:
2731     case MOD:      case UMOD:
2732     case AND:      case IOR:      case XOR:
2733     case ROTATERT: case ROTATE:
2734     case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2735     case NE:       case EQ:
2736     case GE:       case GT:       case GEU:    case GTU:
2737     case LE:       case LT:       case LEU:    case LTU:
2738       {
2739         rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2740                                      for_costs);
2741         rtx new1 = XEXP (x, 1)
2742           ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2743                               for_costs) : 0;
2744
2745         if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2746           return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2747       }
2748       return x;
2749
2750     case EXPR_LIST:
2751       /* If we have something in XEXP (x, 0), the usual case, eliminate it.  */
2752       if (XEXP (x, 0))
2753         {
2754           new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2755                                       for_costs);
2756           if (new_rtx != XEXP (x, 0))
2757             {
2758               /* If this is a REG_DEAD note, it is not valid anymore.
2759                  Using the eliminated version could result in creating a
2760                  REG_DEAD note for the stack or frame pointer.  */
2761               if (REG_NOTE_KIND (x) == REG_DEAD)
2762                 return (XEXP (x, 1)
2763                         ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2764                                             for_costs)
2765                         : NULL_RTX);
2766
2767               x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2768             }
2769         }
2770
2771       /* ... fall through ...  */
2772
2773     case INSN_LIST:
2774       /* Now do eliminations in the rest of the chain.  If this was
2775          an EXPR_LIST, this might result in allocating more memory than is
2776          strictly needed, but it simplifies the code.  */
2777       if (XEXP (x, 1))
2778         {
2779           new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2780                                       for_costs);
2781           if (new_rtx != XEXP (x, 1))
2782             return
2783               gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2784         }
2785       return x;
2786
2787     case PRE_INC:
2788     case POST_INC:
2789     case PRE_DEC:
2790     case POST_DEC:
2791       /* We do not support elimination of a register that is modified.
2792          elimination_effects has already make sure that this does not
2793          happen.  */
2794       return x;
2795
2796     case PRE_MODIFY:
2797     case POST_MODIFY:
2798       /* We do not support elimination of a register that is modified.
2799          elimination_effects has already make sure that this does not
2800          happen.  The only remaining case we need to consider here is
2801          that the increment value may be an eliminable register.  */
2802       if (GET_CODE (XEXP (x, 1)) == PLUS
2803           && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2804         {
2805           rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2806                                           insn, true, for_costs);
2807
2808           if (new_rtx != XEXP (XEXP (x, 1), 1))
2809             return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2810                                    gen_rtx_PLUS (GET_MODE (x),
2811                                                  XEXP (x, 0), new_rtx));
2812         }
2813       return x;
2814
2815     case STRICT_LOW_PART:
2816     case NEG:          case NOT:
2817     case SIGN_EXTEND:  case ZERO_EXTEND:
2818     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2819     case FLOAT:        case FIX:
2820     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2821     case ABS:
2822     case SQRT:
2823     case FFS:
2824     case CLZ:
2825     case CTZ:
2826     case POPCOUNT:
2827     case PARITY:
2828     case BSWAP:
2829       new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2830                                   for_costs);
2831       if (new_rtx != XEXP (x, 0))
2832         return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2833       return x;
2834
2835     case SUBREG:
2836       /* Similar to above processing, but preserve SUBREG_BYTE.
2837          Convert (subreg (mem)) to (mem) if not paradoxical.
2838          Also, if we have a non-paradoxical (subreg (pseudo)) and the
2839          pseudo didn't get a hard reg, we must replace this with the
2840          eliminated version of the memory location because push_reload
2841          may do the replacement in certain circumstances.  */
2842       if (REG_P (SUBREG_REG (x))
2843           && !paradoxical_subreg_p (x)
2844           && reg_equivs
2845           && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2846         {
2847           new_rtx = SUBREG_REG (x);
2848         }
2849       else
2850         new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2851
2852       if (new_rtx != SUBREG_REG (x))
2853         {
2854           int x_size = GET_MODE_SIZE (GET_MODE (x));
2855           int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2856
2857           if (MEM_P (new_rtx)
2858               && ((x_size < new_size
2859 #ifdef WORD_REGISTER_OPERATIONS
2860                    /* On these machines, combine can create rtl of the form
2861                       (set (subreg:m1 (reg:m2 R) 0) ...)
2862                       where m1 < m2, and expects something interesting to
2863                       happen to the entire word.  Moreover, it will use the
2864                       (reg:m2 R) later, expecting all bits to be preserved.
2865                       So if the number of words is the same, preserve the
2866                       subreg so that push_reload can see it.  */
2867                    && ! ((x_size - 1) / UNITS_PER_WORD
2868                          == (new_size -1 ) / UNITS_PER_WORD)
2869 #endif
2870                    )
2871                   || x_size == new_size)
2872               )
2873             return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2874           else
2875             return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2876         }
2877
2878       return x;
2879
2880     case MEM:
2881       /* Our only special processing is to pass the mode of the MEM to our
2882          recursive call and copy the flags.  While we are here, handle this
2883          case more efficiently.  */
2884
2885       new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2886                                   for_costs);
2887       if (for_costs
2888           && memory_address_p (GET_MODE (x), XEXP (x, 0))
2889           && !memory_address_p (GET_MODE (x), new_rtx))
2890         for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2891
2892       return replace_equiv_address_nv (x, new_rtx);
2893
2894     case USE:
2895       /* Handle insn_list USE that a call to a pure function may generate.  */
2896       new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2897                                   for_costs);
2898       if (new_rtx != XEXP (x, 0))
2899         return gen_rtx_USE (GET_MODE (x), new_rtx);
2900       return x;
2901
2902     case CLOBBER:
2903     case ASM_OPERANDS:
2904       gcc_assert (insn && DEBUG_INSN_P (insn));
2905       break;
2906
2907     case SET:
2908       gcc_unreachable ();
2909
2910     default:
2911       break;
2912     }
2913
2914   /* Process each of our operands recursively.  If any have changed, make a
2915      copy of the rtx.  */
2916   fmt = GET_RTX_FORMAT (code);
2917   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2918     {
2919       if (*fmt == 'e')
2920         {
2921           new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2922                                       for_costs);
2923           if (new_rtx != XEXP (x, i) && ! copied)
2924             {
2925               x = shallow_copy_rtx (x);
2926               copied = 1;
2927             }
2928           XEXP (x, i) = new_rtx;
2929         }
2930       else if (*fmt == 'E')
2931         {
2932           int copied_vec = 0;
2933           for (j = 0; j < XVECLEN (x, i); j++)
2934             {
2935               new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2936                                           for_costs);
2937               if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2938                 {
2939                   rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2940                                              XVEC (x, i)->elem);
2941                   if (! copied)
2942                     {
2943                       x = shallow_copy_rtx (x);
2944                       copied = 1;
2945                     }
2946                   XVEC (x, i) = new_v;
2947                   copied_vec = 1;
2948                 }
2949               XVECEXP (x, i, j) = new_rtx;
2950             }
2951         }
2952     }
2953
2954   return x;
2955 }
2956
2957 rtx
2958 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2959 {
2960   return eliminate_regs_1 (x, mem_mode, insn, false, false);
2961 }
2962
2963 /* Scan rtx X for modifications of elimination target registers.  Update
2964    the table of eliminables to reflect the changed state.  MEM_MODE is
2965    the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM.  */
2966
2967 static void
2968 elimination_effects (rtx x, enum machine_mode mem_mode)
2969 {
2970   enum rtx_code code = GET_CODE (x);
2971   struct elim_table *ep;
2972   int regno;
2973   int i, j;
2974   const char *fmt;
2975
2976   switch (code)
2977     {
2978     CASE_CONST_ANY:
2979     case CONST:
2980     case SYMBOL_REF:
2981     case CODE_LABEL:
2982     case PC:
2983     case CC0:
2984     case ASM_INPUT:
2985     case ADDR_VEC:
2986     case ADDR_DIFF_VEC:
2987     case RETURN:
2988       return;
2989
2990     case REG:
2991       regno = REGNO (x);
2992
2993       /* First handle the case where we encounter a bare register that
2994          is eliminable.  Replace it with a PLUS.  */
2995       if (regno < FIRST_PSEUDO_REGISTER)
2996         {
2997           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2998                ep++)
2999             if (ep->from_rtx == x && ep->can_eliminate)
3000               {
3001                 if (! mem_mode)
3002                   ep->ref_outside_mem = 1;
3003                 return;
3004               }
3005
3006         }
3007       else if (reg_renumber[regno] < 0
3008                && reg_equivs
3009                && reg_equiv_constant (regno)
3010                && ! function_invariant_p (reg_equiv_constant (regno)))
3011         elimination_effects (reg_equiv_constant (regno), mem_mode);
3012       return;
3013
3014     case PRE_INC:
3015     case POST_INC:
3016     case PRE_DEC:
3017     case POST_DEC:
3018     case POST_MODIFY:
3019     case PRE_MODIFY:
3020       /* If we modify the source of an elimination rule, disable it.  */
3021       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3022         if (ep->from_rtx == XEXP (x, 0))
3023           ep->can_eliminate = 0;
3024
3025       /* If we modify the target of an elimination rule by adding a constant,
3026          update its offset.  If we modify the target in any other way, we'll
3027          have to disable the rule as well.  */
3028       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3029         if (ep->to_rtx == XEXP (x, 0))
3030           {
3031             int size = GET_MODE_SIZE (mem_mode);
3032
3033             /* If more bytes than MEM_MODE are pushed, account for them.  */
3034 #ifdef PUSH_ROUNDING
3035             if (ep->to_rtx == stack_pointer_rtx)
3036               size = PUSH_ROUNDING (size);
3037 #endif
3038             if (code == PRE_DEC || code == POST_DEC)
3039               ep->offset += size;
3040             else if (code == PRE_INC || code == POST_INC)
3041               ep->offset -= size;
3042             else if (code == PRE_MODIFY || code == POST_MODIFY)
3043               {
3044                 if (GET_CODE (XEXP (x, 1)) == PLUS
3045                     && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3046                     && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3047                   ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3048                 else
3049                   ep->can_eliminate = 0;
3050               }
3051           }
3052
3053       /* These two aren't unary operators.  */
3054       if (code == POST_MODIFY || code == PRE_MODIFY)
3055         break;
3056
3057       /* Fall through to generic unary operation case.  */
3058     case STRICT_LOW_PART:
3059     case NEG:          case NOT:
3060     case SIGN_EXTEND:  case ZERO_EXTEND:
3061     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3062     case FLOAT:        case FIX:
3063     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3064     case ABS:
3065     case SQRT:
3066     case FFS:
3067     case CLZ:
3068     case CTZ:
3069     case POPCOUNT:
3070     case PARITY:
3071     case BSWAP:
3072       elimination_effects (XEXP (x, 0), mem_mode);
3073       return;
3074
3075     case SUBREG:
3076       if (REG_P (SUBREG_REG (x))
3077           && (GET_MODE_SIZE (GET_MODE (x))
3078               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3079           && reg_equivs
3080           && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3081         return;
3082
3083       elimination_effects (SUBREG_REG (x), mem_mode);
3084       return;
3085
3086     case USE:
3087       /* If using a register that is the source of an eliminate we still
3088          think can be performed, note it cannot be performed since we don't
3089          know how this register is used.  */
3090       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3091         if (ep->from_rtx == XEXP (x, 0))
3092           ep->can_eliminate = 0;
3093
3094       elimination_effects (XEXP (x, 0), mem_mode);
3095       return;
3096
3097     case CLOBBER:
3098       /* If clobbering a register that is the replacement register for an
3099          elimination we still think can be performed, note that it cannot
3100          be performed.  Otherwise, we need not be concerned about it.  */
3101       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3102         if (ep->to_rtx == XEXP (x, 0))
3103           ep->can_eliminate = 0;
3104
3105       elimination_effects (XEXP (x, 0), mem_mode);
3106       return;
3107
3108     case SET:
3109       /* Check for setting a register that we know about.  */
3110       if (REG_P (SET_DEST (x)))
3111         {
3112           /* See if this is setting the replacement register for an
3113              elimination.
3114
3115              If DEST is the hard frame pointer, we do nothing because we
3116              assume that all assignments to the frame pointer are for
3117              non-local gotos and are being done at a time when they are valid
3118              and do not disturb anything else.  Some machines want to
3119              eliminate a fake argument pointer (or even a fake frame pointer)
3120              with either the real frame or the stack pointer.  Assignments to
3121              the hard frame pointer must not prevent this elimination.  */
3122
3123           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3124                ep++)
3125             if (ep->to_rtx == SET_DEST (x)
3126                 && SET_DEST (x) != hard_frame_pointer_rtx)
3127               {
3128                 /* If it is being incremented, adjust the offset.  Otherwise,
3129                    this elimination can't be done.  */
3130                 rtx src = SET_SRC (x);
3131
3132                 if (GET_CODE (src) == PLUS
3133                     && XEXP (src, 0) == SET_DEST (x)
3134                     && CONST_INT_P (XEXP (src, 1)))
3135                   ep->offset -= INTVAL (XEXP (src, 1));
3136                 else
3137                   ep->can_eliminate = 0;
3138               }
3139         }
3140
3141       elimination_effects (SET_DEST (x), VOIDmode);
3142       elimination_effects (SET_SRC (x), VOIDmode);
3143       return;
3144
3145     case MEM:
3146       /* Our only special processing is to pass the mode of the MEM to our
3147          recursive call.  */
3148       elimination_effects (XEXP (x, 0), GET_MODE (x));
3149       return;
3150
3151     default:
3152       break;
3153     }
3154
3155   fmt = GET_RTX_FORMAT (code);
3156   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3157     {
3158       if (*fmt == 'e')
3159         elimination_effects (XEXP (x, i), mem_mode);
3160       else if (*fmt == 'E')
3161         for (j = 0; j < XVECLEN (x, i); j++)
3162           elimination_effects (XVECEXP (x, i, j), mem_mode);
3163     }
3164 }
3165
3166 /* Descend through rtx X and verify that no references to eliminable registers
3167    remain.  If any do remain, mark the involved register as not
3168    eliminable.  */
3169
3170 static void
3171 check_eliminable_occurrences (rtx x)
3172 {
3173   const char *fmt;
3174   int i;
3175   enum rtx_code code;
3176
3177   if (x == 0)
3178     return;
3179
3180   code = GET_CODE (x);
3181
3182   if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3183     {
3184       struct elim_table *ep;
3185
3186       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3187         if (ep->from_rtx == x)
3188           ep->can_eliminate = 0;
3189       return;
3190     }
3191
3192   fmt = GET_RTX_FORMAT (code);
3193   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3194     {
3195       if (*fmt == 'e')
3196         check_eliminable_occurrences (XEXP (x, i));
3197       else if (*fmt == 'E')
3198         {
3199           int j;
3200           for (j = 0; j < XVECLEN (x, i); j++)
3201             check_eliminable_occurrences (XVECEXP (x, i, j));
3202         }
3203     }
3204 }
3205 \f
3206 /* Scan INSN and eliminate all eliminable registers in it.
3207
3208    If REPLACE is nonzero, do the replacement destructively.  Also
3209    delete the insn as dead it if it is setting an eliminable register.
3210
3211    If REPLACE is zero, do all our allocations in reload_obstack.
3212
3213    If no eliminations were done and this insn doesn't require any elimination
3214    processing (these are not identical conditions: it might be updating sp,
3215    but not referencing fp; this needs to be seen during reload_as_needed so
3216    that the offset between fp and sp can be taken into consideration), zero
3217    is returned.  Otherwise, 1 is returned.  */
3218
3219 static int
3220 eliminate_regs_in_insn (rtx insn, int replace)
3221 {
3222   int icode = recog_memoized (insn);
3223   rtx old_body = PATTERN (insn);
3224   int insn_is_asm = asm_noperands (old_body) >= 0;
3225   rtx old_set = single_set (insn);
3226   rtx new_body;
3227   int val = 0;
3228   int i;
3229   rtx substed_operand[MAX_RECOG_OPERANDS];
3230   rtx orig_operand[MAX_RECOG_OPERANDS];
3231   struct elim_table *ep;
3232   rtx plus_src, plus_cst_src;
3233
3234   if (! insn_is_asm && icode < 0)
3235     {
3236       gcc_assert (GET_CODE (PATTERN (insn)) == USE
3237                   || GET_CODE (PATTERN (insn)) == CLOBBER
3238                   || GET_CODE (PATTERN (insn)) == ADDR_VEC
3239                   || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3240                   || GET_CODE (PATTERN (insn)) == ASM_INPUT
3241                   || DEBUG_INSN_P (insn));
3242       if (DEBUG_INSN_P (insn))
3243         INSN_VAR_LOCATION_LOC (insn)
3244           = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3245       return 0;
3246     }
3247
3248   if (old_set != 0 && REG_P (SET_DEST (old_set))
3249       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3250     {
3251       /* Check for setting an eliminable register.  */
3252       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3253         if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3254           {
3255 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3256             /* If this is setting the frame pointer register to the
3257                hardware frame pointer register and this is an elimination
3258                that will be done (tested above), this insn is really
3259                adjusting the frame pointer downward to compensate for
3260                the adjustment done before a nonlocal goto.  */
3261             if (ep->from == FRAME_POINTER_REGNUM
3262                 && ep->to == HARD_FRAME_POINTER_REGNUM)
3263               {
3264                 rtx base = SET_SRC (old_set);
3265                 rtx base_insn = insn;
3266                 HOST_WIDE_INT offset = 0;
3267
3268                 while (base != ep->to_rtx)
3269                   {
3270                     rtx prev_insn, prev_set;
3271
3272                     if (GET_CODE (base) == PLUS
3273                         && CONST_INT_P (XEXP (base, 1)))
3274                       {
3275                         offset += INTVAL (XEXP (base, 1));
3276                         base = XEXP (base, 0);
3277                       }
3278                     else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3279                              && (prev_set = single_set (prev_insn)) != 0
3280                              && rtx_equal_p (SET_DEST (prev_set), base))
3281                       {
3282                         base = SET_SRC (prev_set);
3283                         base_insn = prev_insn;
3284                       }
3285                     else
3286                       break;
3287                   }
3288
3289                 if (base == ep->to_rtx)
3290                   {
3291                     rtx src = plus_constant (Pmode, ep->to_rtx,
3292                                              offset - ep->offset);
3293
3294                     new_body = old_body;
3295                     if (! replace)
3296                       {
3297                         new_body = copy_insn (old_body);
3298                         if (REG_NOTES (insn))
3299                           REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3300                       }
3301                     PATTERN (insn) = new_body;
3302                     old_set = single_set (insn);
3303
3304                     /* First see if this insn remains valid when we
3305                        make the change.  If not, keep the INSN_CODE
3306                        the same and let reload fit it up.  */
3307                     validate_change (insn, &SET_SRC (old_set), src, 1);
3308                     validate_change (insn, &SET_DEST (old_set),
3309                                      ep->to_rtx, 1);
3310                     if (! apply_change_group ())
3311                       {
3312                         SET_SRC (old_set) = src;
3313                         SET_DEST (old_set) = ep->to_rtx;
3314                       }
3315
3316                     val = 1;
3317                     goto done;
3318                   }
3319               }
3320 #endif
3321
3322             /* In this case this insn isn't serving a useful purpose.  We
3323                will delete it in reload_as_needed once we know that this
3324                elimination is, in fact, being done.
3325
3326                If REPLACE isn't set, we can't delete this insn, but needn't
3327                process it since it won't be used unless something changes.  */
3328             if (replace)
3329               {
3330                 delete_dead_insn (insn);
3331                 return 1;
3332               }
3333             val = 1;
3334             goto done;
3335           }
3336     }
3337
3338   /* We allow one special case which happens to work on all machines we
3339      currently support: a single set with the source or a REG_EQUAL
3340      note being a PLUS of an eliminable register and a constant.  */
3341   plus_src = plus_cst_src = 0;
3342   if (old_set && REG_P (SET_DEST (old_set)))
3343     {
3344       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3345         plus_src = SET_SRC (old_set);
3346       /* First see if the source is of the form (plus (...) CST).  */
3347       if (plus_src
3348           && CONST_INT_P (XEXP (plus_src, 1)))
3349         plus_cst_src = plus_src;
3350       else if (REG_P (SET_SRC (old_set))
3351                || plus_src)
3352         {
3353           /* Otherwise, see if we have a REG_EQUAL note of the form
3354              (plus (...) CST).  */
3355           rtx links;
3356           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3357             {
3358               if ((REG_NOTE_KIND (links) == REG_EQUAL
3359                    || REG_NOTE_KIND (links) == REG_EQUIV)
3360                   && GET_CODE (XEXP (links, 0)) == PLUS
3361                   && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3362                 {
3363                   plus_cst_src = XEXP (links, 0);
3364                   break;
3365                 }
3366             }
3367         }
3368
3369       /* Check that the first operand of the PLUS is a hard reg or
3370          the lowpart subreg of one.  */
3371       if (plus_cst_src)
3372         {
3373           rtx reg = XEXP (plus_cst_src, 0);
3374           if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3375             reg = SUBREG_REG (reg);
3376
3377           if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3378             plus_cst_src = 0;
3379         }
3380     }
3381   if (plus_cst_src)
3382     {
3383       rtx reg = XEXP (plus_cst_src, 0);
3384       HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3385
3386       if (GET_CODE (reg) == SUBREG)
3387         reg = SUBREG_REG (reg);
3388
3389       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3390         if (ep->from_rtx == reg && ep->can_eliminate)
3391           {
3392             rtx to_rtx = ep->to_rtx;
3393             offset += ep->offset;
3394             offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3395
3396             if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3397               to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3398                                     to_rtx);
3399             /* If we have a nonzero offset, and the source is already
3400                a simple REG, the following transformation would
3401                increase the cost of the insn by replacing a simple REG
3402                with (plus (reg sp) CST).  So try only when we already
3403                had a PLUS before.  */
3404             if (offset == 0 || plus_src)
3405               {
3406                 rtx new_src = plus_constant (GET_MODE (to_rtx),
3407                                              to_rtx, offset);
3408
3409                 new_body = old_body;
3410                 if (! replace)
3411                   {
3412                     new_body = copy_insn (old_body);
3413                     if (REG_NOTES (insn))
3414                       REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3415                   }
3416                 PATTERN (insn) = new_body;
3417                 old_set = single_set (insn);
3418
3419                 /* First see if this insn remains valid when we make the
3420                    change.  If not, try to replace the whole pattern with
3421                    a simple set (this may help if the original insn was a
3422                    PARALLEL that was only recognized as single_set due to
3423                    REG_UNUSED notes).  If this isn't valid either, keep
3424                    the INSN_CODE the same and let reload fix it up.  */
3425                 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3426                   {
3427                     rtx new_pat = gen_rtx_SET (VOIDmode,
3428                                                SET_DEST (old_set), new_src);
3429
3430                     if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3431                       SET_SRC (old_set) = new_src;
3432                   }
3433               }
3434             else
3435               break;
3436
3437             val = 1;
3438             /* This can't have an effect on elimination offsets, so skip right
3439                to the end.  */
3440             goto done;
3441           }
3442     }
3443
3444   /* Determine the effects of this insn on elimination offsets.  */
3445   elimination_effects (old_body, VOIDmode);
3446
3447   /* Eliminate all eliminable registers occurring in operands that
3448      can be handled by reload.  */
3449   extract_insn (insn);
3450   for (i = 0; i < recog_data.n_operands; i++)
3451     {
3452       orig_operand[i] = recog_data.operand[i];
3453       substed_operand[i] = recog_data.operand[i];
3454
3455       /* For an asm statement, every operand is eliminable.  */
3456       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3457         {
3458           bool is_set_src, in_plus;
3459
3460           /* Check for setting a register that we know about.  */
3461           if (recog_data.operand_type[i] != OP_IN
3462               && REG_P (orig_operand[i]))
3463             {
3464               /* If we are assigning to a register that can be eliminated, it
3465                  must be as part of a PARALLEL, since the code above handles
3466                  single SETs.  We must indicate that we can no longer
3467                  eliminate this reg.  */
3468               for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3469                    ep++)
3470                 if (ep->from_rtx == orig_operand[i])
3471                   ep->can_eliminate = 0;
3472             }
3473
3474           /* Companion to the above plus substitution, we can allow
3475              invariants as the source of a plain move.  */
3476           is_set_src = false;
3477           if (old_set
3478               && recog_data.operand_loc[i] == &SET_SRC (old_set))
3479             is_set_src = true;
3480           in_plus = false;
3481           if (plus_src
3482               && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3483                   || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3484             in_plus = true;
3485
3486           substed_operand[i]
3487             = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3488                                 replace ? insn : NULL_RTX,
3489                                 is_set_src || in_plus, false);
3490           if (substed_operand[i] != orig_operand[i])
3491             val = 1;
3492           /* Terminate the search in check_eliminable_occurrences at
3493              this point.  */
3494           *recog_data.operand_loc[i] = 0;
3495
3496           /* If an output operand changed from a REG to a MEM and INSN is an
3497              insn, write a CLOBBER insn.  */
3498           if (recog_data.operand_type[i] != OP_IN
3499               && REG_P (orig_operand[i])
3500               && MEM_P (substed_operand[i])
3501               && replace)
3502             emit_insn_after (gen_clobber (orig_operand[i]), insn);
3503         }
3504     }
3505
3506   for (i = 0; i < recog_data.n_dups; i++)
3507     *recog_data.dup_loc[i]
3508       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3509
3510   /* If any eliminable remain, they aren't eliminable anymore.  */
3511   check_eliminable_occurrences (old_body);
3512
3513   /* Substitute the operands; the new values are in the substed_operand
3514      array.  */
3515   for (i = 0; i < recog_data.n_operands; i++)
3516     *recog_data.operand_loc[i] = substed_operand[i];
3517   for (i = 0; i < recog_data.n_dups; i++)
3518     *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3519
3520   /* If we are replacing a body that was a (set X (plus Y Z)), try to
3521      re-recognize the insn.  We do this in case we had a simple addition
3522      but now can do this as a load-address.  This saves an insn in this
3523      common case.
3524      If re-recognition fails, the old insn code number will still be used,
3525      and some register operands may have changed into PLUS expressions.
3526      These will be handled by find_reloads by loading them into a register
3527      again.  */
3528
3529   if (val)
3530     {
3531       /* If we aren't replacing things permanently and we changed something,
3532          make another copy to ensure that all the RTL is new.  Otherwise
3533          things can go wrong if find_reload swaps commutative operands
3534          and one is inside RTL that has been copied while the other is not.  */
3535       new_body = old_body;
3536       if (! replace)
3537         {
3538           new_body = copy_insn (old_body);
3539           if (REG_NOTES (insn))
3540             REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3541         }
3542       PATTERN (insn) = new_body;
3543
3544       /* If we had a move insn but now we don't, rerecognize it.  This will
3545          cause spurious re-recognition if the old move had a PARALLEL since
3546          the new one still will, but we can't call single_set without
3547          having put NEW_BODY into the insn and the re-recognition won't
3548          hurt in this rare case.  */
3549       /* ??? Why this huge if statement - why don't we just rerecognize the
3550          thing always?  */
3551       if (! insn_is_asm
3552           && old_set != 0
3553           && ((REG_P (SET_SRC (old_set))
3554                && (GET_CODE (new_body) != SET
3555                    || !REG_P (SET_SRC (new_body))))
3556               /* If this was a load from or store to memory, compare
3557                  the MEM in recog_data.operand to the one in the insn.
3558                  If they are not equal, then rerecognize the insn.  */
3559               || (old_set != 0
3560                   && ((MEM_P (SET_SRC (old_set))
3561                        && SET_SRC (old_set) != recog_data.operand[1])
3562                       || (MEM_P (SET_DEST (old_set))
3563                           && SET_DEST (old_set) != recog_data.operand[0])))
3564               /* If this was an add insn before, rerecognize.  */
3565               || GET_CODE (SET_SRC (old_set)) == PLUS))
3566         {
3567           int new_icode = recog (PATTERN (insn), insn, 0);
3568           if (new_icode >= 0)
3569             INSN_CODE (insn) = new_icode;
3570         }
3571     }
3572
3573   /* Restore the old body.  If there were any changes to it, we made a copy
3574      of it while the changes were still in place, so we'll correctly return
3575      a modified insn below.  */
3576   if (! replace)
3577     {
3578       /* Restore the old body.  */
3579       for (i = 0; i < recog_data.n_operands; i++)
3580         /* Restoring a top-level match_parallel would clobber the new_body
3581            we installed in the insn.  */
3582         if (recog_data.operand_loc[i] != &PATTERN (insn))
3583           *recog_data.operand_loc[i] = orig_operand[i];
3584       for (i = 0; i < recog_data.n_dups; i++)
3585         *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3586     }
3587
3588   /* Update all elimination pairs to reflect the status after the current
3589      insn.  The changes we make were determined by the earlier call to
3590      elimination_effects.
3591
3592      We also detect cases where register elimination cannot be done,
3593      namely, if a register would be both changed and referenced outside a MEM
3594      in the resulting insn since such an insn is often undefined and, even if
3595      not, we cannot know what meaning will be given to it.  Note that it is
3596      valid to have a register used in an address in an insn that changes it
3597      (presumably with a pre- or post-increment or decrement).
3598
3599      If anything changes, return nonzero.  */
3600
3601   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3602     {
3603       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3604         ep->can_eliminate = 0;
3605
3606       ep->ref_outside_mem = 0;
3607
3608       if (ep->previous_offset != ep->offset)
3609         val = 1;
3610     }
3611
3612  done:
3613   /* If we changed something, perform elimination in REG_NOTES.  This is
3614      needed even when REPLACE is zero because a REG_DEAD note might refer
3615      to a register that we eliminate and could cause a different number
3616      of spill registers to be needed in the final reload pass than in
3617      the pre-passes.  */
3618   if (val && REG_NOTES (insn) != 0)
3619     REG_NOTES (insn)
3620       = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3621                           false);
3622
3623   return val;
3624 }
3625
3626 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3627    register allocator.  INSN is the instruction we need to examine, we perform
3628    eliminations in its operands and record cases where eliminating a reg with
3629    an invariant equivalence would add extra cost.  */
3630
3631 static void
3632 elimination_costs_in_insn (rtx insn)
3633 {
3634   int icode = recog_memoized (insn);
3635   rtx old_body = PATTERN (insn);
3636   int insn_is_asm = asm_noperands (old_body) >= 0;
3637   rtx old_set = single_set (insn);
3638   int i;
3639   rtx orig_operand[MAX_RECOG_OPERANDS];
3640   rtx orig_dup[MAX_RECOG_OPERANDS];
3641   struct elim_table *ep;
3642   rtx plus_src, plus_cst_src;
3643   bool sets_reg_p;
3644
3645   if (! insn_is_asm && icode < 0)
3646     {
3647       gcc_assert (GET_CODE (PATTERN (insn)) == USE
3648                   || GET_CODE (PATTERN (insn)) == CLOBBER
3649                   || GET_CODE (PATTERN (insn)) == ADDR_VEC
3650                   || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3651                   || GET_CODE (PATTERN (insn)) == ASM_INPUT
3652                   || DEBUG_INSN_P (insn));
3653       return;
3654     }
3655
3656   if (old_set != 0 && REG_P (SET_DEST (old_set))
3657       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3658     {
3659       /* Check for setting an eliminable register.  */
3660       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3661         if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3662           return;
3663     }
3664
3665   /* We allow one special case which happens to work on all machines we
3666      currently support: a single set with the source or a REG_EQUAL
3667      note being a PLUS of an eliminable register and a constant.  */
3668   plus_src = plus_cst_src = 0;
3669   sets_reg_p = false;
3670   if (old_set && REG_P (SET_DEST (old_set)))
3671     {
3672       sets_reg_p = true;
3673       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3674         plus_src = SET_SRC (old_set);
3675       /* First see if the source is of the form (plus (...) CST).  */
3676       if (plus_src
3677           && CONST_INT_P (XEXP (plus_src, 1)))
3678         plus_cst_src = plus_src;
3679       else if (REG_P (SET_SRC (old_set))
3680                || plus_src)
3681         {
3682           /* Otherwise, see if we have a REG_EQUAL note of the form
3683              (plus (...) CST).  */
3684           rtx links;
3685           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3686             {
3687               if ((REG_NOTE_KIND (links) == REG_EQUAL
3688                    || REG_NOTE_KIND (links) == REG_EQUIV)
3689                   && GET_CODE (XEXP (links, 0)) == PLUS
3690                   && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3691                 {
3692                   plus_cst_src = XEXP (links, 0);
3693                   break;
3694                 }
3695             }
3696         }
3697     }
3698
3699   /* Determine the effects of this insn on elimination offsets.  */
3700   elimination_effects (old_body, VOIDmode);
3701
3702   /* Eliminate all eliminable registers occurring in operands that
3703      can be handled by reload.  */
3704   extract_insn (insn);
3705   for (i = 0; i < recog_data.n_dups; i++)
3706     orig_dup[i] = *recog_data.dup_loc[i];
3707
3708   for (i = 0; i < recog_data.n_operands; i++)
3709     {
3710       orig_operand[i] = recog_data.operand[i];
3711
3712       /* For an asm statement, every operand is eliminable.  */
3713       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3714         {
3715           bool is_set_src, in_plus;
3716
3717           /* Check for setting a register that we know about.  */
3718           if (recog_data.operand_type[i] != OP_IN
3719               && REG_P (orig_operand[i]))
3720             {
3721               /* If we are assigning to a register that can be eliminated, it
3722                  must be as part of a PARALLEL, since the code above handles
3723                  single SETs.  We must indicate that we can no longer
3724                  eliminate this reg.  */
3725               for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3726                    ep++)
3727                 if (ep->from_rtx == orig_operand[i])
3728                   ep->can_eliminate = 0;
3729             }
3730
3731           /* Companion to the above plus substitution, we can allow
3732              invariants as the source of a plain move.  */
3733           is_set_src = false;
3734           if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3735             is_set_src = true;
3736           if (is_set_src && !sets_reg_p)
3737             note_reg_elim_costly (&SET_SRC (old_set), insn);
3738           in_plus = false;
3739           if (plus_src && sets_reg_p
3740               && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3741                   || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3742             in_plus = true;
3743
3744           eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3745                             NULL_RTX,
3746                             is_set_src || in_plus, true);
3747           /* Terminate the search in check_eliminable_occurrences at
3748              this point.  */
3749           *recog_data.operand_loc[i] = 0;
3750         }
3751     }
3752
3753   for (i = 0; i < recog_data.n_dups; i++)
3754     *recog_data.dup_loc[i]
3755       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3756
3757   /* If any eliminable remain, they aren't eliminable anymore.  */
3758   check_eliminable_occurrences (old_body);
3759
3760   /* Restore the old body.  */
3761   for (i = 0; i < recog_data.n_operands; i++)
3762     *recog_data.operand_loc[i] = orig_operand[i];
3763   for (i = 0; i < recog_data.n_dups; i++)
3764     *recog_data.dup_loc[i] = orig_dup[i];
3765
3766   /* Update all elimination pairs to reflect the status after the current
3767      insn.  The changes we make were determined by the earlier call to
3768      elimination_effects.  */
3769
3770   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3771     {
3772       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3773         ep->can_eliminate = 0;
3774
3775       ep->ref_outside_mem = 0;
3776     }
3777
3778   return;
3779 }
3780
3781 /* Loop through all elimination pairs.
3782    Recalculate the number not at initial offset.
3783
3784    Compute the maximum offset (minimum offset if the stack does not
3785    grow downward) for each elimination pair.  */
3786
3787 static void
3788 update_eliminable_offsets (void)
3789 {
3790   struct elim_table *ep;
3791
3792   num_not_at_initial_offset = 0;
3793   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3794     {
3795       ep->previous_offset = ep->offset;
3796       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3797         num_not_at_initial_offset++;
3798     }
3799 }
3800
3801 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3802    replacement we currently believe is valid, mark it as not eliminable if X
3803    modifies DEST in any way other than by adding a constant integer to it.
3804
3805    If DEST is the frame pointer, we do nothing because we assume that
3806    all assignments to the hard frame pointer are nonlocal gotos and are being
3807    done at a time when they are valid and do not disturb anything else.
3808    Some machines want to eliminate a fake argument pointer with either the
3809    frame or stack pointer.  Assignments to the hard frame pointer must not
3810    prevent this elimination.
3811
3812    Called via note_stores from reload before starting its passes to scan
3813    the insns of the function.  */
3814
3815 static void
3816 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3817 {
3818   unsigned int i;
3819
3820   /* A SUBREG of a hard register here is just changing its mode.  We should
3821      not see a SUBREG of an eliminable hard register, but check just in
3822      case.  */
3823   if (GET_CODE (dest) == SUBREG)
3824     dest = SUBREG_REG (dest);
3825
3826   if (dest == hard_frame_pointer_rtx)
3827     return;
3828
3829   for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3830     if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3831         && (GET_CODE (x) != SET
3832             || GET_CODE (SET_SRC (x)) != PLUS
3833             || XEXP (SET_SRC (x), 0) != dest
3834             || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3835       {
3836         reg_eliminate[i].can_eliminate_previous
3837           = reg_eliminate[i].can_eliminate = 0;
3838         num_eliminable--;
3839       }
3840 }
3841
3842 /* Verify that the initial elimination offsets did not change since the
3843    last call to set_initial_elim_offsets.  This is used to catch cases
3844    where something illegal happened during reload_as_needed that could
3845    cause incorrect code to be generated if we did not check for it.  */
3846
3847 static bool
3848 verify_initial_elim_offsets (void)
3849 {
3850   HOST_WIDE_INT t;
3851
3852   if (!num_eliminable)
3853     return true;
3854
3855 #ifdef ELIMINABLE_REGS
3856   {
3857    struct elim_table *ep;
3858
3859    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3860      {
3861        INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3862        if (t != ep->initial_offset)
3863          return false;
3864      }
3865   }
3866 #else
3867   INITIAL_FRAME_POINTER_OFFSET (t);
3868   if (t != reg_eliminate[0].initial_offset)
3869     return false;
3870 #endif
3871
3872   return true;
3873 }
3874
3875 /* Reset all offsets on eliminable registers to their initial values.  */
3876
3877 static void
3878 set_initial_elim_offsets (void)
3879 {
3880   struct elim_table *ep = reg_eliminate;
3881
3882 #ifdef ELIMINABLE_REGS
3883   for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3884     {
3885       INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3886       ep->previous_offset = ep->offset = ep->initial_offset;
3887     }
3888 #else
3889   INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3890   ep->previous_offset = ep->offset = ep->initial_offset;
3891 #endif
3892
3893   num_not_at_initial_offset = 0;
3894 }
3895
3896 /* Subroutine of set_initial_label_offsets called via for_each_eh_label.  */
3897
3898 static void
3899 set_initial_eh_label_offset (rtx label)
3900 {
3901   set_label_offsets (label, NULL_RTX, 1);
3902 }
3903
3904 /* Initialize the known label offsets.
3905    Set a known offset for each forced label to be at the initial offset
3906    of each elimination.  We do this because we assume that all
3907    computed jumps occur from a location where each elimination is
3908    at its initial offset.
3909    For all other labels, show that we don't know the offsets.  */
3910
3911 static void
3912 set_initial_label_offsets (void)
3913 {
3914   rtx x;
3915   memset (offsets_known_at, 0, num_labels);
3916
3917   for (x = forced_labels; x; x = XEXP (x, 1))
3918     if (XEXP (x, 0))
3919       set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3920
3921   for (x = nonlocal_goto_handler_labels; x; x = XEXP (x, 1))
3922     if (XEXP (x, 0))
3923       set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3924
3925   for_each_eh_label (set_initial_eh_label_offset);
3926 }
3927
3928 /* Set all elimination offsets to the known values for the code label given
3929    by INSN.  */
3930
3931 static void
3932 set_offsets_for_label (rtx insn)
3933 {
3934   unsigned int i;
3935   int label_nr = CODE_LABEL_NUMBER (insn);
3936   struct elim_table *ep;
3937
3938   num_not_at_initial_offset = 0;
3939   for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3940     {
3941       ep->offset = ep->previous_offset
3942                  = offsets_at[label_nr - first_label_num][i];
3943       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3944         num_not_at_initial_offset++;
3945     }
3946 }
3947
3948 /* See if anything that happened changes which eliminations are valid.
3949    For example, on the SPARC, whether or not the frame pointer can
3950    be eliminated can depend on what registers have been used.  We need
3951    not check some conditions again (such as flag_omit_frame_pointer)
3952    since they can't have changed.  */
3953
3954 static void
3955 update_eliminables (HARD_REG_SET *pset)
3956 {
3957   int previous_frame_pointer_needed = frame_pointer_needed;
3958   struct elim_table *ep;
3959
3960   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3961     if ((ep->from == HARD_FRAME_POINTER_REGNUM
3962          && targetm.frame_pointer_required ())
3963 #ifdef ELIMINABLE_REGS
3964         || ! targetm.can_eliminate (ep->from, ep->to)
3965 #endif
3966         )
3967       ep->can_eliminate = 0;
3968
3969   /* Look for the case where we have discovered that we can't replace
3970      register A with register B and that means that we will now be
3971      trying to replace register A with register C.  This means we can
3972      no longer replace register C with register B and we need to disable
3973      such an elimination, if it exists.  This occurs often with A == ap,
3974      B == sp, and C == fp.  */
3975
3976   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3977     {
3978       struct elim_table *op;
3979       int new_to = -1;
3980
3981       if (! ep->can_eliminate && ep->can_eliminate_previous)
3982         {
3983           /* Find the current elimination for ep->from, if there is a
3984              new one.  */
3985           for (op = reg_eliminate;
3986                op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
3987             if (op->from == ep->from && op->can_eliminate)
3988               {
3989                 new_to = op->to;
3990                 break;
3991               }
3992
3993           /* See if there is an elimination of NEW_TO -> EP->TO.  If so,
3994              disable it.  */
3995           for (op = reg_eliminate;
3996                op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
3997             if (op->from == new_to && op->to == ep->to)
3998               op->can_eliminate = 0;
3999         }
4000     }
4001
4002   /* See if any registers that we thought we could eliminate the previous
4003      time are no longer eliminable.  If so, something has changed and we
4004      must spill the register.  Also, recompute the number of eliminable
4005      registers and see if the frame pointer is needed; it is if there is
4006      no elimination of the frame pointer that we can perform.  */
4007
4008   frame_pointer_needed = 1;
4009   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4010     {
4011       if (ep->can_eliminate
4012           && ep->from == FRAME_POINTER_REGNUM
4013           && ep->to != HARD_FRAME_POINTER_REGNUM
4014           && (! SUPPORTS_STACK_ALIGNMENT
4015               || ! crtl->stack_realign_needed))
4016         frame_pointer_needed = 0;
4017
4018       if (! ep->can_eliminate && ep->can_eliminate_previous)
4019         {
4020           ep->can_eliminate_previous = 0;
4021           SET_HARD_REG_BIT (*pset, ep->from);
4022           num_eliminable--;
4023         }
4024     }
4025
4026   /* If we didn't need a frame pointer last time, but we do now, spill
4027      the hard frame pointer.  */
4028   if (frame_pointer_needed && ! previous_frame_pointer_needed)
4029     SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4030 }
4031
4032 /* Return true if X is used as the target register of an elimination.  */
4033
4034 bool
4035 elimination_target_reg_p (rtx x)
4036 {
4037   struct elim_table *ep;
4038
4039   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4040     if (ep->to_rtx == x && ep->can_eliminate)
4041       return true;
4042
4043   return false;
4044 }
4045
4046 /* Initialize the table of registers to eliminate.
4047    Pre-condition: global flag frame_pointer_needed has been set before
4048    calling this function.  */
4049
4050 static void
4051 init_elim_table (void)
4052 {
4053   struct elim_table *ep;
4054 #ifdef ELIMINABLE_REGS
4055   const struct elim_table_1 *ep1;
4056 #endif
4057
4058   if (!reg_eliminate)
4059     reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4060
4061   num_eliminable = 0;
4062
4063 #ifdef ELIMINABLE_REGS
4064   for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4065        ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4066     {
4067       ep->from = ep1->from;
4068       ep->to = ep1->to;
4069       ep->can_eliminate = ep->can_eliminate_previous
4070         = (targetm.can_eliminate (ep->from, ep->to)
4071            && ! (ep->to == STACK_POINTER_REGNUM
4072                  && frame_pointer_needed
4073                  && (! SUPPORTS_STACK_ALIGNMENT
4074                      || ! stack_realign_fp)));
4075     }
4076 #else
4077   reg_eliminate[0].from = reg_eliminate_1[0].from;
4078   reg_eliminate[0].to = reg_eliminate_1[0].to;
4079   reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4080     = ! frame_pointer_needed;
4081 #endif
4082
4083   /* Count the number of eliminable registers and build the FROM and TO
4084      REG rtx's.  Note that code in gen_rtx_REG will cause, e.g.,
4085      gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4086      We depend on this.  */
4087   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4088     {
4089       num_eliminable += ep->can_eliminate;
4090       ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4091       ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4092     }
4093 }
4094
4095 /* Find all the pseudo registers that didn't get hard regs
4096    but do have known equivalent constants or memory slots.
4097    These include parameters (known equivalent to parameter slots)
4098    and cse'd or loop-moved constant memory addresses.
4099
4100    Record constant equivalents in reg_equiv_constant
4101    so they will be substituted by find_reloads.
4102    Record memory equivalents in reg_mem_equiv so they can
4103    be substituted eventually by altering the REG-rtx's.  */
4104
4105 static void
4106 init_eliminable_invariants (rtx first, bool do_subregs)
4107 {
4108   int i;
4109   rtx insn;
4110
4111   grow_reg_equivs ();
4112   if (do_subregs)
4113     reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4114   else
4115     reg_max_ref_width = NULL;
4116
4117   num_eliminable_invariants = 0;
4118
4119   first_label_num = get_first_label_num ();
4120   num_labels = max_label_num () - first_label_num;
4121
4122   /* Allocate the tables used to store offset information at labels.  */
4123   offsets_known_at = XNEWVEC (char, num_labels);
4124   offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4125
4126 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4127    to.  If DO_SUBREGS is true, also find all paradoxical subregs and
4128    find largest such for each pseudo.  FIRST is the head of the insn
4129    list.  */
4130
4131   for (insn = first; insn; insn = NEXT_INSN (insn))
4132     {
4133       rtx set = single_set (insn);
4134
4135       /* We may introduce USEs that we want to remove at the end, so
4136          we'll mark them with QImode.  Make sure there are no
4137          previously-marked insns left by say regmove.  */
4138       if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4139           && GET_MODE (insn) != VOIDmode)
4140         PUT_MODE (insn, VOIDmode);
4141
4142       if (do_subregs && NONDEBUG_INSN_P (insn))
4143         scan_paradoxical_subregs (PATTERN (insn));
4144
4145       if (set != 0 && REG_P (SET_DEST (set)))
4146         {
4147           rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4148           rtx x;
4149
4150           if (! note)
4151             continue;
4152
4153           i = REGNO (SET_DEST (set));
4154           x = XEXP (note, 0);
4155
4156           if (i <= LAST_VIRTUAL_REGISTER)
4157             continue;
4158
4159           /* If flag_pic and we have constant, verify it's legitimate.  */
4160           if (!CONSTANT_P (x)
4161               || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4162             {
4163               /* It can happen that a REG_EQUIV note contains a MEM
4164                  that is not a legitimate memory operand.  As later
4165                  stages of reload assume that all addresses found
4166                  in the reg_equiv_* arrays were originally legitimate,
4167                  we ignore such REG_EQUIV notes.  */
4168               if (memory_operand (x, VOIDmode))
4169                 {
4170                   /* Always unshare the equivalence, so we can
4171                      substitute into this insn without touching the
4172                        equivalence.  */
4173                   reg_equiv_memory_loc (i) = copy_rtx (x);
4174                 }
4175               else if (function_invariant_p (x))
4176                 {
4177                   enum machine_mode mode;
4178
4179                   mode = GET_MODE (SET_DEST (set));
4180                   if (GET_CODE (x) == PLUS)
4181                     {
4182                       /* This is PLUS of frame pointer and a constant,
4183                          and might be shared.  Unshare it.  */
4184                       reg_equiv_invariant (i) = copy_rtx (x);
4185                       num_eliminable_invariants++;
4186                     }
4187                   else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4188                     {
4189                       reg_equiv_invariant (i) = x;
4190                       num_eliminable_invariants++;
4191                     }
4192                   else if (targetm.legitimate_constant_p (mode, x))
4193                     reg_equiv_constant (i) = x;
4194                   else
4195                     {
4196                       reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4197                       if (! reg_equiv_memory_loc (i))
4198                         reg_equiv_init (i) = NULL_RTX;
4199                     }
4200                 }
4201               else
4202                 {
4203                   reg_equiv_init (i) = NULL_RTX;
4204                   continue;
4205                 }
4206             }
4207           else
4208             reg_equiv_init (i) = NULL_RTX;
4209         }
4210     }
4211
4212   if (dump_file)
4213     for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4214       if (reg_equiv_init (i))
4215         {
4216           fprintf (dump_file, "init_insns for %u: ", i);
4217           print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4218           fprintf (dump_file, "\n");
4219         }
4220 }
4221
4222 /* Indicate that we no longer have known memory locations or constants.
4223    Free all data involved in tracking these.  */
4224
4225 static void
4226 free_reg_equiv (void)
4227 {
4228   int i;
4229
4230   free (offsets_known_at);
4231   free (offsets_at);
4232   offsets_at = 0;
4233   offsets_known_at = 0;
4234
4235   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4236     if (reg_equiv_alt_mem_list (i))
4237       free_EXPR_LIST_list (&reg_equiv_alt_mem_list (i));
4238   vec_free (reg_equivs);
4239 }
4240 \f
4241 /* Kick all pseudos out of hard register REGNO.
4242
4243    If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4244    because we found we can't eliminate some register.  In the case, no pseudos
4245    are allowed to be in the register, even if they are only in a block that
4246    doesn't require spill registers, unlike the case when we are spilling this
4247    hard reg to produce another spill register.
4248
4249    Return nonzero if any pseudos needed to be kicked out.  */
4250
4251 static void
4252 spill_hard_reg (unsigned int regno, int cant_eliminate)
4253 {
4254   int i;
4255
4256   if (cant_eliminate)
4257     {
4258       SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4259       df_set_regs_ever_live (regno, true);
4260     }
4261
4262   /* Spill every pseudo reg that was allocated to this reg
4263      or to something that overlaps this reg.  */
4264
4265   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4266     if (reg_renumber[i] >= 0
4267         && (unsigned int) reg_renumber[i] <= regno
4268         && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4269       SET_REGNO_REG_SET (&spilled_pseudos, i);
4270 }
4271
4272 /* After find_reload_regs has been run for all insn that need reloads,
4273    and/or spill_hard_regs was called, this function is used to actually
4274    spill pseudo registers and try to reallocate them.  It also sets up the
4275    spill_regs array for use by choose_reload_regs.  */
4276
4277 static int
4278 finish_spills (int global)
4279 {
4280   struct insn_chain *chain;
4281   int something_changed = 0;
4282   unsigned i;
4283   reg_set_iterator rsi;
4284
4285   /* Build the spill_regs array for the function.  */
4286   /* If there are some registers still to eliminate and one of the spill regs
4287      wasn't ever used before, additional stack space may have to be
4288      allocated to store this register.  Thus, we may have changed the offset
4289      between the stack and frame pointers, so mark that something has changed.
4290
4291      One might think that we need only set VAL to 1 if this is a call-used
4292      register.  However, the set of registers that must be saved by the
4293      prologue is not identical to the call-used set.  For example, the
4294      register used by the call insn for the return PC is a call-used register,
4295      but must be saved by the prologue.  */
4296
4297   n_spills = 0;
4298   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4299     if (TEST_HARD_REG_BIT (used_spill_regs, i))
4300       {
4301         spill_reg_order[i] = n_spills;
4302         spill_regs[n_spills++] = i;
4303         if (num_eliminable && ! df_regs_ever_live_p (i))
4304           something_changed = 1;
4305         df_set_regs_ever_live (i, true);
4306       }
4307     else
4308       spill_reg_order[i] = -1;
4309
4310   EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4311     if (! ira_conflicts_p || reg_renumber[i] >= 0)
4312       {
4313         /* Record the current hard register the pseudo is allocated to
4314            in pseudo_previous_regs so we avoid reallocating it to the
4315            same hard reg in a later pass.  */
4316         gcc_assert (reg_renumber[i] >= 0);
4317
4318         SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4319         /* Mark it as no longer having a hard register home.  */
4320         reg_renumber[i] = -1;
4321         if (ira_conflicts_p)
4322           /* Inform IRA about the change.  */
4323           ira_mark_allocation_change (i);
4324         /* We will need to scan everything again.  */
4325         something_changed = 1;
4326       }
4327
4328   /* Retry global register allocation if possible.  */
4329   if (global && ira_conflicts_p)
4330     {
4331       unsigned int n;
4332
4333       memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4334       /* For every insn that needs reloads, set the registers used as spill
4335          regs in pseudo_forbidden_regs for every pseudo live across the
4336          insn.  */
4337       for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4338         {
4339           EXECUTE_IF_SET_IN_REG_SET
4340             (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4341             {
4342               IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4343                                 chain->used_spill_regs);
4344             }
4345           EXECUTE_IF_SET_IN_REG_SET
4346             (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4347             {
4348               IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4349                                 chain->used_spill_regs);
4350             }
4351         }
4352
4353       /* Retry allocating the pseudos spilled in IRA and the
4354          reload.  For each reg, merge the various reg sets that
4355          indicate which hard regs can't be used, and call
4356          ira_reassign_pseudos.  */
4357       for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4358         if (reg_old_renumber[i] != reg_renumber[i])
4359           {
4360             if (reg_renumber[i] < 0)
4361               temp_pseudo_reg_arr[n++] = i;
4362             else
4363               CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4364           }
4365       if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4366                                 bad_spill_regs_global,
4367                                 pseudo_forbidden_regs, pseudo_previous_regs,
4368                                 &spilled_pseudos))
4369         something_changed = 1;
4370     }
4371   /* Fix up the register information in the insn chain.
4372      This involves deleting those of the spilled pseudos which did not get
4373      a new hard register home from the live_{before,after} sets.  */
4374   for (chain = reload_insn_chain; chain; chain = chain->next)
4375     {
4376       HARD_REG_SET used_by_pseudos;
4377       HARD_REG_SET used_by_pseudos2;
4378
4379       if (! ira_conflicts_p)
4380         {
4381           /* Don't do it for IRA because IRA and the reload still can
4382              assign hard registers to the spilled pseudos on next
4383              reload iterations.  */
4384           AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4385           AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4386         }
4387       /* Mark any unallocated hard regs as available for spills.  That
4388          makes inheritance work somewhat better.  */
4389       if (chain->need_reload)
4390         {
4391           REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4392           REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4393           IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4394
4395           compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4396           compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4397           /* Value of chain->used_spill_regs from previous iteration
4398              may be not included in the value calculated here because
4399              of possible removing caller-saves insns (see function
4400              delete_caller_save_insns.  */
4401           COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4402           AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4403         }
4404     }
4405
4406   CLEAR_REG_SET (&changed_allocation_pseudos);
4407   /* Let alter_reg modify the reg rtx's for the modified pseudos.  */
4408   for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4409     {
4410       int regno = reg_renumber[i];
4411       if (reg_old_renumber[i] == regno)
4412         continue;
4413
4414       SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4415
4416       alter_reg (i, reg_old_renumber[i], false);
4417       reg_old_renumber[i] = regno;
4418       if (dump_file)
4419         {
4420           if (regno == -1)
4421             fprintf (dump_file, " Register %d now on stack.\n\n", i);
4422           else
4423             fprintf (dump_file, " Register %d now in %d.\n\n",
4424                      i, reg_renumber[i]);
4425         }
4426     }
4427
4428   return something_changed;
4429 }
4430 \f
4431 /* Find all paradoxical subregs within X and update reg_max_ref_width.  */
4432
4433 static void
4434 scan_paradoxical_subregs (rtx x)
4435 {
4436   int i;
4437   const char *fmt;
4438   enum rtx_code code = GET_CODE (x);
4439
4440   switch (code)
4441     {
4442     case REG:
4443     case CONST:
4444     case SYMBOL_REF:
4445     case LABEL_REF:
4446     CASE_CONST_ANY:
4447     case CC0:
4448     case PC:
4449     case USE:
4450     case CLOBBER:
4451       return;
4452
4453     case SUBREG:
4454       if (REG_P (SUBREG_REG (x))
4455           && (GET_MODE_SIZE (GET_MODE (x))
4456               > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4457         {
4458           reg_max_ref_width[REGNO (SUBREG_REG (x))]
4459             = GET_MODE_SIZE (GET_MODE (x));
4460           mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4461         }
4462       return;
4463
4464     default:
4465       break;
4466     }
4467
4468   fmt = GET_RTX_FORMAT (code);
4469   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4470     {
4471       if (fmt[i] == 'e')
4472         scan_paradoxical_subregs (XEXP (x, i));
4473       else if (fmt[i] == 'E')
4474         {
4475           int j;
4476           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4477             scan_paradoxical_subregs (XVECEXP (x, i, j));
4478         }
4479     }
4480 }
4481
4482 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4483    If *OP_PTR is a paradoxical subreg, try to remove that subreg
4484    and apply the corresponding narrowing subreg to *OTHER_PTR.
4485    Return true if the operands were changed, false otherwise.  */
4486
4487 static bool
4488 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4489 {
4490   rtx op, inner, other, tem;
4491
4492   op = *op_ptr;
4493   if (!paradoxical_subreg_p (op))
4494     return false;
4495   inner = SUBREG_REG (op);
4496
4497   other = *other_ptr;
4498   tem = gen_lowpart_common (GET_MODE (inner), other);
4499   if (!tem)
4500     return false;
4501
4502   /* If the lowpart operation turned a hard register into a subreg,
4503      rather than simplifying it to another hard register, then the
4504      mode change cannot be properly represented.  For example, OTHER
4505      might be valid in its current mode, but not in the new one.  */
4506   if (GET_CODE (tem) == SUBREG
4507       && REG_P (other)
4508       && HARD_REGISTER_P (other))
4509     return false;
4510
4511   *op_ptr = inner;
4512   *other_ptr = tem;
4513   return true;
4514 }
4515 \f
4516 /* A subroutine of reload_as_needed.  If INSN has a REG_EH_REGION note,
4517    examine all of the reload insns between PREV and NEXT exclusive, and
4518    annotate all that may trap.  */
4519
4520 static void
4521 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4522 {
4523   rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4524   if (note == NULL)
4525     return;
4526   if (!insn_could_throw_p (insn))
4527     remove_note (insn, note);
4528   copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4529 }
4530
4531 /* Reload pseudo-registers into hard regs around each insn as needed.
4532    Additional register load insns are output before the insn that needs it
4533    and perhaps store insns after insns that modify the reloaded pseudo reg.
4534
4535    reg_last_reload_reg and reg_reloaded_contents keep track of
4536    which registers are already available in reload registers.
4537    We update these for the reloads that we perform,
4538    as the insns are scanned.  */
4539
4540 static void
4541 reload_as_needed (int live_known)
4542 {
4543   struct insn_chain *chain;
4544 #if defined (AUTO_INC_DEC)
4545   int i;
4546 #endif
4547   rtx x, marker;
4548
4549   memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4550   memset (spill_reg_store, 0, sizeof spill_reg_store);
4551   reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4552   INIT_REG_SET (&reg_has_output_reload);
4553   CLEAR_HARD_REG_SET (reg_reloaded_valid);
4554   CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4555
4556   set_initial_elim_offsets ();
4557
4558   /* Generate a marker insn that we will move around.  */
4559   marker = emit_note (NOTE_INSN_DELETED);
4560   unlink_insn_chain (marker, marker);
4561
4562   for (chain = reload_insn_chain; chain; chain = chain->next)
4563     {
4564       rtx prev = 0;
4565       rtx insn = chain->insn;
4566       rtx old_next = NEXT_INSN (insn);
4567 #ifdef AUTO_INC_DEC
4568       rtx old_prev = PREV_INSN (insn);
4569 #endif
4570
4571       /* If we pass a label, copy the offsets from the label information
4572          into the current offsets of each elimination.  */
4573       if (LABEL_P (insn))
4574         set_offsets_for_label (insn);
4575
4576       else if (INSN_P (insn))
4577         {
4578           regset_head regs_to_forget;
4579           INIT_REG_SET (&regs_to_forget);
4580           note_stores (PATTERN (insn), forget_old_reloads_1, &regs_to_forget);
4581
4582           /* If this is a USE and CLOBBER of a MEM, ensure that any
4583              references to eliminable registers have been removed.  */
4584
4585           if ((GET_CODE (PATTERN (insn)) == USE
4586                || GET_CODE (PATTERN (insn)) == CLOBBER)
4587               && MEM_P (XEXP (PATTERN (insn), 0)))
4588             XEXP (XEXP (PATTERN (insn), 0), 0)
4589               = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4590                                 GET_MODE (XEXP (PATTERN (insn), 0)),
4591                                 NULL_RTX);
4592
4593           /* If we need to do register elimination processing, do so.
4594              This might delete the insn, in which case we are done.  */
4595           if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4596             {
4597               eliminate_regs_in_insn (insn, 1);
4598               if (NOTE_P (insn))
4599                 {
4600                   update_eliminable_offsets ();
4601                   CLEAR_REG_SET (&regs_to_forget);
4602                   continue;
4603                 }
4604             }
4605
4606           /* If need_elim is nonzero but need_reload is zero, one might think
4607              that we could simply set n_reloads to 0.  However, find_reloads
4608              could have done some manipulation of the insn (such as swapping
4609              commutative operands), and these manipulations are lost during
4610              the first pass for every insn that needs register elimination.
4611              So the actions of find_reloads must be redone here.  */
4612
4613           if (! chain->need_elim && ! chain->need_reload
4614               && ! chain->need_operand_change)
4615             n_reloads = 0;
4616           /* First find the pseudo regs that must be reloaded for this insn.
4617              This info is returned in the tables reload_... (see reload.h).
4618              Also modify the body of INSN by substituting RELOAD
4619              rtx's for those pseudo regs.  */
4620           else
4621             {
4622               CLEAR_REG_SET (&reg_has_output_reload);
4623               CLEAR_HARD_REG_SET (reg_is_output_reload);
4624
4625               find_reloads (insn, 1, spill_indirect_levels, live_known,
4626                             spill_reg_order);
4627             }
4628
4629           if (n_reloads > 0)
4630             {
4631               rtx next = NEXT_INSN (insn);
4632               rtx p;
4633
4634               /* ??? PREV can get deleted by reload inheritance.
4635                  Work around this by emitting a marker note.  */
4636               prev = PREV_INSN (insn);
4637               reorder_insns_nobb (marker, marker, prev);
4638
4639               /* Now compute which reload regs to reload them into.  Perhaps
4640                  reusing reload regs from previous insns, or else output
4641                  load insns to reload them.  Maybe output store insns too.
4642                  Record the choices of reload reg in reload_reg_rtx.  */
4643               choose_reload_regs (chain);
4644
4645               /* Generate the insns to reload operands into or out of
4646                  their reload regs.  */
4647               emit_reload_insns (chain);
4648
4649               /* Substitute the chosen reload regs from reload_reg_rtx
4650                  into the insn's body (or perhaps into the bodies of other
4651                  load and store insn that we just made for reloading
4652                  and that we moved the structure into).  */
4653               subst_reloads (insn);
4654
4655               prev = PREV_INSN (marker);
4656               unlink_insn_chain (marker, marker);
4657
4658               /* Adjust the exception region notes for loads and stores.  */
4659               if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4660                 fixup_eh_region_note (insn, prev, next);
4661
4662               /* Adjust the location of REG_ARGS_SIZE.  */
4663               p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4664               if (p)
4665                 {
4666                   remove_note (insn, p);
4667                   fixup_args_size_notes (prev, PREV_INSN (next),
4668                                          INTVAL (XEXP (p, 0)));
4669                 }
4670
4671               /* If this was an ASM, make sure that all the reload insns
4672                  we have generated are valid.  If not, give an error
4673                  and delete them.  */
4674               if (asm_noperands (PATTERN (insn)) >= 0)
4675                 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4676                   if (p != insn && INSN_P (p)
4677                       && GET_CODE (PATTERN (p)) != USE
4678                       && (recog_memoized (p) < 0
4679                           || (extract_insn (p), ! constrain_operands (1))))
4680                     {
4681                       error_for_asm (insn,
4682                                      "%<asm%> operand requires "
4683                                      "impossible reload");
4684                       delete_insn (p);
4685                     }
4686             }
4687
4688           if (num_eliminable && chain->need_elim)
4689             update_eliminable_offsets ();
4690
4691           /* Any previously reloaded spilled pseudo reg, stored in this insn,
4692              is no longer validly lying around to save a future reload.
4693              Note that this does not detect pseudos that were reloaded
4694              for this insn in order to be stored in
4695              (obeying register constraints).  That is correct; such reload
4696              registers ARE still valid.  */
4697           forget_marked_reloads (&regs_to_forget);
4698           CLEAR_REG_SET (&regs_to_forget);
4699
4700           /* There may have been CLOBBER insns placed after INSN.  So scan
4701              between INSN and NEXT and use them to forget old reloads.  */
4702           for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4703             if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4704               note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4705
4706 #ifdef AUTO_INC_DEC
4707           /* Likewise for regs altered by auto-increment in this insn.
4708              REG_INC notes have been changed by reloading:
4709              find_reloads_address_1 records substitutions for them,
4710              which have been performed by subst_reloads above.  */
4711           for (i = n_reloads - 1; i >= 0; i--)
4712             {
4713               rtx in_reg = rld[i].in_reg;
4714               if (in_reg)
4715                 {
4716                   enum rtx_code code = GET_CODE (in_reg);
4717                   /* PRE_INC / PRE_DEC will have the reload register ending up
4718                      with the same value as the stack slot, but that doesn't
4719                      hold true for POST_INC / POST_DEC.  Either we have to
4720                      convert the memory access to a true POST_INC / POST_DEC,
4721                      or we can't use the reload register for inheritance.  */
4722                   if ((code == POST_INC || code == POST_DEC)
4723                       && TEST_HARD_REG_BIT (reg_reloaded_valid,
4724                                             REGNO (rld[i].reg_rtx))
4725                       /* Make sure it is the inc/dec pseudo, and not
4726                          some other (e.g. output operand) pseudo.  */
4727                       && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4728                           == REGNO (XEXP (in_reg, 0))))
4729
4730                     {
4731                       rtx reload_reg = rld[i].reg_rtx;
4732                       enum machine_mode mode = GET_MODE (reload_reg);
4733                       int n = 0;
4734                       rtx p;
4735
4736                       for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4737                         {
4738                           /* We really want to ignore REG_INC notes here, so
4739                              use PATTERN (p) as argument to reg_set_p .  */
4740                           if (reg_set_p (reload_reg, PATTERN (p)))
4741                             break;
4742                           n = count_occurrences (PATTERN (p), reload_reg, 0);
4743                           if (! n)
4744                             continue;
4745                           if (n == 1)
4746                             {
4747                               rtx replace_reg
4748                                 = gen_rtx_fmt_e (code, mode, reload_reg);
4749
4750                               validate_replace_rtx_group (reload_reg,
4751                                                           replace_reg, p);
4752                               n = verify_changes (0);
4753
4754                               /* We must also verify that the constraints
4755                                  are met after the replacement.  Make sure
4756                                  extract_insn is only called for an insn
4757                                  where the replacements were found to be
4758                                  valid so far. */
4759                               if (n)
4760                                 {
4761                                   extract_insn (p);
4762                                   n = constrain_operands (1);
4763                                 }
4764
4765                               /* If the constraints were not met, then
4766                                  undo the replacement, else confirm it.  */
4767                               if (!n)
4768                                 cancel_changes (0);
4769                               else
4770                                 confirm_change_group ();
4771                             }
4772                           break;
4773                         }
4774                       if (n == 1)
4775                         {
4776                           add_reg_note (p, REG_INC, reload_reg);
4777                           /* Mark this as having an output reload so that the
4778                              REG_INC processing code below won't invalidate
4779                              the reload for inheritance.  */
4780                           SET_HARD_REG_BIT (reg_is_output_reload,
4781                                             REGNO (reload_reg));
4782                           SET_REGNO_REG_SET (&reg_has_output_reload,
4783                                              REGNO (XEXP (in_reg, 0)));
4784                         }
4785                       else
4786                         forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4787                                               NULL);
4788                     }
4789                   else if ((code == PRE_INC || code == PRE_DEC)
4790                            && TEST_HARD_REG_BIT (reg_reloaded_valid,
4791                                                  REGNO (rld[i].reg_rtx))
4792                            /* Make sure it is the inc/dec pseudo, and not
4793                               some other (e.g. output operand) pseudo.  */
4794                            && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4795                                == REGNO (XEXP (in_reg, 0))))
4796                     {
4797                       SET_HARD_REG_BIT (reg_is_output_reload,
4798                                         REGNO (rld[i].reg_rtx));
4799                       SET_REGNO_REG_SET (&reg_has_output_reload,
4800                                          REGNO (XEXP (in_reg, 0)));
4801                     }
4802                   else if (code == PRE_INC || code == PRE_DEC
4803                            || code == POST_INC || code == POST_DEC)
4804                     {
4805                       int in_regno = REGNO (XEXP (in_reg, 0));
4806
4807                       if (reg_last_reload_reg[in_regno] != NULL_RTX)
4808                         {
4809                           int in_hard_regno;
4810                           bool forget_p = true;
4811
4812                           in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4813                           if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4814                                                  in_hard_regno))
4815                             {
4816                               for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4817                                    x != old_next;
4818                                    x = NEXT_INSN (x))
4819                                 if (x == reg_reloaded_insn[in_hard_regno])
4820                                   {
4821                                     forget_p = false;
4822                                     break;
4823                                   }
4824                             }
4825                           /* If for some reasons, we didn't set up
4826                              reg_last_reload_reg in this insn,
4827                              invalidate inheritance from previous
4828                              insns for the incremented/decremented
4829                              register.  Such registers will be not in
4830                              reg_has_output_reload.  Invalidate it
4831                              also if the corresponding element in
4832                              reg_reloaded_insn is also
4833                              invalidated.  */
4834                           if (forget_p)
4835                             forget_old_reloads_1 (XEXP (in_reg, 0),
4836                                                   NULL_RTX, NULL);
4837                         }
4838                     }
4839                 }
4840             }
4841           /* If a pseudo that got a hard register is auto-incremented,
4842              we must purge records of copying it into pseudos without
4843              hard registers.  */
4844           for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4845             if (REG_NOTE_KIND (x) == REG_INC)
4846               {
4847                 /* See if this pseudo reg was reloaded in this insn.
4848                    If so, its last-reload info is still valid
4849                    because it is based on this insn's reload.  */
4850                 for (i = 0; i < n_reloads; i++)
4851                   if (rld[i].out == XEXP (x, 0))
4852                     break;
4853
4854                 if (i == n_reloads)
4855                   forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4856               }
4857 #endif
4858         }
4859       /* A reload reg's contents are unknown after a label.  */
4860       if (LABEL_P (insn))
4861         CLEAR_HARD_REG_SET (reg_reloaded_valid);
4862
4863       /* Don't assume a reload reg is still good after a call insn
4864          if it is a call-used reg, or if it contains a value that will
4865          be partially clobbered by the call.  */
4866       else if (CALL_P (insn))
4867         {
4868           AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4869           AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4870
4871           /* If this is a call to a setjmp-type function, we must not
4872              reuse any reload reg contents across the call; that will
4873              just be clobbered by other uses of the register in later
4874              code, before the longjmp.  */
4875           if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4876             CLEAR_HARD_REG_SET (reg_reloaded_valid);
4877         }
4878     }
4879
4880   /* Clean up.  */
4881   free (reg_last_reload_reg);
4882   CLEAR_REG_SET (&reg_has_output_reload);
4883 }
4884
4885 /* Discard all record of any value reloaded from X,
4886    or reloaded in X from someplace else;
4887    unless X is an output reload reg of the current insn.
4888
4889    X may be a hard reg (the reload reg)
4890    or it may be a pseudo reg that was reloaded from.
4891
4892    When DATA is non-NULL just mark the registers in regset
4893    to be forgotten later.  */
4894
4895 static void
4896 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4897                       void *data)
4898 {
4899   unsigned int regno;
4900   unsigned int nr;
4901   regset regs = (regset) data;
4902
4903   /* note_stores does give us subregs of hard regs,
4904      subreg_regno_offset requires a hard reg.  */
4905   while (GET_CODE (x) == SUBREG)
4906     {
4907       /* We ignore the subreg offset when calculating the regno,
4908          because we are using the entire underlying hard register
4909          below.  */
4910       x = SUBREG_REG (x);
4911     }
4912
4913   if (!REG_P (x))
4914     return;
4915
4916   regno = REGNO (x);
4917
4918   if (regno >= FIRST_PSEUDO_REGISTER)
4919     nr = 1;
4920   else
4921     {
4922       unsigned int i;
4923
4924       nr = hard_regno_nregs[regno][GET_MODE (x)];
4925       /* Storing into a spilled-reg invalidates its contents.
4926          This can happen if a block-local pseudo is allocated to that reg
4927          and it wasn't spilled because this block's total need is 0.
4928          Then some insn might have an optional reload and use this reg.  */
4929       if (!regs)
4930         for (i = 0; i < nr; i++)
4931           /* But don't do this if the reg actually serves as an output
4932              reload reg in the current instruction.  */
4933           if (n_reloads == 0
4934               || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4935             {
4936               CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4937               spill_reg_store[regno + i] = 0;
4938             }
4939     }
4940
4941   if (regs)
4942     while (nr-- > 0)
4943       SET_REGNO_REG_SET (regs, regno + nr);
4944   else
4945     {
4946       /* Since value of X has changed,
4947          forget any value previously copied from it.  */
4948
4949       while (nr-- > 0)
4950         /* But don't forget a copy if this is the output reload
4951            that establishes the copy's validity.  */
4952         if (n_reloads == 0
4953             || !REGNO_REG_SET_P (&reg_has_output_reload, regno + nr))
4954           reg_last_reload_reg[regno + nr] = 0;
4955      }
4956 }
4957
4958 /* Forget the reloads marked in regset by previous function.  */
4959 static void
4960 forget_marked_reloads (regset regs)
4961 {
4962   unsigned int reg;
4963   reg_set_iterator rsi;
4964   EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4965     {
4966       if (reg < FIRST_PSEUDO_REGISTER
4967           /* But don't do this if the reg actually serves as an output
4968              reload reg in the current instruction.  */
4969           && (n_reloads == 0
4970               || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4971           {
4972             CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4973             spill_reg_store[reg] = 0;
4974           }
4975       if (n_reloads == 0
4976           || !REGNO_REG_SET_P (&reg_has_output_reload, reg))
4977         reg_last_reload_reg[reg] = 0;
4978     }
4979 }
4980 \f
4981 /* The following HARD_REG_SETs indicate when each hard register is
4982    used for a reload of various parts of the current insn.  */
4983
4984 /* If reg is unavailable for all reloads.  */
4985 static HARD_REG_SET reload_reg_unavailable;
4986 /* If reg is in use as a reload reg for a RELOAD_OTHER reload.  */
4987 static HARD_REG_SET reload_reg_used;
4988 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I.  */
4989 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4990 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I.  */
4991 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4992 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I.  */
4993 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4994 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I.  */
4995 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4996 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I.  */
4997 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4998 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I.  */
4999 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5000 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload.  */
5001 static HARD_REG_SET reload_reg_used_in_op_addr;
5002 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload.  */
5003 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5004 /* If reg is in use for a RELOAD_FOR_INSN reload.  */
5005 static HARD_REG_SET reload_reg_used_in_insn;
5006 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload.  */
5007 static HARD_REG_SET reload_reg_used_in_other_addr;
5008
5009 /* If reg is in use as a reload reg for any sort of reload.  */
5010 static HARD_REG_SET reload_reg_used_at_all;
5011
5012 /* If reg is use as an inherited reload.  We just mark the first register
5013    in the group.  */
5014 static HARD_REG_SET reload_reg_used_for_inherit;
5015
5016 /* Records which hard regs are used in any way, either as explicit use or
5017    by being allocated to a pseudo during any point of the current insn.  */
5018 static HARD_REG_SET reg_used_in_insn;
5019
5020 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5021    TYPE. MODE is used to indicate how many consecutive regs are
5022    actually used.  */
5023
5024 static void
5025 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5026                         enum machine_mode mode)
5027 {
5028   switch (type)
5029     {
5030     case RELOAD_OTHER:
5031       add_to_hard_reg_set (&reload_reg_used, mode, regno);
5032       break;
5033
5034     case RELOAD_FOR_INPUT_ADDRESS:
5035       add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5036       break;
5037
5038     case RELOAD_FOR_INPADDR_ADDRESS:
5039       add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5040       break;
5041
5042     case RELOAD_FOR_OUTPUT_ADDRESS:
5043       add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5044       break;
5045
5046     case RELOAD_FOR_OUTADDR_ADDRESS:
5047       add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5048       break;
5049
5050     case RELOAD_FOR_OPERAND_ADDRESS:
5051       add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5052       break;
5053
5054     case RELOAD_FOR_OPADDR_ADDR:
5055       add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5056       break;
5057
5058     case RELOAD_FOR_OTHER_ADDRESS:
5059       add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5060       break;
5061
5062     case RELOAD_FOR_INPUT:
5063       add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5064       break;
5065
5066     case RELOAD_FOR_OUTPUT:
5067       add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5068       break;
5069
5070     case RELOAD_FOR_INSN:
5071       add_to_hard_reg_set (&reload_reg_used_in_insn,  mode, regno);
5072       break;
5073     }
5074
5075   add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5076 }
5077
5078 /* Similarly, but show REGNO is no longer in use for a reload.  */
5079
5080 static void
5081 clear_reload_reg_in_use (unsigned int regno, int opnum,
5082                          enum reload_type type, enum machine_mode mode)
5083 {
5084   unsigned int nregs = hard_regno_nregs[regno][mode];
5085   unsigned int start_regno, end_regno, r;
5086   int i;
5087   /* A complication is that for some reload types, inheritance might
5088      allow multiple reloads of the same types to share a reload register.
5089      We set check_opnum if we have to check only reloads with the same
5090      operand number, and check_any if we have to check all reloads.  */
5091   int check_opnum = 0;
5092   int check_any = 0;
5093   HARD_REG_SET *used_in_set;
5094
5095   switch (type)
5096     {
5097     case RELOAD_OTHER:
5098       used_in_set = &reload_reg_used;
5099       break;
5100
5101     case RELOAD_FOR_INPUT_ADDRESS:
5102       used_in_set = &reload_reg_used_in_input_addr[opnum];
5103       break;
5104
5105     case RELOAD_FOR_INPADDR_ADDRESS:
5106       check_opnum = 1;
5107       used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5108       break;
5109
5110     case RELOAD_FOR_OUTPUT_ADDRESS:
5111       used_in_set = &reload_reg_used_in_output_addr[opnum];
5112       break;
5113
5114     case RELOAD_FOR_OUTADDR_ADDRESS:
5115       check_opnum = 1;
5116       used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5117       break;
5118
5119     case RELOAD_FOR_OPERAND_ADDRESS:
5120       used_in_set = &reload_reg_used_in_op_addr;
5121       break;
5122
5123     case RELOAD_FOR_OPADDR_ADDR:
5124       check_any = 1;
5125       used_in_set = &reload_reg_used_in_op_addr_reload;
5126       break;
5127
5128     case RELOAD_FOR_OTHER_ADDRESS:
5129       used_in_set = &reload_reg_used_in_other_addr;
5130       check_any = 1;
5131       break;
5132
5133     case RELOAD_FOR_INPUT:
5134       used_in_set = &reload_reg_used_in_input[opnum];
5135       break;
5136
5137     case RELOAD_FOR_OUTPUT:
5138       used_in_set = &reload_reg_used_in_output[opnum];
5139       break;
5140
5141     case RELOAD_FOR_INSN:
5142       used_in_set = &reload_reg_used_in_insn;
5143       break;
5144     default:
5145       gcc_unreachable ();
5146     }
5147   /* We resolve conflicts with remaining reloads of the same type by
5148      excluding the intervals of reload registers by them from the
5149      interval of freed reload registers.  Since we only keep track of
5150      one set of interval bounds, we might have to exclude somewhat
5151      more than what would be necessary if we used a HARD_REG_SET here.
5152      But this should only happen very infrequently, so there should
5153      be no reason to worry about it.  */
5154
5155   start_regno = regno;
5156   end_regno = regno + nregs;
5157   if (check_opnum || check_any)
5158     {
5159       for (i = n_reloads - 1; i >= 0; i--)
5160         {
5161           if (rld[i].when_needed == type
5162               && (check_any || rld[i].opnum == opnum)
5163               && rld[i].reg_rtx)
5164             {
5165               unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5166               unsigned int conflict_end
5167                 = end_hard_regno (rld[i].mode, conflict_start);
5168
5169               /* If there is an overlap with the first to-be-freed register,
5170                  adjust the interval start.  */
5171               if (conflict_start <= start_regno && conflict_end > start_regno)
5172                 start_regno = conflict_end;
5173               /* Otherwise, if there is a conflict with one of the other
5174                  to-be-freed registers, adjust the interval end.  */
5175               if (conflict_start > start_regno && conflict_start < end_regno)
5176                 end_regno = conflict_start;
5177             }
5178         }
5179     }
5180
5181   for (r = start_regno; r < end_regno; r++)
5182     CLEAR_HARD_REG_BIT (*used_in_set, r);
5183 }
5184
5185 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5186    specified by OPNUM and TYPE.  */
5187
5188 static int
5189 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5190 {
5191   int i;
5192
5193   /* In use for a RELOAD_OTHER means it's not available for anything.  */
5194   if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5195       || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5196     return 0;
5197
5198   switch (type)
5199     {
5200     case RELOAD_OTHER:
5201       /* In use for anything means we can't use it for RELOAD_OTHER.  */
5202       if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5203           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5204           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5205           || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5206         return 0;
5207
5208       for (i = 0; i < reload_n_operands; i++)
5209         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5210             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5211             || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5212             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5213             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5214             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5215           return 0;
5216
5217       return 1;
5218
5219     case RELOAD_FOR_INPUT:
5220       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5221           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5222         return 0;
5223
5224       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5225         return 0;
5226
5227       /* If it is used for some other input, can't use it.  */
5228       for (i = 0; i < reload_n_operands; i++)
5229         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5230           return 0;
5231
5232       /* If it is used in a later operand's address, can't use it.  */
5233       for (i = opnum + 1; i < reload_n_operands; i++)
5234         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5235             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5236           return 0;
5237
5238       return 1;
5239
5240     case RELOAD_FOR_INPUT_ADDRESS:
5241       /* Can't use a register if it is used for an input address for this
5242          operand or used as an input in an earlier one.  */
5243       if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5244           || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5245         return 0;
5246
5247       for (i = 0; i < opnum; i++)
5248         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5249           return 0;
5250
5251       return 1;
5252
5253     case RELOAD_FOR_INPADDR_ADDRESS:
5254       /* Can't use a register if it is used for an input address
5255          for this operand or used as an input in an earlier
5256          one.  */
5257       if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5258         return 0;
5259
5260       for (i = 0; i < opnum; i++)
5261         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5262           return 0;
5263
5264       return 1;
5265
5266     case RELOAD_FOR_OUTPUT_ADDRESS:
5267       /* Can't use a register if it is used for an output address for this
5268          operand or used as an output in this or a later operand.  Note
5269          that multiple output operands are emitted in reverse order, so
5270          the conflicting ones are those with lower indices.  */
5271       if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5272         return 0;
5273
5274       for (i = 0; i <= opnum; i++)
5275         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5276           return 0;
5277
5278       return 1;
5279
5280     case RELOAD_FOR_OUTADDR_ADDRESS:
5281       /* Can't use a register if it is used for an output address
5282          for this operand or used as an output in this or a
5283          later operand.  Note that multiple output operands are
5284          emitted in reverse order, so the conflicting ones are
5285          those with lower indices.  */
5286       if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5287         return 0;
5288
5289       for (i = 0; i <= opnum; i++)
5290         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5291           return 0;
5292
5293       return 1;
5294
5295     case RELOAD_FOR_OPERAND_ADDRESS:
5296       for (i = 0; i < reload_n_operands; i++)
5297         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5298           return 0;
5299
5300       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5301               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5302
5303     case RELOAD_FOR_OPADDR_ADDR:
5304       for (i = 0; i < reload_n_operands; i++)
5305         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5306           return 0;
5307
5308       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5309
5310     case RELOAD_FOR_OUTPUT:
5311       /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5312          outputs, or an operand address for this or an earlier output.
5313          Note that multiple output operands are emitted in reverse order,
5314          so the conflicting ones are those with higher indices.  */
5315       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5316         return 0;
5317
5318       for (i = 0; i < reload_n_operands; i++)
5319         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5320           return 0;
5321
5322       for (i = opnum; i < reload_n_operands; i++)
5323         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5324             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5325           return 0;
5326
5327       return 1;
5328
5329     case RELOAD_FOR_INSN:
5330       for (i = 0; i < reload_n_operands; i++)
5331         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5332             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5333           return 0;
5334
5335       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5336               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5337
5338     case RELOAD_FOR_OTHER_ADDRESS:
5339       return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5340
5341     default:
5342       gcc_unreachable ();
5343     }
5344 }
5345
5346 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5347    the number RELOADNUM, is still available in REGNO at the end of the insn.
5348
5349    We can assume that the reload reg was already tested for availability
5350    at the time it is needed, and we should not check this again,
5351    in case the reg has already been marked in use.  */
5352
5353 static int
5354 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5355 {
5356   int opnum = rld[reloadnum].opnum;
5357   enum reload_type type = rld[reloadnum].when_needed;
5358   int i;
5359
5360   /* See if there is a reload with the same type for this operand, using
5361      the same register. This case is not handled by the code below.  */
5362   for (i = reloadnum + 1; i < n_reloads; i++)
5363     {
5364       rtx reg;
5365       int nregs;
5366
5367       if (rld[i].opnum != opnum || rld[i].when_needed != type)
5368         continue;
5369       reg = rld[i].reg_rtx;
5370       if (reg == NULL_RTX)
5371         continue;
5372       nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5373       if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5374         return 0;
5375     }
5376
5377   switch (type)
5378     {
5379     case RELOAD_OTHER:
5380       /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5381          its value must reach the end.  */
5382       return 1;
5383
5384       /* If this use is for part of the insn,
5385          its value reaches if no subsequent part uses the same register.
5386          Just like the above function, don't try to do this with lots
5387          of fallthroughs.  */
5388
5389     case RELOAD_FOR_OTHER_ADDRESS:
5390       /* Here we check for everything else, since these don't conflict
5391          with anything else and everything comes later.  */
5392
5393       for (i = 0; i < reload_n_operands; i++)
5394         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5395             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5396             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5397             || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5398             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5399             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5400           return 0;
5401
5402       return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5403               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5404               && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5405               && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5406
5407     case RELOAD_FOR_INPUT_ADDRESS:
5408     case RELOAD_FOR_INPADDR_ADDRESS:
5409       /* Similar, except that we check only for this and subsequent inputs
5410          and the address of only subsequent inputs and we do not need
5411          to check for RELOAD_OTHER objects since they are known not to
5412          conflict.  */
5413
5414       for (i = opnum; i < reload_n_operands; i++)
5415         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5416           return 0;
5417
5418       /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5419          could be killed if the register is also used by reload with type
5420          RELOAD_FOR_INPUT_ADDRESS, so check it.  */
5421       if (type == RELOAD_FOR_INPADDR_ADDRESS
5422           && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5423         return 0;
5424
5425       for (i = opnum + 1; i < reload_n_operands; i++)
5426         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5427             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5428           return 0;
5429
5430       for (i = 0; i < reload_n_operands; i++)
5431         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5432             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5433             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5434           return 0;
5435
5436       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5437         return 0;
5438
5439       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5440               && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5441               && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5442
5443     case RELOAD_FOR_INPUT:
5444       /* Similar to input address, except we start at the next operand for
5445          both input and input address and we do not check for
5446          RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5447          would conflict.  */
5448
5449       for (i = opnum + 1; i < reload_n_operands; i++)
5450         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5451             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5452             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5453           return 0;
5454
5455       /* ... fall through ...  */
5456
5457     case RELOAD_FOR_OPERAND_ADDRESS:
5458       /* Check outputs and their addresses.  */
5459
5460       for (i = 0; i < reload_n_operands; i++)
5461         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5462             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5463             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5464           return 0;
5465
5466       return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5467
5468     case RELOAD_FOR_OPADDR_ADDR:
5469       for (i = 0; i < reload_n_operands; i++)
5470         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5471             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5472             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5473           return 0;
5474
5475       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5476               && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5477               && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5478
5479     case RELOAD_FOR_INSN:
5480       /* These conflict with other outputs with RELOAD_OTHER.  So
5481          we need only check for output addresses.  */
5482
5483       opnum = reload_n_operands;
5484
5485       /* ... fall through ...  */
5486
5487     case RELOAD_FOR_OUTPUT:
5488     case RELOAD_FOR_OUTPUT_ADDRESS:
5489     case RELOAD_FOR_OUTADDR_ADDRESS:
5490       /* We already know these can't conflict with a later output.  So the
5491          only thing to check are later output addresses.
5492          Note that multiple output operands are emitted in reverse order,
5493          so the conflicting ones are those with lower indices.  */
5494       for (i = 0; i < opnum; i++)
5495         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5496             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5497           return 0;
5498
5499       /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5500          could be killed if the register is also used by reload with type
5501          RELOAD_FOR_OUTPUT_ADDRESS, so check it.  */
5502       if (type == RELOAD_FOR_OUTADDR_ADDRESS
5503           && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5504         return 0;
5505
5506       return 1;
5507
5508     default:
5509       gcc_unreachable ();
5510     }
5511 }
5512
5513 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5514    every register in REG.  */
5515
5516 static bool
5517 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5518 {
5519   unsigned int i;
5520
5521   for (i = REGNO (reg); i < END_REGNO (reg); i++)
5522     if (!reload_reg_reaches_end_p (i, reloadnum))
5523       return false;
5524   return true;
5525 }
5526 \f
5527
5528 /*  Returns whether R1 and R2 are uniquely chained: the value of one
5529     is used by the other, and that value is not used by any other
5530     reload for this insn.  This is used to partially undo the decision
5531     made in find_reloads when in the case of multiple
5532     RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5533     RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5534     reloads.  This code tries to avoid the conflict created by that
5535     change.  It might be cleaner to explicitly keep track of which
5536     RELOAD_FOR_OPADDR_ADDR reload is associated with which
5537     RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5538     this after the fact. */
5539 static bool
5540 reloads_unique_chain_p (int r1, int r2)
5541 {
5542   int i;
5543
5544   /* We only check input reloads.  */
5545   if (! rld[r1].in || ! rld[r2].in)
5546     return false;
5547
5548   /* Avoid anything with output reloads.  */
5549   if (rld[r1].out || rld[r2].out)
5550     return false;
5551
5552   /* "chained" means one reload is a component of the other reload,
5553      not the same as the other reload.  */
5554   if (rld[r1].opnum != rld[r2].opnum
5555       || rtx_equal_p (rld[r1].in, rld[r2].in)
5556       || rld[r1].optional || rld[r2].optional
5557       || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5558             || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5559     return false;
5560
5561   for (i = 0; i < n_reloads; i ++)
5562     /* Look for input reloads that aren't our two */
5563     if (i != r1 && i != r2 && rld[i].in)
5564       {
5565         /* If our reload is mentioned at all, it isn't a simple chain.  */
5566         if (reg_mentioned_p (rld[r1].in, rld[i].in))
5567           return false;
5568       }
5569   return true;
5570 }
5571
5572 /* The recursive function change all occurrences of WHAT in *WHERE
5573    to REPL.  */
5574 static void
5575 substitute (rtx *where, const_rtx what, rtx repl)
5576 {
5577   const char *fmt;
5578   int i;
5579   enum rtx_code code;
5580
5581   if (*where == 0)
5582     return;
5583
5584   if (*where == what || rtx_equal_p (*where, what))
5585     {
5586       /* Record the location of the changed rtx.  */
5587       substitute_stack.safe_push (where);
5588       *where = repl;
5589       return;
5590     }
5591
5592   code = GET_CODE (*where);
5593   fmt = GET_RTX_FORMAT (code);
5594   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5595     {
5596       if (fmt[i] == 'E')
5597         {
5598           int j;
5599
5600           for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5601             substitute (&XVECEXP (*where, i, j), what, repl);
5602         }
5603       else if (fmt[i] == 'e')
5604         substitute (&XEXP (*where, i), what, repl);
5605     }
5606 }
5607
5608 /* The function returns TRUE if chain of reload R1 and R2 (in any
5609    order) can be evaluated without usage of intermediate register for
5610    the reload containing another reload.  It is important to see
5611    gen_reload to understand what the function is trying to do.  As an
5612    example, let us have reload chain
5613
5614       r2: const
5615       r1: <something> + const
5616
5617    and reload R2 got reload reg HR.  The function returns true if
5618    there is a correct insn HR = HR + <something>.  Otherwise,
5619    gen_reload will use intermediate register (and this is the reload
5620    reg for R1) to reload <something>.
5621
5622    We need this function to find a conflict for chain reloads.  In our
5623    example, if HR = HR + <something> is incorrect insn, then we cannot
5624    use HR as a reload register for R2.  If we do use it then we get a
5625    wrong code:
5626
5627       HR = const
5628       HR = <something>
5629       HR = HR + HR
5630
5631 */
5632 static bool
5633 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5634 {
5635   /* Assume other cases in gen_reload are not possible for
5636      chain reloads or do need an intermediate hard registers.  */
5637   bool result = true;
5638   int regno, n, code;
5639   rtx out, in, insn;
5640   rtx last = get_last_insn ();
5641
5642   /* Make r2 a component of r1.  */
5643   if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5644     {
5645       n = r1;
5646       r1 = r2;
5647       r2 = n;
5648     }
5649   gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5650   regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5651   gcc_assert (regno >= 0);
5652   out = gen_rtx_REG (rld[r1].mode, regno);
5653   in = rld[r1].in;
5654   substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5655
5656   /* If IN is a paradoxical SUBREG, remove it and try to put the
5657      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
5658   strip_paradoxical_subreg (&in, &out);
5659
5660   if (GET_CODE (in) == PLUS
5661       && (REG_P (XEXP (in, 0))
5662           || GET_CODE (XEXP (in, 0)) == SUBREG
5663           || MEM_P (XEXP (in, 0)))
5664       && (REG_P (XEXP (in, 1))
5665           || GET_CODE (XEXP (in, 1)) == SUBREG
5666           || CONSTANT_P (XEXP (in, 1))
5667           || MEM_P (XEXP (in, 1))))
5668     {
5669       insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5670       code = recog_memoized (insn);
5671       result = false;
5672
5673       if (code >= 0)
5674         {
5675           extract_insn (insn);
5676           /* We want constrain operands to treat this insn strictly in
5677              its validity determination, i.e., the way it would after
5678              reload has completed.  */
5679           result = constrain_operands (1);
5680         }
5681
5682       delete_insns_since (last);
5683     }
5684
5685   /* Restore the original value at each changed address within R1.  */
5686   while (!substitute_stack.is_empty ())
5687     {
5688       rtx *where = substitute_stack.pop ();
5689       *where = rld[r2].in;
5690     }
5691
5692   return result;
5693 }
5694
5695 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5696    Return 0 otherwise.
5697
5698    This function uses the same algorithm as reload_reg_free_p above.  */
5699
5700 static int
5701 reloads_conflict (int r1, int r2)
5702 {
5703   enum reload_type r1_type = rld[r1].when_needed;
5704   enum reload_type r2_type = rld[r2].when_needed;
5705   int r1_opnum = rld[r1].opnum;
5706   int r2_opnum = rld[r2].opnum;
5707
5708   /* RELOAD_OTHER conflicts with everything.  */
5709   if (r2_type == RELOAD_OTHER)
5710     return 1;
5711
5712   /* Otherwise, check conflicts differently for each type.  */
5713
5714   switch (r1_type)
5715     {
5716     case RELOAD_FOR_INPUT:
5717       return (r2_type == RELOAD_FOR_INSN
5718               || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5719               || r2_type == RELOAD_FOR_OPADDR_ADDR
5720               || r2_type == RELOAD_FOR_INPUT
5721               || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5722                    || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5723                   && r2_opnum > r1_opnum));
5724
5725     case RELOAD_FOR_INPUT_ADDRESS:
5726       return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5727               || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5728
5729     case RELOAD_FOR_INPADDR_ADDRESS:
5730       return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5731               || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5732
5733     case RELOAD_FOR_OUTPUT_ADDRESS:
5734       return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5735               || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5736
5737     case RELOAD_FOR_OUTADDR_ADDRESS:
5738       return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5739               || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5740
5741     case RELOAD_FOR_OPERAND_ADDRESS:
5742       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5743               || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5744                   && (!reloads_unique_chain_p (r1, r2)
5745                       || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5746
5747     case RELOAD_FOR_OPADDR_ADDR:
5748       return (r2_type == RELOAD_FOR_INPUT
5749               || r2_type == RELOAD_FOR_OPADDR_ADDR);
5750
5751     case RELOAD_FOR_OUTPUT:
5752       return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5753               || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5754                    || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5755                   && r2_opnum >= r1_opnum));
5756
5757     case RELOAD_FOR_INSN:
5758       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5759               || r2_type == RELOAD_FOR_INSN
5760               || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5761
5762     case RELOAD_FOR_OTHER_ADDRESS:
5763       return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5764
5765     case RELOAD_OTHER:
5766       return 1;
5767
5768     default:
5769       gcc_unreachable ();
5770     }
5771 }
5772 \f
5773 /* Indexed by reload number, 1 if incoming value
5774    inherited from previous insns.  */
5775 static char reload_inherited[MAX_RELOADS];
5776
5777 /* For an inherited reload, this is the insn the reload was inherited from,
5778    if we know it.  Otherwise, this is 0.  */
5779 static rtx reload_inheritance_insn[MAX_RELOADS];
5780
5781 /* If nonzero, this is a place to get the value of the reload,
5782    rather than using reload_in.  */
5783 static rtx reload_override_in[MAX_RELOADS];
5784
5785 /* For each reload, the hard register number of the register used,
5786    or -1 if we did not need a register for this reload.  */
5787 static int reload_spill_index[MAX_RELOADS];
5788
5789 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode.  */
5790 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5791
5792 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode.  */
5793 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5794
5795 /* Subroutine of free_for_value_p, used to check a single register.
5796    START_REGNO is the starting regno of the full reload register
5797    (possibly comprising multiple hard registers) that we are considering.  */
5798
5799 static int
5800 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5801                              enum reload_type type, rtx value, rtx out,
5802                              int reloadnum, int ignore_address_reloads)
5803 {
5804   int time1;
5805   /* Set if we see an input reload that must not share its reload register
5806      with any new earlyclobber, but might otherwise share the reload
5807      register with an output or input-output reload.  */
5808   int check_earlyclobber = 0;
5809   int i;
5810   int copy = 0;
5811
5812   if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5813     return 0;
5814
5815   if (out == const0_rtx)
5816     {
5817       copy = 1;
5818       out = NULL_RTX;
5819     }
5820
5821   /* We use some pseudo 'time' value to check if the lifetimes of the
5822      new register use would overlap with the one of a previous reload
5823      that is not read-only or uses a different value.
5824      The 'time' used doesn't have to be linear in any shape or form, just
5825      monotonic.
5826      Some reload types use different 'buckets' for each operand.
5827      So there are MAX_RECOG_OPERANDS different time values for each
5828      such reload type.
5829      We compute TIME1 as the time when the register for the prospective
5830      new reload ceases to be live, and TIME2 for each existing
5831      reload as the time when that the reload register of that reload
5832      becomes live.
5833      Where there is little to be gained by exact lifetime calculations,
5834      we just make conservative assumptions, i.e. a longer lifetime;
5835      this is done in the 'default:' cases.  */
5836   switch (type)
5837     {
5838     case RELOAD_FOR_OTHER_ADDRESS:
5839       /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads.  */
5840       time1 = copy ? 0 : 1;
5841       break;
5842     case RELOAD_OTHER:
5843       time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5844       break;
5845       /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5846          RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT.  By adding 0 / 1 / 2 ,
5847          respectively, to the time values for these, we get distinct time
5848          values.  To get distinct time values for each operand, we have to
5849          multiply opnum by at least three.  We round that up to four because
5850          multiply by four is often cheaper.  */
5851     case RELOAD_FOR_INPADDR_ADDRESS:
5852       time1 = opnum * 4 + 2;
5853       break;
5854     case RELOAD_FOR_INPUT_ADDRESS:
5855       time1 = opnum * 4 + 3;
5856       break;
5857     case RELOAD_FOR_INPUT:
5858       /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5859          executes (inclusive).  */
5860       time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5861       break;
5862     case RELOAD_FOR_OPADDR_ADDR:
5863       /* opnum * 4 + 4
5864          <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5865       time1 = MAX_RECOG_OPERANDS * 4 + 1;
5866       break;
5867     case RELOAD_FOR_OPERAND_ADDRESS:
5868       /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5869          is executed.  */
5870       time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5871       break;
5872     case RELOAD_FOR_OUTADDR_ADDRESS:
5873       time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5874       break;
5875     case RELOAD_FOR_OUTPUT_ADDRESS:
5876       time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5877       break;
5878     default:
5879       time1 = MAX_RECOG_OPERANDS * 5 + 5;
5880     }
5881
5882   for (i = 0; i < n_reloads; i++)
5883     {
5884       rtx reg = rld[i].reg_rtx;
5885       if (reg && REG_P (reg)
5886           && ((unsigned) regno - true_regnum (reg)
5887               <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5888           && i != reloadnum)
5889         {
5890           rtx other_input = rld[i].in;
5891
5892           /* If the other reload loads the same input value, that
5893              will not cause a conflict only if it's loading it into
5894              the same register.  */
5895           if (true_regnum (reg) != start_regno)
5896             other_input = NULL_RTX;
5897           if (! other_input || ! rtx_equal_p (other_input, value)
5898               || rld[i].out || out)
5899             {
5900               int time2;
5901               switch (rld[i].when_needed)
5902                 {
5903                 case RELOAD_FOR_OTHER_ADDRESS:
5904                   time2 = 0;
5905                   break;
5906                 case RELOAD_FOR_INPADDR_ADDRESS:
5907                   /* find_reloads makes sure that a
5908                      RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5909                      by at most one - the first -
5910                      RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS .  If the
5911                      address reload is inherited, the address address reload
5912                      goes away, so we can ignore this conflict.  */
5913                   if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5914                       && ignore_address_reloads
5915                       /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5916                          Then the address address is still needed to store
5917                          back the new address.  */
5918                       && ! rld[reloadnum].out)
5919                     continue;
5920                   /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5921                      RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5922                      reloads go away.  */
5923                   if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5924                       && ignore_address_reloads
5925                       /* Unless we are reloading an auto_inc expression.  */
5926                       && ! rld[reloadnum].out)
5927                     continue;
5928                   time2 = rld[i].opnum * 4 + 2;
5929                   break;
5930                 case RELOAD_FOR_INPUT_ADDRESS:
5931                   if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5932                       && ignore_address_reloads
5933                       && ! rld[reloadnum].out)
5934                     continue;
5935                   time2 = rld[i].opnum * 4 + 3;
5936                   break;
5937                 case RELOAD_FOR_INPUT:
5938                   time2 = rld[i].opnum * 4 + 4;
5939                   check_earlyclobber = 1;
5940                   break;
5941                   /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5942                      == MAX_RECOG_OPERAND * 4  */
5943                 case RELOAD_FOR_OPADDR_ADDR:
5944                   if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5945                       && ignore_address_reloads
5946                       && ! rld[reloadnum].out)
5947                     continue;
5948                   time2 = MAX_RECOG_OPERANDS * 4 + 1;
5949                   break;
5950                 case RELOAD_FOR_OPERAND_ADDRESS:
5951                   time2 = MAX_RECOG_OPERANDS * 4 + 2;
5952                   check_earlyclobber = 1;
5953                   break;
5954                 case RELOAD_FOR_INSN:
5955                   time2 = MAX_RECOG_OPERANDS * 4 + 3;
5956                   break;
5957                 case RELOAD_FOR_OUTPUT:
5958                   /* All RELOAD_FOR_OUTPUT reloads become live just after the
5959                      instruction is executed.  */
5960                   time2 = MAX_RECOG_OPERANDS * 4 + 4;
5961                   break;
5962                   /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5963                      the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5964                      value.  */
5965                 case RELOAD_FOR_OUTADDR_ADDRESS:
5966                   if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5967                       && ignore_address_reloads
5968                       && ! rld[reloadnum].out)
5969                     continue;
5970                   time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5971                   break;
5972                 case RELOAD_FOR_OUTPUT_ADDRESS:
5973                   time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5974                   break;
5975                 case RELOAD_OTHER:
5976                   /* If there is no conflict in the input part, handle this
5977                      like an output reload.  */
5978                   if (! rld[i].in || rtx_equal_p (other_input, value))
5979                     {
5980                       time2 = MAX_RECOG_OPERANDS * 4 + 4;
5981                       /* Earlyclobbered outputs must conflict with inputs.  */
5982                       if (earlyclobber_operand_p (rld[i].out))
5983                         time2 = MAX_RECOG_OPERANDS * 4 + 3;
5984
5985                       break;
5986                     }
5987                   time2 = 1;
5988                   /* RELOAD_OTHER might be live beyond instruction execution,
5989                      but this is not obvious when we set time2 = 1.  So check
5990                      here if there might be a problem with the new reload
5991                      clobbering the register used by the RELOAD_OTHER.  */
5992                   if (out)
5993                     return 0;
5994                   break;
5995                 default:
5996                   return 0;
5997                 }
5998               if ((time1 >= time2
5999                    && (! rld[i].in || rld[i].out
6000                        || ! rtx_equal_p (other_input, value)))
6001                   || (out && rld[reloadnum].out_reg
6002                       && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6003                 return 0;
6004             }
6005         }
6006     }
6007
6008   /* Earlyclobbered outputs must conflict with inputs.  */
6009   if (check_earlyclobber && out && earlyclobber_operand_p (out))
6010     return 0;
6011
6012   return 1;
6013 }
6014
6015 /* Return 1 if the value in reload reg REGNO, as used by a reload
6016    needed for the part of the insn specified by OPNUM and TYPE,
6017    may be used to load VALUE into it.
6018
6019    MODE is the mode in which the register is used, this is needed to
6020    determine how many hard regs to test.
6021
6022    Other read-only reloads with the same value do not conflict
6023    unless OUT is nonzero and these other reloads have to live while
6024    output reloads live.
6025    If OUT is CONST0_RTX, this is a special case: it means that the
6026    test should not be for using register REGNO as reload register, but
6027    for copying from register REGNO into the reload register.
6028
6029    RELOADNUM is the number of the reload we want to load this value for;
6030    a reload does not conflict with itself.
6031
6032    When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6033    reloads that load an address for the very reload we are considering.
6034
6035    The caller has to make sure that there is no conflict with the return
6036    register.  */
6037
6038 static int
6039 free_for_value_p (int regno, enum machine_mode mode, int opnum,
6040                   enum reload_type type, rtx value, rtx out, int reloadnum,
6041                   int ignore_address_reloads)
6042 {
6043   int nregs = hard_regno_nregs[regno][mode];
6044   while (nregs-- > 0)
6045     if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6046                                        value, out, reloadnum,
6047                                        ignore_address_reloads))
6048       return 0;
6049   return 1;
6050 }
6051
6052 /* Return nonzero if the rtx X is invariant over the current function.  */
6053 /* ??? Actually, the places where we use this expect exactly what is
6054    tested here, and not everything that is function invariant.  In
6055    particular, the frame pointer and arg pointer are special cased;
6056    pic_offset_table_rtx is not, and we must not spill these things to
6057    memory.  */
6058
6059 int
6060 function_invariant_p (const_rtx x)
6061 {
6062   if (CONSTANT_P (x))
6063     return 1;
6064   if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6065     return 1;
6066   if (GET_CODE (x) == PLUS
6067       && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6068       && GET_CODE (XEXP (x, 1)) == CONST_INT)
6069     return 1;
6070   return 0;
6071 }
6072
6073 /* Determine whether the reload reg X overlaps any rtx'es used for
6074    overriding inheritance.  Return nonzero if so.  */
6075
6076 static int
6077 conflicts_with_override (rtx x)
6078 {
6079   int i;
6080   for (i = 0; i < n_reloads; i++)
6081     if (reload_override_in[i]
6082         && reg_overlap_mentioned_p (x, reload_override_in[i]))
6083       return 1;
6084   return 0;
6085 }
6086 \f
6087 /* Give an error message saying we failed to find a reload for INSN,
6088    and clear out reload R.  */
6089 static void
6090 failed_reload (rtx insn, int r)
6091 {
6092   if (asm_noperands (PATTERN (insn)) < 0)
6093     /* It's the compiler's fault.  */
6094     fatal_insn ("could not find a spill register", insn);
6095
6096   /* It's the user's fault; the operand's mode and constraint
6097      don't match.  Disable this reload so we don't crash in final.  */
6098   error_for_asm (insn,
6099                  "%<asm%> operand constraint incompatible with operand size");
6100   rld[r].in = 0;
6101   rld[r].out = 0;
6102   rld[r].reg_rtx = 0;
6103   rld[r].optional = 1;
6104   rld[r].secondary_p = 1;
6105 }
6106
6107 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6108    for reload R.  If it's valid, get an rtx for it.  Return nonzero if
6109    successful.  */
6110 static int
6111 set_reload_reg (int i, int r)
6112 {
6113   /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6114      parameter.  */
6115   int regno ATTRIBUTE_UNUSED;
6116   rtx reg = spill_reg_rtx[i];
6117
6118   if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6119     spill_reg_rtx[i] = reg
6120       = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6121
6122   regno = true_regnum (reg);
6123
6124   /* Detect when the reload reg can't hold the reload mode.
6125      This used to be one `if', but Sequent compiler can't handle that.  */
6126   if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6127     {
6128       enum machine_mode test_mode = VOIDmode;
6129       if (rld[r].in)
6130         test_mode = GET_MODE (rld[r].in);
6131       /* If rld[r].in has VOIDmode, it means we will load it
6132          in whatever mode the reload reg has: to wit, rld[r].mode.
6133          We have already tested that for validity.  */
6134       /* Aside from that, we need to test that the expressions
6135          to reload from or into have modes which are valid for this
6136          reload register.  Otherwise the reload insns would be invalid.  */
6137       if (! (rld[r].in != 0 && test_mode != VOIDmode
6138              && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6139         if (! (rld[r].out != 0
6140                && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6141           {
6142             /* The reg is OK.  */
6143             last_spill_reg = i;
6144
6145             /* Mark as in use for this insn the reload regs we use
6146                for this.  */
6147             mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6148                                     rld[r].when_needed, rld[r].mode);
6149
6150             rld[r].reg_rtx = reg;
6151             reload_spill_index[r] = spill_regs[i];
6152             return 1;
6153           }
6154     }
6155   return 0;
6156 }
6157
6158 /* Find a spill register to use as a reload register for reload R.
6159    LAST_RELOAD is nonzero if this is the last reload for the insn being
6160    processed.
6161
6162    Set rld[R].reg_rtx to the register allocated.
6163
6164    We return 1 if successful, or 0 if we couldn't find a spill reg and
6165    we didn't change anything.  */
6166
6167 static int
6168 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6169                      int last_reload)
6170 {
6171   int i, pass, count;
6172
6173   /* If we put this reload ahead, thinking it is a group,
6174      then insist on finding a group.  Otherwise we can grab a
6175      reg that some other reload needs.
6176      (That can happen when we have a 68000 DATA_OR_FP_REG
6177      which is a group of data regs or one fp reg.)
6178      We need not be so restrictive if there are no more reloads
6179      for this insn.
6180
6181      ??? Really it would be nicer to have smarter handling
6182      for that kind of reg class, where a problem like this is normal.
6183      Perhaps those classes should be avoided for reloading
6184      by use of more alternatives.  */
6185
6186   int force_group = rld[r].nregs > 1 && ! last_reload;
6187
6188   /* If we want a single register and haven't yet found one,
6189      take any reg in the right class and not in use.
6190      If we want a consecutive group, here is where we look for it.
6191
6192      We use three passes so we can first look for reload regs to
6193      reuse, which are already in use for other reloads in this insn,
6194      and only then use additional registers which are not "bad", then
6195      finally any register.
6196
6197      I think that maximizing reuse is needed to make sure we don't
6198      run out of reload regs.  Suppose we have three reloads, and
6199      reloads A and B can share regs.  These need two regs.
6200      Suppose A and B are given different regs.
6201      That leaves none for C.  */
6202   for (pass = 0; pass < 3; pass++)
6203     {
6204       /* I is the index in spill_regs.
6205          We advance it round-robin between insns to use all spill regs
6206          equally, so that inherited reloads have a chance
6207          of leapfrogging each other.  */
6208
6209       i = last_spill_reg;
6210
6211       for (count = 0; count < n_spills; count++)
6212         {
6213           int rclass = (int) rld[r].rclass;
6214           int regnum;
6215
6216           i++;
6217           if (i >= n_spills)
6218             i -= n_spills;
6219           regnum = spill_regs[i];
6220
6221           if ((reload_reg_free_p (regnum, rld[r].opnum,
6222                                   rld[r].when_needed)
6223                || (rld[r].in
6224                    /* We check reload_reg_used to make sure we
6225                       don't clobber the return register.  */
6226                    && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6227                    && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6228                                         rld[r].when_needed, rld[r].in,
6229                                         rld[r].out, r, 1)))
6230               && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6231               && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6232               /* Look first for regs to share, then for unshared.  But
6233                  don't share regs used for inherited reloads; they are
6234                  the ones we want to preserve.  */
6235               && (pass
6236                   || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6237                                          regnum)
6238                       && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6239                                               regnum))))
6240             {
6241               int nr = hard_regno_nregs[regnum][rld[r].mode];
6242
6243               /* During the second pass we want to avoid reload registers
6244                  which are "bad" for this reload.  */
6245               if (pass == 1
6246                   && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6247                 continue;
6248
6249               /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6250                  (on 68000) got us two FP regs.  If NR is 1,
6251                  we would reject both of them.  */
6252               if (force_group)
6253                 nr = rld[r].nregs;
6254               /* If we need only one reg, we have already won.  */
6255               if (nr == 1)
6256                 {
6257                   /* But reject a single reg if we demand a group.  */
6258                   if (force_group)
6259                     continue;
6260                   break;
6261                 }
6262               /* Otherwise check that as many consecutive regs as we need
6263                  are available here.  */
6264               while (nr > 1)
6265                 {
6266                   int regno = regnum + nr - 1;
6267                   if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6268                         && spill_reg_order[regno] >= 0
6269                         && reload_reg_free_p (regno, rld[r].opnum,
6270                                               rld[r].when_needed)))
6271                     break;
6272                   nr--;
6273                 }
6274               if (nr == 1)
6275                 break;
6276             }
6277         }
6278
6279       /* If we found something on the current pass, omit later passes.  */
6280       if (count < n_spills)
6281         break;
6282     }
6283
6284   /* We should have found a spill register by now.  */
6285   if (count >= n_spills)
6286     return 0;
6287
6288   /* I is the index in SPILL_REG_RTX of the reload register we are to
6289      allocate.  Get an rtx for it and find its register number.  */
6290
6291   return set_reload_reg (i, r);
6292 }
6293 \f
6294 /* Initialize all the tables needed to allocate reload registers.
6295    CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6296    is the array we use to restore the reg_rtx field for every reload.  */
6297
6298 static void
6299 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6300 {
6301   int i;
6302
6303   for (i = 0; i < n_reloads; i++)
6304     rld[i].reg_rtx = save_reload_reg_rtx[i];
6305
6306   memset (reload_inherited, 0, MAX_RELOADS);
6307   memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6308   memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6309
6310   CLEAR_HARD_REG_SET (reload_reg_used);
6311   CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6312   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6313   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6314   CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6315   CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6316
6317   CLEAR_HARD_REG_SET (reg_used_in_insn);
6318   {
6319     HARD_REG_SET tmp;
6320     REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6321     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6322     REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6323     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6324     compute_use_by_pseudos (&reg_used_in_insn, &chain->live_throughout);
6325     compute_use_by_pseudos (&reg_used_in_insn, &chain->dead_or_set);
6326   }
6327
6328   for (i = 0; i < reload_n_operands; i++)
6329     {
6330       CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6331       CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6332       CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6333       CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6334       CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6335       CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6336     }
6337
6338   COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6339
6340   CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6341
6342   for (i = 0; i < n_reloads; i++)
6343     /* If we have already decided to use a certain register,
6344        don't use it in another way.  */
6345     if (rld[i].reg_rtx)
6346       mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6347                               rld[i].when_needed, rld[i].mode);
6348 }
6349
6350 #ifdef SECONDARY_MEMORY_NEEDED
6351 /* If X is not a subreg, return it unmodified.  If it is a subreg,
6352    look up whether we made a replacement for the SUBREG_REG.  Return
6353    either the replacement or the SUBREG_REG.  */
6354
6355 static rtx
6356 replaced_subreg (rtx x)
6357 {
6358   if (GET_CODE (x) == SUBREG)
6359     return find_replacement (&SUBREG_REG (x));
6360   return x;
6361 }
6362 #endif
6363
6364 /* Assign hard reg targets for the pseudo-registers we must reload
6365    into hard regs for this insn.
6366    Also output the instructions to copy them in and out of the hard regs.
6367
6368    For machines with register classes, we are responsible for
6369    finding a reload reg in the proper class.  */
6370
6371 static void
6372 choose_reload_regs (struct insn_chain *chain)
6373 {
6374   rtx insn = chain->insn;
6375   int i, j;
6376   unsigned int max_group_size = 1;
6377   enum reg_class group_class = NO_REGS;
6378   int pass, win, inheritance;
6379
6380   rtx save_reload_reg_rtx[MAX_RELOADS];
6381
6382   /* In order to be certain of getting the registers we need,
6383      we must sort the reloads into order of increasing register class.
6384      Then our grabbing of reload registers will parallel the process
6385      that provided the reload registers.
6386
6387      Also note whether any of the reloads wants a consecutive group of regs.
6388      If so, record the maximum size of the group desired and what
6389      register class contains all the groups needed by this insn.  */
6390
6391   for (j = 0; j < n_reloads; j++)
6392     {
6393       reload_order[j] = j;
6394       if (rld[j].reg_rtx != NULL_RTX)
6395         {
6396           gcc_assert (REG_P (rld[j].reg_rtx)
6397                       && HARD_REGISTER_P (rld[j].reg_rtx));
6398           reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6399         }
6400       else
6401         reload_spill_index[j] = -1;
6402
6403       if (rld[j].nregs > 1)
6404         {
6405           max_group_size = MAX (rld[j].nregs, max_group_size);
6406           group_class
6407             = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6408         }
6409
6410       save_reload_reg_rtx[j] = rld[j].reg_rtx;
6411     }
6412
6413   if (n_reloads > 1)
6414     qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6415
6416   /* If -O, try first with inheritance, then turning it off.
6417      If not -O, don't do inheritance.
6418      Using inheritance when not optimizing leads to paradoxes
6419      with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6420      because one side of the comparison might be inherited.  */
6421   win = 0;
6422   for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6423     {
6424       choose_reload_regs_init (chain, save_reload_reg_rtx);
6425
6426       /* Process the reloads in order of preference just found.
6427          Beyond this point, subregs can be found in reload_reg_rtx.
6428
6429          This used to look for an existing reloaded home for all of the
6430          reloads, and only then perform any new reloads.  But that could lose
6431          if the reloads were done out of reg-class order because a later
6432          reload with a looser constraint might have an old home in a register
6433          needed by an earlier reload with a tighter constraint.
6434
6435          To solve this, we make two passes over the reloads, in the order
6436          described above.  In the first pass we try to inherit a reload
6437          from a previous insn.  If there is a later reload that needs a
6438          class that is a proper subset of the class being processed, we must
6439          also allocate a spill register during the first pass.
6440
6441          Then make a second pass over the reloads to allocate any reloads
6442          that haven't been given registers yet.  */
6443
6444       for (j = 0; j < n_reloads; j++)
6445         {
6446           int r = reload_order[j];
6447           rtx search_equiv = NULL_RTX;
6448
6449           /* Ignore reloads that got marked inoperative.  */
6450           if (rld[r].out == 0 && rld[r].in == 0
6451               && ! rld[r].secondary_p)
6452             continue;
6453
6454           /* If find_reloads chose to use reload_in or reload_out as a reload
6455              register, we don't need to chose one.  Otherwise, try even if it
6456              found one since we might save an insn if we find the value lying
6457              around.
6458              Try also when reload_in is a pseudo without a hard reg.  */
6459           if (rld[r].in != 0 && rld[r].reg_rtx != 0
6460               && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6461                   || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6462                       && !MEM_P (rld[r].in)
6463                       && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6464             continue;
6465
6466 #if 0 /* No longer needed for correct operation.
6467          It might give better code, or might not; worth an experiment?  */
6468           /* If this is an optional reload, we can't inherit from earlier insns
6469              until we are sure that any non-optional reloads have been allocated.
6470              The following code takes advantage of the fact that optional reloads
6471              are at the end of reload_order.  */
6472           if (rld[r].optional != 0)
6473             for (i = 0; i < j; i++)
6474               if ((rld[reload_order[i]].out != 0
6475                    || rld[reload_order[i]].in != 0
6476                    || rld[reload_order[i]].secondary_p)
6477                   && ! rld[reload_order[i]].optional
6478                   && rld[reload_order[i]].reg_rtx == 0)
6479                 allocate_reload_reg (chain, reload_order[i], 0);
6480 #endif
6481
6482           /* First see if this pseudo is already available as reloaded
6483              for a previous insn.  We cannot try to inherit for reloads
6484              that are smaller than the maximum number of registers needed
6485              for groups unless the register we would allocate cannot be used
6486              for the groups.
6487
6488              We could check here to see if this is a secondary reload for
6489              an object that is already in a register of the desired class.
6490              This would avoid the need for the secondary reload register.
6491              But this is complex because we can't easily determine what
6492              objects might want to be loaded via this reload.  So let a
6493              register be allocated here.  In `emit_reload_insns' we suppress
6494              one of the loads in the case described above.  */
6495
6496           if (inheritance)
6497             {
6498               int byte = 0;
6499               int regno = -1;
6500               enum machine_mode mode = VOIDmode;
6501
6502               if (rld[r].in == 0)
6503                 ;
6504               else if (REG_P (rld[r].in))
6505                 {
6506                   regno = REGNO (rld[r].in);
6507                   mode = GET_MODE (rld[r].in);
6508                 }
6509               else if (REG_P (rld[r].in_reg))
6510                 {
6511                   regno = REGNO (rld[r].in_reg);
6512                   mode = GET_MODE (rld[r].in_reg);
6513                 }
6514               else if (GET_CODE (rld[r].in_reg) == SUBREG
6515                        && REG_P (SUBREG_REG (rld[r].in_reg)))
6516                 {
6517                   regno = REGNO (SUBREG_REG (rld[r].in_reg));
6518                   if (regno < FIRST_PSEUDO_REGISTER)
6519                     regno = subreg_regno (rld[r].in_reg);
6520                   else
6521                     byte = SUBREG_BYTE (rld[r].in_reg);
6522                   mode = GET_MODE (rld[r].in_reg);
6523                 }
6524 #ifdef AUTO_INC_DEC
6525               else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6526                        && REG_P (XEXP (rld[r].in_reg, 0)))
6527                 {
6528                   regno = REGNO (XEXP (rld[r].in_reg, 0));
6529                   mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6530                   rld[r].out = rld[r].in;
6531                 }
6532 #endif
6533 #if 0
6534               /* This won't work, since REGNO can be a pseudo reg number.
6535                  Also, it takes much more hair to keep track of all the things
6536                  that can invalidate an inherited reload of part of a pseudoreg.  */
6537               else if (GET_CODE (rld[r].in) == SUBREG
6538                        && REG_P (SUBREG_REG (rld[r].in)))
6539                 regno = subreg_regno (rld[r].in);
6540 #endif
6541
6542               if (regno >= 0
6543                   && reg_last_reload_reg[regno] != 0
6544                   && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6545                       >= GET_MODE_SIZE (mode) + byte)
6546 #ifdef CANNOT_CHANGE_MODE_CLASS
6547                   /* Verify that the register it's in can be used in
6548                      mode MODE.  */
6549                   && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6550                                                 GET_MODE (reg_last_reload_reg[regno]),
6551                                                 mode)
6552 #endif
6553                   )
6554                 {
6555                   enum reg_class rclass = rld[r].rclass, last_class;
6556                   rtx last_reg = reg_last_reload_reg[regno];
6557
6558                   i = REGNO (last_reg);
6559                   i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6560                   last_class = REGNO_REG_CLASS (i);
6561
6562                   if (reg_reloaded_contents[i] == regno
6563                       && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6564                       && HARD_REGNO_MODE_OK (i, rld[r].mode)
6565                       && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6566                           /* Even if we can't use this register as a reload
6567                              register, we might use it for reload_override_in,
6568                              if copying it to the desired class is cheap
6569                              enough.  */
6570                           || ((register_move_cost (mode, last_class, rclass)
6571                                < memory_move_cost (mode, rclass, true))
6572                               && (secondary_reload_class (1, rclass, mode,
6573                                                           last_reg)
6574                                   == NO_REGS)
6575 #ifdef SECONDARY_MEMORY_NEEDED
6576                               && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6577                                                             mode)
6578 #endif
6579                               ))
6580
6581                       && (rld[r].nregs == max_group_size
6582                           || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6583                                                   i))
6584                       && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6585                                            rld[r].when_needed, rld[r].in,
6586                                            const0_rtx, r, 1))
6587                     {
6588                       /* If a group is needed, verify that all the subsequent
6589                          registers still have their values intact.  */
6590                       int nr = hard_regno_nregs[i][rld[r].mode];
6591                       int k;
6592
6593                       for (k = 1; k < nr; k++)
6594                         if (reg_reloaded_contents[i + k] != regno
6595                             || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6596                           break;
6597
6598                       if (k == nr)
6599                         {
6600                           int i1;
6601                           int bad_for_class;
6602
6603                           last_reg = (GET_MODE (last_reg) == mode
6604                                       ? last_reg : gen_rtx_REG (mode, i));
6605
6606                           bad_for_class = 0;
6607                           for (k = 0; k < nr; k++)
6608                             bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6609                                                                   i+k);
6610
6611                           /* We found a register that contains the
6612                              value we need.  If this register is the
6613                              same as an `earlyclobber' operand of the
6614                              current insn, just mark it as a place to
6615                              reload from since we can't use it as the
6616                              reload register itself.  */
6617
6618                           for (i1 = 0; i1 < n_earlyclobbers; i1++)
6619                             if (reg_overlap_mentioned_for_reload_p
6620                                 (reg_last_reload_reg[regno],
6621                                  reload_earlyclobbers[i1]))
6622                               break;
6623
6624                           if (i1 != n_earlyclobbers
6625                               || ! (free_for_value_p (i, rld[r].mode,
6626                                                       rld[r].opnum,
6627                                                       rld[r].when_needed, rld[r].in,
6628                                                       rld[r].out, r, 1))
6629                               /* Don't use it if we'd clobber a pseudo reg.  */
6630                               || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6631                                   && rld[r].out
6632                                   && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6633                               /* Don't clobber the frame pointer.  */
6634                               || (i == HARD_FRAME_POINTER_REGNUM
6635                                   && frame_pointer_needed
6636                                   && rld[r].out)
6637                               /* Don't really use the inherited spill reg
6638                                  if we need it wider than we've got it.  */
6639                               || (GET_MODE_SIZE (rld[r].mode)
6640                                   > GET_MODE_SIZE (mode))
6641                               || bad_for_class
6642
6643                               /* If find_reloads chose reload_out as reload
6644                                  register, stay with it - that leaves the
6645                                  inherited register for subsequent reloads.  */
6646                               || (rld[r].out && rld[r].reg_rtx
6647                                   && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6648                             {
6649                               if (! rld[r].optional)
6650                                 {
6651                                   reload_override_in[r] = last_reg;
6652                                   reload_inheritance_insn[r]
6653                                     = reg_reloaded_insn[i];
6654                                 }
6655                             }
6656                           else
6657                             {
6658                               int k;
6659                               /* We can use this as a reload reg.  */
6660                               /* Mark the register as in use for this part of
6661                                  the insn.  */
6662                               mark_reload_reg_in_use (i,
6663                                                       rld[r].opnum,
6664                                                       rld[r].when_needed,
6665                                                       rld[r].mode);
6666                               rld[r].reg_rtx = last_reg;
6667                               reload_inherited[r] = 1;
6668                               reload_inheritance_insn[r]
6669                                 = reg_reloaded_insn[i];
6670                               reload_spill_index[r] = i;
6671                               for (k = 0; k < nr; k++)
6672                                 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6673                                                   i + k);
6674                             }
6675                         }
6676                     }
6677                 }
6678             }
6679
6680           /* Here's another way to see if the value is already lying around.  */
6681           if (inheritance
6682               && rld[r].in != 0
6683               && ! reload_inherited[r]
6684               && rld[r].out == 0
6685               && (CONSTANT_P (rld[r].in)
6686                   || GET_CODE (rld[r].in) == PLUS
6687                   || REG_P (rld[r].in)
6688                   || MEM_P (rld[r].in))
6689               && (rld[r].nregs == max_group_size
6690                   || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6691             search_equiv = rld[r].in;
6692
6693           if (search_equiv)
6694             {
6695               rtx equiv
6696                 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6697                                   -1, NULL, 0, rld[r].mode);
6698               int regno = 0;
6699
6700               if (equiv != 0)
6701                 {
6702                   if (REG_P (equiv))
6703                     regno = REGNO (equiv);
6704                   else
6705                     {
6706                       /* This must be a SUBREG of a hard register.
6707                          Make a new REG since this might be used in an
6708                          address and not all machines support SUBREGs
6709                          there.  */
6710                       gcc_assert (GET_CODE (equiv) == SUBREG);
6711                       regno = subreg_regno (equiv);
6712                       equiv = gen_rtx_REG (rld[r].mode, regno);
6713                       /* If we choose EQUIV as the reload register, but the
6714                          loop below decides to cancel the inheritance, we'll
6715                          end up reloading EQUIV in rld[r].mode, not the mode
6716                          it had originally.  That isn't safe when EQUIV isn't
6717                          available as a spill register since its value might
6718                          still be live at this point.  */
6719                       for (i = regno; i < regno + (int) rld[r].nregs; i++)
6720                         if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6721                           equiv = 0;
6722                     }
6723                 }
6724
6725               /* If we found a spill reg, reject it unless it is free
6726                  and of the desired class.  */
6727               if (equiv != 0)
6728                 {
6729                   int regs_used = 0;
6730                   int bad_for_class = 0;
6731                   int max_regno = regno + rld[r].nregs;
6732
6733                   for (i = regno; i < max_regno; i++)
6734                     {
6735                       regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6736                                                       i);
6737                       bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6738                                                            i);
6739                     }
6740
6741                   if ((regs_used
6742                        && ! free_for_value_p (regno, rld[r].mode,
6743                                               rld[r].opnum, rld[r].when_needed,
6744                                               rld[r].in, rld[r].out, r, 1))
6745                       || bad_for_class)
6746                     equiv = 0;
6747                 }
6748
6749               if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6750                 equiv = 0;
6751
6752               /* We found a register that contains the value we need.
6753                  If this register is the same as an `earlyclobber' operand
6754                  of the current insn, just mark it as a place to reload from
6755                  since we can't use it as the reload register itself.  */
6756
6757               if (equiv != 0)
6758                 for (i = 0; i < n_earlyclobbers; i++)
6759                   if (reg_overlap_mentioned_for_reload_p (equiv,
6760                                                           reload_earlyclobbers[i]))
6761                     {
6762                       if (! rld[r].optional)
6763                         reload_override_in[r] = equiv;
6764                       equiv = 0;
6765                       break;
6766                     }
6767
6768               /* If the equiv register we have found is explicitly clobbered
6769                  in the current insn, it depends on the reload type if we
6770                  can use it, use it for reload_override_in, or not at all.
6771                  In particular, we then can't use EQUIV for a
6772                  RELOAD_FOR_OUTPUT_ADDRESS reload.  */
6773
6774               if (equiv != 0)
6775                 {
6776                   if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6777                     switch (rld[r].when_needed)
6778                       {
6779                       case RELOAD_FOR_OTHER_ADDRESS:
6780                       case RELOAD_FOR_INPADDR_ADDRESS:
6781                       case RELOAD_FOR_INPUT_ADDRESS:
6782                       case RELOAD_FOR_OPADDR_ADDR:
6783                         break;
6784                       case RELOAD_OTHER:
6785                       case RELOAD_FOR_INPUT:
6786                       case RELOAD_FOR_OPERAND_ADDRESS:
6787                         if (! rld[r].optional)
6788                           reload_override_in[r] = equiv;
6789                         /* Fall through.  */
6790                       default:
6791                         equiv = 0;
6792                         break;
6793                       }
6794                   else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6795                     switch (rld[r].when_needed)
6796                       {
6797                       case RELOAD_FOR_OTHER_ADDRESS:
6798                       case RELOAD_FOR_INPADDR_ADDRESS:
6799                       case RELOAD_FOR_INPUT_ADDRESS:
6800                       case RELOAD_FOR_OPADDR_ADDR:
6801                       case RELOAD_FOR_OPERAND_ADDRESS:
6802                       case RELOAD_FOR_INPUT:
6803                         break;
6804                       case RELOAD_OTHER:
6805                         if (! rld[r].optional)
6806                           reload_override_in[r] = equiv;
6807                         /* Fall through.  */
6808                       default:
6809                         equiv = 0;
6810                         break;
6811                       }
6812                 }
6813
6814               /* If we found an equivalent reg, say no code need be generated
6815                  to load it, and use it as our reload reg.  */
6816               if (equiv != 0
6817                   && (regno != HARD_FRAME_POINTER_REGNUM
6818                       || !frame_pointer_needed))
6819                 {
6820                   int nr = hard_regno_nregs[regno][rld[r].mode];
6821                   int k;
6822                   rld[r].reg_rtx = equiv;
6823                   reload_spill_index[r] = regno;
6824                   reload_inherited[r] = 1;
6825
6826                   /* If reg_reloaded_valid is not set for this register,
6827                      there might be a stale spill_reg_store lying around.
6828                      We must clear it, since otherwise emit_reload_insns
6829                      might delete the store.  */
6830                   if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6831                     spill_reg_store[regno] = NULL_RTX;
6832                   /* If any of the hard registers in EQUIV are spill
6833                      registers, mark them as in use for this insn.  */
6834                   for (k = 0; k < nr; k++)
6835                     {
6836                       i = spill_reg_order[regno + k];
6837                       if (i >= 0)
6838                         {
6839                           mark_reload_reg_in_use (regno, rld[r].opnum,
6840                                                   rld[r].when_needed,
6841                                                   rld[r].mode);
6842                           SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6843                                             regno + k);
6844                         }
6845                     }
6846                 }
6847             }
6848
6849           /* If we found a register to use already, or if this is an optional
6850              reload, we are done.  */
6851           if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6852             continue;
6853
6854 #if 0
6855           /* No longer needed for correct operation.  Might or might
6856              not give better code on the average.  Want to experiment?  */
6857
6858           /* See if there is a later reload that has a class different from our
6859              class that intersects our class or that requires less register
6860              than our reload.  If so, we must allocate a register to this
6861              reload now, since that reload might inherit a previous reload
6862              and take the only available register in our class.  Don't do this
6863              for optional reloads since they will force all previous reloads
6864              to be allocated.  Also don't do this for reloads that have been
6865              turned off.  */
6866
6867           for (i = j + 1; i < n_reloads; i++)
6868             {
6869               int s = reload_order[i];
6870
6871               if ((rld[s].in == 0 && rld[s].out == 0
6872                    && ! rld[s].secondary_p)
6873                   || rld[s].optional)
6874                 continue;
6875
6876               if ((rld[s].rclass != rld[r].rclass
6877                    && reg_classes_intersect_p (rld[r].rclass,
6878                                                rld[s].rclass))
6879                   || rld[s].nregs < rld[r].nregs)
6880                 break;
6881             }
6882
6883           if (i == n_reloads)
6884             continue;
6885
6886           allocate_reload_reg (chain, r, j == n_reloads - 1);
6887 #endif
6888         }
6889
6890       /* Now allocate reload registers for anything non-optional that
6891          didn't get one yet.  */
6892       for (j = 0; j < n_reloads; j++)
6893         {
6894           int r = reload_order[j];
6895
6896           /* Ignore reloads that got marked inoperative.  */
6897           if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6898             continue;
6899
6900           /* Skip reloads that already have a register allocated or are
6901              optional.  */
6902           if (rld[r].reg_rtx != 0 || rld[r].optional)
6903             continue;
6904
6905           if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6906             break;
6907         }
6908
6909       /* If that loop got all the way, we have won.  */
6910       if (j == n_reloads)
6911         {
6912           win = 1;
6913           break;
6914         }
6915
6916       /* Loop around and try without any inheritance.  */
6917     }
6918
6919   if (! win)
6920     {
6921       /* First undo everything done by the failed attempt
6922          to allocate with inheritance.  */
6923       choose_reload_regs_init (chain, save_reload_reg_rtx);
6924
6925       /* Some sanity tests to verify that the reloads found in the first
6926          pass are identical to the ones we have now.  */
6927       gcc_assert (chain->n_reloads == n_reloads);
6928
6929       for (i = 0; i < n_reloads; i++)
6930         {
6931           if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6932             continue;
6933           gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6934           for (j = 0; j < n_spills; j++)
6935             if (spill_regs[j] == chain->rld[i].regno)
6936               if (! set_reload_reg (j, i))
6937                 failed_reload (chain->insn, i);
6938         }
6939     }
6940
6941   /* If we thought we could inherit a reload, because it seemed that
6942      nothing else wanted the same reload register earlier in the insn,
6943      verify that assumption, now that all reloads have been assigned.
6944      Likewise for reloads where reload_override_in has been set.  */
6945
6946   /* If doing expensive optimizations, do one preliminary pass that doesn't
6947      cancel any inheritance, but removes reloads that have been needed only
6948      for reloads that we know can be inherited.  */
6949   for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6950     {
6951       for (j = 0; j < n_reloads; j++)
6952         {
6953           int r = reload_order[j];
6954           rtx check_reg;
6955 #ifdef SECONDARY_MEMORY_NEEDED
6956           rtx tem;
6957 #endif
6958           if (reload_inherited[r] && rld[r].reg_rtx)
6959             check_reg = rld[r].reg_rtx;
6960           else if (reload_override_in[r]
6961                    && (REG_P (reload_override_in[r])
6962                        || GET_CODE (reload_override_in[r]) == SUBREG))
6963             check_reg = reload_override_in[r];
6964           else
6965             continue;
6966           if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6967                                   rld[r].opnum, rld[r].when_needed, rld[r].in,
6968                                   (reload_inherited[r]
6969                                    ? rld[r].out : const0_rtx),
6970                                   r, 1))
6971             {
6972               if (pass)
6973                 continue;
6974               reload_inherited[r] = 0;
6975               reload_override_in[r] = 0;
6976             }
6977           /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6978              reload_override_in, then we do not need its related
6979              RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6980              likewise for other reload types.
6981              We handle this by removing a reload when its only replacement
6982              is mentioned in reload_in of the reload we are going to inherit.
6983              A special case are auto_inc expressions; even if the input is
6984              inherited, we still need the address for the output.  We can
6985              recognize them because they have RELOAD_OUT set to RELOAD_IN.
6986              If we succeeded removing some reload and we are doing a preliminary
6987              pass just to remove such reloads, make another pass, since the
6988              removal of one reload might allow us to inherit another one.  */
6989           else if (rld[r].in
6990                    && rld[r].out != rld[r].in
6991                    && remove_address_replacements (rld[r].in))
6992             {
6993               if (pass)
6994                 pass = 2;
6995             }
6996 #ifdef SECONDARY_MEMORY_NEEDED
6997           /* If we needed a memory location for the reload, we also have to
6998              remove its related reloads.  */
6999           else if (rld[r].in
7000                    && rld[r].out != rld[r].in
7001                    && (tem = replaced_subreg (rld[r].in), REG_P (tem))
7002                    && REGNO (tem) < FIRST_PSEUDO_REGISTER
7003                    && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem)),
7004                                                rld[r].rclass, rld[r].inmode)
7005                    && remove_address_replacements
7006                       (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
7007                                           rld[r].when_needed)))
7008             {
7009               if (pass)
7010                 pass = 2;
7011             }
7012 #endif
7013         }
7014     }
7015
7016   /* Now that reload_override_in is known valid,
7017      actually override reload_in.  */
7018   for (j = 0; j < n_reloads; j++)
7019     if (reload_override_in[j])
7020       rld[j].in = reload_override_in[j];
7021
7022   /* If this reload won't be done because it has been canceled or is
7023      optional and not inherited, clear reload_reg_rtx so other
7024      routines (such as subst_reloads) don't get confused.  */
7025   for (j = 0; j < n_reloads; j++)
7026     if (rld[j].reg_rtx != 0
7027         && ((rld[j].optional && ! reload_inherited[j])
7028             || (rld[j].in == 0 && rld[j].out == 0
7029                 && ! rld[j].secondary_p)))
7030       {
7031         int regno = true_regnum (rld[j].reg_rtx);
7032
7033         if (spill_reg_order[regno] >= 0)
7034           clear_reload_reg_in_use (regno, rld[j].opnum,
7035                                    rld[j].when_needed, rld[j].mode);
7036         rld[j].reg_rtx = 0;
7037         reload_spill_index[j] = -1;
7038       }
7039
7040   /* Record which pseudos and which spill regs have output reloads.  */
7041   for (j = 0; j < n_reloads; j++)
7042     {
7043       int r = reload_order[j];
7044
7045       i = reload_spill_index[r];
7046
7047       /* I is nonneg if this reload uses a register.
7048          If rld[r].reg_rtx is 0, this is an optional reload
7049          that we opted to ignore.  */
7050       if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7051           && rld[r].reg_rtx != 0)
7052         {
7053           int nregno = REGNO (rld[r].out_reg);
7054           int nr = 1;
7055
7056           if (nregno < FIRST_PSEUDO_REGISTER)
7057             nr = hard_regno_nregs[nregno][rld[r].mode];
7058
7059           while (--nr >= 0)
7060             SET_REGNO_REG_SET (&reg_has_output_reload,
7061                                nregno + nr);
7062
7063           if (i >= 0)
7064             add_to_hard_reg_set (&reg_is_output_reload, rld[r].mode, i);
7065
7066           gcc_assert (rld[r].when_needed == RELOAD_OTHER
7067                       || rld[r].when_needed == RELOAD_FOR_OUTPUT
7068                       || rld[r].when_needed == RELOAD_FOR_INSN);
7069         }
7070     }
7071 }
7072
7073 /* Deallocate the reload register for reload R.  This is called from
7074    remove_address_replacements.  */
7075
7076 void
7077 deallocate_reload_reg (int r)
7078 {
7079   int regno;
7080
7081   if (! rld[r].reg_rtx)
7082     return;
7083   regno = true_regnum (rld[r].reg_rtx);
7084   rld[r].reg_rtx = 0;
7085   if (spill_reg_order[regno] >= 0)
7086     clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7087                              rld[r].mode);
7088   reload_spill_index[r] = -1;
7089 }
7090 \f
7091 /* These arrays are filled by emit_reload_insns and its subroutines.  */
7092 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7093 static rtx other_input_address_reload_insns = 0;
7094 static rtx other_input_reload_insns = 0;
7095 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7096 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7097 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7098 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7099 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7100 static rtx operand_reload_insns = 0;
7101 static rtx other_operand_reload_insns = 0;
7102 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7103
7104 /* Values to be put in spill_reg_store are put here first.  Instructions
7105    must only be placed here if the associated reload register reaches
7106    the end of the instruction's reload sequence.  */
7107 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7108 static HARD_REG_SET reg_reloaded_died;
7109
7110 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7111    of class NEW_CLASS with mode NEW_MODE.  Or alternatively, if alt_reload_reg
7112    is nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7113    adjusted register, and return true.  Otherwise, return false.  */
7114 static bool
7115 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7116                             enum reg_class new_class,
7117                             enum machine_mode new_mode)
7118
7119 {
7120   rtx reg;
7121
7122   for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7123     {
7124       unsigned regno = REGNO (reg);
7125
7126       if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7127         continue;
7128       if (GET_MODE (reg) != new_mode)
7129         {
7130           if (!HARD_REGNO_MODE_OK (regno, new_mode))
7131             continue;
7132           if (hard_regno_nregs[regno][new_mode]
7133               > hard_regno_nregs[regno][GET_MODE (reg)])
7134             continue;
7135           reg = reload_adjust_reg_for_mode (reg, new_mode);
7136         }
7137       *reload_reg = reg;
7138       return true;
7139     }
7140   return false;
7141 }
7142
7143 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7144    pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7145    nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7146    adjusted register, and return true.  Otherwise, return false.  */
7147 static bool
7148 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7149                              enum insn_code icode)
7150
7151 {
7152   enum reg_class new_class = scratch_reload_class (icode);
7153   enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7154
7155   return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7156                                      new_class, new_mode);
7157 }
7158
7159 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7160    has the number J.  OLD contains the value to be used as input.  */
7161
7162 static void
7163 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7164                          rtx old, int j)
7165 {
7166   rtx insn = chain->insn;
7167   rtx reloadreg;
7168   rtx oldequiv_reg = 0;
7169   rtx oldequiv = 0;
7170   int special = 0;
7171   enum machine_mode mode;
7172   rtx *where;
7173
7174   /* delete_output_reload is only invoked properly if old contains
7175      the original pseudo register.  Since this is replaced with a
7176      hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7177      find the pseudo in RELOAD_IN_REG.  */
7178   if (reload_override_in[j]
7179       && REG_P (rl->in_reg))
7180     {
7181       oldequiv = old;
7182       old = rl->in_reg;
7183     }
7184   if (oldequiv == 0)
7185     oldequiv = old;
7186   else if (REG_P (oldequiv))
7187     oldequiv_reg = oldequiv;
7188   else if (GET_CODE (oldequiv) == SUBREG)
7189     oldequiv_reg = SUBREG_REG (oldequiv);
7190
7191   reloadreg = reload_reg_rtx_for_input[j];
7192   mode = GET_MODE (reloadreg);
7193
7194   /* If we are reloading from a register that was recently stored in
7195      with an output-reload, see if we can prove there was
7196      actually no need to store the old value in it.  */
7197
7198   if (optimize && REG_P (oldequiv)
7199       && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7200       && spill_reg_store[REGNO (oldequiv)]
7201       && REG_P (old)
7202       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7203           || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7204                           rl->out_reg)))
7205     delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7206
7207   /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7208      OLDEQUIV.  */
7209
7210   while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7211     oldequiv = SUBREG_REG (oldequiv);
7212   if (GET_MODE (oldequiv) != VOIDmode
7213       && mode != GET_MODE (oldequiv))
7214     oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7215
7216   /* Switch to the right place to emit the reload insns.  */
7217   switch (rl->when_needed)
7218     {
7219     case RELOAD_OTHER:
7220       where = &other_input_reload_insns;
7221       break;
7222     case RELOAD_FOR_INPUT:
7223       where = &input_reload_insns[rl->opnum];
7224       break;
7225     case RELOAD_FOR_INPUT_ADDRESS:
7226       where = &input_address_reload_insns[rl->opnum];
7227       break;
7228     case RELOAD_FOR_INPADDR_ADDRESS:
7229       where = &inpaddr_address_reload_insns[rl->opnum];
7230       break;
7231     case RELOAD_FOR_OUTPUT_ADDRESS:
7232       where = &output_address_reload_insns[rl->opnum];
7233       break;
7234     case RELOAD_FOR_OUTADDR_ADDRESS:
7235       where = &outaddr_address_reload_insns[rl->opnum];
7236       break;
7237     case RELOAD_FOR_OPERAND_ADDRESS:
7238       where = &operand_reload_insns;
7239       break;
7240     case RELOAD_FOR_OPADDR_ADDR:
7241       where = &other_operand_reload_insns;
7242       break;
7243     case RELOAD_FOR_OTHER_ADDRESS:
7244       where = &other_input_address_reload_insns;
7245       break;
7246     default:
7247       gcc_unreachable ();
7248     }
7249
7250   push_to_sequence (*where);
7251
7252   /* Auto-increment addresses must be reloaded in a special way.  */
7253   if (rl->out && ! rl->out_reg)
7254     {
7255       /* We are not going to bother supporting the case where a
7256          incremented register can't be copied directly from
7257          OLDEQUIV since this seems highly unlikely.  */
7258       gcc_assert (rl->secondary_in_reload < 0);
7259
7260       if (reload_inherited[j])
7261         oldequiv = reloadreg;
7262
7263       old = XEXP (rl->in_reg, 0);
7264
7265       /* Prevent normal processing of this reload.  */
7266       special = 1;
7267       /* Output a special code sequence for this case.  */
7268       inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7269     }
7270
7271   /* If we are reloading a pseudo-register that was set by the previous
7272      insn, see if we can get rid of that pseudo-register entirely
7273      by redirecting the previous insn into our reload register.  */
7274
7275   else if (optimize && REG_P (old)
7276            && REGNO (old) >= FIRST_PSEUDO_REGISTER
7277            && dead_or_set_p (insn, old)
7278            /* This is unsafe if some other reload
7279               uses the same reg first.  */
7280            && ! conflicts_with_override (reloadreg)
7281            && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7282                                 rl->when_needed, old, rl->out, j, 0))
7283     {
7284       rtx temp = PREV_INSN (insn);
7285       while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7286         temp = PREV_INSN (temp);
7287       if (temp
7288           && NONJUMP_INSN_P (temp)
7289           && GET_CODE (PATTERN (temp)) == SET
7290           && SET_DEST (PATTERN (temp)) == old
7291           /* Make sure we can access insn_operand_constraint.  */
7292           && asm_noperands (PATTERN (temp)) < 0
7293           /* This is unsafe if operand occurs more than once in current
7294              insn.  Perhaps some occurrences aren't reloaded.  */
7295           && count_occurrences (PATTERN (insn), old, 0) == 1)
7296         {
7297           rtx old = SET_DEST (PATTERN (temp));
7298           /* Store into the reload register instead of the pseudo.  */
7299           SET_DEST (PATTERN (temp)) = reloadreg;
7300
7301           /* Verify that resulting insn is valid.  */
7302           extract_insn (temp);
7303           if (constrain_operands (1))
7304             {
7305               /* If the previous insn is an output reload, the source is
7306                  a reload register, and its spill_reg_store entry will
7307                  contain the previous destination.  This is now
7308                  invalid.  */
7309               if (REG_P (SET_SRC (PATTERN (temp)))
7310                   && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7311                 {
7312                   spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7313                   spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7314                 }
7315
7316               /* If these are the only uses of the pseudo reg,
7317                  pretend for GDB it lives in the reload reg we used.  */
7318               if (REG_N_DEATHS (REGNO (old)) == 1
7319                   && REG_N_SETS (REGNO (old)) == 1)
7320                 {
7321                   reg_renumber[REGNO (old)] = REGNO (reloadreg);
7322                   if (ira_conflicts_p)
7323                     /* Inform IRA about the change.  */
7324                     ira_mark_allocation_change (REGNO (old));
7325                   alter_reg (REGNO (old), -1, false);
7326                 }
7327               special = 1;
7328
7329               /* Adjust any debug insns between temp and insn.  */
7330               while ((temp = NEXT_INSN (temp)) != insn)
7331                 if (DEBUG_INSN_P (temp))
7332                   replace_rtx (PATTERN (temp), old, reloadreg);
7333                 else
7334                   gcc_assert (NOTE_P (temp));
7335             }
7336           else
7337             {
7338               SET_DEST (PATTERN (temp)) = old;
7339             }
7340         }
7341     }
7342
7343   /* We can't do that, so output an insn to load RELOADREG.  */
7344
7345   /* If we have a secondary reload, pick up the secondary register
7346      and icode, if any.  If OLDEQUIV and OLD are different or
7347      if this is an in-out reload, recompute whether or not we
7348      still need a secondary register and what the icode should
7349      be.  If we still need a secondary register and the class or
7350      icode is different, go back to reloading from OLD if using
7351      OLDEQUIV means that we got the wrong type of register.  We
7352      cannot have different class or icode due to an in-out reload
7353      because we don't make such reloads when both the input and
7354      output need secondary reload registers.  */
7355
7356   if (! special && rl->secondary_in_reload >= 0)
7357     {
7358       rtx second_reload_reg = 0;
7359       rtx third_reload_reg = 0;
7360       int secondary_reload = rl->secondary_in_reload;
7361       rtx real_oldequiv = oldequiv;
7362       rtx real_old = old;
7363       rtx tmp;
7364       enum insn_code icode;
7365       enum insn_code tertiary_icode = CODE_FOR_nothing;
7366
7367       /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7368          and similarly for OLD.
7369          See comments in get_secondary_reload in reload.c.  */
7370       /* If it is a pseudo that cannot be replaced with its
7371          equivalent MEM, we must fall back to reload_in, which
7372          will have all the necessary substitutions registered.
7373          Likewise for a pseudo that can't be replaced with its
7374          equivalent constant.
7375
7376          Take extra care for subregs of such pseudos.  Note that
7377          we cannot use reg_equiv_mem in this case because it is
7378          not in the right mode.  */
7379
7380       tmp = oldequiv;
7381       if (GET_CODE (tmp) == SUBREG)
7382         tmp = SUBREG_REG (tmp);
7383       if (REG_P (tmp)
7384           && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7385           && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7386               || reg_equiv_constant (REGNO (tmp)) != 0))
7387         {
7388           if (! reg_equiv_mem (REGNO (tmp))
7389               || num_not_at_initial_offset
7390               || GET_CODE (oldequiv) == SUBREG)
7391             real_oldequiv = rl->in;
7392           else
7393             real_oldequiv = reg_equiv_mem (REGNO (tmp));
7394         }
7395
7396       tmp = old;
7397       if (GET_CODE (tmp) == SUBREG)
7398         tmp = SUBREG_REG (tmp);
7399       if (REG_P (tmp)
7400           && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7401           && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7402               || reg_equiv_constant (REGNO (tmp)) != 0))
7403         {
7404           if (! reg_equiv_mem (REGNO (tmp))
7405               || num_not_at_initial_offset
7406               || GET_CODE (old) == SUBREG)
7407             real_old = rl->in;
7408           else
7409             real_old = reg_equiv_mem (REGNO (tmp));
7410         }
7411
7412       second_reload_reg = rld[secondary_reload].reg_rtx;
7413       if (rld[secondary_reload].secondary_in_reload >= 0)
7414         {
7415           int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7416
7417           third_reload_reg = rld[tertiary_reload].reg_rtx;
7418           tertiary_icode = rld[secondary_reload].secondary_in_icode;
7419           /* We'd have to add more code for quartary reloads.  */
7420           gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7421         }
7422       icode = rl->secondary_in_icode;
7423
7424       if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7425           || (rl->in != 0 && rl->out != 0))
7426         {
7427           secondary_reload_info sri, sri2;
7428           enum reg_class new_class, new_t_class;
7429
7430           sri.icode = CODE_FOR_nothing;
7431           sri.prev_sri = NULL;
7432           new_class
7433             = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7434                                                          rl->rclass, mode,
7435                                                          &sri);
7436
7437           if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7438             second_reload_reg = 0;
7439           else if (new_class == NO_REGS)
7440             {
7441               if (reload_adjust_reg_for_icode (&second_reload_reg,
7442                                                third_reload_reg,
7443                                                (enum insn_code) sri.icode))
7444                 {
7445                   icode = (enum insn_code) sri.icode;
7446                   third_reload_reg = 0;
7447                 }
7448               else
7449                 {
7450                   oldequiv = old;
7451                   real_oldequiv = real_old;
7452                 }
7453             }
7454           else if (sri.icode != CODE_FOR_nothing)
7455             /* We currently lack a way to express this in reloads.  */
7456             gcc_unreachable ();
7457           else
7458             {
7459               sri2.icode = CODE_FOR_nothing;
7460               sri2.prev_sri = &sri;
7461               new_t_class
7462                 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7463                                                              new_class, mode,
7464                                                              &sri);
7465               if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7466                 {
7467                   if (reload_adjust_reg_for_temp (&second_reload_reg,
7468                                                   third_reload_reg,
7469                                                   new_class, mode))
7470                     {
7471                       third_reload_reg = 0;
7472                       tertiary_icode = (enum insn_code) sri2.icode;
7473                     }
7474                   else
7475                     {
7476                       oldequiv = old;
7477                       real_oldequiv = real_old;
7478                     }
7479                 }
7480               else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7481                 {
7482                   rtx intermediate = second_reload_reg;
7483
7484                   if (reload_adjust_reg_for_temp (&intermediate, NULL,
7485                                                   new_class, mode)
7486                       && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7487                                                       ((enum insn_code)
7488                                                        sri2.icode)))
7489                     {
7490                       second_reload_reg = intermediate;
7491                       tertiary_icode = (enum insn_code) sri2.icode;
7492                     }
7493                   else
7494                     {
7495                       oldequiv = old;
7496                       real_oldequiv = real_old;
7497                     }
7498                 }
7499               else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7500                 {
7501                   rtx intermediate = second_reload_reg;
7502
7503                   if (reload_adjust_reg_for_temp (&intermediate, NULL,
7504                                                   new_class, mode)
7505                       && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7506                                                       new_t_class, mode))
7507                     {
7508                       second_reload_reg = intermediate;
7509                       tertiary_icode = (enum insn_code) sri2.icode;
7510                     }
7511                   else
7512                     {
7513                       oldequiv = old;
7514                       real_oldequiv = real_old;
7515                     }
7516                 }
7517               else
7518                 {
7519                   /* This could be handled more intelligently too.  */
7520                   oldequiv = old;
7521                   real_oldequiv = real_old;
7522                 }
7523             }
7524         }
7525
7526       /* If we still need a secondary reload register, check
7527          to see if it is being used as a scratch or intermediate
7528          register and generate code appropriately.  If we need
7529          a scratch register, use REAL_OLDEQUIV since the form of
7530          the insn may depend on the actual address if it is
7531          a MEM.  */
7532
7533       if (second_reload_reg)
7534         {
7535           if (icode != CODE_FOR_nothing)
7536             {
7537               /* We'd have to add extra code to handle this case.  */
7538               gcc_assert (!third_reload_reg);
7539
7540               emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7541                                           second_reload_reg));
7542               special = 1;
7543             }
7544           else
7545             {
7546               /* See if we need a scratch register to load the
7547                  intermediate register (a tertiary reload).  */
7548               if (tertiary_icode != CODE_FOR_nothing)
7549                 {
7550                   emit_insn ((GEN_FCN (tertiary_icode)
7551                               (second_reload_reg, real_oldequiv,
7552                                third_reload_reg)));
7553                 }
7554               else if (third_reload_reg)
7555                 {
7556                   gen_reload (third_reload_reg, real_oldequiv,
7557                               rl->opnum,
7558                               rl->when_needed);
7559                   gen_reload (second_reload_reg, third_reload_reg,
7560                               rl->opnum,
7561                               rl->when_needed);
7562                 }
7563               else
7564                 gen_reload (second_reload_reg, real_oldequiv,
7565                             rl->opnum,
7566                             rl->when_needed);
7567
7568               oldequiv = second_reload_reg;
7569             }
7570         }
7571     }
7572
7573   if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7574     {
7575       rtx real_oldequiv = oldequiv;
7576
7577       if ((REG_P (oldequiv)
7578            && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7579            && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7580                || reg_equiv_constant (REGNO (oldequiv)) != 0))
7581           || (GET_CODE (oldequiv) == SUBREG
7582               && REG_P (SUBREG_REG (oldequiv))
7583               && (REGNO (SUBREG_REG (oldequiv))
7584                   >= FIRST_PSEUDO_REGISTER)
7585               && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7586                   || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7587           || (CONSTANT_P (oldequiv)
7588               && (targetm.preferred_reload_class (oldequiv,
7589                                                   REGNO_REG_CLASS (REGNO (reloadreg)))
7590                   == NO_REGS)))
7591         real_oldequiv = rl->in;
7592       gen_reload (reloadreg, real_oldequiv, rl->opnum,
7593                   rl->when_needed);
7594     }
7595
7596   if (cfun->can_throw_non_call_exceptions)
7597     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7598
7599   /* End this sequence.  */
7600   *where = get_insns ();
7601   end_sequence ();
7602
7603   /* Update reload_override_in so that delete_address_reloads_1
7604      can see the actual register usage.  */
7605   if (oldequiv_reg)
7606     reload_override_in[j] = oldequiv;
7607 }
7608
7609 /* Generate insns to for the output reload RL, which is for the insn described
7610    by CHAIN and has the number J.  */
7611 static void
7612 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7613                           int j)
7614 {
7615   rtx reloadreg;
7616   rtx insn = chain->insn;
7617   int special = 0;
7618   rtx old = rl->out;
7619   enum machine_mode mode;
7620   rtx p;
7621   rtx rl_reg_rtx;
7622
7623   if (rl->when_needed == RELOAD_OTHER)
7624     start_sequence ();
7625   else
7626     push_to_sequence (output_reload_insns[rl->opnum]);
7627
7628   rl_reg_rtx = reload_reg_rtx_for_output[j];
7629   mode = GET_MODE (rl_reg_rtx);
7630
7631   reloadreg = rl_reg_rtx;
7632
7633   /* If we need two reload regs, set RELOADREG to the intermediate
7634      one, since it will be stored into OLD.  We might need a secondary
7635      register only for an input reload, so check again here.  */
7636
7637   if (rl->secondary_out_reload >= 0)
7638     {
7639       rtx real_old = old;
7640       int secondary_reload = rl->secondary_out_reload;
7641       int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7642
7643       if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7644           && reg_equiv_mem (REGNO (old)) != 0)
7645         real_old = reg_equiv_mem (REGNO (old));
7646
7647       if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7648         {
7649           rtx second_reloadreg = reloadreg;
7650           reloadreg = rld[secondary_reload].reg_rtx;
7651
7652           /* See if RELOADREG is to be used as a scratch register
7653              or as an intermediate register.  */
7654           if (rl->secondary_out_icode != CODE_FOR_nothing)
7655             {
7656               /* We'd have to add extra code to handle this case.  */
7657               gcc_assert (tertiary_reload < 0);
7658
7659               emit_insn ((GEN_FCN (rl->secondary_out_icode)
7660                           (real_old, second_reloadreg, reloadreg)));
7661               special = 1;
7662             }
7663           else
7664             {
7665               /* See if we need both a scratch and intermediate reload
7666                  register.  */
7667
7668               enum insn_code tertiary_icode
7669                 = rld[secondary_reload].secondary_out_icode;
7670
7671               /* We'd have to add more code for quartary reloads.  */
7672               gcc_assert (tertiary_reload < 0
7673                           || rld[tertiary_reload].secondary_out_reload < 0);
7674
7675               if (GET_MODE (reloadreg) != mode)
7676                 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7677
7678               if (tertiary_icode != CODE_FOR_nothing)
7679                 {
7680                   rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7681
7682                   /* Copy primary reload reg to secondary reload reg.
7683                      (Note that these have been swapped above, then
7684                      secondary reload reg to OLD using our insn.)  */
7685
7686                   /* If REAL_OLD is a paradoxical SUBREG, remove it
7687                      and try to put the opposite SUBREG on
7688                      RELOADREG.  */
7689                   strip_paradoxical_subreg (&real_old, &reloadreg);
7690
7691                   gen_reload (reloadreg, second_reloadreg,
7692                               rl->opnum, rl->when_needed);
7693                   emit_insn ((GEN_FCN (tertiary_icode)
7694                               (real_old, reloadreg, third_reloadreg)));
7695                   special = 1;
7696                 }
7697
7698               else
7699                 {
7700                   /* Copy between the reload regs here and then to
7701                      OUT later.  */
7702
7703                   gen_reload (reloadreg, second_reloadreg,
7704                               rl->opnum, rl->when_needed);
7705                   if (tertiary_reload >= 0)
7706                     {
7707                       rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7708
7709                       gen_reload (third_reloadreg, reloadreg,
7710                                   rl->opnum, rl->when_needed);
7711                       reloadreg = third_reloadreg;
7712                     }
7713                 }
7714             }
7715         }
7716     }
7717
7718   /* Output the last reload insn.  */
7719   if (! special)
7720     {
7721       rtx set;
7722
7723       /* Don't output the last reload if OLD is not the dest of
7724          INSN and is in the src and is clobbered by INSN.  */
7725       if (! flag_expensive_optimizations
7726           || !REG_P (old)
7727           || !(set = single_set (insn))
7728           || rtx_equal_p (old, SET_DEST (set))
7729           || !reg_mentioned_p (old, SET_SRC (set))
7730           || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7731                && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7732         gen_reload (old, reloadreg, rl->opnum,
7733                     rl->when_needed);
7734     }
7735
7736   /* Look at all insns we emitted, just to be safe.  */
7737   for (p = get_insns (); p; p = NEXT_INSN (p))
7738     if (INSN_P (p))
7739       {
7740         rtx pat = PATTERN (p);
7741
7742         /* If this output reload doesn't come from a spill reg,
7743            clear any memory of reloaded copies of the pseudo reg.
7744            If this output reload comes from a spill reg,
7745            reg_has_output_reload will make this do nothing.  */
7746         note_stores (pat, forget_old_reloads_1, NULL);
7747
7748         if (reg_mentioned_p (rl_reg_rtx, pat))
7749           {
7750             rtx set = single_set (insn);
7751             if (reload_spill_index[j] < 0
7752                 && set
7753                 && SET_SRC (set) == rl_reg_rtx)
7754               {
7755                 int src = REGNO (SET_SRC (set));
7756
7757                 reload_spill_index[j] = src;
7758                 SET_HARD_REG_BIT (reg_is_output_reload, src);
7759                 if (find_regno_note (insn, REG_DEAD, src))
7760                   SET_HARD_REG_BIT (reg_reloaded_died, src);
7761               }
7762             if (HARD_REGISTER_P (rl_reg_rtx))
7763               {
7764                 int s = rl->secondary_out_reload;
7765                 set = single_set (p);
7766                 /* If this reload copies only to the secondary reload
7767                    register, the secondary reload does the actual
7768                    store.  */
7769                 if (s >= 0 && set == NULL_RTX)
7770                   /* We can't tell what function the secondary reload
7771                      has and where the actual store to the pseudo is
7772                      made; leave new_spill_reg_store alone.  */
7773                   ;
7774                 else if (s >= 0
7775                          && SET_SRC (set) == rl_reg_rtx
7776                          && SET_DEST (set) == rld[s].reg_rtx)
7777                   {
7778                     /* Usually the next instruction will be the
7779                        secondary reload insn;  if we can confirm
7780                        that it is, setting new_spill_reg_store to
7781                        that insn will allow an extra optimization.  */
7782                     rtx s_reg = rld[s].reg_rtx;
7783                     rtx next = NEXT_INSN (p);
7784                     rld[s].out = rl->out;
7785                     rld[s].out_reg = rl->out_reg;
7786                     set = single_set (next);
7787                     if (set && SET_SRC (set) == s_reg
7788                         && reload_reg_rtx_reaches_end_p (s_reg, s))
7789                       {
7790                         SET_HARD_REG_BIT (reg_is_output_reload,
7791                                           REGNO (s_reg));
7792                         new_spill_reg_store[REGNO (s_reg)] = next;
7793                       }
7794                   }
7795                 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7796                   new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7797               }
7798           }
7799       }
7800
7801   if (rl->when_needed == RELOAD_OTHER)
7802     {
7803       emit_insn (other_output_reload_insns[rl->opnum]);
7804       other_output_reload_insns[rl->opnum] = get_insns ();
7805     }
7806   else
7807     output_reload_insns[rl->opnum] = get_insns ();
7808
7809   if (cfun->can_throw_non_call_exceptions)
7810     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7811
7812   end_sequence ();
7813 }
7814
7815 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7816    and has the number J.  */
7817 static void
7818 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7819 {
7820   rtx insn = chain->insn;
7821   rtx old = (rl->in && MEM_P (rl->in)
7822              ? rl->in_reg : rl->in);
7823   rtx reg_rtx = rl->reg_rtx;
7824
7825   if (old && reg_rtx)
7826     {
7827       enum machine_mode mode;
7828
7829       /* Determine the mode to reload in.
7830          This is very tricky because we have three to choose from.
7831          There is the mode the insn operand wants (rl->inmode).
7832          There is the mode of the reload register RELOADREG.
7833          There is the intrinsic mode of the operand, which we could find
7834          by stripping some SUBREGs.
7835          It turns out that RELOADREG's mode is irrelevant:
7836          we can change that arbitrarily.
7837
7838          Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7839          then the reload reg may not support QImode moves, so use SImode.
7840          If foo is in memory due to spilling a pseudo reg, this is safe,
7841          because the QImode value is in the least significant part of a
7842          slot big enough for a SImode.  If foo is some other sort of
7843          memory reference, then it is impossible to reload this case,
7844          so previous passes had better make sure this never happens.
7845
7846          Then consider a one-word union which has SImode and one of its
7847          members is a float, being fetched as (SUBREG:SF union:SI).
7848          We must fetch that as SFmode because we could be loading into
7849          a float-only register.  In this case OLD's mode is correct.
7850
7851          Consider an immediate integer: it has VOIDmode.  Here we need
7852          to get a mode from something else.
7853
7854          In some cases, there is a fourth mode, the operand's
7855          containing mode.  If the insn specifies a containing mode for
7856          this operand, it overrides all others.
7857
7858          I am not sure whether the algorithm here is always right,
7859          but it does the right things in those cases.  */
7860
7861       mode = GET_MODE (old);
7862       if (mode == VOIDmode)
7863         mode = rl->inmode;
7864
7865       /* We cannot use gen_lowpart_common since it can do the wrong thing
7866          when REG_RTX has a multi-word mode.  Note that REG_RTX must
7867          always be a REG here.  */
7868       if (GET_MODE (reg_rtx) != mode)
7869         reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7870     }
7871   reload_reg_rtx_for_input[j] = reg_rtx;
7872
7873   if (old != 0
7874       /* AUTO_INC reloads need to be handled even if inherited.  We got an
7875          AUTO_INC reload if reload_out is set but reload_out_reg isn't.  */
7876       && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7877       && ! rtx_equal_p (reg_rtx, old)
7878       && reg_rtx != 0)
7879     emit_input_reload_insns (chain, rld + j, old, j);
7880
7881   /* When inheriting a wider reload, we have a MEM in rl->in,
7882      e.g. inheriting a SImode output reload for
7883      (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10)))  */
7884   if (optimize && reload_inherited[j] && rl->in
7885       && MEM_P (rl->in)
7886       && MEM_P (rl->in_reg)
7887       && reload_spill_index[j] >= 0
7888       && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7889     rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7890
7891   /* If we are reloading a register that was recently stored in with an
7892      output-reload, see if we can prove there was
7893      actually no need to store the old value in it.  */
7894
7895   if (optimize
7896       && (reload_inherited[j] || reload_override_in[j])
7897       && reg_rtx
7898       && REG_P (reg_rtx)
7899       && spill_reg_store[REGNO (reg_rtx)] != 0
7900 #if 0
7901       /* There doesn't seem to be any reason to restrict this to pseudos
7902          and doing so loses in the case where we are copying from a
7903          register of the wrong class.  */
7904       && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7905 #endif
7906       /* The insn might have already some references to stackslots
7907          replaced by MEMs, while reload_out_reg still names the
7908          original pseudo.  */
7909       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7910           || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7911     delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7912 }
7913
7914 /* Do output reloading for reload RL, which is for the insn described by
7915    CHAIN and has the number J.
7916    ??? At some point we need to support handling output reloads of
7917    JUMP_INSNs or insns that set cc0.  */
7918 static void
7919 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7920 {
7921   rtx note, old;
7922   rtx insn = chain->insn;
7923   /* If this is an output reload that stores something that is
7924      not loaded in this same reload, see if we can eliminate a previous
7925      store.  */
7926   rtx pseudo = rl->out_reg;
7927   rtx reg_rtx = rl->reg_rtx;
7928
7929   if (rl->out && reg_rtx)
7930     {
7931       enum machine_mode mode;
7932
7933       /* Determine the mode to reload in.
7934          See comments above (for input reloading).  */
7935       mode = GET_MODE (rl->out);
7936       if (mode == VOIDmode)
7937         {
7938           /* VOIDmode should never happen for an output.  */
7939           if (asm_noperands (PATTERN (insn)) < 0)
7940             /* It's the compiler's fault.  */
7941             fatal_insn ("VOIDmode on an output", insn);
7942           error_for_asm (insn, "output operand is constant in %<asm%>");
7943           /* Prevent crash--use something we know is valid.  */
7944           mode = word_mode;
7945           rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7946         }
7947       if (GET_MODE (reg_rtx) != mode)
7948         reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7949     }
7950   reload_reg_rtx_for_output[j] = reg_rtx;
7951
7952   if (pseudo
7953       && optimize
7954       && REG_P (pseudo)
7955       && ! rtx_equal_p (rl->in_reg, pseudo)
7956       && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7957       && reg_last_reload_reg[REGNO (pseudo)])
7958     {
7959       int pseudo_no = REGNO (pseudo);
7960       int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7961
7962       /* We don't need to test full validity of last_regno for
7963          inherit here; we only want to know if the store actually
7964          matches the pseudo.  */
7965       if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7966           && reg_reloaded_contents[last_regno] == pseudo_no
7967           && spill_reg_store[last_regno]
7968           && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7969         delete_output_reload (insn, j, last_regno, reg_rtx);
7970     }
7971
7972   old = rl->out_reg;
7973   if (old == 0
7974       || reg_rtx == 0
7975       || rtx_equal_p (old, reg_rtx))
7976     return;
7977
7978   /* An output operand that dies right away does need a reload,
7979      but need not be copied from it.  Show the new location in the
7980      REG_UNUSED note.  */
7981   if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7982       && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7983     {
7984       XEXP (note, 0) = reg_rtx;
7985       return;
7986     }
7987   /* Likewise for a SUBREG of an operand that dies.  */
7988   else if (GET_CODE (old) == SUBREG
7989            && REG_P (SUBREG_REG (old))
7990            && 0 != (note = find_reg_note (insn, REG_UNUSED,
7991                                           SUBREG_REG (old))))
7992     {
7993       XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7994       return;
7995     }
7996   else if (GET_CODE (old) == SCRATCH)
7997     /* If we aren't optimizing, there won't be a REG_UNUSED note,
7998        but we don't want to make an output reload.  */
7999     return;
8000
8001   /* If is a JUMP_INSN, we can't support output reloads yet.  */
8002   gcc_assert (NONJUMP_INSN_P (insn));
8003
8004   emit_output_reload_insns (chain, rld + j, j);
8005 }
8006
8007 /* A reload copies values of MODE from register SRC to register DEST.
8008    Return true if it can be treated for inheritance purposes like a
8009    group of reloads, each one reloading a single hard register.  The
8010    caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8011    occupy the same number of hard registers.  */
8012
8013 static bool
8014 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8015                      int src ATTRIBUTE_UNUSED,
8016                      enum machine_mode mode ATTRIBUTE_UNUSED)
8017 {
8018 #ifdef CANNOT_CHANGE_MODE_CLASS
8019   return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8020           && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8021 #else
8022   return true;
8023 #endif
8024 }
8025
8026 /* Output insns to reload values in and out of the chosen reload regs.  */
8027
8028 static void
8029 emit_reload_insns (struct insn_chain *chain)
8030 {
8031   rtx insn = chain->insn;
8032
8033   int j;
8034
8035   CLEAR_HARD_REG_SET (reg_reloaded_died);
8036
8037   for (j = 0; j < reload_n_operands; j++)
8038     input_reload_insns[j] = input_address_reload_insns[j]
8039       = inpaddr_address_reload_insns[j]
8040       = output_reload_insns[j] = output_address_reload_insns[j]
8041       = outaddr_address_reload_insns[j]
8042       = other_output_reload_insns[j] = 0;
8043   other_input_address_reload_insns = 0;
8044   other_input_reload_insns = 0;
8045   operand_reload_insns = 0;
8046   other_operand_reload_insns = 0;
8047
8048   /* Dump reloads into the dump file.  */
8049   if (dump_file)
8050     {
8051       fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8052       debug_reload_to_stream (dump_file);
8053     }
8054
8055   for (j = 0; j < n_reloads; j++)
8056     if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8057       {
8058         unsigned int i;
8059
8060         for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8061           new_spill_reg_store[i] = 0;
8062       }
8063
8064   /* Now output the instructions to copy the data into and out of the
8065      reload registers.  Do these in the order that the reloads were reported,
8066      since reloads of base and index registers precede reloads of operands
8067      and the operands may need the base and index registers reloaded.  */
8068
8069   for (j = 0; j < n_reloads; j++)
8070     {
8071       do_input_reload (chain, rld + j, j);
8072       do_output_reload (chain, rld + j, j);
8073     }
8074
8075   /* Now write all the insns we made for reloads in the order expected by
8076      the allocation functions.  Prior to the insn being reloaded, we write
8077      the following reloads:
8078
8079      RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8080
8081      RELOAD_OTHER reloads.
8082
8083      For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8084      by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8085      RELOAD_FOR_INPUT reload for the operand.
8086
8087      RELOAD_FOR_OPADDR_ADDRS reloads.
8088
8089      RELOAD_FOR_OPERAND_ADDRESS reloads.
8090
8091      After the insn being reloaded, we write the following:
8092
8093      For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8094      by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8095      RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8096      reloads for the operand.  The RELOAD_OTHER output reloads are
8097      output in descending order by reload number.  */
8098
8099   emit_insn_before (other_input_address_reload_insns, insn);
8100   emit_insn_before (other_input_reload_insns, insn);
8101
8102   for (j = 0; j < reload_n_operands; j++)
8103     {
8104       emit_insn_before (inpaddr_address_reload_insns[j], insn);
8105       emit_insn_before (input_address_reload_insns[j], insn);
8106       emit_insn_before (input_reload_insns[j], insn);
8107     }
8108
8109   emit_insn_before (other_operand_reload_insns, insn);
8110   emit_insn_before (operand_reload_insns, insn);
8111
8112   for (j = 0; j < reload_n_operands; j++)
8113     {
8114       rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8115       x = emit_insn_after (output_address_reload_insns[j], x);
8116       x = emit_insn_after (output_reload_insns[j], x);
8117       emit_insn_after (other_output_reload_insns[j], x);
8118     }
8119
8120   /* For all the spill regs newly reloaded in this instruction,
8121      record what they were reloaded from, so subsequent instructions
8122      can inherit the reloads.
8123
8124      Update spill_reg_store for the reloads of this insn.
8125      Copy the elements that were updated in the loop above.  */
8126
8127   for (j = 0; j < n_reloads; j++)
8128     {
8129       int r = reload_order[j];
8130       int i = reload_spill_index[r];
8131
8132       /* If this is a non-inherited input reload from a pseudo, we must
8133          clear any memory of a previous store to the same pseudo.  Only do
8134          something if there will not be an output reload for the pseudo
8135          being reloaded.  */
8136       if (rld[r].in_reg != 0
8137           && ! (reload_inherited[r] || reload_override_in[r]))
8138         {
8139           rtx reg = rld[r].in_reg;
8140
8141           if (GET_CODE (reg) == SUBREG)
8142             reg = SUBREG_REG (reg);
8143
8144           if (REG_P (reg)
8145               && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8146               && !REGNO_REG_SET_P (&reg_has_output_reload, REGNO (reg)))
8147             {
8148               int nregno = REGNO (reg);
8149
8150               if (reg_last_reload_reg[nregno])
8151                 {
8152                   int last_regno = REGNO (reg_last_reload_reg[nregno]);
8153
8154                   if (reg_reloaded_contents[last_regno] == nregno)
8155                     spill_reg_store[last_regno] = 0;
8156                 }
8157             }
8158         }
8159
8160       /* I is nonneg if this reload used a register.
8161          If rld[r].reg_rtx is 0, this is an optional reload
8162          that we opted to ignore.  */
8163
8164       if (i >= 0 && rld[r].reg_rtx != 0)
8165         {
8166           int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8167           int k;
8168
8169           /* For a multi register reload, we need to check if all or part
8170              of the value lives to the end.  */
8171           for (k = 0; k < nr; k++)
8172             if (reload_reg_reaches_end_p (i + k, r))
8173               CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8174
8175           /* Maybe the spill reg contains a copy of reload_out.  */
8176           if (rld[r].out != 0
8177               && (REG_P (rld[r].out)
8178                   || (rld[r].out_reg
8179                       ? REG_P (rld[r].out_reg)
8180                       /* The reload value is an auto-modification of
8181                          some kind.  For PRE_INC, POST_INC, PRE_DEC
8182                          and POST_DEC, we record an equivalence
8183                          between the reload register and the operand
8184                          on the optimistic assumption that we can make
8185                          the equivalence hold.  reload_as_needed must
8186                          then either make it hold or invalidate the
8187                          equivalence.
8188
8189                          PRE_MODIFY and POST_MODIFY addresses are reloaded
8190                          somewhat differently, and allowing them here leads
8191                          to problems.  */
8192                       : (GET_CODE (rld[r].out) != POST_MODIFY
8193                          && GET_CODE (rld[r].out) != PRE_MODIFY))))
8194             {
8195               rtx reg;
8196
8197               reg = reload_reg_rtx_for_output[r];
8198               if (reload_reg_rtx_reaches_end_p (reg, r))
8199                 {
8200                   enum machine_mode mode = GET_MODE (reg);
8201                   int regno = REGNO (reg);
8202                   int nregs = hard_regno_nregs[regno][mode];
8203                   rtx out = (REG_P (rld[r].out)
8204                              ? rld[r].out
8205                              : rld[r].out_reg
8206                              ? rld[r].out_reg
8207 /* AUTO_INC */               : XEXP (rld[r].in_reg, 0));
8208                   int out_regno = REGNO (out);
8209                   int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8210                                    : hard_regno_nregs[out_regno][mode]);
8211                   bool piecemeal;
8212
8213                   spill_reg_store[regno] = new_spill_reg_store[regno];
8214                   spill_reg_stored_to[regno] = out;
8215                   reg_last_reload_reg[out_regno] = reg;
8216
8217                   piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8218                                && nregs == out_nregs
8219                                && inherit_piecemeal_p (out_regno, regno, mode));
8220
8221                   /* If OUT_REGNO is a hard register, it may occupy more than
8222                      one register.  If it does, say what is in the
8223                      rest of the registers assuming that both registers
8224                      agree on how many words the object takes.  If not,
8225                      invalidate the subsequent registers.  */
8226
8227                   if (HARD_REGISTER_NUM_P (out_regno))
8228                     for (k = 1; k < out_nregs; k++)
8229                       reg_last_reload_reg[out_regno + k]
8230                         = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8231
8232                   /* Now do the inverse operation.  */
8233                   for (k = 0; k < nregs; k++)
8234                     {
8235                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8236                       reg_reloaded_contents[regno + k]
8237                         = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8238                            ? out_regno
8239                            : out_regno + k);
8240                       reg_reloaded_insn[regno + k] = insn;
8241                       SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8242                       if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8243                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8244                                           regno + k);
8245                       else
8246                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8247                                             regno + k);
8248                     }
8249                 }
8250             }
8251           /* Maybe the spill reg contains a copy of reload_in.  Only do
8252              something if there will not be an output reload for
8253              the register being reloaded.  */
8254           else if (rld[r].out_reg == 0
8255                    && rld[r].in != 0
8256                    && ((REG_P (rld[r].in)
8257                         && !HARD_REGISTER_P (rld[r].in)
8258                         && !REGNO_REG_SET_P (&reg_has_output_reload,
8259                                              REGNO (rld[r].in)))
8260                        || (REG_P (rld[r].in_reg)
8261                            && !REGNO_REG_SET_P (&reg_has_output_reload,
8262                                                 REGNO (rld[r].in_reg))))
8263                    && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8264             {
8265               rtx reg;
8266
8267               reg = reload_reg_rtx_for_input[r];
8268               if (reload_reg_rtx_reaches_end_p (reg, r))
8269                 {
8270                   enum machine_mode mode;
8271                   int regno;
8272                   int nregs;
8273                   int in_regno;
8274                   int in_nregs;
8275                   rtx in;
8276                   bool piecemeal;
8277
8278                   mode = GET_MODE (reg);
8279                   regno = REGNO (reg);
8280                   nregs = hard_regno_nregs[regno][mode];
8281                   if (REG_P (rld[r].in)
8282                       && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8283                     in = rld[r].in;
8284                   else if (REG_P (rld[r].in_reg))
8285                     in = rld[r].in_reg;
8286                   else
8287                     in = XEXP (rld[r].in_reg, 0);
8288                   in_regno = REGNO (in);
8289
8290                   in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8291                               : hard_regno_nregs[in_regno][mode]);
8292
8293                   reg_last_reload_reg[in_regno] = reg;
8294
8295                   piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8296                                && nregs == in_nregs
8297                                && inherit_piecemeal_p (regno, in_regno, mode));
8298
8299                   if (HARD_REGISTER_NUM_P (in_regno))
8300                     for (k = 1; k < in_nregs; k++)
8301                       reg_last_reload_reg[in_regno + k]
8302                         = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8303
8304                   /* Unless we inherited this reload, show we haven't
8305                      recently done a store.
8306                      Previous stores of inherited auto_inc expressions
8307                      also have to be discarded.  */
8308                   if (! reload_inherited[r]
8309                       || (rld[r].out && ! rld[r].out_reg))
8310                     spill_reg_store[regno] = 0;
8311
8312                   for (k = 0; k < nregs; k++)
8313                     {
8314                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8315                       reg_reloaded_contents[regno + k]
8316                         = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8317                            ? in_regno
8318                            : in_regno + k);
8319                       reg_reloaded_insn[regno + k] = insn;
8320                       SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8321                       if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8322                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8323                                           regno + k);
8324                       else
8325                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8326                                             regno + k);
8327                     }
8328                 }
8329             }
8330         }
8331
8332       /* The following if-statement was #if 0'd in 1.34 (or before...).
8333          It's reenabled in 1.35 because supposedly nothing else
8334          deals with this problem.  */
8335
8336       /* If a register gets output-reloaded from a non-spill register,
8337          that invalidates any previous reloaded copy of it.
8338          But forget_old_reloads_1 won't get to see it, because
8339          it thinks only about the original insn.  So invalidate it here.
8340          Also do the same thing for RELOAD_OTHER constraints where the
8341          output is discarded.  */
8342       if (i < 0
8343           && ((rld[r].out != 0
8344                && (REG_P (rld[r].out)
8345                    || (MEM_P (rld[r].out)
8346                        && REG_P (rld[r].out_reg))))
8347               || (rld[r].out == 0 && rld[r].out_reg
8348                   && REG_P (rld[r].out_reg))))
8349         {
8350           rtx out = ((rld[r].out && REG_P (rld[r].out))
8351                      ? rld[r].out : rld[r].out_reg);
8352           int out_regno = REGNO (out);
8353           enum machine_mode mode = GET_MODE (out);
8354
8355           /* REG_RTX is now set or clobbered by the main instruction.
8356              As the comment above explains, forget_old_reloads_1 only
8357              sees the original instruction, and there is no guarantee
8358              that the original instruction also clobbered REG_RTX.
8359              For example, if find_reloads sees that the input side of
8360              a matched operand pair dies in this instruction, it may
8361              use the input register as the reload register.
8362
8363              Calling forget_old_reloads_1 is a waste of effort if
8364              REG_RTX is also the output register.
8365
8366              If we know that REG_RTX holds the value of a pseudo
8367              register, the code after the call will record that fact.  */
8368           if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8369             forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8370
8371           if (!HARD_REGISTER_NUM_P (out_regno))
8372             {
8373               rtx src_reg, store_insn = NULL_RTX;
8374
8375               reg_last_reload_reg[out_regno] = 0;
8376
8377               /* If we can find a hard register that is stored, record
8378                  the storing insn so that we may delete this insn with
8379                  delete_output_reload.  */
8380               src_reg = reload_reg_rtx_for_output[r];
8381
8382               if (src_reg)
8383                 {
8384                   if (reload_reg_rtx_reaches_end_p (src_reg, r))
8385                     store_insn = new_spill_reg_store[REGNO (src_reg)];
8386                   else
8387                     src_reg = NULL_RTX;
8388                 }
8389               else
8390                 {
8391                   /* If this is an optional reload, try to find the
8392                      source reg from an input reload.  */
8393                   rtx set = single_set (insn);
8394                   if (set && SET_DEST (set) == rld[r].out)
8395                     {
8396                       int k;
8397
8398                       src_reg = SET_SRC (set);
8399                       store_insn = insn;
8400                       for (k = 0; k < n_reloads; k++)
8401                         {
8402                           if (rld[k].in == src_reg)
8403                             {
8404                               src_reg = reload_reg_rtx_for_input[k];
8405                               break;
8406                             }
8407                         }
8408                     }
8409                 }
8410               if (src_reg && REG_P (src_reg)
8411                   && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8412                 {
8413                   int src_regno, src_nregs, k;
8414                   rtx note;
8415
8416                   gcc_assert (GET_MODE (src_reg) == mode);
8417                   src_regno = REGNO (src_reg);
8418                   src_nregs = hard_regno_nregs[src_regno][mode];
8419                   /* The place where to find a death note varies with
8420                      PRESERVE_DEATH_INFO_REGNO_P .  The condition is not
8421                      necessarily checked exactly in the code that moves
8422                      notes, so just check both locations.  */
8423                   note = find_regno_note (insn, REG_DEAD, src_regno);
8424                   if (! note && store_insn)
8425                     note = find_regno_note (store_insn, REG_DEAD, src_regno);
8426                   for (k = 0; k < src_nregs; k++)
8427                     {
8428                       spill_reg_store[src_regno + k] = store_insn;
8429                       spill_reg_stored_to[src_regno + k] = out;
8430                       reg_reloaded_contents[src_regno + k] = out_regno;
8431                       reg_reloaded_insn[src_regno + k] = store_insn;
8432                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8433                       SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8434                       if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8435                                                           mode))
8436                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8437                                           src_regno + k);
8438                       else
8439                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8440                                             src_regno + k);
8441                       SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8442                       if (note)
8443                         SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8444                       else
8445                         CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8446                     }
8447                   reg_last_reload_reg[out_regno] = src_reg;
8448                   /* We have to set reg_has_output_reload here, or else
8449                      forget_old_reloads_1 will clear reg_last_reload_reg
8450                      right away.  */
8451                   SET_REGNO_REG_SET (&reg_has_output_reload,
8452                                      out_regno);
8453                 }
8454             }
8455           else
8456             {
8457               int k, out_nregs = hard_regno_nregs[out_regno][mode];
8458
8459               for (k = 0; k < out_nregs; k++)
8460                 reg_last_reload_reg[out_regno + k] = 0;
8461             }
8462         }
8463     }
8464   IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8465 }
8466 \f
8467 /* Go through the motions to emit INSN and test if it is strictly valid.
8468    Return the emitted insn if valid, else return NULL.  */
8469
8470 static rtx
8471 emit_insn_if_valid_for_reload (rtx insn)
8472 {
8473   rtx last = get_last_insn ();
8474   int code;
8475
8476   insn = emit_insn (insn);
8477   code = recog_memoized (insn);
8478
8479   if (code >= 0)
8480     {
8481       extract_insn (insn);
8482       /* We want constrain operands to treat this insn strictly in its
8483          validity determination, i.e., the way it would after reload has
8484          completed.  */
8485       if (constrain_operands (1))
8486         return insn;
8487     }
8488
8489   delete_insns_since (last);
8490   return NULL;
8491 }
8492
8493 /* Emit code to perform a reload from IN (which may be a reload register) to
8494    OUT (which may also be a reload register).  IN or OUT is from operand
8495    OPNUM with reload type TYPE.
8496
8497    Returns first insn emitted.  */
8498
8499 static rtx
8500 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8501 {
8502   rtx last = get_last_insn ();
8503   rtx tem;
8504 #ifdef SECONDARY_MEMORY_NEEDED
8505   rtx tem1, tem2;
8506 #endif
8507
8508   /* If IN is a paradoxical SUBREG, remove it and try to put the
8509      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
8510   if (!strip_paradoxical_subreg (&in, &out))
8511     strip_paradoxical_subreg (&out, &in);
8512
8513   /* How to do this reload can get quite tricky.  Normally, we are being
8514      asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8515      register that didn't get a hard register.  In that case we can just
8516      call emit_move_insn.
8517
8518      We can also be asked to reload a PLUS that adds a register or a MEM to
8519      another register, constant or MEM.  This can occur during frame pointer
8520      elimination and while reloading addresses.  This case is handled by
8521      trying to emit a single insn to perform the add.  If it is not valid,
8522      we use a two insn sequence.
8523
8524      Or we can be asked to reload an unary operand that was a fragment of
8525      an addressing mode, into a register.  If it isn't recognized as-is,
8526      we try making the unop operand and the reload-register the same:
8527      (set reg:X (unop:X expr:Y))
8528      -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8529
8530      Finally, we could be called to handle an 'o' constraint by putting
8531      an address into a register.  In that case, we first try to do this
8532      with a named pattern of "reload_load_address".  If no such pattern
8533      exists, we just emit a SET insn and hope for the best (it will normally
8534      be valid on machines that use 'o').
8535
8536      This entire process is made complex because reload will never
8537      process the insns we generate here and so we must ensure that
8538      they will fit their constraints and also by the fact that parts of
8539      IN might be being reloaded separately and replaced with spill registers.
8540      Because of this, we are, in some sense, just guessing the right approach
8541      here.  The one listed above seems to work.
8542
8543      ??? At some point, this whole thing needs to be rethought.  */
8544
8545   if (GET_CODE (in) == PLUS
8546       && (REG_P (XEXP (in, 0))
8547           || GET_CODE (XEXP (in, 0)) == SUBREG
8548           || MEM_P (XEXP (in, 0)))
8549       && (REG_P (XEXP (in, 1))
8550           || GET_CODE (XEXP (in, 1)) == SUBREG
8551           || CONSTANT_P (XEXP (in, 1))
8552           || MEM_P (XEXP (in, 1))))
8553     {
8554       /* We need to compute the sum of a register or a MEM and another
8555          register, constant, or MEM, and put it into the reload
8556          register.  The best possible way of doing this is if the machine
8557          has a three-operand ADD insn that accepts the required operands.
8558
8559          The simplest approach is to try to generate such an insn and see if it
8560          is recognized and matches its constraints.  If so, it can be used.
8561
8562          It might be better not to actually emit the insn unless it is valid,
8563          but we need to pass the insn as an operand to `recog' and
8564          `extract_insn' and it is simpler to emit and then delete the insn if
8565          not valid than to dummy things up.  */
8566
8567       rtx op0, op1, tem, insn;
8568       enum insn_code code;
8569
8570       op0 = find_replacement (&XEXP (in, 0));
8571       op1 = find_replacement (&XEXP (in, 1));
8572
8573       /* Since constraint checking is strict, commutativity won't be
8574          checked, so we need to do that here to avoid spurious failure
8575          if the add instruction is two-address and the second operand
8576          of the add is the same as the reload reg, which is frequently
8577          the case.  If the insn would be A = B + A, rearrange it so
8578          it will be A = A + B as constrain_operands expects.  */
8579
8580       if (REG_P (XEXP (in, 1))
8581           && REGNO (out) == REGNO (XEXP (in, 1)))
8582         tem = op0, op0 = op1, op1 = tem;
8583
8584       if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8585         in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8586
8587       insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8588       if (insn)
8589         return insn;
8590
8591       /* If that failed, we must use a conservative two-insn sequence.
8592
8593          Use a move to copy one operand into the reload register.  Prefer
8594          to reload a constant, MEM or pseudo since the move patterns can
8595          handle an arbitrary operand.  If OP1 is not a constant, MEM or
8596          pseudo and OP1 is not a valid operand for an add instruction, then
8597          reload OP1.
8598
8599          After reloading one of the operands into the reload register, add
8600          the reload register to the output register.
8601
8602          If there is another way to do this for a specific machine, a
8603          DEFINE_PEEPHOLE should be specified that recognizes the sequence
8604          we emit below.  */
8605
8606       code = optab_handler (add_optab, GET_MODE (out));
8607
8608       if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8609           || (REG_P (op1)
8610               && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8611           || (code != CODE_FOR_nothing
8612               && !insn_operand_matches (code, 2, op1)))
8613         tem = op0, op0 = op1, op1 = tem;
8614
8615       gen_reload (out, op0, opnum, type);
8616
8617       /* If OP0 and OP1 are the same, we can use OUT for OP1.
8618          This fixes a problem on the 32K where the stack pointer cannot
8619          be used as an operand of an add insn.  */
8620
8621       if (rtx_equal_p (op0, op1))
8622         op1 = out;
8623
8624       insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8625       if (insn)
8626         {
8627           /* Add a REG_EQUIV note so that find_equiv_reg can find it.  */
8628           set_dst_reg_note (insn, REG_EQUIV, in, out);
8629           return insn;
8630         }
8631
8632       /* If that failed, copy the address register to the reload register.
8633          Then add the constant to the reload register.  */
8634
8635       gcc_assert (!reg_overlap_mentioned_p (out, op0));
8636       gen_reload (out, op1, opnum, type);
8637       insn = emit_insn (gen_add2_insn (out, op0));
8638       set_dst_reg_note (insn, REG_EQUIV, in, out);
8639     }
8640
8641 #ifdef SECONDARY_MEMORY_NEEDED
8642   /* If we need a memory location to do the move, do it that way.  */
8643   else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8644             (REG_P (tem1) && REG_P (tem2)))
8645            && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8646            && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8647            && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1)),
8648                                        REGNO_REG_CLASS (REGNO (tem2)),
8649                                        GET_MODE (out)))
8650     {
8651       /* Get the memory to use and rewrite both registers to its mode.  */
8652       rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8653
8654       if (GET_MODE (loc) != GET_MODE (out))
8655         out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8656
8657       if (GET_MODE (loc) != GET_MODE (in))
8658         in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8659
8660       gen_reload (loc, in, opnum, type);
8661       gen_reload (out, loc, opnum, type);
8662     }
8663 #endif
8664   else if (REG_P (out) && UNARY_P (in))
8665     {
8666       rtx insn;
8667       rtx op1;
8668       rtx out_moded;
8669       rtx set;
8670
8671       op1 = find_replacement (&XEXP (in, 0));
8672       if (op1 != XEXP (in, 0))
8673         in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8674
8675       /* First, try a plain SET.  */
8676       set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8677       if (set)
8678         return set;
8679
8680       /* If that failed, move the inner operand to the reload
8681          register, and try the same unop with the inner expression
8682          replaced with the reload register.  */
8683
8684       if (GET_MODE (op1) != GET_MODE (out))
8685         out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8686       else
8687         out_moded = out;
8688
8689       gen_reload (out_moded, op1, opnum, type);
8690
8691       insn
8692         = gen_rtx_SET (VOIDmode, out,
8693                        gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8694                                       out_moded));
8695       insn = emit_insn_if_valid_for_reload (insn);
8696       if (insn)
8697         {
8698           set_unique_reg_note (insn, REG_EQUIV, in);
8699           return insn;
8700         }
8701
8702       fatal_insn ("failure trying to reload:", set);
8703     }
8704   /* If IN is a simple operand, use gen_move_insn.  */
8705   else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8706     {
8707       tem = emit_insn (gen_move_insn (out, in));
8708       /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note.  */
8709       mark_jump_label (in, tem, 0);
8710     }
8711
8712 #ifdef HAVE_reload_load_address
8713   else if (HAVE_reload_load_address)
8714     emit_insn (gen_reload_load_address (out, in));
8715 #endif
8716
8717   /* Otherwise, just write (set OUT IN) and hope for the best.  */
8718   else
8719     emit_insn (gen_rtx_SET (VOIDmode, out, in));
8720
8721   /* Return the first insn emitted.
8722      We can not just return get_last_insn, because there may have
8723      been multiple instructions emitted.  Also note that gen_move_insn may
8724      emit more than one insn itself, so we can not assume that there is one
8725      insn emitted per emit_insn_before call.  */
8726
8727   return last ? NEXT_INSN (last) : get_insns ();
8728 }
8729 \f
8730 /* Delete a previously made output-reload whose result we now believe
8731    is not needed.  First we double-check.
8732
8733    INSN is the insn now being processed.
8734    LAST_RELOAD_REG is the hard register number for which we want to delete
8735    the last output reload.
8736    J is the reload-number that originally used REG.  The caller has made
8737    certain that reload J doesn't use REG any longer for input.
8738    NEW_RELOAD_REG is reload register that reload J is using for REG.  */
8739
8740 static void
8741 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8742 {
8743   rtx output_reload_insn = spill_reg_store[last_reload_reg];
8744   rtx reg = spill_reg_stored_to[last_reload_reg];
8745   int k;
8746   int n_occurrences;
8747   int n_inherited = 0;
8748   rtx i1;
8749   rtx substed;
8750   unsigned regno;
8751   int nregs;
8752
8753   /* It is possible that this reload has been only used to set another reload
8754      we eliminated earlier and thus deleted this instruction too.  */
8755   if (INSN_DELETED_P (output_reload_insn))
8756     return;
8757
8758   /* Get the raw pseudo-register referred to.  */
8759
8760   while (GET_CODE (reg) == SUBREG)
8761     reg = SUBREG_REG (reg);
8762   substed = reg_equiv_memory_loc (REGNO (reg));
8763
8764   /* This is unsafe if the operand occurs more often in the current
8765      insn than it is inherited.  */
8766   for (k = n_reloads - 1; k >= 0; k--)
8767     {
8768       rtx reg2 = rld[k].in;
8769       if (! reg2)
8770         continue;
8771       if (MEM_P (reg2) || reload_override_in[k])
8772         reg2 = rld[k].in_reg;
8773 #ifdef AUTO_INC_DEC
8774       if (rld[k].out && ! rld[k].out_reg)
8775         reg2 = XEXP (rld[k].in_reg, 0);
8776 #endif
8777       while (GET_CODE (reg2) == SUBREG)
8778         reg2 = SUBREG_REG (reg2);
8779       if (rtx_equal_p (reg2, reg))
8780         {
8781           if (reload_inherited[k] || reload_override_in[k] || k == j)
8782             n_inherited++;
8783           else
8784             return;
8785         }
8786     }
8787   n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8788   if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8789     n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8790                                         reg, 0);
8791   if (substed)
8792     n_occurrences += count_occurrences (PATTERN (insn),
8793                                         eliminate_regs (substed, VOIDmode,
8794                                                         NULL_RTX), 0);
8795   for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8796     {
8797       gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8798       n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8799     }
8800   if (n_occurrences > n_inherited)
8801     return;
8802
8803   regno = REGNO (reg);
8804   if (regno >= FIRST_PSEUDO_REGISTER)
8805     nregs = 1;
8806   else
8807     nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8808
8809   /* If the pseudo-reg we are reloading is no longer referenced
8810      anywhere between the store into it and here,
8811      and we're within the same basic block, then the value can only
8812      pass through the reload reg and end up here.
8813      Otherwise, give up--return.  */
8814   for (i1 = NEXT_INSN (output_reload_insn);
8815        i1 != insn; i1 = NEXT_INSN (i1))
8816     {
8817       if (NOTE_INSN_BASIC_BLOCK_P (i1))
8818         return;
8819       if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8820           && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8821         {
8822           /* If this is USE in front of INSN, we only have to check that
8823              there are no more references than accounted for by inheritance.  */
8824           while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8825             {
8826               n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8827               i1 = NEXT_INSN (i1);
8828             }
8829           if (n_occurrences <= n_inherited && i1 == insn)
8830             break;
8831           return;
8832         }
8833     }
8834
8835   /* We will be deleting the insn.  Remove the spill reg information.  */
8836   for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8837     {
8838       spill_reg_store[last_reload_reg + k] = 0;
8839       spill_reg_stored_to[last_reload_reg + k] = 0;
8840     }
8841
8842   /* The caller has already checked that REG dies or is set in INSN.
8843      It has also checked that we are optimizing, and thus some
8844      inaccuracies in the debugging information are acceptable.
8845      So we could just delete output_reload_insn.  But in some cases
8846      we can improve the debugging information without sacrificing
8847      optimization - maybe even improving the code: See if the pseudo
8848      reg has been completely replaced with reload regs.  If so, delete
8849      the store insn and forget we had a stack slot for the pseudo.  */
8850   if (rld[j].out != rld[j].in
8851       && REG_N_DEATHS (REGNO (reg)) == 1
8852       && REG_N_SETS (REGNO (reg)) == 1
8853       && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8854       && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8855     {
8856       rtx i2;
8857
8858       /* We know that it was used only between here and the beginning of
8859          the current basic block.  (We also know that the last use before
8860          INSN was the output reload we are thinking of deleting, but never
8861          mind that.)  Search that range; see if any ref remains.  */
8862       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8863         {
8864           rtx set = single_set (i2);
8865
8866           /* Uses which just store in the pseudo don't count,
8867              since if they are the only uses, they are dead.  */
8868           if (set != 0 && SET_DEST (set) == reg)
8869             continue;
8870           if (LABEL_P (i2)
8871               || JUMP_P (i2))
8872             break;
8873           if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8874               && reg_mentioned_p (reg, PATTERN (i2)))
8875             {
8876               /* Some other ref remains; just delete the output reload we
8877                  know to be dead.  */
8878               delete_address_reloads (output_reload_insn, insn);
8879               delete_insn (output_reload_insn);
8880               return;
8881             }
8882         }
8883
8884       /* Delete the now-dead stores into this pseudo.  Note that this
8885          loop also takes care of deleting output_reload_insn.  */
8886       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8887         {
8888           rtx set = single_set (i2);
8889
8890           if (set != 0 && SET_DEST (set) == reg)
8891             {
8892               delete_address_reloads (i2, insn);
8893               delete_insn (i2);
8894             }
8895           if (LABEL_P (i2)
8896               || JUMP_P (i2))
8897             break;
8898         }
8899
8900       /* For the debugging info, say the pseudo lives in this reload reg.  */
8901       reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8902       if (ira_conflicts_p)
8903         /* Inform IRA about the change.  */
8904         ira_mark_allocation_change (REGNO (reg));
8905       alter_reg (REGNO (reg), -1, false);
8906     }
8907   else
8908     {
8909       delete_address_reloads (output_reload_insn, insn);
8910       delete_insn (output_reload_insn);
8911     }
8912 }
8913
8914 /* We are going to delete DEAD_INSN.  Recursively delete loads of
8915    reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8916    CURRENT_INSN is being reloaded, so we have to check its reloads too.  */
8917 static void
8918 delete_address_reloads (rtx dead_insn, rtx current_insn)
8919 {
8920   rtx set = single_set (dead_insn);
8921   rtx set2, dst, prev, next;
8922   if (set)
8923     {
8924       rtx dst = SET_DEST (set);
8925       if (MEM_P (dst))
8926         delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8927     }
8928   /* If we deleted the store from a reloaded post_{in,de}c expression,
8929      we can delete the matching adds.  */
8930   prev = PREV_INSN (dead_insn);
8931   next = NEXT_INSN (dead_insn);
8932   if (! prev || ! next)
8933     return;
8934   set = single_set (next);
8935   set2 = single_set (prev);
8936   if (! set || ! set2
8937       || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8938       || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8939       || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8940     return;
8941   dst = SET_DEST (set);
8942   if (! rtx_equal_p (dst, SET_DEST (set2))
8943       || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8944       || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8945       || (INTVAL (XEXP (SET_SRC (set), 1))
8946           != -INTVAL (XEXP (SET_SRC (set2), 1))))
8947     return;
8948   delete_related_insns (prev);
8949   delete_related_insns (next);
8950 }
8951
8952 /* Subfunction of delete_address_reloads: process registers found in X.  */
8953 static void
8954 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8955 {
8956   rtx prev, set, dst, i2;
8957   int i, j;
8958   enum rtx_code code = GET_CODE (x);
8959
8960   if (code != REG)
8961     {
8962       const char *fmt = GET_RTX_FORMAT (code);
8963       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8964         {
8965           if (fmt[i] == 'e')
8966             delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8967           else if (fmt[i] == 'E')
8968             {
8969               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8970                 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8971                                           current_insn);
8972             }
8973         }
8974       return;
8975     }
8976
8977   if (spill_reg_order[REGNO (x)] < 0)
8978     return;
8979
8980   /* Scan backwards for the insn that sets x.  This might be a way back due
8981      to inheritance.  */
8982   for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8983     {
8984       code = GET_CODE (prev);
8985       if (code == CODE_LABEL || code == JUMP_INSN)
8986         return;
8987       if (!INSN_P (prev))
8988         continue;
8989       if (reg_set_p (x, PATTERN (prev)))
8990         break;
8991       if (reg_referenced_p (x, PATTERN (prev)))
8992         return;
8993     }
8994   if (! prev || INSN_UID (prev) < reload_first_uid)
8995     return;
8996   /* Check that PREV only sets the reload register.  */
8997   set = single_set (prev);
8998   if (! set)
8999     return;
9000   dst = SET_DEST (set);
9001   if (!REG_P (dst)
9002       || ! rtx_equal_p (dst, x))
9003     return;
9004   if (! reg_set_p (dst, PATTERN (dead_insn)))
9005     {
9006       /* Check if DST was used in a later insn -
9007          it might have been inherited.  */
9008       for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9009         {
9010           if (LABEL_P (i2))
9011             break;
9012           if (! INSN_P (i2))
9013             continue;
9014           if (reg_referenced_p (dst, PATTERN (i2)))
9015             {
9016               /* If there is a reference to the register in the current insn,
9017                  it might be loaded in a non-inherited reload.  If no other
9018                  reload uses it, that means the register is set before
9019                  referenced.  */
9020               if (i2 == current_insn)
9021                 {
9022                   for (j = n_reloads - 1; j >= 0; j--)
9023                     if ((rld[j].reg_rtx == dst && reload_inherited[j])
9024                         || reload_override_in[j] == dst)
9025                       return;
9026                   for (j = n_reloads - 1; j >= 0; j--)
9027                     if (rld[j].in && rld[j].reg_rtx == dst)
9028                       break;
9029                   if (j >= 0)
9030                     break;
9031                 }
9032               return;
9033             }
9034           if (JUMP_P (i2))
9035             break;
9036           /* If DST is still live at CURRENT_INSN, check if it is used for
9037              any reload.  Note that even if CURRENT_INSN sets DST, we still
9038              have to check the reloads.  */
9039           if (i2 == current_insn)
9040             {
9041               for (j = n_reloads - 1; j >= 0; j--)
9042                 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9043                     || reload_override_in[j] == dst)
9044                   return;
9045               /* ??? We can't finish the loop here, because dst might be
9046                  allocated to a pseudo in this block if no reload in this
9047                  block needs any of the classes containing DST - see
9048                  spill_hard_reg.  There is no easy way to tell this, so we
9049                  have to scan till the end of the basic block.  */
9050             }
9051           if (reg_set_p (dst, PATTERN (i2)))
9052             break;
9053         }
9054     }
9055   delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9056   reg_reloaded_contents[REGNO (dst)] = -1;
9057   delete_insn (prev);
9058 }
9059 \f
9060 /* Output reload-insns to reload VALUE into RELOADREG.
9061    VALUE is an autoincrement or autodecrement RTX whose operand
9062    is a register or memory location;
9063    so reloading involves incrementing that location.
9064    IN is either identical to VALUE, or some cheaper place to reload from.
9065
9066    INC_AMOUNT is the number to increment or decrement by (always positive).
9067    This cannot be deduced from VALUE.  */
9068
9069 static void
9070 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9071 {
9072   /* REG or MEM to be copied and incremented.  */
9073   rtx incloc = find_replacement (&XEXP (value, 0));
9074   /* Nonzero if increment after copying.  */
9075   int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9076               || GET_CODE (value) == POST_MODIFY);
9077   rtx last;
9078   rtx inc;
9079   rtx add_insn;
9080   int code;
9081   rtx real_in = in == value ? incloc : in;
9082
9083   /* No hard register is equivalent to this register after
9084      inc/dec operation.  If REG_LAST_RELOAD_REG were nonzero,
9085      we could inc/dec that register as well (maybe even using it for
9086      the source), but I'm not sure it's worth worrying about.  */
9087   if (REG_P (incloc))
9088     reg_last_reload_reg[REGNO (incloc)] = 0;
9089
9090   if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9091     {
9092       gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9093       inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9094     }
9095   else
9096     {
9097       if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9098         inc_amount = -inc_amount;
9099
9100       inc = GEN_INT (inc_amount);
9101     }
9102
9103   /* If this is post-increment, first copy the location to the reload reg.  */
9104   if (post && real_in != reloadreg)
9105     emit_insn (gen_move_insn (reloadreg, real_in));
9106
9107   if (in == value)
9108     {
9109       /* See if we can directly increment INCLOC.  Use a method similar to
9110          that in gen_reload.  */
9111
9112       last = get_last_insn ();
9113       add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9114                                          gen_rtx_PLUS (GET_MODE (incloc),
9115                                                        incloc, inc)));
9116
9117       code = recog_memoized (add_insn);
9118       if (code >= 0)
9119         {
9120           extract_insn (add_insn);
9121           if (constrain_operands (1))
9122             {
9123               /* If this is a pre-increment and we have incremented the value
9124                  where it lives, copy the incremented value to RELOADREG to
9125                  be used as an address.  */
9126
9127               if (! post)
9128                 emit_insn (gen_move_insn (reloadreg, incloc));
9129               return;
9130             }
9131         }
9132       delete_insns_since (last);
9133     }
9134
9135   /* If couldn't do the increment directly, must increment in RELOADREG.
9136      The way we do this depends on whether this is pre- or post-increment.
9137      For pre-increment, copy INCLOC to the reload register, increment it
9138      there, then save back.  */
9139
9140   if (! post)
9141     {
9142       if (in != reloadreg)
9143         emit_insn (gen_move_insn (reloadreg, real_in));
9144       emit_insn (gen_add2_insn (reloadreg, inc));
9145       emit_insn (gen_move_insn (incloc, reloadreg));
9146     }
9147   else
9148     {
9149       /* Postincrement.
9150          Because this might be a jump insn or a compare, and because RELOADREG
9151          may not be available after the insn in an input reload, we must do
9152          the incrementation before the insn being reloaded for.
9153
9154          We have already copied IN to RELOADREG.  Increment the copy in
9155          RELOADREG, save that back, then decrement RELOADREG so it has
9156          the original value.  */
9157
9158       emit_insn (gen_add2_insn (reloadreg, inc));
9159       emit_insn (gen_move_insn (incloc, reloadreg));
9160       if (CONST_INT_P (inc))
9161         emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9162       else
9163         emit_insn (gen_sub2_insn (reloadreg, inc));
9164     }
9165 }
9166 \f
9167 #ifdef AUTO_INC_DEC
9168 static void
9169 add_auto_inc_notes (rtx insn, rtx x)
9170 {
9171   enum rtx_code code = GET_CODE (x);
9172   const char *fmt;
9173   int i, j;
9174
9175   if (code == MEM && auto_inc_p (XEXP (x, 0)))
9176     {
9177       add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9178       return;
9179     }
9180
9181   /* Scan all the operand sub-expressions.  */
9182   fmt = GET_RTX_FORMAT (code);
9183   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9184     {
9185       if (fmt[i] == 'e')
9186         add_auto_inc_notes (insn, XEXP (x, i));
9187       else if (fmt[i] == 'E')
9188         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9189           add_auto_inc_notes (insn, XVECEXP (x, i, j));
9190     }
9191 }
9192 #endif