gcc/config/arm/arm-protos.h

   1 /* Prototypes for exported functions defined in arm.c and pe.c
   2    Copyright (C) 1999-2016 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rearnsha@arm.com)
   4    Minor hacks by Nick Clifton (nickc@cygnus.com)
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    GCC is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_ARM_PROTOS_H
  23 #define GCC_ARM_PROTOS_H
  24
  25 extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
  26 extern int use_return_insn (int, rtx);
  27 extern bool use_simple_return_p (void);
  28 extern enum reg_class arm_regno_class (int);
  29 extern void arm_load_pic_register (unsigned long);
  30 extern int arm_volatile_func (void);
  31 extern void arm_expand_prologue (void);
  32 extern void arm_expand_epilogue (bool);
  33 extern void arm_declare_function_name (FILE *, const char *, tree);
  34 extern void thumb2_expand_return (bool);
  35 extern const char *arm_strip_name_encoding (const char *);
  36 extern void arm_asm_output_labelref (FILE *, const char *);
  37 extern void thumb2_asm_output_opcode (FILE *);
  38 extern unsigned long arm_current_func_type (void);
  39 extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int,
  40                                                              unsigned int);
  41 extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int,
  42                                                                unsigned int);
  43 extern unsigned int arm_dbx_register_number (unsigned int);
  44 extern void arm_output_fn_unwind (FILE *, bool);
  45
  46 extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget
  47                                ATTRIBUTE_UNUSED, enum machine_mode mode
  48                                ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED);
  49 extern tree arm_builtin_decl (unsigned code, bool initialize_p
  50                               ATTRIBUTE_UNUSED);
  51 extern void arm_init_builtins (void);
  52 extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
  53
  54 #ifdef RTX_CODE
  55 extern bool arm_vector_mode_supported_p (machine_mode);
  56 extern bool arm_small_register_classes_for_mode_p (machine_mode);
  57 extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
  58 extern bool arm_modes_tieable_p (machine_mode, machine_mode);
  59 extern int const_ok_for_arm (HOST_WIDE_INT);
  60 extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
  61 extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
  62 extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
  63                                HOST_WIDE_INT, rtx, rtx, int);
  64 extern int legitimate_pic_operand_p (rtx);
  65 extern rtx legitimize_pic_address (rtx, machine_mode, rtx);
  66 extern rtx legitimize_tls_address (rtx, rtx);
  67 extern bool arm_legitimate_address_p (machine_mode, rtx, bool);
  68 extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int);
  69 extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT);
  70 extern int thumb1_legitimate_address_p (machine_mode, rtx, int);
  71 extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode,
  72                                  bool, bool);
  73 extern int arm_const_double_rtx (rtx);
  74 extern int vfp3_const_double_rtx (rtx);
  75 extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *);
  76 extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *,
  77                                            int *);
  78 extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *,
  79                                            int *, bool);
  80 extern char *neon_output_logic_immediate (const char *, rtx *,
  81                                           machine_mode, int, int);
  82 extern char *neon_output_shift_immediate (const char *, char, rtx *,
  83                                           machine_mode, int, bool);
  84 extern void neon_pairwise_reduce (rtx, rtx, machine_mode,
  85                                   rtx (*) (rtx, rtx, rtx));
  86 extern rtx neon_make_constant (rtx);
  87 extern tree arm_builtin_vectorized_function (unsigned int, tree, tree);
  88 extern void neon_expand_vector_init (rtx, rtx);
  89 extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
  90 extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
  91 extern HOST_WIDE_INT neon_element_bits (machine_mode);
  92 extern void neon_emit_pair_result_insn (machine_mode,
  93                                         rtx (*) (rtx, rtx, rtx, rtx),
  94                                         rtx, rtx, rtx);
  95 extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int);
  96 extern void neon_split_vcombine (rtx op[3]);
  97 extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx,
  98                                                      bool);
  99 extern bool arm_tls_referenced_p (rtx);
 100
 101 extern int arm_coproc_mem_operand (rtx, bool);
 102 extern int neon_vector_mem_operand (rtx, int, bool);
 103 extern int neon_struct_mem_operand (rtx);
 104
 105 extern int tls_mentioned_p (rtx);
 106 extern int symbol_mentioned_p (rtx);
 107 extern int label_mentioned_p (rtx);
 108 extern RTX_CODE minmax_code (rtx);
 109 extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
 110 extern int adjacent_mem_locations (rtx, rtx);
 111 extern bool gen_ldm_seq (rtx *, int, bool);
 112 extern bool gen_stm_seq (rtx *, int);
 113 extern bool gen_const_stm_seq (rtx *, int);
 114 extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
 115 extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
 116 extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT);
 117 extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool);
 118 extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool);
 119 extern int arm_gen_movmemqi (rtx *);
 120 extern bool gen_movmem_ldrd_strd (rtx *);
 121 extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
 122 extern machine_mode arm_select_dominance_cc_mode (rtx, rtx,
 123                                                        HOST_WIDE_INT);
 124 extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
 125 extern rtx arm_gen_return_addr_mask (void);
 126 extern void arm_reload_in_hi (rtx *);
 127 extern void arm_reload_out_hi (rtx *);
 128 extern int arm_max_const_double_inline_cost (void);
 129 extern int arm_const_double_inline_cost (rtx);
 130 extern bool arm_const_double_by_parts (rtx);
 131 extern bool arm_const_double_by_immediates (rtx);
 132 extern void arm_emit_call_insn (rtx, rtx, bool);
 133 extern const char *output_call (rtx *);
 134 void arm_emit_movpair (rtx, rtx);
 135 extern const char *output_mov_long_double_arm_from_arm (rtx *);
 136 extern const char *output_move_double (rtx *, bool, int *count);
 137 extern const char *output_move_quad (rtx *);
 138 extern int arm_count_output_move_double_insns (rtx *);
 139 extern const char *output_move_vfp (rtx *operands);
 140 extern const char *output_move_neon (rtx *operands);
 141 extern int arm_attr_length_move_neon (rtx_insn *);
 142 extern int arm_address_offset_is_imm (rtx_insn *);
 143 extern const char *output_add_immediate (rtx *);
 144 extern const char *arithmetic_instr (rtx, int);
 145 extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
 146 extern const char *output_return_instruction (rtx, bool, bool, bool);
 147 extern const char *output_probe_stack_range (rtx, rtx);
 148 extern void arm_poke_function_name (FILE *, const char *);
 149 extern void arm_final_prescan_insn (rtx_insn *);
 150 extern int arm_debugger_arg_offset (int, rtx);
 151 extern bool arm_is_long_call_p (tree);
 152 extern int    arm_emit_vector_const (FILE *, rtx);
 153 extern void arm_emit_fp16_const (rtx c);
 154 extern const char * arm_output_load_gr (rtx *);
 155 extern const char *vfp_output_vstmd (rtx *);
 156 extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
 157 extern void arm_set_return_address (rtx, rtx);
 158 extern int arm_eliminable_register (rtx);
 159 extern const char *arm_output_shift(rtx *, int);
 160 extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool);
 161 extern const char *arm_output_iwmmxt_tinsr (rtx *);
 162 extern unsigned int arm_sync_loop_insns (rtx , rtx *);
 163 extern int arm_attr_length_push_multi(rtx, rtx);
 164 extern void arm_expand_compare_and_swap (rtx op[]);
 165 extern void arm_split_compare_and_swap (rtx op[]);
 166 extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
 167 extern rtx arm_load_tp (rtx);
 168
 169 #if defined TREE_CODE
 170 extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
 171 extern bool arm_pad_arg_upward (machine_mode, const_tree);
 172 extern bool arm_pad_reg_upward (machine_mode, tree, int);
 173 #endif
 174 extern int arm_apply_result_size (void);
 175
 176 #endif /* RTX_CODE */
 177
 178 /* Thumb functions.  */
 179 extern void arm_init_expanders (void);
 180 extern const char *thumb1_unexpanded_epilogue (void);
 181 extern void thumb1_expand_prologue (void);
 182 extern void thumb1_expand_epilogue (void);
 183 extern const char *thumb1_output_interwork (void);
 184 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
 185 #ifdef RTX_CODE
 186 extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
 187 extern void thumb1_final_prescan_insn (rtx_insn *);
 188 extern void thumb2_final_prescan_insn (rtx_insn *);
 189 extern const char *thumb_load_double_from_address (rtx *);
 190 extern const char *thumb_output_move_mem_multiple (int, rtx *);
 191 extern const char *thumb_call_via_reg (rtx);
 192 extern void thumb_expand_movmemqi (rtx *);
 193 extern rtx arm_return_addr (int, rtx);
 194 extern void thumb_reload_out_hi (rtx *);
 195 extern void thumb_reload_in_hi (rtx *);
 196 extern void thumb_set_return_address (rtx, rtx);
 197 extern const char *thumb1_output_casesi (rtx *);
 198 extern const char *thumb2_output_casesi (rtx *);
 199 #endif
 200
 201 /* Defined in pe.c.  */
 202 extern int arm_dllexport_name_p (const char *);
 203 extern int arm_dllimport_name_p (const char *);
 204
 205 #ifdef TREE_CODE
 206 extern void arm_pe_unique_section (tree, int);
 207 extern void arm_pe_encode_section_info (tree, rtx, int);
 208 extern int arm_dllexport_p (tree);
 209 extern int arm_dllimport_p (tree);
 210 extern void arm_mark_dllexport (tree);
 211 extern void arm_mark_dllimport (tree);
 212 extern bool arm_change_mode_p (tree);
 213 #endif
 214
 215 extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *,
 216                                              struct gcc_options *);
 217 extern void arm_pr_long_calls (struct cpp_reader *);
 218 extern void arm_pr_no_long_calls (struct cpp_reader *);
 219 extern void arm_pr_long_calls_off (struct cpp_reader *);
 220
 221 extern const char *arm_mangle_type (const_tree);
 222 extern const char *arm_mangle_builtin_type (const_tree);
 223
 224 extern void arm_order_regs_for_local_alloc (void);
 225
 226 extern int arm_max_conditional_execute ();
 227
 228 /* Vectorizer cost model implementation.  */
 229 struct cpu_vec_costs {
 230   const int scalar_stmt_cost;   /* Cost of any scalar operation, excluding
 231                                    load and store.  */
 232   const int scalar_load_cost;   /* Cost of scalar load.  */
 233   const int scalar_store_cost;  /* Cost of scalar store.  */
 234   const int vec_stmt_cost;      /* Cost of any vector operation, excluding
 235                                    load, store, vector-to-scalar and
 236                                    scalar-to-vector operation.  */
 237   const int vec_to_scalar_cost;    /* Cost of vect-to-scalar operation.  */
 238   const int scalar_to_vec_cost;    /* Cost of scalar-to-vector operation.  */
 239   const int vec_align_load_cost;   /* Cost of aligned vector load.  */
 240   const int vec_unalign_load_cost; /* Cost of unaligned vector load.  */
 241   const int vec_unalign_store_cost; /* Cost of unaligned vector load.  */
 242   const int vec_store_cost;        /* Cost of vector store.  */
 243   const int cond_taken_branch_cost;    /* Cost of taken branch for vectorizer
 244                                           cost model.  */
 245   const int cond_not_taken_branch_cost;/* Cost of not taken branch for
 246                                           vectorizer cost model.  */
 247 };
 248
 249 #ifdef RTX_CODE
 250 /* This needs to be here because we need RTX_CODE and similar.  */
 251
 252 struct cpu_cost_table;
 253
 254 /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this
 255    structure is modified.  */
 256
 257 struct tune_params
 258 {
 259   bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
 260   const struct cpu_cost_table *insn_extra_cost;
 261   bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
 262   int (*branch_cost) (bool, bool);
 263   /* Vectorizer costs.  */
 264   const struct cpu_vec_costs* vec_costs;
 265   int constant_limit;
 266   /* Maximum number of instructions to conditionalise.  */
 267   int max_insns_skipped;
 268   /* Maximum number of instructions to inline calls to memset.  */
 269   int max_insns_inline_memset;
 270   /* Issue rate of the processor.  */
 271   unsigned int issue_rate;
 272   /* Explicit prefetch data.  */
 273   struct
 274     {
 275       int num_slots;
 276       int l1_cache_size;
 277       int l1_cache_line_size;
 278     } prefetch;
 279   enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE}
 280     prefer_constant_pool: 1;
 281   /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM.  */
 282   enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1;
 283   /* The preference for non short cirtcuit operation when optimizing for
 284      performance. The first element covers Thumb state and the second one
 285      is for ARM state.  */
 286   enum log_op_non_short_circuit {LOG_OP_NON_SHORT_CIRCUIT_FALSE,
 287                                  LOG_OP_NON_SHORT_CIRCUIT_TRUE};
 288   log_op_non_short_circuit logical_op_non_short_circuit_thumb: 1;
 289   log_op_non_short_circuit logical_op_non_short_circuit_arm: 1;
 290   /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding.  */
 291   enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL}
 292     disparage_flag_setting_t16_encodings: 2;
 293   enum {PREF_NEON_64_FALSE, PREF_NEON_64_TRUE} prefer_neon_for_64bits: 1;
 294   /* Prefer to inline string operations like memset by using Neon.  */
 295   enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE}
 296     string_ops_prefer_neon: 1;
 297   /* Bitfield encoding the fusible pairs of instructions.  Use FUSE_OPS
 298      in an initializer if multiple fusion operations are supported on a
 299      target.  */
 300   enum fuse_ops
 301   {
 302     FUSE_NOTHING   = 0,
 303     FUSE_MOVW_MOVT = 1 << 0
 304   } fusible_ops: 1;
 305   /* Depth of scheduling queue to check for L2 autoprefetcher.  */
 306   enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL}
 307     sched_autopref: 2;
 308 };
 309
 310 /* Smash multiple fusion operations into a type that can be used for an
 311    initializer.  */
 312 #define FUSE_OPS(x) ((tune_params::fuse_ops) (x))
 313
 314 extern const struct tune_params *current_tune;
 315 extern int vfp3_const_double_for_fract_bits (rtx);
 316 /* return power of two from operand, otherwise 0.  */
 317 extern int vfp3_const_double_for_bits (rtx);
 318
 319 extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
 320                                            rtx);
 321 extern bool arm_valid_symbolic_address_p (rtx);
 322 extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
 323 #endif /* RTX_CODE */
 324
 325 extern bool arm_gen_setmem (rtx *);
 326 extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
 327 extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
 328
 329 extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
 330
 331 extern void arm_emit_eabi_attribute (const char *, int, int);
 332
 333 extern void arm_reset_previous_fndecl (void);
 334 extern void save_restore_target_globals (tree);
 335
 336 /* Defined in gcc/common/config/arm-common.c.  */
 337 extern const char *arm_rewrite_selected_cpu (const char *name);
 338
 339 /* Defined in gcc/common/config/arm-c.c.  */
 340 extern void arm_lang_object_attributes_init (void);
 341 extern void arm_register_target_pragmas (void);
 342 extern void arm_cpu_cpp_builtins (struct cpp_reader *);
 343
 344 extern bool arm_is_constant_pool_ref (rtx);
 345
 346 /* Flags used to identify the presence of processor capabilities.  */
 347
 348 /* Bit values used to identify processor capabilities.  */
 349 #define FL_NONE       (0)             /* No flags.  */
 350 #define FL_ANY        (0xffffffff)    /* All flags.  */
 351 #define FL_CO_PROC    (1 << 0)        /* Has external co-processor bus */
 352 #define FL_ARCH3M     (1 << 1)        /* Extended multiply */
 353 #define FL_MODE26     (1 << 2)        /* 26-bit mode support */
 354 #define FL_MODE32     (1 << 3)        /* 32-bit mode support */
 355 #define FL_ARCH4      (1 << 4)        /* Architecture rel 4 */
 356 #define FL_ARCH5      (1 << 5)        /* Architecture rel 5 */
 357 #define FL_THUMB      (1 << 6)        /* Thumb aware */
 358 #define FL_LDSCHED    (1 << 7)        /* Load scheduling necessary */
 359 #define FL_STRONG     (1 << 8)        /* StrongARM */
 360 #define FL_ARCH5E     (1 << 9)        /* DSP extensions to v5 */
 361 #define FL_XSCALE     (1 << 10)       /* XScale */
 362 /* spare              (1 << 11) */
 363 #define FL_ARCH6      (1 << 12)       /* Architecture rel 6.  Adds
 364                                          media instructions.  */
 365 #define FL_VFPV2      (1 << 13)       /* Vector Floating Point V2.  */
 366 #define FL_WBUF       (1 << 14)       /* Schedule for write buffer ops.
 367                                          Note: ARM6 & 7 derivatives only.  */
 368 #define FL_ARCH6K     (1 << 15)       /* Architecture rel 6 K extensions.  */
 369 #define FL_THUMB2     (1 << 16)       /* Thumb-2.  */
 370 #define FL_NOTM       (1 << 17)       /* Instructions not present in the 'M'
 371                                          profile.  */
 372 #define FL_THUMB_DIV  (1 << 18)       /* Hardware divide (Thumb mode).  */
 373 #define FL_VFPV3      (1 << 19)       /* Vector Floating Point V3.  */
 374 #define FL_NEON       (1 << 20)       /* Neon instructions.  */
 375 #define FL_ARCH7EM    (1 << 21)       /* Instructions present in the ARMv7E-M
 376                                          architecture.  */
 377 #define FL_ARCH7      (1 << 22)       /* Architecture 7.  */
 378 #define FL_ARM_DIV    (1 << 23)       /* Hardware divide (ARM mode).  */
 379 #define FL_ARCH8      (1 << 24)       /* Architecture 8.  */
 380 #define FL_CRC32      (1 << 25)       /* ARMv8 CRC32 instructions.  */
 381
 382 #define FL_SMALLMUL   (1 << 26)       /* Small multiply supported.  */
 383 #define FL_NO_VOLATILE_CE   (1 << 27) /* No volatile memory in IT block.  */
 384
 385 #define FL_IWMMXT     (1 << 29)       /* XScale v2 or "Intel Wireless MMX technology".  */
 386 #define FL_IWMMXT2    (1 << 30)       /* "Intel Wireless MMX2 technology".  */
 387 #define FL_ARCH6KZ    (1 << 31)       /* ARMv6KZ architecture.  */
 388
 389 #define FL2_ARCH8_1   (1 << 0)        /* Architecture 8.1.  */
 390
 391 /* Flags that only effect tuning, not available instructions.  */
 392 #define FL_TUNE         (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
 393                          | FL_CO_PROC)
 394
 395 #define FL_FOR_ARCH2    FL_NOTM
 396 #define FL_FOR_ARCH3    (FL_FOR_ARCH2 | FL_MODE32)
 397 #define FL_FOR_ARCH3M   (FL_FOR_ARCH3 | FL_ARCH3M)
 398 #define FL_FOR_ARCH4    (FL_FOR_ARCH3M | FL_ARCH4)
 399 #define FL_FOR_ARCH4T   (FL_FOR_ARCH4 | FL_THUMB)
 400 #define FL_FOR_ARCH5    (FL_FOR_ARCH4 | FL_ARCH5)
 401 #define FL_FOR_ARCH5T   (FL_FOR_ARCH5 | FL_THUMB)
 402 #define FL_FOR_ARCH5E   (FL_FOR_ARCH5 | FL_ARCH5E)
 403 #define FL_FOR_ARCH5TE  (FL_FOR_ARCH5E | FL_THUMB)
 404 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
 405 #define FL_FOR_ARCH6    (FL_FOR_ARCH5TE | FL_ARCH6)
 406 #define FL_FOR_ARCH6J   FL_FOR_ARCH6
 407 #define FL_FOR_ARCH6K   (FL_FOR_ARCH6 | FL_ARCH6K)
 408 #define FL_FOR_ARCH6Z   FL_FOR_ARCH6
 409 #define FL_FOR_ARCH6KZ  (FL_FOR_ARCH6K | FL_ARCH6KZ)
 410 #define FL_FOR_ARCH6T2  (FL_FOR_ARCH6 | FL_THUMB2)
 411 #define FL_FOR_ARCH6M   (FL_FOR_ARCH6 & ~FL_NOTM)
 412 #define FL_FOR_ARCH7    ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
 413 #define FL_FOR_ARCH7A   (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
 414 #define FL_FOR_ARCH7VE  (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
 415 #define FL_FOR_ARCH7R   (FL_FOR_ARCH7A | FL_THUMB_DIV)
 416 #define FL_FOR_ARCH7M   (FL_FOR_ARCH7 | FL_THUMB_DIV)
 417 #define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
 418 #define FL_FOR_ARCH8A   (FL_FOR_ARCH7VE | FL_ARCH8)
 419 #define FL2_FOR_ARCH8_1A        FL2_ARCH8_1
 420
 421 /* There are too many feature bits to fit in a single word so the set of cpu and
 422    fpu capabilities is a structure.  A feature set is created and manipulated
 423    with the ARM_FSET macros.  */
 424
 425 typedef struct
 426 {
 427   unsigned long cpu[2];
 428 } arm_feature_set;
 429
 430
 431 /* Initialize a feature set.  */
 432
 433 #define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
 434
 435 #define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
 436 #define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
 437
 438 /* Accessors.  */
 439
 440 #define ARM_FSET_CPU1(S) ((S).cpu[0])
 441 #define ARM_FSET_CPU2(S) ((S).cpu[1])
 442
 443 /* Useful combinations.  */
 444
 445 #define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
 446 #define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
 447
 448 /* Tests for a specific CPU feature.  */
 449
 450 #define ARM_FSET_HAS_CPU1(A, F)  \
 451   (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
 452 #define ARM_FSET_HAS_CPU2(A, F)  \
 453   (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
 454 #define ARM_FSET_HAS_CPU(A, F1, F2)                             \
 455   (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
 456
 457 /* Add a feature to a feature set.  */
 458
 459 #define ARM_FSET_ADD_CPU1(DST, F)               \
 460   do {                                          \
 461     (DST).cpu[0] |= (F);                        \
 462   } while (0)
 463
 464 #define ARM_FSET_ADD_CPU2(DST, F)               \
 465   do {                                          \
 466     (DST).cpu[1] |= (F);                        \
 467   } while (0)
 468
 469 /* Remove a feature from a feature set.  */
 470
 471 #define ARM_FSET_DEL_CPU1(DST, F)               \
 472   do {                                          \
 473     (DST).cpu[0] &= ~(F);                       \
 474   } while (0)
 475
 476 #define ARM_FSET_DEL_CPU2(DST, F)               \
 477   do {                                          \
 478     (DST).cpu[1] &= ~(F);                       \
 479   } while (0)
 480
 481 /* Union of feature sets.  */
 482
 483 #define ARM_FSET_UNION(DST,F1,F2)               \
 484   do {                                          \
 485     (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0];   \
 486     (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1];   \
 487   } while (0)
 488
 489 /* Intersection of feature sets.  */
 490
 491 #define ARM_FSET_INTER(DST,F1,F2)               \
 492   do {                                          \
 493     (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0];   \
 494     (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1];   \
 495   } while (0)
 496
 497 /* Exclusive disjunction.  */
 498
 499 #define ARM_FSET_XOR(DST,F1,F2)                         \
 500   do {                                                  \
 501     (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0];           \
 502     (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1];           \
 503   } while (0)
 504
 505 /* Difference of feature sets: F1 excluding the elements of F2.  */
 506
 507 #define ARM_FSET_EXCLUDE(DST,F1,F2)             \
 508   do {                                          \
 509     (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0];  \
 510     (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1];  \
 511   } while (0)
 512
 513 /* Test for an empty feature set.  */
 514
 515 #define ARM_FSET_IS_EMPTY(A)            \
 516   (!((A).cpu[0]) && !((A).cpu[1]))
 517
 518 /* Tests whether the cpu features of A are a subset of B.  */
 519
 520 #define ARM_FSET_CPU_SUBSET(A,B)                                        \
 521   ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0])                            \
 522    && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
 523
 524 /* The bits in this mask specify which
 525    instructions we are allowed to generate.  */
 526 extern arm_feature_set insn_flags;
 527
 528 /* The bits in this mask specify which instruction scheduling options should
 529    be used.  */
 530 extern arm_feature_set tune_flags;
 531
 532 /* Nonzero if this chip supports the ARM Architecture 3M extensions.  */
 533 extern int arm_arch3m;
 534
 535 /* Nonzero if this chip supports the ARM Architecture 4 extensions.  */
 536 extern int arm_arch4;
 537
 538 /* Nonzero if this chip supports the ARM Architecture 4t extensions.  */
 539 extern int arm_arch4t;
 540
 541 /* Nonzero if this chip supports the ARM Architecture 5 extensions.  */
 542 extern int arm_arch5;
 543
 544 /* Nonzero if this chip supports the ARM Architecture 5E extensions.  */
 545 extern int arm_arch5e;
 546
 547 /* Nonzero if this chip supports the ARM Architecture 6 extensions.  */
 548 extern int arm_arch6;
 549
 550 /* Nonzero if this chip supports the ARM 6K extensions.  */
 551 extern int arm_arch6k;
 552
 553 /* Nonzero if this chip supports the ARM 6KZ extensions.  */
 554 extern int arm_arch6kz;
 555
 556 /* Nonzero if instructions present in ARMv6-M can be used.  */
 557 extern int arm_arch6m;
 558
 559 /* Nonzero if this chip supports the ARM 7 extensions.  */
 560 extern int arm_arch7;
 561
 562 /* Nonzero if instructions not present in the 'M' profile can be used.  */
 563 extern int arm_arch_notm;
 564
 565 /* Nonzero if instructions present in ARMv7E-M can be used.  */
 566 extern int arm_arch7em;
 567
 568 /* Nonzero if instructions present in ARMv8 can be used.  */
 569 extern int arm_arch8;
 570
 571 /* Nonzero if this chip can benefit from load scheduling.  */
 572 extern int arm_ld_sched;
 573
 574 /* Nonzero if this chip is a StrongARM.  */
 575 extern int arm_tune_strongarm;
 576
 577 /* Nonzero if this chip supports Intel Wireless MMX technology.  */
 578 extern int arm_arch_iwmmxt;
 579
 580 /* Nonzero if this chip supports Intel Wireless MMX2 technology.  */
 581 extern int arm_arch_iwmmxt2;
 582
 583 /* Nonzero if this chip is an XScale.  */
 584 extern int arm_arch_xscale;
 585
 586 /* Nonzero if tuning for XScale  */
 587 extern int arm_tune_xscale;
 588
 589 /* Nonzero if we want to tune for stores that access the write-buffer.
 590    This typically means an ARM6 or ARM7 with MMU or MPU.  */
 591 extern int arm_tune_wbuf;
 592
 593 /* Nonzero if tuning for Cortex-A9.  */
 594 extern int arm_tune_cortex_a9;
 595
 596 /* Nonzero if we should define __THUMB_INTERWORK__ in the
 597    preprocessor.
 598    XXX This is a bit of a hack, it's intended to help work around
 599    problems in GLD which doesn't understand that armv5t code is
 600    interworking clean.  */
 601 extern int arm_cpp_interwork;
 602
 603 /* Nonzero if chip supports Thumb 2.  */
 604 extern int arm_arch_thumb2;
 605
 606 /* Nonzero if chip supports integer division instruction.  */
 607 extern int arm_arch_arm_hwdiv;
 608 extern int arm_arch_thumb_hwdiv;
 609
 610 /* Nonzero if chip disallows volatile memory access in IT block.  */
 611 extern int arm_arch_no_volatile_ce;
 612
 613 /* Nonzero if we should use Neon to handle 64-bits operations rather
 614    than core registers.  */
 615 extern int prefer_neon_for_64bits;
 616
 617
 618
 619 #endif /* ! GCC_ARM_PROTOS_H */