| blob | 7d26e8c2bd00df18fc916619615d605ec85e59e2 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
101 /* This file should be included last. */
108 #ifndef CHECK_STACK_LIMIT
109 #define CHECK_STACK_LIMIT (-1)
110 #endif
112 /* Return index of given mode in mult and division cost tables. */
113 #define MODE_INDEX(mode) \
114 ((mode) == QImode ? 0 \
115 : (mode) == HImode ? 1 \
116 : (mode) == SImode ? 2 \
117 : (mode) == DImode ? 3 \
118 : 4)
120 /* Processor costs (relative to an add) */
121 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
122 #define COSTS_N_BYTES(N) ((N) * 2)
124 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
133 const
156 in QImode, HImode and SImode.
157 Relative to reg-reg move (2). */
161 in SFmode, DFmode and XFmode */
163 in SFmode, DFmode and XFmode */
166 in SImode and DImode */
168 in SImode and DImode */
171 in SImode, DImode and TImode */
173 in SImode, DImode and TImode */
186 ix86_size_memcpy,
187 ix86_size_memset,
199 };
201 /* Processor costs (relative to an add) */
204 DUMMY_STRINGOP_ALGS};
207 DUMMY_STRINGOP_ALGS};
209 static const
232 in QImode, HImode and SImode.
233 Relative to reg-reg move (2). */
237 in SFmode, DFmode and XFmode */
239 in SFmode, DFmode and XFmode */
242 in SImode and DImode */
244 in SImode and DImode */
247 in SImode, DImode and TImode */
249 in SImode, DImode and TImode */
262 i386_memcpy,
263 i386_memset,
275 };
279 DUMMY_STRINGOP_ALGS};
282 DUMMY_STRINGOP_ALGS};
284 static const
307 in QImode, HImode and SImode.
308 Relative to reg-reg move (2). */
312 in SFmode, DFmode and XFmode */
314 in SFmode, DFmode and XFmode */
317 in SImode and DImode */
319 in SImode and DImode */
322 in SImode, DImode and TImode */
324 in SImode, DImode and TImode */
327 shared for code and data, so 4kB is
328 not really precise. */
339 i486_memcpy,
340 i486_memset,
352 };
356 DUMMY_STRINGOP_ALGS};
359 DUMMY_STRINGOP_ALGS};
361 static const
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
389 in SFmode, DFmode and XFmode */
391 in SFmode, DFmode and XFmode */
394 in SImode and DImode */
396 in SImode and DImode */
399 in SImode, DImode and TImode */
401 in SImode, DImode and TImode */
414 pentium_memcpy,
415 pentium_memset,
427 };
429 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
430 (we ensure the alignment). For small blocks inline loop is still a
431 noticeable win, for bigger blocks either rep movsl or rep movsb is
432 way to go. Rep movsb has apparently more expensive startup time in CPU,
433 but after 4K the difference is down in the noise. */
438 DUMMY_STRINGOP_ALGS};
443 DUMMY_STRINGOP_ALGS};
444 static const
467 in QImode, HImode and SImode.
468 Relative to reg-reg move (2). */
472 in SFmode, DFmode and XFmode */
474 in SFmode, DFmode and XFmode */
477 in SImode and DImode */
479 in SImode and DImode */
482 in SImode, DImode and TImode */
484 in SImode, DImode and TImode */
497 pentiumpro_memcpy,
498 pentiumpro_memset,
510 };
514 DUMMY_STRINGOP_ALGS};
517 DUMMY_STRINGOP_ALGS};
518 static const
541 in QImode, HImode and SImode.
542 Relative to reg-reg move (2). */
546 in SFmode, DFmode and XFmode */
548 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
572 geode_memcpy,
573 geode_memset,
585 };
589 DUMMY_STRINGOP_ALGS};
592 DUMMY_STRINGOP_ALGS};
593 static const
616 in QImode, HImode and SImode.
617 Relative to reg-reg move (2). */
621 in SFmode, DFmode and XFmode */
623 in SFmode, DFmode and XFmode */
626 in SImode and DImode */
628 in SImode and DImode */
631 in SImode, DImode and TImode */
633 in SImode, DImode and TImode */
637 have integrated l2 cache, but
638 optimizing for k6 is not important
639 enough to worry about that. */
649 k6_memcpy,
650 k6_memset,
662 };
664 /* For some reason, Athlon deals better with REP prefix (relative to loops)
665 compared to K8. Alignment becomes important after 8 bytes for memcpy and
666 128 bytes for memset. */
669 DUMMY_STRINGOP_ALGS};
672 DUMMY_STRINGOP_ALGS};
673 static const
696 in QImode, HImode and SImode.
697 Relative to reg-reg move (2). */
701 in SFmode, DFmode and XFmode */
703 in SFmode, DFmode and XFmode */
706 in SImode and DImode */
708 in SImode and DImode */
711 in SImode, DImode and TImode */
713 in SImode, DImode and TImode */
726 athlon_memcpy,
727 athlon_memset,
739 };
741 /* K8 has optimized REP instruction for medium sized blocks, but for very
742 small blocks it is better to use loop. For large blocks, libcall can
743 do nontemporary accesses and beat inline considerably. */
754 static const
777 in QImode, HImode and SImode.
778 Relative to reg-reg move (2). */
782 in SFmode, DFmode and XFmode */
784 in SFmode, DFmode and XFmode */
787 in SImode and DImode */
789 in SImode and DImode */
792 in SImode, DImode and TImode */
794 in SImode, DImode and TImode */
799 /* New AMD processors never drop prefetches; if they cannot be performed
800 immediately, they are queued. We set number of simultaneous prefetches
801 to a large constant to reflect this (it probably is not a good idea not
802 to limit number of prefetches at all, as their execution also takes some
803 time). */
813 k8_memcpy,
814 k8_memset,
826 };
828 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
829 very small blocks it is better to use loop. For large blocks, libcall can
830 do nontemporary accesses and beat inline considerably. */
863 in QImode, HImode and SImode.
864 Relative to reg-reg move (2). */
868 in SFmode, DFmode and XFmode */
870 in SFmode, DFmode and XFmode */
873 in SImode and DImode */
875 in SImode and DImode */
878 in SImode, DImode and TImode */
880 in SImode, DImode and TImode */
882 /* On K8:
883 MOVD reg64, xmmreg Double FSTORE 4
884 MOVD reg32, xmmreg Double FSTORE 4
885 On AMDFAM10:
886 MOVD reg64, xmmreg Double FADD 3
887 1/1 1/1
888 MOVD reg32, xmmreg Double FADD 3
889 1/1 1/1 */
893 /* New AMD processors never drop prefetches; if they cannot be performed
894 immediately, they are queued. We set number of simultaneous prefetches
895 to a large constant to reflect this (it probably is not a good idea not
896 to limit number of prefetches at all, as their execution also takes some
897 time). */
907 amdfam10_memcpy,
908 amdfam10_memset,
920 };
922 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
923 very small blocks it is better to use loop. For large blocks, libcall
924 can do nontemporary accesses and beat inline considerably. */
958 in QImode, HImode and SImode.
959 Relative to reg-reg move (2). */
963 in SFmode, DFmode and XFmode */
965 in SFmode, DFmode and XFmode */
968 in SImode and DImode */
970 in SImode and DImode */
973 in SImode, DImode and TImode */
975 in SImode, DImode and TImode */
977 /* On K8:
978 MOVD reg64, xmmreg Double FSTORE 4
979 MOVD reg32, xmmreg Double FSTORE 4
980 On AMDFAM10:
981 MOVD reg64, xmmreg Double FADD 3
982 1/1 1/1
983 MOVD reg32, xmmreg Double FADD 3
984 1/1 1/1 */
988 /* New AMD processors never drop prefetches; if they cannot be performed
989 immediately, they are queued. We set number of simultaneous prefetches
990 to a large constant to reflect this (it probably is not a good idea not
991 to limit number of prefetches at all, as their execution also takes some
992 time). */
1002 bdver1_memcpy,
1003 bdver1_memset,
1015 };
1017 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1018 very small blocks it is better to use loop. For large blocks, libcall
1019 can do nontemporary accesses and beat inline considerably. */
1054 in QImode, HImode and SImode.
1055 Relative to reg-reg move (2). */
1059 in SFmode, DFmode and XFmode */
1061 in SFmode, DFmode and XFmode */
1064 in SImode and DImode */
1066 in SImode and DImode */
1069 in SImode, DImode and TImode */
1071 in SImode, DImode and TImode */
1073 /* On K8:
1074 MOVD reg64, xmmreg Double FSTORE 4
1075 MOVD reg32, xmmreg Double FSTORE 4
1076 On AMDFAM10:
1077 MOVD reg64, xmmreg Double FADD 3
1078 1/1 1/1
1079 MOVD reg32, xmmreg Double FADD 3
1080 1/1 1/1 */
1084 /* New AMD processors never drop prefetches; if they cannot be performed
1085 immediately, they are queued. We set number of simultaneous prefetches
1086 to a large constant to reflect this (it probably is not a good idea not
1087 to limit number of prefetches at all, as their execution also takes some
1088 time). */
1098 bdver2_memcpy,
1099 bdver2_memset,
1111 };
1114 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1115 very small blocks it is better to use loop. For large blocks, libcall
1116 can do nontemporary accesses and beat inline considerably. */
1149 in QImode, HImode and SImode.
1150 Relative to reg-reg move (2). */
1154 in SFmode, DFmode and XFmode */
1156 in SFmode, DFmode and XFmode */
1159 in SImode and DImode */
1161 in SImode and DImode */
1164 in SImode, DImode and TImode */
1166 in SImode, DImode and TImode */
1171 /* New AMD processors never drop prefetches; if they cannot be performed
1172 immediately, they are queued. We set number of simultaneous prefetches
1173 to a large constant to reflect this (it probably is not a good idea not
1174 to limit number of prefetches at all, as their execution also takes some
1175 time). */
1185 bdver3_memcpy,
1186 bdver3_memset,
1198 };
1200 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1201 very small blocks it is better to use loop. For large blocks, libcall
1202 can do nontemporary accesses and beat inline considerably. */
1235 in QImode, HImode and SImode.
1236 Relative to reg-reg move (2). */
1240 in SFmode, DFmode and XFmode */
1242 in SFmode, DFmode and XFmode */
1245 in SImode and DImode */
1247 in SImode and DImode */
1250 in SImode, DImode and TImode */
1252 in SImode, DImode and TImode */
1257 /* New AMD processors never drop prefetches; if they cannot be performed
1258 immediately, they are queued. We set number of simultaneous prefetches
1259 to a large constant to reflect this (it probably is not a good idea not
1260 to limit number of prefetches at all, as their execution also takes some
1261 time). */
1271 bdver4_memcpy,
1272 bdver4_memset,
1284 };
1286 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1287 very small blocks it is better to use loop. For large blocks, libcall can
1288 do nontemporary accesses and beat inline considerably. */
1321 in QImode, HImode and SImode.
1322 Relative to reg-reg move (2). */
1326 in SFmode, DFmode and XFmode */
1328 in SFmode, DFmode and XFmode */
1331 in SImode and DImode */
1333 in SImode and DImode */
1336 in SImode, DImode and TImode */
1338 in SImode, DImode and TImode */
1340 /* On K8:
1341 MOVD reg64, xmmreg Double FSTORE 4
1342 MOVD reg32, xmmreg Double FSTORE 4
1343 On AMDFAM10:
1344 MOVD reg64, xmmreg Double FADD 3
1345 1/1 1/1
1346 MOVD reg32, xmmreg Double FADD 3
1347 1/1 1/1 */
1360 btver1_memcpy,
1361 btver1_memset,
1373 };
1407 in QImode, HImode and SImode.
1408 Relative to reg-reg move (2). */
1412 in SFmode, DFmode and XFmode */
1414 in SFmode, DFmode and XFmode */
1417 in SImode and DImode */
1419 in SImode and DImode */
1422 in SImode, DImode and TImode */
1424 in SImode, DImode and TImode */
1426 /* On K8:
1427 MOVD reg64, xmmreg Double FSTORE 4
1428 MOVD reg32, xmmreg Double FSTORE 4
1429 On AMDFAM10:
1430 MOVD reg64, xmmreg Double FADD 3
1431 1/1 1/1
1432 MOVD reg32, xmmreg Double FADD 3
1433 1/1 1/1 */
1445 btver2_memcpy,
1446 btver2_memset,
1458 };
1462 DUMMY_STRINGOP_ALGS};
1466 DUMMY_STRINGOP_ALGS};
1468 static const
1491 in QImode, HImode and SImode.
1492 Relative to reg-reg move (2). */
1496 in SFmode, DFmode and XFmode */
1498 in SFmode, DFmode and XFmode */
1501 in SImode and DImode */
1503 in SImode and DImode */
1506 in SImode, DImode and TImode */
1508 in SImode, DImode and TImode */
1521 pentium4_memcpy,
1522 pentium4_memset,
1534 };
1547 static const
1570 in QImode, HImode and SImode.
1571 Relative to reg-reg move (2). */
1575 in SFmode, DFmode and XFmode */
1577 in SFmode, DFmode and XFmode */
1580 in SImode and DImode */
1582 in SImode and DImode */
1585 in SImode, DImode and TImode */
1587 in SImode, DImode and TImode */
1600 nocona_memcpy,
1601 nocona_memset,
1613 };
1624 static const
1647 in QImode, HImode and SImode.
1648 Relative to reg-reg move (2). */
1652 in SFmode, DFmode and XFmode */
1654 in SFmode, DFmode and XFmode */
1657 in SImode and DImode */
1659 in SImode and DImode */
1662 in SImode, DImode and TImode */
1664 in SImode, DImode and TImode */
1677 atom_memcpy,
1678 atom_memset,
1690 };
1701 static const
1724 in QImode, HImode and SImode.
1725 Relative to reg-reg move (2). */
1729 in SFmode, DFmode and XFmode */
1731 in SFmode, DFmode and XFmode */
1734 in SImode and DImode */
1736 in SImode and DImode */
1739 in SImode, DImode and TImode */
1741 in SImode, DImode and TImode */
1754 slm_memcpy,
1755 slm_memset,
1767 };
1778 static const
1801 in QImode, HImode and SImode.
1802 Relative to reg-reg move (2). */
1806 in SFmode, DFmode and XFmode */
1808 in SFmode, DFmode and XFmode */
1811 in SImode and DImode */
1813 in SImode and DImode */
1816 in SImode, DImode and TImode */
1818 in SImode, DImode and TImode */
1831 intel_memcpy,
1832 intel_memset,
1844 };
1846 /* Generic should produce code tuned for Core-i7 (and newer chips)
1847 and btver1 (and newer chips). */
1859 static const
1862 /* On all chips taken into consideration lea is 2 cycles and more. With
1863 this cost however our current implementation of synth_mult results in
1864 use of unnecessary temporary registers causing regression on several
1865 SPECfp benchmarks. */
1886 in QImode, HImode and SImode.
1887 Relative to reg-reg move (2). */
1891 in SFmode, DFmode and XFmode */
1893 in SFmode, DFmode and XFmode */
1896 in SImode and DImode */
1898 in SImode and DImode */
1901 in SImode, DImode and TImode */
1903 in SImode, DImode and TImode */
1909 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1910 value is increased to perhaps more appropriate value of 5. */
1918 generic_memcpy,
1919 generic_memset,
1931 };
1933 /* core_cost should produce code tuned for Core familly of CPUs. */
1946 static const
1949 /* On all chips taken into consideration lea is 2 cycles and more. With
1950 this cost however our current implementation of synth_mult results in
1951 use of unnecessary temporary registers causing regression on several
1952 SPECfp benchmarks. */
1973 in QImode, HImode and SImode.
1974 Relative to reg-reg move (2). */
1978 in SFmode, DFmode and XFmode */
1980 in SFmode, DFmode and XFmode */
1983 in SImode and DImode */
1985 in SImode and DImode */
1988 in SImode, DImode and TImode */
1990 in SImode, DImode and TImode */
1996 /* FIXME perhaps more appropriate value is 5. */
2004 core_memcpy,
2005 core_memset,
2017 };
2020 /* Set by -mtune. */
2023 /* Set by -mtune or -Os. */
2026 /* Processor feature/optimization bitmasks. */
2027 #define m_386 (1<<PROCESSOR_I386)
2028 #define m_486 (1<<PROCESSOR_I486)
2029 #define m_PENT (1<<PROCESSOR_PENTIUM)
2030 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2031 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2032 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2033 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2034 #define m_CORE2 (1<<PROCESSOR_CORE2)
2035 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2036 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2037 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2038 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2039 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2040 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2041 #define m_KNL (1<<PROCESSOR_KNL)
2042 #define m_INTEL (1<<PROCESSOR_INTEL)
2044 #define m_GEODE (1<<PROCESSOR_GEODE)
2045 #define m_K6 (1<<PROCESSOR_K6)
2046 #define m_K6_GEODE (m_K6 | m_GEODE)
2047 #define m_K8 (1<<PROCESSOR_K8)
2048 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2049 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2050 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2051 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2052 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2053 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2054 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2055 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2056 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2057 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2058 #define m_BTVER (m_BTVER1 | m_BTVER2)
2059 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2061 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2064 #undef DEF_TUNE
2065 #define DEF_TUNE(tune, name, selector) name,
2067 #undef DEF_TUNE
2068 };
2070 /* Feature tests against the various tunings. */
2073 /* Feature tests against the various tunings used to create ix86_tune_features
2074 based on the processor mask. */
2076 #undef DEF_TUNE
2077 #define DEF_TUNE(tune, name, selector) selector,
2079 #undef DEF_TUNE
2080 };
2082 /* Feature tests against the various architecture variations. */
2085 /* Feature tests against the various architecture variations, used to create
2086 ix86_arch_features based on the processor mask. */
2088 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2091 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2094 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2097 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2100 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2102 };
2104 /* In case the average insn count for single function invocation is
2105 lower than this constant, emit fast (but longer) prologue and
2106 epilogue code. */
2107 #define FAST_PROLOGUE_INSN_COUNT 20
2109 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2114 /* Array of the smallest class containing reg number REGNO, indexed by
2115 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2118 {
2119 /* ax, dx, cx, bx */
2121 /* si, di, bp, sp */
2123 /* FP registers */
2126 /* arg pointer */
2127 NON_Q_REGS,
2128 /* flags, fpsr, fpcr, frame */
2130 /* SSE registers */
2133 /* MMX registers */
2136 /* REX registers */
2139 /* SSE REX registers */
2142 /* AVX-512 SSE registers */
2147 /* Mask registers. */
2150 /* MPX bound registers */
2152 };
2154 /* The "default" register map used in 32bit mode. */
2157 {
2169 };
2171 /* The "default" register map used in 64bit mode. */
2174 {
2186 };
2188 /* Define the register numbers to be used in Dwarf debugging information.
2189 The SVR4 reference port C compiler uses the following register numbers
2190 in its Dwarf output code:
2191 0 for %eax (gcc regno = 0)
2192 1 for %ecx (gcc regno = 2)
2193 2 for %edx (gcc regno = 1)
2194 3 for %ebx (gcc regno = 3)
2195 4 for %esp (gcc regno = 7)
2196 5 for %ebp (gcc regno = 6)
2197 6 for %esi (gcc regno = 4)
2198 7 for %edi (gcc regno = 5)
2199 The following three DWARF register numbers are never generated by
2200 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2201 believes these numbers have these meanings.
2202 8 for %eip (no gcc equivalent)
2203 9 for %eflags (gcc regno = 17)
2204 10 for %trapno (no gcc equivalent)
2205 It is not at all clear how we should number the FP stack registers
2206 for the x86 architecture. If the version of SDB on x86/svr4 were
2207 a bit less brain dead with respect to floating-point then we would
2208 have a precedent to follow with respect to DWARF register numbers
2209 for x86 FP registers, but the SDB on x86/svr4 is so completely
2210 broken with respect to FP registers that it is hardly worth thinking
2211 of it as something to strive for compatibility with.
2212 The version of x86/svr4 SDB I have at the moment does (partially)
2213 seem to believe that DWARF register number 11 is associated with
2214 the x86 register %st(0), but that's about all. Higher DWARF
2215 register numbers don't seem to be associated with anything in
2216 particular, and even for DWARF regno 11, SDB only seems to under-
2217 stand that it should say that a variable lives in %st(0) (when
2218 asked via an `=' command) if we said it was in DWARF regno 11,
2219 but SDB still prints garbage when asked for the value of the
2220 variable in question (via a `/' command).
2221 (Also note that the labels SDB prints for various FP stack regs
2222 when doing an `x' command are all wrong.)
2223 Note that these problems generally don't affect the native SVR4
2224 C compiler because it doesn't allow the use of -O with -g and
2225 because when it is *not* optimizing, it allocates a memory
2226 location for each floating-point variable, and the memory
2227 location is what gets described in the DWARF AT_location
2228 attribute for the variable in question.
2229 Regardless of the severe mental illness of the x86/svr4 SDB, we
2230 do something sensible here and we use the following DWARF
2231 register numbers. Note that these are all stack-top-relative
2232 numbers.
2233 11 for %st(0) (gcc regno = 8)
2234 12 for %st(1) (gcc regno = 9)
2235 13 for %st(2) (gcc regno = 10)
2236 14 for %st(3) (gcc regno = 11)
2237 15 for %st(4) (gcc regno = 12)
2238 16 for %st(5) (gcc regno = 13)
2239 17 for %st(6) (gcc regno = 14)
2240 18 for %st(7) (gcc regno = 15)
2241 */
2243 {
2255 };
2257 /* Define parameter passing and return registers. */
2260 {
2262 };
2265 {
2267 };
2270 {
2272 };
2274 /* Additional registers that are clobbered by SYSV calls. */
2277 {
2282 };
2284 /* Define the structure for the machine field in struct function. */
2289 rtx rtl;
2291 };
2293 /* Structure describing stack frame layout.
2294 Stack grows downward:
2296 [arguments]
2297 <- ARG_POINTER
2298 saved pc
2300 saved static chain if ix86_static_chain_on_stack
2302 saved frame pointer if frame_pointer_needed
2303 <- HARD_FRAME_POINTER
2304 [saved regs]
2305 <- regs_save_offset
2306 [padding0]
2308 [saved SSE regs]
2309 <- sse_regs_save_offset
2310 [padding1] |
2311 | <- FRAME_POINTER
2312 [va_arg registers] |
2313 |
2314 [frame] |
2315 |
2316 [padding2] | = to_allocate
2317 <- STACK_POINTER
2318 */
2319 struct ix86_frame
2320 {
2327 /* The offsets relative to ARG_POINTER. */
2328 HOST_WIDE_INT frame_pointer_offset;
2329 HOST_WIDE_INT hard_frame_pointer_offset;
2330 HOST_WIDE_INT stack_pointer_offset;
2331 HOST_WIDE_INT hfp_save_offset;
2332 HOST_WIDE_INT reg_save_offset;
2333 HOST_WIDE_INT sse_reg_save_offset;
2335 /* When save_regs_using_mov is set, emit prologue using
2336 move instead of push instructions. */
2338 };
2340 /* Which cpu are we scheduling for. */
2343 /* Which cpu are we optimizing for. */
2346 /* Which instruction set architecture to use. */
2349 /* True if processor has SSE prefetch instruction. */
2352 /* -mstackrealign option */
2370 /* Preferred alignment for stack boundary in bits. */
2373 /* Alignment for incoming stack boundary in bits specified at
2374 command line. */
2377 /* Default alignment for incoming stack boundary in bits. */
2380 /* Alignment for incoming stack boundary in bits. */
2383 /* Calling abi specific va_list type nodes. */
2387 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2391 /* Fence to use after loop using movnt. */
2392 tree x86_mfence;
2394 /* Register class used for passing given 64bit part of the argument.
2395 These represent classes as documented by the PS ABI, with the exception
2396 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2397 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2399 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2400 whenever possible (upper half does contain padding). */
2401 enum x86_64_reg_class
2402 {
2403 X86_64_NO_CLASS,
2404 X86_64_INTEGER_CLASS,
2405 X86_64_INTEGERSI_CLASS,
2406 X86_64_SSE_CLASS,
2407 X86_64_SSESF_CLASS,
2408 X86_64_SSEDF_CLASS,
2409 X86_64_SSEUP_CLASS,
2410 X86_64_X87_CLASS,
2411 X86_64_X87UP_CLASS,
2412 X86_64_COMPLEX_X87_CLASS,
2413 X86_64_MEMORY_CLASS
2414 };
2416 #define MAX_CLASSES 8
2418 /* Table of constants used by fldpi, fldln2, etc.... */
2422 \f
2427 const_tree);
2439 enum ix86_function_specific_strings
2440 {
2441 IX86_FUNCTION_SPECIFIC_ARCH,
2442 IX86_FUNCTION_SPECIFIC_TUNE,
2443 IX86_FUNCTION_SPECIFIC_MAX
2444 };
2466 \f
2467 #ifndef SUBTARGET32_DEFAULT_CPU
2469 #endif
2471 /* Whether -mtune= or -march= were specified */
2475 /* Vectorization library interface and handlers. */
2481 /* Processor target table, indexed by processor number */
2482 struct ptt
2483 {
2491 };
2493 /* This table must be in sync with enum processor_type in i386.h. */
2495 {
2522 };
2523 \f
2524 static unsigned int
2526 {
2529 /* vzeroupper instructions are inserted immediately after reload to
2530 account for possible spills from 256bit registers. The pass
2531 reuses mode switching infrastructure by re-running mode insertion
2532 pass, so disable entities that have already been processed. */
2538 /* Call optimize_mode_switching. */
2541 }
2546 {
2556 };
2559 {
2563 {}
2565 /* opt_pass methods: */
2567 {
2571 }
2574 {
2576 }
2582 rtl_opt_pass *
2584 {
2586 }
2588 /* Return true if a red-zone is in use. */
2592 {
2594 }
2595 \f
2596 /* Return a string that documents the current -m options. The caller is
2597 responsible for freeing the string. */
2603 {
2604 struct ix86_target_opts
2605 {
2608 };
2610 /* This table is ordered so that options like -msse4.2 that imply
2611 preceding options while match those first. */
2613 {
2667 };
2669 /* Flag options. */
2671 {
2700 };
2717 /* Add -march= option. */
2719 {
2722 }
2724 /* Add -mtune= option. */
2726 {
2729 }
2731 /* Add -m32/-m64/-mx32. */
2733 {
2736 else
2738 isa &= ~ (OPTION_MASK_ISA_64BIT
2739 | OPTION_MASK_ABI_64
2741 }
2742 else
2746 /* Pick out the options in isa options. */
2748 {
2750 {
2753 }
2754 }
2757 {
2760 isa);
2761 }
2763 /* Add flag options. */
2765 {
2767 {
2770 }
2771 }
2774 {
2777 }
2779 /* Add -fpmath= option. */
2781 {
2784 {
2799 }
2800 }
2802 /* Any options? */
2808 /* Size the string. */
2812 {
2817 }
2819 /* Build the string. */
2824 {
2831 {
2833 line_len++;
2836 {
2840 }
2841 }
2845 {
2849 }
2850 }
2856 }
2858 /* Return true, if profiling code should be emitted before
2859 prologue. Otherwise it returns false.
2860 Note: For x86 with "hotfix" it is sorried. */
2861 static bool
2863 {
2865 }
2867 /* Function that is callable from the debugger to print the current
2868 options. */
2869 void ATTRIBUTE_UNUSED
2871 {
2877 {
2880 }
2881 else
2885 }
2888 #define DEF_ENUM
2889 #define DEF_ALG(alg, name) #name,
2891 #undef DEF_ENUM
2892 #undef DEF_ALG
2893 };
2895 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2896 The string is of the following form (or comma separated list of it):
2898 strategy_alg:max_size:[align|noalign]
2900 where the full size range for the strategy is either [0, max_size] or
2901 [min_size, max_size], in which min_size is the max_size + 1 of the
2902 preceding range. The last size range must have max_size == -1.
2904 Examples:
2906 1.
2907 -mmemcpy-strategy=libcall:-1:noalign
2909 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2912 2.
2913 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2915 This is to tell the compiler to use the following strategy for memset
2916 1) when the expected size is between [1, 16], use rep_8byte strategy;
2917 2) when the size is between [17, 2048], use vector_loop;
2918 3) when the size is > 2048, use libcall. */
2920 struct stringop_size_range
2921 {
2923 stringop_alg alg;
2925 };
2927 static void
2929 {
2937 else
2942 do
2943 {
2953 {
2957 }
2960 {
2964 }
2971 {
2973 alg_name,
2976 }
2980 {
2981 /* rep; movq isn't available in 32-bit code. */
2984 alg_name,
2987 }
2995 else
2996 {
3000 }
3001 n++;
3003 }
3007 {
3012 }
3015 {
3019 }
3021 /* Now override the default algs array. */
3023 {
3029 }
3030 }
3032 \f
3033 /* parse -mtune-ctrl= option. When DUMP is true,
3034 print the features that are explicitly set. */
3036 static void
3038 {
3046 do
3047 {
3054 {
3055 curr_feature_string++;
3057 }
3059 {
3061 {
3067 }
3068 }
3073 }
3076 }
3078 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3079 processor type. */
3081 static void
3083 {
3088 {
3091 else
3093 }
3096 {
3101 }
3104 }
3107 /* Default align_* from the processor table. */
3109 static void
3111 {
3113 {
3116 }
3118 {
3121 }
3123 {
3125 }
3126 }
3128 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3130 static void
3132 {
3134 }
3136 /* Override various settings based on options. If MAIN_ARGS_P, the
3137 options are from the command line, otherwise they are from
3138 attributes. */
3140 static void
3144 {
3152 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3153 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3154 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3155 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3156 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3157 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3158 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3159 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3160 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3161 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3162 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3163 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3164 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3165 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3166 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3167 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3168 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3169 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3170 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3171 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3172 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3173 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3174 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3175 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3176 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3177 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3178 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3179 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3180 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3181 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3182 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3183 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3184 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3185 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3186 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3187 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3188 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3189 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3190 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3191 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3192 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3193 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3194 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3195 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3196 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3197 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3198 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3199 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3200 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3201 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3202 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3203 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3204 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3205 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3206 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3207 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3208 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3209 #define PTA_MWAITX (HOST_WIDE_INT_1 << 57)
3211 #define PTA_CORE2 \
3212 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3213 | PTA_CX16 | PTA_FXSR)
3214 #define PTA_NEHALEM \
3215 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3216 #define PTA_WESTMERE \
3217 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3218 #define PTA_SANDYBRIDGE \
3219 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3220 #define PTA_IVYBRIDGE \
3221 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3222 #define PTA_HASWELL \
3223 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3224 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3225 #define PTA_BROADWELL \
3226 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3227 #define PTA_KNL \
3228 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3229 #define PTA_BONNELL \
3230 (PTA_CORE2 | PTA_MOVBE)
3231 #define PTA_SILVERMONT \
3232 (PTA_WESTMERE | PTA_MOVBE)
3234 /* if this reaches 64, need to widen struct pta flags below */
3236 static struct pta
3237 {
3242 }
3244 {
3278 PTA_SANDYBRIDGE},
3280 PTA_SANDYBRIDGE},
3282 PTA_IVYBRIDGE},
3284 PTA_IVYBRIDGE},
3376 PTA_64BIT
3378 };
3380 /* -mrecip options. */
3381 static struct
3382 {
3385 }
3387 {
3394 };
3398 /* Set up prefix/suffix so the error messages refer to either the command
3399 line argument, or the attribute(target). */
3401 {
3405 }
3406 else
3407 {
3411 }
3413 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3414 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3417 #ifdef TARGET_BI_ARCH
3418 else
3419 {
3420 #if TARGET_BI_ARCH == 1
3421 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3422 is on and OPTION_MASK_ABI_X32 is off. We turn off
3423 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3424 -mx32. */
3427 #else
3428 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3429 on and OPTION_MASK_ABI_64 is off. We turn off
3430 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3431 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3435 #endif
3440 }
3441 #endif
3444 {
3445 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3446 OPTION_MASK_ABI_64 for TARGET_X32. */
3449 }
3452 | OPTION_MASK_ABI_X32
3455 {
3456 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3457 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3460 }
3462 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3463 SUBTARGET_OVERRIDE_OPTIONS;
3464 #endif
3466 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3467 SUBSUBTARGET_OVERRIDE_OPTIONS;
3468 #endif
3470 /* -fPIC is the default for x86_64. */
3474 /* Need to check -mtune=generic first. */
3476 {
3477 /* As special support for cross compilers we read -mtune=native
3478 as -mtune=generic. With native compilers we won't see the
3479 -mtune=native, as it was changed by the driver. */
3481 {
3483 }
3488 }
3489 else
3490 {
3494 {
3495 opts->x_ix86_tune_string
3498 }
3500 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3501 or defaulted. We need to use a sensible tune option. */
3503 {
3505 }
3506 }
3510 {
3511 /* rep; movq isn't available in 32-bit code. */
3514 }
3517 opts->x_ix86_arch_string
3520 else
3524 {
3532 }
3533 else
3540 /* For targets using ms ABI enable ms-extensions, if not
3541 explicit turned off. For non-ms ABI we turn off this
3542 option. */
3547 {
3549 {
3593 {
3596 }
3604 }
3605 }
3606 else
3607 {
3608 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3609 use of rip-relative addressing. This eliminates fixups that
3610 would otherwise be needed if this object is to be placed in a
3611 DLL, and is essentially just as efficient as direct addressing. */
3617 else
3619 }
3621 {
3624 }
3632 {
3635 /* Default cpu tuning to the architecture. */
3816 }
3825 {
3826 /* Verify that x87/MMX/SSE/AVX is off for -miamcu. */
3830 | OPTION_MASK_ISA_SSE
3836 }
3854 {
3858 {
3860 {
3862 {
3870 }
3871 else
3874 }
3875 }
3876 /* Intel CPUs have always interpreted SSE prefetch instructions as
3877 NOPs; so, we can enable SSE prefetch instructions even when
3878 -mtune (rather than -march) points us to a processor that has them.
3879 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3880 higher processors. */
3885 }
3893 #ifndef USE_IX86_FRAME_POINTER
3894 #define USE_IX86_FRAME_POINTER 0
3895 #endif
3897 #ifndef USE_X86_64_FRAME_POINTER
3898 #define USE_X86_64_FRAME_POINTER 0
3899 #endif
3901 /* Set the default values for switches whose default depends on TARGET_64BIT
3902 in case they weren't overwritten by command line options. */
3904 {
3912 opts->x_flag_unwind_tables
3916 }
3917 else
3918 {
3920 opts->x_flag_omit_frame_pointer
3925 {
3926 /* Intel MCU psABI specifies that -freg-struct-return should
3927 be on. Instead of setting DEFAULT_PCC_STRUCT_RETURN to 1,
3928 we check -miamcu so that -freg-struct-return is always
3929 turned on if -miamcu is used. */
3932 else
3934 }
3935 }
3938 /* TODO: ix86_cost should be chosen at instruction or function granuality
3939 so for cold code we use size_cost even in !optimize_size compilation. */
3942 else
3945 /* Arrange to set up i386_stack_locals for all functions. */
3948 /* Validate -mregparm= value. */
3950 {
3956 {
3960 }
3961 }
3966 /* Default align_* from the processor table. */
3969 /* Provide default for -mbranch-cost= value. */
3974 {
3975 opts->x_target_flags
3978 /* Enable by default the SSE and MMX builtins. Do allow the user to
3979 explicitly disable any of these. In particular, disabling SSE and
3980 MMX for kernel code is extremely useful. */
3982 opts->x_ix86_isa_flags
3989 }
3990 else
3991 {
3992 opts->x_target_flags
3996 opts->x_ix86_isa_flags
3999 /* i386 ABI does not specify red zone. It still makes sense to use it
4000 when programmer takes care to stack from being destroyed. */
4003 }
4005 /* Keep nonleaf frame pointers. */
4011 /* If we're doing fast math, we don't care about comparison order
4012 wrt NaNs. This lets us use a shorter comparison sequence. */
4016 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
4017 since the insns won't need emulation. */
4021 /* Likewise, if the target doesn't have a 387, or we've specified
4022 software floating point, don't use 387 inline intrinsics. */
4026 /* Turn on MMX builtins for -msse. */
4028 opts->x_ix86_isa_flags
4031 /* Enable SSE prefetch. */
4036 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4039 opts->x_ix86_isa_flags
4042 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4045 opts->x_ix86_isa_flags
4048 /* Enable lzcnt instruction for -mabm. */
4050 opts->x_ix86_isa_flags
4053 /* Validate -mpreferred-stack-boundary= value or default it to
4054 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4057 {
4064 {
4068 else
4071 }
4072 else
4073 ix86_preferred_stack_boundary
4075 }
4077 /* Set the default value for -mstackrealign. */
4083 /* Validate -mincoming-stack-boundary= value or default it to
4084 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4087 {
4094 else
4095 {
4096 ix86_user_incoming_stack_boundary
4098 ix86_incoming_stack_boundary
4100 }
4101 }
4103 #ifndef NO_PROFILE_COUNTERS
4106 #endif
4110 /* Accept -msseregparm only if at least SSE support is enabled. */
4116 {
4118 {
4120 {
4123 }
4126 {
4129 }
4130 }
4131 }
4132 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4133 fpmath=387. The second is however default at many targets since the
4134 extra 80bit precision of temporaries is considered to be part of ABI.
4135 Overwrite the default at least for -ffast-math.
4136 TODO: -mfpmath=both seems to produce same performing code with bit
4137 smaller binaries. It is however not clear if register allocation is
4138 ready for this setting.
4139 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4140 codegen. We may switch to 387 with -ffast-math for size optimized
4141 functions. */
4145 else
4148 /* If the i387 is disabled, then do not return values in it. */
4152 /* Use external vectorized library in vectorizing intrinsics. */
4155 {
4166 }
4172 /* If stack probes are required, the space used for large function
4173 arguments on the stack must also be probed, so enable
4174 -maccumulate-outgoing-args so this happens in the prologue. */
4177 {
4182 }
4184 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4185 {
4191 }
4193 /* When scheduling description is not available, disable scheduler pass
4194 so it won't slow down the compilation and make x87 code slower. */
4215 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4217 && HAVE_prefetch
4223 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4224 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4229 {
4232 {
4234 ix86_gen_tls_local_dynamic_base_64
4236 }
4237 else
4238 {
4240 ix86_gen_tls_local_dynamic_base_64
4242 }
4243 }
4244 else
4248 {
4259 }
4260 else
4261 {
4272 }
4274 #ifdef USE_IX86_CLD
4275 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4278 #endif
4281 {
4286 }
4288 {
4292 }
4294 {
4295 #if defined(PROFILE_BEFORE_PROLOGUE)
4297 #else
4299 #endif
4300 }
4310 /* Enable 128-bit AVX instruction generation
4311 for the auto-vectorizer. */
4317 {
4324 {
4327 {
4329 q++;
4330 }
4331 else
4336 else
4337 {
4340 {
4343 }
4346 {
4350 }
4351 }
4356 else
4358 }
4359 }
4366 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4367 for 64-bit Bionic. Also default long double to 64-bit for Intel
4368 MCU psABI. */
4373 ? MASK_LONG_DOUBLE_128
4376 /* Only one of them can be active. */
4380 /* Save the initial options in case the user does function specific
4381 options. */
4383 target_option_default_node = target_option_current_node
4386 /* Handle stack protector */
4388 opts->x_ix86_stack_protector_guard
4391 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4393 {
4397 }
4400 {
4404 }
4405 }
4407 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4409 static void
4411 {
4413 struct register_pass_info insert_vzeroupper_info
4416 };
4421 /* This needs to be done at start up. It's convenient to do it here. */
4423 }
4425 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4428 {
4432 }
4434 /* Update register usage after having seen the compiler flags. */
4436 static void
4438 {
4441 /* For 32-bit targets, squash the REX registers. */
4443 {
4450 }
4452 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4460 {
4461 /* Set/reset conditionally defined registers from
4462 CALL_USED_REGISTERS initializer. */
4466 /* Calculate registers of CLOBBERED_REGS register set
4467 as call used registers from GENERAL_REGS register set. */
4471 }
4473 /* If MMX is disabled, squash the registers. */
4479 /* If SSE is disabled, squash the registers. */
4485 /* If the FPU is disabled, squash the registers. */
4491 /* If AVX512F is disabled, squash the registers. */
4493 {
4499 }
4501 /* If MPX is disabled, squash the registers. */
4505 }
4507 \f
4508 /* Save the current options */
4510 static void
4513 {
4549 /* The fields are char but the variables are not; make sure the
4550 values fit in the fields. */
4555 }
4557 /* Restore the current options */
4559 static void
4562 {
4568 /* We don't change -fPIC. */
4606 /* TODO: ix86_cost should be chosen at instruction or function granuality
4607 so for cold code we use size_cost even in !optimize_size compilation. */
4610 else
4613 /* Recreate the arch feature tests if the arch changed */
4615 {
4620 }
4622 /* Recreate the tune optimization tests */
4625 }
4627 /* Adjust target options after streaming them in. This is mainly about
4628 reconciling them with global options. */
4630 static void
4632 {
4633 /* flag_pic is a global option, but ix86_cmodel is target saved option
4634 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4635 for PIC, or error out. */
4638 {
4657 }
4658 else
4660 {
4675 }
4676 }
4678 /* Print the current options */
4680 static void
4683 {
4701 {
4704 }
4705 }
4707 \f
4708 /* Inner function to process the attribute((target(...))), take an argument and
4709 set the current options from the argument. If we have a list, recursively go
4710 over the list. */
4712 static bool
4717 {
4721 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4722 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4723 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4724 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4725 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4727 enum ix86_opt_type
4728 {
4729 ix86_opt_unknown,
4730 ix86_opt_yes,
4731 ix86_opt_no,
4732 ix86_opt_str,
4733 ix86_opt_enum,
4734 ix86_opt_isa
4735 };
4737 static const struct
4738 {
4745 /* isa options */
4799 /* enum options */
4802 /* string options */
4806 /* flag options */
4808 OPT_mcld,
4809 MASK_CLD),
4812 OPT_mfancy_math_387,
4813 MASK_NO_FANCY_MATH_387),
4816 OPT_mieee_fp,
4817 MASK_IEEE_FP),
4820 OPT_minline_all_stringops,
4821 MASK_INLINE_ALL_STRINGOPS),
4824 OPT_minline_stringops_dynamically,
4825 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4828 OPT_mno_align_stringops,
4829 MASK_NO_ALIGN_STRINGOPS),
4832 OPT_mrecip,
4833 MASK_RECIP),
4835 };
4837 /* If this is a list, recurse to get the options. */
4839 {
4846 enum_opts_set))
4850 }
4853 {
4856 }
4858 /* Handle multiple arguments separated by commas. */
4862 {
4876 {
4880 }
4881 else
4882 {
4885 }
4887 /* Recognize no-xxx. */
4889 {
4893 }
4894 else
4897 /* Find the option. */
4901 {
4909 {
4914 }
4915 }
4917 /* Process the option. */
4919 {
4922 }
4925 {
4931 }
4934 {
4940 else
4942 }
4945 {
4947 {
4950 }
4951 else
4953 }
4956 {
4964 global_dc);
4965 else
4966 {
4969 }
4970 }
4972 else
4974 }
4977 }
4979 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4981 tree
4985 {
5000 /* Process each of the options on the chain. */
5005 /* If the changed options are different from the default, rerun
5006 ix86_option_override_internal, and then save the options away.
5007 The string options are are attribute options, and will be undone
5008 when we copy the save structure. */
5014 {
5015 /* If we are using the default tune= or arch=, undo the string assigned,
5016 and use the default. */
5027 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
5032 {
5035 }
5037 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5040 /* Add any builtin functions with the new isa if any. */
5043 /* Save the current options unless we are validating options for
5044 #pragma. */
5051 /* Free up memory allocated to hold the strings */
5054 }
5057 }
5059 /* Hook to validate attribute((target("string"))). */
5061 static bool
5064 tree args,
5066 {
5071 /* attribute((target("default"))) does nothing, beyond
5072 affecting multi-versioning. */
5081 /* Get the optimization options of the current function. */
5087 /* Init func_options. */
5095 /* Initialize func_options to the default before its target options can
5096 be set. */
5109 {
5114 }
5117 }
5119 \f
5120 /* Hook to determine if one function can safely inline another. */
5122 static bool
5124 {
5129 /* If callee has no option attributes, then it is ok to inline. */
5133 /* If caller has no option attributes, but callee does then it is not ok to
5134 inline. */
5138 else
5139 {
5143 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5144 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5145 function. */
5150 /* See if we have the same non-isa options. */
5154 /* See if arch, tune, etc. are the same. */
5167 else
5169 }
5172 }
5174 \f
5175 /* Remember the last target of ix86_set_current_function. */
5178 /* Set targets globals to the default (or current #pragma GCC target
5179 if active). Invalidate ix86_previous_fndecl cache. */
5181 void
5183 {
5190 else
5193 }
5195 /* Establish appropriate back-end context for processing the function
5196 FNDECL. The argument might be NULL to indicate processing at top
5197 level, outside of any function scope. */
5198 static void
5200 {
5201 /* Only change the context if the function changes. This hook is called
5202 several times in the course of compiling a function, and we don't want to
5203 slow things down too much or call target_reinit when it isn't safe. */
5207 tree old_tree;
5212 else
5216 {
5220 }
5227 {
5233 else
5235 }
5237 }
5239 \f
5240 /* Return true if this goes in large data/bss. */
5242 static bool
5244 {
5248 /* Functions are never large data. */
5252 /* Automatic variables are never large data. */
5257 {
5263 }
5264 else
5265 {
5268 /* If this is an incomplete type with size 0, then we can't put it
5269 in data because it might be too big when completed. Also,
5270 int_size_in_bytes returns -1 if size can vary or is larger than
5271 an integer in which case also it is safer to assume that it goes in
5272 large data. */
5275 }
5278 }
5280 /* Switch to the appropriate section for output of DECL.
5281 DECL is either a `VAR_DECL' node or a constant of some sort.
5282 RELOC indicates whether forming the initial value of DECL requires
5283 link-time relocations. */
5288 {
5290 {
5294 {
5328 /* We don't split these for medium model. Place them into
5329 default sections and hope for best. */
5331 }
5333 {
5334 /* We might get called with string constants, but get_named_section
5335 doesn't like them as they are not DECLs. Also, we need to set
5336 flags in that case. */
5340 }
5341 }
5343 }
5345 /* Select a set of attributes for section NAME based on the properties
5346 of DECL and whether or not RELOC indicates that DECL's initializer
5347 might contain runtime relocations. */
5349 static unsigned int ATTRIBUTE_UNUSED
5351 {
5365 }
5367 /* Build up a unique section name, expressed as a
5368 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5369 RELOC indicates whether the initial value of EXP requires
5370 link-time relocations. */
5372 static void ATTRIBUTE_UNUSED
5374 {
5376 {
5378 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5382 {
5406 /* We don't split these for medium model. Place them into
5407 default sections and hope for best. */
5409 }
5411 {
5418 /* If we're using one_only, then there needs to be a .gnu.linkonce
5419 prefix to the section name. */
5426 }
5427 }
5429 }
5431 #ifdef COMMON_ASM_OP
5432 /* This says how to output assembler code to declare an
5433 uninitialized external linkage data object.
5435 For medium model x86-64 we need to use .largecomm opcode for
5436 large objects. */
5437 void
5441 {
5445 else
5450 }
5451 #endif
5453 /* Utility function for targets to use in implementing
5454 ASM_OUTPUT_ALIGNED_BSS. */
5456 void
5459 {
5463 else
5466 #ifdef ASM_DECLARE_OBJECT_NAME
5469 #else
5470 /* Standard thing is just output label for the object. */
5474 }
5475 \f
5476 /* Decide whether we must probe the stack before any space allocation
5477 on this target. It's essentially TARGET_STACK_PROBE except when
5478 -fstack-check causes the stack to be already probed differently. */
5480 bool
5482 {
5483 /* Do not probe the stack twice if static stack checking is enabled. */
5488 }
5489 \f
5490 /* Decide whether we can make a sibling call to a function. DECL is the
5491 declaration of the function being targeted by the call and EXP is the
5492 CALL_EXPR representing the call. */
5494 static bool
5496 {
5500 /* If we are generating position-independent code, we cannot sibcall
5501 optimize direct calls to global functions, as the PLT requires
5502 %ebx be live. (Darwin does not have a PLT.) */
5504 && !TARGET_64BIT
5505 && flag_pic
5506 && flag_plt
5510 /* If we need to align the outgoing stack, then sibcalling would
5511 unalign the stack, which may break the called function. */
5517 {
5520 }
5521 else
5522 {
5523 /* We're looking at the CALL_EXPR, we need the type of the function. */
5528 }
5530 /* Check that the return value locations are the same. Like
5531 if we are returning floats on the 80387 register stack, we cannot
5532 make a sibcall from a function that doesn't return a float to a
5533 function that does or, conversely, from a function that does return
5534 a float to a function that doesn't; the necessary stack adjustment
5535 would not be executed. This is also the place we notice
5536 differences in the return value ABI. Note that it is ok for one
5537 of the functions to have void return type as long as the return
5538 value of the other is passed in a register. */
5543 {
5546 }
5548 ;
5553 {
5554 /* The SYSV ABI has more call-clobbered registers;
5555 disallow sibcalls from MS to SYSV. */
5559 }
5560 else
5561 {
5562 /* If this call is indirect, we'll need to be able to use a
5563 call-clobbered register for the address of the target function.
5564 Make sure that all such registers are not used for passing
5565 parameters. Note that DLLIMPORT functions are indirect. */
5568 {
5570 {
5571 /* ??? Need to count the actual number of registers to be used,
5572 not the possible number of registers. Fix later. */
5574 }
5575 }
5576 }
5578 /* Otherwise okay. That also includes certain types of indirect calls. */
5580 }
5582 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5583 and "sseregparm" calling convention attributes;
5584 arguments as in struct attribute_spec.handler. */
5586 static tree
5588 tree args,
5591 {
5596 {
5598 name);
5601 }
5603 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5605 {
5606 tree cst;
5609 {
5611 }
5614 {
5616 }
5620 {
5623 name);
5625 }
5627 {
5631 }
5634 }
5637 {
5638 /* Do not warn when emulating the MS ABI. */
5643 name);
5646 }
5648 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5650 {
5652 {
5654 }
5656 {
5658 }
5660 {
5662 }
5664 {
5666 }
5667 }
5669 /* Can combine stdcall with fastcall (redundant), regparm and
5670 sseregparm. */
5672 {
5674 {
5676 }
5678 {
5680 }
5682 {
5684 }
5685 }
5687 /* Can combine cdecl with regparm and sseregparm. */
5689 {
5691 {
5693 }
5695 {
5697 }
5699 {
5701 }
5702 }
5704 {
5707 name);
5709 {
5711 }
5713 {
5715 }
5717 {
5719 }
5720 }
5722 /* Can combine sseregparm with all attributes. */
5725 }
5727 /* The transactional memory builtins are implicitly regparm or fastcall
5728 depending on the ABI. Override the generic do-nothing attribute that
5729 these builtins were declared with, and replace it with one of the two
5730 attributes that we expect elsewhere. */
5732 static tree
5735 {
5736 tree alt;
5738 /* In no case do we want to add the placeholder attribute. */
5741 /* The 64-bit ABI is unchanged for transactional memory. */
5745 /* ??? Is there a better way to validate 32-bit windows? We have
5746 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5749 else
5750 {
5753 }
5757 }
5759 /* This function determines from TYPE the calling-convention. */
5761 unsigned int
5763 {
5766 tree attrs;
5773 {
5783 /* Regparam isn't allowed for thiscall and fastcall. */
5785 {
5790 }
5794 }
5801 || is_stdarg
5807 }
5809 /* Return 0 if the attributes for two types are incompatible, 1 if they
5810 are compatible, and 2 if they are nearly compatible (which causes a
5811 warning to be generated). */
5813 static int
5815 {
5831 }
5832 \f
5833 /* Return the regparm value for a function with the indicated TYPE and DECL.
5834 DECL may be NULL when calling function indirectly
5835 or considering a libcall. */
5837 static int
5839 {
5840 tree attr;
5851 {
5854 {
5857 }
5858 }
5864 /* Use register calling convention for local functions when possible. */
5867 {
5872 /* Caller and callee must agree on the calling convention, so
5873 checking here just optimize means that with
5874 __attribute__((optimize (...))) caller could use regparm convention
5875 and callee not, or vice versa. Instead look at whether the callee
5876 is optimized or not. */
5879 {
5882 {
5885 /* Make sure no regparm register is taken by a
5886 fixed register variable. */
5888 local_regparm++)
5892 /* We don't want to use regparm(3) for nested functions as
5893 these use a static chain pointer in the third argument. */
5897 /* Save a register for the split stack. */
5901 /* Each fixed register usage increases register pressure,
5902 so less registers should be used for argument passing.
5903 This functionality can be overriden by an explicit
5904 regparm value. */
5907 globals++;
5909 local_regparm
5914 }
5915 }
5916 }
5919 }
5921 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5922 DFmode (2) arguments in SSE registers for a function with the
5923 indicated TYPE and DECL. DECL may be NULL when calling function
5924 indirectly or considering a libcall. Return -1 if any FP parameter
5925 should be rejected by error. This is used in siutation we imply SSE
5926 calling convetion but the function is called from another function with
5927 SSE disabled. Otherwise return 0. */
5929 static int
5931 {
5934 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5935 by the sseregparm attribute. */
5938 {
5940 {
5942 {
5946 else
5949 }
5951 }
5954 }
5963 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5964 (and DFmode for SSE2) arguments in SSE registers. */
5966 /* TARGET_SSE_MATH */
5970 {
5973 {
5974 /* Refuse to produce wrong code when local function with SSE enabled
5975 is called from SSE disabled function.
5976 FIXME: We need a way to detect these cases cross-ltrans partition
5977 and avoid using SSE calling conventions on local functions called
5978 from function with SSE disabled. For now at least delay the
5979 warning until we know we are going to produce wrong code.
5980 See PR66047 */
5985 }
5986 }
5989 }
5991 /* Return true if EAX is live at the start of the function. Used by
5992 ix86_expand_prologue to determine if we need special help before
5993 calling allocate_stack_worker. */
5995 static bool
5997 {
5998 /* Cheat. Don't bother working forward from ix86_function_regparm
5999 to the function type to whether an actual argument is located in
6000 eax. Instead just look at cfg info, which is still close enough
6001 to correct at this point. This gives false positives for broken
6002 functions that might use uninitialized data that happens to be
6003 allocated in eax, but who cares? */
6005 }
6007 static bool
6009 {
6010 tree attr;
6013 {
6019 /* For 32-bit MS-ABI the default is to keep aggregate
6020 return pointer. */
6023 }
6025 }
6027 /* Value is the number of bytes of arguments automatically
6028 popped when returning from a subroutine call.
6029 FUNDECL is the declaration node of the function (as a tree),
6030 FUNTYPE is the data type of the function (as a tree),
6031 or for a library call it is an identifier node for the subroutine name.
6032 SIZE is the number of bytes of arguments passed on the stack.
6034 On the 80386, the RTD insn may be used to pop them if the number
6035 of args is fixed, but if the number is variable then the caller
6036 must pop them all. RTD can't be used for library calls now
6037 because the library is compiled with the Unix compiler.
6038 Use of RTD is a selectable option, since it is incompatible with
6039 standard Unix calling sequences. If the option is not selected,
6040 the caller must always pop the args.
6042 The attribute stdcall is equivalent to RTD on a per module basis. */
6044 static int
6046 {
6049 /* None of the 64-bit ABIs pop arguments. */
6060 /* Lose any fake structure return argument if it is passed on the stack. */
6063 {
6067 }
6070 }
6072 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6074 static bool
6076 {
6077 /* Check operand constraints in case hard registers were propagated
6078 into insn pattern. This check prevents combine pass from
6079 generating insn patterns with invalid hard register operands.
6080 These invalid insns can eventually confuse reload to error out
6081 with a spill failure. See also PRs 46829 and 46843. */
6083 {
6092 {
6100 /* For pre-AVX disallow unaligned loads/stores where the
6101 instructions don't support it. */
6105 {
6109 }
6111 /* A unary operator may be accepted by the predicate, but it
6112 is irrelevant for matching constraints. */
6117 {
6125 }
6132 /* Operand has no constraints, anything is OK. */
6137 {
6142 && operands_match_p
6146 {
6149 }
6150 }
6154 }
6155 }
6158 }
6159 \f
6160 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6162 static unsigned HOST_WIDE_INT
6164 {
6168 }
6169 \f
6170 /* Argument support functions. */
6172 /* Return true when register may be used to pass function parameters. */
6173 bool
6175 {
6184 {
6188 else
6194 }
6200 /* TODO: The function should depend on current function ABI but
6201 builtins.c would need updating then. Therefore we use the
6202 default ABI. */
6205 /* RAX is used as hidden argument to va_arg functions. */
6211 else
6219 }
6221 /* Return if we do not know how to pass TYPE solely in registers. */
6223 static bool
6225 {
6229 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6230 The layout_type routine is crafty and tries to trick us into passing
6231 currently unsupported vector types on the stack by using TImode. */
6234 }
6236 /* It returns the size, in bytes, of the area reserved for arguments passed
6237 in registers for the function represented by fndecl dependent to the used
6238 abi format. */
6239 int
6241 {
6245 else
6250 }
6252 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6253 call abi used. */
6254 enum calling_abi
6256 {
6258 {
6261 {
6263 {
6265 {
6268 {
6271 }
6272 }
6274 }
6275 }
6279 }
6281 }
6283 /* We add this as a workaround in order to use libc_has_function
6284 hook in i386.md. */
6285 bool
6287 {
6289 }
6291 static bool
6293 {
6295 {
6299 else
6301 }
6303 }
6305 static enum calling_abi
6307 {
6311 }
6313 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6314 call abi used. */
6315 enum calling_abi
6317 {
6321 }
6323 /* Write the extra assembler code needed to declare a function properly. */
6325 void
6327 tree decl)
6328 {
6332 {
6338 }
6340 #ifdef SUBTARGET_ASM_UNWIND_INIT
6342 #endif
6346 /* Output magic byte marker, if hot-patch attribute is set. */
6348 {
6350 {
6351 /* leaq [%rsp + 0], %rsp */
6354 }
6355 else
6356 {
6357 /* movl.s %edi, %edi
6358 push %ebp
6359 movl.s %esp, %ebp */
6362 }
6363 }
6364 }
6366 /* regclass.c */
6369 /* Implementation of call abi switching target hook. Specific to FNDECL
6370 the specific call register sets are set. See also
6371 ix86_conditional_register_usage for more details. */
6372 void
6374 {
6377 else
6379 }
6381 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6382 expensive re-initialization of init_regs each time we switch function context
6383 since this is needed only during RTL expansion. */
6384 static void
6386 {
6390 }
6392 /* Return 1 if pseudo register should be created and used to hold
6393 GOT address for PIC code. */
6394 bool
6396 {
6403 }
6405 /* Initialize large model PIC register. */
6407 static void
6409 {
6411 rtx tmp_reg;
6420 label));
6424 }
6426 /* Create and initialize PIC register if required. */
6427 static void
6429 {
6430 edge entry_edge;
6439 {
6442 else
6444 }
6445 else
6446 {
6447 /* If there is future mcount call in the function it is more profitable
6448 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6457 }
6465 }
6467 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6468 for a call to a function whose data type is FNTYPE.
6469 For a library call, FNTYPE is 0. */
6471 void
6475 tree fndecl,
6477 {
6484 {
6487 {
6491 }
6492 else
6494 }
6495 else
6500 /* Set up the number of registers to use for passing arguments. */
6503 {
6505 ? X86_64_REGPARM_MAX
6507 }
6509 {
6512 {
6514 ? X86_64_SSE_REGPARM_MAX
6516 }
6517 }
6525 /* Because type might mismatch in between caller and callee, we need to
6526 use actual type of function for local calls.
6527 FIXME: cgraph_analyze can be told to actually record if function uses
6528 va_start so for local functions maybe_vaarg can be made aggressive
6529 helping K&R code.
6530 FIXME: once typesytem is fixed, we won't need this code anymore. */
6544 {
6545 /* If there are variable arguments, then we won't pass anything
6546 in registers in 32-bit mode. */
6548 {
6557 }
6559 /* Use ecx and edx registers if function has fastcall attribute,
6560 else look for regparm information. */
6562 {
6565 {
6568 }
6570 {
6573 }
6574 else
6576 }
6578 /* Set up the number of SSE registers used for passing SFmode
6579 and DFmode arguments. Warn for mismatching ABI. */
6581 }
6582 }
6584 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6585 But in the case of vector types, it is some vector mode.
6587 When we have only some of our vector isa extensions enabled, then there
6588 are some modes for which vector_mode_supported_p is false. For these
6589 modes, the generic vector support in gcc will choose some non-vector mode
6590 in order to implement the type. By computing the natural mode, we'll
6591 select the proper ABI location for the operand and not depend on whatever
6592 the middle-end decides to do with these vector types.
6594 The midde-end can't deal with the vector types > 16 bytes. In this
6595 case, we return the original mode and warn ABI change if CUM isn't
6596 NULL.
6598 If INT_RETURN is true, warn ABI change if the vector mode isn't
6599 available for function return value. */
6601 static machine_mode
6604 {
6608 {
6611 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6613 {
6618 else
6621 /* Get the mode which has this inner mode and number of units. */
6625 {
6627 {
6632 {
6636 }
6638 {
6642 }
6645 }
6647 {
6652 {
6656 }
6658 {
6662 }
6665 }
6668 {
6673 {
6677 }
6679 {
6683 }
6684 }
6686 {
6691 {
6695 }
6697 {
6701 }
6702 }
6704 }
6707 }
6708 }
6711 }
6713 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6714 this may not agree with the mode that the type system has chosen for the
6715 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6716 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6718 static rtx
6721 {
6722 rtx tmp;
6726 else
6727 {
6731 }
6734 }
6736 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6737 of this code is to classify each 8bytes of incoming argument by the register
6738 class and assign registers accordingly. */
6740 /* Return the union class of CLASS1 and CLASS2.
6741 See the x86-64 PS ABI for details. */
6743 static enum x86_64_reg_class
6745 {
6746 /* Rule #1: If both classes are equal, this is the resulting class. */
6750 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6751 the other class. */
6757 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6761 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6769 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6770 MEMORY is used. */
6779 /* Rule #6: Otherwise class SSE is used. */
6781 }
6783 /* Classify the argument of type TYPE and mode MODE.
6784 CLASSES will be filled by the register class used to pass each word
6785 of the operand. The number of words is returned. In case the parameter
6786 should be passed in memory, 0 is returned. As a special case for zero
6787 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6789 BIT_OFFSET is used internally for handling records and specifies offset
6790 of the offset in bits modulo 512 to avoid overflow cases.
6792 See the x86-64 PS ABI for details.
6793 */
6795 static int
6798 {
6799 HOST_WIDE_INT bytes =
6801 int words
6804 /* Variable sized entities are always passed/returned in memory. */
6813 {
6815 tree field;
6818 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6825 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6826 signalize memory class, so handle it as special case. */
6828 {
6831 }
6833 /* Classify each field of record and merge classes. */
6835 {
6837 /* And now merge the fields of structure. */
6839 {
6841 {
6847 /* Bitfields are always classified as integer. Handle them
6848 early, since later code would consider them to be
6849 misaligned integers. */
6851 {
6860 }
6861 else
6862 {
6867 /* Flexible array member is ignored. */
6874 {
6878 {
6881 "the ABI of passing struct with"
6882 " a flexible array member has"
6884 }
6886 }
6888 subclasses,
6898 }
6899 }
6900 }
6904 /* Arrays are handled as small records. */
6905 {
6912 /* The partial classes are now full classes. */
6923 }
6926 /* Unions are similar to RECORD_TYPE but offset is always 0.
6927 */
6929 {
6931 {
6939 bit_offset);
6944 }
6945 }
6950 }
6953 {
6954 /* When size > 16 bytes, if the first one isn't
6955 X86_64_SSE_CLASS or any other ones aren't
6956 X86_64_SSEUP_CLASS, everything should be passed in
6957 memory. */
6964 }
6966 /* Final merger cleanup. */
6968 {
6969 /* If one class is MEMORY, everything should be passed in
6970 memory. */
6974 /* The X86_64_SSEUP_CLASS should be always preceded by
6975 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6979 {
6980 /* The first one should never be X86_64_SSEUP_CLASS. */
6983 }
6985 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6986 everything should be passed in memory. */
6989 {
6992 /* The first one should never be X86_64_X87UP_CLASS. */
6995 {
6998 "the ABI of passing union with long double"
7000 }
7002 }
7003 }
7005 }
7007 /* Compute alignment needed. We align all types to natural boundaries with
7008 exception of XFmode that is aligned to 64bits. */
7010 {
7019 /* Misaligned fields are always returned in memory. */
7022 }
7024 /* for V1xx modes, just use the base mode */
7029 /* Classification of atomic types. */
7031 {
7047 {
7050 /* Analyze last 128 bits only. */
7054 {
7057 }
7059 {
7062 }
7064 {
7068 }
7070 {
7073 }
7074 else
7076 }
7083 /* OImode shouldn't be used directly. */
7090 else
7108 else
7109 {
7113 {
7116 "the ABI of passing structure with complex float"
7118 }
7121 }
7130 /* This modes is larger than 16 bytes. */
7188 else
7192 }
7193 }
7195 /* Examine the argument and return set number of register required in each
7196 class. Return true iff parameter should be passed in memory. */
7198 static bool
7201 {
7212 {
7233 }
7236 }
7238 /* Construct container for the argument used by GCC interface. See
7239 FUNCTION_ARG for the detailed description. */
7241 static rtx
7245 {
7246 /* The following variables hold the static issued_error state. */
7251 machine_mode tmpmode;
7260 rtx ret;
7271 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7272 some less clueful developer tries to use floating-point anyway. */
7274 {
7276 {
7278 {
7281 }
7282 }
7284 {
7287 }
7289 }
7291 /* Likewise, error if the ABI requires us to return values in the
7292 x87 registers and the user specified -mno-80387. */
7298 {
7300 {
7303 }
7305 }
7307 /* First construct simple cases. Avoid SCmode, since we want to use
7308 single register to pass this type. */
7311 {
7326 /* Zero sized array, struct or class. */
7330 }
7369 /* Otherwise figure out the entries of the PARALLEL. */
7371 {
7375 {
7380 /* Merge TImodes on aligned occasions here too. */
7382 tmpmode
7386 else
7388 /* We've requested 24 bytes we
7389 don't have mode for. Use DImode. */
7396 intreg++;
7404 sse_regno++;
7412 sse_regno++;
7417 {
7423 {
7425 i++;
7426 }
7427 else
7452 }
7458 sse_regno++;
7462 }
7463 }
7465 /* Empty aligned struct, union or class. */
7473 }
7475 /* Update the data in CUM to advance over an argument of mode MODE
7476 and data type TYPE. (TYPE is null for libcalls where that information
7477 may not be available.)
7479 Return a number of integer regsiters advanced over. */
7481 static int
7484 HOST_WIDE_INT words)
7485 {
7490 {
7491 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7492 bytes in registers. */
7496 }
7499 {
7506 /* FALLTHRU */
7512 pass_in_reg:
7519 {
7522 }
7526 /* OImode shouldn't be used directly. */
7539 /* FALLTHRU */
7561 {
7566 {
7569 }
7570 }
7580 {
7585 {
7588 }
7589 }
7591 }
7593 {
7599 }
7602 }
7604 static int
7607 {
7610 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7617 {
7623 }
7624 else
7625 {
7630 }
7631 }
7633 static int
7635 HOST_WIDE_INT words)
7636 {
7637 /* Otherwise, this should be passed indirect. */
7642 {
7646 }
7648 }
7650 /* Update the data in CUM to advance over an argument of mode MODE and
7651 data type TYPE. (TYPE is null for libcalls where that information
7652 may not be available.) */
7654 static void
7657 {
7664 else
7673 {
7674 /* If we pass bounds in BT then just update remained bounds count. */
7676 {
7679 }
7681 /* Update remained number of bounds to force. */
7688 }
7690 /* The first arg not going to Bounds Tables resets this counter. */
7692 /* For unnamed args we always pass bounds to avoid bounds mess when
7693 passed and received types do not match. If bounds do not follow
7694 unnamed arg, still pretend required number of bounds were passed. */
7696 {
7699 }
7702 {
7707 else
7709 }
7710 else
7713 /* For stdarg we expect bounds to be passed for each value passed
7714 in register. */
7717 /* For pointers passed in memory we expect bounds passed in Bounds
7718 Table. */
7721 }
7723 /* Define where to put the arguments to a function.
7724 Value is zero to push the argument on the stack,
7725 or a hard register in which to store the argument.
7727 MODE is the argument's machine mode.
7728 TYPE is the data type of the argument (as a tree).
7729 This is null for libcalls where that information may
7730 not be available.
7731 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7732 the preceding args and about the function being called.
7733 NAMED is nonzero if this argument is a named parameter
7734 (otherwise it is an extra parameter matching an ellipsis). */
7736 static rtx
7740 {
7742 /* Avoid the AL settings for the Unix64 ABI. */
7747 {
7748 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7749 bytes in registers. */
7753 }
7756 {
7763 /* FALLTHRU */
7768 pass_in_reg:
7770 {
7773 /* Fastcall allocates the first two DWORD (SImode) or
7774 smaller arguments to ECX and EDX if it isn't an
7775 aggregate type . */
7777 {
7783 /* ECX not EAX is the first allocated register. */
7786 }
7788 }
7801 /* FALLTHRU */
7803 /* In 32bit, we pass TImode in xmm registers. */
7811 {
7815 }
7820 /* OImode and XImode shouldn't be used directly. */
7836 {
7840 }
7850 {
7854 }
7856 }
7858 {
7864 }
7867 }
7869 static rtx
7872 {
7873 /* Handle a hidden AL argument containing number of registers
7874 for varargs x86-64 functions. */
7878 ? X86_64_SSE_REGPARM_MAX
7883 {
7899 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7903 }
7909 }
7911 static rtx
7914 HOST_WIDE_INT bytes)
7915 {
7918 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7919 We use value of -2 to specify that current function call is MSABI. */
7923 /* If we've run out of registers, it goes on the stack. */
7929 /* Only floating point modes are passed in anything but integer regs. */
7931 {
7934 else
7935 {
7938 /* Unnamed floating parameters are passed in both the
7939 SSE and integer registers. */
7945 }
7946 }
7947 /* Handle aggregated types passed in register. */
7949 {
7954 }
7957 }
7959 /* Return where to put the arguments to a function.
7960 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7962 MODE is the argument's machine mode. TYPE is the data type of the
7963 argument. It is null for libcalls where that information may not be
7964 available. CUM gives information about the preceding args and about
7965 the function being called. NAMED is nonzero if this argument is a
7966 named parameter (otherwise it is an extra parameter matching an
7967 ellipsis). */
7969 static rtx
7972 {
7976 rtx arg;
7978 /* All pointer bounds argumntas are handled separately here. */
7981 {
7982 /* Return NULL if bounds are forced to go in Bounds Table. */
7985 /* Return the next available bound reg if any. */
7988 /* Return the next special slot number otherwise. */
7989 else
7993 }
7997 else
8001 /* To simplify the code below, represent vector types with a vector mode
8002 even if MMX/SSE are not active. */
8007 {
8012 else
8014 }
8015 else
8019 }
8021 /* A C expression that indicates when an argument must be passed by
8022 reference. If nonzero for an argument, a copy of that argument is
8023 made in memory and a pointer to the argument is passed instead of
8024 the argument itself. The pointer is passed in whatever way is
8025 appropriate for passing a pointer to that type. */
8027 static bool
8030 {
8033 /* Bounds are never passed by reference. */
8039 {
8042 /* See Windows x64 Software Convention. */
8044 {
8048 {
8049 /* Arrays are passed by reference. */
8054 {
8055 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
8056 are passed by reference. */
8058 }
8059 }
8061 /* __m128 is passed by reference. */
8063 }
8066 }
8069 }
8071 /* Return true when TYPE should be 128bit aligned for 32bit argument
8072 passing ABI. XXX: This function is obsolete and is only used for
8073 checking psABI compatibility with previous versions of GCC. */
8075 static bool
8077 {
8089 {
8090 /* Walk the aggregates recursively. */
8092 {
8096 {
8097 tree field;
8099 /* Walk all the structure fields. */
8101 {
8105 }
8107 }
8110 /* Just for use if some languages passes arrays by value. */
8117 }
8118 }
8120 }
8122 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8123 XXX: This function is obsolete and is only used for checking psABI
8124 compatibility with previous versions of GCC. */
8126 static unsigned int
8129 {
8130 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8131 natural boundaries. */
8133 {
8134 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8135 make an exception for SSE modes since these require 128bit
8136 alignment.
8138 The handling here differs from field_alignment. ICC aligns MMX
8139 arguments to 4 byte boundaries, while structure fields are aligned
8140 to 8 byte boundaries. */
8142 {
8145 }
8146 else
8147 {
8150 }
8151 }
8155 }
8157 /* Return true when TYPE should be 128bit aligned for 32bit argument
8158 passing ABI. */
8160 static bool
8162 {
8172 {
8173 /* Walk the aggregates recursively. */
8175 {
8179 {
8180 tree field;
8182 /* Walk all the structure fields. */
8184 field;
8186 {
8190 }
8192 }
8195 /* Just for use if some languages passes arrays by value. */
8202 }
8203 }
8204 else
8208 }
8210 /* Gives the alignment boundary, in bits, of an argument with the
8211 specified mode and type. */
8213 static unsigned int
8215 {
8218 {
8219 /* Since the main variant type is used for call, we convert it to
8220 the main variant type. */
8223 }
8224 else
8228 else
8229 {
8234 {
8235 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8237 {
8240 }
8246 }
8249 && !warned
8251 saved_align))
8252 {
8255 "The ABI for passing parameters with %d-byte"
8258 }
8259 }
8262 }
8264 /* Return true if N is a possible register number of function value. */
8266 static bool
8268 {
8270 {
8283 /* Complex values are returned in %st(0)/%st(1) pair. */
8286 /* TODO: The function should depend on current function ABI but
8287 builtins.c would need updating then. Therefore we use the
8288 default ABI. */
8293 /* Complex values are returned in %xmm0/%xmm1 pair. */
8302 }
8305 }
8307 /* Define how to find the value returned by a function.
8308 VALTYPE is the data type of the value (as a tree).
8309 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8310 otherwise, FUNC is 0. */
8312 static rtx
8315 {
8318 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8319 we normally prevent this case when mmx is not available. However
8320 some ABIs may require the result to be returned like DImode. */
8324 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8325 we prevent this case when sse is not available. However some ABIs
8326 may require the result to be returned like integer TImode. */
8331 /* 32-byte vector modes in %ymm0. */
8335 /* 64-byte vector modes in %zmm0. */
8339 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8342 else
8343 /* Most things go in %eax. */
8346 /* Override FP return register with %xmm0 for local functions when
8347 SSE math is enabled or for functions with sseregparm attribute. */
8349 {
8352 {
8357 }
8361 }
8363 /* OImode shouldn't be used directly. */
8367 }
8369 static rtx
8371 const_tree valtype)
8372 {
8373 rtx ret;
8375 /* Handle libcalls, which don't provide a type node. */
8377 {
8381 {
8400 }
8403 }
8405 {
8406 /* Pointers are always returned in word_mode. */
8408 }
8414 /* For zero sized structures, construct_container returns NULL, but we
8415 need to keep rest of compiler happy by returning meaningful value. */
8420 }
8422 static rtx
8424 const_tree valtype)
8425 {
8429 {
8431 {
8450 }
8451 }
8453 }
8455 static rtx
8458 {
8473 else
8475 }
8477 static rtx
8479 {
8485 }
8487 /* Return an RTX representing a place where a function returns
8488 or recieves pointer bounds or NULL if no bounds are returned.
8490 VALTYPE is a data type of a value returned by the function.
8492 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8493 or FUNCTION_TYPE of the function.
8495 If OUTGOING is false, return a place in which the caller will
8496 see the return value. Otherwise, return a place where a
8497 function returns a value. */
8499 static rtx
8501 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8503 {
8509 {
8510 bitmap slots;
8512 bitmap_iterator bi;
8520 {
8525 }
8531 }
8532 else
8536 }
8538 /* Pointer function arguments and return values are promoted to
8539 word_mode. */
8541 static machine_mode
8545 {
8547 {
8550 }
8552 for_return);
8553 }
8555 /* Return true if a structure, union or array with MODE containing FIELD
8556 should be accessed using BLKmode. */
8558 static bool
8560 {
8561 /* Union with XFmode must be in BLKmode. */
8565 }
8567 rtx
8569 {
8571 }
8573 /* Return true iff type is returned in memory. */
8575 static bool
8577 {
8578 #ifdef SUBTARGET_RETURN_IN_MEMORY
8580 #else
8582 HOST_WIDE_INT size;
8588 {
8590 {
8593 /* __m128 is returned in xmm0. */
8602 /* Otherwise, the size must be exactly in [1248]. */
8604 }
8605 else
8606 {
8611 }
8612 }
8613 else
8614 {
8617 /* Intel MCU psABI returns scalars and aggregates no larger than 8
8618 bytes in registers. */
8629 {
8630 /* User-created vectors small enough to fit in EAX. */
8634 /* Unless ABI prescibes otherwise,
8635 MMX/3dNow values are returned in MM0 if available. */
8640 /* SSE values are returned in XMM0 if available. */
8644 /* AVX values are returned in YMM0 if available. */
8648 /* AVX512F values are returned in ZMM0 if available. */
8651 }
8659 /* OImode shouldn't be used directly. */
8663 }
8664 #endif
8665 }
8667 \f
8668 /* Create the va_list data type. */
8670 /* Returns the calling convention specific va_list date type.
8671 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8673 static tree
8675 {
8678 /* For i386 we use plain pointer to argument area. */
8688 unsigned_type_node);
8691 unsigned_type_node);
8694 ptr_type_node);
8697 ptr_type_node);
8716 /* The correct type is an array type of one element. */
8718 }
8720 /* Setup the builtin va_list data type and for 64-bit the additional
8721 calling convention specific va_list data types. */
8723 static tree
8725 {
8728 /* Initialize abi specific va_list builtin types. */
8730 {
8731 tree t;
8733 {
8738 }
8739 else
8740 {
8745 }
8747 {
8752 }
8753 else
8754 {
8759 }
8760 }
8763 }
8765 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8767 static void
8769 {
8771 alias_set_type set;
8774 /* GPR size of varargs save area. */
8777 else
8780 /* FPR size of varargs save area. We don't need it if we don't pass
8781 anything in SSE registers. */
8784 else
8798 {
8806 }
8809 {
8810 machine_mode smode;
8812 rtx test;
8814 /* Now emit code to save SSE registers. The AX parameter contains number
8815 of SSE parameter registers used to call this function, though all we
8816 actually check here is the zero/non-zero status. */
8821 label));
8823 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8824 we used movdqa (i.e. TImode) instead? Perhaps even better would
8825 be if we could determine the real mode of the data, via a hook
8826 into pass_stdarg. Ignore all that for now. */
8836 {
8845 }
8848 }
8849 }
8851 static void
8853 {
8857 /* Reset to zero, as there might be a sysv vaarg used
8858 before. */
8863 {
8874 }
8875 }
8877 static void
8880 {
8882 CUMULATIVE_ARGS next_cum;
8883 tree fntype;
8885 /* This argument doesn't appear to be used anymore. Which is good,
8886 because the old code here didn't suppress rtl generation. */
8894 /* For varargs, we do not want to skip the dummy va_dcl argument.
8895 For stdargs, we do want to skip the last named argument. */
8903 else
8905 }
8907 static void
8910 tree type,
8913 {
8915 CUMULATIVE_ARGS next_cum;
8916 tree fntype;
8917 rtx save_area;
8922 /* Do nothing if we use plain pointer to argument area. */
8928 /* For varargs, we do not want to skip the dummy va_dcl argument.
8929 For stdargs, we do want to skip the last named argument. */
8943 {
8947 rtx bounds;
8951 else
8952 {
8953 rtx ldx_addr =
8960 }
8966 bnd_reg++;
8967 }
8968 }
8971 /* Checks if TYPE is of kind va_list char *. */
8973 static bool
8975 {
8976 tree canonic;
8978 /* For 32-bit it is always true. */
8984 }
8986 /* Implement va_start. */
8988 static void
8990 {
8994 tree type;
8995 rtx ovf_rtx;
8999 {
9002 /* When we are splitting the stack, we can't refer to the stack
9003 arguments using internal_arg_pointer, because they may be on
9004 the old stack. The split stack prologue will arrange to
9005 leave a pointer to the old stack arguments in a scratch
9006 register, which we here copy to a pseudo-register. The split
9007 stack prologue can't set the pseudo-register directly because
9008 it (the prologue) runs before any registers have been saved. */
9012 {
9013 rtx reg;
9027 }
9028 }
9030 /* Only 64bit target needs something special. */
9032 {
9035 else
9036 {
9046 /* Store zero bounds for va_list. */
9050 next));
9052 }
9054 }
9063 /* The following should be folded into the MEM_REF offset. */
9073 /* Count number of gp and fp argument registers used. */
9079 {
9085 }
9088 {
9094 }
9096 /* Find the overflow area. */
9100 else
9106 /* Store zero bounds for overflow area pointer. */
9115 {
9116 /* Find the register save area.
9117 Prologue of the function save it right above stack frame. */
9123 /* Store zero bounds for save area pointer. */
9130 }
9131 }
9133 /* Implement va_arg. */
9135 static tree
9138 {
9145 rtx container;
9147 tree ptrtype;
9148 machine_mode nat_mode;
9151 /* Only 64bit target needs something special. */
9175 {
9188 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9190 {
9193 }
9201 }
9203 /* Pull the value out of the saved registers. */
9208 {
9222 /* In case we are passing structure, verify that it is consecutive block
9223 on the register save area. If not we need to do moves. */
9225 {
9226 /* Verify that all registers are strictly consecutive */
9228 {
9232 {
9237 }
9238 }
9239 else
9240 {
9244 {
9249 }
9250 }
9251 }
9253 {
9256 }
9257 else
9258 {
9261 }
9263 /* First ensure that we fit completely in registers. */
9265 {
9272 }
9274 {
9282 }
9284 /* Compute index to start of area used for integer regs. */
9286 {
9287 /* int_addr = gpr + sav; */
9290 }
9292 {
9293 /* sse_addr = fpr + sav; */
9296 }
9298 {
9302 /* addr = &temp; */
9307 {
9311 tree piece_type;
9312 tree addr_type;
9313 tree daddr_type;
9322 {
9327 }
9331 else
9338 {
9341 }
9342 else
9343 {
9346 }
9353 {
9358 }
9359 else
9360 {
9361 tree copy
9366 }
9368 }
9369 }
9372 {
9376 }
9379 {
9383 }
9388 }
9390 /* ... otherwise out of the overflow area. */
9392 /* When we align parameter on stack for caller, if the parameter
9393 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9394 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9395 here with caller. */
9400 /* Care for on-stack alignment if needed. */
9403 else
9404 {
9409 }
9426 }
9427 \f
9428 /* Return true if OPNUM's MEM should be matched
9429 in movabs* patterns. */
9431 bool
9433 {
9445 }
9446 \f
9447 /* Initialize the table of extra 80387 mathematical constants. */
9449 static void
9451 {
9453 {
9459 };
9463 {
9465 /* Ensure each constant is rounded to XFmode precision. */
9468 }
9471 }
9473 /* Return non-zero if the constant is something that
9474 can be loaded with a special instruction. */
9476 int
9478 {
9481 REAL_VALUE_TYPE r;
9493 /* For XFmode constants, try to find a special 80387 instruction when
9494 optimizing for size or on those CPUs that benefit from them. */
9497 {
9506 }
9508 /* Load of the constant -0.0 or -1.0 will be split as
9509 fldz;fchs or fld1;fchs sequence. */
9516 }
9518 /* Return the opcode of the special instruction to be used to load
9519 the constant X. */
9523 {
9525 {
9545 }
9546 }
9548 /* Return the CONST_DOUBLE representing the 80387 constant that is
9549 loaded by the specified special instruction. The argument IDX
9550 matches the return value from standard_80387_constant_p. */
9552 rtx
9554 {
9561 {
9572 }
9575 XFmode);
9576 }
9578 /* Return 1 if X is all 0s and 2 if x is all 1s
9579 in supported SSE/AVX vector mode. */
9581 int
9583 {
9584 machine_mode mode;
9595 {
9616 }
9619 }
9621 /* Return the opcode of the special instruction to be used to load
9622 the constant X. */
9626 {
9628 {
9631 {
9658 }
9668 else
9673 }
9675 }
9677 /* Returns true if OP contains a symbol reference */
9679 bool
9681 {
9690 {
9692 {
9698 }
9702 }
9705 }
9707 /* Return true if it is appropriate to emit `ret' instructions in the
9708 body of a function. Do this only if the epilogue is simple, needing a
9709 couple of insns. Prior to reloading, we can't tell how many registers
9710 must be saved, so return false then. Return false if there is no frame
9711 marker to de-allocate. */
9713 bool
9715 {
9721 /* Don't allow more than 32k pop, since that's all we can do
9722 with one instruction. */
9729 }
9730 \f
9731 /* Value should be nonzero if functions must have frame pointers.
9732 Zero means the frame pointer need not be set up (and parms may
9733 be accessed via the stack pointer) in functions that seem suitable. */
9735 static bool
9737 {
9738 /* If we accessed previous frames, then the generated code expects
9739 to be able to access the saved ebp value in our frame. */
9743 /* Several x86 os'es need a frame pointer for other reasons,
9744 usually pertaining to setjmp. */
9748 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9752 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9753 allocation is 4GB. */
9757 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9758 turns off the frame pointer by default. Turn it back on now if
9759 we've not got a leaf function. */
9769 }
9771 /* Record that the current function accesses previous call frames. */
9773 void
9775 {
9777 }
9778 \f
9779 #ifndef USE_HIDDEN_LINKONCE
9780 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9781 # define USE_HIDDEN_LINKONCE 1
9782 # else
9783 # define USE_HIDDEN_LINKONCE 0
9784 # endif
9785 #endif
9789 /* Fills in the label name that should be used for a pc thunk for
9790 the given register. */
9792 static void
9794 {
9799 else
9801 }
9804 /* This function generates code for -fpic that loads %ebx with
9805 the return address of the caller and then returns. */
9807 static void
9809 {
9814 {
9816 tree decl;
9832 #if TARGET_MACHO
9834 {
9843 }
9844 else
9845 #endif
9847 {
9858 }
9859 else
9860 {
9863 }
9869 /* Make sure unwind info is emitted for the thunk if needed. */
9872 /* Pad stack IP move with 4 instructions (two NOPs count
9873 as one instruction). */
9875 {
9880 }
9891 }
9895 }
9897 /* Emit code for the SET_GOT patterns. */
9901 {
9907 {
9908 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9913 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9914 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9915 an unadorned address. */
9920 }
9925 {
9927 /* We don't need a pic base, we're not producing pic. */
9934 }
9935 else
9936 {
9945 #if TARGET_MACHO
9946 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9947 This is what will be referenced by the Mach-O PIC subsystem. */
9951 /* When we are restoring the pic base at the site of a nonlocal label,
9952 and we decided to emit the pic base above, we will still output a
9953 local label used for calculating the correction offset (even though
9954 the offset will be 0 in that case). */
9958 #endif
9959 }
9965 }
9967 /* Generate an "push" pattern for input ARG. */
9969 static rtx
9971 {
9983 stack_pointer_rtx)),
9984 arg);
9985 }
9987 /* Generate an "pop" pattern for input ARG. */
9989 static rtx
9991 {
9998 stack_pointer_rtx)));
9999 }
10001 /* Return >= 0 if there is an unused call-clobbered register available
10002 for the entire function. */
10004 static unsigned int
10006 {
10013 {
10015 /* Can't use the same register for both PIC and DRAP. */
10018 else
10023 }
10026 }
10028 /* Return TRUE if we need to save REGNO. */
10030 static bool
10032 {
10035 {
10037 {
10038 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
10039 _mcount in prologue. */
10042 }
10049 }
10052 {
10055 {
10061 }
10062 }
10073 }
10075 /* Return number of saved general prupose registers. */
10077 static int
10079 {
10085 nregs ++;
10087 }
10089 /* Return number of saved SSE registrers. */
10091 static int
10093 {
10101 nregs ++;
10103 }
10105 /* Given FROM and TO register numbers, say whether this elimination is
10106 allowed. If stack alignment is needed, we can only replace argument
10107 pointer with hard frame pointer, or replace frame pointer with stack
10108 pointer. Otherwise, frame pointer elimination is automatically
10109 handled and all other eliminations are valid. */
10111 static bool
10113 {
10119 else
10121 }
10123 /* Return the offset between two registers, one to be eliminated, and the other
10124 its replacement, at the start of a routine. */
10126 HOST_WIDE_INT
10128 {
10137 else
10138 {
10146 }
10147 }
10149 /* In a dynamically-aligned function, we can't know the offset from
10150 stack pointer to frame pointer, so we must ensure that setjmp
10151 eliminates fp against the hard fp (%ebp) rather than trying to
10152 index from %esp up to the top of the frame across a gap that is
10153 of unknown (at compile-time) size. */
10154 static rtx
10156 {
10158 }
10160 /* When using -fsplit-stack, the allocation routines set a field in
10161 the TCB to the bottom of the stack plus this much space, measured
10162 in bytes. */
10164 #define SPLIT_STACK_AVAILABLE 256
10166 /* Fill structure ix86_frame about frame of currently computed function. */
10168 static void
10170 {
10172 HOST_WIDE_INT offset;
10175 HOST_WIDE_INT to_allocate;
10180 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10181 function prologues and leaf. */
10185 {
10188 }
10189 /* preferred_stack_boundary is never updated for call
10190 expanded from tls descriptor. Update it here. We don't update it in
10191 expand stage because according to the comments before
10192 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10193 away. */
10196 {
10200 }
10209 /* For SEH we have to limit the amount of code movement into the prologue.
10210 At present we do this via a BLOCKAGE, at which point there's very little
10211 scheduling that can be done, which means that there's very little point
10212 in doing anything except PUSHs. */
10216 /* During reload iteration the amount of registers saved can change.
10217 Recompute the value as needed. Do not recompute when amount of registers
10218 didn't change as reload does multiple calls to the function and does not
10219 expect the decision to change within single iteration. */
10222 {
10228 /* The fast prologue uses move instead of push to save registers. This
10229 is significantly longer, but also executes faster as modern hardware
10230 can execute the moves in parallel, but can't do that for push/pop.
10232 Be careful about choosing what prologue to emit: When function takes
10233 many instructions to execute we may use slow version as well as in
10234 case function is known to be outside hot spot (this is known with
10235 feedback only). Weight the size of function by number of registers
10236 to save as it is cheap to use one or two push instructions but very
10237 slow to use many of them. */
10241 || (flag_branch_probabilities
10244 else
10247 }
10249 frame->save_regs_using_mov
10251 /* If static stack checking is enabled and done with probes,
10252 the registers need to be saved before allocating the frame. */
10255 /* Skip return address. */
10258 /* Skip pushed static chain. */
10262 /* Skip saved base pointer. */
10267 /* The traditional frame pointer location is at the top of the frame. */
10270 /* Register save area */
10274 /* On SEH target, registers are pushed just before the frame pointer
10275 location. */
10279 /* Align and set SSE register save area. */
10281 {
10282 /* The only ABI that has saved SSE registers (Win64) also has a
10283 16-byte aligned default stack, and thus we don't need to be
10284 within the re-aligned local stack frame to save them. */
10288 }
10291 /* The re-aligned stack starts here. Values before this point are not
10292 directly comparable with values below this point. In order to make
10293 sure that no value happens to be the same before and after, force
10294 the alignment computation below to add a non-zero value. */
10298 /* Va-arg area */
10302 /* Align start of frame for local function. */
10311 /* Frame pointer points here. */
10316 /* Add outgoing arguments area. Can be skipped if we eliminated
10317 all the function calls as dead code.
10318 Skipping is however impossible when function calls alloca. Alloca
10319 expander assumes that last crtl->outgoing_args_size
10320 of stack frame are unused. */
10324 {
10327 }
10328 else
10331 /* Align stack boundary. Only needed if we're calling another function
10332 or using alloca. */
10337 /* We've reached end of stack frame. */
10340 /* Size prologue needs to allocate. */
10351 {
10357 }
10358 else
10362 /* The SEH frame pointer location is near the bottom of the frame.
10363 This is enforced by the fact that the difference between the
10364 stack pointer and the frame pointer is limited to 240 bytes in
10365 the unwind data structure. */
10367 {
10368 HOST_WIDE_INT diff;
10370 /* If we can leave the frame pointer where it is, do so. Also, returns
10371 the establisher frame for __builtin_frame_address (0). */
10376 {
10377 /* Ideally we'd determine what portion of the local stack frame
10378 (within the constraint of the lowest 240) is most heavily used.
10379 But without that complication, simply bias the frame pointer
10380 by 128 bytes so as to maximize the amount of the local stack
10381 frame that is addressable with 8-bit offsets. */
10383 }
10384 }
10385 }
10387 /* This is semi-inlined memory_address_length, but simplified
10388 since we know that we're always dealing with reg+offset, and
10389 to avoid having to create and discard all that rtl. */
10393 {
10397 {
10398 /* EBP and R13 cannot be encoded without an offset. */
10400 }
10404 /* ESP and R12 must be encoded with a SIB byte. */
10406 len++;
10409 }
10411 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10412 The valid base registers are taken from CFUN->MACHINE->FS. */
10414 static rtx
10416 {
10422 {
10423 /* Choose the base register most likely to allow the most scheduling
10424 opportunities. Generally FP is valid throughout the function,
10425 while DRAP must be reloaded within the epilogue. But choose either
10426 over the SP due to increased encoding size. */
10429 {
10432 }
10434 {
10437 }
10439 {
10442 }
10443 }
10444 else
10445 {
10446 HOST_WIDE_INT toffset;
10449 /* Choose the base register with the smallest address encoding.
10450 With a tie, choose FP > DRAP > SP. */
10452 {
10456 }
10458 {
10462 {
10466 }
10467 }
10469 {
10473 {
10477 }
10478 }
10479 }
10483 }
10485 /* Emit code to save registers in the prologue. */
10487 static void
10489 {
10495 {
10498 }
10499 }
10501 /* Emit a single register save at CFA - CFA_OFFSET. */
10503 static void
10505 HOST_WIDE_INT cfa_offset)
10506 {
10514 /* For SSE saves, we need to indicate the 128-bit alignment. */
10525 /* When saving registers into a re-aligned local stack frame, avoid
10526 any tricky guessing by dwarf2out. */
10528 {
10532 {
10533 /* A bit of a hack. We force the DRAP register to be saved in
10534 the re-aligned stack frame, which provides us with a copy
10535 of the CFA that will last past the prologue. Install it. */
10541 }
10542 else
10543 {
10544 /* The frame pointer is a stable reference within the
10545 aligned frame. Use it. */
10551 }
10552 }
10554 /* The memory may not be relative to the current CFA register,
10555 which means that we may need to generate a new pattern for
10556 use by the unwind info. */
10558 {
10563 }
10564 }
10566 /* Emit code to save registers using MOV insns.
10567 First register is stored at CFA - CFA_OFFSET. */
10568 static void
10570 {
10575 {
10578 }
10579 }
10581 /* Emit code to save SSE registers using MOV insns.
10582 First register is stored at CFA - CFA_OFFSET. */
10583 static void
10585 {
10590 {
10593 }
10594 }
10598 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10599 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10600 Don't add the note if the previously saved value will be left untouched
10601 within stack red-zone till return, as unwinders can find the same value
10602 in the register and on the stack. */
10604 static void
10606 {
10612 {
10615 }
10616 else
10617 queued_cfa_restores
10619 }
10621 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10623 static void
10625 {
10626 rtx last;
10630 ;
10635 }
10637 /* Expand prologue or epilogue stack adjustment.
10638 The pattern exist to put a dependency on all ebp-based memory accesses.
10639 STYLE should be negative if instructions should be marked as frame related,
10640 zero if %r11 register is live and cannot be freely used and positive
10641 otherwise. */
10643 static void
10646 {
10648 rtx insn;
10655 else
10656 {
10657 rtx tmp;
10658 /* r11 is used by indirect sibcall return as well, set before the
10659 epilogue and used after the epilogue. */
10662 else
10663 {
10667 }
10673 }
10680 {
10681 rtx r;
10691 }
10693 {
10696 {
10700 }
10701 }
10704 {
10709 {
10712 }
10714 {
10717 }
10718 else
10719 {
10720 /* Else there are two possibilities: SP itself, which we set
10721 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10722 taken care of this by hand along the eh_return path. */
10725 }
10729 }
10730 }
10732 /* Find an available register to be used as dynamic realign argument
10733 pointer regsiter. Such a register will be written in prologue and
10734 used in begin of body, so it must not be
10735 1. parameter passing register.
10736 2. GOT pointer.
10737 We reuse static-chain register if it is available. Otherwise, we
10738 use DI for i386 and R13 for x86-64. We chose R13 since it has
10739 shorter encoding.
10741 Return: the regno of chosen register. */
10743 static unsigned int
10745 {
10749 {
10750 /* Use R13 for nested function or function need static chain.
10751 Since function with tail call may use any caller-saved
10752 registers in epilogue, DRAP must not use caller-saved
10753 register in such case. */
10758 }
10759 else
10760 {
10761 /* Use DI for nested function or function need static chain.
10762 Since function with tail call may use any caller-saved
10763 registers in epilogue, DRAP must not use caller-saved
10764 register in such case. */
10768 /* Reuse static chain register if it isn't used for parameter
10769 passing. */
10771 {
10775 }
10777 }
10778 }
10780 /* Return minimum incoming stack alignment. */
10782 static unsigned int
10784 {
10787 /* Prefer the one specified at command line. */
10790 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10791 if -mstackrealign is used, it isn't used for sibcall check and
10792 estimated stack alignment is 128bit. */
10794 && !TARGET_64BIT
10795 && ix86_force_align_arg_pointer
10798 else
10801 /* Incoming stack alignment can be changed on individual functions
10802 via force_align_arg_pointer attribute. We use the smallest
10803 incoming stack boundary. */
10809 /* The incoming stack frame has to be aligned at least at
10810 parm_stack_boundary. */
10814 /* Stack at entrance of main is aligned by runtime. We use the
10815 smallest incoming stack boundary. */
10823 }
10825 /* Update incoming stack boundary and estimated stack alignment. */
10827 static void
10829 {
10830 ix86_incoming_stack_boundary
10833 /* x86_64 vararg needs 16byte stack alignment for register save
10834 area. */
10839 }
10841 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10842 needed or an rtx for DRAP otherwise. */
10844 static rtx
10846 {
10851 {
10852 /* Assign DRAP to vDRAP and returns vDRAP */
10854 rtx drap_vreg;
10855 rtx arg_ptr;
10868 {
10871 }
10873 }
10874 else
10876 }
10878 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10880 static rtx
10882 {
10884 }
10887 rtx reg;
10889 };
10891 /* Return a short-lived scratch register for use on function entry.
10892 In 32-bit mode, it is valid only after the registers are saved
10893 in the prologue. This register must be released by means of
10894 release_scratch_register_on_entry once it is dead. */
10896 static void
10898 {
10904 {
10905 /* We always use R11 in 64-bit mode. */
10907 }
10908 else
10909 {
10911 bool fastcall_p
10913 bool thiscall_p
10917 int drap_regno
10920 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10921 for the static chain register. */
10925 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10926 for the static chain register. */
10931 /* ecx is the static chain register. */
10933 && !static_chain_p
10938 /* esi is the static chain register. */
10944 else
10945 {
10948 }
10949 }
10953 {
10956 }
10957 }
10959 /* Release a scratch register obtained from the preceding function. */
10961 static void
10963 {
10965 {
10969 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10975 }
10976 }
10978 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10980 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10982 static void
10984 {
10985 /* We skip the probe for the first interval + a small dope of 4 words and
10986 probe that many bytes past the specified size to maintain a protection
10987 area at the botton of the stack. */
10991 /* See if we have a constant small number of probes to generate. If so,
10992 that's the easy case. The run-time loop is made up of 11 insns in the
10993 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10994 for n # of intervals. */
10996 {
11000 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
11001 values of N from 1 until it exceeds SIZE. If only one probe is
11002 needed, this will not generate any code. Then adjust and probe
11003 to PROBE_INTERVAL + SIZE. */
11005 {
11007 {
11010 }
11011 else
11018 }
11022 else
11030 /* Adjust back to account for the additional first interval. */
11034 }
11036 /* Otherwise, do the same as above, but in a loop. Note that we must be
11037 extra careful with variables wrapping around because we might be at
11038 the very top (or the very bottom) of the address space and we have
11039 to be able to handle this case properly; in particular, we use an
11040 equality test for the loop condition. */
11041 else
11042 {
11043 HOST_WIDE_INT rounded_size;
11049 /* Step 1: round SIZE to the previous multiple of the interval. */
11054 /* Step 2: compute initial and final value of the loop counter. */
11056 /* SP = SP_0 + PROBE_INTERVAL. */
11061 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
11065 stack_pointer_rtx)));
11068 /* Step 3: the loop
11070 while (SP != LAST_ADDR)
11071 {
11072 SP = SP + PROBE_INTERVAL
11073 probe at SP
11074 }
11076 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
11077 values of N from 1 until it is equal to ROUNDED_SIZE. */
11082 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
11083 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
11086 {
11091 }
11093 /* Adjust back to account for the additional first interval. */
11099 }
11103 /* Even if the stack pointer isn't the CFA register, we need to correctly
11104 describe the adjustments made to it, in particular differentiate the
11105 frame-related ones from the frame-unrelated ones. */
11107 {
11120 }
11122 /* Make sure nothing is scheduled before we are done. */
11124 }
11126 /* Adjust the stack pointer up to REG while probing it. */
11130 {
11140 /* Jump to END_LAB if SP == LAST_ADDR. */
11148 /* SP = SP + PROBE_INTERVAL. */
11152 /* Probe at SP. */
11163 }
11165 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11166 inclusive. These are offsets from the current stack pointer. */
11168 static void
11170 {
11171 /* See if we have a constant small number of probes to generate. If so,
11172 that's the easy case. The run-time loop is made up of 7 insns in the
11173 generic case while the compile-time loop is made up of n insns for n #
11174 of intervals. */
11176 {
11177 HOST_WIDE_INT i;
11179 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11180 it exceeds SIZE. If only one probe is needed, this will not
11181 generate any code. Then probe at FIRST + SIZE. */
11188 }
11190 /* Otherwise, do the same as above, but in a loop. Note that we must be
11191 extra careful with variables wrapping around because we might be at
11192 the very top (or the very bottom) of the address space and we have
11193 to be able to handle this case properly; in particular, we use an
11194 equality test for the loop condition. */
11195 else
11196 {
11203 /* Step 1: round SIZE to the previous multiple of the interval. */
11208 /* Step 2: compute initial and final value of the loop counter. */
11210 /* TEST_OFFSET = FIRST. */
11213 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11217 /* Step 3: the loop
11219 while (TEST_ADDR != LAST_ADDR)
11220 {
11221 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11222 probe at TEST_ADDR
11223 }
11225 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11226 until it is equal to ROUNDED_SIZE. */
11231 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11232 that SIZE is equal to ROUNDED_SIZE. */
11237 stack_pointer_rtx,
11242 }
11244 /* Make sure nothing is scheduled before we are done. */
11246 }
11248 /* Probe a range of stack addresses from REG to END, inclusive. These are
11249 offsets from the current stack pointer. */
11253 {
11263 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11271 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11275 /* Probe at TEST_ADDR. */
11288 }
11290 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11291 to be generated in correct form. */
11292 static void
11294 {
11295 /* Check if stack realign is really needed after reload, and
11296 stores result in cfun */
11297 unsigned int incoming_stack_boundary
11306 {
11307 /* After stack_realign_needed is finalized, we can't no longer
11308 change it. */
11311 }
11313 /* If the only reason for frame_pointer_needed is that we conservatively
11314 assumed stack realignment might be needed, but in the end nothing that
11315 needed the stack alignment had been spilled, clear frame_pointer_needed
11316 and say we don't need stack realignment. */
11318 && frame_pointer_needed
11320 && flag_omit_frame_pointer
11322 && !ix86_current_function_calls_tls_descriptor
11331 {
11333 basic_block bb;
11340 HARD_FRAME_POINTER_REGNUM);
11342 {
11347 set_up_by_prologue))
11348 {
11352 }
11353 }
11355 /* If drap has been set, but it actually isn't live at the start
11356 of the function, there is no reason to set it up. */
11358 {
11361 {
11364 }
11365 }
11366 else
11381 }
11385 }
11387 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11389 static void
11391 {
11397 {
11400 {
11406 }
11407 }
11408 }
11410 /* Expand the prologue into a bunch of separate insns. */
11412 void
11414 {
11418 HOST_WIDE_INT allocate;
11424 /* DRAP should not coexist with stack_realign_fp */
11429 /* Initialize CFA state for before the prologue. */
11433 /* Track SP offset to the CFA. We continue tracking this after we've
11434 swapped the CFA register away from SP. In the case of re-alignment
11435 this is fudged; we're interested to offsets within the local frame. */
11442 {
11443 /* We should have already generated an error for any use of
11444 ms_hook on a nested function. */
11447 /* Check if profiling is active and we shall use profiling before
11448 prologue variant. If so sorry. */
11453 /* In ix86_asm_output_function_label we emitted:
11454 8b ff movl.s %edi,%edi
11455 55 push %ebp
11456 8b ec movl.s %esp,%ebp
11458 This matches the hookable function prologue in Win32 API
11459 functions in Microsoft Windows XP Service Pack 2 and newer.
11460 Wine uses this to enable Windows apps to hook the Win32 API
11461 functions provided by Wine.
11463 What that means is that we've already set up the frame pointer. */
11467 {
11470 /* We've decided to use the frame pointer already set up.
11471 Describe this to the unwinder by pretending that both
11472 push and mov insns happen right here.
11474 Putting the unwind info here at the end of the ms_hook
11475 is done so that we can make absolutely certain we get
11476 the required byte sequence at the start of the function,
11477 rather than relying on an assembler that can produce
11478 the exact encoding required.
11480 However it does mean (in the unpatched case) that we have
11481 a 1 insn window where the asynchronous unwind info is
11482 incorrect. However, if we placed the unwind info at
11483 its correct location we would have incorrect unwind info
11484 in the patched case. Which is probably all moot since
11485 I don't expect Wine generates dwarf2 unwind info for the
11486 system libraries that use this feature. */
11492 stack_pointer_rtx);
11500 /* Note that gen_push incremented m->fs.cfa_offset, even
11501 though we didn't emit the push insn here. */
11505 }
11506 else
11507 {
11508 /* The frame pointer is not needed so pop %ebp again.
11509 This leaves us with a pristine state. */
11511 }
11512 }
11514 /* The first insn of a function that accepts its static chain on the
11515 stack is to push the register that would be filled in by a direct
11516 call. This insn will be skipped by the trampoline. */
11518 {
11522 /* We don't want to interpret this push insn as a register save,
11523 only as a stack adjustment. The real copy of the register as
11524 a save will be done later, if needed. */
11529 }
11531 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11532 of DRAP is needed and stack realignment is really needed after reload */
11534 {
11537 /* Only need to push parameter pointer reg if it is caller saved. */
11539 {
11540 /* Push arg pointer reg */
11543 }
11545 /* Grab the argument pointer. */
11552 /* Align the stack. */
11554 stack_pointer_rtx,
11558 /* Replicate the return address on the stack so that return
11559 address can be reached via (argp - 1) slot. This is needed
11560 to implement macro RETURN_ADDR_RTX and intrinsic function
11561 expand_builtin_return_addr etc. */
11567 /* For the purposes of frame and register save area addressing,
11568 we've started over with a new frame. */
11571 }
11577 {
11578 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11579 slower on all targets. Also sdb doesn't like it. */
11583 /* Push registers now, before setting the frame pointer
11584 on SEH target. */
11586 && TARGET_SEH
11588 {
11592 }
11595 {
11603 }
11604 }
11607 {
11608 /* If saving registers via PUSH, do so now. */
11610 {
11614 }
11616 /* When using red zone we may start register saving before allocating
11617 the stack frame saving one cycle of the prologue. However, avoid
11618 doing this if we have to probe the stack; at least on x86_64 the
11619 stack probe can turn into a call that clobbers a red zone location. */
11621 && (! TARGET_STACK_PROBE
11623 {
11626 }
11627 }
11630 {
11634 /* The computation of the size of the re-aligned stack frame means
11635 that we must allocate the size of the register save area before
11636 performing the actual alignment. Otherwise we cannot guarantee
11637 that there's enough storage above the realignment point. */
11644 /* Align the stack. */
11646 stack_pointer_rtx,
11649 /* For the purposes of register save area addressing, the stack
11650 pointer is no longer valid. As for the value of sp_offset,
11651 see ix86_compute_frame_layout, which we need to match in order
11652 to pass verification of stack_pointer_offset at the end. */
11655 }
11660 {
11661 /* We start to count from ARG_POINTER. */
11664 /* If it was realigned, take into account the fake frame. */
11666 {
11673 /* This over-estimates by 1 minimal-stack-alignment-unit but
11674 mitigates that by counting in the new return address slot. */
11675 current_function_dynamic_stack_size
11677 }
11680 }
11682 /* On SEH target with very large frame size, allocate an area to save
11683 SSE registers (as the very large allocation won't be described). */
11687 {
11688 HOST_WIDE_INT sse_size =
11693 /* No need to do stack checking as the area will be immediately
11694 written. */
11701 }
11703 /* The stack has already been decremented by the instruction calling us
11704 so probe if the size is non-negative to preserve the protection area. */
11706 {
11707 /* We expect the registers to be saved when probes are used. */
11711 {
11714 {
11717 }
11718 }
11719 else
11720 {
11727 {
11729 {
11732 }
11733 else
11735 }
11736 else
11737 {
11739 {
11743 }
11744 else
11746 }
11747 }
11748 }
11751 ;
11754 {
11758 }
11759 else
11760 {
11772 {
11775 /* Note that SEH directives need to continue tracking the stack
11776 pointer even after the frame pointer has been set up. */
11778 {
11786 }
11787 }
11790 {
11795 {
11803 }
11804 }
11809 /* Use the fact that AX still contains ALLOCATE. */
11811 ? gen_pro_epilogue_adjust_stack_di_sub
11818 {
11826 }
11829 /* Use stack_pointer_rtx for relative addressing so that code
11830 works for realigned stack, too. */
11832 {
11839 }
11841 {
11846 }
11847 }
11850 /* If we havn't already set up the frame pointer, do so now. */
11852 {
11864 }
11871 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11872 in PROLOGUE. */
11874 {
11880 /* Deleting already emmitted SET_GOT if exist and allocated to
11881 REAL_PIC_OFFSET_TABLE_REGNUM. */
11883 }
11886 {
11887 /* vDRAP is setup but after reload it turns out stack realign
11888 isn't necessary, here we will emit prologue to setup DRAP
11889 without stack realign adjustment */
11892 }
11894 /* Prevent instructions from being scheduled into register save push
11895 sequence when access to the redzone area is done through frame pointer.
11896 The offset between the frame pointer and the stack pointer is calculated
11897 relative to the value of the stack pointer at the end of the function
11898 prologue, and moving instructions that access redzone area via frame
11899 pointer inside push sequence violates this assumption. */
11903 /* Emit cld instruction if stringops are used in the function. */
11907 /* SEH requires that the prologue end within 256 bytes of the start of
11908 the function. Prevent instruction schedules that would extend that.
11909 Further, prevent alloca modifications to the stack pointer from being
11910 combined with prologue modifications. */
11913 }
11915 /* Emit code to restore REG using a POP insn. */
11917 static void
11919 {
11928 {
11929 /* Previously we'd represented the CFA as an expression
11930 like *(%ebp - 8). We've just popped that value from
11931 the stack, which means we need to reset the CFA to
11932 the drap register. This will remain until we restore
11933 the stack pointer. */
11937 /* This means that the DRAP register is valid for addressing too. */
11940 }
11943 {
11950 }
11952 /* When the frame pointer is the CFA, and we pop it, we are
11953 swapping back to the stack pointer as the CFA. This happens
11954 for stack frames that don't allocate other data, so we assume
11955 the stack pointer is now pointing at the return address, i.e.
11956 the function entry state, which makes the offset be 1 word. */
11958 {
11961 {
11969 }
11970 }
11971 }
11973 /* Emit code to restore saved registers using POP insns. */
11975 static void
11977 {
11983 }
11985 /* Emit code and notes for the LEAVE instruction. */
11987 static void
11989 {
12001 {
12009 }
12012 }
12014 /* Emit code to restore saved registers using MOV insns.
12015 First register is restored from CFA - CFA_OFFSET. */
12016 static void
12019 {
12025 {
12027 rtx mem;
12035 {
12036 /* Previously we'd represented the CFA as an expression
12037 like *(%ebp - 8). We've just popped that value from
12038 the stack, which means we need to reset the CFA to
12039 the drap register. This will remain until we restore
12040 the stack pointer. */
12044 /* This means that the DRAP register is valid for addressing. */
12046 }
12047 else
12051 }
12052 }
12054 /* Emit code to restore saved registers using MOV insns.
12055 First register is restored from CFA - CFA_OFFSET. */
12056 static void
12059 {
12064 {
12066 rtx mem;
12076 }
12077 }
12079 /* Restore function stack, frame, and registers. */
12081 void
12083 {
12099 /* The FP must be valid if the frame pointer is present. */
12104 /* We must have *some* valid pointer to the stack frame. */
12107 /* The DRAP is never valid at this point. */
12110 /* See the comment about red zone and frame
12111 pointer usage in ix86_expand_prologue. */
12118 /* Determine the CFA offset of the end of the red-zone. */
12121 {
12122 /* The red-zone begins below the return address. */
12125 /* When the register save area is in the aligned portion of
12126 the stack, determine the maximum runtime displacement that
12127 matches up with the aligned frame. */
12131 }
12133 /* Special care must be taken for the normal return case of a function
12134 using eh_return: the eax and edx registers are marked as saved, but
12135 not restored along this path. Adjust the save location to match. */
12139 /* EH_RETURN requires the use of moves to function properly. */
12142 /* SEH requires the use of pops to identify the epilogue. */
12145 /* If we're only restoring one register and sp is not valid then
12146 using a move instruction to restore the register since it's
12147 less work than reloading sp and popping the register. */
12160 && TARGET_USE_LEAVE
12164 else
12168 {
12169 /* Ensure that the entire register save area is addressable via
12170 the stack pointer, if we will restore via sp. */
12175 {
12179 style,
12181 }
12182 }
12184 /* If there are any SSE registers to restore, then we have to do it
12185 via moves, since there's obviously no pop for SSE regs. */
12191 {
12192 rtx t;
12197 /* eh_return epilogues need %ecx added to the stack pointer. */
12199 {
12203 /* Stack align doesn't work with eh_return. */
12205 /* Neither does regparm nested functions. */
12209 {
12217 /* Note that we use SA as a temporary CFA, as the return
12218 address is at the proper place relative to it. We
12219 pretend this happens at the FP restore insn because
12220 prior to this insn the FP would be stored at the wrong
12221 offset relative to SA, and after this insn we have no
12222 other reasonable register to use for the CFA. We don't
12223 bother resetting the CFA to the SP for the duration of
12224 the return insn. */
12237 }
12238 else
12239 {
12247 {
12251 UNITS_PER_WORD));
12253 }
12254 }
12257 }
12258 }
12259 else
12260 {
12261 /* SEH requires that the function end with (1) a stack adjustment
12262 if necessary, (2) a sequence of pops, and (3) a return or
12263 jump instruction. Prevent insns from the function body from
12264 being scheduled into this sequence. */
12266 {
12267 /* Prevent a catch region from being adjacent to the standard
12268 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12269 several other flags that would be interesting to test are
12270 not yet set up. */
12273 else
12275 }
12277 /* First step is to deallocate the stack frame so that we can
12278 pop the registers. Also do it on SEH target for very large
12279 frame as the emitted instructions aren't allowed by the ABI in
12280 epilogues. */
12282 || (TARGET_SEH
12285 {
12290 }
12292 {
12296 style,
12298 }
12301 }
12303 /* If we used a stack pointer and haven't already got rid of it,
12304 then do so now. */
12306 {
12307 /* If the stack pointer is valid and pointing at the frame
12308 pointer store address, then we only need a pop. */
12311 /* Leave results in shorter dependency chains on CPUs that are
12312 able to grok it fast. */
12317 else
12318 {
12320 hard_frame_pointer_rtx,
12323 }
12324 }
12327 {
12355 }
12357 /* At this point the stack pointer must be valid, and we must have
12358 restored all of the registers. We may not have deallocated the
12359 entire stack frame. We've delayed this until now because it may
12360 be possible to merge the local stack deallocation with the
12361 deallocation forced by ix86_static_chain_on_stack. */
12366 {
12370 }
12371 else
12374 /* Sibcall epilogues don't want a return instruction. */
12376 {
12379 }
12382 {
12385 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12386 address, do explicit add, and jump indirectly to the caller. */
12389 {
12393 /* There is no "pascal" calling convention in any 64bit ABI. */
12409 }
12410 else
12412 }
12413 else
12416 /* Restore the state back to the state from the prologue,
12417 so that it's correct for the next epilogue. */
12419 }
12421 /* Reset from the function's potential modifications. */
12423 static void
12425 {
12429 #if TARGET_MACHO
12430 /* Mach-O doesn't support labels at the end of objects, so if
12431 it looks like we might want one, insert a NOP. */
12432 {
12438 {
12439 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12440 notes only, instead set their CODE_LABEL_NUMBER to -1,
12441 otherwise there would be code generation differences
12442 in between -g and -g0. */
12446 }
12456 }
12457 #endif
12459 }
12461 /* Return a scratch register to use in the split stack prologue. The
12462 split stack prologue is used for -fsplit-stack. It is the first
12463 instructions in the function, even before the regular prologue.
12464 The scratch register can be any caller-saved register which is not
12465 used for parameters or for the static chain. */
12467 static unsigned int
12469 {
12472 else
12473 {
12486 {
12488 {
12492 }
12494 }
12496 {
12500 }
12502 {
12505 else
12506 {
12508 {
12512 }
12514 }
12515 }
12516 else
12517 {
12518 /* FIXME: We could make this work by pushing a register
12519 around the addition and comparison. */
12522 }
12523 }
12524 }
12526 /* A SYMBOL_REF for the function which allocates new stackspace for
12527 -fsplit-stack. */
12531 /* A SYMBOL_REF for the more stack function when using the large
12532 model. */
12536 /* Handle -fsplit-stack. These are the first instructions in the
12537 function, even before the regular prologue. */
12539 void
12541 {
12543 HOST_WIDE_INT allocate;
12549 rtx fn;
12557 /* This is the label we will branch to if we have enough stack
12558 space. We expect the basic block reordering pass to reverse this
12559 branch if optimizing, so that we branch in the unlikely case. */
12562 /* We need to compare the stack pointer minus the frame size with
12563 the stack boundary in the TCB. The stack boundary always gives
12564 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12565 can compare directly. Otherwise we need to do an addition. */
12568 UNSPEC_STACK_CHECK);
12573 else
12574 {
12576 rtx offset;
12578 /* We need a scratch register to hold the stack pointer minus
12579 the required frame size. Since this is the very start of the
12580 function, the scratch register can be any caller-saved
12581 register which is not used for parameters. */
12588 {
12589 /* We don't use ix86_gen_add3 in this case because it will
12590 want to split to lea, but when not optimizing the insn
12591 will not be split after this point. */
12594 offset)));
12595 }
12596 else
12597 {
12600 stack_pointer_rtx));
12601 }
12603 }
12609 /* Mark the jump as very likely to be taken. */
12614 {
12617 }
12620 /* Get more stack space. We pass in the desired stack space and the
12621 size of the arguments to copy to the new stack. In 32-bit mode
12622 we push the parameters; __morestack will return on a new stack
12623 anyhow. In 64-bit mode we pass the parameters in r10 and
12624 r11. */
12629 {
12635 /* If this function uses a static chain, it will be in %r10.
12636 Preserve it across the call to __morestack. */
12638 {
12639 rtx rax;
12644 }
12648 {
12649 HOST_WIDE_INT argval;
12652 /* When using the large model we need to load the address
12653 into a register, and we've run out of registers. So we
12654 switch to a different calling convention, and we call a
12655 different function: __morestack_large. We pass the
12656 argument size in the upper 32 bits of r10 and pass the
12657 frame size in the lower 32 bits. */
12662 {
12663 split_stack_fn_large =
12666 }
12668 {
12670 rtx x;
12679 UNSPEC_GOT);
12685 }
12686 else
12693 }
12694 else
12695 {
12699 }
12702 }
12703 else
12704 {
12707 }
12713 /* In order to make call/return prediction work right, we now need
12714 to execute a return instruction. See
12715 libgcc/config/i386/morestack.S for the details on how this works.
12717 For flow purposes gcc must not see this as a return
12718 instruction--we need control flow to continue at the subsequent
12719 label. Therefore, we use an unspec. */
12723 /* If we are in 64-bit mode and this function uses a static chain,
12724 we saved %r10 in %rax before calling _morestack. */
12729 /* If this function calls va_start, we need to store a pointer to
12730 the arguments on the old stack, because they may not have been
12731 all copied to the new stack. At this point the old stack can be
12732 found at the frame pointer value used by __morestack, because
12733 __morestack has set that up before calling back to us. Here we
12734 store that pointer in a scratch register, and in
12735 ix86_expand_prologue we store the scratch register in a stack
12736 slot. */
12738 {
12740 rtx frame_reg;
12747 /* 64-bit:
12748 fp -> old fp value
12749 return address within this function
12750 return address of caller of this function
12751 stack arguments
12752 So we add three words to get to the stack arguments.
12754 32-bit:
12755 fp -> old fp value
12756 return address within this function
12757 first argument to __morestack
12758 second argument to __morestack
12759 return address of caller of this function
12760 stack arguments
12761 So we add five words to get to the stack arguments.
12762 */
12773 }
12778 /* If this function calls va_start, we now have to set the scratch
12779 register for the case where we do not call __morestack. In this
12780 case we need to set it based on the stack pointer. */
12782 {
12789 }
12790 }
12792 /* We may have to tell the dataflow pass that the split stack prologue
12793 is initializing a scratch register. */
12795 static void
12797 {
12799 {
12802 }
12803 }
12804 \f
12805 /* Extract the parts of an RTL expression that is a valid memory address
12806 for an instruction. Return 0 if the structure of the address is
12807 grossly off. Return -1 if the address contains ASHIFT, so it is not
12808 strictly valid, but still used for computing length of lea instruction. */
12810 int
12812 {
12817 rtx tmp;
12821 /* Allow zero-extended SImode addresses,
12822 they will be emitted with addr32 prefix. */
12824 {
12827 {
12831 }
12834 {
12841 }
12842 }
12844 /* Allow SImode subregs of DImode addresses,
12845 they will be emitted with addr32 prefix. */
12847 {
12850 {
12854 }
12855 }
12860 {
12863 else
12865 }
12867 {
12872 do
12873 {
12878 }
12885 {
12888 {
12913 /* FALLTHRU */
12917 && TARGET_TLS_DIRECT_SEG_REFS
12920 else
12927 /* FALLTHRU */
12934 else
12949 }
12950 }
12951 }
12953 {
12956 }
12958 {
12959 /* We're called for lea too, which implements ashift on occasion. */
12969 }
12970 else
12974 {
12976 ;
12979 ;
12980 else
12982 }
12984 /* Extract the integral value of scale. */
12986 {
12990 }
12995 /* Avoid useless 0 displacement. */
12999 /* Allow arg pointer and stack pointer as index if there is not scaling. */
13004 {
13007 }
13009 /* Special case: %ebp cannot be encoded as a base without a displacement.
13010 Similarly %r13. */
13012 && base_reg
13021 /* Special case: on K6, [%esi] makes the instruction vector decoded.
13022 Avoid this by transforming to [%esi+0].
13023 Reload calls address legitimization without cfun defined, so we need
13024 to test cfun for being non-NULL. */
13030 /* Special case: encode reg+reg instead of reg*2. */
13034 /* Special case: scaling cannot be encoded without base or displacement. */
13045 }
13046 \f
13047 /* Return cost of the memory address x.
13048 For i386, it is better to use a complex address than let gcc copy
13049 the address into a reg and make a new pseudo. But not if the address
13050 requires to two regs - that would mean more pseudos with longer
13051 lifetimes. */
13052 static int
13054 {
13066 /* Attempt to minimize number of registers in the address by increasing
13067 address cost for each used register. We don't increase address cost
13068 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
13069 is not invariant itself it most likely means that base or index is not
13070 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
13071 which is not profitable for x86. */
13075 || !pic_offset_table_rtx
13078 cost++;
13083 || !pic_offset_table_rtx
13086 cost++;
13088 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
13089 since it's predecode logic can't detect the length of instructions
13090 and it degenerates to vector decoded. Increase cost of such
13091 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
13092 to split such addresses or even refuse such addresses at all.
13094 Following addressing modes are affected:
13095 [base+scale*index]
13096 [scale*index+disp]
13097 [base+index]
13099 The first and last case may be avoidable by explicitly coding the zero in
13100 memory address, but I don't have AMD-K6 machine handy to check this
13101 theory. */
13110 }
13111 \f
13112 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13113 this is used for to form addresses to local data when -fPIC is in
13114 use. */
13116 static bool
13118 {
13121 }
13123 /* Determine if a given RTX is a valid constant. We already know this
13124 satisfies CONSTANT_P. */
13126 static bool
13128 {
13129 /* Pointer bounds constants are not valid. */
13134 {
13139 {
13143 }
13148 /* Only some unspecs are valid as "constants". */
13151 {
13167 }
13169 /* We must have drilled down to a symbol. */
13174 /* FALLTHRU */
13177 /* TLS symbols are never valid. */
13181 /* DLLIMPORT symbols are never valid. */
13186 #if TARGET_MACHO
13187 /* mdynamic-no-pic */
13190 #endif
13204 }
13206 /* Otherwise we handle everything else in the move patterns. */
13208 }
13210 /* Determine if it's legal to put X into the constant pool. This
13211 is not possible for the address of thread-local symbols, which
13212 is checked above. */
13214 static bool
13216 {
13217 /* We can always put integral constants and vectors in memory. */
13219 {
13228 }
13230 }
13232 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13233 otherwise zero. */
13235 static bool
13237 {
13243 }
13246 /* Nonzero if the constant value X is a legitimate general operand
13247 when generating PIC code. It is given that flag_pic is on and
13248 that X satisfies CONSTANT_P. */
13250 bool
13252 {
13253 rtx inner;
13256 {
13263 /* Only some unspecs are valid as "constants". */
13266 {
13279 }
13280 /* FALLTHRU */
13288 }
13289 }
13291 /* Determine if a given CONST RTX is a valid memory displacement
13292 in PIC mode. */
13294 bool
13296 {
13299 /* In 64bit mode we can allow direct addresses of symbols and labels
13300 when they are not dynamic symbols. */
13302 {
13306 {
13330 /* FALLTHRU */
13333 /* TLS references should always be enclosed in UNSPEC.
13334 The dllimported symbol needs always to be resolved. */
13340 {
13348 /* Function-symbols need to be resolved only for
13349 large-model.
13350 For the small-model we don't need to resolve anything
13351 here. */
13356 /* Non-external symbols don't need to be resolved for
13357 large, and medium-model. */
13362 }
13365 || (HAVE_LD_PIE_COPYRELOC
13366 && flag_pie
13375 }
13376 }
13382 {
13383 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13384 of GOT tables. We should not need these anyway. */
13396 }
13400 {
13405 }
13414 {
13418 /* We need to check for both symbols and labels because VxWorks loads
13419 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13420 details. */
13424 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13425 While ABI specify also 32bit relocation but we don't produce it in
13426 small PIC model at all. */
13448 }
13451 }
13453 /* Determine if op is suitable RTX for an address register.
13454 Return naked register if a register or a register subreg is
13455 found, otherwise return NULL_RTX. */
13457 static rtx
13459 {
13462 /* Only SImode or DImode registers can form the address. */
13469 {
13477 /* Don't allow SUBREGs that span more than a word. It can
13478 lead to spill failures when the register is one word out
13479 of a two word structure. */
13483 /* Allow only SUBREGs of non-eliminable hard registers. */
13486 }
13488 /* Op is not a register. */
13490 }
13492 /* Recognizes RTL expressions that are valid memory addresses for an
13493 instruction. The MODE argument is the machine mode for the MEM
13494 expression that wants to use this address.
13496 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13497 convert common non-canonical forms to canonical form so that they will
13498 be recognized. */
13500 static bool
13502 {
13505 HOST_WIDE_INT scale;
13509 /* Decomposition failed. */
13518 /* Validate base register. */
13520 {
13528 /* Base is not valid. */
13530 }
13532 /* Validate index register. */
13534 {
13542 /* Index is not valid. */
13544 }
13546 /* Index and base should have the same mode. */
13551 /* Address override works only on the (%reg) part of %fs:(%reg). */
13557 /* Validate scale factor. */
13559 {
13561 /* Scale without index. */
13565 /* Scale is not a valid multiplier. */
13567 }
13569 /* Validate displacement. */
13571 {
13576 {
13577 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13578 used. While ABI specify also 32bit relocations, we don't produce
13579 them at all and use IP relative instead. */
13586 /* 64bit address unspec. */
13606 /* Invalid address unspec. */
13608 }
13611 && (flag_pic
13612 || (TARGET_MACHO
13613 #if TARGET_MACHO
13614 && MACHOPIC_INDIRECT
13616 #endif
13617 )))
13618 {
13620 is_legitimate_pic:
13622 {
13623 /* foo@dtpoff(%rX) is ok. */
13630 /* Non-constant pic memory reference. */
13632 }
13635 /* Displacement is an invalid pic construct. */
13637 #if TARGET_MACHO
13640 /* displacment must be referenced via non_lazy_pointer */
13642 #endif
13644 /* This code used to verify that a symbolic pic displacement
13645 includes the pic_offset_table_rtx register.
13647 While this is good idea, unfortunately these constructs may
13648 be created by "adds using lea" optimization for incorrect
13649 code like:
13651 int a;
13652 int foo(int i)
13653 {
13654 return *(&a+i);
13655 }
13657 This code is nonsensical, but results in addressing
13658 GOT table with pic_offset_table_rtx base. We can't
13659 just refuse it easily, since it gets matched by
13660 "addsi3" pattern, that later gets split to lea in the
13661 case output register differs from input. While this
13662 can be handled by separate addsi pattern for this case
13663 that never results in lea, this seems to be easier and
13664 correct fix for crash to disable this test. */
13665 }
13672 /* Displacement is not constant. */
13676 /* Displacement is out of range. */
13678 /* In x32 mode, constant addresses are sign extended to 64bit, so
13679 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13684 }
13686 /* Everything looks valid. */
13688 }
13690 /* Determine if a given RTX is a valid constant address. */
13692 bool
13694 {
13696 }
13697 \f
13698 /* Return a unique alias set for the GOT. */
13700 static alias_set_type
13702 {
13707 }
13709 /* Return a legitimate reference for ORIG (an address) using the
13710 register REG. If REG is 0, a new pseudo is generated.
13712 There are two types of references that must be handled:
13714 1. Global data references must load the address from the GOT, via
13715 the PIC reg. An insn is emitted to do this load, and the reg is
13716 returned.
13718 2. Static data references, constant pool addresses, and code labels
13719 compute the address as an offset from the GOT, whose base is in
13720 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13721 differentiate them from global data objects. The returned
13722 address is the PIC reg + an unspec constant.
13724 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13725 reg also appears in the address. */
13727 static rtx
13729 {
13733 #if TARGET_MACHO
13735 {
13738 /* Use the generic Mach-O PIC machinery. */
13740 }
13741 #endif
13744 {
13748 }
13754 {
13755 rtx tmpreg;
13756 /* This symbol may be referenced via a displacement from the PIC
13757 base address (@GOTOFF). */
13762 {
13764 UNSPEC_GOTOFF);
13766 }
13767 else
13772 else
13777 {
13781 }
13782 else
13784 }
13786 {
13787 /* This symbol may be referenced via a displacement from the PIC
13788 base address (@GOTOFF). */
13793 {
13795 UNSPEC_GOTOFF);
13797 }
13798 else
13804 {
13807 }
13808 }
13810 /* We can't use @GOTOFF for text labels on VxWorks;
13811 see gotoff_operand. */
13813 {
13818 /* For x64 PE-COFF there is no GOT table. So we use address
13819 directly. */
13821 {
13829 }
13831 {
13839 /* Use directly gen_movsi, otherwise the address is loaded
13840 into register for CSE. We don't want to CSE this addresses,
13841 instead we CSE addresses from the GOT table, so skip this. */
13844 }
13845 else
13846 {
13847 /* This symbol must be referenced via a load from the
13848 Global Offset Table (@GOT). */
13862 }
13863 }
13864 else
13865 {
13868 {
13870 {
13873 }
13874 else
13876 }
13878 {
13881 /* We must match stuff we generate before. Assume the only
13882 unspecs that can get here are ours. Not that we could do
13883 anything with them anyway.... */
13889 }
13891 {
13894 /* Check first to see if this is a constant offset from a @GOTOFF
13895 symbol reference. */
13898 {
13900 {
13902 UNSPEC_GOTOFF);
13908 {
13911 }
13912 }
13913 else
13914 {
13917 {
13921 }
13922 }
13923 }
13924 else
13925 {
13928 new_rtx
13932 {
13935 {
13938 new_rtx
13940 }
13941 else
13943 }
13944 else
13945 {
13946 /* For %rip addressing, we have to use just disp32, not
13947 base nor index. */
13954 {
13957 }
13959 }
13960 }
13961 }
13962 }
13964 }
13965 \f
13966 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13968 static rtx
13970 {
13974 {
13979 }
13985 }
13987 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13991 static rtx
13993 {
13995 {
14001 }
14004 {
14006 UNSPEC_PLTOFF);
14009 }
14012 }
14014 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
14018 rtx
14020 {
14022 {
14023 ix86_tls_module_base_symbol
14028 }
14031 }
14033 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
14034 false if we expect this to be used for a memory address and true if
14035 we expect to load the address into a register. */
14037 static rtx
14039 {
14045 /* Fall back to global dynamic model if tool chain cannot support local
14046 dynamic. */
14053 {
14058 {
14061 else
14062 {
14065 }
14066 }
14069 {
14072 else
14082 }
14083 else
14084 {
14088 {
14093 emit_call_insn
14103 }
14104 else
14106 }
14113 {
14116 else
14117 {
14120 }
14121 }
14124 {
14129 else
14135 }
14136 else
14137 {
14141 {
14144 rtx eqv;
14147 emit_call_insn
14152 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14153 share the LD_BASE result with other LD model accesses. */
14155 UNSPEC_TLS_LD_BASE);
14159 }
14160 else
14162 }
14170 {
14177 }
14182 {
14184 {
14185 /* The Sun linker took the AMD64 TLS spec literally
14186 and can only handle %rax as destination of the
14187 initial executable code sequence. */
14192 }
14194 /* Generate DImode references to avoid %fs:(%reg32)
14195 problems and linker IE->LE relaxation bug. */
14199 }
14201 {
14204 }
14206 {
14210 }
14211 else
14212 {
14215 }
14225 {
14230 }
14231 else
14232 {
14236 }
14246 {
14250 }
14251 else
14252 {
14256 }
14261 }
14264 }
14266 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14267 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14268 unique refptr-DECL symbol corresponding to symbol DECL. */
14271 {
14275 {
14277 }
14279 static int
14281 {
14283 }
14284 };
14288 static tree
14290 {
14296 tree to;
14297 rtx rtl;
14324 else
14337 {
14339 #ifdef SUB_TARGET_RECORD_STUB
14341 #endif
14342 }
14351 }
14353 /* Expand SYMBOL into its corresponding far-addresse symbol.
14354 WANT_REG is true if we require the result be a register. */
14356 static rtx
14358 {
14359 tree imp_decl;
14360 rtx x;
14369 }
14371 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14372 true if we require the result be a register. */
14374 static rtx
14376 {
14377 tree imp_decl;
14378 rtx x;
14387 }
14389 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14390 is true if we require the result be a register. */
14392 static rtx
14394 {
14399 {
14406 {
14409 }
14410 }
14426 {
14429 }
14431 }
14433 /* Try machine-dependent ways of modifying an illegitimate address
14434 to be legitimate. If we find one, return the new, valid address.
14435 This macro is used in only one place: `memory_address' in explow.c.
14437 OLDX is the address as it was before break_out_memory_refs was called.
14438 In some cases it is useful to look at this to decide what needs to be done.
14440 It is always safe for this macro to do nothing. It exists to recognize
14441 opportunities to optimize the output.
14443 For the 80386, we handle X+REG by loading X into a register R and
14444 using R+REG. R will go in a general reg and indexing will be used.
14445 However, if REG is a broken-out memory address or multiplication,
14446 nothing needs to be done because REG can certainly go in a general reg.
14448 When -fpic is used, special handling is needed for symbolic references.
14449 See comments by legitimize_pic_address in i386.c for details. */
14451 static rtx
14453 {
14464 {
14468 }
14471 {
14475 }
14480 #if TARGET_MACHO
14483 #endif
14485 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14489 {
14494 }
14497 {
14498 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14503 {
14509 }
14514 {
14520 }
14522 /* Put multiply first if it isn't already. */
14524 {
14527 }
14529 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14530 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14531 created by virtual register instantiation, register elimination, and
14532 similar optimizations. */
14534 {
14540 }
14542 /* Canonicalize
14543 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14544 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14549 {
14550 rtx constant;
14554 {
14557 }
14559 {
14562 }
14563 else
14567 {
14574 }
14575 }
14581 {
14584 }
14587 {
14590 }
14598 {
14601 }
14607 {
14611 {
14614 }
14618 }
14621 {
14625 {
14628 }
14632 }
14633 }
14636 }
14637 \f
14638 /* Print an integer constant expression in assembler syntax. Addition
14639 and subtraction are the only arithmetic that may appear in these
14640 expressions. FILE is the stdio stream to write to, X is the rtx, and
14641 CODE is the operand print code from the output string. */
14643 static void
14645 {
14649 {
14658 else
14659 {
14662 /* Mark the decl as referenced so that cgraph will
14663 output the function. */
14667 #if TARGET_MACHO
14671 #endif
14673 }
14681 /* FALLTHRU */
14692 /* This used to output parentheses around the expression,
14693 but that does not work on the 386 (either ATT or BSD assembler). */
14698 /* We can't handle floating point constants;
14699 TARGET_PRINT_OPERAND must handle them. */
14704 /* Some assemblers need integer constants to appear first. */
14706 {
14710 }
14711 else
14712 {
14717 }
14732 {
14736 }
14741 {
14760 /* FIXME: This might be @TPOFF in Sun ld too. */
14769 else
14779 else
14785 #if TARGET_MACHO
14790 #endif
14794 }
14799 }
14800 }
14802 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14803 We need to emit DTP-relative relocations. */
14805 static void ATTRIBUTE_UNUSED
14807 {
14812 {
14820 }
14821 }
14823 /* Return true if X is a representation of the PIC register. This copes
14824 with calls from ix86_find_base_term, where the register might have
14825 been replaced by a cselib value. */
14827 static bool
14829 {
14836 {
14844 }
14845 else
14847 }
14849 /* Helper function for ix86_delegitimize_address.
14850 Attempt to delegitimize TLS local-exec accesses. */
14852 static rtx
14854 {
14879 {
14884 }
14890 }
14892 /* In the name of slightly smaller debug output, and to cater to
14893 general assembler lossage, recognize PIC+GOTOFF and turn it back
14894 into a direct symbol reference.
14896 On Darwin, this is necessary to avoid a crash, because Darwin
14897 has a different PIC label for each routine but the DWARF debugging
14898 information is not associated with any particular routine, so it's
14899 necessary to remove references to the PIC label from RTL stored by
14900 the DWARF output code. */
14902 static rtx
14904 {
14906 /* addend is NULL or some rtx if x is something+GOTOFF where
14907 something doesn't include the PIC register. */
14909 /* reg_addend is NULL or a multiple of some register. */
14911 /* const_addend is NULL or a const_int. */
14913 /* This is the result, or NULL. */
14922 {
14929 {
14935 }
14942 {
14945 {
14950 }
14952 }
14957 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14958 and -mcmodel=medium -fpic. */
14959 }
14966 /* %ebx + GOT/GOTOFF */
14967 ;
14969 {
14970 /* %ebx + %reg * scale + GOT/GOTOFF */
14976 else
14977 {
14980 }
14981 }
14982 else
14988 {
14991 }
15012 {
15013 /* If the rest of original X doesn't involve the PIC register, add
15014 addend and subtract pic_offset_table_rtx. This can happen e.g.
15015 for code like:
15016 leal (%ebx, %ecx, 4), %ecx
15017 ...
15018 movl foo@GOTOFF(%ecx), %edx
15019 in which case we return (%ecx - %ebx) + foo
15020 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
15021 and reload has completed. */
15025 pic_offset_table_rtx),
15026 result);
15028 {
15032 }
15033 else
15035 }
15037 {
15041 }
15043 }
15045 /* If X is a machine specific address (i.e. a symbol or label being
15046 referenced as a displacement from the GOT implemented using an
15047 UNSPEC), then return the base term. Otherwise return X. */
15049 rtx
15051 {
15052 rtx term;
15055 {
15068 }
15071 }
15072 \f
15073 static void
15076 {
15080 {
15083 }
15088 {
15091 {
15110 }
15114 {
15133 }
15140 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15141 Those same assemblers have the same but opposite lossage on cmov. */
15144 else
15149 {
15162 }
15169 else
15174 {
15187 }
15194 else
15204 else
15215 }
15217 }
15219 /* Print the name of register X to FILE based on its machine mode and number.
15220 If CODE is 'w', pretend the mode is HImode.
15221 If CODE is 'b', pretend the mode is QImode.
15222 If CODE is 'k', pretend the mode is SImode.
15223 If CODE is 'q', pretend the mode is DImode.
15224 If CODE is 'x', pretend the mode is V4SFmode.
15225 If CODE is 't', pretend the mode is V8SFmode.
15226 If CODE is 'g', pretend the mode is V16SFmode.
15227 If CODE is 'h', pretend the reg is the 'high' byte register.
15228 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15229 If CODE is 'd', duplicate the operand for AVX instruction.
15230 */
15232 void
15234 {
15244 {
15248 }
15251 {
15254 }
15272 else
15286 {
15294 normal:
15310 {
15315 }
15319 }
15323 /* Irritatingly, AMD extended registers use
15324 different naming convention: "r%d[bwd]" */
15326 {
15329 {
15343 /* no suffix */
15348 }
15350 }
15353 {
15356 else
15358 }
15359 }
15361 /* Meaning of CODE:
15362 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15363 C -- print opcode suffix for set/cmov insn.
15364 c -- like C, but print reversed condition
15365 F,f -- likewise, but for floating-point.
15366 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15367 otherwise nothing
15368 R -- print embeded rounding and sae.
15369 r -- print only sae.
15370 z -- print the opcode suffix for the size of the current operand.
15371 Z -- likewise, with special suffixes for x87 instructions.
15372 * -- print a star (in certain assembler syntax)
15373 A -- print an absolute memory reference.
15374 E -- print address with DImode register names if TARGET_64BIT.
15375 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15376 s -- print a shift double count, followed by the assemblers argument
15377 delimiter.
15378 b -- print the QImode name of the register for the indicated operand.
15379 %b0 would print %al if operands[0] is reg 0.
15380 w -- likewise, print the HImode name of the register.
15381 k -- likewise, print the SImode name of the register.
15382 q -- likewise, print the DImode name of the register.
15383 x -- likewise, print the V4SFmode name of the register.
15384 t -- likewise, print the V8SFmode name of the register.
15385 g -- likewise, print the V16SFmode name of the register.
15386 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15387 y -- print "st(0)" instead of "st" as a register.
15388 d -- print duplicated register operand for AVX instruction.
15389 D -- print condition for SSE cmp instruction.
15390 P -- if PIC, print an @PLT suffix.
15391 p -- print raw symbol name.
15392 X -- don't print any sort of PIC '@' suffix for a symbol.
15393 & -- print some in-use local-dynamic symbol name.
15394 H -- print a memory address offset by 8; used for sse high-parts
15395 Y -- print condition for XOP pcom* instruction.
15396 + -- print a branch hint as 'cs' or 'ds' prefix
15397 ; -- print a semicolon (after prefixes due to bug in older gas).
15398 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15399 @ -- print a segment register of thread base pointer load
15400 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15401 ! -- print MPX prefix for jxx/call/ret instructions if required.
15402 */
15404 void
15406 {
15408 {
15410 {
15413 {
15419 /* Intel syntax. For absolute addresses, registers should not
15420 be surrounded by braces. */
15422 {
15427 }
15432 }
15438 /* Wrap address in an UNSPEC to declare special handling. */
15476 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15481 {
15495 output_operand_lossage
15498 }
15501 #endif
15506 {
15507 /* Opcodes don't get size suffixes if using Intel opcodes. */
15512 {
15530 output_operand_lossage
15533 }
15534 }
15537 warning
15539 /* FALLTHRU */
15542 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15547 {
15549 {
15551 #ifdef HAVE_AS_IX86_FILDS
15553 #endif
15561 #ifdef HAVE_AS_IX86_FILDQ
15563 #else
15565 #endif
15570 }
15571 }
15573 {
15574 /* 387 opcodes don't get size suffixes
15575 if the operands are registers. */
15580 {
15596 }
15597 }
15598 else
15599 {
15600 output_operand_lossage
15603 }
15605 output_operand_lossage
15626 {
15629 }
15634 {
15685 }
15689 /* Little bit of braindamage here. The SSE compare instructions
15690 does use completely different names for the comparisons that the
15691 fp conditional moves. */
15693 {
15696 {
15699 }
15705 {
15708 }
15714 {
15717 }
15726 {
15729 }
15735 {
15738 }
15744 {
15747 }
15758 }
15763 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15766 #endif
15771 {
15775 }
15779 file);
15784 {
15788 }
15789 /* It doesn't actually matter what mode we use here, as we're
15790 only going to use this for printing. */
15792 /* Output 'qword ptr' for intel assembler dialect. */
15801 #ifdef HAVE_AS_IX86_HLE
15803 #else
15805 #endif
15807 #ifdef HAVE_AS_IX86_HLE
15809 #else
15811 #endif
15812 /* We do not want to print value of the operand. */
15841 {
15856 }
15869 {
15874 else
15877 }
15880 {
15881 rtx x;
15890 {
15895 {
15897 bool cputaken
15900 /* Emit hints only in the case default branch prediction
15901 heuristics would fail. */
15903 {
15904 /* We use 3e (DS) prefix for taken branches and
15905 2e (CS) prefix for not taken branches. */
15908 else
15910 }
15911 }
15912 }
15914 }
15917 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15919 #endif
15926 /* The kernel uses a different segment register for performance
15927 reasons; a system call would not have to trash the userspace
15928 segment register, which would be expensive. */
15931 else
15951 }
15952 }
15958 {
15959 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15962 {
15965 {
15974 else
15981 }
15983 /* Check for explicit size override (codes 'b', 'w', 'k',
15984 'q' and 'x') */
15998 }
16001 /* Avoid (%rip) for call operands. */
16007 else
16009 }
16012 {
16013 REAL_VALUE_TYPE r;
16021 /* Sign extend 32bit SFmode immediate to 8 bytes. */
16025 else
16027 }
16030 {
16031 REAL_VALUE_TYPE r;
16040 }
16042 /* These float cases don't actually occur as immediate operands. */
16044 {
16049 }
16051 else
16052 {
16053 /* We have patterns that allow zero sets of memory, for instance.
16054 In 64-bit mode, we should probably support all 8-byte vectors,
16055 since we can in fact encode that into an immediate. */
16057 {
16060 }
16063 {
16065 {
16068 }
16071 {
16074 else
16076 }
16077 }
16082 else
16084 }
16085 }
16087 static bool
16089 {
16092 }
16093 \f
16094 /* Print a memory operand whose address is ADDR. */
16096 static void
16098 {
16107 {
16114 }
16116 {
16120 }
16122 {
16126 {
16129 }
16132 }
16134 {
16139 }
16140 else
16151 {
16162 }
16164 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16166 {
16178 }
16180 {
16181 /* Displacement only requires special attention. */
16184 {
16188 }
16191 else
16193 }
16194 else
16195 {
16196 /* Print SImode register names to force addr32 prefix. */
16198 {
16199 #ifdef ENABLE_CHECKING
16202 {
16213 }
16214 #endif
16217 }
16219 && TARGET_X32
16220 && disp
16223 {
16224 /* X32 runs in 64-bit mode, where displacement, DISP, in
16225 address DISP(%r64), is encoded as 32-bit immediate sign-
16226 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16227 address is %r64 + 0xffffffffbffffd00. When %r64 <
16228 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16229 which is invalid for x32. The correct address is %r64
16230 - 0x40000300 == 0xf7ffdd64. To properly encode
16231 -0x40000300(%r64) for x32, we zero-extend negative
16232 displacement by forcing addr32 prefix which truncates
16233 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16234 zero-extend all negative displacements, including -1(%rsp).
16235 However, for small negative displacements, sign-extension
16236 won't cause overflow. We only zero-extend negative
16237 displacements if they < -16*1024*1024, which is also used
16238 to check legitimate address displacements for PIC. */
16240 }
16243 {
16245 {
16250 else
16252 }
16258 {
16263 }
16265 }
16266 else
16267 {
16271 {
16272 /* Pull out the offset of a symbol; print any symbol itself. */
16276 {
16280 }
16288 else
16290 }
16294 {
16297 {
16301 }
16302 }
16305 else
16309 {
16314 }
16316 }
16317 }
16318 }
16320 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16322 static bool
16324 {
16325 rtx op;
16332 {
16335 /* FIXME: This might be @TPOFF in Sun ld. */
16346 else
16358 else
16365 #if TARGET_MACHO
16371 #endif
16374 {
16379 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16381 #else
16383 #endif
16386 }
16391 }
16394 }
16395 \f
16396 /* Split one or more double-mode RTL references into pairs of half-mode
16397 references. The RTL can be REG, offsettable MEM, integer constant, or
16398 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16399 split and "num" is its length. lo_half and hi_half are output arrays
16400 that parallel "operands". */
16402 void
16405 {
16406 machine_mode half_mode;
16410 {
16419 }
16424 {
16427 /* simplify_subreg refuse to split volatile memory addresses,
16428 but we still have to handle it. */
16430 {
16433 }
16434 else
16435 {
16442 }
16443 }
16444 }
16445 \f
16446 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16447 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16448 is the expression of the binary operation. The output may either be
16449 emitted here, or returned to the caller, like all output_* functions.
16451 There is no guarantee that the operands are the same mode, as they
16452 might be within FLOAT or FLOAT_EXTEND expressions. */
16454 #ifndef SYSV386_COMPAT
16455 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16456 wants to fix the assemblers because that causes incompatibility
16457 with gcc. No-one wants to fix gcc because that causes
16458 incompatibility with assemblers... You can use the option of
16459 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16460 #define SYSV386_COMPAT 1
16461 #endif
16465 {
16471 #ifdef ENABLE_CHECKING
16472 /* Even if we do not want to check the inputs, this documents input
16473 constraints. Which helps in understanding the following code. */
16483 else
16485 #endif
16488 {
16493 else
16502 else
16511 else
16520 else
16527 }
16530 {
16532 {
16536 else
16538 }
16539 else
16540 {
16544 else
16546 }
16548 }
16552 {
16558 /* know operands[0] == operands[1]. */
16561 {
16564 }
16567 {
16569 /* How is it that we are storing to a dead operand[2]?
16570 Well, presumably operands[1] is dead too. We can't
16571 store the result to st(0) as st(0) gets popped on this
16572 instruction. Instead store to operands[2] (which I
16573 think has to be st(1)). st(1) will be popped later.
16574 gcc <= 2.8.1 didn't have this check and generated
16575 assembly code that the Unixware assembler rejected. */
16577 else
16580 }
16584 else
16591 {
16594 }
16597 {
16600 }
16603 {
16604 #if SYSV386_COMPAT
16605 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16606 derived assemblers, confusingly reverse the direction of
16607 the operation for fsub{r} and fdiv{r} when the
16608 destination register is not st(0). The Intel assembler
16609 doesn't have this brain damage. Read !SYSV386_COMPAT to
16610 figure out what the hardware really does. */
16613 else
16615 #else
16617 /* As above for fmul/fadd, we can't store to st(0). */
16619 else
16621 #endif
16623 }
16626 {
16627 #if SYSV386_COMPAT
16630 else
16632 #else
16635 else
16637 #endif
16639 }
16642 {
16645 else
16648 }
16650 {
16651 #if SYSV386_COMPAT
16653 #else
16655 #endif
16656 }
16657 else
16658 {
16659 #if SYSV386_COMPAT
16661 #else
16663 #endif
16664 }
16669 }
16673 }
16675 /* Check if a 256bit AVX register is referenced inside of EXP. */
16677 static bool
16679 {
16685 }
16687 /* Return needed mode for entity in optimize_mode_switching pass. */
16689 static int
16691 {
16693 {
16694 rtx link;
16696 /* Needed mode is set to AVX_U128_CLEAN if there are
16697 no 256bit modes used in function arguments. */
16699 link;
16701 {
16703 {
16708 }
16709 }
16712 }
16714 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16715 changes state only when a 256bit register is written to, but we need
16716 to prevent the compiler from moving optimal insertion point above
16717 eventual read from 256bit register. */
16724 }
16726 /* Return mode that i387 must be switched into
16727 prior to the execution of insn. */
16729 static int
16731 {
16734 /* The mode UNINITIALIZED is used to store control word after a
16735 function call or ASM pattern. The mode ANY specify that function
16736 has no requirements on the control word and make no changes in the
16737 bits we are interested in. */
16751 {
16774 }
16777 }
16779 /* Return mode that entity must be switched into
16780 prior to the execution of insn. */
16782 static int
16784 {
16786 {
16796 }
16798 }
16800 /* Check if a 256bit AVX register is referenced in stores. */
16802 static void
16804 {
16806 {
16809 }
16810 }
16812 /* Calculate mode of upper 128bit AVX registers after the insn. */
16814 static int
16816 {
16823 /* We know that state is clean after CALL insn if there are no
16824 256bit registers used in the function return register. */
16826 {
16831 }
16833 /* Otherwise, return current mode. Remember that if insn
16834 references AVX 256bit registers, the mode was already changed
16835 to DIRTY from MODE_NEEDED. */
16837 }
16839 /* Return the mode that an insn results in. */
16841 static int
16843 {
16845 {
16855 }
16856 }
16858 static int
16860 {
16861 tree arg;
16863 /* Entry mode is set to AVX_U128_DIRTY if there are
16864 256bit modes used in function arguments. */
16867 {
16872 }
16875 }
16877 /* Return a mode that ENTITY is assumed to be
16878 switched to at function entry. */
16880 static int
16882 {
16884 {
16894 }
16895 }
16897 static int
16899 {
16902 /* Exit mode is set to AVX_U128_DIRTY if there are
16903 256bit modes used in the function return register. */
16908 }
16910 /* Return a mode that ENTITY is assumed to be
16911 switched to at function exit. */
16913 static int
16915 {
16917 {
16927 }
16928 }
16930 static int
16932 {
16934 }
16936 /* Output code to initialize control word copies used by trunc?f?i and
16937 rounding patterns. CURRENT_MODE is set to current control word,
16938 while NEW_MODE is set to new control word. */
16940 static void
16942 {
16944 rtx new_mode;
16955 {
16957 {
16959 /* round toward zero (truncate) */
16965 /* round down toward -oo */
16972 /* round up toward +oo */
16979 /* mask precision exception for nearbyint() */
16986 }
16987 }
16988 else
16989 {
16991 {
16993 /* round toward zero (truncate) */
16999 /* round down toward -oo */
17005 /* round up toward +oo */
17011 /* mask precision exception for nearbyint() */
17018 }
17019 }
17025 }
17027 /* Emit vzeroupper. */
17029 void
17031 {
17034 /* Cancel automatic vzeroupper insertion if there are
17035 live call-saved SSE registers at the insertion point. */
17047 }
17049 /* Generate one or more insns to set ENTITY to MODE. */
17051 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
17052 is the set of hard registers live at the point where the insn(s)
17053 are to be inserted. */
17055 static void
17057 HARD_REG_SET regs_live)
17058 {
17060 {
17075 }
17076 }
17078 /* Output code for INSN to convert a float to a signed int. OPERANDS
17079 are the insn operands. The output may be [HSD]Imode and the input
17080 operand may be [SDX]Fmode. */
17084 {
17089 /* Jump through a hoop or two for DImode, since the hardware has no
17090 non-popping instruction. We used to do this a different way, but
17091 that was somewhat fragile and broke with post-reload splitters. */
17101 else
17102 {
17107 else
17111 }
17114 }
17116 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17117 have the values zero or one, indicates the ffreep insn's operand
17118 from the OPERANDS array. */
17122 {
17124 #ifdef HAVE_AS_IX86_FFREEP
17126 #else
17127 {
17137 }
17138 #endif
17141 }
17144 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17145 should be used. UNORDERED_P is true when fucom should be used. */
17149 {
17155 {
17158 }
17159 else
17160 {
17163 }
17166 {
17170 else
17172 else
17175 else
17177 }
17184 {
17186 {
17189 }
17190 else
17192 }
17195 && stack_top_dies
17198 {
17199 /* If both the top of the 387 stack dies, and the other operand
17200 is also a stack register that dies, then this must be a
17201 `fcompp' float compare */
17204 {
17205 /* There is no double popping fcomi variant. Fortunately,
17206 eflags is immune from the fstp's cc clobbering. */
17209 else
17212 }
17213 else
17214 {
17217 else
17219 }
17220 }
17221 else
17222 {
17223 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17226 {
17234 NULL,
17235 NULL,
17242 NULL,
17243 NULL,
17244 NULL,
17245 NULL
17246 };
17261 }
17262 }
17264 void
17266 {
17269 #ifdef ASM_QUAD
17272 #else
17274 #endif
17277 }
17279 void
17281 {
17284 #ifdef ASM_QUAD
17287 #else
17289 #endif
17290 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17296 #if TARGET_MACHO
17298 {
17302 }
17303 #endif
17304 else
17307 }
17308 \f
17309 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17310 for the target. */
17312 void
17314 {
17315 rtx tmp;
17317 /* We play register width games, which are only valid after reload. */
17320 /* Avoid HImode and its attendant prefix byte. */
17326 {
17329 }
17332 }
17334 /* X is an unchanging MEM. If it is a constant pool reference, return
17335 the constant pool rtx, else NULL. */
17337 rtx
17339 {
17346 }
17348 void
17350 {
17358 {
17359 rtx tmp;
17363 {
17369 }
17372 }
17376 {
17379 rtx tmp;
17384 else
17388 {
17395 }
17396 }
17400 {
17402 {
17403 #if TARGET_MACHO
17404 /* dynamic-no-pic */
17406 {
17413 }
17415 {
17419 }
17422 else
17423 {
17431 }
17432 /* dynamic-no-pic */
17433 #endif
17434 }
17435 else
17436 {
17440 {
17446 }
17447 }
17448 }
17449 else
17450 {
17461 /* Force large constants in 64bit compilation into register
17462 to get them CSEed. */
17473 {
17474 /* If we are loading a floating point constant to a register,
17475 force the value to memory now, since we'll get better code
17476 out the back end. */
17480 {
17485 }
17486 }
17487 }
17490 }
17492 void
17494 {
17501 /* Force constants other than zero into memory. We do not know how
17502 the instructions used to build constants modify the upper 64 bits
17503 of the register, once we have that information we may be able
17504 to handle some of them more efficiently. */
17513 /* We need to check memory alignment for SSE mode since attribute
17514 can make operands unaligned. */
17519 {
17522 /* ix86_expand_vector_move_misalign() does not like constants ... */
17528 /* ... nor both arguments in memory. */
17536 }
17538 /* Make operand1 a register if it isn't already. */
17542 {
17545 }
17548 }
17550 /* Split 32-byte AVX unaligned load and store if needed. */
17552 static void
17554 {
17555 rtx m;
17559 machine_mode mode;
17562 {
17583 }
17586 {
17589 {
17596 }
17597 /* Normal *mov<mode>_internal pattern will handle
17598 unaligned loads just fine if misaligned_operand
17599 is true, and without the UNSPEC it can be combined
17600 with arithmetic instructions. */
17603 else
17605 }
17607 {
17610 {
17615 }
17616 else
17618 }
17619 else
17621 }
17623 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17624 straight to ix86_expand_vector_move. */
17625 /* Code generation for scalar reg-reg moves of single and double precision data:
17626 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17627 movaps reg, reg
17628 else
17629 movss reg, reg
17630 if (x86_sse_partial_reg_dependency == true)
17631 movapd reg, reg
17632 else
17633 movsd reg, reg
17635 Code generation for scalar loads of double precision data:
17636 if (x86_sse_split_regs == true)
17637 movlpd mem, reg (gas syntax)
17638 else
17639 movsd mem, reg
17641 Code generation for unaligned packed loads of single precision data
17642 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17643 if (x86_sse_unaligned_move_optimal)
17644 movups mem, reg
17646 if (x86_sse_partial_reg_dependency == true)
17647 {
17648 xorps reg, reg
17649 movlps mem, reg
17650 movhps mem+8, reg
17651 }
17652 else
17653 {
17654 movlps mem, reg
17655 movhps mem+8, reg
17656 }
17658 Code generation for unaligned packed loads of double precision data
17659 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17660 if (x86_sse_unaligned_move_optimal)
17661 movupd mem, reg
17663 if (x86_sse_split_regs == true)
17664 {
17665 movlpd mem, reg
17666 movhpd mem+8, reg
17667 }
17668 else
17669 {
17670 movsd mem, reg
17671 movhpd mem+8, reg
17672 }
17673 */
17675 void
17677 {
17686 {
17688 {
17692 {
17694 {
17697 }
17698 else
17700 }
17702 /* FALLTHRU */
17706 {
17721 }
17727 else
17735 }
17738 }
17742 {
17744 {
17748 {
17750 {
17753 }
17754 else
17756 }
17758 /* FALLTHRU */
17768 }
17771 }
17774 {
17775 /* Normal *mov<mode>_internal pattern will handle
17776 unaligned loads just fine if misaligned_operand
17777 is true, and without the UNSPEC it can be combined
17778 with arithmetic instructions. */
17784 /* ??? If we have typed data, then it would appear that using
17785 movdqu is the only way to get unaligned data loaded with
17786 integer type. */
17788 {
17790 {
17793 }
17795 /* We will eventually emit movups based on insn attributes. */
17799 }
17801 {
17802 rtx zero;
17805 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17806 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17808 {
17809 /* We will eventually emit movups based on insn attributes. */
17812 }
17814 /* When SSE registers are split into halves, we can avoid
17815 writing to the top half twice. */
17817 {
17820 }
17821 else
17822 {
17823 /* ??? Not sure about the best option for the Intel chips.
17824 The following would seem to satisfy; the register is
17825 entirely cleared, breaking the dependency chain. We
17826 then store to the upper half, with a dependency depth
17827 of one. A rumor has it that Intel recommends two movsd
17828 followed by an unpacklpd, but this is unconfirmed. And
17829 given that the dependency depth of the unpacklpd would
17830 still be one, I'm not sure why this would be better. */
17832 }
17838 }
17839 else
17840 {
17841 rtx t;
17844 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17845 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17847 {
17849 {
17852 }
17859 }
17863 else
17868 else
17877 }
17878 }
17880 {
17882 {
17885 /* We will eventually emit movups based on insn attributes. */
17887 }
17889 {
17891 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17892 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17894 /* We will eventually emit movups based on insn attributes. */
17896 else
17897 {
17902 }
17903 }
17904 else
17905 {
17910 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17911 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17913 {
17916 }
17917 else
17918 {
17923 }
17924 }
17925 }
17926 else
17928 }
17930 /* Helper function of ix86_fixup_binary_operands to canonicalize
17931 operand order. Returns true if the operands should be swapped. */
17933 static bool
17935 rtx operands[])
17936 {
17941 /* If the operation is not commutative, we can't do anything. */
17945 /* Highest priority is that src1 should match dst. */
17951 /* Next highest priority is that immediate constants come second. */
17957 /* Lowest priority is that memory references should come second. */
17964 }
17967 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17968 destination to use for the operation. If different from the true
17969 destination in operands[0], a copy operation will be required. */
17971 rtx
17973 rtx operands[])
17974 {
17979 /* Canonicalize operand order. */
17981 {
17982 /* It is invalid to swap operands of different modes. */
17986 }
17988 /* Both source operands cannot be in memory. */
17990 {
17991 /* Optimization: Only read from memory once. */
17993 {
17996 }
17999 else
18001 }
18003 /* If the destination is memory, and we do not have matching source
18004 operands, do things in registers. */
18008 /* Source 1 cannot be a constant. */
18012 /* Source 1 cannot be a non-matching memory. */
18016 /* Improve address combine. */
18025 }
18027 /* Similarly, but assume that the destination has already been
18028 set up properly. */
18030 void
18033 {
18036 }
18038 /* Attempt to expand a binary operator. Make the expansion closer to the
18039 actual machine, then just general_operand, which will allow 3 separate
18040 memory references (one output, two input) in a single insn. */
18042 void
18044 rtx operands[])
18045 {
18052 /* Emit the instruction. */
18059 {
18060 /* This is going to be an LEA; avoid splitting it later. */
18062 }
18063 else
18064 {
18067 }
18069 /* Fix up the destination if needed. */
18072 }
18074 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
18075 the given OPERANDS. */
18077 void
18079 rtx operands[])
18080 {
18083 {
18086 }
18088 {
18091 }
18092 /* Optimize (__m128i) d | (__m128i) e and similar code
18093 when d and e are float vectors into float vector logical
18094 insn. In C/C++ without using intrinsics there is no other way
18095 to express vector logical operation on float vectors than
18096 to cast them temporarily to integer vectors. */
18098 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18107 {
18108 rtx dst;
18110 {
18119 {
18122 }
18123 else
18124 {
18129 }
18140 }
18141 }
18150 }
18152 /* Return TRUE or FALSE depending on whether the binary operator meets the
18153 appropriate constraints. */
18155 bool
18158 {
18163 /* Both source operands cannot be in memory. */
18167 /* Canonicalize operand order for commutative operators. */
18171 /* If the destination is memory, we must have a matching source operand. */
18175 /* Source 1 cannot be a constant. */
18179 /* Source 1 cannot be a non-matching memory. */
18181 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18189 }
18191 /* Attempt to expand a unary operator. Make the expansion closer to the
18192 actual machine, then just general_operand, which will allow 2 separate
18193 memory references (one output, one input) in a single insn. */
18195 void
18197 rtx operands[])
18198 {
18205 /* If the destination is memory, and we do not have matching source
18206 operands, do things in registers. */
18208 {
18211 else
18213 }
18215 /* When source operand is memory, destination must match. */
18219 /* Emit the instruction. */
18225 else
18226 {
18229 }
18231 /* Fix up the destination if needed. */
18234 }
18236 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18237 divisor are within the range [0-255]. */
18239 void
18242 {
18251 {
18264 }
18271 /* Use 8bit unsigned divimod if dividend and divisor are within
18272 the range [0-255]. */
18281 pc_rtx);
18286 /* Generate original signed/unsigned divimod. */
18291 /* Branch to the end. */
18295 /* Generate 8bit unsigned divide. */
18297 /* Don't use operands[0] for result of 8bit divide since not all
18298 registers support QImode ZERO_EXTRACT. */
18305 {
18308 }
18309 else
18310 {
18313 }
18315 /* Extract remainder from AH. */
18319 else
18320 {
18321 /* Need a new scratch register since the old one has result
18322 of 8bit divide. */
18326 }
18329 /* Zero extend quotient from AL. */
18335 }
18337 #define LEA_MAX_STALL (3)
18338 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18340 /* Increase given DISTANCE in half-cycles according to
18341 dependencies between PREV and NEXT instructions.
18342 Add 1 half-cycle if there is no dependency and
18343 go to next cycle if there is some dependecy. */
18345 static unsigned int
18347 {
18363 }
18365 /* Function checks if instruction INSN defines register number
18366 REGNO1 or REGNO2. */
18368 static bool
18371 {
18372 df_ref def;
18382 }
18384 /* Function checks if instruction INSN uses register number
18385 REGNO as a part of address expression. */
18387 static bool
18389 {
18390 df_ref use;
18397 }
18399 /* Search backward for non-agu definition of register number REGNO1
18400 or register number REGNO2 in basic block starting from instruction
18401 START up to head of basic block or instruction INSN.
18403 Function puts true value into *FOUND var if definition was found
18404 and false otherwise.
18406 Distance in half-cycles between START and found instruction or head
18407 of BB is added to DISTANCE and returned. */
18409 static int
18413 {
18423 {
18425 {
18428 {
18431 {
18434 }
18435 }
18438 }
18443 }
18446 }
18448 /* Search backward for non-agu definition of register number REGNO1
18449 or register number REGNO2 in INSN's basic block until
18450 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18451 2. Reach neighbour BBs boundary, or
18452 3. Reach agu definition.
18453 Returns the distance between the non-agu definition point and INSN.
18454 If no definition point, returns -1. */
18456 static int
18459 {
18470 {
18471 edge e;
18472 edge_iterator ei;
18477 {
18480 }
18486 else
18487 {
18492 {
18493 int bb_dist
18499 {
18506 }
18507 }
18510 }
18511 }
18513 /* get_attr_type may modify recog data. We want to make sure
18514 that recog data is valid for instruction INSN, on which
18515 distance_non_agu_define is called. INSN is unchanged here. */
18522 }
18524 /* Return the distance in half-cycles between INSN and the next
18525 insn that uses register number REGNO in memory address added
18526 to DISTANCE. Return -1 if REGNO0 is set.
18528 Put true value into *FOUND if register usage was found and
18529 false otherwise.
18530 Put true value into *REDEFINED if register redefinition was
18531 found and false otherwise. */
18533 static int
18537 {
18546 {
18549 /* If insn and start belong to the same bb, set prev to insn,
18550 so the call to increase_distance will increase the distance
18551 between insns by 1. */
18553 }
18558 {
18560 {
18563 {
18564 /* Return DISTANCE if OP0 is used in memory
18565 address in NEXT. */
18568 }
18571 {
18572 /* Return -1 if OP0 is set in NEXT. */
18575 }
18578 }
18584 }
18587 }
18589 /* Return the distance between INSN and the next insn that uses
18590 register number REGNO0 in memory address. Return -1 if no such
18591 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18593 static int
18595 {
18607 {
18608 edge e;
18609 edge_iterator ei;
18614 {
18617 }
18623 else
18624 {
18630 {
18631 int bb_dist
18636 {
18643 }
18644 }
18647 }
18648 }
18654 }
18656 /* Define this macro to tune LEA priority vs ADD, it take effect when
18657 there is a dilemma of choicing LEA or ADD
18658 Negative value: ADD is more preferred than LEA
18659 Zero: Netrual
18660 Positive value: LEA is more preferred than ADD*/
18661 #define IX86_LEA_PRIORITY 0
18663 /* Return true if usage of lea INSN has performance advantage
18664 over a sequence of instructions. Instructions sequence has
18665 SPLIT_COST cycles higher latency than lea latency. */
18667 static bool
18670 {
18673 /* For Silvermont if using a 2-source or 3-source LEA for
18674 non-destructive destination purposes, or due to wanting
18675 ability to use SCALE, the use of LEA is justified. */
18677 {
18685 }
18691 {
18692 /* If there is no non AGU operand definition, no AGU
18693 operand usage and split cost is 0 then both lea
18694 and non lea variants have same priority. Currently
18695 we prefer lea for 64 bit code and non lea on 32 bit
18696 code. */
18699 else
18701 }
18703 /* With longer definitions distance lea is more preferable.
18704 Here we change it to take into account splitting cost and
18705 lea priority. */
18708 /* If there is no use in memory addess then we just check
18709 that split cost exceeds AGU stall. */
18713 /* If this insn has both backward non-agu dependence and forward
18714 agu dependence, the one with short distance takes effect. */
18716 }
18718 /* Return true if it is legal to clobber flags by INSN and
18719 false otherwise. */
18721 static bool
18723 {
18725 df_ref use;
18726 bitmap live;
18729 {
18731 {
18738 }
18744 }
18748 }
18750 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18751 move and add to avoid AGU stalls. */
18753 bool
18755 {
18758 /* Check if we need to optimize. */
18762 /* Check it is correct to split here. */
18770 /* We need to split only adds with non destructive
18771 destination operand. */
18774 else
18776 }
18778 /* Return true if we should emit lea instruction instead of mov
18779 instruction. */
18781 bool
18783 {
18786 /* Check if we need to optimize. */
18790 /* Use lea for reg to reg moves only. */
18798 }
18800 /* Return true if we need to split lea into a sequence of
18801 instructions to avoid AGU stalls. */
18803 bool
18805 {
18811 /* Check we need to optimize. */
18815 /* The "at least two components" test below might not catch simple
18816 move or zero extension insns if parts.base is non-NULL and parts.disp
18817 is const0_rtx as the only components in the address, e.g. if the
18818 register is %rbp or %r13. As this test is much cheaper and moves or
18819 zero extensions are the common case, do this check first. */
18825 /* Check if it is OK to split here. */
18832 /* There should be at least two components in the address. */
18837 /* We should not split into add if non legitimate pic
18838 operand is used as displacement. */
18853 /* Compute how many cycles we will add to execution time
18854 if split lea into a sequence of instructions. */
18856 {
18857 /* Have to use mov instruction if non desctructive
18858 destination form is used. */
18862 /* Have to add index to base if both exist. */
18866 /* Have to use shift and adds if scale is 2 or greater. */
18868 {
18873 else
18875 }
18877 /* Have to use add instruction with immediate if
18878 disp is non zero. */
18882 /* Subtract the price of lea. */
18884 }
18888 }
18890 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18891 matches destination. RTX includes clobber of FLAGS_REG. */
18893 static void
18896 {
18903 }
18905 /* Return true if regno1 def is nearest to the insn. */
18907 static bool
18909 {
18916 {
18918 {
18921 }
18927 }
18929 /* None of the regs is defined in the bb. */
18931 }
18933 /* Split lea instructions into a sequence of instructions
18934 which are executed on ALU to avoid AGU stalls.
18935 It is assumed that it is allowed to clobber flags register
18936 at lea position. */
18938 void
18940 {
18956 {
18959 }
18962 {
18965 }
18971 {
18972 /* Case r1 = r1 + ... */
18974 {
18975 /* If we have a case r1 = r1 + C * r2 then we
18976 should use multiplication which is very
18977 expensive. Assume cost model is wrong if we
18978 have such case here. */
18983 }
18984 else
18985 {
18986 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18990 /* Use shift for scaling. */
18999 }
19000 }
19002 {
19005 }
19006 else
19007 {
19009 {
19012 }
19014 {
19017 }
19018 else
19019 {
19024 else
19025 {
19026 rtx tmp1;
19028 /* Find better operand for SET instruction, depending
19029 on which definition is farther from the insn. */
19032 else
19042 }
19045 }
19049 }
19050 }
19052 /* Return true if it is ok to optimize an ADD operation to LEA
19053 operation to avoid flag register consumation. For most processors,
19054 ADD is faster than LEA. For the processors like BONNELL, if the
19055 destination register of LEA holds an actual address which will be
19056 used soon, LEA is better and otherwise ADD is better. */
19058 bool
19060 {
19065 /* If a = b + c, (a!=b && a!=c), must use lea form. */
19073 }
19075 /* Return true if destination reg of SET_BODY is shift count of
19076 USE_BODY. */
19078 static bool
19080 {
19081 rtx set_dest;
19082 rtx shift_rtx;
19085 /* Retrieve destination of SET_BODY. */
19087 {
19096 use_body))
19101 }
19103 /* Retrieve shift count of USE_BODY. */
19105 {
19117 }
19125 {
19128 /* Return true if shift count is dest of SET_BODY. */
19130 {
19131 /* Add check since it can be invoked before register
19132 allocation in pre-reload schedule. */
19138 }
19139 }
19142 }
19144 /* Return true if destination reg of SET_INSN is shift count of
19145 USE_INSN. */
19147 bool
19149 {
19152 }
19154 /* Return TRUE or FALSE depending on whether the unary operator meets the
19155 appropriate constraints. */
19157 bool
19159 machine_mode,
19161 {
19162 /* If one of operands is memory, source and destination must match. */
19168 }
19170 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19171 are ok, keeping in mind the possible movddup alternative. */
19173 bool
19175 {
19181 }
19183 /* Post-reload splitter for converting an SF or DFmode value in an
19184 SSE register into an unsigned SImode. */
19186 void
19188 {
19189 machine_mode vecmode;
19199 /* Load up the value into the low element. We must ensure that the other
19200 elements are valid floats -- zero is the easiest such value. */
19202 {
19205 else
19207 }
19208 else
19209 {
19214 else
19216 }
19236 else
19241 }
19243 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19244 Expects the 64-bit DImode to be supplied in a pair of integral
19245 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19246 -mfpmath=sse, !optimize_size only. */
19248 void
19250 {
19254 rtx x;
19260 {
19263 }
19264 else
19265 {
19269 }
19277 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19280 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19281 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19282 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19283 (0x1.0p84 + double(fp_value_hi_xmm)).
19284 Note these exponents differ by 32. */
19288 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19289 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19298 /* Add the upper and lower DFmode values together. */
19301 else
19302 {
19306 }
19309 }
19311 /* Not used, but eases macroization of patterns. */
19312 void
19314 {
19316 }
19318 /* Convert an unsigned SImode value into a DFmode. Only currently used
19319 for SSE, but applicable anywhere. */
19321 void
19323 {
19324 REAL_VALUE_TYPE TWO31r;
19339 }
19341 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19342 32-bit mode; otherwise we have a direct convert instruction. */
19344 void
19346 {
19347 REAL_VALUE_TYPE TWO32r;
19365 }
19367 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19368 For x86_32, -mfpmath=sse, !optimize_size only. */
19369 void
19371 {
19372 REAL_VALUE_TYPE ONE16r;
19391 }
19393 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19394 a vector of unsigned ints VAL to vector of floats TARGET. */
19396 void
19398 {
19400 REAL_VALUE_TYPE TWO16r;
19407 else
19412 OPTAB_DIRECT);
19423 OPTAB_DIRECT);
19425 OPTAB_DIRECT);
19428 }
19430 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19431 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19432 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19433 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19435 rtx
19437 {
19438 REAL_VALUE_TYPE TWO31r;
19453 {
19459 }
19468 OPTAB_DIRECT);
19469 else
19470 {
19476 OPTAB_DIRECT);
19477 }
19480 }
19482 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19483 then replicate the value for all elements of the vector
19484 register. */
19486 rtx
19488 {
19490 rtvec v;
19491 machine_mode scalar_mode;
19494 {
19527 }
19528 }
19530 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19531 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19532 for an SSE register. If VECT is true, then replicate the mask for
19533 all elements of the vector register. If INVERT is true, then create
19534 a mask excluding the sign bit. */
19536 rtx
19538 {
19540 wide_int w;
19544 {
19575 }
19582 /* Force this value into the low part of a fp vector constant. */
19591 }
19593 /* Generate code for floating point ABS or NEG. */
19595 void
19597 rtx operands[])
19598 {
19609 {
19615 }
19617 /* NEG and ABS performed with SSE use bitwise mask operations.
19618 Create the appropriate mask now. */
19621 else
19631 {
19633 rtvec par;
19638 else
19639 {
19642 }
19644 }
19645 else
19647 }
19649 /* Expand a copysign operation. Special case operand 0 being a constant. */
19651 void
19653 {
19667 else
19671 {
19678 {
19681 else
19682 {
19686 }
19687 }
19697 else
19701 }
19702 else
19703 {
19713 else
19717 }
19718 }
19720 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19721 be a constant, and so has already been expanded into a vector constant. */
19723 void
19725 {
19741 {
19744 }
19745 }
19747 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19748 so we have to do two masks. */
19750 void
19752 {
19767 {
19768 /* Shouldn't happen often (it's useless, obviously), but when it does
19769 we'd generate incorrect code if we continue below. */
19772 }
19775 {
19786 }
19787 else
19788 {
19790 {
19792 }
19794 {
19798 }
19802 {
19805 }
19807 {
19812 }
19814 }
19818 }
19820 /* Return TRUE or FALSE depending on whether the first SET in INSN
19821 has source and destination with matching CC modes, and that the
19822 CC mode is at least as constrained as REQ_MODE. */
19824 bool
19826 {
19827 rtx set;
19828 machine_mode set_mode;
19838 {
19848 /* FALLTHRU */
19852 /* FALLTHRU */
19856 /* FALLTHRU */
19871 }
19874 }
19876 /* Generate insn patterns to do an integer compare of OPERANDS. */
19878 static rtx
19880 {
19881 machine_mode cmpmode;
19887 /* This is very simple, but making the interface the same as in the
19888 FP case makes the rest of the code easier. */
19892 /* Return the test that should be put into the flags user, i.e.
19893 the bcc, scc, or cmov instruction. */
19895 }
19897 /* Figure out whether to use ordered or unordered fp comparisons.
19898 Return the appropriate mode to use. */
19900 machine_mode
19902 {
19903 /* ??? In order to make all comparisons reversible, we do all comparisons
19904 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19905 all forms trapping and nontrapping comparisons, we can make inequality
19906 comparisons trapping again, since it results in better code when using
19907 FCOM based compares. */
19909 }
19911 machine_mode
19913 {
19917 {
19920 }
19923 {
19924 /* Only zero flag is needed. */
19928 /* Codes needing carry flag. */
19931 /* Detect overflow checks. They need just the carry flag. */
19935 else
19940 /* Codes possibly doable only with sign flag when
19941 comparing against zero. */
19946 else
19947 /* For other cases Carry flag is not required. */
19949 /* Codes doable only with sign flag when comparing
19950 against zero, but we miss jump instruction for it
19951 so we need to use relational tests against overflow
19952 that thus needs to be zero. */
19957 else
19959 /* strcmp pattern do (use flags) and combine may ask us for proper
19960 mode. */
19965 }
19966 }
19968 /* Return the fixed registers used for condition codes. */
19970 static bool
19972 {
19976 }
19978 /* If two condition code modes are compatible, return a condition code
19979 mode which is compatible with both. Otherwise, return
19980 VOIDmode. */
19982 static machine_mode
19984 {
20001 {
20016 {
20031 }
20035 /* These are only compatible with themselves, which we already
20036 checked above. */
20038 }
20039 }
20042 /* Return a comparison we can do and that it is equivalent to
20043 swap_condition (code) apart possibly from orderedness.
20044 But, never change orderedness if TARGET_IEEE_FP, returning
20045 UNKNOWN in that case if necessary. */
20047 static enum rtx_code
20049 {
20051 {
20062 }
20063 }
20065 /* Return cost of comparison CODE using the best strategy for performance.
20066 All following functions do use number of instructions as a cost metrics.
20067 In future this should be tweaked to compute bytes for optimize_size and
20068 take into account performance of various instructions on various CPUs. */
20070 static int
20072 {
20075 /* The cost of code using bit-twiddling on %ah. */
20077 {
20100 }
20103 {
20110 }
20111 }
20113 /* Return strategy to use for floating-point. We assume that fcomi is always
20114 preferrable where available, since that is also true when looking at size
20115 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20117 enum ix86_fpcmp_strategy
20119 {
20120 /* Do fcomi/sahf based test when profitable. */
20129 }
20131 /* Swap, force into registers, or otherwise massage the two operands
20132 to a fp comparison. The operands are updated in place; the new
20133 comparison code is returned. */
20135 static enum rtx_code
20137 {
20143 /* All of the unordered compare instructions only work on registers.
20144 The same is true of the fcomi compare instructions. The XFmode
20145 compare instructions require registers except when comparing
20146 against zero or when converting operand 1 from fixed point to
20147 floating point. */
20156 {
20159 }
20160 else
20161 {
20162 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20163 things around if they appear profitable, otherwise force op0
20164 into a register. */
20170 {
20173 {
20176 }
20177 }
20183 {
20188 {
20191 }
20192 else
20194 }
20195 }
20197 /* Try to rearrange the comparison to make it cheaper. */
20201 {
20206 }
20211 }
20213 /* Convert comparison codes we use to represent FP comparison to integer
20214 code that will result in proper branch. Return UNKNOWN if no such code
20215 is available. */
20217 enum rtx_code
20219 {
20221 {
20244 }
20245 }
20247 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20249 static rtx
20251 {
20258 /* Do fcomi/sahf based test when profitable. */
20260 {
20280 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20287 /* In the unordered case, we have to check C2 for NaN's, which
20288 doesn't happen to work out to anything nice combination-wise.
20289 So do some bit twiddling on the value we've got in AH to come
20290 up with an appropriate set of condition codes. */
20294 {
20298 {
20301 }
20302 else
20303 {
20309 }
20314 {
20319 }
20320 else
20321 {
20324 }
20329 {
20332 }
20333 else
20334 {
20338 }
20343 {
20349 }
20350 else
20351 {
20354 }
20359 {
20364 }
20365 else
20366 {
20369 }
20374 {
20379 }
20380 else
20381 {
20384 }
20398 }
20403 }
20405 /* Return the test that should be put into the flags user, i.e.
20406 the bcc, scc, or cmov instruction. */
20409 const0_rtx);
20410 }
20412 static rtx
20414 {
20415 rtx ret;
20421 {
20424 }
20425 else
20429 }
20431 void
20433 {
20435 rtx tmp;
20438 {
20445 simple:
20449 pc_rtx);
20457 /* Expand DImode branch into multiple compare+branch. */
20458 {
20462 machine_mode submode;
20465 {
20468 }
20475 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20476 avoid two branches. This costs one extra insn, so disable when
20477 optimizing for size. */
20482 {
20500 }
20502 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20503 op1 is a constant and the low word is zero, then we can just
20504 examine the high word. Similarly for low word -1 and
20505 less-or-equal-than or greater-than. */
20509 {
20512 {
20515 }
20519 {
20522 }
20526 }
20528 /* Otherwise, we need two or three jumps. */
20537 {
20551 }
20553 /*
20554 * a < b =>
20555 * if (hi(a) < hi(b)) goto true;
20556 * if (hi(a) > hi(b)) goto false;
20557 * if (lo(a) < lo(b)) goto true;
20558 * false:
20559 */
20571 }
20576 }
20577 }
20579 /* Split branch based on floating point condition. */
20580 void
20583 {
20584 rtx condition;
20585 rtx i;
20588 {
20591 }
20594 tmp);
20602 }
20604 void
20606 {
20607 rtx ret;
20614 }
20616 /* Expand comparison setting or clearing carry flag. Return true when
20617 successful and set pop for the operation. */
20618 static bool
20620 {
20621 machine_mode mode =
20624 /* Do not handle double-mode compares that go through special path. */
20629 {
20630 rtx compare_op;
20635 /* Shortcut: following common codes never translate
20636 into carry flag compares. */
20641 /* These comparisons require zero flag; swap operands so they won't. */
20644 {
20647 }
20649 /* Try to expand the comparison and verify that we end up with
20650 carry flag based comparison. This fails to be true only when
20651 we decide to expand comparison using arithmetic that is not
20652 too common scenario. */
20661 else
20670 }
20676 {
20681 /* Convert a==0 into (unsigned)a<1. */
20690 /* Convert a>b into b<a or a>=b-1. */
20694 {
20696 /* Bail out on overflow. We still can swap operands but that
20697 would force loading of the constant into register. */
20702 }
20703 else
20704 {
20707 }
20710 /* Convert a>=0 into (unsigned)a<0x80000000. */
20728 }
20729 /* Swapping operands may cause constant to appear as first operand. */
20731 {
20735 }
20739 }
20741 bool
20743 {
20746 rtx compare_op;
20768 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20769 HImode insns, we'd be swallowed in word prefix ops. */
20775 {
20779 HOST_WIDE_INT diff;
20782 /* Sign bit compares are better done using shifts than we do by using
20783 sbb. */
20786 {
20787 /* Detect overlap between destination and compare sources. */
20791 {
20792 rtx flags;
20801 {
20803 compare_code
20805 }
20807 /* To simplify rest of code, restrict to the GEU case. */
20809 {
20813 }
20814 else
20815 {
20818 reverse_condition_maybe_unordered
20820 else
20823 }
20832 else
20835 }
20836 else
20837 {
20840 else
20841 {
20844 }
20846 }
20849 {
20850 /*
20851 * cmpl op0,op1
20852 * sbbl dest,dest
20853 * [addl dest, ct]
20854 *
20855 * Size 5 - 8.
20856 */
20861 }
20863 {
20864 /*
20865 * cmpl op0,op1
20866 * sbbl dest,dest
20867 * orl $ct, dest
20868 *
20869 * Size 8.
20870 */
20874 }
20876 {
20877 /*
20878 * cmpl op0,op1
20879 * sbbl dest,dest
20880 * notl dest
20881 * [addl dest, cf]
20882 *
20883 * Size 8 - 11.
20884 */
20890 }
20891 else
20892 {
20893 /*
20894 * cmpl op0,op1
20895 * sbbl dest,dest
20896 * [notl dest]
20897 * andl cf - ct, dest
20898 * [addl dest, ct]
20899 *
20900 * Size 8 - 11.
20901 */
20904 {
20908 }
20918 }
20924 }
20927 {
20932 {
20935 /* We may be reversing unordered compare to normal compare, that
20936 is not valid in general (we may convert non-trapping condition
20937 to trapping one), however on i386 we currently emit all
20938 comparisons unordered. */
20940 }
20941 else
20944 {
20948 }
20949 }
20954 {
20959 {
20964 }
20965 }
20967 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20971 {
20972 /* If lea code below could be used, only optimize
20973 if it results in a 2 insn sequence. */
20979 {
20980 /*
20981 * notl op1 (if necessary)
20982 * sarl $31, op1
20983 * orl cf, op1
20984 */
20986 {
20990 }
21001 }
21002 }
21010 {
21011 /*
21012 * xorl dest,dest
21013 * cmpl op1,op2
21014 * setcc dest
21015 * lea cf(dest*(ct-cf)),dest
21016 *
21017 * Size 14.
21018 *
21019 * This also catches the degenerate setcc-only case.
21020 */
21022 rtx tmp;
21028 /* On x86_64 the lea instruction operates on Pmode, so we need
21029 to get arithmetics done in proper mode to match. */
21032 else
21033 {
21034 rtx out1;
21037 nops++;
21039 {
21041 nops++;
21042 }
21043 }
21045 {
21047 nops++;
21048 }
21050 {
21053 else
21055 }
21060 }
21062 /*
21063 * General case: Jumpful:
21064 * xorl dest,dest cmpl op1, op2
21065 * cmpl op1, op2 movl ct, dest
21066 * setcc dest jcc 1f
21067 * decl dest movl cf, dest
21068 * andl (cf-ct),dest 1:
21069 * addl ct,dest
21070 *
21071 * Size 20. Size 14.
21072 *
21073 * This is reasonably steep, but branch mispredict costs are
21074 * high on modern cpus, so consider failing only if optimizing
21075 * for space.
21076 */
21081 {
21083 {
21088 {
21091 /* We may be reversing unordered compare to normal compare,
21092 that is not valid in general (we may convert non-trapping
21093 condition to trapping one), however on i386 we currently
21094 emit all comparisons unordered. */
21096 }
21097 else
21098 {
21102 }
21105 {
21109 }
21110 }
21113 {
21114 /* notl op1 (if needed)
21115 sarl $31, op1
21116 andl (cf-ct), op1
21117 addl ct, op1
21119 For x < 0 (resp. x <= -1) there will be no notl,
21120 so if possible swap the constants to get rid of the
21121 complement.
21122 True/false will be -1/0 while code below (store flag
21123 followed by decrement) is 0/-1, so the constants need
21124 to be exchanged once more. */
21127 {
21130 }
21131 else
21135 }
21136 else
21137 {
21141 constm1_rtx,
21143 }
21155 }
21156 }
21159 {
21160 /* Try a few things more with specific constants and a variable. */
21162 optab op;
21168 /* If one of the two operands is an interesting constant, load a
21169 constant with the above and mask it in with a logical operation. */
21172 {
21178 else
21180 }
21182 {
21188 else
21190 }
21191 else
21198 /* Recurse to get the constant loaded. */
21202 /* Mask in the interesting variable. */
21204 OPTAB_WIDEN);
21209 }
21211 /*
21212 * For comparison with above,
21213 *
21214 * movl cf,dest
21215 * movl ct,tmp
21216 * cmpl op1,op2
21217 * cmovcc tmp,dest
21218 *
21219 * Size 15.
21220 */
21242 }
21244 /* Swap, force into registers, or otherwise massage the two operands
21245 to an sse comparison with a mask result. Thus we differ a bit from
21246 ix86_prepare_fp_compare_args which expects to produce a flags result.
21248 The DEST operand exists to help determine whether to commute commutative
21249 operators. The POP0/POP1 operands are updated in place. The new
21250 comparison code is returned, or UNKNOWN if not implementable. */
21252 static enum rtx_code
21255 {
21257 {
21260 /* AVX supports all the needed comparisons. */
21263 /* We have no LTGT as an operator. We could implement it with
21264 NE & ORDERED, but this requires an extra temporary. It's
21265 not clear that it's worth it. */
21272 /* These are supported directly. */
21279 /* AVX has 3 operand comparisons, no need to swap anything. */
21282 /* For commutative operators, try to canonicalize the destination
21283 operand to be first in the comparison - this helps reload to
21284 avoid extra moves. */
21287 /* FALLTHRU */
21293 /* These are not supported directly before AVX, and furthermore
21294 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21295 comparison operands to transform into something that is
21296 supported. */
21303 }
21306 }
21308 /* Detect conditional moves that exactly match min/max operational
21309 semantics. Note that this is IEEE safe, as long as we don't
21310 interchange the operands.
21312 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21313 and TRUE if the operation is successful and instructions are emitted. */
21315 static bool
21318 {
21319 machine_mode mode;
21321 rtx tmp;
21324 ;
21327 else
21334 else
21339 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21340 but MODE may be a vector mode and thus not appropriate. */
21342 {
21344 rtvec v;
21349 }
21350 else
21351 {
21354 }
21358 }
21360 /* Expand an sse vector comparison. Return the register with the result. */
21362 static rtx
21365 {
21369 /* In general case result of comparison can differ from operands' type. */
21370 machine_mode cmp_mode;
21372 /* In AVX512F the result of comparison is an integer mask. */
21374 rtx x;
21377 {
21382 }
21383 else
21396 /* Compare patterns for int modes are unspec in AVX512F only. */
21398 {
21402 {
21419 }
21422 {
21425 }
21426 }
21430 {
21433 }
21434 else
21438 }
21440 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21441 operations. This is used for both scalar and vector conditional moves. */
21443 static void
21445 {
21449 /* In AVX512F the result of comparison is an integer mask. */
21457 {
21459 }
21462 {
21466 }
21469 {
21474 }
21477 {
21481 }
21484 {
21491 op_true,
21492 op_false)));
21493 }
21494 else
21495 {
21505 {
21519 {
21526 }
21541 {
21548 }
21572 }
21575 {
21579 }
21580 else
21581 {
21587 else
21599 }
21600 }
21601 }
21603 /* Expand a floating-point conditional move. Return true if successful. */
21605 bool
21607 {
21615 {
21616 machine_mode cmode;
21618 /* Since we've no cmove for sse registers, don't force bad register
21619 allocation just to gain access to it. Deny movcc when the
21620 comparison mode doesn't match the move mode. */
21639 }
21646 /* The floating point conditional move instructions don't directly
21647 support conditions resulting from a signed integer comparison. */
21651 {
21656 }
21663 }
21665 /* Expand a floating-point vector conditional move; a vcond operation
21666 rather than a movcc operation. */
21668 bool
21670 {
21672 rtx cmp;
21677 {
21678 rtx temp;
21680 {
21697 }
21699 OPTAB_DIRECT);
21702 }
21712 }
21714 /* Expand a signed/unsigned integral vector conditional move. */
21716 bool
21718 {
21728 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21729 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21738 {
21742 {
21748 }
21751 {
21757 }
21758 }
21767 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21771 ;
21772 else
21773 {
21774 /* Canonicalize the comparison to EQ, GT, GTU. */
21776 {
21793 /* FALLTHRU */
21803 }
21805 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21807 {
21809 {
21811 /* SSE4.1 supports EQ. */
21818 /* SSE4.2 supports GT/GTU. */
21825 }
21826 }
21828 /* Unsigned parallel compare is not supported by the hardware.
21829 Play some tricks to turn this into a signed comparison
21830 against 0. */
21832 {
21836 {
21843 {
21848 {
21857 }
21858 /* Subtract (-(INT MAX) - 1) from both operands to make
21859 them signed. */
21870 }
21879 /* Perform a parallel unsigned saturating subtraction. */
21891 }
21892 }
21893 }
21895 /* Allow the comparison to be done in one mode, but the movcc to
21896 happen in another mode. */
21898 {
21901 }
21902 else
21903 {
21909 }
21914 }
21916 /* AVX512F does support 64-byte integer vector operations,
21917 thus the longest vector we are faced with is V64QImode. */
21918 #define MAX_VECT_LEN 64
21920 struct expand_vec_perm_d
21921 {
21924 machine_mode vmode;
21928 };
21930 static bool
21933 {
21934 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21935 expander, so args are either in d, or in op0, op1 etc. */
21941 {
21972 {
21975 }
21979 {
21982 }
21986 {
21989 }
22005 {
22008 }
22012 {
22015 }
22019 {
22022 }
22026 }
22031 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
22032 expander, so args are either in d, or in op0, op1 etc. */
22034 {
22042 }
22046 }
22048 /* Expand a variable vector permutation. */
22050 void
22052 {
22063 /* Number of elements in the vector. */
22072 {
22074 {
22075 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
22076 an constant shuffle operand. With a tiny bit of effort we can
22077 use VPERMD instead. A re-interpretation stall for V4DFmode is
22078 unfortunate but there's no avoiding it.
22079 Similarly for V16HImode we don't have instructions for variable
22080 shuffling, while for V32QImode we can use after preparing suitable
22081 masks vpshufb; vpshufb; vpermq; vpor. */
22084 {
22088 }
22089 else
22090 {
22094 }
22097 /* Replicate the low bits of the V4DImode mask into V8SImode:
22098 mask = { A B C D }
22099 t1 = { A A B B C C D D }. */
22107 else
22110 /* Multiply the shuffle indicies by two. */
22112 OPTAB_DIRECT);
22114 /* Add one to the odd shuffle indicies:
22115 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22117 {
22120 }
22124 OPTAB_DIRECT);
22126 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22131 }
22134 {
22136 /* The VPERMD and VPERMPS instructions already properly ignore
22137 the high bits of the shuffle elements. No need for us to
22138 perform an AND ourselves. */
22140 {
22145 }
22146 else
22147 {
22153 }
22160 else
22161 {
22167 }
22171 /* By combining the two 128-bit input vectors into one 256-bit
22172 input vector, we can use VPERMD and VPERMPS for the full
22173 two-operand shuffle. */
22205 /* From mask create two adjusted masks, which contain the same
22206 bits as mask in the low 7 bits of each vector element.
22207 The first mask will have the most significant bit clear
22208 if it requests element from the same 128-bit lane
22209 and MSB set if it requests element from the other 128-bit lane.
22210 The second mask will have the opposite values of the MSB,
22211 and additionally will have its 128-bit lanes swapped.
22212 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22213 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22214 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22215 stands for other 12 bytes. */
22216 /* The bit whether element is from the same lane or the other
22217 lane is bit 4, so shift it up by 3 to the MSB position. */
22221 /* Clear MSB bits from the mask just in case it had them set. */
22223 /* After this t1 will have MSB set for elements from other lane. */
22225 /* Clear bits other than MSB. */
22227 /* Or in the lower bits from mask into t3. */
22229 /* And invert MSB bits in t1, so MSB is set for elements from the same
22230 lane. */
22232 /* Swap 128-bit lanes in t3. */
22237 /* And or in the lower bits from mask into t1. */
22240 {
22241 /* Each of these shuffles will put 0s in places where
22242 element from the other 128-bit lane is needed, otherwise
22243 will shuffle in the requested value. */
22247 /* For t3 the 128-bit lanes are swapped again. */
22252 /* And oring both together leads to the result. */
22259 }
22262 /* Similarly to the above one_operand_shuffle code,
22263 just for repeated twice for each operand. merge_two:
22264 code will merge the two results together. */
22288 }
22289 }
22292 {
22293 /* The XOP VPPERM insn supports three inputs. By ignoring the
22294 one_operand_shuffle special case, we avoid creating another
22295 set of constant vectors in memory. */
22298 /* mask = mask & {2*w-1, ...} */
22300 }
22301 else
22302 {
22303 /* mask = mask & {w-1, ...} */
22305 }
22313 /* For non-QImode operations, convert the word permutation control
22314 into a byte permutation control. */
22316 {
22321 /* Convert mask to vector of chars. */
22324 /* Replicate each of the input bytes into byte positions:
22325 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22326 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22327 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22334 else
22337 /* Convert it into the byte positions by doing
22338 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22344 }
22346 /* The actual shuffle operations all operate on V16QImode. */
22351 {
22358 }
22360 {
22367 }
22368 else
22369 {
22373 /* Shuffle the two input vectors independently. */
22379 merge_two:
22380 /* Then merge them together. The key is whether any given control
22381 element contained a bit set that indicates the second word. */
22385 {
22386 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22387 more shuffle to convert the V2DI input mask into a V4SI
22388 input mask. At which point the masking that expand_int_vcond
22389 will work as desired. */
22397 }
22419 }
22420 }
22422 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22423 true if we should do zero extension, else sign extension. HIGH_P is
22424 true if we want the N/2 high elements, else the low elements. */
22426 void
22428 {
22430 rtx tmp;
22433 {
22439 {
22443 else
22446 extract
22452 else
22455 extract
22461 else
22464 extract
22470 else
22473 extract
22479 else
22482 extract
22488 else
22491 extract
22497 else
22503 else
22509 else
22514 }
22517 {
22520 }
22522 {
22523 /* Shift higher 8 bytes to lower 8 bytes. */
22528 }
22529 else
22533 }
22534 else
22535 {
22539 {
22543 else
22549 else
22555 else
22560 }
22564 else
22571 }
22572 }
22574 /* Expand conditional increment or decrement using adb/sbb instructions.
22575 The default case using setcc followed by the conditional move can be
22576 done by generic code. */
22577 bool
22579 {
22581 rtx flags;
22583 rtx compare_op;
22586 machine_mode mode;
22601 {
22604 }
22607 {
22611 reverse_condition_maybe_unordered
22613 else
22615 }
22619 /* Construct either adc or sbb insn. */
22621 {
22623 {
22638 }
22639 }
22640 else
22641 {
22643 {
22658 }
22659 }
22663 }
22666 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22667 but works for floating pointer parameters and nonoffsetable memories.
22668 For pushes, it returns just stack offsets; the values will be saved
22669 in the right order. Maximally three parts are generated. */
22671 static int
22673 {
22678 else
22684 /* Optimize constant pool reference to immediates. This is used by fp
22685 moves, that force all constants to memory to allow combining. */
22687 {
22691 }
22694 {
22695 /* The only non-offsetable memories we handle are pushes. */
22704 }
22707 {
22709 /* Caution: if we looked through a constant pool memory above,
22710 the operand may actually have a different mode now. That's
22711 ok, since we want to pun this all the way back to an integer. */
22715 }
22718 {
22721 else
22722 {
22726 {
22730 }
22732 {
22737 }
22739 {
22740 REAL_VALUE_TYPE r;
22745 {
22752 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22753 long double may not be 80-bit. */
22762 }
22765 }
22766 else
22768 }
22769 }
22770 else
22771 {
22775 {
22778 {
22782 }
22784 {
22788 }
22790 {
22791 REAL_VALUE_TYPE r;
22797 /* real_to_target puts 32-bit pieces in each long. */
22799 gen_int_mode
22802 DImode);
22806 else
22808 gen_int_mode
22811 DImode);
22812 }
22813 else
22815 }
22816 }
22819 }
22821 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22822 Return false when normal moves are needed; true when all required
22823 insns have been emitted. Operands 2-4 contain the input values
22824 int the correct order; operands 5-7 contain the output values. */
22826 void
22828 {
22836 /* The DFmode expanders may ask us to move double.
22837 For 64bit target this is single move. By hiding the fact
22838 here we simplify i386.md splitters. */
22840 {
22841 /* Optimize constant pool reference to immediates. This is used by
22842 fp moves, that force all constants to memory to allow combining. */
22849 {
22852 }
22853 else
22858 }
22860 /* The only non-offsettable memory we handle is push. */
22863 else
22870 /* When emitting push, take care for source operands on the stack. */
22873 {
22876 /* Compensate for the stack decrement by 4. */
22881 /* src_base refers to the stack pointer and is
22882 automatically decreased by emitted push. */
22886 }
22888 /* We need to do copy in the right order in case an address register
22889 of the source overlaps the destination. */
22891 {
22892 rtx tmp;
22895 {
22899 collisions++;
22900 }
22902 /* Collision in the middle part can be handled by reordering. */
22904 {
22907 }
22911 {
22913 {
22916 }
22917 else
22918 {
22921 }
22922 }
22924 /* If there are more collisions, we can't handle it by reordering.
22925 Do an lea to the last part and use only one colliding move. */
22927 {
22934 /* Handle the case when the last part isn't valid for lea.
22935 Happens in 64-bit mode storing the 12-byte XFmode. */
22941 {
22946 {
22947 /* It is not valid to use %gs: or %fs: in
22948 lea though, so we need to remove it from the
22949 address used for lea and add it to each individual
22950 memory loads instead. */
22954 {
22956 {
22962 {
22966 }
22967 }
22971 }
22973 }
22974 }
22980 {
22985 }
22986 }
22987 }
22990 {
22992 {
22994 {
22999 }
23001 {
23004 }
23005 }
23006 else
23007 {
23008 /* In 64bit mode we don't have 32bit push available. In case this is
23009 register, it is OK - we will just use larger counterpart. We also
23010 retype memory - these comes from attempt to avoid REX prefix on
23011 moving of second half of TFmode value. */
23013 {
23015 {
23026 }
23030 }
23031 }
23035 }
23037 /* Choose correct order to not overwrite the source before it is copied. */
23047 {
23049 {
23052 }
23053 }
23054 else
23055 {
23057 {
23060 }
23061 }
23063 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
23065 {
23074 }
23080 }
23082 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
23083 left shift by a constant, either using a single shift or
23084 a sequence of add instructions. */
23086 static void
23088 {
23094 {
23098 }
23099 else
23100 {
23103 }
23104 }
23106 void
23108 {
23117 {
23122 {
23128 }
23129 else
23130 {
23138 }
23140 }
23147 {
23148 /* Assuming we've chosen a QImode capable registers, then 1 << N
23149 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23151 {
23167 }
23169 /* Otherwise, we can get the same results by manually performing
23170 a bit extract operation on bit 5/6, and then performing the two
23171 shifts. The two methods of getting 0/1 into low/high are exactly
23172 the same size. Avoiding the shift in the bit extract case helps
23173 pentium4 a bit; no one else seems to care much either way. */
23174 else
23175 {
23176 machine_mode half_mode;
23180 HOST_WIDE_INT bits;
23181 rtx x;
23184 {
23190 }
23191 else
23192 {
23198 }
23202 else
23210 }
23215 }
23218 {
23219 /* For -1 << N, we can avoid the shld instruction, because we
23220 know that we're shifting 0...31/63 ones into a -1. */
23224 else
23226 }
23227 else
23228 {
23236 }
23241 {
23247 }
23248 else
23249 {
23254 }
23255 }
23257 void
23259 {
23269 {
23274 {
23280 }
23282 {
23291 }
23292 else
23293 {
23301 }
23302 }
23303 else
23304 {
23316 {
23324 scratch));
23325 }
23326 else
23327 {
23332 }
23333 }
23334 }
23336 void
23338 {
23348 {
23353 {
23360 }
23361 else
23362 {
23370 }
23371 }
23372 else
23373 {
23385 {
23391 scratch));
23392 }
23393 else
23394 {
23399 }
23400 }
23401 }
23403 /* Predict just emitted jump instruction to be taken with probability PROB. */
23404 static void
23406 {
23410 }
23412 /* Helper function for the string operations below. Dest VARIABLE whether
23413 it is aligned to VALUE bytes. If true, jump to the label. */
23416 {
23421 else
23427 else
23430 }
23432 /* Adjust COUNTER by the VALUE. */
23433 static void
23435 {
23440 }
23442 /* Zero extend possibly SImode EXP to Pmode register. */
23443 rtx
23445 {
23447 }
23449 /* Divide COUNTREG by SCALE. */
23450 static rtx
23452 {
23453 rtx sc;
23465 }
23467 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23468 DImode for constant loop counts. */
23470 static machine_mode
23472 {
23480 }
23482 /* Copy the address to a Pmode register. This is used for x32 to
23483 truncate DImode TLS address to a SImode register. */
23485 static rtx
23487 {
23488 rtx reg;
23490 {
23494 }
23495 else
23496 {
23501 }
23502 }
23504 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23505 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23506 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23507 memory by VALUE (supposed to be in MODE).
23509 The size is rounded down to whole number of chunk size moved at once.
23510 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23513 static void
23518 {
23525 rtx size;
23534 /* Those two should combine. */
23536 {
23540 }
23547 /* This assert could be relaxed - in this case we'll need to compute
23548 smallest power of two, containing in PIECE_SIZE_N and pass it to
23549 offset_address. */
23555 {
23559 /* When unrolling for chips that reorder memory reads and writes,
23560 we can save registers by using single temporary.
23561 Also using 4 temporaries is overkill in 32bit mode. */
23563 {
23565 {
23567 {
23568 destmem =
23570 srcmem =
23572 }
23574 }
23575 }
23576 else
23577 {
23581 {
23584 {
23585 srcmem =
23587 }
23589 }
23591 {
23593 {
23594 destmem =
23596 }
23598 }
23599 }
23600 }
23601 else
23603 {
23605 destmem =
23608 }
23618 {
23624 else
23626 }
23627 else
23635 {
23640 }
23642 }
23644 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23645 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23646 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23647 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23648 ORIG_VALUE is the original value passed to memset to fill the memory with.
23649 Other arguments have same meaning as for previous function. */
23651 static void
23654 rtx count,
23656 {
23657 rtx destexp;
23658 rtx srcexp;
23659 rtx countreg;
23660 HOST_WIDE_INT rounded_count;
23662 /* If possible, it is shorter to use rep movs.
23663 TODO: Maybe it is better to move this logic to decide_alg. */
23674 {
23678 }
23679 else
23682 {
23687 }
23692 {
23695 }
23696 else
23697 {
23701 {
23705 }
23706 else
23709 {
23714 }
23715 else
23716 {
23719 }
23722 }
23723 }
23725 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23726 DESTMEM.
23727 SRC is passed by pointer to be updated on return.
23728 Return value is updated DST. */
23729 static rtx
23731 HOST_WIDE_INT size_to_move)
23732 {
23735 machine_mode move_mode;
23738 /* Find the widest mode in which we could perform moves.
23739 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23740 it until move of such size is supported. */
23745 {
23749 }
23751 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23752 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23754 {
23759 {
23763 }
23764 }
23770 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23774 {
23775 /* We move from memory to memory, so we'll need to do it via
23776 a temporary register. */
23787 piece_size);
23789 piece_size);
23790 }
23792 /* Update DST and SRC rtx. */
23795 }
23797 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23798 static void
23801 {
23804 {
23809 /* For now MAX_SIZE should be a power of 2. This assert could be
23810 relaxed, but it'll require a bit more complicated epilogue
23811 expanding. */
23814 {
23817 }
23819 }
23821 {
23827 }
23829 /* When there are stringops, we can cheaply increase dest and src pointers.
23830 Otherwise we save code size by maintaining offset (zero is readily
23831 available from preceding rep operation) and using x86 addressing modes.
23832 */
23834 {
23836 {
23843 }
23845 {
23852 }
23854 {
23861 }
23862 }
23863 else
23864 {
23866 rtx tmp;
23869 {
23880 }
23882 {
23895 }
23897 {
23906 }
23907 }
23908 }
23910 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23911 with value PROMOTED_VAL.
23912 SRC is passed by pointer to be updated on return.
23913 Return value is updated DST. */
23914 static rtx
23916 HOST_WIDE_INT size_to_move)
23917 {
23920 machine_mode move_mode;
23923 /* Find the widest mode in which we could perform moves.
23924 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23925 it until move of such size is supported. */
23930 {
23933 }
23940 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23944 {
23946 {
23949 piece_size);
23951 }
23959 piece_size);
23960 }
23962 /* Update DST rtx. */
23964 }
23965 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23966 static void
23969 {
23970 count =
23976 }
23978 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23979 static void
23982 {
23983 rtx dest;
23986 {
23991 /* For now MAX_SIZE should be a power of 2. This assert could be
23992 relaxed, but it'll require a bit more complicated epilogue
23993 expanding. */
23996 {
23998 {
24001 else
24003 }
24004 }
24006 }
24008 {
24011 }
24013 {
24016 {
24021 }
24022 else
24023 {
24032 }
24035 }
24037 {
24040 {
24043 }
24044 else
24045 {
24050 }
24053 }
24055 {
24061 }
24063 {
24069 }
24071 {
24077 }
24078 }
24080 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
24081 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
24082 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
24083 ignored.
24084 Return value is updated DESTMEM. */
24085 static rtx
24090 {
24093 {
24095 {
24098 {
24101 else
24103 }
24104 else
24110 }
24111 }
24113 }
24115 /* Test if COUNT&SIZE is nonzero and if so, expand movme
24116 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
24117 and jump to DONE_LABEL. */
24118 static void
24124 {
24127 rtx modesize;
24130 /* If we do not have vector value to copy, we must reduce size. */
24132 {
24134 {
24139 }
24140 else
24142 }
24143 else
24144 {
24145 /* Choose appropriate vector mode. */
24151 }
24156 {
24159 else
24160 {
24163 }
24165 }
24171 {
24175 }
24177 {
24180 else
24181 {
24184 }
24186 }
24192 }
24194 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24195 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24196 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24197 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24198 DONE_LABEL is a label after the whole copying sequence. The label is created
24199 on demand if *DONE_LABEL is NULL.
24200 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24201 bounds after the initial copies.
24203 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24204 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24205 we will dispatch to a library call for large blocks.
24207 In pseudocode we do:
24209 if (COUNT < SIZE)
24210 {
24211 Assume that SIZE is 4. Bigger sizes are handled analogously
24212 if (COUNT & 4)
24213 {
24214 copy 4 bytes from SRCPTR to DESTPTR
24215 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24216 goto done_label
24217 }
24218 if (!COUNT)
24219 goto done_label;
24220 copy 1 byte from SRCPTR to DESTPTR
24221 if (COUNT & 2)
24222 {
24223 copy 2 bytes from SRCPTR to DESTPTR
24224 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24225 }
24226 }
24227 else
24228 {
24229 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24230 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24232 OLD_DESPTR = DESTPTR;
24233 Align DESTPTR up to DESIRED_ALIGN
24234 SRCPTR += DESTPTR - OLD_DESTPTR
24235 COUNT -= DEST_PTR - OLD_DESTPTR
24236 if (DYNAMIC_CHECK)
24237 Round COUNT down to multiple of SIZE
24238 << optional caller supplied zero size guard is here >>
24239 << optional caller suppplied dynamic check is here >>
24240 << caller supplied main copy loop is here >>
24241 }
24242 done_label:
24243 */
24244 static void
24247 machine_mode mode,
24257 {
24260 rtx modesize;
24262 rtx mode_value;
24264 /* Chose proper value to copy. */
24267 else
24271 /* See if block is big or small, handle small blocks. */
24273 {
24284 /* Handle sizes > 3. */
24291 /* Nothing to copy? Jump to DONE_LABEL if so */
24295 /* Do a byte copy. */
24299 else
24300 {
24303 }
24305 /* Handle sizes 2 and 3. */
24312 else
24313 {
24318 }
24324 }
24325 else
24329 /* Start memcpy for COUNT >= SIZE. */
24331 {
24334 }
24336 /* Copy first desired_align bytes. */
24342 {
24345 else
24346 {
24349 }
24352 }
24355 /* Copy last SIZE bytes. */
24362 else
24363 {
24369 }
24371 {
24375 else
24376 {
24379 }
24380 }
24382 /* Align destination. */
24384 {
24388 /* Align destptr up, place it to new register. */
24397 /* See how many bytes we skipped. */
24401 /* Adjust srcptr and count. */
24407 /* We copied at most size + prolog_size. */
24410 else
24413 /* Our loops always round down the bock size, but for dispatch to library
24414 we need precise value. */
24418 }
24419 else
24420 {
24422 /* Decrease count, so we won't end up copying last word twice. */
24426 else
24430 }
24431 }
24434 /* This function is like the previous one, except here we know how many bytes
24435 need to be copied. That allows us to update alignment not only of DST, which
24436 is returned, but also of SRC, which is passed as a pointer for that
24437 reason. */
24438 static rtx
24443 {
24451 {
24455 }
24460 {
24462 {
24464 {
24467 else
24469 }
24470 else
24473 }
24474 }
24481 {
24487 {
24490 {
24494 }
24499 }
24503 }
24506 }
24508 /* Return true if ALG can be used in current context.
24509 Assume we expand memset if MEMSET is true. */
24510 static bool
24512 {
24517 /* Algorithms using the rep prefix want at least edi and ecx;
24518 additionally, memset wants eax and memcpy wants esi. Don't
24519 consider such algorithms if the user has appropriated those
24520 registers for their own purposes. */
24527 }
24529 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24530 static enum stringop_alg
24534 {
24545 /* Even if the string operation call is cold, we still might spend a lot
24546 of time processing large blocks. */
24552 else
24558 else
24561 /* See maximal size for user defined algorithm. */
24563 {
24570 }
24572 /* If expected size is not known but max size is small enough
24573 so inline version is a win, set expected size into
24574 the range. */
24579 /* If user specified the algorithm, honnor it if possible. */
24583 /* rep; movq or rep; movl is the smallest variant. */
24585 {
24590 else
24593 }
24594 /* Very tiny blocks are best handled via the loop, REP is expensive to
24595 setup. */
24599 {
24603 {
24604 /* We get here if the algorithms that were not libcall-based
24605 were rep-prefix based and we are unable to use rep prefixes
24606 based on global register usage. Break out of the loop and
24607 use the heuristic below. */
24611 {
24615 {
24618 }
24619 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24620 last non-libcall inline algorithm. */
24622 {
24623 /* When the current size is best to be copied by a libcall,
24624 but we are still forced to inline, run the heuristic below
24625 that will pick code for medium sized blocks. */
24627 {
24630 }
24633 }
24635 {
24638 }
24639 }
24640 }
24641 }
24642 /* When asked to inline the call anyway, try to pick meaningful choice.
24643 We look for maximal size of block that is faster to copy by hand and
24644 take blocks of at most of that size guessing that average size will
24645 be roughly half of the block.
24647 If this turns out to be bad, we might simply specify the preferred
24648 choice in ix86_costs. */
24652 {
24655 /* If there aren't any usable algorithms, then recursing on
24656 smaller sizes isn't going to find anything. Just return the
24657 simple byte-at-a-time copy loop. */
24659 {
24660 /* Pick something reasonable. */
24664 }
24672 else
24675 }
24678 }
24680 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24681 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24682 static int
24686 machine_mode move_mode)
24687 {
24698 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24699 copying whole cacheline at once. */
24712 }
24715 /* Helper function for memcpy. For QImode value 0xXY produce
24716 0xXYXYXYXY of wide specified by MODE. This is essentially
24717 a * 0x10101010, but we can do slightly better than
24718 synth_mult by unwinding the sequence by hand on CPUs with
24719 slow multiply. */
24720 static rtx
24722 {
24724 rtx tmp;
24731 {
24739 }
24748 nops--;
24753 {
24757 OPTAB_DIRECT);
24758 }
24759 else
24760 {
24766 else
24768 else
24769 {
24772 reg =
24774 }
24784 }
24785 }
24787 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24788 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24789 alignment from ALIGN to DESIRED_ALIGN. */
24790 static rtx
24793 {
24794 rtx promoted_val;
24803 else
24807 }
24809 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24810 operations when profitable. The code depends upon architecture, block size
24811 and alignment, but always has one of the following overall structures:
24813 Aligned move sequence:
24815 1) Prologue guard: Conditional that jumps up to epilogues for small
24816 blocks that can be handled by epilogue alone. This is faster
24817 but also needed for correctness, since prologue assume the block
24818 is larger than the desired alignment.
24820 Optional dynamic check for size and libcall for large
24821 blocks is emitted here too, with -minline-stringops-dynamically.
24823 2) Prologue: copy first few bytes in order to get destination
24824 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24825 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24826 copied. We emit either a jump tree on power of two sized
24827 blocks, or a byte loop.
24829 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24830 with specified algorithm.
24832 4) Epilogue: code copying tail of the block that is too small to be
24833 handled by main body (or up to size guarded by prologue guard).
24835 Misaligned move sequence
24837 1) missaligned move prologue/epilogue containing:
24838 a) Prologue handling small memory blocks and jumping to done_label
24839 (skipped if blocks are known to be large enough)
24840 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24841 needed by single possibly misaligned move
24842 (skipped if alignment is not needed)
24843 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24845 2) Zero size guard dispatching to done_label, if needed
24847 3) dispatch to library call, if needed,
24849 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24850 with specified algorithm. */
24851 bool
24857 {
24858 rtx destreg;
24861 rtx tmp;
24877 /* TODO: Once value ranges are available, fill in proper data. */
24885 /* i386 can do misaligned access on reasonably increased cost. */
24889 /* ALIGN is the minimum of destination and source alignment, but we care here
24890 just about destination alignment. */
24896 {
24899 /* When COUNT is 0, there is nothing to do. */
24902 }
24903 else
24904 {
24913 }
24915 /* Make sure we don't need to care about overflow later on. */
24919 /* Step 0: Decide on preferred algorithm, desired alignment and
24920 size of chunks to be copied by main loop. */
24922 issetmem,
24929 /* For now vector-version of memset is generated only for memory zeroing, as
24930 creating of promoted vector value is very cheap in this case. */
24943 {
24962 /* Find the widest supported mode. */
24968 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24969 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24971 {
24976 }
24988 }
24996 /* Step 1: Prologue guard. */
24998 /* Alignment code needs count to be in register. */
25000 {
25003 {
25004 align_bytes
25008 else
25010 }
25013 }
25016 /* Misaligned move sequences handle both prologue and epilogue at once.
25017 Default code generation results in a smaller code for large alignments
25018 and also avoids redundant job when sizes are known precisely. */
25019 misaligned_prologue_used
25020 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
25026 /* Do the cheap promotion to allow better CSE across the
25027 main loop and epilogue (ie one load of the big constant in the
25028 front of all code.
25029 For now the misaligned move sequences do not have fast path
25030 without broadcasting. */
25032 {
25034 {
25040 }
25041 else
25042 {
25045 }
25046 }
25047 /* Misaligned move sequences handles both prologues and epilogues at once.
25048 Default code generation results in smaller code for large alignments and
25049 also avoids redundant job when sizes are known precisely. */
25051 {
25052 /* Misaligned move prologue handled small blocks by itself. */
25053 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
25058 desired_align < align
25067 {
25068 /* It is possible that we copied enough so the main loop will not
25069 execute. */
25079 else
25081 }
25082 }
25083 /* Ensure that alignment prologue won't copy past end of block. */
25085 {
25087 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
25088 Make sure it is power of 2. */
25091 /* To improve performance of small blocks, we jump around the VAL
25092 promoting mode. This mean that if the promoted VAL is not constant,
25093 we might not use it in the epilogue and have to use byte
25094 loop variant. */
25099 {
25100 /* If main algorithm works on QImode, no epilogue is needed.
25101 For small sizes just don't align anything. */
25104 else
25106 }
25109 {
25116 else
25118 }
25119 }
25121 /* Emit code to decide on runtime whether library call or inline should be
25122 used. */
25124 {
25126 {
25128 {
25132 }
25133 }
25134 else
25135 {
25145 else
25149 }
25150 }
25152 /* Step 2: Alignment prologue. */
25153 /* Do the expensive promotion once we branched off the small blocks. */
25159 {
25161 {
25162 /* Except for the first move in prologue, we no longer know
25163 constant offset in aliasing info. It don't seems to worth
25164 the pain to maintain it for the first move, so throw away
25165 the info early. */
25172 issetmem);
25173 /* At most desired_align - align bytes are copied. */
25176 else
25178 }
25179 else
25180 {
25181 /* If we know how many bytes need to be stored before dst is
25182 sufficiently aligned, maintain aliasing info accurately. */
25184 srcreg,
25185 promoted_val,
25186 vec_promoted_val,
25187 desired_align,
25188 align_bytes,
25189 issetmem);
25196 }
25198 && !min_size
25203 {
25204 /* It is possible that we copied enough so the main loop will not
25205 execute. */
25215 else
25217 }
25218 }
25220 {
25227 }
25231 /* Step 3: Main loop. */
25234 {
25257 }
25258 /* Adjust properly the offset of src and dest memory for aliasing. */
25260 {
25266 }
25267 else
25268 {
25272 }
25274 /* Step 4: Epilogue to copy the remaining bytes. */
25275 epilogue:
25277 {
25278 /* When the main loop is done, COUNT_EXP might hold original count,
25279 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25280 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25281 bytes. Compensate if needed. */
25284 {
25285 tmp =
25288 OPTAB_DIRECT);
25291 }
25294 }
25297 {
25300 epilogue_size_needed);
25301 else
25302 {
25306 epilogue_size_needed);
25307 else
25309 epilogue_size_needed);
25310 }
25311 }
25315 }
25318 /* Expand the appropriate insns for doing strlen if not just doing
25319 repnz; scasb
25321 out = result, initialized with the start address
25322 align_rtx = alignment of the address.
25323 scratch = scratch register, initialized with the startaddress when
25324 not aligned, otherwise undefined
25326 This is just the body. It needs the initializations mentioned above and
25327 some address computing at the end. These things are done in i386.md. */
25329 static void
25331 {
25333 rtx tmp;
25338 rtx mem;
25341 rtx cmp;
25347 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25349 /* Is there a known alignment and is it less than 4? */
25351 {
25354 /* Is there a known alignment and is it not 2? */
25356 {
25360 /* Leave just the 3 lower bits. */
25370 }
25371 else
25372 {
25373 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25374 check if is aligned to 4 - byte. */
25381 }
25385 /* Now compare the bytes. */
25387 /* Compare the first n unaligned byte on a byte per byte basis. */
25391 /* Increment the address. */
25394 /* Not needed with an alignment of 2 */
25396 {
25400 end_0_label);
25405 }
25408 end_0_label);
25411 }
25413 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25414 align this loop. It gives only huge programs, but does not help to
25415 speed up. */
25422 /* This formula yields a nonzero result iff one of the bytes is zero.
25423 This saves three branches inside loop and many cycles. */
25431 align_4_label);
25434 {
25440 /* If zero is not in the first two bytes, move two bytes forward. */
25446 reg,
25447 tmpreg)));
25448 /* Emit lea manually to avoid clobbering of flags. */
25455 reg2,
25456 out)));
25457 }
25458 else
25459 {
25461 /* Is zero in the first two bytes? */
25468 pc_rtx);
25472 /* Not in the first two. Move two bytes forward. */
25478 }
25480 /* Avoid branch in fixing the byte. */
25488 }
25490 /* Expand strlen. */
25492 bool
25494 {
25497 /* The generic case of strlen expander is long. Avoid it's
25498 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25501 && !TARGET_INLINE_ALL_STRINGOPS
25511 {
25512 /* Well it seems that some optimizer does not combine a call like
25513 foo(strlen(bar), strlen(bar));
25514 when the move and the subtraction is done here. It does calculate
25515 the length just once when these instructions are done inside of
25516 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25517 often used and I use one fewer register for the lifetime of
25518 output_strlen_unroll() this is better. */
25524 /* strlensi_unroll_1 returns the address of the zero at the end of
25525 the string, like memchr(), so compute the length by subtracting
25526 the start address. */
25528 }
25529 else
25530 {
25531 rtx unspec;
25533 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25546 /* If .md starts supporting :P, this can be done in .md. */
25552 }
25554 }
25556 /* For given symbol (function) construct code to compute address of it's PLT
25557 entry in large x86-64 PIC model. */
25558 static rtx
25560 {
25573 }
25575 rtx
25577 rtx callarg2,
25579 {
25589 {
25590 #if TARGET_MACHO
25593 #endif
25594 }
25595 else
25596 {
25597 /* Static functions and indirect calls don't need the pic register. Also,
25598 check if PLT was explicitly avoided via no-plt or "noplt" attribute, making
25599 it an indirect call. */
25601 && (!TARGET_64BIT
25606 && flag_plt
25610 {
25614 pic_offset_table_rtx);
25615 }
25616 }
25618 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25619 parameters passed in vector registers. */
25624 {
25628 }
25631 && !TARGET_PECOFF
25639 {
25642 }
25647 {
25648 /* We should add bounds as destination register in case
25649 pointer with bounds may be returned. */
25651 {
25655 {
25660 }
25661 else
25662 {
25666 }
25667 }
25670 }
25674 {
25678 }
25682 {
25683 int const cregs_size
25688 {
25693 }
25694 }
25703 }
25705 /* Return true if the function being called was marked with attribute "noplt"
25706 or using -fno-plt and we are compiling for non-PIC and x86_64. We need to
25707 handle the non-PIC case in the backend because there is no easy interface
25708 for the front-end to force non-PLT calls to use the GOT. This is currently
25709 used only with 64-bit ELF targets to call the function marked "noplt"
25710 indirectly. */
25712 static bool
25714 {
25728 }
25730 /* Output the assembly for a call instruction. */
25734 {
25740 {
25745 /* SEH epilogue detection requires the indirect branch case
25746 to include REX.W. */
25749 else
25754 }
25756 /* SEH unwinding can require an extra nop to be emitted in several
25757 circumstances. Determine if we have one of those. */
25759 {
25763 {
25764 /* If we get to another real insn, we don't need the nop. */
25768 /* If we get to the epilogue note, prevent a catch region from
25769 being adjacent to the standard epilogue sequence. If non-
25770 call-exceptions, we'll have done this during epilogue emission. */
25772 && !flag_non_call_exceptions
25774 {
25777 }
25778 }
25780 /* If we didn't find a real insn following the call, prevent the
25781 unwinder from looking into the next function. */
25784 }
25790 else
25799 }
25800 \f
25801 /* Clear stack slot assignments remembered from previous functions.
25802 This is called from INIT_EXPANDERS once before RTL is emitted for each
25803 function. */
25807 {
25815 }
25817 /* Return a MEM corresponding to a stack slot with mode MODE.
25818 Allocate a new slot if necessary.
25820 The RTL for a function can have several slots available: N is
25821 which slot to use. */
25823 rtx
25825 {
25842 }
25844 static void
25846 {
25852 }
25853 \f
25854 /* Check whether x86 address PARTS is a pc-relative address. */
25856 static bool
25858 {
25866 {
25868 {
25885 }
25886 }
25888 }
25890 /* Calculate the length of the memory address in the instruction encoding.
25891 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25892 or other prefixes. We never generate addr32 prefix for LEA insn. */
25894 int
25896 {
25913 /* If this is not LEA instruction, add the length of addr32 prefix. */
25918 len++;
25932 /* Rule of thumb:
25933 - esp as the base always wants an index,
25934 - ebp as the base always wants a displacement,
25935 - r12 as the base always wants an index,
25936 - r13 as the base always wants a displacement. */
25938 /* Register Indirect. */
25940 {
25941 /* esp (for its index) and ebp (for its displacement) need
25942 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25943 code. */
25950 len++;
25951 }
25953 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25954 is not disp32, but disp32(%rip), so for disp32
25955 SIB byte is needed, unless print_operand_address
25956 optimizes it into disp32(%rip) or (%rip) is implied
25957 by UNSPEC. */
25959 {
25962 len++;
25963 }
25964 else
25965 {
25966 /* Find the length of the displacement constant. */
25968 {
25971 else
25973 }
25974 /* ebp always wants a displacement. Similarly r13. */
25976 len++;
25978 /* An index requires the two-byte modrm form.... */
25980 /* ...like esp (or r12), which always wants an index. */
25984 len++;
25985 }
25988 }
25990 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25991 is set, expect that insn have 8bit immediate alternative. */
25992 int
25994 {
26000 {
26005 {
26008 {
26020 }
26022 {
26025 }
26026 }
26028 {
26038 /* Immediates for DImode instructions are encoded
26039 as 32bit sign extended values. */
26045 }
26046 }
26048 }
26050 /* Compute default value for "length_address" attribute. */
26051 int
26053 {
26057 {
26068 }
26073 {
26076 {
26081 constraints++;
26084 ;
26085 /* Skip ignored operands. */
26088 }
26090 }
26092 }
26094 /* Compute default value for "length_vex" attribute. It includes
26095 2 or 3 byte VEX prefix and 1 opcode byte. */
26097 int
26100 {
26103 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
26104 byte VEX prefix. */
26108 /* We can always use 2 byte VEX prefix in 32bit. */
26116 {
26117 /* REX.W bit uses 3 byte VEX prefix. */
26121 }
26122 else
26123 {
26124 /* REX.X or REX.B bits use 3 byte VEX prefix. */
26128 }
26131 }
26132 \f
26133 /* Return the maximum number of instructions a cpu can issue. */
26135 static int
26137 {
26139 {
26171 }
26172 }
26174 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26175 by DEP_INSN and nothing set by DEP_INSN. */
26177 static bool
26179 {
26182 /* Simplify the test for uninteresting insns. */
26190 {
26193 }
26198 {
26201 }
26202 else
26208 /* This test is true if the dependent insn reads the flags but
26209 not any other potentially set register. */
26217 }
26219 /* Return true iff USE_INSN has a memory address with operands set by
26220 SET_INSN. */
26222 bool
26224 {
26229 {
26232 }
26234 }
26236 /* Helper function for exact_store_load_dependency.
26237 Return true if addr is found in insn. */
26238 static bool
26240 {
26247 {
26253 CASE_CONST_ANY:
26262 }
26266 {
26268 {
26278 }
26279 }
26281 }
26283 /* Return true if there exists exact dependency for store & load, i.e.
26284 the same memory address is used in them. */
26285 static bool
26287 {
26301 }
26303 static int
26305 {
26311 /* Anti and output dependencies have zero cost on all CPUs. */
26317 /* If we can't recognize the insns, we can't really do anything. */
26325 {
26327 /* Address Generation Interlock adds a cycle of latency. */
26329 {
26340 }
26344 /* ??? Compares pair with jump/setcc. */
26348 /* Floating point stores require value to be ready one cycle earlier. */
26356 /* INT->FP conversion is expensive. */
26360 /* There is one cycle extra latency between an FP op and a store. */
26370 /* Show ability of reorder buffer to hide latency of load by executing
26371 in parallel with previous instruction in case
26372 previous instruction is not needed to compute the address. */
26375 {
26376 /* Claim moves to take one cycle, as core can issue one load
26377 at time and the next load can start cycle later. */
26382 cost--;
26383 }
26387 /* The esp dependency is resolved before
26388 the instruction is really finished. */
26393 /* INT->FP conversion is expensive. */
26399 /* Show ability of reorder buffer to hide latency of load by executing
26400 in parallel with previous instruction in case
26401 previous instruction is not needed to compute the address. */
26404 {
26405 /* Claim moves to take one cycle, as core can issue one load
26406 at time and the next load can start cycle later. */
26412 else
26414 }
26425 /* Stack engine allows to execute push&pop instructions in parall. */
26429 /* FALLTHRU */
26435 /* Show ability of reorder buffer to hide latency of load by executing
26436 in parallel with previous instruction in case
26437 previous instruction is not needed to compute the address. */
26440 {
26444 /* Because of the difference between the length of integer and
26445 floating unit pipeline preparation stages, the memory operands
26446 for floating point are cheaper.
26448 ??? For Athlon it the difference is most probably 2. */
26451 else
26456 else
26458 }
26465 /* Stack engine allows to execute push&pop instructions in parall. */
26472 /* Show ability of reorder buffer to hide latency of load by executing
26473 in parallel with previous instruction in case
26474 previous instruction is not needed to compute the address. */
26477 {
26480 else
26482 }
26491 /* Increase cost of integer loads. */
26494 {
26497 {
26500 else
26501 {
26502 /* Increase cost of ld/st for short int types only
26503 because of store forwarding issue. */
26507 {
26508 /* Increase cost of store/load insn if exact
26509 dependence exists and it is load insn. */
26514 }
26515 }
26516 }
26517 }
26521 }
26524 }
26526 /* How many alternative schedules to try. This should be as wide as the
26527 scheduling freedom in the DFA, but no wider. Making this value too
26528 large results extra work for the scheduler. */
26530 static int
26532 {
26534 {
26546 /* We use lookahead value 4 for BD both before and after reload
26547 schedules. Plan is to have value 8 included for O3. */
26558 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26559 as many instructions can be executed on a cycle, i.e.,
26560 issue_rate. I wonder why tuning for many CPUs does not do this. */
26563 /* Don't use lookahead for pre-reload schedule to save compile time. */
26568 }
26569 }
26571 /* Return true if target platform supports macro-fusion. */
26573 static bool
26575 {
26577 }
26579 /* Check whether current microarchitecture support macro fusion
26580 for insn pair "CONDGEN + CONDJMP". Refer to
26581 "Intel Architectures Optimization Reference Manual". */
26583 static bool
26585 {
26606 {
26611 {
26615 else
26617 }
26618 }
26625 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26626 supported. */
26633 /* No fusion for RIP-relative address. */
26640 ix86_address parts;
26646 }
26651 /* Check whether conditional jump use Sign or Overflow Flags. */
26659 /* Return true for TYPE_TEST and TYPE_ICMP. */
26664 /* The following is the case that macro-fusion for alu + jmp. */
26668 /* No fusion for alu op with memory destination operand. */
26673 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26674 supported. */
26683 }
26685 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26686 execution. It is applied if
26687 (1) IMUL instruction is on the top of list;
26688 (2) There exists the only producer of independent IMUL instruction in
26689 ready list.
26690 Return index of IMUL producer if it was found and -1 otherwise. */
26691 static int
26693 {
26696 sd_iterator_def sd_it;
26697 dep_t dep;
26704 /* Check that IMUL instruction is on the top of ready list. */
26713 /* Search for producer of independent IMUL instruction. */
26715 {
26719 /* Skip IMUL instruction. */
26729 {
26730 rtx con;
26741 {
26742 sd_iterator_def sd_it1;
26743 dep_t dep1;
26744 /* Check if there is no other dependee for IMUL. */
26747 {
26748 rtx pro;
26754 }
26757 }
26758 }
26761 }
26763 }
26765 /* Try to find the best candidate on the top of ready list if two insns
26766 have the same priority - candidate is best if its dependees were
26767 scheduled earlier. Applied for Silvermont only.
26768 Return true if top 2 insns must be interchanged. */
26769 static bool
26771 {
26774 rtx set;
26775 sd_iterator_def sd_it;
26776 dep_t dep;
26779 #define INSN_TICK(INSN) (HID (INSN)->tick)
26800 {
26803 /* Determine winner more precise. */
26805 {
26806 rtx pro;
26812 }
26814 {
26815 rtx pro;
26821 }
26824 {
26825 /* Determine winner - load must win. */
26831 }
26833 }
26835 #undef INSN_TICK
26836 }
26838 /* Perform possible reodering of ready list for Atom/Silvermont only.
26839 Return issue rate. */
26840 static int
26843 {
26850 /* Set up issue rate. */
26853 /* Do reodering for BONNELL/SILVERMONT only. */
26857 /* Nothing to do if ready list contains only 1 instruction. */
26861 /* Do reodering for post-reload scheduler only. */
26866 {
26871 /* Put IMUL producer (ready[index]) at the top of ready list. */
26877 }
26879 /* Skip selective scheduling since HID is not populated in it. */
26883 {
26887 /* Swap 2 top elements of ready list. */
26891 }
26893 }
26895 static bool
26898 /* Returns true if lhs of insn is HW function argument register and set up
26899 is_spilled to true if it is likely spilled HW register. */
26900 static bool
26902 {
26903 rtx dst;
26907 /* Call instructions are not movable, ignore it. */
26918 {
26919 /* Is it likely spilled HW register? */
26924 }
26926 }
26928 /* Add output dependencies for chain of function adjacent arguments if only
26929 there is a move to likely spilled HW register. Return first argument
26930 if at least one dependence was added or NULL otherwise. */
26933 {
26941 /* Find nearest to call argument passing instruction. */
26943 {
26952 }
26956 {
26963 {
26966 }
26968 {
26969 /* Add output depdendence between two function arguments if chain
26970 of output arguments contains likely spilled HW registers. */
26974 }
26975 else
26977 }
26981 }
26983 /* Add output or anti dependency from insn to first_arg to restrict its code
26984 motion. */
26985 static void
26987 {
26988 rtx set;
26989 rtx tmp;
26991 /* Add anti dependencies for bounds stores. */
26996 {
26999 }
27006 {
27007 /* Add output dependency to the first function argument. */
27010 }
27011 /* Add anti dependency. */
27013 }
27015 /* Avoid cross block motion of function argument through adding dependency
27016 from the first non-jump instruction in bb. */
27017 static void
27019 {
27023 {
27025 {
27028 {
27031 }
27032 }
27036 }
27037 }
27039 /* Hook for pre-reload schedule - avoid motion of function arguments
27040 passed in likely spilled HW registers. */
27041 static void
27043 {
27052 {
27055 {
27056 /* Add dependee for first argument to predecessors if only
27057 region contains more than one block. */
27061 /* Skip trivial regions and region head blocks that can have
27062 predecessors outside of region. */
27064 {
27065 edge e;
27066 edge_iterator ei;
27068 /* Regions are SCCs with the exception of selective
27069 scheduling with pipelining of outer blocks enabled.
27070 So also check that immediate predecessors of a non-head
27071 block are in the same region. */
27073 {
27074 /* Avoid creating of loop-carried dependencies through
27075 using topological ordering in the region. */
27079 }
27080 }
27084 }
27085 }
27088 }
27090 /* Hook for pre-reload schedule - set priority of moves from likely spilled
27091 HW registers to maximum, to schedule them at soon as possible. These are
27092 moves from function argument registers at the top of the function entry
27093 and moves from function return value registers after call. */
27094 static int
27096 {
27097 rtx set;
27107 {
27114 }
27117 }
27119 /* Model decoder of Core 2/i7.
27120 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
27121 track the instruction fetch block boundaries and make sure that long
27122 (9+ bytes) instructions are assigned to D0. */
27124 /* Maximum length of an insn that can be handled by
27125 a secondary decoder unit. '8' for Core 2/i7. */
27128 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
27129 '16' for Core 2/i7. */
27132 /* Maximum number of instructions decoder can handle per cycle.
27133 '6' for Core 2/i7. */
27137 ix86_first_cycle_multipass_data_t;
27139 const_ix86_first_cycle_multipass_data_t;
27141 /* A variable to store target state across calls to max_issue within
27142 one cycle. */
27146 /* Initialize DATA. */
27147 static void
27149 {
27150 ix86_first_cycle_multipass_data_t data
27157 }
27159 /* Advancing the cycle; reset ifetch block counts. */
27160 static void
27162 {
27169 }
27173 /* Filter out insns from ready_try that the core will not be able to issue
27174 on current cycle due to decoder. */
27175 static void
27176 core2i7_first_cycle_multipass_filter_ready_try
27179 {
27181 {
27192 (!first_cycle_insn_p
27194 /* ... or it would not fit into the ifetch block ... */
27196 /* ... or the decoder is full already ... */
27198 /* ... mask the insn out. */
27199 {
27204 }
27205 }
27206 }
27208 /* Prepare for a new round of multipass lookahead scheduling. */
27209 static void
27213 {
27214 ix86_first_cycle_multipass_data_t data
27216 const_ix86_first_cycle_multipass_data_t prev_data
27219 /* Restore the state from the end of the previous round. */
27223 /* Filter instructions that cannot be issued on current cycle due to
27224 decoder restrictions. */
27226 first_cycle_insn_p);
27227 }
27229 /* INSN is being issued in current solution. Account for its impact on
27230 the decoder model. */
27231 static void
27235 {
27236 ix86_first_cycle_multipass_data_t data
27238 const_ix86_first_cycle_multipass_data_t prev_data
27248 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27250 {
27253 }
27255 {
27259 }
27262 /* Filter out insns from ready_try that the core will not be able to issue
27263 on current cycle due to decoder. */
27266 }
27268 /* Revert the effect on ready_try. */
27269 static void
27273 {
27274 const_ix86_first_cycle_multipass_data_t data
27277 sbitmap_iterator sbi;
27281 {
27283 }
27284 }
27286 /* Save the result of multipass lookahead scheduling for the next round. */
27287 static void
27289 {
27290 const_ix86_first_cycle_multipass_data_t data
27292 ix86_first_cycle_multipass_data_t next_data
27296 {
27299 }
27300 }
27302 /* Deallocate target data. */
27303 static void
27305 {
27306 ix86_first_cycle_multipass_data_t data
27310 {
27314 }
27315 }
27317 /* Prepare for scheduling pass. */
27318 static void
27320 {
27321 /* Install scheduling hooks for current CPU. Some of these hooks are used
27322 in time-critical parts of the scheduler, so we only set them up when
27323 they are actually used. */
27325 {
27330 /* Do not perform multipass scheduling for pre-reload schedule
27331 to save compile time. */
27333 {
27349 /* Set decoder parameters. */
27354 }
27355 /* ... Fall through ... */
27365 }
27366 }
27368 \f
27369 /* Compute the alignment given to a constant that is being placed in memory.
27370 EXP is the constant and ALIGN is the alignment that the object would
27371 ordinarily have.
27372 The value of this function is used instead of that alignment to align
27373 the object. */
27375 int
27377 {
27380 {
27385 }
27391 }
27393 /* Compute the alignment for a variable for Intel MCU psABI. TYPE is
27394 the data type, and ALIGN is the alignment that the object would
27395 ordinarily have. */
27397 static int
27399 {
27405 /* Intel MCU psABI specifies scalar types > 4 bytes aligned to 4
27406 bytes. */
27409 {
27418 }
27419 }
27421 /* Compute the alignment for a static variable.
27422 TYPE is the data type, and ALIGN is the alignment that
27423 the object would ordinarily have. The value of this function is used
27424 instead of that alignment to align the object. */
27426 int
27428 {
27429 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27430 for symbols from other compilation units or symbols that don't need
27431 to bind locally. In order to preserve some ABI compatibility with
27432 those compilers, ensure we don't decrease alignment from what we
27433 used to assume. */
27437 /* A data structure, equal or greater than the size of a cache line
27438 (64 bytes in the Pentium 4 and other recent Intel processors, including
27439 processors based on Intel Core microarchitecture) should be aligned
27440 so that its base address is a multiple of a cache line size. */
27442 int max_align
27449 {
27453 }
27462 {
27469 }
27471 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27472 to 16byte boundary. */
27474 {
27481 }
27487 {
27492 }
27494 {
27501 }
27506 {
27511 }
27514 {
27519 }
27522 }
27524 /* Compute the alignment for a local variable or a stack slot. EXP is
27525 the data type or decl itself, MODE is the widest mode available and
27526 ALIGN is the alignment that the object would ordinarily have. The
27527 value of this macro is used instead of that alignment to align the
27528 object. */
27530 unsigned int
27533 {
27537 {
27540 }
27541 else
27542 {
27545 }
27547 /* Don't do dynamic stack realignment for long long objects with
27548 -mpreferred-stack-boundary=2. */
27557 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27558 register in MODE. We will return the largest alignment of XF
27559 and DF. */
27561 {
27565 }
27567 /* Don't increase alignment for Intel MCU psABI. */
27571 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27572 to 16byte boundary. Exact wording is:
27574 An array uses the same alignment as its elements, except that a local or
27575 global array variable of length at least 16 bytes or
27576 a C99 variable-length array variable always has alignment of at least 16 bytes.
27578 This was added to allow use of aligned SSE instructions at arrays. This
27579 rule is meant for static storage (where compiler can not do the analysis
27580 by itself). We follow it for automatic variables only when convenient.
27581 We fully control everything in the function compiled and functions from
27582 other unit can not rely on the alignment.
27584 Exclude va_list type. It is the common case of local array where
27585 we can not benefit from the alignment.
27587 TODO: Probably one should optimize for size only when var is not escaping. */
27590 {
27600 }
27602 {
27607 }
27609 {
27615 }
27620 {
27625 }
27628 {
27634 }
27636 }
27638 /* Compute the minimum required alignment for dynamic stack realignment
27639 purposes for a local variable, parameter or a stack slot. EXP is
27640 the data type or decl itself, MODE is its mode and ALIGN is the
27641 alignment that the object would ordinarily have. */
27643 unsigned int
27646 {
27650 {
27653 }
27654 else
27655 {
27658 }
27663 /* Don't do dynamic stack realignment for long long objects with
27664 -mpreferred-stack-boundary=2. */
27671 }
27672 \f
27673 /* Find a location for the static chain incoming to a nested function.
27674 This is a register, unless all free registers are used by arguments. */
27676 static rtx
27678 {
27681 /* While this function won't be called by the middle-end when a static
27682 chain isn't needed, it's also used throughout the backend so it's
27683 easiest to keep this check centralized. */
27688 {
27689 /* We always use R10 in 64-bit mode. */
27691 }
27692 else
27693 {
27697 /* By default in 32-bit mode we use ECX to pass the static chain. */
27701 {
27704 }
27705 else
27706 {
27709 }
27713 {
27714 /* Fastcall functions use ecx/edx for arguments, which leaves
27715 us with EAX for the static chain.
27716 Thiscall functions use ecx for arguments, which also
27717 leaves us with EAX for the static chain. */
27719 }
27721 {
27722 /* Thiscall functions use ecx for arguments, which leaves
27723 us with EAX and EDX for the static chain.
27724 We are using for abi-compatibility EAX. */
27726 }
27728 {
27729 /* For regparm 3, we have no free call-clobbered registers in
27730 which to store the static chain. In order to implement this,
27731 we have the trampoline push the static chain to the stack.
27732 However, we can't push a value below the return address when
27733 we call the nested function directly, so we have to use an
27734 alternate entry point. For this we use ESI, and have the
27735 alternate entry point push ESI, so that things appear the
27736 same once we're executing the nested function. */
27738 {
27744 }
27746 }
27747 }
27750 }
27752 /* Emit RTL insns to initialize the variable parts of a trampoline.
27753 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27754 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27755 to be passed to the target function. */
27757 static void
27759 {
27767 {
27770 /* Load the function address to r11. Try to load address using
27771 the shorter movl instead of movabs. We may want to support
27772 movq for kernel mode, but kernel does not use trampolines at
27773 the moment. FNADDR is a 32bit address and may not be in
27774 DImode when ptr_mode == SImode. Always use movl in this
27775 case. */
27778 {
27787 }
27788 else
27789 {
27796 }
27798 /* Load static chain using movabs to r10. Use the shorter movl
27799 instead of movabs when ptr_mode == SImode. */
27801 {
27804 }
27805 else
27806 {
27809 }
27818 /* Jump to r11; the last (unused) byte is a nop, only there to
27819 pad the write out to a single 32-bit store. */
27823 }
27824 else
27825 {
27828 /* Depending on the static chain location, either load a register
27829 with a constant, or push the constant to the stack. All of the
27830 instructions are the same size. */
27833 {
27835 {
27842 }
27843 }
27844 else
27859 /* Compute offset from the end of the jmp to the target function.
27860 In the case in which the trampoline stores the static chain on
27861 the stack, we need to skip the first insn which pushes the
27862 (call-saved) register static chain; this push is 1 byte. */
27869 }
27873 #ifdef HAVE_ENABLE_EXECUTE_STACK
27874 #ifdef CHECK_EXECUTE_STACK_ENABLED
27876 #endif
27879 #endif
27880 }
27881 \f
27882 /* The following file contains several enumerations and data structures
27883 built from the definitions in i386-builtin-types.def. */
27887 /* Table for the ix86 builtin non-function types. */
27890 /* Retrieve an element from the above table, building some of
27891 the types lazily. */
27893 static tree
27895 {
27907 {
27908 machine_mode mode;
27915 }
27916 else
27917 {
27923 else
27931 }
27935 }
27937 /* Table for the ix86 builtin function types. */
27940 /* Retrieve an element from the above table, building some of
27941 the types lazily. */
27943 static tree
27945 {
27946 tree type;
27955 {
27963 {
27966 }
27969 }
27970 else
27971 {
27977 }
27981 }
27984 /* Codes for all the SSE/MMX builtins. */
27985 enum ix86_builtins
27986 {
27987 IX86_BUILTIN_ADDPS,
27988 IX86_BUILTIN_ADDSS,
27989 IX86_BUILTIN_DIVPS,
27990 IX86_BUILTIN_DIVSS,
27991 IX86_BUILTIN_MULPS,
27992 IX86_BUILTIN_MULSS,
27993 IX86_BUILTIN_SUBPS,
27994 IX86_BUILTIN_SUBSS,
27996 IX86_BUILTIN_CMPEQPS,
27997 IX86_BUILTIN_CMPLTPS,
27998 IX86_BUILTIN_CMPLEPS,
27999 IX86_BUILTIN_CMPGTPS,
28000 IX86_BUILTIN_CMPGEPS,
28001 IX86_BUILTIN_CMPNEQPS,
28002 IX86_BUILTIN_CMPNLTPS,
28003 IX86_BUILTIN_CMPNLEPS,
28004 IX86_BUILTIN_CMPNGTPS,
28005 IX86_BUILTIN_CMPNGEPS,
28006 IX86_BUILTIN_CMPORDPS,
28007 IX86_BUILTIN_CMPUNORDPS,
28008 IX86_BUILTIN_CMPEQSS,
28009 IX86_BUILTIN_CMPLTSS,
28010 IX86_BUILTIN_CMPLESS,
28011 IX86_BUILTIN_CMPNEQSS,
28012 IX86_BUILTIN_CMPNLTSS,
28013 IX86_BUILTIN_CMPNLESS,
28014 IX86_BUILTIN_CMPORDSS,
28015 IX86_BUILTIN_CMPUNORDSS,
28017 IX86_BUILTIN_COMIEQSS,
28018 IX86_BUILTIN_COMILTSS,
28019 IX86_BUILTIN_COMILESS,
28020 IX86_BUILTIN_COMIGTSS,
28021 IX86_BUILTIN_COMIGESS,
28022 IX86_BUILTIN_COMINEQSS,
28023 IX86_BUILTIN_UCOMIEQSS,
28024 IX86_BUILTIN_UCOMILTSS,
28025 IX86_BUILTIN_UCOMILESS,
28026 IX86_BUILTIN_UCOMIGTSS,
28027 IX86_BUILTIN_UCOMIGESS,
28028 IX86_BUILTIN_UCOMINEQSS,
28030 IX86_BUILTIN_CVTPI2PS,
28031 IX86_BUILTIN_CVTPS2PI,
28032 IX86_BUILTIN_CVTSI2SS,
28033 IX86_BUILTIN_CVTSI642SS,
28034 IX86_BUILTIN_CVTSS2SI,
28035 IX86_BUILTIN_CVTSS2SI64,
28036 IX86_BUILTIN_CVTTPS2PI,
28037 IX86_BUILTIN_CVTTSS2SI,
28038 IX86_BUILTIN_CVTTSS2SI64,
28040 IX86_BUILTIN_MAXPS,
28041 IX86_BUILTIN_MAXSS,
28042 IX86_BUILTIN_MINPS,
28043 IX86_BUILTIN_MINSS,
28045 IX86_BUILTIN_LOADUPS,
28046 IX86_BUILTIN_STOREUPS,
28047 IX86_BUILTIN_MOVSS,
28049 IX86_BUILTIN_MOVHLPS,
28050 IX86_BUILTIN_MOVLHPS,
28051 IX86_BUILTIN_LOADHPS,
28052 IX86_BUILTIN_LOADLPS,
28053 IX86_BUILTIN_STOREHPS,
28054 IX86_BUILTIN_STORELPS,
28056 IX86_BUILTIN_MASKMOVQ,
28057 IX86_BUILTIN_MOVMSKPS,
28058 IX86_BUILTIN_PMOVMSKB,
28060 IX86_BUILTIN_MOVNTPS,
28061 IX86_BUILTIN_MOVNTQ,
28063 IX86_BUILTIN_LOADDQU,
28064 IX86_BUILTIN_STOREDQU,
28066 IX86_BUILTIN_PACKSSWB,
28067 IX86_BUILTIN_PACKSSDW,
28068 IX86_BUILTIN_PACKUSWB,
28070 IX86_BUILTIN_PADDB,
28071 IX86_BUILTIN_PADDW,
28072 IX86_BUILTIN_PADDD,
28073 IX86_BUILTIN_PADDQ,
28074 IX86_BUILTIN_PADDSB,
28075 IX86_BUILTIN_PADDSW,
28076 IX86_BUILTIN_PADDUSB,
28077 IX86_BUILTIN_PADDUSW,
28078 IX86_BUILTIN_PSUBB,
28079 IX86_BUILTIN_PSUBW,
28080 IX86_BUILTIN_PSUBD,
28081 IX86_BUILTIN_PSUBQ,
28082 IX86_BUILTIN_PSUBSB,
28083 IX86_BUILTIN_PSUBSW,
28084 IX86_BUILTIN_PSUBUSB,
28085 IX86_BUILTIN_PSUBUSW,
28087 IX86_BUILTIN_PAND,
28088 IX86_BUILTIN_PANDN,
28089 IX86_BUILTIN_POR,
28090 IX86_BUILTIN_PXOR,
28092 IX86_BUILTIN_PAVGB,
28093 IX86_BUILTIN_PAVGW,
28095 IX86_BUILTIN_PCMPEQB,
28096 IX86_BUILTIN_PCMPEQW,
28097 IX86_BUILTIN_PCMPEQD,
28098 IX86_BUILTIN_PCMPGTB,
28099 IX86_BUILTIN_PCMPGTW,
28100 IX86_BUILTIN_PCMPGTD,
28102 IX86_BUILTIN_PMADDWD,
28104 IX86_BUILTIN_PMAXSW,
28105 IX86_BUILTIN_PMAXUB,
28106 IX86_BUILTIN_PMINSW,
28107 IX86_BUILTIN_PMINUB,
28109 IX86_BUILTIN_PMULHUW,
28110 IX86_BUILTIN_PMULHW,
28111 IX86_BUILTIN_PMULLW,
28113 IX86_BUILTIN_PSADBW,
28114 IX86_BUILTIN_PSHUFW,
28116 IX86_BUILTIN_PSLLW,
28117 IX86_BUILTIN_PSLLD,
28118 IX86_BUILTIN_PSLLQ,
28119 IX86_BUILTIN_PSRAW,
28120 IX86_BUILTIN_PSRAD,
28121 IX86_BUILTIN_PSRLW,
28122 IX86_BUILTIN_PSRLD,
28123 IX86_BUILTIN_PSRLQ,
28124 IX86_BUILTIN_PSLLWI,
28125 IX86_BUILTIN_PSLLDI,
28126 IX86_BUILTIN_PSLLQI,
28127 IX86_BUILTIN_PSRAWI,
28128 IX86_BUILTIN_PSRADI,
28129 IX86_BUILTIN_PSRLWI,
28130 IX86_BUILTIN_PSRLDI,
28131 IX86_BUILTIN_PSRLQI,
28133 IX86_BUILTIN_PUNPCKHBW,
28134 IX86_BUILTIN_PUNPCKHWD,
28135 IX86_BUILTIN_PUNPCKHDQ,
28136 IX86_BUILTIN_PUNPCKLBW,
28137 IX86_BUILTIN_PUNPCKLWD,
28138 IX86_BUILTIN_PUNPCKLDQ,
28140 IX86_BUILTIN_SHUFPS,
28142 IX86_BUILTIN_RCPPS,
28143 IX86_BUILTIN_RCPSS,
28144 IX86_BUILTIN_RSQRTPS,
28145 IX86_BUILTIN_RSQRTPS_NR,
28146 IX86_BUILTIN_RSQRTSS,
28147 IX86_BUILTIN_RSQRTF,
28148 IX86_BUILTIN_SQRTPS,
28149 IX86_BUILTIN_SQRTPS_NR,
28150 IX86_BUILTIN_SQRTSS,
28152 IX86_BUILTIN_UNPCKHPS,
28153 IX86_BUILTIN_UNPCKLPS,
28155 IX86_BUILTIN_ANDPS,
28156 IX86_BUILTIN_ANDNPS,
28157 IX86_BUILTIN_ORPS,
28158 IX86_BUILTIN_XORPS,
28160 IX86_BUILTIN_EMMS,
28161 IX86_BUILTIN_LDMXCSR,
28162 IX86_BUILTIN_STMXCSR,
28163 IX86_BUILTIN_SFENCE,
28165 IX86_BUILTIN_FXSAVE,
28166 IX86_BUILTIN_FXRSTOR,
28167 IX86_BUILTIN_FXSAVE64,
28168 IX86_BUILTIN_FXRSTOR64,
28170 IX86_BUILTIN_XSAVE,
28171 IX86_BUILTIN_XRSTOR,
28172 IX86_BUILTIN_XSAVE64,
28173 IX86_BUILTIN_XRSTOR64,
28175 IX86_BUILTIN_XSAVEOPT,
28176 IX86_BUILTIN_XSAVEOPT64,
28178 IX86_BUILTIN_XSAVEC,
28179 IX86_BUILTIN_XSAVEC64,
28181 IX86_BUILTIN_XSAVES,
28182 IX86_BUILTIN_XRSTORS,
28183 IX86_BUILTIN_XSAVES64,
28184 IX86_BUILTIN_XRSTORS64,
28186 /* 3DNow! Original */
28187 IX86_BUILTIN_FEMMS,
28188 IX86_BUILTIN_PAVGUSB,
28189 IX86_BUILTIN_PF2ID,
28190 IX86_BUILTIN_PFACC,
28191 IX86_BUILTIN_PFADD,
28192 IX86_BUILTIN_PFCMPEQ,
28193 IX86_BUILTIN_PFCMPGE,
28194 IX86_BUILTIN_PFCMPGT,
28195 IX86_BUILTIN_PFMAX,
28196 IX86_BUILTIN_PFMIN,
28197 IX86_BUILTIN_PFMUL,
28198 IX86_BUILTIN_PFRCP,
28199 IX86_BUILTIN_PFRCPIT1,
28200 IX86_BUILTIN_PFRCPIT2,
28201 IX86_BUILTIN_PFRSQIT1,
28202 IX86_BUILTIN_PFRSQRT,
28203 IX86_BUILTIN_PFSUB,
28204 IX86_BUILTIN_PFSUBR,
28205 IX86_BUILTIN_PI2FD,
28206 IX86_BUILTIN_PMULHRW,
28208 /* 3DNow! Athlon Extensions */
28209 IX86_BUILTIN_PF2IW,
28210 IX86_BUILTIN_PFNACC,
28211 IX86_BUILTIN_PFPNACC,
28212 IX86_BUILTIN_PI2FW,
28213 IX86_BUILTIN_PSWAPDSI,
28214 IX86_BUILTIN_PSWAPDSF,
28216 /* SSE2 */
28217 IX86_BUILTIN_ADDPD,
28218 IX86_BUILTIN_ADDSD,
28219 IX86_BUILTIN_DIVPD,
28220 IX86_BUILTIN_DIVSD,
28221 IX86_BUILTIN_MULPD,
28222 IX86_BUILTIN_MULSD,
28223 IX86_BUILTIN_SUBPD,
28224 IX86_BUILTIN_SUBSD,
28226 IX86_BUILTIN_CMPEQPD,
28227 IX86_BUILTIN_CMPLTPD,
28228 IX86_BUILTIN_CMPLEPD,
28229 IX86_BUILTIN_CMPGTPD,
28230 IX86_BUILTIN_CMPGEPD,
28231 IX86_BUILTIN_CMPNEQPD,
28232 IX86_BUILTIN_CMPNLTPD,
28233 IX86_BUILTIN_CMPNLEPD,
28234 IX86_BUILTIN_CMPNGTPD,
28235 IX86_BUILTIN_CMPNGEPD,
28236 IX86_BUILTIN_CMPORDPD,
28237 IX86_BUILTIN_CMPUNORDPD,
28238 IX86_BUILTIN_CMPEQSD,
28239 IX86_BUILTIN_CMPLTSD,
28240 IX86_BUILTIN_CMPLESD,
28241 IX86_BUILTIN_CMPNEQSD,
28242 IX86_BUILTIN_CMPNLTSD,
28243 IX86_BUILTIN_CMPNLESD,
28244 IX86_BUILTIN_CMPORDSD,
28245 IX86_BUILTIN_CMPUNORDSD,
28247 IX86_BUILTIN_COMIEQSD,
28248 IX86_BUILTIN_COMILTSD,
28249 IX86_BUILTIN_COMILESD,
28250 IX86_BUILTIN_COMIGTSD,
28251 IX86_BUILTIN_COMIGESD,
28252 IX86_BUILTIN_COMINEQSD,
28253 IX86_BUILTIN_UCOMIEQSD,
28254 IX86_BUILTIN_UCOMILTSD,
28255 IX86_BUILTIN_UCOMILESD,
28256 IX86_BUILTIN_UCOMIGTSD,
28257 IX86_BUILTIN_UCOMIGESD,
28258 IX86_BUILTIN_UCOMINEQSD,
28260 IX86_BUILTIN_MAXPD,
28261 IX86_BUILTIN_MAXSD,
28262 IX86_BUILTIN_MINPD,
28263 IX86_BUILTIN_MINSD,
28265 IX86_BUILTIN_ANDPD,
28266 IX86_BUILTIN_ANDNPD,
28267 IX86_BUILTIN_ORPD,
28268 IX86_BUILTIN_XORPD,
28270 IX86_BUILTIN_SQRTPD,
28271 IX86_BUILTIN_SQRTSD,
28273 IX86_BUILTIN_UNPCKHPD,
28274 IX86_BUILTIN_UNPCKLPD,
28276 IX86_BUILTIN_SHUFPD,
28278 IX86_BUILTIN_LOADUPD,
28279 IX86_BUILTIN_STOREUPD,
28280 IX86_BUILTIN_MOVSD,
28282 IX86_BUILTIN_LOADHPD,
28283 IX86_BUILTIN_LOADLPD,
28285 IX86_BUILTIN_CVTDQ2PD,
28286 IX86_BUILTIN_CVTDQ2PS,
28288 IX86_BUILTIN_CVTPD2DQ,
28289 IX86_BUILTIN_CVTPD2PI,
28290 IX86_BUILTIN_CVTPD2PS,
28291 IX86_BUILTIN_CVTTPD2DQ,
28292 IX86_BUILTIN_CVTTPD2PI,
28294 IX86_BUILTIN_CVTPI2PD,
28295 IX86_BUILTIN_CVTSI2SD,
28296 IX86_BUILTIN_CVTSI642SD,
28298 IX86_BUILTIN_CVTSD2SI,
28299 IX86_BUILTIN_CVTSD2SI64,
28300 IX86_BUILTIN_CVTSD2SS,
28301 IX86_BUILTIN_CVTSS2SD,
28302 IX86_BUILTIN_CVTTSD2SI,
28303 IX86_BUILTIN_CVTTSD2SI64,
28305 IX86_BUILTIN_CVTPS2DQ,
28306 IX86_BUILTIN_CVTPS2PD,
28307 IX86_BUILTIN_CVTTPS2DQ,
28309 IX86_BUILTIN_MOVNTI,
28310 IX86_BUILTIN_MOVNTI64,
28311 IX86_BUILTIN_MOVNTPD,
28312 IX86_BUILTIN_MOVNTDQ,
28314 IX86_BUILTIN_MOVQ128,
28316 /* SSE2 MMX */
28317 IX86_BUILTIN_MASKMOVDQU,
28318 IX86_BUILTIN_MOVMSKPD,
28319 IX86_BUILTIN_PMOVMSKB128,
28321 IX86_BUILTIN_PACKSSWB128,
28322 IX86_BUILTIN_PACKSSDW128,
28323 IX86_BUILTIN_PACKUSWB128,
28325 IX86_BUILTIN_PADDB128,
28326 IX86_BUILTIN_PADDW128,
28327 IX86_BUILTIN_PADDD128,
28328 IX86_BUILTIN_PADDQ128,
28329 IX86_BUILTIN_PADDSB128,
28330 IX86_BUILTIN_PADDSW128,
28331 IX86_BUILTIN_PADDUSB128,
28332 IX86_BUILTIN_PADDUSW128,
28333 IX86_BUILTIN_PSUBB128,
28334 IX86_BUILTIN_PSUBW128,
28335 IX86_BUILTIN_PSUBD128,
28336 IX86_BUILTIN_PSUBQ128,
28337 IX86_BUILTIN_PSUBSB128,
28338 IX86_BUILTIN_PSUBSW128,
28339 IX86_BUILTIN_PSUBUSB128,
28340 IX86_BUILTIN_PSUBUSW128,
28342 IX86_BUILTIN_PAND128,
28343 IX86_BUILTIN_PANDN128,
28344 IX86_BUILTIN_POR128,
28345 IX86_BUILTIN_PXOR128,
28347 IX86_BUILTIN_PAVGB128,
28348 IX86_BUILTIN_PAVGW128,
28350 IX86_BUILTIN_PCMPEQB128,
28351 IX86_BUILTIN_PCMPEQW128,
28352 IX86_BUILTIN_PCMPEQD128,
28353 IX86_BUILTIN_PCMPGTB128,
28354 IX86_BUILTIN_PCMPGTW128,
28355 IX86_BUILTIN_PCMPGTD128,
28357 IX86_BUILTIN_PMADDWD128,
28359 IX86_BUILTIN_PMAXSW128,
28360 IX86_BUILTIN_PMAXUB128,
28361 IX86_BUILTIN_PMINSW128,
28362 IX86_BUILTIN_PMINUB128,
28364 IX86_BUILTIN_PMULUDQ,
28365 IX86_BUILTIN_PMULUDQ128,
28366 IX86_BUILTIN_PMULHUW128,
28367 IX86_BUILTIN_PMULHW128,
28368 IX86_BUILTIN_PMULLW128,
28370 IX86_BUILTIN_PSADBW128,
28371 IX86_BUILTIN_PSHUFHW,
28372 IX86_BUILTIN_PSHUFLW,
28373 IX86_BUILTIN_PSHUFD,
28375 IX86_BUILTIN_PSLLDQI128,
28376 IX86_BUILTIN_PSLLWI128,
28377 IX86_BUILTIN_PSLLDI128,
28378 IX86_BUILTIN_PSLLQI128,
28379 IX86_BUILTIN_PSRAWI128,
28380 IX86_BUILTIN_PSRADI128,
28381 IX86_BUILTIN_PSRLDQI128,
28382 IX86_BUILTIN_PSRLWI128,
28383 IX86_BUILTIN_PSRLDI128,
28384 IX86_BUILTIN_PSRLQI128,
28386 IX86_BUILTIN_PSLLDQ128,
28387 IX86_BUILTIN_PSLLW128,
28388 IX86_BUILTIN_PSLLD128,
28389 IX86_BUILTIN_PSLLQ128,
28390 IX86_BUILTIN_PSRAW128,
28391 IX86_BUILTIN_PSRAD128,
28392 IX86_BUILTIN_PSRLW128,
28393 IX86_BUILTIN_PSRLD128,
28394 IX86_BUILTIN_PSRLQ128,
28396 IX86_BUILTIN_PUNPCKHBW128,
28397 IX86_BUILTIN_PUNPCKHWD128,
28398 IX86_BUILTIN_PUNPCKHDQ128,
28399 IX86_BUILTIN_PUNPCKHQDQ128,
28400 IX86_BUILTIN_PUNPCKLBW128,
28401 IX86_BUILTIN_PUNPCKLWD128,
28402 IX86_BUILTIN_PUNPCKLDQ128,
28403 IX86_BUILTIN_PUNPCKLQDQ128,
28405 IX86_BUILTIN_CLFLUSH,
28406 IX86_BUILTIN_MFENCE,
28407 IX86_BUILTIN_LFENCE,
28408 IX86_BUILTIN_PAUSE,
28410 IX86_BUILTIN_FNSTENV,
28411 IX86_BUILTIN_FLDENV,
28412 IX86_BUILTIN_FNSTSW,
28413 IX86_BUILTIN_FNCLEX,
28415 IX86_BUILTIN_BSRSI,
28416 IX86_BUILTIN_BSRDI,
28417 IX86_BUILTIN_RDPMC,
28418 IX86_BUILTIN_RDTSC,
28419 IX86_BUILTIN_RDTSCP,
28420 IX86_BUILTIN_ROLQI,
28421 IX86_BUILTIN_ROLHI,
28422 IX86_BUILTIN_RORQI,
28423 IX86_BUILTIN_RORHI,
28425 /* SSE3. */
28426 IX86_BUILTIN_ADDSUBPS,
28427 IX86_BUILTIN_HADDPS,
28428 IX86_BUILTIN_HSUBPS,
28429 IX86_BUILTIN_MOVSHDUP,
28430 IX86_BUILTIN_MOVSLDUP,
28431 IX86_BUILTIN_ADDSUBPD,
28432 IX86_BUILTIN_HADDPD,
28433 IX86_BUILTIN_HSUBPD,
28434 IX86_BUILTIN_LDDQU,
28436 IX86_BUILTIN_MONITOR,
28437 IX86_BUILTIN_MWAIT,
28439 /* SSSE3. */
28440 IX86_BUILTIN_PHADDW,
28441 IX86_BUILTIN_PHADDD,
28442 IX86_BUILTIN_PHADDSW,
28443 IX86_BUILTIN_PHSUBW,
28444 IX86_BUILTIN_PHSUBD,
28445 IX86_BUILTIN_PHSUBSW,
28446 IX86_BUILTIN_PMADDUBSW,
28447 IX86_BUILTIN_PMULHRSW,
28448 IX86_BUILTIN_PSHUFB,
28449 IX86_BUILTIN_PSIGNB,
28450 IX86_BUILTIN_PSIGNW,
28451 IX86_BUILTIN_PSIGND,
28452 IX86_BUILTIN_PALIGNR,
28453 IX86_BUILTIN_PABSB,
28454 IX86_BUILTIN_PABSW,
28455 IX86_BUILTIN_PABSD,
28457 IX86_BUILTIN_PHADDW128,
28458 IX86_BUILTIN_PHADDD128,
28459 IX86_BUILTIN_PHADDSW128,
28460 IX86_BUILTIN_PHSUBW128,
28461 IX86_BUILTIN_PHSUBD128,
28462 IX86_BUILTIN_PHSUBSW128,
28463 IX86_BUILTIN_PMADDUBSW128,
28464 IX86_BUILTIN_PMULHRSW128,
28465 IX86_BUILTIN_PSHUFB128,
28466 IX86_BUILTIN_PSIGNB128,
28467 IX86_BUILTIN_PSIGNW128,
28468 IX86_BUILTIN_PSIGND128,
28469 IX86_BUILTIN_PALIGNR128,
28470 IX86_BUILTIN_PABSB128,
28471 IX86_BUILTIN_PABSW128,
28472 IX86_BUILTIN_PABSD128,
28474 /* AMDFAM10 - SSE4A New Instructions. */
28475 IX86_BUILTIN_MOVNTSD,
28476 IX86_BUILTIN_MOVNTSS,
28477 IX86_BUILTIN_EXTRQI,
28478 IX86_BUILTIN_EXTRQ,
28479 IX86_BUILTIN_INSERTQI,
28480 IX86_BUILTIN_INSERTQ,
28482 /* SSE4.1. */
28483 IX86_BUILTIN_BLENDPD,
28484 IX86_BUILTIN_BLENDPS,
28485 IX86_BUILTIN_BLENDVPD,
28486 IX86_BUILTIN_BLENDVPS,
28487 IX86_BUILTIN_PBLENDVB128,
28488 IX86_BUILTIN_PBLENDW128,
28490 IX86_BUILTIN_DPPD,
28491 IX86_BUILTIN_DPPS,
28493 IX86_BUILTIN_INSERTPS128,
28495 IX86_BUILTIN_MOVNTDQA,
28496 IX86_BUILTIN_MPSADBW128,
28497 IX86_BUILTIN_PACKUSDW128,
28498 IX86_BUILTIN_PCMPEQQ,
28499 IX86_BUILTIN_PHMINPOSUW128,
28501 IX86_BUILTIN_PMAXSB128,
28502 IX86_BUILTIN_PMAXSD128,
28503 IX86_BUILTIN_PMAXUD128,
28504 IX86_BUILTIN_PMAXUW128,
28506 IX86_BUILTIN_PMINSB128,
28507 IX86_BUILTIN_PMINSD128,
28508 IX86_BUILTIN_PMINUD128,
28509 IX86_BUILTIN_PMINUW128,
28511 IX86_BUILTIN_PMOVSXBW128,
28512 IX86_BUILTIN_PMOVSXBD128,
28513 IX86_BUILTIN_PMOVSXBQ128,
28514 IX86_BUILTIN_PMOVSXWD128,
28515 IX86_BUILTIN_PMOVSXWQ128,
28516 IX86_BUILTIN_PMOVSXDQ128,
28518 IX86_BUILTIN_PMOVZXBW128,
28519 IX86_BUILTIN_PMOVZXBD128,
28520 IX86_BUILTIN_PMOVZXBQ128,
28521 IX86_BUILTIN_PMOVZXWD128,
28522 IX86_BUILTIN_PMOVZXWQ128,
28523 IX86_BUILTIN_PMOVZXDQ128,
28525 IX86_BUILTIN_PMULDQ128,
28526 IX86_BUILTIN_PMULLD128,
28528 IX86_BUILTIN_ROUNDSD,
28529 IX86_BUILTIN_ROUNDSS,
28531 IX86_BUILTIN_ROUNDPD,
28532 IX86_BUILTIN_ROUNDPS,
28534 IX86_BUILTIN_FLOORPD,
28535 IX86_BUILTIN_CEILPD,
28536 IX86_BUILTIN_TRUNCPD,
28537 IX86_BUILTIN_RINTPD,
28538 IX86_BUILTIN_ROUNDPD_AZ,
28540 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28541 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28542 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28544 IX86_BUILTIN_FLOORPS,
28545 IX86_BUILTIN_CEILPS,
28546 IX86_BUILTIN_TRUNCPS,
28547 IX86_BUILTIN_RINTPS,
28548 IX86_BUILTIN_ROUNDPS_AZ,
28550 IX86_BUILTIN_FLOORPS_SFIX,
28551 IX86_BUILTIN_CEILPS_SFIX,
28552 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28554 IX86_BUILTIN_PTESTZ,
28555 IX86_BUILTIN_PTESTC,
28556 IX86_BUILTIN_PTESTNZC,
28558 IX86_BUILTIN_VEC_INIT_V2SI,
28559 IX86_BUILTIN_VEC_INIT_V4HI,
28560 IX86_BUILTIN_VEC_INIT_V8QI,
28561 IX86_BUILTIN_VEC_EXT_V2DF,
28562 IX86_BUILTIN_VEC_EXT_V2DI,
28563 IX86_BUILTIN_VEC_EXT_V4SF,
28564 IX86_BUILTIN_VEC_EXT_V4SI,
28565 IX86_BUILTIN_VEC_EXT_V8HI,
28566 IX86_BUILTIN_VEC_EXT_V2SI,
28567 IX86_BUILTIN_VEC_EXT_V4HI,
28568 IX86_BUILTIN_VEC_EXT_V16QI,
28569 IX86_BUILTIN_VEC_SET_V2DI,
28570 IX86_BUILTIN_VEC_SET_V4SF,
28571 IX86_BUILTIN_VEC_SET_V4SI,
28572 IX86_BUILTIN_VEC_SET_V8HI,
28573 IX86_BUILTIN_VEC_SET_V4HI,
28574 IX86_BUILTIN_VEC_SET_V16QI,
28576 IX86_BUILTIN_VEC_PACK_SFIX,
28577 IX86_BUILTIN_VEC_PACK_SFIX256,
28579 /* SSE4.2. */
28580 IX86_BUILTIN_CRC32QI,
28581 IX86_BUILTIN_CRC32HI,
28582 IX86_BUILTIN_CRC32SI,
28583 IX86_BUILTIN_CRC32DI,
28585 IX86_BUILTIN_PCMPESTRI128,
28586 IX86_BUILTIN_PCMPESTRM128,
28587 IX86_BUILTIN_PCMPESTRA128,
28588 IX86_BUILTIN_PCMPESTRC128,
28589 IX86_BUILTIN_PCMPESTRO128,
28590 IX86_BUILTIN_PCMPESTRS128,
28591 IX86_BUILTIN_PCMPESTRZ128,
28592 IX86_BUILTIN_PCMPISTRI128,
28593 IX86_BUILTIN_PCMPISTRM128,
28594 IX86_BUILTIN_PCMPISTRA128,
28595 IX86_BUILTIN_PCMPISTRC128,
28596 IX86_BUILTIN_PCMPISTRO128,
28597 IX86_BUILTIN_PCMPISTRS128,
28598 IX86_BUILTIN_PCMPISTRZ128,
28600 IX86_BUILTIN_PCMPGTQ,
28602 /* AES instructions */
28603 IX86_BUILTIN_AESENC128,
28604 IX86_BUILTIN_AESENCLAST128,
28605 IX86_BUILTIN_AESDEC128,
28606 IX86_BUILTIN_AESDECLAST128,
28607 IX86_BUILTIN_AESIMC128,
28608 IX86_BUILTIN_AESKEYGENASSIST128,
28610 /* PCLMUL instruction */
28611 IX86_BUILTIN_PCLMULQDQ128,
28613 /* AVX */
28614 IX86_BUILTIN_ADDPD256,
28615 IX86_BUILTIN_ADDPS256,
28616 IX86_BUILTIN_ADDSUBPD256,
28617 IX86_BUILTIN_ADDSUBPS256,
28618 IX86_BUILTIN_ANDPD256,
28619 IX86_BUILTIN_ANDPS256,
28620 IX86_BUILTIN_ANDNPD256,
28621 IX86_BUILTIN_ANDNPS256,
28622 IX86_BUILTIN_BLENDPD256,
28623 IX86_BUILTIN_BLENDPS256,
28624 IX86_BUILTIN_BLENDVPD256,
28625 IX86_BUILTIN_BLENDVPS256,
28626 IX86_BUILTIN_DIVPD256,
28627 IX86_BUILTIN_DIVPS256,
28628 IX86_BUILTIN_DPPS256,
28629 IX86_BUILTIN_HADDPD256,
28630 IX86_BUILTIN_HADDPS256,
28631 IX86_BUILTIN_HSUBPD256,
28632 IX86_BUILTIN_HSUBPS256,
28633 IX86_BUILTIN_MAXPD256,
28634 IX86_BUILTIN_MAXPS256,
28635 IX86_BUILTIN_MINPD256,
28636 IX86_BUILTIN_MINPS256,
28637 IX86_BUILTIN_MULPD256,
28638 IX86_BUILTIN_MULPS256,
28639 IX86_BUILTIN_ORPD256,
28640 IX86_BUILTIN_ORPS256,
28641 IX86_BUILTIN_SHUFPD256,
28642 IX86_BUILTIN_SHUFPS256,
28643 IX86_BUILTIN_SUBPD256,
28644 IX86_BUILTIN_SUBPS256,
28645 IX86_BUILTIN_XORPD256,
28646 IX86_BUILTIN_XORPS256,
28647 IX86_BUILTIN_CMPSD,
28648 IX86_BUILTIN_CMPSS,
28649 IX86_BUILTIN_CMPPD,
28650 IX86_BUILTIN_CMPPS,
28651 IX86_BUILTIN_CMPPD256,
28652 IX86_BUILTIN_CMPPS256,
28653 IX86_BUILTIN_CVTDQ2PD256,
28654 IX86_BUILTIN_CVTDQ2PS256,
28655 IX86_BUILTIN_CVTPD2PS256,
28656 IX86_BUILTIN_CVTPS2DQ256,
28657 IX86_BUILTIN_CVTPS2PD256,
28658 IX86_BUILTIN_CVTTPD2DQ256,
28659 IX86_BUILTIN_CVTPD2DQ256,
28660 IX86_BUILTIN_CVTTPS2DQ256,
28661 IX86_BUILTIN_EXTRACTF128PD256,
28662 IX86_BUILTIN_EXTRACTF128PS256,
28663 IX86_BUILTIN_EXTRACTF128SI256,
28664 IX86_BUILTIN_VZEROALL,
28665 IX86_BUILTIN_VZEROUPPER,
28666 IX86_BUILTIN_VPERMILVARPD,
28667 IX86_BUILTIN_VPERMILVARPS,
28668 IX86_BUILTIN_VPERMILVARPD256,
28669 IX86_BUILTIN_VPERMILVARPS256,
28670 IX86_BUILTIN_VPERMILPD,
28671 IX86_BUILTIN_VPERMILPS,
28672 IX86_BUILTIN_VPERMILPD256,
28673 IX86_BUILTIN_VPERMILPS256,
28674 IX86_BUILTIN_VPERMIL2PD,
28675 IX86_BUILTIN_VPERMIL2PS,
28676 IX86_BUILTIN_VPERMIL2PD256,
28677 IX86_BUILTIN_VPERMIL2PS256,
28678 IX86_BUILTIN_VPERM2F128PD256,
28679 IX86_BUILTIN_VPERM2F128PS256,
28680 IX86_BUILTIN_VPERM2F128SI256,
28681 IX86_BUILTIN_VBROADCASTSS,
28682 IX86_BUILTIN_VBROADCASTSD256,
28683 IX86_BUILTIN_VBROADCASTSS256,
28684 IX86_BUILTIN_VBROADCASTPD256,
28685 IX86_BUILTIN_VBROADCASTPS256,
28686 IX86_BUILTIN_VINSERTF128PD256,
28687 IX86_BUILTIN_VINSERTF128PS256,
28688 IX86_BUILTIN_VINSERTF128SI256,
28689 IX86_BUILTIN_LOADUPD256,
28690 IX86_BUILTIN_LOADUPS256,
28691 IX86_BUILTIN_STOREUPD256,
28692 IX86_BUILTIN_STOREUPS256,
28693 IX86_BUILTIN_LDDQU256,
28694 IX86_BUILTIN_MOVNTDQ256,
28695 IX86_BUILTIN_MOVNTPD256,
28696 IX86_BUILTIN_MOVNTPS256,
28697 IX86_BUILTIN_LOADDQU256,
28698 IX86_BUILTIN_STOREDQU256,
28699 IX86_BUILTIN_MASKLOADPD,
28700 IX86_BUILTIN_MASKLOADPS,
28701 IX86_BUILTIN_MASKSTOREPD,
28702 IX86_BUILTIN_MASKSTOREPS,
28703 IX86_BUILTIN_MASKLOADPD256,
28704 IX86_BUILTIN_MASKLOADPS256,
28705 IX86_BUILTIN_MASKSTOREPD256,
28706 IX86_BUILTIN_MASKSTOREPS256,
28707 IX86_BUILTIN_MOVSHDUP256,
28708 IX86_BUILTIN_MOVSLDUP256,
28709 IX86_BUILTIN_MOVDDUP256,
28711 IX86_BUILTIN_SQRTPD256,
28712 IX86_BUILTIN_SQRTPS256,
28713 IX86_BUILTIN_SQRTPS_NR256,
28714 IX86_BUILTIN_RSQRTPS256,
28715 IX86_BUILTIN_RSQRTPS_NR256,
28717 IX86_BUILTIN_RCPPS256,
28719 IX86_BUILTIN_ROUNDPD256,
28720 IX86_BUILTIN_ROUNDPS256,
28722 IX86_BUILTIN_FLOORPD256,
28723 IX86_BUILTIN_CEILPD256,
28724 IX86_BUILTIN_TRUNCPD256,
28725 IX86_BUILTIN_RINTPD256,
28726 IX86_BUILTIN_ROUNDPD_AZ256,
28728 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28729 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28730 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28732 IX86_BUILTIN_FLOORPS256,
28733 IX86_BUILTIN_CEILPS256,
28734 IX86_BUILTIN_TRUNCPS256,
28735 IX86_BUILTIN_RINTPS256,
28736 IX86_BUILTIN_ROUNDPS_AZ256,
28738 IX86_BUILTIN_FLOORPS_SFIX256,
28739 IX86_BUILTIN_CEILPS_SFIX256,
28740 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28742 IX86_BUILTIN_UNPCKHPD256,
28743 IX86_BUILTIN_UNPCKLPD256,
28744 IX86_BUILTIN_UNPCKHPS256,
28745 IX86_BUILTIN_UNPCKLPS256,
28747 IX86_BUILTIN_SI256_SI,
28748 IX86_BUILTIN_PS256_PS,
28749 IX86_BUILTIN_PD256_PD,
28750 IX86_BUILTIN_SI_SI256,
28751 IX86_BUILTIN_PS_PS256,
28752 IX86_BUILTIN_PD_PD256,
28754 IX86_BUILTIN_VTESTZPD,
28755 IX86_BUILTIN_VTESTCPD,
28756 IX86_BUILTIN_VTESTNZCPD,
28757 IX86_BUILTIN_VTESTZPS,
28758 IX86_BUILTIN_VTESTCPS,
28759 IX86_BUILTIN_VTESTNZCPS,
28760 IX86_BUILTIN_VTESTZPD256,
28761 IX86_BUILTIN_VTESTCPD256,
28762 IX86_BUILTIN_VTESTNZCPD256,
28763 IX86_BUILTIN_VTESTZPS256,
28764 IX86_BUILTIN_VTESTCPS256,
28765 IX86_BUILTIN_VTESTNZCPS256,
28766 IX86_BUILTIN_PTESTZ256,
28767 IX86_BUILTIN_PTESTC256,
28768 IX86_BUILTIN_PTESTNZC256,
28770 IX86_BUILTIN_MOVMSKPD256,
28771 IX86_BUILTIN_MOVMSKPS256,
28773 /* AVX2 */
28774 IX86_BUILTIN_MPSADBW256,
28775 IX86_BUILTIN_PABSB256,
28776 IX86_BUILTIN_PABSW256,
28777 IX86_BUILTIN_PABSD256,
28778 IX86_BUILTIN_PACKSSDW256,
28779 IX86_BUILTIN_PACKSSWB256,
28780 IX86_BUILTIN_PACKUSDW256,
28781 IX86_BUILTIN_PACKUSWB256,
28782 IX86_BUILTIN_PADDB256,
28783 IX86_BUILTIN_PADDW256,
28784 IX86_BUILTIN_PADDD256,
28785 IX86_BUILTIN_PADDQ256,
28786 IX86_BUILTIN_PADDSB256,
28787 IX86_BUILTIN_PADDSW256,
28788 IX86_BUILTIN_PADDUSB256,
28789 IX86_BUILTIN_PADDUSW256,
28790 IX86_BUILTIN_PALIGNR256,
28791 IX86_BUILTIN_AND256I,
28792 IX86_BUILTIN_ANDNOT256I,
28793 IX86_BUILTIN_PAVGB256,
28794 IX86_BUILTIN_PAVGW256,
28795 IX86_BUILTIN_PBLENDVB256,
28796 IX86_BUILTIN_PBLENDVW256,
28797 IX86_BUILTIN_PCMPEQB256,
28798 IX86_BUILTIN_PCMPEQW256,
28799 IX86_BUILTIN_PCMPEQD256,
28800 IX86_BUILTIN_PCMPEQQ256,
28801 IX86_BUILTIN_PCMPGTB256,
28802 IX86_BUILTIN_PCMPGTW256,
28803 IX86_BUILTIN_PCMPGTD256,
28804 IX86_BUILTIN_PCMPGTQ256,
28805 IX86_BUILTIN_PHADDW256,
28806 IX86_BUILTIN_PHADDD256,
28807 IX86_BUILTIN_PHADDSW256,
28808 IX86_BUILTIN_PHSUBW256,
28809 IX86_BUILTIN_PHSUBD256,
28810 IX86_BUILTIN_PHSUBSW256,
28811 IX86_BUILTIN_PMADDUBSW256,
28812 IX86_BUILTIN_PMADDWD256,
28813 IX86_BUILTIN_PMAXSB256,
28814 IX86_BUILTIN_PMAXSW256,
28815 IX86_BUILTIN_PMAXSD256,
28816 IX86_BUILTIN_PMAXUB256,
28817 IX86_BUILTIN_PMAXUW256,
28818 IX86_BUILTIN_PMAXUD256,
28819 IX86_BUILTIN_PMINSB256,
28820 IX86_BUILTIN_PMINSW256,
28821 IX86_BUILTIN_PMINSD256,
28822 IX86_BUILTIN_PMINUB256,
28823 IX86_BUILTIN_PMINUW256,
28824 IX86_BUILTIN_PMINUD256,
28825 IX86_BUILTIN_PMOVMSKB256,
28826 IX86_BUILTIN_PMOVSXBW256,
28827 IX86_BUILTIN_PMOVSXBD256,
28828 IX86_BUILTIN_PMOVSXBQ256,
28829 IX86_BUILTIN_PMOVSXWD256,
28830 IX86_BUILTIN_PMOVSXWQ256,
28831 IX86_BUILTIN_PMOVSXDQ256,
28832 IX86_BUILTIN_PMOVZXBW256,
28833 IX86_BUILTIN_PMOVZXBD256,
28834 IX86_BUILTIN_PMOVZXBQ256,
28835 IX86_BUILTIN_PMOVZXWD256,
28836 IX86_BUILTIN_PMOVZXWQ256,
28837 IX86_BUILTIN_PMOVZXDQ256,
28838 IX86_BUILTIN_PMULDQ256,
28839 IX86_BUILTIN_PMULHRSW256,
28840 IX86_BUILTIN_PMULHUW256,
28841 IX86_BUILTIN_PMULHW256,
28842 IX86_BUILTIN_PMULLW256,
28843 IX86_BUILTIN_PMULLD256,
28844 IX86_BUILTIN_PMULUDQ256,
28845 IX86_BUILTIN_POR256,
28846 IX86_BUILTIN_PSADBW256,
28847 IX86_BUILTIN_PSHUFB256,
28848 IX86_BUILTIN_PSHUFD256,
28849 IX86_BUILTIN_PSHUFHW256,
28850 IX86_BUILTIN_PSHUFLW256,
28851 IX86_BUILTIN_PSIGNB256,
28852 IX86_BUILTIN_PSIGNW256,
28853 IX86_BUILTIN_PSIGND256,
28854 IX86_BUILTIN_PSLLDQI256,
28855 IX86_BUILTIN_PSLLWI256,
28856 IX86_BUILTIN_PSLLW256,
28857 IX86_BUILTIN_PSLLDI256,
28858 IX86_BUILTIN_PSLLD256,
28859 IX86_BUILTIN_PSLLQI256,
28860 IX86_BUILTIN_PSLLQ256,
28861 IX86_BUILTIN_PSRAWI256,
28862 IX86_BUILTIN_PSRAW256,
28863 IX86_BUILTIN_PSRADI256,
28864 IX86_BUILTIN_PSRAD256,
28865 IX86_BUILTIN_PSRLDQI256,
28866 IX86_BUILTIN_PSRLWI256,
28867 IX86_BUILTIN_PSRLW256,
28868 IX86_BUILTIN_PSRLDI256,
28869 IX86_BUILTIN_PSRLD256,
28870 IX86_BUILTIN_PSRLQI256,
28871 IX86_BUILTIN_PSRLQ256,
28872 IX86_BUILTIN_PSUBB256,
28873 IX86_BUILTIN_PSUBW256,
28874 IX86_BUILTIN_PSUBD256,
28875 IX86_BUILTIN_PSUBQ256,
28876 IX86_BUILTIN_PSUBSB256,
28877 IX86_BUILTIN_PSUBSW256,
28878 IX86_BUILTIN_PSUBUSB256,
28879 IX86_BUILTIN_PSUBUSW256,
28880 IX86_BUILTIN_PUNPCKHBW256,
28881 IX86_BUILTIN_PUNPCKHWD256,
28882 IX86_BUILTIN_PUNPCKHDQ256,
28883 IX86_BUILTIN_PUNPCKHQDQ256,
28884 IX86_BUILTIN_PUNPCKLBW256,
28885 IX86_BUILTIN_PUNPCKLWD256,
28886 IX86_BUILTIN_PUNPCKLDQ256,
28887 IX86_BUILTIN_PUNPCKLQDQ256,
28888 IX86_BUILTIN_PXOR256,
28889 IX86_BUILTIN_MOVNTDQA256,
28890 IX86_BUILTIN_VBROADCASTSS_PS,
28891 IX86_BUILTIN_VBROADCASTSS_PS256,
28892 IX86_BUILTIN_VBROADCASTSD_PD256,
28893 IX86_BUILTIN_VBROADCASTSI256,
28894 IX86_BUILTIN_PBLENDD256,
28895 IX86_BUILTIN_PBLENDD128,
28896 IX86_BUILTIN_PBROADCASTB256,
28897 IX86_BUILTIN_PBROADCASTW256,
28898 IX86_BUILTIN_PBROADCASTD256,
28899 IX86_BUILTIN_PBROADCASTQ256,
28900 IX86_BUILTIN_PBROADCASTB128,
28901 IX86_BUILTIN_PBROADCASTW128,
28902 IX86_BUILTIN_PBROADCASTD128,
28903 IX86_BUILTIN_PBROADCASTQ128,
28904 IX86_BUILTIN_VPERMVARSI256,
28905 IX86_BUILTIN_VPERMDF256,
28906 IX86_BUILTIN_VPERMVARSF256,
28907 IX86_BUILTIN_VPERMDI256,
28908 IX86_BUILTIN_VPERMTI256,
28909 IX86_BUILTIN_VEXTRACT128I256,
28910 IX86_BUILTIN_VINSERT128I256,
28911 IX86_BUILTIN_MASKLOADD,
28912 IX86_BUILTIN_MASKLOADQ,
28913 IX86_BUILTIN_MASKLOADD256,
28914 IX86_BUILTIN_MASKLOADQ256,
28915 IX86_BUILTIN_MASKSTORED,
28916 IX86_BUILTIN_MASKSTOREQ,
28917 IX86_BUILTIN_MASKSTORED256,
28918 IX86_BUILTIN_MASKSTOREQ256,
28919 IX86_BUILTIN_PSLLVV4DI,
28920 IX86_BUILTIN_PSLLVV2DI,
28921 IX86_BUILTIN_PSLLVV8SI,
28922 IX86_BUILTIN_PSLLVV4SI,
28923 IX86_BUILTIN_PSRAVV8SI,
28924 IX86_BUILTIN_PSRAVV4SI,
28925 IX86_BUILTIN_PSRLVV4DI,
28926 IX86_BUILTIN_PSRLVV2DI,
28927 IX86_BUILTIN_PSRLVV8SI,
28928 IX86_BUILTIN_PSRLVV4SI,
28930 IX86_BUILTIN_GATHERSIV2DF,
28931 IX86_BUILTIN_GATHERSIV4DF,
28932 IX86_BUILTIN_GATHERDIV2DF,
28933 IX86_BUILTIN_GATHERDIV4DF,
28934 IX86_BUILTIN_GATHERSIV4SF,
28935 IX86_BUILTIN_GATHERSIV8SF,
28936 IX86_BUILTIN_GATHERDIV4SF,
28937 IX86_BUILTIN_GATHERDIV8SF,
28938 IX86_BUILTIN_GATHERSIV2DI,
28939 IX86_BUILTIN_GATHERSIV4DI,
28940 IX86_BUILTIN_GATHERDIV2DI,
28941 IX86_BUILTIN_GATHERDIV4DI,
28942 IX86_BUILTIN_GATHERSIV4SI,
28943 IX86_BUILTIN_GATHERSIV8SI,
28944 IX86_BUILTIN_GATHERDIV4SI,
28945 IX86_BUILTIN_GATHERDIV8SI,
28947 /* AVX512F */
28948 IX86_BUILTIN_SI512_SI256,
28949 IX86_BUILTIN_PD512_PD256,
28950 IX86_BUILTIN_PS512_PS256,
28951 IX86_BUILTIN_SI512_SI,
28952 IX86_BUILTIN_PD512_PD,
28953 IX86_BUILTIN_PS512_PS,
28954 IX86_BUILTIN_ADDPD512,
28955 IX86_BUILTIN_ADDPS512,
28956 IX86_BUILTIN_ADDSD_ROUND,
28957 IX86_BUILTIN_ADDSS_ROUND,
28958 IX86_BUILTIN_ALIGND512,
28959 IX86_BUILTIN_ALIGNQ512,
28960 IX86_BUILTIN_BLENDMD512,
28961 IX86_BUILTIN_BLENDMPD512,
28962 IX86_BUILTIN_BLENDMPS512,
28963 IX86_BUILTIN_BLENDMQ512,
28964 IX86_BUILTIN_BROADCASTF32X4_512,
28965 IX86_BUILTIN_BROADCASTF64X4_512,
28966 IX86_BUILTIN_BROADCASTI32X4_512,
28967 IX86_BUILTIN_BROADCASTI64X4_512,
28968 IX86_BUILTIN_BROADCASTSD512,
28969 IX86_BUILTIN_BROADCASTSS512,
28970 IX86_BUILTIN_CMPD512,
28971 IX86_BUILTIN_CMPPD512,
28972 IX86_BUILTIN_CMPPS512,
28973 IX86_BUILTIN_CMPQ512,
28974 IX86_BUILTIN_CMPSD_MASK,
28975 IX86_BUILTIN_CMPSS_MASK,
28976 IX86_BUILTIN_COMIDF,
28977 IX86_BUILTIN_COMISF,
28978 IX86_BUILTIN_COMPRESSPD512,
28979 IX86_BUILTIN_COMPRESSPDSTORE512,
28980 IX86_BUILTIN_COMPRESSPS512,
28981 IX86_BUILTIN_COMPRESSPSSTORE512,
28982 IX86_BUILTIN_CVTDQ2PD512,
28983 IX86_BUILTIN_CVTDQ2PS512,
28984 IX86_BUILTIN_CVTPD2DQ512,
28985 IX86_BUILTIN_CVTPD2PS512,
28986 IX86_BUILTIN_CVTPD2UDQ512,
28987 IX86_BUILTIN_CVTPH2PS512,
28988 IX86_BUILTIN_CVTPS2DQ512,
28989 IX86_BUILTIN_CVTPS2PD512,
28990 IX86_BUILTIN_CVTPS2PH512,
28991 IX86_BUILTIN_CVTPS2UDQ512,
28992 IX86_BUILTIN_CVTSD2SS_ROUND,
28993 IX86_BUILTIN_CVTSI2SD64,
28994 IX86_BUILTIN_CVTSI2SS32,
28995 IX86_BUILTIN_CVTSI2SS64,
28996 IX86_BUILTIN_CVTSS2SD_ROUND,
28997 IX86_BUILTIN_CVTTPD2DQ512,
28998 IX86_BUILTIN_CVTTPD2UDQ512,
28999 IX86_BUILTIN_CVTTPS2DQ512,
29000 IX86_BUILTIN_CVTTPS2UDQ512,
29001 IX86_BUILTIN_CVTUDQ2PD512,
29002 IX86_BUILTIN_CVTUDQ2PS512,
29003 IX86_BUILTIN_CVTUSI2SD32,
29004 IX86_BUILTIN_CVTUSI2SD64,
29005 IX86_BUILTIN_CVTUSI2SS32,
29006 IX86_BUILTIN_CVTUSI2SS64,
29007 IX86_BUILTIN_DIVPD512,
29008 IX86_BUILTIN_DIVPS512,
29009 IX86_BUILTIN_DIVSD_ROUND,
29010 IX86_BUILTIN_DIVSS_ROUND,
29011 IX86_BUILTIN_EXPANDPD512,
29012 IX86_BUILTIN_EXPANDPD512Z,
29013 IX86_BUILTIN_EXPANDPDLOAD512,
29014 IX86_BUILTIN_EXPANDPDLOAD512Z,
29015 IX86_BUILTIN_EXPANDPS512,
29016 IX86_BUILTIN_EXPANDPS512Z,
29017 IX86_BUILTIN_EXPANDPSLOAD512,
29018 IX86_BUILTIN_EXPANDPSLOAD512Z,
29019 IX86_BUILTIN_EXTRACTF32X4,
29020 IX86_BUILTIN_EXTRACTF64X4,
29021 IX86_BUILTIN_EXTRACTI32X4,
29022 IX86_BUILTIN_EXTRACTI64X4,
29023 IX86_BUILTIN_FIXUPIMMPD512_MASK,
29024 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
29025 IX86_BUILTIN_FIXUPIMMPS512_MASK,
29026 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
29027 IX86_BUILTIN_FIXUPIMMSD128_MASK,
29028 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
29029 IX86_BUILTIN_FIXUPIMMSS128_MASK,
29030 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
29031 IX86_BUILTIN_GETEXPPD512,
29032 IX86_BUILTIN_GETEXPPS512,
29033 IX86_BUILTIN_GETEXPSD128,
29034 IX86_BUILTIN_GETEXPSS128,
29035 IX86_BUILTIN_GETMANTPD512,
29036 IX86_BUILTIN_GETMANTPS512,
29037 IX86_BUILTIN_GETMANTSD128,
29038 IX86_BUILTIN_GETMANTSS128,
29039 IX86_BUILTIN_INSERTF32X4,
29040 IX86_BUILTIN_INSERTF64X4,
29041 IX86_BUILTIN_INSERTI32X4,
29042 IX86_BUILTIN_INSERTI64X4,
29043 IX86_BUILTIN_LOADAPD512,
29044 IX86_BUILTIN_LOADAPS512,
29045 IX86_BUILTIN_LOADDQUDI512,
29046 IX86_BUILTIN_LOADDQUSI512,
29047 IX86_BUILTIN_LOADUPD512,
29048 IX86_BUILTIN_LOADUPS512,
29049 IX86_BUILTIN_MAXPD512,
29050 IX86_BUILTIN_MAXPS512,
29051 IX86_BUILTIN_MAXSD_ROUND,
29052 IX86_BUILTIN_MAXSS_ROUND,
29053 IX86_BUILTIN_MINPD512,
29054 IX86_BUILTIN_MINPS512,
29055 IX86_BUILTIN_MINSD_ROUND,
29056 IX86_BUILTIN_MINSS_ROUND,
29057 IX86_BUILTIN_MOVAPD512,
29058 IX86_BUILTIN_MOVAPS512,
29059 IX86_BUILTIN_MOVDDUP512,
29060 IX86_BUILTIN_MOVDQA32LOAD512,
29061 IX86_BUILTIN_MOVDQA32STORE512,
29062 IX86_BUILTIN_MOVDQA32_512,
29063 IX86_BUILTIN_MOVDQA64LOAD512,
29064 IX86_BUILTIN_MOVDQA64STORE512,
29065 IX86_BUILTIN_MOVDQA64_512,
29066 IX86_BUILTIN_MOVNTDQ512,
29067 IX86_BUILTIN_MOVNTDQA512,
29068 IX86_BUILTIN_MOVNTPD512,
29069 IX86_BUILTIN_MOVNTPS512,
29070 IX86_BUILTIN_MOVSHDUP512,
29071 IX86_BUILTIN_MOVSLDUP512,
29072 IX86_BUILTIN_MULPD512,
29073 IX86_BUILTIN_MULPS512,
29074 IX86_BUILTIN_MULSD_ROUND,
29075 IX86_BUILTIN_MULSS_ROUND,
29076 IX86_BUILTIN_PABSD512,
29077 IX86_BUILTIN_PABSQ512,
29078 IX86_BUILTIN_PADDD512,
29079 IX86_BUILTIN_PADDQ512,
29080 IX86_BUILTIN_PANDD512,
29081 IX86_BUILTIN_PANDND512,
29082 IX86_BUILTIN_PANDNQ512,
29083 IX86_BUILTIN_PANDQ512,
29084 IX86_BUILTIN_PBROADCASTD512,
29085 IX86_BUILTIN_PBROADCASTD512_GPR,
29086 IX86_BUILTIN_PBROADCASTMB512,
29087 IX86_BUILTIN_PBROADCASTMW512,
29088 IX86_BUILTIN_PBROADCASTQ512,
29089 IX86_BUILTIN_PBROADCASTQ512_GPR,
29090 IX86_BUILTIN_PCMPEQD512_MASK,
29091 IX86_BUILTIN_PCMPEQQ512_MASK,
29092 IX86_BUILTIN_PCMPGTD512_MASK,
29093 IX86_BUILTIN_PCMPGTQ512_MASK,
29094 IX86_BUILTIN_PCOMPRESSD512,
29095 IX86_BUILTIN_PCOMPRESSDSTORE512,
29096 IX86_BUILTIN_PCOMPRESSQ512,
29097 IX86_BUILTIN_PCOMPRESSQSTORE512,
29098 IX86_BUILTIN_PEXPANDD512,
29099 IX86_BUILTIN_PEXPANDD512Z,
29100 IX86_BUILTIN_PEXPANDDLOAD512,
29101 IX86_BUILTIN_PEXPANDDLOAD512Z,
29102 IX86_BUILTIN_PEXPANDQ512,
29103 IX86_BUILTIN_PEXPANDQ512Z,
29104 IX86_BUILTIN_PEXPANDQLOAD512,
29105 IX86_BUILTIN_PEXPANDQLOAD512Z,
29106 IX86_BUILTIN_PMAXSD512,
29107 IX86_BUILTIN_PMAXSQ512,
29108 IX86_BUILTIN_PMAXUD512,
29109 IX86_BUILTIN_PMAXUQ512,
29110 IX86_BUILTIN_PMINSD512,
29111 IX86_BUILTIN_PMINSQ512,
29112 IX86_BUILTIN_PMINUD512,
29113 IX86_BUILTIN_PMINUQ512,
29114 IX86_BUILTIN_PMOVDB512,
29115 IX86_BUILTIN_PMOVDB512_MEM,
29116 IX86_BUILTIN_PMOVDW512,
29117 IX86_BUILTIN_PMOVDW512_MEM,
29118 IX86_BUILTIN_PMOVQB512,
29119 IX86_BUILTIN_PMOVQB512_MEM,
29120 IX86_BUILTIN_PMOVQD512,
29121 IX86_BUILTIN_PMOVQD512_MEM,
29122 IX86_BUILTIN_PMOVQW512,
29123 IX86_BUILTIN_PMOVQW512_MEM,
29124 IX86_BUILTIN_PMOVSDB512,
29125 IX86_BUILTIN_PMOVSDB512_MEM,
29126 IX86_BUILTIN_PMOVSDW512,
29127 IX86_BUILTIN_PMOVSDW512_MEM,
29128 IX86_BUILTIN_PMOVSQB512,
29129 IX86_BUILTIN_PMOVSQB512_MEM,
29130 IX86_BUILTIN_PMOVSQD512,
29131 IX86_BUILTIN_PMOVSQD512_MEM,
29132 IX86_BUILTIN_PMOVSQW512,
29133 IX86_BUILTIN_PMOVSQW512_MEM,
29134 IX86_BUILTIN_PMOVSXBD512,
29135 IX86_BUILTIN_PMOVSXBQ512,
29136 IX86_BUILTIN_PMOVSXDQ512,
29137 IX86_BUILTIN_PMOVSXWD512,
29138 IX86_BUILTIN_PMOVSXWQ512,
29139 IX86_BUILTIN_PMOVUSDB512,
29140 IX86_BUILTIN_PMOVUSDB512_MEM,
29141 IX86_BUILTIN_PMOVUSDW512,
29142 IX86_BUILTIN_PMOVUSDW512_MEM,
29143 IX86_BUILTIN_PMOVUSQB512,
29144 IX86_BUILTIN_PMOVUSQB512_MEM,
29145 IX86_BUILTIN_PMOVUSQD512,
29146 IX86_BUILTIN_PMOVUSQD512_MEM,
29147 IX86_BUILTIN_PMOVUSQW512,
29148 IX86_BUILTIN_PMOVUSQW512_MEM,
29149 IX86_BUILTIN_PMOVZXBD512,
29150 IX86_BUILTIN_PMOVZXBQ512,
29151 IX86_BUILTIN_PMOVZXDQ512,
29152 IX86_BUILTIN_PMOVZXWD512,
29153 IX86_BUILTIN_PMOVZXWQ512,
29154 IX86_BUILTIN_PMULDQ512,
29155 IX86_BUILTIN_PMULLD512,
29156 IX86_BUILTIN_PMULUDQ512,
29157 IX86_BUILTIN_PORD512,
29158 IX86_BUILTIN_PORQ512,
29159 IX86_BUILTIN_PROLD512,
29160 IX86_BUILTIN_PROLQ512,
29161 IX86_BUILTIN_PROLVD512,
29162 IX86_BUILTIN_PROLVQ512,
29163 IX86_BUILTIN_PRORD512,
29164 IX86_BUILTIN_PRORQ512,
29165 IX86_BUILTIN_PRORVD512,
29166 IX86_BUILTIN_PRORVQ512,
29167 IX86_BUILTIN_PSHUFD512,
29168 IX86_BUILTIN_PSLLD512,
29169 IX86_BUILTIN_PSLLDI512,
29170 IX86_BUILTIN_PSLLQ512,
29171 IX86_BUILTIN_PSLLQI512,
29172 IX86_BUILTIN_PSLLVV16SI,
29173 IX86_BUILTIN_PSLLVV8DI,
29174 IX86_BUILTIN_PSRAD512,
29175 IX86_BUILTIN_PSRADI512,
29176 IX86_BUILTIN_PSRAQ512,
29177 IX86_BUILTIN_PSRAQI512,
29178 IX86_BUILTIN_PSRAVV16SI,
29179 IX86_BUILTIN_PSRAVV8DI,
29180 IX86_BUILTIN_PSRLD512,
29181 IX86_BUILTIN_PSRLDI512,
29182 IX86_BUILTIN_PSRLQ512,
29183 IX86_BUILTIN_PSRLQI512,
29184 IX86_BUILTIN_PSRLVV16SI,
29185 IX86_BUILTIN_PSRLVV8DI,
29186 IX86_BUILTIN_PSUBD512,
29187 IX86_BUILTIN_PSUBQ512,
29188 IX86_BUILTIN_PTESTMD512,
29189 IX86_BUILTIN_PTESTMQ512,
29190 IX86_BUILTIN_PTESTNMD512,
29191 IX86_BUILTIN_PTESTNMQ512,
29192 IX86_BUILTIN_PUNPCKHDQ512,
29193 IX86_BUILTIN_PUNPCKHQDQ512,
29194 IX86_BUILTIN_PUNPCKLDQ512,
29195 IX86_BUILTIN_PUNPCKLQDQ512,
29196 IX86_BUILTIN_PXORD512,
29197 IX86_BUILTIN_PXORQ512,
29198 IX86_BUILTIN_RCP14PD512,
29199 IX86_BUILTIN_RCP14PS512,
29200 IX86_BUILTIN_RCP14SD,
29201 IX86_BUILTIN_RCP14SS,
29202 IX86_BUILTIN_RNDSCALEPD,
29203 IX86_BUILTIN_RNDSCALEPS,
29204 IX86_BUILTIN_RNDSCALESD,
29205 IX86_BUILTIN_RNDSCALESS,
29206 IX86_BUILTIN_RSQRT14PD512,
29207 IX86_BUILTIN_RSQRT14PS512,
29208 IX86_BUILTIN_RSQRT14SD,
29209 IX86_BUILTIN_RSQRT14SS,
29210 IX86_BUILTIN_SCALEFPD512,
29211 IX86_BUILTIN_SCALEFPS512,
29212 IX86_BUILTIN_SCALEFSD,
29213 IX86_BUILTIN_SCALEFSS,
29214 IX86_BUILTIN_SHUFPD512,
29215 IX86_BUILTIN_SHUFPS512,
29216 IX86_BUILTIN_SHUF_F32x4,
29217 IX86_BUILTIN_SHUF_F64x2,
29218 IX86_BUILTIN_SHUF_I32x4,
29219 IX86_BUILTIN_SHUF_I64x2,
29220 IX86_BUILTIN_SQRTPD512,
29221 IX86_BUILTIN_SQRTPD512_MASK,
29222 IX86_BUILTIN_SQRTPS512_MASK,
29223 IX86_BUILTIN_SQRTPS_NR512,
29224 IX86_BUILTIN_SQRTSD_ROUND,
29225 IX86_BUILTIN_SQRTSS_ROUND,
29226 IX86_BUILTIN_STOREAPD512,
29227 IX86_BUILTIN_STOREAPS512,
29228 IX86_BUILTIN_STOREDQUDI512,
29229 IX86_BUILTIN_STOREDQUSI512,
29230 IX86_BUILTIN_STOREUPD512,
29231 IX86_BUILTIN_STOREUPS512,
29232 IX86_BUILTIN_SUBPD512,
29233 IX86_BUILTIN_SUBPS512,
29234 IX86_BUILTIN_SUBSD_ROUND,
29235 IX86_BUILTIN_SUBSS_ROUND,
29236 IX86_BUILTIN_UCMPD512,
29237 IX86_BUILTIN_UCMPQ512,
29238 IX86_BUILTIN_UNPCKHPD512,
29239 IX86_BUILTIN_UNPCKHPS512,
29240 IX86_BUILTIN_UNPCKLPD512,
29241 IX86_BUILTIN_UNPCKLPS512,
29242 IX86_BUILTIN_VCVTSD2SI32,
29243 IX86_BUILTIN_VCVTSD2SI64,
29244 IX86_BUILTIN_VCVTSD2USI32,
29245 IX86_BUILTIN_VCVTSD2USI64,
29246 IX86_BUILTIN_VCVTSS2SI32,
29247 IX86_BUILTIN_VCVTSS2SI64,
29248 IX86_BUILTIN_VCVTSS2USI32,
29249 IX86_BUILTIN_VCVTSS2USI64,
29250 IX86_BUILTIN_VCVTTSD2SI32,
29251 IX86_BUILTIN_VCVTTSD2SI64,
29252 IX86_BUILTIN_VCVTTSD2USI32,
29253 IX86_BUILTIN_VCVTTSD2USI64,
29254 IX86_BUILTIN_VCVTTSS2SI32,
29255 IX86_BUILTIN_VCVTTSS2SI64,
29256 IX86_BUILTIN_VCVTTSS2USI32,
29257 IX86_BUILTIN_VCVTTSS2USI64,
29258 IX86_BUILTIN_VFMADDPD512_MASK,
29259 IX86_BUILTIN_VFMADDPD512_MASK3,
29260 IX86_BUILTIN_VFMADDPD512_MASKZ,
29261 IX86_BUILTIN_VFMADDPS512_MASK,
29262 IX86_BUILTIN_VFMADDPS512_MASK3,
29263 IX86_BUILTIN_VFMADDPS512_MASKZ,
29264 IX86_BUILTIN_VFMADDSD3_ROUND,
29265 IX86_BUILTIN_VFMADDSS3_ROUND,
29266 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29267 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29268 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29269 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29270 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29271 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29272 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29273 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29274 IX86_BUILTIN_VFMSUBPD512_MASK3,
29275 IX86_BUILTIN_VFMSUBPS512_MASK3,
29276 IX86_BUILTIN_VFMSUBSD3_MASK3,
29277 IX86_BUILTIN_VFMSUBSS3_MASK3,
29278 IX86_BUILTIN_VFNMADDPD512_MASK,
29279 IX86_BUILTIN_VFNMADDPS512_MASK,
29280 IX86_BUILTIN_VFNMSUBPD512_MASK,
29281 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29282 IX86_BUILTIN_VFNMSUBPS512_MASK,
29283 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29284 IX86_BUILTIN_VPCLZCNTD512,
29285 IX86_BUILTIN_VPCLZCNTQ512,
29286 IX86_BUILTIN_VPCONFLICTD512,
29287 IX86_BUILTIN_VPCONFLICTQ512,
29288 IX86_BUILTIN_VPERMDF512,
29289 IX86_BUILTIN_VPERMDI512,
29290 IX86_BUILTIN_VPERMI2VARD512,
29291 IX86_BUILTIN_VPERMI2VARPD512,
29292 IX86_BUILTIN_VPERMI2VARPS512,
29293 IX86_BUILTIN_VPERMI2VARQ512,
29294 IX86_BUILTIN_VPERMILPD512,
29295 IX86_BUILTIN_VPERMILPS512,
29296 IX86_BUILTIN_VPERMILVARPD512,
29297 IX86_BUILTIN_VPERMILVARPS512,
29298 IX86_BUILTIN_VPERMT2VARD512,
29299 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29300 IX86_BUILTIN_VPERMT2VARPD512,
29301 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29302 IX86_BUILTIN_VPERMT2VARPS512,
29303 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29304 IX86_BUILTIN_VPERMT2VARQ512,
29305 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29306 IX86_BUILTIN_VPERMVARDF512,
29307 IX86_BUILTIN_VPERMVARDI512,
29308 IX86_BUILTIN_VPERMVARSF512,
29309 IX86_BUILTIN_VPERMVARSI512,
29310 IX86_BUILTIN_VTERNLOGD512_MASK,
29311 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29312 IX86_BUILTIN_VTERNLOGQ512_MASK,
29313 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29315 /* Mask arithmetic operations */
29316 IX86_BUILTIN_KAND16,
29317 IX86_BUILTIN_KANDN16,
29318 IX86_BUILTIN_KNOT16,
29319 IX86_BUILTIN_KOR16,
29320 IX86_BUILTIN_KORTESTC16,
29321 IX86_BUILTIN_KORTESTZ16,
29322 IX86_BUILTIN_KUNPCKBW,
29323 IX86_BUILTIN_KXNOR16,
29324 IX86_BUILTIN_KXOR16,
29325 IX86_BUILTIN_KMOV16,
29327 /* AVX512VL. */
29328 IX86_BUILTIN_PMOVUSQD256_MEM,
29329 IX86_BUILTIN_PMOVUSQD128_MEM,
29330 IX86_BUILTIN_PMOVSQD256_MEM,
29331 IX86_BUILTIN_PMOVSQD128_MEM,
29332 IX86_BUILTIN_PMOVQD256_MEM,
29333 IX86_BUILTIN_PMOVQD128_MEM,
29334 IX86_BUILTIN_PMOVUSQW256_MEM,
29335 IX86_BUILTIN_PMOVUSQW128_MEM,
29336 IX86_BUILTIN_PMOVSQW256_MEM,
29337 IX86_BUILTIN_PMOVSQW128_MEM,
29338 IX86_BUILTIN_PMOVQW256_MEM,
29339 IX86_BUILTIN_PMOVQW128_MEM,
29340 IX86_BUILTIN_PMOVUSQB256_MEM,
29341 IX86_BUILTIN_PMOVUSQB128_MEM,
29342 IX86_BUILTIN_PMOVSQB256_MEM,
29343 IX86_BUILTIN_PMOVSQB128_MEM,
29344 IX86_BUILTIN_PMOVQB256_MEM,
29345 IX86_BUILTIN_PMOVQB128_MEM,
29346 IX86_BUILTIN_PMOVUSDW256_MEM,
29347 IX86_BUILTIN_PMOVUSDW128_MEM,
29348 IX86_BUILTIN_PMOVSDW256_MEM,
29349 IX86_BUILTIN_PMOVSDW128_MEM,
29350 IX86_BUILTIN_PMOVDW256_MEM,
29351 IX86_BUILTIN_PMOVDW128_MEM,
29352 IX86_BUILTIN_PMOVUSDB256_MEM,
29353 IX86_BUILTIN_PMOVUSDB128_MEM,
29354 IX86_BUILTIN_PMOVSDB256_MEM,
29355 IX86_BUILTIN_PMOVSDB128_MEM,
29356 IX86_BUILTIN_PMOVDB256_MEM,
29357 IX86_BUILTIN_PMOVDB128_MEM,
29358 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29359 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29360 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29361 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29362 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29363 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29364 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29365 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29366 IX86_BUILTIN_LOADAPD256_MASK,
29367 IX86_BUILTIN_LOADAPD128_MASK,
29368 IX86_BUILTIN_LOADAPS256_MASK,
29369 IX86_BUILTIN_LOADAPS128_MASK,
29370 IX86_BUILTIN_STOREAPD256_MASK,
29371 IX86_BUILTIN_STOREAPD128_MASK,
29372 IX86_BUILTIN_STOREAPS256_MASK,
29373 IX86_BUILTIN_STOREAPS128_MASK,
29374 IX86_BUILTIN_LOADUPD256_MASK,
29375 IX86_BUILTIN_LOADUPD128_MASK,
29376 IX86_BUILTIN_LOADUPS256_MASK,
29377 IX86_BUILTIN_LOADUPS128_MASK,
29378 IX86_BUILTIN_STOREUPD256_MASK,
29379 IX86_BUILTIN_STOREUPD128_MASK,
29380 IX86_BUILTIN_STOREUPS256_MASK,
29381 IX86_BUILTIN_STOREUPS128_MASK,
29382 IX86_BUILTIN_LOADDQUDI256_MASK,
29383 IX86_BUILTIN_LOADDQUDI128_MASK,
29384 IX86_BUILTIN_LOADDQUSI256_MASK,
29385 IX86_BUILTIN_LOADDQUSI128_MASK,
29386 IX86_BUILTIN_LOADDQUHI256_MASK,
29387 IX86_BUILTIN_LOADDQUHI128_MASK,
29388 IX86_BUILTIN_LOADDQUQI256_MASK,
29389 IX86_BUILTIN_LOADDQUQI128_MASK,
29390 IX86_BUILTIN_STOREDQUDI256_MASK,
29391 IX86_BUILTIN_STOREDQUDI128_MASK,
29392 IX86_BUILTIN_STOREDQUSI256_MASK,
29393 IX86_BUILTIN_STOREDQUSI128_MASK,
29394 IX86_BUILTIN_STOREDQUHI256_MASK,
29395 IX86_BUILTIN_STOREDQUHI128_MASK,
29396 IX86_BUILTIN_STOREDQUQI256_MASK,
29397 IX86_BUILTIN_STOREDQUQI128_MASK,
29398 IX86_BUILTIN_COMPRESSPDSTORE256,
29399 IX86_BUILTIN_COMPRESSPDSTORE128,
29400 IX86_BUILTIN_COMPRESSPSSTORE256,
29401 IX86_BUILTIN_COMPRESSPSSTORE128,
29402 IX86_BUILTIN_PCOMPRESSQSTORE256,
29403 IX86_BUILTIN_PCOMPRESSQSTORE128,
29404 IX86_BUILTIN_PCOMPRESSDSTORE256,
29405 IX86_BUILTIN_PCOMPRESSDSTORE128,
29406 IX86_BUILTIN_EXPANDPDLOAD256,
29407 IX86_BUILTIN_EXPANDPDLOAD128,
29408 IX86_BUILTIN_EXPANDPSLOAD256,
29409 IX86_BUILTIN_EXPANDPSLOAD128,
29410 IX86_BUILTIN_PEXPANDQLOAD256,
29411 IX86_BUILTIN_PEXPANDQLOAD128,
29412 IX86_BUILTIN_PEXPANDDLOAD256,
29413 IX86_BUILTIN_PEXPANDDLOAD128,
29414 IX86_BUILTIN_EXPANDPDLOAD256Z,
29415 IX86_BUILTIN_EXPANDPDLOAD128Z,
29416 IX86_BUILTIN_EXPANDPSLOAD256Z,
29417 IX86_BUILTIN_EXPANDPSLOAD128Z,
29418 IX86_BUILTIN_PEXPANDQLOAD256Z,
29419 IX86_BUILTIN_PEXPANDQLOAD128Z,
29420 IX86_BUILTIN_PEXPANDDLOAD256Z,
29421 IX86_BUILTIN_PEXPANDDLOAD128Z,
29422 IX86_BUILTIN_PALIGNR256_MASK,
29423 IX86_BUILTIN_PALIGNR128_MASK,
29424 IX86_BUILTIN_MOVDQA64_256_MASK,
29425 IX86_BUILTIN_MOVDQA64_128_MASK,
29426 IX86_BUILTIN_MOVDQA32_256_MASK,
29427 IX86_BUILTIN_MOVDQA32_128_MASK,
29428 IX86_BUILTIN_MOVAPD256_MASK,
29429 IX86_BUILTIN_MOVAPD128_MASK,
29430 IX86_BUILTIN_MOVAPS256_MASK,
29431 IX86_BUILTIN_MOVAPS128_MASK,
29432 IX86_BUILTIN_MOVDQUHI256_MASK,
29433 IX86_BUILTIN_MOVDQUHI128_MASK,
29434 IX86_BUILTIN_MOVDQUQI256_MASK,
29435 IX86_BUILTIN_MOVDQUQI128_MASK,
29436 IX86_BUILTIN_MINPS128_MASK,
29437 IX86_BUILTIN_MAXPS128_MASK,
29438 IX86_BUILTIN_MINPD128_MASK,
29439 IX86_BUILTIN_MAXPD128_MASK,
29440 IX86_BUILTIN_MAXPD256_MASK,
29441 IX86_BUILTIN_MAXPS256_MASK,
29442 IX86_BUILTIN_MINPD256_MASK,
29443 IX86_BUILTIN_MINPS256_MASK,
29444 IX86_BUILTIN_MULPS128_MASK,
29445 IX86_BUILTIN_DIVPS128_MASK,
29446 IX86_BUILTIN_MULPD128_MASK,
29447 IX86_BUILTIN_DIVPD128_MASK,
29448 IX86_BUILTIN_DIVPD256_MASK,
29449 IX86_BUILTIN_DIVPS256_MASK,
29450 IX86_BUILTIN_MULPD256_MASK,
29451 IX86_BUILTIN_MULPS256_MASK,
29452 IX86_BUILTIN_ADDPD128_MASK,
29453 IX86_BUILTIN_ADDPD256_MASK,
29454 IX86_BUILTIN_ADDPS128_MASK,
29455 IX86_BUILTIN_ADDPS256_MASK,
29456 IX86_BUILTIN_SUBPD128_MASK,
29457 IX86_BUILTIN_SUBPD256_MASK,
29458 IX86_BUILTIN_SUBPS128_MASK,
29459 IX86_BUILTIN_SUBPS256_MASK,
29460 IX86_BUILTIN_XORPD256_MASK,
29461 IX86_BUILTIN_XORPD128_MASK,
29462 IX86_BUILTIN_XORPS256_MASK,
29463 IX86_BUILTIN_XORPS128_MASK,
29464 IX86_BUILTIN_ORPD256_MASK,
29465 IX86_BUILTIN_ORPD128_MASK,
29466 IX86_BUILTIN_ORPS256_MASK,
29467 IX86_BUILTIN_ORPS128_MASK,
29468 IX86_BUILTIN_BROADCASTF32x2_256,
29469 IX86_BUILTIN_BROADCASTI32x2_256,
29470 IX86_BUILTIN_BROADCASTI32x2_128,
29471 IX86_BUILTIN_BROADCASTF64X2_256,
29472 IX86_BUILTIN_BROADCASTI64X2_256,
29473 IX86_BUILTIN_BROADCASTF32X4_256,
29474 IX86_BUILTIN_BROADCASTI32X4_256,
29475 IX86_BUILTIN_EXTRACTF32X4_256,
29476 IX86_BUILTIN_EXTRACTI32X4_256,
29477 IX86_BUILTIN_DBPSADBW256,
29478 IX86_BUILTIN_DBPSADBW128,
29479 IX86_BUILTIN_CVTTPD2QQ256,
29480 IX86_BUILTIN_CVTTPD2QQ128,
29481 IX86_BUILTIN_CVTTPD2UQQ256,
29482 IX86_BUILTIN_CVTTPD2UQQ128,
29483 IX86_BUILTIN_CVTPD2QQ256,
29484 IX86_BUILTIN_CVTPD2QQ128,
29485 IX86_BUILTIN_CVTPD2UQQ256,
29486 IX86_BUILTIN_CVTPD2UQQ128,
29487 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29488 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29489 IX86_BUILTIN_CVTTPS2QQ256,
29490 IX86_BUILTIN_CVTTPS2QQ128,
29491 IX86_BUILTIN_CVTTPS2UQQ256,
29492 IX86_BUILTIN_CVTTPS2UQQ128,
29493 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29494 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29495 IX86_BUILTIN_CVTTPS2UDQ256,
29496 IX86_BUILTIN_CVTTPS2UDQ128,
29497 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29498 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29499 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29500 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29501 IX86_BUILTIN_CVTPD2DQ256_MASK,
29502 IX86_BUILTIN_CVTPD2DQ128_MASK,
29503 IX86_BUILTIN_CVTDQ2PD256_MASK,
29504 IX86_BUILTIN_CVTDQ2PD128_MASK,
29505 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29506 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29507 IX86_BUILTIN_CVTDQ2PS256_MASK,
29508 IX86_BUILTIN_CVTDQ2PS128_MASK,
29509 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29510 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29511 IX86_BUILTIN_CVTPS2PD256_MASK,
29512 IX86_BUILTIN_CVTPS2PD128_MASK,
29513 IX86_BUILTIN_PBROADCASTB256_MASK,
29514 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29515 IX86_BUILTIN_PBROADCASTB128_MASK,
29516 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29517 IX86_BUILTIN_PBROADCASTW256_MASK,
29518 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29519 IX86_BUILTIN_PBROADCASTW128_MASK,
29520 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29521 IX86_BUILTIN_PBROADCASTD256_MASK,
29522 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29523 IX86_BUILTIN_PBROADCASTD128_MASK,
29524 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29525 IX86_BUILTIN_PBROADCASTQ256_MASK,
29526 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29527 IX86_BUILTIN_PBROADCASTQ128_MASK,
29528 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29529 IX86_BUILTIN_BROADCASTSS256,
29530 IX86_BUILTIN_BROADCASTSS128,
29531 IX86_BUILTIN_BROADCASTSD256,
29532 IX86_BUILTIN_EXTRACTF64X2_256,
29533 IX86_BUILTIN_EXTRACTI64X2_256,
29534 IX86_BUILTIN_INSERTF32X4_256,
29535 IX86_BUILTIN_INSERTI32X4_256,
29536 IX86_BUILTIN_PMOVSXBW256_MASK,
29537 IX86_BUILTIN_PMOVSXBW128_MASK,
29538 IX86_BUILTIN_PMOVSXBD256_MASK,
29539 IX86_BUILTIN_PMOVSXBD128_MASK,
29540 IX86_BUILTIN_PMOVSXBQ256_MASK,
29541 IX86_BUILTIN_PMOVSXBQ128_MASK,
29542 IX86_BUILTIN_PMOVSXWD256_MASK,
29543 IX86_BUILTIN_PMOVSXWD128_MASK,
29544 IX86_BUILTIN_PMOVSXWQ256_MASK,
29545 IX86_BUILTIN_PMOVSXWQ128_MASK,
29546 IX86_BUILTIN_PMOVSXDQ256_MASK,
29547 IX86_BUILTIN_PMOVSXDQ128_MASK,
29548 IX86_BUILTIN_PMOVZXBW256_MASK,
29549 IX86_BUILTIN_PMOVZXBW128_MASK,
29550 IX86_BUILTIN_PMOVZXBD256_MASK,
29551 IX86_BUILTIN_PMOVZXBD128_MASK,
29552 IX86_BUILTIN_PMOVZXBQ256_MASK,
29553 IX86_BUILTIN_PMOVZXBQ128_MASK,
29554 IX86_BUILTIN_PMOVZXWD256_MASK,
29555 IX86_BUILTIN_PMOVZXWD128_MASK,
29556 IX86_BUILTIN_PMOVZXWQ256_MASK,
29557 IX86_BUILTIN_PMOVZXWQ128_MASK,
29558 IX86_BUILTIN_PMOVZXDQ256_MASK,
29559 IX86_BUILTIN_PMOVZXDQ128_MASK,
29560 IX86_BUILTIN_REDUCEPD256_MASK,
29561 IX86_BUILTIN_REDUCEPD128_MASK,
29562 IX86_BUILTIN_REDUCEPS256_MASK,
29563 IX86_BUILTIN_REDUCEPS128_MASK,
29564 IX86_BUILTIN_REDUCESD_MASK,
29565 IX86_BUILTIN_REDUCESS_MASK,
29566 IX86_BUILTIN_VPERMVARHI256_MASK,
29567 IX86_BUILTIN_VPERMVARHI128_MASK,
29568 IX86_BUILTIN_VPERMT2VARHI256,
29569 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29570 IX86_BUILTIN_VPERMT2VARHI128,
29571 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29572 IX86_BUILTIN_VPERMI2VARHI256,
29573 IX86_BUILTIN_VPERMI2VARHI128,
29574 IX86_BUILTIN_RCP14PD256,
29575 IX86_BUILTIN_RCP14PD128,
29576 IX86_BUILTIN_RCP14PS256,
29577 IX86_BUILTIN_RCP14PS128,
29578 IX86_BUILTIN_RSQRT14PD256_MASK,
29579 IX86_BUILTIN_RSQRT14PD128_MASK,
29580 IX86_BUILTIN_RSQRT14PS256_MASK,
29581 IX86_BUILTIN_RSQRT14PS128_MASK,
29582 IX86_BUILTIN_SQRTPD256_MASK,
29583 IX86_BUILTIN_SQRTPD128_MASK,
29584 IX86_BUILTIN_SQRTPS256_MASK,
29585 IX86_BUILTIN_SQRTPS128_MASK,
29586 IX86_BUILTIN_PADDB128_MASK,
29587 IX86_BUILTIN_PADDW128_MASK,
29588 IX86_BUILTIN_PADDD128_MASK,
29589 IX86_BUILTIN_PADDQ128_MASK,
29590 IX86_BUILTIN_PSUBB128_MASK,
29591 IX86_BUILTIN_PSUBW128_MASK,
29592 IX86_BUILTIN_PSUBD128_MASK,
29593 IX86_BUILTIN_PSUBQ128_MASK,
29594 IX86_BUILTIN_PADDSB128_MASK,
29595 IX86_BUILTIN_PADDSW128_MASK,
29596 IX86_BUILTIN_PSUBSB128_MASK,
29597 IX86_BUILTIN_PSUBSW128_MASK,
29598 IX86_BUILTIN_PADDUSB128_MASK,
29599 IX86_BUILTIN_PADDUSW128_MASK,
29600 IX86_BUILTIN_PSUBUSB128_MASK,
29601 IX86_BUILTIN_PSUBUSW128_MASK,
29602 IX86_BUILTIN_PADDB256_MASK,
29603 IX86_BUILTIN_PADDW256_MASK,
29604 IX86_BUILTIN_PADDD256_MASK,
29605 IX86_BUILTIN_PADDQ256_MASK,
29606 IX86_BUILTIN_PADDSB256_MASK,
29607 IX86_BUILTIN_PADDSW256_MASK,
29608 IX86_BUILTIN_PADDUSB256_MASK,
29609 IX86_BUILTIN_PADDUSW256_MASK,
29610 IX86_BUILTIN_PSUBB256_MASK,
29611 IX86_BUILTIN_PSUBW256_MASK,
29612 IX86_BUILTIN_PSUBD256_MASK,
29613 IX86_BUILTIN_PSUBQ256_MASK,
29614 IX86_BUILTIN_PSUBSB256_MASK,
29615 IX86_BUILTIN_PSUBSW256_MASK,
29616 IX86_BUILTIN_PSUBUSB256_MASK,
29617 IX86_BUILTIN_PSUBUSW256_MASK,
29618 IX86_BUILTIN_SHUF_F64x2_256,
29619 IX86_BUILTIN_SHUF_I64x2_256,
29620 IX86_BUILTIN_SHUF_I32x4_256,
29621 IX86_BUILTIN_SHUF_F32x4_256,
29622 IX86_BUILTIN_PMOVWB128,
29623 IX86_BUILTIN_PMOVWB256,
29624 IX86_BUILTIN_PMOVSWB128,
29625 IX86_BUILTIN_PMOVSWB256,
29626 IX86_BUILTIN_PMOVUSWB128,
29627 IX86_BUILTIN_PMOVUSWB256,
29628 IX86_BUILTIN_PMOVDB128,
29629 IX86_BUILTIN_PMOVDB256,
29630 IX86_BUILTIN_PMOVSDB128,
29631 IX86_BUILTIN_PMOVSDB256,
29632 IX86_BUILTIN_PMOVUSDB128,
29633 IX86_BUILTIN_PMOVUSDB256,
29634 IX86_BUILTIN_PMOVDW128,
29635 IX86_BUILTIN_PMOVDW256,
29636 IX86_BUILTIN_PMOVSDW128,
29637 IX86_BUILTIN_PMOVSDW256,
29638 IX86_BUILTIN_PMOVUSDW128,
29639 IX86_BUILTIN_PMOVUSDW256,
29640 IX86_BUILTIN_PMOVQB128,
29641 IX86_BUILTIN_PMOVQB256,
29642 IX86_BUILTIN_PMOVSQB128,
29643 IX86_BUILTIN_PMOVSQB256,
29644 IX86_BUILTIN_PMOVUSQB128,
29645 IX86_BUILTIN_PMOVUSQB256,
29646 IX86_BUILTIN_PMOVQW128,
29647 IX86_BUILTIN_PMOVQW256,
29648 IX86_BUILTIN_PMOVSQW128,
29649 IX86_BUILTIN_PMOVSQW256,
29650 IX86_BUILTIN_PMOVUSQW128,
29651 IX86_BUILTIN_PMOVUSQW256,
29652 IX86_BUILTIN_PMOVQD128,
29653 IX86_BUILTIN_PMOVQD256,
29654 IX86_BUILTIN_PMOVSQD128,
29655 IX86_BUILTIN_PMOVSQD256,
29656 IX86_BUILTIN_PMOVUSQD128,
29657 IX86_BUILTIN_PMOVUSQD256,
29658 IX86_BUILTIN_RANGEPD256,
29659 IX86_BUILTIN_RANGEPD128,
29660 IX86_BUILTIN_RANGEPS256,
29661 IX86_BUILTIN_RANGEPS128,
29662 IX86_BUILTIN_GETEXPPS256,
29663 IX86_BUILTIN_GETEXPPD256,
29664 IX86_BUILTIN_GETEXPPS128,
29665 IX86_BUILTIN_GETEXPPD128,
29666 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29667 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29668 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29669 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29670 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29671 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29672 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29673 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29674 IX86_BUILTIN_PABSQ256,
29675 IX86_BUILTIN_PABSQ128,
29676 IX86_BUILTIN_PABSD256_MASK,
29677 IX86_BUILTIN_PABSD128_MASK,
29678 IX86_BUILTIN_PMULHRSW256_MASK,
29679 IX86_BUILTIN_PMULHRSW128_MASK,
29680 IX86_BUILTIN_PMULHUW128_MASK,
29681 IX86_BUILTIN_PMULHUW256_MASK,
29682 IX86_BUILTIN_PMULHW256_MASK,
29683 IX86_BUILTIN_PMULHW128_MASK,
29684 IX86_BUILTIN_PMULLW256_MASK,
29685 IX86_BUILTIN_PMULLW128_MASK,
29686 IX86_BUILTIN_PMULLQ256,
29687 IX86_BUILTIN_PMULLQ128,
29688 IX86_BUILTIN_ANDPD256_MASK,
29689 IX86_BUILTIN_ANDPD128_MASK,
29690 IX86_BUILTIN_ANDPS256_MASK,
29691 IX86_BUILTIN_ANDPS128_MASK,
29692 IX86_BUILTIN_ANDNPD256_MASK,
29693 IX86_BUILTIN_ANDNPD128_MASK,
29694 IX86_BUILTIN_ANDNPS256_MASK,
29695 IX86_BUILTIN_ANDNPS128_MASK,
29696 IX86_BUILTIN_PSLLWI128_MASK,
29697 IX86_BUILTIN_PSLLDI128_MASK,
29698 IX86_BUILTIN_PSLLQI128_MASK,
29699 IX86_BUILTIN_PSLLW128_MASK,
29700 IX86_BUILTIN_PSLLD128_MASK,
29701 IX86_BUILTIN_PSLLQ128_MASK,
29702 IX86_BUILTIN_PSLLWI256_MASK ,
29703 IX86_BUILTIN_PSLLW256_MASK,
29704 IX86_BUILTIN_PSLLDI256_MASK,
29705 IX86_BUILTIN_PSLLD256_MASK,
29706 IX86_BUILTIN_PSLLQI256_MASK,
29707 IX86_BUILTIN_PSLLQ256_MASK,
29708 IX86_BUILTIN_PSRADI128_MASK,
29709 IX86_BUILTIN_PSRAD128_MASK,
29710 IX86_BUILTIN_PSRADI256_MASK,
29711 IX86_BUILTIN_PSRAD256_MASK,
29712 IX86_BUILTIN_PSRAQI128_MASK,
29713 IX86_BUILTIN_PSRAQ128_MASK,
29714 IX86_BUILTIN_PSRAQI256_MASK,
29715 IX86_BUILTIN_PSRAQ256_MASK,
29716 IX86_BUILTIN_PANDD256,
29717 IX86_BUILTIN_PANDD128,
29718 IX86_BUILTIN_PSRLDI128_MASK,
29719 IX86_BUILTIN_PSRLD128_MASK,
29720 IX86_BUILTIN_PSRLDI256_MASK,
29721 IX86_BUILTIN_PSRLD256_MASK,
29722 IX86_BUILTIN_PSRLQI128_MASK,
29723 IX86_BUILTIN_PSRLQ128_MASK,
29724 IX86_BUILTIN_PSRLQI256_MASK,
29725 IX86_BUILTIN_PSRLQ256_MASK,
29726 IX86_BUILTIN_PANDQ256,
29727 IX86_BUILTIN_PANDQ128,
29728 IX86_BUILTIN_PANDND256,
29729 IX86_BUILTIN_PANDND128,
29730 IX86_BUILTIN_PANDNQ256,
29731 IX86_BUILTIN_PANDNQ128,
29732 IX86_BUILTIN_PORD256,
29733 IX86_BUILTIN_PORD128,
29734 IX86_BUILTIN_PORQ256,
29735 IX86_BUILTIN_PORQ128,
29736 IX86_BUILTIN_PXORD256,
29737 IX86_BUILTIN_PXORD128,
29738 IX86_BUILTIN_PXORQ256,
29739 IX86_BUILTIN_PXORQ128,
29740 IX86_BUILTIN_PACKSSWB256_MASK,
29741 IX86_BUILTIN_PACKSSWB128_MASK,
29742 IX86_BUILTIN_PACKUSWB256_MASK,
29743 IX86_BUILTIN_PACKUSWB128_MASK,
29744 IX86_BUILTIN_RNDSCALEPS256,
29745 IX86_BUILTIN_RNDSCALEPD256,
29746 IX86_BUILTIN_RNDSCALEPS128,
29747 IX86_BUILTIN_RNDSCALEPD128,
29748 IX86_BUILTIN_VTERNLOGQ256_MASK,
29749 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29750 IX86_BUILTIN_VTERNLOGD256_MASK,
29751 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29752 IX86_BUILTIN_VTERNLOGQ128_MASK,
29753 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29754 IX86_BUILTIN_VTERNLOGD128_MASK,
29755 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29756 IX86_BUILTIN_SCALEFPD256,
29757 IX86_BUILTIN_SCALEFPS256,
29758 IX86_BUILTIN_SCALEFPD128,
29759 IX86_BUILTIN_SCALEFPS128,
29760 IX86_BUILTIN_VFMADDPD256_MASK,
29761 IX86_BUILTIN_VFMADDPD256_MASK3,
29762 IX86_BUILTIN_VFMADDPD256_MASKZ,
29763 IX86_BUILTIN_VFMADDPD128_MASK,
29764 IX86_BUILTIN_VFMADDPD128_MASK3,
29765 IX86_BUILTIN_VFMADDPD128_MASKZ,
29766 IX86_BUILTIN_VFMADDPS256_MASK,
29767 IX86_BUILTIN_VFMADDPS256_MASK3,
29768 IX86_BUILTIN_VFMADDPS256_MASKZ,
29769 IX86_BUILTIN_VFMADDPS128_MASK,
29770 IX86_BUILTIN_VFMADDPS128_MASK3,
29771 IX86_BUILTIN_VFMADDPS128_MASKZ,
29772 IX86_BUILTIN_VFMSUBPD256_MASK3,
29773 IX86_BUILTIN_VFMSUBPD128_MASK3,
29774 IX86_BUILTIN_VFMSUBPS256_MASK3,
29775 IX86_BUILTIN_VFMSUBPS128_MASK3,
29776 IX86_BUILTIN_VFNMADDPD256_MASK,
29777 IX86_BUILTIN_VFNMADDPD128_MASK,
29778 IX86_BUILTIN_VFNMADDPS256_MASK,
29779 IX86_BUILTIN_VFNMADDPS128_MASK,
29780 IX86_BUILTIN_VFNMSUBPD256_MASK,
29781 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29782 IX86_BUILTIN_VFNMSUBPD128_MASK,
29783 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29784 IX86_BUILTIN_VFNMSUBPS256_MASK,
29785 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29786 IX86_BUILTIN_VFNMSUBPS128_MASK,
29787 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29788 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29789 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29790 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29791 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29792 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29793 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29794 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29795 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29796 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29797 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29798 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29799 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29800 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29801 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29802 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29803 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29804 IX86_BUILTIN_INSERTF64X2_256,
29805 IX86_BUILTIN_INSERTI64X2_256,
29806 IX86_BUILTIN_PSRAVV16HI,
29807 IX86_BUILTIN_PSRAVV8HI,
29808 IX86_BUILTIN_PMADDUBSW256_MASK,
29809 IX86_BUILTIN_PMADDUBSW128_MASK,
29810 IX86_BUILTIN_PMADDWD256_MASK,
29811 IX86_BUILTIN_PMADDWD128_MASK,
29812 IX86_BUILTIN_PSRLVV16HI,
29813 IX86_BUILTIN_PSRLVV8HI,
29814 IX86_BUILTIN_CVTPS2DQ256_MASK,
29815 IX86_BUILTIN_CVTPS2DQ128_MASK,
29816 IX86_BUILTIN_CVTPS2UDQ256,
29817 IX86_BUILTIN_CVTPS2UDQ128,
29818 IX86_BUILTIN_CVTPS2QQ256,
29819 IX86_BUILTIN_CVTPS2QQ128,
29820 IX86_BUILTIN_CVTPS2UQQ256,
29821 IX86_BUILTIN_CVTPS2UQQ128,
29822 IX86_BUILTIN_GETMANTPS256,
29823 IX86_BUILTIN_GETMANTPS128,
29824 IX86_BUILTIN_GETMANTPD256,
29825 IX86_BUILTIN_GETMANTPD128,
29826 IX86_BUILTIN_MOVDDUP256_MASK,
29827 IX86_BUILTIN_MOVDDUP128_MASK,
29828 IX86_BUILTIN_MOVSHDUP256_MASK,
29829 IX86_BUILTIN_MOVSHDUP128_MASK,
29830 IX86_BUILTIN_MOVSLDUP256_MASK,
29831 IX86_BUILTIN_MOVSLDUP128_MASK,
29832 IX86_BUILTIN_CVTQQ2PS256,
29833 IX86_BUILTIN_CVTQQ2PS128,
29834 IX86_BUILTIN_CVTUQQ2PS256,
29835 IX86_BUILTIN_CVTUQQ2PS128,
29836 IX86_BUILTIN_CVTQQ2PD256,
29837 IX86_BUILTIN_CVTQQ2PD128,
29838 IX86_BUILTIN_CVTUQQ2PD256,
29839 IX86_BUILTIN_CVTUQQ2PD128,
29840 IX86_BUILTIN_VPERMT2VARQ256,
29841 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29842 IX86_BUILTIN_VPERMT2VARD256,
29843 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29844 IX86_BUILTIN_VPERMI2VARQ256,
29845 IX86_BUILTIN_VPERMI2VARD256,
29846 IX86_BUILTIN_VPERMT2VARPD256,
29847 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29848 IX86_BUILTIN_VPERMT2VARPS256,
29849 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29850 IX86_BUILTIN_VPERMI2VARPD256,
29851 IX86_BUILTIN_VPERMI2VARPS256,
29852 IX86_BUILTIN_VPERMT2VARQ128,
29853 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29854 IX86_BUILTIN_VPERMT2VARD128,
29855 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29856 IX86_BUILTIN_VPERMI2VARQ128,
29857 IX86_BUILTIN_VPERMI2VARD128,
29858 IX86_BUILTIN_VPERMT2VARPD128,
29859 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29860 IX86_BUILTIN_VPERMT2VARPS128,
29861 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29862 IX86_BUILTIN_VPERMI2VARPD128,
29863 IX86_BUILTIN_VPERMI2VARPS128,
29864 IX86_BUILTIN_PSHUFB256_MASK,
29865 IX86_BUILTIN_PSHUFB128_MASK,
29866 IX86_BUILTIN_PSHUFHW256_MASK,
29867 IX86_BUILTIN_PSHUFHW128_MASK,
29868 IX86_BUILTIN_PSHUFLW256_MASK,
29869 IX86_BUILTIN_PSHUFLW128_MASK,
29870 IX86_BUILTIN_PSHUFD256_MASK,
29871 IX86_BUILTIN_PSHUFD128_MASK,
29872 IX86_BUILTIN_SHUFPD256_MASK,
29873 IX86_BUILTIN_SHUFPD128_MASK,
29874 IX86_BUILTIN_SHUFPS256_MASK,
29875 IX86_BUILTIN_SHUFPS128_MASK,
29876 IX86_BUILTIN_PROLVQ256,
29877 IX86_BUILTIN_PROLVQ128,
29878 IX86_BUILTIN_PROLQ256,
29879 IX86_BUILTIN_PROLQ128,
29880 IX86_BUILTIN_PRORVQ256,
29881 IX86_BUILTIN_PRORVQ128,
29882 IX86_BUILTIN_PRORQ256,
29883 IX86_BUILTIN_PRORQ128,
29884 IX86_BUILTIN_PSRAVQ128,
29885 IX86_BUILTIN_PSRAVQ256,
29886 IX86_BUILTIN_PSLLVV4DI_MASK,
29887 IX86_BUILTIN_PSLLVV2DI_MASK,
29888 IX86_BUILTIN_PSLLVV8SI_MASK,
29889 IX86_BUILTIN_PSLLVV4SI_MASK,
29890 IX86_BUILTIN_PSRAVV8SI_MASK,
29891 IX86_BUILTIN_PSRAVV4SI_MASK,
29892 IX86_BUILTIN_PSRLVV4DI_MASK,
29893 IX86_BUILTIN_PSRLVV2DI_MASK,
29894 IX86_BUILTIN_PSRLVV8SI_MASK,
29895 IX86_BUILTIN_PSRLVV4SI_MASK,
29896 IX86_BUILTIN_PSRAWI256_MASK,
29897 IX86_BUILTIN_PSRAW256_MASK,
29898 IX86_BUILTIN_PSRAWI128_MASK,
29899 IX86_BUILTIN_PSRAW128_MASK,
29900 IX86_BUILTIN_PSRLWI256_MASK,
29901 IX86_BUILTIN_PSRLW256_MASK,
29902 IX86_BUILTIN_PSRLWI128_MASK,
29903 IX86_BUILTIN_PSRLW128_MASK,
29904 IX86_BUILTIN_PRORVD256,
29905 IX86_BUILTIN_PROLVD256,
29906 IX86_BUILTIN_PRORD256,
29907 IX86_BUILTIN_PROLD256,
29908 IX86_BUILTIN_PRORVD128,
29909 IX86_BUILTIN_PROLVD128,
29910 IX86_BUILTIN_PRORD128,
29911 IX86_BUILTIN_PROLD128,
29912 IX86_BUILTIN_FPCLASSPD256,
29913 IX86_BUILTIN_FPCLASSPD128,
29914 IX86_BUILTIN_FPCLASSSD,
29915 IX86_BUILTIN_FPCLASSPS256,
29916 IX86_BUILTIN_FPCLASSPS128,
29917 IX86_BUILTIN_FPCLASSSS,
29918 IX86_BUILTIN_CVTB2MASK128,
29919 IX86_BUILTIN_CVTB2MASK256,
29920 IX86_BUILTIN_CVTW2MASK128,
29921 IX86_BUILTIN_CVTW2MASK256,
29922 IX86_BUILTIN_CVTD2MASK128,
29923 IX86_BUILTIN_CVTD2MASK256,
29924 IX86_BUILTIN_CVTQ2MASK128,
29925 IX86_BUILTIN_CVTQ2MASK256,
29926 IX86_BUILTIN_CVTMASK2B128,
29927 IX86_BUILTIN_CVTMASK2B256,
29928 IX86_BUILTIN_CVTMASK2W128,
29929 IX86_BUILTIN_CVTMASK2W256,
29930 IX86_BUILTIN_CVTMASK2D128,
29931 IX86_BUILTIN_CVTMASK2D256,
29932 IX86_BUILTIN_CVTMASK2Q128,
29933 IX86_BUILTIN_CVTMASK2Q256,
29934 IX86_BUILTIN_PCMPEQB128_MASK,
29935 IX86_BUILTIN_PCMPEQB256_MASK,
29936 IX86_BUILTIN_PCMPEQW128_MASK,
29937 IX86_BUILTIN_PCMPEQW256_MASK,
29938 IX86_BUILTIN_PCMPEQD128_MASK,
29939 IX86_BUILTIN_PCMPEQD256_MASK,
29940 IX86_BUILTIN_PCMPEQQ128_MASK,
29941 IX86_BUILTIN_PCMPEQQ256_MASK,
29942 IX86_BUILTIN_PCMPGTB128_MASK,
29943 IX86_BUILTIN_PCMPGTB256_MASK,
29944 IX86_BUILTIN_PCMPGTW128_MASK,
29945 IX86_BUILTIN_PCMPGTW256_MASK,
29946 IX86_BUILTIN_PCMPGTD128_MASK,
29947 IX86_BUILTIN_PCMPGTD256_MASK,
29948 IX86_BUILTIN_PCMPGTQ128_MASK,
29949 IX86_BUILTIN_PCMPGTQ256_MASK,
29950 IX86_BUILTIN_PTESTMB128,
29951 IX86_BUILTIN_PTESTMB256,
29952 IX86_BUILTIN_PTESTMW128,
29953 IX86_BUILTIN_PTESTMW256,
29954 IX86_BUILTIN_PTESTMD128,
29955 IX86_BUILTIN_PTESTMD256,
29956 IX86_BUILTIN_PTESTMQ128,
29957 IX86_BUILTIN_PTESTMQ256,
29958 IX86_BUILTIN_PTESTNMB128,
29959 IX86_BUILTIN_PTESTNMB256,
29960 IX86_BUILTIN_PTESTNMW128,
29961 IX86_BUILTIN_PTESTNMW256,
29962 IX86_BUILTIN_PTESTNMD128,
29963 IX86_BUILTIN_PTESTNMD256,
29964 IX86_BUILTIN_PTESTNMQ128,
29965 IX86_BUILTIN_PTESTNMQ256,
29966 IX86_BUILTIN_PBROADCASTMB128,
29967 IX86_BUILTIN_PBROADCASTMB256,
29968 IX86_BUILTIN_PBROADCASTMW128,
29969 IX86_BUILTIN_PBROADCASTMW256,
29970 IX86_BUILTIN_COMPRESSPD256,
29971 IX86_BUILTIN_COMPRESSPD128,
29972 IX86_BUILTIN_COMPRESSPS256,
29973 IX86_BUILTIN_COMPRESSPS128,
29974 IX86_BUILTIN_PCOMPRESSQ256,
29975 IX86_BUILTIN_PCOMPRESSQ128,
29976 IX86_BUILTIN_PCOMPRESSD256,
29977 IX86_BUILTIN_PCOMPRESSD128,
29978 IX86_BUILTIN_EXPANDPD256,
29979 IX86_BUILTIN_EXPANDPD128,
29980 IX86_BUILTIN_EXPANDPS256,
29981 IX86_BUILTIN_EXPANDPS128,
29982 IX86_BUILTIN_PEXPANDQ256,
29983 IX86_BUILTIN_PEXPANDQ128,
29984 IX86_BUILTIN_PEXPANDD256,
29985 IX86_BUILTIN_PEXPANDD128,
29986 IX86_BUILTIN_EXPANDPD256Z,
29987 IX86_BUILTIN_EXPANDPD128Z,
29988 IX86_BUILTIN_EXPANDPS256Z,
29989 IX86_BUILTIN_EXPANDPS128Z,
29990 IX86_BUILTIN_PEXPANDQ256Z,
29991 IX86_BUILTIN_PEXPANDQ128Z,
29992 IX86_BUILTIN_PEXPANDD256Z,
29993 IX86_BUILTIN_PEXPANDD128Z,
29994 IX86_BUILTIN_PMAXSD256_MASK,
29995 IX86_BUILTIN_PMINSD256_MASK,
29996 IX86_BUILTIN_PMAXUD256_MASK,
29997 IX86_BUILTIN_PMINUD256_MASK,
29998 IX86_BUILTIN_PMAXSD128_MASK,
29999 IX86_BUILTIN_PMINSD128_MASK,
30000 IX86_BUILTIN_PMAXUD128_MASK,
30001 IX86_BUILTIN_PMINUD128_MASK,
30002 IX86_BUILTIN_PMAXSQ256_MASK,
30003 IX86_BUILTIN_PMINSQ256_MASK,
30004 IX86_BUILTIN_PMAXUQ256_MASK,
30005 IX86_BUILTIN_PMINUQ256_MASK,
30006 IX86_BUILTIN_PMAXSQ128_MASK,
30007 IX86_BUILTIN_PMINSQ128_MASK,
30008 IX86_BUILTIN_PMAXUQ128_MASK,
30009 IX86_BUILTIN_PMINUQ128_MASK,
30010 IX86_BUILTIN_PMINSB256_MASK,
30011 IX86_BUILTIN_PMINUB256_MASK,
30012 IX86_BUILTIN_PMAXSB256_MASK,
30013 IX86_BUILTIN_PMAXUB256_MASK,
30014 IX86_BUILTIN_PMINSB128_MASK,
30015 IX86_BUILTIN_PMINUB128_MASK,
30016 IX86_BUILTIN_PMAXSB128_MASK,
30017 IX86_BUILTIN_PMAXUB128_MASK,
30018 IX86_BUILTIN_PMINSW256_MASK,
30019 IX86_BUILTIN_PMINUW256_MASK,
30020 IX86_BUILTIN_PMAXSW256_MASK,
30021 IX86_BUILTIN_PMAXUW256_MASK,
30022 IX86_BUILTIN_PMINSW128_MASK,
30023 IX86_BUILTIN_PMINUW128_MASK,
30024 IX86_BUILTIN_PMAXSW128_MASK,
30025 IX86_BUILTIN_PMAXUW128_MASK,
30026 IX86_BUILTIN_VPCONFLICTQ256,
30027 IX86_BUILTIN_VPCONFLICTD256,
30028 IX86_BUILTIN_VPCLZCNTQ256,
30029 IX86_BUILTIN_VPCLZCNTD256,
30030 IX86_BUILTIN_UNPCKHPD256_MASK,
30031 IX86_BUILTIN_UNPCKHPD128_MASK,
30032 IX86_BUILTIN_UNPCKHPS256_MASK,
30033 IX86_BUILTIN_UNPCKHPS128_MASK,
30034 IX86_BUILTIN_UNPCKLPD256_MASK,
30035 IX86_BUILTIN_UNPCKLPD128_MASK,
30036 IX86_BUILTIN_UNPCKLPS256_MASK,
30037 IX86_BUILTIN_VPCONFLICTQ128,
30038 IX86_BUILTIN_VPCONFLICTD128,
30039 IX86_BUILTIN_VPCLZCNTQ128,
30040 IX86_BUILTIN_VPCLZCNTD128,
30041 IX86_BUILTIN_UNPCKLPS128_MASK,
30042 IX86_BUILTIN_ALIGND256,
30043 IX86_BUILTIN_ALIGNQ256,
30044 IX86_BUILTIN_ALIGND128,
30045 IX86_BUILTIN_ALIGNQ128,
30046 IX86_BUILTIN_CVTPS2PH256_MASK,
30047 IX86_BUILTIN_CVTPS2PH_MASK,
30048 IX86_BUILTIN_CVTPH2PS_MASK,
30049 IX86_BUILTIN_CVTPH2PS256_MASK,
30050 IX86_BUILTIN_PUNPCKHDQ128_MASK,
30051 IX86_BUILTIN_PUNPCKHDQ256_MASK,
30052 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
30053 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
30054 IX86_BUILTIN_PUNPCKLDQ128_MASK,
30055 IX86_BUILTIN_PUNPCKLDQ256_MASK,
30056 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
30057 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
30058 IX86_BUILTIN_PUNPCKHBW128_MASK,
30059 IX86_BUILTIN_PUNPCKHBW256_MASK,
30060 IX86_BUILTIN_PUNPCKHWD128_MASK,
30061 IX86_BUILTIN_PUNPCKHWD256_MASK,
30062 IX86_BUILTIN_PUNPCKLBW128_MASK,
30063 IX86_BUILTIN_PUNPCKLBW256_MASK,
30064 IX86_BUILTIN_PUNPCKLWD128_MASK,
30065 IX86_BUILTIN_PUNPCKLWD256_MASK,
30066 IX86_BUILTIN_PSLLVV16HI,
30067 IX86_BUILTIN_PSLLVV8HI,
30068 IX86_BUILTIN_PACKSSDW256_MASK,
30069 IX86_BUILTIN_PACKSSDW128_MASK,
30070 IX86_BUILTIN_PACKUSDW256_MASK,
30071 IX86_BUILTIN_PACKUSDW128_MASK,
30072 IX86_BUILTIN_PAVGB256_MASK,
30073 IX86_BUILTIN_PAVGW256_MASK,
30074 IX86_BUILTIN_PAVGB128_MASK,
30075 IX86_BUILTIN_PAVGW128_MASK,
30076 IX86_BUILTIN_VPERMVARSF256_MASK,
30077 IX86_BUILTIN_VPERMVARDF256_MASK,
30078 IX86_BUILTIN_VPERMDF256_MASK,
30079 IX86_BUILTIN_PABSB256_MASK,
30080 IX86_BUILTIN_PABSB128_MASK,
30081 IX86_BUILTIN_PABSW256_MASK,
30082 IX86_BUILTIN_PABSW128_MASK,
30083 IX86_BUILTIN_VPERMILVARPD_MASK,
30084 IX86_BUILTIN_VPERMILVARPS_MASK,
30085 IX86_BUILTIN_VPERMILVARPD256_MASK,
30086 IX86_BUILTIN_VPERMILVARPS256_MASK,
30087 IX86_BUILTIN_VPERMILPD_MASK,
30088 IX86_BUILTIN_VPERMILPS_MASK,
30089 IX86_BUILTIN_VPERMILPD256_MASK,
30090 IX86_BUILTIN_VPERMILPS256_MASK,
30091 IX86_BUILTIN_BLENDMQ256,
30092 IX86_BUILTIN_BLENDMD256,
30093 IX86_BUILTIN_BLENDMPD256,
30094 IX86_BUILTIN_BLENDMPS256,
30095 IX86_BUILTIN_BLENDMQ128,
30096 IX86_BUILTIN_BLENDMD128,
30097 IX86_BUILTIN_BLENDMPD128,
30098 IX86_BUILTIN_BLENDMPS128,
30099 IX86_BUILTIN_BLENDMW256,
30100 IX86_BUILTIN_BLENDMB256,
30101 IX86_BUILTIN_BLENDMW128,
30102 IX86_BUILTIN_BLENDMB128,
30103 IX86_BUILTIN_PMULLD256_MASK,
30104 IX86_BUILTIN_PMULLD128_MASK,
30105 IX86_BUILTIN_PMULUDQ256_MASK,
30106 IX86_BUILTIN_PMULDQ256_MASK,
30107 IX86_BUILTIN_PMULDQ128_MASK,
30108 IX86_BUILTIN_PMULUDQ128_MASK,
30109 IX86_BUILTIN_CVTPD2PS256_MASK,
30110 IX86_BUILTIN_CVTPD2PS_MASK,
30111 IX86_BUILTIN_VPERMVARSI256_MASK,
30112 IX86_BUILTIN_VPERMVARDI256_MASK,
30113 IX86_BUILTIN_VPERMDI256_MASK,
30114 IX86_BUILTIN_CMPQ256,
30115 IX86_BUILTIN_CMPD256,
30116 IX86_BUILTIN_UCMPQ256,
30117 IX86_BUILTIN_UCMPD256,
30118 IX86_BUILTIN_CMPB256,
30119 IX86_BUILTIN_CMPW256,
30120 IX86_BUILTIN_UCMPB256,
30121 IX86_BUILTIN_UCMPW256,
30122 IX86_BUILTIN_CMPPD256_MASK,
30123 IX86_BUILTIN_CMPPS256_MASK,
30124 IX86_BUILTIN_CMPQ128,
30125 IX86_BUILTIN_CMPD128,
30126 IX86_BUILTIN_UCMPQ128,
30127 IX86_BUILTIN_UCMPD128,
30128 IX86_BUILTIN_CMPB128,
30129 IX86_BUILTIN_CMPW128,
30130 IX86_BUILTIN_UCMPB128,
30131 IX86_BUILTIN_UCMPW128,
30132 IX86_BUILTIN_CMPPD128_MASK,
30133 IX86_BUILTIN_CMPPS128_MASK,
30135 IX86_BUILTIN_GATHER3SIV8SF,
30136 IX86_BUILTIN_GATHER3SIV4SF,
30137 IX86_BUILTIN_GATHER3SIV4DF,
30138 IX86_BUILTIN_GATHER3SIV2DF,
30139 IX86_BUILTIN_GATHER3DIV8SF,
30140 IX86_BUILTIN_GATHER3DIV4SF,
30141 IX86_BUILTIN_GATHER3DIV4DF,
30142 IX86_BUILTIN_GATHER3DIV2DF,
30143 IX86_BUILTIN_GATHER3SIV8SI,
30144 IX86_BUILTIN_GATHER3SIV4SI,
30145 IX86_BUILTIN_GATHER3SIV4DI,
30146 IX86_BUILTIN_GATHER3SIV2DI,
30147 IX86_BUILTIN_GATHER3DIV8SI,
30148 IX86_BUILTIN_GATHER3DIV4SI,
30149 IX86_BUILTIN_GATHER3DIV4DI,
30150 IX86_BUILTIN_GATHER3DIV2DI,
30151 IX86_BUILTIN_SCATTERSIV8SF,
30152 IX86_BUILTIN_SCATTERSIV4SF,
30153 IX86_BUILTIN_SCATTERSIV4DF,
30154 IX86_BUILTIN_SCATTERSIV2DF,
30155 IX86_BUILTIN_SCATTERDIV8SF,
30156 IX86_BUILTIN_SCATTERDIV4SF,
30157 IX86_BUILTIN_SCATTERDIV4DF,
30158 IX86_BUILTIN_SCATTERDIV2DF,
30159 IX86_BUILTIN_SCATTERSIV8SI,
30160 IX86_BUILTIN_SCATTERSIV4SI,
30161 IX86_BUILTIN_SCATTERSIV4DI,
30162 IX86_BUILTIN_SCATTERSIV2DI,
30163 IX86_BUILTIN_SCATTERDIV8SI,
30164 IX86_BUILTIN_SCATTERDIV4SI,
30165 IX86_BUILTIN_SCATTERDIV4DI,
30166 IX86_BUILTIN_SCATTERDIV2DI,
30168 /* AVX512DQ. */
30169 IX86_BUILTIN_RANGESD128,
30170 IX86_BUILTIN_RANGESS128,
30171 IX86_BUILTIN_KUNPCKWD,
30172 IX86_BUILTIN_KUNPCKDQ,
30173 IX86_BUILTIN_BROADCASTF32x2_512,
30174 IX86_BUILTIN_BROADCASTI32x2_512,
30175 IX86_BUILTIN_BROADCASTF64X2_512,
30176 IX86_BUILTIN_BROADCASTI64X2_512,
30177 IX86_BUILTIN_BROADCASTF32X8_512,
30178 IX86_BUILTIN_BROADCASTI32X8_512,
30179 IX86_BUILTIN_EXTRACTF64X2_512,
30180 IX86_BUILTIN_EXTRACTF32X8,
30181 IX86_BUILTIN_EXTRACTI64X2_512,
30182 IX86_BUILTIN_EXTRACTI32X8,
30183 IX86_BUILTIN_REDUCEPD512_MASK,
30184 IX86_BUILTIN_REDUCEPS512_MASK,
30185 IX86_BUILTIN_PMULLQ512,
30186 IX86_BUILTIN_XORPD512,
30187 IX86_BUILTIN_XORPS512,
30188 IX86_BUILTIN_ORPD512,
30189 IX86_BUILTIN_ORPS512,
30190 IX86_BUILTIN_ANDPD512,
30191 IX86_BUILTIN_ANDPS512,
30192 IX86_BUILTIN_ANDNPD512,
30193 IX86_BUILTIN_ANDNPS512,
30194 IX86_BUILTIN_INSERTF32X8,
30195 IX86_BUILTIN_INSERTI32X8,
30196 IX86_BUILTIN_INSERTF64X2_512,
30197 IX86_BUILTIN_INSERTI64X2_512,
30198 IX86_BUILTIN_FPCLASSPD512,
30199 IX86_BUILTIN_FPCLASSPS512,
30200 IX86_BUILTIN_CVTD2MASK512,
30201 IX86_BUILTIN_CVTQ2MASK512,
30202 IX86_BUILTIN_CVTMASK2D512,
30203 IX86_BUILTIN_CVTMASK2Q512,
30204 IX86_BUILTIN_CVTPD2QQ512,
30205 IX86_BUILTIN_CVTPS2QQ512,
30206 IX86_BUILTIN_CVTPD2UQQ512,
30207 IX86_BUILTIN_CVTPS2UQQ512,
30208 IX86_BUILTIN_CVTQQ2PS512,
30209 IX86_BUILTIN_CVTUQQ2PS512,
30210 IX86_BUILTIN_CVTQQ2PD512,
30211 IX86_BUILTIN_CVTUQQ2PD512,
30212 IX86_BUILTIN_CVTTPS2QQ512,
30213 IX86_BUILTIN_CVTTPS2UQQ512,
30214 IX86_BUILTIN_CVTTPD2QQ512,
30215 IX86_BUILTIN_CVTTPD2UQQ512,
30216 IX86_BUILTIN_RANGEPS512,
30217 IX86_BUILTIN_RANGEPD512,
30219 /* AVX512BW. */
30220 IX86_BUILTIN_PACKUSDW512,
30221 IX86_BUILTIN_PACKSSDW512,
30222 IX86_BUILTIN_LOADDQUHI512_MASK,
30223 IX86_BUILTIN_LOADDQUQI512_MASK,
30224 IX86_BUILTIN_PSLLDQ512,
30225 IX86_BUILTIN_PSRLDQ512,
30226 IX86_BUILTIN_STOREDQUHI512_MASK,
30227 IX86_BUILTIN_STOREDQUQI512_MASK,
30228 IX86_BUILTIN_PALIGNR512,
30229 IX86_BUILTIN_PALIGNR512_MASK,
30230 IX86_BUILTIN_MOVDQUHI512_MASK,
30231 IX86_BUILTIN_MOVDQUQI512_MASK,
30232 IX86_BUILTIN_PSADBW512,
30233 IX86_BUILTIN_DBPSADBW512,
30234 IX86_BUILTIN_PBROADCASTB512,
30235 IX86_BUILTIN_PBROADCASTB512_GPR,
30236 IX86_BUILTIN_PBROADCASTW512,
30237 IX86_BUILTIN_PBROADCASTW512_GPR,
30238 IX86_BUILTIN_PMOVSXBW512_MASK,
30239 IX86_BUILTIN_PMOVZXBW512_MASK,
30240 IX86_BUILTIN_VPERMVARHI512_MASK,
30241 IX86_BUILTIN_VPERMT2VARHI512,
30242 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30243 IX86_BUILTIN_VPERMI2VARHI512,
30244 IX86_BUILTIN_PAVGB512,
30245 IX86_BUILTIN_PAVGW512,
30246 IX86_BUILTIN_PADDB512,
30247 IX86_BUILTIN_PSUBB512,
30248 IX86_BUILTIN_PSUBSB512,
30249 IX86_BUILTIN_PADDSB512,
30250 IX86_BUILTIN_PSUBUSB512,
30251 IX86_BUILTIN_PADDUSB512,
30252 IX86_BUILTIN_PSUBW512,
30253 IX86_BUILTIN_PADDW512,
30254 IX86_BUILTIN_PSUBSW512,
30255 IX86_BUILTIN_PADDSW512,
30256 IX86_BUILTIN_PSUBUSW512,
30257 IX86_BUILTIN_PADDUSW512,
30258 IX86_BUILTIN_PMAXUW512,
30259 IX86_BUILTIN_PMAXSW512,
30260 IX86_BUILTIN_PMINUW512,
30261 IX86_BUILTIN_PMINSW512,
30262 IX86_BUILTIN_PMAXUB512,
30263 IX86_BUILTIN_PMAXSB512,
30264 IX86_BUILTIN_PMINUB512,
30265 IX86_BUILTIN_PMINSB512,
30266 IX86_BUILTIN_PMOVWB512,
30267 IX86_BUILTIN_PMOVSWB512,
30268 IX86_BUILTIN_PMOVUSWB512,
30269 IX86_BUILTIN_PMULHRSW512_MASK,
30270 IX86_BUILTIN_PMULHUW512_MASK,
30271 IX86_BUILTIN_PMULHW512_MASK,
30272 IX86_BUILTIN_PMULLW512_MASK,
30273 IX86_BUILTIN_PSLLWI512_MASK,
30274 IX86_BUILTIN_PSLLW512_MASK,
30275 IX86_BUILTIN_PACKSSWB512,
30276 IX86_BUILTIN_PACKUSWB512,
30277 IX86_BUILTIN_PSRAVV32HI,
30278 IX86_BUILTIN_PMADDUBSW512_MASK,
30279 IX86_BUILTIN_PMADDWD512_MASK,
30280 IX86_BUILTIN_PSRLVV32HI,
30281 IX86_BUILTIN_PUNPCKHBW512,
30282 IX86_BUILTIN_PUNPCKHWD512,
30283 IX86_BUILTIN_PUNPCKLBW512,
30284 IX86_BUILTIN_PUNPCKLWD512,
30285 IX86_BUILTIN_PSHUFB512,
30286 IX86_BUILTIN_PSHUFHW512,
30287 IX86_BUILTIN_PSHUFLW512,
30288 IX86_BUILTIN_PSRAWI512,
30289 IX86_BUILTIN_PSRAW512,
30290 IX86_BUILTIN_PSRLWI512,
30291 IX86_BUILTIN_PSRLW512,
30292 IX86_BUILTIN_CVTB2MASK512,
30293 IX86_BUILTIN_CVTW2MASK512,
30294 IX86_BUILTIN_CVTMASK2B512,
30295 IX86_BUILTIN_CVTMASK2W512,
30296 IX86_BUILTIN_PCMPEQB512_MASK,
30297 IX86_BUILTIN_PCMPEQW512_MASK,
30298 IX86_BUILTIN_PCMPGTB512_MASK,
30299 IX86_BUILTIN_PCMPGTW512_MASK,
30300 IX86_BUILTIN_PTESTMB512,
30301 IX86_BUILTIN_PTESTMW512,
30302 IX86_BUILTIN_PTESTNMB512,
30303 IX86_BUILTIN_PTESTNMW512,
30304 IX86_BUILTIN_PSLLVV32HI,
30305 IX86_BUILTIN_PABSB512,
30306 IX86_BUILTIN_PABSW512,
30307 IX86_BUILTIN_BLENDMW512,
30308 IX86_BUILTIN_BLENDMB512,
30309 IX86_BUILTIN_CMPB512,
30310 IX86_BUILTIN_CMPW512,
30311 IX86_BUILTIN_UCMPB512,
30312 IX86_BUILTIN_UCMPW512,
30314 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30315 where all operands are 32-byte or 64-byte wide respectively. */
30316 IX86_BUILTIN_GATHERALTSIV4DF,
30317 IX86_BUILTIN_GATHERALTDIV8SF,
30318 IX86_BUILTIN_GATHERALTSIV4DI,
30319 IX86_BUILTIN_GATHERALTDIV8SI,
30320 IX86_BUILTIN_GATHER3ALTDIV16SF,
30321 IX86_BUILTIN_GATHER3ALTDIV16SI,
30322 IX86_BUILTIN_GATHER3ALTSIV4DF,
30323 IX86_BUILTIN_GATHER3ALTDIV8SF,
30324 IX86_BUILTIN_GATHER3ALTSIV4DI,
30325 IX86_BUILTIN_GATHER3ALTDIV8SI,
30326 IX86_BUILTIN_GATHER3ALTSIV8DF,
30327 IX86_BUILTIN_GATHER3ALTSIV8DI,
30328 IX86_BUILTIN_GATHER3DIV16SF,
30329 IX86_BUILTIN_GATHER3DIV16SI,
30330 IX86_BUILTIN_GATHER3DIV8DF,
30331 IX86_BUILTIN_GATHER3DIV8DI,
30332 IX86_BUILTIN_GATHER3SIV16SF,
30333 IX86_BUILTIN_GATHER3SIV16SI,
30334 IX86_BUILTIN_GATHER3SIV8DF,
30335 IX86_BUILTIN_GATHER3SIV8DI,
30336 IX86_BUILTIN_SCATTERDIV16SF,
30337 IX86_BUILTIN_SCATTERDIV16SI,
30338 IX86_BUILTIN_SCATTERDIV8DF,
30339 IX86_BUILTIN_SCATTERDIV8DI,
30340 IX86_BUILTIN_SCATTERSIV16SF,
30341 IX86_BUILTIN_SCATTERSIV16SI,
30342 IX86_BUILTIN_SCATTERSIV8DF,
30343 IX86_BUILTIN_SCATTERSIV8DI,
30345 /* AVX512PF */
30346 IX86_BUILTIN_GATHERPFQPD,
30347 IX86_BUILTIN_GATHERPFDPS,
30348 IX86_BUILTIN_GATHERPFDPD,
30349 IX86_BUILTIN_GATHERPFQPS,
30350 IX86_BUILTIN_SCATTERPFDPD,
30351 IX86_BUILTIN_SCATTERPFDPS,
30352 IX86_BUILTIN_SCATTERPFQPD,
30353 IX86_BUILTIN_SCATTERPFQPS,
30355 /* AVX-512ER */
30356 IX86_BUILTIN_EXP2PD_MASK,
30357 IX86_BUILTIN_EXP2PS_MASK,
30358 IX86_BUILTIN_EXP2PS,
30359 IX86_BUILTIN_RCP28PD,
30360 IX86_BUILTIN_RCP28PS,
30361 IX86_BUILTIN_RCP28SD,
30362 IX86_BUILTIN_RCP28SS,
30363 IX86_BUILTIN_RSQRT28PD,
30364 IX86_BUILTIN_RSQRT28PS,
30365 IX86_BUILTIN_RSQRT28SD,
30366 IX86_BUILTIN_RSQRT28SS,
30368 /* AVX-512IFMA */
30369 IX86_BUILTIN_VPMADD52LUQ512,
30370 IX86_BUILTIN_VPMADD52HUQ512,
30371 IX86_BUILTIN_VPMADD52LUQ256,
30372 IX86_BUILTIN_VPMADD52HUQ256,
30373 IX86_BUILTIN_VPMADD52LUQ128,
30374 IX86_BUILTIN_VPMADD52HUQ128,
30375 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30376 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30377 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30378 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30379 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30380 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30382 /* AVX-512VBMI */
30383 IX86_BUILTIN_VPMULTISHIFTQB512,
30384 IX86_BUILTIN_VPMULTISHIFTQB256,
30385 IX86_BUILTIN_VPMULTISHIFTQB128,
30386 IX86_BUILTIN_VPERMVARQI512_MASK,
30387 IX86_BUILTIN_VPERMT2VARQI512,
30388 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30389 IX86_BUILTIN_VPERMI2VARQI512,
30390 IX86_BUILTIN_VPERMVARQI256_MASK,
30391 IX86_BUILTIN_VPERMVARQI128_MASK,
30392 IX86_BUILTIN_VPERMT2VARQI256,
30393 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30394 IX86_BUILTIN_VPERMT2VARQI128,
30395 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30396 IX86_BUILTIN_VPERMI2VARQI256,
30397 IX86_BUILTIN_VPERMI2VARQI128,
30399 /* SHA builtins. */
30400 IX86_BUILTIN_SHA1MSG1,
30401 IX86_BUILTIN_SHA1MSG2,
30402 IX86_BUILTIN_SHA1NEXTE,
30403 IX86_BUILTIN_SHA1RNDS4,
30404 IX86_BUILTIN_SHA256MSG1,
30405 IX86_BUILTIN_SHA256MSG2,
30406 IX86_BUILTIN_SHA256RNDS2,
30408 /* CLWB instructions. */
30409 IX86_BUILTIN_CLWB,
30411 /* PCOMMIT instructions. */
30412 IX86_BUILTIN_PCOMMIT,
30414 /* CLFLUSHOPT instructions. */
30415 IX86_BUILTIN_CLFLUSHOPT,
30417 /* TFmode support builtins. */
30418 IX86_BUILTIN_INFQ,
30419 IX86_BUILTIN_HUGE_VALQ,
30420 IX86_BUILTIN_FABSQ,
30421 IX86_BUILTIN_COPYSIGNQ,
30423 /* Vectorizer support builtins. */
30424 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30425 IX86_BUILTIN_CPYSGNPS,
30426 IX86_BUILTIN_CPYSGNPD,
30427 IX86_BUILTIN_CPYSGNPS256,
30428 IX86_BUILTIN_CPYSGNPS512,
30429 IX86_BUILTIN_CPYSGNPD256,
30430 IX86_BUILTIN_CPYSGNPD512,
30431 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30432 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30435 /* FMA4 instructions. */
30436 IX86_BUILTIN_VFMADDSS,
30437 IX86_BUILTIN_VFMADDSD,
30438 IX86_BUILTIN_VFMADDPS,
30439 IX86_BUILTIN_VFMADDPD,
30440 IX86_BUILTIN_VFMADDPS256,
30441 IX86_BUILTIN_VFMADDPD256,
30442 IX86_BUILTIN_VFMADDSUBPS,
30443 IX86_BUILTIN_VFMADDSUBPD,
30444 IX86_BUILTIN_VFMADDSUBPS256,
30445 IX86_BUILTIN_VFMADDSUBPD256,
30447 /* FMA3 instructions. */
30448 IX86_BUILTIN_VFMADDSS3,
30449 IX86_BUILTIN_VFMADDSD3,
30451 /* XOP instructions. */
30452 IX86_BUILTIN_VPCMOV,
30453 IX86_BUILTIN_VPCMOV_V2DI,
30454 IX86_BUILTIN_VPCMOV_V4SI,
30455 IX86_BUILTIN_VPCMOV_V8HI,
30456 IX86_BUILTIN_VPCMOV_V16QI,
30457 IX86_BUILTIN_VPCMOV_V4SF,
30458 IX86_BUILTIN_VPCMOV_V2DF,
30459 IX86_BUILTIN_VPCMOV256,
30460 IX86_BUILTIN_VPCMOV_V4DI256,
30461 IX86_BUILTIN_VPCMOV_V8SI256,
30462 IX86_BUILTIN_VPCMOV_V16HI256,
30463 IX86_BUILTIN_VPCMOV_V32QI256,
30464 IX86_BUILTIN_VPCMOV_V8SF256,
30465 IX86_BUILTIN_VPCMOV_V4DF256,
30467 IX86_BUILTIN_VPPERM,
30469 IX86_BUILTIN_VPMACSSWW,
30470 IX86_BUILTIN_VPMACSWW,
30471 IX86_BUILTIN_VPMACSSWD,
30472 IX86_BUILTIN_VPMACSWD,
30473 IX86_BUILTIN_VPMACSSDD,
30474 IX86_BUILTIN_VPMACSDD,
30475 IX86_BUILTIN_VPMACSSDQL,
30476 IX86_BUILTIN_VPMACSSDQH,
30477 IX86_BUILTIN_VPMACSDQL,
30478 IX86_BUILTIN_VPMACSDQH,
30479 IX86_BUILTIN_VPMADCSSWD,
30480 IX86_BUILTIN_VPMADCSWD,
30482 IX86_BUILTIN_VPHADDBW,
30483 IX86_BUILTIN_VPHADDBD,
30484 IX86_BUILTIN_VPHADDBQ,
30485 IX86_BUILTIN_VPHADDWD,
30486 IX86_BUILTIN_VPHADDWQ,
30487 IX86_BUILTIN_VPHADDDQ,
30488 IX86_BUILTIN_VPHADDUBW,
30489 IX86_BUILTIN_VPHADDUBD,
30490 IX86_BUILTIN_VPHADDUBQ,
30491 IX86_BUILTIN_VPHADDUWD,
30492 IX86_BUILTIN_VPHADDUWQ,
30493 IX86_BUILTIN_VPHADDUDQ,
30494 IX86_BUILTIN_VPHSUBBW,
30495 IX86_BUILTIN_VPHSUBWD,
30496 IX86_BUILTIN_VPHSUBDQ,
30498 IX86_BUILTIN_VPROTB,
30499 IX86_BUILTIN_VPROTW,
30500 IX86_BUILTIN_VPROTD,
30501 IX86_BUILTIN_VPROTQ,
30502 IX86_BUILTIN_VPROTB_IMM,
30503 IX86_BUILTIN_VPROTW_IMM,
30504 IX86_BUILTIN_VPROTD_IMM,
30505 IX86_BUILTIN_VPROTQ_IMM,
30507 IX86_BUILTIN_VPSHLB,
30508 IX86_BUILTIN_VPSHLW,
30509 IX86_BUILTIN_VPSHLD,
30510 IX86_BUILTIN_VPSHLQ,
30511 IX86_BUILTIN_VPSHAB,
30512 IX86_BUILTIN_VPSHAW,
30513 IX86_BUILTIN_VPSHAD,
30514 IX86_BUILTIN_VPSHAQ,
30516 IX86_BUILTIN_VFRCZSS,
30517 IX86_BUILTIN_VFRCZSD,
30518 IX86_BUILTIN_VFRCZPS,
30519 IX86_BUILTIN_VFRCZPD,
30520 IX86_BUILTIN_VFRCZPS256,
30521 IX86_BUILTIN_VFRCZPD256,
30523 IX86_BUILTIN_VPCOMEQUB,
30524 IX86_BUILTIN_VPCOMNEUB,
30525 IX86_BUILTIN_VPCOMLTUB,
30526 IX86_BUILTIN_VPCOMLEUB,
30527 IX86_BUILTIN_VPCOMGTUB,
30528 IX86_BUILTIN_VPCOMGEUB,
30529 IX86_BUILTIN_VPCOMFALSEUB,
30530 IX86_BUILTIN_VPCOMTRUEUB,
30532 IX86_BUILTIN_VPCOMEQUW,
30533 IX86_BUILTIN_VPCOMNEUW,
30534 IX86_BUILTIN_VPCOMLTUW,
30535 IX86_BUILTIN_VPCOMLEUW,
30536 IX86_BUILTIN_VPCOMGTUW,
30537 IX86_BUILTIN_VPCOMGEUW,
30538 IX86_BUILTIN_VPCOMFALSEUW,
30539 IX86_BUILTIN_VPCOMTRUEUW,
30541 IX86_BUILTIN_VPCOMEQUD,
30542 IX86_BUILTIN_VPCOMNEUD,
30543 IX86_BUILTIN_VPCOMLTUD,
30544 IX86_BUILTIN_VPCOMLEUD,
30545 IX86_BUILTIN_VPCOMGTUD,
30546 IX86_BUILTIN_VPCOMGEUD,
30547 IX86_BUILTIN_VPCOMFALSEUD,
30548 IX86_BUILTIN_VPCOMTRUEUD,
30550 IX86_BUILTIN_VPCOMEQUQ,
30551 IX86_BUILTIN_VPCOMNEUQ,
30552 IX86_BUILTIN_VPCOMLTUQ,
30553 IX86_BUILTIN_VPCOMLEUQ,
30554 IX86_BUILTIN_VPCOMGTUQ,
30555 IX86_BUILTIN_VPCOMGEUQ,
30556 IX86_BUILTIN_VPCOMFALSEUQ,
30557 IX86_BUILTIN_VPCOMTRUEUQ,
30559 IX86_BUILTIN_VPCOMEQB,
30560 IX86_BUILTIN_VPCOMNEB,
30561 IX86_BUILTIN_VPCOMLTB,
30562 IX86_BUILTIN_VPCOMLEB,
30563 IX86_BUILTIN_VPCOMGTB,
30564 IX86_BUILTIN_VPCOMGEB,
30565 IX86_BUILTIN_VPCOMFALSEB,
30566 IX86_BUILTIN_VPCOMTRUEB,
30568 IX86_BUILTIN_VPCOMEQW,
30569 IX86_BUILTIN_VPCOMNEW,
30570 IX86_BUILTIN_VPCOMLTW,
30571 IX86_BUILTIN_VPCOMLEW,
30572 IX86_BUILTIN_VPCOMGTW,
30573 IX86_BUILTIN_VPCOMGEW,
30574 IX86_BUILTIN_VPCOMFALSEW,
30575 IX86_BUILTIN_VPCOMTRUEW,
30577 IX86_BUILTIN_VPCOMEQD,
30578 IX86_BUILTIN_VPCOMNED,
30579 IX86_BUILTIN_VPCOMLTD,
30580 IX86_BUILTIN_VPCOMLED,
30581 IX86_BUILTIN_VPCOMGTD,
30582 IX86_BUILTIN_VPCOMGED,
30583 IX86_BUILTIN_VPCOMFALSED,
30584 IX86_BUILTIN_VPCOMTRUED,
30586 IX86_BUILTIN_VPCOMEQQ,
30587 IX86_BUILTIN_VPCOMNEQ,
30588 IX86_BUILTIN_VPCOMLTQ,
30589 IX86_BUILTIN_VPCOMLEQ,
30590 IX86_BUILTIN_VPCOMGTQ,
30591 IX86_BUILTIN_VPCOMGEQ,
30592 IX86_BUILTIN_VPCOMFALSEQ,
30593 IX86_BUILTIN_VPCOMTRUEQ,
30595 /* LWP instructions. */
30596 IX86_BUILTIN_LLWPCB,
30597 IX86_BUILTIN_SLWPCB,
30598 IX86_BUILTIN_LWPVAL32,
30599 IX86_BUILTIN_LWPVAL64,
30600 IX86_BUILTIN_LWPINS32,
30601 IX86_BUILTIN_LWPINS64,
30603 IX86_BUILTIN_CLZS,
30605 /* RTM */
30606 IX86_BUILTIN_XBEGIN,
30607 IX86_BUILTIN_XEND,
30608 IX86_BUILTIN_XABORT,
30609 IX86_BUILTIN_XTEST,
30611 /* MPX */
30612 IX86_BUILTIN_BNDMK,
30613 IX86_BUILTIN_BNDSTX,
30614 IX86_BUILTIN_BNDLDX,
30615 IX86_BUILTIN_BNDCL,
30616 IX86_BUILTIN_BNDCU,
30617 IX86_BUILTIN_BNDRET,
30618 IX86_BUILTIN_BNDNARROW,
30619 IX86_BUILTIN_BNDINT,
30620 IX86_BUILTIN_SIZEOF,
30621 IX86_BUILTIN_BNDLOWER,
30622 IX86_BUILTIN_BNDUPPER,
30624 /* BMI instructions. */
30625 IX86_BUILTIN_BEXTR32,
30626 IX86_BUILTIN_BEXTR64,
30627 IX86_BUILTIN_CTZS,
30629 /* TBM instructions. */
30630 IX86_BUILTIN_BEXTRI32,
30631 IX86_BUILTIN_BEXTRI64,
30633 /* BMI2 instructions. */
30634 IX86_BUILTIN_BZHI32,
30635 IX86_BUILTIN_BZHI64,
30636 IX86_BUILTIN_PDEP32,
30637 IX86_BUILTIN_PDEP64,
30638 IX86_BUILTIN_PEXT32,
30639 IX86_BUILTIN_PEXT64,
30641 /* ADX instructions. */
30642 IX86_BUILTIN_ADDCARRYX32,
30643 IX86_BUILTIN_ADDCARRYX64,
30645 /* SBB instructions. */
30646 IX86_BUILTIN_SBB32,
30647 IX86_BUILTIN_SBB64,
30649 /* FSGSBASE instructions. */
30650 IX86_BUILTIN_RDFSBASE32,
30651 IX86_BUILTIN_RDFSBASE64,
30652 IX86_BUILTIN_RDGSBASE32,
30653 IX86_BUILTIN_RDGSBASE64,
30654 IX86_BUILTIN_WRFSBASE32,
30655 IX86_BUILTIN_WRFSBASE64,
30656 IX86_BUILTIN_WRGSBASE32,
30657 IX86_BUILTIN_WRGSBASE64,
30659 /* RDRND instructions. */
30660 IX86_BUILTIN_RDRAND16_STEP,
30661 IX86_BUILTIN_RDRAND32_STEP,
30662 IX86_BUILTIN_RDRAND64_STEP,
30664 /* RDSEED instructions. */
30665 IX86_BUILTIN_RDSEED16_STEP,
30666 IX86_BUILTIN_RDSEED32_STEP,
30667 IX86_BUILTIN_RDSEED64_STEP,
30669 /* F16C instructions. */
30670 IX86_BUILTIN_CVTPH2PS,
30671 IX86_BUILTIN_CVTPH2PS256,
30672 IX86_BUILTIN_CVTPS2PH,
30673 IX86_BUILTIN_CVTPS2PH256,
30675 /* MONITORX and MWAITX instrucions. */
30676 IX86_BUILTIN_MONITORX,
30677 IX86_BUILTIN_MWAITX,
30679 /* CFString built-in for darwin */
30680 IX86_BUILTIN_CFSTRING,
30682 /* Builtins to get CPU type and supported features. */
30683 IX86_BUILTIN_CPU_INIT,
30684 IX86_BUILTIN_CPU_IS,
30685 IX86_BUILTIN_CPU_SUPPORTS,
30687 /* Read/write FLAGS register built-ins. */
30688 IX86_BUILTIN_READ_FLAGS,
30689 IX86_BUILTIN_WRITE_FLAGS,
30691 IX86_BUILTIN_MAX
30692 };
30694 /* Table for the ix86 builtin decls. */
30697 /* Table of all of the builtin functions that are possible with different ISA's
30698 but are waiting to be built until a function is declared to use that
30699 ISA. */
30708 };
30712 /* Bits that can still enable any inclusion of a builtin. */
30715 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30716 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30717 function decl in the ix86_builtins array. Returns the function decl or
30718 NULL_TREE, if the builtin was not added.
30720 If the front end has a special hook for builtin functions, delay adding
30721 builtin functions that aren't in the current ISA until the ISA is changed
30722 with function specific optimization. Doing so, can save about 300K for the
30723 default compiler. When the builtin is expanded, check at that time whether
30724 it is valid.
30726 If the front end doesn't have a special hook, record all builtins, even if
30727 it isn't an instruction set in the current ISA in case the user uses
30728 function specific options for a different ISA, so that we don't get scope
30729 errors if a builtin is added in the middle of a function scope. */
30735 {
30739 {
30748 {
30754 }
30755 else
30756 {
30757 /* Just a MASK where set_and_not_built_p == true can potentially
30758 include a builtin. */
30767 }
30768 }
30771 }
30773 /* Like def_builtin, but also marks the function decl "const". */
30778 {
30782 else
30786 }
30788 /* Add any new builtin functions for a given ISA that may not have been
30789 declared. This saves a bit of space compared to adding all of the
30790 declarations to the tree, even if we didn't use them. */
30792 static void
30794 {
30798 /* Bits in ISA value can be removed from potential isa values. */
30806 {
30809 {
30812 /* Don't define the builtin again. */
30818 NULL_TREE);
30825 NULL_TREE);
30828 }
30829 }
30832 }
30834 /* Bits for builtin_description.flag. */
30836 /* Set when we don't support the comparison natively, and should
30837 swap_comparison in order to support it. */
30838 #define BUILTIN_DESC_SWAP_OPERANDS 1
30840 struct builtin_description
30841 {
30848 };
30851 {
30852 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30853 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30854 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30855 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30856 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30857 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30858 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30859 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30860 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30861 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30862 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30863 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30864 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30865 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30866 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30867 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30868 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30870 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30871 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30872 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30875 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30876 };
30879 {
30880 /* SSE4.2 */
30881 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30882 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30883 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30884 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30885 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30886 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30887 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30888 };
30891 {
30892 /* SSE4.2 */
30893 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30894 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30895 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30896 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30897 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30898 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30899 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30900 };
30902 /* Special builtins with variable number of arguments. */
30904 {
30905 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30906 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30907 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30909 /* 80387 (for use internally for atomic compound assignment). */
30910 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30911 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30912 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30913 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30915 /* MMX */
30916 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30918 /* 3DNow! */
30919 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30921 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30922 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30923 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30924 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30925 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30926 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30927 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30928 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30929 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30931 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30932 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30933 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30934 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30935 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30936 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30937 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30938 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30940 /* SSE */
30941 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30942 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30943 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30945 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30946 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30947 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30948 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30950 /* SSE or 3DNow!A */
30951 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30952 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30954 /* SSE2 */
30955 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30956 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30957 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30958 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30959 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30960 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30961 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30962 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30963 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30966 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30969 /* SSE3 */
30970 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30972 /* SSE4.1 */
30973 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30975 /* SSE4A */
30976 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30977 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30979 /* AVX */
30980 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30981 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30983 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30984 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30985 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30986 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30987 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30989 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30990 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30991 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30992 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30993 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30994 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30995 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30997 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30998 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30999 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
31001 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
31002 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
31003 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
31004 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
31005 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
31006 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
31007 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
31008 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
31010 /* AVX2 */
31011 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
31012 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
31013 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
31014 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
31015 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
31016 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
31017 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
31018 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
31019 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
31021 /* AVX512F */
31022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
31023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
31024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
31025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
31026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
31043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
31044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
31045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
31046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
31047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
31048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
31049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
31050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
31051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
31052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
31053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
31054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
31055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
31056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
31057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
31058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
31059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
31060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
31061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
31062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
31063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
31064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
31065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
31066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
31067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
31068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
31070 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
31071 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
31072 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
31073 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
31074 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
31075 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
31077 /* FSGSBASE */
31078 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31079 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31080 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31081 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31082 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31083 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31084 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31085 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31087 /* RTM */
31088 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31089 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
31090 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
31092 /* AVX512BW */
31093 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
31094 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
31095 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
31096 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
31098 /* AVX512VL */
31099 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
31100 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
31101 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
31102 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
31103 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31104 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31105 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31106 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31107 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31108 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31109 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31110 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31111 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31112 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31113 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31114 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31115 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31116 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31117 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31118 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31119 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31120 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31121 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31122 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31123 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31124 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31125 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31126 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31127 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31128 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31129 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31130 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31131 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31132 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31133 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31134 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31135 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
31136 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
31137 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
31138 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
31139 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31140 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31141 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31142 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31143 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31144 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31145 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31146 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31147 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31148 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31149 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31150 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31151 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31152 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31153 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31154 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31155 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31156 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31159 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31162 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31163 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31164 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31194 /* PCOMMIT. */
31195 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
31196 };
31198 /* Builtins with variable number of arguments. */
31200 {
31201 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
31202 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31203 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31204 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31205 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31206 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31207 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31209 /* MMX */
31210 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31211 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31212 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31213 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31214 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31215 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31217 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31218 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31219 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31220 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31221 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31222 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31223 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31224 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31226 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31227 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31229 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31230 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31231 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31232 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31234 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31235 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31236 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31237 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31238 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31241 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31242 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31243 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31244 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31245 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31246 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31248 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31249 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31250 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31252 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31254 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31255 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31256 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31257 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31258 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31259 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31261 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31262 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31263 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31264 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31265 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31266 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31268 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31269 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31270 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31271 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31273 /* 3DNow! */
31274 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31275 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31276 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31277 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31279 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31280 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31281 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31282 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31283 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31284 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31285 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31286 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31287 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31288 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31289 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31290 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31291 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31292 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31293 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31295 /* 3DNow!A */
31296 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31297 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31298 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31299 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31300 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31301 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31303 /* SSE */
31304 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31305 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31306 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31308 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31309 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31310 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31311 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31312 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31313 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31314 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31315 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31317 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31319 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31320 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31321 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31322 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31323 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31324 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31325 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31326 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31328 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31329 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31330 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31331 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31332 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31333 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31334 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31335 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31336 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31337 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31338 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31339 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31340 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31341 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31342 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31343 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31344 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31345 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31346 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31347 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31349 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31350 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31351 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31352 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31354 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31355 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31356 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31357 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31359 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31361 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31362 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31363 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31364 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31365 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31367 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31368 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31369 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31371 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31373 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31374 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31375 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31377 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31378 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31380 /* SSE MMX or 3Dnow!A */
31381 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31382 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31383 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31385 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31386 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31387 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31388 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31390 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31391 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31393 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31395 /* SSE2 */
31396 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31398 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31402 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31414 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31415 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31417 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31419 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31421 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31422 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31423 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31424 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31426 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31428 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31431 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31433 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31434 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31435 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31436 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31438 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31439 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31445 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31448 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31449 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31452 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31456 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31458 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31459 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31461 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31464 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31465 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31467 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31469 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31470 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31471 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31472 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31473 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31474 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31475 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31476 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31481 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31483 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31484 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31487 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31488 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31490 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31491 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31492 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31493 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31496 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31505 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31506 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31507 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31510 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31511 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31512 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31513 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31514 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31515 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31516 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31517 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31519 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31523 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31526 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31527 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31529 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31532 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31537 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31538 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31539 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31540 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31541 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31542 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31545 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31546 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31547 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31548 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31549 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31550 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31552 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31553 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31554 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31555 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31557 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31558 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31559 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31561 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31563 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31565 /* SSE2 MMX */
31566 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31567 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31569 /* SSE3 */
31570 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31571 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31573 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31574 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31575 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31576 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31577 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31578 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31580 /* SSSE3 */
31581 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31582 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31583 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31584 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31585 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31586 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31588 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31589 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31590 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31591 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31592 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31593 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31594 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31595 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31596 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31597 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31598 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31599 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31600 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31601 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31602 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31603 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31604 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31605 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31606 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31607 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31608 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31609 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31610 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31611 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31613 /* SSSE3. */
31614 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31615 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31617 /* SSE4.1 */
31618 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31619 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31620 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31621 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31622 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31623 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31624 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31625 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31626 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31627 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31629 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31630 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31631 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31632 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31633 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31634 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31635 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31636 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31637 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31638 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31639 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31640 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31641 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31643 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31644 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31645 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31646 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31647 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31648 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31649 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31650 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31651 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31652 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31653 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31654 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31656 /* SSE4.1 */
31657 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31658 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31659 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31660 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31662 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31663 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31664 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31665 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31667 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31668 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31670 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31671 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31673 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31674 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31675 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31676 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31678 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31679 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31681 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31682 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31684 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31685 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31686 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31688 /* SSE4.2 */
31689 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31690 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31691 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31692 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31693 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31695 /* SSE4A */
31696 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31697 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31698 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31699 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31701 /* AES */
31702 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31703 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31705 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31706 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31707 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31708 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31710 /* PCLMUL */
31711 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31713 /* AVX */
31714 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31715 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31718 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31719 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31722 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31728 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31729 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31730 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31731 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31732 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31733 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31734 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31735 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31736 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31737 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31738 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31739 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31755 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31757 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31758 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31759 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31760 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31761 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31762 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31763 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31764 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31765 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31766 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31767 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31768 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31769 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31770 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31772 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31773 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31774 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31775 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31776 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31782 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31785 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31787 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31788 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31789 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31799 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31801 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31802 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31815 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31816 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31821 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31826 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31827 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31828 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31831 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31834 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31837 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31839 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31841 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31842 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31844 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31846 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31849 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31850 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31852 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31854 /* AVX2 */
31855 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31856 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31857 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31858 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31859 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31860 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31861 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31862 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31863 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31864 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31865 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31866 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31867 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31871 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31872 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31873 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31875 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31877 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31878 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31879 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31894 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31895 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31896 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31897 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31898 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31899 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31900 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31901 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31902 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31903 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31904 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31905 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31907 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31908 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31909 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31910 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31911 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31912 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31913 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31914 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31915 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31916 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31917 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31918 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31919 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31920 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31921 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31922 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31923 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31924 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31925 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31926 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31927 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31928 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31931 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31932 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31933 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31934 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31935 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31936 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31937 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31938 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31939 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31940 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31941 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31942 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31943 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31944 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31945 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31947 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31948 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31949 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31950 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31951 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31952 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31953 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31954 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31955 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31956 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31957 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31958 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31959 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31960 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31961 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31962 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31963 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31964 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31965 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31966 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31967 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31968 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31969 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31970 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31971 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31972 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31973 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31974 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31975 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31976 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31977 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31978 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31979 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31980 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31981 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31982 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31983 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31984 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31985 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31986 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31987 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31988 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31989 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31990 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31991 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31992 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31993 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31994 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31995 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31996 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31997 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31998 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31999 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32000 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32002 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32004 /* BMI */
32005 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32006 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32007 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32009 /* TBM */
32010 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32011 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32013 /* F16C */
32014 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
32015 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
32016 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
32017 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
32019 /* BMI2 */
32020 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32021 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32022 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32023 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32024 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32025 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32027 /* AVX512F */
32028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
32029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
32030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
32031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
32032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
32033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
32034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
32042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
32044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
32051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
32052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
32053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
32054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
32059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
32060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
32061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
32062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
32063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
32064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
32065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
32066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
32083 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
32084 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
32085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
32087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32194 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32195 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32196 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32197 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32229 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32234 /* Mask arithmetic operations */
32235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32246 /* SHA */
32247 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32248 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32249 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32250 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32251 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32252 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32253 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32255 /* AVX512VL. */
32256 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32257 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32258 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32266 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32267 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32268 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32269 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32276 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32277 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32278 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32280 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32281 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32282 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32288 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32289 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32290 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32294 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32295 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32296 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32297 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32298 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32299 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32300 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32301 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32302 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32303 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32304 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32305 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32306 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32307 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32308 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32309 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32310 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32311 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32312 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32313 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32314 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32315 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32316 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32317 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32318 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32319 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32320 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32323 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32324 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32325 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32326 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32347 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32348 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32349 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32350 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32351 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32352 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32353 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32354 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32366 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32367 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32370 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32371 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32382 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32383 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32394 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32395 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32396 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32397 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32398 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32399 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32400 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32401 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32402 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32403 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32404 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32405 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32406 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32407 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32420 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32421 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32424 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32425 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32426 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32428 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32429 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32430 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32431 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32432 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32433 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32434 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32435 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32436 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32437 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32440 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32441 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32442 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32443 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32444 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32445 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32448 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32449 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32450 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32451 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32456 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32457 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32458 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32459 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32460 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32461 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32492 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32493 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32494 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32495 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32499 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32500 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32512 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32513 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32514 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32515 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32516 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32517 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32518 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32519 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32520 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32521 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32522 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32523 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32524 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32525 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32526 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32527 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32528 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32529 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32530 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32533 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32536 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32537 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32549 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32550 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32551 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32552 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32553 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32564 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32565 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32573 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32574 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32575 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32576 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32577 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32581 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32582 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32583 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32584 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32587 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32638 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32639 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32640 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32641 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32642 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32647 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32648 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32649 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32650 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32652 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32653 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32654 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32655 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32657 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32658 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32659 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32660 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32662 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32666 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32667 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32668 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32669 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32670 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32671 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32672 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32673 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32682 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32683 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32684 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32685 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32698 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32699 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32700 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32701 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32702 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32703 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32704 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32711 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32712 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32713 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32722 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32730 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32731 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32732 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32733 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32734 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32735 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32736 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32737 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32741 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32742 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32743 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32746 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32747 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32748 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32749 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32750 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32751 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32752 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32753 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32754 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32755 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32756 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32757 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32758 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32759 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32760 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32761 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32762 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32763 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32764 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32765 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32766 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32767 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32768 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32769 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32770 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32771 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32772 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32773 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32776 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32777 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32778 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32779 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32780 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32781 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32782 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32783 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32784 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32785 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32786 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32787 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32788 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32789 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32790 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32791 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32792 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32793 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32794 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32795 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32796 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32798 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32799 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32800 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32801 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32802 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32803 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32804 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32805 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32806 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32807 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32808 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32809 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32810 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32811 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32812 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32813 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32814 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32815 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32816 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32817 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32818 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32819 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32820 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32821 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32822 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32823 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32824 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32825 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32826 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32827 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32828 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32829 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32830 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32831 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32832 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32833 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32835 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32836 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32837 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32838 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32839 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32840 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32841 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32844 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32845 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32846 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32847 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32848 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32849 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32850 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32851 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32852 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32853 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32854 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32855 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32856 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32857 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32858 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32859 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32860 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32861 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32862 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32863 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32870 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32871 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32872 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32873 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32874 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32875 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32876 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32879 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32880 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32881 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32882 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32883 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32884 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32885 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32886 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32887 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32888 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32892 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32893 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32894 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32895 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32896 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32897 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32898 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32899 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32900 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32901 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32902 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32903 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32904 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32905 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32906 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32907 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32908 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32909 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32913 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32914 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32915 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32916 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32921 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32922 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32923 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32924 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32925 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32926 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32927 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32928 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32930 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32931 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32932 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32933 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32934 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32935 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32936 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32942 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32943 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32944 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32945 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32946 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32947 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32948 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32949 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32950 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32951 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32952 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32953 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32954 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32955 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32956 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32957 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32958 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32959 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32960 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32961 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32962 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32963 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32964 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32965 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32966 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32967 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32969 /* AVX512DQ. */
32970 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32971 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32972 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32973 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32974 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32975 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32976 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32977 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32978 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32979 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32980 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32981 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32982 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32983 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32984 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32985 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32986 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32987 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32988 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32989 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32990 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32991 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32992 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32993 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32994 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32995 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32996 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32997 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32998 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32999 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
33000 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
33002 /* AVX512BW. */
33003 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
33004 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
33005 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
33006 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33007 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33008 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
33009 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
33010 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
33011 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33012 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33013 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
33014 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
33015 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
33016 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
33017 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
33018 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
33019 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
33020 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
33021 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33022 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33023 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33024 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33025 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33026 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33027 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33028 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33029 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33030 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33031 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33032 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33033 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33034 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33035 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33036 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33037 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33038 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33039 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33040 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33041 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33042 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33043 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33044 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33045 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33046 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33047 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
33048 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
33049 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
33050 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33051 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33052 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33053 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33054 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33055 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
33056 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
33057 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
33058 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33059 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
33060 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
33061 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33062 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33063 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33064 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33065 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33066 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33067 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33068 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33069 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33070 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
33071 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33072 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
33073 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
33074 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
33075 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
33076 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
33077 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33078 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33079 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33080 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33081 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33082 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33083 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33084 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33085 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33086 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33087 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33088 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33089 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33090 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33091 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33092 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33093 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33095 /* AVX512IFMA */
33096 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33097 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33098 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33099 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33100 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33101 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33102 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33103 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33104 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33105 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33106 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33107 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33109 /* AVX512VBMI */
33110 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33111 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33112 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33113 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33114 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33115 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33116 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33117 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33118 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33119 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33120 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33121 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33122 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33123 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33124 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33125 };
33127 /* Builtins with rounding support. */
33129 {
33130 /* AVX512F */
33131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
33136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
33137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
33138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
33139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
33140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
33141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
33144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
33146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
33148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
33150 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
33151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
33152 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
33153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
33154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33159 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
33160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
33161 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
33162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33211 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33213 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33215 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33217 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33219 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33221 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33223 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33225 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33251 /* AVX512ER */
33252 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33253 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33254 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33255 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33256 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33257 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33258 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33259 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33260 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33261 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33263 /* AVX512DQ. */
33264 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33265 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33266 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33267 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33268 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33269 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33270 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33271 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33272 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33273 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33274 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33275 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33276 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33277 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33278 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33279 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33280 };
33282 /* Bultins for MPX. */
33284 {
33285 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33286 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33287 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33288 };
33290 /* Const builtins for MPX. */
33292 {
33293 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33294 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33295 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33296 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33297 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33298 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33299 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33300 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33301 };
33303 /* FMA4 and XOP. */
33304 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33305 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33306 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33307 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33308 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33309 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33310 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33311 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33312 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33313 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33314 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33315 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33316 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33317 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33318 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33319 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33320 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33321 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33322 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33323 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33324 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33325 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33326 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33327 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33328 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33329 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33330 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33331 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33332 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33333 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33334 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33335 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33336 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33337 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33338 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33339 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33340 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33341 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33342 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33343 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33344 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33345 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33346 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33347 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33348 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33349 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33350 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33351 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33352 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33353 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33354 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33355 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33358 {
33399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33468 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33557 };
33558 \f
33559 /* TM vector builtins. */
33561 /* Reuse the existing x86-specific `struct builtin_description' cause
33562 we're lazy. Add casts to make them fit. */
33564 {
33565 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33566 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33567 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33568 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33569 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33570 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33571 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33573 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33574 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33575 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33576 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33577 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33578 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33579 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33581 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33582 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33583 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33584 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33585 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33586 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33587 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33589 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33590 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33591 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33592 };
33594 /* TM callbacks. */
33596 /* Return the builtin decl needed to load a vector of TYPE. */
33598 static tree
33600 {
33602 {
33604 {
33611 }
33612 }
33614 }
33616 /* Return the builtin decl needed to store a vector of TYPE. */
33618 static tree
33620 {
33622 {
33624 {
33631 }
33632 }
33634 }
33635 \f
33636 /* Initialize the transactional memory vector load/store builtins. */
33638 static void
33640 {
33644 tree decl;
33651 /* If there are no builtins defined, we must be compiling in a
33652 language without trans-mem support. */
33656 /* Use whatever attributes a normal TM load has. */
33660 /* Use whatever attributes a normal TM store has. */
33664 /* Use whatever attributes a normal TM log has. */
33672 {
33676 {
33684 {
33687 }
33689 {
33692 }
33693 else
33694 {
33697 }
33699 /* The builtin without the prefix for
33700 calling it directly. */
33702 attrs);
33703 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33704 set the TYPE_ATTRIBUTES. */
33708 }
33709 }
33710 }
33712 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33713 in the current target ISA to allow the user to compile particular modules
33714 with different target specific options that differ from the command line
33715 options. */
33716 static void
33718 {
33723 /* Add all special builtins with variable number of operands. */
33727 {
33733 }
33735 /* Add all builtins with variable number of operands. */
33739 {
33745 }
33747 /* Add all builtins with rounding. */
33751 {
33757 }
33759 /* pcmpestr[im] insns. */
33763 {
33766 else
33769 }
33771 /* pcmpistr[im] insns. */
33775 {
33778 else
33781 }
33783 /* comi/ucomi insns. */
33785 {
33788 else
33791 }
33793 /* SSE */
33799 /* SSE or 3DNow!A */
33802 IX86_BUILTIN_MASKMOVQ);
33804 /* SSE2 */
33813 /* SSE3. */
33819 /* AES */
33833 /* PCLMUL */
33837 /* RDRND */
33844 IX86_BUILTIN_RDRAND64_STEP);
33846 /* AVX2 */
33848 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33849 IX86_BUILTIN_GATHERSIV2DF);
33852 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33853 IX86_BUILTIN_GATHERSIV4DF);
33856 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33857 IX86_BUILTIN_GATHERDIV2DF);
33860 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33861 IX86_BUILTIN_GATHERDIV4DF);
33864 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33865 IX86_BUILTIN_GATHERSIV4SF);
33868 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33869 IX86_BUILTIN_GATHERSIV8SF);
33872 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33873 IX86_BUILTIN_GATHERDIV4SF);
33876 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33877 IX86_BUILTIN_GATHERDIV8SF);
33880 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33881 IX86_BUILTIN_GATHERSIV2DI);
33884 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33885 IX86_BUILTIN_GATHERSIV4DI);
33888 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33889 IX86_BUILTIN_GATHERDIV2DI);
33892 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33893 IX86_BUILTIN_GATHERDIV4DI);
33896 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33897 IX86_BUILTIN_GATHERSIV4SI);
33900 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33901 IX86_BUILTIN_GATHERSIV8SI);
33904 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33905 IX86_BUILTIN_GATHERDIV4SI);
33908 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33909 IX86_BUILTIN_GATHERDIV8SI);
33912 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33913 IX86_BUILTIN_GATHERALTSIV4DF);
33916 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33917 IX86_BUILTIN_GATHERALTDIV8SF);
33920 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33921 IX86_BUILTIN_GATHERALTSIV4DI);
33924 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33925 IX86_BUILTIN_GATHERALTDIV8SI);
33927 /* AVX512F */
33929 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33930 IX86_BUILTIN_GATHER3SIV16SF);
33933 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33934 IX86_BUILTIN_GATHER3SIV8DF);
33937 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33938 IX86_BUILTIN_GATHER3DIV16SF);
33941 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33942 IX86_BUILTIN_GATHER3DIV8DF);
33945 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33946 IX86_BUILTIN_GATHER3SIV16SI);
33949 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33950 IX86_BUILTIN_GATHER3SIV8DI);
33953 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33954 IX86_BUILTIN_GATHER3DIV16SI);
33957 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33958 IX86_BUILTIN_GATHER3DIV8DI);
33961 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33962 IX86_BUILTIN_GATHER3ALTSIV8DF);
33965 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33966 IX86_BUILTIN_GATHER3ALTDIV16SF);
33969 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33970 IX86_BUILTIN_GATHER3ALTSIV8DI);
33973 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33974 IX86_BUILTIN_GATHER3ALTDIV16SI);
33977 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33978 IX86_BUILTIN_SCATTERSIV16SF);
33981 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33982 IX86_BUILTIN_SCATTERSIV8DF);
33985 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33986 IX86_BUILTIN_SCATTERDIV16SF);
33989 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33990 IX86_BUILTIN_SCATTERDIV8DF);
33993 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33994 IX86_BUILTIN_SCATTERSIV16SI);
33997 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33998 IX86_BUILTIN_SCATTERSIV8DI);
34001 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
34002 IX86_BUILTIN_SCATTERDIV16SI);
34005 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
34006 IX86_BUILTIN_SCATTERDIV8DI);
34008 /* AVX512VL */
34010 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
34011 IX86_BUILTIN_GATHER3SIV2DF);
34014 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
34015 IX86_BUILTIN_GATHER3SIV4DF);
34018 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
34019 IX86_BUILTIN_GATHER3DIV2DF);
34022 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
34023 IX86_BUILTIN_GATHER3DIV4DF);
34026 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
34027 IX86_BUILTIN_GATHER3SIV4SF);
34030 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
34031 IX86_BUILTIN_GATHER3SIV8SF);
34034 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
34035 IX86_BUILTIN_GATHER3DIV4SF);
34038 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
34039 IX86_BUILTIN_GATHER3DIV8SF);
34042 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
34043 IX86_BUILTIN_GATHER3SIV2DI);
34046 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
34047 IX86_BUILTIN_GATHER3SIV4DI);
34050 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
34051 IX86_BUILTIN_GATHER3DIV2DI);
34054 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
34055 IX86_BUILTIN_GATHER3DIV4DI);
34058 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
34059 IX86_BUILTIN_GATHER3SIV4SI);
34062 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
34063 IX86_BUILTIN_GATHER3SIV8SI);
34066 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
34067 IX86_BUILTIN_GATHER3DIV4SI);
34070 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
34071 IX86_BUILTIN_GATHER3DIV8SI);
34074 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
34075 IX86_BUILTIN_GATHER3ALTSIV4DF);
34078 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
34079 IX86_BUILTIN_GATHER3ALTDIV8SF);
34082 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
34083 IX86_BUILTIN_GATHER3ALTSIV4DI);
34086 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
34087 IX86_BUILTIN_GATHER3ALTDIV8SI);
34090 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
34091 IX86_BUILTIN_SCATTERSIV8SF);
34094 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
34095 IX86_BUILTIN_SCATTERSIV4SF);
34098 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
34099 IX86_BUILTIN_SCATTERSIV4DF);
34102 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
34103 IX86_BUILTIN_SCATTERSIV2DF);
34106 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
34107 IX86_BUILTIN_SCATTERDIV8SF);
34110 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
34111 IX86_BUILTIN_SCATTERDIV4SF);
34114 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
34115 IX86_BUILTIN_SCATTERDIV4DF);
34118 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
34119 IX86_BUILTIN_SCATTERDIV2DF);
34122 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
34123 IX86_BUILTIN_SCATTERSIV8SI);
34126 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
34127 IX86_BUILTIN_SCATTERSIV4SI);
34130 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
34131 IX86_BUILTIN_SCATTERSIV4DI);
34134 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
34135 IX86_BUILTIN_SCATTERSIV2DI);
34138 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
34139 IX86_BUILTIN_SCATTERDIV8SI);
34142 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
34143 IX86_BUILTIN_SCATTERDIV4SI);
34146 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
34147 IX86_BUILTIN_SCATTERDIV4DI);
34150 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
34151 IX86_BUILTIN_SCATTERDIV2DI);
34153 /* AVX512PF */
34155 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34156 IX86_BUILTIN_GATHERPFDPD);
34158 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34159 IX86_BUILTIN_GATHERPFDPS);
34161 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34162 IX86_BUILTIN_GATHERPFQPD);
34164 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34165 IX86_BUILTIN_GATHERPFQPS);
34167 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34168 IX86_BUILTIN_SCATTERPFDPD);
34170 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34171 IX86_BUILTIN_SCATTERPFDPS);
34173 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34174 IX86_BUILTIN_SCATTERPFQPD);
34176 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34177 IX86_BUILTIN_SCATTERPFQPS);
34179 /* SHA */
34195 /* RTM. */
34199 /* MMX access to the vec_init patterns. */
34204 V4HI_FTYPE_HI_HI_HI_HI,
34205 IX86_BUILTIN_VEC_INIT_V4HI);
34208 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34209 IX86_BUILTIN_VEC_INIT_V8QI);
34211 /* Access to the vec_extract patterns. */
34233 /* Access to the vec_set patterns. */
34254 /* RDSEED */
34263 /* ADCX */
34268 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34269 IX86_BUILTIN_ADDCARRYX64);
34271 /* SBB */
34276 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34277 IX86_BUILTIN_SBB64);
34279 /* Read/write FLAGS. */
34289 /* CLFLUSHOPT. */
34293 /* CLWB. */
34297 /* MONITORX and MWAITX. */
34303 /* Add FMA4 multi-arg argument instructions */
34305 {
34311 }
34312 }
34314 static void
34316 {
34319 tree decl;
34325 {
34332 /* With no leaf and nothrow flags for MPX builtins
34333 abnormal edges may follow its call when setjmp
34334 presents in the function. Since we may have a lot
34335 of MPX builtins calls it causes lots of useless
34336 edges and enormous PHI nodes. To avoid this we mark
34337 MPX builtins as leaf and nothrow. */
34339 {
34341 NULL_TREE);
34343 }
34344 else
34345 {
34348 }
34349 }
34354 {
34362 {
34364 NULL_TREE);
34366 }
34367 else
34368 {
34371 }
34372 }
34373 }
34375 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34376 to return a pointer to VERSION_DECL if the outcome of the expression
34377 formed by PREDICATE_CHAIN is true. This function will be called during
34378 version dispatch to decide which function version to execute. It returns
34379 the basic block at the end, to which more conditions can be added. */
34381 static basic_block
34384 {
34385 gimple return_stmt;
34387 gimple convert_stmt;
34388 gimple call_cond_stmt;
34389 gimple if_else_stmt;
34395 gimple_seq gseq;
34412 {
34420 }
34423 {
34438 else
34439 {
34440 gimple assign_stmt;
34441 /* Use MIN_EXPR to check if any integer is zero?.
34442 and_expr_var = min_expr <cond_var, and_expr_var> */
34450 }
34451 }
34454 integer_zero_node,
34484 }
34486 /* This parses the attribute arguments to target in DECL and determines
34487 the right builtin to use to match the platform specification.
34488 It returns the priority value for this version decl. If PREDICATE_LIST
34489 is not NULL, it stores the list of cpu features that need to be checked
34490 before dispatching this function. */
34492 static unsigned int
34494 {
34495 tree attrs;
34497 tree target_node;
34504 /* Priority of i386 features, greater value is higher priority. This is
34505 used to decide the order in which function dispatch must happen. For
34506 instance, a version specialized for SSE4.2 should be checked for dispatch
34507 before a version for SSE3, as SSE4.2 implies SSE3. */
34508 enum feature_priority
34509 {
34511 P_MMX,
34512 P_SSE,
34513 P_SSE2,
34514 P_SSE3,
34515 P_SSSE3,
34516 P_PROC_SSSE3,
34517 P_SSE4_A,
34518 P_PROC_SSE4_A,
34519 P_SSE4_1,
34520 P_SSE4_2,
34521 P_PROC_SSE4_2,
34522 P_POPCNT,
34523 P_AVX,
34524 P_PROC_AVX,
34525 P_BMI,
34526 P_PROC_BMI,
34527 P_FMA4,
34528 P_XOP,
34529 P_PROC_XOP,
34530 P_FMA,
34531 P_PROC_FMA,
34532 P_BMI2,
34533 P_AVX2,
34534 P_PROC_AVX2,
34535 P_AVX512F,
34536 P_PROC_AVX512F
34537 };
34541 /* These are the target attribute strings for which a dispatcher is
34542 available, from fold_builtin_cpu. */
34544 static struct _feature_list
34545 {
34548 }
34550 {
34568 };
34571 static unsigned int NUM_FEATURES
34587 /* Return priority zero for default function. */
34591 /* Handle arch= if specified. For priority, set it to be 1 more than
34592 the best instruction set the processor can handle. For instance, if
34593 there is a version for atom and a version for ssse3 (the highest ISA
34594 priority for atom), the atom version must be checked for dispatch
34595 before the ssse3 version. */
34597 {
34607 {
34609 {
34617 else
34618 /* We translate "arch=corei7" and "arch=nehalem" to
34619 "corei7" so that it will be mapped to M_INTEL_COREI7
34620 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34627 else
34634 else
34678 }
34679 }
34684 {
34688 }
34691 {
34693 /* For a C string literal the length includes the trailing NULL. */
34696 predicate_chain);
34697 }
34698 }
34700 /* Process feature name. */
34707 {
34708 /* Do not process "arch=" */
34710 {
34713 }
34715 {
34717 {
34719 {
34724 predicate_chain);
34725 }
34726 /* Find the maximum priority feature. */
34731 }
34732 }
34734 {
34738 }
34740 }
34744 {
34747 attrs_str);
34749 }
34751 {
34754 }
34757 }
34759 /* This compares the priority of target features in function DECL1
34760 and DECL2. It returns positive value if DECL1 is higher priority,
34761 negative value if DECL2 is higher priority and 0 if they are the
34762 same. */
34764 static int
34766 {
34771 }
34773 /* V1 and V2 point to function versions with different priorities
34774 based on the target ISA. This function compares their priorities. */
34776 static int
34778 {
34780 {
34781 tree version_decl;
34782 tree predicate_chain;
34789 }
34791 /* This function generates the dispatch function for
34792 multi-versioned functions. DISPATCH_DECL is the function which will
34793 contain the dispatch logic. FNDECLS are the function choices for
34794 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34795 in DISPATCH_DECL in which the dispatch code is generated. */
34797 static int
34801 {
34802 tree default_decl;
34803 gimple ifunc_cpu_init_stmt;
34804 gimple_seq gseq;
34806 tree ele;
34812 struct _function_version_info
34813 {
34814 tree version_decl;
34815 tree predicate_chain;
34823 /*fndecls_p is actually a vector. */
34826 /* At least one more version other than the default. */
34833 /* The first version in the vector is the default decl. */
34839 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34840 constructors, so explicity call __builtin_cpu_init here. */
34851 {
34855 /* Get attribute string, parse it and find the right predicate decl.
34856 The predicate function could be a lengthy combination of many
34857 features, like arch-type and various isa-variants. */
34868 actual_versions++;
34869 }
34871 /* Sort the versions according to descending order of dispatch priority. The
34872 priority is based on the ISA. This is not a perfect solution. There
34873 could still be ambiguity. If more than one function version is suitable
34874 to execute, which one should be dispatched? In future, allow the user
34875 to specify a dispatch priority next to the version. */
34885 /* dispatch default version at the end. */
34891 }
34893 /* Comparator function to be used in qsort routine to sort attribute
34894 specification strings to "target". */
34896 static int
34898 {
34902 }
34904 /* ARGLIST is the argument to target attribute. This function tokenizes
34905 the comma separated arguments, sorts them and returns a string which
34906 is a unique identifier for the comma separated arguments. It also
34907 replaces non-identifier characters "=,-" with "_". */
34911 {
34912 tree arg;
34921 {
34926 argnum++;
34929 argnum++;
34930 }
34935 {
34941 }
34943 /* Replace "=,-" with "_". */
34956 {
34958 i++;
34960 }
34967 {
34972 }
34977 }
34979 /* This function changes the assembler name for functions that are
34980 versions. If DECL is a function version and has a "target"
34981 attribute, it appends the attribute string to its assembler name. */
34983 static tree
34985 {
34986 tree version_attr;
34994 "Function versions cannot be marked as gnu_inline,"
35003 /* target attribute string cannot be NULL. */
35007 version_string
35018 /* Allow assembler name to be modified if already set. */
35026 }
35028 /* This function returns true if FN1 and FN2 are versions of the same function,
35029 that is, the target strings of the function decls are different. This assumes
35030 that FN1 and FN2 have the same signature. */
35032 static bool
35034 {
35046 /* At least one function decl should have the target attribute specified. */
35050 /* Diagnose missing target attribute if one of the decls is already
35051 multi-versioned. */
35053 {
35055 {
35057 {
35060 }
35063 fn2);
35066 /* Prevent diagnosing of the same error multiple times. */
35071 }
35073 }
35078 /* The sorted target strings must be different for fn1 and fn2
35079 to be versions. */
35082 else
35089 }
35091 static tree
35093 {
35094 /* For function version, add the target suffix to the assembler name. */
35098 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
35100 #endif
35103 }
35105 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
35106 is true, append the full path name of the source file. */
35110 {
35118 /* Get a unique name that can be used globally without any chances
35119 of collision at link time. */
35129 /* Use '.' to concatenate names as it is demangler friendly. */
35132 suffix);
35133 else
35137 }
35139 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35141 /* Make a dispatcher declaration for the multi-versioned function DECL.
35142 Calls to DECL function will be replaced with calls to the dispatcher
35143 by the front-end. Return the decl created. */
35145 static tree
35147 {
35148 tree func_decl;
35168 /* Mark this func as external, the resolver will flip it again if
35169 it gets generated. */
35171 /* This will be of type IFUNCs have to be externally visible. */
35175 }
35177 #endif
35179 /* Returns true if decl is multi-versioned and DECL is the default function,
35180 that is it is not tagged with target specific optimization. */
35182 static bool
35184 {
35193 }
35195 /* Make a dispatcher declaration for the multi-versioned function DECL.
35196 Calls to DECL function will be replaced with calls to the dispatcher
35197 by the front-end. Returns the decl of the dispatcher function. */
35199 static tree
35201 {
35223 /* Find the default version and make it the first node. */
35225 /* Go to the beginning of the chain. */
35230 {
35235 }
35237 /* If there is no default node, just return NULL. */
35241 /* Make default info the first node. */
35243 {
35250 }
35254 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35256 {
35261 /* Right now, the dispatching is done via ifunc. */
35267 dispatcher_version_info
35272 /* Set the dispatcher for all the versions. */
35275 {
35278 }
35279 }
35280 else
35281 #endif
35282 {
35284 "multiversioning needs ifunc which is not supported "
35286 }
35289 }
35291 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35292 it to CHAIN. */
35294 static tree
35296 {
35297 tree attr_name;
35298 tree attr_arg_name;
35299 tree attr_args;
35300 tree attr;
35307 }
35309 /* Make the resolver function decl to dispatch the versions of
35310 a multi-versioned function, DEFAULT_DECL. Create an
35311 empty basic block in the resolver and store the pointer in
35312 EMPTY_BB. Return the decl of the resolver function. */
35314 static tree
35318 {
35323 /* IFUNC's have to be globally visible. So, if the default_decl is
35324 not, then the name of the IFUNC should be made unique. */
35328 /* Append the filename to the resolver function if the versions are
35329 not externally visible. This is because the resolver function has
35330 to be externally visible for the loader to find it. So, appending
35331 the filename will prevent conflicts with a resolver function from
35332 another module which is based on the same version name. */
35335 /* The resolver function should return a (void *). */
35346 /* IFUNC resolvers have to be externally visible. */
35350 /* Resolver is not external, body is generated. */
35360 {
35361 /* In this case, each translation unit with a call to this
35362 versioned function will put out a resolver. Ensure it
35363 is comdat to keep just one copy. */
35366 }
35367 /* Build result decl and add to function_decl. */
35383 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35387 /* Create the alias for dispatch to resolver here. */
35388 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35392 }
35394 /* Generate the dispatching code body to dispatch multi-versioned function
35395 DECL. The target hook is called to process the "target" attributes and
35396 provide the code to dispatch the right function at run-time. NODE points
35397 to the dispatcher decl whose body will be created. */
35399 static tree
35401 {
35402 tree resolver_decl;
35403 basic_block empty_bb;
35404 tree default_ver_decl;
35420 /* The first version in the chain corresponds to the default version. */
35423 /* node is going to be an alias, so remove the finalized bit. */
35437 {
35439 /* Check for virtual functions here again, as by this time it should
35440 have been determined if this function needs a vtable index or
35441 not. This happens for methods in derived classes that override
35442 virtual methods in base classes but are not explicitly marked as
35443 virtual. */
35448 }
35454 }
35455 /* This builds the processor_model struct type defined in
35456 libgcc/config/i386/cpuinfo.c */
35458 static tree
35460 {
35467 /* The first 3 fields are unsigned int. */
35469 {
35475 }
35477 /* The last field is an array of unsigned integers of size one. */
35488 }
35490 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35492 static tree
35494 {
35495 tree new_decl;
35498 VAR_DECL,
35500 type);
35513 }
35515 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35516 into an integer defined in libgcc/config/i386/cpuinfo.c */
35518 static tree
35520 {
35526 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35527 enum processor_features
35528 {
35530 F_MMX,
35531 F_POPCNT,
35532 F_SSE,
35533 F_SSE2,
35534 F_SSE3,
35535 F_SSSE3,
35536 F_SSE4_1,
35537 F_SSE4_2,
35538 F_AVX,
35539 F_AVX2,
35540 F_SSE4_A,
35541 F_FMA4,
35542 F_XOP,
35543 F_FMA,
35544 F_AVX512F,
35545 F_BMI,
35546 F_BMI2,
35547 F_MAX
35548 };
35550 /* These are the values for vendor types and cpu types and subtypes
35551 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35552 the corresponding start value. */
35553 enum processor_model
35554 {
35556 M_AMD,
35557 M_CPU_TYPE_START,
35558 M_INTEL_BONNELL,
35559 M_INTEL_CORE2,
35560 M_INTEL_COREI7,
35561 M_AMDFAM10H,
35562 M_AMDFAM15H,
35563 M_INTEL_SILVERMONT,
35564 M_INTEL_KNL,
35565 M_AMD_BTVER1,
35566 M_AMD_BTVER2,
35567 M_CPU_SUBTYPE_START,
35568 M_INTEL_COREI7_NEHALEM,
35569 M_INTEL_COREI7_WESTMERE,
35570 M_INTEL_COREI7_SANDYBRIDGE,
35571 M_AMDFAM10H_BARCELONA,
35572 M_AMDFAM10H_SHANGHAI,
35573 M_AMDFAM10H_ISTANBUL,
35574 M_AMDFAM15H_BDVER1,
35575 M_AMDFAM15H_BDVER2,
35576 M_AMDFAM15H_BDVER3,
35577 M_AMDFAM15H_BDVER4,
35578 M_INTEL_COREI7_IVYBRIDGE,
35579 M_INTEL_COREI7_HASWELL,
35580 M_INTEL_COREI7_BROADWELL
35581 };
35583 static struct _arch_names_table
35584 {
35587 }
35589 {
35616 };
35618 static struct _isa_names_table
35619 {
35622 }
35624 {
35643 };
35657 {
35658 /* *args must be a expr that can contain other EXPRS leading to a
35659 STRING_CST. */
35661 {
35664 }
35666 }
35671 {
35672 tree ref;
35673 tree field;
35674 tree final;
35677 unsigned int NUM_ARCH_NAMES
35686 {
35690 }
35695 /* CPU types are stored in the next field. */
35698 {
35701 }
35703 /* CPU subtypes are stored in the next field. */
35705 {
35708 }
35710 /* Get the appropriate field in __cpu_model. */
35714 /* Check the value. */
35718 }
35720 {
35721 tree ref;
35722 tree array_elt;
35723 tree field;
35724 tree final;
35727 unsigned int NUM_ISA_NAMES
35736 {
35740 }
35743 /* Get the last field, which is __cpu_features. */
35747 /* Get the appropriate field: __cpu_model.__cpu_features */
35751 /* Access the 0th element of __cpu_features array. */
35756 /* Return __cpu_model.__cpu_features[0] & field_val */
35760 }
35762 }
35764 static tree
35767 {
35769 {
35774 {
35777 }
35778 }
35780 #ifdef SUBTARGET_FOLD_BUILTIN
35782 #endif
35785 }
35787 /* Make builtins to detect cpu type and features supported. NAME is
35788 the builtin name, CODE is the builtin code, and FTYPE is the function
35789 type of the builtin. */
35791 static void
35794 {
35795 tree decl;
35796 tree type;
35804 }
35806 /* Make builtins to get CPU type and features supported. The created
35807 builtins are :
35809 __builtin_cpu_init (), to detect cpu type and features,
35810 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35811 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35812 */
35814 static void
35816 {
35823 }
35825 /* Internal method for ix86_init_builtins. */
35827 static void
35829 {
35841 sysv_va_ref =
35844 fnvoid_va_end_ms =
35846 fnvoid_va_start_ms =
35848 fnvoid_va_end_sysv =
35850 fnvoid_va_start_sysv =
35852 NULL_TREE);
35853 fnvoid_va_copy_ms =
35855 NULL_TREE);
35856 fnvoid_va_copy_sysv =
35872 }
35874 static void
35876 {
35879 /* The __float80 type. */
35882 {
35883 /* The __float80 type. */
35888 }
35891 /* The __float128 type. */
35897 /* This macro is built by i386-builtin-types.awk. */
35898 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35899 }
35901 static void
35903 {
35904 tree t;
35908 /* Builtins to get CPU type and features. */
35911 /* TFmode support builtins. */
35917 /* We will expand them to normal call if SSE isn't available since
35918 they are used by libgcc. */
35938 #ifdef SUBTARGET_INIT_BUILTINS
35939 SUBTARGET_INIT_BUILTINS;
35940 #endif
35941 }
35943 /* Return the ix86 builtin for CODE. */
35945 static tree
35947 {
35952 }
35954 /* Errors in the source file can cause expand_expr to return const0_rtx
35955 where we expect a vector. To avoid crashing, use one of the vector
35956 clear instructions. */
35957 static rtx
35959 {
35963 }
35965 /* Fixup modeless constants to fit required mode. */
35966 static rtx
35968 {
35972 }
35974 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35976 static rtx
35978 {
35979 rtx pat;
35999 {
36003 }
36017 }
36019 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
36021 static rtx
36025 {
36026 rtx pat;
36034 rtx op;
36035 machine_mode mode;
36041 {
36121 }
36131 {
36138 {
36140 {
36143 {
36161 xop_rotl:
36163 {
36166 gcc_checking_assert
36168 }
36169 else
36170 {
36171 gcc_checking_assert
36182 }
36186 }
36187 }
36188 }
36189 else
36190 {
36191 non_constant:
36195 /* If we aren't optimizing, only allow one memory operand to be
36196 generated. */
36198 num_memory++;
36206 }
36210 }
36213 {
36224 else
36225 {
36231 }
36244 }
36251 }
36253 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36254 insns with vec_merge. */
36256 static rtx
36258 rtx target)
36259 {
36260 rtx pat;
36287 }
36289 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36291 static rtx
36294 {
36295 rtx pat;
36300 rtx op2;
36311 /* Swap operands if we have a comparison that isn't available in
36312 hardware. */
36334 }
36336 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36338 static rtx
36340 rtx target)
36341 {
36342 rtx pat;
36356 /* Swap operands if we have a comparison that isn't available in
36357 hardware. */
36379 const0_rtx)));
36382 }
36384 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36386 static rtx
36388 rtx target)
36389 {
36390 rtx pat;
36415 }
36417 static rtx
36420 {
36421 rtx pat;
36426 rtx op2;
36453 }
36455 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36457 static rtx
36459 rtx target)
36460 {
36461 rtx pat;
36493 const0_rtx)));
36496 }
36498 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36500 static rtx
36503 {
36504 rtx pat;
36542 {
36545 }
36548 {
36557 }
36559 {
36568 }
36569 else
36570 {
36577 }
36585 {
36590 emit_insn
36594 FLAGS_REG),
36595 const0_rtx)));
36597 }
36598 else
36600 }
36603 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36605 static rtx
36608 {
36609 rtx pat;
36637 {
36640 }
36643 {
36652 }
36654 {
36663 }
36664 else
36665 {
36672 }
36680 {
36685 emit_insn
36689 FLAGS_REG),
36690 const0_rtx)));
36692 }
36693 else
36695 }
36697 /* Subroutine of ix86_expand_builtin to take care of insns with
36698 variable number of operands. */
36700 static rtx
36703 {
36709 struct
36710 {
36711 rtx op;
36712 machine_mode mode;
36723 {
37433 }
37438 {
37441 }
37444 {
37451 }
37452 else
37453 {
37456 }
37459 {
37466 {
37467 /* SIMD shift insns take either an 8-bit immediate or
37468 register as count. But builtin functions take int as
37469 count. If count doesn't match, we put it in register. */
37471 {
37475 }
37476 }
37479 {
37482 {
37591 {
37595 {
37598 }
37604 }
37606 }
37607 }
37608 else
37609 {
37613 /* If we aren't optimizing, only allow one memory operand to
37614 be generated. */
37616 num_memory++;
37621 {
37624 }
37625 else
37626 {
37629 }
37630 }
37634 }
37637 {
37662 }
37669 }
37671 /* Transform pattern of following layout:
37672 (parallel [
37673 set (A B)
37674 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37675 ])
37676 into:
37677 (set (A B))
37679 Or:
37680 (parallel [ A B
37681 ...
37682 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37683 ...
37684 ])
37685 into:
37686 (parallel [ A B ... ]) */
37688 static rtx
37690 {
37697 {
37706 }
37707 else
37708 {
37714 {
37719 }
37721 /* No more than 1 occurence was removed. */
37725 }
37726 }
37728 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37729 with rounding. */
37730 static rtx
37733 {
37750 /* See avxintrin.h for values. */
37752 {
37756 };
37758 {
37763 };
37766 {
37769 }
37771 {
37774 }
37777 {
37780 }
37803 ? CODE_FOR_sse_ucomi_round
37810 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37812 {
37818 }
37819 else
37820 {
37823 }
37828 set_dst,
37829 const0_rtx)));
37832 }
37834 static rtx
37837 {
37838 rtx pat;
37840 struct
37841 {
37842 rtx op;
37843 machine_mode mode;
37852 {
37935 }
37945 {
37952 {
37954 {
37956 {
37972 }
37973 }
37974 }
37976 {
37978 {
37981 }
37983 /* If there is no rounding use normal version of the pattern. */
37986 }
37987 else
37988 {
37995 {
37998 }
37999 else
38000 {
38003 }
38004 }
38008 }
38011 {
38036 }
38046 }
38048 /* Subroutine of ix86_expand_builtin to take care of special insns
38049 with variable number of operands. */
38051 static rtx
38054 {
38055 tree arg;
38059 struct
38060 {
38061 rtx op;
38062 machine_mode mode;
38071 {
38111 {
38119 }
38138 /* Reserve memory operand for target. */
38141 {
38142 /* These builtins and instructions require the memory
38143 to be properly aligned. */
38162 }
38191 {
38192 /* These builtins and instructions require the memory
38193 to be properly aligned. */
38210 }
38211 /* FALLTHRU */
38249 /* Reserve memory operand for target. */
38276 {
38277 /* These builtins and instructions require the memory
38278 to be properly aligned. */
38301 }
38314 }
38319 {
38324 {
38327 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38328 on it. Try to improve it using get_pointer_alignment,
38329 and if the special builtin is one that requires strict
38330 mode alignment, also from it's GET_MODE_ALIGNMENT.
38331 Failure to do so could lead to ix86_legitimate_combined_insn
38332 rejecting all changes to such insns. */
38338 }
38339 else
38342 }
38343 else
38344 {
38351 }
38354 {
38363 {
38365 {
38371 else
38374 }
38375 }
38376 else
38377 {
38379 {
38380 /* This must be the memory operand. */
38383 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38384 on it. Try to improve it using get_pointer_alignment,
38385 and if the special builtin is one that requires strict
38386 mode alignment, also from it's GET_MODE_ALIGNMENT.
38387 Failure to do so could lead to ix86_legitimate_combined_insn
38388 rejecting all changes to such insns. */
38394 }
38395 else
38396 {
38397 /* This must be register. */
38405 else
38406 {
38409 }
38410 }
38411 }
38415 }
38418 {
38433 }
38439 }
38441 /* Return the integer constant in ARG. Constrain it to be in the range
38442 of the subparts of VEC_TYPE; issue an error if not. */
38444 static int
38446 {
38451 {
38454 }
38457 }
38459 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38460 ix86_expand_vector_init. We DO have language-level syntax for this, in
38461 the form of (type){ init-list }. Except that since we can't place emms
38462 instructions from inside the compiler, we can't allow the use of MMX
38463 registers unless the user explicitly asks for it. So we do *not* define
38464 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38465 we have builtins invoked by mmintrin.h that gives us license to emit
38466 these sorts of instructions. */
38468 static rtx
38470 {
38480 {
38483 }
38490 }
38492 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38493 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38494 had a language-level syntax for referencing vector elements. */
38496 static rtx
38498 {
38502 rtx op0;
38522 }
38524 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38525 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38526 a language-level syntax for referencing vector elements. */
38528 static rtx
38530 {
38554 /* OP0 is the source of these builtin functions and shouldn't be
38555 modified. Create a copy, use it and return it as target. */
38561 }
38563 /* Emit conditional move of SRC to DST with condition
38564 OP1 CODE OP2. */
38565 static void
38567 {
38568 rtx t;
38571 {
38575 }
38576 else
38577 {
38583 }
38584 }
38586 /* Choose max of DST and SRC and put it to DST. */
38587 static void
38589 {
38591 }
38593 /* Expand an expression EXP that calls a built-in function,
38594 with result going to TARGET if that's convenient
38595 (and in mode MODE if that's convenient).
38596 SUBTARGET may be used as the target for computing one of EXP's operands.
38597 IGNORE is nonzero if the value is to be ignored. */
38599 static rtx
38602 {
38612 /* For CPU builtins that can be folded, fold first and expand the fold. */
38614 {
38616 {
38617 /* Make it call __cpu_indicator_init in libgcc. */
38623 }
38626 {
38631 }
38632 }
38634 /* Determine whether the builtin function is available under the current ISA.
38635 Originally the builtin was not created if it wasn't applicable to the
38636 current ISA based on the command line switches. With function specific
38637 options, we need to check in the context of the function making the call
38638 whether it is supported. */
38641 {
38647 else
38648 {
38652 }
38654 }
38657 {
38675 /* Builtin arg1 is size of block but instruction op1 should
38676 be (size - 1). */
38767 /* If no bounds were specified for returned value,
38768 then use INIT bounds. It usually happens when
38769 some built-in function is expanded. */
38771 {
38780 }
38786 {
38789 /* Return value and lb. */
38791 /* Bounds. */
38793 /* Size. */
38800 /* Size was passed but we need to use (size - 1) as for bndmk. */
38804 /* Add LB to size and inverse to get UB. */
38814 /* We need to move bounds to memory before any computations. */
38817 else
38818 {
38821 }
38823 /* Generate mem expression to be used for access to LB and UB. */
38829 /* Compute LB. */
38834 /* Compute UB. UB is stored in 1's complement form. Therefore
38835 we also use max here. */
38844 }
38847 {
38865 /* Put first bounds to temporaries. */
38869 {
38873 }
38874 else
38875 {
38879 }
38881 /* Put second bounds to temporaries. */
38885 {
38889 }
38890 else
38891 {
38895 }
38897 /* Compute LB. */
38901 /* Compute UB. UB is stored in 1's complement form. Therefore
38902 we also use max here. */
38909 }
38912 {
38913 tree name;
38914 rtx symbol;
38932 }
38935 {
38946 /* We need to move bounds to memory first. */
38949 else
38950 {
38953 }
38955 /* Generate mem expression to access LB and load it. */
38960 }
38963 {
38974 /* We need to move bounds to memory first. */
38977 else
38978 {
38981 }
38983 /* Generate mem expression to access UB. */
38986 /* We need to inverse all bits of UB. */
38993 }
38998 ? CODE_FOR_mmx_maskmovq
39000 /* Note the arg order is different from the operand order. */
39141 {
39142 REAL_VALUE_TYPE inf;
39143 rtx tmp;
39155 }
39165 {
39171 insn = (TARGET_64BIT
39175 }
39177 {
39178 insn = (TARGET_64BIT
39182 }
39183 else
39184 {
39187 insn = (TARGET_64BIT
39195 {
39198 }
39200 }
39203 {
39204 /* mode is VOIDmode if __builtin_rd* has been called
39205 without lhs. */
39209 }
39212 {
39217 }
39230 {
39251 }
39257 {
39260 }
39286 {
39289 }
39295 {
39299 {
39338 }
39343 }
39344 else
39345 {
39347 {
39368 }
39370 }
39400 ? CODE_FOR_tbm_bextri_si
39403 {
39406 }
39407 else
39408 {
39417 }
39433 rdrand_step:
39440 {
39443 }
39449 /* Emit SImode conditional move. */
39451 {
39454 }
39457 else
39465 const0_rtx);
39484 rdseed_step:
39491 {
39494 }
39500 const0_rtx);
39529 addcarryx:
39537 /* Generate CF from input operand. */
39542 /* Gen ADCX instruction to compute X+Y+CF. */
39557 /* Store the result. */
39560 {
39563 }
39566 /* Return current CF value. */
39608 kortest:
39622 /* Emit kortest. */
39624 /* And use setcc to return result from flags. */
39882 gather_gen:
39883 rtx half;
39896 /* Note the arg order is different from the operand order. */
39907 else
39911 {
39935 else
39942 {
39947 }
39956 else
39963 {
39968 }
39972 }
39974 /* Force memory operand only with base register here. But we
39975 don't want to do it on memory operand for other builtin
39976 functions. */
39989 {
39992 }
39993 else
39994 {
39997 }
39999 {
40002 }
40004 /* Optimize. If mask is known to have all high bits set,
40005 replace op0 with pc_rtx to signal that the instruction
40006 overwrites the whole destination and doesn't use its
40007 previous contents. */
40009 {
40011 {
40014 }
40016 {
40019 {
40023 negative++;
40026 negative++;
40027 }
40030 }
40033 {
40034 /* Recognize also when mask is like:
40035 __v2df src = _mm_setzero_pd ();
40036 __v2df mask = _mm_cmpeq_pd (src, src);
40037 or
40038 __v8sf src = _mm256_setzero_ps ();
40039 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
40040 as that is a cheaper way to load all ones into
40041 a register than having to load a constant from
40042 memory. */
40045 {
40050 {
40057 /* FALLTHRU */
40067 }
40068 }
40069 }
40070 }
40078 {
40104 }
40107 scatter_gen:
40123 /* Force memory operand only with base register here. But we
40124 don't want to do it on memory operand for other builtin
40125 functions. */
40134 {
40137 }
40138 else
40139 {
40142 }
40151 {
40154 }
40163 vec_prefetch_gen:
40183 {
40186 }
40188 {
40191 }
40196 /* Force memory operand only with base register here. But we
40197 don't want to do it on memory operand for other builtin
40198 functions. */
40205 {
40208 }
40211 {
40214 }
40230 {
40233 }
40239 }
40252 {
40256 /* Emit a normal call if SSE isn't available. */
40260 }
40289 }
40291 /* This returns the target-specific builtin with code CODE if
40292 current_function_decl has visibility on this builtin, which is checked
40293 using isa flags. Returns NULL_TREE otherwise. */
40296 {
40300 /* Determine the isa flags of current_function_decl. */
40312 else
40314 }
40316 /* Return function decl for target specific builtin
40317 for given MPX builtin passed i FCODE. */
40318 static tree
40320 {
40322 {
40358 }
40361 }
40363 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40365 Return an address to be used to load/store bounds for pointer
40366 passed in SLOT.
40368 SLOT_NO is an integer constant holding number of a target
40369 dependent special slot to be used in case SLOT is not a memory.
40371 SPECIAL_BASE is a pointer to be used as a base of fake address
40372 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40373 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40375 static rtx
40377 {
40380 /* NULL slot means we pass bounds for pointer not passed to the
40381 function at all. Register slot means we pass pointer in a
40382 register. In both these cases bounds are passed via Bounds
40383 Table. Since we do not have actual pointer stored in memory,
40384 we have to use fake addresses to access Bounds Table. We
40385 start with (special_base - sizeof (void*)) and decrease this
40386 address by pointer size to get addresses for other slots. */
40388 {
40392 }
40393 /* If pointer is passed in a memory then its address is used to
40394 access Bounds Table. */
40396 {
40400 }
40401 else
40405 }
40407 /* Expand pass uses this hook to load bounds for function parameter
40408 PTR passed in SLOT in case its bounds are not passed in a register.
40410 If SLOT is a memory, then bounds are loaded as for regular pointer
40411 loaded from memory. PTR may be NULL in case SLOT is a memory.
40412 In such case value of PTR (if required) may be loaded from SLOT.
40414 If SLOT is NULL or a register then SLOT_NO is an integer constant
40415 holding number of the target dependent special slot which should be
40416 used to obtain bounds.
40418 Return loaded bounds. */
40420 static rtx
40422 {
40424 rtx addr;
40426 /* Get address to be used to access Bounds Table. Special slots start
40427 at the location of return address of the current function. */
40430 /* Load pointer value from a memory if we don't have it. */
40432 {
40435 }
40445 }
40447 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40448 passed in SLOT in case BOUNDS are not passed in a register.
40450 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40451 stored in memory. PTR may be NULL in case SLOT is a memory.
40452 In such case value of PTR (if required) may be loaded from SLOT.
40454 If SLOT is NULL or a register then SLOT_NO is an integer constant
40455 holding number of the target dependent special slot which should be
40456 used to store BOUNDS. */
40458 static void
40460 {
40461 rtx addr;
40463 /* Get address to be used to access Bounds Table. Special slots start
40464 at the location of return address of a called function. */
40467 /* Load pointer value from a memory if we don't have it. */
40469 {
40472 }
40484 }
40486 /* Load and return bounds returned by function in SLOT. */
40488 static rtx
40490 {
40491 rtx res;
40498 }
40500 /* Store BOUNDS returned by function into SLOT. */
40502 static void
40504 {
40507 }
40509 /* Returns a function decl for a vectorized version of the builtin function
40510 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40511 if it is not available. */
40513 static tree
40515 tree type_in)
40516 {
40532 {
40535 {
40542 }
40547 {
40550 }
40555 {
40562 }
40568 /* The round insn does not trap on denormals. */
40573 {
40580 }
40586 /* The round insn does not trap on denormals. */
40591 {
40596 }
40602 /* The round insn does not trap on denormals. */
40607 {
40614 }
40620 /* The round insn does not trap on denormals. */
40625 {
40630 }
40637 {
40642 }
40649 {
40654 }
40660 /* The round insn does not trap on denormals. */
40665 {
40672 }
40678 /* The round insn does not trap on denormals. */
40683 {
40688 }
40693 {
40700 }
40705 {
40712 }
40716 /* The round insn does not trap on denormals. */
40721 {
40726 }
40730 /* The round insn does not trap on denormals. */
40735 {
40740 }
40744 /* The round insn does not trap on denormals. */
40749 {
40754 }
40758 /* The round insn does not trap on denormals. */
40763 {
40768 }
40772 /* The round insn does not trap on denormals. */
40777 {
40782 }
40786 /* The round insn does not trap on denormals. */
40791 {
40796 }
40800 /* The round insn does not trap on denormals. */
40805 {
40810 }
40814 /* The round insn does not trap on denormals. */
40819 {
40824 }
40828 /* The round insn does not trap on denormals. */
40833 {
40838 }
40842 /* The round insn does not trap on denormals. */
40847 {
40852 }
40857 {
40862 }
40867 {
40872 }
40877 }
40879 /* Dispatch to a handler for a vectorization library. */
40882 type_in);
40885 }
40887 /* Handler for an SVML-style interface to
40888 a library with vectorized intrinsics. */
40890 static tree
40892 {
40900 /* The SVML is suitable for unsafe math only. */
40913 {
40960 }
40969 {
40972 }
40973 else
40976 /* Convert to uppercase. */
40981 args;
40983 arity++;
40987 else
40990 /* Build a function declaration for the vectorized function. */
40999 }
41001 /* Handler for an ACML-style interface to
41002 a library with vectorized intrinsics. */
41004 static tree
41006 {
41014 /* The ACML is 64bits only and suitable for unsafe math only as
41015 it does not correctly support parts of IEEE with the required
41016 precision such as denormals. */
41030 {
41060 }
41067 args;
41069 arity++;
41073 else
41076 /* Build a function declaration for the vectorized function. */
41085 }
41087 /* Returns a decl of a function that implements gather load with
41088 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
41089 Return NULL_TREE if it is not available. */
41091 static tree
41094 {
41110 /* v*gather* insn sign extends index to pointer mode. */
41122 {
41126 else
41132 else
41138 else
41144 else
41150 else
41156 else
41162 else
41168 else
41174 else
41180 else
41186 else
41192 else
41197 }
41200 }
41202 /* Returns a code for a target-specific builtin that implements
41203 reciprocal of the function, or NULL_TREE if not available. */
41205 static tree
41207 {
41214 /* Machine dependent builtins. */
41216 {
41217 /* Vectorized version of sqrt to rsqrt conversion. */
41226 }
41227 else
41228 /* Normal builtins. */
41230 {
41231 /* Sqrt to rsqrt conversion. */
41237 }
41238 }
41239 \f
41240 /* Helper for avx_vpermilps256_operand et al. This is also used by
41241 the expansion functions to turn the parallel back into a mask.
41242 The return value is 0 for no match and the imm8+1 for a match. */
41244 int
41246 {
41254 /* Validate that all of the elements are constants, and not totally
41255 out of range. Copy the data into an integral array to make the
41256 subsequent checks easier. */
41258 {
41268 }
41271 {
41273 /* In the 512-bit DFmode case, we can only move elements within
41274 a 128-bit lane. First fill the second part of the mask,
41275 then fallthru. */
41277 {
41281 }
41283 {
41287 }
41288 /* FALLTHRU */
41291 /* In the 256-bit DFmode case, we can only move elements within
41292 a 128-bit lane. */
41294 {
41298 }
41300 {
41304 }
41308 /* In 512 bit SFmode case, permutation in the upper 256 bits
41309 must mirror the permutation in the lower 256-bits. */
41313 /* FALLTHRU */
41316 /* In 256 bit SFmode case, we have full freedom of
41317 movement within the low 128-bit lane, but the high 128-bit
41318 lane must mirror the exact same pattern. */
41323 /* FALLTHRU */
41327 /* In the 128-bit case, we've full freedom in the placement of
41328 the elements from the source operand. */
41335 }
41337 /* Make sure success has a non-zero value by adding one. */
41339 }
41341 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41342 the expansion functions to turn the parallel back into a mask.
41343 The return value is 0 for no match and the imm8+1 for a match. */
41345 int
41347 {
41355 /* Validate that all of the elements are constants, and not totally
41356 out of range. Copy the data into an integral array to make the
41357 subsequent checks easier. */
41359 {
41369 }
41371 /* Validate that the halves of the permute are halves. */
41379 /* Reconstruct the mask. */
41381 {
41387 }
41389 /* Make sure success has a non-zero value by adding one. */
41391 }
41392 \f
41393 /* Return a register priority for hard reg REGNO. */
41394 static int
41396 {
41397 /* ebp and r13 as the base always wants a displacement, r12 as the
41398 base always wants an index. So discourage their usage in an
41399 address. */
41404 /* New x86-64 int registers result in bigger code size. Discourage
41405 them. */
41408 /* New x86-64 SSE registers result in bigger code size. Discourage
41409 them. */
41412 /* Usage of AX register results in smaller code. Prefer it. */
41416 }
41418 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41420 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41421 QImode must go into class Q_REGS.
41422 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41423 movdf to do mem-to-mem moves through integer regs. */
41425 static reg_class_t
41427 {
41430 /* We're only allowed to return a subclass of CLASS. Many of the
41431 following checks fail for NO_REGS, so eliminate that early. */
41435 /* All classes can load zeros. */
41439 /* Force constants into memory if we are loading a (nonzero) constant into
41440 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41441 instructions to load from a constant. */
41448 /* Prefer SSE regs only, if we can use them for math. */
41452 /* Floating-point constants need more complex checks. */
41454 {
41455 /* General regs can load everything. */
41459 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41460 zero above. We only want to wind up preferring 80387 registers if
41461 we plan on doing computation with them. */
41464 {
41465 /* Limit class to non-sse. */
41474 }
41477 }
41479 /* Generally when we see PLUS here, it's the function invariant
41480 (plus soft-fp const_int). Which can only be computed into general
41481 regs. */
41485 /* QImode constants are easy to load, but non-constant QImode data
41486 must go into Q_REGS. */
41488 {
41494 }
41497 }
41499 /* Discourage putting floating-point values in SSE registers unless
41500 SSE math is being used, and likewise for the 387 registers. */
41501 static reg_class_t
41503 {
41506 /* Restrict the output reload class to the register bank that we are doing
41507 math on. If we would like not to return a subset of CLASS, reject this
41508 alternative: if reload cannot do this, it will still use its choice. */
41514 {
41519 else
41521 }
41524 }
41526 static reg_class_t
41529 {
41530 /* Double-word spills from general registers to non-offsettable memory
41531 references (zero-extended addresses) require special handling. */
41537 {
41539 ? CODE_FOR_reload_noff_load
41541 /* Add the cost of moving address to a temporary. */
41545 }
41547 /* QImode spills from non-QI registers require
41548 intermediate register on 32bit targets. */
41554 {
41559 else
41565 /* Return Q_REGS if the operand is in memory. */
41568 }
41570 /* This condition handles corner case where an expression involving
41571 pointers gets vectorized. We're trying to use the address of a
41572 stack slot as a vector initializer.
41574 (set (reg:V2DI 74 [ vect_cst_.2 ])
41575 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41577 Eventually frame gets turned into sp+offset like this:
41579 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41580 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41581 (const_int 392 [0x188]))))
41583 That later gets turned into:
41585 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41586 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41587 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41589 We'll have the following reload recorded:
41591 Reload 0: reload_in (DI) =
41592 (plus:DI (reg/f:DI 7 sp)
41593 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41594 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41595 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41596 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41597 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41598 reload_reg_rtx: (reg:V2DI 22 xmm1)
41600 Which isn't going to work since SSE instructions can't handle scalar
41601 additions. Returning GENERAL_REGS forces the addition into integer
41602 register and reload can handle subsequent reloads without problems. */
41610 }
41612 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41614 static bool
41616 {
41618 {
41634 }
41637 }
41639 /* If we are copying between general and FP registers, we need a memory
41640 location. The same is true for SSE and MMX registers.
41642 To optimize register_move_cost performance, allow inline variant.
41644 The macro can't work reliably when one of the CLASSES is class containing
41645 registers from multiple units (SSE, MMX, integer). We avoid this by never
41646 combining those units in single alternative in the machine description.
41647 Ensure that this constraint holds to avoid unexpected surprises.
41649 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41650 enforce these sanity checks. */
41655 {
41664 {
41667 }
41672 /* Between mask and general, we have moves no larger than word size. */
41677 /* ??? This is a lie. We do have moves between mmx/general, and for
41678 mmx/sse2. But by saying we need secondary memory we discourage the
41679 register allocator from using the mmx registers unless needed. */
41684 {
41685 /* SSE1 doesn't have any direct moves from other classes. */
41689 /* If the target says that inter-unit moves are more expensive
41690 than moving through memory, then don't generate them. */
41695 /* Between SSE and general, we have moves no larger than word size. */
41698 }
41701 }
41703 bool
41706 {
41708 }
41710 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41712 On the 80386, this is the size of MODE in words,
41713 except in the FP regs, where a single reg is always enough. */
41715 static unsigned char
41717 {
41719 {
41724 else
41726 }
41727 else
41728 {
41731 else
41733 }
41734 }
41736 /* Return true if the registers in CLASS cannot represent the change from
41737 modes FROM to TO. */
41739 bool
41742 {
41746 /* x87 registers can't do subreg at all, as all values are reformatted
41747 to extended precision. */
41752 {
41753 /* Vector registers do not support QI or HImode loads. If we don't
41754 disallow a change to these modes, reload will assume it's ok to
41755 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41756 the vec_dupv4hi pattern. */
41759 }
41762 }
41764 /* Return the cost of moving data of mode M between a
41765 register and memory. A value of 2 is the default; this cost is
41766 relative to those in `REGISTER_MOVE_COST'.
41768 This function is used extensively by register_move_cost that is used to
41769 build tables at startup. Make it inline in this case.
41770 When IN is 2, return maximum of in and out move cost.
41772 If moving between registers and memory is more expensive than
41773 between two registers, you should define this macro to express the
41774 relative cost.
41776 Model also increased moving costs of QImode registers in non
41777 Q_REGS classes.
41778 */
41782 {
41785 {
41788 {
41800 }
41804 }
41806 {
41809 {
41821 }
41825 }
41827 {
41830 {
41839 }
41843 }
41845 {
41848 {
41854 else
41859 }
41860 else
41861 {
41866 else
41868 }
41875 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41882 else
41886 }
41887 }
41889 static int
41892 {
41894 }
41897 /* Return the cost of moving data from a register in class CLASS1 to
41898 one in class CLASS2.
41900 It is not required that the cost always equal 2 when FROM is the same as TO;
41901 on some machines it is expensive to move between registers if they are not
41902 general registers. */
41904 static int
41906 reg_class_t class2_i)
41907 {
41911 /* In case we require secondary memory, compute cost of the store followed
41912 by load. In order to avoid bad register allocation choices, we need
41913 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41916 {
41922 /* In case of copying from general_purpose_register we may emit multiple
41923 stores followed by single load causing memory size mismatch stall.
41924 Count this as arbitrarily high cost of 20. */
41929 /* In the case of FP/MMX moves, the registers actually overlap, and we
41930 have to switch modes in order to treat them differently. */
41936 }
41938 /* Moves between SSE/MMX and integer unit are expensive. */
41942 /* ??? By keeping returned value relatively high, we limit the number
41943 of moves between integer and MMX/SSE registers for all targets.
41944 Additionally, high value prevents problem with x86_modes_tieable_p(),
41945 where integer modes in MMX/SSE registers are not tieable
41946 because of missing QImode and HImode moves to, from or between
41947 MMX/SSE registers. */
41957 }
41959 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41960 MODE. */
41962 bool
41964 {
41965 /* Flags and only flags can only hold CCmode values. */
41976 || (TARGET_AVX512BW
41981 {
41982 /* We implement the move patterns for all vector modes into and
41983 out of SSE registers, even when no operation instructions
41984 are available. */
41986 /* For AVX-512 we allow, regardless of regno:
41987 - XI mode
41988 - any of 512-bit wide vector mode
41989 - any scalar mode. */
41996 /* TODO check for QI/HI scalars. */
41997 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
42005 /* xmm16-xmm31 are only available for AVX-512. */
42009 /* OImode and AVX modes are available only when AVX is enabled. */
42016 }
42018 {
42019 /* We implement the move patterns for 3DNOW modes even in MMX mode,
42020 so if the register is available at all, then we can move data of
42021 the given mode into or out of it. */
42024 }
42027 {
42028 /* Take care for QImode values - they can be in non-QI regs,
42029 but then they do cause partial register stalls. */
42034 /* LRA checks if the hard register is OK for the given mode.
42035 QImode values can live in non-QI regs, so we allow all
42036 registers here. */
42040 }
42041 /* We handle both integer and floats in the general purpose registers. */
42048 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
42049 on to use that value in smaller contexts, this can easily force a
42050 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
42051 supporting DImode, allow it. */
42056 }
42058 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
42059 tieable integer mode. */
42061 static bool
42063 {
42065 {
42078 }
42079 }
42081 /* Return true if MODE1 is accessible in a register that can hold MODE2
42082 without copying. That is, all register classes that can hold MODE2
42083 can also hold MODE1. */
42085 bool
42087 {
42095 /* MODE2 being XFmode implies fp stack or general regs, which means we
42096 can tie any smaller floating point modes to it. Note that we do not
42097 tie this with TFmode. */
42101 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
42102 that we can tie it with SFmode. */
42106 /* If MODE2 is only appropriate for an SSE register, then tie with
42107 any other mode acceptable to SSE registers. */
42117 /* If MODE2 is appropriate for an MMX register, then tie
42118 with any other mode acceptable to MMX registers. */
42125 }
42127 /* Return the cost of moving between two registers of mode MODE. */
42129 static int
42131 {
42135 {
42167 }
42169 /* Return the cost of moving between two registers of mode MODE,
42170 assuming that the move will be in pieces of at most UNITS bytes. */
42172 }
42174 /* Compute a (partial) cost for rtx X. Return true if the complete
42175 cost has been computed, and false if subexpressions should be
42176 scanned. In either case, *TOTAL contains the cost result. */
42178 static bool
42181 {
42182 rtx mask;
42189 {
42193 {
42196 }
42208 && !(TARGET_64BIT
42212 /* Use 0 cost for CONST to improve its propagation. */
42215 else
42225 {
42235 }
42237 {
42240 {
42249 }
42250 }
42251 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42252 it'll probably end up. Add a penalty for size. */
42259 /* The zero extensions is often completely free on x86_64, so make
42260 it as cheap as possible. */
42266 else
42278 {
42281 {
42284 }
42287 {
42290 }
42291 }
42292 /* FALLTHRU */
42299 {
42300 /* ??? Should be SSE vector operation cost. */
42301 /* At least for published AMD latencies, this really is the same
42302 as the latency for a simple fpu operation like fabs. */
42303 /* V*QImode is emulated with 1-11 insns. */
42305 {
42308 {
42309 /* For XOP we use vpshab, which requires a broadcast of the
42310 value to the variable shift insn. For constants this
42311 means a V16Q const in mem; even when we can perform the
42312 shift with one insn set the cost to prefer paddb. */
42314 {
42319 }
42321 }
42325 }
42326 else
42328 }
42330 {
42332 {
42335 else
42337 }
42338 else
42339 {
42342 else
42344 }
42345 }
42346 else
42347 {
42352 {
42353 /* Return the cost after shift-and truncation. */
42356 }
42357 else
42359 }
42363 {
42364 rtx sub;
42369 /* ??? SSE scalar/vector cost should be used here. */
42370 /* ??? Bald assumption that fma has the same cost as fmul. */
42374 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42385 }
42389 {
42390 /* ??? SSE scalar cost should be used here. */
42393 }
42395 {
42398 }
42400 {
42401 /* ??? SSE vector cost should be used here. */
42404 }
42406 {
42407 /* V*QImode is emulated with 7-13 insns. */
42409 {
42416 }
42417 /* V*DImode is emulated with 5-8 insns. */
42419 {
42422 else
42424 }
42425 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42426 insns, including two PMULUDQ. */
42429 else
42432 }
42433 else
42434 {
42439 {
42442 nbits++;
42443 }
42444 else
42445 /* This is arbitrary. */
42448 /* Compute costs correctly for widening multiplication. */
42452 {
42459 {
42463 else
42465 }
42469 }
42477 }
42484 /* ??? SSE cost should be used here. */
42489 /* ??? SSE vector cost should be used here. */
42491 else
42498 {
42503 {
42506 {
42514 }
42515 }
42518 {
42521 {
42527 }
42528 }
42530 {
42538 }
42539 }
42540 /* FALLTHRU */
42544 {
42545 /* ??? SSE cost should be used here. */
42548 }
42550 {
42553 }
42555 {
42556 /* ??? SSE vector cost should be used here. */
42559 }
42560 /* FALLTHRU */
42567 {
42574 }
42575 /* FALLTHRU */
42579 {
42580 /* ??? SSE cost should be used here. */
42583 }
42585 {
42588 }
42590 {
42591 /* ??? SSE vector cost should be used here. */
42594 }
42595 /* FALLTHRU */
42599 {
42600 /* ??? Should be SSE vector operation cost. */
42601 /* At least for published AMD latencies, this really is the same
42602 as the latency for a simple fpu operation like fabs. */
42604 }
42607 else
42616 {
42617 /* This kind of construct is implemented using test[bwl].
42618 Treat it as if we had an AND. */
42623 }
42625 /* The embedded comparison operand is completely free. */
42639 /* ??? SSE cost should be used here. */
42644 /* ??? SSE vector cost should be used here. */
42650 /* ??? SSE cost should be used here. */
42655 /* ??? SSE vector cost should be used here. */
42667 /* ??? Assume all of these vector manipulation patterns are
42668 recognizable. In which case they all pretty much have the
42669 same cost. */
42674 /* This is masked instruction, assume the same cost,
42675 as nonmasked variant. */
42678 else
42684 }
42685 }
42687 #if TARGET_MACHO
42691 /* Given a symbol name and its associated stub, write out the
42692 definition of the stub. */
42694 void
42696 {
42701 /* For 64-bit we shouldn't get here. */
42704 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42721 else
42728 {
42730 }
42732 {
42733 /* PIC stub. */
42734 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42740 }
42741 else
42744 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42745 it needs no stub-binding-helper. */
42752 {
42755 }
42756 else
42761 /* N.B. Keep the correspondence of these
42762 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42763 old-pic/new-pic/non-pic stubs; altering this will break
42764 compatibility with existing dylibs. */
42766 {
42767 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42769 }
42770 else
42771 /* 16-byte -mdynamic-no-pic stub. */
42777 }
42780 /* Order the registers for register allocator. */
42782 void
42784 {
42788 /* First allocate the local general purpose registers. */
42793 /* Global general purpose registers. */
42798 /* x87 registers come first in case we are doing FP math
42799 using them. */
42804 /* SSE registers. */
42810 /* Extended REX SSE registers. */
42814 /* Mask register. */
42818 /* MPX bound registers. */
42822 /* x87 registers. */
42830 /* Initialize the rest of array as we do not allocate some registers
42831 at all. */
42834 }
42836 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42837 in struct attribute_spec handler. */
42838 static tree
42840 tree args,
42843 {
42848 {
42850 name);
42853 }
42855 {
42857 name);
42860 }
42862 {
42863 tree cst;
42867 {
42870 name);
42872 }
42875 {
42878 name);
42880 }
42883 }
42886 }
42888 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42889 struct attribute_spec.handler. */
42890 static tree
42893 {
42898 {
42900 name);
42903 }
42905 /* Can combine regparm with all attributes but fastcall. */
42907 {
42909 {
42911 }
42914 }
42916 {
42918 {
42920 }
42923 }
42926 }
42928 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42929 struct attribute_spec.handler. */
42930 static tree
42933 {
42936 {
42939 }
42940 else
42944 {
42946 name);
42948 }
42954 {
42956 name);
42958 }
42961 }
42963 static tree
42966 {
42968 {
42970 name);
42972 }
42974 }
42976 static bool
42978 {
42982 }
42984 /* Returns an expression indicating where the this parameter is
42985 located on entry to the FUNCTION. */
42987 static rtx
42989 {
42995 {
43000 else
43003 }
43008 {
43015 {
43020 }
43021 else
43022 {
43025 {
43031 }
43032 }
43034 }
43038 }
43040 /* Determine whether x86_output_mi_thunk can succeed. */
43042 static bool
43044 const_tree function)
43045 {
43046 /* 64-bit can handle anything. */
43050 /* For 32-bit, everything's fine if we have one free register. */
43054 /* Need a free register for vcall_offset. */
43058 /* Need a free register for GOT references. */
43062 /* Otherwise ok. */
43064 }
43066 /* Output the assembler code for a thunk function. THUNK_DECL is the
43067 declaration for the thunk function itself, FUNCTION is the decl for
43068 the target function. DELTA is an immediate constant offset to be
43069 added to THIS. If VCALL_OFFSET is nonzero, the word at
43070 *(*this + vcall_offset) should be added to THIS. */
43072 static void
43075 {
43083 else
43084 {
43090 else
43092 }
43096 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
43097 pull it in now and let DELTA benefit. */
43101 {
43102 /* Put the this parameter into %eax. */
43105 }
43106 else
43109 /* Adjust the this parameter by a fixed constant. */
43111 {
43116 {
43118 {
43122 }
43123 }
43126 }
43128 /* Adjust the this parameter by a value stored in the vtable. */
43130 {
43140 /* Adjust the this parameter. */
43144 {
43148 }
43155 vcall_mem));
43156 else
43158 }
43160 /* If necessary, drop THIS back to its stack slot. */
43166 {
43169 ;
43170 else
43171 {
43175 }
43176 }
43177 else
43178 {
43180 ;
43181 #if TARGET_MACHO
43183 {
43186 }
43188 else
43189 {
43197 }
43198 }
43200 /* Our sibling call patterns do not allow memories, because we have no
43201 predicate that can distinguish between frame and non-frame memory.
43202 For our purposes here, we can get away with (ab)using a jump pattern,
43203 because we're going to do no optimization. */
43205 {
43207 {
43213 }
43214 else
43216 }
43217 else
43218 {
43220 {
43221 // CM_LARGE_PIC always uses pseudo PIC register which is
43222 // uninitialized. Since FUNCTION is local and calling it
43223 // doesn't go through PLT, we use scratch register %r11 as
43224 // PIC register and initialize it here.
43229 }
43232 {
43238 }
43244 }
43247 /* Emit just enough of rest_of_compilation to get the insns emitted.
43248 Note that use_thunk calls assemble_start_function et al. */
43254 }
43256 static void
43258 {
43262 #if TARGET_MACHO
43264 #endif
43271 }
43273 int
43275 {
43276 machine_mode mode;
43289 }
43291 /* Print call to TARGET to FILE. */
43293 static void
43295 {
43298 else
43300 }
43302 /* Output assembler code to FILE to increment profiler label # LABELNO
43303 for profiling a function entry. */
43304 void
43306 {
43310 {
43311 #ifndef NO_PROFILE_COUNTERS
43313 #endif
43317 else
43319 }
43321 {
43322 #ifndef NO_PROFILE_COUNTERS
43325 #endif
43327 }
43328 else
43329 {
43330 #ifndef NO_PROFILE_COUNTERS
43333 #endif
43335 }
43338 {
43342 }
43343 }
43345 /* We don't have exact information about the insn sizes, but we may assume
43346 quite safely that we are informed about all 1 byte insns and memory
43347 address sizes. This is enough to eliminate unnecessary padding in
43348 99% of cases. */
43350 static int
43352 {
43358 /* Discard alignments we've emit and jump instructions. */
43363 /* Important case - calls are always 5 bytes.
43364 It is common to have many calls in the row. */
43373 /* For normal instructions we rely on get_attr_length being exact,
43374 with a few exceptions. */
43376 {
43380 {
43390 /* Otherwise trust get_attr_length. */
43392 }
43397 }
43400 else
43402 }
43404 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43406 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43407 window. */
43409 static void
43411 {
43416 /* Look for all minimal intervals of instructions containing 4 jumps.
43417 The intervals are bounded by START and INSN. NBYTES is the total
43418 size of instructions in the interval including INSN and not including
43419 START. When the NBYTES is smaller than 16 bytes, it is possible
43420 that the end of START and INSN ends up in the same 16byte page.
43422 The smallest offset in the page INSN can start is the case where START
43423 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43424 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43426 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43427 have to, control transfer to label(s) can be performed through other
43428 means, and also we estimate minimum length of all asm stmts as 0. */
43430 {
43434 {
43440 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43441 already in the current 16 byte page, because otherwise
43442 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43443 bytes to reach 16 byte boundary. */
43451 {
43453 {
43458 else
43461 }
43462 }
43464 }
43473 njumps++;
43474 else
43478 {
43483 else
43486 }
43493 {
43500 }
43501 }
43502 }
43503 #endif
43505 /* AMD Athlon works faster
43506 when RET is not destination of conditional jump or directly preceded
43507 by other jump instruction. We avoid the penalty by inserting NOP just
43508 before the RET instructions in such cases. */
43509 static void
43511 {
43512 edge e;
43513 edge_iterator ei;
43516 {
43529 {
43530 edge e;
43531 edge_iterator ei;
43536 {
43539 }
43540 }
43542 {
43548 /* Empty functions get branch mispredict even when
43549 the jump destination is not visible to us. */
43552 }
43554 {
43557 }
43558 }
43559 }
43561 /* Count the minimum number of instructions in BB. Return 4 if the
43562 number of instructions >= 4. */
43564 static int
43566 {
43570 /* Count number of instructions in this block. Return 4 if the number
43571 of instructions >= 4. */
43573 {
43574 /* Only happen in exit blocks. */
43582 {
43583 insn_count++;
43586 }
43587 }
43590 }
43593 /* Count the minimum number of instructions in code path in BB.
43594 Return 4 if the number of instructions >= 4. */
43596 static int
43598 {
43599 edge e;
43600 edge_iterator ei;
43603 /* Only bother counting instructions along paths with no
43604 more than 2 basic blocks between entry and exit. Given
43605 that BB has an edge to exit, determine if a predecessor
43606 of BB has an edge from entry. If so, compute the number
43607 of instructions in the predecessor block. If there
43608 happen to be multiple such blocks, compute the minimum. */
43611 {
43612 edge prev_e;
43613 edge_iterator prev_ei;
43616 {
43619 }
43621 {
43623 {
43628 }
43629 }
43630 }
43636 }
43638 /* Pad short function to 4 instructions. */
43640 static void
43642 {
43643 edge e;
43644 edge_iterator ei;
43647 {
43650 {
43653 /* Pad short function. */
43655 {
43658 /* Find epilogue. */
43667 /* Two NOPs count as one instruction. */
43670 }
43671 }
43672 }
43673 }
43675 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43676 the epilogue, the Windows system unwinder will apply epilogue logic and
43677 produce incorrect offsets. This can be avoided by adding a nop between
43678 the last insn that can throw and the first insn of the epilogue. */
43680 static void
43682 {
43683 edge e;
43684 edge_iterator ei;
43687 {
43690 /* Find the beginning of the epilogue. */
43697 /* We only care about preceding insns that can throw. */
43702 /* Do not separate calls from their debug information. */
43708 else
43712 }
43713 }
43715 /* Implement machine specific optimizations. We implement padding of returns
43716 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43717 static void
43719 {
43720 /* We are freeing block_for_insn in the toplev to keep compatibility
43721 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43728 {
43733 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43736 #endif
43737 }
43738 }
43740 /* Return nonzero when QImode register that must be represented via REX prefix
43741 is used. */
43742 bool
43744 {
43752 }
43754 /* Return true when INSN mentions register that must be encoded using REX
43755 prefix. */
43756 bool
43758 {
43761 {
43766 }
43768 }
43770 /* If profitable, negate (without causing overflow) integer constant
43771 of mode MODE at location LOC. Return true in this case. */
43772 bool
43774 {
43775 HOST_WIDE_INT val;
43781 {
43783 /* DImode x86_64 constants must fit in 32 bits. */
43796 }
43798 /* Avoid overflows. */
43804 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43805 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43808 {
43811 }
43814 }
43816 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43817 optabs would emit if we didn't have TFmode patterns. */
43819 void
43821 {
43856 }
43857 \f
43863 /* Get a vector mode of the same size as the original but with elements
43864 twice as wide. This is only guaranteed to apply to integral vectors. */
43868 {
43869 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43874 }
43876 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43877 fill target with val via vec_duplicate. */
43879 static bool
43881 {
43884 rtx dup;
43886 /* First attempt to recognize VAL as-is. */
43890 {
43892 /* If that fails, force VAL into a register. */
43903 }
43905 }
43907 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43908 with all elements equal to VAR. Return true if successful. */
43910 static bool
43913 {
43917 {
43922 /* FALLTHRU */
43942 {
43943 rtx x;
43950 }
43963 {
43967 permute:
43975 /* Extend to SImode using a paradoxical SUBREG. */
43979 /* Insert the SImode value as low element of a V4SImode vector. */
43988 }
43999 widen:
44000 /* Replicate the value once into the next wider mode and recurse. */
44001 {
44003 rtx x;
44020 }
44026 else
44027 {
44036 }
44043 else
44044 {
44053 }
44058 }
44059 }
44061 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44062 whose ONE_VAR element is VAR, and other elements are zero. Return true
44063 if successful. */
44065 static bool
44068 {
44069 machine_mode vsimode;
44070 rtx new_target;
44075 {
44077 /* For SSE4.1, we normally use vector set. But if the second
44078 element is zero and inter-unit moves are OK, we use movq
44079 instead. */
44081 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
44103 /* Use ix86_expand_vector_set in 64bit mode only. */
44108 }
44111 {
44116 }
44119 {
44124 /* FALLTHRU */
44139 else
44146 {
44147 /* We need to shuffle the value to the correct position, so
44148 create a new pseudo to store the intermediate result. */
44150 /* With SSE2, we can use the integer shuffle insns. */
44152 {
44154 const1_rtx,
44161 }
44163 /* Otherwise convert the intermediate result to V4SFmode and
44164 use the SSE1 shuffle instructions. */
44166 {
44169 }
44170 else
44174 const1_rtx,
44183 }
44198 widen:
44202 /* Zero extend the variable element to SImode and recurse. */
44215 }
44216 }
44218 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44219 consisting of the values in VALS. It is known that all elements
44220 except ONE_VAR are constants. Return true if successful. */
44222 static bool
44225 {
44227 machine_mode wmode;
44235 {
44240 /* For the two element vectors, it's just as easy to use
44241 the general case. */
44245 /* Use ix86_expand_vector_set in 64bit mode only. */
44267 widen:
44268 /* There's no way to set one QImode entry easily. Combine
44269 the variable value with its adjacent constant value, and
44270 promote to an HImode set. */
44273 {
44278 }
44279 else
44280 {
44283 }
44297 }
44302 }
44304 /* A subroutine of ix86_expand_vector_init_general. Use vector
44305 concatenate to handle the most general case: all values variable,
44306 and none identical. */
44308 static void
44311 {
44314 rtvec v;
44318 {
44321 {
44366 }
44378 {
44393 }
44398 {
44417 }
44422 {
44435 }
44438 half:
44439 /* FIXME: We process inputs backward to help RA. PR 36222. */
44443 {
44448 }
44452 {
44456 {
44460 }
44463 {
44467 }
44470 }
44472 {
44475 {
44479 }
44482 }
44483 else
44489 }
44490 }
44492 /* A subroutine of ix86_expand_vector_init_general. Use vector
44493 interleave to handle the most general case: all values variable,
44494 and none identical. */
44496 static void
44499 {
44508 {
44529 }
44532 {
44533 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44537 /* Insert the SImode value as low element of V4SImode vector. */
44541 op0),
44543 const1_rtx);
44546 /* Cast the V4SImode vector back to a vector in orignal mode. */
44550 /* Load even elements into the second position. */
44554 const1_rtx));
44556 /* Cast vector to FIRST_IMODE vector. */
44559 }
44561 /* Interleave low FIRST_IMODE vectors. */
44563 {
44567 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44570 }
44572 /* Interleave low SECOND_IMODE vectors. */
44574 {
44577 {
44582 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44583 vector. */
44586 }
44589 /* FALLTHRU */
44596 /* Cast the SECOND_IMODE vector back to a vector on original
44597 mode. */
44603 }
44604 }
44606 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44607 all values variable, and none identical. */
44609 static void
44612 {
44619 {
44624 /* FALLTHRU */
44652 half:
44675 quarter:
44701 /* FALLTHRU */
44707 /* Don't use ix86_expand_vector_init_interleave if we can't
44708 move from GPR to SSE register directly. */
44724 }
44726 {
44728 machine_mode inner_mode;
44738 {
44742 {
44748 else
44749 {
44754 }
44755 }
44758 }
44763 {
44769 }
44771 {
44777 }
44778 else
44780 }
44781 }
44783 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44784 instructions unless MMX_OK is true. */
44786 void
44788 {
44795 rtx x;
44798 {
44808 }
44810 /* Constants are best loaded from the constant pool. */
44812 {
44815 }
44817 /* If all values are identical, broadcast the value. */
44823 /* Values where only one field is non-constant are best loaded from
44824 the pool and overwritten via move later. */
44826 {
44830 one_var))
44835 }
44838 }
44840 void
44842 {
44845 machine_mode half_mode;
44847 rtx tmp;
44849 = {
44856 };
44858 = {
44865 };
44871 {
44875 {
44880 else
44884 }
44896 else
44902 {
44905 /* For the two element vectors, we implement a VEC_CONCAT with
44906 the extraction of the other element. */
44913 else
44918 }
44927 {
44933 /* tmp = target = A B C D */
44935 /* target = A A B B */
44937 /* target = X A B B */
44939 /* target = A X C D */
44946 /* tmp = target = A B C D */
44948 /* tmp = X B C D */
44950 /* target = A B X D */
44957 /* tmp = target = A B C D */
44959 /* tmp = X B C D */
44961 /* target = A B X D */
44969 }
44977 /* Element 0 handled by vec_merge below. */
44979 {
44982 }
44985 {
44986 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44987 store into element 0, then shuffle them back. */
45004 }
45005 else
45006 {
45007 /* For SSE1, we have to reuse the V4SF code. */
45011 }
45064 half:
45065 /* Compute offset. */
45071 /* Extract the half. */
45075 /* Put val in tmp at elt. */
45078 /* Put it back. */
45084 {
45087 }
45092 {
45095 }
45100 {
45103 }
45108 {
45111 }
45116 {
45119 }
45124 {
45127 }
45132 }
45135 {
45141 }
45143 {
45147 }
45148 else
45149 {
45158 }
45159 }
45161 void
45163 {
45167 rtx tmp;
45170 {
45175 /* FALLTHRU */
45188 {
45208 }
45220 {
45222 {
45242 }
45246 }
45247 else
45248 {
45249 /* For SSE1, we have to reuse the V4SF code. */
45253 }
45269 {
45273 else
45277 }
45282 {
45286 else
45290 }
45295 {
45299 else
45303 }
45308 {
45312 else
45316 }
45321 {
45325 else
45329 }
45334 {
45338 else
45342 }
45347 {
45351 else
45355 }
45360 {
45364 else
45368 }
45375 else
45384 else
45393 else
45402 else
45408 /* ??? Could extract the appropriate HImode element and shift. */
45411 }
45414 {
45418 /* Let the rtl optimizers know about the zero extension performed. */
45420 {
45423 }
45426 }
45427 else
45428 {
45435 }
45436 }
45438 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45439 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45440 The upper bits of DEST are undefined, though they shouldn't cause
45441 exceptions (some bits from src or all zeros are ok). */
45443 static void
45445 {
45448 {
45452 else
45470 else
45477 else
45485 {
45490 const1_rtx);
45491 }
45492 else
45493 {
45497 }
45519 else
45541 }
45545 }
45547 /* Expand a vector reduction. FN is the binary pattern to reduce;
45548 DEST is the destination; IN is the input vector. */
45550 void
45552 {
45557 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45561 {
45564 }
45569 {
45574 else
45578 }
45579 }
45580 \f
45581 /* Target hook for scalar_mode_supported_p. */
45582 static bool
45584 {
45589 else
45591 }
45593 /* Implements target hook vector_mode_supported_p. */
45594 static bool
45596 {
45610 }
45612 /* Implement target hook libgcc_floating_mode_supported_p. */
45613 static bool
45615 {
45617 {
45624 #ifdef IX86_NO_LIBGCC_TFMODE
45626 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45628 #else
45630 #endif
45634 }
45635 }
45637 /* Target hook for c_mode_for_suffix. */
45638 static machine_mode
45640 {
45647 }
45649 /* Worker function for TARGET_MD_ASM_ADJUST.
45651 We implement asm flag outputs, and maintain source compatibility
45652 with the old cc0-based compiler. */
45658 {
45666 {
45672 {
45675 }
45685 {
45734 }
45736 {
45739 }
45745 {
45746 /* This is the first asm flag output. Here we put the flags
45747 register in as the real output and adjust the condition to
45748 allow it. */
45752 }
45753 else
45754 {
45755 /* We don't need the flags register as output twice. */
45758 }
45765 {
45768 }
45770 {
45774 }
45776 }
45782 else
45783 {
45784 /* If we had no asm flag outputs, clobber the flags. */
45788 }
45789 }
45791 /* Implements target vector targetm.asm.encode_section_info. */
45793 static void ATTRIBUTE_UNUSED
45795 {
45800 }
45802 /* Worker function for REVERSE_CONDITION. */
45804 enum rtx_code
45806 {
45810 }
45812 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45813 to OPERANDS[0]. */
45817 {
45819 {
45822 {
45826 }
45830 }
45832 {
45836 else
45837 {
45838 /* There is no non-popping store to memory for XFmode.
45839 So if we need one, follow the store with a load. */
45842 else
45844 }
45845 }
45846 else
45848 }
45850 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45851 FP status register is set. */
45853 void
45855 {
45857 rtx temp;
45862 {
45867 }
45868 else
45869 {
45874 }
45878 pc_rtx);
45883 }
45885 /* Output code to perform a log1p XFmode calculation. */
45888 {
45894 rtx test;
45900 XFmode));
45914 }
45916 /* Emit code for round calculation. */
45918 {
45925 rtx insn;
45930 {
45942 }
45945 {
45966 }
45974 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45976 /* scratch = fxam(op1) */
45979 UNSPEC_FXAM)));
45980 /* e1 = fabs(op1) */
45983 /* e2 = e1 + 0.5 */
45987 /* res = floor(e2) */
45989 {
45993 }
45994 else
45998 {
46001 {
46008 UNSPEC_TRUNC_NOOP)));
46009 }
46025 }
46027 /* flags = signbit(a) */
46030 /* if (flags) then res = -res */
46034 pc_rtx);
46045 }
46047 /* Output code to perform a Newton-Rhapson approximation of a single precision
46048 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
46051 {
46059 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
46063 /* x0 = rcp(b) estimate */
46066 UNSPEC_RCP14)));
46067 else
46069 UNSPEC_RCP)));
46071 /* e0 = x0 * b */
46074 /* e0 = x0 * e0 */
46077 /* e1 = x0 + x0 */
46080 /* x1 = e1 - e0 */
46083 /* res = a * x1 */
46085 }
46087 /* Output code to perform a Newton-Rhapson approximation of a
46088 single precision floating point [reciprocal] square root. */
46092 {
46094 REAL_VALUE_TYPE r;
46111 {
46114 /* There is no 512-bit rsqrt. There is however rsqrt14. */
46117 }
46119 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
46120 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
46124 /* x0 = rsqrt(a) estimate */
46126 unspec)));
46128 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
46130 {
46138 /* Handle masked compare. */
46140 {
46142 /* Imm value 0x4 corresponds to not-equal comparison. */
46145 }
46146 else
46147 {
46151 }
46152 }
46154 /* e0 = x0 * a */
46156 /* e1 = e0 * x0 */
46159 /* e2 = e1 - 3. */
46165 /* e3 = -.5 * x0 */
46167 else
46168 /* e3 = -.5 * e0 */
46170 /* ret = e2 * e3 */
46172 }
46174 #ifdef TARGET_SOLARIS
46175 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
46177 static void
46179 tree decl)
46180 {
46181 /* With Binutils 2.15, the "@unwind" marker must be specified on
46182 every occurrence of the ".eh_frame" section, not just the first
46183 one. */
46186 {
46190 }
46192 #ifndef USE_GAS
46194 {
46197 }
46198 #endif
46201 }
46204 /* Return the mangling of TYPE if it is an extended fundamental type. */
46208 {
46216 {
46218 /* __float128 is "g". */
46221 /* "long double" or __float80 is "e". */
46225 }
46226 }
46228 /* For 32-bit code we can save PIC register setup by using
46229 __stack_chk_fail_local hidden function instead of calling
46230 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
46231 register, so it is better to call __stack_chk_fail directly. */
46233 static tree ATTRIBUTE_UNUSED
46235 {
46236 return TARGET_64BIT
46239 }
46241 /* Select a format to encode pointers in exception handling data. CODE
46242 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
46243 true if the symbol may be affected by dynamic relocations.
46245 ??? All x86 object file formats are capable of representing this.
46246 After all, the relocation needed is the same as for the call insn.
46247 Whether or not a particular assembler allows us to enter such, I
46248 guess we'll have to see. */
46249 int
46251 {
46253 {
46260 }
46265 }
46266 \f
46267 /* Expand copysign from SIGN to the positive value ABS_VALUE
46268 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
46269 the sign-bit. */
46270 static void
46272 {
46276 {
46277 machine_mode vmode;
46283 else
46288 {
46289 /* We need to generate a scalar mode mask in this case. */
46294 }
46295 }
46296 else
46300 }
46302 /* Expand fabs (OP0) and return a new rtx that holds the result. The
46303 mask for masking out the sign-bit is stored in *SMASK, if that is
46304 non-null. */
46305 static rtx
46307 {
46316 else
46320 {
46321 /* We need to generate a scalar mode mask in this case. */
46326 }
46333 }
46335 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46336 swapping the operands if SWAP_OPERANDS is true. The expanded
46337 code is a forward jump to a newly created label in case the
46338 comparison is true. The generated label rtx is returned. */
46342 {
46345 rtx tmp;
46360 }
46362 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46363 using comparison code CODE. Operands are swapped for the comparison if
46364 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46365 static rtx
46368 {
46381 }
46383 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46384 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46385 static rtx
46387 {
46388 REAL_VALUE_TYPE TWO52r;
46389 rtx TWO52;
46396 }
46398 /* Expand SSE sequence for computing lround from OP1 storing
46399 into OP0. */
46400 void
46402 {
46403 /* C code for the stuff we're doing below:
46404 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46405 return (long)tmp;
46406 */
46410 rtx adj;
46412 /* load nextafter (0.5, 0.0) */
46417 /* adj = copysign (0.5, op1) */
46421 /* adj = op1 + adj */
46424 /* op0 = (imode)adj */
46426 }
46428 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46429 into OPERAND0. */
46430 void
46432 {
46433 /* C code for the stuff we're doing below (for do_floor):
46434 xi = (long)op1;
46435 xi -= (double)xi > op1 ? 1 : 0;
46436 return xi;
46437 */
46443 /* reg = (long)op1 */
46447 /* freg = (double)reg */
46451 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46462 }
46464 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46465 result in OPERAND0. */
46466 void
46468 {
46469 /* C code for the stuff we're doing below:
46470 xa = fabs (operand1);
46471 if (!isless (xa, 2**52))
46472 return operand1;
46473 xa = xa + 2**52 - 2**52;
46474 return copysign (xa, operand1);
46475 */
46483 /* xa = abs (operand1) */
46486 /* if (!isless (xa, TWO52)) goto label; */
46499 }
46501 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46502 into OPERAND0. */
46503 void
46505 {
46506 /* C code for the stuff we expand below.
46507 double xa = fabs (x), x2;
46508 if (!isless (xa, TWO52))
46509 return x;
46510 xa = xa + TWO52 - TWO52;
46511 x2 = copysign (xa, x);
46512 Compensate. Floor:
46513 if (x2 > x)
46514 x2 -= 1;
46515 Compensate. Ceil:
46516 if (x2 < x)
46517 x2 -= -1;
46518 return x2;
46519 */
46526 /* Temporary for holding the result, initialized to the input
46527 operand to ease control flow. */
46531 /* xa = abs (operand1) */
46534 /* if (!isless (xa, TWO52)) goto label; */
46537 /* xa = xa + TWO52 - TWO52; */
46541 /* xa = copysign (xa, operand1) */
46544 /* generate 1.0 or -1.0 */
46549 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46552 /* We always need to subtract here to preserve signed zero. */
46561 }
46563 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46564 into OPERAND0. */
46565 void
46567 {
46568 /* C code for the stuff we expand below.
46569 double xa = fabs (x), x2;
46570 if (!isless (xa, TWO52))
46571 return x;
46572 x2 = (double)(long)x;
46573 Compensate. Floor:
46574 if (x2 > x)
46575 x2 -= 1;
46576 Compensate. Ceil:
46577 if (x2 < x)
46578 x2 += 1;
46579 if (HONOR_SIGNED_ZEROS (mode))
46580 return copysign (x2, x);
46581 return x2;
46582 */
46589 /* Temporary for holding the result, initialized to the input
46590 operand to ease control flow. */
46594 /* xa = abs (operand1) */
46597 /* if (!isless (xa, TWO52)) goto label; */
46600 /* xa = (double)(long)x */
46605 /* generate 1.0 */
46608 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46622 }
46624 /* Expand SSE sequence for computing round from OPERAND1 storing
46625 into OPERAND0. Sequence that works without relying on DImode truncation
46626 via cvttsd2siq that is only available on 64bit targets. */
46627 void
46629 {
46630 /* C code for the stuff we expand below.
46631 double xa = fabs (x), xa2, x2;
46632 if (!isless (xa, TWO52))
46633 return x;
46634 Using the absolute value and copying back sign makes
46635 -0.0 -> -0.0 correct.
46636 xa2 = xa + TWO52 - TWO52;
46637 Compensate.
46638 dxa = xa2 - xa;
46639 if (dxa <= -0.5)
46640 xa2 += 1;
46641 else if (dxa > 0.5)
46642 xa2 -= 1;
46643 x2 = copysign (xa2, x);
46644 return x2;
46645 */
46652 /* Temporary for holding the result, initialized to the input
46653 operand to ease control flow. */
46657 /* xa = abs (operand1) */
46660 /* if (!isless (xa, TWO52)) goto label; */
46663 /* xa2 = xa + TWO52 - TWO52; */
46667 /* dxa = xa2 - xa; */
46670 /* generate 0.5, 1.0 and -0.5 */
46676 /* Compensate. */
46678 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46682 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46687 /* res = copysign (xa2, operand1) */
46694 }
46696 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46697 into OPERAND0. */
46698 void
46700 {
46701 /* C code for SSE variant we expand below.
46702 double xa = fabs (x), x2;
46703 if (!isless (xa, TWO52))
46704 return x;
46705 x2 = (double)(long)x;
46706 if (HONOR_SIGNED_ZEROS (mode))
46707 return copysign (x2, x);
46708 return x2;
46709 */
46716 /* Temporary for holding the result, initialized to the input
46717 operand to ease control flow. */
46721 /* xa = abs (operand1) */
46724 /* if (!isless (xa, TWO52)) goto label; */
46727 /* x = (double)(long)x */
46739 }
46741 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46742 into OPERAND0. */
46743 void
46745 {
46750 /* C code for SSE variant we expand below.
46751 double xa = fabs (x), x2;
46752 if (!isless (xa, TWO52))
46753 return x;
46754 xa2 = xa + TWO52 - TWO52;
46755 Compensate:
46756 if (xa2 > xa)
46757 xa2 -= 1.0;
46758 x2 = copysign (xa2, x);
46759 return x2;
46760 */
46764 /* Temporary for holding the result, initialized to the input
46765 operand to ease control flow. */
46769 /* xa = abs (operand1) */
46772 /* if (!isless (xa, TWO52)) goto label; */
46775 /* res = xa + TWO52 - TWO52; */
46780 /* generate 1.0 */
46783 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46790 /* res = copysign (res, operand1) */
46797 }
46799 /* Expand SSE sequence for computing round from OPERAND1 storing
46800 into OPERAND0. */
46801 void
46803 {
46804 /* C code for the stuff we're doing below:
46805 double xa = fabs (x);
46806 if (!isless (xa, TWO52))
46807 return x;
46808 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46809 return copysign (xa, x);
46810 */
46817 /* Temporary for holding the result, initialized to the input
46818 operand to ease control flow. */
46826 /* load nextafter (0.5, 0.0) */
46831 /* xa = xa + 0.5 */
46835 /* xa = (double)(int64_t)xa */
46840 /* res = copysign (xa, operand1) */
46847 }
46849 /* Expand SSE sequence for computing round
46850 from OP1 storing into OP0 using sse4 round insn. */
46851 void
46853 {
46862 {
46873 }
46875 /* round (a) = trunc (a + copysign (0.5, a)) */
46877 /* load nextafter (0.5, 0.0) */
46883 /* e1 = copysign (0.5, op1) */
46887 /* e2 = op1 + e1 */
46890 /* res = trunc (e2) */
46895 }
46896 \f
46898 /* Table of valid machine attributes. */
46900 {
46901 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46902 affects_type_identity } */
46903 /* Stdcall attribute says callee is responsible for popping arguments
46904 if they are not variable. */
46907 /* Fastcall attribute says callee is responsible for popping arguments
46908 if they are not variable. */
46911 /* Thiscall attribute says callee is responsible for popping arguments
46912 if they are not variable. */
46915 /* Cdecl attribute says the callee is a normal C declaration */
46918 /* Regparm attribute specifies how many integer arguments are to be
46919 passed in registers. */
46922 /* Sseregparm attribute says we are using x86_64 calling conventions
46923 for FP arguments. */
46926 /* The transactional memory builtins are implicitly regparm or fastcall
46927 depending on the ABI. Override the generic do-nothing attribute that
46928 these builtins were declared with. */
46931 /* force_align_arg_pointer says this function realigns the stack at entry. */
46934 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46939 #endif
46944 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46945 SUBTARGET_ATTRIBUTE_TABLE,
46946 #endif
46947 /* ms_abi and sysv_abi calling convention function attributes. */
46954 /* End element. */
46956 };
46958 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46959 static int
46962 {
46966 {
47011 }
47012 }
47014 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
47015 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
47016 insn every time. */
47020 /* Initialize vselect_insn. */
47022 static void
47024 {
47026 rtx x;
47037 }
47039 /* Construct (set target (vec_select op0 (parallel perm))) and
47040 return true if that's a valid instruction in the active ISA. */
47042 static bool
47045 {
47071 }
47073 /* Similar, but generate a vec_concat from op0 and op1 as well. */
47075 static bool
47079 {
47080 machine_mode v2mode;
47081 rtx x;
47096 }
47098 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47099 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
47101 static bool
47103 {
47112 && (TARGET_AVX512BW
47114 ;
47116 ;
47118 ;
47120 ;
47121 else
47124 /* This is a blend, not a permute. Elements must stay in their
47125 respective lanes. */
47127 {
47131 }
47136 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
47137 decision should be extracted elsewhere, so that we only try that
47138 sequence once all budget==3 options have been tried. */
47145 {
47175 /* See if bytes move in pairs so we can use pblendw with
47176 an immediate argument, rather than pblendvb with a vector
47177 argument. */
47180 {
47181 use_pblendvb:
47185 finish_pblendvb:
47191 else
47196 }
47201 /* FALLTHRU */
47203 do_subreg:
47210 /* See if bytes move in pairs. If not, vpblendvb must be used. */
47214 /* See if bytes move in quadruplets. If yes, vpblendd
47215 with immediate can be used. */
47220 {
47221 /* See if bytes move the same in both lanes. If yes,
47222 vpblendw with immediate can be used. */
47227 /* Use vpblendw. */
47232 }
47234 /* Use vpblendd. */
47241 /* See if words move in pairs. If yes, vpblendd can be used. */
47246 {
47247 /* See if words move the same in both lanes. If not,
47248 vpblendvb must be used. */
47251 {
47252 /* Use vpblendvb. */
47262 }
47264 /* Use vpblendw. */
47268 }
47270 /* Use vpblendd. */
47277 /* Use vpblendd. */
47285 }
47288 {
47305 }
47309 else
47312 /* This matches five different patterns with the different modes. */
47320 }
47322 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47323 in terms of the variable form of vpermilps.
47325 Note that we will have already failed the immediate input vpermilps,
47326 which requires that the high and low part shuffle be identical; the
47327 variable form doesn't require that. */
47329 static bool
47331 {
47338 /* We can only permute within the 128-bit lane. */
47340 {
47344 }
47350 {
47353 /* Within each 128-bit lane, the elements of op0 are numbered
47354 from 0 and the elements of op1 are numbered from 4. */
47361 }
47368 }
47370 /* Return true if permutation D can be performed as VMODE permutation
47371 instead. */
47373 static bool
47375 {
47390 else
47396 }
47398 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47399 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47401 static bool
47403 {
47412 {
47414 {
47417 {
47421 /* Use vperm2i128 insn. The pattern uses
47422 V4DImode instead of V2TImode. */
47435 }
47437 }
47438 }
47439 else
47440 {
47442 {
47445 }
47447 {
47451 /* V4DImode should be already handled through
47452 expand_vselect by vpermq instruction. */
47459 {
47460 /* First see if vpermq can be used for
47461 V8SImode/V16HImode/V32QImode. */
47463 {
47471 {
47475 }
47477 }
47479 /* Next see if vpermd can be used. */
47482 }
47483 /* Or if vpermps can be used. */
47488 {
47489 /* vpshufb only works intra lanes, it is not
47490 possible to shuffle bytes in between the lanes. */
47494 }
47495 }
47497 {
47501 /* If vpermq didn't work, vpshufb won't work either. */
47509 {
47510 /* First see if vpermq can be used for
47511 V16SImode/V32HImode/V64QImode. */
47513 {
47521 {
47525 }
47527 }
47529 /* Next see if vpermd can be used. */
47532 }
47533 /* Or if vpermps can be used. */
47537 {
47538 /* vpshufb only works intra lanes, it is not
47539 possible to shuffle bytes in between the lanes. */
47543 }
47544 }
47545 else
47547 }
47558 else
47559 {
47567 else
47571 {
47575 }
47576 }
47587 {
47602 else
47604 }
47605 else
47606 {
47609 }
47614 }
47616 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47617 in a single instruction. */
47619 static bool
47621 {
47625 /* Check plain VEC_SELECT first, because AVX has instructions that could
47626 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47627 input where SEL+CONCAT may not. */
47629 {
47635 {
47641 }
47644 {
47648 }
47650 {
47651 /* Use vpbroadcast{b,w,d}. */
47654 {
47697 /* For other modes prefer other shuffles this function creates. */
47699 }
47701 {
47705 }
47706 }
47711 /* There are plenty of patterns in sse.md that are written for
47712 SEL+CONCAT and are not replicated for a single op. Perhaps
47713 that should be changed, to avoid the nastiness here. */
47715 /* Recognize interleave style patterns, which means incrementing
47716 every other permutation operand. */
47718 {
47721 }
47726 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47728 {
47730 {
47735 }
47740 }
47741 }
47743 /* Finally, try the fully general two operand permute. */
47748 /* Recognize interleave style patterns with reversed operands. */
47750 {
47752 {
47756 else
47759 }
47764 }
47766 /* Try the SSE4.1 blend variable merge instructions. */
47770 /* Try one of the AVX vpermil variable permutations. */
47774 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47775 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47779 /* Try the AVX2 vpalignr instruction. */
47783 /* Try the AVX512F vpermi2 instructions. */
47788 }
47790 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47791 in terms of a pair of pshuflw + pshufhw instructions. */
47793 static bool
47795 {
47803 /* The two permutations only operate in 64-bit lanes. */
47814 /* Emit the pshuflw. */
47821 /* Emit the pshufhw. */
47829 }
47831 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47832 the permutation using the SSSE3 palignr instruction. This succeeds
47833 when all of the elements in PERM fit within one vector and we merely
47834 need to shift them down so that a single vector permutation has a
47835 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47836 the vpalignr instruction itself can perform the requested permutation. */
47838 static bool
47840 {
47847 /* Even with AVX, palignr only operates on 128-bit vectors,
47848 in AVX2 palignr operates on both 128-bit lanes. */
47858 {
47862 {
47865 }
47874 }
47877 {
47886 }
47888 /* Given that we have SSSE3, we know we'll be able to implement the
47889 single operand permutation after the palignr with pshufb for
47890 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47891 first. */
47897 {
47902 }
47906 {
47912 else
47917 }
47923 /* For AVX2, test whether we can permute the result in one instruction. */
47925 {
47930 }
47934 {
47938 }
47939 else
47940 {
47945 shift));
47946 }
47950 /* Test for the degenerate case where the alignment by itself
47951 produces the desired permutation. */
47953 {
47956 }
47962 }
47964 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47965 the permutation using the SSE4_1 pblendv instruction. Potentially
47966 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47968 static bool
47970 {
47976 /* Use the same checks as in expand_vec_perm_blend. */
47980 ;
47982 ;
47984 ;
47985 else
47988 /* Figure out where permutation elements stay not in their
47989 respective lanes. */
47991 {
47995 }
47996 /* We can pblend the part where elements stay not in their
47997 respective lanes only when these elements are all in one
47998 half of a permutation.
47999 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
48000 lanes, but both 8 and 9 >= 8
48001 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
48002 respective lanes and 8 >= 8, but 2 not. */
48008 /* First we apply one operand permutation to the part where
48009 elements stay not in their respective lanes. */
48013 else
48025 else
48030 /* Next we put permuted elements into their positions. */
48034 else
48044 }
48048 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48049 a two vector permutation into a single vector permutation by using
48050 an interleave operation to merge the vectors. */
48052 static bool
48054 {
48063 {
48066 }
48068 {
48071 /* For 32-byte modes allow even d->one_operand_p.
48072 The lack of cross-lane shuffling in some instructions
48073 might prevent a single insn shuffle. */
48076 /* If expand_vec_perm_interleave3 can expand this into
48077 a 3 insn sequence, give up and let it be expanded as
48078 3 insn sequence. While that is one insn longer,
48079 it doesn't need a memory operand and in the common
48080 case that both interleave low and high permutations
48081 with the same operands are adjacent needs 4 insns
48082 for both after CSE. */
48085 }
48086 else
48089 /* Examine from whence the elements come. */
48098 {
48101 /* Split the two input vectors into 4 halves. */
48107 /* If the elements from the low halves use interleave low, and similarly
48108 for interleave high. If the elements are from mis-matched halves, we
48109 can use shufps for V4SF/V4SI or do a DImode shuffle. */
48111 {
48112 /* punpckl* */
48114 {
48119 }
48122 }
48124 {
48125 /* punpckh* */
48127 {
48132 }
48135 }
48137 {
48138 /* shufps */
48140 {
48145 }
48147 {
48148 /* shufpd */
48153 }
48154 }
48156 {
48157 /* shufps */
48159 {
48164 }
48166 {
48167 /* shufpd */
48172 }
48173 }
48174 else
48176 }
48177 else
48178 {
48183 /* Split the two input vectors into 8 quarters. */
48189 {
48192 }
48195 {
48199 }
48201 {
48204 }
48207 {
48209 {
48210 /* Attempt to increase the likelihood that dfinal
48211 shuffle will be intra-lane. */
48213 }
48215 /* vperm2f128 or vperm2i128. */
48217 {
48222 }
48227 {
48231 {
48234 }
48235 }
48236 }
48241 {
48242 /* vpunpckl* */
48244 {
48253 }
48254 }
48257 {
48258 /* vpunpckh* */
48260 {
48269 }
48270 }
48271 else
48273 }
48275 /* Use the remapping array set up above to move the elements from their
48276 swizzled locations into their final destinations. */
48279 {
48282 /* If same_halves is true, both halves of the remapped vector are the
48283 same. Avoid cross-lane accesses if possible. */
48285 {
48288 }
48289 else
48291 }
48293 {
48296 }
48300 /* Test if the final remap can be done with a single insn. For V4SFmode or
48301 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
48314 {
48317 }
48324 }
48326 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48327 a single vector cross-lane permutation into vpermq followed
48328 by any of the single insn permutations. */
48330 static bool
48332 {
48346 {
48349 }
48352 {
48357 }
48370 {
48377 }
48384 {
48389 ;
48392 else
48394 }
48403 }
48405 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48406 a vector permutation using two instructions, vperm2f128 resp.
48407 vperm2i128 followed by any single in-lane permutation. */
48409 static bool
48411 {
48425 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48426 immediate. For perm < 16 the second permutation uses
48427 d->op0 as first operand, for perm >= 16 it uses d->op1
48428 as first operand. The second operand is the result of
48429 vperm2[fi]128. */
48431 {
48432 /* Ignore permutations which do not move anything cross-lane. */
48434 {
48435 /* The second shuffle for e.g. V4DFmode has
48436 0123 and ABCD operands.
48437 Ignore AB23, as 23 is already in the second lane
48438 of the first operand. */
48440 /* And 01CD, as 01 is in the first lane of the first
48441 operand. */
48443 /* And 4567, as then the vperm2[fi]128 doesn't change
48444 anything on the original 4567 second operand. */
48446 }
48447 else
48448 {
48449 /* The second shuffle for e.g. V4DFmode has
48450 4567 and ABCD operands.
48451 Ignore AB67, as 67 is already in the second lane
48452 of the first operand. */
48454 /* And 45CD, as 45 is in the first lane of the first
48455 operand. */
48457 /* And 0123, as then the vperm2[fi]128 doesn't change
48458 anything on the original 0123 first operand. */
48460 }
48463 {
48469 else
48471 }
48474 {
48478 }
48479 else
48483 {
48487 /* Found a usable second shuffle. dfirst will be
48488 vperm2f128 on d->op0 and d->op1. */
48500 /* And dsecond is some single insn shuffle, taking
48501 d->op0 and result of vperm2f128 (if perm < 16) or
48502 d->op1 and result of vperm2f128 (otherwise). */
48511 }
48513 /* For one operand, the only useful vperm2f128 permutation is 0x01
48514 aka lanes swap. */
48517 }
48520 }
48522 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48523 a two vector permutation using 2 intra-lane interleave insns
48524 and cross-lane shuffle for 32-byte vectors. */
48526 static bool
48528 {
48535 ;
48537 ;
48538 else
48553 {
48557 else
48563 else
48569 else
48575 else
48581 else
48587 else
48592 }
48596 }
48598 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48599 a single vector permutation using a single intra-lane vector
48600 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48601 the non-swapped and swapped vectors together. */
48603 static bool
48605 {
48613 || TARGET_AVX2
48622 {
48629 }
48664 }
48666 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48667 permutation using two vperm2f128, followed by a vshufpd insn blending
48668 the two vectors together. */
48670 static bool
48672 {
48715 }
48717 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48718 permutation with two pshufb insns and an ior. We should have already
48719 failed all two instruction sequences. */
48721 static bool
48723 {
48737 /* Generate two permutation masks. If the required element is within
48738 the given vector it is shuffled into the proper lane. If the required
48739 element is in the other vector, force a zero into the lane by setting
48740 bit 7 in the permutation mask. */
48743 {
48750 {
48753 }
48754 }
48778 }
48780 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48781 with two vpshufb insns, vpermq and vpor. We should have already failed
48782 all two or three instruction sequences. */
48784 static bool
48786 {
48801 /* Generate two permutation masks. If the required element is within
48802 the same lane, it is shuffled in. If the required element from the
48803 other lane, force a zero by setting bit 7 in the permutation mask.
48804 In the other mask the mask has non-negative elements if element
48805 is requested from the other lane, but also moved to the other lane,
48806 so that the result of vpshufb can have the two V2TImode halves
48807 swapped. */
48810 {
48815 {
48818 }
48819 }
48828 /* Swap the 128-byte lanes of h into hp. */
48832 const1_rtx));
48849 }
48851 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48852 and extract-odd permutations of two V32QImode and V16QImode operand
48853 with two vpshufb insns, vpor and vpermq. We should have already
48854 failed all two or three instruction sequences. */
48856 static bool
48858 {
48877 /* Generate two permutation masks. In the first permutation mask
48878 the first quarter will contain indexes for the first half
48879 of the op0, the second quarter will contain bit 7 set, third quarter
48880 will contain indexes for the second half of the op0 and the
48881 last quarter bit 7 set. In the second permutation mask
48882 the first quarter will contain bit 7 set, the second quarter
48883 indexes for the first half of the op1, the third quarter bit 7 set
48884 and last quarter indexes for the second half of the op1.
48885 I.e. the first mask e.g. for V32QImode extract even will be:
48886 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48887 (all values masked with 0xf except for -128) and second mask
48888 for extract even will be
48889 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48892 {
48898 {
48901 }
48902 }
48921 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48929 }
48931 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48932 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48933 with two "and" and "pack" or two "shift" and "pack" insns. We should
48934 have already failed all two instruction sequences. */
48936 static bool
48938 {
48942 machine_mode half_mode;
48951 {
48953 /* Required for "pack". */
48964 /* No check as all instructions are SSE2. */
48995 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48996 general shuffles. */
48998 }
49000 /* Check that permutation is even or odd. */
49015 {
49022 }
49023 else
49024 {
49031 }
49032 /* In AVX2 for 256 bit case we need to permute pack result. */
49034 {
49040 const0_rtx,
49041 const2_rtx,
49042 const1_rtx,
49045 }
49046 else
49050 }
49052 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
49053 and extract-odd permutations. */
49055 static bool
49057 {
49061 {
49068 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49072 /* Now an unpck[lh]pd will produce the result required. */
49075 else
49081 {
49090 /* Shuffle within the 128-bit lanes to produce:
49091 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
49095 /* Shuffle the lanes around to produce:
49096 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
49100 /* Shuffle within the 128-bit lanes to produce:
49101 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
49104 /* Shuffle within the 128-bit lanes to produce:
49105 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
49108 /* Shuffle the lanes around to produce:
49109 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
49112 }
49119 /* These are always directly implementable by expand_vec_perm_1. */
49127 else
49128 {
49131 /* We need 2*log2(N)-1 operations to achieve odd/even
49132 with interleave. */
49141 else
49144 }
49156 {
49161 else
49166 {
49171 }
49173 }
49181 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49185 /* Now an vpunpck[lh]qdq will produce the result required. */
49188 else
49195 {
49200 else
49205 {
49210 }
49212 }
49223 /* Shuffle the lanes around into
49224 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
49232 /* Swap the 2nd and 3rd position in each lane into
49233 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
49239 /* Now an vpunpck[lh]qdq will produce
49240 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
49244 else
49253 }
49256 }
49258 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49259 extract-even and extract-odd permutations. */
49261 static bool
49263 {
49275 }
49277 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
49278 permutations. We assume that expand_vec_perm_1 has already failed. */
49280 static bool
49282 {
49290 {
49293 /* These are special-cased in sse.md so that we can optionally
49294 use the vbroadcast instruction. They expand to two insns
49295 if the input happens to be in a register. */
49302 /* These are always implementable using standard shuffle patterns. */
49307 /* These can be implemented via interleave. We save one insn by
49308 stopping once we have promoted to V4SImode and then use pshufd. */
49311 do
49312 {
49313 rtx dest;
49319 {
49323 }
49330 }
49346 /* For AVX2 broadcasts of the first element vpbroadcast* or
49347 vpermq should be used by expand_vec_perm_1. */
49353 }
49354 }
49356 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49357 broadcast permutations. */
49359 static bool
49361 {
49373 }
49375 /* Implement arbitrary permutations of two V64QImode operands
49376 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49377 static bool
49379 {
49389 machine_mode vmode;
49395 {
49402 }
49404 /* Prepare permutations such that the first one takes care of
49405 putting the even bytes into the right positions or one higher
49406 positions (ds[0]) and the second one takes care of
49407 putting the odd bytes into the right positions or one below
49408 (ds[1]). */
49411 {
49414 {
49417 }
49418 else
49419 {
49422 }
49423 }
49445 }
49447 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49448 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49449 all the shorter instruction sequences. */
49451 static bool
49453 {
49469 /* Generate 4 permutation masks. If the required element is within
49470 the same lane, it is shuffled in. If the required element from the
49471 other lane, force a zero by setting bit 7 in the permutation mask.
49472 In the other mask the mask has non-negative elements if element
49473 is requested from the other lane, but also moved to the other lane,
49474 so that the result of vpshufb can have the two V2TImode halves
49475 swapped. */
49478 {
49483 }
49489 {
49497 }
49500 {
49502 {
49505 }
49512 }
49514 /* Swap the 128-byte lanes of h[X]. */
49516 {
49522 const1_rtx));
49524 }
49527 {
49529 {
49532 }
49538 }
49541 {
49543 {
49547 }
49550 }
49560 }
49562 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49563 With all of the interface bits taken care of, perform the expansion
49564 in D and return true on success. */
49566 static bool
49568 {
49569 /* Try a single instruction expansion. */
49573 /* Try sequences of two instructions. */
49596 /* Try sequences of three instructions. */
49613 /* Try sequences of four instructions. */
49624 /* ??? Look for narrow permutations whose element orderings would
49625 allow the promotion to a wider mode. */
49627 /* ??? Look for sequences of interleave or a wider permute that place
49628 the data into the correct lanes for a half-vector shuffle like
49629 pshuf[lh]w or vpermilps. */
49631 /* ??? Look for sequences of interleave that produce the desired results.
49632 The combinatorics of punpck[lh] get pretty ugly... */
49637 /* Even longer sequences. */
49642 }
49644 /* If a permutation only uses one operand, make it clear. Returns true
49645 if the permutation references both operands. */
49647 static bool
49649 {
49657 {
49663 {
49666 }
49667 /* The elements of PERM do not suggest that only the first operand
49668 is used, but both operands are identical. Allow easier matching
49669 of the permutation by folding the permutation into the single
49670 input vector. */
49671 /* FALLTHRU */
49682 }
49685 }
49687 bool
49689 {
49694 rtx sel;
49711 {
49716 }
49723 /* If the selector says both arguments are needed, but the operands are the
49724 same, the above tried to expand with one_operand_p and flattened selector.
49725 If that didn't work, retry without one_operand_p; we succeeded with that
49726 during testing. */
49728 {
49732 }
49735 }
49737 /* Implement targetm.vectorize.vec_perm_const_ok. */
49739 static bool
49742 {
49751 /* Given sufficient ISA support we can just return true here
49752 for selected vector modes. */
49754 {
49760 /* All implementable with a single vpermi2 insn. */
49765 /* All implementable with a single vpermi2 insn. */
49770 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49778 /* All implementable with a single vpermi2 insn. */
49783 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49788 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49795 /* All implementable with a single vpperm insn. */
49798 /* All implementable with 2 pshufb + 1 ior. */
49804 /* All implementable with shufpd or unpck[lh]pd. */
49808 }
49810 /* Extract the values from the vector CST into the permutation
49811 array in D. */
49814 {
49818 }
49820 /* For all elements from second vector, fold the elements to first. */
49825 /* Check whether the mask can be applied to the vector type. */
49828 /* Implementable with shufps or pshufd. */
49832 /* Otherwise we have to go through the motions and see if we can
49833 figure out how to generate the requested permutation. */
49844 }
49846 void
49848 {
49863 /* We'll either be able to implement the permutation directly... */
49867 /* ... or we use the special-case patterns. */
49869 }
49871 static void
49873 {
49888 {
49891 }
49893 /* Note that for AVX this isn't one instruction. */
49896 }
49899 /* Expand a vector operation CODE for a V*QImode in terms of the
49900 same operation on V*HImode. */
49902 void
49904 {
49906 machine_mode himode;
49916 {
49934 }
49938 {
49940 /* Unpack data such that we've got a source byte in each low byte of
49941 each word. We don't care what goes into the high byte of each word.
49942 Rather than trying to get zero in there, most convenient is to let
49943 it be a copy of the low byte. */
49948 /* FALLTHRU */
49960 /* FALLTHRU */
49970 }
49972 /* Perform the operation. */
49979 /* Merge the data back into the right place. */
49989 {
49990 /* For SSE2, we used an full interleave, so the desired
49991 results are in the even elements. */
49994 }
49995 else
49996 {
49997 /* For AVX, the interleave used above was not cross-lane. So the
49998 extraction is evens but with the second and third quarter swapped.
49999 Happily, that is even one insn shorter than even extraction. */
50002 }
50009 }
50011 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
50012 if op is CONST_VECTOR with all odd elements equal to their
50013 preceding element. */
50015 static bool
50017 {
50027 }
50029 void
50032 {
50035 rtx x;
50043 /* We only play even/odd games with vectors of SImode. */
50046 /* If we're looking for the odd results, shift those members down to
50047 the even slots. For some cpus this is faster than a PSHUFD. */
50049 {
50050 /* For XOP use vpmacsdqh, but only for smult, as it is only
50051 signed. */
50053 {
50057 }
50068 }
50071 {
50074 else
50076 }
50078 {
50081 else
50083 }
50088 else
50089 {
50092 /* The easiest way to implement this without PMULDQ is to go through
50093 the motions as if we are performing a full 64-bit multiply. With
50094 the exception that we need to do less shuffling of the elements. */
50096 /* Compute the sign-extension, aka highparts, of the two operands. */
50102 /* Multiply LO(A) * HI(B), and vice-versa. */
50108 /* Multiply LO(A) * LO(B). */
50112 /* Combine and shift the highparts into place. */
50117 /* Combine high and low parts. */
50120 }
50122 }
50124 void
50127 {
50133 {
50138 {
50139 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
50140 shuffle the elements once so that all elements are in the right
50141 place for immediate use: { A C B D }. */
50146 }
50147 else
50148 {
50149 /* Put the elements into place for the multiply. */
50153 }
50158 /* Shuffle the elements between the lanes. After this we
50159 have { A B E F | C D G H } for each operand. */
50169 /* Shuffle the elements within the lanes. After this we
50170 have { A A B B | C C D D } or { E E F F | G G H H }. */
50211 }
50212 }
50214 void
50216 {
50226 /* Move the results in element 2 down to element 1; we don't care
50227 what goes in elements 2 and 3. Then we can merge the parts
50228 back together with an interleave.
50230 Note that two other sequences were tried:
50231 (1) Use interleaves at the start instead of psrldq, which allows
50232 us to use a single shufps to merge things back at the end.
50233 (2) Use shufps here to combine the two vectors, then pshufd to
50234 put the elements in the correct order.
50235 In both cases the cost of the reformatting stall was too high
50236 and the overall sequence slower. */
50247 }
50249 void
50251 {
50262 {
50263 /* op1: A,B,C,D, op2: E,F,G,H */
50272 /* t1: B,A,D,C */
50279 /* t2: (B*E),(A*F),(D*G),(C*H) */
50282 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
50285 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
50288 /* Multiply lower parts and add all */
50295 }
50296 else
50297 {
50298 machine_mode nmode;
50302 {
50305 }
50307 {
50310 }
50312 {
50315 }
50316 else
50320 /* Multiply low parts. */
50324 /* Shift input vectors right 32 bits so we can multiply high parts. */
50329 /* Multiply high parts by low parts. */
50335 /* Combine and shift the highparts back. */
50339 /* Combine high and low parts. */
50341 }
50345 }
50347 /* Return 1 if control tansfer instruction INSN
50348 should be encoded with bnd prefix.
50349 If insn is NULL then return 1 when control
50350 transfer instructions should be prefixed with
50351 bnd by default for current function. */
50353 bool
50355 {
50356 /* For call insns check special flag. */
50358 {
50362 }
50364 /* All other insns are prefixed only if function is instrumented. */
50366 }
50368 /* Calculate integer abs() using only SSE2 instructions. */
50370 void
50372 {
50377 {
50378 /* For 32-bit signed integer X, the best way to calculate the absolute
50379 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50391 /* For 16-bit signed integer X, the best way to calculate the absolute
50392 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50400 /* For 8-bit signed integer X, the best way to calculate the absolute
50401 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50402 as SSE2 provides the PMINUB insn. */
50412 }
50416 }
50418 /* Expand an insert into a vector register through pinsr insn.
50419 Return true if successful. */
50421 bool
50423 {
50431 {
50434 }
50440 {
50445 {
50452 {
50484 }
50498 }
50502 }
50503 }
50504 \f
50505 /* This function returns the calling abi specific va_list type node.
50506 It returns the FNDECL specific va_list type. */
50508 static tree
50510 {
50517 else
50519 }
50521 /* Returns the canonical va_list type specified by TYPE. If there
50522 is no valid TYPE provided, it return NULL_TREE. */
50524 static tree
50526 {
50529 /* Resolve references and pointers to va_list type. */
50538 {
50543 {
50544 /* If va_list is an array type, the argument may have decayed
50545 to a pointer type, e.g. by being passed to another function.
50546 In that case, unwrap both types so that we can compare the
50547 underlying records. */
50550 {
50553 }
50554 }
50561 {
50562 /* If va_list is an array type, the argument may have decayed
50563 to a pointer type, e.g. by being passed to another function.
50564 In that case, unwrap both types so that we can compare the
50565 underlying records. */
50568 {
50571 }
50572 }
50579 {
50580 /* If va_list is an array type, the argument may have decayed
50581 to a pointer type, e.g. by being passed to another function.
50582 In that case, unwrap both types so that we can compare the
50583 underlying records. */
50586 {
50589 }
50590 }
50594 }
50596 }
50598 /* Iterate through the target-specific builtin types for va_list.
50599 IDX denotes the iterator, *PTREE is set to the result type of
50600 the va_list builtin, and *PNAME to its internal type.
50601 Returns zero if there is no element for this index, otherwise
50602 IDX should be increased upon the next call.
50603 Note, do not iterate a base builtin's name like __builtin_va_list.
50604 Used from c_common_nodes_and_builtins. */
50606 static int
50608 {
50610 {
50612 {
50625 }
50626 }
50629 }
50631 #undef TARGET_SCHED_DISPATCH
50632 #define TARGET_SCHED_DISPATCH has_dispatch
50633 #undef TARGET_SCHED_DISPATCH_DO
50634 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50635 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50636 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50637 #undef TARGET_SCHED_REORDER
50638 #define TARGET_SCHED_REORDER ix86_sched_reorder
50639 #undef TARGET_SCHED_ADJUST_PRIORITY
50640 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50641 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50642 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50643 ix86_dependencies_evaluation_hook
50645 /* The size of the dispatch window is the total number of bytes of
50646 object code allowed in a window. */
50647 #define DISPATCH_WINDOW_SIZE 16
50649 /* Number of dispatch windows considered for scheduling. */
50650 #define MAX_DISPATCH_WINDOWS 3
50652 /* Maximum number of instructions in a window. */
50653 #define MAX_INSN 4
50655 /* Maximum number of immediate operands in a window. */
50656 #define MAX_IMM 4
50658 /* Maximum number of immediate bits allowed in a window. */
50659 #define MAX_IMM_SIZE 128
50661 /* Maximum number of 32 bit immediates allowed in a window. */
50662 #define MAX_IMM_32 4
50664 /* Maximum number of 64 bit immediates allowed in a window. */
50665 #define MAX_IMM_64 2
50667 /* Maximum total of loads or prefetches allowed in a window. */
50668 #define MAX_LOAD 2
50670 /* Maximum total of stores allowed in a window. */
50671 #define MAX_STORE 1
50673 #undef BIG
50674 #define BIG 100
50677 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50680 disp_load,
50681 disp_store,
50682 disp_load_store,
50683 disp_prefetch,
50684 disp_imm,
50685 disp_imm_32,
50686 disp_imm_64,
50687 disp_branch,
50688 disp_cmp,
50689 disp_jcc,
50690 disp_last
50691 };
50693 /* Number of allowable groups in a dispatch window. It is an array
50694 indexed by dispatch_group enum. 100 is used as a big number,
50695 because the number of these kind of operations does not have any
50696 effect in dispatch window, but we need them for other reasons in
50697 the table. */
50700 };
50706 };
50708 /* Instruction path. */
50714 last_path
50715 };
50717 /* sched_insn_info defines a window to the instructions scheduled in
50718 the basic block. It contains a pointer to the insn_info table and
50719 the instruction scheduled.
50721 Windows are allocated for each basic block and are linked
50722 together. */
50724 rtx insn;
50731 /* Linked list of dispatch windows. This is a two way list of
50732 dispatch windows of a basic block. It contains information about
50733 the number of uops in the window and the total number of
50734 instructions and of bytes in the object code for this dispatch
50735 window. */
50753 /* Immediate valuse used in an insn. */
50755 {
50764 /* Get dispatch group of insn. */
50766 static enum dispatch_group
50768 {
50784 }
50786 /* Return true if insn is a compare instruction. */
50788 static bool
50790 {
50798 }
50800 /* Return true if a dispatch violation encountered. */
50802 static bool
50804 {
50808 }
50810 /* Return true if insn is a branch instruction. */
50812 static bool
50814 {
50816 }
50818 /* Return true if insn is a prefetch instruction. */
50820 static bool
50822 {
50824 }
50826 /* This function initializes a dispatch window and the list container holding a
50827 pointer to the window. */
50829 static void
50831 {
50837 else
50855 {
50861 }
50863 }
50865 /* This function allocates and initializes a dispatch window and the
50866 list container holding a pointer to the window. */
50870 {
50875 }
50877 /* This routine initializes the dispatch scheduling information. It
50878 initiates building dispatch scheduler tables and constructs the
50879 first dispatch window. */
50881 static void
50883 {
50884 /* Allocate a dispatch list and a window. */
50889 }
50891 /* This function returns true if a branch is detected. End of a basic block
50892 does not have to be a branch, but here we assume only branches end a
50893 window. */
50895 static bool
50897 {
50899 }
50901 /* This function is called when the end of a window processing is reached. */
50903 static void
50905 {
50908 {
50913 }
50915 }
50917 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50918 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50919 for 48 bytes of instructions. Note that these windows are not dispatch
50920 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50924 {
50926 {
50931 }
50937 }
50939 /* Compute number of immediate operands of an instruction. */
50941 static void
50943 {
50950 {
50957 else
50969 {
50972 }
50977 }
50978 }
50980 /* Return total size of immediate operands of an instruction along with number
50981 of corresponding immediate-operands. It initializes its parameters to zero
50982 befor calling FIND_CONSTANT.
50983 INSN is the input instruction. IMM is the total of immediates.
50984 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50985 bit immediates. */
50987 static int
50989 {
50997 }
50999 /* This function indicates if an operand of an instruction is an
51000 immediate. */
51002 static bool
51004 {
51013 }
51015 /* Return single or double path for instructions. */
51017 static enum insn_path
51019 {
51029 }
51031 /* Return insn dispatch group. */
51033 static enum dispatch_group
51035 {
51053 }
51055 /* Count number of GROUP restricted instructions in a dispatch
51056 window WINDOW_LIST. */
51058 static int
51060 {
51071 {
51090 }
51103 }
51105 /* This function returns true if insn satisfies dispatch rules on the
51106 last window scheduled. */
51108 static bool
51110 {
51118 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
51119 instructions should be given the lowest priority in the
51120 scheduling process in Haifa scheduler to make sure they will be
51121 scheduled in the same dispatch window as the reference to them. */
51125 /* Check nonrestricted. */
51129 /* Get last dispatch window. */
51134 {
51139 /* Window 1 is full. Go for next window. */
51141 }
51148 /* See if it fits in the first window. */
51150 {
51151 /* The first widow should have only single and double path
51152 uops. */
51158 }
51160 }
51162 /* Add an instruction INSN with NUM_UOPS micro-operations to the
51163 dispatch window WINDOW_LIST. */
51165 static void
51167 {
51185 /* Initialize window with new instruction. */
51206 {
51209 }
51210 }
51212 /* Adds a scheduled instruction, INSN, to the current dispatch window.
51213 If the total bytes of instructions or the number of instructions in
51214 the window exceed allowable, it allocates a new window. */
51216 static void
51218 {
51241 /* Get the last dispatch window. */
51249 else
51252 /* If current window is full, get a new window.
51253 Window number zero is full, if MAX_INSN uops are scheduled in it.
51254 Window number one is full, if window zero's bytes plus window
51255 one's bytes is 32, or if the bytes of the new instruction added
51256 to the total makes it greater than 48, or it has already MAX_INSN
51257 instructions in it. */
51266 {
51269 }
51272 {
51276 {
51279 }
51280 }
51282 {
51287 {
51290 }
51293 }
51294 else
51298 {
51299 /* End of basic block is reached do end-basic-block process. */
51302 }
51303 }
51305 /* Print the dispatch window, WINDOW_NUM, to FILE. */
51307 DEBUG_FUNCTION static void
51309 {
51315 else
51329 {
51332 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
51338 }
51339 }
51341 /* Print to stdout a dispatch window. */
51343 DEBUG_FUNCTION void
51345 {
51347 }
51349 /* Print INSN dispatch information to FILE. */
51351 DEBUG_FUNCTION static void
51353 {
51376 }
51378 /* Print to STDERR the status of the ready list with respect to
51379 dispatch windows. */
51381 DEBUG_FUNCTION void
51383 {
51391 }
51393 /* This routine is the driver of the dispatch scheduler. */
51395 static void
51397 {
51402 }
51404 /* Return TRUE if Dispatch Scheduling is supported. */
51406 static bool
51408 {
51412 {
51428 }
51431 }
51433 /* Implementation of reassociation_width target hook used by
51434 reassoc phase to identify parallelism level in reassociated
51435 tree. Statements tree_code is passed in OPC. Arguments type
51436 is passed in MODE.
51438 Currently parallel reassociation is enabled for Atom
51439 processors only and we set reassociation width to be 2
51440 because Atom may issue up to 2 instructions per cycle.
51442 Return value should be fixed if parallel reassociation is
51443 enabled for other processors. */
51445 static int
51447 {
51448 /* Vector part. */
51450 {
51453 else
51455 }
51457 /* Scalar part. */
51462 else
51464 }
51466 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51467 place emms and femms instructions. */
51469 static machine_mode
51471 {
51476 {
51495 else
51507 /* FALLTHRU */
51511 }
51512 }
51514 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51515 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51516 256bit and 128bit vectors. */
51518 static unsigned int
51520 {
51523 }
51525 \f
51527 /* Return class of registers which could be used for pseudo of MODE
51528 and of class RCLASS for spilling instead of memory. Return NO_REGS
51529 if it is not possible or non-profitable. */
51530 static reg_class_t
51532 {
51538 }
51540 /* Implement targetm.vectorize.init_cost. */
51544 {
51548 }
51550 /* Implement targetm.vectorize.add_stmt_cost. */
51552 static unsigned
51556 {
51563 /* Statements in an inner loop relative to the loop being
51564 vectorized are weighted more heavily. The value here is
51565 arbitrary and could potentially be improved with analysis. */
51571 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51572 for Silvermont as it has out of order integer pipeline and can execute
51573 2 scalar instruction per tick, but has in order SIMD pipeline. */
51576 {
51580 }
51585 }
51587 /* Implement targetm.vectorize.finish_cost. */
51589 static void
51592 {
51597 }
51599 /* Implement targetm.vectorize.destroy_cost_data. */
51601 static void
51603 {
51605 }
51607 /* Validate target specific memory model bits in VAL. */
51609 static unsigned HOST_WIDE_INT
51611 {
51618 {
51622 }
51625 {
51629 }
51631 {
51635 }
51637 }
51639 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51640 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51641 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51642 or number of vecsize_mangle variants that should be emitted. */
51644 static int
51648 {
51655 {
51659 }
51664 {
51671 /* case SCmode: */
51672 /* case DCmode: */
51678 }
51680 tree t;
51684 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51686 {
51693 /* case SCmode: */
51694 /* case DCmode: */
51700 }
51703 {
51704 /* Parse here processor clause. If not present, default to 'b'. */
51706 }
51708 {
51709 /* If the function isn't exported, we can pick up just one ISA
51710 for the clones. */
51715 else
51718 }
51719 else
51720 {
51723 }
51725 {
51738 }
51740 {
51743 else
51748 }
51750 }
51752 /* Add target attribute to SIMD clone NODE if needed. */
51754 static void
51756 {
51760 {
51775 }
51785 }
51787 /* If SIMD clone NODE can't be used in a vectorized loop
51788 in current function, return -1, otherwise return a badness of using it
51789 (0 if it is most desirable from vecsize_mangle point of view, 1
51790 slightly less desirable, etc.). */
51792 static int
51794 {
51796 {
51814 }
51815 }
51817 /* This function adjusts the unroll factor based on
51818 the hardware capabilities. For ex, bdver3 has
51819 a loop buffer which makes unrolling of smaller
51820 loops less important. This function decides the
51821 unroll factor using number of memory references
51822 (value 32 is used) as a heuristic. */
51824 static unsigned
51826 {
51835 /* Count the number of memory references within the loop body.
51836 This value determines the unrolling factor for bdver3 and bdver4
51837 architectures. */
51846 {
51851 else
51853 }
51860 }
51863 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51865 static bool
51867 {
51868 /* For x87 floating point with standard excess precision handling,
51869 there is no adddf3 pattern (since x87 floating point only has
51870 XFmode operations) so the default hook implementation gets this
51871 wrong. */
51873 }
51875 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51877 static void
51879 {
51884 {
51899 hold_fnclex);
51912 }
51914 {
51923 mxcsr_orig_var,
51933 ldmxcsr_hold_call);
51936 else
51941 ldmxcsr_clear_call);
51942 else
51946 stxmcsr_update_call);
51948 {
51954 exceptions_assign);
51955 }
51956 else
51961 ldmxcsr_update_call);
51962 }
51963 tree atomic_feraiseexcept
51968 atomic_feraiseexcept_call);
51969 }
51971 /* Return mode to be used for bounds or VOIDmode
51972 if bounds are not supported. */
51974 static enum machine_mode
51976 {
51977 /* Do not support pointer checker if MPX
51978 is not enabled. */
51980 {
51985 }
51988 }
51990 /* Return constant used to statically initialize constant bounds.
51992 This function is used to create special bound values. For now
51993 only INIT bounds and NONE bounds are expected. More special
51994 values may be added later. */
51996 static tree
51998 {
52004 /* This function is supposed to be used to create INIT and
52005 NONE bounds only. */
52010 }
52012 /* Generate a list of statements STMTS to initialize pointer bounds
52013 variable VAR with bounds LB and UB. Return the number of generated
52014 statements. */
52016 static int
52018 {
52036 }
52038 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
52039 /* For i386, common symbol is local only for non-PIE binaries. For
52040 x86-64, common symbol is local only for non-PIE binaries or linker
52041 supports copy reloc in PIE binaries. */
52043 static bool
52045 {
52047 (!flag_pic
52048 || (TARGET_64BIT
52050 }
52051 #endif
52053 /* If MEM is in the form of [base+offset], extract the two parts
52054 of address and set to BASE and OFFSET, otherwise return false. */
52056 static bool
52058 {
52059 rtx addr;
52069 {
52073 }
52079 {
52083 }
52086 }
52088 /* Given OPERANDS of consecutive load/store, check if we can merge
52089 them into move multiple. LOAD is true if they are load instructions.
52090 MODE is the mode of memory operands. */
52092 bool
52095 {
52100 {
52105 }
52106 else
52107 {
52112 }
52119 /* Check if the addresses are in the form of [base+offset]. */
52125 /* Check if the bases are the same. */
52132 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
52137 }
52139 /* Initialize the GCC target structure. */
52140 #undef TARGET_RETURN_IN_MEMORY
52141 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
52143 #undef TARGET_LEGITIMIZE_ADDRESS
52144 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
52146 #undef TARGET_ATTRIBUTE_TABLE
52147 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
52148 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
52149 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
52150 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52151 # undef TARGET_MERGE_DECL_ATTRIBUTES
52152 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
52153 #endif
52155 #undef TARGET_COMP_TYPE_ATTRIBUTES
52156 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
52158 #undef TARGET_INIT_BUILTINS
52159 #define TARGET_INIT_BUILTINS ix86_init_builtins
52160 #undef TARGET_BUILTIN_DECL
52161 #define TARGET_BUILTIN_DECL ix86_builtin_decl
52162 #undef TARGET_EXPAND_BUILTIN
52163 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
52165 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
52166 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
52167 ix86_builtin_vectorized_function
52169 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
52170 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
52172 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
52173 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
52175 #undef TARGET_VECTORIZE_BUILTIN_GATHER
52176 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
52178 #undef TARGET_BUILTIN_RECIPROCAL
52179 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
52181 #undef TARGET_ASM_FUNCTION_EPILOGUE
52182 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
52184 #undef TARGET_ENCODE_SECTION_INFO
52185 #ifndef SUBTARGET_ENCODE_SECTION_INFO
52186 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
52187 #else
52188 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
52189 #endif
52191 #undef TARGET_ASM_OPEN_PAREN
52193 #undef TARGET_ASM_CLOSE_PAREN
52196 #undef TARGET_ASM_BYTE_OP
52197 #define TARGET_ASM_BYTE_OP ASM_BYTE
52199 #undef TARGET_ASM_ALIGNED_HI_OP
52200 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
52201 #undef TARGET_ASM_ALIGNED_SI_OP
52202 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
52203 #ifdef ASM_QUAD
52204 #undef TARGET_ASM_ALIGNED_DI_OP
52205 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
52206 #endif
52208 #undef TARGET_PROFILE_BEFORE_PROLOGUE
52209 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
52211 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
52212 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
52214 #undef TARGET_ASM_UNALIGNED_HI_OP
52215 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
52216 #undef TARGET_ASM_UNALIGNED_SI_OP
52217 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
52218 #undef TARGET_ASM_UNALIGNED_DI_OP
52219 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
52221 #undef TARGET_PRINT_OPERAND
52222 #define TARGET_PRINT_OPERAND ix86_print_operand
52223 #undef TARGET_PRINT_OPERAND_ADDRESS
52224 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
52225 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
52226 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
52227 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
52228 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
52230 #undef TARGET_SCHED_INIT_GLOBAL
52231 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
52232 #undef TARGET_SCHED_ADJUST_COST
52233 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
52234 #undef TARGET_SCHED_ISSUE_RATE
52235 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
52236 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
52237 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
52238 ia32_multipass_dfa_lookahead
52239 #undef TARGET_SCHED_MACRO_FUSION_P
52240 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
52241 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
52242 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
52244 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
52245 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
52247 #undef TARGET_MEMMODEL_CHECK
52248 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
52250 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
52251 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
52253 #ifdef HAVE_AS_TLS
52254 #undef TARGET_HAVE_TLS
52255 #define TARGET_HAVE_TLS true
52256 #endif
52257 #undef TARGET_CANNOT_FORCE_CONST_MEM
52258 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
52259 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
52260 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
52262 #undef TARGET_DELEGITIMIZE_ADDRESS
52263 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
52265 #undef TARGET_MS_BITFIELD_LAYOUT_P
52266 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
52268 #if TARGET_MACHO
52269 #undef TARGET_BINDS_LOCAL_P
52270 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
52271 #else
52272 #undef TARGET_BINDS_LOCAL_P
52273 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
52274 #endif
52275 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52276 #undef TARGET_BINDS_LOCAL_P
52277 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
52278 #endif
52280 #undef TARGET_ASM_OUTPUT_MI_THUNK
52281 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
52282 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
52283 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
52285 #undef TARGET_ASM_FILE_START
52286 #define TARGET_ASM_FILE_START x86_file_start
52288 #undef TARGET_OPTION_OVERRIDE
52289 #define TARGET_OPTION_OVERRIDE ix86_option_override
52291 #undef TARGET_REGISTER_MOVE_COST
52292 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
52293 #undef TARGET_MEMORY_MOVE_COST
52294 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
52295 #undef TARGET_RTX_COSTS
52296 #define TARGET_RTX_COSTS ix86_rtx_costs
52297 #undef TARGET_ADDRESS_COST
52298 #define TARGET_ADDRESS_COST ix86_address_cost
52300 #undef TARGET_FIXED_CONDITION_CODE_REGS
52301 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
52302 #undef TARGET_CC_MODES_COMPATIBLE
52303 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
52305 #undef TARGET_MACHINE_DEPENDENT_REORG
52306 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
52308 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
52309 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
52311 #undef TARGET_BUILD_BUILTIN_VA_LIST
52312 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
52314 #undef TARGET_FOLD_BUILTIN
52315 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
52317 #undef TARGET_COMPARE_VERSION_PRIORITY
52318 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
52320 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
52321 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
52322 ix86_generate_version_dispatcher_body
52324 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
52325 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
52326 ix86_get_function_versions_dispatcher
52328 #undef TARGET_ENUM_VA_LIST_P
52329 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
52331 #undef TARGET_FN_ABI_VA_LIST
52332 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
52334 #undef TARGET_CANONICAL_VA_LIST_TYPE
52335 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
52337 #undef TARGET_EXPAND_BUILTIN_VA_START
52338 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
52340 #undef TARGET_MD_ASM_ADJUST
52341 #define TARGET_MD_ASM_ADJUST ix86_md_asm_adjust
52343 #undef TARGET_PROMOTE_PROTOTYPES
52344 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
52345 #undef TARGET_SETUP_INCOMING_VARARGS
52346 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
52347 #undef TARGET_MUST_PASS_IN_STACK
52348 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
52349 #undef TARGET_FUNCTION_ARG_ADVANCE
52350 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
52351 #undef TARGET_FUNCTION_ARG
52352 #define TARGET_FUNCTION_ARG ix86_function_arg
52353 #undef TARGET_INIT_PIC_REG
52354 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52355 #undef TARGET_USE_PSEUDO_PIC_REG
52356 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52357 #undef TARGET_FUNCTION_ARG_BOUNDARY
52358 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52359 #undef TARGET_PASS_BY_REFERENCE
52360 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52361 #undef TARGET_INTERNAL_ARG_POINTER
52362 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52363 #undef TARGET_UPDATE_STACK_BOUNDARY
52364 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52365 #undef TARGET_GET_DRAP_RTX
52366 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52367 #undef TARGET_STRICT_ARGUMENT_NAMING
52368 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52369 #undef TARGET_STATIC_CHAIN
52370 #define TARGET_STATIC_CHAIN ix86_static_chain
52371 #undef TARGET_TRAMPOLINE_INIT
52372 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52373 #undef TARGET_RETURN_POPS_ARGS
52374 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52376 #undef TARGET_LEGITIMATE_COMBINED_INSN
52377 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52379 #undef TARGET_ASAN_SHADOW_OFFSET
52380 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52382 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52383 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52385 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52386 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52388 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52389 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52391 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52392 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52393 ix86_libgcc_floating_mode_supported_p
52395 #undef TARGET_C_MODE_FOR_SUFFIX
52396 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52398 #ifdef HAVE_AS_TLS
52399 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52400 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52401 #endif
52403 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52404 #undef TARGET_INSERT_ATTRIBUTES
52405 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52406 #endif
52408 #undef TARGET_MANGLE_TYPE
52409 #define TARGET_MANGLE_TYPE ix86_mangle_type
52411 #if !TARGET_MACHO
52412 #undef TARGET_STACK_PROTECT_FAIL
52413 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52414 #endif
52416 #undef TARGET_FUNCTION_VALUE
52417 #define TARGET_FUNCTION_VALUE ix86_function_value
52419 #undef TARGET_FUNCTION_VALUE_REGNO_P
52420 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52422 #undef TARGET_PROMOTE_FUNCTION_MODE
52423 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52425 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52426 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52428 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52429 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52431 #undef TARGET_INSTANTIATE_DECLS
52432 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52434 #undef TARGET_SECONDARY_RELOAD
52435 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52437 #undef TARGET_CLASS_MAX_NREGS
52438 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52440 #undef TARGET_PREFERRED_RELOAD_CLASS
52441 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52442 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52443 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52444 #undef TARGET_CLASS_LIKELY_SPILLED_P
52445 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52447 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52448 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52449 ix86_builtin_vectorization_cost
52450 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52451 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52452 ix86_vectorize_vec_perm_const_ok
52453 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52454 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52455 ix86_preferred_simd_mode
52456 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52457 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52458 ix86_autovectorize_vector_sizes
52459 #undef TARGET_VECTORIZE_INIT_COST
52460 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52461 #undef TARGET_VECTORIZE_ADD_STMT_COST
52462 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52463 #undef TARGET_VECTORIZE_FINISH_COST
52464 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52465 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52466 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52468 #undef TARGET_SET_CURRENT_FUNCTION
52469 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52471 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52472 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52474 #undef TARGET_OPTION_SAVE
52475 #define TARGET_OPTION_SAVE ix86_function_specific_save
52477 #undef TARGET_OPTION_RESTORE
52478 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52480 #undef TARGET_OPTION_POST_STREAM_IN
52481 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52483 #undef TARGET_OPTION_PRINT
52484 #define TARGET_OPTION_PRINT ix86_function_specific_print
52486 #undef TARGET_OPTION_FUNCTION_VERSIONS
52487 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52489 #undef TARGET_CAN_INLINE_P
52490 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52492 #undef TARGET_EXPAND_TO_RTL_HOOK
52493 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52495 #undef TARGET_LEGITIMATE_ADDRESS_P
52496 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52498 #undef TARGET_LRA_P
52499 #define TARGET_LRA_P hook_bool_void_true
52501 #undef TARGET_REGISTER_PRIORITY
52502 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52504 #undef TARGET_REGISTER_USAGE_LEVELING_P
52505 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52507 #undef TARGET_LEGITIMATE_CONSTANT_P
52508 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52510 #undef TARGET_FRAME_POINTER_REQUIRED
52511 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52513 #undef TARGET_CAN_ELIMINATE
52514 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52516 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52517 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52519 #undef TARGET_ASM_CODE_END
52520 #define TARGET_ASM_CODE_END ix86_code_end
52522 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52523 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52525 #if TARGET_MACHO
52526 #undef TARGET_INIT_LIBFUNCS
52527 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52528 #endif
52530 #undef TARGET_LOOP_UNROLL_ADJUST
52531 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52533 #undef TARGET_SPILL_CLASS
52534 #define TARGET_SPILL_CLASS ix86_spill_class
52536 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52537 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52538 ix86_simd_clone_compute_vecsize_and_simdlen
52540 #undef TARGET_SIMD_CLONE_ADJUST
52541 #define TARGET_SIMD_CLONE_ADJUST \
52542 ix86_simd_clone_adjust
52544 #undef TARGET_SIMD_CLONE_USABLE
52545 #define TARGET_SIMD_CLONE_USABLE \
52546 ix86_simd_clone_usable
52548 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52549 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52550 ix86_float_exceptions_rounding_supported_p
52552 #undef TARGET_MODE_EMIT
52553 #define TARGET_MODE_EMIT ix86_emit_mode_set
52555 #undef TARGET_MODE_NEEDED
52556 #define TARGET_MODE_NEEDED ix86_mode_needed
52558 #undef TARGET_MODE_AFTER
52559 #define TARGET_MODE_AFTER ix86_mode_after
52561 #undef TARGET_MODE_ENTRY
52562 #define TARGET_MODE_ENTRY ix86_mode_entry
52564 #undef TARGET_MODE_EXIT
52565 #define TARGET_MODE_EXIT ix86_mode_exit
52567 #undef TARGET_MODE_PRIORITY
52568 #define TARGET_MODE_PRIORITY ix86_mode_priority
52570 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52571 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52573 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52574 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52576 #undef TARGET_STORE_BOUNDS_FOR_ARG
52577 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52579 #undef TARGET_LOAD_RETURNED_BOUNDS
52580 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52582 #undef TARGET_STORE_RETURNED_BOUNDS
52583 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52585 #undef TARGET_CHKP_BOUND_MODE
52586 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52588 #undef TARGET_BUILTIN_CHKP_FUNCTION
52589 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52591 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52592 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52594 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52595 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52597 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52598 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52600 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52601 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52603 #undef TARGET_OFFLOAD_OPTIONS
52604 #define TARGET_OFFLOAD_OPTIONS \
52605 ix86_offload_options
52607 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52608 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52611 \f