1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 /* This file contains two passes of the compiler: reg_scan and reg_class.
25 It also defines some tables of information about the hardware registers
26 and a function init_reg_sets to initialize the tables. */
30 #include "coretypes.h"
32 #include "hard-reg-set.h"
37 #include "basic-block.h"
40 #include "insn-config.h"
49 static void init_reg_sets_1 (void);
50 static void init_reg_autoinc (void);
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set
;
75 /* Data for initializing the above. */
77 static const char initial_fixed_regs
[] = FIXED_REGISTERS
;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set
;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set
;
94 /* Data for initializing the above. */
96 static const char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
98 /* This is much like call_used_regs, except it doesn't have to
99 be a superset of FIXED_REGISTERS. This vector indicates
100 what is really call clobbered, and is used when defining
101 regs_invalidated_by_call. */
103 #ifdef CALL_REALLY_USED_REGISTERS
104 char call_really_used_regs
[] = CALL_REALLY_USED_REGISTERS
;
107 /* Indexed by hard register number, contains 1 for registers that are
108 fixed use or call used registers that cannot hold quantities across
109 calls even if we are willing to save and restore them. call fixed
110 registers are a subset of call used registers. */
112 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
114 /* The same info as a HARD_REG_SET. */
116 HARD_REG_SET call_fixed_reg_set
;
118 /* Number of non-fixed registers. */
120 int n_non_fixed_regs
;
122 /* Indexed by hard register number, contains 1 for registers
123 that are being used for global register decls.
124 These must be exempt from ordinary flow analysis
125 and are also considered fixed. */
127 char global_regs
[FIRST_PSEUDO_REGISTER
];
129 /* Contains 1 for registers that are set or clobbered by calls. */
130 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
131 for someone's bright idea to have call_used_regs strictly include
132 fixed_regs. Which leaves us guessing as to the set of fixed_regs
133 that are actually preserved. We know for sure that those associated
134 with the local stack frame are safe, but scant others. */
136 HARD_REG_SET regs_invalidated_by_call
;
138 /* Table of register numbers in the order in which to try to use them. */
139 #ifdef REG_ALLOC_ORDER
140 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
142 /* The inverse of reg_alloc_order. */
143 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
146 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
148 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
150 /* The same information, but as an array of unsigned ints. We copy from
151 these unsigned ints to the table above. We do this so the tm.h files
152 do not have to be aware of the wordsize for machines with <= 64 regs.
153 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
156 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
158 static const unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
159 = REG_CLASS_CONTENTS
;
161 /* For each reg class, number of regs it contains. */
163 unsigned int reg_class_size
[N_REG_CLASSES
];
165 /* For each reg class, table listing all the containing classes. */
167 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
169 /* For each reg class, table listing all the classes contained in it. */
171 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
173 /* For each pair of reg classes,
174 a largest reg class contained in their union. */
176 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
178 /* For each pair of reg classes,
179 the smallest reg class containing their union. */
181 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
183 /* Array containing all of the register names. */
185 const char * reg_names
[] = REGISTER_NAMES
;
187 /* For each hard register, the widest mode object that it can contain.
188 This will be a MODE_INT mode if the register can hold integers. Otherwise
189 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
192 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
194 /* 1 if class does contain register of given mode. */
196 static char contains_reg_of_mode
[N_REG_CLASSES
] [MAX_MACHINE_MODE
];
198 /* Maximum cost of moving from a register in one class to a register in
199 another class. Based on REGISTER_MOVE_COST. */
201 static int move_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
203 /* Similar, but here we don't have to move if the first index is a subset
204 of the second so in that case the cost is zero. */
206 static int may_move_in_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
208 /* Similar, but here we don't have to move if the first index is a superset
209 of the second so in that case the cost is zero. */
211 static int may_move_out_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
213 #ifdef FORBIDDEN_INC_DEC_CLASSES
215 /* These are the classes that regs which are auto-incremented or decremented
218 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
220 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
223 static char *in_inc_dec
;
225 #endif /* FORBIDDEN_INC_DEC_CLASSES */
227 #ifdef CANNOT_CHANGE_MODE_CLASS
228 /* All registers that have been subreged. Indexed by regno * MAX_MACHINE_MODE
230 bitmap_head subregs_of_mode
;
233 /* Sample MEM values for use by memory_move_secondary_cost. */
235 static GTY(()) rtx top_of_stack
[MAX_MACHINE_MODE
];
237 /* Linked list of reg_info structures allocated for reg_n_info array.
238 Grouping all of the allocated structures together in one lump
239 means only one call to bzero to clear them, rather than n smaller
241 struct reg_info_data
{
242 struct reg_info_data
*next
; /* next set of reg_info structures */
243 size_t min_index
; /* minimum index # */
244 size_t max_index
; /* maximum index # */
245 char used_p
; /* nonzero if this has been used previously */
246 reg_info data
[1]; /* beginning of the reg_info data */
249 static struct reg_info_data
*reg_info_head
;
251 /* No more global register variables may be declared; true once
252 regclass has been initialized. */
254 static int no_global_reg_vars
= 0;
256 /* Specify number of hard registers given machine mode occupy. */
257 unsigned char hard_regno_nregs
[FIRST_PSEUDO_REGISTER
][MAX_MACHINE_MODE
];
259 /* Function called only once to initialize the above data on reg usage.
260 Once this is done, various switches may override. */
267 /* First copy the register information from the initial int form into
270 for (i
= 0; i
< N_REG_CLASSES
; i
++)
272 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
274 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
275 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
276 if (int_reg_class_contents
[i
][j
/ 32]
277 & ((unsigned) 1 << (j
% 32)))
278 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
281 memcpy (fixed_regs
, initial_fixed_regs
, sizeof fixed_regs
);
282 memcpy (call_used_regs
, initial_call_used_regs
, sizeof call_used_regs
);
283 memset (global_regs
, 0, sizeof global_regs
);
285 /* Do any additional initialization regsets may need. */
286 INIT_ONCE_REG_SET ();
288 #ifdef REG_ALLOC_ORDER
289 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
290 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
294 /* After switches have been processed, which perhaps alter
295 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
298 init_reg_sets_1 (void)
301 unsigned int /* enum machine_mode */ m
;
302 char allocatable_regs_of_mode
[MAX_MACHINE_MODE
];
304 /* This macro allows the fixed or call-used registers
305 and the register classes to depend on target flags. */
307 #ifdef CONDITIONAL_REGISTER_USAGE
308 CONDITIONAL_REGISTER_USAGE
;
311 /* Compute number of hard regs in each class. */
313 memset (reg_class_size
, 0, sizeof reg_class_size
);
314 for (i
= 0; i
< N_REG_CLASSES
; i
++)
315 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
316 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
319 /* Initialize the table of subunions.
320 reg_class_subunion[I][J] gets the largest-numbered reg-class
321 that is contained in the union of classes I and J. */
323 for (i
= 0; i
< N_REG_CLASSES
; i
++)
325 for (j
= 0; j
< N_REG_CLASSES
; j
++)
330 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
331 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
332 for (k
= 0; k
< N_REG_CLASSES
; k
++)
334 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
339 /* Keep the largest subclass. */ /* SPEE 900308 */
340 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
341 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
343 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
350 /* Initialize the table of superunions.
351 reg_class_superunion[I][J] gets the smallest-numbered reg-class
352 containing the union of classes I and J. */
354 for (i
= 0; i
< N_REG_CLASSES
; i
++)
356 for (j
= 0; j
< N_REG_CLASSES
; j
++)
361 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
362 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
363 for (k
= 0; k
< N_REG_CLASSES
; k
++)
364 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
367 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
371 /* Initialize the tables of subclasses and superclasses of each reg class.
372 First clear the whole table, then add the elements as they are found. */
374 for (i
= 0; i
< N_REG_CLASSES
; i
++)
376 for (j
= 0; j
< N_REG_CLASSES
; j
++)
378 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
379 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
383 for (i
= 0; i
< N_REG_CLASSES
; i
++)
385 if (i
== (int) NO_REGS
)
388 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
392 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
396 /* Reg class I is a subclass of J.
397 Add J to the table of superclasses of I. */
398 p
= ®_class_superclasses
[i
][0];
399 while (*p
!= LIM_REG_CLASSES
) p
++;
400 *p
= (enum reg_class
) j
;
401 /* Add I to the table of superclasses of J. */
402 p
= ®_class_subclasses
[j
][0];
403 while (*p
!= LIM_REG_CLASSES
) p
++;
404 *p
= (enum reg_class
) i
;
408 /* Initialize "constant" tables. */
410 CLEAR_HARD_REG_SET (fixed_reg_set
);
411 CLEAR_HARD_REG_SET (call_used_reg_set
);
412 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
413 CLEAR_HARD_REG_SET (regs_invalidated_by_call
);
415 memcpy (call_fixed_regs
, fixed_regs
, sizeof call_fixed_regs
);
417 n_non_fixed_regs
= 0;
419 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
422 SET_HARD_REG_BIT (fixed_reg_set
, i
);
426 if (call_used_regs
[i
])
427 SET_HARD_REG_BIT (call_used_reg_set
, i
);
428 if (call_fixed_regs
[i
])
429 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
430 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
431 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
433 /* There are a couple of fixed registers that we know are safe to
434 exclude from being clobbered by calls:
436 The frame pointer is always preserved across calls. The arg pointer
437 is if it is fixed. The stack pointer usually is, unless
438 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
439 If we are generating PIC code, the PIC offset table register is
440 preserved across calls, though the target can override that. */
442 if (i
== STACK_POINTER_REGNUM
|| i
== FRAME_POINTER_REGNUM
)
444 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
445 else if (i
== HARD_FRAME_POINTER_REGNUM
)
448 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
449 else if (i
== ARG_POINTER_REGNUM
&& fixed_regs
[i
])
452 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
453 else if (i
== (unsigned) PIC_OFFSET_TABLE_REGNUM
&& fixed_regs
[i
])
457 #ifdef CALL_REALLY_USED_REGISTERS
458 || call_really_used_regs
[i
]
463 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
466 memset (contains_reg_of_mode
, 0, sizeof (contains_reg_of_mode
));
467 memset (allocatable_regs_of_mode
, 0, sizeof (allocatable_regs_of_mode
));
468 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
469 for (i
= 0; i
< N_REG_CLASSES
; i
++)
470 if ((unsigned) CLASS_MAX_NREGS (i
, m
) <= reg_class_size
[i
])
471 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
472 if (!fixed_regs
[j
] && TEST_HARD_REG_BIT (reg_class_contents
[i
], j
)
473 && HARD_REGNO_MODE_OK (j
, m
))
475 contains_reg_of_mode
[i
][m
] = 1;
476 allocatable_regs_of_mode
[m
] = 1;
480 /* Initialize the move cost table. Find every subset of each class
481 and take the maximum cost of moving any subset to any other. */
483 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
484 if (allocatable_regs_of_mode
[m
])
486 for (i
= 0; i
< N_REG_CLASSES
; i
++)
487 if (contains_reg_of_mode
[i
][m
])
488 for (j
= 0; j
< N_REG_CLASSES
; j
++)
491 enum reg_class
*p1
, *p2
;
493 if (!contains_reg_of_mode
[j
][m
])
495 move_cost
[m
][i
][j
] = 65536;
496 may_move_in_cost
[m
][i
][j
] = 65536;
497 may_move_out_cost
[m
][i
][j
] = 65536;
501 cost
= REGISTER_MOVE_COST (m
, i
, j
);
503 for (p2
= ®_class_subclasses
[j
][0];
504 *p2
!= LIM_REG_CLASSES
;
506 if (*p2
!= i
&& contains_reg_of_mode
[*p2
][m
])
507 cost
= MAX (cost
, move_cost
[m
][i
][*p2
]);
509 for (p1
= ®_class_subclasses
[i
][0];
510 *p1
!= LIM_REG_CLASSES
;
512 if (*p1
!= j
&& contains_reg_of_mode
[*p1
][m
])
513 cost
= MAX (cost
, move_cost
[m
][*p1
][j
]);
515 move_cost
[m
][i
][j
] = cost
;
517 if (reg_class_subset_p (i
, j
))
518 may_move_in_cost
[m
][i
][j
] = 0;
520 may_move_in_cost
[m
][i
][j
] = cost
;
522 if (reg_class_subset_p (j
, i
))
523 may_move_out_cost
[m
][i
][j
] = 0;
525 may_move_out_cost
[m
][i
][j
] = cost
;
529 for (j
= 0; j
< N_REG_CLASSES
; j
++)
531 move_cost
[m
][i
][j
] = 65536;
532 may_move_in_cost
[m
][i
][j
] = 65536;
533 may_move_out_cost
[m
][i
][j
] = 65536;
538 /* Compute the table of register modes.
539 These values are used to record death information for individual registers
540 (as opposed to a multi-register mode). */
543 init_reg_modes_once (void)
547 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
548 for (j
= 0; j
< MAX_MACHINE_MODE
; j
++)
549 hard_regno_nregs
[i
][j
] = HARD_REGNO_NREGS(i
, (enum machine_mode
)j
);
551 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
553 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1, false);
555 /* If we couldn't find a valid mode, just use the previous mode.
556 ??? One situation in which we need to do this is on the mips where
557 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
558 to use DF mode for the even registers and VOIDmode for the odd
559 (for the cpu models where the odd ones are inaccessible). */
560 if (reg_raw_mode
[i
] == VOIDmode
)
561 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
565 /* Finish initializing the register sets and
566 initialize the register modes. */
571 /* This finishes what was started by init_reg_sets, but couldn't be done
572 until after register usage was specified. */
578 /* Initialize some fake stack-frame MEM references for use in
579 memory_move_secondary_cost. */
582 init_fake_stack_mems (void)
584 #ifdef HAVE_SECONDARY_RELOADS
588 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
589 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
594 #ifdef HAVE_SECONDARY_RELOADS
596 /* Compute extra cost of moving registers to/from memory due to reloads.
597 Only needed if secondary reloads are required for memory moves. */
600 memory_move_secondary_cost (enum machine_mode mode
, enum reg_class
class, int in
)
602 enum reg_class altclass
;
603 int partial_cost
= 0;
604 /* We need a memory reference to feed to SECONDARY... macros. */
605 /* mem may be unused even if the SECONDARY_ macros are defined. */
606 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
611 #ifdef SECONDARY_INPUT_RELOAD_CLASS
612 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
619 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
620 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
626 if (altclass
== NO_REGS
)
630 partial_cost
= REGISTER_MOVE_COST (mode
, altclass
, class);
632 partial_cost
= REGISTER_MOVE_COST (mode
, class, altclass
);
634 if (class == altclass
)
635 /* This isn't simply a copy-to-temporary situation. Can't guess
636 what it is, so MEMORY_MOVE_COST really ought not to be calling
639 I'm tempted to put in an abort here, but returning this will
640 probably only give poor estimates, which is what we would've
641 had before this code anyways. */
644 /* Check if the secondary reload register will also need a
646 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
650 /* Return a machine mode that is legitimate for hard reg REGNO and large
651 enough to save nregs. If we can't find one, return VOIDmode.
652 If CALL_SAVED is true, only consider modes that are call saved. */
655 choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED
,
656 unsigned int nregs
, bool call_saved
)
658 unsigned int /* enum machine_mode */ m
;
659 enum machine_mode found_mode
= VOIDmode
, mode
;
661 /* We first look for the largest integer mode that can be validly
662 held in REGNO. If none, we look for the largest floating-point mode.
663 If we still didn't find a valid mode, try CCmode. */
665 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
667 mode
= GET_MODE_WIDER_MODE (mode
))
668 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
669 && HARD_REGNO_MODE_OK (regno
, mode
)
670 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
673 if (found_mode
!= VOIDmode
)
676 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
678 mode
= GET_MODE_WIDER_MODE (mode
))
679 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
680 && HARD_REGNO_MODE_OK (regno
, mode
)
681 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
684 if (found_mode
!= VOIDmode
)
687 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT
);
689 mode
= GET_MODE_WIDER_MODE (mode
))
690 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
691 && HARD_REGNO_MODE_OK (regno
, mode
)
692 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
695 if (found_mode
!= VOIDmode
)
698 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT
);
700 mode
= GET_MODE_WIDER_MODE (mode
))
701 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
702 && HARD_REGNO_MODE_OK (regno
, mode
)
703 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
706 if (found_mode
!= VOIDmode
)
709 /* Iterate over all of the CCmodes. */
710 for (m
= (unsigned int) CCmode
; m
< (unsigned int) NUM_MACHINE_MODES
; ++m
)
712 mode
= (enum machine_mode
) m
;
713 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
714 && HARD_REGNO_MODE_OK (regno
, mode
)
715 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
719 /* We can't find a mode valid for this register. */
723 /* Specify the usage characteristics of the register named NAME.
724 It should be a fixed register if FIXED and a
725 call-used register if CALL_USED. */
728 fix_register (const char *name
, int fixed
, int call_used
)
732 /* Decode the name and update the primary form of
733 the register info. */
735 if ((i
= decode_reg_name (name
)) >= 0)
737 if ((i
== STACK_POINTER_REGNUM
738 #ifdef HARD_FRAME_POINTER_REGNUM
739 || i
== HARD_FRAME_POINTER_REGNUM
741 || i
== FRAME_POINTER_REGNUM
744 && (fixed
== 0 || call_used
== 0))
746 static const char * const what_option
[2][2] = {
747 { "call-saved", "call-used" },
748 { "no-such-option", "fixed" }};
750 error ("can't use '%s' as a %s register", name
,
751 what_option
[fixed
][call_used
]);
755 fixed_regs
[i
] = fixed
;
756 call_used_regs
[i
] = call_used
;
757 #ifdef CALL_REALLY_USED_REGISTERS
759 call_really_used_regs
[i
] = call_used
;
765 warning ("unknown register name: %s", name
);
769 /* Mark register number I as global. */
772 globalize_reg (int i
)
774 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
775 error ("global register variable follows a function definition");
779 warning ("register used for two global register variables");
783 if (call_used_regs
[i
] && ! fixed_regs
[i
])
784 warning ("call-clobbered register used for global register variable");
788 /* If already fixed, nothing else to do. */
792 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
795 SET_HARD_REG_BIT (fixed_reg_set
, i
);
796 SET_HARD_REG_BIT (call_used_reg_set
, i
);
797 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
798 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
801 /* Now the data and code for the `regclass' pass, which happens
802 just before local-alloc. */
804 /* The `costs' struct records the cost of using a hard register of each class
805 and of using memory for each pseudo. We use this data to set up
806 register class preferences. */
810 int cost
[N_REG_CLASSES
];
814 /* Structure used to record preferences of given pseudo. */
817 /* (enum reg_class) prefclass is the preferred class. */
820 /* altclass is a register class that we should use for allocating
821 pseudo if no register in the preferred class is available.
822 If no register in this class is available, memory is preferred.
824 It might appear to be more general to have a bitmask of classes here,
825 but since it is recommended that there be a class corresponding to the
826 union of most major pair of classes, that generality is not required. */
830 /* Record the cost of each class for each pseudo. */
832 static struct costs
*costs
;
834 /* Initialized once, and used to initialize cost values for each insn. */
836 static struct costs init_cost
;
838 /* Record preferences of each pseudo.
839 This is available after `regclass' is run. */
841 static struct reg_pref
*reg_pref
;
843 /* Allocated buffers for reg_pref. */
845 static struct reg_pref
*reg_pref_buffer
;
847 /* Frequency of executions of current insn. */
849 static int frequency
;
851 static rtx
scan_one_insn (rtx
, int);
852 static void record_operand_costs (rtx
, struct costs
*, struct reg_pref
*);
853 static void dump_regclass (FILE *);
854 static void record_reg_classes (int, int, rtx
*, enum machine_mode
*,
855 const char **, rtx
, struct costs
*,
857 static int copy_cost (rtx
, enum machine_mode
, enum reg_class
, int);
858 static void record_address_regs (rtx
, enum reg_class
, int);
859 #ifdef FORBIDDEN_INC_DEC_CLASSES
860 static int auto_inc_dec_reg_p (rtx
, enum machine_mode
);
862 static void reg_scan_mark_refs (rtx
, rtx
, int, unsigned int);
864 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
865 This function is sometimes called before the info has been computed.
866 When that happens, just return GENERAL_REGS, which is innocuous. */
869 reg_preferred_class (int regno
)
873 return (enum reg_class
) reg_pref
[regno
].prefclass
;
877 reg_alternate_class (int regno
)
882 return (enum reg_class
) reg_pref
[regno
].altclass
;
885 /* Initialize some global data for this pass. */
892 init_cost
.mem_cost
= 10000;
893 for (i
= 0; i
< N_REG_CLASSES
; i
++)
894 init_cost
.cost
[i
] = 10000;
896 /* This prevents dump_flow_info from losing if called
897 before regclass is run. */
900 /* No more global register variables may be declared. */
901 no_global_reg_vars
= 1;
904 /* Dump register costs. */
906 dump_regclass (FILE *dump
)
908 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
910 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
912 int /* enum reg_class */ class;
915 fprintf (dump
, " Register %i costs:", i
);
916 for (class = 0; class < (int) N_REG_CLASSES
; class++)
917 if (contains_reg_of_mode
[(enum reg_class
) class][PSEUDO_REGNO_MODE (i
)]
918 #ifdef FORBIDDEN_INC_DEC_CLASSES
920 || !forbidden_inc_dec_class
[(enum reg_class
) class])
922 #ifdef CANNOT_CHANGE_MODE_CLASS
923 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
924 PSEUDO_REGNO_MODE (i
))
927 fprintf (dump
, " %s:%i", reg_class_names
[class],
928 costs
[i
].cost
[(enum reg_class
) class]);
929 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
935 /* Calculate the costs of insn operands. */
938 record_operand_costs (rtx insn
, struct costs
*op_costs
,
939 struct reg_pref
*reg_pref
)
941 const char *constraints
[MAX_RECOG_OPERANDS
];
942 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
945 for (i
= 0; i
< recog_data
.n_operands
; i
++)
947 constraints
[i
] = recog_data
.constraints
[i
];
948 modes
[i
] = recog_data
.operand_mode
[i
];
951 /* If we get here, we are set up to record the costs of all the
952 operands for this insn. Start by initializing the costs.
953 Then handle any address registers. Finally record the desired
954 classes for any pseudos, doing it twice if some pair of
955 operands are commutative. */
957 for (i
= 0; i
< recog_data
.n_operands
; i
++)
959 op_costs
[i
] = init_cost
;
961 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
962 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
964 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
965 record_address_regs (XEXP (recog_data
.operand
[i
], 0),
966 MODE_BASE_REG_CLASS (modes
[i
]), frequency
* 2);
967 else if (constraints
[i
][0] == 'p'
968 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0], constraints
[i
]))
969 record_address_regs (recog_data
.operand
[i
],
970 MODE_BASE_REG_CLASS (modes
[i
]), frequency
* 2);
973 /* Check for commutative in a separate loop so everything will
974 have been initialized. We must do this even if one operand
975 is a constant--see addsi3 in m68k.md. */
977 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
978 if (constraints
[i
][0] == '%')
980 const char *xconstraints
[MAX_RECOG_OPERANDS
];
983 /* Handle commutative operands by swapping the constraints.
984 We assume the modes are the same. */
986 for (j
= 0; j
< recog_data
.n_operands
; j
++)
987 xconstraints
[j
] = constraints
[j
];
989 xconstraints
[i
] = constraints
[i
+1];
990 xconstraints
[i
+1] = constraints
[i
];
991 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
992 recog_data
.operand
, modes
,
993 xconstraints
, insn
, op_costs
, reg_pref
);
996 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
997 recog_data
.operand
, modes
,
998 constraints
, insn
, op_costs
, reg_pref
);
1001 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1002 time it would save code to put a certain register in a certain class.
1003 PASS, when nonzero, inhibits some optimizations which need only be done
1005 Return the last insn processed, so that the scan can be continued from
1009 scan_one_insn (rtx insn
, int pass
)
1011 enum rtx_code code
= GET_CODE (insn
);
1012 enum rtx_code pat_code
;
1015 struct costs op_costs
[MAX_RECOG_OPERANDS
];
1017 if (GET_RTX_CLASS (code
) != 'i')
1020 pat_code
= GET_CODE (PATTERN (insn
));
1022 || pat_code
== CLOBBER
1023 || pat_code
== ASM_INPUT
1024 || pat_code
== ADDR_VEC
1025 || pat_code
== ADDR_DIFF_VEC
)
1028 set
= single_set (insn
);
1029 extract_insn (insn
);
1031 /* If this insn loads a parameter from its stack slot, then
1032 it represents a savings, rather than a cost, if the
1033 parameter is stored in memory. Record this fact. */
1035 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
1036 && GET_CODE (SET_SRC (set
)) == MEM
1037 && (note
= find_reg_note (insn
, REG_EQUIV
,
1039 && GET_CODE (XEXP (note
, 0)) == MEM
)
1041 costs
[REGNO (SET_DEST (set
))].mem_cost
1042 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
1045 record_address_regs (XEXP (SET_SRC (set
), 0),
1046 MODE_BASE_REG_CLASS (VOIDmode
), frequency
* 2);
1050 /* Improve handling of two-address insns such as
1051 (set X (ashift CONST Y)) where CONST must be made to
1052 match X. Change it into two insns: (set X CONST)
1053 (set X (ashift X Y)). If we left this for reloading, it
1054 would probably get three insns because X and Y might go
1055 in the same place. This prevents X and Y from receiving
1058 We can only do this if the modes of operands 0 and 1
1059 (which might not be the same) are tieable and we only need
1060 do this during our first pass. */
1062 if (pass
== 0 && optimize
1063 && recog_data
.n_operands
>= 3
1064 && recog_data
.constraints
[1][0] == '0'
1065 && recog_data
.constraints
[1][1] == 0
1066 && CONSTANT_P (recog_data
.operand
[1])
1067 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[1])
1068 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[2])
1069 && GET_CODE (recog_data
.operand
[0]) == REG
1070 && MODES_TIEABLE_P (GET_MODE (recog_data
.operand
[0]),
1071 recog_data
.operand_mode
[1]))
1073 rtx previnsn
= prev_real_insn (insn
);
1075 = gen_lowpart (recog_data
.operand_mode
[1],
1076 recog_data
.operand
[0]);
1078 = emit_insn_before (gen_move_insn (dest
, recog_data
.operand
[1]), insn
);
1080 /* If this insn was the start of a basic block,
1081 include the new insn in that block.
1082 We need not check for code_label here;
1083 while a basic block can start with a code_label,
1084 INSN could not be at the beginning of that block. */
1085 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
1089 if (insn
== BB_HEAD (b
))
1090 BB_HEAD (b
) = newinsn
;
1093 /* This makes one more setting of new insns's dest. */
1094 REG_N_SETS (REGNO (recog_data
.operand
[0]))++;
1095 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1096 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1098 *recog_data
.operand_loc
[1] = recog_data
.operand
[0];
1099 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1100 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1101 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
1102 if (recog_data
.dup_num
[i
] == 1)
1104 *recog_data
.dup_loc
[i
] = recog_data
.operand
[0];
1105 REG_N_REFS (REGNO (recog_data
.operand
[0]))++;
1106 REG_FREQ (REGNO (recog_data
.operand
[0])) += frequency
;
1109 return PREV_INSN (newinsn
);
1112 record_operand_costs (insn
, op_costs
, reg_pref
);
1114 /* Now add the cost for each operand to the total costs for
1117 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1118 if (GET_CODE (recog_data
.operand
[i
]) == REG
1119 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1121 int regno
= REGNO (recog_data
.operand
[i
]);
1122 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
1124 p
->mem_cost
+= q
->mem_cost
* frequency
;
1125 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1126 p
->cost
[j
] += q
->cost
[j
] * frequency
;
1132 /* Initialize information about which register classes can be used for
1133 pseudos that are auto-incremented or auto-decremented. */
1136 init_reg_autoinc (void)
1138 #ifdef FORBIDDEN_INC_DEC_CLASSES
1141 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1143 rtx r
= gen_rtx_raw_REG (VOIDmode
, 0);
1144 enum machine_mode m
;
1147 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1148 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1152 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1153 m
= (enum machine_mode
) ((int) m
+ 1))
1154 if (HARD_REGNO_MODE_OK (j
, m
))
1158 /* If a register is not directly suitable for an
1159 auto-increment or decrement addressing mode and
1160 requires secondary reloads, disallow its class from
1161 being used in such addresses. */
1164 #ifdef SECONDARY_RELOAD_CLASS
1165 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode
), m
, r
)
1168 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1169 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode
), m
, r
)
1172 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1173 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode
), m
, r
)
1178 && ! auto_inc_dec_reg_p (r
, m
))
1179 forbidden_inc_dec_class
[i
] = 1;
1183 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1186 /* This is a pass of the compiler that scans all instructions
1187 and calculates the preferred class for each pseudo-register.
1188 This information can be accessed later by calling `reg_preferred_class'.
1189 This pass comes just before local register allocation. */
1192 regclass (rtx f
, int nregs
, FILE *dump
)
1200 costs
= xmalloc (nregs
* sizeof (struct costs
));
1202 #ifdef FORBIDDEN_INC_DEC_CLASSES
1204 in_inc_dec
= xmalloc (nregs
);
1206 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1208 /* Normally we scan the insns once and determine the best class to use for
1209 each register. However, if -fexpensive_optimizations are on, we do so
1210 twice, the second time using the tentative best classes to guide the
1213 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1218 fprintf (dump
, "\n\nPass %i\n\n",pass
);
1219 /* Zero out our accumulation of the cost of each class for each reg. */
1221 memset (costs
, 0, nregs
* sizeof (struct costs
));
1223 #ifdef FORBIDDEN_INC_DEC_CLASSES
1224 memset (in_inc_dec
, 0, nregs
);
1227 /* Scan the instructions and record each time it would
1228 save code to put a certain register in a certain class. */
1232 frequency
= REG_FREQ_MAX
;
1233 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1234 insn
= scan_one_insn (insn
, pass
);
1239 /* Show that an insn inside a loop is likely to be executed three
1240 times more than insns outside a loop. This is much more
1241 aggressive than the assumptions made elsewhere and is being
1242 tried as an experiment. */
1243 frequency
= REG_FREQ_FROM_BB (bb
);
1244 for (insn
= BB_HEAD (bb
); ; insn
= NEXT_INSN (insn
))
1246 insn
= scan_one_insn (insn
, pass
);
1247 if (insn
== BB_END (bb
))
1252 /* Now for each register look at how desirable each class is
1253 and find which class is preferred. Store that in
1254 `prefclass'. Record in `altclass' the largest register
1255 class any of whose registers is better than memory. */
1258 reg_pref
= reg_pref_buffer
;
1262 dump_regclass (dump
);
1263 fprintf (dump
,"\n");
1265 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1267 int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1268 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1269 /* This is an enum reg_class, but we call it an int
1270 to save lots of casts. */
1272 struct costs
*p
= &costs
[i
];
1274 /* In non-optimizing compilation REG_N_REFS is not initialized
1276 if (optimize
&& !REG_N_REFS (i
) && !REG_N_SETS (i
))
1279 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1281 /* Ignore classes that are too small for this operand or
1282 invalid for an operand that was auto-incremented. */
1283 if (!contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1284 #ifdef FORBIDDEN_INC_DEC_CLASSES
1285 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1287 #ifdef CANNOT_CHANGE_MODE_CLASS
1288 || invalid_mode_change_p (i
, (enum reg_class
) class,
1289 PSEUDO_REGNO_MODE (i
))
1293 else if (p
->cost
[class] < best_cost
)
1295 best_cost
= p
->cost
[class];
1296 best
= (enum reg_class
) class;
1298 else if (p
->cost
[class] == best_cost
)
1299 best
= reg_class_subunion
[(int) best
][class];
1302 /* Record the alternate register class; i.e., a class for which
1303 every register in it is better than using memory. If adding a
1304 class would make a smaller class (i.e., no union of just those
1305 classes exists), skip that class. The major unions of classes
1306 should be provided as a register class. Don't do this if we
1307 will be doing it again later. */
1309 if ((pass
== 1 || dump
) || ! flag_expensive_optimizations
)
1310 for (class = 0; class < N_REG_CLASSES
; class++)
1311 if (p
->cost
[class] < p
->mem_cost
1312 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1313 > reg_class_size
[(int) alt
])
1314 #ifdef FORBIDDEN_INC_DEC_CLASSES
1315 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1317 #ifdef CANNOT_CHANGE_MODE_CLASS
1318 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
1319 PSEUDO_REGNO_MODE (i
))
1322 alt
= reg_class_subunion
[(int) alt
][class];
1324 /* If we don't add any classes, nothing to try. */
1329 && (reg_pref
[i
].prefclass
!= (int) best
1330 || reg_pref
[i
].altclass
!= (int) alt
))
1332 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1333 fprintf (dump
, " Register %i", i
);
1334 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1335 fprintf (dump
, " pref %s\n", reg_class_names
[(int) best
]);
1336 else if (alt
== NO_REGS
)
1337 fprintf (dump
, " pref %s or none\n", reg_class_names
[(int) best
]);
1339 fprintf (dump
, " pref %s, else %s\n",
1340 reg_class_names
[(int) best
],
1341 reg_class_names
[(int) alt
]);
1344 /* We cast to (int) because (char) hits bugs in some compilers. */
1345 reg_pref
[i
].prefclass
= (int) best
;
1346 reg_pref
[i
].altclass
= (int) alt
;
1350 #ifdef FORBIDDEN_INC_DEC_CLASSES
1356 /* Record the cost of using memory or registers of various classes for
1357 the operands in INSN.
1359 N_ALTS is the number of alternatives.
1361 N_OPS is the number of operands.
1363 OPS is an array of the operands.
1365 MODES are the modes of the operands, in case any are VOIDmode.
1367 CONSTRAINTS are the constraints to use for the operands. This array
1368 is modified by this procedure.
1370 This procedure works alternative by alternative. For each alternative
1371 we assume that we will be able to allocate all pseudos to their ideal
1372 register class and calculate the cost of using that alternative. Then
1373 we compute for each operand that is a pseudo-register, the cost of
1374 having the pseudo allocated to each register class and using it in that
1375 alternative. To this cost is added the cost of the alternative.
1377 The cost of each class for this insn is its lowest cost among all the
1381 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
1382 enum machine_mode
*modes
, const char **constraints
,
1383 rtx insn
, struct costs
*op_costs
,
1384 struct reg_pref
*reg_pref
)
1390 /* Process each alternative, each time minimizing an operand's cost with
1391 the cost for each operand in that alternative. */
1393 for (alt
= 0; alt
< n_alts
; alt
++)
1395 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1398 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1399 int allows_mem
[MAX_RECOG_OPERANDS
];
1402 for (i
= 0; i
< n_ops
; i
++)
1404 const char *p
= constraints
[i
];
1406 enum machine_mode mode
= modes
[i
];
1407 int allows_addr
= 0;
1411 /* Initially show we know nothing about the register class. */
1412 classes
[i
] = NO_REGS
;
1415 /* If this operand has no constraints at all, we can conclude
1416 nothing about it since anything is valid. */
1420 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1421 memset (&this_op_costs
[i
], 0, sizeof this_op_costs
[i
]);
1426 /* If this alternative is only relevant when this operand
1427 matches a previous operand, we do different things depending
1428 on whether this operand is a pseudo-reg or not. We must process
1429 any modifiers for the operand before we can make this test. */
1431 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1434 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1436 /* Copy class and whether memory is allowed from the matching
1437 alternative. Then perform any needed cost computations
1438 and/or adjustments. */
1440 classes
[i
] = classes
[j
];
1441 allows_mem
[i
] = allows_mem
[j
];
1443 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1445 /* If this matches the other operand, we have no added
1447 if (rtx_equal_p (ops
[j
], op
))
1450 /* If we can put the other operand into a register, add to
1451 the cost of this alternative the cost to copy this
1452 operand to the register used for the other operand. */
1454 else if (classes
[j
] != NO_REGS
)
1455 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1457 else if (GET_CODE (ops
[j
]) != REG
1458 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1460 /* This op is a pseudo but the one it matches is not. */
1462 /* If we can't put the other operand into a register, this
1463 alternative can't be used. */
1465 if (classes
[j
] == NO_REGS
)
1468 /* Otherwise, add to the cost of this alternative the cost
1469 to copy the other operand to the register used for this
1473 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1477 /* The costs of this operand are not the same as the other
1478 operand since move costs are not symmetric. Moreover,
1479 if we cannot tie them, this alternative needs to do a
1480 copy, which is one instruction. */
1482 struct costs
*pp
= &this_op_costs
[i
];
1484 for (class = 0; class < N_REG_CLASSES
; class++)
1486 = ((recog_data
.operand_type
[i
] != OP_OUT
1487 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1489 + (recog_data
.operand_type
[i
] != OP_IN
1490 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1493 /* If the alternative actually allows memory, make things
1494 a bit cheaper since we won't need an extra insn to
1498 = ((recog_data
.operand_type
[i
] != OP_IN
1499 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1501 + (recog_data
.operand_type
[i
] != OP_OUT
1502 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1503 : 0) - allows_mem
[i
]);
1505 /* If we have assigned a class to this register in our
1506 first pass, add a cost to this alternative corresponding
1507 to what we would add if this register were not in the
1508 appropriate class. */
1512 += (may_move_in_cost
[mode
]
1513 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1514 [(int) classes
[i
]]);
1516 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1517 && ! find_reg_note (insn
, REG_DEAD
, op
))
1520 /* This is in place of ordinary cost computation
1521 for this operand, so skip to the end of the
1522 alternative (should be just one character). */
1523 while (*p
&& *p
++ != ',')
1531 /* Scan all the constraint letters. See if the operand matches
1532 any of the constraints. Collect the valid register classes
1533 and see if this operand accepts memory. */
1542 /* Ignore the next letter for this pass. */
1548 case '!': case '#': case '&':
1549 case '0': case '1': case '2': case '3': case '4':
1550 case '5': case '6': case '7': case '8': case '9':
1555 win
= address_operand (op
, GET_MODE (op
));
1556 /* We know this operand is an address, so we want it to be
1557 allocated to a register that can be the base of an
1558 address, ie BASE_REG_CLASS. */
1560 = reg_class_subunion
[(int) classes
[i
]]
1561 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1564 case 'm': case 'o': case 'V':
1565 /* It doesn't seem worth distinguishing between offsettable
1566 and non-offsettable addresses here. */
1568 if (GET_CODE (op
) == MEM
)
1573 if (GET_CODE (op
) == MEM
1574 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1575 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1580 if (GET_CODE (op
) == MEM
1581 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1582 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1588 if (GET_CODE (op
) == CONST_DOUBLE
1589 || (GET_CODE (op
) == CONST_VECTOR
1590 && (GET_MODE_CLASS (GET_MODE (op
))
1591 == MODE_VECTOR_FLOAT
)))
1597 if (GET_CODE (op
) == CONST_DOUBLE
1598 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1603 if (GET_CODE (op
) == CONST_INT
1604 || (GET_CODE (op
) == CONST_DOUBLE
1605 && GET_MODE (op
) == VOIDmode
))
1609 #ifdef LEGITIMATE_PIC_OPERAND_P
1610 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1617 if (GET_CODE (op
) == CONST_INT
1618 || (GET_CODE (op
) == CONST_DOUBLE
1619 && GET_MODE (op
) == VOIDmode
))
1631 if (GET_CODE (op
) == CONST_INT
1632 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1641 if (GET_CODE (op
) == MEM
1643 #ifdef LEGITIMATE_PIC_OPERAND_P
1644 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1651 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1655 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
1657 = reg_class_subunion
[(int) classes
[i
]]
1658 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1659 #ifdef EXTRA_CONSTRAINT_STR
1660 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1663 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1665 /* Every MEM can be reloaded to fit. */
1667 if (GET_CODE (op
) == MEM
)
1670 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1672 /* Every address can be reloaded to fit. */
1674 if (address_operand (op
, GET_MODE (op
)))
1676 /* We know this operand is an address, so we want it to
1677 be allocated to a register that can be the base of an
1678 address, ie BASE_REG_CLASS. */
1680 = reg_class_subunion
[(int) classes
[i
]]
1681 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1686 p
+= CONSTRAINT_LEN (c
, p
);
1693 /* How we account for this operand now depends on whether it is a
1694 pseudo register or not. If it is, we first check if any
1695 register classes are valid. If not, we ignore this alternative,
1696 since we want to assume that all pseudos get allocated for
1697 register preferencing. If some register class is valid, compute
1698 the costs of moving the pseudo into that class. */
1700 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1702 if (classes
[i
] == NO_REGS
)
1704 /* We must always fail if the operand is a REG, but
1705 we did not find a suitable class.
1707 Otherwise we may perform an uninitialized read
1708 from this_op_costs after the `continue' statement
1714 struct costs
*pp
= &this_op_costs
[i
];
1716 for (class = 0; class < N_REG_CLASSES
; class++)
1718 = ((recog_data
.operand_type
[i
] != OP_OUT
1719 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1721 + (recog_data
.operand_type
[i
] != OP_IN
1722 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1725 /* If the alternative actually allows memory, make things
1726 a bit cheaper since we won't need an extra insn to
1730 = ((recog_data
.operand_type
[i
] != OP_IN
1731 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1733 + (recog_data
.operand_type
[i
] != OP_OUT
1734 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1735 : 0) - allows_mem
[i
]);
1737 /* If we have assigned a class to this register in our
1738 first pass, add a cost to this alternative corresponding
1739 to what we would add if this register were not in the
1740 appropriate class. */
1744 += (may_move_in_cost
[mode
]
1745 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1746 [(int) classes
[i
]]);
1750 /* Otherwise, if this alternative wins, either because we
1751 have already determined that or if we have a hard register of
1752 the proper class, there is no cost for this alternative. */
1755 || (GET_CODE (op
) == REG
1756 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1759 /* If registers are valid, the cost of this alternative includes
1760 copying the object to and/or from a register. */
1762 else if (classes
[i
] != NO_REGS
)
1764 if (recog_data
.operand_type
[i
] != OP_OUT
)
1765 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1767 if (recog_data
.operand_type
[i
] != OP_IN
)
1768 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1771 /* The only other way this alternative can be used is if this is a
1772 constant that could be placed into memory. */
1774 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1775 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1783 /* Finally, update the costs with the information we've calculated
1784 about this alternative. */
1786 for (i
= 0; i
< n_ops
; i
++)
1787 if (GET_CODE (ops
[i
]) == REG
1788 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1790 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1791 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1793 pp
->mem_cost
= MIN (pp
->mem_cost
,
1794 (qq
->mem_cost
+ alt_cost
) * scale
);
1796 for (class = 0; class < N_REG_CLASSES
; class++)
1797 pp
->cost
[class] = MIN (pp
->cost
[class],
1798 (qq
->cost
[class] + alt_cost
) * scale
);
1802 /* If this insn is a single set copying operand 1 to operand 0
1803 and one operand is a pseudo with the other a hard reg or a pseudo
1804 that prefers a register that is in its own register class then
1805 we may want to adjust the cost of that register class to -1.
1807 Avoid the adjustment if the source does not die to avoid stressing of
1808 register allocator by preferrencing two colliding registers into single
1811 Also avoid the adjustment if a copy between registers of the class
1812 is expensive (ten times the cost of a default copy is considered
1813 arbitrarily expensive). This avoids losing when the preferred class
1814 is very expensive as the source of a copy instruction. */
1816 if ((set
= single_set (insn
)) != 0
1817 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1818 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
1819 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1820 for (i
= 0; i
<= 1; i
++)
1821 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1823 unsigned int regno
= REGNO (ops
[!i
]);
1824 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1828 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0)
1830 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1832 if ((reg_class_size
[(unsigned char) pref
]
1833 == (unsigned) CLASS_MAX_NREGS (pref
, mode
))
1834 && REGISTER_MOVE_COST (mode
, pref
, pref
) < 10 * 2)
1835 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1837 else if (regno
< FIRST_PSEUDO_REGISTER
)
1838 for (class = 0; class < N_REG_CLASSES
; class++)
1839 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1840 && reg_class_size
[class] == (unsigned) CLASS_MAX_NREGS (class, mode
))
1842 if (reg_class_size
[class] == 1)
1843 op_costs
[i
].cost
[class] = -1;
1846 for (nr
= 0; nr
< (unsigned) hard_regno_nregs
[regno
][mode
]; nr
++)
1848 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
1853 if (nr
== (unsigned) hard_regno_nregs
[regno
][mode
])
1854 op_costs
[i
].cost
[class] = -1;
1860 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
1861 TO_P is zero) a register of class CLASS in mode MODE.
1863 X must not be a pseudo. */
1866 copy_cost (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1867 enum reg_class
class, int to_p ATTRIBUTE_UNUSED
)
1869 #ifdef HAVE_SECONDARY_RELOADS
1870 enum reg_class secondary_class
= NO_REGS
;
1873 /* If X is a SCRATCH, there is actually nothing to move since we are
1874 assuming optimal allocation. */
1876 if (GET_CODE (x
) == SCRATCH
)
1879 /* Get the class we will actually use for a reload. */
1880 class = PREFERRED_RELOAD_CLASS (x
, class);
1882 #ifdef HAVE_SECONDARY_RELOADS
1883 /* If we need a secondary reload (we assume here that we are using
1884 the secondary reload as an intermediate, not a scratch register), the
1885 cost is that to load the input into the intermediate register, then
1886 to copy them. We use a special value of TO_P to avoid recursion. */
1888 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1890 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1893 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1895 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1898 if (secondary_class
!= NO_REGS
)
1899 return (move_cost
[mode
][(int) secondary_class
][(int) class]
1900 + copy_cost (x
, mode
, secondary_class
, 2));
1901 #endif /* HAVE_SECONDARY_RELOADS */
1903 /* For memory, use the memory move cost, for (hard) registers, use the
1904 cost to move between the register classes, and use 2 for everything
1905 else (constants). */
1907 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1908 return MEMORY_MOVE_COST (mode
, class, to_p
);
1910 else if (GET_CODE (x
) == REG
)
1911 return move_cost
[mode
][(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1914 /* If this is a constant, we may eventually want to call rtx_cost here. */
1915 return COSTS_N_INSNS (1);
1918 /* Record the pseudo registers we must reload into hard registers
1919 in a subexpression of a memory address, X.
1921 CLASS is the class that the register needs to be in and is either
1922 BASE_REG_CLASS or INDEX_REG_CLASS.
1924 SCALE is twice the amount to multiply the cost by (it is twice so we
1925 can represent half-cost adjustments). */
1928 record_address_regs (rtx x
, enum reg_class
class, int scale
)
1930 enum rtx_code code
= GET_CODE (x
);
1943 /* When we have an address that is a sum,
1944 we must determine whether registers are "base" or "index" regs.
1945 If there is a sum of two registers, we must choose one to be
1946 the "base". Luckily, we can use the REG_POINTER to make a good
1947 choice most of the time. We only need to do this on machines
1948 that can have two registers in an address and where the base
1949 and index register classes are different.
1951 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1952 that seems bogus since it should only be set when we are sure
1953 the register is being used as a pointer. */
1956 rtx arg0
= XEXP (x
, 0);
1957 rtx arg1
= XEXP (x
, 1);
1958 enum rtx_code code0
= GET_CODE (arg0
);
1959 enum rtx_code code1
= GET_CODE (arg1
);
1961 /* Look inside subregs. */
1962 if (code0
== SUBREG
)
1963 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1964 if (code1
== SUBREG
)
1965 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1967 /* If this machine only allows one register per address, it must
1968 be in the first operand. */
1970 if (MAX_REGS_PER_ADDRESS
== 1)
1971 record_address_regs (arg0
, class, scale
);
1973 /* If index and base registers are the same on this machine, just
1974 record registers in any non-constant operands. We assume here,
1975 as well as in the tests below, that all addresses are in
1978 else if (INDEX_REG_CLASS
== MODE_BASE_REG_CLASS (VOIDmode
))
1980 record_address_regs (arg0
, class, scale
);
1981 if (! CONSTANT_P (arg1
))
1982 record_address_regs (arg1
, class, scale
);
1985 /* If the second operand is a constant integer, it doesn't change
1986 what class the first operand must be. */
1988 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1989 record_address_regs (arg0
, class, scale
);
1991 /* If the second operand is a symbolic constant, the first operand
1992 must be an index register. */
1994 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1995 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1997 /* If both operands are registers but one is already a hard register
1998 of index or base class, give the other the class that the hard
2001 #ifdef REG_OK_FOR_BASE_P
2002 else if (code0
== REG
&& code1
== REG
2003 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
2004 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
2005 record_address_regs (arg1
,
2006 REG_OK_FOR_BASE_P (arg0
)
2007 ? INDEX_REG_CLASS
: MODE_BASE_REG_CLASS (VOIDmode
),
2009 else if (code0
== REG
&& code1
== REG
2010 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
2011 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
2012 record_address_regs (arg0
,
2013 REG_OK_FOR_BASE_P (arg1
)
2014 ? INDEX_REG_CLASS
: MODE_BASE_REG_CLASS (VOIDmode
),
2018 /* If one operand is known to be a pointer, it must be the base
2019 with the other operand the index. Likewise if the other operand
2022 else if ((code0
== REG
&& REG_POINTER (arg0
))
2025 record_address_regs (arg0
, MODE_BASE_REG_CLASS (VOIDmode
), scale
);
2026 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
2028 else if ((code1
== REG
&& REG_POINTER (arg1
))
2031 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
2032 record_address_regs (arg1
, MODE_BASE_REG_CLASS (VOIDmode
), scale
);
2035 /* Otherwise, count equal chances that each might be a base
2036 or index register. This case should be rare. */
2040 record_address_regs (arg0
, MODE_BASE_REG_CLASS (VOIDmode
),
2042 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
2043 record_address_regs (arg1
, MODE_BASE_REG_CLASS (VOIDmode
),
2045 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
2050 /* Double the importance of a pseudo register that is incremented
2051 or decremented, since it would take two extra insns
2052 if it ends up in the wrong place. */
2055 record_address_regs (XEXP (x
, 0), MODE_BASE_REG_CLASS (VOIDmode
),
2057 if (REG_P (XEXP (XEXP (x
, 1), 1)))
2058 record_address_regs (XEXP (XEXP (x
, 1), 1),
2059 INDEX_REG_CLASS
, 2 * scale
);
2066 /* Double the importance of a pseudo register that is incremented
2067 or decremented, since it would take two extra insns
2068 if it ends up in the wrong place. If the operand is a pseudo,
2069 show it is being used in an INC_DEC context. */
2071 #ifdef FORBIDDEN_INC_DEC_CLASSES
2072 if (GET_CODE (XEXP (x
, 0)) == REG
2073 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
2074 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
2077 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
2082 struct costs
*pp
= &costs
[REGNO (x
)];
2085 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
2087 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2088 pp
->cost
[i
] += (may_move_in_cost
[Pmode
][i
][(int) class] * scale
) / 2;
2094 const char *fmt
= GET_RTX_FORMAT (code
);
2096 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2098 record_address_regs (XEXP (x
, i
), class, scale
);
2103 #ifdef FORBIDDEN_INC_DEC_CLASSES
2105 /* Return 1 if REG is valid as an auto-increment memory reference
2106 to an object of MODE. */
2109 auto_inc_dec_reg_p (rtx reg
, enum machine_mode mode
)
2111 if (HAVE_POST_INCREMENT
2112 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
2115 if (HAVE_POST_DECREMENT
2116 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
2119 if (HAVE_PRE_INCREMENT
2120 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
2123 if (HAVE_PRE_DECREMENT
2124 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
2131 static short *renumber
;
2132 static size_t regno_allocated
;
2133 static unsigned int reg_n_max
;
2135 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2136 reg_scan and flow_analysis that are indexed by the register number. If
2137 NEW_P is nonzero, initialize all of the registers, otherwise only
2138 initialize the new registers allocated. The same table is kept from
2139 function to function, only reallocating it when we need more room. If
2140 RENUMBER_P is nonzero, allocate the reg_renumber array also. */
2143 allocate_reg_info (size_t num_regs
, int new_p
, int renumber_p
)
2146 size_t size_renumber
;
2147 size_t min
= (new_p
) ? 0 : reg_n_max
;
2148 struct reg_info_data
*reg_data
;
2150 if (num_regs
> regno_allocated
)
2152 size_t old_allocated
= regno_allocated
;
2154 regno_allocated
= num_regs
+ (num_regs
/ 20); /* Add some slop space. */
2155 size_renumber
= regno_allocated
* sizeof (short);
2159 VARRAY_REG_INIT (reg_n_info
, regno_allocated
, "reg_n_info");
2160 renumber
= xmalloc (size_renumber
);
2161 reg_pref_buffer
= xmalloc (regno_allocated
2162 * sizeof (struct reg_pref
));
2167 VARRAY_GROW (reg_n_info
, regno_allocated
);
2169 if (new_p
) /* If we're zapping everything, no need to realloc. */
2171 free ((char *) renumber
);
2172 free ((char *) reg_pref
);
2173 renumber
= xmalloc (size_renumber
);
2174 reg_pref_buffer
= xmalloc (regno_allocated
2175 * sizeof (struct reg_pref
));
2180 renumber
= xrealloc (renumber
, size_renumber
);
2181 reg_pref_buffer
= xrealloc (reg_pref_buffer
,
2183 * sizeof (struct reg_pref
));
2187 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
2188 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
2189 reg_data
= xcalloc (size_info
, 1);
2190 reg_data
->min_index
= old_allocated
;
2191 reg_data
->max_index
= regno_allocated
- 1;
2192 reg_data
->next
= reg_info_head
;
2193 reg_info_head
= reg_data
;
2196 reg_n_max
= num_regs
;
2199 /* Loop through each of the segments allocated for the actual
2200 reg_info pages, and set up the pointers, zero the pages, etc. */
2201 for (reg_data
= reg_info_head
;
2202 reg_data
&& reg_data
->max_index
>= min
;
2203 reg_data
= reg_data
->next
)
2205 size_t min_index
= reg_data
->min_index
;
2206 size_t max_index
= reg_data
->max_index
;
2207 size_t max
= MIN (max_index
, num_regs
);
2208 size_t local_min
= min
- min_index
;
2211 if (reg_data
->min_index
> num_regs
)
2214 if (min
< min_index
)
2216 if (!reg_data
->used_p
) /* page just allocated with calloc */
2217 reg_data
->used_p
= 1; /* no need to zero */
2219 memset (®_data
->data
[local_min
], 0,
2220 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
2222 for (i
= min_index
+local_min
; i
<= max
; i
++)
2224 VARRAY_REG (reg_n_info
, i
) = ®_data
->data
[i
-min_index
];
2225 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
2227 reg_pref_buffer
[i
].prefclass
= (char) NO_REGS
;
2228 reg_pref_buffer
[i
].altclass
= (char) NO_REGS
;
2233 /* If {pref,alt}class have already been allocated, update the pointers to
2234 the newly realloced ones. */
2236 reg_pref
= reg_pref_buffer
;
2239 reg_renumber
= renumber
;
2241 /* Tell the regset code about the new number of registers. */
2242 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
2245 /* Free up the space allocated by allocate_reg_info. */
2247 free_reg_info (void)
2251 struct reg_info_data
*reg_data
;
2252 struct reg_info_data
*reg_next
;
2254 VARRAY_FREE (reg_n_info
);
2255 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
2257 reg_next
= reg_data
->next
;
2258 free ((char *) reg_data
);
2261 free (reg_pref_buffer
);
2262 reg_pref_buffer
= (struct reg_pref
*) 0;
2263 reg_info_head
= (struct reg_info_data
*) 0;
2264 renumber
= (short *) 0;
2266 regno_allocated
= 0;
2270 /* This is the `regscan' pass of the compiler, run just before cse
2271 and again just before loop.
2273 It finds the first and last use of each pseudo-register
2274 and records them in the vectors regno_first_uid, regno_last_uid
2275 and counts the number of sets in the vector reg_n_sets.
2277 REPEAT is nonzero the second time this is called. */
2279 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2280 Always at least 3, since the combiner could put that many together
2281 and we want this to remain correct for all the remaining passes.
2282 This corresponds to the maximum number of times note_stores will call
2283 a function for any insn. */
2287 /* Used as a temporary to record the largest number of registers in
2288 PARALLEL in a SET_DEST. This is added to max_parallel. */
2290 static int max_set_parallel
;
2293 reg_scan (rtx f
, unsigned int nregs
, int repeat ATTRIBUTE_UNUSED
)
2297 timevar_push (TV_REG_SCAN
);
2299 allocate_reg_info (nregs
, TRUE
, FALSE
);
2301 max_set_parallel
= 0;
2303 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2306 rtx pat
= PATTERN (insn
);
2307 if (GET_CODE (pat
) == PARALLEL
2308 && XVECLEN (pat
, 0) > max_parallel
)
2309 max_parallel
= XVECLEN (pat
, 0);
2310 reg_scan_mark_refs (pat
, insn
, 0, 0);
2312 if (REG_NOTES (insn
))
2313 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, 0);
2316 max_parallel
+= max_set_parallel
;
2318 timevar_pop (TV_REG_SCAN
);
2321 /* Update 'regscan' information by looking at the insns
2322 from FIRST to LAST. Some new REGs have been created,
2323 and any REG with number greater than OLD_MAX_REGNO is
2324 such a REG. We only update information for those. */
2327 reg_scan_update (rtx first
, rtx last
, unsigned int old_max_regno
)
2331 allocate_reg_info (max_reg_num (), FALSE
, FALSE
);
2333 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
2336 rtx pat
= PATTERN (insn
);
2337 if (GET_CODE (pat
) == PARALLEL
2338 && XVECLEN (pat
, 0) > max_parallel
)
2339 max_parallel
= XVECLEN (pat
, 0);
2340 reg_scan_mark_refs (pat
, insn
, 0, old_max_regno
);
2342 if (REG_NOTES (insn
))
2343 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, old_max_regno
);
2347 /* X is the expression to scan. INSN is the insn it appears in.
2348 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2349 We should only record information for REGs with numbers
2350 greater than or equal to MIN_REGNO. */
2353 reg_scan_mark_refs (rtx x
, rtx insn
, int note_flag
, unsigned int min_regno
)
2361 code
= GET_CODE (x
);
2378 unsigned int regno
= REGNO (x
);
2380 if (regno
>= min_regno
)
2382 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
2384 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2385 if (REGNO_FIRST_UID (regno
) == 0)
2386 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2387 /* If we are called by reg_scan_update() (indicated by min_regno
2388 being set), we also need to update the reference count. */
2390 REG_N_REFS (regno
)++;
2397 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
, min_regno
);
2399 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2404 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2409 rtx reg
= XEXP (x
, 0);
2411 && REGNO (reg
) >= min_regno
)
2413 REG_N_SETS (REGNO (reg
))++;
2414 REG_N_REFS (REGNO (reg
))++;
2416 else if (GET_CODE (reg
) == MEM
)
2417 reg_scan_mark_refs (XEXP (reg
, 0), insn
, note_flag
, min_regno
);
2422 /* Count a set of the destination if it is a register. */
2423 for (dest
= SET_DEST (x
);
2424 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2425 || GET_CODE (dest
) == ZERO_EXTEND
;
2426 dest
= XEXP (dest
, 0))
2429 /* For a PARALLEL, record the number of things (less the usual one for a
2430 SET) that are set. */
2431 if (GET_CODE (dest
) == PARALLEL
)
2432 max_set_parallel
= MAX (max_set_parallel
, XVECLEN (dest
, 0) - 1);
2434 if (GET_CODE (dest
) == REG
2435 && REGNO (dest
) >= min_regno
)
2437 REG_N_SETS (REGNO (dest
))++;
2438 REG_N_REFS (REGNO (dest
))++;
2441 /* If this is setting a pseudo from another pseudo or the sum of a
2442 pseudo and a constant integer and the other pseudo is known to be
2443 a pointer, set the destination to be a pointer as well.
2445 Likewise if it is setting the destination from an address or from a
2446 value equivalent to an address or to the sum of an address and
2449 But don't do any of this if the pseudo corresponds to a user
2450 variable since it should have already been set as a pointer based
2453 if (GET_CODE (SET_DEST (x
)) == REG
2454 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2455 && REGNO (SET_DEST (x
)) >= min_regno
2456 /* If the destination pseudo is set more than once, then other
2457 sets might not be to a pointer value (consider access to a
2458 union in two threads of control in the presence of global
2459 optimizations). So only set REG_POINTER on the destination
2460 pseudo if this is the only set of that pseudo. */
2461 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2462 && ! REG_USERVAR_P (SET_DEST (x
))
2463 && ! REG_POINTER (SET_DEST (x
))
2464 && ((GET_CODE (SET_SRC (x
)) == REG
2465 && REG_POINTER (SET_SRC (x
)))
2466 || ((GET_CODE (SET_SRC (x
)) == PLUS
2467 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2468 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2469 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2470 && REG_POINTER (XEXP (SET_SRC (x
), 0)))
2471 || GET_CODE (SET_SRC (x
)) == CONST
2472 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2473 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2474 || (GET_CODE (SET_SRC (x
)) == HIGH
2475 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2476 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2477 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2478 || ((GET_CODE (SET_SRC (x
)) == PLUS
2479 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2480 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2481 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2482 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2483 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2484 && (GET_CODE (XEXP (note
, 0)) == CONST
2485 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2486 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2487 REG_POINTER (SET_DEST (x
)) = 1;
2489 /* If this is setting a register from a register or from a simple
2490 conversion of a register, propagate REG_EXPR. */
2491 if (GET_CODE (dest
) == REG
)
2493 rtx src
= SET_SRC (x
);
2495 while (GET_CODE (src
) == SIGN_EXTEND
2496 || GET_CODE (src
) == ZERO_EXTEND
2497 || GET_CODE (src
) == TRUNCATE
2498 || (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)))
2499 src
= XEXP (src
, 0);
2501 if (!REG_ATTRS (dest
) && REG_P (src
))
2502 REG_ATTRS (dest
) = REG_ATTRS (src
);
2503 if (!REG_ATTRS (dest
) && GET_CODE (src
) == MEM
)
2504 set_reg_attrs_from_mem (dest
, src
);
2507 /* ... fall through ... */
2511 const char *fmt
= GET_RTX_FORMAT (code
);
2513 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2516 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
, min_regno
);
2517 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2520 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2521 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
, min_regno
);
2528 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2532 reg_class_subset_p (enum reg_class c1
, enum reg_class c2
)
2534 if (c1
== c2
) return 1;
2539 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) c1
],
2540 reg_class_contents
[(int) c2
],
2545 /* Return nonzero if there is a register that is in both C1 and C2. */
2548 reg_classes_intersect_p (enum reg_class c1
, enum reg_class c2
)
2552 if (c1
== c2
) return 1;
2554 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2557 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2558 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2560 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2567 /* Release any memory allocated by register sets. */
2570 regset_release_memory (void)
2572 bitmap_release_memory ();
2575 #ifdef CANNOT_CHANGE_MODE_CLASS
2576 /* Set bits in *USED which correspond to registers which can't change
2577 their mode from FROM to any mode in which REGNO was encountered. */
2580 cannot_change_mode_set_regs (HARD_REG_SET
*used
, enum machine_mode from
,
2583 enum machine_mode to
;
2585 int start
= regno
* MAX_MACHINE_MODE
;
2587 EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode
, start
, n
,
2588 if (n
>= MAX_MACHINE_MODE
+ start
)
2591 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2592 if (! TEST_HARD_REG_BIT (*used
, i
)
2593 && REG_CANNOT_CHANGE_MODE_P (i
, from
, to
))
2594 SET_HARD_REG_BIT (*used
, i
);
2598 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2602 invalid_mode_change_p (unsigned int regno
, enum reg_class
class,
2603 enum machine_mode from_mode
)
2605 enum machine_mode to_mode
;
2607 int start
= regno
* MAX_MACHINE_MODE
;
2609 EXECUTE_IF_SET_IN_BITMAP (&subregs_of_mode
, start
, n
,
2610 if (n
>= MAX_MACHINE_MODE
+ start
)
2612 to_mode
= n
- start
;
2613 if (CANNOT_CHANGE_MODE_CLASS (from_mode
, to_mode
, class))
2618 #endif /* CANNOT_CHANGE_MODE_CLASS */
2620 #include "gt-regclass.h"