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1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables.
27 Basic induction variables (BIVs) are a pseudo registers which are set within
28 a loop only by incrementing or decrementing its value. General induction
29 variables (GIVs) are pseudo registers with a value which is a linear function
30 of a basic induction variable. BIVs are recognized by `basic_induction_var';
31 GIVs by `general_induction_var'.
33 Once induction variables are identified, strength reduction is applied to the
34 general induction variables, and induction variable elimination is applied to
35 the basic induction variables.
37 It also finds cases where
38 a register is set within the loop by zero-extending a narrower value
39 and changes these to zero the entire register once before the loop
40 and merely copy the low part within the loop.
42 Most of the complexity is in heuristics to decide when it is worth
43 while to do these things. */
70 /* Not really meaningful values, but at least something. */
71 #ifndef SIMULTANEOUS_PREFETCHES
72 #define SIMULTANEOUS_PREFETCHES 3
73 #endif
74 #ifndef PREFETCH_BLOCK
75 #define PREFETCH_BLOCK 32
76 #endif
77 #ifndef HAVE_prefetch
78 #define HAVE_prefetch 0
79 #define CODE_FOR_prefetch 0
80 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
81 #endif
83 /* Give up the prefetch optimizations once we exceed a given threshold.
84 It is unlikely that we would be able to optimize something in a loop
85 with so many detected prefetches. */
86 #define MAX_PREFETCHES 100
87 /* The number of prefetch blocks that are beneficial to fetch at once before
88 a loop with a known (and low) iteration count. */
89 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
90 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
91 since it is likely that the data are already in the cache. */
92 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
94 /* Parameterize some prefetch heuristics so they can be turned on and off
95 easily for performance testing on new architectures. These can be
96 defined in target-dependent files. */
98 /* Prefetch is worthwhile only when loads/stores are dense. */
99 #ifndef PREFETCH_ONLY_DENSE_MEM
100 #define PREFETCH_ONLY_DENSE_MEM 1
101 #endif
103 /* Define what we mean by "dense" loads and stores; This value divided by 256
104 is the minimum percentage of memory references that worth prefetching. */
105 #ifndef PREFETCH_DENSE_MEM
106 #define PREFETCH_DENSE_MEM 220
107 #endif
109 /* Do not prefetch for a loop whose iteration count is known to be low. */
110 #ifndef PREFETCH_NO_LOW_LOOPCNT
111 #define PREFETCH_NO_LOW_LOOPCNT 1
112 #endif
114 /* Define what we mean by a "low" iteration count. */
115 #ifndef PREFETCH_LOW_LOOPCNT
116 #define PREFETCH_LOW_LOOPCNT 32
117 #endif
119 /* Do not prefetch for a loop that contains a function call; such a loop is
120 probably not an internal loop. */
121 #ifndef PREFETCH_NO_CALL
122 #define PREFETCH_NO_CALL 1
123 #endif
125 /* Do not prefetch accesses with an extreme stride. */
126 #ifndef PREFETCH_NO_EXTREME_STRIDE
127 #define PREFETCH_NO_EXTREME_STRIDE 1
128 #endif
130 /* Define what we mean by an "extreme" stride. */
131 #ifndef PREFETCH_EXTREME_STRIDE
132 #define PREFETCH_EXTREME_STRIDE 4096
133 #endif
135 /* Define a limit to how far apart indices can be and still be merged
136 into a single prefetch. */
137 #ifndef PREFETCH_EXTREME_DIFFERENCE
138 #define PREFETCH_EXTREME_DIFFERENCE 4096
139 #endif
141 /* Issue prefetch instructions before the loop to fetch data to be used
142 in the first few loop iterations. */
143 #ifndef PREFETCH_BEFORE_LOOP
144 #define PREFETCH_BEFORE_LOOP 1
145 #endif
147 /* Do not handle reversed order prefetches (negative stride). */
148 #ifndef PREFETCH_NO_REVERSE_ORDER
149 #define PREFETCH_NO_REVERSE_ORDER 1
150 #endif
152 /* Prefetch even if the GIV is in conditional code. */
153 #ifndef PREFETCH_CONDITIONAL
154 #define PREFETCH_CONDITIONAL 1
155 #endif
157 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
158 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
160 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
161 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
162 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
164 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
165 ((REGNO) < FIRST_PSEUDO_REGISTER \
166 ? (int) hard_regno_nregs[(REGNO)][GET_MODE (SET_DEST)] : 1)
169 /* Vector mapping INSN_UIDs to luids.
170 The luids are like uids but increase monotonically always.
171 We use them to see whether a jump comes from outside a given loop. */
175 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
176 number the insn is contained in. */
180 /* 1 + largest uid of any insn. */
184 /* Number of loops detected in current function. Used as index to the
185 next few tables. */
189 /* Bound on pseudo register number before loop optimization.
190 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
193 /* The value to pass to the next call of reg_scan_update. */
195 \f
196 /* During the analysis of a loop, a chain of `struct movable's
197 is made to record all the movable insns found.
198 Then the entire chain can be scanned to decide which to move. */
200 struct movable
201 {
206 of any registers used within the LIBCALL. */
208 that must be moved with this one. */
211 may be adjusted when matching movables
212 that load the same value are found. */
214 including other movables that force this
215 or match this one. */
217 a low part that we should avoid changing when
218 clearing the rest of the reg. */
222 /* If PARTIAL is 1, GLOBAL means something different:
223 that the reg is live outside the range from where it is set
224 to the following label. */
228 In particular, moving it does not make it
229 invariant. */
231 load SRC, rather than copying INSN. */
233 first insn of a consecutive sets group. */
236 the original insn with a copy from that
237 pseudo, rather than deleting it. */
241 };
246 /* Forward declarations. */
261 #if 0
263 #endif
304 rtx *);
365 {
366 rtx match;
367 rtx replacement;
368 rtx insn;
371 /* Nonzero iff INSN is between START and END, inclusive. */
372 #define INSN_IN_RANGE_P(INSN, START, END) \
373 (INSN_UID (INSN) < max_uid_for_loop \
374 && INSN_LUID (INSN) >= INSN_LUID (START) \
375 && INSN_LUID (INSN) <= INSN_LUID (END))
377 /* Indirect_jump_in_function is computed once per function. */
385 \f
386 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
387 copy the value of the strength reduced giv to its original register. */
390 /* Cost of using a register, to normalize the benefits of a giv. */
393 void
395 {
401 }
402 \f
403 /* Compute the mapping from uids to luids.
404 LUIDs are numbers assigned to insns, like uids,
405 except that luids increase monotonically through the code.
406 Start at insn START and stop just before END. Assign LUIDs
407 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
408 static int
410 {
412 rtx insn;
415 {
418 /* Don't assign luids to line-number NOTEs, so that the distance in
419 luids between two insns is not affected by -g. */
423 else
424 /* Give a line number note the same luid as preceding insn. */
426 }
428 }
429 \f
430 /* Entry point of this file. Perform loop optimization
431 on the current function. F is the first insn of the function
432 and DUMPFILE is a stream for output of a trace of actions taken
433 (or 0 if none should be output). */
435 void
437 {
438 rtx insn;
453 /* Count the number of loops. */
457 {
460 max_loop_num++;
461 }
463 /* Don't waste time if no loops. */
469 /* Get size to use for tables indexed by uids.
470 Leave some space for labels allocated by find_and_verify_loops. */
476 /* Allocate storage for array of loops. */
479 /* Find and process each loop.
480 First, find them, and record them in order of their beginnings. */
483 /* Allocate and initialize auxiliary loop information. */
488 /* Now find all register lifetimes. This must be done after
489 find_and_verify_loops, because it might reorder the insns in the
490 function. */
493 /* This must occur after reg_scan so that registers created by gcse
494 will have entries in the register tables.
496 We could have added a call to reg_scan after gcse_main in toplev.c,
497 but moving this call to init_alias_analysis is more efficient. */
500 /* See if we went too far. Note that get_max_uid already returns
501 one more that the maximum uid of all insn. */
504 /* Now reset it to the actual size we need. See above. */
507 /* find_and_verify_loops has already called compute_luids, but it
508 might have rearranged code afterwards, so we need to recompute
509 the luids now. */
512 /* Don't leave gaps in uid_luid for insns that have been
513 deleted. It is possible that the first or last insn
514 using some register has been deleted by cross-jumping.
515 Make sure that uid_luid for that former insn's uid
516 points to the general area where that insn used to be. */
518 {
522 }
527 /* Determine if the function has indirect jump. On some systems
528 this prevents low overhead loop instructions from being used. */
531 /* Now scan the loops, last ones first, since this means inner ones are done
532 before outer ones. */
534 {
538 {
541 }
542 }
546 /* Clean up. */
554 }
555 \f
556 /* Returns the next insn, in execution order, after INSN. START and
557 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
558 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
559 insn-stream; it is used with loops that are entered near the
560 bottom. */
562 static rtx
564 {
568 {
570 /* Go to the top of the loop, and continue there. */
572 else
573 /* We're done. */
575 }
578 /* We're done. */
582 }
584 /* Find any register references hidden inside X and add them to
585 the dependency list DEPS. This is used to look inside CLOBBER (MEM
586 when checking whether a PARALLEL can be pulled out of a loop. */
588 static rtx
590 {
594 else
595 {
599 {
605 }
606 }
608 }
610 /* Optimize one loop described by LOOP. */
612 /* ??? Could also move memory writes out of loops if the destination address
613 is invariant, the source is invariant, the memory write is not volatile,
614 and if we can prove that no read inside the loop can read this address
615 before the write occurs. If there is a read of this address after the
616 write, then we can also mark the memory read as invariant. */
618 static void
620 {
626 rtx p;
627 /* 1 if we are scanning insns that could be executed zero times. */
629 /* 1 if we are scanning insns that might never be executed
630 due to a subroutine call which might exit before they are reached. */
632 /* Number of insns in the loop. */
636 /* The SET from an insn, if it is the only SET in the insn. */
638 /* Chain describing insns movable in current loop. */
640 /* Ratio of extra register life span we can justify
641 for saving an instruction. More if loop doesn't call subroutines
642 since in that case saving an insn makes more difference
643 and more registers are available. */
645 /* Nonzero if we are scanning instructions in a sub-loop. */
654 /* Determine whether this loop starts with a jump down to a test at
655 the end. This will occur for a small number of loops with a test
656 that is too complex to duplicate in front of the loop.
658 We search for the first insn or label in the loop, skipping NOTEs.
659 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
660 (because we might have a loop executed only once that contains a
661 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
662 (in case we have a degenerate loop).
664 Note that if we mistakenly think that a loop is entered at the top
665 when, in fact, it is entered at the exit test, the only effect will be
666 slightly poorer optimization. Making the opposite error can generate
667 incorrect code. Since very few loops now start with a jump to the
668 exit test, the code here to detect that case is very conservative. */
671 p != loop_end
677 ;
681 /* If loop end is the end of the current function, then emit a
682 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
683 note insn. This is the position we use when sinking insns out of
684 the loop. */
687 else
690 /* Set up variables describing this loop. */
694 /* If loop has a jump before the first label,
695 the true entry is the target of that jump.
696 Start scan from there.
697 But record in LOOP->TOP the place where the end-test jumps
698 back to so we can scan that after the end of the loop. */
700 /* Loop entry must be unconditional jump (and not a RETURN) */
703 /* Check to see whether the jump actually
704 jumps out of the loop (meaning it's no loop).
705 This case can happen for things like
706 do {..} while (0). If this label was generated previously
707 by loop, we can't tell anything about it and have to reject
708 the loop. */
710 {
713 }
715 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
716 as required by loop_reg_used_before_p. So skip such loops. (This
717 test may never be true, but it's best to play it safe.)
719 Also, skip loops where we do not start scanning at a label. This
720 test also rejects loops starting with a JUMP_INSN that failed the
721 test above. */
725 {
730 }
732 /* Allocate extra space for REGs that might be created by load_mems.
733 We allocate a little extra slop as well, in the hopes that we
734 won't have to reallocate the regs array. */
739 {
745 }
747 /* Scan through the loop finding insns that are safe to move.
748 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
749 this reg will be considered invariant for subsequent insns.
750 We consider whether subsequent insns use the reg
751 in deciding whether it is worth actually moving.
753 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
754 and therefore it is possible that the insns we are scanning
755 would never be executed. At such times, we must make sure
756 that it is safe to execute the insn once instead of zero times.
757 When MAYBE_NEVER is 0, all insns will be executed at least once
758 so that is not a problem. */
763 {
765 in_libcall--;
767 {
770 in_libcall++;
774 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
776 #endif
778 {
786 /* Figure out what to use as a source of this insn. If a
787 REG_EQUIV note is given or if a REG_EQUAL note with a
788 constant operand is specified, use it as the source and
789 mark that we should move this insn by calling
790 emit_move_insn rather that duplicating the insn.
792 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
793 note is present. */
797 else
798 {
803 {
805 /* A libcall block can use regs that don't appear in
806 the equivalent expression. To move the libcall,
807 we must move those regs too. */
809 }
810 }
812 /* For parallels, add any possible uses to the dependencies, as
813 we can't move the insn without resolving them first.
814 MEMs inside CLOBBERs may also reference registers; these
815 count as implicit uses. */
817 {
819 {
822 dependencies
824 dependencies);
829 }
830 }
833 than the one where it is set (meaning that
834 something after this point in the loop might
835 depend on its value before the set). */
837 /* And the set is not guaranteed to be executed once
838 the loop starts, or the value before the set is
839 needed before the set occurs...
841 ??? Note we have quadratic behavior here, mitigated
842 by the fact that the previous test will often fail for
843 large loops. Rather than re-scanning the entire loop
844 each time for register usage, we should build tables
845 of the register usage and use them here instead. */
846 && (maybe_never
848 /* It is unsafe to move the set. However, it may be OK to
849 move the source into a new pseudo, and substitute a
850 reg-to-reg copy for the original insn.
852 This code used to consider it OK to move a set of a variable
853 which was not created by the user and not used in an exit
854 test.
855 That behavior is incorrect and was removed. */
858 /* Don't try to optimize a MODE_CC set with a constant
859 source. It probably will be combined with a conditional
860 jump. */
863 ;
864 /* Don't try to optimize a register that was made
865 by loop-optimization for an inner loop.
866 We don't know its life-span, so we can't compute
867 the benefit. */
869 ;
870 /* Don't move the source and add a reg-to-reg copy:
871 - with -Os (this certainly increases size),
872 - if the mode doesn't support copy operations (obviously),
873 - if the source is already a reg (the motion will gain nothing),
874 - if the source is a legitimate constant (likewise). */
876 && (optimize_size
881 ;
884 || (tem2
887 || (tem1
888 = consec_sets_invariant_p
891 p)))
892 /* If the insn can cause a trap (such as divide by zero),
893 can't move it unless it's guaranteed to be executed
894 once loop is entered. Even a function call might
895 prevent the trap insn from being reached
896 (since it might exit!) */
899 {
903 /* A potential lossage is where we have a case where two insns
904 can be combined as long as they are both in the loop, but
905 we move one of them outside the loop. For large loops,
906 this can lose. The most common case of this is the address
907 of a function being called.
909 Therefore, if this register is marked as being used
910 exactly once if we are in a loop with calls
911 (a "large loop"), see if we can replace the usage of
912 this register with the source of this SET. If we can,
913 delete this insn.
915 Don't do this if P has a REG_RETVAL note or if we have
916 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
928 && (! SMALL_REGISTER_CLASSES
932 /* This test is not redundant; SET_SRC (set) might be
933 a call-clobbered register and the life of REGNO
934 might span a call. */
941 {
942 /* Replace any usage in a REG_EQUAL note. Must copy
943 the new source, so that we don't get rtx sharing
944 between the SET_SOURCE and REG_NOTES of insn p. */
946 = (replace_rtx
952 i++)
955 }
964 m->consec
975 /* Set M->cond if either loop_invariant_p
976 or consec_sets_invariant_p returned 2
977 (only conditionally invariant). */
987 /* Add M to the end of the chain MOVABLES. */
991 {
992 /* It is possible for the first instruction to have a
993 REG_EQUAL note but a non-invariant SET_SRC, so we must
994 remember the status of the first instruction in case
995 the last instruction doesn't have a REG_EQUAL note. */
998 /* Skip this insn, not checking REG_LIBCALL notes. */
1000 /* Skip the consecutive insns, if there are any. */
1002 /* Back up to the last insn of the consecutive group. */
1005 /* We must now reset m->move_insn, m->is_equiv, and
1006 possibly m->set_src to correspond to the effects of
1007 all the insns. */
1011 else
1012 {
1016 else
1019 }
1020 m->is_equiv
1022 }
1023 }
1024 /* If this register is always set within a STRICT_LOW_PART
1025 or set to zero, then its high bytes are constant.
1026 So clear them outside the loop and within the loop
1027 just load the low bytes.
1028 We must check that the machine has an instruction to do so.
1029 Also, if the value loaded into the register
1030 depends on the same register, this cannot be done. */
1040 {
1043 {
1058 /* If the insn may not be executed on some cycles,
1059 we can't clear the whole reg; clear just high part.
1060 Not even if the reg is used only within this loop.
1061 Consider this:
1062 while (1)
1063 while (s != t) {
1064 if (foo ()) x = *s;
1065 use (x);
1066 }
1067 Clearing x before the inner loop could clobber a value
1068 being saved from the last time around the outer loop.
1069 However, if the reg is not used outside this loop
1070 and all uses of the register are in the same
1071 basic block as the store, there is no problem.
1073 If this insn was made by loop, we don't know its
1074 INSN_LUID and hence must make a conservative
1075 assumption. */
1078 || (labels_in_range_p
1082 else
1091 i++)
1093 /* Add M to the end of the chain MOVABLES. */
1095 }
1096 }
1097 }
1098 }
1099 /* Past a call insn, we get to insns which might not be executed
1100 because the call might exit. This matters for insns that trap.
1101 Constant and pure call insns always return, so they don't count. */
1104 /* Past a label or a jump, we get to insns for which we
1105 can't count on whether or how many times they will be
1106 executed during each iteration. Therefore, we can
1107 only move out sets of trivial variables
1108 (those not used after the loop). */
1109 /* Similar code appears twice in strength_reduce. */
1111 /* If we enter the loop in the middle, and scan around to the
1112 beginning, don't set maybe_never for that. This must be an
1113 unconditional jump, otherwise the code at the top of the
1114 loop might never be executed. Unconditional jumps are
1115 followed by a barrier then the loop_end. */
1121 {
1122 /* At the virtual top of a converted loop, insns are again known to
1123 be executed: logically, the loop begins here even though the exit
1124 code has been duplicated. */
1128 loop_depth++;
1130 loop_depth--;
1131 }
1132 }
1134 /* If one movable subsumes another, ignore that other. */
1138 /* For each movable insn, see if the reg that it loads
1139 leads when it dies right into another conditionally movable insn.
1140 If so, record that the second insn "forces" the first one,
1141 since the second can be moved only if the first is. */
1145 /* See if there are multiple movable insns that load the same value.
1146 If there are, make all but the first point at the first one
1147 through the `match' field, and add the priorities of them
1148 all together as the priority of the first. */
1152 /* Now consider each movable insn to decide whether it is worth moving.
1153 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1155 For machines with few registers this increases code size, so do not
1156 move moveables when optimizing for code size on such machines.
1157 (The 18 below is the value for i386.) */
1161 {
1164 /* Recalculate regs->array if move_movables has created new
1165 registers. */
1167 {
1173 ;
1178 }
1179 }
1181 /* Now candidates that still are negative are those not moved.
1182 Change regs->array[I].set_in_loop to indicate that those are not actually
1183 invariant. */
1188 /* Now that we've moved some things out of the loop, we might be able to
1189 hoist even more memory references. */
1192 /* Recalculate regs->array if load_mems has created new registers. */
1200 ;
1207 {
1209 /* Ensure our label doesn't go away. */
1220 }
1223 /* The movable information is required for strength reduction. */
1229 }
1230 \f
1231 /* Add elements to *OUTPUT to record all the pseudo-regs
1232 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1234 void
1236 {
1244 {
1262 }
1266 {
1270 {
1279 }
1280 }
1281 }
1282 \f
1283 /* Check what regs are referred to in the libcall block ending with INSN,
1284 aside from those mentioned in the equivalent value.
1285 If there are none, return 0.
1286 If there are one or more, return an EXPR_LIST containing all of them. */
1288 rtx
1290 {
1295 /* First, find all the regs used in the libcall block
1296 that are not mentioned as inputs to the result. */
1299 {
1304 }
1307 }
1308 \f
1309 /* Return 1 if all uses of REG
1310 are between INSN and the end of the basic block. */
1312 static int
1314 {
1316 rtx p;
1321 /* Search this basic block for the already recorded last use of the reg. */
1323 {
1325 {
1331 /* Ordinary insn: if this is the last use, we win. */
1337 /* Jump insn: if this is the last use, we win. */
1340 /* Otherwise, it's the end of the basic block, so we lose. */
1345 /* It's the end of the basic block, so we lose. */
1350 }
1351 }
1353 /* The "last use" that was recorded can't be found after the first
1354 use. This can happen when the last use was deleted while
1355 processing an inner loop, this inner loop was then completely
1356 unrolled, and the outer loop is always exited after the inner loop,
1357 so that everything after the first use becomes a single basic block. */
1359 }
1360 \f
1361 /* Compute the benefit of eliminating the insns in the block whose
1362 last insn is LAST. This may be a group of insns used to compute a
1363 value directly or can contain a library call. */
1365 static int
1367 {
1368 rtx insn;
1373 {
1376 routine. */
1380 benefit++;
1381 }
1384 }
1385 \f
1386 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1388 static rtx
1390 {
1392 {
1393 rtx temp;
1395 /* If first insn of libcall sequence, skip to end. */
1396 /* Do this at start of loop, since INSN is guaranteed to
1397 be an insn here. */
1402 do
1405 }
1408 }
1410 /* Ignore any movable whose insn falls within a libcall
1411 which is part of another movable.
1412 We make use of the fact that the movable for the libcall value
1413 was made later and so appears later on the chain. */
1415 static void
1417 {
1421 {
1422 /* Is this a movable for the value of a libcall? */
1425 {
1426 rtx insn;
1427 /* Check for earlier movables inside that range,
1428 and mark them invalid. We cannot use LUIDs here because
1429 insns created by loop.c for prior loops don't have LUIDs.
1430 Rather than reject all such insns from movables, we just
1431 explicitly check each insn in the libcall (since invariant
1432 libcalls aren't that common). */
1437 }
1438 }
1439 }
1441 /* For each movable insn, see if the reg that it loads
1442 leads when it dies right into another conditionally movable insn.
1443 If so, record that the second insn "forces" the first one,
1444 since the second can be moved only if the first is. */
1446 static void
1448 {
1452 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1454 {
1457 /* ??? Could this be a bug? What if CSE caused the
1458 register of M1 to be used after this insn?
1459 Since CSE does not update regno_last_uid,
1460 this insn M->insn might not be where it dies.
1461 But very likely this doesn't matter; what matters is
1462 that M's reg is computed from M1's reg. */
1467 /* If m->consec, m->set_src isn't valid. */
1471 /* Increase the priority of the moving the first insn
1472 since it permits the second to be moved as well.
1473 Likewise for insns already forced by the first insn. */
1475 {
1480 {
1483 }
1484 }
1485 }
1486 }
1487 \f
1488 /* Find invariant expressions that are equal and can be combined into
1489 one register. */
1491 static void
1493 {
1498 /* Regs that are set more than once are not allowed to match
1499 or be matched. I'm no longer sure why not. */
1500 /* Only pseudo registers are allowed to match or be matched,
1501 since move_movables does not validate the change. */
1502 /* Perhaps testing m->consec_sets would be more appropriate here? */
1509 {
1516 /* We want later insns to match the first one. Don't make the first
1517 one match any later ones. So start this loop at m->next. */
1523 /* A reg used outside the loop mustn't be eliminated. */
1525 /* A reg used for zero-extending mustn't be eliminated. */
1528 ||
1529 (
1530 /* Can combine regs with different modes loaded from the
1531 same constant only if the modes are the same or
1532 if both are integer modes with M wider or the same
1533 width as M1. The check for integer is redundant, but
1534 safe, since the only case of differing destination
1535 modes with equal sources is when both sources are
1536 VOIDmode, i.e., CONST_INT. */
1542 /* See if the source of M1 says it matches M. */
1549 {
1555 }
1556 }
1558 /* Now combine the regs used for zero-extension.
1559 This can be done for those not marked `global'
1560 provided their lives don't overlap. */
1564 {
1567 /* Combine all the registers for extension from mode MODE.
1568 Don't combine any that are used outside this loop. */
1572 {
1579 {
1580 /* First one: don't check for overlap, just record it. */
1583 }
1585 /* Make sure they extend to the same mode.
1586 (Almost always true.) */
1590 /* We already have one: check for overlap with those
1591 already combined together. */
1598 /* No overlap: we can combine this with the others. */
1604 overlap:
1605 ;
1606 }
1607 }
1609 /* Clean up. */
1611 }
1613 /* Returns the number of movable instructions in LOOP that were not
1614 moved outside the loop. */
1616 static int
1618 {
1627 }
1629 \f
1630 /* Return 1 if regs X and Y will become the same if moved. */
1632 static int
1634 {
1651 }
1653 /* Return 1 if X and Y are identical-looking rtx's.
1654 This is the Lisp function EQUAL for rtx arguments.
1656 If two registers are matching movables or a movable register and an
1657 equivalent constant, consider them equal. */
1659 static int
1662 {
1676 /* If we have a register and a constant, they may sometimes be
1677 equal. */
1680 {
1685 }
1688 {
1693 }
1695 /* Otherwise, rtx's of different codes cannot be equal. */
1699 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1700 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1705 /* These three types of rtx's can be compared nonrecursively. */
1714 /* Compare the elements. If any pair of corresponding elements
1715 fail to match, return 0 for the whole things. */
1719 {
1721 {
1733 /* Two vectors must have the same length. */
1737 /* And the corresponding elements must match. */
1756 /* These are just backpointers, so they don't matter. */
1762 /* It is believed that rtx's at this level will never
1763 contain anything but integers and other rtx's,
1764 except for within LABEL_REFs and SYMBOL_REFs. */
1767 }
1768 }
1770 }
1771 \f
1772 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1773 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1774 references is incremented once for each added note. */
1776 static void
1778 {
1782 rtx insn;
1785 {
1786 /* This code used to ignore labels that referred to dispatch tables to
1787 avoid flow generating (slightly) worse code.
1789 We no longer ignore such label references (see LABEL_REF handling in
1790 mark_jump_label for additional information). */
1793 {
1798 }
1799 }
1803 {
1809 }
1810 }
1811 \f
1812 /* Scan MOVABLES, and move the insns that deserve to be moved.
1813 If two matching movables are combined, replace one reg with the
1814 other throughout. */
1816 static void
1819 {
1824 rtx p;
1827 /* Map of pseudo-register replacements to handle combining
1828 when we move several insns that load the same value
1829 into different pseudo-registers. */
1834 {
1835 /* Describe this movable insn. */
1838 {
1859 }
1861 /* Ignore the insn if it's already done (it matched something else).
1862 Otherwise, see if it is now safe to move. */
1874 {
1876 rtx p;
1879 /* We have an insn that is safe to move.
1880 Compute its desirability. */
1891 /* An insn MUST be moved if we already moved something else
1892 which is safe only if this one is moved too: that is,
1893 if already_moved[REGNO] is nonzero. */
1895 /* An insn is desirable to move if the new lifetime of the
1896 register is no more than THRESHOLD times the old lifetime.
1897 If it's not desirable, it means the loop is so big
1898 that moving won't speed things up much,
1899 and it is liable to make register usage worse. */
1901 /* It is also desirable to move if it can be moved at no
1902 extra cost because something else was already moved. */
1905 || flag_move_all_movables
1910 {
1919 /* Now move the insns that set the reg. */
1922 {
1925 /* Find the end of this chain of matching regs.
1926 Thus, we load each reg in the chain from that one reg.
1927 And that reg is loaded with 0 directly,
1928 since it has ->match == 0. */
1934 /* Mark the moved, invariant reg as being allowed to
1935 share a hard reg with the other matching invariant. */
1939 regs_may_share
1942 regs_may_share));
1950 }
1951 /* If we are to re-generate the item being moved with a
1952 new move insn, first delete what we have and then emit
1953 the move insn before the loop. */
1955 {
1959 {
1960 /* If this is the first insn of a library call sequence,
1961 something is very wrong. */
1966 /* If this is the last insn of a libcall sequence, then
1967 delete every insn in the sequence except the last.
1968 The last insn is handled in the normal manner. */
1971 {
1975 }
1980 /* simplify_giv_expr expects that it can walk the insns
1981 at m->insn forwards and see this old sequence we are
1982 tossing here. delete_insn does preserve the next
1983 pointers, but when we skip over a NOTE we must fix
1984 it up. Otherwise that code walks into the non-deleted
1985 insn stream. */
1990 {
1991 /* Replace the original insn with a move from
1992 our newly created temp. */
1998 }
1999 }
2018 /* The more regs we move, the less we like moving them. */
2020 }
2021 else
2022 {
2024 {
2027 /* If first insn of libcall sequence, skip to end. */
2028 /* Do this at start of loop, since p is guaranteed to
2029 be an insn here. */
2034 /* If last insn of libcall sequence, move all
2035 insns except the last before the loop. The last
2036 insn is handled in the normal manner. */
2039 {
2047 {
2048 rtx body;
2049 rtx n;
2050 rtx next;
2057 /* Find the next insn after TEMP,
2058 not counting USE or NOTE insns. */
2066 /* If that is the call, this may be the insn
2067 that loads the function address.
2069 Extract the function address from the insn
2070 that loads it into a register.
2071 If this insn was cse'd, we get incorrect code.
2073 So emit a new move insn that copies the
2074 function address into the register that the
2075 call insn will use. flow.c will delete any
2076 redundant stores that we have created. */
2081 NULL_RTX)))
2082 {
2088 }
2089 /* We have the call insn.
2090 If it uses the register we suspect it might,
2091 load it with the correct address directly. */
2096 gen_move_insn
2100 {
2102 /* Because the USAGE information potentially
2103 contains objects other than hard registers
2104 we need to copy it. */
2108 }
2109 else
2118 }
2121 }
2123 {
2124 /* P sets REG to zero; but we should clear only
2125 the bits that are not covered by the mode
2126 m->savemode. */
2128 rtx sequence;
2129 rtx tem;
2132 tem = expand_simple_binop
2145 }
2147 {
2149 /* Because the USAGE information potentially
2150 contains objects other than hard registers
2151 we need to copy it. */
2155 }
2157 {
2158 rtx seq;
2159 /* The SET_SRC might not be invariant, so we must
2160 use the REG_EQUAL note. */
2173 }
2175 {
2183 }
2184 else
2188 {
2192 /* If there is a REG_EQUAL note present whose value
2193 is not loop invariant, then delete it, since it
2194 may cause problems with later optimization passes.
2195 It is possible for cse to create such notes
2196 like this as a result of record_jump_cond. */
2201 }
2210 /* If library call, now fix the REG_NOTES that contain
2211 insn pointers, namely REG_LIBCALL on FIRST
2212 and REG_RETVAL on I1. */
2214 {
2218 }
2224 /* simplify_giv_expr expects that it can walk the insns
2225 at m->insn forwards and see this old sequence we are
2226 tossing here. delete_insn does preserve the next
2227 pointers, but when we skip over a NOTE we must fix
2228 it up. Otherwise that code walks into the non-deleted
2229 insn stream. */
2234 {
2235 rtx seq;
2236 /* Replace the original insn with a move from
2237 our newly created temp. */
2243 }
2244 }
2246 /* The more regs we move, the less we like moving them. */
2248 }
2253 {
2254 /* Any other movable that loads the same register
2255 MUST be moved. */
2258 /* This reg has been moved out of one loop. */
2261 /* The reg set here is now invariant. */
2263 {
2267 }
2269 /* Change the length-of-life info for the register
2270 to say it lives at least the full length of this loop.
2271 This will help guide optimizations in outer loops. */
2274 /* This is the old insn before all the moved insns.
2275 We can't use the moved insn because it is out of range
2276 in uid_luid. Only the old insns have luids. */
2280 }
2282 /* Combine with this moved insn any other matching movables. */
2287 {
2288 rtx temp;
2290 /* Schedule the reg loaded by M1
2291 for replacement so that shares the reg of M.
2292 If the modes differ (only possible in restricted
2293 circumstances, make a SUBREG.
2295 Note this assumes that the target dependent files
2296 treat REG and SUBREG equally, including within
2297 GO_IF_LEGITIMATE_ADDRESS and in all the
2298 predicates since we never verify that replacing the
2299 original register with a SUBREG results in a
2300 recognizable insn. */
2303 else
2308 /* Get rid of the matching insn
2309 and prevent further processing of it. */
2312 /* If library call, delete all insns. */
2314 NULL_RTX)))
2316 else
2319 /* Any other movable that loads the same register
2320 MUST be moved. */
2323 /* The reg merged here is now invariant,
2324 if the reg it matches is invariant. */
2326 {
2330 i++)
2332 }
2333 }
2334 }
2337 }
2343 }
2348 /* Go through all the instructions in the loop, making
2349 all the register substitutions scheduled in REG_MAP. */
2353 {
2357 }
2359 /* Clean up. */
2362 }
2365 static void
2367 {
2370 else
2373 }
2376 static void
2378 {
2383 {
2386 }
2387 }
2388 \f
2389 #if 0
2390 /* Scan X and replace the address of any MEM in it with ADDR.
2391 REG is the address that MEM should have before the replacement. */
2393 static void
2395 {
2404 {
2416 /* Short cut for very common case. */
2421 /* Short cut for very common case. */
2426 /* If this MEM uses a reg other than the one we expected,
2427 something is wrong. */
2435 }
2439 {
2443 {
2447 }
2448 }
2449 }
2450 #endif
2451 \f
2452 /* Return the number of memory refs to addresses that vary
2453 in the rtx X. */
2455 static int
2457 {
2468 {
2485 }
2490 {
2494 {
2498 }
2499 }
2501 }
2502 \f
2503 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2504 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2505 `unknown_address_altered', `unknown_constant_address_altered', and
2506 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2507 list `store_mems' in LOOP. */
2509 static void
2511 {
2513 rtx insn;
2517 /* The label after END. Jumping here is just like falling off the
2518 end of the loop. We use next_nonnote_insn instead of next_label
2519 as a hedge against the (pathological) case where some actual insn
2520 might end up between the two. */
2539 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2544 {
2546 {
2549 }
2550 }
2554 {
2556 {
2559 {
2561 /* Count number of loops contained in this one. */
2563 }
2570 {
2573 }
2580 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2581 attached FUNCTION_USAGE expression list, not accounted for by the
2582 code above. We should note these to avoid missing dependencies in
2583 later references. */
2584 {
2585 rtx fusage_entry;
2589 {
2595 {
2600 }
2601 }
2602 }
2607 {
2611 {
2616 {
2619 }
2620 else
2621 {
2624 }
2626 do
2627 {
2629 {
2631 {
2632 /* Something tricky. */
2635 }
2638 {
2639 /* A jump outside the current loop. */
2642 }
2643 }
2647 }
2649 }
2650 else
2651 {
2652 /* A return, or something tricky. */
2654 }
2655 }
2656 /* Fall through. */
2677 }
2678 }
2680 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2682 anywhere. */
2684 /* We don't want loads for MEMs moved to a location before the
2685 one at which their stack memory becomes allocated. (Note
2686 that this is not a problem for malloc, etc., since those
2687 require actual function calls. */
2688 && ! current_function_calls_alloca
2689 /* There are ways to leave the loop other than falling off the
2690 end. */
2696 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2697 that loop_invariant_p and load_mems can use true_dependence
2698 to determine what is really clobbered. */
2700 {
2703 loop_info->store_mems
2705 }
2707 {
2711 loop_info->store_mems
2713 }
2714 }
2715 \f
2716 /* Invalidate all loops containing LABEL. */
2718 static void
2720 {
2724 }
2726 /* Scan the function looking for loops. Record the start and end of each loop.
2727 Also mark as invalid loops any loops that contain a setjmp or are branched
2728 to from outside the loop. */
2730 static void
2732 {
2733 rtx insn;
2734 rtx label;
2744 /* If there are jumps to undefined labels,
2745 treat them as jumps out of any/all loops.
2746 This also avoids writing past end of tables when there are no loops. */
2749 /* Find boundaries of loops, mark which loops are contained within
2750 loops, and invalidate loops that have setjmp. */
2755 {
2758 {
2762 num_loops++;
2786 }
2790 {
2791 /* In this case, we must invalidate our current loop and any
2792 enclosing loop. */
2794 {
2800 }
2801 }
2803 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2804 enclosing loop, but this doesn't matter. */
2806 }
2808 /* Any loop containing a label used in an initializer must be invalidated,
2809 because it can be jumped into from anywhere. */
2813 /* Any loop containing a label used for an exception handler must be
2814 invalidated, because it can be jumped into from anywhere. */
2817 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2818 loop that it is not contained within, that loop is marked invalid.
2819 If any INSN or CALL_INSN uses a label's address, then the loop containing
2820 that label is marked invalid, because it could be jumped into from
2821 anywhere.
2823 Also look for blocks of code ending in an unconditional branch that
2824 exits the loop. If such a block is surrounded by a conditional
2825 branch around the block, move the block elsewhere (see below) and
2826 invert the jump to point to the code block. This may eliminate a
2827 label in our loop and will simplify processing by both us and a
2828 possible second cse pass. */
2832 {
2836 {
2840 }
2847 /* See if this is an unconditional branch outside the loop. */
2855 {
2856 rtx p;
2862 /* Go backwards until we reach the start of the loop, a label,
2863 or a JUMP_INSN. */
2870 ;
2872 /* Check for the case where we have a jump to an inner nested
2873 loop, and do not perform the optimization in that case. */
2876 {
2879 {
2884 }
2885 }
2887 /* Make sure that the target of P is within the current loop. */
2893 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2894 we have a block of code to try to move.
2896 We look backward and then forward from the target of INSN
2897 to find a BARRIER at the same loop depth as the target.
2898 If we find such a BARRIER, we make a new label for the start
2899 of the block, invert the jump in P and point it to that label,
2900 and move the block of code to the spot we found. */
2905 /* Just ignore jumps to labels that were never emitted.
2906 These always indicate compilation errors. */
2910 /* If it's not safe to move the sequence, then we
2911 mustn't try. */
2914 {
2915 rtx target
2919 rtx tmp;
2921 /* Search for possible garbage past the conditional jumps
2922 and look for the last barrier. */
2930 /* Don't move things inside a tablejump. */
2943 /* Don't move things inside a tablejump. */
2954 {
2958 /* Ensure our label doesn't go away. */
2961 /* Verify that uid_loop is large enough and that
2962 we can invert P. */
2964 {
2967 /* If no suitable BARRIER was found, create a suitable
2968 one before TARGET. Since TARGET is a fall through
2969 path, we'll need to insert a jump around our block
2970 and add a BARRIER before TARGET.
2972 This creates an extra unconditional jump outside
2973 the loop. However, the benefits of removing rarely
2974 executed instructions from inside the loop usually
2975 outweighs the cost of the extra unconditional jump
2976 outside the loop. */
2978 {
2979 rtx temp;
2986 }
2988 /* Include the BARRIER after INSN and copy the
2989 block after LOC. */
2994 /* All those insns are now in TARGET_LOOP. */
3000 /* The label jumped to by INSN is no longer a loop
3001 exit. Unless INSN does not have a label (e.g.,
3002 it is a RETURN insn), search loop->exit_labels
3003 to find its label_ref, and remove it. Also turn
3004 off LABEL_OUTSIDE_LOOP_P bit. */
3006 {
3008 r;
3011 {
3015 else
3018 }
3024 /* If we didn't find it, then something is
3025 wrong. */
3028 }
3030 /* P is now a jump outside the loop, so it must be put
3031 in loop->exit_labels, and marked as such.
3032 The easiest way to do this is to just call
3033 mark_loop_jump again for P. */
3036 /* If INSN now jumps to the insn after it,
3037 delete INSN. */
3042 }
3044 /* Continue the loop after where the conditional
3045 branch used to jump, since the only branch insn
3046 in the block (if it still remains) is an inter-loop
3047 branch and hence needs no processing. */
3053 /* This loop will be continued with NEXT_INSN (insn). */
3055 }
3056 }
3057 }
3058 }
3059 }
3061 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3062 loops it is contained in, mark the target loop invalid.
3064 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3066 static void
3068 {
3074 {
3086 /* There could be a label reference in here. */
3098 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3110 /* Link together all labels that branch outside the loop. This
3111 is used by final_[bg]iv_value and the loop unrolling code. Also
3112 mark this LABEL_REF so we know that this branch should predict
3113 false. */
3115 /* A check to make sure the label is not in an inner nested loop,
3116 since this does not count as a loop exit. */
3118 {
3123 }
3124 else
3128 {
3137 }
3139 /* If this is inside a loop, but not in the current loop or one enclosed
3140 by it, it invalidates at least one loop. */
3145 /* We must invalidate every nested loop containing the target of this
3146 label, except those that also contain the jump insn. */
3149 {
3150 /* Stop when we reach a loop that also contains the jump insn. */
3155 /* If we get here, we know we need to invalidate a loop. */
3162 }
3166 /* If this is not setting pc, ignore. */
3188 /* Strictly speaking this is not a jump into the loop, only a possible
3189 jump out of the loop. However, we have no way to link the destination
3190 of this jump onto the list of exit labels. To be safe we mark this
3191 loop and any containing loops as invalid. */
3193 {
3195 {
3201 }
3202 }
3204 }
3205 }
3206 \f
3207 /* Return nonzero if there is a label in the range from
3208 insn INSN to and including the insn whose luid is END
3209 INSN must have an assigned luid (i.e., it must not have
3210 been previously created by loop.c). */
3212 static int
3214 {
3216 {
3220 }
3223 }
3225 /* Record that a memory reference X is being set. */
3227 static void
3230 {
3236 /* Count number of memory writes.
3237 This affects heuristics in strength_reduce. */
3240 /* BLKmode MEM means all memory is clobbered. */
3242 {
3245 else
3249 }
3253 }
3255 /* X is a value modified by an INSN that references a biv inside a loop
3256 exit test (ie, X is somehow related to the value of the biv). If X
3257 is a pseudo that is used more than once, then the biv is (effectively)
3258 used more than once. DATA is a pointer to a loop_regs structure. */
3260 static void
3262 {
3277 /* If we do not have usage information, or if we know the register
3278 is used more than once, note that fact for check_dbra_loop. */
3283 }
3284 \f
3285 /* Return nonzero if the rtx X is invariant over the current loop.
3287 The value is 2 if we refer to something only conditionally invariant.
3289 A memory ref is invariant if it is not volatile and does not conflict
3290 with anything stored in `loop_info->store_mems'. */
3292 int
3294 {
3301 rtx mem_list_entry;
3307 {
3315 /* A LABEL_REF is normally invariant, however, if we are unrolling
3316 loops, and this label is inside the loop, then it isn't invariant.
3317 This is because each unrolled copy of the loop body will have
3318 a copy of this label. If this was invariant, then an insn loading
3319 the address of this label into a register might get moved outside
3320 the loop, and then each loop body would end up using the same label.
3322 We don't know the loop bounds here though, so just fail for all
3323 labels. */
3326 else
3335 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3336 since the reg might be set by initialization within the loop. */
3347 /* Out-of-range regs can occur when we are called from unrolling.
3348 These registers created by the unroller are set in the loop,
3349 hence are never invariant.
3350 Other out-of-range regs can be generated by load_mems; those that
3351 are written to in the loop are not invariant, while those that are
3352 not written to are invariant. It would be easy for load_mems
3353 to set n_times_set correctly for these registers, however, there
3354 is no easy way to distinguish them from registers created by the
3355 unroller. */
3366 /* Volatile memory references must be rejected. Do this before
3367 checking for read-only items, so that volatile read-only items
3368 will be rejected also. */
3372 /* See if there is any dependence between a store and this load. */
3375 {
3381 }
3383 /* It's not invalidated by a store in memory
3384 but we must still verify the address is invariant. */
3388 /* Don't mess with insns declared volatile. */
3395 }
3399 {
3401 {
3407 }
3409 {
3412 {
3418 }
3420 }
3421 }
3424 }
3425 \f
3426 /* Return nonzero if all the insns in the loop that set REG
3427 are INSN and the immediately following insns,
3428 and if each of those insns sets REG in an invariant way
3429 (not counting uses of REG in them).
3431 The value is 2 if some of these insns are only conditionally invariant.
3433 We assume that INSN itself is the first set of REG
3434 and that its source is invariant. */
3436 static int
3438 rtx insn)
3439 {
3443 rtx temp;
3444 /* Number of sets we have to insist on finding after INSN. */
3450 /* If N_SETS hit the limit, we can't rely on its value. */
3457 {
3459 rtx set;
3464 /* If library call, skip to end of it. */
3473 {
3478 {
3479 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3480 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3481 notes are OK. */
3487 }
3488 }
3490 count--;
3492 {
3495 }
3496 }
3499 /* If loop_invariant_p ever returned 2, we return 2. */
3501 }
3502 \f
3503 /* Look at all uses (not sets) of registers in X. For each, if it is
3504 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3505 a different insn, set USAGE[REGNO] to const0_rtx. */
3507 static void
3509 {
3521 {
3522 /* Don't count SET_DEST if it is a REG; otherwise count things
3523 in SET_DEST because if a register is partially modified, it won't
3524 show up as a potential movable so we don't care how USAGE is set
3525 for it. */
3529 }
3530 else
3532 {
3538 }
3539 }
3540 \f
3541 /* Count and record any set in X which is contained in INSN. Update
3542 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3543 in X. */
3545 static void
3547 {
3549 /* Don't move a reg that has an explicit clobber.
3550 It's not worth the pain to try to do it correctly. */
3554 {
3562 {
3566 {
3567 /* If this is the first setting of this reg
3568 in current basic block, and it was set before,
3569 it must be set in two basic blocks, so it cannot
3570 be moved out of the loop. */
3574 /* If this is not first setting in current basic block,
3575 see if reg was used in between previous one and this.
3576 If so, neither one can be moved. */
3583 }
3584 }
3585 }
3586 }
3587 \f
3588 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3589 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3590 contained in insn INSN is used by any insn that precedes INSN in
3591 cyclic order starting from the loop entry point.
3593 We don't want to use INSN_LUID here because if we restrict INSN to those
3594 that have a valid INSN_LUID, it means we cannot move an invariant out
3595 from an inner loop past two loops. */
3597 static int
3599 {
3601 rtx p;
3603 /* Scan forward checking for register usage. If we hit INSN, we
3604 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3606 {
3612 }
3615 }
3616 \f
3618 /* Information we collect about arrays that we might want to prefetch. */
3619 struct prefetch_info
3620 {
3624 index. */
3625 HOST_WIDE_INT index;
3627 iteration. */
3629 prefetch area in one iteration. */
3631 This is set only for loops with known
3632 iteration counts and is 0xffffffff
3633 otherwise. */
3637 };
3639 /* Data used by check_store function. */
3640 struct check_store_data
3641 {
3642 rtx mem_address;
3644 };
3650 /* Set mem_write when mem_address is found. Used as callback to
3651 note_stores. */
3652 static void
3654 {
3659 }
3660 \f
3661 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3662 important to get some addresses combined. Later more sophisticated
3663 transformations can be added when necessary.
3665 ??? Same trick with swapping operand is done at several other places.
3666 It can be nice to develop some common way to handle this. */
3668 static int
3670 {
3684 {
3689 }
3690 /* Compare the elements. If any pair of corresponding elements fails to
3691 match, return 0 for the whole thing. */
3695 {
3697 {
3709 /* Two vectors must have the same length. */
3713 /* And the corresponding elements must match. */
3731 /* These are just backpointers, so they don't matter. */
3737 /* It is believed that rtx's at this level will never
3738 contain anything but integers and other rtx's,
3739 except for within LABEL_REFs and SYMBOL_REFs. */
3742 }
3743 }
3745 }
3746 \f
3747 /* Remove constant addition value from the expression X (when present)
3748 and return it. */
3750 static HOST_WIDE_INT
3752 {
3756 /* Avoid clobbering a shared CONST expression. */
3758 {
3762 {
3765 }
3767 }
3770 {
3773 }
3775 /* For plus expression recurse on ourself. */
3777 {
3781 /* In case our parameter was constant, remove extra zero from the
3782 expression. */
3787 }
3790 }
3792 /* Attempt to identify accesses to arrays that are most likely to cause cache
3793 misses, and emit prefetch instructions a few prefetch blocks forward.
3795 To detect the arrays we use the GIV information that was collected by the
3796 strength reduction pass.
3798 The prefetch instructions are generated after the GIV information is done
3799 and before the strength reduction process. The new GIVs are injected into
3800 the strength reduction tables, so the prefetch addresses are optimized as
3801 well.
3803 GIVs are split into base address, stride, and constant addition values.
3804 GIVs with the same address, stride and close addition values are combined
3805 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3806 for write instructions can be used for the block we write to, on machines
3807 that support write prefetches.
3809 Several heuristics are used to determine when to prefetch. They are
3810 controlled by defined symbols that can be overridden for each target. */
3812 static void
3814 {
3830 /* Consider only loops w/o calls. When a call is done, the loop is probably
3831 slow enough to read the memory. */
3833 {
3838 }
3840 /* Don't prefetch in loops known to have few iterations. */
3844 {
3849 }
3851 /* Search all induction variables and pick those interesting for the prefetch
3852 machinery. */
3854 {
3860 /* Expect all BIVs to be executed in each iteration. This makes our
3861 analysis more conservative. */
3863 {
3864 /* Discard non-constant additions that we can't handle well yet, and
3865 BIVs that are executed multiple times; such BIVs ought to be
3866 handled in the nested loop. We accept not_every_iteration BIVs,
3867 since these only result in larger strides and make our
3868 heuristics more conservative. */
3870 {
3872 {
3878 }
3880 }
3883 {
3885 {
3891 }
3893 }
3897 }
3903 {
3904 rtx address;
3905 rtx temp;
3914 /* See whether an induction variable is interesting to us and if
3915 not, report the reason. */
3919 /* We are interested only in constant stride memory references
3920 in order to be able to compute density easily. */
3924 else
3925 {
3928 {
3931 }
3933 /* On some targets, reversed order prefetches are not
3934 worthwhile. */
3938 /* Prefetch of accesses with an extreme stride might not be
3939 worthwhile, either. */
3944 /* Ignore GIVs with varying add values; we can't predict the
3945 value for the next iteration. */
3949 /* Ignore GIVs in the nested loops; they ought to have been
3950 handled already. */
3953 }
3956 {
3962 }
3964 /* Determine the pointer to the basic array we are examining. It is
3965 the sum of the BIV's initial value and the GIV's add_val. */
3975 /* When the GIV is not always executed, we might be better off by
3976 not dirtying the cache pages. */
3979 else
3980 {
3985 }
3987 /* Attempt to find another prefetch to the same array and see if we
3988 can merge this one. */
3992 {
3993 /* In case both access same array (same location
3994 just with small difference in constant indexes), merge
3995 the prefetches. Just do the later and the earlier will
3996 get prefetched from previous iteration.
3997 The artificial threshold should not be too small,
3998 but also not bigger than small portion of memory usually
3999 traversed by single loop. */
4002 {
4011 }
4015 {
4020 }
4021 }
4023 /* Merging failed. */
4025 {
4033 num_prefetches++;
4035 {
4040 }
4041 }
4042 }
4043 }
4046 {
4049 /* Attempt to calculate the total number of bytes fetched by all
4050 iterations of the loop. Avoid overflow. */
4055 else
4060 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4065 {
4070 }
4071 else
4072 {
4078 }
4079 else
4082 /* Find how many prefetch instructions we'll use within the loop. */
4084 {
4090 }
4091 }
4093 /* Determine how many iterations ahead to prefetch within the loop, based
4094 on how many prefetches we currently expect to do within the loop. */
4096 {
4098 {
4104 }
4105 }
4106 /* We'll also use AHEAD to determine how many prefetch instructions to
4107 emit before a loop, so don't leave it zero. */
4112 {
4113 /* Update if we've decided not to prefetch anything within the loop. */
4117 /* Find how many prefetch instructions we'll use before the loop. */
4119 {
4127 }
4130 {
4150 }
4151 }
4154 {
4155 /* Record that this loop uses prefetch instructions. */
4159 {
4164 }
4165 }
4168 {
4172 {
4174 rtx insn;
4178 rtx seq;
4180 /* We can save some effort by offsetting the address on
4181 architectures with offsettable memory references. */
4184 else
4185 {
4191 }
4194 /* Make sure the address operand is valid for prefetch. */
4204 /* Check all insns emitted and record the new GIV
4205 information. */
4208 {
4213 }
4214 }
4217 {
4218 /* Emit insns before the loop to fetch the first cache lines or,
4219 if we're not prefetching within the loop, everything we expect
4220 to need. */
4222 {
4230 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4231 non-constant INIT_VAL to have the same mode as REG, which
4232 in this case we know to be Pmode. */
4234 {
4235 rtx seq;
4242 }
4248 loop_start);
4249 }
4250 }
4251 }
4254 }
4255 \f
4256 /* Communication with routines called via `note_stores'. */
4260 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4264 /* ??? Unfinished optimizations, and possible future optimizations,
4265 for the strength reduction code. */
4267 /* ??? The interaction of biv elimination, and recognition of 'constant'
4268 bivs, may cause problems. */
4270 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4271 performance problems.
4273 Perhaps don't eliminate things that can be combined with an addressing
4274 mode. Find all givs that have the same biv, mult_val, and add_val;
4275 then for each giv, check to see if its only use dies in a following
4276 memory address. If so, generate a new memory address and check to see
4277 if it is valid. If it is valid, then store the modified memory address,
4278 otherwise, mark the giv as not done so that it will get its own iv. */
4280 /* ??? Could try to optimize branches when it is known that a biv is always
4281 positive. */
4283 /* ??? When replace a biv in a compare insn, we should replace with closest
4284 giv so that an optimized branch can still be recognized by the combiner,
4285 e.g. the VAX acb insn. */
4287 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4288 was rerun in loop_optimize whenever a register was added or moved.
4289 Also, some of the optimizations could be a little less conservative. */
4290 \f
4291 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4292 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4293 callback.
4295 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4296 least once for every loop iteration except for the last one.
4298 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4299 loop iteration.
4300 */
4301 void
4303 {
4308 rtx p;
4310 /* If loop_scan_start points to the loop exit test, we have to be wary of
4311 subversive use of gotos inside expression statements. */
4315 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4319 {
4322 /* Past CODE_LABEL, we get to insns that may be executed multiple
4323 times. The only way we can be sure that they can't is if every
4324 jump insn between here and the end of the loop either
4325 returns, exits the loop, is a jump to a location that is still
4326 behind the label, or is a jump to the loop start. */
4329 {
4335 {
4340 {
4343 else
4347 }
4355 {
4358 }
4359 }
4360 }
4362 /* Past a jump, we get to insns for which we can't count
4363 on whether they will be executed during each iteration. */
4364 /* This code appears twice in strength_reduce. There is also similar
4365 code in scan_loop. */
4367 /* If we enter the loop in the middle, and scan around to the
4368 beginning, don't set not_every_iteration for that.
4369 This can be any kind of jump, since we want to know if insns
4370 will be executed if the loop is executed. */
4375 {
4378 /* If this is a jump outside the loop, then it also doesn't
4379 matter. Check to see if the target of this branch is on the
4380 loop->exits_labels list. */
4388 }
4391 {
4392 /* At the virtual top of a converted loop, insns are again known to
4393 be executed each iteration: logically, the loop begins here
4394 even though the exit code has been duplicated.
4396 Insns are also again known to be executed each iteration at
4397 the LOOP_CONT note. */
4403 loop_depth++;
4405 loop_depth--;
4406 }
4408 /* Note if we pass a loop latch. If we do, then we can not clear
4409 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4410 a loop since a jump before the last CODE_LABEL may have started
4411 a new loop iteration.
4413 Note that LOOP_TOP is only set for rotated loops and we need
4414 this check for all loops, so compare against the CODE_LABEL
4415 which immediately follows LOOP_START. */
4420 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4421 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4422 or not an insn is known to be executed each iteration of the
4423 loop, whether or not any iterations are known to occur.
4425 Therefore, if we have just passed a label and have no more labels
4426 between here and the test insn of the loop, and we have not passed
4427 a jump to the top of the loop, then we know these insns will be
4428 executed each iteration. */
4431 && !past_loop_latch
4436 }
4437 }
4438 \f
4439 static void
4441 {
4444 /* Temporary list pointers for traversing ivs->list. */
4451 /* Scan ivs->list to remove all regs that proved not to be bivs.
4452 Make a sanity check against regs->n_times_set. */
4454 {
4456 /* Above happens if register modified by subreg, etc. */
4457 /* Make sure it is not recognized as a basic induction var: */
4459 /* If never incremented, it is invariant that we decided not to
4460 move. So leave it alone. */
4462 {
4473 }
4474 else
4475 {
4480 }
4481 }
4482 }
4485 /* Determine how BIVS are initialized by looking through pre-header
4486 extended basic block. */
4487 static void
4489 {
4491 /* Temporary list pointers for traversing ivs->list. */
4494 rtx p;
4496 /* Find initial value for each biv by searching backwards from loop_start,
4497 halting at first label. Also record any test condition. */
4501 {
4502 rtx test;
4512 /* Record any test of a biv that branches around the loop if no store
4513 between it and the start of loop. We only care about tests with
4514 constants and registers and only certain of those. */
4524 {
4525 /* If an NE test, we have an initial value! */
4527 {
4531 }
4532 else
4534 }
4535 }
4536 }
4539 /* Look at the each biv and see if we can say anything better about its
4540 initial value from any initializing insns set up above. (This is done
4541 in two passes to avoid missing SETs in a PARALLEL.) */
4542 static void
4544 {
4546 /* Temporary list pointers for traversing ivs->list. */
4551 {
4552 rtx src;
4553 rtx note;
4558 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4559 is a constant, use the value of that. */
4565 else
4578 {
4582 {
4585 }
4586 }
4587 /* If we can't make it a giv,
4588 let biv keep initial value of "itself". */
4591 }
4592 }
4595 /* Search the loop for general induction variables. */
4597 static void
4599 {
4601 }
4604 /* For each giv for which we still don't know whether or not it is
4605 replaceable, check to see if it is replaceable because its final value
4606 can be calculated. */
4608 static void
4610 {
4615 {
4621 }
4622 }
4625 /* Return nonzero if it is possible to eliminate the biv BL provided
4626 all givs are reduced. This is possible if either the reg is not
4627 used outside the loop, or we can compute what its final value will
4628 be. */
4630 static int
4633 {
4634 /* For architectures with a decrement_and_branch_until_zero insn,
4635 don't do this if we put a REG_NONNEG note on the endtest for this
4636 biv. */
4638 #ifdef HAVE_decrement_and_branch_until_zero
4640 {
4645 }
4646 #endif
4648 /* Check that biv is used outside loop or if it has a final value.
4649 Compare against bl->init_insn rather than loop->start. We aren't
4650 concerned with any uses of the biv between init_insn and
4651 loop->start since these won't be affected by the value of the biv
4652 elsewhere in the function, so long as init_insn doesn't use the
4653 biv itself. */
4664 {
4672 }
4674 }
4677 /* Reduce each giv of BL that we have decided to reduce. */
4679 static void
4681 {
4685 {
4688 {
4691 /* If the code for derived givs immediately below has already
4692 allocated a new_reg, we must keep it. */
4696 #ifdef AUTO_INC_DEC
4697 /* If the target has auto-increment addressing modes, and
4698 this is an address giv, then try to put the increment
4699 immediately after its use, so that flow can create an
4700 auto-increment addressing mode. */
4703 /* We don't handle reversed biv's because bl->biv->insn
4704 does not have a valid INSN_LUID. */
4708 {
4709 /* If other giv's have been combined with this one, then
4710 this will work only if all uses of the other giv's occur
4711 before this giv's insn. This is difficult to check.
4713 We simplify this by looking for the common case where
4714 there is one DEST_REG giv, and this giv's insn is the
4715 last use of the dest_reg of that DEST_REG giv. If the
4716 increment occurs after the address giv, then we can
4717 perform the optimization. (Otherwise, the increment
4718 would have to go before other_giv, and we would not be
4719 able to combine it with the address giv to get an
4720 auto-inc address.) */
4722 {
4727 {
4730 else
4732 }
4739 }
4740 /* Check for case where increment is before the address
4741 giv. Do this test in "loop order". */
4750 else
4753 #ifdef HAVE_cc0
4754 {
4755 rtx prev;
4757 /* We can't put an insn immediately after one setting
4758 cc0, or immediately before one using cc0. */
4765 }
4766 #endif
4770 }
4771 #endif
4773 /* For each place where the biv is incremented, add an insn
4774 to increment the new, reduced reg for the giv. */
4776 {
4777 rtx insert_before;
4779 /* Skip if location is the same as a previous one. */
4786 else
4794 /* A multiply is acceptable here
4795 since this is presumed to be seldom executed. */
4799 }
4801 /* Add code at loop start to initialize giv's reduced reg. */
4806 }
4807 }
4808 }
4811 /* Check for givs whose first use is their definition and whose
4812 last use is the definition of another giv. If so, it is likely
4813 dead and should not be used to derive another giv nor to
4814 eliminate a biv. */
4816 static void
4818 {
4822 {
4829 {
4835 }
4836 }
4837 }
4840 static void
4842 {
4846 {
4853 /* Update expression if this was combined, in case other giv was
4854 replaced. */
4859 /* See if this register is known to be a pointer to something. If
4860 so, see if we can find the alignment. First see if there is a
4861 destination register that is a pointer. If so, this shares the
4862 alignment too. Next see if we can deduce anything from the
4863 computational information. If not, and this is a DEST_ADDR
4864 giv, at least we know that it's a pointer, though we don't know
4865 the alignment. */
4873 {
4882 }
4886 {
4894 }
4899 /* Store reduced reg as the address in the memref where we found
4900 this giv. */
4903 {
4905 }
4906 else
4907 {
4909 rtx note;
4911 /* Not replaceable; emit an insn to set the original giv reg from
4912 the reduced giv, same as above. */
4917 /* The original insn may have a REG_EQUAL note. This note is
4918 now incorrect and may result in invalid substitutions later.
4919 The original insn is dead, but may be part of a libcall
4920 sequence, which doesn't seem worth the bother of handling. */
4924 }
4926 /* When a loop is reversed, givs which depend on the reversed
4927 biv, and which are live outside the loop, must be set to their
4928 correct final value. This insn is only needed if the giv is
4929 not replaceable. The correct final value is the same as the
4930 value that the giv starts the reversed loop with. */
4941 {
4946 }
4947 }
4948 }
4951 static int
4954 rtx test_reg)
4955 {
4964 /* Reduce benefit if not replaceable, since we will insert a
4965 move-insn to replace the insn that calculates this giv. Don't do
4966 this unless the giv is a user variable, since it will often be
4967 marked non-replaceable because of the duplication of the exit
4968 code outside the loop. In such a case, the copies we insert are
4969 dead and will be deleted. So they don't have a cost. Similar
4970 situations exist. */
4971 /* ??? The new final_[bg]iv_value code does a much better job of
4972 finding replaceable giv's, and hence this code may no longer be
4973 necessary. */
4978 /* Decrease the benefit to count the add-insns that we will insert
4979 to increment the reduced reg for the giv. ??? This can
4980 overestimate the run-time cost of the additional insns, e.g. if
4981 there are multiple basic blocks that increment the biv, but only
4982 one of these blocks is executed during each iteration. There is
4983 no good way to detect cases like this with the current structure
4984 of the loop optimizer. This code is more accurate for
4985 determining code size than run-time benefits. */
4988 /* Decide whether to strength-reduce this giv or to leave the code
4989 unchanged (recompute it from the biv each time it is used). This
4990 decision can be made independently for each giv. */
4992 #ifdef AUTO_INC_DEC
4993 /* Attempt to guess whether autoincrement will handle some of the
4994 new add insns; if so, increase BENEFIT (undo the subtraction of
4995 add_cost that was done above). */
4997 /* Increasing the benefit is risky, since this is only a guess.
4998 Avoid increasing register pressure in cases where there would
4999 be no other benefit from reducing this giv. */
5002 {
5017 }
5018 #endif
5021 }
5024 /* Free IV structures for LOOP. */
5026 static void
5028 {
5035 {
5041 {
5044 }
5046 {
5049 }
5053 }
5054 }
5057 /* Perform strength reduction and induction variable elimination.
5059 Pseudo registers created during this function will be beyond the
5060 last valid index in several tables including
5061 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5062 problem here, because the added registers cannot be givs outside of
5063 their loop, and hence will never be reconsidered. But scan_loop
5064 must check regnos to make sure they are in bounds. */
5066 static void
5068 {
5072 rtx p;
5073 /* Temporary list pointer for traversing ivs->list. */
5075 /* Ratio of extra register life span we can justify
5076 for saving an instruction. More if loop doesn't call subroutines
5077 since in that case saving an insn makes more difference
5078 and more registers are available. */
5079 /* ??? could set this to last value of threshold in move_movables */
5081 /* Map of pseudo-register replacements. */
5093 /* Find all BIVs in loop. */
5096 /* Exit if there are no bivs. */
5098 {
5099 /* Can still unroll the loop anyways, but indicate that there is no
5100 strength reduction info available. */
5106 }
5108 /* Determine how BIVS are initialized by looking through pre-header
5109 extended basic block. */
5112 /* Look at the each biv and see if we can say anything better about its
5113 initial value from any initializing insns set up above. */
5116 /* Search the loop for general induction variables. */
5119 /* Try to calculate and save the number of loop iterations. This is
5120 set to zero if the actual number can not be calculated. This must
5121 be called after all giv's have been identified, since otherwise it may
5122 fail if the iteration variable is a giv. */
5125 #ifdef HAVE_prefetch
5128 #endif
5130 /* Now for each giv for which we still don't know whether or not it is
5131 replaceable, check to see if it is replaceable because its final value
5132 can be calculated. This must be done after loop_iterations is called,
5133 so that final_giv_value will work correctly. */
5136 /* Try to prove that the loop counter variable (if any) is always
5137 nonnegative; if so, record that fact with a REG_NONNEG note
5138 so that "decrement and branch until zero" insn can be used. */
5141 /* Create reg_map to hold substitutions for replaceable giv regs.
5142 Some givs might have been made from biv increments, so look at
5143 ivs->reg_iv_type for a suitable size. */
5147 /* Examine each iv class for feasibility of strength reduction/induction
5148 variable elimination. */
5151 {
5155 /* Test whether it will be possible to eliminate this biv
5156 provided all givs are reduced. */
5159 /* This will be true at the end, if all givs which depend on this
5160 biv have been strength reduced.
5161 We can't (currently) eliminate the biv unless this is so. */
5164 /* Check each extension dependent giv in this class to see if its
5165 root biv is safe from wrapping in the interior mode. */
5168 /* Combine all giv's for this iv_class. */
5172 {
5180 /* If an insn is not to be strength reduced, then set its ignore
5181 flag, and clear bl->all_reduced. */
5183 /* A giv that depends on a reversed biv must be reduced if it is
5184 used after the loop exit, otherwise, it would have the wrong
5185 value after the loop exit. To make it simple, just reduce all
5186 of such giv's whether or not we know they are used after the loop
5187 exit. */
5192 {
5200 }
5201 else
5202 {
5203 /* Check that we can increment the reduced giv without a
5204 multiply insn. If not, reject it. */
5209 {
5217 }
5218 }
5219 }
5221 /* Check for givs whose first use is their definition and whose
5222 last use is the definition of another giv. If so, it is likely
5223 dead and should not be used to derive another giv nor to
5224 eliminate a biv. */
5227 /* Reduce each giv that we decided to reduce. */
5230 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5231 as not reduced.
5233 For each giv register that can be reduced now: if replaceable,
5234 substitute reduced reg wherever the old giv occurs;
5235 else add new move insn "giv_reg = reduced_reg". */
5238 /* All the givs based on the biv bl have been reduced if they
5239 merit it. */
5241 /* For each giv not marked as maybe dead that has been combined with a
5242 second giv, clear any "maybe dead" mark on that second giv.
5243 v->new_reg will either be or refer to the register of the giv it
5244 combined with.
5246 Doing this clearing avoids problems in biv elimination where
5247 a giv's new_reg is a complex value that can't be put in the
5248 insn but the giv combined with (with a reg as new_reg) is
5249 marked maybe_dead. Since the register will be used in either
5250 case, we'd prefer it be used from the simpler giv. */
5256 /* Try to eliminate the biv, if it is a candidate.
5257 This won't work if ! bl->all_reduced,
5258 since the givs we planned to use might not have been reduced.
5260 We have to be careful that we didn't initially think we could
5261 eliminate this biv because of a giv that we now think may be
5262 dead and shouldn't be used as a biv replacement.
5264 Also, there is the possibility that we may have a giv that looks
5265 like it can be used to eliminate a biv, but the resulting insn
5266 isn't valid. This can happen, for example, on the 88k, where a
5267 JUMP_INSN can compare a register only with zero. Attempts to
5268 replace it with a compare with a constant will fail.
5270 Note that in cases where this call fails, we may have replaced some
5271 of the occurrences of the biv with a giv, but no harm was done in
5272 doing so in the rare cases where it can occur. */
5276 {
5277 /* ?? If we created a new test to bypass the loop entirely,
5278 or otherwise drop straight in, based on this test, then
5279 we might want to rewrite it also. This way some later
5280 pass has more hope of removing the initialization of this
5281 biv entirely. */
5283 /* If final_value != 0, then the biv may be used after loop end
5284 and we must emit an insn to set it just in case.
5286 Reversed bivs already have an insn after the loop setting their
5287 value, so we don't need another one. We can't calculate the
5288 proper final value for such a biv here anyways. */
5297 }
5298 /* See above note wrt final_value. But since we couldn't eliminate
5299 the biv, we must set the value after the loop instead of before. */
5303 }
5305 /* Go through all the instructions in the loop, making all the
5306 register substitutions scheduled in REG_MAP. */
5311 {
5315 }
5318 {
5319 /* When we completely unroll a loop we will likely not need the increment
5320 of the loop BIV and we will not need the conditional branch at the
5321 end of the loop. */
5324 #ifdef HAVE_cc0
5325 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5326 need the comparison before the conditional branch at the end of the
5327 loop. */
5329 #endif
5331 /* We'll need one copy for each loop iteration. */
5334 /* A little slop to account for the ability to remove initialization
5335 code, better CSE, and other secondary benefits of completely
5336 unrolling some loops. */
5339 /* Clamp the value. */
5342 }
5344 /* Unroll loops from within strength reduction so that we can use the
5345 induction variable information that strength_reduce has already
5346 collected. Always unroll loops that would be as small or smaller
5347 unrolled than when rolled. */
5354 #ifdef HAVE_doloop_end
5359 /* In case number of iterations is known, drop branch prediction note
5360 in the branch. Do that only in second loop pass, as loop unrolling
5361 may change the number of iterations performed. */
5363 {
5364 unsigned HOST_WIDE_INT n
5369 }
5377 }
5378 \f
5379 /*Record all basic induction variables calculated in the insn. */
5380 static rtx
5383 {
5385 rtx set;
5386 rtx dest_reg;
5387 rtx inc_val;
5388 rtx mult_val;
5394 {
5399 {
5404 {
5405 /* It is a possible basic induction variable.
5406 Create and initialize an induction structure for it. */
5413 }
5416 }
5417 }
5419 }
5420 \f
5421 /* Record all givs calculated in the insn.
5422 A register is a giv if: it is only set once, it is a function of a
5423 biv and a constant (or invariant), and it is not a biv. */
5424 static rtx
5427 {
5430 rtx set;
5431 /* Look for a general induction variable in a register. */
5436 {
5437 rtx src_reg;
5438 rtx dest_reg;
5439 rtx add_val;
5440 rtx mult_val;
5441 rtx ext_val;
5444 rtx last_consec_insn;
5453 /* Equivalent expression is a giv. */
5458 /* Don't try to handle any regs made by loop optimization.
5459 We have nothing on them in regno_first_uid, etc. */
5461 /* Don't recognize a BASIC_INDUCT_VAR here. */
5463 /* This must be the only place where the register is set. */
5465 /* or all sets must be consecutive and make a giv. */
5470 {
5473 /* If this is a library call, increase benefit. */
5477 /* Skip the consecutive insns, if there are any. */
5485 }
5486 }
5488 /* Look for givs which are memory addresses. */
5491 maybe_multiple);
5493 /* Update the status of whether giv can derive other givs. This can
5494 change when we pass a label or an insn that updates a biv. */
5499 }
5500 \f
5501 /* Return 1 if X is a valid source for an initial value (or as value being
5502 compared against in an initial test).
5504 X must be either a register or constant and must not be clobbered between
5505 the current insn and the start of the loop.
5507 INSN is the insn containing X. */
5509 static int
5511 {
5515 /* Only consider pseudos we know about initialized in insns whose luids
5516 we know. */
5521 /* Don't use call-clobbered registers across a call which clobbers it. On
5522 some machines, don't use any hard registers at all. */
5524 && (SMALL_REGISTER_CLASSES
5528 /* Don't use registers that have been clobbered before the start of the
5529 loop. */
5534 }
5535 \f
5536 /* Scan X for memory refs and check each memory address
5537 as a possible giv. INSN is the insn whose pattern X comes from.
5538 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5539 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5540 more than once in each loop iteration. */
5542 static void
5545 {
5555 {
5571 {
5572 rtx src_reg;
5573 rtx add_val;
5574 rtx mult_val;
5575 rtx ext_val;
5578 /* This code used to disable creating GIVs with mult_val == 1 and
5579 add_val == 0. However, this leads to lost optimizations when
5580 it comes time to combine a set of related DEST_ADDR GIVs, since
5581 this one would not be seen. */
5586 {
5587 /* Found one; record it. */
5595 }
5596 }
5601 }
5603 /* Recursively scan the subexpressions for other mem refs. */
5609 maybe_multiple);
5613 maybe_multiple);
5614 }
5615 \f
5616 /* Fill in the data about one biv update.
5617 V is the `struct induction' in which we record the biv. (It is
5618 allocated by the caller, with alloca.)
5619 INSN is the insn that sets it.
5620 DEST_REG is the biv's reg.
5622 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5623 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5624 being set to INC_VAL.
5626 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5627 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5628 can be executed more than once per iteration. If MAYBE_MULTIPLE
5629 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5630 executed exactly once per iteration. */
5632 static void
5636 {
5653 /* Add this to the reg's iv_class, creating a class
5654 if this is the first incrementation of the reg. */
5658 {
5659 /* Create and initialize new iv_class. */
5669 /* Set initial value to the reg itself. */
5672 /* We haven't seen the initializing insn yet. */
5682 /* Add this class to ivs->list. */
5686 /* Put it in the array of biv register classes. */
5688 }
5689 else
5690 {
5691 /* Check if location is the same as a previous one. */
5695 {
5698 }
5699 }
5701 /* Update IV_CLASS entry for this biv. */
5710 }
5711 \f
5712 /* Fill in the data about one giv.
5713 V is the `struct induction' in which we record the giv. (It is
5714 allocated by the caller, with alloca.)
5715 INSN is the insn that sets it.
5716 BENEFIT estimates the savings from deleting this insn.
5717 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5718 into a register or is used as a memory address.
5720 SRC_REG is the biv reg which the giv is computed from.
5721 DEST_REG is the giv's reg (if the giv is stored in a reg).
5722 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5723 LOCATION points to the place where this giv's value appears in INSN. */
5725 static void
5730 {
5735 rtx temp;
5737 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5738 undo the MULT canonicalization that we performed earlier. */
5768 /* The v->always_computable field is used in update_giv_derive, to
5769 determine whether a giv can be used to derive another giv. For a
5770 DEST_REG giv, INSN computes a new value for the giv, so its value
5771 isn't computable if INSN insn't executed every iteration.
5772 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5773 it does not compute a new value. Hence the value is always computable
5774 regardless of whether INSN is executed each iteration. */
5778 else
5784 {
5787 }
5789 {
5794 /* If the lifetime is zero, it means that this register is
5795 really a dead store. So mark this as a giv that can be
5796 ignored. This will not prevent the biv from being eliminated. */
5802 }
5804 /* Add the giv to the class of givs computed from one biv. */
5808 {
5811 /* Don't count DEST_ADDR. This is supposed to count the number of
5812 insns that calculate givs. */
5816 }
5817 else
5818 /* Fatal error, biv missing for this giv? */
5822 {
5825 }
5826 else
5827 {
5828 /* The giv can be replaced outright by the reduced register only if all
5829 of the following conditions are true:
5830 - the insn that sets the giv is always executed on any iteration
5831 on which the giv is used at all
5832 (there are two ways to deduce this:
5833 either the insn is executed on every iteration,
5834 or all uses follow that insn in the same basic block),
5835 - the giv is not used outside the loop
5836 - no assignments to the biv occur during the giv's lifetime. */
5839 /* Previous line always fails if INSN was moved by loop opt. */
5842 && (! not_every_iteration
5844 {
5845 /* Now check that there are no assignments to the biv within the
5846 giv's lifetime. This requires two separate checks. */
5848 /* Check each biv update, and fail if any are between the first
5849 and last use of the giv.
5851 If this loop contains an inner loop that was unrolled, then
5852 the insn modifying the biv may have been emitted by the loop
5853 unrolling code, and hence does not have a valid luid. Just
5854 mark the biv as not replaceable in this case. It is not very
5855 useful as a biv, because it is used in two different loops.
5856 It is very unlikely that we would be able to optimize the giv
5857 using this biv anyways. */
5862 {
5868 {
5872 }
5873 }
5875 /* If there are any backwards branches that go from after the
5876 biv update to before it, then this giv is not replaceable. */
5880 {
5884 }
5885 }
5886 else
5887 {
5888 /* May still be replaceable, we don't have enough info here to
5889 decide. */
5892 }
5893 }
5895 /* Record whether the add_val contains a const_int, for later use by
5896 combine_givs. */
5897 {
5902 ;
5906 {
5908 {
5913 else
5915 }
5918 }
5919 }
5923 }
5925 /* All this does is determine whether a giv can be made replaceable because
5926 its final value can be calculated. This code can not be part of record_giv
5927 above, because final_giv_value requires that the number of loop iterations
5928 be known, and that can not be accurately calculated until after all givs
5929 have been identified. */
5931 static void
5933 {
5936 /* DEST_ADDR givs will never reach here, because they are always marked
5937 replaceable above in record_giv. */
5939 /* The giv can be replaced outright by the reduced register only if all
5940 of the following conditions are true:
5941 - the insn that sets the giv is always executed on any iteration
5942 on which the giv is used at all
5943 (there are two ways to deduce this:
5944 either the insn is executed on every iteration,
5945 or all uses follow that insn in the same basic block),
5946 - its final value can be calculated (this condition is different
5947 than the one above in record_giv)
5948 - it's not used before the it's set
5949 - no assignments to the biv occur during the giv's lifetime. */
5951 #if 0
5952 /* This is only called now when replaceable is known to be false. */
5953 /* Clear replaceable, so that it won't confuse final_giv_value. */
5955 #endif
5960 {
5963 rtx last_giv_use;
5968 /* When trying to determine whether or not a biv increment occurs
5969 during the lifetime of the giv, we can ignore uses of the variable
5970 outside the loop because final_value is true. Hence we can not
5971 use regno_last_uid and regno_first_uid as above in record_giv. */
5973 /* Search the loop to determine whether any assignments to the
5974 biv occur during the giv's lifetime. Start with the insn
5975 that sets the giv, and search around the loop until we come
5976 back to that insn again.
5978 Also fail if there is a jump within the giv's lifetime that jumps
5979 to somewhere outside the lifetime but still within the loop. This
5980 catches spaghetti code where the execution order is not linear, and
5981 hence the above test fails. Here we assume that the giv lifetime
5982 does not extend from one iteration of the loop to the next, so as
5983 to make the test easier. Since the lifetime isn't known yet,
5984 this requires two loops. See also record_giv above. */
5989 {
5992 {
5995 }
6001 {
6002 /* It is possible for the BIV increment to use the GIV if we
6003 have a cycle. Thus we must be sure to check each insn for
6004 both BIV and GIV uses, and we must check for BIV uses
6005 first. */
6012 {
6014 {
6018 }
6020 }
6021 }
6022 }
6024 /* Now that the lifetime of the giv is known, check for branches
6025 from within the lifetime to outside the lifetime if it is still
6026 replaceable. */
6029 {
6032 {
6045 {
6054 }
6055 }
6056 }
6058 /* If it is replaceable, then save the final value. */
6061 }
6066 }
6067 \f
6068 /* Update the status of whether a giv can derive other givs.
6070 We need to do something special if there is or may be an update to the biv
6071 between the time the giv is defined and the time it is used to derive
6072 another giv.
6074 In addition, a giv that is only conditionally set is not allowed to
6075 derive another giv once a label has been passed.
6077 The cases we look at are when a label or an update to a biv is passed. */
6079 static void
6081 {
6085 rtx tem;
6088 /* Search all IV classes, then all bivs, and finally all givs.
6090 There are three cases we are concerned with. First we have the situation
6091 of a giv that is only updated conditionally. In that case, it may not
6092 derive any givs after a label is passed.
6094 The second case is when a biv update occurs, or may occur, after the
6095 definition of a giv. For certain biv updates (see below) that are
6096 known to occur between the giv definition and use, we can adjust the
6097 giv definition. For others, or when the biv update is conditional,
6098 we must prevent the giv from deriving any other givs. There are two
6099 sub-cases within this case.
6101 If this is a label, we are concerned with any biv update that is done
6102 conditionally, since it may be done after the giv is defined followed by
6103 a branch here (actually, we need to pass both a jump and a label, but
6104 this extra tracking doesn't seem worth it).
6106 If this is a jump, we are concerned about any biv update that may be
6107 executed multiple times. We are actually only concerned about
6108 backward jumps, but it is probably not worth performing the test
6109 on the jump again here.
6111 If this is a biv update, we must adjust the giv status to show that a
6112 subsequent biv update was performed. If this adjustment cannot be done,
6113 the giv cannot derive further givs. */
6119 {
6120 /* Skip if location is the same as a previous one. */
6125 {
6126 /* If cant_derive is already true, there is no point in
6127 checking all of these conditions again. */
6131 /* If this giv is conditionally set and we have passed a label,
6132 it cannot derive anything. */
6136 /* Skip givs that have mult_val == 0, since
6137 they are really invariants. Also skip those that are
6138 replaceable, since we know their lifetime doesn't contain
6139 any biv update. */
6143 /* The only way we can allow this giv to derive another
6144 is if this is a biv increment and we can form the product
6145 of biv->add_val and giv->mult_val. In this case, we will
6146 be able to compute a compensation. */
6148 {
6149 rtx ext_val_dummy;
6160 tem = simplify_giv_expr
6167 else
6169 }
6173 }
6174 }
6175 }
6176 \f
6177 /* Check whether an insn is an increment legitimate for a basic induction var.
6178 X is the source of insn P, or a part of it.
6179 MODE is the mode in which X should be interpreted.
6181 DEST_REG is the putative biv, also the destination of the insn.
6182 We accept patterns of these forms:
6183 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6184 REG = INVARIANT + REG
6186 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6187 store the additive term into *INC_VAL, and store the place where
6188 we found the additive term into *LOCATION.
6190 If X is an assignment of an invariant into DEST_REG, we set
6191 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6193 We also want to detect a BIV when it corresponds to a variable
6194 whose mode was promoted. In that case, an increment
6195 of the variable may be a PLUS that adds a SUBREG of that variable to
6196 an invariant and then sign- or zero-extends the result of the PLUS
6197 into the variable.
6199 Most GIVs in such cases will be in the promoted mode, since that is the
6200 probably the natural computation mode (and almost certainly the mode
6201 used for addresses) on the machine. So we view the pseudo-reg containing
6202 the variable as the BIV, as if it were simply incremented.
6204 Note that treating the entire pseudo as a BIV will result in making
6205 simple increments to any GIVs based on it. However, if the variable
6206 overflows in its declared mode but not its promoted mode, the result will
6207 be incorrect. This is acceptable if the variable is signed, since
6208 overflows in such cases are undefined, but not if it is unsigned, since
6209 those overflows are defined. So we only check for SIGN_EXTEND and
6210 not ZERO_EXTEND.
6212 If we cannot find a biv, we return 0. */
6214 static int
6218 {
6226 {
6232 {
6234 }
6239 {
6241 }
6242 else
6249 /* convert_modes can emit new instructions, e.g. when arg is a loop
6250 invariant MEM and dest_reg has a different mode.
6251 These instructions would be emitted after the end of the function
6252 and then *inc_val would be an uninitialized pseudo.
6253 Detect this and bail in this case.
6254 Other alternatives to solve this can be introducing a convert_modes
6255 variant which is allowed to fail but not allowed to emit new
6256 instructions, emit these instructions before loop start and let
6257 it be garbage collected if *inc_val is never used or saving the
6258 *inc_val initialization sequence generated here and when *inc_val
6259 is going to be actually used, emit it at some suitable place. */
6263 {
6266 }
6274 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6275 handle addition of promoted variables.
6276 ??? The comment at the start of this function is wrong: promoted
6277 variable increments don't look like it says they do. */
6283 /* If this register is assigned in a previous insn, look at its
6284 source, but don't go outside the loop or past a label. */
6286 /* If this sets a register to itself, we would repeat any previous
6287 biv increment if we applied this strategy blindly. */
6293 {
6294 rtx dest;
6295 do
6296 {
6298 }
6327 }
6328 /* Fall through. */
6330 /* Can accept constant setting of biv only when inside inner most loop.
6331 Otherwise, a biv of an inner loop may be incorrectly recognized
6332 as a biv of the outer loop,
6333 causing code to be moved INTO the inner loop. */
6340 /* convert_modes aborts if we try to convert to or from CCmode, so just
6341 exclude that case. It is very unlikely that a condition code value
6342 would be a useful iterator anyways. convert_modes aborts if we try to
6343 convert a float mode to non-float or vice versa too. */
6347 {
6348 /* Possible bug here? Perhaps we don't know the mode of X. */
6352 {
6355 }
6360 }
6361 else
6365 /* Ignore this BIV if signed arithmetic overflow is defined. */
6372 /* Similar, since this can be a sign extension. */
6377 ;
6391 location);
6396 }
6397 }
6398 \f
6399 /* A general induction variable (giv) is any quantity that is a linear
6400 function of a basic induction variable,
6401 i.e. giv = biv * mult_val + add_val.
6402 The coefficients can be any loop invariant quantity.
6403 A giv need not be computed directly from the biv;
6404 it can be computed by way of other givs. */
6406 /* Determine whether X computes a giv.
6407 If it does, return a nonzero value
6408 which is the benefit from eliminating the computation of X;
6409 set *SRC_REG to the register of the biv that it is computed from;
6410 set *ADD_VAL and *MULT_VAL to the coefficients,
6411 such that the value of X is biv * mult + add; */
6413 static int
6418 {
6422 /* If this is an invariant, forget it, it isn't a giv. */
6433 {
6436 /* Since this is now an invariant and wasn't before, it must be a giv
6437 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6438 with. */
6445 /* This is equivalent to a BIV. */
6452 /* Either (plus (biv) (invar)) or
6453 (plus (mult (biv) (invar_1)) (invar_2)). */
6455 {
6458 }
6459 else
6460 {
6463 }
6468 /* ADD_VAL is zero. */
6476 }
6478 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6479 unless they are CONST_INT). */
6487 else
6490 /* Always return true if this is a giv so it will be detected as such,
6491 even if the benefit is zero or negative. This allows elimination
6492 of bivs that might otherwise not be eliminated. */
6494 }
6495 \f
6496 /* Given an expression, X, try to form it as a linear function of a biv.
6497 We will canonicalize it to be of the form
6498 (plus (mult (BIV) (invar_1))
6499 (invar_2))
6500 with possible degeneracies.
6502 The invariant expressions must each be of a form that can be used as a
6503 machine operand. We surround then with a USE rtx (a hack, but localized
6504 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6505 routine; it is the caller's responsibility to strip them.
6507 If no such canonicalization is possible (i.e., two biv's are used or an
6508 expression that is neither invariant nor a biv or giv), this routine
6509 returns 0.
6511 For a nonzero return, the result will have a code of CONST_INT, USE,
6512 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6514 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6519 static rtx
6521 {
6526 rtx tem;
6528 /* If this is not an integer mode, or if we cannot do arithmetic in this
6529 mode, this can't be a giv. */
6536 {
6543 /* Put constant last, CONST_INT last if both constant. */
6551 /* Handle addition of zero, then addition of an invariant. */
6556 {
6559 /* Adding two invariants must result in an invariant, so enclose
6560 addition operation inside a USE and return it. */
6570 else
6579 /* biv + invar or mult + invar. Return sum. */
6583 /* (a + invar_1) + invar_2. Associate. */
6584 return
6590 arg1)),
6595 }
6597 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6598 MULT to reduce cases. */
6604 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6605 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6606 Recurse to associate the second PLUS. */
6611 return
6619 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6635 /* Handle "a - b" as "a + b * (-1)". */
6641 constm1_rtx)),
6650 /* Put constant last, CONST_INT last if both constant. */
6655 /* If second argument is not now constant, not giv. */
6659 /* Handle multiply by 0 or 1. */
6667 {
6669 /* biv * invar. Done. */
6673 /* Product of two constants. */
6677 /* invar * invar is a giv, but attempt to simplify it somehow. */
6683 {
6684 /* (invar_0 * invar_1) * invar_2. Associate. */
6691 arg1)),
6693 }
6694 /* Propagate the MULT expressions to the innermost nodes. */
6696 {
6697 /* (invar_0 + invar_1) * invar_2. Distribute. */
6703 arg1),
6707 arg1)),
6709 }
6713 /* (a * invar_1) * invar_2. Associate. */
6719 arg1)),
6723 /* (a + invar_1) * invar_2. Distribute. */
6728 arg1),
6731 arg1)),
6736 }
6739 /* Shift by constant is multiply by power of two. */
6743 return
6752 /* "-a" is "a * (-1)" */
6758 /* "~a" is "-a - 1". Silly, but easy. */
6762 const1_rtx),
6766 /* Already in proper form for invariant. */
6772 /* Conditionally recognize extensions of simple IVs. After we've
6773 computed loop traversal counts and verified the range of the
6774 source IV, we'll reevaluate this as a GIV. */
6776 {
6779 {
6782 }
6783 }
6787 /* If this is a new register, we can't deal with it. */
6791 /* Check for biv or giv. */
6793 {
6797 {
6800 /* Form expression from giv and add benefit. Ensure this giv
6801 can derive another and subtract any needed adjustment if so. */
6803 /* Increasing the benefit here is risky. The only case in which it
6804 is arguably correct is if this is the only use of V. In other
6805 cases, this will artificially inflate the benefit of the current
6806 giv, and lead to suboptimal code. Thus, it is disabled, since
6807 potentially not reducing an only marginally beneficial giv is
6808 less harmful than reducing many givs that are not really
6809 beneficial. */
6810 {
6814 }
6827 {
6830 }
6831 else
6832 {
6835 }
6837 }
6840 do_default:
6841 /* If it isn't an induction variable, and it is invariant, we
6842 may be able to simplify things further by looking through
6843 the bits we just moved outside the loop. */
6845 {
6851 {
6852 /* Ok, we found a match. Substitute and simplify. */
6854 /* If we match another movable, we must use that, as
6855 this one is going away. */
6860 /* If consec is nonzero, this is a member of a group of
6861 instructions that were moved together. We handle this
6862 case only to the point of seeking to the last insn and
6863 looking for a REG_EQUAL. Fail if we don't find one. */
6865 {
6868 do
6869 {
6871 }
6877 }
6878 else
6879 {
6883 }
6886 {
6887 /* What we are most interested in is pointer
6888 arithmetic on invariants -- only take
6889 patterns we may be able to do something with. */
6895 {
6897 benefit);
6900 }
6905 {
6910 }
6911 }
6913 }
6914 }
6916 }
6918 /* Fall through to general case. */
6920 /* If invariant, return as USE (unless CONST_INT).
6921 Otherwise, not giv. */
6926 {
6935 }
6936 else
6938 }
6939 }
6941 /* This routine folds invariants such that there is only ever one
6942 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6944 static rtx
6946 {
6952 {
6955 }
6958 {
6961 }
6962 else
6963 {
6966 }
6967 }
6969 static rtx
6971 {
6973 {
6977 else
6980 }
6983 else
6986 }
6987 \f
6988 /* Help detect a giv that is calculated by several consecutive insns;
6989 for example,
6990 giv = biv * M
6991 giv = giv + A
6992 The caller has already identified the first insn P as having a giv as dest;
6993 we check that all other insns that set the same register follow
6994 immediately after P, that they alter nothing else,
6995 and that the result of the last is still a giv.
6997 The value is 0 if the reg set in P is not really a giv.
6998 Otherwise, the value is the amount gained by eliminating
6999 all the consecutive insns that compute the value.
7001 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7002 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7004 The coefficients of the ultimate giv value are stored in
7005 *MULT_VAL and *ADD_VAL. */
7007 static int
7011 {
7017 rtx temp;
7018 rtx set;
7020 /* Indicate that this is a giv so that we can update the value produced in
7021 each insn of the multi-insn sequence.
7023 This induction structure will be used only by the call to
7024 general_induction_var below, so we can allocate it on our stack.
7025 If this is a giv, our caller will replace the induct var entry with
7026 a new induction structure. */
7047 {
7051 /* If libcall, skip to end of call sequence. */
7062 /* Giv created by equivalent expression. */
7068 {
7072 count--;
7076 }
7078 {
7079 /* Allow insns that set something other than this giv to a
7080 constant. Such insns are needed on machines which cannot
7081 include long constants and should not disqualify a giv. */
7090 }
7091 }
7096 }
7097 \f
7098 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7099 represented by G1. If no such expression can be found, or it is clear that
7100 it cannot possibly be a valid address, 0 is returned.
7102 To perform the computation, we note that
7103 G1 = x * v + a and
7104 G2 = y * v + b
7105 where `v' is the biv.
7107 So G2 = (y/b) * G1 + (b - a*y/x).
7109 Note that MULT = y/x.
7111 Update: A and B are now allowed to be additive expressions such that
7112 B contains all variables in A. That is, computing B-A will not require
7113 subtracting variables. */
7115 static rtx
7117 {
7118 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7123 /* If MULT is not 1, we cannot handle A with non-constants, since we
7124 would then be required to subtract multiples of the registers in A.
7125 This is theoretically possible, and may even apply to some Fortran
7126 constructs, but it is a lot of work and we do not attempt it here. */
7131 /* In general these structures are sorted top to bottom (down the PLUS
7132 chain), but not left to right across the PLUS. If B is a higher
7133 order giv than A, we can strip one level and recurse. If A is higher
7134 order, we'll eventually bail out, but won't know that until the end.
7135 If they are the same, we'll strip one level around this loop. */
7138 {
7150 /* We matched: remove one reg completely. */
7153 /* An alternate match. */
7156 /* An alternate match. */
7158 else
7159 {
7160 /* Indicates an extra register in B. Strip one level from B and
7161 recurse, hoping B was the higher order expression. */
7166 }
7167 }
7169 /* Here we are at the last level of A, go through the cases hoping to
7170 get rid of everything but a constant. */
7173 {
7186 }
7188 {
7190 }
7192 {
7197 }
7199 {
7204 else
7206 }
7211 }
7213 rtx
7215 {
7218 /* The value that G1 will be multiplied by must be a constant integer. Also,
7219 the only chance we have of getting a valid address is if b*c/a (see above
7220 for notation) is also an integer. */
7223 {
7231 }
7234 else
7235 {
7236 /* ??? Find out if the one is a multiple of the other? */
7238 }
7242 {
7243 /* Failed. If we've got a multiplication factor between G1 and G2,
7244 scale G1's addend and try again. */
7246 {
7250 {
7251 HOST_WIDE_INT m;
7255 }
7256 else
7257 {
7259 mult);
7260 }
7263 }
7264 }
7268 /* Form simplified final result. */
7273 else
7278 else
7279 {
7282 {
7286 }
7289 }
7290 }
7291 \f
7292 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7293 represented by G1. This indicates that G2 should be combined with G1 and
7294 that G2 can use (either directly or via an address expression) a register
7295 used to represent G1. */
7297 static rtx
7299 {
7302 /* With the introduction of ext dependent givs, we must care for modes.
7303 G2 must not use a wider mode than G1. */
7313 /* If these givs are identical, they can be combined. We use the results
7314 of express_from because the addends are not in a canonical form, so
7315 rtx_equal_p is a weaker test. */
7316 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7317 combination to be the other way round. */
7320 {
7322 }
7324 /* If G2 can be expressed as a function of G1 and that function is valid
7325 as an address and no more expensive than using a register for G2,
7326 the expression of G2 in terms of G1 can be used. */
7333 }
7334 \f
7335 /* Check each extension dependent giv in this class to see if its
7336 root biv is safe from wrapping in the interior mode, which would
7337 make the giv illegal. */
7339 static void
7341 {
7345 HOST_WIDE_INT start_val;
7351 /* Make sure the iteration data is available. We must have
7352 constants in order to be certain of no overflow. */
7358 /* Make sure the host can represent the arithmetic. */
7360 {
7362 HOST_WIDE_INT s_end_val;
7374 /* Check for host arithmetic overflow. */
7376 {
7378 HOST_WIDE_INT s_max;
7385 /* Check zero extension of biv ok. */
7387 /* Check for host arithmetic overflow. */
7388 && (neg_incr
7391 /* Check for target arithmetic overflow. */
7392 && (neg_incr
7395 {
7397 }
7399 /* Check sign extension of biv ok. */
7400 /* ??? While it is true that overflow with signed and pointer
7401 arithmetic is undefined, I fear too many programmers don't
7402 keep this fact in mind -- myself included on occasion.
7403 So leave alone with the signed overflow optimizations. */
7405 /* Check for host arithmetic overflow. */
7406 && (neg_incr
7409 /* Check for target arithmetic overflow. */
7410 && (neg_incr
7413 {
7415 }
7416 }
7417 }
7419 /* If we know the BIV is compared at run-time against an
7420 invariant value, and the increment is +/- 1, we may also
7421 be able to prove that the BIV cannot overflow. */
7427 {
7428 /* If the increment is +1, and the exit test is a <,
7429 the BIV cannot overflow. (For <=, we have the
7430 problematic case that the comparison value might
7431 be the maximum value of the range.) */
7433 {
7438 }
7440 /* Likewise for increment -1 and exit test >. */
7442 {
7447 }
7448 }
7450 /* Invalidate givs that fail the tests. */
7453 {
7458 {
7467 /* We don't know whether this value is being used as either
7468 signed or unsigned, so to safely truncate we must satisfy
7469 both. The initial check here verifies the BIV itself;
7470 once that is successful we may check its range wrt the
7471 derived GIV. This works only if we were able to determine
7472 constant start and end values above. */
7474 {
7478 /* We know from the above that both endpoints are nonnegative,
7479 and that there is no wrapping. Verify that both endpoints
7480 are within the (signed) range of the outer mode. */
7483 }
7488 }
7491 {
7493 {
7497 }
7498 }
7499 else
7500 {
7502 {
7507 else
7508 {
7513 else
7515 }
7520 }
7523 }
7524 }
7525 }
7527 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7529 rtx
7531 {
7537 /* Recall that check_ext_dependent_givs verified that the known bounds
7538 of a biv did not overflow or wrap with respect to the extension for
7539 the giv. Therefore, constants need no additional adjustment. */
7543 /* Otherwise, we must adjust the value to compensate for the
7544 differing modes of the biv and the giv. */
7546 }
7547 \f
7548 struct combine_givs_stats
7549 {
7552 };
7554 static int
7556 {
7563 /* Stabilize the sort. */
7567 }
7569 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7570 any other. If so, point SAME to the giv combined with and set NEW_REG to
7571 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7572 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7574 static void
7576 {
7577 /* Additional benefit to add for being combined multiple times. */
7585 /* Count givs, because bl->giv_count is incorrect here. */
7589 giv_count++;
7601 {
7603 rtx single_use;
7608 /* If a DEST_REG GIV is used only once, do not allow it to combine
7609 with anything, for in doing so we will gain nothing that cannot
7610 be had by simply letting the GIV with which we would have combined
7611 to be reduced on its own. The losage shows up in particular with
7612 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7613 be seen elsewhere as well. */
7620 /* Add an additional weight for zero addends. */
7625 {
7626 rtx this_combine;
7631 {
7634 }
7635 }
7637 }
7639 /* Iterate, combining until we can't. */
7640 restart:
7644 {
7647 {
7653 }
7655 }
7658 {
7664 /* If it has already been combined, skip. */
7669 {
7672 /* If it has already been combined, skip. */
7674 {
7679 /* For destination, we now may replace by mem expression instead
7680 of register. This changes the costs considerably, so add the
7681 compensation. */
7691 /* ??? The new final_[bg]iv_value code does a much better job
7692 of finding replaceable giv's, and hence this code may no
7693 longer be necessary. */
7697 /* To help optimize the next set of combinations, remove
7698 this giv from the benefits of other potential mates. */
7700 {
7704 }
7711 }
7712 }
7714 /* To help optimize the next set of combinations, remove
7715 this giv from the benefits of other potential mates. */
7717 {
7719 {
7723 }
7727 /* We've finished with this giv, and everything it touched.
7728 Restart the combination so that proper weights for the
7729 rest of the givs are properly taken into account. */
7730 /* ??? Ideally we would compact the arrays at this point, so
7731 as to not cover old ground. But sanely compacting
7732 can_combine is tricky. */
7734 }
7735 }
7737 /* Clean up. */
7740 }
7741 \f
7742 /* Generate sequence for REG = B * M + A. B is the initial value of
7743 the basic induction variable, M a multiplicative constant, A an
7744 additive constant and REG the destination register. */
7746 static rtx
7748 {
7749 rtx seq;
7750 rtx result;
7753 /* Use unsigned arithmetic. */
7761 }
7764 /* Update registers created in insn sequence SEQ. */
7766 static void
7768 {
7769 rtx insn;
7771 /* Update register info for alias analysis. */
7775 {
7782 }
7783 }
7786 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7787 is the initial value of the basic induction variable, M a
7788 multiplicative constant, A an additive constant and REG the
7789 destination register. */
7791 void
7794 {
7795 rtx seq;
7798 {
7801 }
7803 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7806 /* Increase the lifetime of any invariants moved further in code. */
7811 /* It is possible that the expansion created lots of new registers.
7812 Iterate over the sequence we just created and record them all. We
7813 must do this before inserting the sequence. */
7817 }
7820 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7821 initial value of the basic induction variable, M a multiplicative
7822 constant, A an additive constant and REG the destination
7823 register. */
7825 void
7827 {
7828 rtx seq;
7830 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7833 /* Increase the lifetime of any invariants moved further in code.
7834 ???? Is this really necessary? */
7839 /* It is possible that the expansion created lots of new registers.
7840 Iterate over the sequence we just created and record them all. We
7841 must do this before inserting the sequence. */
7845 }
7848 /* Emit insns after loop to set REG = B * M + A. B is the initial
7849 value of the basic induction variable, M a multiplicative constant,
7850 A an additive constant and REG the destination register. */
7852 void
7854 {
7855 rtx seq;
7857 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7860 /* It is possible that the expansion created lots of new registers.
7861 Iterate over the sequence we just created and record them all. We
7862 must do this before inserting the sequence. */
7866 }
7870 /* Similar to gen_add_mult, but compute cost rather than generating
7871 sequence. */
7873 static int
7875 {
7885 {
7890 }
7893 }
7894 \f
7895 /* Test whether A * B can be computed without
7896 an actual multiply insn. Value is 1 if so.
7898 ??? This function stinks because it generates a ton of wasted RTL
7899 ??? and as a result fragments GC memory to no end. There are other
7900 ??? places in the compiler which are invoked a lot and do the same
7901 ??? thing, generate wasted RTL just to see if something is possible. */
7903 static int
7905 {
7906 rtx tmp;
7909 /* If only one is constant, make it B. */
7913 /* If first constant, both constant, so don't need multiply. */
7917 /* If second not constant, neither is constant, so would need multiply. */
7921 /* One operand is constant, so might not need multiply insn. Generate the
7922 code for the multiply and see if a call or multiply, or long sequence
7923 of insns is generated. */
7932 {
7935 {
7945 {
7948 }
7951 }
7952 }
7962 }
7963 \f
7964 /* Check to see if loop can be terminated by a "decrement and branch until
7965 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7966 Also try reversing an increment loop to a decrement loop
7967 to see if the optimization can be performed.
7968 Value is nonzero if optimization was performed. */
7970 /* This is useful even if the architecture doesn't have such an insn,
7971 because it might change a loops which increments from 0 to n to a loop
7972 which decrements from n to 0. A loop that decrements to zero is usually
7973 faster than one that increments from zero. */
7975 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7976 such as approx_final_value, biv_total_increment, loop_iterations, and
7977 final_[bg]iv_value. */
7979 static int
7981 {
7986 rtx reg;
7988 rtx jump_label;
7989 rtx final_value;
7990 rtx start_value;
7991 rtx new_add_val;
7992 rtx comparison;
7993 rtx before_comparison;
7994 rtx p;
7995 rtx jump;
7996 rtx first_compare;
8001 /* If last insn is a conditional branch, and the insn before tests a
8002 register value, try to optimize it. Otherwise, we can't do anything. */
8011 /* Try to compute whether the compare/branch at the loop end is one or
8012 two instructions. */
8018 else
8021 {
8022 /* If more than one condition is present to control the loop, then
8023 do not proceed, as this function does not know how to rewrite
8024 loop tests with more than one condition.
8026 Look backwards from the first insn in the last comparison
8027 sequence and see if we've got another comparison sequence. */
8029 rtx jump1;
8033 }
8035 /* Check all of the bivs to see if the compare uses one of them.
8036 Skip biv's set more than once because we can't guarantee that
8037 it will be zero on the last iteration. Also skip if the biv is
8038 used between its update and the test insn. */
8041 {
8046 first_compare))
8048 }
8050 /* Try swapping the comparison to identify a suitable biv. */
8057 first_compare))
8058 {
8060 VOIDmode,
8064 }
8069 /* Look for the case where the basic induction variable is always
8070 nonnegative, and equals zero on the last iteration.
8071 In this case, add a reg_note REG_NONNEG, which allows the
8072 m68k DBRA instruction to be used. */
8078 {
8079 /* Initial value must be greater than 0,
8080 init_val % -dec_value == 0 to ensure that it equals zero on
8081 the last iteration */
8087 {
8088 /* Register always nonnegative, add REG_NOTE to branch. */
8096 }
8098 /* If the decrement is 1 and the value was tested as >= 0 before
8099 the loop, then we can safely optimize. */
8101 {
8115 {
8123 }
8124 }
8125 }
8128 {
8129 /* Try to change inc to dec, so can apply above optimization. */
8130 /* Can do this if:
8131 all registers modified are induction variables or invariant,
8132 all memory references have non-overlapping addresses
8133 (obviously true if only one write)
8134 allow 2 insns for the compare/jump at the end of the loop. */
8135 /* Also, we must avoid any instructions which use both the reversed
8136 biv and another biv. Such instructions will fail if the loop is
8137 reversed. We meet this condition by requiring that either
8138 no_use_except_counting is true, or else that there is only
8139 one biv. */
8141 /* 1 if the iteration var is used only to count iterations. */
8143 /* 1 if the loop has no memory store, or it has a single memory store
8144 which is reversible. */
8150 {
8154 /* If there are no givs for this biv, and the only exit is the
8155 fall through at the end of the loop, then
8156 see if perhaps there are no uses except to count. */
8160 {
8165 /* An insn that sets the biv is okay. */
8166 ;
8168 /* An insn that doesn't mention the biv is okay. */
8169 ;
8172 {
8173 /* If either of these insns uses the biv and sets a pseudo
8174 that has more than one usage, then the biv has uses
8175 other than counting since it's used to derive a value
8176 that is used more than one time. */
8178 regs);
8180 {
8183 }
8184 }
8185 else
8186 {
8189 }
8190 }
8192 /* A biv has uses besides counting if it is used to set
8193 another biv. */
8197 {
8200 }
8201 }
8204 /* No need to worry about MEMs. */
8205 ;
8207 {
8212 /* If the loop has a single store, and the destination address is
8213 invariant, then we can't reverse the loop, because this address
8214 might then have the wrong value at loop exit.
8215 This would work if the source was invariant also, however, in that
8216 case, the insn should have been moved out of the loop. */
8219 {
8222 /* If we could prove that each of the memory locations
8223 written to was different, then we could reverse the
8224 store -- but we don't presently have any way of
8225 knowing that. */
8228 /* If the store depends on a register that is set after the
8229 store, it depends on the initial value, and is thus not
8230 reversible. */
8232 {
8239 }
8240 }
8241 }
8242 else
8245 /* This code only acts for innermost loops. Also it simplifies
8246 the memory address check by only reversing loops with
8247 zero or one memory access.
8248 Two memory accesses could involve parts of the same array,
8249 and that can't be reversed.
8250 If the biv is used only for counting, than we don't need to worry
8251 about all these things. */
8257 && reversible_mem_store
8262 {
8263 rtx tem;
8265 /* Loop can be reversed. */
8269 /* Now check other conditions:
8271 The increment must be a constant, as must the initial value,
8272 and the comparison code must be LT.
8274 This test can probably be improved since +/- 1 in the constant
8275 can be obtained by changing LT to LE and vice versa; this is
8276 confusing. */
8279 /* for constants, LE gets turned into LT */
8284 {
8295 comparison_const_width
8297 else
8298 comparison_const_width
8302 comparison_sign_mask
8305 /* If the comparison value is not a loop invariant, then we
8306 can not reverse this loop.
8308 ??? If the insns which initialize the comparison value as
8309 a whole compute an invariant result, then we could move
8310 them out of the loop and proceed with loop reversal. */
8318 /* Normalize the initial value if it is an integer and
8319 has no other use except as a counter. This will allow
8320 a few more loops to be reversed. */
8324 {
8326 /* The code below requires comparison_val to be a multiple
8327 of add_val in order to do the loop reversal, so
8328 round up comparison_val to a multiple of add_val.
8329 Since comparison_value is constant, we know that the
8330 current comparison code is LT. */
8332 comparison_val
8334 /* We postpone overflow checks for COMPARISON_VAL here;
8335 even if there is an overflow, we might still be able to
8336 reverse the loop, if converting the loop exit test to
8337 NE is possible. */
8339 }
8341 /* First check if we can do a vanilla loop reversal. */
8343 /* If we have a decrement_and_branch_on_count,
8344 prefer the NE test, since this will allow that
8345 instruction to be generated. Note that we must
8346 use a vanilla loop reversal if the biv is used to
8347 calculate a giv or has a non-counting use. */
8348 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8349 && defined (HAVE_decrement_and_branch_on_count)
8353 #endif
8355 /* Now do postponed overflow checks on COMPARISON_VAL. */
8358 {
8359 /* Register will always be nonnegative, with value
8360 0 on last iteration */
8364 }
8368 {
8371 }
8372 else
8378 /* If the initial value is not zero, or if the comparison
8379 value is not an exact multiple of the increment, then we
8380 can not reverse this loop. */
8383 {
8386 }
8387 else
8388 {
8391 }
8395 /* Reset these in case we normalized the initial value
8396 and comparison value above. */
8399 {
8401 final_value
8403 }
8406 /* Save some info needed to produce the new insns. */
8412 /* Set start_value; if this is not a CONST_INT, we need
8413 to generate a SUB.
8414 Initialize biv to start_value before loop start.
8415 The old initializing insn will be deleted as a
8416 dead store by flow.c. */
8419 {
8420 start_value
8423 }
8425 {
8432 start_value
8438 }
8440 {
8442 initial_value);
8446 start_value
8449 }
8450 else
8451 /* We could handle the other cases too, but it'll be
8452 better to have a testcase first. */
8455 /* We may not have a single insn which can increment a reg, so
8456 create a sequence to hold all the insns from expand_inc. */
8465 /* Update biv info to reflect its new status. */
8470 /* Update loop info. */
8479 /* Inc LABEL_NUSES so that delete_insn will
8480 not delete the label. */
8483 /* Emit an insn after the end of the loop to set the biv's
8484 proper exit value if it is used anywhere outside the loop. */
8490 /* Delete compare/branch at end of loop. */
8495 /* Add new compare/branch insn at end of loop. */
8507 ;
8513 {
8515 {
8516 /* Increment of LABEL_NUSES done above. */
8517 /* Register is now always nonnegative,
8518 so add REG_NONNEG note to the branch. */
8521 }
8523 }
8525 /* No insn may reference both the reversed and another biv or it
8526 will fail (see comment near the top of the loop reversal
8527 code).
8528 Earlier on, we have verified that the biv has no use except
8529 counting, or it is the only biv in this function.
8530 However, the code that computes no_use_except_counting does
8531 not verify reg notes. It's possible to have an insn that
8532 references another biv, and has a REG_EQUAL note with an
8533 expression based on the reversed biv. To avoid this case,
8534 remove all REG_EQUAL notes based on the reversed biv
8535 here. */
8538 {
8541 /* If this is a set of a GIV based on the reversed biv, any
8542 REG_EQUAL notes should still be correct. */
8549 {
8554 else
8556 }
8557 }
8559 /* Mark that this biv has been reversed. Each giv which depends
8560 on this biv, and which is also live past the end of the loop
8561 will have to be fixed up. */
8566 {
8570 else
8572 }
8575 }
8576 }
8577 }
8580 }
8581 \f
8582 /* Verify whether the biv BL appears to be eliminable,
8583 based on the insns in the loop that refer to it.
8585 If ELIMINATE_P is nonzero, actually do the elimination.
8587 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8588 determine whether invariant insns should be placed inside or at the
8589 start of the loop. */
8591 static int
8594 {
8597 rtx p;
8599 /* Scan all insns in the loop, stopping if we find one that uses the
8600 biv in a way that we cannot eliminate. */
8603 {
8607 rtx note;
8609 /* If this is a libcall that sets a giv, skip ahead to its end. */
8611 {
8615 {
8620 {
8627 }
8628 }
8629 }
8631 /* Closely examine the insn if the biv is mentioned. */
8636 {
8642 }
8644 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8649 }
8652 {
8657 }
8660 }
8661 \f
8662 /* INSN and REFERENCE are instructions in the same insn chain.
8663 Return nonzero if INSN is first. */
8665 int
8667 {
8671 {
8672 /* Start with test for not first so that INSN == REFERENCE yields not
8673 first. */
8679 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8680 previous insn, hence the <= comparison below does not work if
8681 P is a note. */
8692 }
8693 }
8695 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8696 the offset that we have to take into account due to auto-increment /
8697 div derivation is zero. */
8698 static int
8701 {
8702 /* If the giv V had the auto-inc address optimization applied
8703 to it, and INSN occurs between the giv insn and the biv
8704 insn, then we'd have to adjust the value used here.
8705 This is rare, so we don't bother to make this possible. */
8714 }
8716 /* If BL appears in X (part of the pattern of INSN), see if we can
8717 eliminate its use. If so, return 1. If not, return 0.
8719 If BIV does not appear in X, return 1.
8721 If ELIMINATE_P is nonzero, actually do the elimination.
8722 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8723 Depending on how many items have been moved out of the loop, it
8724 will either be before INSN (when WHERE_INSN is nonzero) or at the
8725 start of the loop (when WHERE_INSN is zero). */
8727 static int
8731 {
8737 #ifdef HAVE_cc0
8739 #endif
8745 {
8747 /* If we haven't already been able to do something with this BIV,
8748 we can't eliminate it. */
8754 /* If this sets the BIV, it is not a problem. */
8758 /* If this is an insn that defines a giv, it is also ok because
8759 it will go away when the giv is reduced. */
8764 #ifdef HAVE_cc0
8766 {
8767 /* Can replace with any giv that was reduced and
8768 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8769 Require a constant for MULT_VAL, so we know it's nonzero.
8770 ??? We disable this optimization to avoid potential
8771 overflows. */
8779 {
8786 /* If the giv has the opposite direction of change,
8787 then reverse the comparison. */
8791 else
8794 /* We can probably test that giv's reduced reg. */
8797 }
8799 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8800 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8801 Require a constant for MULT_VAL, so we know it's nonzero.
8802 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8803 overflow problem. */
8815 {
8822 /* If the giv has the opposite direction of change,
8823 then reverse the comparison. */
8827 else
8831 /* Replace biv with the giv's reduced register. */
8836 /* Insn doesn't support that constant or invariant. Copy it
8837 into a register (it will be a loop invariant.) */
8844 /* Substitute the new register for its invariant value in
8845 the compare expression. */
8849 }
8850 }
8851 #endif
8858 /* See if either argument is the biv. */
8863 else
8867 {
8868 /* First try to replace with any giv that has constant positive
8869 mult_val and constant add_val. We might be able to support
8870 negative mult_val, but it seems complex to do it in general. */
8882 {
8886 /* Don't eliminate if the linear combination that makes up
8887 the giv overflows when it is applied to ARG. */
8889 {
8890 rtx add_val;
8894 else
8900 }
8905 /* Replace biv with the giv's reduced reg. */
8908 /* If all constants are actually constant integers and
8909 the derived constant can be directly placed in the COMPARE,
8910 do so. */
8913 {
8916 }
8917 else
8918 {
8919 /* Otherwise, load it into a register. */
8924 }
8930 }
8932 /* Look for giv with positive constant mult_val and nonconst add_val.
8933 Insert insns to calculate new compare value.
8934 ??? Turn this off due to possible overflow. */
8942 {
8943 rtx tem;
8953 /* Replace biv with giv's reduced register. */
8957 /* Compute value to compare against. */
8961 /* Use it in this insn. */
8965 }
8966 }
8968 {
8970 {
8971 /* Look for giv with constant positive mult_val and nonconst
8972 add_val. Insert insns to compute new compare value.
8973 ??? Turn this off due to possible overflow. */
8980 {
8981 rtx tem;
8991 /* Replace biv with giv's reduced register. */
8995 /* Compute value to compare against. */
9002 }
9003 }
9005 /* This code has problems. Basically, you can't know when
9006 seeing if we will eliminate BL, whether a particular giv
9007 of ARG will be reduced. If it isn't going to be reduced,
9008 we can't eliminate BL. We can try forcing it to be reduced,
9009 but that can generate poor code.
9011 The problem is that the benefit of reducing TV, below should
9012 be increased if BL can actually be eliminated, but this means
9013 we might have to do a topological sort of the order in which
9014 we try to process biv. It doesn't seem worthwhile to do
9015 this sort of thing now. */
9017 #if 0
9018 /* Otherwise the reg compared with had better be a biv. */
9023 /* Look for a pair of givs, one for each biv,
9024 with identical coefficients. */
9026 {
9038 {
9045 /* Replace biv with its giv's reduced reg. */
9047 /* Replace other operand with the other giv's
9048 reduced reg. */
9051 }
9052 }
9053 #endif
9054 }
9056 /* If we get here, the biv can't be eliminated. */
9060 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9061 biv is used in it, since it will be replaced. */
9069 }
9071 /* See if any subexpression fails elimination. */
9074 {
9076 {
9089 }
9090 }
9093 }
9094 \f
9095 /* Return nonzero if the last use of REG
9096 is in an insn following INSN in the same basic block. */
9098 static int
9100 {
9101 rtx n;
9105 {
9108 }
9110 }
9111 \f
9112 /* Called via `note_stores' to record the initial value of a biv. Here we
9113 just record the location of the set and process it later. */
9115 static void
9117 {
9128 /* If this is the first set found, record it. */
9130 {
9133 }
9134 }
9135 \f
9136 /* If any of the registers in X are "old" and currently have a last use earlier
9137 than INSN, update them to have a last use of INSN. Their actual last use
9138 will be the previous insn but it will not have a valid uid_luid so we can't
9139 use it. X must be a source expression only. */
9141 static void
9143 {
9144 /* Check for the case where INSN does not have a valid luid. In this case,
9145 there is no need to modify the regno_last_uid, as this can only happen
9146 when code is inserted after the loop_end to set a pseudo's final value,
9147 and hence this insn will never be the last use of x.
9148 ???? This comment is not correct. See for example loop_givs_reduce.
9149 This may insert an insn before another new insn. */
9153 {
9155 }
9156 else
9157 {
9161 {
9167 }
9168 }
9169 }
9170 \f
9171 /* Given an insn INSN and condition COND, return the condition in a
9172 canonical form to simplify testing by callers. Specifically:
9174 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9175 (2) Both operands will be machine operands; (cc0) will have been replaced.
9176 (3) If an operand is a constant, it will be the second operand.
9177 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9178 for GE, GEU, and LEU.
9180 If the condition cannot be understood, or is an inequality floating-point
9181 comparison which needs to be reversed, 0 will be returned.
9183 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9185 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9186 insn used in locating the condition was found. If a replacement test
9187 of the condition is desired, it should be placed in front of that
9188 insn and we will be sure that the inputs are still valid.
9190 If WANT_REG is nonzero, we wish the condition to be relative to that
9191 register, if possible. Therefore, do not canonicalize the condition
9192 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
9193 to be a compare to a CC mode register. */
9195 rtx
9198 {
9201 rtx set;
9202 rtx tem;
9220 /* If we are comparing a register with zero, see if the register is set
9221 in the previous insn to a COMPARE or a comparison operation. Perform
9222 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9223 in cse.c */
9228 {
9229 /* Set nonzero when we find something of interest. */
9232 #ifdef HAVE_cc0
9233 /* If comparison with cc0, import actual comparison from compare
9234 insn. */
9236 {
9247 }
9248 #endif
9250 /* If this is a COMPARE, pick up the two things being compared. */
9252 {
9256 }
9260 /* Go back to the previous insn. Stop if it is not an INSN. We also
9261 stop if it isn't a single set or if it has a REG_INC note because
9262 we don't want to bother dealing with it. */
9276 /* If this is setting OP0, get what it sets it to if it looks
9277 relevant. */
9279 {
9281 #ifdef FLOAT_STORE_FLAG_VALUE
9282 REAL_VALUE_TYPE fsfv;
9283 #endif
9285 /* ??? We may not combine comparisons done in a CCmode with
9286 comparisons not done in a CCmode. This is to aid targets
9287 like Alpha that have an IEEE compliant EQ instruction, and
9288 a non-IEEE compliant BEQ instruction. The use of CCmode is
9289 actually artificial, simply to prevent the combination, but
9290 should not affect other platforms.
9292 However, we must allow VOIDmode comparisons to match either
9293 CCmode or non-CCmode comparison, because some ports have
9294 modeless comparisons inside branch patterns.
9296 ??? This mode check should perhaps look more like the mode check
9297 in simplify_comparison in combine. */
9305 && (STORE_FLAG_VALUE
9308 #ifdef FLOAT_STORE_FLAG_VALUE
9313 #endif
9314 ))
9325 && (STORE_FLAG_VALUE
9328 #ifdef FLOAT_STORE_FLAG_VALUE
9333 #endif
9334 ))
9340 {
9343 }
9344 else
9346 }
9349 /* If this sets OP0, but not directly, we have to give up. */
9353 {
9357 {
9362 }
9367 }
9368 }
9370 /* If constant is first, put it last. */
9374 /* If OP0 is the result of a comparison, we weren't able to find what
9375 was really being compared, so fail. */
9380 /* Canonicalize any ordered comparison with integers involving equality
9381 if we can do computations in the relevant mode and we do not
9382 overflow. */
9388 {
9391 unsigned HOST_WIDE_INT max_val
9395 {
9401 /* When cross-compiling, const_val might be sign-extended from
9402 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9422 }
9423 }
9425 /* Never return CC0; return zero instead. */
9430 }
9432 /* Given a jump insn JUMP, return the condition that will cause it to branch
9433 to its JUMP_LABEL. If the condition cannot be understood, or is an
9434 inequality floating-point comparison which needs to be reversed, 0 will
9435 be returned.
9437 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9438 insn used in locating the condition was found. If a replacement test
9439 of the condition is desired, it should be placed in front of that
9440 insn and we will be sure that the inputs are still valid.
9442 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
9443 compare CC mode register. */
9445 rtx
9447 {
9448 rtx cond;
9450 rtx set;
9452 /* If this is not a standard conditional jump, we can't parse it. */
9460 /* If this branches to JUMP_LABEL when the condition is false, reverse
9461 the condition. */
9462 reverse
9467 allow_cc_mode);
9468 }
9470 /* Similar to above routine, except that we also put an invariant last
9471 unless both operands are invariants. */
9473 rtx
9475 {
9485 }
9487 /* Scan the function and determine whether it has indirect (computed) jumps.
9489 This is taken mostly from flow.c; similar code exists elsewhere
9490 in the compiler. It may be useful to put this into rtlanal.c. */
9491 static int
9493 {
9494 rtx insn;
9501 }
9503 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9504 documentation for LOOP_MEMS for the definition of `appropriate'.
9505 This function is called from prescan_loop via for_each_rtx. */
9507 static int
9509 {
9518 {
9523 /* We're not interested in MEMs that are only clobbered. */
9527 /* We're not interested in the MEM associated with a
9528 CONST_DOUBLE, so there's no need to traverse into this. */
9532 /* We're not interested in any MEMs that only appear in notes. */
9536 /* This is not a MEM. */
9538 }
9540 /* See if we've already seen this MEM. */
9543 {
9547 /* The modes of the two memory accesses are different. If
9548 this happens, something tricky is going on, and we just
9549 don't optimize accesses to this MEM. */
9553 }
9555 /* Resize the array, if necessary. */
9557 {
9560 else
9565 }
9567 /* Actually insert the MEM. */
9569 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9570 because we can't put it in a register. We still store it in the
9571 table, though, so that if we see the same address later, but in a
9572 non-BLK mode, we'll not think we can optimize it at that point. */
9578 }
9581 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9583 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9584 register that is modified by an insn between FROM and TO. If the
9585 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9586 more, stop incrementing it, to avoid overflow.
9588 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9589 register I is used, if it is only used once. Otherwise, it is set
9590 to 0 (for no uses) or const0_rtx for more than one use. This
9591 parameter may be zero, in which case this processing is not done.
9593 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9594 optimize register I. */
9596 static void
9598 {
9601 /* last_set[n] is nonzero iff reg n has been set in the current
9602 basic block. In that case, it is the insn that last set reg n. */
9604 rtx insn;
9610 /* Grow the regs array if not allocated or too small. */
9612 {
9617 /* Zero the new elements. */
9620 }
9622 /* Clear previously scanned fields but do not clear n_times_set. */
9624 {
9628 }
9632 /* Scan the loop, recording register usage. */
9635 {
9637 {
9638 /* Record registers that have exactly one use. */
9641 /* Include uses in REG_EQUAL notes. */
9649 {
9653 last_set);
9654 }
9655 }
9660 /* Invalidate all registers used for function argument passing.
9661 We check rtx_varies_p for the same reason as below, to allow
9662 optimizing PIC calculations. */
9664 {
9665 rtx link;
9667 link;
9669 {
9676 }
9677 }
9678 }
9680 /* Invalidate all hard registers clobbered by calls. With one exception:
9681 a call-clobbered PIC register is still function-invariant for our
9682 purposes, since we can hoist any PIC calculations out of the loop.
9683 Thus the call to rtx_varies_p. */
9688 {
9691 }
9693 #ifdef AVOID_CCMODE_COPIES
9694 /* Don't try to move insns which set CC registers if we should not
9695 create CCmode register copies. */
9699 #endif
9701 /* Set regs->array[I].n_times_set for the new registers. */
9706 }
9708 /* Returns the number of real INSNs in the LOOP. */
9710 static int
9712 {
9714 rtx insn;
9722 }
9724 /* Move MEMs into registers for the duration of the loop. */
9726 static void
9728 {
9735 rtx end_label;
9736 /* Nonzero if the next instruction may never be executed. */
9743 /* We cannot use next_label here because it skips over normal insns. */
9748 /* Check to see if it's possible that some instructions in the loop are
9749 never executed. Also check if there is a goto out of the loop other
9750 than right after the end of the loop. */
9754 {
9758 /* If we enter the loop in the middle, and scan
9759 around to the beginning, don't set maybe_never
9760 for that. This must be an unconditional jump,
9761 otherwise the code at the top of the loop might
9762 never be executed. Unconditional jumps are
9763 followed a by barrier then loop end. */
9768 {
9769 /* If this is a jump outside of the loop but not right
9770 after the end of the loop, we would have to emit new fixup
9771 sequences for each such label. */
9773 JUMP_INSN is executed, we must be conservative. */
9782 /* Something complicated. */
9784 else
9785 /* If there are any more instructions in the loop, they
9786 might not be reached. */
9788 }
9791 }
9793 /* Find start of the extended basic block that enters the loop. */
9797 ;
9802 /* Build table of mems that get set to constant values before the
9803 loop. */
9807 /* Actually move the MEMs. */
9809 {
9810 regset_head load_copies;
9811 regset_head store_copies;
9813 rtx reg;
9815 rtx mem_list_entry;
9819 /* There's no telling whether or not MEM is modified. */
9822 /* Go through the MEMs written to in the loop to see if this
9823 one is aliased by one of them. */
9826 {
9831 {
9832 /* MEM is indeed aliased by this store. */
9835 }
9837 }
9843 /* If this MEM is written to, we must be sure that there
9844 are no reads from another MEM that aliases this one. */
9846 {
9850 {
9854 VOIDmode,
9856 rtx_varies_p))
9857 {
9858 /* It's not safe to hoist loop_info->mems[i] out of
9859 the loop because writes to it might not be
9860 seen by reads from loop_info->mems[j]. */
9863 }
9864 }
9865 }
9868 /* We can't access the MEM outside the loop; it might
9869 cause a trap that wouldn't have happened otherwise. */
9873 /* We thought we were going to lift this MEM out of the
9874 loop, but later discovered that we could not. */
9880 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9881 order to keep scan_loop from moving stores to this MEM
9882 out of the loop just because this REG is neither a
9883 user-variable nor used in the loop test. */
9888 /* Now, replace all references to the MEM with the
9889 corresponding pseudos. */
9894 {
9896 {
9897 rtx set;
9901 /* See if this copies the mem into a register that isn't
9902 modified afterwards. We'll try to do copy propagation
9903 a little further on. */
9905 /* @@@ This test is _way_ too conservative. */
9906 && ! maybe_never
9914 /* See if this copies the mem from a register that isn't
9915 modified afterwards. We'll try to remove the
9916 redundant copy later on by doing a little register
9917 renaming and copy propagation. This will help
9918 to untangle things for the BIV detection code. */
9920 && ! maybe_never
9928 /* If this is a call which uses / clobbers this memory
9929 location, we must not change the interface here. */
9933 {
9937 }
9938 else
9939 /* Replace the memory reference with the shadow register. */
9942 }
9947 }
9952 /* We couldn't replace all occurrences of the MEM. */
9954 else
9955 {
9956 /* Load the memory immediately before LOOP->START, which is
9957 the NOTE_LOOP_BEG. */
9959 rtx set;
9965 {
9969 {
9973 /* Extending hard register lifetimes causes crash
9974 on SRC targets. Doing so on non-SRC is
9975 probably also not good idea, since we most
9976 probably have pseudoregister equivalence as
9977 well. */
9980 }
9981 /* Use the constant equivalence if that is cheap enough. */
9987 {
9990 }
9992 /* If best_equiv is nonzero, we know that MEM is set to a
9993 constant or register before the loop. We will use this
9994 knowledge to initialize the shadow register with that
9995 constant or reg rather than by loading from MEM. */
9998 }
10003 {
10006 {
10009 }
10010 }
10016 {
10018 {
10021 }
10023 /* Store the memory immediately after END, which is
10024 the NOTE_LOOP_END. */
10027 }
10030 {
10035 }
10037 /* Attempt a bit of copy propagation. This helps untangle the
10038 data flow, and enables {basic,general}_induction_var to find
10039 more bivs/givs. */
10040 EXECUTE_IF_SET_IN_REG_SET
10042 {
10044 });
10047 EXECUTE_IF_SET_IN_REG_SET
10049 {
10051 });
10053 }
10054 }
10056 /* Now, we need to replace all references to the previous exit
10057 label with the new one. */
10064 }
10066 /* For communication between note_reg_stored and its caller. */
10067 struct note_reg_stored_arg
10068 {
10070 rtx reg;
10071 };
10073 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10074 is equal to ARG. */
10075 static void
10077 {
10081 }
10083 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10084 There must be exactly one insn that sets this pseudo; it will be
10085 deleted if all replacements succeed and we can prove that the register
10086 is not used after the loop. */
10088 static void
10090 {
10091 /* This is the reg that we are copying from. */
10094 rtx insn;
10095 /* These help keep track of whether we replaced all uses of the reg. */
10102 {
10103 rtx set;
10105 /* Only substitute within one extended basic block from the initializing
10106 insn. */
10113 /* Is this the initializing insn? */
10118 {
10125 }
10127 /* Only substitute after seeing the initializing insn. */
10129 {
10136 /* Stop replacing when REPLACEMENT is modified. */
10141 {
10144 /* It is possible that we've turned previously valid REG_EQUAL to
10145 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10146 REPLACEMENT is modified, we get different meaning. */
10150 }
10151 }
10152 }
10156 {
10160 {
10161 rtx first;
10162 rtx retval_note;
10164 /* Assume we're just deleting INIT_INSN. */
10166 /* Look for REG_RETVAL note. If we're deleting the end of
10167 the libcall sequence, the whole sequence can go. */
10169 /* If we found a REG_RETVAL note, find the first instruction
10170 in the sequence. */
10174 /* Delete the instructions. */
10176 }
10179 }
10180 }
10182 /* Replace all the instructions from FIRST up to and including LAST
10183 with NOTE_INSN_DELETED notes. */
10185 static void
10187 {
10189 {
10195 /* If this was the LAST instructions we're supposed to delete,
10196 we're done. */
10201 }
10202 }
10204 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10205 loop LOOP if the order of the sets of these registers can be
10206 swapped. There must be exactly one insn within the loop that sets
10207 this pseudo followed immediately by a move insn that sets
10208 REPLACEMENT with REGNO. */
10209 static void
10212 {
10213 rtx insn;
10222 {
10223 /* Search for the insn that copies REGNO to NEW_REGNO? */
10231 }
10234 {
10235 rtx prev_insn;
10236 rtx prev_set;
10238 /* Some DEF-USE info would come in handy here to make this
10239 function more general. For now, just check the previous insn
10240 which is the most likely candidate for setting REGNO. */
10248 {
10249 /* We have:
10250 (set (reg regno) (expr))
10251 (set (reg new_regno) (reg regno))
10253 so try converting this to:
10254 (set (reg new_regno) (expr))
10255 (set (reg regno) (reg new_regno))
10257 The former construct is often generated when a global
10258 variable used for an induction variable is shadowed by a
10259 register (NEW_REGNO). The latter construct improves the
10260 chances of GIV replacement and BIV elimination. */
10270 {
10277 /* Update first use of REGNO. */
10281 /* Now perform copy propagation to hopefully
10282 remove all uses of REGNO within the loop. */
10284 }
10285 }
10286 }
10287 }
10289 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10291 static int
10293 {
10295 {
10299 }
10301 }
10303 /* Returns the first MEM found in NOTE by depth-first search. */
10305 static rtx
10307 {
10311 }
10313 /* Replace MEM with its associated pseudo register. This function is
10314 called from load_mems via for_each_rtx. DATA is actually a pointer
10315 to a structure describing the instruction currently being scanned
10316 and the MEM we are currently replacing. */
10318 static int
10320 {
10328 {
10333 /* We're not interested in the MEM associated with a
10334 CONST_DOUBLE, so there's no need to traverse into one. */
10338 /* This is not a MEM. */
10340 }
10343 /* This is not the MEM we are currently replacing. */
10346 /* Actually replace the MEM. */
10350 }
10352 static void
10354 {
10355 loop_replace_args args;
10363 /* If we hoist a mem write out of the loop, then REG_EQUAL
10364 notes referring to the mem are no longer valid. */
10366 {
10371 {
10375 {
10376 /* Remove the note. */
10379 }
10380 }
10381 }
10382 }
10384 /* Replace one register with another. Called through for_each_rtx; PX points
10385 to the rtx being scanned. DATA is actually a pointer to
10386 a structure of arguments. */
10388 static int
10390 {
10401 }
10403 static void
10405 {
10406 loop_replace_args args;
10413 }
10414 \f
10415 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10416 (ignored in the interim). */
10418 static rtx
10421 rtx pattern)
10422 {
10424 }
10427 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10428 in basic block WHERE_BB (ignored in the interim) within the loop
10429 otherwise hoist PATTERN into the loop pre-header. */
10431 rtx
10433 basic_block where_bb ATTRIBUTE_UNUSED,
10435 {
10439 }
10442 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10443 WHERE_BB (ignored in the interim) within the loop. */
10445 static rtx
10447 basic_block where_bb ATTRIBUTE_UNUSED,
10449 {
10451 }
10454 /* Hoist insn for PATTERN into the loop pre-header. */
10456 rtx
10458 {
10460 }
10463 /* Hoist call insn for PATTERN into the loop pre-header. */
10465 static rtx
10467 {
10469 }
10472 /* Sink insn for PATTERN after the loop end. */
10474 rtx
10476 {
10478 }
10480 /* bl->final_value can be either general_operand or PLUS of general_operand
10481 and constant. Emit sequence of instructions to load it into REG. */
10482 static rtx
10484 {
10485 rtx seq;
10493 }
10495 /* If the loop has multiple exits, emit insn for PATTERN before the
10496 loop to ensure that it will always be executed no matter how the
10497 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10498 since this is slightly more efficient. */
10500 static rtx
10502 {
10505 else
10507 }
10508 \f
10509 static void
10511 {
10519 iv_num++;
10524 {
10527 }
10528 }
10531 static void
10534 {
10536 rtx incr;
10547 {
10550 }
10552 {
10555 }
10559 {
10563 }
10566 {
10570 }
10572 /* List the increments. */
10574 {
10578 }
10580 /* List the givs. */
10582 {
10587 else
10590 }
10591 }
10594 static void
10596 {
10607 {
10611 }
10614 }
10617 static void
10619 {
10626 else
10642 {
10644 {
10656 }
10657 }
10668 {
10672 }
10675 }
10678 void
10680 {
10682 }
10685 void
10687 {
10689 }
10692 void
10694 {
10696 }
10699 void
10701 {
10703 }
10706 #define LOOP_BLOCK_NUM_1(INSN) \
10707 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10709 /* The notes do not have an assigned block, so look at the next insn. */
10710 #define LOOP_BLOCK_NUM(INSN) \
10711 ((INSN) ? (GET_CODE (INSN) == NOTE \
10712 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10713 : LOOP_BLOCK_NUM_1 (INSN)) \
10714 : -1)
10716 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10718 static void
10721 {
10722 rtx label;
10727 /* Print diagnostics to compare our concept of a loop with
10728 what the loop notes say. */
10743 {
10763 {
10766 {
10769 }
10770 }
10773 /* This can happen when a marked loop appears as two nested loops,
10774 say from while (a || b) {}. The inner loop won't match
10775 the loop markers but the outer one will. */
10778 }
10779 }
10781 /* Call this function from the debugger to dump LOOP. */
10783 void
10785 {
10787 }
10789 /* Call this function from the debugger to dump LOOPS. */
10791 void
10793 {
10795 }