1 ;; Predicate description for RISC-V target.
2 ;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
3 ;; Contributed by Andrew Waterman (andrew@sifive.com).
4 ;; Based on MIPS target for GNU compiler.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 (define_predicate "const_arith_operand"
23 (and (match_code "const_int")
24 (match_test "SMALL_OPERAND (INTVAL (op))")))
26 (define_predicate "arith_operand"
27 (ior (match_operand 0 "const_arith_operand")
28 (match_operand 0 "register_operand")))
30 (define_predicate "const_csr_operand"
31 (and (match_code "const_int")
32 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
34 (define_predicate "csr_operand"
35 (ior (match_operand 0 "const_csr_operand")
36 (match_operand 0 "register_operand")))
38 (define_predicate "sle_operand"
39 (and (match_code "const_int")
40 (match_test "SMALL_OPERAND (INTVAL (op) + 1)")))
42 (define_predicate "sleu_operand"
43 (and (match_operand 0 "sle_operand")
44 (match_test "INTVAL (op) + 1 != 0")))
46 (define_predicate "const_0_operand"
47 (and (match_code "const_int,const_wide_int,const_double,const_vector")
48 (match_test "op == CONST0_RTX (GET_MODE (op))")))
50 (define_predicate "reg_or_0_operand"
51 (ior (match_operand 0 "const_0_operand")
52 (match_operand 0 "register_operand")))
54 ;; Only use branch-on-bit sequences when the mask is not an ANDI immediate.
55 (define_predicate "branch_on_bit_operand"
56 (and (match_code "const_int")
57 (match_test "INTVAL (op) >= IMM_BITS - 1")))
59 ;; A legitimate CONST_INT operand that takes more than one instruction
61 (define_predicate "splittable_const_int_operand"
62 (match_code "const_int")
64 /* Don't handle multi-word moves this way; we don't want to introduce
65 the individual word-mode moves until after reload. */
66 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
69 /* Otherwise check whether the constant can be loaded in a single
71 return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op));
74 (define_predicate "move_operand"
75 (match_operand 0 "general_operand")
77 enum riscv_symbol_type symbol_type;
79 /* The thinking here is as follows:
81 (1) The move expanders should split complex load sequences into
82 individual instructions. Those individual instructions can
83 then be optimized by all rtl passes.
85 (2) The target of pre-reload load sequences should not be used
86 to store temporary results. If the target register is only
87 assigned one value, reload can rematerialize that value
88 on demand, rather than spill it to the stack.
90 (3) If we allowed pre-reload passes like combine and cse to recreate
91 complex load sequences, we would want to be able to split the
92 sequences before reload as well, so that the pre-reload scheduler
93 can see the individual instructions. This falls foul of (2);
94 the splitter would be forced to reuse the target register for
97 (4) We want to define complex load splitters for combine. These
98 splitters can request a temporary scratch register, which avoids
99 the problem in (2). They allow things like:
101 (set (reg T1) (high SYM))
102 (set (reg T2) (low (reg T1) SYM))
103 (set (reg X) (plus (reg T2) (const_int OFFSET)))
107 (set (reg T3) (high SYM+OFFSET))
108 (set (reg X) (lo_sum (reg T3) SYM+OFFSET))
110 if T2 is only used this once. */
111 switch (GET_CODE (op))
114 return !splittable_const_int_operand (op, mode);
119 return riscv_symbolic_constant_p (op, &symbol_type)
120 && !riscv_split_symbol_type (symbol_type);
124 return riscv_symbolic_constant_p (op, &symbol_type)
125 && riscv_split_symbol_type (symbol_type)
126 && symbol_type != SYMBOL_PCREL;
133 (define_predicate "symbolic_operand"
134 (match_code "const,symbol_ref,label_ref")
136 enum riscv_symbol_type type;
137 return riscv_symbolic_constant_p (op, &type);
140 (define_predicate "absolute_symbolic_operand"
141 (match_code "const,symbol_ref,label_ref")
143 enum riscv_symbol_type type;
144 return (riscv_symbolic_constant_p (op, &type)
145 && (type == SYMBOL_ABSOLUTE || type == SYMBOL_PCREL));
148 (define_predicate "plt_symbolic_operand"
149 (match_code "const,symbol_ref,label_ref")
151 enum riscv_symbol_type type;
152 return (riscv_symbolic_constant_p (op, &type)
153 && type == SYMBOL_GOT_DISP && !SYMBOL_REF_WEAK (op) && TARGET_PLT);
156 (define_predicate "call_insn_operand"
157 (ior (match_operand 0 "absolute_symbolic_operand")
158 (match_operand 0 "plt_symbolic_operand")
159 (match_operand 0 "register_operand")))
161 (define_predicate "modular_operator"
162 (match_code "plus,minus,mult,ashift"))
164 (define_predicate "equality_operator"
165 (match_code "eq,ne"))
167 (define_predicate "order_operator"
168 (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu"))
170 (define_predicate "signed_order_operator"
171 (match_code "eq,ne,lt,le,ge,gt"))
173 (define_predicate "fp_native_comparison"
174 (match_code "eq,lt,le,gt,ge"))
176 (define_predicate "fp_scc_comparison"
177 (match_code "unordered,ordered,unlt,unge,unle,ungt,ltgt,ne,eq,lt,le,gt,ge"))
179 (define_predicate "fp_branch_comparison"
180 (match_code "unordered,ordered,unlt,unge,unle,ungt,uneq,ltgt,ne,eq,lt,le,gt,ge"))