gcc/config/aarch64/aarch64-modes.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 CC_MODE (CCFP);
  22 CC_MODE (CCFPE);
  23 CC_MODE (CC_SWP);
  24 CC_MODE (CC_NZ);    /* Only N and Z bits of condition flags are valid.  */
  25 CC_MODE (CC_Z);     /* Only Z bit of condition flags is valid.  */
  26 CC_MODE (CC_C);     /* Only C bit of condition flags is valid.  */
  27
  28 /* Half-precision floating point for __fp16.  */
  29 FLOAT_MODE (HF, 2, 0);
  30 ADJUST_FLOAT_FORMAT (HF, &ieee_half_format);
  31
  32 /* Vector modes.  */
  33
  34 VECTOR_BOOL_MODE (VNx16BI, 16, 2);
  35 VECTOR_BOOL_MODE (VNx8BI, 8, 2);
  36 VECTOR_BOOL_MODE (VNx4BI, 4, 2);
  37 VECTOR_BOOL_MODE (VNx2BI, 2, 2);
  38
  39 ADJUST_NUNITS (VNx16BI, aarch64_sve_vg * 8);
  40 ADJUST_NUNITS (VNx8BI, aarch64_sve_vg * 4);
  41 ADJUST_NUNITS (VNx4BI, aarch64_sve_vg * 2);
  42 ADJUST_NUNITS (VNx2BI, aarch64_sve_vg);
  43
  44 ADJUST_ALIGNMENT (VNx16BI, 2);
  45 ADJUST_ALIGNMENT (VNx8BI, 2);
  46 ADJUST_ALIGNMENT (VNx4BI, 2);
  47 ADJUST_ALIGNMENT (VNx2BI, 2);
  48
  49 VECTOR_MODES (INT, 8);        /*       V8QI V4HI V2SI.  */
  50 VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI.  */
  51 VECTOR_MODES (FLOAT, 8);      /*                 V2SF.  */
  52 VECTOR_MODES (FLOAT, 16);     /*            V4SF V2DF.  */
  53 VECTOR_MODE (FLOAT, DF, 1);   /*                 V1DF.  */
  54 VECTOR_MODE (FLOAT, HF, 2);   /*                 V2HF.  */
  55
  56 /* Oct Int: 256-bit integer mode needed for 32-byte vector arguments.  */
  57 INT_MODE (OI, 32);
  58
  59 /* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
  60    (2 d-regs = 1 q-reg = TImode).  */
  61 INT_MODE (CI, 48);
  62 INT_MODE (XI, 64);
  63
  64 /* Define SVE modes for NVECS vectors.  VB, VH, VS and VD are the prefixes
  65    for 8-bit, 16-bit, 32-bit and 64-bit elements respectively.  It isn't
  66    strictly necessary to set the alignment here, since the default would
  67    be clamped to BIGGEST_ALIGNMENT anyhow, but it seems clearer.  */
  68 #define SVE_MODES(NVECS, VB, VH, VS, VD) \
  69   VECTOR_MODES_WITH_PREFIX (VNx, INT, 16 * NVECS); \
  70   VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 16 * NVECS); \
  71   \
  72   ADJUST_NUNITS (VB##QI, aarch64_sve_vg * NVECS * 8); \
  73   ADJUST_NUNITS (VH##HI, aarch64_sve_vg * NVECS * 4); \
  74   ADJUST_NUNITS (VS##SI, aarch64_sve_vg * NVECS * 2); \
  75   ADJUST_NUNITS (VD##DI, aarch64_sve_vg * NVECS); \
  76   ADJUST_NUNITS (VH##HF, aarch64_sve_vg * NVECS * 4); \
  77   ADJUST_NUNITS (VS##SF, aarch64_sve_vg * NVECS * 2); \
  78   ADJUST_NUNITS (VD##DF, aarch64_sve_vg * NVECS); \
  79   \
  80   ADJUST_ALIGNMENT (VB##QI, 16); \
  81   ADJUST_ALIGNMENT (VH##HI, 16); \
  82   ADJUST_ALIGNMENT (VS##SI, 16); \
  83   ADJUST_ALIGNMENT (VD##DI, 16); \
  84   ADJUST_ALIGNMENT (VH##HF, 16); \
  85   ADJUST_ALIGNMENT (VS##SF, 16); \
  86   ADJUST_ALIGNMENT (VD##DF, 16);
  87
  88 /* Give SVE vectors the names normally used for 256-bit vectors.
  89    The actual number depends on command-line flags.  */
  90 SVE_MODES (1, VNx16, VNx8, VNx4, VNx2)
  91 SVE_MODES (2, VNx32, VNx16, VNx8, VNx4)
  92 SVE_MODES (3, VNx48, VNx24, VNx12, VNx6)
  93 SVE_MODES (4, VNx64, VNx32, VNx16, VNx8)
  94
  95 /* Quad float: 128-bit floating mode for long doubles.  */
  96 FLOAT_MODE (TF, 16, ieee_quad_format);
  97
  98 /* A 4-tuple of SVE vectors with the maximum -msve-vector-bits= setting.
  99    Note that this is a limit only on the compile-time sizes of modes;
 100    it is not a limit on the runtime sizes, since VL-agnostic code
 101    must work with arbitary vector lengths.  */
 102 #define MAX_BITSIZE_MODE_ANY_MODE (2048 * 4)
 103
 104 /* Coefficient 1 is multiplied by the number of 128-bit chunks in an
 105    SVE vector (referred to as "VQ") minus one.  */
 106 #define NUM_POLY_INT_COEFFS 2