1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
39 #include "m32r-protos.h"
41 #include "target-def.h"
43 /* Save the operands last given to a compare for use when we
44 generate a scc or bcc insn. */
45 rtx m32r_compare_op0
, m32r_compare_op1
;
47 /* Array of valid operand punctuation characters. */
48 char m32r_punct_chars
[256];
50 /* Selected code model. */
51 const char * m32r_model_string
= M32R_MODEL_DEFAULT
;
52 enum m32r_model m32r_model
;
54 /* Selected SDA support. */
55 const char * m32r_sdata_string
= M32R_SDATA_DEFAULT
;
56 enum m32r_sdata m32r_sdata
;
58 /* Scheduler support */
59 static int m32r_sched_odd_word_p
;
61 /* Forward declaration. */
62 static void init_reg_tables
PARAMS ((void));
63 static void block_move_call
PARAMS ((rtx
, rtx
, rtx
));
64 static int m32r_is_insn
PARAMS ((rtx
));
65 const struct attribute_spec m32r_attribute_table
[];
66 static tree m32r_handle_model_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
67 static void m32r_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
68 static void m32r_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
70 static int m32r_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
71 static int m32r_adjust_priority
PARAMS ((rtx
, int));
72 static void m32r_sched_init
PARAMS ((FILE *, int, int));
73 static int m32r_sched_reorder
PARAMS ((FILE *, int, rtx
*, int *, int));
74 static int m32r_variable_issue
PARAMS ((FILE *, int, rtx
, int));
75 static int m32r_issue_rate
PARAMS ((void));
77 static void m32r_select_section
PARAMS ((tree
, int, unsigned HOST_WIDE_INT
));
78 static void m32r_encode_section_info
PARAMS ((tree
, int));
79 static const char *m32r_strip_name_encoding
PARAMS ((const char *));
81 /* Initialize the GCC target structure. */
82 #undef TARGET_ATTRIBUTE_TABLE
83 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
85 #undef TARGET_ASM_ALIGNED_HI_OP
86 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
87 #undef TARGET_ASM_ALIGNED_SI_OP
88 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
90 #undef TARGET_ASM_FUNCTION_PROLOGUE
91 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
92 #undef TARGET_ASM_FUNCTION_EPILOGUE
93 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
95 #undef TARGET_SCHED_ADJUST_COST
96 #define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
97 #undef TARGET_SCHED_ADJUST_PRIORITY
98 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
99 #undef TARGET_SCHED_ISSUE_RATE
100 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
101 #undef TARGET_SCHED_VARIABLE_ISSUE
102 #define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
103 #undef TARGET_SCHED_INIT
104 #define TARGET_SCHED_INIT m32r_sched_init
105 #undef TARGET_SCHED_REORDER
106 #define TARGET_SCHED_REORDER m32r_sched_reorder
108 #undef TARGET_ENCODE_SECTION_INFO
109 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
110 #undef TARGET_STRIP_NAME_ENCODING
111 #define TARGET_STRIP_NAME_ENCODING m32r_strip_name_encoding
113 struct gcc_target targetm
= TARGET_INITIALIZER
;
115 /* Called by OVERRIDE_OPTIONS to initialize various things. */
122 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
123 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
124 m32r_punct_chars
['#'] = 1;
125 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
127 /* Provide default value if not specified. */
129 g_switch_value
= SDATA_DEFAULT_SIZE
;
131 if (strcmp (m32r_model_string
, "small") == 0)
132 m32r_model
= M32R_MODEL_SMALL
;
133 else if (strcmp (m32r_model_string
, "medium") == 0)
134 m32r_model
= M32R_MODEL_MEDIUM
;
135 else if (strcmp (m32r_model_string
, "large") == 0)
136 m32r_model
= M32R_MODEL_LARGE
;
138 error ("bad value (%s) for -mmodel switch", m32r_model_string
);
140 if (strcmp (m32r_sdata_string
, "none") == 0)
141 m32r_sdata
= M32R_SDATA_NONE
;
142 else if (strcmp (m32r_sdata_string
, "sdata") == 0)
143 m32r_sdata
= M32R_SDATA_SDATA
;
144 else if (strcmp (m32r_sdata_string
, "use") == 0)
145 m32r_sdata
= M32R_SDATA_USE
;
147 error ("bad value (%s) for -msdata switch", m32r_sdata_string
);
150 /* Vectors to keep interesting information about registers where it can easily
151 be got. We use to use the actual mode value as the bit number, but there
152 is (or may be) more than 32 modes now. Instead we use two tables: one
153 indexed by hard register number, and one indexed by mode. */
155 /* The purpose of m32r_mode_class is to shrink the range of modes so that
156 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
157 mapped into one m32r_mode_class mode. */
162 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
163 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
166 /* Modes for condition codes. */
167 #define C_MODES (1 << (int) C_MODE)
169 /* Modes for single-word and smaller quantities. */
170 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
172 /* Modes for double-word and smaller quantities. */
173 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
175 /* Modes for quad-word and smaller quantities. */
176 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
178 /* Modes for accumulators. */
179 #define A_MODES (1 << (int) A_MODE)
181 /* Value is 1 if register/mode pair is acceptable on arc. */
183 const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
185 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
186 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
187 S_MODES
, C_MODES
, A_MODES
, A_MODES
190 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
192 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
199 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
201 switch (GET_MODE_CLASS (i
))
204 case MODE_PARTIAL_INT
:
205 case MODE_COMPLEX_INT
:
206 if (GET_MODE_SIZE (i
) <= 4)
207 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
208 else if (GET_MODE_SIZE (i
) == 8)
209 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
210 else if (GET_MODE_SIZE (i
) == 16)
211 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
212 else if (GET_MODE_SIZE (i
) == 32)
213 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
215 m32r_mode_class
[i
] = 0;
218 case MODE_COMPLEX_FLOAT
:
219 if (GET_MODE_SIZE (i
) <= 4)
220 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
221 else if (GET_MODE_SIZE (i
) == 8)
222 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
223 else if (GET_MODE_SIZE (i
) == 16)
224 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
225 else if (GET_MODE_SIZE (i
) == 32)
226 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
228 m32r_mode_class
[i
] = 0;
232 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
233 we must explicitly check for them here. */
234 if (i
== (int) CCmode
)
235 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
237 m32r_mode_class
[i
] = 0;
242 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
245 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
246 else if (i
== ARG_POINTER_REGNUM
)
247 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
249 m32r_regno_reg_class
[i
] = NO_REGS
;
253 /* M32R specific attribute support.
255 interrupt - for interrupt functions
257 model - select code model used to access object
259 small: addresses use 24 bits, use bl to make calls
260 medium: addresses use 32 bits, use bl to make calls
261 large: addresses use 32 bits, use seth/add3/jl to make calls
263 Grep for MODEL in m32r.h for more info.
266 static tree small_ident1
;
267 static tree small_ident2
;
268 static tree medium_ident1
;
269 static tree medium_ident2
;
270 static tree large_ident1
;
271 static tree large_ident2
;
274 init_idents
PARAMS ((void))
276 if (small_ident1
== 0)
278 small_ident1
= get_identifier ("small");
279 small_ident2
= get_identifier ("__small__");
280 medium_ident1
= get_identifier ("medium");
281 medium_ident2
= get_identifier ("__medium__");
282 large_ident1
= get_identifier ("large");
283 large_ident2
= get_identifier ("__large__");
287 const struct attribute_spec m32r_attribute_table
[] =
289 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
290 { "interrupt", 0, 0, true, false, false, NULL
},
291 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
},
292 { NULL
, 0, 0, false, false, false, NULL
}
296 /* Handle an "model" attribute; arguments as in
297 struct attribute_spec.handler. */
299 m32r_handle_model_attribute (node
, name
, args
, flags
, no_add_attrs
)
300 tree
*node ATTRIBUTE_UNUSED
;
303 int flags ATTRIBUTE_UNUSED
;
309 arg
= TREE_VALUE (args
);
311 if (arg
!= small_ident1
312 && arg
!= small_ident2
313 && arg
!= medium_ident1
314 && arg
!= medium_ident2
315 && arg
!= large_ident1
316 && arg
!= large_ident2
)
318 warning ("invalid argument of `%s' attribute",
319 IDENTIFIER_POINTER (name
));
320 *no_add_attrs
= true;
326 /* A C statement or statements to switch to the appropriate
327 section for output of DECL. DECL is either a `VAR_DECL' node
328 or a constant of some sort. RELOC indicates whether forming
329 the initial value of DECL requires link-time relocations. */
332 m32r_select_section (decl
, reloc
, align
)
335 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
;
337 if (TREE_CODE (decl
) == STRING_CST
)
339 if (! flag_writable_strings
)
340 readonly_data_section ();
344 else if (TREE_CODE (decl
) == VAR_DECL
)
346 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl
), 0), 0)))
348 else if ((flag_pic
&& reloc
)
349 || !TREE_READONLY (decl
)
350 || TREE_SIDE_EFFECTS (decl
)
351 || !DECL_INITIAL (decl
)
352 || (DECL_INITIAL (decl
) != error_mark_node
353 && !TREE_CONSTANT (DECL_INITIAL (decl
))))
356 readonly_data_section ();
359 readonly_data_section ();
362 /* Encode section information of DECL, which is either a VAR_DECL,
363 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
365 For the M32R we want to record:
367 - whether the object lives in .sdata/.sbss.
368 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
370 - what code model should be used to access the object
371 small: recorded with no flag - for space efficiency since they'll
373 medium: prefixed with MEDIUM_FLAG_CHAR
374 large: prefixed with LARGE_FLAG_CHAR
378 m32r_encode_section_info (decl
, first
)
388 switch (TREE_CODE (decl
))
392 model
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
396 /* ??? document all others that can appear here */
401 /* Only mark the object as being small data area addressable if
402 it hasn't been explicitly marked with a code model.
404 The user can explicitly put an object in the small data area with the
405 section attribute. If the object is in sdata/sbss and marked with a
406 code model do both [put the object in .sdata and mark it as being
407 addressed with a specific code model - don't mark it as being addressed
408 with an SDA reloc though]. This is ok and might be useful at times. If
409 the object doesn't fit the linker will give an error. */
413 if (TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd'
414 && DECL_SECTION_NAME (decl
) != NULL_TREE
)
416 char *name
= (char *) TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
417 if (! strcmp (name
, ".sdata") || ! strcmp (name
, ".sbss"))
419 #if 0 /* ??? There's no reason to disallow this, is there? */
420 if (TREE_READONLY (decl
))
421 error_with_decl (decl
, "const objects cannot go in .sdata/.sbss");
423 prefix
= SDATA_FLAG_CHAR
;
428 if (TREE_CODE (decl
) == VAR_DECL
429 && ! TREE_READONLY (decl
)
430 && ! TARGET_SDATA_NONE
)
432 int size
= int_size_in_bytes (TREE_TYPE (decl
));
434 if (size
> 0 && size
<= g_switch_value
)
435 prefix
= SDATA_FLAG_CHAR
;
440 /* If data area not decided yet, check for a code model. */
449 id
= TREE_VALUE (TREE_VALUE (model
));
451 if (id
== small_ident1
|| id
== small_ident2
)
452 ; /* don't mark the symbol specially */
453 else if (id
== medium_ident1
|| id
== medium_ident2
)
454 prefix
= MEDIUM_FLAG_CHAR
;
455 else if (id
== large_ident1
|| id
== large_ident2
)
456 prefix
= LARGE_FLAG_CHAR
;
458 abort (); /* shouldn't happen */
462 if (TARGET_MODEL_SMALL
)
463 ; /* don't mark the symbol specially */
464 else if (TARGET_MODEL_MEDIUM
)
465 prefix
= MEDIUM_FLAG_CHAR
;
466 else if (TARGET_MODEL_LARGE
)
467 prefix
= LARGE_FLAG_CHAR
;
469 abort (); /* shouldn't happen */
475 rtx rtl
= (TREE_CODE_CLASS (TREE_CODE (decl
)) != 'd'
476 ? TREE_CST_RTL (decl
) : DECL_RTL (decl
));
477 const char *str
= XSTR (XEXP (rtl
, 0), 0);
478 int len
= strlen (str
);
479 char *newstr
= ggc_alloc (len
+ 2);
481 strcpy (newstr
+ 1, str
);
483 /* Note - we cannot leave the string in the ggc_alloc'ed space.
484 It must reside in the stringtable's domain. */
485 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 2);
487 XSTR (XEXP (rtl
, 0), 0) = newstr
;
491 /* Undo the effects of the above. */
494 m32r_strip_name_encoding (str
)
497 str
+= ENCODED_NAME_P (str
);
502 /* Do anything needed before RTL is emitted for each function. */
505 m32r_init_expanders ()
507 /* ??? At one point there was code here. The function is left in
508 to make it easy to experiment. */
511 /* Acceptable arguments to the call insn. */
514 call_address_operand (op
, mode
)
516 enum machine_mode mode
;
518 return symbolic_operand (op
, mode
);
520 /* Constants and values in registers are not OK, because
521 the m32r BL instruction can only support PC relative branching. */
525 call_operand (op
, mode
)
527 enum machine_mode mode
;
529 if (GET_CODE (op
) != MEM
)
532 return call_address_operand (op
, mode
);
535 /* Returns 1 if OP is a symbol reference. */
538 symbolic_operand (op
, mode
)
540 enum machine_mode mode ATTRIBUTE_UNUSED
;
542 switch (GET_CODE (op
))
554 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
557 small_data_operand (op
, mode
)
559 enum machine_mode mode ATTRIBUTE_UNUSED
;
561 if (! TARGET_SDATA_USE
)
564 if (GET_CODE (op
) == SYMBOL_REF
)
565 return SDATA_NAME_P (XSTR (op
, 0));
567 if (GET_CODE (op
) == CONST
568 && GET_CODE (XEXP (op
, 0)) == PLUS
569 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
570 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
571 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
572 return SDATA_NAME_P (XSTR (XEXP (XEXP (op
, 0), 0), 0));
577 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
580 addr24_operand (op
, mode
)
582 enum machine_mode mode ATTRIBUTE_UNUSED
;
584 if (GET_CODE (op
) == LABEL_REF
)
585 return TARGET_ADDR24
;
587 if (GET_CODE (op
) == SYMBOL_REF
)
588 return (SMALL_NAME_P (XSTR (op
, 0))
590 && (CONSTANT_POOL_ADDRESS_P (op
)
591 || LIT_NAME_P (XSTR (op
, 0)))));
593 if (GET_CODE (op
) == CONST
594 && GET_CODE (XEXP (op
, 0)) == PLUS
595 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
596 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
597 && UINT24_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
599 rtx sym
= XEXP (XEXP (op
, 0), 0);
600 return (SMALL_NAME_P (XSTR (sym
, 0))
602 && (CONSTANT_POOL_ADDRESS_P (op
)
603 || LIT_NAME_P (XSTR (op
, 0)))));
609 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
612 addr32_operand (op
, mode
)
614 enum machine_mode mode
;
616 if (GET_CODE (op
) == LABEL_REF
)
617 return TARGET_ADDR32
;
619 if (GET_CODE (op
) == SYMBOL_REF
)
620 return (! addr24_operand (op
, mode
)
621 && ! small_data_operand (op
, mode
));
623 if (GET_CODE (op
) == CONST
624 && GET_CODE (XEXP (op
, 0)) == PLUS
625 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
626 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
628 return (! addr24_operand (op
, mode
)
629 && ! small_data_operand (op
, mode
));
635 /* Return 1 if OP is a function that can be called with the `bl' insn. */
638 call26_operand (op
, mode
)
640 enum machine_mode mode ATTRIBUTE_UNUSED
;
642 if (GET_CODE (op
) == SYMBOL_REF
)
643 return ! LARGE_NAME_P (XSTR (op
, 0));
645 return TARGET_CALL26
;
648 /* Returns 1 if OP is an acceptable operand for seth/add3. */
651 seth_add3_operand (op
, mode
)
653 enum machine_mode mode ATTRIBUTE_UNUSED
;
655 if (GET_CODE (op
) == SYMBOL_REF
656 || GET_CODE (op
) == LABEL_REF
)
659 if (GET_CODE (op
) == CONST
660 && GET_CODE (XEXP (op
, 0)) == PLUS
661 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
662 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
663 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
669 /* Return true if OP is a signed 8 bit immediate value. */
672 int8_operand (op
, mode
)
674 enum machine_mode mode ATTRIBUTE_UNUSED
;
676 if (GET_CODE (op
) != CONST_INT
)
678 return INT8_P (INTVAL (op
));
681 /* Return true if OP is a signed 16 bit immediate value
682 useful in comparisons. */
685 cmp_int16_operand (op
, mode
)
687 enum machine_mode mode ATTRIBUTE_UNUSED
;
689 if (GET_CODE (op
) != CONST_INT
)
691 return CMP_INT16_P (INTVAL (op
));
694 /* Return true if OP is an unsigned 16 bit immediate value. */
697 uint16_operand (op
, mode
)
699 enum machine_mode mode ATTRIBUTE_UNUSED
;
701 if (GET_CODE (op
) != CONST_INT
)
703 return UINT16_P (INTVAL (op
));
706 /* Return true if OP is a register or signed 16 bit value. */
709 reg_or_int16_operand (op
, mode
)
711 enum machine_mode mode
;
713 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
714 return register_operand (op
, mode
);
715 if (GET_CODE (op
) != CONST_INT
)
717 return INT16_P (INTVAL (op
));
720 /* Return true if OP is a register or an unsigned 16 bit value. */
723 reg_or_uint16_operand (op
, mode
)
725 enum machine_mode mode
;
727 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
728 return register_operand (op
, mode
);
729 if (GET_CODE (op
) != CONST_INT
)
731 return UINT16_P (INTVAL (op
));
734 /* Return true if OP is a register or an integer value that can be
735 used is SEQ/SNE. We can use either XOR of the value or ADD of
736 the negative of the value for the constant. Don't allow 0,
737 because that is special cased. */
740 reg_or_eq_int16_operand (op
, mode
)
742 enum machine_mode mode
;
746 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
747 return register_operand (op
, mode
);
749 if (GET_CODE (op
) != CONST_INT
)
753 return (value
!= 0) && (UINT16_P (value
) || CMP_INT16_P (-value
));
756 /* Return true if OP is a register or signed 16 bit value for compares. */
759 reg_or_cmp_int16_operand (op
, mode
)
761 enum machine_mode mode
;
763 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
764 return register_operand (op
, mode
);
765 if (GET_CODE (op
) != CONST_INT
)
767 return CMP_INT16_P (INTVAL (op
));
770 /* Return true if OP is a register or the constant 0. */
773 reg_or_zero_operand (op
, mode
)
775 enum machine_mode mode
;
777 if (GET_CODE (op
) == REG
|| GET_CODE (op
) == SUBREG
)
778 return register_operand (op
, mode
);
780 if (GET_CODE (op
) != CONST_INT
)
783 return INTVAL (op
) == 0;
786 /* Return true if OP is a const_int requiring two instructions to load. */
789 two_insn_const_operand (op
, mode
)
791 enum machine_mode mode ATTRIBUTE_UNUSED
;
793 if (GET_CODE (op
) != CONST_INT
)
795 if (INT16_P (INTVAL (op
))
796 || UINT24_P (INTVAL (op
))
797 || UPPER16_P (INTVAL (op
)))
802 /* Return true if OP is an acceptable argument for a single word
806 move_src_operand (op
, mode
)
808 enum machine_mode mode
;
810 switch (GET_CODE (op
))
814 return addr24_operand (op
, mode
);
816 /* ??? We allow more cse opportunities if we only allow constants
817 loadable with one insn, and split the rest into two. The instances
818 where this would help should be rare and the current way is
820 if (HOST_BITS_PER_WIDE_INT
> 32)
822 HOST_WIDE_INT rest
= INTVAL (op
) >> 31;
823 return (rest
== 0 || rest
== -1);
828 return TARGET_ADDR24
;
832 else if (mode
== SImode
)
834 /* Large unsigned constants are represented as const_double's. */
835 unsigned HOST_WIDE_INT low
, high
;
837 low
= CONST_DOUBLE_LOW (op
);
838 high
= CONST_DOUBLE_HIGH (op
);
839 return high
== 0 && low
<= 0xffffffff;
844 return register_operand (op
, mode
);
846 /* (subreg (mem ...) ...) can occur here if the inner part was once a
847 pseudo-reg and is now a stack slot. */
848 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
849 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
851 return register_operand (op
, mode
);
853 if (GET_CODE (XEXP (op
, 0)) == PRE_INC
854 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
)
855 return 0; /* loads can't do pre-{inc,dec} */
856 return address_operand (XEXP (op
, 0), mode
);
862 /* Return true if OP is an acceptable argument for a double word
866 move_double_src_operand (op
, mode
)
868 enum machine_mode mode
;
870 switch (GET_CODE (op
))
876 return register_operand (op
, mode
);
878 /* (subreg (mem ...) ...) can occur here if the inner part was once a
879 pseudo-reg and is now a stack slot. */
880 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
881 return move_double_src_operand (SUBREG_REG (op
), mode
);
883 return register_operand (op
, mode
);
885 /* Disallow auto inc/dec for now. */
886 if (GET_CODE (XEXP (op
, 0)) == PRE_DEC
887 || GET_CODE (XEXP (op
, 0)) == PRE_INC
)
889 return address_operand (XEXP (op
, 0), mode
);
895 /* Return true if OP is an acceptable argument for a move destination. */
898 move_dest_operand (op
, mode
)
900 enum machine_mode mode
;
902 switch (GET_CODE (op
))
905 return register_operand (op
, mode
);
907 /* (subreg (mem ...) ...) can occur here if the inner part was once a
908 pseudo-reg and is now a stack slot. */
909 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
910 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
912 return register_operand (op
, mode
);
914 if (GET_CODE (XEXP (op
, 0)) == POST_INC
)
915 return 0; /* stores can't do post inc */
916 return address_operand (XEXP (op
, 0), mode
);
922 /* Return 1 if OP is a DImode const we want to handle inline.
923 This must match the code in the movdi pattern.
924 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
930 rtx high_rtx
, low_rtx
;
931 HOST_WIDE_INT high
, low
;
933 split_double (op
, &high_rtx
, &low_rtx
);
934 high
= INTVAL (high_rtx
);
935 low
= INTVAL (low_rtx
);
936 /* Pick constants loadable with 2 16 bit `ldi' insns. */
937 if (high
>= -128 && high
<= 127
938 && low
>= -128 && low
<= 127)
943 /* Return 1 if OP is a DFmode const we want to handle inline.
944 This must match the code in the movdf pattern.
945 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
954 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
955 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
956 if (l
[0] == 0 && l
[1] == 0)
958 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
963 /* Return 1 if OP is an EQ or NE comparison operator. */
966 eqne_comparison_operator (op
, mode
)
968 enum machine_mode mode ATTRIBUTE_UNUSED
;
970 enum rtx_code code
= GET_CODE (op
);
972 if (GET_RTX_CLASS (code
) != '<')
974 return (code
== EQ
|| code
== NE
);
977 /* Return 1 if OP is a signed comparison operator. */
980 signed_comparison_operator (op
, mode
)
982 enum machine_mode mode ATTRIBUTE_UNUSED
;
984 enum rtx_code code
= GET_CODE (op
);
986 if (GET_RTX_CLASS (code
) != '<')
988 return (code
== EQ
|| code
== NE
989 || code
== LT
|| code
== LE
|| code
== GT
|| code
== GE
);
992 /* Return 1 if OP is (mem (reg ...)).
993 This is used in insn length calcs. */
996 memreg_operand (op
, mode
)
998 enum machine_mode mode ATTRIBUTE_UNUSED
;
1000 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == REG
;
1003 /* Return true if OP is an acceptable input argument for a zero/sign extend
1007 extend_operand (op
, mode
)
1009 enum machine_mode mode
;
1013 switch (GET_CODE (op
))
1017 return register_operand (op
, mode
);
1020 addr
= XEXP (op
, 0);
1021 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1022 return 0; /* loads can't do pre inc/pre dec */
1024 return address_operand (addr
, mode
);
1031 /* Return non-zero if the operand is an insn that is a small insn.
1032 Allow const_int 0 as well, which is a placeholder for NOP slots. */
1035 small_insn_p (op
, mode
)
1037 enum machine_mode mode ATTRIBUTE_UNUSED
;
1039 if (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
1045 return get_attr_length (op
) == 2;
1048 /* Return non-zero if the operand is an insn that is a large insn. */
1051 large_insn_p (op
, mode
)
1053 enum machine_mode mode ATTRIBUTE_UNUSED
;
1058 return get_attr_length (op
) != 2;
1064 /* X and Y are two things to compare using CODE. Emit the compare insn and
1065 return the rtx for compare [arg0 of the if_then_else].
1066 If need_compare is true then the comparison insn must be generated, rather
1067 than being susummed into the following branch instruction. */
1070 gen_compare (code
, x
, y
, need_compare
)
1075 enum rtx_code compare_code
, branch_code
;
1076 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
1081 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
1082 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
1083 case LT
: compare_code
= LT
; branch_code
= NE
; break;
1084 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
1085 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
1086 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
1087 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
1088 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
1089 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
1090 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
1098 switch (compare_code
)
1101 if (GET_CODE (y
) == CONST_INT
1102 && CMP_INT16_P (INTVAL (y
)) /* reg equal to small const. */
1105 rtx tmp
= gen_reg_rtx (SImode
);
1107 emit_insn (gen_cmp_ne_small_const_insn (tmp
, x
, y
));
1111 else if (CONSTANT_P (y
)) /* reg equal to const. */
1113 rtx tmp
= force_reg (GET_MODE (x
), y
);
1117 if (register_operand (y
, SImode
) /* reg equal to reg. */
1118 || y
== const0_rtx
) /* req equal to zero. */
1120 emit_insn (gen_cmp_eqsi_insn (x
, y
));
1122 return gen_rtx (code
, CCmode
, cc_reg
, const0_rtx
);
1127 if (register_operand (y
, SImode
)
1128 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
1130 rtx tmp
= gen_reg_rtx (SImode
); /* reg compared to reg. */
1135 emit_insn (gen_cmp_ltsi_insn (x
, y
));
1139 if (y
== const0_rtx
)
1142 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1143 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
1147 if (GET_CODE (y
) == CONST_INT
)
1148 tmp
= gen_rtx (PLUS
, SImode
, y
, const1_rtx
);
1150 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1151 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
1155 emit_insn (gen_cmp_ltsi_insn (x
, y
));
1162 return gen_rtx (code
, CCmode
, cc_reg
, const0_rtx
);
1167 if (register_operand (y
, SImode
)
1168 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
1170 rtx tmp
= gen_reg_rtx (SImode
); /* reg (unsigned) compared to reg. */
1175 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1179 if (y
== const0_rtx
)
1182 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1183 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1187 if (GET_CODE (y
) == CONST_INT
)
1188 tmp
= gen_rtx (PLUS
, SImode
, y
, const1_rtx
);
1190 emit_insn (gen_cmp_ne_small_const_insn (tmp
, y
, const1_rtx
));
1191 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
1195 emit_insn (gen_cmp_ltusi_insn (x
, y
));
1202 return gen_rtx (code
, CCmode
, cc_reg
, const0_rtx
);
1212 /* reg/reg equal comparison */
1213 if (compare_code
== EQ
1214 && register_operand (y
, SImode
))
1215 return gen_rtx (code
, CCmode
, x
, y
);
1217 /* reg/zero signed comparison */
1218 if ((compare_code
== EQ
|| compare_code
== LT
)
1220 return gen_rtx (code
, CCmode
, x
, y
);
1222 /* reg/smallconst equal comparison */
1223 if (compare_code
== EQ
1224 && GET_CODE (y
) == CONST_INT
1225 && CMP_INT16_P (INTVAL (y
)))
1227 rtx tmp
= gen_reg_rtx (SImode
);
1228 emit_insn (gen_cmp_ne_small_const_insn (tmp
, x
, y
));
1229 return gen_rtx (code
, CCmode
, tmp
, const0_rtx
);
1232 /* reg/const equal comparison */
1233 if (compare_code
== EQ
1236 rtx tmp
= force_reg (GET_MODE (x
), y
);
1237 return gen_rtx (code
, CCmode
, x
, tmp
);
1244 y
= force_reg (GET_MODE (x
), y
);
1248 (code
== LTU
|| code
== LEU
|| code
== GTU
|| code
== GEU
)
1249 ? uint16_operand (y
, GET_MODE (y
))
1250 : reg_or_cmp_int16_operand (y
, GET_MODE (y
));
1253 y
= force_reg (GET_MODE (x
), y
);
1257 switch (compare_code
)
1260 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1263 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1266 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
1273 return gen_rtx (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
1276 /* Split a 2 word move (DI or DF) into component parts. */
1279 gen_split_move_double (operands
)
1282 enum machine_mode mode
= GET_MODE (operands
[0]);
1283 rtx dest
= operands
[0];
1284 rtx src
= operands
[1];
1287 /* We might have (SUBREG (MEM)) here, so just get rid of the
1288 subregs to make this code simpler. It is safe to call
1289 alter_subreg any time after reload. */
1290 if (GET_CODE (dest
) == SUBREG
)
1291 alter_subreg (&dest
);
1292 if (GET_CODE (src
) == SUBREG
)
1293 alter_subreg (&src
);
1296 if (GET_CODE (dest
) == REG
)
1298 int dregno
= REGNO (dest
);
1301 if (GET_CODE (src
) == REG
)
1303 int sregno
= REGNO (src
);
1305 int reverse
= (dregno
== sregno
+ 1);
1307 /* We normally copy the low-numbered register first. However, if
1308 the first register operand 0 is the same as the second register of
1309 operand 1, we must copy in the opposite order. */
1310 emit_insn (gen_rtx_SET (VOIDmode
,
1311 operand_subword (dest
, reverse
, TRUE
, mode
),
1312 operand_subword (src
, reverse
, TRUE
, mode
)));
1314 emit_insn (gen_rtx_SET (VOIDmode
,
1315 operand_subword (dest
, !reverse
, TRUE
, mode
),
1316 operand_subword (src
, !reverse
, TRUE
, mode
)));
1319 /* reg = constant */
1320 else if (GET_CODE (src
) == CONST_INT
|| GET_CODE (src
) == CONST_DOUBLE
)
1323 split_double (src
, &words
[0], &words
[1]);
1324 emit_insn (gen_rtx_SET (VOIDmode
,
1325 operand_subword (dest
, 0, TRUE
, mode
),
1328 emit_insn (gen_rtx_SET (VOIDmode
,
1329 operand_subword (dest
, 1, TRUE
, mode
),
1334 else if (GET_CODE (src
) == MEM
)
1336 /* If the high-address word is used in the address, we must load it
1337 last. Otherwise, load it first. */
1339 = (refers_to_regno_p (dregno
, dregno
+ 1, XEXP (src
, 0), 0) != 0);
1341 /* We used to optimize loads from single registers as
1345 if r3 were not used subsequently. However, the REG_NOTES aren't
1346 propigated correctly by the reload phase, and it can cause bad
1347 code to be generated. We could still try:
1349 ld r1,r3+; ld r2,r3; addi r3,-4
1351 which saves 2 bytes and doesn't force longword alignment. */
1352 emit_insn (gen_rtx_SET (VOIDmode
,
1353 operand_subword (dest
, reverse
, TRUE
, mode
),
1354 adjust_address (src
, SImode
,
1355 reverse
* UNITS_PER_WORD
)));
1357 emit_insn (gen_rtx_SET (VOIDmode
,
1358 operand_subword (dest
, !reverse
, TRUE
, mode
),
1359 adjust_address (src
, SImode
,
1360 !reverse
* UNITS_PER_WORD
)));
1368 /* We used to optimize loads from single registers as
1372 if r3 were not used subsequently. However, the REG_NOTES aren't
1373 propigated correctly by the reload phase, and it can cause bad
1374 code to be generated. We could still try:
1376 st r1,r3; st r2,+r3; addi r3,-4
1378 which saves 2 bytes and doesn't force longword alignment. */
1379 else if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
1381 emit_insn (gen_rtx_SET (VOIDmode
,
1382 adjust_address (dest
, SImode
, 0),
1383 operand_subword (src
, 0, TRUE
, mode
)));
1385 emit_insn (gen_rtx_SET (VOIDmode
,
1386 adjust_address (dest
, SImode
, UNITS_PER_WORD
),
1387 operand_subword (src
, 1, TRUE
, mode
)));
1393 val
= gen_sequence ();
1399 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1402 function_arg_partial_nregs (cum
, mode
, type
, named
)
1403 CUMULATIVE_ARGS
*cum
;
1404 enum machine_mode mode
;
1406 int named ATTRIBUTE_UNUSED
;
1410 (((mode
== BLKmode
&& type
)
1411 ? (unsigned int) int_size_in_bytes (type
)
1412 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1415 if (*cum
>= M32R_MAX_PARM_REGS
)
1417 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1418 ret
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1425 /* Do any needed setup for a variadic function. For the M32R, we must
1426 create a register parameter block, and then copy any anonymous arguments
1427 in registers to memory.
1429 CUM has not been updated for the last named argument which has type TYPE
1430 and mode MODE, and we rely on this fact. */
1433 m32r_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
1434 CUMULATIVE_ARGS
*cum
;
1435 enum machine_mode mode
;
1445 /* All BLKmode values are passed by reference. */
1446 if (mode
== BLKmode
)
1449 /* We must treat `__builtin_va_alist' as an anonymous arg. */
1450 if (current_function_varargs
)
1451 first_anon_arg
= *cum
;
1453 first_anon_arg
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1454 + ROUND_ADVANCE_ARG (mode
, type
));
1456 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1458 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1459 int first_reg_offset
= first_anon_arg
;
1460 /* Size in words to "pretend" allocate. */
1461 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1464 regblock
= gen_rtx_MEM (BLKmode
,
1465 plus_constant (arg_pointer_rtx
,
1466 FIRST_PARM_OFFSET (0)));
1467 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1468 move_block_from_reg (first_reg_offset
, regblock
,
1469 size
, size
* UNITS_PER_WORD
);
1471 *pretend_size
= (size
* UNITS_PER_WORD
);
1476 /* Implement `va_arg'. */
1479 m32r_va_arg (valist
, type
)
1482 HOST_WIDE_INT size
, rsize
;
1486 size
= int_size_in_bytes (type
);
1487 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
1491 tree type_ptr
, type_ptr_ptr
;
1493 /* Pass by reference. */
1495 type_ptr
= build_pointer_type (type
);
1496 type_ptr_ptr
= build_pointer_type (type_ptr
);
1498 t
= build (POSTINCREMENT_EXPR
, va_list_type_node
, valist
,
1499 build_int_2 (UNITS_PER_WORD
, 0));
1500 TREE_SIDE_EFFECTS (t
) = 1;
1501 t
= build1 (NOP_EXPR
, type_ptr_ptr
, t
);
1502 TREE_SIDE_EFFECTS (t
) = 1;
1503 t
= build1 (INDIRECT_REF
, type_ptr
, t
);
1505 addr_rtx
= expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1509 /* Pass by value. */
1511 if (size
< UNITS_PER_WORD
)
1513 /* Care for bigendian correction on the aligned address. */
1514 t
= build (PLUS_EXPR
, ptr_type_node
, valist
,
1515 build_int_2 (rsize
- size
, 0));
1516 addr_rtx
= expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1517 addr_rtx
= copy_to_reg (addr_rtx
);
1520 t
= build (PLUS_EXPR
, va_list_type_node
, valist
,
1521 build_int_2 (rsize
, 0));
1522 t
= build (MODIFY_EXPR
, va_list_type_node
, valist
, t
);
1523 TREE_SIDE_EFFECTS (t
) = 1;
1524 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
1528 t
= build (POSTINCREMENT_EXPR
, va_list_type_node
, valist
,
1529 build_int_2 (rsize
, 0));
1530 TREE_SIDE_EFFECTS (t
) = 1;
1531 addr_rtx
= expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1539 m32r_adjust_cost (insn
, link
, dep_insn
, cost
)
1540 rtx insn ATTRIBUTE_UNUSED
;
1541 rtx link ATTRIBUTE_UNUSED
;
1542 rtx dep_insn ATTRIBUTE_UNUSED
;
1549 /* Return true if INSN is real instruction bearing insn. */
1555 return (INSN_P (insn
)
1556 && GET_CODE (PATTERN (insn
)) != USE
1557 && GET_CODE (PATTERN (insn
)) != CLOBBER
1558 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
);
1561 /* Increase the priority of long instructions so that the
1562 short instructions are scheduled ahead of the long ones. */
1565 m32r_adjust_priority (insn
, priority
)
1569 if (m32r_is_insn (insn
)
1570 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1577 /* Initialize for scheduling a group of instructions. */
1580 m32r_sched_init (stream
, verbose
, max_ready
)
1581 FILE * stream ATTRIBUTE_UNUSED
;
1582 int verbose ATTRIBUTE_UNUSED
;
1583 int max_ready ATTRIBUTE_UNUSED
;
1585 m32r_sched_odd_word_p
= FALSE
;
1589 /* Reorder the schedulers priority list if needed */
1592 m32r_sched_reorder (stream
, verbose
, ready
, n_readyp
, clock
)
1597 int clock ATTRIBUTE_UNUSED
;
1599 int n_ready
= *n_readyp
;
1602 return m32r_issue_rate ();
1609 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1611 (m32r_sched_odd_word_p
) ? "odd" : "even");
1615 rtx
* long_head
= (rtx
*) alloca (sizeof (rtx
) * n_ready
);
1616 rtx
* long_tail
= long_head
;
1617 rtx
* short_head
= (rtx
*) alloca (sizeof (rtx
) * n_ready
);
1618 rtx
* short_tail
= short_head
;
1619 rtx
* new_head
= (rtx
*) alloca (sizeof (rtx
) * n_ready
);
1620 rtx
* new_tail
= new_head
+ (n_ready
- 1);
1623 /* Loop through the instructions, classifing them as short/long. Try
1624 to keep 2 short together and/or 1 long. Note, the ready list is
1625 actually ordered backwards, so keep it in that manner. */
1626 for (i
= n_ready
-1; i
>= 0; i
--)
1628 rtx insn
= ready
[i
];
1630 if (! m32r_is_insn (insn
))
1632 /* Dump all current short/long insns just in case. */
1633 while (long_head
!= long_tail
)
1634 *new_tail
-- = *long_head
++;
1636 while (short_head
!= short_tail
)
1637 *new_tail
-- = *short_head
++;
1642 ";;\t\t::: Skipping non instruction %d\n",
1649 if (get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1650 *long_tail
++ = insn
;
1653 *short_tail
++ = insn
;
1657 /* If we are on an odd word, emit a single short instruction if
1659 if (m32r_sched_odd_word_p
&& short_head
!= short_tail
)
1660 *new_tail
-- = *short_head
++;
1662 /* Now dump out all of the long instructions */
1663 while (long_head
!= long_tail
)
1664 *new_tail
-- = *long_head
++;
1666 /* Now dump out all of the short instructions */
1667 while (short_head
!= short_tail
)
1668 *new_tail
-- = *short_head
++;
1670 if (new_tail
+1 != new_head
)
1673 memcpy (ready
, new_head
, sizeof (rtx
) * n_ready
);
1677 fprintf (stream
, ";;\t\t::: New ready list: ");
1678 for (i
= 0; i
< n_ready
; i
++)
1680 rtx insn
= ready
[i
];
1682 fprintf (stream
, " %d", INSN_UID (ready
[i
]));
1684 if (! m32r_is_insn (insn
))
1685 fputs ("(?)", stream
);
1687 else if (get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1688 fputs ("(l)", stream
);
1691 fputs ("(s)", stream
);
1694 fprintf (stream
, "\n");
1697 return m32r_issue_rate ();
1700 /* Indicate how many instructions can be issued at the same time.
1701 This is sort of a lie. The m32r can issue only 1 long insn at
1702 once, but it can issue 2 short insns. The default therefore is
1703 set at 2, but this can be overridden by the command line option
1708 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1711 /* If we have a machine that can issue a variable # of instructions
1712 per cycle, indicate how many more instructions can be issued
1713 after the current one. */
1715 m32r_variable_issue (stream
, verbose
, insn
, how_many
)
1721 int orig_odd_word_p
= m32r_sched_odd_word_p
;
1722 int short_p
= FALSE
;
1725 if (how_many
> 0 && !TARGET_DEBUG
)
1727 if (! m32r_is_insn (insn
))
1730 else if (get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1733 m32r_sched_odd_word_p
= 0;
1737 m32r_sched_odd_word_p
= !m32r_sched_odd_word_p
;
1742 if (verbose
> 7 && stream
)
1744 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1745 short_p
? "short" : "long",
1747 orig_odd_word_p
? "odd" : "even",
1753 /* Cost functions. */
1755 /* Provide the costs of an addressing mode that contains ADDR.
1756 If ADDR is not a valid address, its cost is irrelevant.
1758 This function is trivial at the moment. This code doesn't live
1759 in m32r.h so it's easy to experiment. */
1762 m32r_address_cost (addr
)
1763 rtx addr ATTRIBUTE_UNUSED
;
1768 /* Type of function DECL.
1770 The result is cached. To reset the cache at the end of a function,
1771 call with DECL = NULL_TREE. */
1773 enum m32r_function_type
1774 m32r_compute_function_type (decl
)
1778 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1779 /* Last function we were called for. */
1780 static tree last_fn
= NULL_TREE
;
1782 /* Resetting the cached value? */
1783 if (decl
== NULL_TREE
)
1785 fn_type
= M32R_FUNCTION_UNKNOWN
;
1786 last_fn
= NULL_TREE
;
1790 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1793 /* Compute function type. */
1794 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1795 ? M32R_FUNCTION_INTERRUPT
1796 : M32R_FUNCTION_NORMAL
);
1801 \f/* Function prologue/epilogue handlers. */
1803 /* M32R stack frames look like:
1805 Before call After call
1806 +-----------------------+ +-----------------------+
1808 high | local variables, | | local variables, |
1809 mem | reg save area, etc. | | reg save area, etc. |
1811 +-----------------------+ +-----------------------+
1813 | arguments on stack. | | arguments on stack. |
1815 SP+0->+-----------------------+ +-----------------------+
1816 | reg parm save area, |
1817 | only created for |
1818 | variable argument |
1820 +-----------------------+
1821 | previous frame ptr |
1822 +-----------------------+
1824 | register save area |
1826 +-----------------------+
1828 +-----------------------+
1832 +-----------------------+
1834 | alloca allocations |
1836 +-----------------------+
1838 low | arguments on stack |
1840 SP+0->+-----------------------+
1843 1) The "reg parm save area" does not exist for non variable argument fns.
1844 2) The "reg parm save area" can be eliminated completely if we saved regs
1845 containing anonymous args separately but that complicates things too
1846 much (so it's not done).
1847 3) The return address is saved after the register save area so as to have as
1848 many insns as possible between the restoration of `lr' and the `jmp lr'.
1851 /* Structure to be filled in by m32r_compute_frame_size with register
1852 save masks, and offsets for the current function. */
1853 struct m32r_frame_info
1855 unsigned int total_size
; /* # bytes that the entire frame takes up */
1856 unsigned int extra_size
; /* # bytes of extra stuff */
1857 unsigned int pretend_size
; /* # bytes we push and pretend caller did */
1858 unsigned int args_size
; /* # bytes that outgoing arguments take up */
1859 unsigned int reg_size
; /* # bytes needed to store regs */
1860 unsigned int var_size
; /* # bytes that variables take up */
1861 unsigned int gmask
; /* mask of saved gp registers */
1862 unsigned int save_fp
; /* nonzero if fp must be saved */
1863 unsigned int save_lr
; /* nonzero if lr (return addr) must be saved */
1864 int initialized
; /* nonzero if frame size already calculated */
1867 /* Current frame information calculated by m32r_compute_frame_size. */
1868 static struct m32r_frame_info current_frame_info
;
1870 /* Zero structure to initialize current_frame_info. */
1871 static struct m32r_frame_info zero_frame_info
;
1873 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1874 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1876 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1877 The return address and frame pointer are treated separately.
1878 Don't consider them here. */
1879 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1880 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1881 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1883 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1884 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1886 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1887 #define LONG_INSN_SIZE 4 /* size of long instructions */
1889 /* Return the bytes needed to compute the frame pointer from the current
1892 SIZE is the size needed for local variables. */
1895 m32r_compute_frame_size (size
)
1896 int size
; /* # of var. bytes allocated. */
1899 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1900 unsigned int reg_size
, frame_size
;
1902 enum m32r_function_type fn_type
;
1905 var_size
= M32R_STACK_ALIGN (size
);
1906 args_size
= M32R_STACK_ALIGN (current_function_outgoing_args_size
);
1907 pretend_size
= current_function_pretend_args_size
;
1908 extra_size
= FIRST_PARM_OFFSET (0);
1909 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1913 /* See if this is an interrupt handler. Call used registers must be saved
1915 fn_type
= m32r_compute_function_type (current_function_decl
);
1916 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1918 /* Calculate space needed for registers. */
1920 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1922 if (MUST_SAVE_REGISTER (regno
, interrupt_p
))
1924 reg_size
+= UNITS_PER_WORD
;
1925 gmask
|= 1 << regno
;
1929 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1930 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
;
1932 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1934 total_size
+= reg_size
;
1936 /* ??? Not sure this is necessary, and I don't think the epilogue
1937 handler will do the right thing if this changes total_size. */
1938 total_size
= M32R_STACK_ALIGN (total_size
);
1940 frame_size
= total_size
- (pretend_size
+ reg_size
);
1942 /* Save computed information. */
1943 current_frame_info
.total_size
= total_size
;
1944 current_frame_info
.extra_size
= extra_size
;
1945 current_frame_info
.pretend_size
= pretend_size
;
1946 current_frame_info
.var_size
= var_size
;
1947 current_frame_info
.args_size
= args_size
;
1948 current_frame_info
.reg_size
= reg_size
;
1949 current_frame_info
.gmask
= gmask
;
1950 current_frame_info
.initialized
= reload_completed
;
1952 /* Ok, we're done. */
1956 /* When the `length' insn attribute is used, this macro specifies the
1957 value to be assigned to the address of the first insn in a
1958 function. If not specified, 0 is used. */
1961 m32r_first_insn_address ()
1963 if (! current_frame_info
.initialized
)
1964 m32r_compute_frame_size (get_frame_size ());
1969 /* Expand the m32r prologue as a series of insns. */
1972 m32r_expand_prologue ()
1978 if (! current_frame_info
.initialized
)
1979 m32r_compute_frame_size (get_frame_size ());
1981 gmask
= current_frame_info
.gmask
;
1983 /* These cases shouldn't happen. Catch them now. */
1984 if (current_frame_info
.total_size
== 0 && gmask
)
1987 /* Allocate space for register arguments if this is a variadic function. */
1988 if (current_frame_info
.pretend_size
!= 0)
1990 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1991 the wrong result on a 64-bit host. */
1992 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1993 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1995 GEN_INT (-pretend_size
)));
1998 /* Save any registers we need to and set up fp. */
2000 if (current_frame_info
.save_fp
)
2001 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
2003 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
2005 /* Save any needed call-saved regs (and call-used if this is an
2006 interrupt handler). */
2007 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
2009 if ((gmask
& (1 << regno
)) != 0)
2010 emit_insn (gen_movsi_push (stack_pointer_rtx
,
2011 gen_rtx_REG (Pmode
, regno
)));
2014 if (current_frame_info
.save_lr
)
2015 emit_insn (gen_movsi_push (stack_pointer_rtx
,
2016 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
2018 /* Allocate the stack frame. */
2019 frame_size
= (current_frame_info
.total_size
2020 - (current_frame_info
.pretend_size
2021 + current_frame_info
.reg_size
));
2023 if (frame_size
== 0)
2024 ; /* nothing to do */
2025 else if (frame_size
<= 32768)
2026 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2027 GEN_INT (-frame_size
)));
2030 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
2031 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
2032 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
2035 if (frame_pointer_needed
)
2036 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2038 if (current_function_profile
)
2039 emit_insn (gen_blockage ());
2043 /* Set up the stack and frame pointer (if desired) for the function.
2044 Note, if this is changed, you need to mirror the changes in
2045 m32r_compute_frame_size which calculates the prolog size. */
2048 m32r_output_function_prologue (file
, size
)
2052 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
2054 /* If this is an interrupt handler, mark it as such. */
2055 if (M32R_INTERRUPT_P (fn_type
))
2057 fprintf (file
, "\t%s interrupt handler\n",
2061 if (! current_frame_info
.initialized
)
2062 m32r_compute_frame_size (size
);
2064 /* This is only for the human reader. */
2066 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2068 current_frame_info
.var_size
,
2069 current_frame_info
.reg_size
/ 4,
2070 current_frame_info
.args_size
,
2071 current_frame_info
.extra_size
);
2074 /* Do any necessary cleanup after a function to restore stack, frame,
2078 m32r_output_function_epilogue (file
, size
)
2080 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
2083 int noepilogue
= FALSE
;
2085 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
2087 /* This is only for the human reader. */
2088 fprintf (file
, "\t%s EPILOGUE\n", ASM_COMMENT_START
);
2090 if (!current_frame_info
.initialized
)
2092 total_size
= current_frame_info
.total_size
;
2094 if (total_size
== 0)
2096 rtx insn
= get_last_insn ();
2098 /* If the last insn was a BARRIER, we don't have to write any code
2099 because a jump (aka return) was put there. */
2100 if (GET_CODE (insn
) == NOTE
)
2101 insn
= prev_nonnote_insn (insn
);
2102 if (insn
&& GET_CODE (insn
) == BARRIER
)
2108 unsigned int var_size
= current_frame_info
.var_size
;
2109 unsigned int args_size
= current_frame_info
.args_size
;
2110 unsigned int gmask
= current_frame_info
.gmask
;
2111 int can_trust_sp_p
= !current_function_calls_alloca
;
2112 const char * sp_str
= reg_names
[STACK_POINTER_REGNUM
];
2113 const char * fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
2115 /* The first thing to do is point the sp at the bottom of the register
2119 unsigned int reg_offset
= var_size
+ args_size
;
2120 if (reg_offset
== 0)
2121 ; /* nothing to do */
2122 else if (reg_offset
< 128)
2123 fprintf (file
, "\taddi %s,%s%d\n",
2124 sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
2125 else if (reg_offset
< 32768)
2126 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
2127 sp_str
, sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
2129 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2130 reg_names
[PROLOGUE_TMP_REGNUM
],
2131 IMMEDIATE_PREFIX
, reg_offset
,
2132 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
2134 else if (frame_pointer_needed
)
2136 unsigned int reg_offset
= var_size
+ args_size
;
2137 if (reg_offset
== 0)
2138 fprintf (file
, "\tmv %s,%s\n", sp_str
, fp_str
);
2139 else if (reg_offset
< 32768)
2140 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
2141 sp_str
, fp_str
, IMMEDIATE_PREFIX
, reg_offset
);
2143 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2144 reg_names
[PROLOGUE_TMP_REGNUM
],
2145 IMMEDIATE_PREFIX
, reg_offset
,
2146 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
2151 if (current_frame_info
.save_lr
)
2152 fprintf (file
, "\tpop %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
2154 /* Restore any saved registers, in reverse order of course. */
2155 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
2156 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
2158 if ((gmask
& (1L << regno
)) != 0)
2159 fprintf (file
, "\tpop %s\n", reg_names
[regno
]);
2162 if (current_frame_info
.save_fp
)
2163 fprintf (file
, "\tpop %s\n", fp_str
);
2165 /* Remove varargs area if present. */
2166 if (current_frame_info
.pretend_size
!= 0)
2167 fprintf (file
, "\taddi %s,%s%d\n",
2168 sp_str
, IMMEDIATE_PREFIX
, current_frame_info
.pretend_size
);
2170 /* Emit the return instruction. */
2171 if (M32R_INTERRUPT_P (fn_type
))
2172 fprintf (file
, "\trte\n");
2174 fprintf (file
, "\tjmp %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
2177 #if 0 /* no longer needed */
2178 /* Ensure the function cleanly ends on a 32 bit boundary. */
2179 fprintf (file
, "\t.fillinsn\n");
2182 /* Reset state info for each function. */
2183 current_frame_info
= zero_frame_info
;
2184 m32r_compute_function_type (NULL_TREE
);
2187 /* Return non-zero if this function is known to have a null or 1 instruction
2193 if (!reload_completed
)
2196 if (! current_frame_info
.initialized
)
2197 m32r_compute_frame_size (get_frame_size ());
2199 return current_frame_info
.total_size
== 0;
2205 /* Emit special PIC prologues and epilogues. */
2208 m32r_finalize_pic ()
2213 /* Nested function support. */
2215 /* Emit RTL insns to initialize the variable parts of a trampoline.
2216 FNADDR is an RTX for the address of the function's pure code.
2217 CXT is an RTX for the static chain value for the function. */
2220 m32r_initialize_trampoline (tramp
, fnaddr
, cxt
)
2221 rtx tramp ATTRIBUTE_UNUSED
;
2222 rtx fnaddr ATTRIBUTE_UNUSED
;
2223 rtx cxt ATTRIBUTE_UNUSED
;
2227 /* Set the cpu type and print out other fancy things,
2228 at the top of the file. */
2231 m32r_asm_file_start (file
)
2234 if (flag_verbose_asm
)
2235 fprintf (file
, "%s M32R/D special options: -G %d\n",
2236 ASM_COMMENT_START
, g_switch_value
);
2239 /* Print operand X (an rtx) in assembler syntax to file FILE.
2240 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2241 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2244 m32r_print_operand (file
, x
, code
)
2253 /* The 's' and 'p' codes are used by output_block_move() to
2254 indicate post-increment 's'tores and 'p're-increment loads. */
2256 if (GET_CODE (x
) == REG
)
2257 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2259 output_operand_lossage ("invalid operand to %%s code");
2263 if (GET_CODE (x
) == REG
)
2264 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2266 output_operand_lossage ("invalid operand to %%p code");
2270 /* Write second word of DImode or DFmode reference,
2271 register or memory. */
2272 if (GET_CODE (x
) == REG
)
2273 fputs (reg_names
[REGNO (x
)+1], file
);
2274 else if (GET_CODE (x
) == MEM
)
2276 fprintf (file
, "@(");
2277 /* Handle possible auto-increment. Since it is pre-increment and
2278 we have already done it, we can just use an offset of four. */
2279 /* ??? This is taken from rs6000.c I think. I don't think it is
2280 currently necessary, but keep it around. */
2281 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2282 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2283 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
2285 output_address (plus_constant (XEXP (x
, 0), 4));
2289 output_operand_lossage ("invalid operand to %%R code");
2292 case 'H' : /* High word */
2293 case 'L' : /* Low word */
2294 if (GET_CODE (x
) == REG
)
2296 /* L = least significant word, H = most significant word */
2297 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2298 fputs (reg_names
[REGNO (x
)], file
);
2300 fputs (reg_names
[REGNO (x
)+1], file
);
2302 else if (GET_CODE (x
) == CONST_INT
2303 || GET_CODE (x
) == CONST_DOUBLE
)
2307 split_double (x
, &first
, &second
);
2308 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2309 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2312 output_operand_lossage ("invalid operand to %%H/%%L code");
2320 if (GET_CODE (x
) != CONST_DOUBLE
2321 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2322 fatal_insn ("bad insn for 'A'", x
);
2323 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2324 REAL_VALUE_TO_DECIMAL (d
, "%.20e", str
);
2325 fprintf (file
, "%s", str
);
2329 case 'B' : /* Bottom half */
2330 case 'T' : /* Top half */
2331 /* Output the argument to a `seth' insn (sets the Top half-word).
2332 For constants output arguments to a seth/or3 pair to set Top and
2333 Bottom halves. For symbols output arguments to a seth/add3 pair to
2334 set Top and Bottom halves. The difference exists because for
2335 constants seth/or3 is more readable but for symbols we need to use
2336 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2337 switch (GET_CODE (x
))
2344 split_double (x
, &first
, &second
);
2345 x
= WORDS_BIG_ENDIAN
? second
: first
;
2347 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2353 ? INTVAL (x
) & 0xffff
2354 : (INTVAL (x
) >> 16) & 0xffff));
2360 && small_data_operand (x
, VOIDmode
))
2362 fputs ("sda(", file
);
2363 output_addr_const (file
, x
);
2369 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2370 output_addr_const (file
, x
);
2374 output_operand_lossage ("invalid operand to %%T/%%B code");
2381 /* Output a load/store with update indicator if appropriate. */
2382 if (GET_CODE (x
) == MEM
)
2384 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2385 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2389 output_operand_lossage ("invalid operand to %%U code");
2393 /* Print a constant value negated. */
2394 if (GET_CODE (x
) == CONST_INT
)
2395 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2397 output_operand_lossage ("invalid operand to %%N code");
2401 /* Print a const_int in hex. Used in comments. */
2402 if (GET_CODE (x
) == CONST_INT
)
2404 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2413 fputs (IMMEDIATE_PREFIX
, file
);
2416 #if 0 /* ??? no longer used */
2418 fputs (reg_names
[SDA_REGNUM
], file
);
2423 /* Do nothing special. */
2428 output_operand_lossage ("invalid operand output code");
2431 switch (GET_CODE (x
))
2434 fputs (reg_names
[REGNO (x
)], file
);
2439 if (GET_CODE (addr
) == PRE_INC
)
2441 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2442 fatal_insn ("pre-increment address is not a register", x
);
2444 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2446 else if (GET_CODE (addr
) == PRE_DEC
)
2448 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2449 fatal_insn ("pre-decrement address is not a register", x
);
2451 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2453 else if (GET_CODE (addr
) == POST_INC
)
2455 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2456 fatal_insn ("post-increment address is not a register", x
);
2458 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2463 output_address (XEXP (x
, 0));
2469 /* We handle SFmode constants here as output_addr_const doesn't. */
2470 if (GET_MODE (x
) == SFmode
)
2475 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2476 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
2477 fprintf (file
, "0x%08lx", l
);
2481 /* Fall through. Let output_addr_const deal with it. */
2484 output_addr_const (file
, x
);
2489 /* Print a memory address as an operand to reference that memory location. */
2492 m32r_print_operand_address (file
, addr
)
2497 register rtx index
= 0;
2500 switch (GET_CODE (addr
))
2503 fputs (reg_names
[REGNO (addr
)], file
);
2507 if (GET_CODE (XEXP (addr
, 0)) == CONST_INT
)
2508 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2509 else if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2510 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2512 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2513 if (GET_CODE (base
) == REG
)
2515 /* Print the offset first (if present) to conform to the manual. */
2519 fprintf (file
, "%d,", offset
);
2520 fputs (reg_names
[REGNO (base
)], file
);
2522 /* The chip doesn't support this, but left in for generality. */
2523 else if (GET_CODE (index
) == REG
)
2524 fprintf (file
, "%s,%s",
2525 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2526 /* Not sure this can happen, but leave in for now. */
2527 else if (GET_CODE (index
) == SYMBOL_REF
)
2529 output_addr_const (file
, index
);
2531 fputs (reg_names
[REGNO (base
)], file
);
2534 fatal_insn ("bad address", addr
);
2536 else if (GET_CODE (base
) == LO_SUM
)
2539 || GET_CODE (XEXP (base
, 0)) != REG
)
2541 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2542 fputs ("sda(", file
);
2544 fputs ("low(", file
);
2545 output_addr_const (file
, plus_constant (XEXP (base
, 1), offset
));
2547 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2550 fatal_insn ("bad address", addr
);
2554 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2555 fatal_insn ("lo_sum not of register", addr
);
2556 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2557 fputs ("sda(", file
);
2559 fputs ("low(", file
);
2560 output_addr_const (file
, XEXP (addr
, 1));
2562 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2565 case PRE_INC
: /* Assume SImode */
2566 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2569 case PRE_DEC
: /* Assume SImode */
2570 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2573 case POST_INC
: /* Assume SImode */
2574 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2578 output_addr_const (file
, addr
);
2583 /* Return true if the operands are the constants 0 and 1. */
2585 zero_and_one (operand1
, operand2
)
2590 GET_CODE (operand1
) == CONST_INT
2591 && GET_CODE (operand2
) == CONST_INT
2592 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2593 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2596 /* Return non-zero if the operand is suitable for use in a conditional move sequence. */
2598 conditional_move_operand (operand
, mode
)
2600 enum machine_mode mode
;
2602 /* Only defined for simple integers so far... */
2603 if (mode
!= SImode
&& mode
!= HImode
&& mode
!= QImode
)
2606 /* At the moment we can hanndle moving registers and loading constants. */
2607 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2609 switch (GET_CODE (operand
))
2615 return INT8_P (INTVAL (operand
));
2619 fprintf (stderr
, "Test for cond move op of type: %s\n",
2620 GET_RTX_NAME (GET_CODE (operand
)));
2626 /* Return true if the code is a test of the carry bit */
2628 carry_compare_operand (op
, mode
)
2630 enum machine_mode mode ATTRIBUTE_UNUSED
;
2634 if (GET_MODE (op
) != CCmode
&& GET_MODE (op
) != VOIDmode
)
2637 if (GET_CODE (op
) != NE
&& GET_CODE (op
) != EQ
)
2641 if (GET_CODE (x
) != REG
|| REGNO (x
) != CARRY_REGNUM
)
2645 if (GET_CODE (x
) != CONST_INT
|| INTVAL (x
) != 0)
2651 /* Generate the correct assembler code to handle the conditional loading of a
2652 value into a register. It is known that the operands satisfy the
2653 conditional_move_operand() function above. The destination is operand[0].
2654 The condition is operand [1]. The 'true' value is operand [2] and the
2655 'false' value is operand [3]. */
2657 emit_cond_move (operands
, insn
)
2659 rtx insn ATTRIBUTE_UNUSED
;
2661 static char buffer
[100];
2662 const char * dest
= reg_names
[REGNO (operands
[0])];
2666 /* Destination must be a register. */
2667 if (GET_CODE (operands
[0]) != REG
)
2669 if (! conditional_move_operand (operands
[2], SImode
))
2671 if (! conditional_move_operand (operands
[3], SImode
))
2674 /* Check to see if the test is reversed. */
2675 if (GET_CODE (operands
[1]) == NE
)
2677 rtx tmp
= operands
[2];
2678 operands
[2] = operands
[3];
2682 sprintf (buffer
, "mvfc %s, cbr", dest
);
2684 /* If the true value was '0' then we need to invert the results of the move. */
2685 if (INTVAL (operands
[2]) == 0)
2686 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2692 /* Returns true if the registers contained in the two
2693 rtl expressions are different. */
2695 m32r_not_same_reg (a
, b
)
2702 while (GET_CODE (a
) == SUBREG
)
2705 if (GET_CODE (a
) == REG
)
2708 while (GET_CODE (b
) == SUBREG
)
2711 if (GET_CODE (b
) == REG
)
2714 return reg_a
!= reg_b
;
2718 /* Use a library function to move some bytes. */
2720 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2725 /* We want to pass the size as Pmode, which will normally be SImode
2726 but will be DImode if we are using 64 bit longs and pointers. */
2727 if (GET_MODE (bytes_rtx
) != VOIDmode
2728 && GET_MODE (bytes_rtx
) != Pmode
)
2729 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2731 #ifdef TARGET_MEM_FUNCTIONS
2732 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2733 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2734 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2735 TREE_UNSIGNED (sizetype
)),
2736 TYPE_MODE (sizetype
));
2738 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2739 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
2740 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
2741 TREE_UNSIGNED (integer_type_node
)),
2742 TYPE_MODE (integer_type_node
));
2746 /* The maximum number of bytes to copy using pairs of load/store instructions.
2747 If a block is larger than this then a loop will be generated to copy
2748 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2749 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2750 string copy in it. */
2751 #define MAX_MOVE_BYTES 32
2753 /* Expand string/block move operations.
2755 operands[0] is the pointer to the destination.
2756 operands[1] is the pointer to the source.
2757 operands[2] is the number of bytes to move.
2758 operands[3] is the alignment. */
2761 m32r_expand_block_move (operands
)
2764 rtx orig_dst
= operands
[0];
2765 rtx orig_src
= operands
[1];
2766 rtx bytes_rtx
= operands
[2];
2767 rtx align_rtx
= operands
[3];
2768 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
2769 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2770 int align
= INTVAL (align_rtx
);
2775 if (constp
&& bytes
<= 0)
2778 /* Move the address into scratch registers. */
2779 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2780 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2782 if (align
> UNITS_PER_WORD
)
2783 align
= UNITS_PER_WORD
;
2785 /* If we prefer size over speed, always use a function call.
2786 If we do not know the size, use a function call.
2787 If the blocks are not word aligned, use a function call. */
2788 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2790 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2794 leftover
= bytes
% MAX_MOVE_BYTES
;
2797 /* If necessary, generate a loop to handle the bulk of the copy. */
2800 rtx label
= NULL_RTX
;
2801 rtx final_src
= NULL_RTX
;
2802 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2803 rtx rounded_total
= GEN_INT (bytes
);
2805 /* If we are going to have to perform this loop more than
2806 once, then generate a label and compute the address the
2807 source register will contain upon completion of the final
2809 if (bytes
> MAX_MOVE_BYTES
)
2811 final_src
= gen_reg_rtx (Pmode
);
2814 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2817 emit_insn (gen_movsi (final_src
, rounded_total
));
2818 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2821 label
= gen_label_rtx ();
2825 /* It is known that output_block_move() will update src_reg to point
2826 to the word after the end of the source block, and dst_reg to point
2827 to the last word of the destination block, provided that the block
2828 is MAX_MOVE_BYTES long. */
2829 emit_insn (gen_movstrsi_internal (dst_reg
, src_reg
, at_a_time
));
2830 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2832 if (bytes
> MAX_MOVE_BYTES
)
2834 emit_insn (gen_cmpsi (src_reg
, final_src
));
2835 emit_jump_insn (gen_bne (label
));
2840 emit_insn (gen_movstrsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
)));
2844 /* Emit load/stores for a small constant word aligned block_move.
2846 operands[0] is the memory address of the destination.
2847 operands[1] is the memory address of the source.
2848 operands[2] is the number of bytes to move.
2849 operands[3] is a temp register.
2850 operands[4] is a temp register. */
2853 m32r_output_block_move (insn
, operands
)
2854 rtx insn ATTRIBUTE_UNUSED
;
2857 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2861 if (bytes
< 1 || bytes
> MAX_MOVE_BYTES
)
2864 /* We do not have a post-increment store available, so the first set of
2865 stores are done without any increment, then the remaining ones can use
2866 the pre-increment addressing mode.
2868 Note: expand_block_move() also relies upon this behaviour when building
2869 loops to copy large blocks. */
2878 output_asm_insn ("ld\t%3, %p1", operands
);
2879 output_asm_insn ("ld\t%4, %p1", operands
);
2880 output_asm_insn ("st\t%3, @%0", operands
);
2881 output_asm_insn ("st\t%4, %s0", operands
);
2885 output_asm_insn ("ld\t%3, %p1", operands
);
2886 output_asm_insn ("ld\t%4, %p1", operands
);
2887 output_asm_insn ("st\t%3, %s0", operands
);
2888 output_asm_insn ("st\t%4, %s0", operands
);
2893 else if (bytes
>= 4)
2898 output_asm_insn ("ld\t%3, %p1", operands
);
2901 output_asm_insn ("ld\t%4, %p1", operands
);
2904 output_asm_insn ("st\t%3, @%0", operands
);
2906 output_asm_insn ("st\t%3, %s0", operands
);
2912 /* Get the entire next word, even though we do not want all of it.
2913 The saves us from doing several smaller loads, and we assume that
2914 we cannot cause a page fault when at least part of the word is in
2915 valid memory [since we don't get called if things aren't properly
2917 int dst_offset
= first_time
? 0 : 4;
2921 /* If got_extra is true then we have already loaded
2922 the next word as part of loading and storing the previous word. */
2924 output_asm_insn ("ld\t%4, @%1", operands
);
2930 output_asm_insn ("sra3\t%3, %4, #16", operands
);
2931 my_operands
[0] = operands
[3];
2932 my_operands
[1] = GEN_INT (dst_offset
);
2933 my_operands
[2] = operands
[0];
2934 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2936 /* If there is a byte left to store then increment the
2937 destination address and shift the contents of the source
2938 register down by 8 bits. We could not do the address
2939 increment in the store half word instruction, because it does
2940 not have an auto increment mode. */
2941 if (bytes
> 0) /* assert (bytes == 1) */
2952 my_operands
[0] = operands
[4];
2953 my_operands
[1] = GEN_INT (last_shift
);
2954 output_asm_insn ("srai\t%0, #%1", my_operands
);
2955 my_operands
[0] = operands
[4];
2956 my_operands
[1] = GEN_INT (dst_offset
);
2957 my_operands
[2] = operands
[0];
2958 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2968 /* Return true if op is an integer constant, less than or equal to
2971 m32r_block_immediate_operand (op
, mode
)
2973 enum machine_mode mode ATTRIBUTE_UNUSED
;
2975 if (GET_CODE (op
) != CONST_INT
2976 || INTVAL (op
) > MAX_MOVE_BYTES
2977 || INTVAL (op
) <= 0)