1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block
;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks
;
202 static int need_refresh
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; unsigned int i
;} old_contents
;
318 union {rtx
*r
; unsigned int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too.
327 previous_undos is the value of undobuf.undos when we started processing
328 this substitution. This will prevent gen_rtx_combine from re-used a piece
329 from the previous expression. Doing so can produce circular rtl
336 struct undo
*previous_undos
;
340 static struct undobuf undobuf
;
342 /* Number of times the pseudo being substituted for
343 was found and replaced. */
345 static int n_occurrences
;
347 static void do_SUBST
PARAMS ((rtx
*, rtx
));
348 static void do_SUBST_INT
PARAMS ((unsigned int *,
350 static void init_reg_last_arrays
PARAMS ((void));
351 static void setup_incoming_promotions
PARAMS ((void));
352 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
353 static int cant_combine_insn_p
PARAMS ((rtx
));
354 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
355 static int sets_function_arg_p
PARAMS ((rtx
));
356 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
357 static int contains_muldiv
PARAMS ((rtx
));
358 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
359 static void undo_all
PARAMS ((void));
360 static void undo_commit
PARAMS ((void));
361 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
362 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
363 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
364 static rtx simplify_if_then_else
PARAMS ((rtx
));
365 static rtx simplify_set
PARAMS ((rtx
));
366 static rtx simplify_logical
PARAMS ((rtx
, int));
367 static rtx expand_compound_operation
PARAMS ((rtx
));
368 static rtx expand_field_assignment
PARAMS ((rtx
));
369 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
370 rtx
, unsigned HOST_WIDE_INT
, int,
372 static rtx extract_left_shift
PARAMS ((rtx
, int));
373 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
374 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
375 unsigned HOST_WIDE_INT
*));
376 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
377 unsigned HOST_WIDE_INT
, rtx
, int));
378 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
379 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
380 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
381 static rtx make_field_assignment
PARAMS ((rtx
));
382 static rtx apply_distributive_law
PARAMS ((rtx
));
383 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
384 unsigned HOST_WIDE_INT
));
385 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
386 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
387 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
388 enum rtx_code
, HOST_WIDE_INT
,
389 enum machine_mode
, int *));
390 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
392 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
393 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
394 static rtx gen_rtx_combine
PARAMS ((enum rtx_code code
, enum machine_mode mode
,
396 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
398 static rtx gen_unary
PARAMS ((enum rtx_code
, enum machine_mode
,
399 enum machine_mode
, rtx
));
400 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
401 static void update_table_tick
PARAMS ((rtx
));
402 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
403 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
404 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
405 static void record_dead_and_set_regs
PARAMS ((rtx
));
406 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
407 static rtx get_last_value
PARAMS ((rtx
));
408 static int use_crosses_set_p
PARAMS ((rtx
, int));
409 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
410 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
411 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
412 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
413 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
414 static void distribute_links
PARAMS ((rtx
));
415 static void mark_used_regs_combine
PARAMS ((rtx
));
416 static int insn_cuid
PARAMS ((rtx
));
417 static void record_promoted_value
PARAMS ((rtx
, rtx
));
418 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
419 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
421 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
422 insn. The substitution can be undone by undo_all. If INTO is already
423 set to NEWVAL, do not record this change. Because computing NEWVAL might
424 also call SUBST, we have to compute it before we put anything into
428 do_SUBST (into
, newval
)
434 if (oldval
== newval
)
438 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
440 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
444 buf
->old_contents
.r
= oldval
;
447 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
450 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
452 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
453 for the value of a HOST_WIDE_INT value (including CONST_INT) is
457 do_SUBST_INT (into
, newval
)
458 unsigned int *into
, newval
;
461 unsigned int oldval
= *into
;
463 if (oldval
== newval
)
467 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
469 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
473 buf
->old_contents
.i
= oldval
;
476 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
479 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
481 /* Main entry point for combiner. F is the first insn of the function.
482 NREGS is the first unused pseudo-reg number.
484 Return non-zero if the combiner has turned an indirect jump
485 instruction into a direct jump. */
487 combine_instructions (f
, nregs
)
491 register rtx insn
, next
;
496 register rtx links
, nextlinks
;
498 int new_direct_jump_p
= 0;
500 combine_attempts
= 0;
503 combine_successes
= 0;
505 combine_max_regno
= nregs
;
507 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
508 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
510 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
512 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
513 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
514 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
515 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
516 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
517 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
519 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
520 reg_last_set_nonzero_bits
521 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
522 reg_last_set_sign_bit_copies
523 = (char *) xmalloc (nregs
* sizeof (char));
525 init_reg_last_arrays ();
527 init_recog_no_volatile ();
529 /* Compute maximum uid value so uid_cuid can be allocated. */
531 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
532 if (INSN_UID (insn
) > i
)
535 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
538 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
540 /* Don't use reg_nonzero_bits when computing it. This can cause problems
541 when, for example, we have j <<= 1 in a loop. */
543 nonzero_sign_valid
= 0;
545 /* Compute the mapping from uids to cuids.
546 Cuids are numbers assigned to insns, like uids,
547 except that cuids increase monotonically through the code.
549 Scan all SETs and see if we can deduce anything about what
550 bits are known to be zero for some registers and how many copies
551 of the sign bit are known to exist for those registers.
553 Also set any known values so that we can use it while searching
554 for what bits are known to be set. */
558 /* We need to initialize it here, because record_dead_and_set_regs may call
560 subst_prev_insn
= NULL_RTX
;
562 setup_incoming_promotions ();
564 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
565 sbitmap_zero (refresh_blocks
);
568 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
570 uid_cuid
[INSN_UID (insn
)] = ++i
;
576 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
578 record_dead_and_set_regs (insn
);
581 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
582 if (REG_NOTE_KIND (links
) == REG_INC
)
583 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
588 if (GET_CODE (insn
) == CODE_LABEL
)
592 nonzero_sign_valid
= 1;
594 /* Now scan all the insns in forward order. */
596 this_basic_block
= -1;
600 init_reg_last_arrays ();
601 setup_incoming_promotions ();
603 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
607 /* If INSN starts a new basic block, update our basic block number. */
608 if (this_basic_block
+ 1 < n_basic_blocks
609 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
612 if (GET_CODE (insn
) == CODE_LABEL
)
615 else if (INSN_P (insn
))
617 /* See if we know about function return values before this
618 insn based upon SUBREG flags. */
619 check_promoted_subreg (insn
, PATTERN (insn
));
621 /* Try this insn with each insn it links back to. */
623 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
624 if ((next
= try_combine (insn
, XEXP (links
, 0),
625 NULL_RTX
, &new_direct_jump_p
)) != 0)
628 /* Try each sequence of three linked insns ending with this one. */
630 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
632 rtx link
= XEXP (links
, 0);
634 /* If the linked insn has been replaced by a note, then there
635 is no point in persuing this chain any further. */
636 if (GET_CODE (link
) == NOTE
)
639 for (nextlinks
= LOG_LINKS (link
);
641 nextlinks
= XEXP (nextlinks
, 1))
642 if ((next
= try_combine (insn
, XEXP (links
, 0),
644 &new_direct_jump_p
)) != 0)
649 /* Try to combine a jump insn that uses CC0
650 with a preceding insn that sets CC0, and maybe with its
651 logical predecessor as well.
652 This is how we make decrement-and-branch insns.
653 We need this special code because data flow connections
654 via CC0 do not get entered in LOG_LINKS. */
656 if (GET_CODE (insn
) == JUMP_INSN
657 && (prev
= prev_nonnote_insn (insn
)) != 0
658 && GET_CODE (prev
) == INSN
659 && sets_cc0_p (PATTERN (prev
)))
661 if ((next
= try_combine (insn
, prev
,
662 NULL_RTX
, &new_direct_jump_p
)) != 0)
665 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
666 nextlinks
= XEXP (nextlinks
, 1))
667 if ((next
= try_combine (insn
, prev
,
669 &new_direct_jump_p
)) != 0)
673 /* Do the same for an insn that explicitly references CC0. */
674 if (GET_CODE (insn
) == INSN
675 && (prev
= prev_nonnote_insn (insn
)) != 0
676 && GET_CODE (prev
) == INSN
677 && sets_cc0_p (PATTERN (prev
))
678 && GET_CODE (PATTERN (insn
)) == SET
679 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
681 if ((next
= try_combine (insn
, prev
,
682 NULL_RTX
, &new_direct_jump_p
)) != 0)
685 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
686 nextlinks
= XEXP (nextlinks
, 1))
687 if ((next
= try_combine (insn
, prev
,
689 &new_direct_jump_p
)) != 0)
693 /* Finally, see if any of the insns that this insn links to
694 explicitly references CC0. If so, try this insn, that insn,
695 and its predecessor if it sets CC0. */
696 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
697 if (GET_CODE (XEXP (links
, 0)) == INSN
698 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
699 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
700 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
701 && GET_CODE (prev
) == INSN
702 && sets_cc0_p (PATTERN (prev
))
703 && (next
= try_combine (insn
, XEXP (links
, 0),
704 prev
, &new_direct_jump_p
)) != 0)
708 /* Try combining an insn with two different insns whose results it
710 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
711 for (nextlinks
= XEXP (links
, 1); nextlinks
;
712 nextlinks
= XEXP (nextlinks
, 1))
713 if ((next
= try_combine (insn
, XEXP (links
, 0),
715 &new_direct_jump_p
)) != 0)
718 if (GET_CODE (insn
) != NOTE
)
719 record_dead_and_set_regs (insn
);
728 compute_bb_for_insn (get_max_uid ());
729 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
734 sbitmap_free (refresh_blocks
);
735 free (reg_nonzero_bits
);
736 free (reg_sign_bit_copies
);
737 free (reg_last_death
);
739 free (reg_last_set_value
);
740 free (reg_last_set_table_tick
);
741 free (reg_last_set_label
);
742 free (reg_last_set_invalid
);
743 free (reg_last_set_mode
);
744 free (reg_last_set_nonzero_bits
);
745 free (reg_last_set_sign_bit_copies
);
749 struct undo
*undo
, *next
;
750 for (undo
= undobuf
.frees
; undo
; undo
= next
)
758 total_attempts
+= combine_attempts
;
759 total_merges
+= combine_merges
;
760 total_extras
+= combine_extras
;
761 total_successes
+= combine_successes
;
763 nonzero_sign_valid
= 0;
765 /* Make recognizer allow volatile MEMs again. */
768 return new_direct_jump_p
;
771 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
774 init_reg_last_arrays ()
776 unsigned int nregs
= combine_max_regno
;
778 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
779 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
780 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
781 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
782 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
783 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
784 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
785 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
786 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
789 /* Set up any promoted values for incoming argument registers. */
792 setup_incoming_promotions ()
794 #ifdef PROMOTE_FUNCTION_ARGS
797 enum machine_mode mode
;
799 rtx first
= get_insns ();
801 #ifndef OUTGOING_REGNO
802 #define OUTGOING_REGNO(N) N
804 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
805 /* Check whether this register can hold an incoming pointer
806 argument. FUNCTION_ARG_REGNO_P tests outgoing register
807 numbers, so translate if necessary due to register windows. */
808 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
809 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
812 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
815 gen_rtx_CLOBBER (mode
, const0_rtx
)));
820 /* Called via note_stores. If X is a pseudo that is narrower than
821 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
823 If we are setting only a portion of X and we can't figure out what
824 portion, assume all bits will be used since we don't know what will
827 Similarly, set how many bits of X are known to be copies of the sign bit
828 at all locations in the function. This is the smallest number implied
832 set_nonzero_bits_and_sign_copies (x
, set
, data
)
835 void *data ATTRIBUTE_UNUSED
;
839 if (GET_CODE (x
) == REG
840 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
841 /* If this register is undefined at the start of the file, we can't
842 say what its contents were. */
843 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
844 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
846 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
848 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
849 reg_sign_bit_copies
[REGNO (x
)] = 1;
853 /* If this is a complex assignment, see if we can convert it into a
854 simple assignment. */
855 set
= expand_field_assignment (set
);
857 /* If this is a simple assignment, or we have a paradoxical SUBREG,
858 set what we know about X. */
860 if (SET_DEST (set
) == x
861 || (GET_CODE (SET_DEST (set
)) == SUBREG
862 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
863 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
864 && SUBREG_REG (SET_DEST (set
)) == x
))
866 rtx src
= SET_SRC (set
);
868 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
869 /* If X is narrower than a word and SRC is a non-negative
870 constant that would appear negative in the mode of X,
871 sign-extend it for use in reg_nonzero_bits because some
872 machines (maybe most) will actually do the sign-extension
873 and this is the conservative approach.
875 ??? For 2.5, try to tighten up the MD files in this regard
876 instead of this kludge. */
878 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
879 && GET_CODE (src
) == CONST_INT
881 && 0 != (INTVAL (src
)
883 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
884 src
= GEN_INT (INTVAL (src
)
885 | ((HOST_WIDE_INT
) (-1)
886 << GET_MODE_BITSIZE (GET_MODE (x
))));
889 reg_nonzero_bits
[REGNO (x
)]
890 |= nonzero_bits (src
, nonzero_bits_mode
);
891 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
892 if (reg_sign_bit_copies
[REGNO (x
)] == 0
893 || reg_sign_bit_copies
[REGNO (x
)] > num
)
894 reg_sign_bit_copies
[REGNO (x
)] = num
;
898 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
899 reg_sign_bit_copies
[REGNO (x
)] = 1;
904 /* See if INSN can be combined into I3. PRED and SUCC are optionally
905 insns that were previously combined into I3 or that will be combined
906 into the merger of INSN and I3.
908 Return 0 if the combination is not allowed for any reason.
910 If the combination is allowed, *PDEST will be set to the single
911 destination of INSN and *PSRC to the single source, and this function
915 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
918 rtx pred ATTRIBUTE_UNUSED
;
923 rtx set
= 0, src
, dest
;
928 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
929 && next_active_insn (succ
) == i3
)
930 : next_active_insn (insn
) == i3
);
932 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
933 or a PARALLEL consisting of such a SET and CLOBBERs.
935 If INSN has CLOBBER parallel parts, ignore them for our processing.
936 By definition, these happen during the execution of the insn. When it
937 is merged with another insn, all bets are off. If they are, in fact,
938 needed and aren't also supplied in I3, they may be added by
939 recog_for_combine. Otherwise, it won't match.
941 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
944 Get the source and destination of INSN. If more than one, can't
947 if (GET_CODE (PATTERN (insn
)) == SET
)
948 set
= PATTERN (insn
);
949 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
950 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
952 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
954 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
956 switch (GET_CODE (elt
))
958 /* This is important to combine floating point insns
961 /* Combining an isolated USE doesn't make sense.
962 We depend here on combinable_i3_pat to reject them. */
963 /* The code below this loop only verifies that the inputs of
964 the SET in INSN do not change. We call reg_set_between_p
965 to verify that the REG in the USE does not change betweeen
967 If the USE in INSN was for a pseudo register, the matching
968 insn pattern will likely match any register; combining this
969 with any other USE would only be safe if we knew that the
970 used registers have identical values, or if there was
971 something to tell them apart, e.g. different modes. For
972 now, we forgo such compilcated tests and simply disallow
973 combining of USES of pseudo registers with any other USE. */
974 if (GET_CODE (XEXP (elt
, 0)) == REG
975 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
977 rtx i3pat
= PATTERN (i3
);
978 int i
= XVECLEN (i3pat
, 0) - 1;
979 unsigned int regno
= REGNO (XEXP (elt
, 0));
983 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
985 if (GET_CODE (i3elt
) == USE
986 && GET_CODE (XEXP (i3elt
, 0)) == REG
987 && (REGNO (XEXP (i3elt
, 0)) == regno
988 ? reg_set_between_p (XEXP (elt
, 0),
989 PREV_INSN (insn
), i3
)
990 : regno
>= FIRST_PSEUDO_REGISTER
))
997 /* We can ignore CLOBBERs. */
1002 /* Ignore SETs whose result isn't used but not those that
1003 have side-effects. */
1004 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1005 && ! side_effects_p (elt
))
1008 /* If we have already found a SET, this is a second one and
1009 so we cannot combine with this insn. */
1017 /* Anything else means we can't combine. */
1023 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1024 so don't do anything with it. */
1025 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1034 set
= expand_field_assignment (set
);
1035 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1037 /* Don't eliminate a store in the stack pointer. */
1038 if (dest
== stack_pointer_rtx
1039 /* If we couldn't eliminate a field assignment, we can't combine. */
1040 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1041 /* Don't combine with an insn that sets a register to itself if it has
1042 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1043 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1044 /* Can't merge an ASM_OPERANDS. */
1045 || GET_CODE (src
) == ASM_OPERANDS
1046 /* Can't merge a function call. */
1047 || GET_CODE (src
) == CALL
1048 /* Don't eliminate a function call argument. */
1049 || (GET_CODE (i3
) == CALL_INSN
1050 && (find_reg_fusage (i3
, USE
, dest
)
1051 || (GET_CODE (dest
) == REG
1052 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1053 && global_regs
[REGNO (dest
)])))
1054 /* Don't substitute into an incremented register. */
1055 || FIND_REG_INC_NOTE (i3
, dest
)
1056 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1058 /* Don't combine the end of a libcall into anything. */
1059 /* ??? This gives worse code, and appears to be unnecessary, since no
1060 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1061 use REG_RETVAL notes for noconflict blocks, but other code here
1062 makes sure that those insns don't disappear. */
1063 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1065 /* Make sure that DEST is not used after SUCC but before I3. */
1066 || (succ
&& ! all_adjacent
1067 && reg_used_between_p (dest
, succ
, i3
))
1068 /* Make sure that the value that is to be substituted for the register
1069 does not use any registers whose values alter in between. However,
1070 If the insns are adjacent, a use can't cross a set even though we
1071 think it might (this can happen for a sequence of insns each setting
1072 the same destination; reg_last_set of that register might point to
1073 a NOTE). If INSN has a REG_EQUIV note, the register is always
1074 equivalent to the memory so the substitution is valid even if there
1075 are intervening stores. Also, don't move a volatile asm or
1076 UNSPEC_VOLATILE across any other insns. */
1078 && (((GET_CODE (src
) != MEM
1079 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1080 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1081 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1082 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1083 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1084 better register allocation by not doing the combine. */
1085 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1086 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1087 /* Don't combine across a CALL_INSN, because that would possibly
1088 change whether the life span of some REGs crosses calls or not,
1089 and it is a pain to update that information.
1090 Exception: if source is a constant, moving it later can't hurt.
1091 Accept that special case, because it helps -fforce-addr a lot. */
1092 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1095 /* DEST must either be a REG or CC0. */
1096 if (GET_CODE (dest
) == REG
)
1098 /* If register alignment is being enforced for multi-word items in all
1099 cases except for parameters, it is possible to have a register copy
1100 insn referencing a hard register that is not allowed to contain the
1101 mode being copied and which would not be valid as an operand of most
1102 insns. Eliminate this problem by not combining with such an insn.
1104 Also, on some machines we don't want to extend the life of a hard
1107 if (GET_CODE (src
) == REG
1108 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1109 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1110 /* Don't extend the life of a hard register unless it is
1111 user variable (if we have few registers) or it can't
1112 fit into the desired register (meaning something special
1114 Also avoid substituting a return register into I3, because
1115 reload can't handle a conflict with constraints of other
1117 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1118 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1121 else if (GET_CODE (dest
) != CC0
)
1124 /* Don't substitute for a register intended as a clobberable operand.
1125 Similarly, don't substitute an expression containing a register that
1126 will be clobbered in I3. */
1127 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1128 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1129 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1130 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1132 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1135 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1136 or not), reject, unless nothing volatile comes between it and I3 */
1138 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1140 /* Make sure succ doesn't contain a volatile reference. */
1141 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1144 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1145 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1149 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1150 to be an explicit register variable, and was chosen for a reason. */
1152 if (GET_CODE (src
) == ASM_OPERANDS
1153 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1156 /* If there are any volatile insns between INSN and I3, reject, because
1157 they might affect machine state. */
1159 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1160 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1163 /* If INSN or I2 contains an autoincrement or autodecrement,
1164 make sure that register is not used between there and I3,
1165 and not already used in I3 either.
1166 Also insist that I3 not be a jump; if it were one
1167 and the incremented register were spilled, we would lose. */
1170 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1171 if (REG_NOTE_KIND (link
) == REG_INC
1172 && (GET_CODE (i3
) == JUMP_INSN
1173 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1174 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1179 /* Don't combine an insn that follows a CC0-setting insn.
1180 An insn that uses CC0 must not be separated from the one that sets it.
1181 We do, however, allow I2 to follow a CC0-setting insn if that insn
1182 is passed as I1; in that case it will be deleted also.
1183 We also allow combining in this case if all the insns are adjacent
1184 because that would leave the two CC0 insns adjacent as well.
1185 It would be more logical to test whether CC0 occurs inside I1 or I2,
1186 but that would be much slower, and this ought to be equivalent. */
1188 p
= prev_nonnote_insn (insn
);
1189 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1194 /* If we get here, we have passed all the tests and the combination is
1203 /* Check if PAT is an insn - or a part of it - used to set up an
1204 argument for a function in a hard register. */
1207 sets_function_arg_p (pat
)
1213 switch (GET_CODE (pat
))
1216 return sets_function_arg_p (PATTERN (pat
));
1219 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1220 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1226 inner_dest
= SET_DEST (pat
);
1227 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1228 || GET_CODE (inner_dest
) == SUBREG
1229 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1230 inner_dest
= XEXP (inner_dest
, 0);
1232 return (GET_CODE (inner_dest
) == REG
1233 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1234 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1243 /* LOC is the location within I3 that contains its pattern or the component
1244 of a PARALLEL of the pattern. We validate that it is valid for combining.
1246 One problem is if I3 modifies its output, as opposed to replacing it
1247 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1248 so would produce an insn that is not equivalent to the original insns.
1252 (set (reg:DI 101) (reg:DI 100))
1253 (set (subreg:SI (reg:DI 101) 0) <foo>)
1255 This is NOT equivalent to:
1257 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1258 (set (reg:DI 101) (reg:DI 100))])
1260 Not only does this modify 100 (in which case it might still be valid
1261 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1263 We can also run into a problem if I2 sets a register that I1
1264 uses and I1 gets directly substituted into I3 (not via I2). In that
1265 case, we would be getting the wrong value of I2DEST into I3, so we
1266 must reject the combination. This case occurs when I2 and I1 both
1267 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1268 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1269 of a SET must prevent combination from occurring.
1271 Before doing the above check, we first try to expand a field assignment
1272 into a set of logical operations.
1274 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1275 we place a register that is both set and used within I3. If more than one
1276 such register is detected, we fail.
1278 Return 1 if the combination is valid, zero otherwise. */
1281 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1287 rtx
*pi3dest_killed
;
1291 if (GET_CODE (x
) == SET
)
1293 rtx set
= expand_field_assignment (x
);
1294 rtx dest
= SET_DEST (set
);
1295 rtx src
= SET_SRC (set
);
1296 rtx inner_dest
= dest
;
1299 rtx inner_src
= src
;
1304 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1305 || GET_CODE (inner_dest
) == SUBREG
1306 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1307 inner_dest
= XEXP (inner_dest
, 0);
1309 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1312 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1313 || GET_CODE (inner_src
) == SUBREG
1314 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1315 inner_src
= XEXP (inner_src
, 0);
1317 /* If it is better that two different modes keep two different pseudos,
1318 avoid combining them. This avoids producing the following pattern
1320 (set (subreg:SI (reg/v:QI 21) 0)
1321 (lshiftrt:SI (reg/v:SI 20)
1323 If that were made, reload could not handle the pair of
1324 reg 20/21, since it would try to get any GENERAL_REGS
1325 but some of them don't handle QImode. */
1327 if (rtx_equal_p (inner_src
, i2dest
)
1328 && GET_CODE (inner_dest
) == REG
1329 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1333 /* Check for the case where I3 modifies its output, as
1335 if ((inner_dest
!= dest
1336 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1337 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1339 /* This is the same test done in can_combine_p except we can't test
1340 all_adjacent; we don't have to, since this instruction will stay
1341 in place, thus we are not considering increasing the lifetime of
1344 Also, if this insn sets a function argument, combining it with
1345 something that might need a spill could clobber a previous
1346 function argument; the all_adjacent test in can_combine_p also
1347 checks this; here, we do a more specific test for this case. */
1349 || (GET_CODE (inner_dest
) == REG
1350 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1351 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1352 GET_MODE (inner_dest
))))
1353 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1356 /* If DEST is used in I3, it is being killed in this insn,
1357 so record that for later.
1358 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1359 STACK_POINTER_REGNUM, since these are always considered to be
1360 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1361 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1362 && reg_referenced_p (dest
, PATTERN (i3
))
1363 && REGNO (dest
) != FRAME_POINTER_REGNUM
1364 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1365 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1367 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1368 && (REGNO (dest
) != ARG_POINTER_REGNUM
1369 || ! fixed_regs
[REGNO (dest
)])
1371 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1373 if (*pi3dest_killed
)
1376 *pi3dest_killed
= dest
;
1380 else if (GET_CODE (x
) == PARALLEL
)
1384 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1385 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1386 i1_not_in_src
, pi3dest_killed
))
1393 /* Return 1 if X is an arithmetic expression that contains a multiplication
1394 and division. We don't count multiplications by powers of two here. */
1400 switch (GET_CODE (x
))
1402 case MOD
: case DIV
: case UMOD
: case UDIV
:
1406 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1407 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1409 switch (GET_RTX_CLASS (GET_CODE (x
)))
1411 case 'c': case '<': case '2':
1412 return contains_muldiv (XEXP (x
, 0))
1413 || contains_muldiv (XEXP (x
, 1));
1416 return contains_muldiv (XEXP (x
, 0));
1424 /* Determine whether INSN can be used in a combination. Return nonzero if
1425 not. This is used in try_combine to detect early some cases where we
1426 can't perform combinations. */
1429 cant_combine_insn_p (insn
)
1435 /* If this isn't really an insn, we can't do anything.
1436 This can occur when flow deletes an insn that it has merged into an
1437 auto-increment address. */
1438 if (! INSN_P (insn
))
1441 /* Never combine loads and stores involving hard regs. The register
1442 allocator can usually handle such reg-reg moves by tying. If we allow
1443 the combiner to make substitutions of hard regs, we risk aborting in
1444 reload on machines that have SMALL_REGISTER_CLASSES.
1445 As an exception, we allow combinations involving fixed regs; these are
1446 not available to the register allocator so there's no risk involved. */
1448 set
= single_set (insn
);
1451 src
= SET_SRC (set
);
1452 dest
= SET_DEST (set
);
1453 if (GET_CODE (src
) == SUBREG
)
1454 src
= SUBREG_REG (src
);
1455 if (GET_CODE (dest
) == SUBREG
)
1456 dest
= SUBREG_REG (dest
);
1457 if (REG_P (src
) && REG_P (dest
)
1458 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1459 && ! fixed_regs
[REGNO (src
)])
1460 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1461 && ! fixed_regs
[REGNO (dest
)])))
1467 /* Try to combine the insns I1 and I2 into I3.
1468 Here I1 and I2 appear earlier than I3.
1469 I1 can be zero; then we combine just I2 into I3.
1471 If we are combining three insns and the resulting insn is not recognized,
1472 try splitting it into two insns. If that happens, I2 and I3 are retained
1473 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1476 Return 0 if the combination does not work. Then nothing is changed.
1477 If we did the combination, return the insn at which combine should
1480 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1481 new direct jump instruction. */
1484 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1485 register rtx i3
, i2
, i1
;
1486 register int *new_direct_jump_p
;
1488 /* New patterns for I3 and I2, respectively. */
1489 rtx newpat
, newi2pat
= 0;
1490 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1491 int added_sets_1
, added_sets_2
;
1492 /* Total number of SETs to put into I3. */
1494 /* Nonzero is I2's body now appears in I3. */
1496 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1497 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1498 /* Contains I3 if the destination of I3 is used in its source, which means
1499 that the old life of I3 is being killed. If that usage is placed into
1500 I2 and not in I3, a REG_DEAD note must be made. */
1501 rtx i3dest_killed
= 0;
1502 /* SET_DEST and SET_SRC of I2 and I1. */
1503 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1504 /* PATTERN (I2), or a copy of it in certain cases. */
1506 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1507 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1508 int i1_feeds_i3
= 0;
1509 /* Notes that must be added to REG_NOTES in I3 and I2. */
1510 rtx new_i3_notes
, new_i2_notes
;
1511 /* Notes that we substituted I3 into I2 instead of the normal case. */
1512 int i3_subst_into_i2
= 0;
1513 /* Notes that I1, I2 or I3 is a MULT operation. */
1521 /* Exit early if one of the insns involved can't be used for
1523 if (cant_combine_insn_p (i3
)
1524 || cant_combine_insn_p (i2
)
1525 || (i1
&& cant_combine_insn_p (i1
))
1526 /* We also can't do anything if I3 has a
1527 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1530 /* ??? This gives worse code, and appears to be unnecessary, since no
1531 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1532 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1538 undobuf
.other_insn
= 0;
1540 /* Reset the hard register usage information. */
1541 CLEAR_HARD_REG_SET (newpat_used_regs
);
1543 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1544 code below, set I1 to be the earlier of the two insns. */
1545 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1546 temp
= i1
, i1
= i2
, i2
= temp
;
1548 added_links_insn
= 0;
1550 /* First check for one important special-case that the code below will
1551 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1552 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1553 we may be able to replace that destination with the destination of I3.
1554 This occurs in the common code where we compute both a quotient and
1555 remainder into a structure, in which case we want to do the computation
1556 directly into the structure to avoid register-register copies.
1558 Note that this case handles both multiple sets in I2 and also
1559 cases where I2 has a number of CLOBBER or PARALLELs.
1561 We make very conservative checks below and only try to handle the
1562 most common cases of this. For example, we only handle the case
1563 where I2 and I3 are adjacent to avoid making difficult register
1566 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1567 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1568 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1569 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1570 && GET_CODE (PATTERN (i2
)) == PARALLEL
1571 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1572 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1573 below would need to check what is inside (and reg_overlap_mentioned_p
1574 doesn't support those codes anyway). Don't allow those destinations;
1575 the resulting insn isn't likely to be recognized anyway. */
1576 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1577 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1578 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1579 SET_DEST (PATTERN (i3
)))
1580 && next_real_insn (i2
) == i3
)
1582 rtx p2
= PATTERN (i2
);
1584 /* Make sure that the destination of I3,
1585 which we are going to substitute into one output of I2,
1586 is not used within another output of I2. We must avoid making this:
1587 (parallel [(set (mem (reg 69)) ...)
1588 (set (reg 69) ...)])
1589 which is not well-defined as to order of actions.
1590 (Besides, reload can't handle output reloads for this.)
1592 The problem can also happen if the dest of I3 is a memory ref,
1593 if another dest in I2 is an indirect memory ref. */
1594 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1595 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1596 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1597 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1598 SET_DEST (XVECEXP (p2
, 0, i
))))
1601 if (i
== XVECLEN (p2
, 0))
1602 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1603 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1604 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1605 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1610 subst_low_cuid
= INSN_CUID (i2
);
1612 added_sets_2
= added_sets_1
= 0;
1613 i2dest
= SET_SRC (PATTERN (i3
));
1615 /* Replace the dest in I2 with our dest and make the resulting
1616 insn the new pattern for I3. Then skip to where we
1617 validate the pattern. Everything was set up above. */
1618 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1619 SET_DEST (PATTERN (i3
)));
1622 i3_subst_into_i2
= 1;
1623 goto validate_replacement
;
1627 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1628 one of those words to another constant, merge them by making a new
1631 && (temp
= single_set (i2
)) != 0
1632 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1633 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1634 && GET_CODE (SET_DEST (temp
)) == REG
1635 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1636 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1637 && GET_CODE (PATTERN (i3
)) == SET
1638 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1639 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1640 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1641 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1642 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1644 HOST_WIDE_INT lo
, hi
;
1646 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1647 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1650 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1651 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1654 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1656 /* We don't handle the case of the target word being wider
1657 than a host wide int. */
1658 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1661 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1662 lo
|= INTVAL (SET_SRC (PATTERN (i3
)));
1664 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1665 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1666 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1668 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1669 >> (HOST_BITS_PER_WIDE_INT
- 1));
1671 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1672 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1673 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1674 (INTVAL (SET_SRC (PATTERN (i3
)))));
1676 hi
= lo
< 0 ? -1 : 0;
1679 /* We don't handle the case of the higher word not fitting
1680 entirely in either hi or lo. */
1685 subst_low_cuid
= INSN_CUID (i2
);
1686 added_sets_2
= added_sets_1
= 0;
1687 i2dest
= SET_DEST (temp
);
1689 SUBST (SET_SRC (temp
),
1690 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1692 newpat
= PATTERN (i2
);
1693 goto validate_replacement
;
1697 /* If we have no I1 and I2 looks like:
1698 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1700 make up a dummy I1 that is
1703 (set (reg:CC X) (compare:CC Y (const_int 0)))
1705 (We can ignore any trailing CLOBBERs.)
1707 This undoes a previous combination and allows us to match a branch-and-
1710 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1711 && XVECLEN (PATTERN (i2
), 0) >= 2
1712 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1713 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1715 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1716 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1717 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1718 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1719 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1720 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1722 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1723 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1728 /* We make I1 with the same INSN_UID as I2. This gives it
1729 the same INSN_CUID for value tracking. Our fake I1 will
1730 never appear in the insn stream so giving it the same INSN_UID
1731 as I2 will not cause a problem. */
1733 subst_prev_insn
= i1
1734 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1735 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1738 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1739 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1740 SET_DEST (PATTERN (i1
)));
1745 /* Verify that I2 and I1 are valid for combining. */
1746 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1747 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1753 /* Record whether I2DEST is used in I2SRC and similarly for the other
1754 cases. Knowing this will help in register status updating below. */
1755 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1756 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1757 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1759 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1761 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1763 /* Ensure that I3's pattern can be the destination of combines. */
1764 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1765 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1772 /* See if any of the insns is a MULT operation. Unless one is, we will
1773 reject a combination that is, since it must be slower. Be conservative
1775 if (GET_CODE (i2src
) == MULT
1776 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1777 || (GET_CODE (PATTERN (i3
)) == SET
1778 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1781 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1782 We used to do this EXCEPT in one case: I3 has a post-inc in an
1783 output operand. However, that exception can give rise to insns like
1785 which is a famous insn on the PDP-11 where the value of r3 used as the
1786 source was model-dependent. Avoid this sort of thing. */
1789 if (!(GET_CODE (PATTERN (i3
)) == SET
1790 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1791 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1792 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1793 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1794 /* It's not the exception. */
1797 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1798 if (REG_NOTE_KIND (link
) == REG_INC
1799 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1801 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1808 /* See if the SETs in I1 or I2 need to be kept around in the merged
1809 instruction: whenever the value set there is still needed past I3.
1810 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1812 For the SET in I1, we have two cases: If I1 and I2 independently
1813 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1814 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1815 in I1 needs to be kept around unless I1DEST dies or is set in either
1816 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1817 I1DEST. If so, we know I1 feeds into I2. */
1819 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1822 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1823 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1825 /* If the set in I2 needs to be kept around, we must make a copy of
1826 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1827 PATTERN (I2), we are only substituting for the original I1DEST, not into
1828 an already-substituted copy. This also prevents making self-referential
1829 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1832 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1833 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1837 i2pat
= copy_rtx (i2pat
);
1841 /* Substitute in the latest insn for the regs set by the earlier ones. */
1843 maxreg
= max_reg_num ();
1847 /* It is possible that the source of I2 or I1 may be performing an
1848 unneeded operation, such as a ZERO_EXTEND of something that is known
1849 to have the high part zero. Handle that case by letting subst look at
1850 the innermost one of them.
1852 Another way to do this would be to have a function that tries to
1853 simplify a single insn instead of merging two or more insns. We don't
1854 do this because of the potential of infinite loops and because
1855 of the potential extra memory required. However, doing it the way
1856 we are is a bit of a kludge and doesn't catch all cases.
1858 But only do this if -fexpensive-optimizations since it slows things down
1859 and doesn't usually win. */
1861 if (flag_expensive_optimizations
)
1863 /* Pass pc_rtx so no substitutions are done, just simplifications.
1864 The cases that we are interested in here do not involve the few
1865 cases were is_replaced is checked. */
1868 subst_low_cuid
= INSN_CUID (i1
);
1869 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1873 subst_low_cuid
= INSN_CUID (i2
);
1874 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1877 undobuf
.previous_undos
= undobuf
.undos
;
1881 /* Many machines that don't use CC0 have insns that can both perform an
1882 arithmetic operation and set the condition code. These operations will
1883 be represented as a PARALLEL with the first element of the vector
1884 being a COMPARE of an arithmetic operation with the constant zero.
1885 The second element of the vector will set some pseudo to the result
1886 of the same arithmetic operation. If we simplify the COMPARE, we won't
1887 match such a pattern and so will generate an extra insn. Here we test
1888 for this case, where both the comparison and the operation result are
1889 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1890 I2SRC. Later we will make the PARALLEL that contains I2. */
1892 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1893 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1894 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1895 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1897 #ifdef EXTRA_CC_MODES
1899 enum machine_mode compare_mode
;
1902 newpat
= PATTERN (i3
);
1903 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1907 #ifdef EXTRA_CC_MODES
1908 /* See if a COMPARE with the operand we substituted in should be done
1909 with the mode that is currently being used. If not, do the same
1910 processing we do in `subst' for a SET; namely, if the destination
1911 is used only once, try to replace it with a register of the proper
1912 mode and also replace the COMPARE. */
1913 if (undobuf
.other_insn
== 0
1914 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1915 &undobuf
.other_insn
))
1916 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1918 != GET_MODE (SET_DEST (newpat
))))
1920 unsigned int regno
= REGNO (SET_DEST (newpat
));
1921 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1923 if (regno
< FIRST_PSEUDO_REGISTER
1924 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1925 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1927 if (regno
>= FIRST_PSEUDO_REGISTER
)
1928 SUBST (regno_reg_rtx
[regno
], new_dest
);
1930 SUBST (SET_DEST (newpat
), new_dest
);
1931 SUBST (XEXP (*cc_use
, 0), new_dest
);
1932 SUBST (SET_SRC (newpat
),
1933 gen_rtx_combine (COMPARE
, compare_mode
,
1934 i2src
, const0_rtx
));
1937 undobuf
.other_insn
= 0;
1944 n_occurrences
= 0; /* `subst' counts here */
1946 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1947 need to make a unique copy of I2SRC each time we substitute it
1948 to avoid self-referential rtl. */
1950 subst_low_cuid
= INSN_CUID (i2
);
1951 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1952 ! i1_feeds_i3
&& i1dest_in_i1src
);
1953 undobuf
.previous_undos
= undobuf
.undos
;
1955 /* Record whether i2's body now appears within i3's body. */
1956 i2_is_used
= n_occurrences
;
1959 /* If we already got a failure, don't try to do more. Otherwise,
1960 try to substitute in I1 if we have it. */
1962 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1964 /* Before we can do this substitution, we must redo the test done
1965 above (see detailed comments there) that ensures that I1DEST
1966 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1968 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1976 subst_low_cuid
= INSN_CUID (i1
);
1977 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1978 undobuf
.previous_undos
= undobuf
.undos
;
1981 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1982 to count all the ways that I2SRC and I1SRC can be used. */
1983 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1984 && i2_is_used
+ added_sets_2
> 1)
1985 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1986 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1988 /* Fail if we tried to make a new register (we used to abort, but there's
1989 really no reason to). */
1990 || max_reg_num () != maxreg
1991 /* Fail if we couldn't do something and have a CLOBBER. */
1992 || GET_CODE (newpat
) == CLOBBER
1993 /* Fail if this new pattern is a MULT and we didn't have one before
1994 at the outer level. */
1995 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2002 /* If the actions of the earlier insns must be kept
2003 in addition to substituting them into the latest one,
2004 we must make a new PARALLEL for the latest insn
2005 to hold additional the SETs. */
2007 if (added_sets_1
|| added_sets_2
)
2011 if (GET_CODE (newpat
) == PARALLEL
)
2013 rtvec old
= XVEC (newpat
, 0);
2014 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2015 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2016 bcopy ((char *) &old
->elem
[0], (char *) XVEC (newpat
, 0)->elem
,
2017 sizeof (old
->elem
[0]) * old
->num_elem
);
2022 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2023 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2024 XVECEXP (newpat
, 0, 0) = old
;
2028 XVECEXP (newpat
, 0, --total_sets
)
2029 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2030 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2034 /* If there is no I1, use I2's body as is. We used to also not do
2035 the subst call below if I2 was substituted into I3,
2036 but that could lose a simplification. */
2038 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2040 /* See comment where i2pat is assigned. */
2041 XVECEXP (newpat
, 0, --total_sets
)
2042 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2046 /* We come here when we are replacing a destination in I2 with the
2047 destination of I3. */
2048 validate_replacement
:
2050 /* Note which hard regs this insn has as inputs. */
2051 mark_used_regs_combine (newpat
);
2053 /* Is the result of combination a valid instruction? */
2054 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2056 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2057 the second SET's destination is a register that is unused. In that case,
2058 we just need the first SET. This can occur when simplifying a divmod
2059 insn. We *must* test for this case here because the code below that
2060 splits two independent SETs doesn't handle this case correctly when it
2061 updates the register status. Also check the case where the first
2062 SET's destination is unused. That would not cause incorrect code, but
2063 does cause an unneeded insn to remain. */
2065 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2066 && XVECLEN (newpat
, 0) == 2
2067 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2068 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2069 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2070 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2071 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2072 && asm_noperands (newpat
) < 0)
2074 newpat
= XVECEXP (newpat
, 0, 0);
2075 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2078 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2079 && XVECLEN (newpat
, 0) == 2
2080 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2081 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2082 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2083 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2084 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2085 && asm_noperands (newpat
) < 0)
2087 newpat
= XVECEXP (newpat
, 0, 1);
2088 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2091 /* If we were combining three insns and the result is a simple SET
2092 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2093 insns. There are two ways to do this. It can be split using a
2094 machine-specific method (like when you have an addition of a large
2095 constant) or by combine in the function find_split_point. */
2097 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2098 && asm_noperands (newpat
) < 0)
2100 rtx m_split
, *split
;
2101 rtx ni2dest
= i2dest
;
2103 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2104 use I2DEST as a scratch register will help. In the latter case,
2105 convert I2DEST to the mode of the source of NEWPAT if we can. */
2107 m_split
= split_insns (newpat
, i3
);
2109 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2110 inputs of NEWPAT. */
2112 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2113 possible to try that as a scratch reg. This would require adding
2114 more code to make it work though. */
2116 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2118 /* If I2DEST is a hard register or the only use of a pseudo,
2119 we can change its mode. */
2120 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2121 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2122 && GET_CODE (i2dest
) == REG
2123 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2124 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2125 && ! REG_USERVAR_P (i2dest
))))
2126 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2129 m_split
= split_insns (gen_rtx_PARALLEL
2131 gen_rtvec (2, newpat
,
2132 gen_rtx_CLOBBER (VOIDmode
,
2137 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2139 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2140 if (insn_code_number
>= 0)
2143 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2144 && XVECLEN (m_split
, 0) == 2
2145 && (next_real_insn (i2
) == i3
2146 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2150 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2151 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2153 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2154 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2156 /* In case we changed the mode of I2DEST, replace it in the
2157 pseudo-register table here. We can't do it above in case this
2158 code doesn't get executed and we do a split the other way. */
2160 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2161 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2163 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2165 /* If I2 or I3 has multiple SETs, we won't know how to track
2166 register status, so don't use these insns. If I2's destination
2167 is used between I2 and I3, we also can't use these insns. */
2169 if (i2_code_number
>= 0 && i2set
&& i3set
2170 && (next_real_insn (i2
) == i3
2171 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2172 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2174 if (insn_code_number
>= 0)
2177 /* It is possible that both insns now set the destination of I3.
2178 If so, we must show an extra use of it. */
2180 if (insn_code_number
>= 0)
2182 rtx new_i3_dest
= SET_DEST (i3set
);
2183 rtx new_i2_dest
= SET_DEST (i2set
);
2185 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2186 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2187 || GET_CODE (new_i3_dest
) == SUBREG
)
2188 new_i3_dest
= XEXP (new_i3_dest
, 0);
2190 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2191 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2192 || GET_CODE (new_i2_dest
) == SUBREG
)
2193 new_i2_dest
= XEXP (new_i2_dest
, 0);
2195 if (GET_CODE (new_i3_dest
) == REG
2196 && GET_CODE (new_i2_dest
) == REG
2197 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2198 REG_N_SETS (REGNO (new_i2_dest
))++;
2202 /* If we can split it and use I2DEST, go ahead and see if that
2203 helps things be recognized. Verify that none of the registers
2204 are set between I2 and I3. */
2205 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2207 && GET_CODE (i2dest
) == REG
2209 /* We need I2DEST in the proper mode. If it is a hard register
2210 or the only use of a pseudo, we can change its mode. */
2211 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2212 || GET_MODE (*split
) == VOIDmode
2213 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2214 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2215 && ! REG_USERVAR_P (i2dest
)))
2216 && (next_real_insn (i2
) == i3
2217 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2218 /* We can't overwrite I2DEST if its value is still used by
2220 && ! reg_referenced_p (i2dest
, newpat
))
2222 rtx newdest
= i2dest
;
2223 enum rtx_code split_code
= GET_CODE (*split
);
2224 enum machine_mode split_mode
= GET_MODE (*split
);
2226 /* Get NEWDEST as a register in the proper mode. We have already
2227 validated that we can do this. */
2228 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2230 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2232 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2233 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2236 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2237 an ASHIFT. This can occur if it was inside a PLUS and hence
2238 appeared to be a memory address. This is a kludge. */
2239 if (split_code
== MULT
2240 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2241 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2243 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
2244 XEXP (*split
, 0), GEN_INT (i
)));
2245 /* Update split_code because we may not have a multiply
2247 split_code
= GET_CODE (*split
);
2250 #ifdef INSN_SCHEDULING
2251 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2252 be written as a ZERO_EXTEND. */
2253 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2254 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
2258 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
2259 SUBST (*split
, newdest
);
2260 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2262 /* If the split point was a MULT and we didn't have one before,
2263 don't use one now. */
2264 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2265 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2269 /* Check for a case where we loaded from memory in a narrow mode and
2270 then sign extended it, but we need both registers. In that case,
2271 we have a PARALLEL with both loads from the same memory location.
2272 We can split this into a load from memory followed by a register-register
2273 copy. This saves at least one insn, more if register allocation can
2276 We cannot do this if the destination of the second assignment is
2277 a register that we have already assumed is zero-extended. Similarly
2278 for a SUBREG of such a register. */
2280 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2281 && GET_CODE (newpat
) == PARALLEL
2282 && XVECLEN (newpat
, 0) == 2
2283 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2284 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2285 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2286 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2287 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2288 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2290 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2291 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2292 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2293 (GET_CODE (temp
) == REG
2294 && reg_nonzero_bits
[REGNO (temp
)] != 0
2295 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2296 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2297 && (reg_nonzero_bits
[REGNO (temp
)]
2298 != GET_MODE_MASK (word_mode
))))
2299 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2300 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2301 (GET_CODE (temp
) == REG
2302 && reg_nonzero_bits
[REGNO (temp
)] != 0
2303 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2304 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2305 && (reg_nonzero_bits
[REGNO (temp
)]
2306 != GET_MODE_MASK (word_mode
)))))
2307 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2308 SET_SRC (XVECEXP (newpat
, 0, 1)))
2309 && ! find_reg_note (i3
, REG_UNUSED
,
2310 SET_DEST (XVECEXP (newpat
, 0, 0))))
2314 newi2pat
= XVECEXP (newpat
, 0, 0);
2315 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2316 newpat
= XVECEXP (newpat
, 0, 1);
2317 SUBST (SET_SRC (newpat
),
2318 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2319 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2321 if (i2_code_number
>= 0)
2322 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2324 if (insn_code_number
>= 0)
2329 /* If we will be able to accept this, we have made a change to the
2330 destination of I3. This can invalidate a LOG_LINKS pointing
2331 to I3. No other part of combine.c makes such a transformation.
2333 The new I3 will have a destination that was previously the
2334 destination of I1 or I2 and which was used in i2 or I3. Call
2335 distribute_links to make a LOG_LINK from the next use of
2336 that destination. */
2338 PATTERN (i3
) = newpat
;
2339 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2341 /* I3 now uses what used to be its destination and which is
2342 now I2's destination. That means we need a LOG_LINK from
2343 I3 to I2. But we used to have one, so we still will.
2345 However, some later insn might be using I2's dest and have
2346 a LOG_LINK pointing at I3. We must remove this link.
2347 The simplest way to remove the link is to point it at I1,
2348 which we know will be a NOTE. */
2350 for (insn
= NEXT_INSN (i3
);
2351 insn
&& (this_basic_block
== n_basic_blocks
- 1
2352 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2353 insn
= NEXT_INSN (insn
))
2355 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2357 for (link
= LOG_LINKS (insn
); link
;
2358 link
= XEXP (link
, 1))
2359 if (XEXP (link
, 0) == i3
)
2360 XEXP (link
, 0) = i1
;
2368 /* Similarly, check for a case where we have a PARALLEL of two independent
2369 SETs but we started with three insns. In this case, we can do the sets
2370 as two separate insns. This case occurs when some SET allows two
2371 other insns to combine, but the destination of that SET is still live. */
2373 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2374 && GET_CODE (newpat
) == PARALLEL
2375 && XVECLEN (newpat
, 0) == 2
2376 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2379 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2380 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2381 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2382 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2384 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2385 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2387 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2388 XVECEXP (newpat
, 0, 0))
2389 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2390 XVECEXP (newpat
, 0, 1))
2391 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2392 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2394 /* Normally, it doesn't matter which of the two is done first,
2395 but it does if one references cc0. In that case, it has to
2398 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2400 newi2pat
= XVECEXP (newpat
, 0, 0);
2401 newpat
= XVECEXP (newpat
, 0, 1);
2406 newi2pat
= XVECEXP (newpat
, 0, 1);
2407 newpat
= XVECEXP (newpat
, 0, 0);
2410 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2412 if (i2_code_number
>= 0)
2413 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2416 /* If it still isn't recognized, fail and change things back the way they
2418 if ((insn_code_number
< 0
2419 /* Is the result a reasonable ASM_OPERANDS? */
2420 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2426 /* If we had to change another insn, make sure it is valid also. */
2427 if (undobuf
.other_insn
)
2429 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2430 rtx new_other_notes
;
2433 CLEAR_HARD_REG_SET (newpat_used_regs
);
2435 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2438 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2444 PATTERN (undobuf
.other_insn
) = other_pat
;
2446 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2447 are still valid. Then add any non-duplicate notes added by
2448 recog_for_combine. */
2449 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2451 next
= XEXP (note
, 1);
2453 if (REG_NOTE_KIND (note
) == REG_UNUSED
2454 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2456 if (GET_CODE (XEXP (note
, 0)) == REG
)
2457 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2459 remove_note (undobuf
.other_insn
, note
);
2463 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2464 if (GET_CODE (XEXP (note
, 0)) == REG
)
2465 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2467 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2468 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2471 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2472 they are adjacent to each other or not. */
2474 rtx p
= prev_nonnote_insn (i3
);
2475 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2476 && sets_cc0_p (newi2pat
))
2484 /* We now know that we can do this combination. Merge the insns and
2485 update the status of registers and LOG_LINKS. */
2488 rtx i3notes
, i2notes
, i1notes
= 0;
2489 rtx i3links
, i2links
, i1links
= 0;
2492 /* Compute which registers we expect to eliminate. newi2pat may be setting
2493 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2494 same as i3dest, in which case newi2pat may be setting i1dest. */
2495 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2496 || i2dest_in_i2src
|| i2dest_in_i1src
2498 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2499 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2502 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2504 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2505 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2507 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2509 /* Ensure that we do not have something that should not be shared but
2510 occurs multiple times in the new insns. Check this by first
2511 resetting all the `used' flags and then copying anything is shared. */
2513 reset_used_flags (i3notes
);
2514 reset_used_flags (i2notes
);
2515 reset_used_flags (i1notes
);
2516 reset_used_flags (newpat
);
2517 reset_used_flags (newi2pat
);
2518 if (undobuf
.other_insn
)
2519 reset_used_flags (PATTERN (undobuf
.other_insn
));
2521 i3notes
= copy_rtx_if_shared (i3notes
);
2522 i2notes
= copy_rtx_if_shared (i2notes
);
2523 i1notes
= copy_rtx_if_shared (i1notes
);
2524 newpat
= copy_rtx_if_shared (newpat
);
2525 newi2pat
= copy_rtx_if_shared (newi2pat
);
2526 if (undobuf
.other_insn
)
2527 reset_used_flags (PATTERN (undobuf
.other_insn
));
2529 INSN_CODE (i3
) = insn_code_number
;
2530 PATTERN (i3
) = newpat
;
2531 if (undobuf
.other_insn
)
2532 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2534 /* We had one special case above where I2 had more than one set and
2535 we replaced a destination of one of those sets with the destination
2536 of I3. In that case, we have to update LOG_LINKS of insns later
2537 in this basic block. Note that this (expensive) case is rare.
2539 Also, in this case, we must pretend that all REG_NOTEs for I2
2540 actually came from I3, so that REG_UNUSED notes from I2 will be
2541 properly handled. */
2543 if (i3_subst_into_i2
)
2545 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2546 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2547 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2548 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2549 && ! find_reg_note (i2
, REG_UNUSED
,
2550 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2551 for (temp
= NEXT_INSN (i2
);
2552 temp
&& (this_basic_block
== n_basic_blocks
- 1
2553 || BLOCK_HEAD (this_basic_block
) != temp
);
2554 temp
= NEXT_INSN (temp
))
2555 if (temp
!= i3
&& INSN_P (temp
))
2556 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2557 if (XEXP (link
, 0) == i2
)
2558 XEXP (link
, 0) = i3
;
2563 while (XEXP (link
, 1))
2564 link
= XEXP (link
, 1);
2565 XEXP (link
, 1) = i2notes
;
2579 INSN_CODE (i2
) = i2_code_number
;
2580 PATTERN (i2
) = newi2pat
;
2584 PUT_CODE (i2
, NOTE
);
2585 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2586 NOTE_SOURCE_FILE (i2
) = 0;
2593 PUT_CODE (i1
, NOTE
);
2594 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2595 NOTE_SOURCE_FILE (i1
) = 0;
2598 /* Get death notes for everything that is now used in either I3 or
2599 I2 and used to die in a previous insn. If we built two new
2600 patterns, move from I1 to I2 then I2 to I3 so that we get the
2601 proper movement on registers that I2 modifies. */
2605 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2606 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2609 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2612 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2614 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2617 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2620 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2623 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2626 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2627 know these are REG_UNUSED and want them to go to the desired insn,
2628 so we always pass it as i3. We have not counted the notes in
2629 reg_n_deaths yet, so we need to do so now. */
2631 if (newi2pat
&& new_i2_notes
)
2633 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2634 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2635 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2637 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2642 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2643 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2644 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2646 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2649 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2650 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2651 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2652 in that case, it might delete I2. Similarly for I2 and I1.
2653 Show an additional death due to the REG_DEAD note we make here. If
2654 we discard it in distribute_notes, we will decrement it again. */
2658 if (GET_CODE (i3dest_killed
) == REG
)
2659 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2661 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2662 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2664 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2668 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2672 if (i2dest_in_i2src
)
2674 if (GET_CODE (i2dest
) == REG
)
2675 REG_N_DEATHS (REGNO (i2dest
))++;
2677 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2679 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2682 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2683 NULL_RTX
, NULL_RTX
);
2686 if (i1dest_in_i1src
)
2688 if (GET_CODE (i1dest
) == REG
)
2689 REG_N_DEATHS (REGNO (i1dest
))++;
2691 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2692 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2693 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2695 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2696 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2697 NULL_RTX
, NULL_RTX
);
2700 distribute_links (i3links
);
2701 distribute_links (i2links
);
2702 distribute_links (i1links
);
2704 if (GET_CODE (i2dest
) == REG
)
2707 rtx i2_insn
= 0, i2_val
= 0, set
;
2709 /* The insn that used to set this register doesn't exist, and
2710 this life of the register may not exist either. See if one of
2711 I3's links points to an insn that sets I2DEST. If it does,
2712 that is now the last known value for I2DEST. If we don't update
2713 this and I2 set the register to a value that depended on its old
2714 contents, we will get confused. If this insn is used, thing
2715 will be set correctly in combine_instructions. */
2717 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2718 if ((set
= single_set (XEXP (link
, 0))) != 0
2719 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2720 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2722 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2724 /* If the reg formerly set in I2 died only once and that was in I3,
2725 zero its use count so it won't make `reload' do any work. */
2727 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2728 && ! i2dest_in_i2src
)
2730 regno
= REGNO (i2dest
);
2731 REG_N_SETS (regno
)--;
2735 if (i1
&& GET_CODE (i1dest
) == REG
)
2738 rtx i1_insn
= 0, i1_val
= 0, set
;
2740 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2741 if ((set
= single_set (XEXP (link
, 0))) != 0
2742 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2743 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2745 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2747 regno
= REGNO (i1dest
);
2748 if (! added_sets_1
&& ! i1dest_in_i1src
)
2749 REG_N_SETS (regno
)--;
2752 /* Update reg_nonzero_bits et al for any changes that may have been made
2753 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2754 important. Because newi2pat can affect nonzero_bits of newpat */
2756 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2757 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2759 /* Set new_direct_jump_p if a new return or simple jump instruction
2762 If I3 is now an unconditional jump, ensure that it has a
2763 BARRIER following it since it may have initially been a
2764 conditional jump. It may also be the last nonnote insn. */
2766 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
))
2768 *new_direct_jump_p
= 1;
2770 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2771 || GET_CODE (temp
) != BARRIER
)
2772 emit_barrier_after (i3
);
2776 combine_successes
++;
2779 /* Clear this here, so that subsequent get_last_value calls are not
2781 subst_prev_insn
= NULL_RTX
;
2783 if (added_links_insn
2784 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2785 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2786 return added_links_insn
;
2788 return newi2pat
? i2
: i3
;
2791 /* Undo all the modifications recorded in undobuf. */
2796 struct undo
*undo
, *next
;
2798 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2802 *undo
->where
.i
= undo
->old_contents
.i
;
2804 *undo
->where
.r
= undo
->old_contents
.r
;
2806 undo
->next
= undobuf
.frees
;
2807 undobuf
.frees
= undo
;
2810 undobuf
.undos
= undobuf
.previous_undos
= 0;
2812 /* Clear this here, so that subsequent get_last_value calls are not
2814 subst_prev_insn
= NULL_RTX
;
2817 /* We've committed to accepting the changes we made. Move all
2818 of the undos to the free list. */
2823 struct undo
*undo
, *next
;
2825 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2828 undo
->next
= undobuf
.frees
;
2829 undobuf
.frees
= undo
;
2831 undobuf
.undos
= undobuf
.previous_undos
= 0;
2835 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2836 where we have an arithmetic expression and return that point. LOC will
2839 try_combine will call this function to see if an insn can be split into
2843 find_split_point (loc
, insn
)
2848 enum rtx_code code
= GET_CODE (x
);
2850 unsigned HOST_WIDE_INT len
= 0;
2851 HOST_WIDE_INT pos
= 0;
2853 rtx inner
= NULL_RTX
;
2855 /* First special-case some codes. */
2859 #ifdef INSN_SCHEDULING
2860 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2862 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2865 return find_split_point (&SUBREG_REG (x
), insn
);
2869 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2870 using LO_SUM and HIGH. */
2871 if (GET_CODE (XEXP (x
, 0)) == CONST
2872 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2875 gen_rtx_combine (LO_SUM
, Pmode
,
2876 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2878 return &XEXP (XEXP (x
, 0), 0);
2882 /* If we have a PLUS whose second operand is a constant and the
2883 address is not valid, perhaps will can split it up using
2884 the machine-specific way to split large constants. We use
2885 the first pseudo-reg (one of the virtual regs) as a placeholder;
2886 it will not remain in the result. */
2887 if (GET_CODE (XEXP (x
, 0)) == PLUS
2888 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2889 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2891 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2892 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2895 /* This should have produced two insns, each of which sets our
2896 placeholder. If the source of the second is a valid address,
2897 we can make put both sources together and make a split point
2900 if (seq
&& XVECLEN (seq
, 0) == 2
2901 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2902 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2903 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2904 && ! reg_mentioned_p (reg
,
2905 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2906 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2907 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2908 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2909 && memory_address_p (GET_MODE (x
),
2910 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2912 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2913 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2915 /* Replace the placeholder in SRC2 with SRC1. If we can
2916 find where in SRC2 it was placed, that can become our
2917 split point and we can replace this address with SRC2.
2918 Just try two obvious places. */
2920 src2
= replace_rtx (src2
, reg
, src1
);
2922 if (XEXP (src2
, 0) == src1
)
2923 split
= &XEXP (src2
, 0);
2924 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2925 && XEXP (XEXP (src2
, 0), 0) == src1
)
2926 split
= &XEXP (XEXP (src2
, 0), 0);
2930 SUBST (XEXP (x
, 0), src2
);
2935 /* If that didn't work, perhaps the first operand is complex and
2936 needs to be computed separately, so make a split point there.
2937 This will occur on machines that just support REG + CONST
2938 and have a constant moved through some previous computation. */
2940 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2941 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2942 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2944 return &XEXP (XEXP (x
, 0), 0);
2950 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2951 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2952 we need to put the operand into a register. So split at that
2955 if (SET_DEST (x
) == cc0_rtx
2956 && GET_CODE (SET_SRC (x
)) != COMPARE
2957 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2958 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2959 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2960 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2961 return &SET_SRC (x
);
2964 /* See if we can split SET_SRC as it stands. */
2965 split
= find_split_point (&SET_SRC (x
), insn
);
2966 if (split
&& split
!= &SET_SRC (x
))
2969 /* See if we can split SET_DEST as it stands. */
2970 split
= find_split_point (&SET_DEST (x
), insn
);
2971 if (split
&& split
!= &SET_DEST (x
))
2974 /* See if this is a bitfield assignment with everything constant. If
2975 so, this is an IOR of an AND, so split it into that. */
2976 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2977 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2978 <= HOST_BITS_PER_WIDE_INT
)
2979 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2980 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2981 && GET_CODE (SET_SRC (x
)) == CONST_INT
2982 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2983 + INTVAL (XEXP (SET_DEST (x
), 2)))
2984 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2985 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2987 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2988 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2989 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2990 rtx dest
= XEXP (SET_DEST (x
), 0);
2991 enum machine_mode mode
= GET_MODE (dest
);
2992 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2994 if (BITS_BIG_ENDIAN
)
2995 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2999 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3002 gen_binary (IOR
, mode
,
3003 gen_binary (AND
, mode
, dest
,
3004 GEN_INT (~(mask
<< pos
)
3005 & GET_MODE_MASK (mode
))),
3006 GEN_INT (src
<< pos
)));
3008 SUBST (SET_DEST (x
), dest
);
3010 split
= find_split_point (&SET_SRC (x
), insn
);
3011 if (split
&& split
!= &SET_SRC (x
))
3015 /* Otherwise, see if this is an operation that we can split into two.
3016 If so, try to split that. */
3017 code
= GET_CODE (SET_SRC (x
));
3022 /* If we are AND'ing with a large constant that is only a single
3023 bit and the result is only being used in a context where we
3024 need to know if it is zero or non-zero, replace it with a bit
3025 extraction. This will avoid the large constant, which might
3026 have taken more than one insn to make. If the constant were
3027 not a valid argument to the AND but took only one insn to make,
3028 this is no worse, but if it took more than one insn, it will
3031 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3032 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3033 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3034 && GET_CODE (SET_DEST (x
)) == REG
3035 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
3036 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3037 && XEXP (*split
, 0) == SET_DEST (x
)
3038 && XEXP (*split
, 1) == const0_rtx
)
3040 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3041 XEXP (SET_SRC (x
), 0),
3042 pos
, NULL_RTX
, 1, 1, 0, 0);
3043 if (extraction
!= 0)
3045 SUBST (SET_SRC (x
), extraction
);
3046 return find_split_point (loc
, insn
);
3052 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3053 is known to be on, this can be converted into a NEG of a shift. */
3054 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3055 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3056 && 1 <= (pos
= exact_log2
3057 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3058 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3060 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3063 gen_rtx_combine (NEG
, mode
,
3064 gen_rtx_combine (LSHIFTRT
, mode
,
3065 XEXP (SET_SRC (x
), 0),
3068 split
= find_split_point (&SET_SRC (x
), insn
);
3069 if (split
&& split
!= &SET_SRC (x
))
3075 inner
= XEXP (SET_SRC (x
), 0);
3077 /* We can't optimize if either mode is a partial integer
3078 mode as we don't know how many bits are significant
3080 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3081 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3085 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3091 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3092 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3094 inner
= XEXP (SET_SRC (x
), 0);
3095 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3096 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3098 if (BITS_BIG_ENDIAN
)
3099 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3100 unsignedp
= (code
== ZERO_EXTRACT
);
3108 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3110 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3112 /* For unsigned, we have a choice of a shift followed by an
3113 AND or two shifts. Use two shifts for field sizes where the
3114 constant might be too large. We assume here that we can
3115 always at least get 8-bit constants in an AND insn, which is
3116 true for every current RISC. */
3118 if (unsignedp
&& len
<= 8)
3123 gen_rtx_combine (LSHIFTRT
, mode
,
3124 gen_lowpart_for_combine (mode
, inner
),
3126 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3128 split
= find_split_point (&SET_SRC (x
), insn
);
3129 if (split
&& split
!= &SET_SRC (x
))
3136 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3137 gen_rtx_combine (ASHIFT
, mode
,
3138 gen_lowpart_for_combine (mode
, inner
),
3139 GEN_INT (GET_MODE_BITSIZE (mode
)
3141 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3143 split
= find_split_point (&SET_SRC (x
), insn
);
3144 if (split
&& split
!= &SET_SRC (x
))
3149 /* See if this is a simple operation with a constant as the second
3150 operand. It might be that this constant is out of range and hence
3151 could be used as a split point. */
3152 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3153 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3154 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3155 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3156 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3157 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3158 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3160 return &XEXP (SET_SRC (x
), 1);
3162 /* Finally, see if this is a simple operation with its first operand
3163 not in a register. The operation might require this operand in a
3164 register, so return it as a split point. We can always do this
3165 because if the first operand were another operation, we would have
3166 already found it as a split point. */
3167 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3168 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3169 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3170 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3171 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3172 return &XEXP (SET_SRC (x
), 0);
3178 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3179 it is better to write this as (not (ior A B)) so we can split it.
3180 Similarly for IOR. */
3181 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3184 gen_rtx_combine (NOT
, GET_MODE (x
),
3185 gen_rtx_combine (code
== IOR
? AND
: IOR
,
3187 XEXP (XEXP (x
, 0), 0),
3188 XEXP (XEXP (x
, 1), 0))));
3189 return find_split_point (loc
, insn
);
3192 /* Many RISC machines have a large set of logical insns. If the
3193 second operand is a NOT, put it first so we will try to split the
3194 other operand first. */
3195 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3197 rtx tem
= XEXP (x
, 0);
3198 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3199 SUBST (XEXP (x
, 1), tem
);
3207 /* Otherwise, select our actions depending on our rtx class. */
3208 switch (GET_RTX_CLASS (code
))
3210 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3212 split
= find_split_point (&XEXP (x
, 2), insn
);
3215 /* ... fall through ... */
3219 split
= find_split_point (&XEXP (x
, 1), insn
);
3222 /* ... fall through ... */
3224 /* Some machines have (and (shift ...) ...) insns. If X is not
3225 an AND, but XEXP (X, 0) is, use it as our split point. */
3226 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3227 return &XEXP (x
, 0);
3229 split
= find_split_point (&XEXP (x
, 0), insn
);
3235 /* Otherwise, we don't have a split point. */
3239 /* Throughout X, replace FROM with TO, and return the result.
3240 The result is TO if X is FROM;
3241 otherwise the result is X, but its contents may have been modified.
3242 If they were modified, a record was made in undobuf so that
3243 undo_all will (among other things) return X to its original state.
3245 If the number of changes necessary is too much to record to undo,
3246 the excess changes are not made, so the result is invalid.
3247 The changes already made can still be undone.
3248 undobuf.num_undo is incremented for such changes, so by testing that
3249 the caller can tell whether the result is valid.
3251 `n_occurrences' is incremented each time FROM is replaced.
3253 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3255 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3256 by copying if `n_occurrences' is non-zero. */
3259 subst (x
, from
, to
, in_dest
, unique_copy
)
3260 register rtx x
, from
, to
;
3264 register enum rtx_code code
= GET_CODE (x
);
3265 enum machine_mode op0_mode
= VOIDmode
;
3266 register const char *fmt
;
3267 register int len
, i
;
3270 /* Two expressions are equal if they are identical copies of a shared
3271 RTX or if they are both registers with the same register number
3274 #define COMBINE_RTX_EQUAL_P(X,Y) \
3276 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3277 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3279 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3282 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3285 /* If X and FROM are the same register but different modes, they will
3286 not have been seen as equal above. However, flow.c will make a
3287 LOG_LINKS entry for that case. If we do nothing, we will try to
3288 rerecognize our original insn and, when it succeeds, we will
3289 delete the feeding insn, which is incorrect.
3291 So force this insn not to match in this (rare) case. */
3292 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3293 && REGNO (x
) == REGNO (from
))
3294 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3296 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3297 of which may contain things that can be combined. */
3298 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3301 /* It is possible to have a subexpression appear twice in the insn.
3302 Suppose that FROM is a register that appears within TO.
3303 Then, after that subexpression has been scanned once by `subst',
3304 the second time it is scanned, TO may be found. If we were
3305 to scan TO here, we would find FROM within it and create a
3306 self-referent rtl structure which is completely wrong. */
3307 if (COMBINE_RTX_EQUAL_P (x
, to
))
3310 /* Parallel asm_operands need special attention because all of the
3311 inputs are shared across the arms. Furthermore, unsharing the
3312 rtl results in recognition failures. Failure to handle this case
3313 specially can result in circular rtl.
3315 Solve this by doing a normal pass across the first entry of the
3316 parallel, and only processing the SET_DESTs of the subsequent
3319 if (code
== PARALLEL
3320 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3321 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3323 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3325 /* If this substitution failed, this whole thing fails. */
3326 if (GET_CODE (new) == CLOBBER
3327 && XEXP (new, 0) == const0_rtx
)
3330 SUBST (XVECEXP (x
, 0, 0), new);
3332 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3334 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3336 if (GET_CODE (dest
) != REG
3337 && GET_CODE (dest
) != CC0
3338 && GET_CODE (dest
) != PC
)
3340 new = subst (dest
, from
, to
, 0, unique_copy
);
3342 /* If this substitution failed, this whole thing fails. */
3343 if (GET_CODE (new) == CLOBBER
3344 && XEXP (new, 0) == const0_rtx
)
3347 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3353 len
= GET_RTX_LENGTH (code
);
3354 fmt
= GET_RTX_FORMAT (code
);
3356 /* We don't need to process a SET_DEST that is a register, CC0,
3357 or PC, so set up to skip this common case. All other cases
3358 where we want to suppress replacing something inside a
3359 SET_SRC are handled via the IN_DEST operand. */
3361 && (GET_CODE (SET_DEST (x
)) == REG
3362 || GET_CODE (SET_DEST (x
)) == CC0
3363 || GET_CODE (SET_DEST (x
)) == PC
))
3366 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3369 op0_mode
= GET_MODE (XEXP (x
, 0));
3371 for (i
= 0; i
< len
; i
++)
3376 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3378 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3380 new = (unique_copy
&& n_occurrences
3381 ? copy_rtx (to
) : to
);
3386 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3389 /* If this substitution failed, this whole thing
3391 if (GET_CODE (new) == CLOBBER
3392 && XEXP (new, 0) == const0_rtx
)
3396 SUBST (XVECEXP (x
, i
, j
), new);
3399 else if (fmt
[i
] == 'e')
3401 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3403 /* In general, don't install a subreg involving two
3404 modes not tieable. It can worsen register
3405 allocation, and can even make invalid reload
3406 insns, since the reg inside may need to be copied
3407 from in the outside mode, and that may be invalid
3408 if it is an fp reg copied in integer mode.
3410 We allow two exceptions to this: It is valid if
3411 it is inside another SUBREG and the mode of that
3412 SUBREG and the mode of the inside of TO is
3413 tieable and it is valid if X is a SET that copies
3416 if (GET_CODE (to
) == SUBREG
3417 && ! MODES_TIEABLE_P (GET_MODE (to
),
3418 GET_MODE (SUBREG_REG (to
)))
3419 && ! (code
== SUBREG
3420 && MODES_TIEABLE_P (GET_MODE (x
),
3421 GET_MODE (SUBREG_REG (to
))))
3423 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3426 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3428 #ifdef CLASS_CANNOT_CHANGE_MODE
3430 && GET_CODE (to
) == REG
3431 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3432 && (TEST_HARD_REG_BIT
3433 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3435 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3437 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3440 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3444 /* If we are in a SET_DEST, suppress most cases unless we
3445 have gone inside a MEM, in which case we want to
3446 simplify the address. We assume here that things that
3447 are actually part of the destination have their inner
3448 parts in the first expression. This is true for SUBREG,
3449 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3450 things aside from REG and MEM that should appear in a
3452 new = subst (XEXP (x
, i
), from
, to
,
3454 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3455 || code
== ZERO_EXTRACT
))
3457 && i
== 0), unique_copy
);
3459 /* If we found that we will have to reject this combination,
3460 indicate that by returning the CLOBBER ourselves, rather than
3461 an expression containing it. This will speed things up as
3462 well as prevent accidents where two CLOBBERs are considered
3463 to be equal, thus producing an incorrect simplification. */
3465 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3468 SUBST (XEXP (x
, i
), new);
3473 /* Try to simplify X. If the simplification changed the code, it is likely
3474 that further simplification will help, so loop, but limit the number
3475 of repetitions that will be performed. */
3477 for (i
= 0; i
< 4; i
++)
3479 /* If X is sufficiently simple, don't bother trying to do anything
3481 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3482 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3484 if (GET_CODE (x
) == code
)
3487 code
= GET_CODE (x
);
3489 /* We no longer know the original mode of operand 0 since we
3490 have changed the form of X) */
3491 op0_mode
= VOIDmode
;
3497 /* Simplify X, a piece of RTL. We just operate on the expression at the
3498 outer level; call `subst' to simplify recursively. Return the new
3501 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3502 will be the iteration even if an expression with a code different from
3503 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3506 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3508 enum machine_mode op0_mode
;
3512 enum rtx_code code
= GET_CODE (x
);
3513 enum machine_mode mode
= GET_MODE (x
);
3518 /* If this is a commutative operation, put a constant last and a complex
3519 expression first. We don't need to do this for comparisons here. */
3520 if (GET_RTX_CLASS (code
) == 'c'
3521 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3522 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3523 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3524 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3525 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3526 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3529 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3530 SUBST (XEXP (x
, 1), temp
);
3533 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3534 sign extension of a PLUS with a constant, reverse the order of the sign
3535 extension and the addition. Note that this not the same as the original
3536 code, but overflow is undefined for signed values. Also note that the
3537 PLUS will have been partially moved "inside" the sign-extension, so that
3538 the first operand of X will really look like:
3539 (ashiftrt (plus (ashift A C4) C5) C4).
3541 (plus (ashiftrt (ashift A C4) C2) C4)
3542 and replace the first operand of X with that expression. Later parts
3543 of this function may simplify the expression further.
3545 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3546 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3547 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3549 We do this to simplify address expressions. */
3551 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3552 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3553 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3554 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3555 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3556 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3557 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3558 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3559 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3560 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3561 XEXP (XEXP (x
, 0), 1))) != 0)
3564 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3565 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3566 INTVAL (XEXP (XEXP (x
, 0), 1)));
3568 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3569 INTVAL (XEXP (XEXP (x
, 0), 1)));
3571 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3574 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3575 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3576 things. Check for cases where both arms are testing the same
3579 Don't do anything if all operands are very simple. */
3581 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3582 || GET_RTX_CLASS (code
) == '<')
3583 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3584 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3585 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3587 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3588 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3589 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3591 || (GET_RTX_CLASS (code
) == '1'
3592 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3593 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3594 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3597 rtx cond
, true_rtx
, false_rtx
;
3599 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3601 /* If everything is a comparison, what we have is highly unlikely
3602 to be simpler, so don't use it. */
3603 && ! (GET_RTX_CLASS (code
) == '<'
3604 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3605 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3607 rtx cop1
= const0_rtx
;
3608 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3610 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3613 /* Simplify the alternative arms; this may collapse the true and
3614 false arms to store-flag values. */
3615 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3616 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3618 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3619 is unlikely to be simpler. */
3620 if (general_operand (true_rtx
, VOIDmode
)
3621 && general_operand (false_rtx
, VOIDmode
))
3623 /* Restarting if we generate a store-flag expression will cause
3624 us to loop. Just drop through in this case. */
3626 /* If the result values are STORE_FLAG_VALUE and zero, we can
3627 just make the comparison operation. */
3628 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3629 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3630 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
)
3631 x
= gen_binary (reverse_condition (cond_code
),
3634 /* Likewise, we can make the negate of a comparison operation
3635 if the result values are - STORE_FLAG_VALUE and zero. */
3636 else if (GET_CODE (true_rtx
) == CONST_INT
3637 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3638 && false_rtx
== const0_rtx
)
3639 x
= gen_unary (NEG
, mode
, mode
,
3640 gen_binary (cond_code
, mode
, cond
, cop1
));
3641 else if (GET_CODE (false_rtx
) == CONST_INT
3642 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3643 && true_rtx
== const0_rtx
)
3644 x
= gen_unary (NEG
, mode
, mode
,
3645 gen_binary (reverse_condition (cond_code
),
3648 return gen_rtx_IF_THEN_ELSE (mode
,
3649 gen_binary (cond_code
, VOIDmode
,
3651 true_rtx
, false_rtx
);
3653 code
= GET_CODE (x
);
3654 op0_mode
= VOIDmode
;
3659 /* Try to fold this expression in case we have constants that weren't
3662 switch (GET_RTX_CLASS (code
))
3665 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3669 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3670 if (cmp_mode
== VOIDmode
)
3672 cmp_mode
= GET_MODE (XEXP (x
, 1));
3673 if (cmp_mode
== VOIDmode
)
3674 cmp_mode
= op0_mode
;
3676 temp
= simplify_relational_operation (code
, cmp_mode
,
3677 XEXP (x
, 0), XEXP (x
, 1));
3679 #ifdef FLOAT_STORE_FLAG_VALUE
3680 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3682 if (temp
== const0_rtx
)
3683 temp
= CONST0_RTX (mode
);
3685 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3691 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3695 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3696 XEXP (x
, 1), XEXP (x
, 2));
3701 x
= temp
, code
= GET_CODE (temp
);
3703 /* First see if we can apply the inverse distributive law. */
3704 if (code
== PLUS
|| code
== MINUS
3705 || code
== AND
|| code
== IOR
|| code
== XOR
)
3707 x
= apply_distributive_law (x
);
3708 code
= GET_CODE (x
);
3711 /* If CODE is an associative operation not otherwise handled, see if we
3712 can associate some operands. This can win if they are constants or
3713 if they are logically related (i.e. (a & b) & a. */
3714 if ((code
== PLUS
|| code
== MINUS
3715 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3716 || code
== DIV
|| code
== UDIV
3717 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3718 && INTEGRAL_MODE_P (mode
))
3720 if (GET_CODE (XEXP (x
, 0)) == code
)
3722 rtx other
= XEXP (XEXP (x
, 0), 0);
3723 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3724 rtx inner_op1
= XEXP (x
, 1);
3727 /* Make sure we pass the constant operand if any as the second
3728 one if this is a commutative operation. */
3729 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3731 rtx tem
= inner_op0
;
3732 inner_op0
= inner_op1
;
3735 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3736 : code
== DIV
? MULT
3737 : code
== UDIV
? MULT
3739 mode
, inner_op0
, inner_op1
);
3741 /* For commutative operations, try the other pair if that one
3743 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3745 other
= XEXP (XEXP (x
, 0), 1);
3746 inner
= simplify_binary_operation (code
, mode
,
3747 XEXP (XEXP (x
, 0), 0),
3752 return gen_binary (code
, mode
, other
, inner
);
3756 /* A little bit of algebraic simplification here. */
3760 /* Ensure that our address has any ASHIFTs converted to MULT in case
3761 address-recognizing predicates are called later. */
3762 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3763 SUBST (XEXP (x
, 0), temp
);
3767 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3768 is paradoxical. If we can't do that safely, then it becomes
3769 something nonsensical so that this combination won't take place. */
3771 if (GET_CODE (SUBREG_REG (x
)) == MEM
3772 && (GET_MODE_SIZE (mode
)
3773 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3775 rtx inner
= SUBREG_REG (x
);
3776 int endian_offset
= 0;
3777 /* Don't change the mode of the MEM
3778 if that would change the meaning of the address. */
3779 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3780 || mode_dependent_address_p (XEXP (inner
, 0)))
3781 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3783 if (BYTES_BIG_ENDIAN
)
3785 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3786 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3787 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3788 endian_offset
-= (UNITS_PER_WORD
3789 - GET_MODE_SIZE (GET_MODE (inner
)));
3791 /* Note if the plus_constant doesn't make a valid address
3792 then this combination won't be accepted. */
3793 x
= gen_rtx_MEM (mode
,
3794 plus_constant (XEXP (inner
, 0),
3795 (SUBREG_WORD (x
) * UNITS_PER_WORD
3797 MEM_COPY_ATTRIBUTES (x
, inner
);
3801 /* If we are in a SET_DEST, these other cases can't apply. */
3805 /* Changing mode twice with SUBREG => just change it once,
3806 or not at all if changing back to starting mode. */
3807 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3809 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3810 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3811 return SUBREG_REG (SUBREG_REG (x
));
3813 SUBST_INT (SUBREG_WORD (x
),
3814 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3815 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3818 /* SUBREG of a hard register => just change the register number
3819 and/or mode. If the hard register is not valid in that mode,
3820 suppress this combination. If the hard register is the stack,
3821 frame, or argument pointer, leave this as a SUBREG. */
3823 if (GET_CODE (SUBREG_REG (x
)) == REG
3824 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3825 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3826 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3827 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3829 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3830 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3832 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3834 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3836 return gen_rtx_REG (mode
,
3837 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3839 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3842 /* For a constant, try to pick up the part we want. Handle a full
3843 word and low-order part. Only do this if we are narrowing
3844 the constant; if it is being widened, we have no idea what
3845 the extra bits will have been set to. */
3847 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3848 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3849 && GET_MODE_SIZE (op0_mode
) > UNITS_PER_WORD
3850 && GET_MODE_CLASS (mode
) == MODE_INT
)
3852 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3858 /* If we want a subreg of a constant, at offset 0,
3859 take the low bits. On a little-endian machine, that's
3860 always valid. On a big-endian machine, it's valid
3861 only if the constant's mode fits in one word. Note that we
3862 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3863 if (CONSTANT_P (SUBREG_REG (x
))
3864 && ((GET_MODE_SIZE (op0_mode
) <= UNITS_PER_WORD
3865 || ! WORDS_BIG_ENDIAN
)
3866 ? SUBREG_WORD (x
) == 0
3868 == ((GET_MODE_SIZE (op0_mode
)
3869 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
3871 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3872 && (! WORDS_BIG_ENDIAN
3873 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3874 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3876 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3877 since we are saying that the high bits don't matter. */
3878 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3879 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3881 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
3882 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
3883 return operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
), 0, mode
);
3884 return SUBREG_REG (x
);
3887 /* Note that we cannot do any narrowing for non-constants since
3888 we might have been counting on using the fact that some bits were
3889 zero. We now do this in the SET. */
3894 /* (not (plus X -1)) can become (neg X). */
3895 if (GET_CODE (XEXP (x
, 0)) == PLUS
3896 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3897 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3899 /* Similarly, (not (neg X)) is (plus X -1). */
3900 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3901 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3904 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3905 if (GET_CODE (XEXP (x
, 0)) == XOR
3906 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3907 && (temp
= simplify_unary_operation (NOT
, mode
,
3908 XEXP (XEXP (x
, 0), 1),
3910 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3912 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3913 other than 1, but that is not valid. We could do a similar
3914 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3915 but this doesn't seem common enough to bother with. */
3916 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3917 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3918 return gen_rtx_ROTATE (mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3919 XEXP (XEXP (x
, 0), 1));
3921 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3922 && subreg_lowpart_p (XEXP (x
, 0))
3923 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3924 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3925 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3926 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3928 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3930 x
= gen_rtx_ROTATE (inner_mode
,
3931 gen_unary (NOT
, inner_mode
, inner_mode
,
3933 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3934 return gen_lowpart_for_combine (mode
, x
);
3937 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3938 reversing the comparison code if valid. */
3939 if (STORE_FLAG_VALUE
== -1
3940 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3941 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3942 XEXP (XEXP (x
, 0), 1))))
3945 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3946 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3947 perform the above simplification. */
3949 if (STORE_FLAG_VALUE
== -1
3950 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3951 && XEXP (x
, 1) == const1_rtx
3952 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3953 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3954 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3956 /* Apply De Morgan's laws to reduce number of patterns for machines
3957 with negating logical insns (and-not, nand, etc.). If result has
3958 only one NOT, put it first, since that is how the patterns are
3961 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3963 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3964 enum machine_mode op_mode
;
3966 op_mode
= GET_MODE (in1
);
3967 in1
= gen_unary (NOT
, op_mode
, op_mode
, in1
);
3969 op_mode
= GET_MODE (in2
);
3970 if (op_mode
== VOIDmode
)
3972 in2
= gen_unary (NOT
, op_mode
, op_mode
, in2
);
3974 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3977 in2
= in1
; in1
= tem
;
3980 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3986 /* (neg (plus X 1)) can become (not X). */
3987 if (GET_CODE (XEXP (x
, 0)) == PLUS
3988 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3989 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
3991 /* Similarly, (neg (not X)) is (plus X 1). */
3992 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3993 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3995 /* (neg (minus X Y)) can become (minus Y X). */
3996 if (GET_CODE (XEXP (x
, 0)) == MINUS
3997 && (! FLOAT_MODE_P (mode
)
3998 /* x-y != -(y-x) with IEEE floating point. */
3999 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4001 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
4002 XEXP (XEXP (x
, 0), 0));
4004 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4005 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
4006 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4007 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4009 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4010 if we can then eliminate the NEG (e.g.,
4011 if the operand is a constant). */
4013 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
4015 temp
= simplify_unary_operation (NEG
, mode
,
4016 XEXP (XEXP (x
, 0), 0), mode
);
4019 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
4024 temp
= expand_compound_operation (XEXP (x
, 0));
4026 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4027 replaced by (lshiftrt X C). This will convert
4028 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4030 if (GET_CODE (temp
) == ASHIFTRT
4031 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4032 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4033 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4034 INTVAL (XEXP (temp
, 1)));
4036 /* If X has only a single bit that might be nonzero, say, bit I, convert
4037 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4038 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4039 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4040 or a SUBREG of one since we'd be making the expression more
4041 complex if it was just a register. */
4043 if (GET_CODE (temp
) != REG
4044 && ! (GET_CODE (temp
) == SUBREG
4045 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4046 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4048 rtx temp1
= simplify_shift_const
4049 (NULL_RTX
, ASHIFTRT
, mode
,
4050 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4051 GET_MODE_BITSIZE (mode
) - 1 - i
),
4052 GET_MODE_BITSIZE (mode
) - 1 - i
);
4054 /* If all we did was surround TEMP with the two shifts, we
4055 haven't improved anything, so don't use it. Otherwise,
4056 we are better off with TEMP1. */
4057 if (GET_CODE (temp1
) != ASHIFTRT
4058 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4059 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4065 /* We can't handle truncation to a partial integer mode here
4066 because we don't know the real bitsize of the partial
4068 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4071 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4072 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4073 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4075 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4076 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4078 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4079 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4080 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4081 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4082 return XEXP (XEXP (x
, 0), 0);
4084 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4085 (OP:SI foo:SI) if OP is NEG or ABS. */
4086 if ((GET_CODE (XEXP (x
, 0)) == ABS
4087 || GET_CODE (XEXP (x
, 0)) == NEG
)
4088 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4089 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4090 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4091 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4092 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4094 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4096 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4097 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4098 && subreg_lowpart_p (XEXP (x
, 0)))
4099 return SUBREG_REG (XEXP (x
, 0));
4101 /* If we know that the value is already truncated, we can
4102 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4103 is nonzero for the corresponding modes. But don't do this
4104 for an (LSHIFTRT (MULT ...)) since this will cause problems
4105 with the umulXi3_highpart patterns. */
4106 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4107 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4108 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4109 >= GET_MODE_BITSIZE (mode
) + 1
4110 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4111 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4112 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4114 /* A truncate of a comparison can be replaced with a subreg if
4115 STORE_FLAG_VALUE permits. This is like the previous test,
4116 but it works even if the comparison is done in a mode larger
4117 than HOST_BITS_PER_WIDE_INT. */
4118 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4119 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4120 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4121 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4123 /* Similarly, a truncate of a register whose value is a
4124 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4126 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4127 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4128 && (temp
= get_last_value (XEXP (x
, 0)))
4129 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4130 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4134 case FLOAT_TRUNCATE
:
4135 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4136 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4137 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4138 return XEXP (XEXP (x
, 0), 0);
4140 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4141 (OP:SF foo:SF) if OP is NEG or ABS. */
4142 if ((GET_CODE (XEXP (x
, 0)) == ABS
4143 || GET_CODE (XEXP (x
, 0)) == NEG
)
4144 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4145 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4146 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4147 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4149 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4150 is (float_truncate:SF x). */
4151 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4152 && subreg_lowpart_p (XEXP (x
, 0))
4153 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4154 return SUBREG_REG (XEXP (x
, 0));
4159 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4160 using cc0, in which case we want to leave it as a COMPARE
4161 so we can distinguish it from a register-register-copy. */
4162 if (XEXP (x
, 1) == const0_rtx
)
4165 /* In IEEE floating point, x-0 is not the same as x. */
4166 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4167 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4169 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4175 /* (const (const X)) can become (const X). Do it this way rather than
4176 returning the inner CONST since CONST can be shared with a
4178 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4179 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4184 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4185 can add in an offset. find_split_point will split this address up
4186 again if it doesn't match. */
4187 if (GET_CODE (XEXP (x
, 0)) == HIGH
4188 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4194 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4195 outermost. That's because that's the way indexed addresses are
4196 supposed to appear. This code used to check many more cases, but
4197 they are now checked elsewhere. */
4198 if (GET_CODE (XEXP (x
, 0)) == PLUS
4199 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4200 return gen_binary (PLUS
, mode
,
4201 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4203 XEXP (XEXP (x
, 0), 1));
4205 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4206 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4207 bit-field and can be replaced by either a sign_extend or a
4208 sign_extract. The `and' may be a zero_extend and the two
4209 <c>, -<c> constants may be reversed. */
4210 if (GET_CODE (XEXP (x
, 0)) == XOR
4211 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4212 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4213 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4214 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4215 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4216 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4217 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4218 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4219 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4220 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4221 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4222 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4223 == (unsigned int) i
+ 1))))
4224 return simplify_shift_const
4225 (NULL_RTX
, ASHIFTRT
, mode
,
4226 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4227 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4228 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4229 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4231 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4232 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4233 is 1. This produces better code than the alternative immediately
4235 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4236 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4237 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4238 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4239 XEXP (XEXP (x
, 0), 0),
4240 XEXP (XEXP (x
, 0), 1))))
4242 gen_unary (NEG
, mode
, mode
, reversed
);
4244 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4245 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4246 the bitsize of the mode - 1. This allows simplification of
4247 "a = (b & 8) == 0;" */
4248 if (XEXP (x
, 1) == constm1_rtx
4249 && GET_CODE (XEXP (x
, 0)) != REG
4250 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4251 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4252 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4253 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4254 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4255 gen_rtx_combine (XOR
, mode
,
4256 XEXP (x
, 0), const1_rtx
),
4257 GET_MODE_BITSIZE (mode
) - 1),
4258 GET_MODE_BITSIZE (mode
) - 1);
4260 /* If we are adding two things that have no bits in common, convert
4261 the addition into an IOR. This will often be further simplified,
4262 for example in cases like ((a & 1) + (a & 2)), which can
4265 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4266 && (nonzero_bits (XEXP (x
, 0), mode
)
4267 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4269 /* Try to simplify the expression further. */
4270 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4271 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4273 /* If we could, great. If not, do not go ahead with the IOR
4274 replacement, since PLUS appears in many special purpose
4275 address arithmetic instructions. */
4276 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4282 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4283 by reversing the comparison code if valid. */
4284 if (STORE_FLAG_VALUE
== 1
4285 && XEXP (x
, 0) == const1_rtx
4286 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4287 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4288 XEXP (XEXP (x
, 1), 0),
4289 XEXP (XEXP (x
, 1), 1))))
4292 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4293 (and <foo> (const_int pow2-1)) */
4294 if (GET_CODE (XEXP (x
, 1)) == AND
4295 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4296 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4297 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4298 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4299 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4301 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4303 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4304 return gen_binary (MINUS
, mode
,
4305 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4306 XEXP (XEXP (x
, 1), 0)),
4307 XEXP (XEXP (x
, 1), 1));
4311 /* If we have (mult (plus A B) C), apply the distributive law and then
4312 the inverse distributive law to see if things simplify. This
4313 occurs mostly in addresses, often when unrolling loops. */
4315 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4317 x
= apply_distributive_law
4318 (gen_binary (PLUS
, mode
,
4319 gen_binary (MULT
, mode
,
4320 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4321 gen_binary (MULT
, mode
,
4322 XEXP (XEXP (x
, 0), 1),
4323 copy_rtx (XEXP (x
, 1)))));
4325 if (GET_CODE (x
) != MULT
)
4331 /* If this is a divide by a power of two, treat it as a shift if
4332 its first operand is a shift. */
4333 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4334 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4335 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4336 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4337 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4338 || GET_CODE (XEXP (x
, 0)) == ROTATE
4339 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4340 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4344 case GT
: case GTU
: case GE
: case GEU
:
4345 case LT
: case LTU
: case LE
: case LEU
:
4346 case UNEQ
: case LTGT
:
4347 case UNGT
: case UNGE
:
4348 case UNLT
: case UNLE
:
4349 case UNORDERED
: case ORDERED
:
4350 /* If the first operand is a condition code, we can't do anything
4352 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4353 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4355 && XEXP (x
, 0) != cc0_rtx
4359 rtx op0
= XEXP (x
, 0);
4360 rtx op1
= XEXP (x
, 1);
4361 enum rtx_code new_code
;
4363 if (GET_CODE (op0
) == COMPARE
)
4364 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4366 /* Simplify our comparison, if possible. */
4367 new_code
= simplify_comparison (code
, &op0
, &op1
);
4369 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4370 if only the low-order bit is possibly nonzero in X (such as when
4371 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4372 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4373 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4376 Remove any ZERO_EXTRACT we made when thinking this was a
4377 comparison. It may now be simpler to use, e.g., an AND. If a
4378 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4379 the call to make_compound_operation in the SET case. */
4381 if (STORE_FLAG_VALUE
== 1
4382 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4383 && op1
== const0_rtx
4384 && mode
== GET_MODE (op0
)
4385 && nonzero_bits (op0
, mode
) == 1)
4386 return gen_lowpart_for_combine (mode
,
4387 expand_compound_operation (op0
));
4389 else if (STORE_FLAG_VALUE
== 1
4390 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4391 && op1
== const0_rtx
4392 && mode
== GET_MODE (op0
)
4393 && (num_sign_bit_copies (op0
, mode
)
4394 == GET_MODE_BITSIZE (mode
)))
4396 op0
= expand_compound_operation (op0
);
4397 return gen_unary (NEG
, mode
, mode
,
4398 gen_lowpart_for_combine (mode
, op0
));
4401 else if (STORE_FLAG_VALUE
== 1
4402 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4403 && op1
== const0_rtx
4404 && mode
== GET_MODE (op0
)
4405 && nonzero_bits (op0
, mode
) == 1)
4407 op0
= expand_compound_operation (op0
);
4408 return gen_binary (XOR
, mode
,
4409 gen_lowpart_for_combine (mode
, op0
),
4413 else if (STORE_FLAG_VALUE
== 1
4414 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4415 && op1
== const0_rtx
4416 && mode
== GET_MODE (op0
)
4417 && (num_sign_bit_copies (op0
, mode
)
4418 == GET_MODE_BITSIZE (mode
)))
4420 op0
= expand_compound_operation (op0
);
4421 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4424 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4426 if (STORE_FLAG_VALUE
== -1
4427 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4428 && op1
== const0_rtx
4429 && (num_sign_bit_copies (op0
, mode
)
4430 == GET_MODE_BITSIZE (mode
)))
4431 return gen_lowpart_for_combine (mode
,
4432 expand_compound_operation (op0
));
4434 else if (STORE_FLAG_VALUE
== -1
4435 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4436 && op1
== const0_rtx
4437 && mode
== GET_MODE (op0
)
4438 && nonzero_bits (op0
, mode
) == 1)
4440 op0
= expand_compound_operation (op0
);
4441 return gen_unary (NEG
, mode
, mode
,
4442 gen_lowpart_for_combine (mode
, op0
));
4445 else if (STORE_FLAG_VALUE
== -1
4446 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4447 && op1
== const0_rtx
4448 && mode
== GET_MODE (op0
)
4449 && (num_sign_bit_copies (op0
, mode
)
4450 == GET_MODE_BITSIZE (mode
)))
4452 op0
= expand_compound_operation (op0
);
4453 return gen_unary (NOT
, mode
, mode
,
4454 gen_lowpart_for_combine (mode
, op0
));
4457 /* If X is 0/1, (eq X 0) is X-1. */
4458 else if (STORE_FLAG_VALUE
== -1
4459 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4460 && op1
== const0_rtx
4461 && mode
== GET_MODE (op0
)
4462 && nonzero_bits (op0
, mode
) == 1)
4464 op0
= expand_compound_operation (op0
);
4465 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4468 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4469 one bit that might be nonzero, we can convert (ne x 0) to
4470 (ashift x c) where C puts the bit in the sign bit. Remove any
4471 AND with STORE_FLAG_VALUE when we are done, since we are only
4472 going to test the sign bit. */
4473 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4474 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4475 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4476 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4477 && op1
== const0_rtx
4478 && mode
== GET_MODE (op0
)
4479 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4481 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4482 expand_compound_operation (op0
),
4483 GET_MODE_BITSIZE (mode
) - 1 - i
);
4484 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4490 /* If the code changed, return a whole new comparison. */
4491 if (new_code
!= code
)
4492 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
4494 /* Otherwise, keep this operation, but maybe change its operands.
4495 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4496 SUBST (XEXP (x
, 0), op0
);
4497 SUBST (XEXP (x
, 1), op1
);
4502 return simplify_if_then_else (x
);
4508 /* If we are processing SET_DEST, we are done. */
4512 return expand_compound_operation (x
);
4515 return simplify_set (x
);
4520 return simplify_logical (x
, last
);
4523 /* (abs (neg <foo>)) -> (abs <foo>) */
4524 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4525 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4527 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4529 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4532 /* If operand is something known to be positive, ignore the ABS. */
4533 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4534 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4535 <= HOST_BITS_PER_WIDE_INT
)
4536 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4537 & ((HOST_WIDE_INT
) 1
4538 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4542 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4543 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4544 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
4549 /* (ffs (*_extend <X>)) = (ffs <X>) */
4550 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4551 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4552 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4556 /* (float (sign_extend <X>)) = (float <X>). */
4557 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4558 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4566 /* If this is a shift by a constant amount, simplify it. */
4567 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4568 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4569 INTVAL (XEXP (x
, 1)));
4571 #ifdef SHIFT_COUNT_TRUNCATED
4572 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4574 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4576 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4585 rtx op0
= XEXP (x
, 0);
4586 rtx op1
= XEXP (x
, 1);
4589 if (GET_CODE (op1
) != PARALLEL
)
4591 len
= XVECLEN (op1
, 0);
4593 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4594 && GET_CODE (op0
) == VEC_CONCAT
)
4596 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4598 /* Try to find the element in the VEC_CONCAT. */
4601 if (GET_MODE (op0
) == GET_MODE (x
))
4603 if (GET_CODE (op0
) == VEC_CONCAT
)
4605 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4606 if (op0_size
< offset
)
4607 op0
= XEXP (op0
, 0);
4611 op0
= XEXP (op0
, 1);
4629 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4632 simplify_if_then_else (x
)
4635 enum machine_mode mode
= GET_MODE (x
);
4636 rtx cond
= XEXP (x
, 0);
4637 rtx true_rtx
= XEXP (x
, 1);
4638 rtx false_rtx
= XEXP (x
, 2);
4639 enum rtx_code true_code
= GET_CODE (cond
);
4640 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4643 enum rtx_code false_code
;
4646 /* Simplify storing of the truth value. */
4647 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4648 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4650 /* Also when the truth value has to be reversed. */
4652 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4653 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4657 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4658 in it is being compared against certain values. Get the true and false
4659 comparisons and see if that says anything about the value of each arm. */
4662 && ((false_code
= combine_reversed_comparison_code (cond
))
4664 && GET_CODE (XEXP (cond
, 0)) == REG
)
4667 rtx from
= XEXP (cond
, 0);
4668 rtx true_val
= XEXP (cond
, 1);
4669 rtx false_val
= true_val
;
4672 /* If FALSE_CODE is EQ, swap the codes and arms. */
4674 if (false_code
== EQ
)
4676 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4677 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4680 /* If we are comparing against zero and the expression being tested has
4681 only a single bit that might be nonzero, that is its value when it is
4682 not equal to zero. Similarly if it is known to be -1 or 0. */
4684 if (true_code
== EQ
&& true_val
== const0_rtx
4685 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4686 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4687 else if (true_code
== EQ
&& true_val
== const0_rtx
4688 && (num_sign_bit_copies (from
, GET_MODE (from
))
4689 == GET_MODE_BITSIZE (GET_MODE (from
))))
4690 false_code
= EQ
, false_val
= constm1_rtx
;
4692 /* Now simplify an arm if we know the value of the register in the
4693 branch and it is used in the arm. Be careful due to the potential
4694 of locally-shared RTL. */
4696 if (reg_mentioned_p (from
, true_rtx
))
4697 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4699 pc_rtx
, pc_rtx
, 0, 0);
4700 if (reg_mentioned_p (from
, false_rtx
))
4701 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4703 pc_rtx
, pc_rtx
, 0, 0);
4705 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4706 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4708 true_rtx
= XEXP (x
, 1);
4709 false_rtx
= XEXP (x
, 2);
4710 true_code
= GET_CODE (cond
);
4713 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4714 reversed, do so to avoid needing two sets of patterns for
4715 subtract-and-branch insns. Similarly if we have a constant in the true
4716 arm, the false arm is the same as the first operand of the comparison, or
4717 the false arm is more complicated than the true arm. */
4720 && combine_reversed_comparison_code (cond
) != UNKNOWN
4721 && (true_rtx
== pc_rtx
4722 || (CONSTANT_P (true_rtx
)
4723 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4724 || true_rtx
== const0_rtx
4725 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4726 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4727 || (GET_CODE (true_rtx
) == SUBREG
4728 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4729 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4730 || reg_mentioned_p (true_rtx
, false_rtx
)
4731 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4733 true_code
= reversed_comparison_code (cond
, NULL
);
4735 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4738 SUBST (XEXP (x
, 1), false_rtx
);
4739 SUBST (XEXP (x
, 2), true_rtx
);
4741 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4744 /* It is possible that the conditional has been simplified out. */
4745 true_code
= GET_CODE (cond
);
4746 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4749 /* If the two arms are identical, we don't need the comparison. */
4751 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4754 /* Convert a == b ? b : a to "a". */
4755 if (true_code
== EQ
&& ! side_effects_p (cond
)
4756 && (! FLOAT_MODE_P (mode
) || flag_fast_math
)
4757 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4758 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4760 else if (true_code
== NE
&& ! side_effects_p (cond
)
4761 && (! FLOAT_MODE_P (mode
) || flag_fast_math
)
4762 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4763 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4766 /* Look for cases where we have (abs x) or (neg (abs X)). */
4768 if (GET_MODE_CLASS (mode
) == MODE_INT
4769 && GET_CODE (false_rtx
) == NEG
4770 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4772 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4773 && ! side_effects_p (true_rtx
))
4778 return gen_unary (ABS
, mode
, mode
, true_rtx
);
4781 return gen_unary (NEG
, mode
, mode
,
4782 gen_unary (ABS
, mode
, mode
, true_rtx
));
4787 /* Look for MIN or MAX. */
4789 if ((! FLOAT_MODE_P (mode
) || flag_fast_math
)
4791 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4792 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4793 && ! side_effects_p (cond
))
4798 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4801 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4804 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4807 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4812 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4813 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4814 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4815 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4816 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4817 neither 1 or -1, but it isn't worth checking for. */
4819 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4820 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4822 rtx t
= make_compound_operation (true_rtx
, SET
);
4823 rtx f
= make_compound_operation (false_rtx
, SET
);
4824 rtx cond_op0
= XEXP (cond
, 0);
4825 rtx cond_op1
= XEXP (cond
, 1);
4826 enum rtx_code op
= NIL
, extend_op
= NIL
;
4827 enum machine_mode m
= mode
;
4828 rtx z
= 0, c1
= NULL_RTX
;
4830 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4831 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4832 || GET_CODE (t
) == ASHIFT
4833 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4834 && rtx_equal_p (XEXP (t
, 0), f
))
4835 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4837 /* If an identity-zero op is commutative, check whether there
4838 would be a match if we swapped the operands. */
4839 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4840 || GET_CODE (t
) == XOR
)
4841 && rtx_equal_p (XEXP (t
, 1), f
))
4842 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4843 else if (GET_CODE (t
) == SIGN_EXTEND
4844 && (GET_CODE (XEXP (t
, 0)) == PLUS
4845 || GET_CODE (XEXP (t
, 0)) == MINUS
4846 || GET_CODE (XEXP (t
, 0)) == IOR
4847 || GET_CODE (XEXP (t
, 0)) == XOR
4848 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4849 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4850 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4851 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4852 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4853 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4854 && (num_sign_bit_copies (f
, GET_MODE (f
))
4855 > (GET_MODE_BITSIZE (mode
)
4856 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4858 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4859 extend_op
= SIGN_EXTEND
;
4860 m
= GET_MODE (XEXP (t
, 0));
4862 else if (GET_CODE (t
) == SIGN_EXTEND
4863 && (GET_CODE (XEXP (t
, 0)) == PLUS
4864 || GET_CODE (XEXP (t
, 0)) == IOR
4865 || GET_CODE (XEXP (t
, 0)) == XOR
)
4866 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4867 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4868 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4869 && (num_sign_bit_copies (f
, GET_MODE (f
))
4870 > (GET_MODE_BITSIZE (mode
)
4871 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4873 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4874 extend_op
= SIGN_EXTEND
;
4875 m
= GET_MODE (XEXP (t
, 0));
4877 else if (GET_CODE (t
) == ZERO_EXTEND
4878 && (GET_CODE (XEXP (t
, 0)) == PLUS
4879 || GET_CODE (XEXP (t
, 0)) == MINUS
4880 || GET_CODE (XEXP (t
, 0)) == IOR
4881 || GET_CODE (XEXP (t
, 0)) == XOR
4882 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4883 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4884 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4885 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4886 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4887 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4888 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4889 && ((nonzero_bits (f
, GET_MODE (f
))
4890 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4893 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4894 extend_op
= ZERO_EXTEND
;
4895 m
= GET_MODE (XEXP (t
, 0));
4897 else if (GET_CODE (t
) == ZERO_EXTEND
4898 && (GET_CODE (XEXP (t
, 0)) == PLUS
4899 || GET_CODE (XEXP (t
, 0)) == IOR
4900 || GET_CODE (XEXP (t
, 0)) == XOR
)
4901 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4902 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4903 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4904 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4905 && ((nonzero_bits (f
, GET_MODE (f
))
4906 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4909 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4910 extend_op
= ZERO_EXTEND
;
4911 m
= GET_MODE (XEXP (t
, 0));
4916 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4917 pc_rtx
, pc_rtx
, 0, 0);
4918 temp
= gen_binary (MULT
, m
, temp
,
4919 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4920 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4921 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4923 if (extend_op
!= NIL
)
4924 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4930 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4931 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4932 negation of a single bit, we can convert this operation to a shift. We
4933 can actually do this more generally, but it doesn't seem worth it. */
4935 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4936 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4937 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4938 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4939 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4940 == GET_MODE_BITSIZE (mode
))
4941 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4943 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4944 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4949 /* Simplify X, a SET expression. Return the new expression. */
4955 rtx src
= SET_SRC (x
);
4956 rtx dest
= SET_DEST (x
);
4957 enum machine_mode mode
4958 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4962 /* (set (pc) (return)) gets written as (return). */
4963 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4966 /* Now that we know for sure which bits of SRC we are using, see if we can
4967 simplify the expression for the object knowing that we only need the
4970 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4972 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4973 SUBST (SET_SRC (x
), src
);
4976 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4977 the comparison result and try to simplify it unless we already have used
4978 undobuf.other_insn. */
4979 if ((GET_CODE (src
) == COMPARE
4984 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4985 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4986 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4987 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4989 enum rtx_code old_code
= GET_CODE (*cc_use
);
4990 enum rtx_code new_code
;
4992 int other_changed
= 0;
4993 enum machine_mode compare_mode
= GET_MODE (dest
);
4995 if (GET_CODE (src
) == COMPARE
)
4996 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4998 op0
= src
, op1
= const0_rtx
;
5000 /* Simplify our comparison, if possible. */
5001 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5003 #ifdef EXTRA_CC_MODES
5004 /* If this machine has CC modes other than CCmode, check to see if we
5005 need to use a different CC mode here. */
5006 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5007 #endif /* EXTRA_CC_MODES */
5009 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5010 /* If the mode changed, we have to change SET_DEST, the mode in the
5011 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5012 a hard register, just build new versions with the proper mode. If it
5013 is a pseudo, we lose unless it is only time we set the pseudo, in
5014 which case we can safely change its mode. */
5015 if (compare_mode
!= GET_MODE (dest
))
5017 unsigned int regno
= REGNO (dest
);
5018 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5020 if (regno
< FIRST_PSEUDO_REGISTER
5021 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5023 if (regno
>= FIRST_PSEUDO_REGISTER
)
5024 SUBST (regno_reg_rtx
[regno
], new_dest
);
5026 SUBST (SET_DEST (x
), new_dest
);
5027 SUBST (XEXP (*cc_use
, 0), new_dest
);
5035 /* If the code changed, we have to build a new comparison in
5036 undobuf.other_insn. */
5037 if (new_code
!= old_code
)
5039 unsigned HOST_WIDE_INT mask
;
5041 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
5044 /* If the only change we made was to change an EQ into an NE or
5045 vice versa, OP0 has only one bit that might be nonzero, and OP1
5046 is zero, check if changing the user of the condition code will
5047 produce a valid insn. If it won't, we can keep the original code
5048 in that insn by surrounding our operation with an XOR. */
5050 if (((old_code
== NE
&& new_code
== EQ
)
5051 || (old_code
== EQ
&& new_code
== NE
))
5052 && ! other_changed
&& op1
== const0_rtx
5053 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5054 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5056 rtx pat
= PATTERN (other_insn
), note
= 0;
5058 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5059 && ! check_asm_operands (pat
)))
5061 PUT_CODE (*cc_use
, old_code
);
5064 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5072 undobuf
.other_insn
= other_insn
;
5075 /* If we are now comparing against zero, change our source if
5076 needed. If we do not use cc0, we always have a COMPARE. */
5077 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5079 SUBST (SET_SRC (x
), op0
);
5085 /* Otherwise, if we didn't previously have a COMPARE in the
5086 correct mode, we need one. */
5087 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5090 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
5095 /* Otherwise, update the COMPARE if needed. */
5096 SUBST (XEXP (src
, 0), op0
);
5097 SUBST (XEXP (src
, 1), op1
);
5102 /* Get SET_SRC in a form where we have placed back any
5103 compound expressions. Then do the checks below. */
5104 src
= make_compound_operation (src
, SET
);
5105 SUBST (SET_SRC (x
), src
);
5108 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5109 and X being a REG or (subreg (reg)), we may be able to convert this to
5110 (set (subreg:m2 x) (op)).
5112 We can always do this if M1 is narrower than M2 because that means that
5113 we only care about the low bits of the result.
5115 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5116 perform a narrower operation than requested since the high-order bits will
5117 be undefined. On machine where it is defined, this transformation is safe
5118 as long as M1 and M2 have the same number of words. */
5120 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5121 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5122 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5124 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5125 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5126 #ifndef WORD_REGISTER_OPERATIONS
5127 && (GET_MODE_SIZE (GET_MODE (src
))
5128 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5130 #ifdef CLASS_CANNOT_CHANGE_MODE
5131 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5132 && (TEST_HARD_REG_BIT
5133 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5135 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5136 GET_MODE (SUBREG_REG (src
))))
5138 && (GET_CODE (dest
) == REG
5139 || (GET_CODE (dest
) == SUBREG
5140 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5142 SUBST (SET_DEST (x
),
5143 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5145 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5147 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5150 #ifdef LOAD_EXTEND_OP
5151 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5152 would require a paradoxical subreg. Replace the subreg with a
5153 zero_extend to avoid the reload that would otherwise be required. */
5155 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5156 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5157 && SUBREG_WORD (src
) == 0
5158 && (GET_MODE_SIZE (GET_MODE (src
))
5159 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5160 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5163 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5164 GET_MODE (src
), XEXP (src
, 0)));
5170 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5171 are comparing an item known to be 0 or -1 against 0, use a logical
5172 operation instead. Check for one of the arms being an IOR of the other
5173 arm with some value. We compute three terms to be IOR'ed together. In
5174 practice, at most two will be nonzero. Then we do the IOR's. */
5176 if (GET_CODE (dest
) != PC
5177 && GET_CODE (src
) == IF_THEN_ELSE
5178 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5179 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5180 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5181 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5182 #ifdef HAVE_conditional_move
5183 && ! can_conditionally_move_p (GET_MODE (src
))
5185 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5186 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5187 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5188 && ! side_effects_p (src
))
5190 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5191 ? XEXP (src
, 1) : XEXP (src
, 2));
5192 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5193 ? XEXP (src
, 2) : XEXP (src
, 1));
5194 rtx term1
= const0_rtx
, term2
, term3
;
5196 if (GET_CODE (true_rtx
) == IOR
5197 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5198 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5199 else if (GET_CODE (true_rtx
) == IOR
5200 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5201 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5202 else if (GET_CODE (false_rtx
) == IOR
5203 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5204 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5205 else if (GET_CODE (false_rtx
) == IOR
5206 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5207 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5209 term2
= gen_binary (AND
, GET_MODE (src
),
5210 XEXP (XEXP (src
, 0), 0), true_rtx
);
5211 term3
= gen_binary (AND
, GET_MODE (src
),
5212 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
5213 XEXP (XEXP (src
, 0), 0)),
5217 gen_binary (IOR
, GET_MODE (src
),
5218 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5224 #ifdef HAVE_conditional_arithmetic
5225 /* If we have conditional arithmetic and the operand of a SET is
5226 a conditional expression, replace this with an IF_THEN_ELSE.
5227 We can either have a conditional expression or a MULT of that expression
5229 if ((GET_RTX_CLASS (GET_CODE (src
)) == '1'
5230 || GET_RTX_CLASS (GET_CODE (src
)) == '2'
5231 || GET_RTX_CLASS (GET_CODE (src
)) == 'c')
5232 && (GET_RTX_CLASS (GET_CODE (XEXP (src
, 0))) == '<'
5233 || (GET_CODE (XEXP (src
, 0)) == MULT
5234 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src
, 0), 0))) == '<'
5235 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
)))
5237 rtx cond
= XEXP (src
, 0);
5238 rtx true_val
= const1_rtx
;
5239 rtx false_arm
, true_arm
;
5242 if (GET_CODE (cond
) == MULT
)
5244 true_val
= XEXP (cond
, 1);
5245 cond
= XEXP (cond
, 0);
5248 if (GET_RTX_CLASS (GET_CODE (src
)) == '1')
5250 true_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5251 GET_MODE (XEXP (src
, 0)), true_val
);
5252 false_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5253 GET_MODE (XEXP (src
, 0)), const0_rtx
);
5257 true_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5258 true_val
, XEXP (src
, 1));
5259 false_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5260 const0_rtx
, XEXP (src
, 1));
5263 /* Canonicalize if true_arm is the simpler one. */
5264 if (GET_RTX_CLASS (GET_CODE (true_arm
)) == 'o'
5265 && GET_RTX_CLASS (GET_CODE (false_arm
)) != 'o'
5266 && (reversed
= reversed_comparison_code (cond
, GET_MODE (cond
),
5270 rtx temp
= true_arm
;
5272 true_arm
= false_arm
;
5278 src
= gen_rtx_combine (IF_THEN_ELSE
, GET_MODE (src
),
5279 gen_rtx_combine (GET_CODE (cond
), VOIDmode
,
5282 true_arm
, false_arm
);
5283 SUBST (SET_SRC (x
), src
);
5287 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5288 whole thing fail. */
5289 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5291 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5294 /* Convert this into a field assignment operation, if possible. */
5295 return make_field_assignment (x
);
5298 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5299 result. LAST is nonzero if this is the last retry. */
5302 simplify_logical (x
, last
)
5306 enum machine_mode mode
= GET_MODE (x
);
5307 rtx op0
= XEXP (x
, 0);
5308 rtx op1
= XEXP (x
, 1);
5311 switch (GET_CODE (x
))
5314 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5315 insn (and may simplify more). */
5316 if (GET_CODE (op0
) == XOR
5317 && rtx_equal_p (XEXP (op0
, 0), op1
)
5318 && ! side_effects_p (op1
))
5319 x
= gen_binary (AND
, mode
,
5320 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
5322 if (GET_CODE (op0
) == XOR
5323 && rtx_equal_p (XEXP (op0
, 1), op1
)
5324 && ! side_effects_p (op1
))
5325 x
= gen_binary (AND
, mode
,
5326 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
5328 /* Similarly for (~(A ^ B)) & A. */
5329 if (GET_CODE (op0
) == NOT
5330 && GET_CODE (XEXP (op0
, 0)) == XOR
5331 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5332 && ! side_effects_p (op1
))
5333 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5335 if (GET_CODE (op0
) == NOT
5336 && GET_CODE (XEXP (op0
, 0)) == XOR
5337 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5338 && ! side_effects_p (op1
))
5339 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5341 /* We can call simplify_and_const_int only if we don't lose
5342 any (sign) bits when converting INTVAL (op1) to
5343 "unsigned HOST_WIDE_INT". */
5344 if (GET_CODE (op1
) == CONST_INT
5345 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5346 || INTVAL (op1
) > 0))
5348 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5350 /* If we have (ior (and (X C1) C2)) and the next restart would be
5351 the last, simplify this by making C1 as small as possible
5354 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5355 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5356 && GET_CODE (op1
) == CONST_INT
)
5357 return gen_binary (IOR
, mode
,
5358 gen_binary (AND
, mode
, XEXP (op0
, 0),
5359 GEN_INT (INTVAL (XEXP (op0
, 1))
5360 & ~INTVAL (op1
))), op1
);
5362 if (GET_CODE (x
) != AND
)
5365 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5366 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5367 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5370 /* Convert (A | B) & A to A. */
5371 if (GET_CODE (op0
) == IOR
5372 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5373 || rtx_equal_p (XEXP (op0
, 1), op1
))
5374 && ! side_effects_p (XEXP (op0
, 0))
5375 && ! side_effects_p (XEXP (op0
, 1)))
5378 /* In the following group of tests (and those in case IOR below),
5379 we start with some combination of logical operations and apply
5380 the distributive law followed by the inverse distributive law.
5381 Most of the time, this results in no change. However, if some of
5382 the operands are the same or inverses of each other, simplifications
5385 For example, (and (ior A B) (not B)) can occur as the result of
5386 expanding a bit field assignment. When we apply the distributive
5387 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5388 which then simplifies to (and (A (not B))).
5390 If we have (and (ior A B) C), apply the distributive law and then
5391 the inverse distributive law to see if things simplify. */
5393 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5395 x
= apply_distributive_law
5396 (gen_binary (GET_CODE (op0
), mode
,
5397 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5398 gen_binary (AND
, mode
, XEXP (op0
, 1),
5400 if (GET_CODE (x
) != AND
)
5404 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5405 return apply_distributive_law
5406 (gen_binary (GET_CODE (op1
), mode
,
5407 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5408 gen_binary (AND
, mode
, XEXP (op1
, 1),
5411 /* Similarly, taking advantage of the fact that
5412 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5414 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5415 return apply_distributive_law
5416 (gen_binary (XOR
, mode
,
5417 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5418 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5421 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5422 return apply_distributive_law
5423 (gen_binary (XOR
, mode
,
5424 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5425 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5429 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5430 if (GET_CODE (op1
) == CONST_INT
5431 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5432 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5435 /* Convert (A & B) | A to A. */
5436 if (GET_CODE (op0
) == AND
5437 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5438 || rtx_equal_p (XEXP (op0
, 1), op1
))
5439 && ! side_effects_p (XEXP (op0
, 0))
5440 && ! side_effects_p (XEXP (op0
, 1)))
5443 /* If we have (ior (and A B) C), apply the distributive law and then
5444 the inverse distributive law to see if things simplify. */
5446 if (GET_CODE (op0
) == AND
)
5448 x
= apply_distributive_law
5449 (gen_binary (AND
, mode
,
5450 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5451 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5454 if (GET_CODE (x
) != IOR
)
5458 if (GET_CODE (op1
) == AND
)
5460 x
= apply_distributive_law
5461 (gen_binary (AND
, mode
,
5462 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5463 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5466 if (GET_CODE (x
) != IOR
)
5470 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5471 mode size to (rotate A CX). */
5473 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5474 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5475 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5476 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5477 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5478 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5479 == GET_MODE_BITSIZE (mode
)))
5480 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5481 (GET_CODE (op0
) == ASHIFT
5482 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5484 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5485 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5486 does not affect any of the bits in OP1, it can really be done
5487 as a PLUS and we can associate. We do this by seeing if OP1
5488 can be safely shifted left C bits. */
5489 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5490 && GET_CODE (XEXP (op0
, 0)) == PLUS
5491 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5492 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5493 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5495 int count
= INTVAL (XEXP (op0
, 1));
5496 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5498 if (mask
>> count
== INTVAL (op1
)
5499 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5501 SUBST (XEXP (XEXP (op0
, 0), 1),
5502 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5509 /* If we are XORing two things that have no bits in common,
5510 convert them into an IOR. This helps to detect rotation encoded
5511 using those methods and possibly other simplifications. */
5513 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5514 && (nonzero_bits (op0
, mode
)
5515 & nonzero_bits (op1
, mode
)) == 0)
5516 return (gen_binary (IOR
, mode
, op0
, op1
));
5518 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5519 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5522 int num_negated
= 0;
5524 if (GET_CODE (op0
) == NOT
)
5525 num_negated
++, op0
= XEXP (op0
, 0);
5526 if (GET_CODE (op1
) == NOT
)
5527 num_negated
++, op1
= XEXP (op1
, 0);
5529 if (num_negated
== 2)
5531 SUBST (XEXP (x
, 0), op0
);
5532 SUBST (XEXP (x
, 1), op1
);
5534 else if (num_negated
== 1)
5535 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
5538 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5539 correspond to a machine insn or result in further simplifications
5540 if B is a constant. */
5542 if (GET_CODE (op0
) == AND
5543 && rtx_equal_p (XEXP (op0
, 1), op1
)
5544 && ! side_effects_p (op1
))
5545 return gen_binary (AND
, mode
,
5546 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
5549 else if (GET_CODE (op0
) == AND
5550 && rtx_equal_p (XEXP (op0
, 0), op1
)
5551 && ! side_effects_p (op1
))
5552 return gen_binary (AND
, mode
,
5553 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
5556 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5557 comparison if STORE_FLAG_VALUE is 1. */
5558 if (STORE_FLAG_VALUE
== 1
5559 && op1
== const1_rtx
5560 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5561 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5565 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5566 is (lt foo (const_int 0)), so we can perform the above
5567 simplification if STORE_FLAG_VALUE is 1. */
5569 if (STORE_FLAG_VALUE
== 1
5570 && op1
== const1_rtx
5571 && GET_CODE (op0
) == LSHIFTRT
5572 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5573 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5574 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
5576 /* (xor (comparison foo bar) (const_int sign-bit))
5577 when STORE_FLAG_VALUE is the sign bit. */
5578 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5579 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5580 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5581 && op1
== const_true_rtx
5582 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5583 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5596 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5597 operations" because they can be replaced with two more basic operations.
5598 ZERO_EXTEND is also considered "compound" because it can be replaced with
5599 an AND operation, which is simpler, though only one operation.
5601 The function expand_compound_operation is called with an rtx expression
5602 and will convert it to the appropriate shifts and AND operations,
5603 simplifying at each stage.
5605 The function make_compound_operation is called to convert an expression
5606 consisting of shifts and ANDs into the equivalent compound expression.
5607 It is the inverse of this function, loosely speaking. */
5610 expand_compound_operation (x
)
5613 unsigned HOST_WIDE_INT pos
= 0, len
;
5615 unsigned int modewidth
;
5618 switch (GET_CODE (x
))
5623 /* We can't necessarily use a const_int for a multiword mode;
5624 it depends on implicitly extending the value.
5625 Since we don't know the right way to extend it,
5626 we can't tell whether the implicit way is right.
5628 Even for a mode that is no wider than a const_int,
5629 we can't win, because we need to sign extend one of its bits through
5630 the rest of it, and we don't know which bit. */
5631 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5634 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5635 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5636 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5637 reloaded. If not for that, MEM's would very rarely be safe.
5639 Reject MODEs bigger than a word, because we might not be able
5640 to reference a two-register group starting with an arbitrary register
5641 (and currently gen_lowpart might crash for a SUBREG). */
5643 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5646 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5647 /* If the inner object has VOIDmode (the only way this can happen
5648 is if it is a ASM_OPERANDS), we can't do anything since we don't
5649 know how much masking to do. */
5658 /* If the operand is a CLOBBER, just return it. */
5659 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5662 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5663 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5664 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5667 len
= INTVAL (XEXP (x
, 1));
5668 pos
= INTVAL (XEXP (x
, 2));
5670 /* If this goes outside the object being extracted, replace the object
5671 with a (use (mem ...)) construct that only combine understands
5672 and is used only for this purpose. */
5673 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5674 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5676 if (BITS_BIG_ENDIAN
)
5677 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5684 /* Convert sign extension to zero extension, if we know that the high
5685 bit is not set, as this is easier to optimize. It will be converted
5686 back to cheaper alternative in make_extraction. */
5687 if (GET_CODE (x
) == SIGN_EXTEND
5688 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5689 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5690 & ~(((unsigned HOST_WIDE_INT
)
5691 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5695 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5696 return expand_compound_operation (temp
);
5699 /* We can optimize some special cases of ZERO_EXTEND. */
5700 if (GET_CODE (x
) == ZERO_EXTEND
)
5702 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5703 know that the last value didn't have any inappropriate bits
5705 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5706 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5707 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5708 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5709 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5710 return XEXP (XEXP (x
, 0), 0);
5712 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5713 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5714 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5715 && subreg_lowpart_p (XEXP (x
, 0))
5716 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5717 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5718 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5719 return SUBREG_REG (XEXP (x
, 0));
5721 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5722 is a comparison and STORE_FLAG_VALUE permits. This is like
5723 the first case, but it works even when GET_MODE (x) is larger
5724 than HOST_WIDE_INT. */
5725 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5726 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5727 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5728 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5729 <= HOST_BITS_PER_WIDE_INT
)
5730 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5731 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5732 return XEXP (XEXP (x
, 0), 0);
5734 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5735 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5736 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5737 && subreg_lowpart_p (XEXP (x
, 0))
5738 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5739 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5740 <= HOST_BITS_PER_WIDE_INT
)
5741 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5742 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5743 return SUBREG_REG (XEXP (x
, 0));
5747 /* If we reach here, we want to return a pair of shifts. The inner
5748 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5749 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5750 logical depending on the value of UNSIGNEDP.
5752 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5753 converted into an AND of a shift.
5755 We must check for the case where the left shift would have a negative
5756 count. This can happen in a case like (x >> 31) & 255 on machines
5757 that can't shift by a constant. On those machines, we would first
5758 combine the shift with the AND to produce a variable-position
5759 extraction. Then the constant of 31 would be substituted in to produce
5760 a such a position. */
5762 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5763 if (modewidth
+ len
>= pos
)
5764 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5766 simplify_shift_const (NULL_RTX
, ASHIFT
,
5769 modewidth
- pos
- len
),
5772 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5773 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5774 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5777 ((HOST_WIDE_INT
) 1 << len
) - 1);
5779 /* Any other cases we can't handle. */
5782 /* If we couldn't do this for some reason, return the original
5784 if (GET_CODE (tem
) == CLOBBER
)
5790 /* X is a SET which contains an assignment of one object into
5791 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5792 or certain SUBREGS). If possible, convert it into a series of
5795 We half-heartedly support variable positions, but do not at all
5796 support variable lengths. */
5799 expand_field_assignment (x
)
5803 rtx pos
; /* Always counts from low bit. */
5806 enum machine_mode compute_mode
;
5808 /* Loop until we find something we can't simplify. */
5811 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5812 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5814 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5815 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5816 pos
= GEN_INT (BITS_PER_WORD
* SUBREG_WORD (XEXP (SET_DEST (x
), 0)));
5818 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5819 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5821 inner
= XEXP (SET_DEST (x
), 0);
5822 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5823 pos
= XEXP (SET_DEST (x
), 2);
5825 /* If the position is constant and spans the width of INNER,
5826 surround INNER with a USE to indicate this. */
5827 if (GET_CODE (pos
) == CONST_INT
5828 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5829 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5831 if (BITS_BIG_ENDIAN
)
5833 if (GET_CODE (pos
) == CONST_INT
)
5834 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5836 else if (GET_CODE (pos
) == MINUS
5837 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5838 && (INTVAL (XEXP (pos
, 1))
5839 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5840 /* If position is ADJUST - X, new position is X. */
5841 pos
= XEXP (pos
, 0);
5843 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5844 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5850 /* A SUBREG between two modes that occupy the same numbers of words
5851 can be done by moving the SUBREG to the source. */
5852 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5853 /* We need SUBREGs to compute nonzero_bits properly. */
5854 && nonzero_sign_valid
5855 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5856 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5857 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5858 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5860 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5861 gen_lowpart_for_combine
5862 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5869 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5870 inner
= SUBREG_REG (inner
);
5872 compute_mode
= GET_MODE (inner
);
5874 /* Don't attempt bitwise arithmetic on non-integral modes. */
5875 if (! INTEGRAL_MODE_P (compute_mode
))
5877 enum machine_mode imode
;
5879 /* Something is probably seriously wrong if this matches. */
5880 if (! FLOAT_MODE_P (compute_mode
))
5883 /* Try to find an integral mode to pun with. */
5884 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5885 if (imode
== BLKmode
)
5888 compute_mode
= imode
;
5889 inner
= gen_lowpart_for_combine (imode
, inner
);
5892 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5893 if (len
< HOST_BITS_PER_WIDE_INT
)
5894 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5898 /* Now compute the equivalent expression. Make a copy of INNER
5899 for the SET_DEST in case it is a MEM into which we will substitute;
5900 we don't want shared RTL in that case. */
5902 (VOIDmode
, copy_rtx (inner
),
5903 gen_binary (IOR
, compute_mode
,
5904 gen_binary (AND
, compute_mode
,
5905 gen_unary (NOT
, compute_mode
,
5911 gen_binary (ASHIFT
, compute_mode
,
5912 gen_binary (AND
, compute_mode
,
5913 gen_lowpart_for_combine
5914 (compute_mode
, SET_SRC (x
)),
5922 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5923 it is an RTX that represents a variable starting position; otherwise,
5924 POS is the (constant) starting bit position (counted from the LSB).
5926 INNER may be a USE. This will occur when we started with a bitfield
5927 that went outside the boundary of the object in memory, which is
5928 allowed on most machines. To isolate this case, we produce a USE
5929 whose mode is wide enough and surround the MEM with it. The only
5930 code that understands the USE is this routine. If it is not removed,
5931 it will cause the resulting insn not to match.
5933 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5936 IN_DEST is non-zero if this is a reference in the destination of a
5937 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5938 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5941 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5942 ZERO_EXTRACT should be built even for bits starting at bit 0.
5944 MODE is the desired mode of the result (if IN_DEST == 0).
5946 The result is an RTX for the extraction or NULL_RTX if the target
5950 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5951 unsignedp
, in_dest
, in_compare
)
5952 enum machine_mode mode
;
5956 unsigned HOST_WIDE_INT len
;
5958 int in_dest
, in_compare
;
5960 /* This mode describes the size of the storage area
5961 to fetch the overall value from. Within that, we
5962 ignore the POS lowest bits, etc. */
5963 enum machine_mode is_mode
= GET_MODE (inner
);
5964 enum machine_mode inner_mode
;
5965 enum machine_mode wanted_inner_mode
= byte_mode
;
5966 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5967 enum machine_mode pos_mode
= word_mode
;
5968 enum machine_mode extraction_mode
= word_mode
;
5969 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5972 rtx orig_pos_rtx
= pos_rtx
;
5973 HOST_WIDE_INT orig_pos
;
5975 /* Get some information about INNER and get the innermost object. */
5976 if (GET_CODE (inner
) == USE
)
5977 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5978 /* We don't need to adjust the position because we set up the USE
5979 to pretend that it was a full-word object. */
5980 spans_byte
= 1, inner
= XEXP (inner
, 0);
5981 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5983 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5984 consider just the QI as the memory to extract from.
5985 The subreg adds or removes high bits; its mode is
5986 irrelevant to the meaning of this extraction,
5987 since POS and LEN count from the lsb. */
5988 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5989 is_mode
= GET_MODE (SUBREG_REG (inner
));
5990 inner
= SUBREG_REG (inner
);
5993 inner_mode
= GET_MODE (inner
);
5995 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5996 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5998 /* See if this can be done without an extraction. We never can if the
5999 width of the field is not the same as that of some integer mode. For
6000 registers, we can only avoid the extraction if the position is at the
6001 low-order bit and this is either not in the destination or we have the
6002 appropriate STRICT_LOW_PART operation available.
6004 For MEM, we can avoid an extract if the field starts on an appropriate
6005 boundary and we can change the mode of the memory reference. However,
6006 we cannot directly access the MEM if we have a USE and the underlying
6007 MEM is not TMODE. This combination means that MEM was being used in a
6008 context where bits outside its mode were being referenced; that is only
6009 valid in bit-field insns. */
6011 if (tmode
!= BLKmode
6012 && ! (spans_byte
&& inner_mode
!= tmode
)
6013 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6014 && GET_CODE (inner
) != MEM
6016 || (GET_CODE (inner
) == REG
6017 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
6018 != CODE_FOR_nothing
))))
6019 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6021 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6022 : BITS_PER_UNIT
)) == 0
6023 /* We can't do this if we are widening INNER_MODE (it
6024 may not be aligned, for one thing). */
6025 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6026 && (inner_mode
== tmode
6027 || (! mode_dependent_address_p (XEXP (inner
, 0))
6028 && ! MEM_VOLATILE_P (inner
))))))
6030 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6031 field. If the original and current mode are the same, we need not
6032 adjust the offset. Otherwise, we do if bytes big endian.
6034 If INNER is not a MEM, get a piece consisting of just the field
6035 of interest (in this case POS % BITS_PER_WORD must be 0). */
6037 if (GET_CODE (inner
) == MEM
)
6040 /* POS counts from lsb, but make OFFSET count in memory order. */
6041 if (BYTES_BIG_ENDIAN
)
6042 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6044 offset
= pos
/ BITS_PER_UNIT
;
6046 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
6047 MEM_COPY_ATTRIBUTES (new, inner
);
6049 else if (GET_CODE (inner
) == REG
)
6051 /* We can't call gen_lowpart_for_combine here since we always want
6052 a SUBREG and it would sometimes return a new hard register. */
6053 if (tmode
!= inner_mode
)
6054 new = gen_rtx_SUBREG (tmode
, inner
,
6056 && (GET_MODE_SIZE (inner_mode
)
6058 ? (((GET_MODE_SIZE (inner_mode
)
6059 - GET_MODE_SIZE (tmode
))
6061 - pos
/ BITS_PER_WORD
)
6062 : pos
/ BITS_PER_WORD
));
6067 new = force_to_mode (inner
, tmode
,
6068 len
>= HOST_BITS_PER_WIDE_INT
6069 ? ~(unsigned HOST_WIDE_INT
) 0
6070 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6073 /* If this extraction is going into the destination of a SET,
6074 make a STRICT_LOW_PART unless we made a MEM. */
6077 return (GET_CODE (new) == MEM
? new
6078 : (GET_CODE (new) != SUBREG
6079 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6080 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
6085 /* If we know that no extraneous bits are set, and that the high
6086 bit is not set, convert the extraction to the cheaper of
6087 sign and zero extension, that are equivalent in these cases. */
6088 if (flag_expensive_optimizations
6089 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6090 && ((nonzero_bits (new, tmode
)
6091 & ~(((unsigned HOST_WIDE_INT
)
6092 GET_MODE_MASK (tmode
))
6096 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6097 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6099 /* Prefer ZERO_EXTENSION, since it gives more information to
6101 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6106 /* Otherwise, sign- or zero-extend unless we already are in the
6109 return (gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6113 /* Unless this is a COMPARE or we have a funny memory reference,
6114 don't do anything with zero-extending field extracts starting at
6115 the low-order bit since they are simple AND operations. */
6116 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6117 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6120 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6121 we would be spanning bytes or if the position is not a constant and the
6122 length is not 1. In all other cases, we would only be going outside
6123 our object in cases when an original shift would have been
6125 if (! spans_byte
&& GET_CODE (inner
) == MEM
6126 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6127 || (pos_rtx
!= 0 && len
!= 1)))
6130 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6131 and the mode for the result. */
6135 wanted_inner_reg_mode
6136 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
6137 if (wanted_inner_reg_mode
== VOIDmode
)
6138 wanted_inner_reg_mode
= word_mode
;
6140 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
6141 if (pos_mode
== VOIDmode
)
6142 pos_mode
= word_mode
;
6144 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
6145 if (extraction_mode
== VOIDmode
)
6146 extraction_mode
= word_mode
;
6151 if (! in_dest
&& unsignedp
)
6153 wanted_inner_reg_mode
6154 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
6155 if (wanted_inner_reg_mode
== VOIDmode
)
6156 wanted_inner_reg_mode
= word_mode
;
6158 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
6159 if (pos_mode
== VOIDmode
)
6160 pos_mode
= word_mode
;
6162 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
6163 if (extraction_mode
== VOIDmode
)
6164 extraction_mode
= word_mode
;
6169 if (! in_dest
&& ! unsignedp
)
6171 wanted_inner_reg_mode
6172 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
6173 if (wanted_inner_reg_mode
== VOIDmode
)
6174 wanted_inner_reg_mode
= word_mode
;
6176 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
6177 if (pos_mode
== VOIDmode
)
6178 pos_mode
= word_mode
;
6180 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
6181 if (extraction_mode
== VOIDmode
)
6182 extraction_mode
= word_mode
;
6186 /* Never narrow an object, since that might not be safe. */
6188 if (mode
!= VOIDmode
6189 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6190 extraction_mode
= mode
;
6192 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6193 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6194 pos_mode
= GET_MODE (pos_rtx
);
6196 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6197 if we have to change the mode of memory and cannot, the desired mode is
6199 if (GET_CODE (inner
) != MEM
)
6200 wanted_inner_mode
= wanted_inner_reg_mode
;
6201 else if (inner_mode
!= wanted_inner_mode
6202 && (mode_dependent_address_p (XEXP (inner
, 0))
6203 || MEM_VOLATILE_P (inner
)))
6204 wanted_inner_mode
= extraction_mode
;
6208 if (BITS_BIG_ENDIAN
)
6210 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6211 BITS_BIG_ENDIAN style. If position is constant, compute new
6212 position. Otherwise, build subtraction.
6213 Note that POS is relative to the mode of the original argument.
6214 If it's a MEM we need to recompute POS relative to that.
6215 However, if we're extracting from (or inserting into) a register,
6216 we want to recompute POS relative to wanted_inner_mode. */
6217 int width
= (GET_CODE (inner
) == MEM
6218 ? GET_MODE_BITSIZE (is_mode
)
6219 : GET_MODE_BITSIZE (wanted_inner_mode
));
6222 pos
= width
- len
- pos
;
6225 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
6226 GEN_INT (width
- len
), pos_rtx
);
6227 /* POS may be less than 0 now, but we check for that below.
6228 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6231 /* If INNER has a wider mode, make it smaller. If this is a constant
6232 extract, try to adjust the byte to point to the byte containing
6234 if (wanted_inner_mode
!= VOIDmode
6235 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6236 && ((GET_CODE (inner
) == MEM
6237 && (inner_mode
== wanted_inner_mode
6238 || (! mode_dependent_address_p (XEXP (inner
, 0))
6239 && ! MEM_VOLATILE_P (inner
))))))
6243 /* The computations below will be correct if the machine is big
6244 endian in both bits and bytes or little endian in bits and bytes.
6245 If it is mixed, we must adjust. */
6247 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6248 adjust OFFSET to compensate. */
6249 if (BYTES_BIG_ENDIAN
6251 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6252 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6254 /* If this is a constant position, we can move to the desired byte. */
6257 offset
+= pos
/ BITS_PER_UNIT
;
6258 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6261 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6263 && is_mode
!= wanted_inner_mode
)
6264 offset
= (GET_MODE_SIZE (is_mode
)
6265 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6267 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6269 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
6270 plus_constant (XEXP (inner
, 0), offset
));
6272 MEM_COPY_ATTRIBUTES (newmem
, inner
);
6277 /* If INNER is not memory, we can always get it into the proper mode. If we
6278 are changing its mode, POS must be a constant and smaller than the size
6280 else if (GET_CODE (inner
) != MEM
)
6282 if (GET_MODE (inner
) != wanted_inner_mode
6284 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6287 inner
= force_to_mode (inner
, wanted_inner_mode
,
6289 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6290 ? ~(unsigned HOST_WIDE_INT
) 0
6291 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6296 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6297 have to zero extend. Otherwise, we can just use a SUBREG. */
6299 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6301 rtx temp
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
6303 /* If we know that no extraneous bits are set, and that the high
6304 bit is not set, convert extraction to cheaper one - eighter
6305 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6307 if (flag_expensive_optimizations
6308 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6309 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6310 & ~(((unsigned HOST_WIDE_INT
)
6311 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6315 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6317 /* Prefer ZERO_EXTENSION, since it gives more information to
6319 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6324 else if (pos_rtx
!= 0
6325 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6326 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6328 /* Make POS_RTX unless we already have it and it is correct. If we don't
6329 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6331 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6332 pos_rtx
= orig_pos_rtx
;
6334 else if (pos_rtx
== 0)
6335 pos_rtx
= GEN_INT (pos
);
6337 /* Make the required operation. See if we can use existing rtx. */
6338 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6339 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6341 new = gen_lowpart_for_combine (mode
, new);
6346 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6347 with any other operations in X. Return X without that shift if so. */
6350 extract_left_shift (x
, count
)
6354 enum rtx_code code
= GET_CODE (x
);
6355 enum machine_mode mode
= GET_MODE (x
);
6361 /* This is the shift itself. If it is wide enough, we will return
6362 either the value being shifted if the shift count is equal to
6363 COUNT or a shift for the difference. */
6364 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6365 && INTVAL (XEXP (x
, 1)) >= count
)
6366 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6367 INTVAL (XEXP (x
, 1)) - count
);
6371 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6372 return gen_unary (code
, mode
, mode
, tem
);
6376 case PLUS
: case IOR
: case XOR
: case AND
:
6377 /* If we can safely shift this constant and we find the inner shift,
6378 make a new operation. */
6379 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6380 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6381 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6382 return gen_binary (code
, mode
, tem
,
6383 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6394 /* Look at the expression rooted at X. Look for expressions
6395 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6396 Form these expressions.
6398 Return the new rtx, usually just X.
6400 Also, for machines like the Vax that don't have logical shift insns,
6401 try to convert logical to arithmetic shift operations in cases where
6402 they are equivalent. This undoes the canonicalizations to logical
6403 shifts done elsewhere.
6405 We try, as much as possible, to re-use rtl expressions to save memory.
6407 IN_CODE says what kind of expression we are processing. Normally, it is
6408 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6409 being kludges), it is MEM. When processing the arguments of a comparison
6410 or a COMPARE against zero, it is COMPARE. */
6413 make_compound_operation (x
, in_code
)
6415 enum rtx_code in_code
;
6417 enum rtx_code code
= GET_CODE (x
);
6418 enum machine_mode mode
= GET_MODE (x
);
6419 int mode_width
= GET_MODE_BITSIZE (mode
);
6421 enum rtx_code next_code
;
6427 /* Select the code to be used in recursive calls. Once we are inside an
6428 address, we stay there. If we have a comparison, set to COMPARE,
6429 but once inside, go back to our default of SET. */
6431 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6432 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6433 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6434 : in_code
== COMPARE
? SET
: in_code
);
6436 /* Process depending on the code of this operation. If NEW is set
6437 non-zero, it will be returned. */
6442 /* Convert shifts by constants into multiplications if inside
6444 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6445 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6446 && INTVAL (XEXP (x
, 1)) >= 0)
6448 new = make_compound_operation (XEXP (x
, 0), next_code
);
6449 new = gen_rtx_combine (MULT
, mode
, new,
6450 GEN_INT ((HOST_WIDE_INT
) 1
6451 << INTVAL (XEXP (x
, 1))));
6456 /* If the second operand is not a constant, we can't do anything
6458 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6461 /* If the constant is a power of two minus one and the first operand
6462 is a logical right shift, make an extraction. */
6463 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6464 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6466 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6467 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6468 0, in_code
== COMPARE
);
6471 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6472 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6473 && subreg_lowpart_p (XEXP (x
, 0))
6474 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6475 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6477 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6479 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6480 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6481 0, in_code
== COMPARE
);
6483 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6484 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6485 || GET_CODE (XEXP (x
, 0)) == IOR
)
6486 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6487 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6488 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6490 /* Apply the distributive law, and then try to make extractions. */
6491 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
6492 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6494 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6496 new = make_compound_operation (new, in_code
);
6499 /* If we are have (and (rotate X C) M) and C is larger than the number
6500 of bits in M, this is an extraction. */
6502 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6503 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6504 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6505 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6507 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6508 new = make_extraction (mode
, new,
6509 (GET_MODE_BITSIZE (mode
)
6510 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6511 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6514 /* On machines without logical shifts, if the operand of the AND is
6515 a logical shift and our mask turns off all the propagated sign
6516 bits, we can replace the logical shift with an arithmetic shift. */
6517 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6518 && (lshr_optab
->handlers
[(int) mode
].insn_code
6519 == CODE_FOR_nothing
)
6520 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6521 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6522 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6523 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6524 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6526 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6528 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6529 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6531 gen_rtx_combine (ASHIFTRT
, mode
,
6532 make_compound_operation (XEXP (XEXP (x
, 0), 0),
6534 XEXP (XEXP (x
, 0), 1)));
6537 /* If the constant is one less than a power of two, this might be
6538 representable by an extraction even if no shift is present.
6539 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6540 we are in a COMPARE. */
6541 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6542 new = make_extraction (mode
,
6543 make_compound_operation (XEXP (x
, 0),
6545 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6547 /* If we are in a comparison and this is an AND with a power of two,
6548 convert this into the appropriate bit extract. */
6549 else if (in_code
== COMPARE
6550 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6551 new = make_extraction (mode
,
6552 make_compound_operation (XEXP (x
, 0),
6554 i
, NULL_RTX
, 1, 1, 0, 1);
6559 /* If the sign bit is known to be zero, replace this with an
6560 arithmetic shift. */
6561 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6562 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6563 && mode_width
<= HOST_BITS_PER_WIDE_INT
6564 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6566 new = gen_rtx_combine (ASHIFTRT
, mode
,
6567 make_compound_operation (XEXP (x
, 0),
6573 /* ... fall through ... */
6579 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6580 this is a SIGN_EXTRACT. */
6581 if (GET_CODE (rhs
) == CONST_INT
6582 && GET_CODE (lhs
) == ASHIFT
6583 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6584 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6586 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6587 new = make_extraction (mode
, new,
6588 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6589 NULL_RTX
, mode_width
- INTVAL (rhs
),
6590 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6594 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6595 If so, try to merge the shifts into a SIGN_EXTEND. We could
6596 also do this for some cases of SIGN_EXTRACT, but it doesn't
6597 seem worth the effort; the case checked for occurs on Alpha. */
6599 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6600 && ! (GET_CODE (lhs
) == SUBREG
6601 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6602 && GET_CODE (rhs
) == CONST_INT
6603 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6604 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6605 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6606 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6607 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6612 /* Call ourselves recursively on the inner expression. If we are
6613 narrowing the object and it has a different RTL code from
6614 what it originally did, do this SUBREG as a force_to_mode. */
6616 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6617 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6618 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6619 && subreg_lowpart_p (x
))
6621 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6624 /* If we have something other than a SUBREG, we might have
6625 done an expansion, so rerun outselves. */
6626 if (GET_CODE (newer
) != SUBREG
)
6627 newer
= make_compound_operation (newer
, in_code
);
6632 /* If this is a paradoxical subreg, and the new code is a sign or
6633 zero extension, omit the subreg and widen the extension. If it
6634 is a regular subreg, we can still get rid of the subreg by not
6635 widening so much, or in fact removing the extension entirely. */
6636 if ((GET_CODE (tem
) == SIGN_EXTEND
6637 || GET_CODE (tem
) == ZERO_EXTEND
)
6638 && subreg_lowpart_p (x
))
6640 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6641 || (GET_MODE_SIZE (mode
) >
6642 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6643 tem
= gen_rtx_combine (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6645 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6656 x
= gen_lowpart_for_combine (mode
, new);
6657 code
= GET_CODE (x
);
6660 /* Now recursively process each operand of this operation. */
6661 fmt
= GET_RTX_FORMAT (code
);
6662 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6665 new = make_compound_operation (XEXP (x
, i
), next_code
);
6666 SUBST (XEXP (x
, i
), new);
6672 /* Given M see if it is a value that would select a field of bits
6673 within an item, but not the entire word. Return -1 if not.
6674 Otherwise, return the starting position of the field, where 0 is the
6677 *PLEN is set to the length of the field. */
6680 get_pos_from_mask (m
, plen
)
6681 unsigned HOST_WIDE_INT m
;
6682 unsigned HOST_WIDE_INT
*plen
;
6684 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6685 int pos
= exact_log2 (m
& -m
);
6691 /* Now shift off the low-order zero bits and see if we have a power of
6693 len
= exact_log2 ((m
>> pos
) + 1);
6702 /* See if X can be simplified knowing that we will only refer to it in
6703 MODE and will only refer to those bits that are nonzero in MASK.
6704 If other bits are being computed or if masking operations are done
6705 that select a superset of the bits in MASK, they can sometimes be
6708 Return a possibly simplified expression, but always convert X to
6709 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6711 Also, if REG is non-zero and X is a register equal in value to REG,
6714 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6715 are all off in X. This is used when X will be complemented, by either
6716 NOT, NEG, or XOR. */
6719 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6721 enum machine_mode mode
;
6722 unsigned HOST_WIDE_INT mask
;
6726 enum rtx_code code
= GET_CODE (x
);
6727 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6728 enum machine_mode op_mode
;
6729 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6732 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6733 code below will do the wrong thing since the mode of such an
6734 expression is VOIDmode.
6736 Also do nothing if X is a CLOBBER; this can happen if X was
6737 the return value from a call to gen_lowpart_for_combine. */
6738 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6741 /* We want to perform the operation is its present mode unless we know
6742 that the operation is valid in MODE, in which case we do the operation
6744 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6745 && code_to_optab
[(int) code
] != 0
6746 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6747 != CODE_FOR_nothing
))
6748 ? mode
: GET_MODE (x
));
6750 /* It is not valid to do a right-shift in a narrower mode
6751 than the one it came in with. */
6752 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6753 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6754 op_mode
= GET_MODE (x
);
6756 /* Truncate MASK to fit OP_MODE. */
6758 mask
&= GET_MODE_MASK (op_mode
);
6760 /* When we have an arithmetic operation, or a shift whose count we
6761 do not know, we need to assume that all bit the up to the highest-order
6762 bit in MASK will be needed. This is how we form such a mask. */
6764 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6765 ? GET_MODE_MASK (op_mode
)
6766 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6769 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6771 /* Determine what bits of X are guaranteed to be (non)zero. */
6772 nonzero
= nonzero_bits (x
, mode
);
6774 /* If none of the bits in X are needed, return a zero. */
6775 if (! just_select
&& (nonzero
& mask
) == 0)
6778 /* If X is a CONST_INT, return a new one. Do this here since the
6779 test below will fail. */
6780 if (GET_CODE (x
) == CONST_INT
)
6782 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6783 int width
= GET_MODE_BITSIZE (mode
);
6785 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6786 number, sign extend it. */
6787 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6788 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6789 cval
|= (HOST_WIDE_INT
) -1 << width
;
6791 return GEN_INT (cval
);
6794 /* If X is narrower than MODE and we want all the bits in X's mode, just
6795 get X in the proper mode. */
6796 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6797 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6798 return gen_lowpart_for_combine (mode
, x
);
6800 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6801 MASK are already known to be zero in X, we need not do anything. */
6802 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6808 /* If X is a (clobber (const_int)), return it since we know we are
6809 generating something that won't match. */
6813 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6814 spanned the boundary of the MEM. If we are now masking so it is
6815 within that boundary, we don't need the USE any more. */
6816 if (! BITS_BIG_ENDIAN
6817 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6818 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6825 x
= expand_compound_operation (x
);
6826 if (GET_CODE (x
) != code
)
6827 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6831 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6832 || rtx_equal_p (reg
, get_last_value (x
))))
6837 if (subreg_lowpart_p (x
)
6838 /* We can ignore the effect of this SUBREG if it narrows the mode or
6839 if the constant masks to zero all the bits the mode doesn't
6841 && ((GET_MODE_SIZE (GET_MODE (x
))
6842 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6844 & GET_MODE_MASK (GET_MODE (x
))
6845 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6846 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6850 /* If this is an AND with a constant, convert it into an AND
6851 whose constant is the AND of that constant with MASK. If it
6852 remains an AND of MASK, delete it since it is redundant. */
6854 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6856 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6857 mask
& INTVAL (XEXP (x
, 1)));
6859 /* If X is still an AND, see if it is an AND with a mask that
6860 is just some low-order bits. If so, and it is MASK, we don't
6863 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6864 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6867 /* If it remains an AND, try making another AND with the bits
6868 in the mode mask that aren't in MASK turned on. If the
6869 constant in the AND is wide enough, this might make a
6870 cheaper constant. */
6872 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6873 && GET_MODE_MASK (GET_MODE (x
)) != mask
6874 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6876 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6877 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6878 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6881 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6882 number, sign extend it. */
6883 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6884 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6885 cval
|= (HOST_WIDE_INT
) -1 << width
;
6887 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6888 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6898 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6899 low-order bits (as in an alignment operation) and FOO is already
6900 aligned to that boundary, mask C1 to that boundary as well.
6901 This may eliminate that PLUS and, later, the AND. */
6904 unsigned int width
= GET_MODE_BITSIZE (mode
);
6905 unsigned HOST_WIDE_INT smask
= mask
;
6907 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6908 number, sign extend it. */
6910 if (width
< HOST_BITS_PER_WIDE_INT
6911 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6912 smask
|= (HOST_WIDE_INT
) -1 << width
;
6914 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6915 && exact_log2 (- smask
) >= 0)
6919 && (XEXP (x
, 0) == stack_pointer_rtx
6920 || XEXP (x
, 0) == frame_pointer_rtx
))
6922 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6923 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6925 sp_mask
&= ~(sp_alignment
- 1);
6926 if ((sp_mask
& ~smask
) == 0
6927 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6928 return force_to_mode (plus_constant (XEXP (x
, 0),
6929 ((INTVAL (XEXP (x
, 1)) -
6930 STACK_BIAS
) & smask
)
6932 mode
, smask
, reg
, next_select
);
6935 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6936 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6937 return force_to_mode (plus_constant (XEXP (x
, 0),
6938 (INTVAL (XEXP (x
, 1))
6940 mode
, smask
, reg
, next_select
);
6944 /* ... fall through ... */
6947 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6948 most significant bit in MASK since carries from those bits will
6949 affect the bits we are interested in. */
6954 /* If X is (minus C Y) where C's least set bit is larger than any bit
6955 in the mask, then we may replace with (neg Y). */
6956 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6957 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6958 & -INTVAL (XEXP (x
, 0))))
6961 x
= gen_unary (NEG
, GET_MODE (x
), GET_MODE (x
), XEXP (x
, 1));
6962 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6965 /* Similarly, if C contains every bit in the mask, then we may
6966 replace with (not Y). */
6967 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6968 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6969 == INTVAL (XEXP (x
, 0))))
6971 x
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), XEXP (x
, 1));
6972 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6980 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6981 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6982 operation which may be a bitfield extraction. Ensure that the
6983 constant we form is not wider than the mode of X. */
6985 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6986 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6987 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6988 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6989 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6990 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6991 + floor_log2 (INTVAL (XEXP (x
, 1))))
6992 < GET_MODE_BITSIZE (GET_MODE (x
)))
6993 && (INTVAL (XEXP (x
, 1))
6994 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6996 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6997 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6998 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6999 XEXP (XEXP (x
, 0), 0), temp
);
7000 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7001 XEXP (XEXP (x
, 0), 1));
7002 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7006 /* For most binary operations, just propagate into the operation and
7007 change the mode if we have an operation of that mode. */
7009 op0
= gen_lowpart_for_combine (op_mode
,
7010 force_to_mode (XEXP (x
, 0), mode
, mask
,
7012 op1
= gen_lowpart_for_combine (op_mode
,
7013 force_to_mode (XEXP (x
, 1), mode
, mask
,
7016 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
7017 MASK since OP1 might have been sign-extended but we never want
7018 to turn on extra bits, since combine might have previously relied
7019 on them being off. */
7020 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
7021 && (INTVAL (op1
) & mask
) != 0)
7022 op1
= GEN_INT (INTVAL (op1
) & mask
);
7024 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7025 x
= gen_binary (code
, op_mode
, op0
, op1
);
7029 /* For left shifts, do the same, but just for the first operand.
7030 However, we cannot do anything with shifts where we cannot
7031 guarantee that the counts are smaller than the size of the mode
7032 because such a count will have a different meaning in a
7035 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7036 && INTVAL (XEXP (x
, 1)) >= 0
7037 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7038 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7039 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7040 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7043 /* If the shift count is a constant and we can do arithmetic in
7044 the mode of the shift, refine which bits we need. Otherwise, use the
7045 conservative form of the mask. */
7046 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7047 && INTVAL (XEXP (x
, 1)) >= 0
7048 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7049 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7050 mask
>>= INTVAL (XEXP (x
, 1));
7054 op0
= gen_lowpart_for_combine (op_mode
,
7055 force_to_mode (XEXP (x
, 0), op_mode
,
7056 mask
, reg
, next_select
));
7058 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7059 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7063 /* Here we can only do something if the shift count is a constant,
7064 this shift constant is valid for the host, and we can do arithmetic
7067 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7068 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7069 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7071 rtx inner
= XEXP (x
, 0);
7072 unsigned HOST_WIDE_INT inner_mask
;
7074 /* Select the mask of the bits we need for the shift operand. */
7075 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7077 /* We can only change the mode of the shift if we can do arithmetic
7078 in the mode of the shift and INNER_MASK is no wider than the
7079 width of OP_MODE. */
7080 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7081 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7082 op_mode
= GET_MODE (x
);
7084 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7086 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7087 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7090 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7091 shift and AND produces only copies of the sign bit (C2 is one less
7092 than a power of two), we can do this with just a shift. */
7094 if (GET_CODE (x
) == LSHIFTRT
7095 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7096 /* The shift puts one of the sign bit copies in the least significant
7098 && ((INTVAL (XEXP (x
, 1))
7099 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7100 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7101 && exact_log2 (mask
+ 1) >= 0
7102 /* Number of bits left after the shift must be more than the mask
7104 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7105 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7106 /* Must be more sign bit copies than the mask needs. */
7107 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7108 >= exact_log2 (mask
+ 1)))
7109 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7110 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7111 - exact_log2 (mask
+ 1)));
7116 /* If we are just looking for the sign bit, we don't need this shift at
7117 all, even if it has a variable count. */
7118 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7119 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7120 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7121 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7123 /* If this is a shift by a constant, get a mask that contains those bits
7124 that are not copies of the sign bit. We then have two cases: If
7125 MASK only includes those bits, this can be a logical shift, which may
7126 allow simplifications. If MASK is a single-bit field not within
7127 those bits, we are requesting a copy of the sign bit and hence can
7128 shift the sign bit to the appropriate location. */
7130 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7131 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7135 /* If the considered data is wider then HOST_WIDE_INT, we can't
7136 represent a mask for all its bits in a single scalar.
7137 But we only care about the lower bits, so calculate these. */
7139 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7141 nonzero
= ~(HOST_WIDE_INT
) 0;
7143 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7144 is the number of bits a full-width mask would have set.
7145 We need only shift if these are fewer than nonzero can
7146 hold. If not, we must keep all bits set in nonzero. */
7148 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7149 < HOST_BITS_PER_WIDE_INT
)
7150 nonzero
>>= INTVAL (XEXP (x
, 1))
7151 + HOST_BITS_PER_WIDE_INT
7152 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7156 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7157 nonzero
>>= INTVAL (XEXP (x
, 1));
7160 if ((mask
& ~nonzero
) == 0
7161 || (i
= exact_log2 (mask
)) >= 0)
7163 x
= simplify_shift_const
7164 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7165 i
< 0 ? INTVAL (XEXP (x
, 1))
7166 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7168 if (GET_CODE (x
) != ASHIFTRT
)
7169 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7173 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7174 even if the shift count isn't a constant. */
7176 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7180 /* If this is a zero- or sign-extension operation that just affects bits
7181 we don't care about, remove it. Be sure the call above returned
7182 something that is still a shift. */
7184 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7185 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7186 && INTVAL (XEXP (x
, 1)) >= 0
7187 && (INTVAL (XEXP (x
, 1))
7188 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7189 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7190 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7191 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7192 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7199 /* If the shift count is constant and we can do computations
7200 in the mode of X, compute where the bits we care about are.
7201 Otherwise, we can't do anything. Don't change the mode of
7202 the shift or propagate MODE into the shift, though. */
7203 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7204 && INTVAL (XEXP (x
, 1)) >= 0)
7206 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7207 GET_MODE (x
), GEN_INT (mask
),
7209 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7211 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7212 INTVAL (temp
), reg
, next_select
));
7217 /* If we just want the low-order bit, the NEG isn't needed since it
7218 won't change the low-order bit. */
7220 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7222 /* We need any bits less significant than the most significant bit in
7223 MASK since carries from those bits will affect the bits we are
7229 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7230 same as the XOR case above. Ensure that the constant we form is not
7231 wider than the mode of X. */
7233 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7234 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7235 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7236 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7237 < GET_MODE_BITSIZE (GET_MODE (x
)))
7238 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7240 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7241 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7242 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7244 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7247 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7248 use the full mask inside the NOT. */
7252 op0
= gen_lowpart_for_combine (op_mode
,
7253 force_to_mode (XEXP (x
, 0), mode
, mask
,
7255 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7256 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
7260 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7261 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7262 which is equal to STORE_FLAG_VALUE. */
7263 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7264 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7265 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7266 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7271 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7272 written in a narrower mode. We play it safe and do not do so. */
7275 gen_lowpart_for_combine (GET_MODE (x
),
7276 force_to_mode (XEXP (x
, 1), mode
,
7277 mask
, reg
, next_select
)));
7279 gen_lowpart_for_combine (GET_MODE (x
),
7280 force_to_mode (XEXP (x
, 2), mode
,
7281 mask
, reg
,next_select
)));
7288 /* Ensure we return a value of the proper mode. */
7289 return gen_lowpart_for_combine (mode
, x
);
7292 /* Return nonzero if X is an expression that has one of two values depending on
7293 whether some other value is zero or nonzero. In that case, we return the
7294 value that is being tested, *PTRUE is set to the value if the rtx being
7295 returned has a nonzero value, and *PFALSE is set to the other alternative.
7297 If we return zero, we set *PTRUE and *PFALSE to X. */
7300 if_then_else_cond (x
, ptrue
, pfalse
)
7302 rtx
*ptrue
, *pfalse
;
7304 enum machine_mode mode
= GET_MODE (x
);
7305 enum rtx_code code
= GET_CODE (x
);
7306 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7307 unsigned HOST_WIDE_INT nz
;
7309 /* If we are comparing a value against zero, we are done. */
7310 if ((code
== NE
|| code
== EQ
)
7311 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7313 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7314 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7318 /* If this is a unary operation whose operand has one of two values, apply
7319 our opcode to compute those values. */
7320 else if (GET_RTX_CLASS (code
) == '1'
7321 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7323 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
7324 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
7328 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7329 make can't possibly match and would suppress other optimizations. */
7330 else if (code
== COMPARE
)
7333 /* If this is a binary operation, see if either side has only one of two
7334 values. If either one does or if both do and they are conditional on
7335 the same value, compute the new true and false values. */
7336 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7337 || GET_RTX_CLASS (code
) == '<')
7339 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7340 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7342 if ((cond0
!= 0 || cond1
!= 0)
7343 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7345 /* If if_then_else_cond returned zero, then true/false are the
7346 same rtl. We must copy one of them to prevent invalid rtl
7349 true0
= copy_rtx (true0
);
7350 else if (cond1
== 0)
7351 true1
= copy_rtx (true1
);
7353 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7354 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7355 return cond0
? cond0
: cond1
;
7358 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7359 operands is zero when the other is non-zero, and vice-versa,
7360 and STORE_FLAG_VALUE is 1 or -1. */
7362 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7363 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7365 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7367 rtx op0
= XEXP (XEXP (x
, 0), 1);
7368 rtx op1
= XEXP (XEXP (x
, 1), 1);
7370 cond0
= XEXP (XEXP (x
, 0), 0);
7371 cond1
= XEXP (XEXP (x
, 1), 0);
7373 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7374 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7375 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7376 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7377 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7378 || ((swap_condition (GET_CODE (cond0
))
7379 == combine_reversed_comparison_code (cond1
))
7380 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7381 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7382 && ! side_effects_p (x
))
7384 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7385 *pfalse
= gen_binary (MULT
, mode
,
7387 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
7393 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7395 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7396 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7397 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7399 cond0
= XEXP (XEXP (x
, 0), 0);
7400 cond1
= XEXP (XEXP (x
, 1), 0);
7402 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7403 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7404 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7405 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7406 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7407 || ((swap_condition (GET_CODE (cond0
))
7408 == combine_reversed_comparison_code (cond1
))
7409 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7410 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7411 && ! side_effects_p (x
))
7413 *ptrue
= *pfalse
= const0_rtx
;
7419 else if (code
== IF_THEN_ELSE
)
7421 /* If we have IF_THEN_ELSE already, extract the condition and
7422 canonicalize it if it is NE or EQ. */
7423 cond0
= XEXP (x
, 0);
7424 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7425 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7426 return XEXP (cond0
, 0);
7427 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7429 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7430 return XEXP (cond0
, 0);
7436 /* If X is a normal SUBREG with both inner and outer modes integral,
7437 we can narrow both the true and false values of the inner expression,
7438 if there is a condition. */
7439 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
7440 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
7441 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
7442 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7445 if ((GET_CODE (SUBREG_REG (x
)) == REG
7446 || GET_CODE (SUBREG_REG (x
)) == MEM
7447 || CONSTANT_P (SUBREG_REG (x
)))
7448 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
7449 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
7451 true0
= operand_subword (true0
, SUBREG_WORD (x
), 0,
7452 GET_MODE (SUBREG_REG (x
)));
7453 false0
= operand_subword (false0
, SUBREG_WORD (x
), 0,
7454 GET_MODE (SUBREG_REG (x
)));
7456 *ptrue
= force_to_mode (true0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7458 = force_to_mode (false0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7463 /* If X is a constant, this isn't special and will cause confusions
7464 if we treat it as such. Likewise if it is equivalent to a constant. */
7465 else if (CONSTANT_P (x
)
7466 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7469 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7470 will be least confusing to the rest of the compiler. */
7471 else if (mode
== BImode
)
7473 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7477 /* If X is known to be either 0 or -1, those are the true and
7478 false values when testing X. */
7479 else if (x
== constm1_rtx
|| x
== const0_rtx
7480 || (mode
!= VOIDmode
7481 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7483 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7487 /* Likewise for 0 or a single bit. */
7488 else if (mode
!= VOIDmode
7489 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7490 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7492 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7496 /* Otherwise fail; show no condition with true and false values the same. */
7497 *ptrue
= *pfalse
= x
;
7501 /* Return the value of expression X given the fact that condition COND
7502 is known to be true when applied to REG as its first operand and VAL
7503 as its second. X is known to not be shared and so can be modified in
7506 We only handle the simplest cases, and specifically those cases that
7507 arise with IF_THEN_ELSE expressions. */
7510 known_cond (x
, cond
, reg
, val
)
7515 enum rtx_code code
= GET_CODE (x
);
7520 if (side_effects_p (x
))
7523 if (cond
== EQ
&& rtx_equal_p (x
, reg
) && !FLOAT_MODE_P (cond
))
7525 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7528 /* If X is (abs REG) and we know something about REG's relationship
7529 with zero, we may be able to simplify this. */
7531 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7534 case GE
: case GT
: case EQ
:
7537 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
7543 /* The only other cases we handle are MIN, MAX, and comparisons if the
7544 operands are the same as REG and VAL. */
7546 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7548 if (rtx_equal_p (XEXP (x
, 0), val
))
7549 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7551 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7553 if (GET_RTX_CLASS (code
) == '<')
7555 if (comparison_dominates_p (cond
, code
))
7556 return const_true_rtx
;
7558 code
= combine_reversed_comparison_code (x
);
7560 && comparison_dominates_p (cond
, code
))
7565 else if (code
== SMAX
|| code
== SMIN
7566 || code
== UMIN
|| code
== UMAX
)
7568 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7570 if (code
== SMAX
|| code
== UMAX
)
7571 cond
= reverse_condition (cond
);
7576 return unsignedp
? x
: XEXP (x
, 1);
7578 return unsignedp
? x
: XEXP (x
, 0);
7580 return unsignedp
? XEXP (x
, 1) : x
;
7582 return unsignedp
? XEXP (x
, 0) : x
;
7590 fmt
= GET_RTX_FORMAT (code
);
7591 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7594 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7595 else if (fmt
[i
] == 'E')
7596 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7597 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7604 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7605 assignment as a field assignment. */
7608 rtx_equal_for_field_assignment_p (x
, y
)
7612 if (x
== y
|| rtx_equal_p (x
, y
))
7615 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7618 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7619 Note that all SUBREGs of MEM are paradoxical; otherwise they
7620 would have been rewritten. */
7621 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7622 && GET_CODE (SUBREG_REG (y
)) == MEM
7623 && rtx_equal_p (SUBREG_REG (y
),
7624 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7627 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7628 && GET_CODE (SUBREG_REG (x
)) == MEM
7629 && rtx_equal_p (SUBREG_REG (x
),
7630 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7633 /* We used to see if get_last_value of X and Y were the same but that's
7634 not correct. In one direction, we'll cause the assignment to have
7635 the wrong destination and in the case, we'll import a register into this
7636 insn that might have already have been dead. So fail if none of the
7637 above cases are true. */
7641 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7642 Return that assignment if so.
7644 We only handle the most common cases. */
7647 make_field_assignment (x
)
7650 rtx dest
= SET_DEST (x
);
7651 rtx src
= SET_SRC (x
);
7656 unsigned HOST_WIDE_INT len
;
7658 enum machine_mode mode
;
7660 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7661 a clear of a one-bit field. We will have changed it to
7662 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7665 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7666 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7667 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7668 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7670 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7673 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7677 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7678 && subreg_lowpart_p (XEXP (src
, 0))
7679 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7680 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7681 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7682 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7683 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7685 assign
= make_extraction (VOIDmode
, dest
, 0,
7686 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7689 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7693 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7695 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7696 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7697 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7699 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7702 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7706 /* The other case we handle is assignments into a constant-position
7707 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7708 a mask that has all one bits except for a group of zero bits and
7709 OTHER is known to have zeros where C1 has ones, this is such an
7710 assignment. Compute the position and length from C1. Shift OTHER
7711 to the appropriate position, force it to the required mode, and
7712 make the extraction. Check for the AND in both operands. */
7714 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7717 rhs
= expand_compound_operation (XEXP (src
, 0));
7718 lhs
= expand_compound_operation (XEXP (src
, 1));
7720 if (GET_CODE (rhs
) == AND
7721 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7722 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7723 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7724 else if (GET_CODE (lhs
) == AND
7725 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7726 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7727 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7731 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7732 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7733 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7734 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7737 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7741 /* The mode to use for the source is the mode of the assignment, or of
7742 what is inside a possible STRICT_LOW_PART. */
7743 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7744 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7746 /* Shift OTHER right POS places and make it the source, restricting it
7747 to the proper length and mode. */
7749 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7750 GET_MODE (src
), other
, pos
),
7752 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7753 ? ~(unsigned HOST_WIDE_INT
) 0
7754 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7757 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
7760 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7764 apply_distributive_law (x
)
7767 enum rtx_code code
= GET_CODE (x
);
7768 rtx lhs
, rhs
, other
;
7770 enum rtx_code inner_code
;
7772 /* Distributivity is not true for floating point.
7773 It can change the value. So don't do it.
7774 -- rms and moshier@world.std.com. */
7775 if (FLOAT_MODE_P (GET_MODE (x
)))
7778 /* The outer operation can only be one of the following: */
7779 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7780 && code
!= PLUS
&& code
!= MINUS
)
7783 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7785 /* If either operand is a primitive we can't do anything, so get out
7787 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7788 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7791 lhs
= expand_compound_operation (lhs
);
7792 rhs
= expand_compound_operation (rhs
);
7793 inner_code
= GET_CODE (lhs
);
7794 if (inner_code
!= GET_CODE (rhs
))
7797 /* See if the inner and outer operations distribute. */
7804 /* These all distribute except over PLUS. */
7805 if (code
== PLUS
|| code
== MINUS
)
7810 if (code
!= PLUS
&& code
!= MINUS
)
7815 /* This is also a multiply, so it distributes over everything. */
7819 /* Non-paradoxical SUBREGs distributes over all operations, provided
7820 the inner modes and word numbers are the same, this is an extraction
7821 of a low-order part, we don't convert an fp operation to int or
7822 vice versa, and we would not be converting a single-word
7823 operation into a multi-word operation. The latter test is not
7824 required, but it prevents generating unneeded multi-word operations.
7825 Some of the previous tests are redundant given the latter test, but
7826 are retained because they are required for correctness.
7828 We produce the result slightly differently in this case. */
7830 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7831 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
7832 || ! subreg_lowpart_p (lhs
)
7833 || (GET_MODE_CLASS (GET_MODE (lhs
))
7834 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7835 || (GET_MODE_SIZE (GET_MODE (lhs
))
7836 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7837 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7840 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7841 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7842 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7848 /* Set LHS and RHS to the inner operands (A and B in the example
7849 above) and set OTHER to the common operand (C in the example).
7850 These is only one way to do this unless the inner operation is
7852 if (GET_RTX_CLASS (inner_code
) == 'c'
7853 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7854 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7855 else if (GET_RTX_CLASS (inner_code
) == 'c'
7856 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7857 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7858 else if (GET_RTX_CLASS (inner_code
) == 'c'
7859 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7860 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7861 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7862 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7866 /* Form the new inner operation, seeing if it simplifies first. */
7867 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7869 /* There is one exception to the general way of distributing:
7870 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7871 if (code
== XOR
&& inner_code
== IOR
)
7874 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
7877 /* We may be able to continuing distributing the result, so call
7878 ourselves recursively on the inner operation before forming the
7879 outer operation, which we return. */
7880 return gen_binary (inner_code
, GET_MODE (x
),
7881 apply_distributive_law (tem
), other
);
7884 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7887 Return an equivalent form, if different from X. Otherwise, return X. If
7888 X is zero, we are to always construct the equivalent form. */
7891 simplify_and_const_int (x
, mode
, varop
, constop
)
7893 enum machine_mode mode
;
7895 unsigned HOST_WIDE_INT constop
;
7897 unsigned HOST_WIDE_INT nonzero
;
7900 /* Simplify VAROP knowing that we will be only looking at some of the
7902 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7904 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7905 CONST_INT, we are done. */
7906 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7909 /* See what bits may be nonzero in VAROP. Unlike the general case of
7910 a call to nonzero_bits, here we don't care about bits outside
7913 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7914 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7916 /* Turn off all bits in the constant that are known to already be zero.
7917 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7918 which is tested below. */
7922 /* If we don't have any bits left, return zero. */
7926 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7927 a power of two, we can replace this with a ASHIFT. */
7928 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7929 && (i
= exact_log2 (constop
)) >= 0)
7930 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7932 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7933 or XOR, then try to apply the distributive law. This may eliminate
7934 operations if either branch can be simplified because of the AND.
7935 It may also make some cases more complex, but those cases probably
7936 won't match a pattern either with or without this. */
7938 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7940 gen_lowpart_for_combine
7942 apply_distributive_law
7943 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7944 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7945 XEXP (varop
, 0), constop
),
7946 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7947 XEXP (varop
, 1), constop
))));
7949 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7950 if we already had one (just check for the simplest cases). */
7951 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7952 && GET_MODE (XEXP (x
, 0)) == mode
7953 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7954 varop
= XEXP (x
, 0);
7956 varop
= gen_lowpart_for_combine (mode
, varop
);
7958 /* If we can't make the SUBREG, try to return what we were given. */
7959 if (GET_CODE (varop
) == CLOBBER
)
7960 return x
? x
: varop
;
7962 /* If we are only masking insignificant bits, return VAROP. */
7963 if (constop
== nonzero
)
7966 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7967 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7968 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7972 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7973 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7974 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7976 SUBST (XEXP (x
, 0), varop
);
7982 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7983 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7984 is less useful. We can't allow both, because that results in exponential
7985 run time recursion. There is a nullstone testcase that triggered
7986 this. This macro avoids accidental uses of num_sign_bit_copies. */
7987 #define num_sign_bit_copies()
7989 /* Given an expression, X, compute which bits in X can be non-zero.
7990 We don't care about bits outside of those defined in MODE.
7992 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7993 a shift, AND, or zero_extract, we can do better. */
7995 static unsigned HOST_WIDE_INT
7996 nonzero_bits (x
, mode
)
7998 enum machine_mode mode
;
8000 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8001 unsigned HOST_WIDE_INT inner_nz
;
8003 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8006 /* For floating-point values, assume all bits are needed. */
8007 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8010 /* If X is wider than MODE, use its mode instead. */
8011 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8013 mode
= GET_MODE (x
);
8014 nonzero
= GET_MODE_MASK (mode
);
8015 mode_width
= GET_MODE_BITSIZE (mode
);
8018 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8019 /* Our only callers in this case look for single bit values. So
8020 just return the mode mask. Those tests will then be false. */
8023 #ifndef WORD_REGISTER_OPERATIONS
8024 /* If MODE is wider than X, but both are a single word for both the host
8025 and target machines, we can compute this from which bits of the
8026 object might be nonzero in its own mode, taking into account the fact
8027 that on many CISC machines, accessing an object in a wider mode
8028 causes the high-order bits to become undefined. So they are
8029 not known to be zero. */
8031 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8032 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8033 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8034 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8036 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
8037 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8042 code
= GET_CODE (x
);
8046 #ifdef POINTERS_EXTEND_UNSIGNED
8047 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8048 all the bits above ptr_mode are known to be zero. */
8049 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8051 nonzero
&= GET_MODE_MASK (ptr_mode
);
8054 #ifdef STACK_BOUNDARY
8055 /* If this is the stack pointer, we may know something about its
8056 alignment. If PUSH_ROUNDING is defined, it is possible for the
8057 stack to be momentarily aligned only to that amount, so we pick
8058 the least alignment. */
8060 /* We can't check for arg_pointer_rtx here, because it is not
8061 guaranteed to have as much alignment as the stack pointer.
8062 In particular, in the Irix6 n64 ABI, the stack has 128 bit
8063 alignment but the argument pointer has only 64 bit alignment. */
8065 if ((x
== frame_pointer_rtx
8066 || x
== stack_pointer_rtx
8067 || x
== hard_frame_pointer_rtx
8068 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
8069 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
8075 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8077 #ifdef PUSH_ROUNDING
8078 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
8079 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
8082 /* We must return here, otherwise we may get a worse result from
8083 one of the choices below. There is nothing useful below as
8084 far as the stack pointer is concerned. */
8085 return nonzero
&= ~(sp_alignment
- 1);
8089 /* If X is a register whose nonzero bits value is current, use it.
8090 Otherwise, if X is a register whose value we can find, use that
8091 value. Otherwise, use the previously-computed global nonzero bits
8092 for this register. */
8094 if (reg_last_set_value
[REGNO (x
)] != 0
8095 && reg_last_set_mode
[REGNO (x
)] == mode
8096 && (reg_last_set_label
[REGNO (x
)] == label_tick
8097 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8098 && REG_N_SETS (REGNO (x
)) == 1
8099 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8101 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8102 return reg_last_set_nonzero_bits
[REGNO (x
)];
8104 tem
= get_last_value (x
);
8108 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8109 /* If X is narrower than MODE and TEM is a non-negative
8110 constant that would appear negative in the mode of X,
8111 sign-extend it for use in reg_nonzero_bits because some
8112 machines (maybe most) will actually do the sign-extension
8113 and this is the conservative approach.
8115 ??? For 2.5, try to tighten up the MD files in this regard
8116 instead of this kludge. */
8118 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8119 && GET_CODE (tem
) == CONST_INT
8121 && 0 != (INTVAL (tem
)
8122 & ((HOST_WIDE_INT
) 1
8123 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8124 tem
= GEN_INT (INTVAL (tem
)
8125 | ((HOST_WIDE_INT
) (-1)
8126 << GET_MODE_BITSIZE (GET_MODE (x
))));
8128 return nonzero_bits (tem
, mode
);
8130 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8131 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
8136 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8137 /* If X is negative in MODE, sign-extend the value. */
8138 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8139 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8140 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8146 #ifdef LOAD_EXTEND_OP
8147 /* In many, if not most, RISC machines, reading a byte from memory
8148 zeros the rest of the register. Noticing that fact saves a lot
8149 of extra zero-extends. */
8150 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8151 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8156 case UNEQ
: case LTGT
:
8157 case GT
: case GTU
: case UNGT
:
8158 case LT
: case LTU
: case UNLT
:
8159 case GE
: case GEU
: case UNGE
:
8160 case LE
: case LEU
: case UNLE
:
8161 case UNORDERED
: case ORDERED
:
8163 /* If this produces an integer result, we know which bits are set.
8164 Code here used to clear bits outside the mode of X, but that is
8167 if (GET_MODE_CLASS (mode
) == MODE_INT
8168 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8169 nonzero
= STORE_FLAG_VALUE
;
8174 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8175 and num_sign_bit_copies. */
8176 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8177 == GET_MODE_BITSIZE (GET_MODE (x
)))
8181 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8182 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8187 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8188 and num_sign_bit_copies. */
8189 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8190 == GET_MODE_BITSIZE (GET_MODE (x
)))
8196 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8200 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8201 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8202 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8206 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8207 Otherwise, show all the bits in the outer mode but not the inner
8209 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8210 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8212 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8214 & (((HOST_WIDE_INT
) 1
8215 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8216 inner_nz
|= (GET_MODE_MASK (mode
)
8217 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8220 nonzero
&= inner_nz
;
8224 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8225 & nonzero_bits (XEXP (x
, 1), mode
));
8229 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8230 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8231 | nonzero_bits (XEXP (x
, 1), mode
));
8234 case PLUS
: case MINUS
:
8236 case DIV
: case UDIV
:
8237 case MOD
: case UMOD
:
8238 /* We can apply the rules of arithmetic to compute the number of
8239 high- and low-order zero bits of these operations. We start by
8240 computing the width (position of the highest-order non-zero bit)
8241 and the number of low-order zero bits for each value. */
8243 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8244 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8245 int width0
= floor_log2 (nz0
) + 1;
8246 int width1
= floor_log2 (nz1
) + 1;
8247 int low0
= floor_log2 (nz0
& -nz0
);
8248 int low1
= floor_log2 (nz1
& -nz1
);
8249 HOST_WIDE_INT op0_maybe_minusp
8250 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8251 HOST_WIDE_INT op1_maybe_minusp
8252 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8253 unsigned int result_width
= mode_width
;
8261 && (XEXP (x
, 0) == stack_pointer_rtx
8262 || XEXP (x
, 0) == frame_pointer_rtx
)
8263 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8265 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8267 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8268 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8269 width0
= floor_log2 (nz0
) + 1;
8270 width1
= floor_log2 (nz1
) + 1;
8271 low0
= floor_log2 (nz0
& -nz0
);
8272 low1
= floor_log2 (nz1
& -nz1
);
8275 result_width
= MAX (width0
, width1
) + 1;
8276 result_low
= MIN (low0
, low1
);
8279 result_low
= MIN (low0
, low1
);
8282 result_width
= width0
+ width1
;
8283 result_low
= low0
+ low1
;
8286 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8287 result_width
= width0
;
8290 result_width
= width0
;
8293 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8294 result_width
= MIN (width0
, width1
);
8295 result_low
= MIN (low0
, low1
);
8298 result_width
= MIN (width0
, width1
);
8299 result_low
= MIN (low0
, low1
);
8305 if (result_width
< mode_width
)
8306 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8309 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8311 #ifdef POINTERS_EXTEND_UNSIGNED
8312 /* If pointers extend unsigned and this is an addition or subtraction
8313 to a pointer in Pmode, all the bits above ptr_mode are known to be
8315 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8316 && (code
== PLUS
|| code
== MINUS
)
8317 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8318 nonzero
&= GET_MODE_MASK (ptr_mode
);
8324 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8325 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8326 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8330 /* If this is a SUBREG formed for a promoted variable that has
8331 been zero-extended, we know that at least the high-order bits
8332 are zero, though others might be too. */
8334 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8335 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8336 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8338 /* If the inner mode is a single word for both the host and target
8339 machines, we can compute this from which bits of the inner
8340 object might be nonzero. */
8341 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8342 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8343 <= HOST_BITS_PER_WIDE_INT
))
8345 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8347 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8348 /* If this is a typical RISC machine, we only have to worry
8349 about the way loads are extended. */
8350 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8352 & (((unsigned HOST_WIDE_INT
) 1
8353 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8355 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8358 /* On many CISC machines, accessing an object in a wider mode
8359 causes the high-order bits to become undefined. So they are
8360 not known to be zero. */
8361 if (GET_MODE_SIZE (GET_MODE (x
))
8362 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8363 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8364 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8373 /* The nonzero bits are in two classes: any bits within MODE
8374 that aren't in GET_MODE (x) are always significant. The rest of the
8375 nonzero bits are those that are significant in the operand of
8376 the shift when shifted the appropriate number of bits. This
8377 shows that high-order bits are cleared by the right shift and
8378 low-order bits by left shifts. */
8379 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8380 && INTVAL (XEXP (x
, 1)) >= 0
8381 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8383 enum machine_mode inner_mode
= GET_MODE (x
);
8384 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8385 int count
= INTVAL (XEXP (x
, 1));
8386 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8387 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8388 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8389 unsigned HOST_WIDE_INT outer
= 0;
8391 if (mode_width
> width
)
8392 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8394 if (code
== LSHIFTRT
)
8396 else if (code
== ASHIFTRT
)
8400 /* If the sign bit may have been nonzero before the shift, we
8401 need to mark all the places it could have been copied to
8402 by the shift as possibly nonzero. */
8403 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8404 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8406 else if (code
== ASHIFT
)
8409 inner
= ((inner
<< (count
% width
)
8410 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8412 nonzero
&= (outer
| inner
);
8417 /* This is at most the number of bits in the mode. */
8418 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8422 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8423 | nonzero_bits (XEXP (x
, 2), mode
));
8433 /* See the macro definition above. */
8434 #undef num_sign_bit_copies
8436 /* Return the number of bits at the high-order end of X that are known to
8437 be equal to the sign bit. X will be used in mode MODE; if MODE is
8438 VOIDmode, X will be used in its own mode. The returned value will always
8439 be between 1 and the number of bits in MODE. */
8442 num_sign_bit_copies (x
, mode
)
8444 enum machine_mode mode
;
8446 enum rtx_code code
= GET_CODE (x
);
8447 unsigned int bitwidth
;
8448 int num0
, num1
, result
;
8449 unsigned HOST_WIDE_INT nonzero
;
8452 /* If we weren't given a mode, use the mode of X. If the mode is still
8453 VOIDmode, we don't know anything. Likewise if one of the modes is
8456 if (mode
== VOIDmode
)
8457 mode
= GET_MODE (x
);
8459 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8462 bitwidth
= GET_MODE_BITSIZE (mode
);
8464 /* For a smaller object, just ignore the high bits. */
8465 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8467 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8469 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8472 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8474 #ifndef WORD_REGISTER_OPERATIONS
8475 /* If this machine does not do all register operations on the entire
8476 register and MODE is wider than the mode of X, we can say nothing
8477 at all about the high-order bits. */
8480 /* Likewise on machines that do, if the mode of the object is smaller
8481 than a word and loads of that size don't sign extend, we can say
8482 nothing about the high order bits. */
8483 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8484 #ifdef LOAD_EXTEND_OP
8485 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8496 #ifdef POINTERS_EXTEND_UNSIGNED
8497 /* If pointers extend signed and this is a pointer in Pmode, say that
8498 all the bits above ptr_mode are known to be sign bit copies. */
8499 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8501 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8504 if (reg_last_set_value
[REGNO (x
)] != 0
8505 && reg_last_set_mode
[REGNO (x
)] == mode
8506 && (reg_last_set_label
[REGNO (x
)] == label_tick
8507 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8508 && REG_N_SETS (REGNO (x
)) == 1
8509 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8511 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8512 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8514 tem
= get_last_value (x
);
8516 return num_sign_bit_copies (tem
, mode
);
8518 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8519 return reg_sign_bit_copies
[REGNO (x
)];
8523 #ifdef LOAD_EXTEND_OP
8524 /* Some RISC machines sign-extend all loads of smaller than a word. */
8525 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8526 return MAX (1, ((int) bitwidth
8527 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8532 /* If the constant is negative, take its 1's complement and remask.
8533 Then see how many zero bits we have. */
8534 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8535 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8536 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8537 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8539 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8542 /* If this is a SUBREG for a promoted object that is sign-extended
8543 and we are looking at it in a wider mode, we know that at least the
8544 high-order bits are known to be sign bit copies. */
8546 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8548 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8549 return MAX ((int) bitwidth
8550 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8554 /* For a smaller object, just ignore the high bits. */
8555 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8557 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8558 return MAX (1, (num0
8559 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8563 #ifdef WORD_REGISTER_OPERATIONS
8564 #ifdef LOAD_EXTEND_OP
8565 /* For paradoxical SUBREGs on machines where all register operations
8566 affect the entire register, just look inside. Note that we are
8567 passing MODE to the recursive call, so the number of sign bit copies
8568 will remain relative to that mode, not the inner mode. */
8570 /* This works only if loads sign extend. Otherwise, if we get a
8571 reload for the inner part, it may be loaded from the stack, and
8572 then we lose all sign bit copies that existed before the store
8575 if ((GET_MODE_SIZE (GET_MODE (x
))
8576 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8577 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8578 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8584 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8585 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8589 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8590 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8593 /* For a smaller object, just ignore the high bits. */
8594 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8595 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8599 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8601 case ROTATE
: case ROTATERT
:
8602 /* If we are rotating left by a number of bits less than the number
8603 of sign bit copies, we can just subtract that amount from the
8605 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8606 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8608 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8609 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8610 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8615 /* In general, this subtracts one sign bit copy. But if the value
8616 is known to be positive, the number of sign bit copies is the
8617 same as that of the input. Finally, if the input has just one bit
8618 that might be nonzero, all the bits are copies of the sign bit. */
8619 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8620 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8621 return num0
> 1 ? num0
- 1 : 1;
8623 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8628 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8633 case IOR
: case AND
: case XOR
:
8634 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8635 /* Logical operations will preserve the number of sign-bit copies.
8636 MIN and MAX operations always return one of the operands. */
8637 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8638 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8639 return MIN (num0
, num1
);
8641 case PLUS
: case MINUS
:
8642 /* For addition and subtraction, we can have a 1-bit carry. However,
8643 if we are subtracting 1 from a positive number, there will not
8644 be such a carry. Furthermore, if the positive number is known to
8645 be 0 or 1, we know the result is either -1 or 0. */
8647 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8648 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8650 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8651 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8652 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8653 : bitwidth
- floor_log2 (nonzero
) - 1);
8656 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8657 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8658 result
= MAX (1, MIN (num0
, num1
) - 1);
8660 #ifdef POINTERS_EXTEND_UNSIGNED
8661 /* If pointers extend signed and this is an addition or subtraction
8662 to a pointer in Pmode, all the bits above ptr_mode are known to be
8664 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8665 && (code
== PLUS
|| code
== MINUS
)
8666 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8667 result
= MAX ((GET_MODE_BITSIZE (Pmode
)
8668 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8674 /* The number of bits of the product is the sum of the number of
8675 bits of both terms. However, unless one of the terms if known
8676 to be positive, we must allow for an additional bit since negating
8677 a negative number can remove one sign bit copy. */
8679 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8680 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8682 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8684 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8685 || (((nonzero_bits (XEXP (x
, 0), mode
)
8686 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8687 && ((nonzero_bits (XEXP (x
, 1), mode
)
8688 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8691 return MAX (1, result
);
8694 /* The result must be <= the first operand. If the first operand
8695 has the high bit set, we know nothing about the number of sign
8697 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8699 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8700 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8703 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8706 /* The result must be <= the scond operand. */
8707 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8710 /* Similar to unsigned division, except that we have to worry about
8711 the case where the divisor is negative, in which case we have
8713 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8715 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8716 || (nonzero_bits (XEXP (x
, 1), mode
)
8717 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8723 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8725 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8726 || (nonzero_bits (XEXP (x
, 1), mode
)
8727 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8733 /* Shifts by a constant add to the number of bits equal to the
8735 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8736 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8737 && INTVAL (XEXP (x
, 1)) > 0)
8738 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8743 /* Left shifts destroy copies. */
8744 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8745 || INTVAL (XEXP (x
, 1)) < 0
8746 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8749 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8750 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8753 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8754 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8755 return MIN (num0
, num1
);
8757 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8758 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8759 case GEU
: case GTU
: case LEU
: case LTU
:
8760 case UNORDERED
: case ORDERED
:
8761 /* If the constant is negative, take its 1's complement and remask.
8762 Then see how many zero bits we have. */
8763 nonzero
= STORE_FLAG_VALUE
;
8764 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8765 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8766 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8768 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8775 /* If we haven't been able to figure it out by one of the above rules,
8776 see if some of the high-order bits are known to be zero. If so,
8777 count those bits and return one less than that amount. If we can't
8778 safely compute the mask for this mode, always return BITWIDTH. */
8780 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8783 nonzero
= nonzero_bits (x
, mode
);
8784 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8785 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8788 /* Return the number of "extended" bits there are in X, when interpreted
8789 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8790 unsigned quantities, this is the number of high-order zero bits.
8791 For signed quantities, this is the number of copies of the sign bit
8792 minus 1. In both case, this function returns the number of "spare"
8793 bits. For example, if two quantities for which this function returns
8794 at least 1 are added, the addition is known not to overflow.
8796 This function will always return 0 unless called during combine, which
8797 implies that it must be called from a define_split. */
8800 extended_count (x
, mode
, unsignedp
)
8802 enum machine_mode mode
;
8805 if (nonzero_sign_valid
== 0)
8809 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8810 ? (GET_MODE_BITSIZE (mode
) - 1
8811 - floor_log2 (nonzero_bits (x
, mode
)))
8813 : num_sign_bit_copies (x
, mode
) - 1);
8816 /* This function is called from `simplify_shift_const' to merge two
8817 outer operations. Specifically, we have already found that we need
8818 to perform operation *POP0 with constant *PCONST0 at the outermost
8819 position. We would now like to also perform OP1 with constant CONST1
8820 (with *POP0 being done last).
8822 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8823 the resulting operation. *PCOMP_P is set to 1 if we would need to
8824 complement the innermost operand, otherwise it is unchanged.
8826 MODE is the mode in which the operation will be done. No bits outside
8827 the width of this mode matter. It is assumed that the width of this mode
8828 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8830 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8831 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8832 result is simply *PCONST0.
8834 If the resulting operation cannot be expressed as one operation, we
8835 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8838 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8839 enum rtx_code
*pop0
;
8840 HOST_WIDE_INT
*pconst0
;
8842 HOST_WIDE_INT const1
;
8843 enum machine_mode mode
;
8846 enum rtx_code op0
= *pop0
;
8847 HOST_WIDE_INT const0
= *pconst0
;
8849 const0
&= GET_MODE_MASK (mode
);
8850 const1
&= GET_MODE_MASK (mode
);
8852 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8856 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8859 if (op1
== NIL
|| op0
== SET
)
8862 else if (op0
== NIL
)
8863 op0
= op1
, const0
= const1
;
8865 else if (op0
== op1
)
8889 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8890 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8893 /* If the two constants aren't the same, we can't do anything. The
8894 remaining six cases can all be done. */
8895 else if (const0
!= const1
)
8903 /* (a & b) | b == b */
8905 else /* op1 == XOR */
8906 /* (a ^ b) | b == a | b */
8912 /* (a & b) ^ b == (~a) & b */
8913 op0
= AND
, *pcomp_p
= 1;
8914 else /* op1 == IOR */
8915 /* (a | b) ^ b == a & ~b */
8916 op0
= AND
, *pconst0
= ~const0
;
8921 /* (a | b) & b == b */
8923 else /* op1 == XOR */
8924 /* (a ^ b) & b) == (~a) & b */
8931 /* Check for NO-OP cases. */
8932 const0
&= GET_MODE_MASK (mode
);
8934 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8936 else if (const0
== 0 && op0
== AND
)
8938 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8942 /* ??? Slightly redundant with the above mask, but not entirely.
8943 Moving this above means we'd have to sign-extend the mode mask
8944 for the final test. */
8945 const0
= trunc_int_for_mode (const0
, mode
);
8953 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8954 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8955 that we started with.
8957 The shift is normally computed in the widest mode we find in VAROP, as
8958 long as it isn't a different number of words than RESULT_MODE. Exceptions
8959 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8962 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8965 enum machine_mode result_mode
;
8969 enum rtx_code orig_code
= code
;
8970 int orig_count
= input_count
;
8973 enum machine_mode mode
= result_mode
;
8974 enum machine_mode shift_mode
, tmode
;
8975 unsigned int mode_words
8976 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8977 /* We form (outer_op (code varop count) (outer_const)). */
8978 enum rtx_code outer_op
= NIL
;
8979 HOST_WIDE_INT outer_const
= 0;
8981 int complement_p
= 0;
8984 /* If we were given an invalid count, don't do anything except exactly
8985 what was requested. */
8987 if (input_count
< 0 || input_count
> (int) GET_MODE_BITSIZE (mode
))
8992 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8995 count
= input_count
;
8997 /* Make sure and truncate the "natural" shift on the way in. We don't
8998 want to do this inside the loop as it makes it more difficult to
9000 #ifdef SHIFT_COUNT_TRUNCATED
9001 if (SHIFT_COUNT_TRUNCATED
)
9002 count
%= GET_MODE_BITSIZE (mode
);
9005 /* Unless one of the branches of the `if' in this loop does a `continue',
9006 we will `break' the loop after the `if'. */
9010 /* If we have an operand of (clobber (const_int 0)), just return that
9012 if (GET_CODE (varop
) == CLOBBER
)
9015 /* If we discovered we had to complement VAROP, leave. Making a NOT
9016 here would cause an infinite loop. */
9020 /* Convert ROTATERT to ROTATE. */
9021 if (code
== ROTATERT
)
9022 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
9024 /* We need to determine what mode we will do the shift in. If the
9025 shift is a right shift or a ROTATE, we must always do it in the mode
9026 it was originally done in. Otherwise, we can do it in MODE, the
9027 widest mode encountered. */
9029 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9030 ? result_mode
: mode
);
9032 /* Handle cases where the count is greater than the size of the mode
9033 minus 1. For ASHIFT, use the size minus one as the count (this can
9034 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9035 take the count modulo the size. For other shifts, the result is
9038 Since these shifts are being produced by the compiler by combining
9039 multiple operations, each of which are defined, we know what the
9040 result is supposed to be. */
9042 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
9044 if (code
== ASHIFTRT
)
9045 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9046 else if (code
== ROTATE
|| code
== ROTATERT
)
9047 count
%= GET_MODE_BITSIZE (shift_mode
);
9050 /* We can't simply return zero because there may be an
9058 /* An arithmetic right shift of a quantity known to be -1 or 0
9060 if (code
== ASHIFTRT
9061 && (num_sign_bit_copies (varop
, shift_mode
)
9062 == GET_MODE_BITSIZE (shift_mode
)))
9068 /* If we are doing an arithmetic right shift and discarding all but
9069 the sign bit copies, this is equivalent to doing a shift by the
9070 bitsize minus one. Convert it into that shift because it will often
9071 allow other simplifications. */
9073 if (code
== ASHIFTRT
9074 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9075 >= GET_MODE_BITSIZE (shift_mode
)))
9076 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9078 /* We simplify the tests below and elsewhere by converting
9079 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9080 `make_compound_operation' will convert it to a ASHIFTRT for
9081 those machines (such as Vax) that don't have a LSHIFTRT. */
9082 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9084 && ((nonzero_bits (varop
, shift_mode
)
9085 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9089 switch (GET_CODE (varop
))
9095 new = expand_compound_operation (varop
);
9104 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9105 minus the width of a smaller mode, we can do this with a
9106 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9107 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9108 && ! mode_dependent_address_p (XEXP (varop
, 0))
9109 && ! MEM_VOLATILE_P (varop
)
9110 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9111 MODE_INT
, 1)) != BLKmode
)
9113 if (BYTES_BIG_ENDIAN
)
9114 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
9116 new = gen_rtx_MEM (tmode
,
9117 plus_constant (XEXP (varop
, 0),
9118 count
/ BITS_PER_UNIT
));
9120 MEM_COPY_ATTRIBUTES (new, varop
);
9121 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
9122 : ZERO_EXTEND
, mode
, new);
9129 /* Similar to the case above, except that we can only do this if
9130 the resulting mode is the same as that of the underlying
9131 MEM and adjust the address depending on the *bits* endianness
9132 because of the way that bit-field extract insns are defined. */
9133 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9134 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9135 MODE_INT
, 1)) != BLKmode
9136 && tmode
== GET_MODE (XEXP (varop
, 0)))
9138 if (BITS_BIG_ENDIAN
)
9139 new = XEXP (varop
, 0);
9142 new = copy_rtx (XEXP (varop
, 0));
9143 SUBST (XEXP (new, 0),
9144 plus_constant (XEXP (new, 0),
9145 count
/ BITS_PER_UNIT
));
9148 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
9149 : ZERO_EXTEND
, mode
, new);
9156 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9157 the same number of words as what we've seen so far. Then store
9158 the widest mode in MODE. */
9159 if (subreg_lowpart_p (varop
)
9160 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9161 > GET_MODE_SIZE (GET_MODE (varop
)))
9162 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9163 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9166 varop
= SUBREG_REG (varop
);
9167 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9168 mode
= GET_MODE (varop
);
9174 /* Some machines use MULT instead of ASHIFT because MULT
9175 is cheaper. But it is still better on those machines to
9176 merge two shifts into one. */
9177 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9178 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9181 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9182 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9188 /* Similar, for when divides are cheaper. */
9189 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9190 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9193 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9194 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9200 /* If we are extracting just the sign bit of an arithmetic
9201 right shift, that shift is not needed. However, the sign
9202 bit of a wider mode may be different from what would be
9203 interpreted as the sign bit in a narrower mode, so, if
9204 the result is narrower, don't discard the shift. */
9205 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9206 && (GET_MODE_BITSIZE (result_mode
)
9207 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9209 varop
= XEXP (varop
, 0);
9213 /* ... fall through ... */
9218 /* Here we have two nested shifts. The result is usually the
9219 AND of a new shift with a mask. We compute the result below. */
9220 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9221 && INTVAL (XEXP (varop
, 1)) >= 0
9222 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9223 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9224 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9226 enum rtx_code first_code
= GET_CODE (varop
);
9227 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9228 unsigned HOST_WIDE_INT mask
;
9231 /* We have one common special case. We can't do any merging if
9232 the inner code is an ASHIFTRT of a smaller mode. However, if
9233 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9234 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9235 we can convert it to
9236 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9237 This simplifies certain SIGN_EXTEND operations. */
9238 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9239 && (GET_MODE_BITSIZE (result_mode
)
9240 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9242 /* C3 has the low-order C1 bits zero. */
9244 mask
= (GET_MODE_MASK (mode
)
9245 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9247 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9248 XEXP (varop
, 0), mask
);
9249 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9251 count
= first_count
;
9256 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9257 than C1 high-order bits equal to the sign bit, we can convert
9258 this to either an ASHIFT or a ASHIFTRT depending on the
9261 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9263 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9264 && GET_MODE (varop
) == shift_mode
9265 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9268 varop
= XEXP (varop
, 0);
9270 signed_count
= count
- first_count
;
9271 if (signed_count
< 0)
9272 count
= -signed_count
, code
= ASHIFT
;
9274 count
= signed_count
;
9279 /* There are some cases we can't do. If CODE is ASHIFTRT,
9280 we can only do this if FIRST_CODE is also ASHIFTRT.
9282 We can't do the case when CODE is ROTATE and FIRST_CODE is
9285 If the mode of this shift is not the mode of the outer shift,
9286 we can't do this if either shift is a right shift or ROTATE.
9288 Finally, we can't do any of these if the mode is too wide
9289 unless the codes are the same.
9291 Handle the case where the shift codes are the same
9294 if (code
== first_code
)
9296 if (GET_MODE (varop
) != result_mode
9297 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9301 count
+= first_count
;
9302 varop
= XEXP (varop
, 0);
9306 if (code
== ASHIFTRT
9307 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9308 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9309 || (GET_MODE (varop
) != result_mode
9310 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9311 || first_code
== ROTATE
9312 || code
== ROTATE
)))
9315 /* To compute the mask to apply after the shift, shift the
9316 nonzero bits of the inner shift the same way the
9317 outer shift will. */
9319 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9322 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9325 /* Give up if we can't compute an outer operation to use. */
9327 || GET_CODE (mask_rtx
) != CONST_INT
9328 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9330 result_mode
, &complement_p
))
9333 /* If the shifts are in the same direction, we add the
9334 counts. Otherwise, we subtract them. */
9335 signed_count
= count
;
9336 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9337 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9338 signed_count
+= first_count
;
9340 signed_count
-= first_count
;
9342 /* If COUNT is positive, the new shift is usually CODE,
9343 except for the two exceptions below, in which case it is
9344 FIRST_CODE. If the count is negative, FIRST_CODE should
9346 if (signed_count
> 0
9347 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9348 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9349 code
= first_code
, count
= signed_count
;
9350 else if (signed_count
< 0)
9351 code
= first_code
, count
= -signed_count
;
9353 count
= signed_count
;
9355 varop
= XEXP (varop
, 0);
9359 /* If we have (A << B << C) for any shift, we can convert this to
9360 (A << C << B). This wins if A is a constant. Only try this if
9361 B is not a constant. */
9363 else if (GET_CODE (varop
) == code
9364 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9366 = simplify_binary_operation (code
, mode
,
9370 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
9377 /* Make this fit the case below. */
9378 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
9379 GEN_INT (GET_MODE_MASK (mode
)));
9385 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9386 with C the size of VAROP - 1 and the shift is logical if
9387 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9388 we have an (le X 0) operation. If we have an arithmetic shift
9389 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9390 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9392 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9393 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9394 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9395 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9396 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9397 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9400 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
9403 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9404 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9409 /* If we have (shift (logical)), move the logical to the outside
9410 to allow it to possibly combine with another logical and the
9411 shift to combine with another shift. This also canonicalizes to
9412 what a ZERO_EXTRACT looks like. Also, some machines have
9413 (and (shift)) insns. */
9415 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9416 && (new = simplify_binary_operation (code
, result_mode
,
9418 GEN_INT (count
))) != 0
9419 && GET_CODE (new) == CONST_INT
9420 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9421 INTVAL (new), result_mode
, &complement_p
))
9423 varop
= XEXP (varop
, 0);
9427 /* If we can't do that, try to simplify the shift in each arm of the
9428 logical expression, make a new logical expression, and apply
9429 the inverse distributive law. */
9431 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9432 XEXP (varop
, 0), count
);
9433 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9434 XEXP (varop
, 1), count
);
9436 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9437 varop
= apply_distributive_law (varop
);
9444 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9445 says that the sign bit can be tested, FOO has mode MODE, C is
9446 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9447 that may be nonzero. */
9448 if (code
== LSHIFTRT
9449 && XEXP (varop
, 1) == const0_rtx
9450 && GET_MODE (XEXP (varop
, 0)) == result_mode
9451 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9452 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9453 && ((STORE_FLAG_VALUE
9454 & ((HOST_WIDE_INT
) 1
9455 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9456 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9457 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9458 (HOST_WIDE_INT
) 1, result_mode
,
9461 varop
= XEXP (varop
, 0);
9468 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9469 than the number of bits in the mode is equivalent to A. */
9470 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9471 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9473 varop
= XEXP (varop
, 0);
9478 /* NEG commutes with ASHIFT since it is multiplication. Move the
9479 NEG outside to allow shifts to combine. */
9481 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9482 (HOST_WIDE_INT
) 0, result_mode
,
9485 varop
= XEXP (varop
, 0);
9491 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9492 is one less than the number of bits in the mode is
9493 equivalent to (xor A 1). */
9494 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9495 && XEXP (varop
, 1) == constm1_rtx
9496 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9497 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9498 (HOST_WIDE_INT
) 1, result_mode
,
9502 varop
= XEXP (varop
, 0);
9506 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9507 that might be nonzero in BAR are those being shifted out and those
9508 bits are known zero in FOO, we can replace the PLUS with FOO.
9509 Similarly in the other operand order. This code occurs when
9510 we are computing the size of a variable-size array. */
9512 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9513 && count
< HOST_BITS_PER_WIDE_INT
9514 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9515 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9516 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9518 varop
= XEXP (varop
, 0);
9521 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9522 && count
< HOST_BITS_PER_WIDE_INT
9523 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9524 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9526 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9527 & nonzero_bits (XEXP (varop
, 1),
9530 varop
= XEXP (varop
, 1);
9534 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9536 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9537 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9539 GEN_INT (count
))) != 0
9540 && GET_CODE (new) == CONST_INT
9541 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9542 INTVAL (new), result_mode
, &complement_p
))
9544 varop
= XEXP (varop
, 0);
9550 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9551 with C the size of VAROP - 1 and the shift is logical if
9552 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9553 we have a (gt X 0) operation. If the shift is arithmetic with
9554 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9555 we have a (neg (gt X 0)) operation. */
9557 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9558 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9559 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9560 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9561 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9562 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9563 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9566 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
9569 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9570 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9577 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9578 if the truncate does not affect the value. */
9579 if (code
== LSHIFTRT
9580 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9581 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9582 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9583 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9584 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9586 rtx varop_inner
= XEXP (varop
, 0);
9589 = gen_rtx_combine (LSHIFTRT
, GET_MODE (varop_inner
),
9590 XEXP (varop_inner
, 0),
9592 + INTVAL (XEXP (varop_inner
, 1))));
9593 varop
= gen_rtx_combine (TRUNCATE
, GET_MODE (varop
),
9607 /* We need to determine what mode to do the shift in. If the shift is
9608 a right shift or ROTATE, we must always do it in the mode it was
9609 originally done in. Otherwise, we can do it in MODE, the widest mode
9610 encountered. The code we care about is that of the shift that will
9611 actually be done, not the shift that was originally requested. */
9613 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9614 ? result_mode
: mode
);
9616 /* We have now finished analyzing the shift. The result should be
9617 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9618 OUTER_OP is non-NIL, it is an operation that needs to be applied
9619 to the result of the shift. OUTER_CONST is the relevant constant,
9620 but we must turn off all bits turned off in the shift.
9622 If we were passed a value for X, see if we can use any pieces of
9623 it. If not, make new rtx. */
9625 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9626 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9627 && INTVAL (XEXP (x
, 1)) == count
)
9628 const_rtx
= XEXP (x
, 1);
9630 const_rtx
= GEN_INT (count
);
9632 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9633 && GET_MODE (XEXP (x
, 0)) == shift_mode
9634 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9635 varop
= XEXP (x
, 0);
9636 else if (GET_MODE (varop
) != shift_mode
)
9637 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9639 /* If we can't make the SUBREG, try to return what we were given. */
9640 if (GET_CODE (varop
) == CLOBBER
)
9641 return x
? x
: varop
;
9643 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9648 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9649 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
9651 SUBST (XEXP (x
, 0), varop
);
9652 SUBST (XEXP (x
, 1), const_rtx
);
9655 /* If we have an outer operation and we just made a shift, it is
9656 possible that we could have simplified the shift were it not
9657 for the outer operation. So try to do the simplification
9660 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9661 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9662 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9663 INTVAL (XEXP (x
, 1)));
9665 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9666 turn off all the bits that the shift would have turned off. */
9667 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9668 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9669 GET_MODE_MASK (result_mode
) >> orig_count
);
9671 /* Do the remainder of the processing in RESULT_MODE. */
9672 x
= gen_lowpart_for_combine (result_mode
, x
);
9674 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9677 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
9679 if (outer_op
!= NIL
)
9681 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9682 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9684 if (outer_op
== AND
)
9685 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9686 else if (outer_op
== SET
)
9687 /* This means that we have determined that the result is
9688 equivalent to a constant. This should be rare. */
9689 x
= GEN_INT (outer_const
);
9690 else if (GET_RTX_CLASS (outer_op
) == '1')
9691 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
9693 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9699 /* Like recog, but we receive the address of a pointer to a new pattern.
9700 We try to match the rtx that the pointer points to.
9701 If that fails, we may try to modify or replace the pattern,
9702 storing the replacement into the same pointer object.
9704 Modifications include deletion or addition of CLOBBERs.
9706 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9707 the CLOBBERs are placed.
9709 The value is the final insn code from the pattern ultimately matched,
9713 recog_for_combine (pnewpat
, insn
, pnotes
)
9718 register rtx pat
= *pnewpat
;
9719 int insn_code_number
;
9720 int num_clobbers_to_add
= 0;
9725 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9726 we use to indicate that something didn't match. If we find such a
9727 thing, force rejection. */
9728 if (GET_CODE (pat
) == PARALLEL
)
9729 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9730 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9731 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9734 /* Remove the old notes prior to trying to recognize the new pattern. */
9735 old_notes
= REG_NOTES (insn
);
9736 REG_NOTES (insn
) = 0;
9738 /* Is the result of combination a valid instruction? */
9739 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9741 /* If it isn't, there is the possibility that we previously had an insn
9742 that clobbered some register as a side effect, but the combined
9743 insn doesn't need to do that. So try once more without the clobbers
9744 unless this represents an ASM insn. */
9746 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9747 && GET_CODE (pat
) == PARALLEL
)
9751 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9752 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9755 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9759 SUBST_INT (XVECLEN (pat
, 0), pos
);
9762 pat
= XVECEXP (pat
, 0, 0);
9764 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9767 REG_NOTES (insn
) = old_notes
;
9769 /* If we had any clobbers to add, make a new pattern than contains
9770 them. Then check to make sure that all of them are dead. */
9771 if (num_clobbers_to_add
)
9773 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9774 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9776 + num_clobbers_to_add
)
9777 : num_clobbers_to_add
+ 1));
9779 if (GET_CODE (pat
) == PARALLEL
)
9780 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9781 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9783 XVECEXP (newpat
, 0, 0) = pat
;
9785 add_clobbers (newpat
, insn_code_number
);
9787 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9788 i
< XVECLEN (newpat
, 0); i
++)
9790 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9791 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9793 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9794 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9802 return insn_code_number
;
9805 /* Like gen_lowpart but for use by combine. In combine it is not possible
9806 to create any new pseudoregs. However, it is safe to create
9807 invalid memory addresses, because combine will try to recognize
9808 them and all they will do is make the combine attempt fail.
9810 If for some reason this cannot do its job, an rtx
9811 (clobber (const_int 0)) is returned.
9812 An insn containing that will not be recognized. */
9817 gen_lowpart_for_combine (mode
, x
)
9818 enum machine_mode mode
;
9823 if (GET_MODE (x
) == mode
)
9826 /* We can only support MODE being wider than a word if X is a
9827 constant integer or has a mode the same size. */
9829 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9830 && ! ((GET_MODE (x
) == VOIDmode
9831 && (GET_CODE (x
) == CONST_INT
9832 || GET_CODE (x
) == CONST_DOUBLE
))
9833 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9834 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9836 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9837 won't know what to do. So we will strip off the SUBREG here and
9838 process normally. */
9839 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9842 if (GET_MODE (x
) == mode
)
9846 result
= gen_lowpart_common (mode
, x
);
9847 #ifdef CLASS_CANNOT_CHANGE_MODE
9849 && GET_CODE (result
) == SUBREG
9850 && GET_CODE (SUBREG_REG (result
)) == REG
9851 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9852 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9853 GET_MODE (SUBREG_REG (result
))))
9854 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9860 if (GET_CODE (x
) == MEM
)
9862 register int offset
= 0;
9865 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9867 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9868 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9870 /* If we want to refer to something bigger than the original memref,
9871 generate a perverse subreg instead. That will force a reload
9872 of the original memref X. */
9873 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9874 return gen_rtx_SUBREG (mode
, x
, 0);
9876 if (WORDS_BIG_ENDIAN
)
9877 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9878 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9880 if (BYTES_BIG_ENDIAN
)
9882 /* Adjust the address so that the address-after-the-data is
9884 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9885 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9887 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9888 MEM_COPY_ATTRIBUTES (new, x
);
9892 /* If X is a comparison operator, rewrite it in a new mode. This
9893 probably won't match, but may allow further simplifications. */
9894 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9895 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9897 /* If we couldn't simplify X any other way, just enclose it in a
9898 SUBREG. Normally, this SUBREG won't match, but some patterns may
9899 include an explicit SUBREG or we may simplify it further in combine. */
9904 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
9905 word
= ((GET_MODE_SIZE (GET_MODE (x
))
9906 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
9908 return gen_rtx_SUBREG (mode
, x
, word
);
9912 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9913 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9915 If the identical expression was previously in the insn (in the undobuf),
9916 it will be returned. Only if it is not found will a new expression
9921 gen_rtx_combine
VPARAMS ((enum rtx_code code
, enum machine_mode mode
, ...))
9923 #ifndef ANSI_PROTOTYPES
9925 enum machine_mode mode
;
9937 #ifndef ANSI_PROTOTYPES
9938 code
= va_arg (p
, enum rtx_code
);
9939 mode
= va_arg (p
, enum machine_mode
);
9942 n_args
= GET_RTX_LENGTH (code
);
9943 fmt
= GET_RTX_FORMAT (code
);
9945 if (n_args
== 0 || n_args
> 3)
9948 /* Get each arg and verify that it is supposed to be an expression. */
9949 for (j
= 0; j
< n_args
; j
++)
9954 args
[j
] = va_arg (p
, rtx
);
9959 /* See if this is in undobuf. Be sure we don't use objects that came
9960 from another insn; this could produce circular rtl structures. */
9962 for (undo
= undobuf
.undos
; undo
!= undobuf
.previous_undos
; undo
= undo
->next
)
9964 && GET_CODE (undo
->old_contents
.r
) == code
9965 && GET_MODE (undo
->old_contents
.r
) == mode
)
9967 for (j
= 0; j
< n_args
; j
++)
9968 if (XEXP (undo
->old_contents
.r
, j
) != args
[j
])
9972 return undo
->old_contents
.r
;
9975 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9976 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9977 rt
= rtx_alloc (code
);
9978 PUT_MODE (rt
, mode
);
9979 XEXP (rt
, 0) = args
[0];
9982 XEXP (rt
, 1) = args
[1];
9984 XEXP (rt
, 2) = args
[2];
9989 /* These routines make binary and unary operations by first seeing if they
9990 fold; if not, a new expression is allocated. */
9993 gen_binary (code
, mode
, op0
, op1
)
9995 enum machine_mode mode
;
10001 if (GET_RTX_CLASS (code
) == 'c'
10002 && (GET_CODE (op0
) == CONST_INT
10003 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
10004 tem
= op0
, op0
= op1
, op1
= tem
;
10006 if (GET_RTX_CLASS (code
) == '<')
10008 enum machine_mode op_mode
= GET_MODE (op0
);
10010 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10011 just (REL_OP X Y). */
10012 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10014 op1
= XEXP (op0
, 1);
10015 op0
= XEXP (op0
, 0);
10016 op_mode
= GET_MODE (op0
);
10019 if (op_mode
== VOIDmode
)
10020 op_mode
= GET_MODE (op1
);
10021 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10024 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10029 /* Put complex operands first and constants second. */
10030 if (GET_RTX_CLASS (code
) == 'c'
10031 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
10032 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
10033 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
10034 || (GET_CODE (op0
) == SUBREG
10035 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
10036 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
10037 return gen_rtx_combine (code
, mode
, op1
, op0
);
10039 /* If we are turning off bits already known off in OP0, we need not do
10041 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10042 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10043 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10046 return gen_rtx_combine (code
, mode
, op0
, op1
);
10050 gen_unary (code
, mode
, op0_mode
, op0
)
10051 enum rtx_code code
;
10052 enum machine_mode mode
, op0_mode
;
10055 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
10060 return gen_rtx_combine (code
, mode
, op0
);
10063 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10064 comparison code that will be tested.
10066 The result is a possibly different comparison code to use. *POP0 and
10067 *POP1 may be updated.
10069 It is possible that we might detect that a comparison is either always
10070 true or always false. However, we do not perform general constant
10071 folding in combine, so this knowledge isn't useful. Such tautologies
10072 should have been detected earlier. Hence we ignore all such cases. */
10074 static enum rtx_code
10075 simplify_comparison (code
, pop0
, pop1
)
10076 enum rtx_code code
;
10084 enum machine_mode mode
, tmode
;
10086 /* Try a few ways of applying the same transformation to both operands. */
10089 #ifndef WORD_REGISTER_OPERATIONS
10090 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10091 so check specially. */
10092 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10093 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10094 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10095 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10096 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10097 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10098 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10099 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10100 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10101 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
10102 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10103 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
10104 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
10105 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
10106 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
10107 && (INTVAL (XEXP (op0
, 1))
10108 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10109 - (GET_MODE_BITSIZE
10110 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10112 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10113 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10117 /* If both operands are the same constant shift, see if we can ignore the
10118 shift. We can if the shift is a rotate or if the bits shifted out of
10119 this shift are known to be zero for both inputs and if the type of
10120 comparison is compatible with the shift. */
10121 if (GET_CODE (op0
) == GET_CODE (op1
)
10122 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10123 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10124 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10125 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10126 || (GET_CODE (op0
) == ASHIFTRT
10127 && (code
!= GTU
&& code
!= LTU
10128 && code
!= GEU
&& code
!= GEU
)))
10129 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10130 && INTVAL (XEXP (op0
, 1)) >= 0
10131 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10132 && XEXP (op0
, 1) == XEXP (op1
, 1))
10134 enum machine_mode mode
= GET_MODE (op0
);
10135 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10136 int shift_count
= INTVAL (XEXP (op0
, 1));
10138 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10139 mask
&= (mask
>> shift_count
) << shift_count
;
10140 else if (GET_CODE (op0
) == ASHIFT
)
10141 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10143 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10144 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10145 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10150 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10151 SUBREGs are of the same mode, and, in both cases, the AND would
10152 be redundant if the comparison was done in the narrower mode,
10153 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10154 and the operand's possibly nonzero bits are 0xffffff01; in that case
10155 if we only care about QImode, we don't need the AND). This case
10156 occurs if the output mode of an scc insn is not SImode and
10157 STORE_FLAG_VALUE == 1 (e.g., the 386).
10159 Similarly, check for a case where the AND's are ZERO_EXTEND
10160 operations from some narrower mode even though a SUBREG is not
10163 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10164 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10165 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10167 rtx inner_op0
= XEXP (op0
, 0);
10168 rtx inner_op1
= XEXP (op1
, 0);
10169 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10170 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10173 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10174 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10175 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10176 && (GET_MODE (SUBREG_REG (inner_op0
))
10177 == GET_MODE (SUBREG_REG (inner_op1
)))
10178 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10179 <= HOST_BITS_PER_WIDE_INT
)
10180 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10181 GET_MODE (SUBREG_REG (inner_op0
)))))
10182 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10183 GET_MODE (SUBREG_REG (inner_op1
))))))
10185 op0
= SUBREG_REG (inner_op0
);
10186 op1
= SUBREG_REG (inner_op1
);
10188 /* The resulting comparison is always unsigned since we masked
10189 off the original sign bit. */
10190 code
= unsigned_condition (code
);
10196 for (tmode
= GET_CLASS_NARROWEST_MODE
10197 (GET_MODE_CLASS (GET_MODE (op0
)));
10198 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10199 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10201 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10202 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10203 code
= unsigned_condition (code
);
10212 /* If both operands are NOT, we can strip off the outer operation
10213 and adjust the comparison code for swapped operands; similarly for
10214 NEG, except that this must be an equality comparison. */
10215 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10216 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10217 && (code
== EQ
|| code
== NE
)))
10218 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10224 /* If the first operand is a constant, swap the operands and adjust the
10225 comparison code appropriately, but don't do this if the second operand
10226 is already a constant integer. */
10227 if (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
10229 tem
= op0
, op0
= op1
, op1
= tem
;
10230 code
= swap_condition (code
);
10233 /* We now enter a loop during which we will try to simplify the comparison.
10234 For the most part, we only are concerned with comparisons with zero,
10235 but some things may really be comparisons with zero but not start
10236 out looking that way. */
10238 while (GET_CODE (op1
) == CONST_INT
)
10240 enum machine_mode mode
= GET_MODE (op0
);
10241 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10242 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10243 int equality_comparison_p
;
10244 int sign_bit_comparison_p
;
10245 int unsigned_comparison_p
;
10246 HOST_WIDE_INT const_op
;
10248 /* We only want to handle integral modes. This catches VOIDmode,
10249 CCmode, and the floating-point modes. An exception is that we
10250 can handle VOIDmode if OP0 is a COMPARE or a comparison
10253 if (GET_MODE_CLASS (mode
) != MODE_INT
10254 && ! (mode
== VOIDmode
10255 && (GET_CODE (op0
) == COMPARE
10256 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10259 /* Get the constant we are comparing against and turn off all bits
10260 not on in our mode. */
10261 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10263 /* If we are comparing against a constant power of two and the value
10264 being compared can only have that single bit nonzero (e.g., it was
10265 `and'ed with that bit), we can replace this with a comparison
10268 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10269 || code
== LT
|| code
== LTU
)
10270 && mode_width
<= HOST_BITS_PER_WIDE_INT
10271 && exact_log2 (const_op
) >= 0
10272 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10274 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10275 op1
= const0_rtx
, const_op
= 0;
10278 /* Similarly, if we are comparing a value known to be either -1 or
10279 0 with -1, change it to the opposite comparison against zero. */
10282 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10283 || code
== GEU
|| code
== LTU
)
10284 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10286 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10287 op1
= const0_rtx
, const_op
= 0;
10290 /* Do some canonicalizations based on the comparison code. We prefer
10291 comparisons against zero and then prefer equality comparisons.
10292 If we can reduce the size of a constant, we will do that too. */
10297 /* < C is equivalent to <= (C - 1) */
10301 op1
= GEN_INT (const_op
);
10303 /* ... fall through to LE case below. */
10309 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10313 op1
= GEN_INT (const_op
);
10317 /* If we are doing a <= 0 comparison on a value known to have
10318 a zero sign bit, we can replace this with == 0. */
10319 else if (const_op
== 0
10320 && mode_width
<= HOST_BITS_PER_WIDE_INT
10321 && (nonzero_bits (op0
, mode
)
10322 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10327 /* >= C is equivalent to > (C - 1). */
10331 op1
= GEN_INT (const_op
);
10333 /* ... fall through to GT below. */
10339 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10343 op1
= GEN_INT (const_op
);
10347 /* If we are doing a > 0 comparison on a value known to have
10348 a zero sign bit, we can replace this with != 0. */
10349 else if (const_op
== 0
10350 && mode_width
<= HOST_BITS_PER_WIDE_INT
10351 && (nonzero_bits (op0
, mode
)
10352 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10357 /* < C is equivalent to <= (C - 1). */
10361 op1
= GEN_INT (const_op
);
10363 /* ... fall through ... */
10366 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10367 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10368 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10370 const_op
= 0, op1
= const0_rtx
;
10378 /* unsigned <= 0 is equivalent to == 0 */
10382 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10383 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10384 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10386 const_op
= 0, op1
= const0_rtx
;
10392 /* >= C is equivalent to < (C - 1). */
10396 op1
= GEN_INT (const_op
);
10398 /* ... fall through ... */
10401 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10402 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10403 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10405 const_op
= 0, op1
= const0_rtx
;
10413 /* unsigned > 0 is equivalent to != 0 */
10417 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10418 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10419 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10421 const_op
= 0, op1
= const0_rtx
;
10430 /* Compute some predicates to simplify code below. */
10432 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10433 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10434 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10437 /* If this is a sign bit comparison and we can do arithmetic in
10438 MODE, say that we will only be needing the sign bit of OP0. */
10439 if (sign_bit_comparison_p
10440 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10441 op0
= force_to_mode (op0
, mode
,
10443 << (GET_MODE_BITSIZE (mode
) - 1)),
10446 /* Now try cases based on the opcode of OP0. If none of the cases
10447 does a "continue", we exit this loop immediately after the
10450 switch (GET_CODE (op0
))
10453 /* If we are extracting a single bit from a variable position in
10454 a constant that has only a single bit set and are comparing it
10455 with zero, we can convert this into an equality comparison
10456 between the position and the location of the single bit. */
10458 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10459 && XEXP (op0
, 1) == const1_rtx
10460 && equality_comparison_p
&& const_op
== 0
10461 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10463 if (BITS_BIG_ENDIAN
)
10466 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10467 if (mode
== VOIDmode
)
10469 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10471 i
= BITS_PER_WORD
- 1 - i
;
10475 op0
= XEXP (op0
, 2);
10479 /* Result is nonzero iff shift count is equal to I. */
10480 code
= reverse_condition (code
);
10484 /* ... fall through ... */
10487 tem
= expand_compound_operation (op0
);
10496 /* If testing for equality, we can take the NOT of the constant. */
10497 if (equality_comparison_p
10498 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10500 op0
= XEXP (op0
, 0);
10505 /* If just looking at the sign bit, reverse the sense of the
10507 if (sign_bit_comparison_p
)
10509 op0
= XEXP (op0
, 0);
10510 code
= (code
== GE
? LT
: GE
);
10516 /* If testing for equality, we can take the NEG of the constant. */
10517 if (equality_comparison_p
10518 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10520 op0
= XEXP (op0
, 0);
10525 /* The remaining cases only apply to comparisons with zero. */
10529 /* When X is ABS or is known positive,
10530 (neg X) is < 0 if and only if X != 0. */
10532 if (sign_bit_comparison_p
10533 && (GET_CODE (XEXP (op0
, 0)) == ABS
10534 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10535 && (nonzero_bits (XEXP (op0
, 0), mode
)
10536 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10538 op0
= XEXP (op0
, 0);
10539 code
= (code
== LT
? NE
: EQ
);
10543 /* If we have NEG of something whose two high-order bits are the
10544 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10545 if (num_sign_bit_copies (op0
, mode
) >= 2)
10547 op0
= XEXP (op0
, 0);
10548 code
= swap_condition (code
);
10554 /* If we are testing equality and our count is a constant, we
10555 can perform the inverse operation on our RHS. */
10556 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10557 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10558 op1
, XEXP (op0
, 1))) != 0)
10560 op0
= XEXP (op0
, 0);
10565 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10566 a particular bit. Convert it to an AND of a constant of that
10567 bit. This will be converted into a ZERO_EXTRACT. */
10568 if (const_op
== 0 && sign_bit_comparison_p
10569 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10570 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10572 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10575 - INTVAL (XEXP (op0
, 1)))));
10576 code
= (code
== LT
? NE
: EQ
);
10580 /* Fall through. */
10583 /* ABS is ignorable inside an equality comparison with zero. */
10584 if (const_op
== 0 && equality_comparison_p
)
10586 op0
= XEXP (op0
, 0);
10592 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10593 to (compare FOO CONST) if CONST fits in FOO's mode and we
10594 are either testing inequality or have an unsigned comparison
10595 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10596 if (! unsigned_comparison_p
10597 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10598 <= HOST_BITS_PER_WIDE_INT
)
10599 && ((unsigned HOST_WIDE_INT
) const_op
10600 < (((unsigned HOST_WIDE_INT
) 1
10601 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10603 op0
= XEXP (op0
, 0);
10609 /* Check for the case where we are comparing A - C1 with C2,
10610 both constants are smaller than 1/2 the maximum positive
10611 value in MODE, and the comparison is equality or unsigned.
10612 In that case, if A is either zero-extended to MODE or has
10613 sufficient sign bits so that the high-order bit in MODE
10614 is a copy of the sign in the inner mode, we can prove that it is
10615 safe to do the operation in the wider mode. This simplifies
10616 many range checks. */
10618 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10619 && subreg_lowpart_p (op0
)
10620 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10621 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10622 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10623 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10624 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10625 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10626 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10627 GET_MODE (SUBREG_REG (op0
)))
10628 & ~GET_MODE_MASK (mode
))
10629 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10630 GET_MODE (SUBREG_REG (op0
)))
10631 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10632 - GET_MODE_BITSIZE (mode
)))))
10634 op0
= SUBREG_REG (op0
);
10638 /* If the inner mode is narrower and we are extracting the low part,
10639 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10640 if (subreg_lowpart_p (op0
)
10641 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10642 /* Fall through */ ;
10646 /* ... fall through ... */
10649 if ((unsigned_comparison_p
|| equality_comparison_p
)
10650 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10651 <= HOST_BITS_PER_WIDE_INT
)
10652 && ((unsigned HOST_WIDE_INT
) const_op
10653 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10655 op0
= XEXP (op0
, 0);
10661 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10662 this for equality comparisons due to pathological cases involving
10664 if (equality_comparison_p
10665 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10666 op1
, XEXP (op0
, 1))))
10668 op0
= XEXP (op0
, 0);
10673 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10674 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10675 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10677 op0
= XEXP (XEXP (op0
, 0), 0);
10678 code
= (code
== LT
? EQ
: NE
);
10684 /* We used to optimize signed comparisons against zero, but that
10685 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10686 arrive here as equality comparisons, or (GEU, LTU) are
10687 optimized away. No need to special-case them. */
10689 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10690 (eq B (minus A C)), whichever simplifies. We can only do
10691 this for equality comparisons due to pathological cases involving
10693 if (equality_comparison_p
10694 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10695 XEXP (op0
, 1), op1
)))
10697 op0
= XEXP (op0
, 0);
10702 if (equality_comparison_p
10703 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10704 XEXP (op0
, 0), op1
)))
10706 op0
= XEXP (op0
, 1);
10711 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10712 of bits in X minus 1, is one iff X > 0. */
10713 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10714 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10715 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10716 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10718 op0
= XEXP (op0
, 1);
10719 code
= (code
== GE
? LE
: GT
);
10725 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10726 if C is zero or B is a constant. */
10727 if (equality_comparison_p
10728 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10729 XEXP (op0
, 1), op1
)))
10731 op0
= XEXP (op0
, 0);
10738 case UNEQ
: case LTGT
:
10739 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10740 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10741 case UNORDERED
: case ORDERED
:
10742 /* We can't do anything if OP0 is a condition code value, rather
10743 than an actual data value. */
10746 || XEXP (op0
, 0) == cc0_rtx
10748 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10751 /* Get the two operands being compared. */
10752 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10753 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10755 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10757 /* Check for the cases where we simply want the result of the
10758 earlier test or the opposite of that result. */
10759 if (code
== NE
|| code
== EQ
10760 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10761 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10762 && (STORE_FLAG_VALUE
10763 & (((HOST_WIDE_INT
) 1
10764 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10765 && (code
== LT
|| code
== GE
)))
10767 enum rtx_code new_code
;
10768 if (code
== LT
|| code
== NE
)
10769 new_code
= GET_CODE (op0
);
10771 new_code
= combine_reversed_comparison_code (op0
);
10773 if (new_code
!= UNKNOWN
)
10784 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10786 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10787 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10788 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10790 op0
= XEXP (op0
, 1);
10791 code
= (code
== GE
? GT
: LE
);
10797 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10798 will be converted to a ZERO_EXTRACT later. */
10799 if (const_op
== 0 && equality_comparison_p
10800 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10801 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10803 op0
= simplify_and_const_int
10804 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10806 XEXP (XEXP (op0
, 0), 1)),
10807 (HOST_WIDE_INT
) 1);
10811 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10812 zero and X is a comparison and C1 and C2 describe only bits set
10813 in STORE_FLAG_VALUE, we can compare with X. */
10814 if (const_op
== 0 && equality_comparison_p
10815 && mode_width
<= HOST_BITS_PER_WIDE_INT
10816 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10817 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10818 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10819 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10820 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10822 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10823 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10824 if ((~STORE_FLAG_VALUE
& mask
) == 0
10825 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10826 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10827 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10829 op0
= XEXP (XEXP (op0
, 0), 0);
10834 /* If we are doing an equality comparison of an AND of a bit equal
10835 to the sign bit, replace this with a LT or GE comparison of
10836 the underlying value. */
10837 if (equality_comparison_p
10839 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10840 && mode_width
<= HOST_BITS_PER_WIDE_INT
10841 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10842 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10844 op0
= XEXP (op0
, 0);
10845 code
= (code
== EQ
? GE
: LT
);
10849 /* If this AND operation is really a ZERO_EXTEND from a narrower
10850 mode, the constant fits within that mode, and this is either an
10851 equality or unsigned comparison, try to do this comparison in
10852 the narrower mode. */
10853 if ((equality_comparison_p
|| unsigned_comparison_p
)
10854 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10855 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10856 & GET_MODE_MASK (mode
))
10858 && const_op
>> i
== 0
10859 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10861 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10865 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10866 in both M1 and M2 and the SUBREG is either paradoxical or
10867 represents the low part, permute the SUBREG and the AND and
10869 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10871 #ifdef WORD_REGISTER_OPERATIONS
10873 > (GET_MODE_BITSIZE
10874 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10875 && mode_width
<= BITS_PER_WORD
)
10878 <= (GET_MODE_BITSIZE
10879 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10880 && subreg_lowpart_p (XEXP (op0
, 0))))
10881 #ifndef WORD_REGISTER_OPERATIONS
10882 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10883 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10884 As originally written the upper bits have a defined value
10885 due to the AND operation. However, if we commute the AND
10886 inside the SUBREG then they no longer have defined values
10887 and the meaning of the code has been changed. */
10888 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10889 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10891 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10892 && mode_width
<= HOST_BITS_PER_WIDE_INT
10893 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10894 <= HOST_BITS_PER_WIDE_INT
)
10895 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10896 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10897 & INTVAL (XEXP (op0
, 1)))
10898 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10899 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10900 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10904 = gen_lowpart_for_combine
10906 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10907 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10911 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10912 (eq (and (lshiftrt X) 1) 0). */
10913 if (const_op
== 0 && equality_comparison_p
10914 && XEXP (op0
, 1) == const1_rtx
10915 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10916 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10918 op0
= simplify_and_const_int
10919 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10920 XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10921 XEXP (XEXP (op0
, 0), 1)),
10922 (HOST_WIDE_INT
) 1);
10923 code
= (code
== NE
? EQ
: NE
);
10929 /* If we have (compare (ashift FOO N) (const_int C)) and
10930 the high order N bits of FOO (N+1 if an inequality comparison)
10931 are known to be zero, we can do this by comparing FOO with C
10932 shifted right N bits so long as the low-order N bits of C are
10934 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10935 && INTVAL (XEXP (op0
, 1)) >= 0
10936 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10937 < HOST_BITS_PER_WIDE_INT
)
10939 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10940 && mode_width
<= HOST_BITS_PER_WIDE_INT
10941 && (nonzero_bits (XEXP (op0
, 0), mode
)
10942 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10943 + ! equality_comparison_p
))) == 0)
10945 /* We must perform a logical shift, not an arithmetic one,
10946 as we want the top N bits of C to be zero. */
10947 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10949 temp
>>= INTVAL (XEXP (op0
, 1));
10950 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10951 op0
= XEXP (op0
, 0);
10955 /* If we are doing a sign bit comparison, it means we are testing
10956 a particular bit. Convert it to the appropriate AND. */
10957 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10958 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10960 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10963 - INTVAL (XEXP (op0
, 1)))));
10964 code
= (code
== LT
? NE
: EQ
);
10968 /* If this an equality comparison with zero and we are shifting
10969 the low bit to the sign bit, we can convert this to an AND of the
10971 if (const_op
== 0 && equality_comparison_p
10972 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10973 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10975 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10976 (HOST_WIDE_INT
) 1);
10982 /* If this is an equality comparison with zero, we can do this
10983 as a logical shift, which might be much simpler. */
10984 if (equality_comparison_p
&& const_op
== 0
10985 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10987 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10989 INTVAL (XEXP (op0
, 1)));
10993 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10994 do the comparison in a narrower mode. */
10995 if (! unsigned_comparison_p
10996 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10997 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10998 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10999 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11000 MODE_INT
, 1)) != BLKmode
11001 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
11002 || ((unsigned HOST_WIDE_INT
) -const_op
11003 <= GET_MODE_MASK (tmode
))))
11005 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11009 /* Likewise if OP0 is a PLUS of a sign extension with a
11010 constant, which is usually represented with the PLUS
11011 between the shifts. */
11012 if (! unsigned_comparison_p
11013 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11014 && GET_CODE (XEXP (op0
, 0)) == PLUS
11015 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11016 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11017 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11018 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11019 MODE_INT
, 1)) != BLKmode
11020 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
11021 || ((unsigned HOST_WIDE_INT
) -const_op
11022 <= GET_MODE_MASK (tmode
))))
11024 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11025 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11026 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11029 op0
= gen_binary (PLUS
, tmode
,
11030 gen_lowpart_for_combine (tmode
, inner
),
11035 /* ... fall through ... */
11037 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11038 the low order N bits of FOO are known to be zero, we can do this
11039 by comparing FOO with C shifted left N bits so long as no
11040 overflow occurs. */
11041 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11042 && INTVAL (XEXP (op0
, 1)) >= 0
11043 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11044 && mode_width
<= HOST_BITS_PER_WIDE_INT
11045 && (nonzero_bits (XEXP (op0
, 0), mode
)
11046 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11048 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
11051 const_op
<<= INTVAL (XEXP (op0
, 1));
11052 op1
= GEN_INT (const_op
);
11053 op0
= XEXP (op0
, 0);
11057 /* If we are using this shift to extract just the sign bit, we
11058 can replace this with an LT or GE comparison. */
11060 && (equality_comparison_p
|| sign_bit_comparison_p
)
11061 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11062 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11064 op0
= XEXP (op0
, 0);
11065 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11077 /* Now make any compound operations involved in this comparison. Then,
11078 check for an outmost SUBREG on OP0 that is not doing anything or is
11079 paradoxical. The latter case can only occur when it is known that the
11080 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
11081 We can never remove a SUBREG for a non-equality comparison because the
11082 sign bit is in a different place in the underlying object. */
11084 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11085 op1
= make_compound_operation (op1
, SET
);
11087 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11088 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11089 && (code
== NE
|| code
== EQ
)
11090 && ((GET_MODE_SIZE (GET_MODE (op0
))
11091 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
11093 op0
= SUBREG_REG (op0
);
11094 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11097 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11098 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11099 && (code
== NE
|| code
== EQ
)
11100 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11101 <= HOST_BITS_PER_WIDE_INT
)
11102 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
11103 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
11104 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
11106 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11107 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
11108 op0
= SUBREG_REG (op0
), op1
= tem
;
11110 /* We now do the opposite procedure: Some machines don't have compare
11111 insns in all modes. If OP0's mode is an integer mode smaller than a
11112 word and we can't do a compare in that mode, see if there is a larger
11113 mode for which we can do the compare. There are a number of cases in
11114 which we can use the wider mode. */
11116 mode
= GET_MODE (op0
);
11117 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11118 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11119 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
11120 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11122 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11123 tmode
= GET_MODE_WIDER_MODE (tmode
))
11124 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
11126 /* If the only nonzero bits in OP0 and OP1 are those in the
11127 narrower mode and this is an equality or unsigned comparison,
11128 we can use the wider mode. Similarly for sign-extended
11129 values, in which case it is true for all comparisons. */
11130 if (((code
== EQ
|| code
== NE
11131 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
11132 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
11133 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
11134 || ((num_sign_bit_copies (op0
, tmode
)
11135 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
11136 && (num_sign_bit_copies (op1
, tmode
)
11137 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
11139 /* If OP0 is an AND and we don't have an AND in MODE either,
11140 make a new AND in the proper mode. */
11141 if (GET_CODE (op0
) == AND
11142 && (add_optab
->handlers
[(int) mode
].insn_code
11143 == CODE_FOR_nothing
))
11144 op0
= gen_binary (AND
, tmode
,
11145 gen_lowpart_for_combine (tmode
,
11147 gen_lowpart_for_combine (tmode
,
11150 op0
= gen_lowpart_for_combine (tmode
, op0
);
11151 op1
= gen_lowpart_for_combine (tmode
, op1
);
11155 /* If this is a test for negative, we can make an explicit
11156 test of the sign bit. */
11158 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11159 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11161 op0
= gen_binary (AND
, tmode
,
11162 gen_lowpart_for_combine (tmode
, op0
),
11163 GEN_INT ((HOST_WIDE_INT
) 1
11164 << (GET_MODE_BITSIZE (mode
) - 1)));
11165 code
= (code
== LT
) ? NE
: EQ
;
11170 #ifdef CANONICALIZE_COMPARISON
11171 /* If this machine only supports a subset of valid comparisons, see if we
11172 can convert an unsupported one into a supported one. */
11173 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11182 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11183 searching backward. */
11184 static enum rtx_code
11185 combine_reversed_comparison_code (exp
)
11188 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11191 if (code1
!= UNKNOWN
11192 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11194 /* Otherwise try and find where the condition codes were last set and
11196 x
= get_last_value (XEXP (exp
, 0));
11197 if (!x
|| GET_CODE (x
) != COMPARE
)
11199 return reversed_comparison_code_parts (GET_CODE (exp
),
11200 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11202 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11203 Return NULL_RTX in case we fail to do the reversal. */
11205 reversed_comparison (exp
, mode
, op0
, op1
)
11207 enum machine_mode mode
;
11209 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11210 if (reversed_code
== UNKNOWN
)
11213 return gen_binary (reversed_code
, mode
, op0
, op1
);
11216 /* Utility function for following routine. Called when X is part of a value
11217 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11218 for each register mentioned. Similar to mention_regs in cse.c */
11221 update_table_tick (x
)
11224 register enum rtx_code code
= GET_CODE (x
);
11225 register const char *fmt
= GET_RTX_FORMAT (code
);
11230 unsigned int regno
= REGNO (x
);
11231 unsigned int endregno
11232 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11233 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11236 for (r
= regno
; r
< endregno
; r
++)
11237 reg_last_set_table_tick
[r
] = label_tick
;
11242 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11243 /* Note that we can't have an "E" in values stored; see
11244 get_last_value_validate. */
11246 update_table_tick (XEXP (x
, i
));
11249 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11250 are saying that the register is clobbered and we no longer know its
11251 value. If INSN is zero, don't update reg_last_set; this is only permitted
11252 with VALUE also zero and is used to invalidate the register. */
11255 record_value_for_reg (reg
, insn
, value
)
11260 unsigned int regno
= REGNO (reg
);
11261 unsigned int endregno
11262 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11263 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11266 /* If VALUE contains REG and we have a previous value for REG, substitute
11267 the previous value. */
11268 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11272 /* Set things up so get_last_value is allowed to see anything set up to
11274 subst_low_cuid
= INSN_CUID (insn
);
11275 tem
= get_last_value (reg
);
11277 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11278 it isn't going to be useful and will take a lot of time to process,
11279 so just use the CLOBBER. */
11283 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11284 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11285 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11286 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11287 tem
= XEXP (tem
, 0);
11289 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11293 /* For each register modified, show we don't know its value, that
11294 we don't know about its bitwise content, that its value has been
11295 updated, and that we don't know the location of the death of the
11297 for (i
= regno
; i
< endregno
; i
++)
11300 reg_last_set
[i
] = insn
;
11302 reg_last_set_value
[i
] = 0;
11303 reg_last_set_mode
[i
] = 0;
11304 reg_last_set_nonzero_bits
[i
] = 0;
11305 reg_last_set_sign_bit_copies
[i
] = 0;
11306 reg_last_death
[i
] = 0;
11309 /* Mark registers that are being referenced in this value. */
11311 update_table_tick (value
);
11313 /* Now update the status of each register being set.
11314 If someone is using this register in this block, set this register
11315 to invalid since we will get confused between the two lives in this
11316 basic block. This makes using this register always invalid. In cse, we
11317 scan the table to invalidate all entries using this register, but this
11318 is too much work for us. */
11320 for (i
= regno
; i
< endregno
; i
++)
11322 reg_last_set_label
[i
] = label_tick
;
11323 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11324 reg_last_set_invalid
[i
] = 1;
11326 reg_last_set_invalid
[i
] = 0;
11329 /* The value being assigned might refer to X (like in "x++;"). In that
11330 case, we must replace it with (clobber (const_int 0)) to prevent
11332 if (value
&& ! get_last_value_validate (&value
, insn
,
11333 reg_last_set_label
[regno
], 0))
11335 value
= copy_rtx (value
);
11336 if (! get_last_value_validate (&value
, insn
,
11337 reg_last_set_label
[regno
], 1))
11341 /* For the main register being modified, update the value, the mode, the
11342 nonzero bits, and the number of sign bit copies. */
11344 reg_last_set_value
[regno
] = value
;
11348 subst_low_cuid
= INSN_CUID (insn
);
11349 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11350 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11351 reg_last_set_sign_bit_copies
[regno
]
11352 = num_sign_bit_copies (value
, GET_MODE (reg
));
11356 /* Called via note_stores from record_dead_and_set_regs to handle one
11357 SET or CLOBBER in an insn. DATA is the instruction in which the
11358 set is occurring. */
11361 record_dead_and_set_regs_1 (dest
, setter
, data
)
11365 rtx record_dead_insn
= (rtx
) data
;
11367 if (GET_CODE (dest
) == SUBREG
)
11368 dest
= SUBREG_REG (dest
);
11370 if (GET_CODE (dest
) == REG
)
11372 /* If we are setting the whole register, we know its value. Otherwise
11373 show that we don't know the value. We can handle SUBREG in
11375 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11376 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11377 else if (GET_CODE (setter
) == SET
11378 && GET_CODE (SET_DEST (setter
)) == SUBREG
11379 && SUBREG_REG (SET_DEST (setter
)) == dest
11380 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11381 && subreg_lowpart_p (SET_DEST (setter
)))
11382 record_value_for_reg (dest
, record_dead_insn
,
11383 gen_lowpart_for_combine (GET_MODE (dest
),
11384 SET_SRC (setter
)));
11386 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11388 else if (GET_CODE (dest
) == MEM
11389 /* Ignore pushes, they clobber nothing. */
11390 && ! push_operand (dest
, GET_MODE (dest
)))
11391 mem_last_set
= INSN_CUID (record_dead_insn
);
11394 /* Update the records of when each REG was most recently set or killed
11395 for the things done by INSN. This is the last thing done in processing
11396 INSN in the combiner loop.
11398 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11399 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11400 and also the similar information mem_last_set (which insn most recently
11401 modified memory) and last_call_cuid (which insn was the most recent
11402 subroutine call). */
11405 record_dead_and_set_regs (insn
)
11411 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11413 if (REG_NOTE_KIND (link
) == REG_DEAD
11414 && GET_CODE (XEXP (link
, 0)) == REG
)
11416 unsigned int regno
= REGNO (XEXP (link
, 0));
11417 unsigned int endregno
11418 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11419 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11422 for (i
= regno
; i
< endregno
; i
++)
11423 reg_last_death
[i
] = insn
;
11425 else if (REG_NOTE_KIND (link
) == REG_INC
)
11426 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11429 if (GET_CODE (insn
) == CALL_INSN
)
11431 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11432 if (call_used_regs
[i
])
11434 reg_last_set_value
[i
] = 0;
11435 reg_last_set_mode
[i
] = 0;
11436 reg_last_set_nonzero_bits
[i
] = 0;
11437 reg_last_set_sign_bit_copies
[i
] = 0;
11438 reg_last_death
[i
] = 0;
11441 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11444 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11447 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11448 register present in the SUBREG, so for each such SUBREG go back and
11449 adjust nonzero and sign bit information of the registers that are
11450 known to have some zero/sign bits set.
11452 This is needed because when combine blows the SUBREGs away, the
11453 information on zero/sign bits is lost and further combines can be
11454 missed because of that. */
11457 record_promoted_value (insn
, subreg
)
11462 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11463 enum machine_mode mode
= GET_MODE (subreg
);
11465 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11468 for (links
= LOG_LINKS (insn
); links
;)
11470 insn
= XEXP (links
, 0);
11471 set
= single_set (insn
);
11473 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11474 || REGNO (SET_DEST (set
)) != regno
11475 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11477 links
= XEXP (links
, 1);
11481 if (reg_last_set
[regno
] == insn
)
11483 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11484 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11487 if (GET_CODE (SET_SRC (set
)) == REG
)
11489 regno
= REGNO (SET_SRC (set
));
11490 links
= LOG_LINKS (insn
);
11497 /* Scan X for promoted SUBREGs. For each one found,
11498 note what it implies to the registers used in it. */
11501 check_promoted_subreg (insn
, x
)
11505 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11506 && GET_CODE (SUBREG_REG (x
)) == REG
)
11507 record_promoted_value (insn
, x
);
11510 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11513 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11517 check_promoted_subreg (insn
, XEXP (x
, i
));
11521 if (XVEC (x
, i
) != 0)
11522 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11523 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11529 /* Utility routine for the following function. Verify that all the registers
11530 mentioned in *LOC are valid when *LOC was part of a value set when
11531 label_tick == TICK. Return 0 if some are not.
11533 If REPLACE is non-zero, replace the invalid reference with
11534 (clobber (const_int 0)) and return 1. This replacement is useful because
11535 we often can get useful information about the form of a value (e.g., if
11536 it was produced by a shift that always produces -1 or 0) even though
11537 we don't know exactly what registers it was produced from. */
11540 get_last_value_validate (loc
, insn
, tick
, replace
)
11547 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11548 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11551 if (GET_CODE (x
) == REG
)
11553 unsigned int regno
= REGNO (x
);
11554 unsigned int endregno
11555 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11556 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11559 for (j
= regno
; j
< endregno
; j
++)
11560 if (reg_last_set_invalid
[j
]
11561 /* If this is a pseudo-register that was only set once and not
11562 live at the beginning of the function, it is always valid. */
11563 || (! (regno
>= FIRST_PSEUDO_REGISTER
11564 && REG_N_SETS (regno
) == 1
11565 && (! REGNO_REG_SET_P
11566 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11567 && reg_last_set_label
[j
] > tick
))
11570 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11576 /* If this is a memory reference, make sure that there were
11577 no stores after it that might have clobbered the value. We don't
11578 have alias info, so we assume any store invalidates it. */
11579 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11580 && INSN_CUID (insn
) <= mem_last_set
)
11583 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11587 for (i
= 0; i
< len
; i
++)
11589 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11590 /* Don't bother with these. They shouldn't occur anyway. */
11594 /* If we haven't found a reason for it to be invalid, it is valid. */
11598 /* Get the last value assigned to X, if known. Some registers
11599 in the value may be replaced with (clobber (const_int 0)) if their value
11600 is known longer known reliably. */
11606 unsigned int regno
;
11609 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11610 then convert it to the desired mode. If this is a paradoxical SUBREG,
11611 we cannot predict what values the "extra" bits might have. */
11612 if (GET_CODE (x
) == SUBREG
11613 && subreg_lowpart_p (x
)
11614 && (GET_MODE_SIZE (GET_MODE (x
))
11615 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11616 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11617 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11619 if (GET_CODE (x
) != REG
)
11623 value
= reg_last_set_value
[regno
];
11625 /* If we don't have a value, or if it isn't for this basic block and
11626 it's either a hard register, set more than once, or it's a live
11627 at the beginning of the function, return 0.
11629 Because if it's not live at the beginnning of the function then the reg
11630 is always set before being used (is never used without being set).
11631 And, if it's set only once, and it's always set before use, then all
11632 uses must have the same last value, even if it's not from this basic
11636 || (reg_last_set_label
[regno
] != label_tick
11637 && (regno
< FIRST_PSEUDO_REGISTER
11638 || REG_N_SETS (regno
) != 1
11639 || (REGNO_REG_SET_P
11640 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11643 /* If the value was set in a later insn than the ones we are processing,
11644 we can't use it even if the register was only set once. */
11645 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11648 /* If the value has all its registers valid, return it. */
11649 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11650 reg_last_set_label
[regno
], 0))
11653 /* Otherwise, make a copy and replace any invalid register with
11654 (clobber (const_int 0)). If that fails for some reason, return 0. */
11656 value
= copy_rtx (value
);
11657 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11658 reg_last_set_label
[regno
], 1))
11664 /* Return nonzero if expression X refers to a REG or to memory
11665 that is set in an instruction more recent than FROM_CUID. */
11668 use_crosses_set_p (x
, from_cuid
)
11672 register const char *fmt
;
11674 register enum rtx_code code
= GET_CODE (x
);
11678 unsigned int regno
= REGNO (x
);
11679 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11680 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11682 #ifdef PUSH_ROUNDING
11683 /* Don't allow uses of the stack pointer to be moved,
11684 because we don't know whether the move crosses a push insn. */
11685 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11688 for (; regno
< endreg
; regno
++)
11689 if (reg_last_set
[regno
]
11690 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11695 if (code
== MEM
&& mem_last_set
> from_cuid
)
11698 fmt
= GET_RTX_FORMAT (code
);
11700 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11705 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11706 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11709 else if (fmt
[i
] == 'e'
11710 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11716 /* Define three variables used for communication between the following
11719 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11720 static int reg_dead_flag
;
11722 /* Function called via note_stores from reg_dead_at_p.
11724 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11725 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11728 reg_dead_at_p_1 (dest
, x
, data
)
11731 void *data ATTRIBUTE_UNUSED
;
11733 unsigned int regno
, endregno
;
11735 if (GET_CODE (dest
) != REG
)
11738 regno
= REGNO (dest
);
11739 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11740 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11742 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11743 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11746 /* Return non-zero if REG is known to be dead at INSN.
11748 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11749 referencing REG, it is dead. If we hit a SET referencing REG, it is
11750 live. Otherwise, see if it is live or dead at the start of the basic
11751 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11752 must be assumed to be always live. */
11755 reg_dead_at_p (reg
, insn
)
11762 /* Set variables for reg_dead_at_p_1. */
11763 reg_dead_regno
= REGNO (reg
);
11764 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11765 ? HARD_REGNO_NREGS (reg_dead_regno
,
11771 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11772 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11774 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11775 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11779 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11780 beginning of function. */
11781 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11782 insn
= prev_nonnote_insn (insn
))
11784 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11786 return reg_dead_flag
== 1 ? 1 : 0;
11788 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11792 /* Get the basic block number that we were in. */
11797 for (block
= 0; block
< n_basic_blocks
; block
++)
11798 if (insn
== BLOCK_HEAD (block
))
11801 if (block
== n_basic_blocks
)
11805 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11806 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11812 /* Note hard registers in X that are used. This code is similar to
11813 that in flow.c, but much simpler since we don't care about pseudos. */
11816 mark_used_regs_combine (x
)
11819 RTX_CODE code
= GET_CODE (x
);
11820 unsigned int regno
;
11832 case ADDR_DIFF_VEC
:
11835 /* CC0 must die in the insn after it is set, so we don't need to take
11836 special note of it here. */
11842 /* If we are clobbering a MEM, mark any hard registers inside the
11843 address as used. */
11844 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11845 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11850 /* A hard reg in a wide mode may really be multiple registers.
11851 If so, mark all of them just like the first. */
11852 if (regno
< FIRST_PSEUDO_REGISTER
)
11854 unsigned int endregno
, r
;
11856 /* None of this applies to the stack, frame or arg pointers */
11857 if (regno
== STACK_POINTER_REGNUM
11858 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11859 || regno
== HARD_FRAME_POINTER_REGNUM
11861 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11862 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11864 || regno
== FRAME_POINTER_REGNUM
)
11867 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11868 for (r
= regno
; r
< endregno
; r
++)
11869 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11875 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11877 register rtx testreg
= SET_DEST (x
);
11879 while (GET_CODE (testreg
) == SUBREG
11880 || GET_CODE (testreg
) == ZERO_EXTRACT
11881 || GET_CODE (testreg
) == SIGN_EXTRACT
11882 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11883 testreg
= XEXP (testreg
, 0);
11885 if (GET_CODE (testreg
) == MEM
)
11886 mark_used_regs_combine (XEXP (testreg
, 0));
11888 mark_used_regs_combine (SET_SRC (x
));
11896 /* Recursively scan the operands of this expression. */
11899 register const char *fmt
= GET_RTX_FORMAT (code
);
11901 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11904 mark_used_regs_combine (XEXP (x
, i
));
11905 else if (fmt
[i
] == 'E')
11909 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11910 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11916 /* Remove register number REGNO from the dead registers list of INSN.
11918 Return the note used to record the death, if there was one. */
11921 remove_death (regno
, insn
)
11922 unsigned int regno
;
11925 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11929 REG_N_DEATHS (regno
)--;
11930 remove_note (insn
, note
);
11936 /* For each register (hardware or pseudo) used within expression X, if its
11937 death is in an instruction with cuid between FROM_CUID (inclusive) and
11938 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11939 list headed by PNOTES.
11941 That said, don't move registers killed by maybe_kill_insn.
11943 This is done when X is being merged by combination into TO_INSN. These
11944 notes will then be distributed as needed. */
11947 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11949 rtx maybe_kill_insn
;
11954 register const char *fmt
;
11955 register int len
, i
;
11956 register enum rtx_code code
= GET_CODE (x
);
11960 unsigned int regno
= REGNO (x
);
11961 register rtx where_dead
= reg_last_death
[regno
];
11962 register rtx before_dead
, after_dead
;
11964 /* Don't move the register if it gets killed in between from and to */
11965 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11966 && ! reg_referenced_p (x
, maybe_kill_insn
))
11969 /* WHERE_DEAD could be a USE insn made by combine, so first we
11970 make sure that we have insns with valid INSN_CUID values. */
11971 before_dead
= where_dead
;
11972 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11973 before_dead
= PREV_INSN (before_dead
);
11975 after_dead
= where_dead
;
11976 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11977 after_dead
= NEXT_INSN (after_dead
);
11979 if (before_dead
&& after_dead
11980 && INSN_CUID (before_dead
) >= from_cuid
11981 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11982 || (where_dead
!= after_dead
11983 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11985 rtx note
= remove_death (regno
, where_dead
);
11987 /* It is possible for the call above to return 0. This can occur
11988 when reg_last_death points to I2 or I1 that we combined with.
11989 In that case make a new note.
11991 We must also check for the case where X is a hard register
11992 and NOTE is a death note for a range of hard registers
11993 including X. In that case, we must put REG_DEAD notes for
11994 the remaining registers in place of NOTE. */
11996 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11997 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11998 > GET_MODE_SIZE (GET_MODE (x
))))
12000 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12001 unsigned int deadend
12002 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12003 GET_MODE (XEXP (note
, 0))));
12004 unsigned int ourend
12005 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12008 for (i
= deadregno
; i
< deadend
; i
++)
12009 if (i
< regno
|| i
>= ourend
)
12010 REG_NOTES (where_dead
)
12011 = gen_rtx_EXPR_LIST (REG_DEAD
,
12012 gen_rtx_REG (reg_raw_mode
[i
], i
),
12013 REG_NOTES (where_dead
));
12016 /* If we didn't find any note, or if we found a REG_DEAD note that
12017 covers only part of the given reg, and we have a multi-reg hard
12018 register, then to be safe we must check for REG_DEAD notes
12019 for each register other than the first. They could have
12020 their own REG_DEAD notes lying around. */
12021 else if ((note
== 0
12023 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12024 < GET_MODE_SIZE (GET_MODE (x
)))))
12025 && regno
< FIRST_PSEUDO_REGISTER
12026 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12028 unsigned int ourend
12029 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12030 unsigned int i
, offset
;
12034 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12038 for (i
= regno
+ offset
; i
< ourend
; i
++)
12039 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
12040 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12043 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12045 XEXP (note
, 1) = *pnotes
;
12049 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12051 REG_N_DEATHS (regno
)++;
12057 else if (GET_CODE (x
) == SET
)
12059 rtx dest
= SET_DEST (x
);
12061 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12063 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12064 that accesses one word of a multi-word item, some
12065 piece of everything register in the expression is used by
12066 this insn, so remove any old death. */
12068 if (GET_CODE (dest
) == ZERO_EXTRACT
12069 || GET_CODE (dest
) == STRICT_LOW_PART
12070 || (GET_CODE (dest
) == SUBREG
12071 && (((GET_MODE_SIZE (GET_MODE (dest
))
12072 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12073 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12074 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12076 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12080 /* If this is some other SUBREG, we know it replaces the entire
12081 value, so use that as the destination. */
12082 if (GET_CODE (dest
) == SUBREG
)
12083 dest
= SUBREG_REG (dest
);
12085 /* If this is a MEM, adjust deaths of anything used in the address.
12086 For a REG (the only other possibility), the entire value is
12087 being replaced so the old value is not used in this insn. */
12089 if (GET_CODE (dest
) == MEM
)
12090 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12095 else if (GET_CODE (x
) == CLOBBER
)
12098 len
= GET_RTX_LENGTH (code
);
12099 fmt
= GET_RTX_FORMAT (code
);
12101 for (i
= 0; i
< len
; i
++)
12106 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12107 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12110 else if (fmt
[i
] == 'e')
12111 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12115 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12116 pattern of an insn. X must be a REG. */
12119 reg_bitfield_target_p (x
, body
)
12125 if (GET_CODE (body
) == SET
)
12127 rtx dest
= SET_DEST (body
);
12129 unsigned int regno
, tregno
, endregno
, endtregno
;
12131 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12132 target
= XEXP (dest
, 0);
12133 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12134 target
= SUBREG_REG (XEXP (dest
, 0));
12138 if (GET_CODE (target
) == SUBREG
)
12139 target
= SUBREG_REG (target
);
12141 if (GET_CODE (target
) != REG
)
12144 tregno
= REGNO (target
), regno
= REGNO (x
);
12145 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12146 return target
== x
;
12148 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12149 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12151 return endregno
> tregno
&& regno
< endtregno
;
12154 else if (GET_CODE (body
) == PARALLEL
)
12155 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12156 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12162 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12163 as appropriate. I3 and I2 are the insns resulting from the combination
12164 insns including FROM (I2 may be zero).
12166 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12167 not need REG_DEAD notes because they are being substituted for. This
12168 saves searching in the most common cases.
12170 Each note in the list is either ignored or placed on some insns, depending
12171 on the type of note. */
12174 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
12178 rtx elim_i2
, elim_i1
;
12180 rtx note
, next_note
;
12183 for (note
= notes
; note
; note
= next_note
)
12185 rtx place
= 0, place2
= 0;
12187 /* If this NOTE references a pseudo register, ensure it references
12188 the latest copy of that register. */
12189 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12190 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12191 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12193 next_note
= XEXP (note
, 1);
12194 switch (REG_NOTE_KIND (note
))
12197 case REG_EXEC_COUNT
:
12198 /* Doesn't matter much where we put this, as long as it's somewhere.
12199 It is preferable to keep these notes on branches, which is most
12200 likely to be i3. */
12204 case REG_NON_LOCAL_GOTO
:
12205 if (GET_CODE (i3
) == JUMP_INSN
)
12207 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12213 case REG_EH_REGION
:
12214 /* These notes must remain with the call or trapping instruction. */
12215 if (GET_CODE (i3
) == CALL_INSN
)
12217 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12219 else if (flag_non_call_exceptions
)
12221 if (may_trap_p (i3
))
12223 else if (i2
&& may_trap_p (i2
))
12225 /* ??? Otherwise assume we've combined things such that we
12226 can now prove that the instructions can't trap. Drop the
12227 note in this case. */
12233 case REG_EH_RETHROW
:
12235 /* These notes must remain with the call. It should not be
12236 possible for both I2 and I3 to be a call. */
12237 if (GET_CODE (i3
) == CALL_INSN
)
12239 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12246 /* Any clobbers for i3 may still exist, and so we must process
12247 REG_UNUSED notes from that insn.
12249 Any clobbers from i2 or i1 can only exist if they were added by
12250 recog_for_combine. In that case, recog_for_combine created the
12251 necessary REG_UNUSED notes. Trying to keep any original
12252 REG_UNUSED notes from these insns can cause incorrect output
12253 if it is for the same register as the original i3 dest.
12254 In that case, we will notice that the register is set in i3,
12255 and then add a REG_UNUSED note for the destination of i3, which
12256 is wrong. However, it is possible to have REG_UNUSED notes from
12257 i2 or i1 for register which were both used and clobbered, so
12258 we keep notes from i2 or i1 if they will turn into REG_DEAD
12261 /* If this register is set or clobbered in I3, put the note there
12262 unless there is one already. */
12263 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12265 if (from_insn
!= i3
)
12268 if (! (GET_CODE (XEXP (note
, 0)) == REG
12269 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12270 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12273 /* Otherwise, if this register is used by I3, then this register
12274 now dies here, so we must put a REG_DEAD note here unless there
12276 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12277 && ! (GET_CODE (XEXP (note
, 0)) == REG
12278 ? find_regno_note (i3
, REG_DEAD
,
12279 REGNO (XEXP (note
, 0)))
12280 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12282 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12290 /* These notes say something about results of an insn. We can
12291 only support them if they used to be on I3 in which case they
12292 remain on I3. Otherwise they are ignored.
12294 If the note refers to an expression that is not a constant, we
12295 must also ignore the note since we cannot tell whether the
12296 equivalence is still true. It might be possible to do
12297 slightly better than this (we only have a problem if I2DEST
12298 or I1DEST is present in the expression), but it doesn't
12299 seem worth the trouble. */
12301 if (from_insn
== i3
12302 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12307 case REG_NO_CONFLICT
:
12308 /* These notes say something about how a register is used. They must
12309 be present on any use of the register in I2 or I3. */
12310 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12313 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12323 /* This can show up in several ways -- either directly in the
12324 pattern, or hidden off in the constant pool with (or without?)
12325 a REG_EQUAL note. */
12326 /* ??? Ignore the without-reg_equal-note problem for now. */
12327 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12328 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12329 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12330 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12334 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12335 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12336 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12337 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12348 /* These notes say something about the value of a register prior
12349 to the execution of an insn. It is too much trouble to see
12350 if the note is still correct in all situations. It is better
12351 to simply delete it. */
12355 /* If the insn previously containing this note still exists,
12356 put it back where it was. Otherwise move it to the previous
12357 insn. Adjust the corresponding REG_LIBCALL note. */
12358 if (GET_CODE (from_insn
) != NOTE
)
12362 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12363 place
= prev_real_insn (from_insn
);
12365 XEXP (tem
, 0) = place
;
12366 /* If we're deleting the last remaining instruction of a
12367 libcall sequence, don't add the notes. */
12368 else if (XEXP (note
, 0) == from_insn
)
12374 /* This is handled similarly to REG_RETVAL. */
12375 if (GET_CODE (from_insn
) != NOTE
)
12379 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12380 place
= next_real_insn (from_insn
);
12382 XEXP (tem
, 0) = place
;
12383 /* If we're deleting the last remaining instruction of a
12384 libcall sequence, don't add the notes. */
12385 else if (XEXP (note
, 0) == from_insn
)
12391 /* If the register is used as an input in I3, it dies there.
12392 Similarly for I2, if it is non-zero and adjacent to I3.
12394 If the register is not used as an input in either I3 or I2
12395 and it is not one of the registers we were supposed to eliminate,
12396 there are two possibilities. We might have a non-adjacent I2
12397 or we might have somehow eliminated an additional register
12398 from a computation. For example, we might have had A & B where
12399 we discover that B will always be zero. In this case we will
12400 eliminate the reference to A.
12402 In both cases, we must search to see if we can find a previous
12403 use of A and put the death note there. */
12406 && GET_CODE (from_insn
) == CALL_INSN
12407 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12409 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12411 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12412 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12415 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12416 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12421 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12423 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12425 if (! INSN_P (tem
))
12427 if (tem
== bb
->head
)
12432 /* If the register is being set at TEM, see if that is all
12433 TEM is doing. If so, delete TEM. Otherwise, make this
12434 into a REG_UNUSED note instead. */
12435 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12437 rtx set
= single_set (tem
);
12438 rtx inner_dest
= 0;
12440 rtx cc0_setter
= NULL_RTX
;
12444 for (inner_dest
= SET_DEST (set
);
12445 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12446 || GET_CODE (inner_dest
) == SUBREG
12447 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12448 inner_dest
= XEXP (inner_dest
, 0))
12451 /* Verify that it was the set, and not a clobber that
12452 modified the register.
12454 CC0 targets must be careful to maintain setter/user
12455 pairs. If we cannot delete the setter due to side
12456 effects, mark the user with an UNUSED note instead
12459 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12460 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12462 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12463 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12464 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12468 /* Move the notes and links of TEM elsewhere.
12469 This might delete other dead insns recursively.
12470 First set the pattern to something that won't use
12473 PATTERN (tem
) = pc_rtx
;
12475 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12476 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12477 distribute_links (LOG_LINKS (tem
));
12479 PUT_CODE (tem
, NOTE
);
12480 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12481 NOTE_SOURCE_FILE (tem
) = 0;
12484 /* Delete the setter too. */
12487 PATTERN (cc0_setter
) = pc_rtx
;
12489 distribute_notes (REG_NOTES (cc0_setter
),
12490 cc0_setter
, cc0_setter
,
12491 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12492 distribute_links (LOG_LINKS (cc0_setter
));
12494 PUT_CODE (cc0_setter
, NOTE
);
12495 NOTE_LINE_NUMBER (cc0_setter
)
12496 = NOTE_INSN_DELETED
;
12497 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12501 /* If the register is both set and used here, put the
12502 REG_DEAD note here, but place a REG_UNUSED note
12503 here too unless there already is one. */
12504 else if (reg_referenced_p (XEXP (note
, 0),
12509 if (! find_regno_note (tem
, REG_UNUSED
,
12510 REGNO (XEXP (note
, 0))))
12512 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12517 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12519 /* If there isn't already a REG_UNUSED note, put one
12521 if (! find_regno_note (tem
, REG_UNUSED
,
12522 REGNO (XEXP (note
, 0))))
12527 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12528 || (GET_CODE (tem
) == CALL_INSN
12529 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12533 /* If we are doing a 3->2 combination, and we have a
12534 register which formerly died in i3 and was not used
12535 by i2, which now no longer dies in i3 and is used in
12536 i2 but does not die in i2, and place is between i2
12537 and i3, then we may need to move a link from place to
12539 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12540 && INSN_CUID (place
) > INSN_CUID (i2
)
12542 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12543 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12545 rtx links
= LOG_LINKS (place
);
12546 LOG_LINKS (place
) = 0;
12547 distribute_links (links
);
12552 if (tem
== bb
->head
)
12556 /* We haven't found an insn for the death note and it
12557 is still a REG_DEAD note, but we have hit the beginning
12558 of the block. If the existing life info says the reg
12559 was dead, there's nothing left to do. Otherwise, we'll
12560 need to do a global life update after combine. */
12561 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12562 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12563 REGNO (XEXP (note
, 0))))
12565 SET_BIT (refresh_blocks
, this_basic_block
);
12570 /* If the register is set or already dead at PLACE, we needn't do
12571 anything with this note if it is still a REG_DEAD note.
12572 We can here if it is set at all, not if is it totally replace,
12573 which is what `dead_or_set_p' checks, so also check for it being
12576 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12578 unsigned int regno
= REGNO (XEXP (note
, 0));
12580 if (dead_or_set_p (place
, XEXP (note
, 0))
12581 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12583 /* Unless the register previously died in PLACE, clear
12584 reg_last_death. [I no longer understand why this is
12586 if (reg_last_death
[regno
] != place
)
12587 reg_last_death
[regno
] = 0;
12591 reg_last_death
[regno
] = place
;
12593 /* If this is a death note for a hard reg that is occupying
12594 multiple registers, ensure that we are still using all
12595 parts of the object. If we find a piece of the object
12596 that is unused, we must arrange for an appropriate REG_DEAD
12597 note to be added for it. However, we can't just emit a USE
12598 and tag the note to it, since the register might actually
12599 be dead; so we recourse, and the recursive call then finds
12600 the previous insn that used this register. */
12602 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12603 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12605 unsigned int endregno
12606 = regno
+ HARD_REGNO_NREGS (regno
,
12607 GET_MODE (XEXP (note
, 0)));
12611 for (i
= regno
; i
< endregno
; i
++)
12612 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12613 && ! find_regno_fusage (place
, USE
, i
))
12614 || dead_or_set_regno_p (place
, i
))
12619 /* Put only REG_DEAD notes for pieces that are
12620 not already dead or set. */
12622 for (i
= regno
; i
< endregno
;
12623 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12625 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12626 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12628 if (! dead_or_set_p (place
, piece
)
12629 && ! reg_bitfield_target_p (piece
,
12633 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12635 distribute_notes (new_note
, place
, place
,
12636 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12638 else if (! refers_to_regno_p (i
, i
+ 1,
12639 PATTERN (place
), 0)
12640 && ! find_regno_fusage (place
, USE
, i
))
12641 for (tem
= PREV_INSN (place
); ;
12642 tem
= PREV_INSN (tem
))
12644 if (! INSN_P (tem
))
12646 if (tem
== bb
->head
)
12648 SET_BIT (refresh_blocks
,
12655 if (dead_or_set_p (tem
, piece
)
12656 || reg_bitfield_target_p (piece
,
12660 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12675 /* Any other notes should not be present at this point in the
12682 XEXP (note
, 1) = REG_NOTES (place
);
12683 REG_NOTES (place
) = note
;
12685 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12686 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12687 && GET_CODE (XEXP (note
, 0)) == REG
)
12688 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12692 if ((REG_NOTE_KIND (note
) == REG_DEAD
12693 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12694 && GET_CODE (XEXP (note
, 0)) == REG
)
12695 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12697 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12698 REG_NOTE_KIND (note
),
12700 REG_NOTES (place2
));
12705 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12706 I3, I2, and I1 to new locations. This is also called in one case to
12707 add a link pointing at I3 when I3's destination is changed. */
12710 distribute_links (links
)
12713 rtx link
, next_link
;
12715 for (link
= links
; link
; link
= next_link
)
12721 next_link
= XEXP (link
, 1);
12723 /* If the insn that this link points to is a NOTE or isn't a single
12724 set, ignore it. In the latter case, it isn't clear what we
12725 can do other than ignore the link, since we can't tell which
12726 register it was for. Such links wouldn't be used by combine
12729 It is not possible for the destination of the target of the link to
12730 have been changed by combine. The only potential of this is if we
12731 replace I3, I2, and I1 by I3 and I2. But in that case the
12732 destination of I2 also remains unchanged. */
12734 if (GET_CODE (XEXP (link
, 0)) == NOTE
12735 || (set
= single_set (XEXP (link
, 0))) == 0)
12738 reg
= SET_DEST (set
);
12739 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12740 || GET_CODE (reg
) == SIGN_EXTRACT
12741 || GET_CODE (reg
) == STRICT_LOW_PART
)
12742 reg
= XEXP (reg
, 0);
12744 /* A LOG_LINK is defined as being placed on the first insn that uses
12745 a register and points to the insn that sets the register. Start
12746 searching at the next insn after the target of the link and stop
12747 when we reach a set of the register or the end of the basic block.
12749 Note that this correctly handles the link that used to point from
12750 I3 to I2. Also note that not much searching is typically done here
12751 since most links don't point very far away. */
12753 for (insn
= NEXT_INSN (XEXP (link
, 0));
12754 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12755 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12756 insn
= NEXT_INSN (insn
))
12757 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12759 if (reg_referenced_p (reg
, PATTERN (insn
)))
12763 else if (GET_CODE (insn
) == CALL_INSN
12764 && find_reg_fusage (insn
, USE
, reg
))
12770 /* If we found a place to put the link, place it there unless there
12771 is already a link to the same insn as LINK at that point. */
12777 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12778 if (XEXP (link2
, 0) == XEXP (link
, 0))
12783 XEXP (link
, 1) = LOG_LINKS (place
);
12784 LOG_LINKS (place
) = link
;
12786 /* Set added_links_insn to the earliest insn we added a
12788 if (added_links_insn
== 0
12789 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12790 added_links_insn
= place
;
12796 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12802 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12803 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12804 insn
= NEXT_INSN (insn
);
12806 if (INSN_UID (insn
) > max_uid_cuid
)
12809 return INSN_CUID (insn
);
12813 dump_combine_stats (file
)
12818 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12819 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12823 dump_combine_total_stats (file
)
12828 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12829 total_attempts
, total_merges
, total_extras
, total_successes
);