| blob | 273a9820df8abf6d06602a74b112028aa0799025 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
101 /* Include output.h for dump_file. */
109 /* Number of attempts to combine instructions in this function. */
113 /* Number of attempts that got as far as substitution in this function. */
117 /* Number of instructions combined with added SETs in this function. */
121 /* Number of instructions combined in this function. */
125 /* Totals over entire compilation. */
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
145 \f
147 /* Record last point of death of (hard or pseudo) register n. */
148 rtx last_death;
150 /* Record last point of modification of (hard or pseudo) register n. */
151 rtx last_set;
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
160 following ways:
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
175 register's value
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
180 table.
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
198 rtx last_set_value;
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
205 /* Record the value of label_tick when the value for register n is placed in
206 last_set_value. */
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
233 zero.
235 If an entry is zero, it means that we don't know anything special. */
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
250 value. */
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
294 that location. */
298 /* Basic block in which we are performing combines. */
302 \f
303 /* Length of the currently allocated uid_insn_cost array. */
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
324 /* Reset to label_tick for each extended basic block in scanning order. */
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
337 in a loop. */
341 \f
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
347 struct undo
348 {
353 };
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
361 struct undobuf
362 {
365 rtx other_insn;
366 };
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
451 \f
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
473 \f
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
478 register. */
480 static rtx
482 {
483 rtx ret;
491 }
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
501 {
510 {
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
544 }
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
551 {
553 {
558 else
564 /* Duplicate usage. */
566 }
568 {
572 {
578 else
585 }
586 }
587 }
590 }
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
595 it is used.
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
609 {
610 basic_block bb;
611 rtx next;
613 rtx link;
615 #ifdef HAVE_cc0
617 {
627 }
628 #endif
638 {
644 {
649 }
650 }
653 }
654 \f
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
659 the undo table. */
661 static void
663 {
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
677 {
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
693 }
697 else
706 }
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
712 not safe. */
714 static void
716 {
725 else
734 }
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
741 well. */
743 static void
745 {
754 else
763 }
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
766 \f
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
774 sequence. */
776 static bool
779 {
784 /* Lookup the original insn_rtx_costs. */
789 {
792 {
796 }
797 else
798 {
802 }
803 }
804 else
805 {
808 }
810 /* Calculate the replacement insn_rtx_costs. */
813 {
817 }
818 else
819 {
822 }
825 {
831 {
834 }
835 else
837 }
839 /* Disallow this recombination if both new_cost and old_cost are
840 greater than zero, and new_cost is greater than old cost. */
843 {
845 {
847 {
854 }
856 {
862 }
863 else
864 {
870 }
873 {
876 }
877 else
879 }
882 }
884 /* Update the uid_insn_cost array with the replacement costs. */
891 }
894 /* Delete any insns that copy a register to itself. */
896 static void
898 {
900 basic_block bb;
903 {
905 {
908 {
913 }
914 }
915 }
916 }
918 \f
919 /* Fill in log links field for all insns. */
921 static void
923 {
924 basic_block bb;
930 /* Pass through each block from the end, recording the uses of each
931 register and establishing log links when def is encountered.
932 Note that we do not clear next_use array in order to save time,
933 so we have to test whether the use is in the same basic block as def.
935 There are a few cases below when we do not consider the definition or
936 usage -- these are taken from original flow.c did. Don't ask me why it is
937 done this way; I don't know and if it works, I don't want to know. */
940 {
942 {
946 /* Log links are created only once. */
950 {
953 rtx use_insn;
958 /* Do not consider if it is pre/post modification in MEM. */
962 /* Do not make the log link for frame pointer. */
965 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
968 #endif
969 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
971 #endif
972 )
977 {
978 /* flow.c claimed:
980 We don't build a LOG_LINK for hard registers contained
981 in ASM_OPERANDs. If these registers get replaced,
982 we might wind up changing the semantics of the insn,
983 even if reload can make what appear to be valid
984 assignments later. */
987 {
988 /* Don't add duplicate links between instructions. */
989 rtx links;
998 }
999 }
1001 }
1004 {
1008 /* Do not consider the usage of the stack pointer
1009 by function call. */
1014 }
1015 }
1016 }
1019 }
1021 /* Clear LOG_LINKS fields of insns. */
1023 static void
1025 {
1026 rtx insn;
1031 }
1033 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1034 true if we found a LOG_LINK that proves that A feeds B. This only works
1035 if there are no instructions between A and B which could have a link
1036 depending on A, since in that case we would not record a link for B. */
1038 static bool
1040 {
1041 rtx links;
1046 }
1047 \f
1048 /* Main entry point for combiner. F is the first insn of the function.
1049 NREGS is the first unused pseudo-reg number.
1051 Return nonzero if the combiner has turned an indirect jump
1052 instruction into a direct jump. */
1053 static int
1055 {
1057 #ifdef HAVE_cc0
1058 rtx prev;
1059 #endif
1061 rtx first;
1062 basic_block last_bb;
1082 /* Allocate array for insn info. */
1089 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1090 problems when, for example, we have j <<= 1 in a loop. */
1095 /* Scan all SETs and see if we can deduce anything about what
1096 bits are known to be zero for some registers and how many copies
1097 of the sign bit are known to exist for those registers.
1099 Also set any known values so that we can use it while searching
1100 for what bits are known to be set. */
1103 /* Allow the entry block and the first block to fall into the same EBB.
1104 Conceptually the incoming promotions are assigned to the entry block. */
1109 {
1114 label_tick++;
1122 {
1127 insn);
1130 #ifdef AUTO_INC_DEC
1134 insn);
1135 #endif
1137 /* Record the current insn_rtx_cost of this instruction. */
1140 optimize_this_for_speed_p);
1144 }
1145 }
1149 /* Now scan all the insns in forward order. */
1156 {
1161 label_tick++;
1171 {
1174 {
1175 /* See if we know about function return values before this
1176 insn based upon SUBREG flags. */
1179 /* See if we can find hardregs and subreg of pseudos in
1180 narrower modes. This could help turning TRUNCATEs
1181 into SUBREGs. */
1184 /* Try this insn with each insn it links back to. */
1191 /* Try each sequence of three linked insns ending with this one. */
1194 {
1197 /* If the linked insn has been replaced by a note, then there
1198 is no point in pursuing this chain any further. */
1203 nextlinks;
1206 NULL_RTX,
1209 }
1211 #ifdef HAVE_cc0
1212 /* Try to combine a jump insn that uses CC0
1213 with a preceding insn that sets CC0, and maybe with its
1214 logical predecessor as well.
1215 This is how we make decrement-and-branch insns.
1216 We need this special code because data flow connections
1217 via CC0 do not get entered in LOG_LINKS. */
1223 {
1231 NULL_RTX,
1234 }
1236 /* Do the same for an insn that explicitly references CC0. */
1243 {
1251 NULL_RTX,
1254 }
1256 /* Finally, see if any of the insns that this insn links to
1257 explicitly references CC0. If so, try this insn, that insn,
1258 and its predecessor if it sets CC0. */
1270 #endif
1272 /* Try combining an insn with two different insns whose results it
1273 uses. */
1282 /* Try four-instruction combinations. */
1284 {
1285 rtx next1;
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1294 {
1298 /* I0 -> I1 -> I2 -> I3. */
1305 /* I0, I1 -> I2, I2 -> I3. */
1312 }
1315 {
1319 /* I0 -> I2; I1, I2 -> I3. */
1326 /* I0 -> I1; I1, I2 -> I3. */
1333 }
1334 }
1336 /* Try this insn with each REG_EQUAL note it links back to. */
1338 {
1344 /* Avoid using a register that may already been marked
1345 dead by an earlier instruction. */
1350 {
1351 /* Temporarily replace the set's source with the
1352 contents of the REG_EQUAL note. The insn will
1353 be deleted or recognized by try_combine. */
1365 }
1366 }
1371 retry:
1372 ;
1373 }
1374 }
1375 }
1383 /* Clean up. */
1388 {
1391 {
1394 }
1396 }
1406 /* Make recognizer allow volatile MEMs again. */
1410 }
1412 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1414 static void
1416 {
1422 }
1423 \f
1424 /* Set up any promoted values for incoming argument registers. */
1426 static void
1428 {
1429 tree arg;
1434 {
1439 /* Only continue if the incoming argument is in a register. */
1443 /* Determine, if possible, whether all call sites of the current
1444 function lie within the current compilation unit. (This does
1445 take into account the exporting of a function via taking its
1446 address, and so forth.) */
1449 /* The mode and signedness of the argument before any promotions happen
1450 (equal to the mode of the pseudo holding it at that stage). */
1454 /* The mode and signedness of the argument after any source language and
1455 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1459 /* The mode and signedness of the argument as it is actually passed,
1460 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1464 /* The mode of the register in which the argument is being passed. */
1467 /* Eliminate sign extensions in the callee when:
1468 (a) A mode promotion has occurred; */
1471 /* (b) The mode of the register is the same as the mode of
1472 the argument as it is passed; */
1475 /* (c) There's no language level extension; */
1477 ;
1478 /* (c.1) All callers are from the current compilation unit. If that's
1479 the case we don't have to rely on an ABI, we only have to know
1480 what we're generating right now, and we know that we will do the
1481 mode1 to mode2 promotion with the given sign. */
1484 /* (c.2) The combination of the two promotions is useful. This is
1485 true when the signs match, or if the first promotion is unsigned.
1486 In the later case, (sign_extend (zero_extend x)) is the same as
1487 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1493 /* Record that the value was promoted from mode1 to mode3,
1494 so that any sign extension at the head of the current
1495 function may be eliminated. */
1499 }
1500 }
1502 /* Called via note_stores. If X is a pseudo that is narrower than
1503 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1505 If we are setting only a portion of X and we can't figure out what
1506 portion, assume all bits will be used since we don't know what will
1507 be happening.
1509 Similarly, set how many bits of X are known to be copies of the sign bit
1510 at all locations in the function. This is the smallest number implied
1511 by any set of X. */
1513 static void
1515 {
1521 /* If this register is undefined at the start of the file, we can't
1522 say what its contents were. */
1523 && ! REGNO_REG_SET_P
1526 {
1530 {
1534 }
1536 /* If this register is being initialized using itself, and the
1537 register is uninitialized in this basic block, and there are
1538 no LOG_LINKS which set the register, then part of the
1539 register is uninitialized. In that case we can't assume
1540 anything about the number of nonzero bits.
1542 ??? We could do better if we checked this in
1543 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1544 could avoid making assumptions about the insn which initially
1545 sets the register, while still using the information in other
1546 insns. We would have to be careful to check every insn
1547 involved in the combination. */
1553 {
1554 rtx link;
1557 {
1560 }
1562 {
1566 }
1567 }
1569 /* If this is a complex assignment, see if we can convert it into a
1570 simple assignment. */
1573 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1574 set what we know about X. */
1581 {
1584 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1585 /* If X is narrower than a word and SRC is a non-negative
1586 constant that would appear negative in the mode of X,
1587 sign-extend it for use in reg_stat[].nonzero_bits because some
1588 machines (maybe most) will actually do the sign-extension
1589 and this is the conservative approach.
1591 ??? For 2.5, try to tighten up the MD files in this regard
1592 instead of this kludge. */
1603 #endif
1605 /* Don't call nonzero_bits if it cannot change anything. */
1612 }
1613 else
1614 {
1617 }
1618 }
1619 }
1620 \f
1621 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1622 optionally insns that were previously combined into I3 or that will be
1623 combined into the merger of INSN and I3. The order is PRED, PRED2,
1624 INSN, SUCC, SUCC2, I3.
1626 Return 0 if the combination is not allowed for any reason.
1628 If the combination is allowed, *PDEST will be set to the single
1629 destination of INSN and *PSRC to the single source, and this function
1630 will return 1. */
1632 static int
1636 {
1640 rtx p;
1641 #ifdef AUTO_INC_DEC
1642 rtx link;
1643 #endif
1647 {
1649 {
1654 }
1659 }
1663 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1664 or a PARALLEL consisting of such a SET and CLOBBERs.
1666 If INSN has CLOBBER parallel parts, ignore them for our processing.
1667 By definition, these happen during the execution of the insn. When it
1668 is merged with another insn, all bets are off. If they are, in fact,
1669 needed and aren't also supplied in I3, they may be added by
1670 recog_for_combine. Otherwise, it won't match.
1672 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1673 note.
1675 Get the source and destination of INSN. If more than one, can't
1676 combine. */
1682 {
1684 {
1688 {
1689 /* This is important to combine floating point insns
1690 for the SH4 port. */
1692 /* Combining an isolated USE doesn't make sense.
1693 We depend here on combinable_i3pat to reject them. */
1694 /* The code below this loop only verifies that the inputs of
1695 the SET in INSN do not change. We call reg_set_between_p
1696 to verify that the REG in the USE does not change between
1697 I3 and INSN.
1698 If the USE in INSN was for a pseudo register, the matching
1699 insn pattern will likely match any register; combining this
1700 with any other USE would only be safe if we knew that the
1701 used registers have identical values, or if there was
1702 something to tell them apart, e.g. different modes. For
1703 now, we forgo such complicated tests and simply disallow
1704 combining of USES of pseudo registers with any other USE. */
1707 {
1712 do
1713 {
1723 }
1725 }
1728 /* We can ignore CLOBBERs. */
1733 /* Ignore SETs whose result isn't used but not those that
1734 have side-effects. */
1740 /* If we have already found a SET, this is a second one and
1741 so we cannot combine with this insn. */
1749 /* Anything else means we can't combine. */
1751 }
1752 }
1755 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1756 so don't do anything with it. */
1759 }
1760 else
1769 /* Don't eliminate a store in the stack pointer. */
1771 /* Don't combine with an insn that sets a register to itself if it has
1772 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1774 /* Can't merge an ASM_OPERANDS. */
1776 /* Can't merge a function call. */
1778 /* Don't eliminate a function call argument. */
1784 /* Don't substitute into an incremented register. */
1788 /* Don't substitute into a non-local goto, this confuses CFG. */
1790 /* Make sure that DEST is not used after SUCC but before I3. */
1791 || (!all_adjacent
1792 && ((succ2
1796 /* Make sure that the value that is to be substituted for the register
1797 does not use any registers whose values alter in between. However,
1798 If the insns are adjacent, a use can't cross a set even though we
1799 think it might (this can happen for a sequence of insns each setting
1800 the same destination; last_set of that register might point to
1801 a NOTE). If INSN has a REG_EQUIV note, the register is always
1802 equivalent to the memory so the substitution is valid even if there
1803 are intervening stores. Also, don't move a volatile asm or
1804 UNSPEC_VOLATILE across any other insns. */
1805 || (! all_adjacent
1811 /* Don't combine across a CALL_INSN, because that would possibly
1812 change whether the life span of some REGs crosses calls or not,
1813 and it is a pain to update that information.
1814 Exception: if source is a constant, moving it later can't hurt.
1815 Accept that as a special case. */
1819 /* DEST must either be a REG or CC0. */
1821 {
1822 /* If register alignment is being enforced for multi-word items in all
1823 cases except for parameters, it is possible to have a register copy
1824 insn referencing a hard register that is not allowed to contain the
1825 mode being copied and which would not be valid as an operand of most
1826 insns. Eliminate this problem by not combining with such an insn.
1828 Also, on some machines we don't want to extend the life of a hard
1829 register. */
1834 /* Don't extend the life of a hard register unless it is
1835 user variable (if we have few registers) or it can't
1836 fit into the desired register (meaning something special
1837 is going on).
1838 Also avoid substituting a return register into I3, because
1839 reload can't handle a conflict with constraints of other
1840 inputs. */
1844 }
1852 {
1853 /* Don't substitute for a register intended as a clobberable
1854 operand. */
1859 /* If the clobber represents an earlyclobber operand, we must not
1860 substitute an expression containing the clobbered register.
1861 As we do not analyze the constraint strings here, we have to
1862 make the conservative assumption. However, if the register is
1863 a fixed hard reg, the clobber cannot represent any operand;
1864 we leave it up to the machine description to either accept or
1865 reject use-and-clobber patterns. */
1871 }
1873 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1874 or not), reject, unless nothing volatile comes between it and I3 */
1877 {
1878 /* Make sure neither succ nor succ2 contains a volatile reference. */
1883 /* We'll check insns between INSN and I3 below. */
1884 }
1886 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1887 to be an explicit register variable, and was chosen for a reason. */
1893 /* If there are any volatile insns between INSN and I3, reject, because
1894 they might affect machine state. */
1900 /* If INSN contains an autoincrement or autodecrement, make sure that
1901 register is not used between there and I3, and not already used in
1902 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1903 Also insist that I3 not be a jump; if it were one
1904 and the incremented register were spilled, we would lose. */
1906 #ifdef AUTO_INC_DEC
1921 #endif
1923 #ifdef HAVE_cc0
1924 /* Don't combine an insn that follows a CC0-setting insn.
1925 An insn that uses CC0 must not be separated from the one that sets it.
1926 We do, however, allow I2 to follow a CC0-setting insn if that insn
1927 is passed as I1; in that case it will be deleted also.
1928 We also allow combining in this case if all the insns are adjacent
1929 because that would leave the two CC0 insns adjacent as well.
1930 It would be more logical to test whether CC0 occurs inside I1 or I2,
1931 but that would be much slower, and this ought to be equivalent. */
1937 #endif
1939 /* If we get here, we have passed all the tests and the combination is
1940 to be allowed. */
1946 }
1947 \f
1948 /* LOC is the location within I3 that contains its pattern or the component
1949 of a PARALLEL of the pattern. We validate that it is valid for combining.
1951 One problem is if I3 modifies its output, as opposed to replacing it
1952 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1953 doing so would produce an insn that is not equivalent to the original insns.
1955 Consider:
1957 (set (reg:DI 101) (reg:DI 100))
1958 (set (subreg:SI (reg:DI 101) 0) <foo>)
1960 This is NOT equivalent to:
1962 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1963 (set (reg:DI 101) (reg:DI 100))])
1965 Not only does this modify 100 (in which case it might still be valid
1966 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1968 We can also run into a problem if I2 sets a register that I1
1969 uses and I1 gets directly substituted into I3 (not via I2). In that
1970 case, we would be getting the wrong value of I2DEST into I3, so we
1971 must reject the combination. This case occurs when I2 and I1 both
1972 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1973 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1974 of a SET must prevent combination from occurring. The same situation
1975 can occur for I0, in which case I0_NOT_IN_SRC is set.
1977 Before doing the above check, we first try to expand a field assignment
1978 into a set of logical operations.
1980 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1981 we place a register that is both set and used within I3. If more than one
1982 such register is detected, we fail.
1984 Return 1 if the combination is valid, zero otherwise. */
1986 static int
1989 {
1993 {
1998 rtx subdest;
2005 /* Check for the case where I3 modifies its output, as discussed
2006 above. We don't want to prevent pseudos from being combined
2007 into the address of a MEM, so only prevent the combination if
2008 i1 or i2 set the same MEM. */
2018 /* This is the same test done in can_combine_p except we can't test
2019 all_adjacent; we don't have to, since this instruction will stay
2020 in place, thus we are not considering increasing the lifetime of
2021 INNER_DEST.
2023 Also, if this insn sets a function argument, combining it with
2024 something that might need a spill could clobber a previous
2025 function argument; the all_adjacent test in can_combine_p also
2026 checks this; here, we do a more specific test for this case. */
2036 /* If DEST is used in I3, it is being killed in this insn, so
2037 record that for later. We have to consider paradoxical
2038 subregs here, since they kill the whole register, but we
2039 ignore partial subregs, STRICT_LOW_PART, etc.
2040 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2041 STACK_POINTER_REGNUM, since these are always considered to be
2042 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2052 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2054 #endif
2055 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2058 #endif
2060 {
2065 }
2066 }
2069 {
2076 }
2079 }
2080 \f
2081 /* Return 1 if X is an arithmetic expression that contains a multiplication
2082 and division. We don't count multiplications by powers of two here. */
2084 static int
2086 {
2088 {
2104 }
2105 }
2106 \f
2107 /* Determine whether INSN can be used in a combination. Return nonzero if
2108 not. This is used in try_combine to detect early some cases where we
2109 can't perform combinations. */
2111 static int
2113 {
2114 rtx set;
2117 /* If this isn't really an insn, we can't do anything.
2118 This can occur when flow deletes an insn that it has merged into an
2119 auto-increment address. */
2123 /* Never combine loads and stores involving hard regs that are likely
2124 to be spilled. The register allocator can usually handle such
2125 reg-reg moves by tying. If we allow the combiner to make
2126 substitutions of likely-spilled regs, reload might die.
2127 As an exception, we allow combinations involving fixed regs; these are
2128 not available to the register allocator so there's no risk involved. */
2149 }
2151 struct likely_spilled_retval_info
2152 {
2155 };
2157 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2158 hard registers that are known to be written to / clobbered in full. */
2159 static void
2161 {
2178 else
2181 }
2183 /* Return nonzero iff part of the return value is live during INSN, and
2184 it is likely spilled. This can happen when more than one insn is needed
2185 to copy the return value, e.g. when we consider to combine into the
2186 second copy insn for a complex value. */
2188 static int
2190 {
2194 /* We assume here that no machine mode needs more than
2195 32 hard registers when the value overlaps with a register
2196 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2211 /* Disregard parts of the return value that are set later. */
2220 /* Check if any of the (probably) live return value registers is
2221 likely spilled. */
2222 nregs --;
2223 do
2224 {
2230 }
2232 /* Adjust INSN after we made a change to its destination.
2234 Changing the destination can invalidate notes that say something about
2235 the results of the insn and a LOG_LINK pointing to the insn. */
2237 static void
2239 {
2240 /* For notes, be conservative and simply remove them. */
2243 /* The new insn will have a destination that was previously the destination
2244 of an insn just above it. Call distribute_links to make a LOG_LINK from
2245 the next use of that destination. */
2249 }
2251 /* Return TRUE if combine can reuse reg X in mode MODE.
2252 ADDED_SETS is nonzero if the original set is still required. */
2253 static bool
2255 {
2262 /* Allow hard registers if the new mode is legal, and occupies no more
2263 registers than the old mode. */
2269 /* Or a pseudo that is only used once. */
2272 }
2275 /* Check whether X, the destination of a set, refers to part of
2276 the register specified by REG. */
2278 static bool
2280 {
2281 /* Check that reg is an integer mode register. */
2292 }
2294 #ifdef AUTO_INC_DEC
2295 /* Replace auto-increment addressing modes with explicit operations to
2296 access the same addresses without modifying the corresponding
2297 registers. If AFTER holds, SRC is meant to be reused after the
2298 side effect, otherwise it is to be reused before that. */
2300 static rtx
2302 {
2309 {
2320 /* SCRATCH must be shared because they represent distinct values. */
2343 else
2355 else
2361 }
2363 /* Copy the various flags, fields, and other information. We assume
2364 that all fields need copying, and then clear the fields that should
2365 not be copied. That is the sensible default behavior, and forces
2366 us to explicitly document why we are *not* copying a flag. */
2369 /* We do not copy the USED flag, which is used as a mark bit during
2370 walks over the RTL. */
2373 /* We do not copy FRAME_RELATED for INSNs. */
2382 {
2388 }
2391 }
2392 #endif
2394 /* Auxiliary data structure for propagate_for_debug_stmt. */
2396 struct rtx_subst_pair
2397 {
2398 rtx to;
2401 };
2403 /* DATA points to an rtx_subst_pair. Return the value that should be
2404 substituted. */
2406 static rtx
2408 {
2414 {
2416 #ifdef AUTO_INC_DEC
2418 #else
2420 #endif
2423 }
2425 }
2427 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2428 and LAST. If MOVE holds, debug insns must also be moved past
2429 LAST. */
2431 static void
2433 {
2443 {
2447 {
2454 {
2458 }
2459 else
2461 }
2462 }
2463 }
2465 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2466 Note that the INSN should be deleted *after* removing dead edges, so
2467 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2468 but not for a (set (pc) (label_ref FOO)). */
2470 static void
2472 {
2482 }
2484 /* Try to combine the insns I0, I1 and I2 into I3.
2485 Here I0, I1 and I2 appear earlier than I3.
2486 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2487 I3.
2489 If we are combining more than two insns and the resulting insn is not
2490 recognized, try splitting it into two insns. If that happens, I2 and I3
2491 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2492 Otherwise, I0, I1 and I2 are pseudo-deleted.
2494 Return 0 if the combination does not work. Then nothing is changed.
2495 If we did the combination, return the insn at which combine should
2496 resume scanning.
2498 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2499 new direct jump instruction. */
2501 static rtx
2503 {
2504 /* New patterns for I3 and I2, respectively. */
2508 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2509 dead. */
2511 /* Total number of SETs to put into I3. */
2513 /* Nonzero if I2's or I1's body now appears in I3. */
2515 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2517 /* Contains I3 if the destination of I3 is used in its source, which means
2518 that the old life of I3 is being killed. If that usage is placed into
2519 I2 and not in I3, a REG_DEAD note must be made. */
2521 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2523 /* Set if I2DEST was reused as a scratch register. */
2525 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2532 /* Notes that must be added to REG_NOTES in I3 and I2. */
2534 /* Notes that we substituted I3 into I2 instead of the normal case. */
2536 /* Notes that I1, I2 or I3 is a MULT operation. */
2542 rtx temp;
2543 rtx link;
2545 rtx new_other_notes;
2548 /* Only try four-insn combinations when there's high likelihood of
2549 success. Look for simple insns, such as loads of constants or
2550 binary operations involving a constant. */
2552 {
2561 {
2564 rtx src;
2569 {
2572 }
2574 ngood++;
2577 nshift++;
2578 }
2581 }
2583 /* Exit early if one of the insns involved can't be used for
2584 combinations. */
2592 combine_attempts++;
2595 /* Reset the hard register usage information. */
2599 {
2606 else
2609 }
2611 /* If multiple insns feed into one of I2 or I3, they can be in any
2612 order. To simplify the code below, reorder them in sequence. */
2622 /* First check for one important special-case that the code below will
2623 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2624 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2625 we may be able to replace that destination with the destination of I3.
2626 This occurs in the common code where we compute both a quotient and
2627 remainder into a structure, in which case we want to do the computation
2628 directly into the structure to avoid register-register copies.
2630 Note that this case handles both multiple sets in I2 and also
2631 cases where I2 has a number of CLOBBER or PARALLELs.
2633 We make very conservative checks below and only try to handle the
2634 most common cases of this. For example, we only handle the case
2635 where I2 and I3 are adjacent to avoid making difficult register
2636 usage tests. */
2644 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2645 below would need to check what is inside (and reg_overlap_mentioned_p
2646 doesn't support those codes anyway). Don't allow those destinations;
2647 the resulting insn isn't likely to be recognized anyway. */
2653 {
2656 /* Make sure that the destination of I3,
2657 which we are going to substitute into one output of I2,
2658 is not used within another output of I2. We must avoid making this:
2659 (parallel [(set (mem (reg 69)) ...)
2660 (set (reg 69) ...)])
2661 which is not well-defined as to order of actions.
2662 (Besides, reload can't handle output reloads for this.)
2664 The problem can also happen if the dest of I3 is a memory ref,
2665 if another dest in I2 is an indirect memory ref. */
2678 {
2679 combine_merges++;
2689 /* Replace the dest in I2 with our dest and make the resulting
2690 insn the new pattern for I3. Then skip to where we
2691 validate the pattern. Everything was set up above. */
2698 }
2699 }
2701 /* If I2 is setting a pseudo to a constant and I3 is setting some
2702 sub-part of it to another constant, merge them by making a new
2703 constant. */
2712 {
2718 {
2721 {
2727 }
2728 }
2729 else
2730 {
2735 }
2738 {
2739 /* If this is the low part, we're done. */
2741 ;
2742 /* Handle the case where inner is twice the size of outer. */
2746 /* Otherwise give up for now. */
2747 else
2749 }
2754 {
2768 combine_merges++;
2775 /* Replace the source in I2 with the new constant and make the
2776 resulting insn the new pattern for I3. Then skip to where we
2777 validate the pattern. Everything was set up above. */
2783 /* The dest of I3 has been replaced with the dest of I2. */
2786 }
2787 }
2789 #ifndef HAVE_cc0
2790 /* If we have no I1 and I2 looks like:
2791 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2792 (set Y OP)])
2793 make up a dummy I1 that is
2794 (set Y OP)
2795 and change I2 to be
2796 (set (reg:CC X) (compare:CC Y (const_int 0)))
2798 (We can ignore any trailing CLOBBERs.)
2800 This undoes a previous combination and allows us to match a branch-and-
2801 decrement insn. */
2814 {
2820 {
2821 /* We make I1 with the same INSN_UID as I2. This gives it
2822 the same DF_INSN_LUID for value tracking. Our fake I1 will
2823 never appear in the insn stream so giving it the same INSN_UID
2824 as I2 will not cause a problem. */
2833 }
2834 }
2835 #endif
2837 /* Verify that I2 and I1 are valid for combining. */
2843 {
2846 }
2848 /* Record whether I2DEST is used in I2SRC and similarly for the other
2849 cases. Knowing this will help in register status updating below. */
2860 /* For the earlier insns, determine which of the subsequent ones they
2861 feed. */
2868 /* Ensure that I3's pattern can be the destination of combines. */
2874 {
2877 }
2879 /* See if any of the insns is a MULT operation. Unless one is, we will
2880 reject a combination that is, since it must be slower. Be conservative
2881 here. */
2889 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2890 We used to do this EXCEPT in one case: I3 has a post-inc in an
2891 output operand. However, that exception can give rise to insns like
2892 mov r3,(r3)+
2893 which is a famous insn on the PDP-11 where the value of r3 used as the
2894 source was model-dependent. Avoid this sort of thing. */
2896 #if 0
2902 /* It's not the exception. */
2903 #endif
2904 #ifdef AUTO_INC_DEC
2910 {
2913 }
2914 #endif
2916 /* See if the SETs in I1 or I2 need to be kept around in the merged
2917 instruction: whenever the value set there is still needed past I3.
2918 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2920 For the SET in I1, we have two cases: If I1 and I2 independently
2921 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2922 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2923 in I1 needs to be kept around unless I1DEST dies or is set in either
2924 I2 or I3. The same consideration applies to I0. */
2931 else
2938 else
2941 /* If the set in I2 needs to be kept around, we must make a copy of
2942 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2943 PATTERN (I2), we are only substituting for the original I1DEST, not into
2944 an already-substituted copy. This also prevents making self-referential
2945 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2946 I2DEST. */
2949 {
2952 else
2954 }
2957 {
2960 else
2962 }
2965 {
2968 else
2970 }
2972 combine_merges++;
2974 /* Substitute in the latest insn for the regs set by the earlier ones. */
2980 #ifndef HAVE_cc0
2981 /* Many machines that don't use CC0 have insns that can both perform an
2982 arithmetic operation and set the condition code. These operations will
2983 be represented as a PARALLEL with the first element of the vector
2984 being a COMPARE of an arithmetic operation with the constant zero.
2985 The second element of the vector will set some pseudo to the result
2986 of the same arithmetic operation. If we simplify the COMPARE, we won't
2987 match such a pattern and so will generate an extra insn. Here we test
2988 for this case, where both the comparison and the operation result are
2989 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2990 I2SRC. Later we will make the PARALLEL that contains I2. */
2996 {
2997 #ifdef SELECT_CC_MODE
3000 #endif
3007 #ifdef SELECT_CC_MODE
3008 /* See if a COMPARE with the operand we substituted in should be done
3009 with the mode that is currently being used. If not, do the same
3010 processing we do in `subst' for a SET; namely, if the destination
3011 is used only once, try to replace it with a register of the proper
3012 mode and also replace the COMPARE. */
3019 {
3021 compare_mode))
3022 {
3024 rtx new_dest;
3028 else
3029 {
3032 }
3038 }
3039 else
3041 }
3042 #endif
3043 }
3044 else
3045 #endif
3046 {
3047 /* It is possible that the source of I2 or I1 may be performing
3048 an unneeded operation, such as a ZERO_EXTEND of something
3049 that is known to have the high part zero. Handle that case
3050 by letting subst look at the innermost one of them.
3052 Another way to do this would be to have a function that tries
3053 to simplify a single insn instead of merging two or more
3054 insns. We don't do this because of the potential of infinite
3055 loops and because of the potential extra memory required.
3056 However, doing it the way we are is a bit of a kludge and
3057 doesn't catch all cases.
3059 But only do this if -fexpensive-optimizations since it slows
3060 things down and doesn't usually win.
3062 This is not done in the COMPARE case above because the
3063 unmodified I2PAT is used in the PARALLEL and so a pattern
3064 with a modified I2SRC would not match. */
3067 {
3068 /* Pass pc_rtx so no substitutions are done, just
3069 simplifications. */
3071 {
3074 }
3075 else
3076 {
3079 }
3080 }
3084 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a
3085 unique copy of I2SRC each time we substitute it to avoid
3086 self-referential rtl. */
3094 /* Record whether i2's body now appears within i3's body. */
3096 }
3098 /* If we already got a failure, don't try to do more. Otherwise,
3099 try to substitute in I1 if we have it. */
3102 {
3103 /* Check that an autoincrement side-effect on I1 has not been lost.
3104 This happens if I1DEST is mentioned in I2 and dies there, and
3105 has disappeared from the new pattern. */
3107 && i1_feeds_i2_n
3110 /* Before we can do this substitution, we must redo the test done
3111 above (see detailed comments there) that ensures that I1DEST
3112 isn't mentioned in any SETs in NEWPAT that are field assignments. */
3115 {
3118 }
3126 }
3128 {
3135 {
3138 }
3145 }
3147 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3148 to count all the ways that I2SRC and I1SRC can be used. */
3159 /* Fail if we tried to make a new register. */
3161 /* Fail if we couldn't do something and have a CLOBBER. */
3163 /* Fail if this new pattern is a MULT and we didn't have one before
3164 at the outer level. */
3167 {
3170 }
3172 /* If the actions of the earlier insns must be kept
3173 in addition to substituting them into the latest one,
3174 we must make a new PARALLEL for the latest insn
3175 to hold additional the SETs. */
3178 {
3180 combine_extras++;
3183 {
3189 }
3190 else
3191 {
3196 }
3202 {
3208 }
3210 {
3218 }
3219 }
3221 validate_replacement:
3223 /* Note which hard regs this insn has as inputs. */
3226 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3227 consider splitting this pattern, we might need these clobbers. */
3230 {
3236 }
3238 /* Is the result of combination a valid instruction? */
3241 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242 the second SET's destination is a register that is unused and isn't
3243 marked as an instruction that might trap in an EH region. In that case,
3244 we just need the first SET. This can occur when simplifying a divmod
3245 insn. We *must* test for this case here because the code below that
3246 splits two independent SETs doesn't handle this case correctly when it
3247 updates the register status.
3249 It's pointless doing this if we originally had two sets, one from
3250 i3, and one from i2. Combining then splitting the parallel results
3251 in the original i2 again plus an invalid insn (which we delete).
3252 The net effect is only to move instructions around, which makes
3253 debug info less accurate.
3255 Also check the case where the first SET's destination is unused.
3256 That would not cause incorrect code, but does cause an unneeded
3257 insn to remain. */
3266 {
3276 {
3279 }
3288 {
3294 }
3295 }
3297 /* If we were combining three insns and the result is a simple SET
3298 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299 insns. There are two ways to do this. It can be split using a
3300 machine-specific method (like when you have an addition of a large
3301 constant) or by combine in the function find_split_point. */
3305 {
3308 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3309 use I2DEST as a scratch register will help. In the latter case,
3310 convert I2DEST to the mode of the source of NEWPAT if we can. */
3314 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315 inputs of NEWPAT. */
3317 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318 possible to try that as a scratch reg. This would require adding
3319 more code to make it work though. */
3322 {
3325 /* First try to split using the original register as a
3326 scratch register. */
3330 i2dest)));
3333 /* If that didn't work, try changing the mode of I2DEST if
3334 we can. */
3339 {
3341 rtx ni2dest;
3345 else
3346 {
3349 }
3351 parallel = (gen_rtx_PARALLEL
3355 ni2dest))));
3360 {
3368 }
3369 }
3372 }
3374 /* If recog_for_combine has discarded clobbers, try to use them
3375 again for the split. */
3377 {
3380 }
3383 {
3388 }
3392 {
3402 /* If I2 or I3 has multiple SETs, we won't know how to track
3403 register status, so don't use these insns. If I2's destination
3404 is used between I2 and I3, we also can't use these insns. */
3414 /* It is possible that both insns now set the destination of I3.
3415 If so, we must show an extra use of it. */
3418 {
3436 }
3437 }
3439 /* If we can split it and use I2DEST, go ahead and see if that
3440 helps things be recognized. Verify that none of the registers
3441 are set between I2 and I3. */
3444 #ifdef HAVE_cc0
3446 #endif
3447 /* We need I2DEST in the proper mode. If it is a hard register
3448 or the only use of a pseudo, we can change its mode.
3449 Make sure we don't change a hard register to have a mode that
3450 isn't valid for it, or change the number of registers. */
3457 /* We can't overwrite I2DEST if its value is still used by
3458 NEWPAT. */
3460 {
3469 /* *SPLIT may be part of I2SRC, so make sure we have the
3470 original expression around for later debug processing.
3471 We should not need I2SRC any more in other cases. */
3474 else
3477 /* Get NEWDEST as a register in the proper mode. We have already
3478 validated that we can do this. */
3480 {
3483 else
3484 {
3487 }
3488 }
3490 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491 an ASHIFT. This can occur if it was inside a PLUS and hence
3492 appeared to be a memory address. This is a kludge. */
3497 {
3500 /* Update split_code because we may not have a multiply
3501 anymore. */
3503 }
3505 #ifdef INSN_SCHEDULING
3506 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507 be written as a ZERO_EXTEND. */
3509 {
3510 #ifdef LOAD_EXTEND_OP
3511 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512 what it really is. */
3517 else
3518 #endif
3521 }
3522 #endif
3524 /* Attempt to split binary operators using arithmetic identities. */
3528 {
3535 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3537 {
3542 }
3543 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3550 {
3556 /* Split both "((X op Y) op X) op Y" and
3557 "((X op Y) op Y) op X" as "T op T" where T is
3558 "X op Y". */
3561 {
3567 }
3568 /* Split "((X op X) op Y) op Y)" as "T op T" where
3569 T is "X op Y". */
3571 {
3577 }
3578 }
3579 }
3582 {
3585 }
3589 /* recog_for_combine might have added CLOBBERs to newi2pat.
3590 Make sure NEWPAT does not depend on the clobbered regs. */
3594 {
3597 {
3600 }
3601 }
3603 /* If the split point was a MULT and we didn't have one before,
3604 don't use one now. */
3607 }
3608 }
3610 /* Check for a case where we loaded from memory in a narrow mode and
3611 then sign extended it, but we need both registers. In that case,
3612 we have a PARALLEL with both loads from the same memory location.
3613 We can split this into a load from memory followed by a register-register
3614 copy. This saves at least one insn, more if register allocation can
3615 eliminate the copy.
3617 We cannot do this if the destination of the first assignment is a
3618 condition code register or cc0. We eliminate this case by making sure
3619 the SET_DEST and SET_SRC have the same mode.
3621 We cannot do this if the destination of the second assignment is
3622 a register that we have already assumed is zero-extended. Similarly
3623 for a SUBREG of such a register. */
3662 {
3663 rtx ni2dest;
3677 }
3679 /* Similarly, check for a case where we have a PARALLEL of two independent
3680 SETs but we started with three insns. In this case, we can do the sets
3681 as two separate insns. This case occurs when some SET allows two
3682 other insns to combine, but the destination of that SET is still live. */
3701 #ifdef HAVE_cc0
3702 /* We cannot split the parallel into two sets if both sets
3703 reference cc0. */
3706 #endif
3707 )
3708 {
3709 /* Normally, it doesn't matter which of the two is done first,
3710 but it does if one references cc0. In that case, it has to
3711 be first. */
3712 #ifdef HAVE_cc0
3714 {
3717 }
3718 else
3719 #endif
3720 {
3723 }
3728 {
3729 /* recog_for_combine might have added CLOBBERs to newi2pat.
3730 Make sure NEWPAT does not depend on the clobbered regs. */
3732 {
3735 {
3739 }
3742 {
3743 /* CLOBBERs on newi2pat prevent it going first.
3744 Try the other order of the insns if possible. */
3748 #ifdef HAVE_cc0
3750 {
3753 }
3754 #endif
3759 {
3762 }
3767 {
3770 {
3773 }
3774 }
3775 }
3776 }
3779 }
3780 }
3782 /* If it still isn't recognized, fail and change things back the way they
3783 were. */
3785 /* Is the result a reasonable ASM_OPERANDS? */
3787 {
3790 }
3792 /* If we had to change another insn, make sure it is valid also. */
3794 {
3802 {
3805 }
3806 }
3808 #ifdef HAVE_cc0
3809 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3810 they are adjacent to each other or not. */
3811 {
3815 {
3818 }
3819 }
3820 #endif
3822 /* Only allow this combination if insn_rtx_costs reports that the
3823 replacement instructions are cheaper than the originals. */
3825 {
3828 }
3831 {
3836 {
3841 /* Temporarily revert mode back. */
3845 {
3846 /* If we used i2dest as a scratch register with a
3847 different mode, substitute it for the original
3848 i2src while its original mode is temporarily
3849 restored, and then clear i2scratch so that we don't
3850 do it again later. */
3853 /* Put back the new mode. */
3855 }
3856 else
3857 {
3862 {
3865 }
3866 else
3867 {
3871 }
3873 /* We're dealing with a reg that changed mode but not
3874 meaning, so we want to turn it into a subreg for
3875 the new mode. However, because of REG sharing and
3876 because its mode had already changed, we have to do
3877 it in two steps. First, replace any debug uses of
3878 reg, with its original mode temporarily restored,
3879 with this copy we have created; then, replace the
3880 copy with the SUBREG of the original shared reg,
3881 once again changed to the new mode. */
3887 }
3888 }
3889 }
3891 /* If we will be able to accept this, we have made a
3892 change to the destination of I3. This requires us to
3893 do a few adjustments. */
3896 {
3899 }
3901 /* We now know that we can do this combination. Merge the insns and
3902 update the status of registers and LOG_LINKS. */
3905 {
3910 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3911 are still valid. Then add any non-duplicate notes added by
3912 recog_for_combine. */
3914 {
3920 }
3924 NULL_RTX);
3925 }
3928 {
3929 rtx insn;
3930 rtx link;
3931 rtx ni2dest;
3933 /* I3 now uses what used to be its destination and which is now
3934 I2's destination. This requires us to do a few adjustments. */
3938 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3939 so we still will.
3941 However, some later insn might be using I2's dest and have
3942 a LOG_LINK pointing at I3. We must remove this link.
3943 The simplest way to remove the link is to point it at I1,
3944 which we know will be a NOTE. */
3946 /* newi2pat is usually a SET here; however, recog_for_combine might
3947 have added some clobbers. */
3950 else
3957 {
3959 {
3966 }
3967 }
3968 }
3970 {
3976 /* Compute which registers we expect to eliminate. newi2pat may be setting
3977 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3978 same as i3dest, in which case newi2pat may be setting i1dest. */
3981 || !i2dest_killed
3985 || !i1dest_killed
3989 || !i0dest_killed
3992 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3993 clear them. */
4001 /* Ensure that we do not have something that should not be shared but
4002 occurs multiple times in the new insns. Check this by first
4003 resetting all the `used' flags and then copying anything is shared. */
4027 {
4034 {
4035 /* I2SRC must still be meaningful at this point. Some splitting
4036 operations can invalidate I2SRC, but those operations do not
4037 apply to calls. */
4040 }
4048 }
4053 /* We had one special case above where I2 had more than one set and
4054 we replaced a destination of one of those sets with the destination
4055 of I3. In that case, we have to update LOG_LINKS of insns later
4056 in this basic block. Note that this (expensive) case is rare.
4058 Also, in this case, we must pretend that all REG_NOTEs for I2
4059 actually came from I3, so that REG_UNUSED notes from I2 will be
4060 properly handled. */
4063 {
4081 {
4086 }
4087 else
4090 }
4098 {
4103 }
4104 else
4105 {
4109 }
4112 {
4118 }
4121 {
4127 }
4129 /* Get death notes for everything that is now used in either I3 or
4130 I2 and used to die in a previous insn. If we built two new
4131 patterns, move from I1 to I2 then I2 to I3 so that we get the
4132 proper movement on registers that I2 modifies. */
4138 else
4144 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4161 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4162 know these are REG_UNUSED and want them to go to the desired insn,
4163 so we always pass it as i3. */
4167 NULL_RTX);
4171 NULL_RTX);
4173 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4174 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4175 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4176 in that case, it might delete I2. Similarly for I2 and I1.
4177 Show an additional death due to the REG_DEAD note we make here. If
4178 we discard it in distribute_notes, we will decrement it again. */
4181 {
4184 NULL_RTX),
4186 else
4188 NULL_RTX),
4191 }
4194 {
4199 else
4202 }
4205 {
4210 else
4213 }
4216 {
4221 else
4224 }
4232 {
4233 rtx link;
4236 /* The insn that used to set this register doesn't exist, and
4237 this life of the register may not exist either. See if one of
4238 I3's links points to an insn that sets I2DEST. If it does,
4239 that is now the last known value for I2DEST. If we don't update
4240 this and I2 set the register to a value that depended on its old
4241 contents, we will get confused. If this insn is used, thing
4242 will be set correctly in combine_instructions. */
4251 /* If the reg formerly set in I2 died only once and that was in I3,
4252 zero its use count so it won't make `reload' do any work. */
4256 {
4259 }
4260 }
4263 {
4264 rtx link;
4277 }
4280 {
4281 rtx link;
4294 }
4296 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4297 been made to this insn. The order of
4298 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4299 can affect nonzero_bits of newpat */
4303 }
4306 {
4308 {
4311 }
4313 }
4316 {
4318 {
4321 }
4323 }
4326 {
4328 {
4331 }
4333 }
4336 {
4338 {
4341 }
4343 }
4346 {
4348 {
4351 }
4353 }
4355 /* Set new_direct_jump_p if a new return or simple jump instruction
4356 has been created. Adjust the CFG accordingly. */
4359 {
4363 }
4368 {
4371 }
4373 /* A noop might also need cleaning up of CFG, if it comes from the
4374 simplification of a jump. */
4378 {
4381 }
4383 combine_successes++;
4390 else
4392 }
4393 \f
4394 /* Undo all the modifications recorded in undobuf. */
4396 static void
4398 {
4402 {
4405 {
4417 }
4421 }
4424 }
4426 /* We've committed to accepting the changes we made. Move all
4427 of the undos to the free list. */
4429 static void
4431 {
4435 {
4439 }
4441 }
4442 \f
4443 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4444 where we have an arithmetic expression and return that point. LOC will
4445 be inside INSN.
4447 try_combine will call this function to see if an insn can be split into
4448 two insns. */
4452 {
4461 /* First special-case some codes. */
4463 {
4465 #ifdef INSN_SCHEDULING
4466 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4467 point. */
4470 #endif
4474 #ifdef HAVE_lo_sum
4475 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4476 using LO_SUM and HIGH. */
4479 {
4480 enum machine_mode address_mode
4488 }
4489 #endif
4491 /* If we have a PLUS whose second operand is a constant and the
4492 address is not valid, perhaps will can split it up using
4493 the machine-specific way to split large constants. We use
4494 the first pseudo-reg (one of the virtual regs) as a placeholder;
4495 it will not remain in the result. */
4500 {
4504 subst_insn);
4506 /* This should have produced two insns, each of which sets our
4507 placeholder. If the source of the second is a valid address,
4508 we can make put both sources together and make a split point
4509 in the middle. */
4522 && memory_address_addr_space_p
4525 {
4529 /* Replace the placeholder in SRC2 with SRC1. If we can
4530 find where in SRC2 it was placed, that can become our
4531 split point and we can replace this address with SRC2.
4532 Just try two obvious places. */
4543 {
4546 }
4547 }
4549 /* If that didn't work, perhaps the first operand is complex and
4550 needs to be computed separately, so make a split point there.
4551 This will occur on machines that just support REG + CONST
4552 and have a constant moved through some previous computation. */
4558 }
4560 /* If we have a PLUS whose first operand is complex, try computing it
4561 separately by making a split there. */
4572 #ifdef HAVE_cc0
4573 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4574 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4575 we need to put the operand into a register. So split at that
4576 point. */
4585 #endif
4587 /* See if we can split SET_SRC as it stands. */
4592 /* See if we can split SET_DEST as it stands. */
4597 /* See if this is a bitfield assignment with everything constant. If
4598 so, this is an IOR of an AND, so split it into that. */
4609 {
4616 rtx or_mask;
4625 else
4626 {
4632 or_mask));
4633 }
4640 }
4642 /* Otherwise, see if this is an operation that we can split into two.
4643 If so, try to split that. */
4647 {
4649 /* If we are AND'ing with a large constant that is only a single
4650 bit and the result is only being used in a context where we
4651 need to know if it is zero or nonzero, replace it with a bit
4652 extraction. This will avoid the large constant, which might
4653 have taken more than one insn to make. If the constant were
4654 not a valid argument to the AND but took only one insn to make,
4655 this is no worse, but if it took more than one insn, it will
4656 be better. */
4666 {
4671 {
4674 }
4675 }
4679 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4680 is known to be on, this can be converted into a NEG of a shift. */
4686 {
4698 }
4704 /* We can't optimize if either mode is a partial integer
4705 mode as we don't know how many bits are significant
4706 in those modes. */
4720 {
4728 }
4733 }
4736 {
4739 /* For unsigned, we have a choice of a shift followed by an
4740 AND or two shifts. Use two shifts for field sizes where the
4741 constant might be too large. We assume here that we can
4742 always at least get 8-bit constants in an AND insn, which is
4743 true for every current RISC. */
4746 {
4749 gen_rtx_LSHIFTRT
4757 }
4758 else
4759 {
4761 gen_rtx_fmt_ee
4772 }
4773 }
4775 /* See if this is a simple operation with a constant as the second
4776 operand. It might be that this constant is out of range and hence
4777 could be used as a split point. */
4785 /* Finally, see if this is a simple operation with its first operand
4786 not in a register. The operation might require this operand in a
4787 register, so return it as a split point. We can always do this
4788 because if the first operand were another operation, we would have
4789 already found it as a split point. */
4798 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4799 it is better to write this as (not (ior A B)) so we can split it.
4800 Similarly for IOR. */
4802 {
4810 }
4812 /* Many RISC machines have a large set of logical insns. If the
4813 second operand is a NOT, put it first so we will try to split the
4814 other operand first. */
4816 {
4820 }
4825 /* Canonicalization can produce (minus A (mult B C)), where C is a
4826 constant. It may be better to try splitting (plus (mult B -C) A)
4827 instead if this isn't a multiply by a power of two. */
4831 {
4840 }
4842 /* Split at a multiply-accumulate instruction. However if this is
4843 the SET_SRC, we likely do not have such an instruction and it's
4844 worthless to try this split. */
4850 }
4852 /* Otherwise, select our actions depending on our rtx class. */
4854 {
4860 /* ... fall through ... */
4868 /* ... fall through ... */
4870 /* Some machines have (and (shift ...) ...) insns. If X is not
4871 an AND, but XEXP (X, 0) is, use it as our split point. */
4881 /* Otherwise, we don't have a split point. */
4883 }
4884 }
4885 \f
4886 /* Throughout X, replace FROM with TO, and return the result.
4887 The result is TO if X is FROM;
4888 otherwise the result is X, but its contents may have been modified.
4889 If they were modified, a record was made in undobuf so that
4890 undo_all will (among other things) return X to its original state.
4892 If the number of changes necessary is too much to record to undo,
4893 the excess changes are not made, so the result is invalid.
4894 The changes already made can still be undone.
4895 undobuf.num_undo is incremented for such changes, so by testing that
4896 the caller can tell whether the result is valid.
4898 `n_occurrences' is incremented each time FROM is replaced.
4900 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4902 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4903 by copying if `n_occurrences' is nonzero. */
4905 static rtx
4907 {
4912 rtx new_rtx;
4914 /* Two expressions are equal if they are identical copies of a shared
4915 RTX or if they are both registers with the same register number
4916 and mode. */
4918 #define COMBINE_RTX_EQUAL_P(X,Y) \
4919 ((X) == (Y) \
4920 || (REG_P (X) && REG_P (Y) \
4921 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4924 {
4925 n_occurrences++;
4927 }
4929 /* If X and FROM are the same register but different modes, they
4930 will not have been seen as equal above. However, the log links code
4931 will make a LOG_LINKS entry for that case. If we do nothing, we
4932 will try to rerecognize our original insn and, when it succeeds,
4933 we will delete the feeding insn, which is incorrect.
4935 So force this insn not to match in this (rare) case. */
4940 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4941 of which may contain things that can be combined. */
4945 /* It is possible to have a subexpression appear twice in the insn.
4946 Suppose that FROM is a register that appears within TO.
4947 Then, after that subexpression has been scanned once by `subst',
4948 the second time it is scanned, TO may be found. If we were
4949 to scan TO here, we would find FROM within it and create a
4950 self-referent rtl structure which is completely wrong. */
4954 /* Parallel asm_operands need special attention because all of the
4955 inputs are shared across the arms. Furthermore, unsharing the
4956 rtl results in recognition failures. Failure to handle this case
4957 specially can result in circular rtl.
4959 Solve this by doing a normal pass across the first entry of the
4960 parallel, and only processing the SET_DESTs of the subsequent
4961 entries. Ug. */
4966 {
4969 /* If this substitution failed, this whole thing fails. */
4977 {
4983 {
4986 /* If this substitution failed, this whole thing fails. */
4992 }
4993 }
4994 }
4995 else
4996 {
5000 /* We don't need to process a SET_DEST that is a register, CC0,
5001 or PC, so set up to skip this common case. All other cases
5002 where we want to suppress replacing something inside a
5003 SET_SRC are handled via the IN_DEST operand. */
5010 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5011 constant. */
5016 {
5018 {
5021 {
5023 {
5026 n_occurrences++;
5027 }
5028 else
5029 {
5031 unique_copy);
5033 /* If this substitution failed, this whole thing
5034 fails. */
5038 }
5041 }
5042 }
5044 {
5045 /* If this is a register being set, ignore it. */
5052 ;
5055 {
5056 /* In general, don't install a subreg involving two
5057 modes not tieable. It can worsen register
5058 allocation, and can even make invalid reload
5059 insns, since the reg inside may need to be copied
5060 from in the outside mode, and that may be invalid
5061 if it is an fp reg copied in integer mode.
5063 We allow two exceptions to this: It is valid if
5064 it is inside another SUBREG and the mode of that
5065 SUBREG and the mode of the inside of TO is
5066 tieable and it is valid if X is a SET that copies
5067 FROM to CC0. */
5075 #ifdef HAVE_cc0
5077 #endif
5078 )
5081 #ifdef CANNOT_CHANGE_MODE_CLASS
5089 #endif
5092 n_occurrences++;
5093 }
5094 else
5095 /* If we are in a SET_DEST, suppress most cases unless we
5096 have gone inside a MEM, in which case we want to
5097 simplify the address. We assume here that things that
5098 are actually part of the destination have their inner
5099 parts in the first expression. This is true for SUBREG,
5100 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5101 things aside from REG and MEM that should appear in a
5102 SET_DEST. */
5104 (((in_dest
5110 /* If we found that we will have to reject this combination,
5111 indicate that by returning the CLOBBER ourselves, rather than
5112 an expression containing it. This will speed things up as
5113 well as prevent accidents where two CLOBBERs are considered
5114 to be equal, thus producing an incorrect simplification. */
5122 {
5130 }
5133 {
5137 }
5138 else
5140 }
5141 }
5142 }
5144 /* Check if we are loading something from the constant pool via float
5145 extension; in this case we would undo compress_float_constant
5146 optimization and degenerate constant load to an immediate value. */
5150 {
5154 }
5156 /* Try to simplify X. If the simplification changed the code, it is likely
5157 that further simplification will help, so loop, but limit the number
5158 of repetitions that will be performed. */
5161 {
5162 /* If X is sufficiently simple, don't bother trying to do anything
5163 with it. */
5172 /* We no longer know the original mode of operand 0 since we
5173 have changed the form of X) */
5175 }
5178 }
5179 \f
5180 /* Simplify X, a piece of RTL. We just operate on the expression at the
5181 outer level; call `subst' to simplify recursively. Return the new
5182 expression.
5184 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5185 if we are inside a SET_DEST. */
5187 static rtx
5189 {
5192 rtx temp;
5195 /* If this is a commutative operation, put a constant last and a complex
5196 expression first. We don't need to do this for comparisons here. */
5199 {
5203 }
5205 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5206 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5207 things. Check for cases where both arms are testing the same
5208 condition.
5210 Don't do anything if all operands are very simple. */
5223 {
5228 /* If everything is a comparison, what we have is highly unlikely
5229 to be simpler, so don't use it. */
5232 {
5239 /* Simplify the alternative arms; this may collapse the true and
5240 false arms to store-flag values. Be careful to use copy_rtx
5241 here since true_rtx or false_rtx might share RTL with x as a
5242 result of the if_then_else_cond call above. */
5246 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5247 is unlikely to be simpler. */
5250 {
5253 /* Restarting if we generate a store-flag expression will cause
5254 us to loop. Just drop through in this case. */
5256 /* If the result values are STORE_FLAG_VALUE and zero, we can
5257 just make the comparison operation. */
5268 /* Likewise, we can make the negate of a comparison operation
5269 if the result values are - STORE_FLAG_VALUE and zero. */
5277 mode);
5288 mode);
5289 else
5292 mode,
5293 VOIDmode,
5294 cond,
5295 cop1),
5300 }
5301 }
5302 }
5304 /* Try to fold this expression in case we have constants that weren't
5305 present before. */
5308 {
5316 {
5319 {
5323 }
5326 }
5339 }
5342 {
5347 }
5349 /* First see if we can apply the inverse distributive law. */
5352 {
5356 }
5358 /* If CODE is an associative operation not otherwise handled, see if we
5359 can associate some operands. This can win if they are constants or
5360 if they are logically related (i.e. (a & b) & a). */
5366 {
5368 {
5372 rtx inner;
5374 /* Make sure we pass the constant operand if any as the second
5375 one if this is a commutative operation. */
5377 {
5381 }
5387 /* For commutative operations, try the other pair if that one
5388 didn't simplify. */
5390 {
5395 }
5399 }
5400 }
5402 /* A little bit of algebraic simplification here. */
5404 {
5406 /* Ensure that our address has any ASHIFTs converted to MULT in case
5407 address-recognizing predicates are called later. */
5416 /* See if this can be moved to simplify_subreg. */
5419 /* Don't call gen_lowpart if the inner mode
5420 is VOIDmode and we cannot simplify it, as SUBREG without
5421 inner mode is invalid. */
5428 {
5429 rtx temp;
5434 }
5436 /* Don't change the mode of the MEM if that would change the meaning
5437 of the address. */
5443 /* Note that we cannot do any narrowing for non-constants since
5444 we might have been counting on using the fact that some bits were
5445 zero. We now do this in the SET. */
5452 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5453 replaced by (lshiftrt X C). This will convert
5454 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5462 /* If X has only a single bit that might be nonzero, say, bit I, convert
5463 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5464 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5465 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5466 or a SUBREG of one since we'd be making the expression more
5467 complex if it was just a register. */
5473 {
5474 rtx temp1 = simplify_shift_const
5480 /* If all we did was surround TEMP with the two shifts, we
5481 haven't improved anything, so don't use it. Otherwise,
5482 we are better off with TEMP1. */
5487 }
5491 /* We can't handle truncation to a partial integer mode here
5492 because we don't know the real bitsize of the partial
5493 integer mode. */
5502 /* We can truncate a constant value and return it. */
5506 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5507 whose value is a comparison can be replaced with a subreg if
5508 STORE_FLAG_VALUE permits. */
5517 /* (const (const X)) can become (const X). Do it this way rather than
5518 returning the inner CONST since CONST can be shared with a
5519 REG_EQUAL note. */
5524 #ifdef HAVE_lo_sum
5526 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5527 can add in an offset. find_split_point will split this address up
5528 again if it doesn't match. */
5533 #endif
5536 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5537 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5538 bit-field and can be replaced by either a sign_extend or a
5539 sign_extract. The `and' may be a zero_extend and the two
5540 <c>, -<c> constants may be reversed. */
5555 return simplify_shift_const
5562 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5563 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5564 the bitsize of the mode - 1. This allows simplification of
5565 "a = (b & 8) == 0;" */
5577 /* If we are adding two things that have no bits in common, convert
5578 the addition into an IOR. This will often be further simplified,
5579 for example in cases like ((a & 1) + (a & 2)), which can
5580 become a & 3. */
5585 {
5586 /* Try to simplify the expression further. */
5590 /* If we could, great. If not, do not go ahead with the IOR
5591 replacement, since PLUS appears in many special purpose
5592 address arithmetic instructions. */
5595 }
5599 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5600 (and <foo> (const_int pow2-1)) */
5610 /* If we have (mult (plus A B) C), apply the distributive law and then
5611 the inverse distributive law to see if things simplify. This
5612 occurs mostly in addresses, often when unrolling loops. */
5615 {
5619 }
5621 /* Try simplify a*(b/c) as (a*b)/c. */
5624 {
5630 }
5634 /* If this is a divide by a power of two, treat it as a shift if
5635 its first operand is a shift. */
5653 /* If the first operand is a condition code, we can't do anything
5654 with it. */
5658 {
5666 /* Simplify our comparison, if possible. */
5669 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5670 if only the low-order bit is possibly nonzero in X (such as when
5671 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5672 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5673 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5674 (plus X 1).
5676 Remove any ZERO_EXTRACT we made when thinking this was a
5677 comparison. It may now be simpler to use, e.g., an AND. If a
5678 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5679 the call to make_compound_operation in the SET case. */
5695 {
5699 mode);
5700 }
5707 {
5711 const1_rtx);
5712 }
5720 {
5723 }
5725 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5726 those above. */
5740 {
5744 mode);
5745 }
5753 {
5757 mode);
5758 }
5760 /* If X is 0/1, (eq X 0) is X-1. */
5766 {
5769 }
5771 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5772 one bit that might be nonzero, we can convert (ne x 0) to
5773 (ashift x c) where C puts the bit in the sign bit. Remove any
5774 AND with STORE_FLAG_VALUE when we are done, since we are only
5775 going to test the sign bit. */
5783 {
5789 else
5791 }
5793 /* If the code changed, return a whole new comparison. */
5797 /* Otherwise, keep this operation, but maybe change its operands.
5798 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5801 }
5811 /* If we are processing SET_DEST, we are done. */
5829 /* If this is a shift by a constant amount, simplify it. */
5845 }
5848 }
5849 \f
5850 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5852 static rtx
5854 {
5861 rtx temp;
5864 rtx reversed;
5866 /* Simplify storing of the truth value. */
5871 /* Also when the truth value has to be reversed. */
5877 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5878 in it is being compared against certain values. Get the true and false
5879 comparisons and see if that says anything about the value of each arm. */
5885 {
5886 HOST_WIDE_INT nzb;
5892 /* If FALSE_CODE is EQ, swap the codes and arms. */
5895 {
5898 }
5900 /* If we are comparing against zero and the expression being tested has
5901 only a single bit that might be nonzero, that is its value when it is
5902 not equal to zero. Similarly if it is known to be -1 or 0. */
5906 {
5909 }
5913 {
5916 }
5918 /* Now simplify an arm if we know the value of the register in the
5919 branch and it is used in the arm. Be careful due to the potential
5920 of locally-shared RTL. */
5937 }
5939 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5940 reversed, do so to avoid needing two sets of patterns for
5941 subtract-and-branch insns. Similarly if we have a constant in the true
5942 arm, the false arm is the same as the first operand of the comparison, or
5943 the false arm is more complicated than the true arm. */
5956 {
5965 /* It is possible that the conditional has been simplified out. */
5968 }
5970 /* If the two arms are identical, we don't need the comparison. */
5975 /* Convert a == b ? b : a to "a". */
5987 /* Look for cases where we have (abs x) or (neg (abs X)). */
5990 && comparison_p
5997 {
6003 return
6006 mode);
6009 }
6011 /* Look for MIN or MAX. */
6014 && comparison_p
6019 {
6034 }
6036 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6037 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6038 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6039 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6040 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6041 neither 1 or -1, but it isn't worth checking for. */
6044 && comparison_p
6047 {
6063 /* If an identity-zero op is commutative, check whether there
6064 would be a match if we swapped the operands. */
6084 {
6088 }
6100 {
6104 }
6120 {
6124 }
6136 {
6140 }
6143 {
6149 const_true_rtx));
6157 }
6158 }
6160 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6161 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6162 negation of a single bit, we can convert this operation to a shift. We
6163 can actually do this more generally, but it doesn't seem worth it. */
6172 return
6176 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6186 }
6187 \f
6188 /* Simplify X, a SET expression. Return the new expression. */
6190 static rtx
6192 {
6195 enum machine_mode mode
6197 rtx other_insn;
6200 /* (set (pc) (return)) gets written as (return). */
6204 /* Now that we know for sure which bits of SRC we are using, see if we can
6205 simplify the expression for the object knowing that we only need the
6206 low-order bits. */
6210 {
6213 }
6215 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6216 the comparison result and try to simplify it unless we already have used
6217 undobuf.other_insn. */
6225 {
6234 else
6242 {
6246 }
6247 else
6248 {
6253 /* Attempt to simplify CC user. */
6255 {
6259 }
6261 /* Convert X into a no-op move. */
6265 }
6267 /* Simplify our comparison, if possible. */
6270 #ifdef SELECT_CC_MODE
6271 /* If this machine has CC modes other than CCmode, check to see if we
6272 need to use a different CC mode here. */
6275 else
6278 #ifndef HAVE_cc0
6279 /* If the mode changed, we have to change SET_DEST, the mode in the
6280 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6281 a hard register, just build new versions with the proper mode. If it
6282 is a pseudo, we lose unless it is only time we set the pseudo, in
6283 which case we can safely change its mode. */
6285 {
6287 {
6289 rtx new_dest;
6293 else
6294 {
6297 }
6304 }
6305 }
6309 /* If the code changed, we have to build a new comparison in
6310 undobuf.other_insn. */
6312 {
6321 /* If the only change we made was to change an EQ into an NE or
6322 vice versa, OP0 has only one bit that might be nonzero, and OP1
6323 is zero, check if changing the user of the condition code will
6324 produce a valid insn. If it won't, we can keep the original code
6325 in that insn by surrounding our operation with an XOR. */
6332 {
6337 {
6343 }
6344 }
6345 }
6350 /* Otherwise, if we didn't previously have a COMPARE in the
6351 correct mode, we need one. */
6353 {
6356 }
6358 {
6361 }
6362 /* Otherwise, update the COMPARE if needed. */
6364 {
6367 }
6368 }
6369 else
6370 {
6371 /* Get SET_SRC in a form where we have placed back any
6372 compound expressions. Then do the checks below. */
6375 }
6377 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6378 and X being a REG or (subreg (reg)), we may be able to convert this to
6379 (set (subreg:m2 x) (op)).
6381 We can always do this if M1 is narrower than M2 because that means that
6382 we only care about the low bits of the result.
6384 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6385 perform a narrower operation than requested since the high-order bits will
6386 be undefined. On machine where it is defined, this transformation is safe
6387 as long as M1 and M2 have the same number of words. */
6395 #ifndef WORD_REGISTER_OPERATIONS
6398 #endif
6399 #ifdef CANNOT_CHANGE_MODE_CLASS
6404 #endif
6408 {
6411 dest));
6415 }
6417 #ifdef HAVE_cc0
6418 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6419 in SRC. */
6425 {
6429 /* Here we make sure that we don't have a sign bit on. */
6434 {
6437 }
6438 }
6439 #endif
6441 #ifdef LOAD_EXTEND_OP
6442 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6443 would require a paradoxical subreg. Replace the subreg with a
6444 zero_extend to avoid the reload that would otherwise be required. */
6453 {
6459 }
6460 #endif
6462 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6463 are comparing an item known to be 0 or -1 against 0, use a logical
6464 operation instead. Check for one of the arms being an IOR of the other
6465 arm with some value. We compute three terms to be IOR'ed together. In
6466 practice, at most two will be nonzero. Then we do the IOR's. */
6474 #ifdef HAVE_conditional_move
6476 #endif
6481 {
6507 false_rtx);
6513 term3));
6516 }
6518 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6519 whole thing fail. */
6524 else
6525 /* Convert this into a field assignment operation, if possible. */
6527 }
6528 \f
6529 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6530 result. */
6532 static rtx
6534 {
6540 {
6542 /* We can call simplify_and_const_int only if we don't lose
6543 any (sign) bits when converting INTVAL (op1) to
6544 "unsigned HOST_WIDE_INT". */
6548 {
6555 }
6557 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6558 apply the distributive law and then the inverse distributive
6559 law to see if things simplify. */
6561 {
6565 }
6567 {
6571 }
6575 /* If we have (ior (and A B) C), apply the distributive law and then
6576 the inverse distributive law to see if things simplify. */
6579 {
6583 }
6586 {
6590 }
6595 }
6598 }
6599 \f
6600 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6601 operations" because they can be replaced with two more basic operations.
6602 ZERO_EXTEND is also considered "compound" because it can be replaced with
6603 an AND operation, which is simpler, though only one operation.
6605 The function expand_compound_operation is called with an rtx expression
6606 and will convert it to the appropriate shifts and AND operations,
6607 simplifying at each stage.
6609 The function make_compound_operation is called to convert an expression
6610 consisting of shifts and ANDs into the equivalent compound expression.
6611 It is the inverse of this function, loosely speaking. */
6613 static rtx
6615 {
6619 rtx tem;
6622 {
6626 /* We can't necessarily use a const_int for a multiword mode;
6627 it depends on implicitly extending the value.
6628 Since we don't know the right way to extend it,
6629 we can't tell whether the implicit way is right.
6631 Even for a mode that is no wider than a const_int,
6632 we can't win, because we need to sign extend one of its bits through
6633 the rest of it, and we don't know which bit. */
6637 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6638 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6639 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6640 reloaded. If not for that, MEM's would very rarely be safe.
6642 Reject MODEs bigger than a word, because we might not be able
6643 to reference a two-register group starting with an arbitrary register
6644 (and currently gen_lowpart might crash for a SUBREG). */
6649 /* Reject MODEs that aren't scalar integers because turning vector
6650 or complex modes into shifts causes problems. */
6656 /* If the inner object has VOIDmode (the only way this can happen
6657 is if it is an ASM_OPERANDS), we can't do anything since we don't
6658 know how much masking to do. */
6667 /* ... fall through ... */
6670 /* If the operand is a CLOBBER, just return it. */
6679 /* Reject MODEs that aren't scalar integers because turning vector
6680 or complex modes into shifts causes problems. */
6688 /* This should stay within the object being extracted, fail otherwise. */
6699 }
6700 /* Convert sign extension to zero extension, if we know that the high
6701 bit is not set, as this is easier to optimize. It will be converted
6702 back to cheaper alternative in make_extraction. */
6710 {
6714 /* Make sure this is a profitable operation. */
6721 else
6723 }
6725 /* We can optimize some special cases of ZERO_EXTEND. */
6727 {
6728 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6729 know that the last value didn't have any inappropriate bits
6730 set. */
6738 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6747 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6748 is a comparison and STORE_FLAG_VALUE permits. This is like
6749 the first case, but it works even when GET_MODE (x) is larger
6750 than HOST_WIDE_INT. */
6760 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6771 }
6773 /* If we reach here, we want to return a pair of shifts. The inner
6774 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6775 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6776 logical depending on the value of UNSIGNEDP.
6778 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6779 converted into an AND of a shift.
6781 We must check for the case where the left shift would have a negative
6782 count. This can happen in a case like (x >> 31) & 255 on machines
6783 that can't shift by a constant. On those machines, we would first
6784 combine the shift with the AND to produce a variable-position
6785 extraction. Then the constant of 31 would be substituted in to produce
6786 a such a position. */
6790 {
6799 }
6806 else
6807 /* Any other cases we can't handle. */
6810 /* If we couldn't do this for some reason, return the original
6811 expression. */
6816 }
6817 \f
6818 /* X is a SET which contains an assignment of one object into
6819 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6820 or certain SUBREGS). If possible, convert it into a series of
6821 logical operations.
6823 We half-heartedly support variable positions, but do not at all
6824 support variable lengths. */
6826 static const_rtx
6828 {
6829 rtx inner;
6835 /* Loop until we find something we can't simplify. */
6837 {
6840 {
6844 }
6847 {
6852 /* A constant position should stay within the width of INNER. */
6858 {
6866 /* If position is ADJUST - X, new position is X. */
6868 else
6873 pos);
6874 }
6875 }
6877 /* A SUBREG between two modes that occupy the same numbers of words
6878 can be done by moving the SUBREG to the source. */
6880 /* We need SUBREGs to compute nonzero_bits properly. */
6881 && nonzero_sign_valid
6886 {
6888 gen_lowpart
6892 }
6893 else
6901 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6903 {
6906 /* Don't do anything for vector or complex integral types. */
6910 /* Try to find an integral mode to pun with. */
6917 }
6919 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6923 /* Now compute the equivalent expression. Make a copy of INNER
6924 for the SET_DEST in case it is a MEM into which we will substitute;
6925 we don't want shared RTL in that case. */
6930 compute_mode,
6932 compute_mode),
6933 inner);
6938 mask),
6939 pos);
6944 }
6947 }
6948 \f
6949 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6950 it is an RTX that represents a variable starting position; otherwise,
6951 POS is the (constant) starting bit position (counted from the LSB).
6953 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6954 signed reference.
6956 IN_DEST is nonzero if this is a reference in the destination of a
6957 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6958 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6959 be used.
6961 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6962 ZERO_EXTRACT should be built even for bits starting at bit 0.
6964 MODE is the desired mode of the result (if IN_DEST == 0).
6966 The result is an RTX for the extraction or NULL_RTX if the target
6967 can't handle it. */
6969 static rtx
6973 {
6974 /* This mode describes the size of the storage area
6975 to fetch the overall value from. Within that, we
6976 ignore the POS lowest bits, etc. */
6986 HOST_WIDE_INT orig_pos;
6989 {
6990 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6991 consider just the QI as the memory to extract from.
6992 The subreg adds or removes high bits; its mode is
6993 irrelevant to the meaning of this extraction,
6994 since POS and LEN count from the lsb. */
6998 }
7003 {
7004 /* We're extracting the least significant bits of an rtx
7005 (ashift X (const_int C)), where LEN > C. Extract the
7006 least significant (LEN - C) bits of X, giving an rtx
7007 whose mode is MODE, then shift it left C times. */
7013 }
7020 /* See if this can be done without an extraction. We never can if the
7021 width of the field is not the same as that of some integer mode. For
7022 registers, we can only avoid the extraction if the position is at the
7023 low-order bit and this is either not in the destination or we have the
7024 appropriate STRICT_LOW_PART operation available.
7026 For MEM, we can avoid an extract if the field starts on an appropriate
7027 boundary and we can change the mode of the memory reference. */
7037 && (! in_dest
7041 && (pos
7044 /* We can't do this if we are widening INNER_MODE (it
7045 may not be aligned, for one thing). */
7050 {
7051 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7052 field. If the original and current mode are the same, we need not
7053 adjust the offset. Otherwise, we do if bytes big endian.
7055 If INNER is not a MEM, get a piece consisting of just the field
7056 of interest (in this case POS % BITS_PER_WORD must be 0). */
7059 {
7060 HOST_WIDE_INT offset;
7062 /* POS counts from lsb, but make OFFSET count in memory order. */
7065 else
7069 }
7071 {
7073 {
7074 /* We can't call gen_lowpart in a DEST since we
7075 always want a SUBREG (see below) and it would sometimes
7076 return a new hard register. */
7078 {
7093 /* Avoid creating invalid subregs, for example when
7094 simplifying (x>>32)&255. */
7099 }
7100 else
7102 }
7103 else
7105 }
7106 else
7108 len >= HOST_BITS_PER_WIDE_INT
7113 /* If this extraction is going into the destination of a SET,
7114 make a STRICT_LOW_PART unless we made a MEM. */
7130 /* If we know that no extraneous bits are set, and that the high
7131 bit is not set, convert the extraction to the cheaper of
7132 sign and zero extension, that are equivalent in these cases. */
7140 {
7144 /* Prefer ZERO_EXTENSION, since it gives more information to
7145 backends. */
7150 }
7152 /* Otherwise, sign- or zero-extend unless we already are in the
7153 proper mode. */
7157 }
7159 /* Unless this is a COMPARE or we have a funny memory reference,
7160 don't do anything with zero-extending field extracts starting at
7161 the low-order bit since they are simple AND operations. */
7166 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7167 if the position is not a constant and the length is not 1. In all
7168 other cases, we would only be going outside our object in cases when
7169 an original shift would have been undefined. */
7175 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7176 and the mode for the result. */
7178 {
7182 }
7186 {
7190 }
7194 {
7198 }
7200 /* Never narrow an object, since that might not be safe. */
7210 /* If this is not from memory, the desired mode is the preferred mode
7211 for an extraction pattern's first input operand, or word_mode if there
7212 is none. */
7215 else
7216 {
7217 /* Be careful not to go beyond the extracted object and maintain the
7218 natural alignment of the memory. */
7222 {
7225 }
7227 /* If we have to change the mode of memory and cannot, the desired mode
7228 is EXTRACTION_MODE. */
7234 }
7239 {
7240 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7241 BITS_BIG_ENDIAN style. If position is constant, compute new
7242 position. Otherwise, build subtraction.
7243 Note that POS is relative to the mode of the original argument.
7244 If it's a MEM we need to recompute POS relative to that.
7245 However, if we're extracting from (or inserting into) a register,
7246 we want to recompute POS relative to wanted_inner_mode. */
7253 else
7254 pos_rtx
7256 /* POS may be less than 0 now, but we check for that below.
7257 Note that it can only be less than 0 if !MEM_P (inner). */
7258 }
7260 /* If INNER has a wider mode, and this is a constant extraction, try to
7261 make it smaller and adjust the byte to point to the byte containing
7262 the value. */
7265 && ! pos_rtx
7270 {
7273 /* The computations below will be correct if the machine is big
7274 endian in both bits and bytes or little endian in bits and bytes.
7275 If it is mixed, we must adjust. */
7277 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7278 adjust OFFSET to compensate. */
7283 /* We can now move to the desired byte. */
7294 }
7296 /* If INNER is not memory, get it into the proper mode. If we are changing
7297 its mode, POS must be a constant and smaller than the size of the new
7298 mode. */
7300 {
7301 /* On the LHS, don't create paradoxical subregs implicitely truncating
7302 the register unless TRULY_NOOP_TRUNCATION. */
7317 pos_rtx
7323 }
7325 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7326 have to zero extend. Otherwise, we can just use a SUBREG. */
7329 {
7332 /* If we know that no extraneous bits are set, and that the high
7333 bit is not set, convert extraction to cheaper one - either
7334 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7335 cases. */
7343 {
7346 /* Prefer ZERO_EXTENSION, since it gives more information to
7347 backends. */
7351 }
7353 }
7358 /* Make POS_RTX unless we already have it and it is correct. If we don't
7359 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7360 be a CONST_INT. */
7367 /* Make the required operation. See if we can use existing rtx. */
7374 }
7375 \f
7376 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7377 with any other operations in X. Return X without that shift if so. */
7379 static rtx
7381 {
7384 rtx tem;
7387 {
7389 /* This is the shift itself. If it is wide enough, we will return
7390 either the value being shifted if the shift count is equal to
7391 COUNT or a shift for the difference. */
7405 /* If we can safely shift this constant and we find the inner shift,
7406 make a new operation. */
7417 }
7420 }
7421 \f
7422 /* Look at the expression rooted at X. Look for expressions
7423 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7424 Form these expressions.
7426 Return the new rtx, usually just X.
7428 Also, for machines like the VAX that don't have logical shift insns,
7429 try to convert logical to arithmetic shift operations in cases where
7430 they are equivalent. This undoes the canonicalizations to logical
7431 shifts done elsewhere.
7433 We try, as much as possible, to re-use rtl expressions to save memory.
7435 IN_CODE says what kind of expression we are processing. Normally, it is
7436 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7437 being kludges), it is MEM. When processing the arguments of a comparison
7438 or a COMPARE against zero, it is COMPARE. */
7440 static rtx
7442 {
7450 rtx tem;
7453 /* Select the code to be used in recursive calls. Once we are inside an
7454 address, we stay there. If we have a comparison, set to COMPARE,
7455 but once inside, go back to our default of SET. */
7464 /* Process depending on the code of this operation. If NEW is set
7465 nonzero, it will be returned. */
7468 {
7470 /* Convert shifts by constants into multiplications if inside
7471 an address. */
7475 {
7481 {
7484 }
7487 }
7497 {
7501 }
7504 {
7508 mode));
7510 }
7511 else
7512 {
7516 }
7527 {
7531 }
7534 {
7538 mode));
7540 }
7541 else
7542 {
7546 }
7550 /* If the second operand is not a constant, we can't do anything
7551 with it. */
7555 /* If the constant is a power of two minus one and the first operand
7556 is a logical right shift, make an extraction. */
7559 {
7563 }
7565 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7570 {
7572 next_code);
7576 }
7577 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7583 {
7584 /* Apply the distributive law, and then try to make extractions. */
7591 }
7593 /* If we are have (and (rotate X C) M) and C is larger than the number
7594 of bits in M, this is an extraction. */
7600 {
7606 }
7608 /* On machines without logical shifts, if the operand of the AND is
7609 a logical shift and our mask turns off all the propagated sign
7610 bits, we can replace the logical shift with an arithmetic shift. */
7618 {
7625 make_compound_operation
7628 }
7630 /* If the constant is one less than a power of two, this might be
7631 representable by an extraction even if no shift is present.
7632 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7633 we are in a COMPARE. */
7637 next_code),
7640 /* If we are in a comparison and this is an AND with a power of two,
7641 convert this into the appropriate bit extract. */
7646 next_code),
7652 /* If the sign bit is known to be zero, replace this with an
7653 arithmetic shift. */
7658 {
7661 next_code),
7664 }
7666 /* ... fall through ... */
7672 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7673 this is a SIGN_EXTRACT. */
7679 {
7686 }
7688 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7689 If so, try to merge the shifts into a SIGN_EXTEND. We could
7690 also do this for some cases of SIGN_EXTRACT, but it doesn't
7691 seem worth the effort; the case checked for occurs on Alpha. */
7707 /* Call ourselves recursively on the inner expression. If we are
7708 narrowing the object and it has a different RTL code from
7709 what it originally did, do this SUBREG as a force_to_mode. */
7710 {
7715 simplified
7723 {
7726 /* If we have something other than a SUBREG, we might have
7727 done an expansion, so rerun ourselves. */
7731 /* force_to_mode can expand compounds. If it just re-expanded the
7732 compound, use gen_lowpart to convert to the desired mode. */
7734 /* Likewise if it re-expanded the compound only partially.
7735 This happens for SUBREG of ZERO_EXTRACT if they extract
7736 the same number of bits. */
7745 }
7749 }
7754 }
7757 {
7760 }
7762 /* Now recursively process each operand of this operation. */
7766 {
7769 }
7772 {
7775 }
7777 maybe_swap:
7778 /* If this is a commutative operation, the changes to the operands
7779 may have made it noncanonical. */
7782 {
7786 }
7789 }
7790 \f
7791 /* Given M see if it is a value that would select a field of bits
7792 within an item, but not the entire word. Return -1 if not.
7793 Otherwise, return the starting position of the field, where 0 is the
7794 low-order bit.
7796 *PLEN is set to the length of the field. */
7798 static int
7800 {
7801 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7806 /* Now shift off the low-order zero bits and see if we have a
7807 power of two minus 1. */
7815 }
7816 \f
7817 /* If X refers to a register that equals REG in value, replace these
7818 references with REG. */
7819 static rtx
7821 {
7829 {
7865 {
7869 else
7871 }
7873 /* fall through */
7880 {
7883 {
7885 {
7888 }
7890 }
7891 }
7893 {
7896 {
7899 {
7901 {
7904 }
7906 }
7907 }
7908 }
7911 }
7914 }
7916 /* Return X converted to MODE. If the value is already truncated to
7917 MODE we can just return a subreg even though in the general case we
7918 would need an explicit truncation. */
7920 static rtx
7922 {
7928 {
7929 /* Bit-cast X into an integer mode. */
7934 }
7937 }
7939 /* See if X can be simplified knowing that we will only refer to it in
7940 MODE and will only refer to those bits that are nonzero in MASK.
7941 If other bits are being computed or if masking operations are done
7942 that select a superset of the bits in MASK, they can sometimes be
7943 ignored.
7945 Return a possibly simplified expression, but always convert X to
7946 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7948 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7949 are all off in X. This is used when X will be complemented, by either
7950 NOT, NEG, or XOR. */
7952 static rtx
7955 {
7962 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7963 code below will do the wrong thing since the mode of such an
7964 expression is VOIDmode.
7966 Also do nothing if X is a CLOBBER; this can happen if X was
7967 the return value from a call to gen_lowpart. */
7971 /* We want to perform the operation is its present mode unless we know
7972 that the operation is valid in MODE, in which case we do the operation
7973 in MODE. */
7978 /* It is not valid to do a right-shift in a narrower mode
7979 than the one it came in with. */
7984 /* Truncate MASK to fit OP_MODE. */
7988 /* When we have an arithmetic operation, or a shift whose count we
7989 do not know, we need to assume that all bits up to the highest-order
7990 bit in MASK will be needed. This is how we form such a mask. */
7993 else
7997 /* Determine what bits of X are guaranteed to be (non)zero. */
8000 /* If none of the bits in X are needed, return a zero. */
8004 /* If X is a CONST_INT, return a new one. Do this here since the
8005 test below will fail. */
8007 {
8010 else
8011 {
8014 }
8015 }
8017 /* If X is narrower than MODE and we want all the bits in X's mode, just
8018 get X in the proper mode. */
8023 /* We can ignore the effect of a SUBREG if it narrows the mode or
8024 if the constant masks to zero all the bits the mode doesn't have. */
8034 /* The arithmetic simplifications here only work for scalar integer modes. */
8039 {
8041 /* If X is a (clobber (const_int)), return it since we know we are
8042 generating something that won't match. */
8055 /* Similarly for a truncate. */
8059 /* If this is an AND with a constant, convert it into an AND
8060 whose constant is the AND of that constant with MASK. If it
8061 remains an AND of MASK, delete it since it is redundant. */
8064 {
8068 /* If X is still an AND, see if it is an AND with a mask that
8069 is just some low-order bits. If so, and it is MASK, we don't
8070 need it. */
8077 /* If it remains an AND, try making another AND with the bits
8078 in the mode mask that aren't in MASK turned on. If the
8079 constant in the AND is wide enough, this might make a
8080 cheaper constant. */
8085 {
8089 rtx y;
8091 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8092 number, sign extend it. */
8102 }
8105 }
8110 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8111 low-order bits (as in an alignment operation) and FOO is already
8112 aligned to that boundary, mask C1 to that boundary as well.
8113 This may eliminate that PLUS and, later, the AND. */
8115 {
8119 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8120 number, sign extend it. */
8133 }
8135 /* ... fall through ... */
8138 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8139 most significant bit in MASK since carries from those bits will
8140 affect the bits we are interested in. */
8145 /* If X is (minus C Y) where C's least set bit is larger than any bit
8146 in the mask, then we may replace with (neg Y). */
8151 {
8155 }
8157 /* Similarly, if C contains every bit in the fuller_mask, then we may
8158 replace with (not Y). */
8162 {
8166 }
8173 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8174 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8175 operation which may be a bitfield extraction. Ensure that the
8176 constant we form is not wider than the mode of X. */
8188 {
8196 }
8198 binop:
8199 /* For most binary operations, just propagate into the operation and
8200 change the mode if we have an operation of that mode. */
8205 /* If we ended up truncating both operands, truncate the result of the
8206 operation instead. */
8209 {
8212 }
8222 /* For left shifts, do the same, but just for the first operand.
8223 However, we cannot do anything with shifts where we cannot
8224 guarantee that the counts are smaller than the size of the mode
8225 because such a count will have a different meaning in a
8226 wider mode. */
8236 /* If the shift count is a constant and we can do arithmetic in
8237 the mode of the shift, refine which bits we need. Otherwise, use the
8238 conservative form of the mask. */
8244 else
8256 /* Here we can only do something if the shift count is a constant,
8257 this shift constant is valid for the host, and we can do arithmetic
8258 in OP_MODE. */
8263 {
8267 /* Select the mask of the bits we need for the shift operand. */
8270 /* We can only change the mode of the shift if we can do arithmetic
8271 in the mode of the shift and INNER_MASK is no wider than the
8272 width of X's mode. */
8280 }
8282 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8283 shift and AND produces only copies of the sign bit (C2 is one less
8284 than a power of two), we can do this with just a shift. */
8288 /* The shift puts one of the sign bit copies in the least significant
8289 bit. */
8294 /* Number of bits left after the shift must be more than the mask
8295 needs. */
8298 /* Must be more sign bit copies than the mask needs. */
8308 /* If we are just looking for the sign bit, we don't need this shift at
8309 all, even if it has a variable count. */
8315 /* If this is a shift by a constant, get a mask that contains those bits
8316 that are not copies of the sign bit. We then have two cases: If
8317 MASK only includes those bits, this can be a logical shift, which may
8318 allow simplifications. If MASK is a single-bit field not within
8319 those bits, we are requesting a copy of the sign bit and hence can
8320 shift the sign bit to the appropriate location. */
8324 {
8327 /* If the considered data is wider than HOST_WIDE_INT, we can't
8328 represent a mask for all its bits in a single scalar.
8329 But we only care about the lower bits, so calculate these. */
8332 {
8335 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8336 is the number of bits a full-width mask would have set.
8337 We need only shift if these are fewer than nonzero can
8338 hold. If not, we must keep all bits set in nonzero. */
8343 + HOST_BITS_PER_WIDE_INT
8345 }
8346 else
8347 {
8350 }
8353 {
8358 }
8361 {
8362 x = simplify_shift_const
8368 }
8369 }
8371 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8372 even if the shift count isn't a constant. */
8377 shiftrt:
8379 /* If this is a zero- or sign-extension operation that just affects bits
8380 we don't care about, remove it. Be sure the call above returned
8381 something that is still a shift. */
8391 next_select);
8397 /* If the shift count is constant and we can do computations
8398 in the mode of X, compute where the bits we care about are.
8399 Otherwise, we can't do anything. Don't change the mode of
8400 the shift or propagate MODE into the shift, though. */
8403 {
8411 }
8415 /* If we just want the low-order bit, the NEG isn't needed since it
8416 won't change the low-order bit. */
8420 /* We need any bits less significant than the most significant bit in
8421 MASK since carries from those bits will affect the bits we are
8422 interested in. */
8427 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8428 same as the XOR case above. Ensure that the constant we form is not
8429 wider than the mode of X. */
8437 {
8446 }
8448 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8449 use the full mask inside the NOT. */
8452 unop:
8455 next_select));
8461 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8462 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8463 which is equal to STORE_FLAG_VALUE. */
8474 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8475 written in a narrower mode. We play it safe and do not do so. */
8489 }
8491 /* Ensure we return a value of the proper mode. */
8493 }
8494 \f
8495 /* Return nonzero if X is an expression that has one of two values depending on
8496 whether some other value is zero or nonzero. In that case, we return the
8497 value that is being tested, *PTRUE is set to the value if the rtx being
8498 returned has a nonzero value, and *PFALSE is set to the other alternative.
8500 If we return zero, we set *PTRUE and *PFALSE to X. */
8502 static rtx
8504 {
8510 /* If we are comparing a value against zero, we are done. */
8513 {
8517 }
8519 /* If this is a unary operation whose operand has one of two values, apply
8520 our opcode to compute those values. */
8523 {
8528 }
8530 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8531 make can't possibly match and would suppress other optimizations. */
8533 ;
8535 /* If this is a binary operation, see if either side has only one of two
8536 values. If either one does or if both do and they are conditional on
8537 the same value, compute the new true and false values. */
8539 {
8545 {
8546 /* If if_then_else_cond returned zero, then true/false are the
8547 same rtl. We must copy one of them to prevent invalid rtl
8548 sharing. */
8555 {
8560 }
8561 else
8562 {
8565 }
8568 }
8570 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8571 operands is zero when the other is nonzero, and vice-versa,
8572 and STORE_FLAG_VALUE is 1 or -1. */
8578 {
8595 {
8602 const_true_rtx);
8604 }
8605 }
8607 /* Similarly for MULT, AND and UMIN, except that for these the result
8608 is always zero. */
8612 {
8626 {
8629 }
8630 }
8631 }
8634 {
8635 /* If we have IF_THEN_ELSE already, extract the condition and
8636 canonicalize it if it is NE or EQ. */
8642 {
8645 }
8646 else
8648 }
8650 /* If X is a SUBREG, we can narrow both the true and false values
8651 if the inner expression, if there is a condition. */
8655 {
8661 {
8665 }
8666 }
8668 /* If X is a constant, this isn't special and will cause confusions
8669 if we treat it as such. Likewise if it is equivalent to a constant. */
8672 ;
8674 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8675 will be least confusing to the rest of the compiler. */
8677 {
8680 }
8682 /* If X is known to be either 0 or -1, those are the true and
8683 false values when testing X. */
8687 {
8690 }
8692 /* Likewise for 0 or a single bit. */
8696 {
8699 }
8701 /* Otherwise fail; show no condition with true and false values the same. */
8704 }
8705 \f
8706 /* Return the value of expression X given the fact that condition COND
8707 is known to be true when applied to REG as its first operand and VAL
8708 as its second. X is known to not be shared and so can be modified in
8709 place.
8711 We only handle the simplest cases, and specifically those cases that
8712 arise with IF_THEN_ELSE expressions. */
8714 static rtx
8716 {
8718 rtx temp;
8725 /* If either operand of the condition is a floating point value,
8726 then we have to avoid collapsing an EQ comparison. */
8736 /* If X is (abs REG) and we know something about REG's relationship
8737 with zero, we may be able to simplify this. */
8741 {
8750 }
8752 /* The only other cases we handle are MIN, MAX, and comparisons if the
8753 operands are the same as REG and VAL. */
8756 {
8761 {
8763 {
8771 else
8773 }
8776 {
8779 /* Do not reverse the condition when it is NE or EQ.
8780 This is because we cannot conclude anything about
8781 the value of 'SMAX (x, y)' when x is not equal to y,
8782 but we can when x equals y. */
8788 {
8799 }
8800 }
8801 }
8802 }
8804 {
8809 {
8810 /* We must simplify subreg here, before we lose track of the
8811 original inner_mode. */
8816 else
8818 }
8821 }
8822 /* We don't have to handle SIGN_EXTEND here, because even in the
8823 case of replacing something with a modeless CONST_INT, a
8824 CONST_INT is already (supposed to be) a valid sign extension for
8825 its narrower mode, which implies it's already properly
8826 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8827 story is different. */
8829 {
8834 {
8835 /* We must simplify the zero_extend here, before we lose
8836 track of the original inner_mode. */
8841 else
8843 }
8846 }
8850 {
8857 }
8860 }
8861 \f
8862 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8863 assignment as a field assignment. */
8865 static int
8867 {
8874 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8875 Note that all SUBREGs of MEM are paradoxical; otherwise they
8876 would have been rewritten. */
8889 /* We used to see if get_last_value of X and Y were the same but that's
8890 not correct. In one direction, we'll cause the assignment to have
8891 the wrong destination and in the case, we'll import a register into this
8892 insn that might have already have been dead. So fail if none of the
8893 above cases are true. */
8895 }
8896 \f
8897 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8898 Return that assignment if so.
8900 We only handle the most common cases. */
8902 static rtx
8904 {
8907 rtx assign;
8909 HOST_WIDE_INT c1;
8910 HOST_WIDE_INT pos;
8912 rtx other;
8915 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8916 a clear of a one-bit field. We will have changed it to
8917 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8918 for a SUBREG. */
8924 {
8930 }
8940 {
8947 }
8949 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8950 one-bit field. */
8954 {
8960 }
8962 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8963 SRC is an AND with all bits of that field set, then we can discard
8964 the AND. */
8969 {
8976 else
8979 /* Complete overlap. We can remove the source AND. */
8983 /* Partial overlap. We can reduce the source AND. */
8985 {
8990 }
8991 }
8993 /* The other case we handle is assignments into a constant-position
8994 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8995 a mask that has all one bits except for a group of zero bits and
8996 OTHER is known to have zeros where C1 has ones, this is such an
8997 assignment. Compute the position and length from C1. Shift OTHER
8998 to the appropriate position, force it to the required mode, and
8999 make the extraction. Check for the AND in both operands. */
9015 else
9028 /* The mode to use for the source is the mode of the assignment, or of
9029 what is inside a possible STRICT_LOW_PART. */
9033 /* Shift OTHER right POS places and make it the source, restricting it
9034 to the proper length and mode. */
9039 dest);
9046 /* If SRC is masked by an AND that does not make a difference in
9047 the value being stored, strip it. */
9058 }
9059 \f
9060 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9061 if so. */
9063 static rtx
9065 {
9069 rtx tem;
9071 /* Distributivity is not true for floating point as it can change the
9072 value. So we don't do it unless -funsafe-math-optimizations. */
9077 /* The outer operation can only be one of the following: */
9085 /* If either operand is a primitive we can't do anything, so get out
9086 fast. */
9096 /* See if the inner and outer operations distribute. */
9098 {
9103 /* These all distribute except over PLUS. */
9114 /* This is also a multiply, so it distributes over everything. */
9118 /* Non-paradoxical SUBREGs distributes over all operations,
9119 provided the inner modes and byte offsets are the same, this
9120 is an extraction of a low-order part, we don't convert an fp
9121 operation to int or vice versa, this is not a vector mode,
9122 and we would not be converting a single-word operation into a
9123 multi-word operation. The latter test is not required, but
9124 it prevents generating unneeded multi-word operations. Some
9125 of the previous tests are redundant given the latter test,
9126 but are retained because they are required for correctness.
9128 We produce the result slightly differently in this case. */
9139 /* Result might need to be truncated. Don't change mode if
9140 explicit truncation is needed. */
9141 || !TRULY_NOOP_TRUNCATION
9152 }
9154 /* Set LHS and RHS to the inner operands (A and B in the example
9155 above) and set OTHER to the common operand (C in the example).
9156 There is only one way to do this unless the inner operation is
9157 commutative. */
9169 else
9172 /* Form the new inner operation, seeing if it simplifies first. */
9175 /* There is one exception to the general way of distributing:
9176 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9178 {
9181 }
9183 /* We may be able to continuing distributing the result, so call
9184 ourselves recursively on the inner operation before forming the
9185 outer operation, which we return. */
9188 }
9190 /* See if X is of the form (* (+ A B) C), and if so convert to
9191 (+ (* A C) (* B C)) and try to simplify.
9193 Most of the time, this results in no change. However, if some of
9194 the operands are the same or inverses of each other, simplifications
9195 will result.
9197 For example, (and (ior A B) (not B)) can occur as the result of
9198 expanding a bit field assignment. When we apply the distributive
9199 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9200 which then simplifies to (and (A (not B))).
9202 Note that no checks happen on the validity of applying the inverse
9203 distributive law. This is pointless since we can do it in the
9204 few places where this routine is called.
9206 N is the index of the term that is decomposed (the arithmetic operation,
9207 i.e. (+ A B) in the first example above). !N is the index of the term that
9208 is distributed, i.e. of C in the first example above. */
9209 static rtx
9211 {
9216 /* Distributivity is not true for floating point as it can change the
9217 value. So we don't do it unless -funsafe-math-optimizations. */
9234 /* Special case (and (xor B C) (not A)), which is equivalent to
9235 (xor (ior A B) (ior A C)) */
9237 {
9240 }
9243 {
9244 /* Distribute the second term. */
9247 }
9248 else
9249 {
9250 /* Distribute the first term. */
9253 }
9263 }
9264 \f
9265 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9266 in MODE. Return an equivalent form, if different from (and VAROP
9267 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9269 static rtx
9272 {
9275 rtx orig_varop;
9283 /* Simplify VAROP knowing that we will be only looking at some of the
9284 bits in it.
9286 Note by passing in CONSTOP, we guarantee that the bits not set in
9287 CONSTOP are not significant and will never be examined. We must
9288 ensure that is the case by explicitly masking out those bits
9289 before returning. */
9292 /* If VAROP is a CLOBBER, we will fail so return it. */
9296 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9297 to VAROP and return the new constant. */
9301 /* See what bits may be nonzero in VAROP. Unlike the general case of
9302 a call to nonzero_bits, here we don't care about bits outside
9303 MODE. */
9307 /* Turn off all bits in the constant that are known to already be zero.
9308 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9309 which is tested below. */
9313 /* If we don't have any bits left, return zero. */
9317 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9318 a power of two, we can replace this with an ASHIFT. */
9323 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9324 or XOR, then try to apply the distributive law. This may eliminate
9325 operations if either branch can be simplified because of the AND.
9326 It may also make some cases more complex, but those cases probably
9327 won't match a pattern either with or without this. */
9330 return
9331 gen_lowpart
9333 apply_distributive_law
9338 constop),
9342 constop))));
9344 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9345 the AND and see if one of the operands simplifies to zero. If so, we
9346 may eliminate it. */
9350 {
9359 }
9361 /* Make a SUBREG if necessary. If we can't make it, fail. */
9366 /* If we are only masking insignificant bits, return VAROP. */
9373 /* Otherwise, return an AND. */
9375 }
9378 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9379 in MODE.
9381 Return an equivalent form, if different from X. Otherwise, return X. If
9382 X is zero, we are to always construct the equivalent form. */
9384 static rtx
9387 {
9398 }
9399 \f
9400 /* Given a REG, X, compute which bits in X can be nonzero.
9401 We don't care about bits outside of those defined in MODE.
9403 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9404 a shift, AND, or zero_extract, we can do better. */
9406 static rtx
9408 const_rtx known_x ATTRIBUTE_UNUSED,
9412 {
9413 rtx tem;
9416 /* If X is a register whose nonzero bits value is current, use it.
9417 Otherwise, if X is a register whose value we can find, use that
9418 value. Otherwise, use the previously-computed global nonzero bits
9419 for this register. */
9432 && !REGNO_REG_SET_P
9434 {
9437 }
9442 {
9443 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9444 /* If X is narrower than MODE and TEM is a non-negative
9445 constant that would appear negative in the mode of X,
9446 sign-extend it for use in reg_nonzero_bits because some
9447 machines (maybe most) will actually do the sign-extension
9448 and this is the conservative approach.
9450 ??? For 2.5, try to tighten up the MD files in this regard
9451 instead of this kludge. */
9462 #endif
9464 }
9466 {
9470 /* We don't know anything about the upper bits. */
9473 }
9476 }
9478 /* Return the number of bits at the high-order end of X that are known to
9479 be equal to the sign bit. X will be used in mode MODE; if MODE is
9480 VOIDmode, X will be used in its own mode. The returned value will always
9481 be between 1 and the number of bits in MODE. */
9483 static rtx
9485 const_rtx known_x ATTRIBUTE_UNUSED,
9486 enum machine_mode known_mode
9487 ATTRIBUTE_UNUSED,
9490 {
9491 rtx tem;
9503 && !REGNO_REG_SET_P
9505 {
9508 }
9519 }
9520 \f
9521 /* Return the number of "extended" bits there are in X, when interpreted
9522 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9523 unsigned quantities, this is the number of high-order zero bits.
9524 For signed quantities, this is the number of copies of the sign bit
9525 minus 1. In both case, this function returns the number of "spare"
9526 bits. For example, if two quantities for which this function returns
9527 at least 1 are added, the addition is known not to overflow.
9529 This function will always return 0 unless called during combine, which
9530 implies that it must be called from a define_split. */
9532 unsigned int
9534 {
9544 }
9545 \f
9546 /* This function is called from `simplify_shift_const' to merge two
9547 outer operations. Specifically, we have already found that we need
9548 to perform operation *POP0 with constant *PCONST0 at the outermost
9549 position. We would now like to also perform OP1 with constant CONST1
9550 (with *POP0 being done last).
9552 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9553 the resulting operation. *PCOMP_P is set to 1 if we would need to
9554 complement the innermost operand, otherwise it is unchanged.
9556 MODE is the mode in which the operation will be done. No bits outside
9557 the width of this mode matter. It is assumed that the width of this mode
9558 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9560 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9561 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9562 result is simply *PCONST0.
9564 If the resulting operation cannot be expressed as one operation, we
9565 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9567 static int
9568 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9569 {
9576 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9580 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9581 if OP0 is SET. */
9590 {
9592 {
9610 }
9611 }
9613 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9617 /* If the two constants aren't the same, we can't do anything. The
9618 remaining six cases can all be done. */
9622 else
9624 {
9627 /* (a & b) | b == b */
9630 /* (a ^ b) | b == a | b */
9631 {;}
9636 /* (a & b) ^ b == (~a) & b */
9639 /* (a | b) ^ b == a & ~b */
9645 /* (a | b) & b == b */
9648 /* (a ^ b) & b) == (~a) & b */
9653 }
9655 /* Check for NO-OP cases. */
9668 /* ??? Slightly redundant with the above mask, but not entirely.
9669 Moving this above means we'd have to sign-extend the mode mask
9670 for the final test. */
9675 }
9676 \f
9677 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9678 the shift in. The original shift operation CODE is performed on OP in
9679 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9680 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9681 result of the shift is subject to operation OUTER_CODE with operand
9682 OUTER_CONST. */
9684 static enum machine_mode
9688 {
9693 /* In general we can't perform in wider mode for right shift and rotate. */
9695 {
9697 /* We can still widen if the bits brought in from the left are identical
9698 to the sign bit of ORIG_MODE. */
9706 /* Similarly here but with zero bits. */
9711 /* We can also widen if the bits brought in will be masked off. This
9712 operation is performed in ORIG_MODE. */
9714 {
9720 }
9721 /* fall through */
9731 }
9732 }
9734 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9735 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9736 simplify it. Otherwise, return a simplified value.
9738 The shift is normally computed in the widest mode we find in VAROP, as
9739 long as it isn't a different number of words than RESULT_MODE. Exceptions
9740 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9742 static rtx
9745 {
9751 unsigned int mode_words
9753 /* We form (outer_op (code varop count) (outer_const)). */
9759 /* Make sure and truncate the "natural" shift on the way in. We don't
9760 want to do this inside the loop as it makes it more difficult to
9761 combine shifts. */
9765 /* If we were given an invalid count, don't do anything except exactly
9766 what was requested. */
9773 /* Unless one of the branches of the `if' in this loop does a `continue',
9774 we will `break' the loop after the `if'. */
9777 {
9778 /* If we have an operand of (clobber (const_int 0)), fail. */
9782 /* Convert ROTATERT to ROTATE. */
9784 {
9789 else
9791 }
9796 /* Handle cases where the count is greater than the size of the mode
9797 minus 1. For ASHIFT, use the size minus one as the count (this can
9798 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9799 take the count modulo the size. For other shifts, the result is
9800 zero.
9802 Since these shifts are being produced by the compiler by combining
9803 multiple operations, each of which are defined, we know what the
9804 result is supposed to be. */
9807 {
9812 else
9813 {
9814 /* We can't simply return zero because there may be an
9815 outer op. */
9819 }
9820 }
9822 /* If we discovered we had to complement VAROP, leave. Making a NOT
9823 here would cause an infinite loop. */
9827 /* An arithmetic right shift of a quantity known to be -1 or 0
9828 is a no-op. */
9832 {
9835 }
9837 /* If we are doing an arithmetic right shift and discarding all but
9838 the sign bit copies, this is equivalent to doing a shift by the
9839 bitsize minus one. Convert it into that shift because it will often
9840 allow other simplifications. */
9847 /* We simplify the tests below and elsewhere by converting
9848 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9849 `make_compound_operation' will convert it to an ASHIFTRT for
9850 those machines (such as VAX) that don't have an LSHIFTRT. */
9869 {
9876 {
9879 }
9883 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9884 minus the width of a smaller mode, we can do this with a
9885 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9891 {
9900 }
9904 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9905 the same number of words as what we've seen so far. Then store
9906 the widest mode in MODE. */
9912 == mode_words
9915 {
9920 }
9924 /* Some machines use MULT instead of ASHIFT because MULT
9925 is cheaper. But it is still better on those machines to
9926 merge two shifts into one. */
9929 {
9930 varop
9936 }
9940 /* Similar, for when divides are cheaper. */
9943 {
9944 varop
9950 }
9954 /* If we are extracting just the sign bit of an arithmetic
9955 right shift, that shift is not needed. However, the sign
9956 bit of a wider mode may be different from what would be
9957 interpreted as the sign bit in a narrower mode, so, if
9958 the result is narrower, don't discard the shift. */
9963 {
9966 }
9968 /* ... fall through ... */
9973 /* Here we have two nested shifts. The result is usually the
9974 AND of a new shift with a mask. We compute the result below. */
9981 {
9985 rtx mask_rtx;
9987 /* We have one common special case. We can't do any merging if
9988 the inner code is an ASHIFTRT of a smaller mode. However, if
9989 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9990 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9991 we can convert it to
9992 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9993 This simplifies certain SIGN_EXTEND operations. */
9997 {
9998 /* C3 has the low-order C1 bits zero. */
10010 }
10012 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10013 than C1 high-order bits equal to the sign bit, we can convert
10014 this to either an ASHIFT or an ASHIFTRT depending on the
10015 two counts.
10017 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10023 {
10027 {
10030 }
10033 }
10035 /* There are some cases we can't do. If CODE is ASHIFTRT,
10036 we can only do this if FIRST_CODE is also ASHIFTRT.
10038 We can't do the case when CODE is ROTATE and FIRST_CODE is
10039 ASHIFTRT.
10041 If the mode of this shift is not the mode of the outer shift,
10042 we can't do this if either shift is a right shift or ROTATE.
10044 Finally, we can't do any of these if the mode is too wide
10045 unless the codes are the same.
10047 Handle the case where the shift codes are the same
10048 first. */
10051 {
10060 }
10071 /* To compute the mask to apply after the shift, shift the
10072 nonzero bits of the inner shift the same way the
10073 outer shift will. */
10077 mask_rtx
10081 /* Give up if we can't compute an outer operation to use. */
10089 /* If the shifts are in the same direction, we add the
10090 counts. Otherwise, we subtract them. */
10094 else
10097 /* If COUNT is positive, the new shift is usually CODE,
10098 except for the two exceptions below, in which case it is
10099 FIRST_CODE. If the count is negative, FIRST_CODE should
10100 always be used */
10110 }
10112 /* If we have (A << B << C) for any shift, we can convert this to
10113 (A << C << B). This wins if A is a constant. Only try this if
10114 B is not a constant. */
10119 {
10126 }
10133 /* Make this fit the case below. */
10141 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10142 with C the size of VAROP - 1 and the shift is logical if
10143 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10144 we have an (le X 0) operation. If we have an arithmetic shift
10145 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10146 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10154 {
10157 const0_rtx);
10163 }
10165 /* If we have (shift (logical)), move the logical to the outside
10166 to allow it to possibly combine with another logical and the
10167 shift to combine with another shift. This also canonicalizes to
10168 what a ZERO_EXTRACT looks like. Also, some machines have
10169 (and (shift)) insns. */
10172 /* We can't do this if we have (ashiftrt (xor)) and the
10173 constant has its sign bit set in shift_mode. */
10176 shift_mode))
10183 {
10186 }
10188 /* If we can't do that, try to simplify the shift in each arm of the
10189 logical expression, make a new logical expression, and apply
10190 the inverse distributive law. This also can't be done
10191 for some (ashiftrt (xor)). */
10195 shift_mode)))
10196 {
10208 }
10212 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10213 says that the sign bit can be tested, FOO has mode MODE, C is
10214 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10215 that may be nonzero. */
10226 {
10230 }
10234 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10235 than the number of bits in the mode is equivalent to A. */
10239 {
10243 }
10245 /* NEG commutes with ASHIFT since it is multiplication. Move the
10246 NEG outside to allow shifts to combine. */
10251 {
10254 }
10258 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10259 is one less than the number of bits in the mode is
10260 equivalent to (xor A 1). */
10268 {
10272 }
10274 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10275 that might be nonzero in BAR are those being shifted out and those
10276 bits are known zero in FOO, we can replace the PLUS with FOO.
10277 Similarly in the other operand order. This code occurs when
10278 we are computing the size of a variable-size array. */
10285 {
10288 }
10296 result_mode)))
10297 {
10300 }
10302 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10311 {
10314 }
10316 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10317 signbit', and attempt to change the PLUS to an XOR and move it to
10318 the outer operation as is done above in the AND/IOR/XOR case
10319 leg for shift(logical). See details in logical handling above
10320 for reasoning in doing so. */
10330 {
10333 }
10338 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10339 with C the size of VAROP - 1 and the shift is logical if
10340 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10341 we have a (gt X 0) operation. If the shift is arithmetic with
10342 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10343 we have a (neg (gt X 0)) operation. */
10352 {
10355 const0_rtx);
10361 }
10365 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10366 if the truncate does not affect the value. */
10373 {
10376 varop_inner
10379 GEN_INT
10384 }
10389 }
10392 }
10397 /* We have now finished analyzing the shift. The result should be
10398 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10399 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10400 to the result of the shift. OUTER_CONST is the relevant constant,
10401 but we must turn off all bits turned off in the shift. */
10409 /* Make a SUBREG if necessary. If we can't make it, fail. */
10414 /* If we have an outer operation and we just made a shift, it is
10415 possible that we could have simplified the shift were it not
10416 for the outer operation. So try to do the simplification
10417 recursively. */
10421 else
10427 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10428 turn off all the bits that the shift would have turned off. */
10433 /* Do the remainder of the processing in RESULT_MODE. */
10436 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10437 operation. */
10442 {
10450 {
10451 /* This means that we have determined that the result is
10452 equivalent to a constant. This should be rare. */
10455 }
10458 else
10461 }
10464 }
10466 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10467 The result of the shift is RESULT_MODE. If we cannot simplify it,
10468 return X or, if it is NULL, synthesize the expression with
10469 simplify_gen_binary. Otherwise, return a simplified value.
10471 The shift is normally computed in the widest mode we find in VAROP, as
10472 long as it isn't a different number of words than RESULT_MODE. Exceptions
10473 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10475 static rtx
10478 {
10488 }
10490 \f
10491 /* Like recog, but we receive the address of a pointer to a new pattern.
10492 We try to match the rtx that the pointer points to.
10493 If that fails, we may try to modify or replace the pattern,
10494 storing the replacement into the same pointer object.
10496 Modifications include deletion or addition of CLOBBERs.
10498 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10499 the CLOBBERs are placed.
10501 The value is the final insn code from the pattern ultimately matched,
10502 or -1. */
10504 static int
10506 {
10514 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10515 we use to indicate that something didn't match. If we find such a
10516 thing, force rejection. */
10530 {
10533 else
10536 }
10538 /* If it isn't, there is the possibility that we previously had an insn
10539 that clobbered some register as a side effect, but the combined
10540 insn doesn't need to do that. So try once more without the clobbers
10541 unless this represents an ASM insn. */
10545 {
10550 {
10553 pos++;
10554 }
10564 {
10567 else
10570 }
10571 }
10575 /* Recognize all noop sets, these will be killed by followup pass. */
10579 /* If we had any clobbers to add, make a new pattern than contains
10580 them. Then check to make sure that all of them are dead. */
10582 {
10592 else
10599 {
10604 {
10608 }
10609 }
10611 }
10617 }
10618 \f
10619 /* Like gen_lowpart_general but for use by combine. In combine it
10620 is not possible to create any new pseudoregs. However, it is
10621 safe to create invalid memory addresses, because combine will
10622 try to recognize them and all they will do is make the combine
10623 attempt fail.
10625 If for some reason this cannot do its job, an rtx
10626 (clobber (const_int 0)) is returned.
10627 An insn containing that will not be recognized. */
10629 static rtx
10631 {
10635 rtx result;
10640 /* Return identity if this is a CONST or symbolic reference. */
10647 /* We can only support MODE being wider than a word if X is a
10648 constant integer or has a mode the same size. */
10656 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10657 won't know what to do. So we will strip off the SUBREG here and
10658 process normally. */
10660 {
10663 /* For use in case we fall down into the address adjustments
10664 further below, we need to adjust the known mode and size of
10665 x; imode and isize, since we just adjusted x. */
10672 }
10680 {
10683 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10684 address. */
10688 /* If we want to refer to something bigger than the original memref,
10689 generate a paradoxical subreg instead. That will force a reload
10690 of the original memref X. */
10697 /* Adjust the address so that the address-after-the-data is
10698 unchanged. */
10703 }
10705 /* If X is a comparison operator, rewrite it in a new mode. This
10706 probably won't match, but may allow further simplifications. */
10710 /* If we couldn't simplify X any other way, just enclose it in a
10711 SUBREG. Normally, this SUBREG won't match, but some patterns may
10712 include an explicit SUBREG or we may simplify it further in combine. */
10713 else
10714 {
10716 rtx res;
10720 {
10725 }
10729 }
10731 fail:
10733 }
10734 \f
10735 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10736 comparison code that will be tested.
10738 The result is a possibly different comparison code to use. *POP0 and
10739 *POP1 may be updated.
10741 It is possible that we might detect that a comparison is either always
10742 true or always false. However, we do not perform general constant
10743 folding in combine, so this knowledge isn't useful. Such tautologies
10744 should have been detected earlier. Hence we ignore all such cases. */
10746 static enum rtx_code
10748 {
10755 /* Try a few ways of applying the same transformation to both operands. */
10757 {
10758 #ifndef WORD_REGISTER_OPERATIONS
10759 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10760 so check specially. */
10775 - (GET_MODE_BITSIZE
10777 {
10780 }
10781 #endif
10783 /* If both operands are the same constant shift, see if we can ignore the
10784 shift. We can if the shift is a rotate or if the bits shifted out of
10785 this shift are known to be zero for both inputs and if the type of
10786 comparison is compatible with the shift. */
10799 {
10812 else
10814 }
10816 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10817 SUBREGs are of the same mode, and, in both cases, the AND would
10818 be redundant if the comparison was done in the narrower mode,
10819 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10820 and the operand's possibly nonzero bits are 0xffffff01; in that case
10821 if we only care about QImode, we don't need the AND). This case
10822 occurs if the output mode of an scc insn is not SImode and
10823 STORE_FLAG_VALUE == 1 (e.g., the 386).
10825 Similarly, check for a case where the AND's are ZERO_EXTEND
10826 operations from some narrower mode even though a SUBREG is not
10827 present. */
10832 {
10850 {
10854 /* The resulting comparison is always unsigned since we masked
10855 off the original sign bit. */
10859 }
10866 {
10872 }
10876 }
10878 /* If both operands are NOT, we can strip off the outer operation
10879 and adjust the comparison code for swapped operands; similarly for
10880 NEG, except that this must be an equality comparison. */
10886 else
10888 }
10890 /* If the first operand is a constant, swap the operands and adjust the
10891 comparison code appropriately, but don't do this if the second operand
10892 is already a constant integer. */
10894 {
10897 }
10899 /* We now enter a loop during which we will try to simplify the comparison.
10900 For the most part, we only are concerned with comparisons with zero,
10901 but some things may really be comparisons with zero but not start
10902 out looking that way. */
10905 {
10912 HOST_WIDE_INT const_op;
10914 /* We only want to handle integral modes. This catches VOIDmode,
10915 CCmode, and the floating-point modes. An exception is that we
10916 can handle VOIDmode if OP0 is a COMPARE or a comparison
10917 operation. */
10924 /* Get the constant we are comparing against and turn off all bits
10925 not on in our mode. */
10931 /* If we are comparing against a constant power of two and the value
10932 being compared can only have that single bit nonzero (e.g., it was
10933 `and'ed with that bit), we can replace this with a comparison
10934 with zero. */
10941 {
10944 }
10946 /* Similarly, if we are comparing a value known to be either -1 or
10947 0 with -1, change it to the opposite comparison against zero. */
10953 {
10956 }
10958 /* Do some canonicalizations based on the comparison code. We prefer
10959 comparisons against zero and then prefer equality comparisons.
10960 If we can reduce the size of a constant, we will do that too. */
10963 {
10965 /* < C is equivalent to <= (C - 1) */
10967 {
10971 /* ... fall through to LE case below. */
10972 }
10973 else
10977 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10979 {
10983 }
10985 /* If we are doing a <= 0 comparison on a value known to have
10986 a zero sign bit, we can replace this with == 0. */
10995 /* >= C is equivalent to > (C - 1). */
10997 {
11001 /* ... fall through to GT below. */
11002 }
11003 else
11007 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11009 {
11013 }
11015 /* If we are doing a > 0 comparison on a value known to have
11016 a zero sign bit, we can replace this with != 0. */
11025 /* < C is equivalent to <= (C - 1). */
11027 {
11031 /* ... fall through ... */
11032 }
11034 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11037 {
11041 }
11042 else
11046 /* unsigned <= 0 is equivalent to == 0 */
11050 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11053 {
11056 }
11060 /* >= C is equivalent to > (C - 1). */
11062 {
11066 /* ... fall through ... */
11067 }
11069 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11072 {
11076 }
11077 else
11081 /* unsigned > 0 is equivalent to != 0 */
11085 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11088 {
11091 }
11096 }
11098 /* Compute some predicates to simplify code below. */
11105 /* If this is a sign bit comparison and we can do arithmetic in
11106 MODE, say that we will only be needing the sign bit of OP0. */
11114 /* Now try cases based on the opcode of OP0. If none of the cases
11115 does a "continue", we exit this loop immediately after the
11116 switch. */
11119 {
11121 /* If we are extracting a single bit from a variable position in
11122 a constant that has only a single bit set and are comparing it
11123 with zero, we can convert this into an equality comparison
11124 between the position and the location of the single bit. */
11125 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11126 have already reduced the shift count modulo the word size. */
11132 {
11134 {
11135 enum machine_mode new_mode
11139 else
11140 {
11143 }
11144 }
11150 /* Result is nonzero iff shift count is equal to I. */
11153 }
11155 /* ... fall through ... */
11160 {
11163 }
11167 /* If testing for equality, we can take the NOT of the constant. */
11170 {
11174 }
11176 /* If just looking at the sign bit, reverse the sense of the
11177 comparison. */
11179 {
11183 }
11187 /* If testing for equality, we can take the NEG of the constant. */
11190 {
11194 }
11196 /* The remaining cases only apply to comparisons with zero. */
11200 /* When X is ABS or is known positive,
11201 (neg X) is < 0 if and only if X != 0. */
11208 {
11212 }
11214 /* If we have NEG of something whose two high-order bits are the
11215 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11217 {
11221 }
11225 /* If we are testing equality and our count is a constant, we
11226 can perform the inverse operation on our RHS. */
11230 {
11234 }
11236 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11237 a particular bit. Convert it to an AND of a constant of that
11238 bit. This will be converted into a ZERO_EXTRACT. */
11242 {
11249 }
11251 /* Fall through. */
11254 /* ABS is ignorable inside an equality comparison with zero. */
11256 {
11259 }
11263 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11264 (compare FOO CONST) if CONST fits in FOO's mode and we
11265 are either testing inequality or have an unsigned
11266 comparison with ZERO_EXTEND or a signed comparison with
11267 SIGN_EXTEND. But don't do it if we don't have a compare
11268 insn of the given mode, since we'd have to revert it
11269 later on, and then we wouldn't know whether to sign- or
11270 zero-extend. */
11273 && ! unsigned_comparison_p
11279 {
11282 }
11286 /* Check for the case where we are comparing A - C1 with C2, that is
11288 (subreg:MODE (plus (A) (-C1))) op (C2)
11290 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11291 comparison in the wider mode. One of the following two conditions
11292 must be true in order for this to be valid:
11294 1. The mode extension results in the same bit pattern being added
11295 on both sides and the comparison is equality or unsigned. As
11296 C2 has been truncated to fit in MODE, the pattern can only be
11297 all 0s or all 1s.
11299 2. The mode extension results in the sign bit being copied on
11300 each side.
11302 The difficulty here is that we have predicates for A but not for
11303 (A - C1) so we need to check that C1 is within proper bounds so
11304 as to perturbate A as little as possible. */
11311 {
11320 /* (A - C1) zero-extends if it is positive and sign-extends
11321 if it is negative, C2 both zero- and sign-extends. */
11325 /* (A - C1) sign-extends if it is positive and 1-extends
11326 if it is negative, C2 both sign- and 1-extends. */
11333 /* (A - C1) always sign-extends, like C2. */
11337 {
11340 }
11341 }
11343 /* If the inner mode is narrower and we are extracting the low part,
11344 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11348 else
11351 /* ... fall through ... */
11360 {
11363 }
11367 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11368 this for equality comparisons due to pathological cases involving
11369 overflows. */
11373 {
11377 }
11379 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11382 {
11386 }
11390 /* We used to optimize signed comparisons against zero, but that
11391 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11392 arrive here as equality comparisons, or (GEU, LTU) are
11393 optimized away. No need to special-case them. */
11395 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11396 (eq B (minus A C)), whichever simplifies. We can only do
11397 this for equality comparisons due to pathological cases involving
11398 overflows. */
11402 {
11406 }
11411 {
11415 }
11417 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11418 of bits in X minus 1, is one iff X > 0. */
11424 {
11428 }
11432 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11433 if C is zero or B is a constant. */
11437 {
11441 }
11449 /* We can't do anything if OP0 is a condition code value, rather
11450 than an actual data value. */
11456 /* Get the two operands being compared. */
11459 else
11462 /* Check for the cases where we simply want the result of the
11463 earlier test or the opposite of that result. */
11467 && (STORE_FLAG_VALUE
11471 {
11475 else
11479 {
11484 }
11485 }
11489 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11490 iff X <= 0. */
11494 {
11498 }
11502 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11503 will be converted to a ZERO_EXTRACT later. */
11507 {
11508 op0 = simplify_and_const_int
11514 }
11516 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11517 zero and X is a comparison and C1 and C2 describe only bits set
11518 in STORE_FLAG_VALUE, we can compare with X. */
11526 {
11533 {
11536 }
11537 }
11539 /* If we are doing an equality comparison of an AND of a bit equal
11540 to the sign bit, replace this with a LT or GE comparison of
11541 the underlying value. */
11548 {
11552 }
11554 /* If this AND operation is really a ZERO_EXTEND from a narrower
11555 mode, the constant fits within that mode, and this is either an
11556 equality or unsigned comparison, try to do this comparison in
11557 the narrower mode.
11559 Note that in:
11561 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11562 -> (ne:DI (reg:SI 4) (const_int 0))
11564 unless TRULY_NOOP_TRUNCATION allows it or the register is
11565 known to hold a value of the required mode the
11566 transformation is invalid. */
11578 {
11581 }
11583 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11584 fits in both M1 and M2 and the SUBREG is either paradoxical
11585 or represents the low part, permute the SUBREG and the AND
11586 and try again. */
11588 {
11591 /* Require an integral mode, to avoid creating something like
11592 (AND:SF ...). */
11594 /* It is unsafe to commute the AND into the SUBREG if the
11595 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11596 not defined. As originally written the upper bits
11597 have a defined value due to the AND operation.
11598 However, if we commute the AND inside the SUBREG then
11599 they no longer have defined values and the meaning of
11600 the code has been changed. */
11602 #ifdef WORD_REGISTER_OPERATIONS
11605 #endif
11615 {
11621 }
11622 }
11624 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11628 {
11629 op0 = simplify_and_const_int
11633 }
11635 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11636 (eq (and (lshiftrt X) 1) 0).
11637 Also handle the case where (not X) is expressed using xor. */
11641 {
11652 {
11653 op0 = simplify_and_const_int
11659 }
11660 }
11664 /* If we have (compare (ashift FOO N) (const_int C)) and
11665 the high order N bits of FOO (N+1 if an inequality comparison)
11666 are known to be zero, we can do this by comparing FOO with C
11667 shifted right N bits so long as the low-order N bits of C are
11668 zero. */
11673 && ((const_op
11679 {
11680 /* We must perform a logical shift, not an arithmetic one,
11681 as we want the top N bits of C to be zero. */
11688 }
11690 /* If we are doing a sign bit comparison, it means we are testing
11691 a particular bit. Convert it to the appropriate AND. */
11694 {
11701 }
11703 /* If this an equality comparison with zero and we are shifting
11704 the low bit to the sign bit, we can convert this to an AND of the
11705 low-order bit. */
11710 {
11714 }
11718 /* If this is an equality comparison with zero, we can do this
11719 as a logical shift, which might be much simpler. */
11722 {
11727 }
11729 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11730 do the comparison in a narrower mode. */
11740 {
11743 }
11745 /* Likewise if OP0 is a PLUS of a sign extension with a
11746 constant, which is usually represented with the PLUS
11747 between the shifts. */
11759 {
11767 new_const);
11769 }
11771 /* ... fall through ... */
11773 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11774 the low order N bits of FOO are known to be zero, we can do this
11775 by comparing FOO with C shifted left N bits so long as no
11776 overflow occurs. */
11789 {
11790 /* If the shift was logical, then we must make the condition
11791 unsigned. */
11799 }
11801 /* If we are using this shift to extract just the sign bit, we
11802 can replace this with an LT or GE comparison. */
11808 {
11812 }
11817 }
11820 }
11822 /* Now make any compound operations involved in this comparison. Then,
11823 check for an outmost SUBREG on OP0 that is not doing anything or is
11824 paradoxical. The latter transformation must only be performed when
11825 it is known that the "extra" bits will be the same in op0 and op1 or
11826 that they don't matter. There are three cases to consider:
11828 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11829 care bits and we can assume they have any convenient value. So
11830 making the transformation is safe.
11832 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11833 In this case the upper bits of op0 are undefined. We should not make
11834 the simplification in that case as we do not know the contents of
11835 those bits.
11837 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11838 UNKNOWN. In that case we know those bits are zeros or ones. We must
11839 also be sure that they are the same as the upper bits of op1.
11841 We can never remove a SUBREG for a non-equality comparison because
11842 the sign bit is in a different place in the underlying object. */
11851 {
11854 {
11855 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11856 implemented. */
11858 {
11861 }
11862 }
11868 {
11874 }
11875 }
11877 /* We now do the opposite procedure: Some machines don't have compare
11878 insns in all modes. If OP0's mode is an integer mode smaller than a
11879 word and we can't do a compare in that mode, see if there is a larger
11880 mode for which we can do the compare. There are a number of cases in
11881 which we can use the wider mode. */
11892 {
11895 /* If this is a test for negative, we can make an explicit
11896 test of the sign bit. Test this first so we can use
11897 a paradoxical subreg to extend OP0. */
11901 {
11909 }
11911 /* If the only nonzero bits in OP0 and OP1 are those in the
11912 narrower mode and this is an equality or unsigned comparison,
11913 we can use the wider mode. Similarly for sign-extended
11914 values, in which case it is true for all comparisons. */
11931 {
11932 /* If OP0 is an AND and we don't have an AND in MODE either,
11933 make a new AND in the proper mode. */
11941 else
11942 {
11944 {
11947 }
11948 else
11949 {
11952 }
11954 }
11955 }
11956 }
11958 #ifdef CANONICALIZE_COMPARISON
11959 /* If this machine only supports a subset of valid comparisons, see if we
11960 can convert an unsupported one into a supported one. */
11962 #endif
11968 }
11969 \f
11970 /* Utility function for record_value_for_reg. Count number of
11971 rtxs in X. */
11972 static int
11974 {
11981 {
12001 }
12012 }
12013 \f
12014 /* Utility function for following routine. Called when X is part of a value
12015 being stored into last_set_value. Sets last_set_table_tick
12016 for each register mentioned. Similar to mention_regs in cse.c */
12018 static void
12020 {
12026 {
12032 {
12035 }
12038 }
12042 {
12043 /* Check for identical subexpressions. If x contains
12044 identical subexpression we only have to traverse one of
12045 them. */
12047 {
12048 /* Note that at this point x1 has already been
12049 processed. */
12053 /* If x0 and x1 are identical then there is no need to
12054 process x0. */
12058 /* If x0 is identical to a subexpression of x1 then while
12059 processing x1, x0 has already been processed. Thus we
12060 are done with x. */
12065 /* If x1 is identical to a subexpression of x0 then we
12066 still have to process the rest of x0. */
12069 {
12072 }
12073 }
12076 }
12080 }
12082 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12083 are saying that the register is clobbered and we no longer know its
12084 value. If INSN is zero, don't update reg_stat[].last_set; this is
12085 only permitted with VALUE also zero and is used to invalidate the
12086 register. */
12088 static void
12090 {
12096 /* If VALUE contains REG and we have a previous value for REG, substitute
12097 the previous value. */
12099 {
12100 rtx tem;
12102 /* Set things up so get_last_value is allowed to see anything set up to
12103 our insn. */
12107 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12108 it isn't going to be useful and will take a lot of time to process,
12109 so just use the CLOBBER. */
12112 {
12118 {
12119 /* If there are two or more occurrences of REG in VALUE,
12120 prevent the value from growing too much. */
12123 }
12126 }
12127 }
12129 /* For each register modified, show we don't know its value, that
12130 we don't know about its bitwise content, that its value has been
12131 updated, and that we don't know the location of the death of the
12132 register. */
12134 {
12146 }
12148 /* Mark registers that are being referenced in this value. */
12152 /* Now update the status of each register being set.
12153 If someone is using this register in this block, set this register
12154 to invalid since we will get confused between the two lives in this
12155 basic block. This makes using this register always invalid. In cse, we
12156 scan the table to invalidate all entries using this register, but this
12157 is too much work for us. */
12160 {
12166 else
12168 }
12170 /* The value being assigned might refer to X (like in "x++;"). In that
12171 case, we must replace it with (clobber (const_int 0)) to prevent
12172 infinite loops. */
12175 {
12179 }
12181 /* For the main register being modified, update the value, the mode, the
12182 nonzero bits, and the number of sign bit copies. */
12187 {
12195 rsp->last_set_sign_bit_copies
12197 }
12198 }
12200 /* Called via note_stores from record_dead_and_set_regs to handle one
12201 SET or CLOBBER in an insn. DATA is the instruction in which the
12202 set is occurring. */
12204 static void
12206 {
12213 {
12217 }
12220 {
12221 /* If we are setting the whole register, we know its value. Otherwise
12222 show that we don't know the value. We can handle SUBREG in
12223 some cases. */
12234 else
12236 }
12238 /* Ignore pushes, they clobber nothing. */
12241 }
12243 /* Update the records of when each REG was most recently set or killed
12244 for the things done by INSN. This is the last thing done in processing
12245 INSN in the combiner loop.
12247 We update reg_stat[], in particular fields last_set, last_set_value,
12248 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12249 last_death, and also the similar information mem_last_set (which insn
12250 most recently modified memory) and last_call_luid (which insn was the
12251 most recent subroutine call). */
12253 static void
12255 {
12256 rtx link;
12260 {
12263 {
12268 {
12273 }
12274 }
12277 }
12280 {
12283 {
12295 }
12299 /* We can't combine into a call pattern. Remember, though, that
12300 the return value register is set at this LUID. We could
12301 still replace a register with the return value from the
12302 wrong subroutine call! */
12304 }
12305 else
12307 }
12309 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12310 register present in the SUBREG, so for each such SUBREG go back and
12311 adjust nonzero and sign bit information of the registers that are
12312 known to have some zero/sign bits set.
12314 This is needed because when combine blows the SUBREGs away, the
12315 information on zero/sign bits is lost and further combines can be
12316 missed because of that. */
12318 static void
12320 {
12329 {
12338 {
12341 }
12345 {
12348 }
12351 {
12354 }
12355 else
12357 }
12358 }
12360 /* Check if X, a register, is known to contain a value already
12361 truncated to MODE. In this case we can use a subreg to refer to
12362 the truncated value even though in the generic case we would need
12363 an explicit truncation. */
12365 static bool
12367 {
12380 }
12382 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12383 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12384 might be able to turn a truncate into a subreg using this information.
12385 Return -1 if traversing *P is complete or 0 otherwise. */
12387 static int
12389 {
12395 {
12407 }
12408 /* ??? For hard-regs we now record everything. We might be able to
12409 optimize this using last_set_mode. */
12412 else
12420 {
12423 }
12426 }
12428 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12429 the modes they are used in. This can help truning TRUNCATEs into
12430 SUBREGs. */
12432 static void
12434 {
12436 }
12438 /* Scan X for promoted SUBREGs. For each one found,
12439 note what it implies to the registers used in it. */
12441 static void
12443 {
12448 else
12449 {
12455 {
12465 }
12466 }
12467 }
12468 \f
12469 /* Verify that all the registers and memory references mentioned in *LOC are
12470 still valid. *LOC was part of a value set in INSN when label_tick was
12471 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12472 the invalid references with (clobber (const_int 0)) and return 1. This
12473 replacement is useful because we often can get useful information about
12474 the form of a value (e.g., if it was produced by a shift that always
12475 produces -1 or 0) even though we don't know exactly what registers it
12476 was produced from. */
12478 static int
12480 {
12487 {
12493 {
12496 /* If this is a pseudo-register that was only set once and not
12497 live at the beginning of the function, it is always valid. */
12500 && (!REGNO_REG_SET_P
12503 {
12507 }
12508 }
12511 }
12512 /* If this is a memory reference, make sure that there were no stores after
12513 it that might have clobbered the value. We don't have alias info, so we
12514 assume any store invalidates it. Moreover, we only have local UIDs, so
12515 we also assume that there were stores in the intervening basic blocks. */
12518 {
12522 }
12525 {
12527 {
12528 /* Check for identical subexpressions. If x contains
12529 identical subexpression we only have to traverse one of
12530 them. */
12532 {
12533 /* Note that at this point x0 has already been checked
12534 and found valid. */
12538 /* If x0 and x1 are identical then x is also valid. */
12542 /* If x1 is identical to a subexpression of x0 then
12543 while checking x0, x1 has already been checked. Thus
12544 it is valid and so as x. */
12549 /* If x0 is identical to a subexpression of x1 then x is
12550 valid iff the rest of x1 is valid. */
12553 return
12557 }
12562 }
12568 }
12570 /* If we haven't found a reason for it to be invalid, it is valid. */
12572 }
12574 /* Get the last value assigned to X, if known. Some registers
12575 in the value may be replaced with (clobber (const_int 0)) if their value
12576 is known longer known reliably. */
12578 static rtx
12580 {
12582 rtx value;
12585 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12586 then convert it to the desired mode. If this is a paradoxical SUBREG,
12587 we cannot predict what values the "extra" bits might have. */
12602 /* If we don't have a value, or if it isn't for this basic block and
12603 it's either a hard register, set more than once, or it's a live
12604 at the beginning of the function, return 0.
12606 Because if it's not live at the beginning of the function then the reg
12607 is always set before being used (is never used without being set).
12608 And, if it's set only once, and it's always set before use, then all
12609 uses must have the same last value, even if it's not from this basic
12610 block. */
12616 || REGNO_REG_SET_P
12620 /* If the value was set in a later insn than the ones we are processing,
12621 we can't use it even if the register was only set once. */
12626 /* If the value has all its registers valid, return it. */
12630 /* Otherwise, make a copy and replace any invalid register with
12631 (clobber (const_int 0)). If that fails for some reason, return 0. */
12638 }
12639 \f
12640 /* Return nonzero if expression X refers to a REG or to memory
12641 that is set in an instruction more recent than FROM_LUID. */
12643 static int
12645 {
12651 {
12655 #ifdef PUSH_ROUNDING
12656 /* Don't allow uses of the stack pointer to be moved,
12657 because we don't know whether the move crosses a push insn. */
12660 #endif
12662 {
12668 }
12670 }
12678 {
12680 {
12685 }
12689 }
12691 }
12692 \f
12693 /* Define three variables used for communication between the following
12694 routines. */
12699 /* Function called via note_stores from reg_dead_at_p.
12701 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12702 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12704 static void
12706 {
12716 }
12718 /* Return nonzero if REG is known to be dead at INSN.
12720 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12721 referencing REG, it is dead. If we hit a SET referencing REG, it is
12722 live. Otherwise, see if it is live or dead at the start of the basic
12723 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12724 must be assumed to be always live. */
12726 static int
12728 {
12729 basic_block block;
12732 /* Set variables for reg_dead_at_p_1. */
12738 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12739 we allow the machine description to decide whether use-and-clobber
12740 patterns are OK. */
12742 {
12746 }
12748 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12749 beginning of basic block. */
12752 {
12754 {
12761 }
12767 }
12769 /* Look at live-in sets for the basic block that we were in. */
12775 }
12776 \f
12777 /* Note hard registers in X that are used. */
12779 static void
12781 {
12787 {
12798 #ifdef HAVE_cc0
12799 /* CC0 must die in the insn after it is set, so we don't need to take
12800 special note of it here. */
12802 #endif
12806 /* If we are clobbering a MEM, mark any hard registers inside the
12807 address as used. */
12814 /* A hard reg in a wide mode may really be multiple registers.
12815 If so, mark all of them just like the first. */
12817 {
12818 /* None of this applies to the stack, frame or arg pointers. */
12820 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12822 #endif
12823 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12825 #endif
12830 }
12834 {
12835 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12836 the address. */
12848 }
12853 }
12855 /* Recursively scan the operands of this expression. */
12857 {
12861 {
12865 {
12870 }
12871 }
12872 }
12873 }
12874 \f
12875 /* Remove register number REGNO from the dead registers list of INSN.
12877 Return the note used to record the death, if there was one. */
12879 rtx
12881 {
12888 }
12890 /* For each register (hardware or pseudo) used within expression X, if its
12891 death is in an instruction with luid between FROM_LUID (inclusive) and
12892 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12893 list headed by PNOTES.
12895 That said, don't move registers killed by maybe_kill_insn.
12897 This is done when X is being merged by combination into TO_INSN. These
12898 notes will then be distributed as needed. */
12900 static void
12903 {
12909 {
12913 /* Don't move the register if it gets killed in between from and to. */
12922 {
12925 /* It is possible for the call above to return 0. This can occur
12926 when last_death points to I2 or I1 that we combined with.
12927 In that case make a new note.
12929 We must also check for the case where X is a hard register
12930 and NOTE is a death note for a range of hard registers
12931 including X. In that case, we must put REG_DEAD notes for
12932 the remaining registers in place of NOTE. */
12937 {
12946 }
12948 /* If we didn't find any note, or if we found a REG_DEAD note that
12949 covers only part of the given reg, and we have a multi-reg hard
12950 register, then to be safe we must check for REG_DEAD notes
12951 for each register other than the first. They could have
12952 their own REG_DEAD notes lying around. */
12959 {
12966 else
12972 }
12975 {
12978 }
12979 else
12981 }
12984 }
12987 {
12992 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12993 that accesses one word of a multi-word item, some
12994 piece of everything register in the expression is used by
12995 this insn, so remove any old death. */
12996 /* ??? So why do we test for equality of the sizes? */
13005 {
13008 }
13010 /* If this is some other SUBREG, we know it replaces the entire
13011 value, so use that as the destination. */
13015 /* If this is a MEM, adjust deaths of anything used in the address.
13016 For a REG (the only other possibility), the entire value is
13017 being replaced so the old value is not used in this insn. */
13023 }
13032 {
13034 {
13039 }
13042 }
13043 }
13044 \f
13045 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13046 pattern of an insn. X must be a REG. */
13048 static int
13050 {
13054 {
13056 rtx target;
13063 else
13080 }
13088 }
13089 \f
13090 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13091 as appropriate. I3 and I2 are the insns resulting from the combination
13092 insns including FROM (I2 may be zero).
13094 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13095 not need REG_DEAD notes because they are being substituted for. This
13096 saves searching in the most common cases.
13098 Each note in the list is either ignored or placed on some insns, depending
13099 on the type of note. */
13101 static void
13104 {
13106 rtx tem;
13109 {
13114 {
13117 /* Doesn't matter much where we put this, as long as it's somewhere.
13118 It is preferable to keep these notes on branches, which is most
13119 likely to be i3. */
13124 /* Just get rid of this note, as it is unused later anyway. */
13130 else
13131 {
13134 }
13138 /* These notes must remain with the call or trapping instruction. */
13143 else
13144 {
13150 /* ??? Otherwise assume we've combined things such that we
13151 can now prove that the instructions can't trap. Drop the
13152 note in this case. */
13153 }
13158 /* These notes must remain with the call. It should not be
13159 possible for both I2 and I3 to be a call. */
13162 else
13163 {
13166 }
13170 /* Any clobbers for i3 may still exist, and so we must process
13171 REG_UNUSED notes from that insn.
13173 Any clobbers from i2 or i1 can only exist if they were added by
13174 recog_for_combine. In that case, recog_for_combine created the
13175 necessary REG_UNUSED notes. Trying to keep any original
13176 REG_UNUSED notes from these insns can cause incorrect output
13177 if it is for the same register as the original i3 dest.
13178 In that case, we will notice that the register is set in i3,
13179 and then add a REG_UNUSED note for the destination of i3, which
13180 is wrong. However, it is possible to have REG_UNUSED notes from
13181 i2 or i1 for register which were both used and clobbered, so
13182 we keep notes from i2 or i1 if they will turn into REG_DEAD
13183 notes. */
13185 /* If this register is set or clobbered in I3, put the note there
13186 unless there is one already. */
13188 {
13196 }
13197 /* Otherwise, if this register is used by I3, then this register
13198 now dies here, so we must put a REG_DEAD note here unless there
13199 is one already. */
13205 {
13208 }
13214 /* These notes say something about results of an insn. We can
13215 only support them if they used to be on I3 in which case they
13216 remain on I3. Otherwise they are ignored.
13218 If the note refers to an expression that is not a constant, we
13219 must also ignore the note since we cannot tell whether the
13220 equivalence is still true. It might be possible to do
13221 slightly better than this (we only have a problem if I2DEST
13222 or I1DEST is present in the expression), but it doesn't
13223 seem worth the trouble. */
13231 /* These notes say something about how a register is used. They must
13232 be present on any use of the register in I2 or I3. */
13237 {
13240 else
13242 }
13247 /* This can show up in several ways -- either directly in the
13248 pattern, or hidden off in the constant pool with (or without?)
13249 a REG_EQUAL note. */
13250 /* ??? Ignore the without-reg_equal-note problem for now. */
13262 {
13265 else
13267 }
13269 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13270 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13271 there. */
13276 {
13283 }
13289 {
13297 }
13301 /* This note says something about the value of a register prior
13302 to the execution of an insn. It is too much trouble to see
13303 if the note is still correct in all situations. It is better
13304 to simply delete it. */
13308 /* If we replaced the right hand side of FROM_INSN with a
13309 REG_EQUAL note, the original use of the dying register
13310 will not have been combined into I3 and I2. In such cases,
13311 FROM_INSN is guaranteed to be the first of the combined
13312 instructions, so we simply need to search back before
13313 FROM_INSN for the previous use or set of this register,
13314 then alter the notes there appropriately.
13316 If the register is used as an input in I3, it dies there.
13317 Similarly for I2, if it is nonzero and adjacent to I3.
13319 If the register is not used as an input in either I3 or I2
13320 and it is not one of the registers we were supposed to eliminate,
13321 there are two possibilities. We might have a non-adjacent I2
13322 or we might have somehow eliminated an additional register
13323 from a computation. For example, we might have had A & B where
13324 we discover that B will always be zero. In this case we will
13325 eliminate the reference to A.
13327 In both cases, we must search to see if we can find a previous
13328 use of A and put the death note there. */
13334 else
13335 {
13346 && !(i2mod
13348 i2mod_old_rhs)))
13353 }
13356 {
13360 {
13362 {
13366 }
13368 /* If the register is being set at TEM, see if that is all
13369 TEM is doing. If so, delete TEM. Otherwise, make this
13370 into a REG_UNUSED note instead. Don't delete sets to
13371 global register vars. */
13375 {
13378 #ifdef HAVE_cc0
13380 #endif
13388 ;
13390 /* Verify that it was the set, and not a clobber that
13391 modified the register.
13393 CC0 targets must be careful to maintain setter/user
13394 pairs. If we cannot delete the setter due to side
13395 effects, mark the user with an UNUSED note instead
13396 of deleting it. */
13400 #ifdef HAVE_cc0
13404 #endif
13405 )
13406 {
13407 /* Move the notes and links of TEM elsewhere.
13408 This might delete other dead insns recursively.
13409 First set the pattern to something that won't use
13410 any register. */
13424 #ifdef HAVE_cc0
13425 /* Delete the setter too. */
13427 {
13440 }
13441 #endif
13442 }
13443 else
13444 {
13447 /* If there isn't already a REG_UNUSED note, put one
13448 here. Do not place a REG_DEAD note, even if
13449 the register is also used here; that would not
13450 match the algorithm used in lifetime analysis
13451 and can cause the consistency check in the
13452 scheduler to fail. */
13457 }
13458 }
13462 {
13465 /* If we are doing a 3->2 combination, and we have a
13466 register which formerly died in i3 and was not used
13467 by i2, which now no longer dies in i3 and is used in
13468 i2 but does not die in i2, and place is between i2
13469 and i3, then we may need to move a link from place to
13470 i2. */
13472 && from_insn
13475 {
13479 }
13481 }
13485 }
13487 }
13489 /* If the register is set or already dead at PLACE, we needn't do
13490 anything with this note if it is still a REG_DEAD note.
13491 We check here if it is set at all, not if is it totally replaced,
13492 which is what `dead_or_set_p' checks, so also check for it being
13493 set partially. */
13496 {
13502 {
13503 /* Unless the register previously died in PLACE, clear
13504 last_death. [I no longer understand why this is
13505 being done.] */
13509 }
13510 else
13513 /* If this is a death note for a hard reg that is occupying
13514 multiple registers, ensure that we are still using all
13515 parts of the object. If we find a piece of the object
13516 that is unused, we must arrange for an appropriate REG_DEAD
13517 note to be added for it. However, we can't just emit a USE
13518 and tag the note to it, since the register might actually
13519 be dead; so we recourse, and the recursive call then finds
13520 the previous insn that used this register. */
13524 {
13536 {
13537 /* Put only REG_DEAD notes for pieces that are
13538 not already dead or set. */
13542 {
13549 {
13551 NULL_RTX);
13555 NULL_RTX);
13556 }
13562 {
13564 {
13568 }
13572 {
13575 }
13576 }
13578 }
13581 }
13582 }
13583 }
13587 /* Any other notes should not be present at this point in the
13588 compilation. */
13590 }
13593 {
13596 }
13600 }
13601 }
13602 \f
13603 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13604 I3, I2, and I1 to new locations. This is also called to add a link
13605 pointing at I3 when I3's destination is changed. */
13607 static void
13609 {
13613 {
13615 rtx insn;
13620 /* If the insn that this link points to is a NOTE or isn't a single
13621 set, ignore it. In the latter case, it isn't clear what we
13622 can do other than ignore the link, since we can't tell which
13623 register it was for. Such links wouldn't be used by combine
13624 anyway.
13626 It is not possible for the destination of the target of the link to
13627 have been changed by combine. The only potential of this is if we
13628 replace I3, I2, and I1 by I3 and I2. But in that case the
13629 destination of I2 also remains unchanged. */
13640 /* A LOG_LINK is defined as being placed on the first insn that uses
13641 a register and points to the insn that sets the register. Start
13642 searching at the next insn after the target of the link and stop
13643 when we reach a set of the register or the end of the basic block.
13645 Note that this correctly handles the link that used to point from
13646 I3 to I2. Also note that not much searching is typically done here
13647 since most links don't point very far away. */
13656 {
13660 }
13663 {
13666 }
13670 /* If we found a place to put the link, place it there unless there
13671 is already a link to the same insn as LINK at that point. */
13674 {
13675 rtx link2;
13682 {
13686 /* Set added_links_insn to the earliest insn we added a
13687 link to. */
13691 }
13692 }
13693 }
13694 }
13695 \f
13696 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13697 Check whether the expression pointer to by LOC is a register or
13698 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13699 Otherwise return zero. */
13701 static int
13703 {
13711 }
13713 /* Check for any register or memory mentioned in EQUIV that is not
13714 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13715 of EXPR where some registers may have been replaced by constants. */
13717 static bool
13719 {
13721 }
13722 \f
13723 void
13725 {
13726 fprintf
13728 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13730 }
13732 void
13734 {
13735 fprintf
13737 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13739 }
13740 \f
13741 static bool
13743 {
13745 }
13747 /* Try combining insns through substitution. */
13748 static unsigned int
13750 {
13759 rebuild_jump_labels_after_combine
13762 /* Combining insns may have turned an indirect jump into a
13763 direct jump. Rebuild the JUMP_LABEL fields of jumping
13764 instructions. */
13766 {
13771 }
13775 }
13778 {
13779 {
13780 RTL_PASS,
13792 TODO_dump_func |
13795 }
13796 };