1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
34 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36 #include "addresses.h"
39 /* Forward declarations */
40 static void set_of_1 (rtx
, const_rtx
, void *);
41 static bool covers_regno_p (const_rtx
, unsigned int);
42 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
43 static int computed_jump_p_1 (const_rtx
);
44 static void parms_set (rtx
, const_rtx
, void *);
46 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, machine_mode
,
47 const_rtx
, machine_mode
,
48 unsigned HOST_WIDE_INT
);
49 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, machine_mode
,
50 const_rtx
, machine_mode
,
51 unsigned HOST_WIDE_INT
);
52 static unsigned int cached_num_sign_bit_copies (const_rtx
, machine_mode
, const_rtx
,
55 static unsigned int num_sign_bit_copies1 (const_rtx
, machine_mode
, const_rtx
,
56 machine_mode
, unsigned int);
58 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
59 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
61 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
62 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
63 SIGN_EXTEND then while narrowing we also have to enforce the
64 representation and sign-extend the value to mode DESTINATION_REP.
66 If the value is already sign-extended to DESTINATION_REP mode we
67 can just switch to DESTINATION mode on it. For each pair of
68 integral modes SOURCE and DESTINATION, when truncating from SOURCE
69 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
70 contains the number of high-order bits in SOURCE that have to be
71 copies of the sign-bit so that we can do this mode-switch to
75 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
77 /* Store X into index I of ARRAY. ARRAY is known to have at least I
78 elements. Return the new base of ARRAY. */
81 typename
T::value_type
*
82 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
84 size_t i
, value_type x
)
86 if (base
== array
.stack
)
93 gcc_checking_assert (i
== LOCAL_ELEMS
);
94 /* A previous iteration might also have moved from the stack to the
95 heap, in which case the heap array will already be big enough. */
96 if (vec_safe_length (array
.heap
) <= i
)
97 vec_safe_grow (array
.heap
, i
+ 1);
98 base
= array
.heap
->address ();
99 memcpy (base
, array
.stack
, sizeof (array
.stack
));
100 base
[LOCAL_ELEMS
] = x
;
103 unsigned int length
= array
.heap
->length ();
106 gcc_checking_assert (base
== array
.heap
->address ());
112 gcc_checking_assert (i
== length
);
113 vec_safe_push (array
.heap
, x
);
114 return array
.heap
->address ();
118 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
119 number of elements added to the worklist. */
121 template <typename T
>
123 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
125 size_t end
, rtx_type x
)
127 enum rtx_code code
= GET_CODE (x
);
128 const char *format
= GET_RTX_FORMAT (code
);
129 size_t orig_end
= end
;
130 if (__builtin_expect (INSN_P (x
), false))
132 /* Put the pattern at the top of the queue, since that's what
133 we're likely to want most. It also allows for the SEQUENCE
135 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
136 if (format
[i
] == 'e')
138 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
139 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
142 base
= add_single_to_queue (array
, base
, end
++, subx
);
146 for (int i
= 0; format
[i
]; ++i
)
147 if (format
[i
] == 'e')
149 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
150 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
153 base
= add_single_to_queue (array
, base
, end
++, subx
);
155 else if (format
[i
] == 'E')
157 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
158 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
159 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
160 for (unsigned int j
= 0; j
< length
; j
++)
161 base
[end
++] = T::get_value (vec
[j
]);
163 for (unsigned int j
= 0; j
< length
; j
++)
164 base
= add_single_to_queue (array
, base
, end
++,
165 T::get_value (vec
[j
]));
166 if (code
== SEQUENCE
&& end
== length
)
167 /* If the subrtxes of the sequence fill the entire array then
168 we know that no other parts of a containing insn are queued.
169 The caller is therefore iterating over the sequence as a
170 PATTERN (...), so we also want the patterns of the
172 for (unsigned int j
= 0; j
< length
; j
++)
174 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
176 base
[j
] = T::get_value (PATTERN (x
));
179 return end
- orig_end
;
182 template <typename T
>
184 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
186 vec_free (array
.heap
);
189 template <typename T
>
190 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
192 template class generic_subrtx_iterator
<const_rtx_accessor
>;
193 template class generic_subrtx_iterator
<rtx_var_accessor
>;
194 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
196 /* Return 1 if the value of X is unstable
197 (would be different at a different point in the program).
198 The frame pointer, arg pointer, etc. are considered stable
199 (within one function) and so is anything marked `unchanging'. */
202 rtx_unstable_p (const_rtx x
)
204 const RTX_CODE code
= GET_CODE (x
);
211 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
220 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
221 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
222 /* The arg pointer varies if it is not a fixed register. */
223 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
225 /* ??? When call-clobbered, the value is stable modulo the restore
226 that must happen after a call. This currently screws up local-alloc
227 into believing that the restore is not needed. */
228 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
233 if (MEM_VOLATILE_P (x
))
242 fmt
= GET_RTX_FORMAT (code
);
243 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
246 if (rtx_unstable_p (XEXP (x
, i
)))
249 else if (fmt
[i
] == 'E')
252 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
253 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
260 /* Return 1 if X has a value that can vary even between two
261 executions of the program. 0 means X can be compared reliably
262 against certain constants or near-constants.
263 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
264 zero, we are slightly more conservative.
265 The frame pointer and the arg pointer are considered constant. */
268 rtx_varies_p (const_rtx x
, bool for_alias
)
281 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
290 /* Note that we have to test for the actual rtx used for the frame
291 and arg pointers and not just the register number in case we have
292 eliminated the frame and/or arg pointer and are using it
294 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
295 /* The arg pointer varies if it is not a fixed register. */
296 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
298 if (x
== pic_offset_table_rtx
299 /* ??? When call-clobbered, the value is stable modulo the restore
300 that must happen after a call. This currently screws up
301 local-alloc into believing that the restore is not needed, so we
302 must return 0 only if we are called from alias analysis. */
303 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
308 /* The operand 0 of a LO_SUM is considered constant
309 (in fact it is related specifically to operand 1)
310 during alias analysis. */
311 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
312 || rtx_varies_p (XEXP (x
, 1), for_alias
);
315 if (MEM_VOLATILE_P (x
))
324 fmt
= GET_RTX_FORMAT (code
);
325 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
328 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
331 else if (fmt
[i
] == 'E')
334 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
335 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
342 /* Compute an approximation for the offset between the register
343 FROM and TO for the current function, as it was at the start
347 get_initial_register_offset (int from
, int to
)
349 static const struct elim_table_t
353 } table
[] = ELIMINABLE_REGS
;
354 HOST_WIDE_INT offset1
, offset2
;
360 /* It is not safe to call INITIAL_ELIMINATION_OFFSET
361 before the reload pass. We need to give at least
362 an estimation for the resulting frame size. */
363 if (! reload_completed
)
365 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
366 #if !STACK_GROWS_DOWNWARD
369 if (to
== STACK_POINTER_REGNUM
)
371 else if (from
== STACK_POINTER_REGNUM
)
377 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
378 if (table
[i
].from
== from
)
380 if (table
[i
].to
== to
)
382 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
386 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
388 if (table
[j
].to
== to
389 && table
[j
].from
== table
[i
].to
)
391 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
393 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
395 return offset1
+ offset2
;
397 if (table
[j
].from
== to
398 && table
[j
].to
== table
[i
].to
)
400 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
402 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
404 return offset1
- offset2
;
408 else if (table
[i
].to
== from
)
410 if (table
[i
].from
== to
)
412 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
416 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
418 if (table
[j
].to
== to
419 && table
[j
].from
== table
[i
].from
)
421 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
423 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
425 return - offset1
+ offset2
;
427 if (table
[j
].from
== to
428 && table
[j
].to
== table
[i
].from
)
430 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
432 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
434 return - offset1
- offset2
;
439 /* If the requested register combination was not found,
440 try a different more simple combination. */
441 if (from
== ARG_POINTER_REGNUM
)
442 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
443 else if (to
== ARG_POINTER_REGNUM
)
444 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
445 else if (from
== HARD_FRAME_POINTER_REGNUM
)
446 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
447 else if (to
== HARD_FRAME_POINTER_REGNUM
)
448 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
453 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
454 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
455 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
456 references on strict alignment machines. */
459 rtx_addr_can_trap_p_1 (const_rtx x
, HOST_WIDE_INT offset
, HOST_WIDE_INT size
,
460 machine_mode mode
, bool unaligned_mems
)
462 enum rtx_code code
= GET_CODE (x
);
464 /* The offset must be a multiple of the mode size if we are considering
465 unaligned memory references on strict alignment machines. */
466 if (STRICT_ALIGNMENT
&& unaligned_mems
&& GET_MODE_SIZE (mode
) != 0)
468 HOST_WIDE_INT actual_offset
= offset
;
470 #ifdef SPARC_STACK_BOUNDARY_HACK
471 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
472 the real alignment of %sp. However, when it does this, the
473 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
474 if (SPARC_STACK_BOUNDARY_HACK
475 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
476 actual_offset
-= STACK_POINTER_OFFSET
;
479 if (actual_offset
% GET_MODE_SIZE (mode
) != 0)
486 if (SYMBOL_REF_WEAK (x
))
488 if (!CONSTANT_POOL_ADDRESS_P (x
))
491 HOST_WIDE_INT decl_size
;
496 size
= GET_MODE_SIZE (mode
);
500 /* If the size of the access or of the symbol is unknown,
502 decl
= SYMBOL_REF_DECL (x
);
504 /* Else check that the access is in bounds. TODO: restructure
505 expr_size/tree_expr_size/int_expr_size and just use the latter. */
508 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
509 decl_size
= (tree_fits_shwi_p (DECL_SIZE_UNIT (decl
))
510 ? tree_to_shwi (DECL_SIZE_UNIT (decl
))
512 else if (TREE_CODE (decl
) == STRING_CST
)
513 decl_size
= TREE_STRING_LENGTH (decl
);
514 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
515 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
519 return (decl_size
<= 0 ? offset
!= 0 : offset
+ size
> decl_size
);
528 /* Stack references are assumed not to trap, but we need to deal with
529 nonsensical offsets. */
530 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
531 || x
== stack_pointer_rtx
532 /* The arg pointer varies if it is not a fixed register. */
533 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
536 HOST_WIDE_INT red_zone_size
= RED_ZONE_SIZE
;
538 HOST_WIDE_INT red_zone_size
= 0;
540 HOST_WIDE_INT stack_boundary
= PREFERRED_STACK_BOUNDARY
542 HOST_WIDE_INT low_bound
, high_bound
;
545 size
= GET_MODE_SIZE (mode
);
549 if (x
== frame_pointer_rtx
)
551 if (FRAME_GROWS_DOWNWARD
)
553 high_bound
= STARTING_FRAME_OFFSET
;
554 low_bound
= high_bound
- get_frame_size ();
558 low_bound
= STARTING_FRAME_OFFSET
;
559 high_bound
= low_bound
+ get_frame_size ();
562 else if (x
== hard_frame_pointer_rtx
)
564 HOST_WIDE_INT sp_offset
565 = get_initial_register_offset (STACK_POINTER_REGNUM
,
566 HARD_FRAME_POINTER_REGNUM
);
567 HOST_WIDE_INT ap_offset
568 = get_initial_register_offset (ARG_POINTER_REGNUM
,
569 HARD_FRAME_POINTER_REGNUM
);
571 #if STACK_GROWS_DOWNWARD
572 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
573 high_bound
= ap_offset
574 + FIRST_PARM_OFFSET (current_function_decl
)
575 #if !ARGS_GROW_DOWNWARD
580 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
581 low_bound
= ap_offset
582 + FIRST_PARM_OFFSET (current_function_decl
)
583 #if ARGS_GROW_DOWNWARD
589 else if (x
== stack_pointer_rtx
)
591 HOST_WIDE_INT ap_offset
592 = get_initial_register_offset (ARG_POINTER_REGNUM
,
593 STACK_POINTER_REGNUM
);
595 #if STACK_GROWS_DOWNWARD
596 low_bound
= - red_zone_size
- stack_boundary
;
597 high_bound
= ap_offset
598 + FIRST_PARM_OFFSET (current_function_decl
)
599 #if !ARGS_GROW_DOWNWARD
604 high_bound
= red_zone_size
+ stack_boundary
;
605 low_bound
= ap_offset
606 + FIRST_PARM_OFFSET (current_function_decl
)
607 #if ARGS_GROW_DOWNWARD
615 /* We assume that accesses are safe to at least the
617 Examples are varargs and __builtin_return_address. */
618 #if ARGS_GROW_DOWNWARD
619 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
621 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
622 - crtl
->args
.size
- stack_boundary
;
624 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
626 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
627 + crtl
->args
.size
+ stack_boundary
;
631 if (offset
>= low_bound
&& offset
<= high_bound
- size
)
635 /* All of the virtual frame registers are stack references. */
636 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
637 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
642 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
643 mode
, unaligned_mems
);
646 /* An address is assumed not to trap if:
647 - it is the pic register plus a constant. */
648 if (XEXP (x
, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x
, 1)))
651 /* - or it is an address that can't trap plus a constant integer. */
652 if (CONST_INT_P (XEXP (x
, 1))
653 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
654 size
, mode
, unaligned_mems
))
661 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
662 mode
, unaligned_mems
);
669 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
670 mode
, unaligned_mems
);
676 /* If it isn't one of the case above, it can cause a trap. */
680 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
683 rtx_addr_can_trap_p (const_rtx x
)
685 return rtx_addr_can_trap_p_1 (x
, 0, 0, VOIDmode
, false);
688 /* Return true if X is an address that is known to not be zero. */
691 nonzero_address_p (const_rtx x
)
693 const enum rtx_code code
= GET_CODE (x
);
698 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
704 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
705 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
706 || x
== stack_pointer_rtx
707 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
709 /* All of the virtual frame registers are stack references. */
710 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
711 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
716 return nonzero_address_p (XEXP (x
, 0));
719 /* Handle PIC references. */
720 if (XEXP (x
, 0) == pic_offset_table_rtx
721 && CONSTANT_P (XEXP (x
, 1)))
726 /* Similar to the above; allow positive offsets. Further, since
727 auto-inc is only allowed in memories, the register must be a
729 if (CONST_INT_P (XEXP (x
, 1))
730 && INTVAL (XEXP (x
, 1)) > 0)
732 return nonzero_address_p (XEXP (x
, 0));
735 /* Similarly. Further, the offset is always positive. */
742 return nonzero_address_p (XEXP (x
, 0));
745 return nonzero_address_p (XEXP (x
, 1));
751 /* If it isn't one of the case above, might be zero. */
755 /* Return 1 if X refers to a memory location whose address
756 cannot be compared reliably with constant addresses,
757 or if X refers to a BLKmode memory object.
758 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
759 zero, we are slightly more conservative. */
762 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
773 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
775 fmt
= GET_RTX_FORMAT (code
);
776 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
779 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
782 else if (fmt
[i
] == 'E')
785 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
786 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
792 /* Return the CALL in X if there is one. */
795 get_call_rtx_from (rtx x
)
799 if (GET_CODE (x
) == PARALLEL
)
800 x
= XVECEXP (x
, 0, 0);
801 if (GET_CODE (x
) == SET
)
803 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
808 /* Return the value of the integer term in X, if one is apparent;
810 Only obvious integer terms are detected.
811 This is used in cse.c with the `related_value' field. */
814 get_integer_term (const_rtx x
)
816 if (GET_CODE (x
) == CONST
)
819 if (GET_CODE (x
) == MINUS
820 && CONST_INT_P (XEXP (x
, 1)))
821 return - INTVAL (XEXP (x
, 1));
822 if (GET_CODE (x
) == PLUS
823 && CONST_INT_P (XEXP (x
, 1)))
824 return INTVAL (XEXP (x
, 1));
828 /* If X is a constant, return the value sans apparent integer term;
830 Only obvious integer terms are detected. */
833 get_related_value (const_rtx x
)
835 if (GET_CODE (x
) != CONST
)
838 if (GET_CODE (x
) == PLUS
839 && CONST_INT_P (XEXP (x
, 1)))
841 else if (GET_CODE (x
) == MINUS
842 && CONST_INT_P (XEXP (x
, 1)))
847 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
848 to somewhere in the same object or object_block as SYMBOL. */
851 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
855 if (GET_CODE (symbol
) != SYMBOL_REF
)
863 if (CONSTANT_POOL_ADDRESS_P (symbol
)
864 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
867 decl
= SYMBOL_REF_DECL (symbol
);
868 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
872 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
873 && SYMBOL_REF_BLOCK (symbol
)
874 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
875 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
876 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
882 /* Split X into a base and a constant offset, storing them in *BASE_OUT
883 and *OFFSET_OUT respectively. */
886 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
888 if (GET_CODE (x
) == CONST
)
891 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
893 *base_out
= XEXP (x
, 0);
894 *offset_out
= XEXP (x
, 1);
899 *offset_out
= const0_rtx
;
902 /* Return the number of places FIND appears within X. If COUNT_DEST is
903 zero, we do not count occurrences inside the destination of a SET. */
906 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
910 const char *format_ptr
;
929 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
931 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
935 if (MEM_P (find
) && rtx_equal_p (x
, find
))
940 if (SET_DEST (x
) == find
&& ! count_dest
)
941 return count_occurrences (SET_SRC (x
), find
, count_dest
);
948 format_ptr
= GET_RTX_FORMAT (code
);
951 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
953 switch (*format_ptr
++)
956 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
960 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
961 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
969 /* Return TRUE if OP is a register or subreg of a register that
970 holds an unsigned quantity. Otherwise, return FALSE. */
973 unsigned_reg_p (rtx op
)
977 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
980 if (GET_CODE (op
) == SUBREG
981 && SUBREG_PROMOTED_SIGN (op
))
988 /* Nonzero if register REG appears somewhere within IN.
989 Also works if REG is not a register; in this case it checks
990 for a subexpression of IN that is Lisp "equal" to REG. */
993 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1005 if (GET_CODE (in
) == LABEL_REF
)
1006 return reg
== label_ref_label (in
);
1008 code
= GET_CODE (in
);
1012 /* Compare registers by number. */
1014 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1016 /* These codes have no constituent expressions
1024 /* These are kept unique for a given value. */
1031 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1034 fmt
= GET_RTX_FORMAT (code
);
1036 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1041 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1042 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1045 else if (fmt
[i
] == 'e'
1046 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1052 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1053 no CODE_LABEL insn. */
1056 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1061 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1067 /* Nonzero if register REG is used in an insn between
1068 FROM_INSN and TO_INSN (exclusive of those two). */
1071 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1072 const rtx_insn
*to_insn
)
1076 if (from_insn
== to_insn
)
1079 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1080 if (NONDEBUG_INSN_P (insn
)
1081 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1082 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1087 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1088 is entirely replaced by a new value and the only use is as a SET_DEST,
1089 we do not consider it a reference. */
1092 reg_referenced_p (const_rtx x
, const_rtx body
)
1096 switch (GET_CODE (body
))
1099 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1102 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1103 of a REG that occupies all of the REG, the insn references X if
1104 it is mentioned in the destination. */
1105 if (GET_CODE (SET_DEST (body
)) != CC0
1106 && GET_CODE (SET_DEST (body
)) != PC
1107 && !REG_P (SET_DEST (body
))
1108 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1109 && REG_P (SUBREG_REG (SET_DEST (body
)))
1110 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body
))))
1111 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
1112 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body
)))
1113 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
1114 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1119 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1120 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1127 return reg_overlap_mentioned_p (x
, body
);
1130 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1133 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1136 case UNSPEC_VOLATILE
:
1137 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1138 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1143 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1144 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1149 if (MEM_P (XEXP (body
, 0)))
1150 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1155 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1157 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1164 /* Nonzero if register REG is set or clobbered in an insn between
1165 FROM_INSN and TO_INSN (exclusive of those two). */
1168 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1169 const rtx_insn
*to_insn
)
1171 const rtx_insn
*insn
;
1173 if (from_insn
== to_insn
)
1176 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1177 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1182 /* Return true if REG is set or clobbered inside INSN. */
1185 reg_set_p (const_rtx reg
, const_rtx insn
)
1187 /* After delay slot handling, call and branch insns might be in a
1188 sequence. Check all the elements there. */
1189 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1191 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1192 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1198 /* We can be passed an insn or part of one. If we are passed an insn,
1199 check if a side-effect of the insn clobbers REG. */
1201 && (FIND_REG_INC_NOTE (insn
, reg
)
1204 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1205 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1206 GET_MODE (reg
), REGNO (reg
)))
1208 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1211 return set_of (reg
, insn
) != NULL_RTX
;
1214 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1215 only if none of them are modified between START and END. Return 1 if
1216 X contains a MEM; this routine does use memory aliasing. */
1219 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1221 const enum rtx_code code
= GET_CODE (x
);
1242 if (modified_between_p (XEXP (x
, 0), start
, end
))
1244 if (MEM_READONLY_P (x
))
1246 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1247 if (memory_modified_in_insn_p (x
, insn
))
1252 return reg_set_between_p (x
, start
, end
);
1258 fmt
= GET_RTX_FORMAT (code
);
1259 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1261 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1264 else if (fmt
[i
] == 'E')
1265 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1266 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1273 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1274 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1275 does use memory aliasing. */
1278 modified_in_p (const_rtx x
, const_rtx insn
)
1280 const enum rtx_code code
= GET_CODE (x
);
1297 if (modified_in_p (XEXP (x
, 0), insn
))
1299 if (MEM_READONLY_P (x
))
1301 if (memory_modified_in_insn_p (x
, insn
))
1306 return reg_set_p (x
, insn
);
1312 fmt
= GET_RTX_FORMAT (code
);
1313 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1315 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1318 else if (fmt
[i
] == 'E')
1319 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1320 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1327 /* Helper function for set_of. */
1335 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1337 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1338 if (rtx_equal_p (x
, data
->pat
)
1339 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1343 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1344 (either directly or via STRICT_LOW_PART and similar modifiers). */
1346 set_of (const_rtx pat
, const_rtx insn
)
1348 struct set_of_data data
;
1349 data
.found
= NULL_RTX
;
1351 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1355 /* Add all hard register in X to *PSET. */
1357 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1359 subrtx_iterator::array_type array
;
1360 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1362 const_rtx x
= *iter
;
1363 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1364 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1368 /* This function, called through note_stores, collects sets and
1369 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1372 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1374 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1375 if (REG_P (x
) && HARD_REGISTER_P (x
))
1376 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1379 /* Examine INSN, and compute the set of hard registers written by it.
1380 Store it in *PSET. Should only be called after reload. */
1382 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1386 CLEAR_HARD_REG_SET (*pset
);
1387 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1391 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1393 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1394 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1396 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1397 if (REG_NOTE_KIND (link
) == REG_INC
)
1398 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1401 /* Like record_hard_reg_sets, but called through note_uses. */
1403 record_hard_reg_uses (rtx
*px
, void *data
)
1405 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1408 /* Given an INSN, return a SET expression if this insn has only a single SET.
1409 It may also have CLOBBERs, USEs, or SET whose output
1410 will not be used, which we ignore. */
1413 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1416 int set_verified
= 1;
1419 if (GET_CODE (pat
) == PARALLEL
)
1421 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1423 rtx sub
= XVECEXP (pat
, 0, i
);
1424 switch (GET_CODE (sub
))
1431 /* We can consider insns having multiple sets, where all
1432 but one are dead as single set insns. In common case
1433 only single set is present in the pattern so we want
1434 to avoid checking for REG_UNUSED notes unless necessary.
1436 When we reach set first time, we just expect this is
1437 the single set we are looking for and only when more
1438 sets are found in the insn, we check them. */
1441 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1442 && !side_effects_p (set
))
1448 set
= sub
, set_verified
= 0;
1449 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1450 || side_effects_p (sub
))
1462 /* Given an INSN, return nonzero if it has more than one SET, else return
1466 multiple_sets (const_rtx insn
)
1471 /* INSN must be an insn. */
1472 if (! INSN_P (insn
))
1475 /* Only a PARALLEL can have multiple SETs. */
1476 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1478 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1479 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1481 /* If we have already found a SET, then return now. */
1489 /* Either zero or one SET. */
1493 /* Return nonzero if the destination of SET equals the source
1494 and there are no side effects. */
1497 set_noop_p (const_rtx set
)
1499 rtx src
= SET_SRC (set
);
1500 rtx dst
= SET_DEST (set
);
1502 if (dst
== pc_rtx
&& src
== pc_rtx
)
1505 if (MEM_P (dst
) && MEM_P (src
))
1506 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1508 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1509 return rtx_equal_p (XEXP (dst
, 0), src
)
1510 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1511 && !side_effects_p (src
);
1513 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1514 dst
= XEXP (dst
, 0);
1516 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1518 if (SUBREG_BYTE (src
) != SUBREG_BYTE (dst
))
1520 src
= SUBREG_REG (src
);
1521 dst
= SUBREG_REG (dst
);
1524 /* It is a NOOP if destination overlaps with selected src vector
1526 if (GET_CODE (src
) == VEC_SELECT
1527 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1528 && HARD_REGISTER_P (XEXP (src
, 0))
1529 && HARD_REGISTER_P (dst
))
1532 rtx par
= XEXP (src
, 1);
1533 rtx src0
= XEXP (src
, 0);
1534 int c0
= INTVAL (XVECEXP (par
, 0, 0));
1535 HOST_WIDE_INT offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1537 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1538 if (INTVAL (XVECEXP (par
, 0, i
)) != c0
+ i
)
1541 simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1542 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1545 return (REG_P (src
) && REG_P (dst
)
1546 && REGNO (src
) == REGNO (dst
));
1549 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1553 noop_move_p (const rtx_insn
*insn
)
1555 rtx pat
= PATTERN (insn
);
1557 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1560 /* Insns carrying these notes are useful later on. */
1561 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1564 /* Check the code to be executed for COND_EXEC. */
1565 if (GET_CODE (pat
) == COND_EXEC
)
1566 pat
= COND_EXEC_CODE (pat
);
1568 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1571 if (GET_CODE (pat
) == PARALLEL
)
1574 /* If nothing but SETs of registers to themselves,
1575 this insn can also be deleted. */
1576 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1578 rtx tem
= XVECEXP (pat
, 0, i
);
1580 if (GET_CODE (tem
) == USE
1581 || GET_CODE (tem
) == CLOBBER
)
1584 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1594 /* Return nonzero if register in range [REGNO, ENDREGNO)
1595 appears either explicitly or implicitly in X
1596 other than being stored into.
1598 References contained within the substructure at LOC do not count.
1599 LOC may be zero, meaning don't ignore anything. */
1602 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1606 unsigned int x_regno
;
1611 /* The contents of a REG_NONNEG note is always zero, so we must come here
1612 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1616 code
= GET_CODE (x
);
1621 x_regno
= REGNO (x
);
1623 /* If we modifying the stack, frame, or argument pointer, it will
1624 clobber a virtual register. In fact, we could be more precise,
1625 but it isn't worth it. */
1626 if ((x_regno
== STACK_POINTER_REGNUM
1627 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1628 && x_regno
== ARG_POINTER_REGNUM
)
1629 || x_regno
== FRAME_POINTER_REGNUM
)
1630 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1633 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1636 /* If this is a SUBREG of a hard reg, we can see exactly which
1637 registers are being modified. Otherwise, handle normally. */
1638 if (REG_P (SUBREG_REG (x
))
1639 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1641 unsigned int inner_regno
= subreg_regno (x
);
1642 unsigned int inner_endregno
1643 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1644 ? subreg_nregs (x
) : 1);
1646 return endregno
> inner_regno
&& regno
< inner_endregno
;
1652 if (&SET_DEST (x
) != loc
1653 /* Note setting a SUBREG counts as referring to the REG it is in for
1654 a pseudo but not for hard registers since we can
1655 treat each word individually. */
1656 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1657 && loc
!= &SUBREG_REG (SET_DEST (x
))
1658 && REG_P (SUBREG_REG (SET_DEST (x
)))
1659 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1660 && refers_to_regno_p (regno
, endregno
,
1661 SUBREG_REG (SET_DEST (x
)), loc
))
1662 || (!REG_P (SET_DEST (x
))
1663 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1666 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1675 /* X does not match, so try its subexpressions. */
1677 fmt
= GET_RTX_FORMAT (code
);
1678 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1680 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1688 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1691 else if (fmt
[i
] == 'E')
1694 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1695 if (loc
!= &XVECEXP (x
, i
, j
)
1696 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1703 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1704 we check if any register number in X conflicts with the relevant register
1705 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1706 contains a MEM (we don't bother checking for memory addresses that can't
1707 conflict because we expect this to be a rare case. */
1710 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1712 unsigned int regno
, endregno
;
1714 /* If either argument is a constant, then modifying X can not
1715 affect IN. Here we look at IN, we can profitably combine
1716 CONSTANT_P (x) with the switch statement below. */
1717 if (CONSTANT_P (in
))
1721 switch (GET_CODE (x
))
1723 case STRICT_LOW_PART
:
1726 /* Overly conservative. */
1731 regno
= REGNO (SUBREG_REG (x
));
1732 if (regno
< FIRST_PSEUDO_REGISTER
)
1733 regno
= subreg_regno (x
);
1734 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1735 ? subreg_nregs (x
) : 1);
1740 endregno
= END_REGNO (x
);
1742 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1752 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1753 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1756 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1759 else if (fmt
[i
] == 'E')
1762 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1763 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1773 return reg_mentioned_p (x
, in
);
1779 /* If any register in here refers to it we return true. */
1780 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1781 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1782 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1788 gcc_assert (CONSTANT_P (x
));
1793 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1794 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1795 ignored by note_stores, but passed to FUN.
1797 FUN receives three arguments:
1798 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1799 2. the SET or CLOBBER rtx that does the store,
1800 3. the pointer DATA provided to note_stores.
1802 If the item being stored in or clobbered is a SUBREG of a hard register,
1803 the SUBREG will be passed. */
1806 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1810 if (GET_CODE (x
) == COND_EXEC
)
1811 x
= COND_EXEC_CODE (x
);
1813 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1815 rtx dest
= SET_DEST (x
);
1817 while ((GET_CODE (dest
) == SUBREG
1818 && (!REG_P (SUBREG_REG (dest
))
1819 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1820 || GET_CODE (dest
) == ZERO_EXTRACT
1821 || GET_CODE (dest
) == STRICT_LOW_PART
)
1822 dest
= XEXP (dest
, 0);
1824 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1825 each of whose first operand is a register. */
1826 if (GET_CODE (dest
) == PARALLEL
)
1828 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1829 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1830 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1833 (*fun
) (dest
, x
, data
);
1836 else if (GET_CODE (x
) == PARALLEL
)
1837 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1838 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1841 /* Like notes_stores, but call FUN for each expression that is being
1842 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1843 FUN for each expression, not any interior subexpressions. FUN receives a
1844 pointer to the expression and the DATA passed to this function.
1846 Note that this is not quite the same test as that done in reg_referenced_p
1847 since that considers something as being referenced if it is being
1848 partially set, while we do not. */
1851 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1856 switch (GET_CODE (body
))
1859 (*fun
) (&COND_EXEC_TEST (body
), data
);
1860 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1864 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1865 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1869 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1870 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1874 (*fun
) (&XEXP (body
, 0), data
);
1878 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1879 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1883 (*fun
) (&TRAP_CONDITION (body
), data
);
1887 (*fun
) (&XEXP (body
, 0), data
);
1891 case UNSPEC_VOLATILE
:
1892 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1893 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1897 if (MEM_P (XEXP (body
, 0)))
1898 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1903 rtx dest
= SET_DEST (body
);
1905 /* For sets we replace everything in source plus registers in memory
1906 expression in store and operands of a ZERO_EXTRACT. */
1907 (*fun
) (&SET_SRC (body
), data
);
1909 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1911 (*fun
) (&XEXP (dest
, 1), data
);
1912 (*fun
) (&XEXP (dest
, 2), data
);
1915 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1916 dest
= XEXP (dest
, 0);
1919 (*fun
) (&XEXP (dest
, 0), data
);
1924 /* All the other possibilities never store. */
1925 (*fun
) (pbody
, data
);
1930 /* Return nonzero if X's old contents don't survive after INSN.
1931 This will be true if X is (cc0) or if X is a register and
1932 X dies in INSN or because INSN entirely sets X.
1934 "Entirely set" means set directly and not through a SUBREG, or
1935 ZERO_EXTRACT, so no trace of the old contents remains.
1936 Likewise, REG_INC does not count.
1938 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1939 but for this use that makes no difference, since regs don't overlap
1940 during their lifetimes. Therefore, this function may be used
1941 at any time after deaths have been computed.
1943 If REG is a hard reg that occupies multiple machine registers, this
1944 function will only return 1 if each of those registers will be replaced
1948 dead_or_set_p (const rtx_insn
*insn
, const_rtx x
)
1950 unsigned int regno
, end_regno
;
1953 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1954 if (GET_CODE (x
) == CC0
)
1957 gcc_assert (REG_P (x
));
1960 end_regno
= END_REGNO (x
);
1961 for (i
= regno
; i
< end_regno
; i
++)
1962 if (! dead_or_set_regno_p (insn
, i
))
1968 /* Return TRUE iff DEST is a register or subreg of a register and
1969 doesn't change the number of words of the inner register, and any
1970 part of the register is TEST_REGNO. */
1973 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
1975 unsigned int regno
, endregno
;
1977 if (GET_CODE (dest
) == SUBREG
1978 && (((GET_MODE_SIZE (GET_MODE (dest
))
1979 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
1980 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
1981 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)))
1982 dest
= SUBREG_REG (dest
);
1987 regno
= REGNO (dest
);
1988 endregno
= END_REGNO (dest
);
1989 return (test_regno
>= regno
&& test_regno
< endregno
);
1992 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
1993 any member matches the covers_regno_no_parallel_p criteria. */
1996 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
1998 if (GET_CODE (dest
) == PARALLEL
)
2000 /* Some targets place small structures in registers for return
2001 values of functions, and those registers are wrapped in
2002 PARALLELs that we may see as the destination of a SET. */
2005 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2007 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2008 if (inner
!= NULL_RTX
2009 && covers_regno_no_parallel_p (inner
, test_regno
))
2016 return covers_regno_no_parallel_p (dest
, test_regno
);
2019 /* Utility function for dead_or_set_p to check an individual register. */
2022 dead_or_set_regno_p (const rtx_insn
*insn
, unsigned int test_regno
)
2026 /* See if there is a death note for something that includes TEST_REGNO. */
2027 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2031 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2034 pattern
= PATTERN (insn
);
2036 /* If a COND_EXEC is not executed, the value survives. */
2037 if (GET_CODE (pattern
) == COND_EXEC
)
2040 if (GET_CODE (pattern
) == SET
)
2041 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2042 else if (GET_CODE (pattern
) == PARALLEL
)
2046 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2048 rtx body
= XVECEXP (pattern
, 0, i
);
2050 if (GET_CODE (body
) == COND_EXEC
)
2051 body
= COND_EXEC_CODE (body
);
2053 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2054 && covers_regno_p (SET_DEST (body
), test_regno
))
2062 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2063 If DATUM is nonzero, look for one whose datum is DATUM. */
2066 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2070 gcc_checking_assert (insn
);
2072 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2073 if (! INSN_P (insn
))
2077 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2078 if (REG_NOTE_KIND (link
) == kind
)
2083 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2084 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2089 /* Return the reg-note of kind KIND in insn INSN which applies to register
2090 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2091 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2092 it might be the case that the note overlaps REGNO. */
2095 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2099 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2100 if (! INSN_P (insn
))
2103 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2104 if (REG_NOTE_KIND (link
) == kind
2105 /* Verify that it is a register, so that scratch and MEM won't cause a
2107 && REG_P (XEXP (link
, 0))
2108 && REGNO (XEXP (link
, 0)) <= regno
2109 && END_REGNO (XEXP (link
, 0)) > regno
)
2114 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2118 find_reg_equal_equiv_note (const_rtx insn
)
2125 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2126 if (REG_NOTE_KIND (link
) == REG_EQUAL
2127 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2129 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2130 insns that have multiple sets. Checking single_set to
2131 make sure of this is not the proper check, as explained
2132 in the comment in set_unique_reg_note.
2134 This should be changed into an assert. */
2135 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2142 /* Check whether INSN is a single_set whose source is known to be
2143 equivalent to a constant. Return that constant if so, otherwise
2147 find_constant_src (const rtx_insn
*insn
)
2151 set
= single_set (insn
);
2154 x
= avoid_constant_pool_reference (SET_SRC (set
));
2159 note
= find_reg_equal_equiv_note (insn
);
2160 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2161 return XEXP (note
, 0);
2166 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2167 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2170 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2172 /* If it's not a CALL_INSN, it can't possibly have a
2173 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2183 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2185 link
= XEXP (link
, 1))
2186 if (GET_CODE (XEXP (link
, 0)) == code
2187 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2192 unsigned int regno
= REGNO (datum
);
2194 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2195 to pseudo registers, so don't bother checking. */
2197 if (regno
< FIRST_PSEUDO_REGISTER
)
2199 unsigned int end_regno
= END_REGNO (datum
);
2202 for (i
= regno
; i
< end_regno
; i
++)
2203 if (find_regno_fusage (insn
, code
, i
))
2211 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2212 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2215 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2219 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2220 to pseudo registers, so don't bother checking. */
2222 if (regno
>= FIRST_PSEUDO_REGISTER
2226 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2230 if (GET_CODE (op
= XEXP (link
, 0)) == code
2231 && REG_P (reg
= XEXP (op
, 0))
2232 && REGNO (reg
) <= regno
2233 && END_REGNO (reg
) > regno
)
2241 /* Return true if KIND is an integer REG_NOTE. */
2244 int_reg_note_p (enum reg_note kind
)
2246 return kind
== REG_BR_PROB
;
2249 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2250 stored as the pointer to the next register note. */
2253 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2257 gcc_checking_assert (!int_reg_note_p (kind
));
2262 case REG_LABEL_TARGET
:
2263 case REG_LABEL_OPERAND
:
2265 /* These types of register notes use an INSN_LIST rather than an
2266 EXPR_LIST, so that copying is done right and dumps look
2268 note
= alloc_INSN_LIST (datum
, list
);
2269 PUT_REG_NOTE_KIND (note
, kind
);
2273 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2280 /* Add register note with kind KIND and datum DATUM to INSN. */
2283 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2285 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2288 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2291 add_int_reg_note (rtx_insn
*insn
, enum reg_note kind
, int datum
)
2293 gcc_checking_assert (int_reg_note_p (kind
));
2294 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2295 datum
, REG_NOTES (insn
));
2298 /* Add a register note like NOTE to INSN. */
2301 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2303 if (GET_CODE (note
) == INT_LIST
)
2304 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2306 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2309 /* Duplicate NOTE and return the copy. */
2311 duplicate_reg_note (rtx note
)
2313 reg_note kind
= REG_NOTE_KIND (note
);
2315 if (GET_CODE (note
) == INT_LIST
)
2316 return gen_rtx_INT_LIST ((machine_mode
) kind
, XINT (note
, 0), NULL_RTX
);
2317 else if (GET_CODE (note
) == EXPR_LIST
)
2318 return alloc_reg_note (kind
, copy_insn_1 (XEXP (note
, 0)), NULL_RTX
);
2320 return alloc_reg_note (kind
, XEXP (note
, 0), NULL_RTX
);
2323 /* Remove register note NOTE from the REG_NOTES of INSN. */
2326 remove_note (rtx_insn
*insn
, const_rtx note
)
2330 if (note
== NULL_RTX
)
2333 if (REG_NOTES (insn
) == note
)
2334 REG_NOTES (insn
) = XEXP (note
, 1);
2336 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2337 if (XEXP (link
, 1) == note
)
2339 XEXP (link
, 1) = XEXP (note
, 1);
2343 switch (REG_NOTE_KIND (note
))
2347 df_notes_rescan (insn
);
2354 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2355 Return true if any note has been removed. */
2358 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2363 loc
= ®_NOTES (insn
);
2366 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2367 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2369 *loc
= XEXP (*loc
, 1);
2373 loc
= &XEXP (*loc
, 1);
2378 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2381 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2388 /* This loop is a little tricky. We cannot just go down the chain because
2389 it is being modified by some actions in the loop. So we just iterate
2390 over the head. We plan to drain the list anyway. */
2391 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2393 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2394 rtx note
= find_reg_equal_equiv_note (insn
);
2396 /* This assert is generally triggered when someone deletes a REG_EQUAL
2397 or REG_EQUIV note by hacking the list manually rather than calling
2401 remove_note (insn
, note
);
2405 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2406 return 1 if it is found. A simple equality test is used to determine if
2410 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2414 for (x
= listp
; x
; x
= XEXP (x
, 1))
2415 if (node
== XEXP (x
, 0))
2421 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2422 remove that entry from the list if it is found.
2424 A simple equality test is used to determine if NODE matches. */
2427 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2429 rtx_expr_list
*temp
= *listp
;
2430 rtx_expr_list
*prev
= NULL
;
2434 if (node
== temp
->element ())
2436 /* Splice the node out of the list. */
2438 XEXP (prev
, 1) = temp
->next ();
2440 *listp
= temp
->next ();
2446 temp
= temp
->next ();
2450 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2451 remove that entry from the list if it is found.
2453 A simple equality test is used to determine if NODE matches. */
2456 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2458 rtx_insn_list
*temp
= *listp
;
2459 rtx_insn_list
*prev
= NULL
;
2463 if (node
== temp
->insn ())
2465 /* Splice the node out of the list. */
2467 XEXP (prev
, 1) = temp
->next ();
2469 *listp
= temp
->next ();
2475 temp
= temp
->next ();
2479 /* Nonzero if X contains any volatile instructions. These are instructions
2480 which may cause unpredictable machine state instructions, and thus no
2481 instructions or register uses should be moved or combined across them.
2482 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2485 volatile_insn_p (const_rtx x
)
2487 const RTX_CODE code
= GET_CODE (x
);
2505 case UNSPEC_VOLATILE
:
2510 if (MEM_VOLATILE_P (x
))
2517 /* Recursively scan the operands of this expression. */
2520 const char *const fmt
= GET_RTX_FORMAT (code
);
2523 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2527 if (volatile_insn_p (XEXP (x
, i
)))
2530 else if (fmt
[i
] == 'E')
2533 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2534 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2542 /* Nonzero if X contains any volatile memory references
2543 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2546 volatile_refs_p (const_rtx x
)
2548 const RTX_CODE code
= GET_CODE (x
);
2564 case UNSPEC_VOLATILE
:
2570 if (MEM_VOLATILE_P (x
))
2577 /* Recursively scan the operands of this expression. */
2580 const char *const fmt
= GET_RTX_FORMAT (code
);
2583 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2587 if (volatile_refs_p (XEXP (x
, i
)))
2590 else if (fmt
[i
] == 'E')
2593 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2594 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2602 /* Similar to above, except that it also rejects register pre- and post-
2606 side_effects_p (const_rtx x
)
2608 const RTX_CODE code
= GET_CODE (x
);
2625 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2626 when some combination can't be done. If we see one, don't think
2627 that we can simplify the expression. */
2628 return (GET_MODE (x
) != VOIDmode
);
2637 case UNSPEC_VOLATILE
:
2643 if (MEM_VOLATILE_P (x
))
2650 /* Recursively scan the operands of this expression. */
2653 const char *fmt
= GET_RTX_FORMAT (code
);
2656 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2660 if (side_effects_p (XEXP (x
, i
)))
2663 else if (fmt
[i
] == 'E')
2666 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2667 if (side_effects_p (XVECEXP (x
, i
, j
)))
2675 /* Return nonzero if evaluating rtx X might cause a trap.
2676 FLAGS controls how to consider MEMs. A nonzero means the context
2677 of the access may have changed from the original, such that the
2678 address may have become invalid. */
2681 may_trap_p_1 (const_rtx x
, unsigned flags
)
2687 /* We make no distinction currently, but this function is part of
2688 the internal target-hooks ABI so we keep the parameter as
2689 "unsigned flags". */
2690 bool code_changed
= flags
!= 0;
2694 code
= GET_CODE (x
);
2697 /* Handle these cases quickly. */
2709 return targetm
.unspec_may_trap_p (x
, flags
);
2711 case UNSPEC_VOLATILE
:
2717 return MEM_VOLATILE_P (x
);
2719 /* Memory ref can trap unless it's a static var or a stack slot. */
2721 /* Recognize specific pattern of stack checking probes. */
2722 if (flag_stack_check
2723 && MEM_VOLATILE_P (x
)
2724 && XEXP (x
, 0) == stack_pointer_rtx
)
2726 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2727 reference; moving it out of context such as when moving code
2728 when optimizing, might cause its address to become invalid. */
2730 || !MEM_NOTRAP_P (x
))
2732 HOST_WIDE_INT size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : 0;
2733 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2734 GET_MODE (x
), code_changed
);
2739 /* Division by a non-constant might trap. */
2744 if (HONOR_SNANS (x
))
2746 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2747 return flag_trapping_math
;
2748 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2753 /* An EXPR_LIST is used to represent a function call. This
2754 certainly may trap. */
2763 /* Some floating point comparisons may trap. */
2764 if (!flag_trapping_math
)
2766 /* ??? There is no machine independent way to check for tests that trap
2767 when COMPARE is used, though many targets do make this distinction.
2768 For instance, sparc uses CCFPE for compares which generate exceptions
2769 and CCFP for compares which do not generate exceptions. */
2772 /* But often the compare has some CC mode, so check operand
2774 if (HONOR_NANS (XEXP (x
, 0))
2775 || HONOR_NANS (XEXP (x
, 1)))
2781 if (HONOR_SNANS (x
))
2783 /* Often comparison is CC mode, so check operand modes. */
2784 if (HONOR_SNANS (XEXP (x
, 0))
2785 || HONOR_SNANS (XEXP (x
, 1)))
2790 /* Conversion of floating point might trap. */
2791 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2798 /* These operations don't trap even with floating point. */
2802 /* Any floating arithmetic may trap. */
2803 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2807 fmt
= GET_RTX_FORMAT (code
);
2808 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2812 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2815 else if (fmt
[i
] == 'E')
2818 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2819 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2826 /* Return nonzero if evaluating rtx X might cause a trap. */
2829 may_trap_p (const_rtx x
)
2831 return may_trap_p_1 (x
, 0);
2834 /* Same as above, but additionally return nonzero if evaluating rtx X might
2835 cause a fault. We define a fault for the purpose of this function as a
2836 erroneous execution condition that cannot be encountered during the normal
2837 execution of a valid program; the typical example is an unaligned memory
2838 access on a strict alignment machine. The compiler guarantees that it
2839 doesn't generate code that will fault from a valid program, but this
2840 guarantee doesn't mean anything for individual instructions. Consider
2841 the following example:
2843 struct S { int d; union { char *cp; int *ip; }; };
2845 int foo(struct S *s)
2853 on a strict alignment machine. In a valid program, foo will never be
2854 invoked on a structure for which d is equal to 1 and the underlying
2855 unique field of the union not aligned on a 4-byte boundary, but the
2856 expression *s->ip might cause a fault if considered individually.
2858 At the RTL level, potentially problematic expressions will almost always
2859 verify may_trap_p; for example, the above dereference can be emitted as
2860 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2861 However, suppose that foo is inlined in a caller that causes s->cp to
2862 point to a local character variable and guarantees that s->d is not set
2863 to 1; foo may have been effectively translated into pseudo-RTL as:
2866 (set (reg:SI) (mem:SI (%fp - 7)))
2868 (set (reg:QI) (mem:QI (%fp - 7)))
2870 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2871 memory reference to a stack slot, but it will certainly cause a fault
2872 on a strict alignment machine. */
2875 may_trap_or_fault_p (const_rtx x
)
2877 return may_trap_p_1 (x
, 1);
2880 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2881 i.e., an inequality. */
2884 inequality_comparisons_p (const_rtx x
)
2888 const enum rtx_code code
= GET_CODE (x
);
2916 len
= GET_RTX_LENGTH (code
);
2917 fmt
= GET_RTX_FORMAT (code
);
2919 for (i
= 0; i
< len
; i
++)
2923 if (inequality_comparisons_p (XEXP (x
, i
)))
2926 else if (fmt
[i
] == 'E')
2929 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2930 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
2938 /* Replace any occurrence of FROM in X with TO. The function does
2939 not enter into CONST_DOUBLE for the replace.
2941 Note that copying is not done so X must not be shared unless all copies
2944 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
2945 those pointer-equal ones. */
2948 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
2956 /* Allow this function to make replacements in EXPR_LISTs. */
2963 && REGNO (x
) == REGNO (from
))
2965 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
2968 else if (GET_CODE (x
) == SUBREG
)
2970 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
2972 if (CONST_INT_P (new_rtx
))
2974 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
2975 GET_MODE (SUBREG_REG (x
)),
2980 SUBREG_REG (x
) = new_rtx
;
2984 else if (GET_CODE (x
) == ZERO_EXTEND
)
2986 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
2988 if (CONST_INT_P (new_rtx
))
2990 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
2991 new_rtx
, GET_MODE (XEXP (x
, 0)));
2995 XEXP (x
, 0) = new_rtx
;
3000 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3001 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3004 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
3005 else if (fmt
[i
] == 'E')
3006 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3007 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3008 from
, to
, all_regs
);
3014 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3015 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3018 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3020 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3022 if (JUMP_TABLE_DATA_P (x
))
3025 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3026 int len
= GET_NUM_ELEM (vec
);
3027 for (int i
= 0; i
< len
; ++i
)
3029 rtx ref
= RTVEC_ELT (vec
, i
);
3030 if (XEXP (ref
, 0) == old_label
)
3032 XEXP (ref
, 0) = new_label
;
3033 if (update_label_nuses
)
3035 ++LABEL_NUSES (new_label
);
3036 --LABEL_NUSES (old_label
);
3043 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3044 field. This is not handled by the iterator because it doesn't
3045 handle unprinted ('0') fields. */
3046 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3047 JUMP_LABEL (x
) = new_label
;
3049 subrtx_ptr_iterator::array_type array
;
3050 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3055 if (GET_CODE (x
) == SYMBOL_REF
3056 && CONSTANT_POOL_ADDRESS_P (x
))
3058 rtx c
= get_pool_constant (x
);
3059 if (rtx_referenced_p (old_label
, c
))
3061 /* Create a copy of constant C; replace the label inside
3062 but do not update LABEL_NUSES because uses in constant pool
3064 rtx new_c
= copy_rtx (c
);
3065 replace_label (&new_c
, old_label
, new_label
, false);
3067 /* Add the new constant NEW_C to constant pool and replace
3068 the old reference to constant by new reference. */
3069 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3070 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3074 if ((GET_CODE (x
) == LABEL_REF
3075 || GET_CODE (x
) == INSN_LIST
)
3076 && XEXP (x
, 0) == old_label
)
3078 XEXP (x
, 0) = new_label
;
3079 if (update_label_nuses
)
3081 ++LABEL_NUSES (new_label
);
3082 --LABEL_NUSES (old_label
);
3090 replace_label_in_insn (rtx_insn
*insn
, rtx_insn
*old_label
,
3091 rtx_insn
*new_label
, bool update_label_nuses
)
3093 rtx insn_as_rtx
= insn
;
3094 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3095 gcc_checking_assert (insn_as_rtx
== insn
);
3098 /* Return true if X is referenced in BODY. */
3101 rtx_referenced_p (const_rtx x
, const_rtx body
)
3103 subrtx_iterator::array_type array
;
3104 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3105 if (const_rtx y
= *iter
)
3107 /* Check if a label_ref Y refers to label X. */
3108 if (GET_CODE (y
) == LABEL_REF
3110 && label_ref_label (y
) == x
)
3113 if (rtx_equal_p (x
, y
))
3116 /* If Y is a reference to pool constant traverse the constant. */
3117 if (GET_CODE (y
) == SYMBOL_REF
3118 && CONSTANT_POOL_ADDRESS_P (y
))
3119 iter
.substitute (get_pool_constant (y
));
3124 /* If INSN is a tablejump return true and store the label (before jump table) to
3125 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3128 tablejump_p (const rtx_insn
*insn
, rtx_insn
**labelp
,
3129 rtx_jump_table_data
**tablep
)
3134 rtx target
= JUMP_LABEL (insn
);
3135 if (target
== NULL_RTX
|| ANY_RETURN_P (target
))
3138 rtx_insn
*label
= as_a
<rtx_insn
*> (target
);
3139 rtx_insn
*table
= next_insn (label
);
3140 if (table
== NULL_RTX
|| !JUMP_TABLE_DATA_P (table
))
3146 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3150 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3151 constant that is not in the constant pool and not in the condition
3152 of an IF_THEN_ELSE. */
3155 computed_jump_p_1 (const_rtx x
)
3157 const enum rtx_code code
= GET_CODE (x
);
3174 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3175 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3178 return (computed_jump_p_1 (XEXP (x
, 1))
3179 || computed_jump_p_1 (XEXP (x
, 2)));
3185 fmt
= GET_RTX_FORMAT (code
);
3186 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3189 && computed_jump_p_1 (XEXP (x
, i
)))
3192 else if (fmt
[i
] == 'E')
3193 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3194 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3201 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3203 Tablejumps and casesi insns are not considered indirect jumps;
3204 we can recognize them by a (use (label_ref)). */
3207 computed_jump_p (const rtx_insn
*insn
)
3212 rtx pat
= PATTERN (insn
);
3214 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3215 if (JUMP_LABEL (insn
) != NULL
)
3218 if (GET_CODE (pat
) == PARALLEL
)
3220 int len
= XVECLEN (pat
, 0);
3221 int has_use_labelref
= 0;
3223 for (i
= len
- 1; i
>= 0; i
--)
3224 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3225 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3228 has_use_labelref
= 1;
3232 if (! has_use_labelref
)
3233 for (i
= len
- 1; i
>= 0; i
--)
3234 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3235 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3236 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3239 else if (GET_CODE (pat
) == SET
3240 && SET_DEST (pat
) == pc_rtx
3241 && computed_jump_p_1 (SET_SRC (pat
)))
3249 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3250 the equivalent add insn and pass the result to FN, using DATA as the
3254 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3256 rtx x
= XEXP (mem
, 0);
3257 switch (GET_CODE (x
))
3262 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3263 rtx r1
= XEXP (x
, 0);
3264 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3265 return fn (mem
, x
, r1
, r1
, c
, data
);
3271 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3272 rtx r1
= XEXP (x
, 0);
3273 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3274 return fn (mem
, x
, r1
, r1
, c
, data
);
3280 rtx r1
= XEXP (x
, 0);
3281 rtx add
= XEXP (x
, 1);
3282 return fn (mem
, x
, r1
, add
, NULL
, data
);
3290 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3291 For each such autoinc operation found, call FN, passing it
3292 the innermost enclosing MEM, the operation itself, the RTX modified
3293 by the operation, two RTXs (the second may be NULL) that, once
3294 added, represent the value to be held by the modified RTX
3295 afterwards, and DATA. FN is to return 0 to continue the
3296 traversal or any other value to have it returned to the caller of
3297 for_each_inc_dec. */
3300 for_each_inc_dec (rtx x
,
3301 for_each_inc_dec_fn fn
,
3304 subrtx_var_iterator::array_type array
;
3305 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3310 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3312 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3315 iter
.skip_subrtxes ();
3322 /* Searches X for any reference to REGNO, returning the rtx of the
3323 reference found if any. Otherwise, returns NULL_RTX. */
3326 regno_use_in (unsigned int regno
, rtx x
)
3332 if (REG_P (x
) && REGNO (x
) == regno
)
3335 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3336 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3340 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3343 else if (fmt
[i
] == 'E')
3344 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3345 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3352 /* Return a value indicating whether OP, an operand of a commutative
3353 operation, is preferred as the first or second operand. The more
3354 positive the value, the stronger the preference for being the first
3358 commutative_operand_precedence (rtx op
)
3360 enum rtx_code code
= GET_CODE (op
);
3362 /* Constants always become the second operand. Prefer "nice" constants. */
3363 if (code
== CONST_INT
)
3365 if (code
== CONST_WIDE_INT
)
3367 if (code
== CONST_DOUBLE
)
3369 if (code
== CONST_FIXED
)
3371 op
= avoid_constant_pool_reference (op
);
3372 code
= GET_CODE (op
);
3374 switch (GET_RTX_CLASS (code
))
3377 if (code
== CONST_INT
)
3379 if (code
== CONST_WIDE_INT
)
3381 if (code
== CONST_DOUBLE
)
3383 if (code
== CONST_FIXED
)
3388 /* SUBREGs of objects should come second. */
3389 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3394 /* Complex expressions should be the first, so decrease priority
3395 of objects. Prefer pointer objects over non pointer objects. */
3396 if ((REG_P (op
) && REG_POINTER (op
))
3397 || (MEM_P (op
) && MEM_POINTER (op
)))
3401 case RTX_COMM_ARITH
:
3402 /* Prefer operands that are themselves commutative to be first.
3403 This helps to make things linear. In particular,
3404 (and (and (reg) (reg)) (not (reg))) is canonical. */
3408 /* If only one operand is a binary expression, it will be the first
3409 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3410 is canonical, although it will usually be further simplified. */
3414 /* Then prefer NEG and NOT. */
3415 if (code
== NEG
|| code
== NOT
)
3424 /* Return 1 iff it is necessary to swap operands of commutative operation
3425 in order to canonicalize expression. */
3428 swap_commutative_operands_p (rtx x
, rtx y
)
3430 return (commutative_operand_precedence (x
)
3431 < commutative_operand_precedence (y
));
3434 /* Return 1 if X is an autoincrement side effect and the register is
3435 not the stack pointer. */
3437 auto_inc_p (const_rtx x
)
3439 switch (GET_CODE (x
))
3447 /* There are no REG_INC notes for SP. */
3448 if (XEXP (x
, 0) != stack_pointer_rtx
)
3456 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3458 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3467 code
= GET_CODE (in
);
3468 fmt
= GET_RTX_FORMAT (code
);
3469 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3473 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3476 else if (fmt
[i
] == 'E')
3477 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3478 if (loc
== &XVECEXP (in
, i
, j
)
3479 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3485 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3486 and SUBREG_BYTE, return the bit offset where the subreg begins
3487 (counting from the least significant bit of the operand). */
3490 subreg_lsb_1 (machine_mode outer_mode
,
3491 machine_mode inner_mode
,
3492 unsigned int subreg_byte
)
3494 unsigned int bitpos
;
3498 /* A paradoxical subreg begins at bit position 0. */
3499 if (GET_MODE_PRECISION (outer_mode
) > GET_MODE_PRECISION (inner_mode
))
3502 if (WORDS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
3503 /* If the subreg crosses a word boundary ensure that
3504 it also begins and ends on a word boundary. */
3505 gcc_assert (!((subreg_byte
% UNITS_PER_WORD
3506 + GET_MODE_SIZE (outer_mode
)) > UNITS_PER_WORD
3507 && (subreg_byte
% UNITS_PER_WORD
3508 || GET_MODE_SIZE (outer_mode
) % UNITS_PER_WORD
)));
3510 if (WORDS_BIG_ENDIAN
)
3511 word
= (GET_MODE_SIZE (inner_mode
)
3512 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) / UNITS_PER_WORD
;
3514 word
= subreg_byte
/ UNITS_PER_WORD
;
3515 bitpos
= word
* BITS_PER_WORD
;
3517 if (BYTES_BIG_ENDIAN
)
3518 byte
= (GET_MODE_SIZE (inner_mode
)
3519 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) % UNITS_PER_WORD
;
3521 byte
= subreg_byte
% UNITS_PER_WORD
;
3522 bitpos
+= byte
* BITS_PER_UNIT
;
3527 /* Given a subreg X, return the bit offset where the subreg begins
3528 (counting from the least significant bit of the reg). */
3531 subreg_lsb (const_rtx x
)
3533 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3537 /* Return the subreg byte offset for a subreg whose outer value has
3538 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
3539 there are LSB_SHIFT *bits* between the lsb of the outer value and the
3540 lsb of the inner value. This is the inverse of the calculation
3541 performed by subreg_lsb_1 (which converts byte offsets to bit shifts). */
3544 subreg_size_offset_from_lsb (unsigned int outer_bytes
,
3545 unsigned int inner_bytes
,
3546 unsigned int lsb_shift
)
3548 /* A paradoxical subreg begins at bit position 0. */
3549 if (outer_bytes
> inner_bytes
)
3551 gcc_checking_assert (lsb_shift
== 0);
3555 gcc_assert (lsb_shift
% BITS_PER_UNIT
== 0);
3556 unsigned int lower_bytes
= lsb_shift
/ BITS_PER_UNIT
;
3557 unsigned int upper_bytes
= inner_bytes
- (lower_bytes
+ outer_bytes
);
3558 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3560 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3564 unsigned int lower_word_part
= lower_bytes
& -UNITS_PER_WORD
;
3565 unsigned int upper_word_part
= upper_bytes
& -UNITS_PER_WORD
;
3566 if (WORDS_BIG_ENDIAN
)
3567 return upper_word_part
+ (lower_bytes
- lower_word_part
);
3569 return lower_word_part
+ (upper_bytes
- upper_word_part
);
3573 /* Fill in information about a subreg of a hard register.
3574 xregno - A regno of an inner hard subreg_reg (or what will become one).
3575 xmode - The mode of xregno.
3576 offset - The byte offset.
3577 ymode - The mode of a top level SUBREG (or what may become one).
3578 info - Pointer to structure to fill in.
3580 Rather than considering one particular inner register (and thus one
3581 particular "outer" register) in isolation, this function really uses
3582 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3583 function does not check whether adding INFO->offset to XREGNO gives
3584 a valid hard register; even if INFO->offset + XREGNO is out of range,
3585 there might be another register of the same type that is in range.
3586 Likewise it doesn't check whether HARD_REGNO_MODE_OK accepts the new
3587 register, since that can depend on things like whether the final
3588 register number is even or odd. Callers that want to check whether
3589 this particular subreg can be replaced by a simple (reg ...) should
3590 use simplify_subreg_regno. */
3593 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3594 unsigned int offset
, machine_mode ymode
,
3595 struct subreg_info
*info
)
3597 unsigned int nregs_xmode
, nregs_ymode
;
3599 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3601 unsigned int xsize
= GET_MODE_SIZE (xmode
);
3602 unsigned int ysize
= GET_MODE_SIZE (ymode
);
3603 bool rknown
= false;
3605 /* If the register representation of a non-scalar mode has holes in it,
3606 we expect the scalar units to be concatenated together, with the holes
3607 distributed evenly among the scalar units. Each scalar unit must occupy
3608 at least one register. */
3609 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3611 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3612 unsigned int nunits
= GET_MODE_NUNITS (xmode
);
3613 machine_mode xmode_unit
= GET_MODE_INNER (xmode
);
3614 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3615 gcc_assert (nregs_xmode
3617 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3618 gcc_assert (hard_regno_nregs
[xregno
][xmode
]
3619 == hard_regno_nregs
[xregno
][xmode_unit
] * nunits
);
3621 /* You can only ask for a SUBREG of a value with holes in the middle
3622 if you don't cross the holes. (Such a SUBREG should be done by
3623 picking a different register class, or doing it in memory if
3624 necessary.) An example of a value with holes is XCmode on 32-bit
3625 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3626 3 for each part, but in memory it's two 128-bit parts.
3627 Padding is assumed to be at the end (not necessarily the 'high part')
3629 if ((offset
/ GET_MODE_SIZE (xmode_unit
) + 1 < nunits
)
3630 && (offset
/ GET_MODE_SIZE (xmode_unit
)
3631 != ((offset
+ ysize
- 1) / GET_MODE_SIZE (xmode_unit
))))
3633 info
->representable_p
= false;
3638 nregs_xmode
= hard_regno_nregs
[xregno
][xmode
];
3640 nregs_ymode
= hard_regno_nregs
[xregno
][ymode
];
3642 /* Paradoxical subregs are otherwise valid. */
3643 if (!rknown
&& offset
== 0 && ysize
> xsize
)
3645 info
->representable_p
= true;
3646 /* If this is a big endian paradoxical subreg, which uses more
3647 actual hard registers than the original register, we must
3648 return a negative offset so that we find the proper highpart
3651 We assume that the ordering of registers within a multi-register
3652 value has a consistent endianness: if bytes and register words
3653 have different endianness, the hard registers that make up a
3654 multi-register value must be at least word-sized. */
3655 if (REG_WORDS_BIG_ENDIAN
)
3656 info
->offset
= (int) nregs_xmode
- (int) nregs_ymode
;
3659 info
->nregs
= nregs_ymode
;
3663 /* If registers store different numbers of bits in the different
3664 modes, we cannot generally form this subreg. */
3665 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3666 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3667 && (xsize
% nregs_xmode
) == 0
3668 && (ysize
% nregs_ymode
) == 0)
3670 int regsize_xmode
= xsize
/ nregs_xmode
;
3671 int regsize_ymode
= ysize
/ nregs_ymode
;
3673 && ((nregs_ymode
> 1 && regsize_xmode
> regsize_ymode
)
3674 || (nregs_xmode
> 1 && regsize_ymode
> regsize_xmode
)))
3676 info
->representable_p
= false;
3677 info
->nregs
= CEIL (ysize
, regsize_xmode
);
3678 info
->offset
= offset
/ regsize_xmode
;
3681 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
3682 would go outside of XMODE. */
3683 if (!rknown
&& ysize
+ offset
> xsize
)
3685 info
->representable_p
= false;
3686 info
->nregs
= nregs_ymode
;
3687 info
->offset
= offset
/ regsize_xmode
;
3690 /* Quick exit for the simple and common case of extracting whole
3691 subregisters from a multiregister value. */
3692 /* ??? It would be better to integrate this into the code below,
3693 if we can generalize the concept enough and figure out how
3694 odd-sized modes can coexist with the other weird cases we support. */
3696 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3697 && regsize_xmode
== regsize_ymode
3698 && (offset
% regsize_ymode
) == 0)
3700 info
->representable_p
= true;
3701 info
->nregs
= nregs_ymode
;
3702 info
->offset
= offset
/ regsize_ymode
;
3703 gcc_assert (info
->offset
+ info
->nregs
<= (int) nregs_xmode
);
3708 /* Lowpart subregs are otherwise valid. */
3709 if (!rknown
&& offset
== subreg_lowpart_offset (ymode
, xmode
))
3711 info
->representable_p
= true;
3714 if (offset
== 0 || nregs_xmode
== nregs_ymode
)
3717 info
->nregs
= nregs_ymode
;
3722 /* Set NUM_BLOCKS to the number of independently-representable YMODE
3723 values there are in (reg:XMODE XREGNO). We can view the register
3724 as consisting of this number of independent "blocks", where each
3725 block occupies NREGS_YMODE registers and contains exactly one
3726 representable YMODE value. */
3727 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3728 unsigned int num_blocks
= nregs_xmode
/ nregs_ymode
;
3730 /* Calculate the number of bytes in each block. This must always
3731 be exact, otherwise we don't know how to verify the constraint.
3732 These conditions may be relaxed but subreg_regno_offset would
3733 need to be redesigned. */
3734 gcc_assert ((xsize
% num_blocks
) == 0);
3735 unsigned int bytes_per_block
= xsize
/ num_blocks
;
3737 /* Get the number of the first block that contains the subreg and the byte
3738 offset of the subreg from the start of that block. */
3739 unsigned int block_number
= offset
/ bytes_per_block
;
3740 unsigned int subblock_offset
= offset
% bytes_per_block
;
3744 /* Only the lowpart of each block is representable. */
3745 info
->representable_p
3747 == subreg_size_lowpart_offset (ysize
, bytes_per_block
));
3751 /* We assume that the ordering of registers within a multi-register
3752 value has a consistent endianness: if bytes and register words
3753 have different endianness, the hard registers that make up a
3754 multi-register value must be at least word-sized. */
3755 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
)
3756 /* The block number we calculated above followed memory endianness.
3757 Convert it to register endianness by counting back from the end.
3758 (Note that, because of the assumption above, each block must be
3759 at least word-sized.) */
3760 info
->offset
= (num_blocks
- block_number
- 1) * nregs_ymode
;
3762 info
->offset
= block_number
* nregs_ymode
;
3763 info
->nregs
= nregs_ymode
;
3766 /* This function returns the regno offset of a subreg expression.
3767 xregno - A regno of an inner hard subreg_reg (or what will become one).
3768 xmode - The mode of xregno.
3769 offset - The byte offset.
3770 ymode - The mode of a top level SUBREG (or what may become one).
3771 RETURN - The regno offset which would be used. */
3773 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3774 unsigned int offset
, machine_mode ymode
)
3776 struct subreg_info info
;
3777 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3781 /* This function returns true when the offset is representable via
3782 subreg_offset in the given regno.
3783 xregno - A regno of an inner hard subreg_reg (or what will become one).
3784 xmode - The mode of xregno.
3785 offset - The byte offset.
3786 ymode - The mode of a top level SUBREG (or what may become one).
3787 RETURN - Whether the offset is representable. */
3789 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3790 unsigned int offset
, machine_mode ymode
)
3792 struct subreg_info info
;
3793 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3794 return info
.representable_p
;
3797 /* Return the number of a YMODE register to which
3799 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3801 can be simplified. Return -1 if the subreg can't be simplified.
3803 XREGNO is a hard register number. */
3806 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3807 unsigned int offset
, machine_mode ymode
)
3809 struct subreg_info info
;
3810 unsigned int yregno
;
3812 #ifdef CANNOT_CHANGE_MODE_CLASS
3813 /* Give the backend a chance to disallow the mode change. */
3814 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3815 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3816 && REG_CANNOT_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3817 /* We can use mode change in LRA for some transformations. */
3818 && ! lra_in_progress
)
3822 /* We shouldn't simplify stack-related registers. */
3823 if ((!reload_completed
|| frame_pointer_needed
)
3824 && xregno
== FRAME_POINTER_REGNUM
)
3827 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3828 && xregno
== ARG_POINTER_REGNUM
)
3831 if (xregno
== STACK_POINTER_REGNUM
3832 /* We should convert hard stack register in LRA if it is
3834 && ! lra_in_progress
)
3837 /* Try to get the register offset. */
3838 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3839 if (!info
.representable_p
)
3842 /* Make sure that the offsetted register value is in range. */
3843 yregno
= xregno
+ info
.offset
;
3844 if (!HARD_REGISTER_NUM_P (yregno
))
3847 /* See whether (reg:YMODE YREGNO) is valid.
3849 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3850 This is a kludge to work around how complex FP arguments are passed
3851 on IA-64 and should be fixed. See PR target/49226. */
3852 if (!HARD_REGNO_MODE_OK (yregno
, ymode
)
3853 && HARD_REGNO_MODE_OK (xregno
, xmode
))
3856 return (int) yregno
;
3859 /* Return the final regno that a subreg expression refers to. */
3861 subreg_regno (const_rtx x
)
3864 rtx subreg
= SUBREG_REG (x
);
3865 int regno
= REGNO (subreg
);
3867 ret
= regno
+ subreg_regno_offset (regno
,
3875 /* Return the number of registers that a subreg expression refers
3878 subreg_nregs (const_rtx x
)
3880 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3883 /* Return the number of registers that a subreg REG with REGNO
3884 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3885 changed so that the regno can be passed in. */
3888 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3890 struct subreg_info info
;
3891 rtx subreg
= SUBREG_REG (x
);
3893 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3898 struct parms_set_data
3904 /* Helper function for noticing stores to parameter registers. */
3906 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3908 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3909 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3910 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
3912 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
3917 /* Look backward for first parameter to be loaded.
3918 Note that loads of all parameters will not necessarily be
3919 found if CSE has eliminated some of them (e.g., an argument
3920 to the outer function is passed down as a parameter).
3921 Do not skip BOUNDARY. */
3923 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
3925 struct parms_set_data parm
;
3927 rtx_insn
*before
, *first_set
;
3929 /* Since different machines initialize their parameter registers
3930 in different orders, assume nothing. Collect the set of all
3931 parameter registers. */
3932 CLEAR_HARD_REG_SET (parm
.regs
);
3934 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
3935 if (GET_CODE (XEXP (p
, 0)) == USE
3936 && REG_P (XEXP (XEXP (p
, 0), 0))
3937 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p
, 0), 0)))
3939 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
3941 /* We only care about registers which can hold function
3943 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
3946 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
3950 first_set
= call_insn
;
3952 /* Search backward for the first set of a register in this set. */
3953 while (parm
.nregs
&& before
!= boundary
)
3955 before
= PREV_INSN (before
);
3957 /* It is possible that some loads got CSEed from one call to
3958 another. Stop in that case. */
3959 if (CALL_P (before
))
3962 /* Our caller needs either ensure that we will find all sets
3963 (in case code has not been optimized yet), or take care
3964 for possible labels in a way by setting boundary to preceding
3966 if (LABEL_P (before
))
3968 gcc_assert (before
== boundary
);
3972 if (INSN_P (before
))
3974 int nregs_old
= parm
.nregs
;
3975 note_stores (PATTERN (before
), parms_set
, &parm
);
3976 /* If we found something that did not set a parameter reg,
3977 we're done. Do not keep going, as that might result
3978 in hoisting an insn before the setting of a pseudo
3979 that is used by the hoisted insn. */
3980 if (nregs_old
!= parm
.nregs
)
3989 /* Return true if we should avoid inserting code between INSN and preceding
3990 call instruction. */
3993 keep_with_call_p (const rtx_insn
*insn
)
3997 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
3999 if (REG_P (SET_DEST (set
))
4000 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
4001 && fixed_regs
[REGNO (SET_DEST (set
))]
4002 && general_operand (SET_SRC (set
), VOIDmode
))
4004 if (REG_P (SET_SRC (set
))
4005 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
4006 && REG_P (SET_DEST (set
))
4007 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
4009 /* There may be a stack pop just after the call and before the store
4010 of the return register. Search for the actual store when deciding
4011 if we can break or not. */
4012 if (SET_DEST (set
) == stack_pointer_rtx
)
4014 /* This CONST_CAST is okay because next_nonnote_insn just
4015 returns its argument and we assign it to a const_rtx
4018 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
4019 if (i2
&& keep_with_call_p (i2
))
4026 /* Return true if LABEL is a target of JUMP_INSN. This applies only
4027 to non-complex jumps. That is, direct unconditional, conditional,
4028 and tablejumps, but not computed jumps or returns. It also does
4029 not apply to the fallthru case of a conditional jump. */
4032 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4034 rtx tmp
= JUMP_LABEL (jump_insn
);
4035 rtx_jump_table_data
*table
;
4040 if (tablejump_p (jump_insn
, NULL
, &table
))
4042 rtvec vec
= table
->get_labels ();
4043 int i
, veclen
= GET_NUM_ELEM (vec
);
4045 for (i
= 0; i
< veclen
; ++i
)
4046 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4050 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4057 /* Return an estimate of the cost of computing rtx X.
4058 One use is in cse, to decide which expression to keep in the hash table.
4059 Another is in rtl generation, to pick the cheapest way to multiply.
4060 Other uses like the latter are expected in the future.
4062 X appears as operand OPNO in an expression with code OUTER_CODE.
4063 SPEED specifies whether costs optimized for speed or size should
4067 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4068 int opno
, bool speed
)
4079 if (GET_MODE (x
) != VOIDmode
)
4080 mode
= GET_MODE (x
);
4082 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4083 many insns, taking N times as long. */
4084 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4088 /* Compute the default costs of certain things.
4089 Note that targetm.rtx_costs can override the defaults. */
4091 code
= GET_CODE (x
);
4095 /* Multiplication has time-complexity O(N*N), where N is the
4096 number of units (translated from digits) when using
4097 schoolbook long multiplication. */
4098 total
= factor
* factor
* COSTS_N_INSNS (5);
4104 /* Similarly, complexity for schoolbook long division. */
4105 total
= factor
* factor
* COSTS_N_INSNS (7);
4108 /* Used in combine.c as a marker. */
4112 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4113 the mode for the factor. */
4114 mode
= GET_MODE (SET_DEST (x
));
4115 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4120 total
= factor
* COSTS_N_INSNS (1);
4130 /* If we can't tie these modes, make this expensive. The larger
4131 the mode, the more expensive it is. */
4132 if (! MODES_TIEABLE_P (mode
, GET_MODE (SUBREG_REG (x
))))
4133 return COSTS_N_INSNS (2 + factor
);
4137 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4142 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4143 which is already in total. */
4145 fmt
= GET_RTX_FORMAT (code
);
4146 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4148 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4149 else if (fmt
[i
] == 'E')
4150 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4151 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4156 /* Fill in the structure C with information about both speed and size rtx
4157 costs for X, which is operand OPNO in an expression with code OUTER. */
4160 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4161 struct full_rtx_costs
*c
)
4163 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4164 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4168 /* Return cost of address expression X.
4169 Expect that X is properly formed address reference.
4171 SPEED parameter specify whether costs optimized for speed or size should
4175 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4177 /* We may be asked for cost of various unusual addresses, such as operands
4178 of push instruction. It is not worthwhile to complicate writing
4179 of the target hook by such cases. */
4181 if (!memory_address_addr_space_p (mode
, x
, as
))
4184 return targetm
.address_cost (x
, mode
, as
, speed
);
4187 /* If the target doesn't override, compute the cost as with arithmetic. */
4190 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4192 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4196 unsigned HOST_WIDE_INT
4197 nonzero_bits (const_rtx x
, machine_mode mode
)
4199 return cached_nonzero_bits (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4203 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4205 return cached_num_sign_bit_copies (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4208 /* Return true if nonzero_bits1 might recurse into both operands
4212 nonzero_bits_binary_arith_p (const_rtx x
)
4214 if (!ARITHMETIC_P (x
))
4216 switch (GET_CODE (x
))
4238 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4239 It avoids exponential behavior in nonzero_bits1 when X has
4240 identical subexpressions on the first or the second level. */
4242 static unsigned HOST_WIDE_INT
4243 cached_nonzero_bits (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4244 machine_mode known_mode
,
4245 unsigned HOST_WIDE_INT known_ret
)
4247 if (x
== known_x
&& mode
== known_mode
)
4250 /* Try to find identical subexpressions. If found call
4251 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4252 precomputed value for the subexpression as KNOWN_RET. */
4254 if (nonzero_bits_binary_arith_p (x
))
4256 rtx x0
= XEXP (x
, 0);
4257 rtx x1
= XEXP (x
, 1);
4259 /* Check the first level. */
4261 return nonzero_bits1 (x
, mode
, x0
, mode
,
4262 cached_nonzero_bits (x0
, mode
, known_x
,
4263 known_mode
, known_ret
));
4265 /* Check the second level. */
4266 if (nonzero_bits_binary_arith_p (x0
)
4267 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4268 return nonzero_bits1 (x
, mode
, x1
, mode
,
4269 cached_nonzero_bits (x1
, mode
, known_x
,
4270 known_mode
, known_ret
));
4272 if (nonzero_bits_binary_arith_p (x1
)
4273 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4274 return nonzero_bits1 (x
, mode
, x0
, mode
,
4275 cached_nonzero_bits (x0
, mode
, known_x
,
4276 known_mode
, known_ret
));
4279 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4282 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4283 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4284 is less useful. We can't allow both, because that results in exponential
4285 run time recursion. There is a nullstone testcase that triggered
4286 this. This macro avoids accidental uses of num_sign_bit_copies. */
4287 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4289 /* Given an expression, X, compute which bits in X can be nonzero.
4290 We don't care about bits outside of those defined in MODE.
4292 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4293 an arithmetic operation, we can do better. */
4295 static unsigned HOST_WIDE_INT
4296 nonzero_bits1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4297 machine_mode known_mode
,
4298 unsigned HOST_WIDE_INT known_ret
)
4300 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4301 unsigned HOST_WIDE_INT inner_nz
;
4303 machine_mode inner_mode
;
4304 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4306 /* For floating-point and vector values, assume all bits are needed. */
4307 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
)
4308 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4311 /* If X is wider than MODE, use its mode instead. */
4312 if (GET_MODE_PRECISION (GET_MODE (x
)) > mode_width
)
4314 mode
= GET_MODE (x
);
4315 nonzero
= GET_MODE_MASK (mode
);
4316 mode_width
= GET_MODE_PRECISION (mode
);
4319 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4320 /* Our only callers in this case look for single bit values. So
4321 just return the mode mask. Those tests will then be false. */
4324 /* If MODE is wider than X, but both are a single word for both the host
4325 and target machines, we can compute this from which bits of the
4326 object might be nonzero in its own mode, taking into account the fact
4327 that on many CISC machines, accessing an object in a wider mode
4328 causes the high-order bits to become undefined. So they are
4329 not known to be zero. */
4331 if (!WORD_REGISTER_OPERATIONS
4332 && GET_MODE (x
) != VOIDmode
4333 && GET_MODE (x
) != mode
4334 && GET_MODE_PRECISION (GET_MODE (x
)) <= BITS_PER_WORD
4335 && GET_MODE_PRECISION (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
4336 && GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (GET_MODE (x
)))
4338 nonzero
&= cached_nonzero_bits (x
, GET_MODE (x
),
4339 known_x
, known_mode
, known_ret
);
4340 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
4344 /* Please keep nonzero_bits_binary_arith_p above in sync with
4345 the code in the switch below. */
4346 code
= GET_CODE (x
);
4350 #if defined(POINTERS_EXTEND_UNSIGNED)
4351 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4352 all the bits above ptr_mode are known to be zero. */
4353 /* As we do not know which address space the pointer is referring to,
4354 we can do this only if the target does not support different pointer
4355 or address modes depending on the address space. */
4356 if (target_default_pointer_address_modes_p ()
4357 && POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4359 && !targetm
.have_ptr_extend ())
4360 nonzero
&= GET_MODE_MASK (ptr_mode
);
4363 /* Include declared information about alignment of pointers. */
4364 /* ??? We don't properly preserve REG_POINTER changes across
4365 pointer-to-integer casts, so we can't trust it except for
4366 things that we know must be pointers. See execute/960116-1.c. */
4367 if ((x
== stack_pointer_rtx
4368 || x
== frame_pointer_rtx
4369 || x
== arg_pointer_rtx
)
4370 && REGNO_POINTER_ALIGN (REGNO (x
)))
4372 unsigned HOST_WIDE_INT alignment
4373 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4375 #ifdef PUSH_ROUNDING
4376 /* If PUSH_ROUNDING is defined, it is possible for the
4377 stack to be momentarily aligned only to that amount,
4378 so we pick the least alignment. */
4379 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4380 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4384 nonzero
&= ~(alignment
- 1);
4388 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4389 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, mode
, known_x
,
4390 known_mode
, known_ret
,
4394 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4395 known_mode
, known_ret
);
4397 return nonzero_for_hook
;
4401 /* If X is negative in MODE, sign-extend the value. */
4402 if (SHORT_IMMEDIATES_SIGN_EXTEND
&& INTVAL (x
) > 0
4403 && mode_width
< BITS_PER_WORD
4404 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
4406 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4411 /* In many, if not most, RISC machines, reading a byte from memory
4412 zeros the rest of the register. Noticing that fact saves a lot
4413 of extra zero-extends. */
4414 if (load_extend_op (GET_MODE (x
)) == ZERO_EXTEND
)
4415 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
4419 case UNEQ
: case LTGT
:
4420 case GT
: case GTU
: case UNGT
:
4421 case LT
: case LTU
: case UNLT
:
4422 case GE
: case GEU
: case UNGE
:
4423 case LE
: case LEU
: case UNLE
:
4424 case UNORDERED
: case ORDERED
:
4425 /* If this produces an integer result, we know which bits are set.
4426 Code here used to clear bits outside the mode of X, but that is
4428 /* Mind that MODE is the mode the caller wants to look at this
4429 operation in, and not the actual operation mode. We can wind
4430 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4431 that describes the results of a vector compare. */
4432 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
4433 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4434 nonzero
= STORE_FLAG_VALUE
;
4439 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4440 and num_sign_bit_copies. */
4441 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4442 == GET_MODE_PRECISION (GET_MODE (x
)))
4446 if (GET_MODE_PRECISION (GET_MODE (x
)) < mode_width
)
4447 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
4452 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4453 and num_sign_bit_copies. */
4454 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4455 == GET_MODE_PRECISION (GET_MODE (x
)))
4461 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4462 known_x
, known_mode
, known_ret
)
4463 & GET_MODE_MASK (mode
));
4467 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4468 known_x
, known_mode
, known_ret
);
4469 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4470 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4474 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4475 Otherwise, show all the bits in the outer mode but not the inner
4477 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4478 known_x
, known_mode
, known_ret
);
4479 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4481 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4482 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4483 inner_nz
|= (GET_MODE_MASK (mode
)
4484 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4487 nonzero
&= inner_nz
;
4491 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4492 known_x
, known_mode
, known_ret
)
4493 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4494 known_x
, known_mode
, known_ret
);
4498 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4500 unsigned HOST_WIDE_INT nonzero0
4501 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4502 known_x
, known_mode
, known_ret
);
4504 /* Don't call nonzero_bits for the second time if it cannot change
4506 if ((nonzero
& nonzero0
) != nonzero
)
4508 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4509 known_x
, known_mode
, known_ret
);
4513 case PLUS
: case MINUS
:
4515 case DIV
: case UDIV
:
4516 case MOD
: case UMOD
:
4517 /* We can apply the rules of arithmetic to compute the number of
4518 high- and low-order zero bits of these operations. We start by
4519 computing the width (position of the highest-order nonzero bit)
4520 and the number of low-order zero bits for each value. */
4522 unsigned HOST_WIDE_INT nz0
4523 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4524 known_x
, known_mode
, known_ret
);
4525 unsigned HOST_WIDE_INT nz1
4526 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4527 known_x
, known_mode
, known_ret
);
4528 int sign_index
= GET_MODE_PRECISION (GET_MODE (x
)) - 1;
4529 int width0
= floor_log2 (nz0
) + 1;
4530 int width1
= floor_log2 (nz1
) + 1;
4531 int low0
= ctz_or_zero (nz0
);
4532 int low1
= ctz_or_zero (nz1
);
4533 unsigned HOST_WIDE_INT op0_maybe_minusp
4534 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
4535 unsigned HOST_WIDE_INT op1_maybe_minusp
4536 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
4537 unsigned int result_width
= mode_width
;
4543 result_width
= MAX (width0
, width1
) + 1;
4544 result_low
= MIN (low0
, low1
);
4547 result_low
= MIN (low0
, low1
);
4550 result_width
= width0
+ width1
;
4551 result_low
= low0
+ low1
;
4556 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4557 result_width
= width0
;
4562 result_width
= width0
;
4567 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4568 result_width
= MIN (width0
, width1
);
4569 result_low
= MIN (low0
, low1
);
4574 result_width
= MIN (width0
, width1
);
4575 result_low
= MIN (low0
, low1
);
4581 if (result_width
< mode_width
)
4582 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
4585 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
4590 if (CONST_INT_P (XEXP (x
, 1))
4591 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4592 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
4596 /* If this is a SUBREG formed for a promoted variable that has
4597 been zero-extended, we know that at least the high-order bits
4598 are zero, though others might be too. */
4599 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4600 nonzero
= GET_MODE_MASK (GET_MODE (x
))
4601 & cached_nonzero_bits (SUBREG_REG (x
), GET_MODE (x
),
4602 known_x
, known_mode
, known_ret
);
4604 /* If the inner mode is a single word for both the host and target
4605 machines, we can compute this from which bits of the inner
4606 object might be nonzero. */
4607 inner_mode
= GET_MODE (SUBREG_REG (x
));
4608 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4609 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
)
4611 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4612 known_x
, known_mode
, known_ret
);
4614 /* On many CISC machines, accessing an object in a wider mode
4615 causes the high-order bits to become undefined. So they are
4616 not known to be zero. */
4618 if ((!WORD_REGISTER_OPERATIONS
4619 /* If this is a typical RISC machine, we only have to worry
4620 about the way loads are extended. */
4621 || ((extend_op
= load_extend_op (inner_mode
)) == SIGN_EXTEND
4622 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4623 : extend_op
!= ZERO_EXTEND
)
4624 || (!MEM_P (SUBREG_REG (x
)) && !REG_P (SUBREG_REG (x
))))
4625 && GET_MODE_PRECISION (GET_MODE (x
))
4626 > GET_MODE_PRECISION (inner_mode
))
4628 |= (GET_MODE_MASK (GET_MODE (x
)) & ~GET_MODE_MASK (inner_mode
));
4636 /* The nonzero bits are in two classes: any bits within MODE
4637 that aren't in GET_MODE (x) are always significant. The rest of the
4638 nonzero bits are those that are significant in the operand of
4639 the shift when shifted the appropriate number of bits. This
4640 shows that high-order bits are cleared by the right shift and
4641 low-order bits by left shifts. */
4642 if (CONST_INT_P (XEXP (x
, 1))
4643 && INTVAL (XEXP (x
, 1)) >= 0
4644 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4645 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4647 machine_mode inner_mode
= GET_MODE (x
);
4648 unsigned int width
= GET_MODE_PRECISION (inner_mode
);
4649 int count
= INTVAL (XEXP (x
, 1));
4650 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
4651 unsigned HOST_WIDE_INT op_nonzero
4652 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4653 known_x
, known_mode
, known_ret
);
4654 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4655 unsigned HOST_WIDE_INT outer
= 0;
4657 if (mode_width
> width
)
4658 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4660 if (code
== LSHIFTRT
)
4662 else if (code
== ASHIFTRT
)
4666 /* If the sign bit may have been nonzero before the shift, we
4667 need to mark all the places it could have been copied to
4668 by the shift as possibly nonzero. */
4669 if (inner
& (HOST_WIDE_INT_1U
<< (width
- 1 - count
)))
4670 inner
|= ((HOST_WIDE_INT_1U
<< count
) - 1)
4673 else if (code
== ASHIFT
)
4676 inner
= ((inner
<< (count
% width
)
4677 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
4679 nonzero
&= (outer
| inner
);
4685 /* This is at most the number of bits in the mode. */
4686 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4690 /* If CLZ has a known value at zero, then the nonzero bits are
4691 that value, plus the number of bits in the mode minus one. */
4692 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4694 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4700 /* If CTZ has a known value at zero, then the nonzero bits are
4701 that value, plus the number of bits in the mode minus one. */
4702 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4704 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4710 /* This is at most the number of bits in the mode minus 1. */
4711 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4720 unsigned HOST_WIDE_INT nonzero_true
4721 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4722 known_x
, known_mode
, known_ret
);
4724 /* Don't call nonzero_bits for the second time if it cannot change
4726 if ((nonzero
& nonzero_true
) != nonzero
)
4727 nonzero
&= nonzero_true
4728 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4729 known_x
, known_mode
, known_ret
);
4740 /* See the macro definition above. */
4741 #undef cached_num_sign_bit_copies
4744 /* Return true if num_sign_bit_copies1 might recurse into both operands
4748 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4750 if (!ARITHMETIC_P (x
))
4752 switch (GET_CODE (x
))
4770 /* The function cached_num_sign_bit_copies is a wrapper around
4771 num_sign_bit_copies1. It avoids exponential behavior in
4772 num_sign_bit_copies1 when X has identical subexpressions on the
4773 first or the second level. */
4776 cached_num_sign_bit_copies (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4777 machine_mode known_mode
,
4778 unsigned int known_ret
)
4780 if (x
== known_x
&& mode
== known_mode
)
4783 /* Try to find identical subexpressions. If found call
4784 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4785 the precomputed value for the subexpression as KNOWN_RET. */
4787 if (num_sign_bit_copies_binary_arith_p (x
))
4789 rtx x0
= XEXP (x
, 0);
4790 rtx x1
= XEXP (x
, 1);
4792 /* Check the first level. */
4795 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4796 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4800 /* Check the second level. */
4801 if (num_sign_bit_copies_binary_arith_p (x0
)
4802 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4804 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4805 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4809 if (num_sign_bit_copies_binary_arith_p (x1
)
4810 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4812 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4813 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4818 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4821 /* Return the number of bits at the high-order end of X that are known to
4822 be equal to the sign bit. X will be used in mode MODE; if MODE is
4823 VOIDmode, X will be used in its own mode. The returned value will always
4824 be between 1 and the number of bits in MODE. */
4827 num_sign_bit_copies1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4828 machine_mode known_mode
,
4829 unsigned int known_ret
)
4831 enum rtx_code code
= GET_CODE (x
);
4832 machine_mode inner_mode
;
4833 int num0
, num1
, result
;
4834 unsigned HOST_WIDE_INT nonzero
;
4836 /* If we weren't given a mode, use the mode of X. If the mode is still
4837 VOIDmode, we don't know anything. Likewise if one of the modes is
4840 if (mode
== VOIDmode
)
4841 mode
= GET_MODE (x
);
4843 gcc_checking_assert (mode
!= BLKmode
);
4845 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
))
4846 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4849 /* For a smaller mode, just ignore the high bits. */
4850 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4851 if (bitwidth
< GET_MODE_PRECISION (GET_MODE (x
)))
4853 num0
= cached_num_sign_bit_copies (x
, GET_MODE (x
),
4854 known_x
, known_mode
, known_ret
);
4856 num0
- (int) (GET_MODE_PRECISION (GET_MODE (x
)) - bitwidth
));
4859 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_PRECISION (GET_MODE (x
)))
4861 /* If this machine does not do all register operations on the entire
4862 register and MODE is wider than the mode of X, we can say nothing
4863 at all about the high-order bits. */
4864 if (!WORD_REGISTER_OPERATIONS
)
4867 /* Likewise on machines that do, if the mode of the object is smaller
4868 than a word and loads of that size don't sign extend, we can say
4869 nothing about the high order bits. */
4870 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
4871 && load_extend_op (GET_MODE (x
)) != SIGN_EXTEND
)
4875 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
4876 the code in the switch below. */
4881 #if defined(POINTERS_EXTEND_UNSIGNED)
4882 /* If pointers extend signed and this is a pointer in Pmode, say that
4883 all the bits above ptr_mode are known to be sign bit copies. */
4884 /* As we do not know which address space the pointer is referring to,
4885 we can do this only if the target does not support different pointer
4886 or address modes depending on the address space. */
4887 if (target_default_pointer_address_modes_p ()
4888 && ! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4889 && mode
== Pmode
&& REG_POINTER (x
)
4890 && !targetm
.have_ptr_extend ())
4891 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4895 unsigned int copies_for_hook
= 1, copies
= 1;
4896 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, mode
, known_x
,
4897 known_mode
, known_ret
,
4901 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
4902 known_mode
, known_ret
);
4904 if (copies
> 1 || copies_for_hook
> 1)
4905 return MAX (copies
, copies_for_hook
);
4907 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4912 /* Some RISC machines sign-extend all loads of smaller than a word. */
4913 if (load_extend_op (GET_MODE (x
)) == SIGN_EXTEND
)
4914 return MAX (1, ((int) bitwidth
4915 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1));
4919 /* If the constant is negative, take its 1's complement and remask.
4920 Then see how many zero bits we have. */
4921 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4922 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4923 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
4924 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4926 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4929 /* If this is a SUBREG for a promoted object that is sign-extended
4930 and we are looking at it in a wider mode, we know that at least the
4931 high-order bits are known to be sign bit copies. */
4933 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
4935 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4936 known_x
, known_mode
, known_ret
);
4937 return MAX ((int) bitwidth
4938 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1,
4942 /* For a smaller object, just ignore the high bits. */
4943 inner_mode
= GET_MODE (SUBREG_REG (x
));
4944 if (bitwidth
<= GET_MODE_PRECISION (inner_mode
))
4946 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
,
4947 known_x
, known_mode
, known_ret
);
4949 MAX (1, num0
- (int) (GET_MODE_PRECISION (inner_mode
) - bitwidth
));
4952 /* For paradoxical SUBREGs on machines where all register operations
4953 affect the entire register, just look inside. Note that we are
4954 passing MODE to the recursive call, so the number of sign bit copies
4955 will remain relative to that mode, not the inner mode. */
4957 /* This works only if loads sign extend. Otherwise, if we get a
4958 reload for the inner part, it may be loaded from the stack, and
4959 then we lose all sign bit copies that existed before the store
4962 if (WORD_REGISTER_OPERATIONS
4963 && load_extend_op (inner_mode
) == SIGN_EXTEND
4964 && paradoxical_subreg_p (x
)
4965 && (MEM_P (SUBREG_REG (x
)) || REG_P (SUBREG_REG (x
))))
4966 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4967 known_x
, known_mode
, known_ret
);
4971 if (CONST_INT_P (XEXP (x
, 1)))
4972 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
4976 return (bitwidth
- GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4977 + cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4978 known_x
, known_mode
, known_ret
));
4981 /* For a smaller object, just ignore the high bits. */
4982 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4983 known_x
, known_mode
, known_ret
);
4984 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4988 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4989 known_x
, known_mode
, known_ret
);
4991 case ROTATE
: case ROTATERT
:
4992 /* If we are rotating left by a number of bits less than the number
4993 of sign bit copies, we can just subtract that amount from the
4995 if (CONST_INT_P (XEXP (x
, 1))
4996 && INTVAL (XEXP (x
, 1)) >= 0
4997 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
4999 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5000 known_x
, known_mode
, known_ret
);
5001 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
5002 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
5007 /* In general, this subtracts one sign bit copy. But if the value
5008 is known to be positive, the number of sign bit copies is the
5009 same as that of the input. Finally, if the input has just one bit
5010 that might be nonzero, all the bits are copies of the sign bit. */
5011 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5012 known_x
, known_mode
, known_ret
);
5013 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5014 return num0
> 1 ? num0
- 1 : 1;
5016 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5021 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
5026 case IOR
: case AND
: case XOR
:
5027 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5028 /* Logical operations will preserve the number of sign-bit copies.
5029 MIN and MAX operations always return one of the operands. */
5030 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5031 known_x
, known_mode
, known_ret
);
5032 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5033 known_x
, known_mode
, known_ret
);
5035 /* If num1 is clearing some of the top bits then regardless of
5036 the other term, we are guaranteed to have at least that many
5037 high-order zero bits. */
5040 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5041 && CONST_INT_P (XEXP (x
, 1))
5042 && (UINTVAL (XEXP (x
, 1))
5043 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5046 /* Similarly for IOR when setting high-order bits. */
5049 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5050 && CONST_INT_P (XEXP (x
, 1))
5051 && (UINTVAL (XEXP (x
, 1))
5052 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5055 return MIN (num0
, num1
);
5057 case PLUS
: case MINUS
:
5058 /* For addition and subtraction, we can have a 1-bit carry. However,
5059 if we are subtracting 1 from a positive number, there will not
5060 be such a carry. Furthermore, if the positive number is known to
5061 be 0 or 1, we know the result is either -1 or 0. */
5063 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5064 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5066 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5067 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5068 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5069 : bitwidth
- floor_log2 (nonzero
) - 1);
5072 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5073 known_x
, known_mode
, known_ret
);
5074 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5075 known_x
, known_mode
, known_ret
);
5076 result
= MAX (1, MIN (num0
, num1
) - 1);
5081 /* The number of bits of the product is the sum of the number of
5082 bits of both terms. However, unless one of the terms if known
5083 to be positive, we must allow for an additional bit since negating
5084 a negative number can remove one sign bit copy. */
5086 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5087 known_x
, known_mode
, known_ret
);
5088 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5089 known_x
, known_mode
, known_ret
);
5091 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5093 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5094 || (((nonzero_bits (XEXP (x
, 0), mode
)
5095 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5096 && ((nonzero_bits (XEXP (x
, 1), mode
)
5097 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5101 return MAX (1, result
);
5104 /* The result must be <= the first operand. If the first operand
5105 has the high bit set, we know nothing about the number of sign
5107 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5109 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5110 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5113 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5114 known_x
, known_mode
, known_ret
);
5117 /* The result must be <= the second operand. If the second operand
5118 has (or just might have) the high bit set, we know nothing about
5119 the number of sign bit copies. */
5120 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5122 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5123 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5126 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5127 known_x
, known_mode
, known_ret
);
5130 /* Similar to unsigned division, except that we have to worry about
5131 the case where the divisor is negative, in which case we have
5133 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5134 known_x
, known_mode
, known_ret
);
5136 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5137 || (nonzero_bits (XEXP (x
, 1), mode
)
5138 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5144 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5145 known_x
, known_mode
, known_ret
);
5147 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5148 || (nonzero_bits (XEXP (x
, 1), mode
)
5149 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5155 /* Shifts by a constant add to the number of bits equal to the
5157 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5158 known_x
, known_mode
, known_ret
);
5159 if (CONST_INT_P (XEXP (x
, 1))
5160 && INTVAL (XEXP (x
, 1)) > 0
5161 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
5162 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5167 /* Left shifts destroy copies. */
5168 if (!CONST_INT_P (XEXP (x
, 1))
5169 || INTVAL (XEXP (x
, 1)) < 0
5170 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5171 || INTVAL (XEXP (x
, 1)) >= GET_MODE_PRECISION (GET_MODE (x
)))
5174 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5175 known_x
, known_mode
, known_ret
);
5176 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5179 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5180 known_x
, known_mode
, known_ret
);
5181 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5182 known_x
, known_mode
, known_ret
);
5183 return MIN (num0
, num1
);
5185 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5186 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5187 case GEU
: case GTU
: case LEU
: case LTU
:
5188 case UNORDERED
: case ORDERED
:
5189 /* If the constant is negative, take its 1's complement and remask.
5190 Then see how many zero bits we have. */
5191 nonzero
= STORE_FLAG_VALUE
;
5192 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5193 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5194 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5196 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5202 /* If we haven't been able to figure it out by one of the above rules,
5203 see if some of the high-order bits are known to be zero. If so,
5204 count those bits and return one less than that amount. If we can't
5205 safely compute the mask for this mode, always return BITWIDTH. */
5207 bitwidth
= GET_MODE_PRECISION (mode
);
5208 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5211 nonzero
= nonzero_bits (x
, mode
);
5212 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5213 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5216 /* Calculate the rtx_cost of a single instruction. A return value of
5217 zero indicates an instruction pattern without a known cost. */
5220 insn_rtx_cost (rtx pat
, bool speed
)
5225 /* Extract the single set rtx from the instruction pattern.
5226 We can't use single_set since we only have the pattern. */
5227 if (GET_CODE (pat
) == SET
)
5229 else if (GET_CODE (pat
) == PARALLEL
)
5232 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5234 rtx x
= XVECEXP (pat
, 0, i
);
5235 if (GET_CODE (x
) == SET
)
5248 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5249 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5252 /* Returns estimate on cost of computing SEQ. */
5255 seq_cost (const rtx_insn
*seq
, bool speed
)
5260 for (; seq
; seq
= NEXT_INSN (seq
))
5262 set
= single_set (seq
);
5264 cost
+= set_rtx_cost (set
, speed
);
5272 /* Given an insn INSN and condition COND, return the condition in a
5273 canonical form to simplify testing by callers. Specifically:
5275 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5276 (2) Both operands will be machine operands; (cc0) will have been replaced.
5277 (3) If an operand is a constant, it will be the second operand.
5278 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5279 for GE, GEU, and LEU.
5281 If the condition cannot be understood, or is an inequality floating-point
5282 comparison which needs to be reversed, 0 will be returned.
5284 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5286 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5287 insn used in locating the condition was found. If a replacement test
5288 of the condition is desired, it should be placed in front of that
5289 insn and we will be sure that the inputs are still valid.
5291 If WANT_REG is nonzero, we wish the condition to be relative to that
5292 register, if possible. Therefore, do not canonicalize the condition
5293 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5294 to be a compare to a CC mode register.
5296 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5300 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5301 rtx_insn
**earliest
,
5302 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5305 rtx_insn
*prev
= insn
;
5309 int reverse_code
= 0;
5311 basic_block bb
= BLOCK_FOR_INSN (insn
);
5313 code
= GET_CODE (cond
);
5314 mode
= GET_MODE (cond
);
5315 op0
= XEXP (cond
, 0);
5316 op1
= XEXP (cond
, 1);
5319 code
= reversed_comparison_code (cond
, insn
);
5320 if (code
== UNKNOWN
)
5326 /* If we are comparing a register with zero, see if the register is set
5327 in the previous insn to a COMPARE or a comparison operation. Perform
5328 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5331 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5332 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5333 && op1
== CONST0_RTX (GET_MODE (op0
))
5336 /* Set nonzero when we find something of interest. */
5339 /* If comparison with cc0, import actual comparison from compare
5343 if ((prev
= prev_nonnote_insn (prev
)) == 0
5344 || !NONJUMP_INSN_P (prev
)
5345 || (set
= single_set (prev
)) == 0
5346 || SET_DEST (set
) != cc0_rtx
)
5349 op0
= SET_SRC (set
);
5350 op1
= CONST0_RTX (GET_MODE (op0
));
5355 /* If this is a COMPARE, pick up the two things being compared. */
5356 if (GET_CODE (op0
) == COMPARE
)
5358 op1
= XEXP (op0
, 1);
5359 op0
= XEXP (op0
, 0);
5362 else if (!REG_P (op0
))
5365 /* Go back to the previous insn. Stop if it is not an INSN. We also
5366 stop if it isn't a single set or if it has a REG_INC note because
5367 we don't want to bother dealing with it. */
5369 prev
= prev_nonnote_nondebug_insn (prev
);
5372 || !NONJUMP_INSN_P (prev
)
5373 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5374 /* In cfglayout mode, there do not have to be labels at the
5375 beginning of a block, or jumps at the end, so the previous
5376 conditions would not stop us when we reach bb boundary. */
5377 || BLOCK_FOR_INSN (prev
) != bb
)
5380 set
= set_of (op0
, prev
);
5383 && (GET_CODE (set
) != SET
5384 || !rtx_equal_p (SET_DEST (set
), op0
)))
5387 /* If this is setting OP0, get what it sets it to if it looks
5391 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5392 #ifdef FLOAT_STORE_FLAG_VALUE
5393 REAL_VALUE_TYPE fsfv
;
5396 /* ??? We may not combine comparisons done in a CCmode with
5397 comparisons not done in a CCmode. This is to aid targets
5398 like Alpha that have an IEEE compliant EQ instruction, and
5399 a non-IEEE compliant BEQ instruction. The use of CCmode is
5400 actually artificial, simply to prevent the combination, but
5401 should not affect other platforms.
5403 However, we must allow VOIDmode comparisons to match either
5404 CCmode or non-CCmode comparison, because some ports have
5405 modeless comparisons inside branch patterns.
5407 ??? This mode check should perhaps look more like the mode check
5408 in simplify_comparison in combine. */
5409 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5410 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5412 && inner_mode
!= VOIDmode
)
5414 if (GET_CODE (SET_SRC (set
)) == COMPARE
5417 && val_signbit_known_set_p (inner_mode
,
5419 #ifdef FLOAT_STORE_FLAG_VALUE
5421 && SCALAR_FLOAT_MODE_P (inner_mode
)
5422 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5423 REAL_VALUE_NEGATIVE (fsfv
)))
5426 && COMPARISON_P (SET_SRC (set
))))
5428 else if (((code
== EQ
5430 && val_signbit_known_set_p (inner_mode
,
5432 #ifdef FLOAT_STORE_FLAG_VALUE
5434 && SCALAR_FLOAT_MODE_P (inner_mode
)
5435 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5436 REAL_VALUE_NEGATIVE (fsfv
)))
5439 && COMPARISON_P (SET_SRC (set
)))
5444 else if ((code
== EQ
|| code
== NE
)
5445 && GET_CODE (SET_SRC (set
)) == XOR
)
5446 /* Handle sequences like:
5449 ...(eq|ne op0 (const_int 0))...
5453 (eq op0 (const_int 0)) reduces to (eq X Y)
5454 (ne op0 (const_int 0)) reduces to (ne X Y)
5456 This is the form used by MIPS16, for example. */
5462 else if (reg_set_p (op0
, prev
))
5463 /* If this sets OP0, but not directly, we have to give up. */
5468 /* If the caller is expecting the condition to be valid at INSN,
5469 make sure X doesn't change before INSN. */
5470 if (valid_at_insn_p
)
5471 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5473 if (COMPARISON_P (x
))
5474 code
= GET_CODE (x
);
5477 code
= reversed_comparison_code (x
, prev
);
5478 if (code
== UNKNOWN
)
5483 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5489 /* If constant is first, put it last. */
5490 if (CONSTANT_P (op0
))
5491 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5493 /* If OP0 is the result of a comparison, we weren't able to find what
5494 was really being compared, so fail. */
5496 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5499 /* Canonicalize any ordered comparison with integers involving equality
5500 if we can do computations in the relevant mode and we do not
5503 if (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_CC
5504 && CONST_INT_P (op1
)
5505 && GET_MODE (op0
) != VOIDmode
5506 && GET_MODE_PRECISION (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
)
5508 HOST_WIDE_INT const_val
= INTVAL (op1
);
5509 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5510 unsigned HOST_WIDE_INT max_val
5511 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (op0
));
5516 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5517 code
= LT
, op1
= gen_int_mode (const_val
+ 1, GET_MODE (op0
));
5520 /* When cross-compiling, const_val might be sign-extended from
5521 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5523 if ((const_val
& max_val
)
5524 != (HOST_WIDE_INT_1U
5525 << (GET_MODE_PRECISION (GET_MODE (op0
)) - 1)))
5526 code
= GT
, op1
= gen_int_mode (const_val
- 1, GET_MODE (op0
));
5530 if (uconst_val
< max_val
)
5531 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, GET_MODE (op0
));
5535 if (uconst_val
!= 0)
5536 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, GET_MODE (op0
));
5544 /* Never return CC0; return zero instead. */
5548 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5551 /* Given a jump insn JUMP, return the condition that will cause it to branch
5552 to its JUMP_LABEL. If the condition cannot be understood, or is an
5553 inequality floating-point comparison which needs to be reversed, 0 will
5556 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5557 insn used in locating the condition was found. If a replacement test
5558 of the condition is desired, it should be placed in front of that
5559 insn and we will be sure that the inputs are still valid. If EARLIEST
5560 is null, the returned condition will be valid at INSN.
5562 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5563 compare CC mode register.
5565 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5568 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5569 int valid_at_insn_p
)
5575 /* If this is not a standard conditional jump, we can't parse it. */
5577 || ! any_condjump_p (jump
))
5579 set
= pc_set (jump
);
5581 cond
= XEXP (SET_SRC (set
), 0);
5583 /* If this branches to JUMP_LABEL when the condition is false, reverse
5586 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5587 && label_ref_label (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5589 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5590 allow_cc_mode
, valid_at_insn_p
);
5593 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5594 TARGET_MODE_REP_EXTENDED.
5596 Note that we assume that the property of
5597 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5598 narrower than mode B. I.e., if A is a mode narrower than B then in
5599 order to be able to operate on it in mode B, mode A needs to
5600 satisfy the requirements set by the representation of mode B. */
5603 init_num_sign_bit_copies_in_rep (void)
5605 machine_mode mode
, in_mode
;
5607 for (in_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); in_mode
!= VOIDmode
;
5608 in_mode
= GET_MODE_WIDER_MODE (mode
))
5609 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= in_mode
;
5610 mode
= GET_MODE_WIDER_MODE (mode
))
5614 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5615 extends to the next widest mode. */
5616 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5617 || GET_MODE_WIDER_MODE (mode
) == in_mode
);
5619 /* We are in in_mode. Count how many bits outside of mode
5620 have to be copies of the sign-bit. */
5621 for (i
= mode
; i
!= in_mode
; i
= GET_MODE_WIDER_MODE (i
))
5623 machine_mode wider
= GET_MODE_WIDER_MODE (i
);
5625 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5626 /* We can only check sign-bit copies starting from the
5627 top-bit. In order to be able to check the bits we
5628 have already seen we pretend that subsequent bits
5629 have to be sign-bit copies too. */
5630 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5631 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5632 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5637 /* Suppose that truncation from the machine mode of X to MODE is not a
5638 no-op. See if there is anything special about X so that we can
5639 assume it already contains a truncated value of MODE. */
5642 truncated_to_mode (machine_mode mode
, const_rtx x
)
5644 /* This register has already been used in MODE without explicit
5646 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5649 /* See if we already satisfy the requirements of MODE. If yes we
5650 can just switch to MODE. */
5651 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5652 && (num_sign_bit_copies (x
, GET_MODE (x
))
5653 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5659 /* Return true if RTX code CODE has a single sequence of zero or more
5660 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5661 entry in that case. */
5664 setup_reg_subrtx_bounds (unsigned int code
)
5666 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5668 for (; format
[i
] != 'e'; ++i
)
5671 /* No subrtxes. Leave start and count as 0. */
5673 if (format
[i
] == 'E' || format
[i
] == 'V')
5677 /* Record the sequence of 'e's. */
5678 rtx_all_subrtx_bounds
[code
].start
= i
;
5681 while (format
[i
] == 'e');
5682 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5683 /* rtl-iter.h relies on this. */
5684 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5686 for (; format
[i
]; ++i
)
5687 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5693 /* Initialize rtx_all_subrtx_bounds. */
5698 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5700 if (!setup_reg_subrtx_bounds (i
))
5701 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5702 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5703 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5706 init_num_sign_bit_copies_in_rep ();
5709 /* Check whether this is a constant pool constant. */
5711 constant_pool_constant_p (rtx x
)
5713 x
= avoid_constant_pool_reference (x
);
5714 return CONST_DOUBLE_P (x
);
5717 /* If M is a bitmask that selects a field of low-order bits within an item but
5718 not the entire word, return the length of the field. Return -1 otherwise.
5719 M is used in machine mode MODE. */
5722 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5724 if (mode
!= VOIDmode
)
5726 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
5728 m
&= GET_MODE_MASK (mode
);
5731 return exact_log2 (m
+ 1);
5734 /* Return the mode of MEM's address. */
5737 get_address_mode (rtx mem
)
5741 gcc_assert (MEM_P (mem
));
5742 mode
= GET_MODE (XEXP (mem
, 0));
5743 if (mode
!= VOIDmode
)
5745 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5748 /* Split up a CONST_DOUBLE or integer constant rtx
5749 into two rtx's for single words,
5750 storing in *FIRST the word that comes first in memory in the target
5751 and in *SECOND the other.
5753 TODO: This function needs to be rewritten to work on any size
5757 split_double (rtx value
, rtx
*first
, rtx
*second
)
5759 if (CONST_INT_P (value
))
5761 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5763 /* In this case the CONST_INT holds both target words.
5764 Extract the bits from it into two word-sized pieces.
5765 Sign extend each half to HOST_WIDE_INT. */
5766 unsigned HOST_WIDE_INT low
, high
;
5767 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5768 unsigned bits_per_word
= BITS_PER_WORD
;
5770 /* Set sign_bit to the most significant bit of a word. */
5772 sign_bit
<<= bits_per_word
- 1;
5774 /* Set mask so that all bits of the word are set. We could
5775 have used 1 << BITS_PER_WORD instead of basing the
5776 calculation on sign_bit. However, on machines where
5777 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5778 compiler warning, even though the code would never be
5780 mask
= sign_bit
<< 1;
5783 /* Set sign_extend as any remaining bits. */
5784 sign_extend
= ~mask
;
5786 /* Pick the lower word and sign-extend it. */
5787 low
= INTVAL (value
);
5792 /* Pick the higher word, shifted to the least significant
5793 bits, and sign-extend it. */
5794 high
= INTVAL (value
);
5795 high
>>= bits_per_word
- 1;
5798 if (high
& sign_bit
)
5799 high
|= sign_extend
;
5801 /* Store the words in the target machine order. */
5802 if (WORDS_BIG_ENDIAN
)
5804 *first
= GEN_INT (high
);
5805 *second
= GEN_INT (low
);
5809 *first
= GEN_INT (low
);
5810 *second
= GEN_INT (high
);
5815 /* The rule for using CONST_INT for a wider mode
5816 is that we regard the value as signed.
5817 So sign-extend it. */
5818 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5819 if (WORDS_BIG_ENDIAN
)
5831 else if (GET_CODE (value
) == CONST_WIDE_INT
)
5833 /* All of this is scary code and needs to be converted to
5834 properly work with any size integer. */
5835 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
5836 if (WORDS_BIG_ENDIAN
)
5838 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5839 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5843 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5844 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5847 else if (!CONST_DOUBLE_P (value
))
5849 if (WORDS_BIG_ENDIAN
)
5851 *first
= const0_rtx
;
5857 *second
= const0_rtx
;
5860 else if (GET_MODE (value
) == VOIDmode
5861 /* This is the old way we did CONST_DOUBLE integers. */
5862 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5864 /* In an integer, the words are defined as most and least significant.
5865 So order them by the target's convention. */
5866 if (WORDS_BIG_ENDIAN
)
5868 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5869 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
5873 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
5874 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5881 /* Note, this converts the REAL_VALUE_TYPE to the target's
5882 format, splits up the floating point double and outputs
5883 exactly 32 bits of it into each of l[0] and l[1] --
5884 not necessarily BITS_PER_WORD bits. */
5885 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
5887 /* If 32 bits is an entire word for the target, but not for the host,
5888 then sign-extend on the host so that the number will look the same
5889 way on the host that it would on the target. See for instance
5890 simplify_unary_operation. The #if is needed to avoid compiler
5893 #if HOST_BITS_PER_LONG > 32
5894 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
5896 if (l
[0] & ((long) 1 << 31))
5897 l
[0] |= ((unsigned long) (-1) << 32);
5898 if (l
[1] & ((long) 1 << 31))
5899 l
[1] |= ((unsigned long) (-1) << 32);
5903 *first
= GEN_INT (l
[0]);
5904 *second
= GEN_INT (l
[1]);
5908 /* Return true if X is a sign_extract or zero_extract from the least
5912 lsb_bitfield_op_p (rtx x
)
5914 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
5916 machine_mode mode
= GET_MODE (XEXP (x
, 0));
5917 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
5918 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
5920 return (pos
== (BITS_BIG_ENDIAN
? GET_MODE_PRECISION (mode
) - len
: 0));
5925 /* Strip outer address "mutations" from LOC and return a pointer to the
5926 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5927 stripped expression there.
5929 "Mutations" either convert between modes or apply some kind of
5930 extension, truncation or alignment. */
5933 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
5937 enum rtx_code code
= GET_CODE (*loc
);
5938 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
5939 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5940 used to convert between pointer sizes. */
5941 loc
= &XEXP (*loc
, 0);
5942 else if (lsb_bitfield_op_p (*loc
))
5943 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
5944 acts as a combined truncation and extension. */
5945 loc
= &XEXP (*loc
, 0);
5946 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
5947 /* (and ... (const_int -X)) is used to align to X bytes. */
5948 loc
= &XEXP (*loc
, 0);
5949 else if (code
== SUBREG
5950 && !OBJECT_P (SUBREG_REG (*loc
))
5951 && subreg_lowpart_p (*loc
))
5952 /* (subreg (operator ...) ...) inside and is used for mode
5954 loc
= &SUBREG_REG (*loc
);
5962 /* Return true if CODE applies some kind of scale. The scaled value is
5963 is the first operand and the scale is the second. */
5966 binary_scale_code_p (enum rtx_code code
)
5968 return (code
== MULT
5970 /* Needed by ARM targets. */
5974 || code
== ROTATERT
);
5977 /* If *INNER can be interpreted as a base, return a pointer to the inner term
5978 (see address_info). Return null otherwise. */
5981 get_base_term (rtx
*inner
)
5983 if (GET_CODE (*inner
) == LO_SUM
)
5984 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5987 || GET_CODE (*inner
) == SUBREG
5988 || GET_CODE (*inner
) == SCRATCH
)
5993 /* If *INNER can be interpreted as an index, return a pointer to the inner term
5994 (see address_info). Return null otherwise. */
5997 get_index_term (rtx
*inner
)
5999 /* At present, only constant scales are allowed. */
6000 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
6001 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6004 || GET_CODE (*inner
) == SUBREG
6005 || GET_CODE (*inner
) == SCRATCH
)
6010 /* Set the segment part of address INFO to LOC, given that INNER is the
6014 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6016 gcc_assert (!info
->segment
);
6017 info
->segment
= loc
;
6018 info
->segment_term
= inner
;
6021 /* Set the base part of address INFO to LOC, given that INNER is the
6025 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6027 gcc_assert (!info
->base
);
6029 info
->base_term
= inner
;
6032 /* Set the index part of address INFO to LOC, given that INNER is the
6036 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6038 gcc_assert (!info
->index
);
6040 info
->index_term
= inner
;
6043 /* Set the displacement part of address INFO to LOC, given that INNER
6044 is the constant term. */
6047 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6049 gcc_assert (!info
->disp
);
6051 info
->disp_term
= inner
;
6054 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6055 rest of INFO accordingly. */
6058 decompose_incdec_address (struct address_info
*info
)
6060 info
->autoinc_p
= true;
6062 rtx
*base
= &XEXP (*info
->inner
, 0);
6063 set_address_base (info
, base
, base
);
6064 gcc_checking_assert (info
->base
== info
->base_term
);
6066 /* These addresses are only valid when the size of the addressed
6068 gcc_checking_assert (info
->mode
!= VOIDmode
);
6071 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6072 of INFO accordingly. */
6075 decompose_automod_address (struct address_info
*info
)
6077 info
->autoinc_p
= true;
6079 rtx
*base
= &XEXP (*info
->inner
, 0);
6080 set_address_base (info
, base
, base
);
6081 gcc_checking_assert (info
->base
== info
->base_term
);
6083 rtx plus
= XEXP (*info
->inner
, 1);
6084 gcc_assert (GET_CODE (plus
) == PLUS
);
6086 info
->base_term2
= &XEXP (plus
, 0);
6087 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6089 rtx
*step
= &XEXP (plus
, 1);
6090 rtx
*inner_step
= strip_address_mutations (step
);
6091 if (CONSTANT_P (*inner_step
))
6092 set_address_disp (info
, step
, inner_step
);
6094 set_address_index (info
, step
, inner_step
);
6097 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6098 values in [PTR, END). Return a pointer to the end of the used array. */
6101 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6104 if (GET_CODE (x
) == PLUS
)
6106 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6107 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6111 gcc_assert (ptr
!= end
);
6117 /* Evaluate the likelihood of X being a base or index value, returning
6118 positive if it is likely to be a base, negative if it is likely to be
6119 an index, and 0 if we can't tell. Make the magnitude of the return
6120 value reflect the amount of confidence we have in the answer.
6122 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6125 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6126 enum rtx_code outer_code
, enum rtx_code index_code
)
6128 /* Believe *_POINTER unless the address shape requires otherwise. */
6129 if (REG_P (x
) && REG_POINTER (x
))
6131 if (MEM_P (x
) && MEM_POINTER (x
))
6134 if (REG_P (x
) && HARD_REGISTER_P (x
))
6136 /* X is a hard register. If it only fits one of the base
6137 or index classes, choose that interpretation. */
6138 int regno
= REGNO (x
);
6139 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6140 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6141 if (base_p
!= index_p
)
6142 return base_p
? 1 : -1;
6147 /* INFO->INNER describes a normal, non-automodified address.
6148 Fill in the rest of INFO accordingly. */
6151 decompose_normal_address (struct address_info
*info
)
6153 /* Treat the address as the sum of up to four values. */
6155 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6156 ops
+ ARRAY_SIZE (ops
)) - ops
;
6158 /* If there is more than one component, any base component is in a PLUS. */
6160 info
->base_outer_code
= PLUS
;
6162 /* Try to classify each sum operand now. Leave those that could be
6163 either a base or an index in OPS. */
6166 for (size_t in
= 0; in
< n_ops
; ++in
)
6169 rtx
*inner
= strip_address_mutations (loc
);
6170 if (CONSTANT_P (*inner
))
6171 set_address_disp (info
, loc
, inner
);
6172 else if (GET_CODE (*inner
) == UNSPEC
)
6173 set_address_segment (info
, loc
, inner
);
6176 /* The only other possibilities are a base or an index. */
6177 rtx
*base_term
= get_base_term (inner
);
6178 rtx
*index_term
= get_index_term (inner
);
6179 gcc_assert (base_term
|| index_term
);
6181 set_address_index (info
, loc
, index_term
);
6182 else if (!index_term
)
6183 set_address_base (info
, loc
, base_term
);
6186 gcc_assert (base_term
== index_term
);
6188 inner_ops
[out
] = base_term
;
6194 /* Classify the remaining OPS members as bases and indexes. */
6197 /* If we haven't seen a base or an index yet, assume that this is
6198 the base. If we were confident that another term was the base
6199 or index, treat the remaining operand as the other kind. */
6201 set_address_base (info
, ops
[0], inner_ops
[0]);
6203 set_address_index (info
, ops
[0], inner_ops
[0]);
6207 /* In the event of a tie, assume the base comes first. */
6208 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6210 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6211 GET_CODE (*ops
[0])))
6213 set_address_base (info
, ops
[0], inner_ops
[0]);
6214 set_address_index (info
, ops
[1], inner_ops
[1]);
6218 set_address_base (info
, ops
[1], inner_ops
[1]);
6219 set_address_index (info
, ops
[0], inner_ops
[0]);
6223 gcc_assert (out
== 0);
6226 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6227 or VOIDmode if not known. AS is the address space associated with LOC.
6228 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6231 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6232 addr_space_t as
, enum rtx_code outer_code
)
6234 memset (info
, 0, sizeof (*info
));
6237 info
->addr_outer_code
= outer_code
;
6239 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6240 info
->base_outer_code
= outer_code
;
6241 switch (GET_CODE (*info
->inner
))
6247 decompose_incdec_address (info
);
6252 decompose_automod_address (info
);
6256 decompose_normal_address (info
);
6261 /* Describe address operand LOC in INFO. */
6264 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6266 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6269 /* Describe the address of MEM X in INFO. */
6272 decompose_mem_address (struct address_info
*info
, rtx x
)
6274 gcc_assert (MEM_P (x
));
6275 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6276 MEM_ADDR_SPACE (x
), MEM
);
6279 /* Update INFO after a change to the address it describes. */
6282 update_address (struct address_info
*info
)
6284 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6285 info
->addr_outer_code
);
6288 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6289 more complicated than that. */
6292 get_index_scale (const struct address_info
*info
)
6294 rtx index
= *info
->index
;
6295 if (GET_CODE (index
) == MULT
6296 && CONST_INT_P (XEXP (index
, 1))
6297 && info
->index_term
== &XEXP (index
, 0))
6298 return INTVAL (XEXP (index
, 1));
6300 if (GET_CODE (index
) == ASHIFT
6301 && CONST_INT_P (XEXP (index
, 1))
6302 && info
->index_term
== &XEXP (index
, 0))
6303 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6305 if (info
->index
== info
->index_term
)
6311 /* Return the "index code" of INFO, in the form required by
6315 get_index_code (const struct address_info
*info
)
6318 return GET_CODE (*info
->index
);
6321 return GET_CODE (*info
->disp
);
6326 /* Return true if RTL X contains a SYMBOL_REF. */
6329 contains_symbol_ref_p (const_rtx x
)
6331 subrtx_iterator::array_type array
;
6332 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6333 if (SYMBOL_REF_P (*iter
))
6339 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6342 contains_symbolic_reference_p (const_rtx x
)
6344 subrtx_iterator::array_type array
;
6345 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6346 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6352 /* Return true if X contains a thread-local symbol. */
6355 tls_referenced_p (const_rtx x
)
6357 if (!targetm
.have_tls
)
6360 subrtx_iterator::array_type array
;
6361 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6362 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)