1 ;; ARM 926EJ-S Pipeline Description
2 ;; Copyright (C) 2003-2013 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; These descriptions are based on the information contained in the
22 ;; ARM926EJ-S Technical Reference Manual, Copyright (c) 2002 ARM
26 ;; This automaton provides a pipeline description for the ARM
29 ;; The model given here assumes that the condition for all conditional
30 ;; instructions is "true", i.e., that all of the instructions are
33 (define_automaton "arm926ejs")
35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
39 ;; There is a single pipeline
41 ;; The ALU pipeline has fetch, decode, execute, memory, and
42 ;; write stages. We only need to model the execute, memory and write
45 (define_cpu_unit "e,m,w" "arm926ejs")
47 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
49 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
51 ;; ALU instructions require three cycles to execute, and use the ALU
52 ;; pipeline in each of the three stages. The results are available
53 ;; after the execute stage stage has finished.
55 ;; If the destination register is the PC, the pipelines are stalled
56 ;; for several cycles. That case is not modeled here.
58 ;; ALU operations with no shifted operand
59 (define_insn_reservation "9_alu_op" 1
60 (and (eq_attr "tune" "arm926ejs")
61 (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,\
62 mov_imm,mov_reg,mov_shift,\
63 mvn_imm,mvn_reg,mvn_shift"))
66 ;; ALU operations with a shift-by-register operand
67 ;; These really stall in the decoder, in order to read
68 ;; the shift value in a second cycle. Pretend we take two cycles in
70 (define_insn_reservation "9_alu_shift_reg_op" 2
71 (and (eq_attr "tune" "arm926ejs")
72 (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
75 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
76 ;; Multiplication Instructions
77 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
79 ;; Multiplication instructions loop in the execute stage until the
80 ;; instruction has been passed through the multiplier array enough
81 ;; times. Multiply operations occur in both the execute and memory
82 ;; stages of the pipeline
84 (define_insn_reservation "9_mult1" 3
85 (and (eq_attr "tune" "arm926ejs")
86 (eq_attr "type" "smlalxy,mul,mla"))
89 (define_insn_reservation "9_mult2" 4
90 (and (eq_attr "tune" "arm926ejs")
91 (eq_attr "type" "muls,mlas"))
94 (define_insn_reservation "9_mult3" 4
95 (and (eq_attr "tune" "arm926ejs")
96 (eq_attr "type" "umull,umlal,smull,smlal"))
99 (define_insn_reservation "9_mult4" 5
100 (and (eq_attr "tune" "arm926ejs")
101 (eq_attr "type" "umulls,umlals,smulls,smlals"))
104 (define_insn_reservation "9_mult5" 2
105 (and (eq_attr "tune" "arm926ejs")
106 (eq_attr "type" "smulxy,smlaxy,smlawx"))
109 (define_insn_reservation "9_mult6" 3
110 (and (eq_attr "tune" "arm926ejs")
111 (eq_attr "type" "smlalxy"))
114 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
115 ;; Load/Store Instructions
116 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
118 ;; The models for load/store instructions do not accurately describe
119 ;; the difference between operations with a base register writeback
120 ;; (such as "ldm!"). These models assume that all memory references
123 ;; Loads with a shifted offset take 3 cycles, and are (a) probably the
124 ;; most common and (b) the pessimistic assumption will lead to fewer stalls.
125 (define_insn_reservation "9_load1_op" 3
126 (and (eq_attr "tune" "arm926ejs")
127 (eq_attr "type" "load1,load_byte"))
130 (define_insn_reservation "9_store1_op" 0
131 (and (eq_attr "tune" "arm926ejs")
132 (eq_attr "type" "store1"))
135 ;; multiple word loads and stores
136 (define_insn_reservation "9_load2_op" 3
137 (and (eq_attr "tune" "arm926ejs")
138 (eq_attr "type" "load2"))
141 (define_insn_reservation "9_load3_op" 4
142 (and (eq_attr "tune" "arm926ejs")
143 (eq_attr "type" "load3"))
146 (define_insn_reservation "9_load4_op" 5
147 (and (eq_attr "tune" "arm926ejs")
148 (eq_attr "type" "load4"))
151 (define_insn_reservation "9_store2_op" 0
152 (and (eq_attr "tune" "arm926ejs")
153 (eq_attr "type" "store2"))
156 (define_insn_reservation "9_store3_op" 0
157 (and (eq_attr "tune" "arm926ejs")
158 (eq_attr "type" "store3"))
161 (define_insn_reservation "9_store4_op" 0
162 (and (eq_attr "tune" "arm926ejs")
163 (eq_attr "type" "store4"))
166 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
167 ;; Branch and Call Instructions
168 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
170 ;; Branch instructions are difficult to model accurately. The ARM
171 ;; core can predict most branches. If the branch is predicted
172 ;; correctly, and predicted early enough, the branch can be completely
173 ;; eliminated from the instruction stream. Some branches can
174 ;; therefore appear to require zero cycles to execute. We assume that
175 ;; all branches are predicted correctly, and that the latency is
176 ;; therefore the minimum value.
178 (define_insn_reservation "9_branch_op" 0
179 (and (eq_attr "tune" "arm926ejs")
180 (eq_attr "type" "branch"))
183 ;; The latency for a call is not predictable. Therefore, we use 32 as
184 ;; roughly equivalent to positive infinity.
186 (define_insn_reservation "9_call_op" 32
187 (and (eq_attr "tune" "arm926ejs")
188 (eq_attr "type" "call"))