1 ; Copyright (C) 2005-2015 Free Software Foundation, Inc.
3 ; This file is part of GCC.
5 ; GCC is free software; you can redistribute it and/or modify it under
6 ; the terms of the GNU General Public License as published by the Free
7 ; Software Foundation; either version 3, or (at your option) any later
10 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
11 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 ; You should have received a copy of the GNU General Public License
16 ; along with GCC; see the file COPYING3. If not see
17 ; <http://www.gnu.org/licenses/>.
20 config/ia64/ia64-opts.h
22 ; Which cpu are we scheduling for.
24 enum processor_type ia64_tune = PROCESSOR_ITANIUM2
27 Target Report RejectNegative Mask(BIG_ENDIAN)
28 Generate big endian code
31 Target Report RejectNegative InverseMask(BIG_ENDIAN)
32 Generate little endian code
35 Target Report Mask(GNU_AS)
36 Generate code for GNU as
39 Target Report Mask(GNU_LD)
40 Generate code for GNU ld
43 Target Report Mask(VOL_ASM_STOP)
44 Emit stop bits before and after volatile extended asms
47 Target Mask(REG_NAMES)
48 Use in/loc/out register names
51 Target Report RejectNegative Mask(NO_SDATA)
54 Target Report RejectNegative InverseMask(NO_SDATA)
55 Enable use of sdata/scommon/sbss
58 Target Report RejectNegative Mask(NO_PIC)
59 Generate code without GP reg
62 Target Report RejectNegative Mask(CONST_GP)
63 gp is constant (but save/restore gp on indirect calls)
66 Target Report RejectNegative Mask(AUTO_PIC)
67 Generate self-relocatable code
69 minline-float-divide-min-latency
70 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
71 Generate inline floating point division, optimize for latency
73 minline-float-divide-max-throughput
74 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
75 Generate inline floating point division, optimize for throughput
77 mno-inline-float-divide
78 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
80 minline-int-divide-min-latency
81 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
82 Generate inline integer division, optimize for latency
84 minline-int-divide-max-throughput
85 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
86 Generate inline integer division, optimize for throughput
89 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
90 Do not inline integer division
92 minline-sqrt-min-latency
93 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1)
94 Generate inline square root, optimize for latency
96 minline-sqrt-max-throughput
97 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2)
98 Generate inline square root, optimize for throughput
101 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0)
102 Do not inline square root
105 Target Report Mask(DWARF2_ASM)
106 Enable Dwarf 2 line debug info via GNU as
109 Target Report Mask(EARLY_STOP_BITS)
110 Enable earlier placing stop bits for better scheduling
113 Target RejectNegative Joined Var(ia64_deferred_options) Defer
114 Specify range of registers to make fixed
117 Target RejectNegative Joined UInteger Var(ia64_tls_size) Init(22)
118 Specify bit size of immediate TLS offsets
121 Target RejectNegative Joined Enum(ia64_tune) Var(ia64_tune)
122 Schedule code for given CPU
125 Name(ia64_tune) Type(enum processor_type)
126 Known Itanium CPUs (for use with the -mtune= option):
129 Enum(ia64_tune) String(itanium2) Value(PROCESSOR_ITANIUM2)
132 Enum(ia64_tune) String(mckinley) Value(PROCESSOR_ITANIUM2)
135 Target Report Var(mflag_sched_br_data_spec) Init(0)
136 Use data speculation before reload
139 Target Report Var(mflag_sched_ar_data_spec) Init(1)
140 Use data speculation after reload
143 Target Report Var(mflag_sched_control_spec) Init(2)
144 Use control speculation
146 msched-br-in-data-spec
147 Target Report Var(mflag_sched_br_in_data_spec) Init(1)
148 Use in block data speculation before reload
150 msched-ar-in-data-spec
151 Target Report Var(mflag_sched_ar_in_data_spec) Init(1)
152 Use in block data speculation after reload
154 msched-in-control-spec
155 Target Report Var(mflag_sched_in_control_spec) Init(1)
156 Use in block control speculation
159 Target Report Var(mflag_sched_spec_ldc) Init(1)
160 Use simple data speculation check
162 msched-spec-control-ldc
163 Target Report Var(mflag_sched_spec_control_ldc) Init(0)
164 Use simple data speculation check for control speculation
166 msched-prefer-non-data-spec-insns
167 Target Ignore Warn(switch %qs is no longer supported)
169 msched-prefer-non-control-spec-insns
170 Target Ignore Warn(switch %qs is no longer supported)
172 msched-count-spec-in-critical-path
173 Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
174 Count speculative dependencies while calculating priority of instructions
176 msched-stop-bits-after-every-cycle
177 Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
178 Place a stop bit after every cycle when scheduling
180 msched-fp-mem-deps-zero-cost
181 Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
182 Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group
184 msched-max-memory-insns=
185 Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1)
186 Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1
188 msched-max-memory-insns-hard-limit
189 Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0)
190 Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached)
192 msel-sched-dont-check-control-spec
193 Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
194 Don't generate checks for control speculation in selective scheduling
196 ; This comment is to ensure we retain the blank line above.