| blob | 3ab031622d6d1bcbbe3c310520e5fafb1600b2c2 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2013 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
60 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
61 (TOC_SAVE_OFFSET_32BIT 20)
62 (TOC_SAVE_OFFSET_64BIT 40)
64 ; Function TOC offset in the AIX function descriptor.
65 (AIX_FUNC_DESC_TOC_32BIT 4)
66 (AIX_FUNC_DESC_TOC_64BIT 8)
68 ; Static chain offset in the AIX function descriptor.
69 (AIX_FUNC_DESC_SC_32BIT 8)
70 (AIX_FUNC_DESC_SC_64BIT 16)
71 ])
73 ;;
74 ;; UNSPEC usage
75 ;;
77 (define_c_enum "unspec"
78 [UNSPEC_FRSP ; frsp for POWER machines
79 UNSPEC_PROBE_STACK ; probe stack memory reference
80 UNSPEC_TOCPTR ; address of a word pointing to the TOC
81 UNSPEC_TOC ; address of the TOC (more-or-less)
82 UNSPEC_MOVSI_GOT
83 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
84 UNSPEC_FCTIWZ
85 UNSPEC_FRIM
86 UNSPEC_FRIN
87 UNSPEC_FRIP
88 UNSPEC_FRIZ
89 UNSPEC_LD_MPIC ; load_macho_picbase
90 UNSPEC_MPIC_CORRECT ; macho_correct_pic
91 UNSPEC_TLSGD
92 UNSPEC_TLSLD
93 UNSPEC_MOVESI_FROM_CR
94 UNSPEC_MOVESI_TO_CR
95 UNSPEC_TLSDTPREL
96 UNSPEC_TLSDTPRELHA
97 UNSPEC_TLSDTPRELLO
98 UNSPEC_TLSGOTDTPREL
99 UNSPEC_TLSTPREL
100 UNSPEC_TLSTPRELHA
101 UNSPEC_TLSTPRELLO
102 UNSPEC_TLSGOTTPREL
103 UNSPEC_TLSTLS
104 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
105 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
106 UNSPEC_STFIWX
107 UNSPEC_POPCNTB
108 UNSPEC_FRES
109 UNSPEC_SP_SET
110 UNSPEC_SP_TEST
111 UNSPEC_SYNC
112 UNSPEC_LWSYNC
113 UNSPEC_SYNC_OP
114 UNSPEC_ATOMIC
115 UNSPEC_CMPXCHG
116 UNSPEC_XCHG
117 UNSPEC_AND
118 UNSPEC_DLMZB
119 UNSPEC_DLMZB_CR
120 UNSPEC_DLMZB_STRLEN
121 UNSPEC_RSQRT
122 UNSPEC_TOCREL
123 UNSPEC_MACHOPIC_OFFSET
124 UNSPEC_BPERM
125 UNSPEC_COPYSIGN
126 UNSPEC_PARITY
127 UNSPEC_FCTIW
128 UNSPEC_FCTID
129 UNSPEC_LFIWAX
130 UNSPEC_LFIWZX
131 UNSPEC_FCTIWUZ
132 UNSPEC_GRP_END_NOP
133 UNSPEC_P8V_FMRGOW
134 UNSPEC_P8V_MTVSRWZ
135 UNSPEC_P8V_RELOAD_FROM_GPR
136 UNSPEC_P8V_MTVSRD
137 UNSPEC_P8V_XXPERMDI
138 UNSPEC_P8V_RELOAD_FROM_VSX
139 ])
141 ;;
142 ;; UNSPEC_VOLATILE usage
143 ;;
145 (define_c_enum "unspecv"
146 [UNSPECV_BLOCK
147 UNSPECV_LL ; load-locked
148 UNSPECV_SC ; store-conditional
149 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
150 UNSPECV_EH_RR ; eh_reg_restore
151 UNSPECV_ISYNC ; isync instruction
152 UNSPECV_MFTB ; move from time base
153 ])
155 \f
156 ;; Define an insn type attribute. This is used in function unit delay
157 ;; computations.
158 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"
159 (const_string "integer"))
161 ;; Define floating point instruction sub-types for use with Xfpu.md
162 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
164 ;; Length (in bytes).
165 ; '(pc)' in the following doesn't include the instruction itself; it is
166 ; calculated as if the instruction had zero size.
167 (define_attr "length" ""
168 (if_then_else (eq_attr "type" "branch")
169 (if_then_else (and (ge (minus (match_dup 0) (pc))
170 (const_int -32768))
171 (lt (minus (match_dup 0) (pc))
172 (const_int 32764)))
173 (const_int 4)
174 (const_int 8))
175 (const_int 4)))
177 ;; Processor type -- this attribute must exactly match the processor_type
178 ;; enumeration in rs6000-opts.h.
179 (define_attr "cpu"
180 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
181 ppc750,ppc7400,ppc7450,
182 ppc403,ppc405,ppc440,ppc476,
183 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
184 power4,power5,power6,power7,power8,
185 rs64a,mpccore,cell,ppca2,titan"
186 (const (symbol_ref "rs6000_cpu_attr")))
189 ;; If this instruction is microcoded on the CELL processor
190 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
191 (define_attr "cell_micro" "not,conditional,always"
192 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
193 (const_string "always")
194 (const_string "not")))
196 (automata_option "ndfa")
198 (include "rs64.md")
199 (include "mpc.md")
200 (include "40x.md")
201 (include "440.md")
202 (include "476.md")
203 (include "601.md")
204 (include "603.md")
205 (include "6xx.md")
206 (include "7xx.md")
207 (include "7450.md")
208 (include "8540.md")
209 (include "e300c2c3.md")
210 (include "e500mc.md")
211 (include "e500mc64.md")
212 (include "e5500.md")
213 (include "e6500.md")
214 (include "power4.md")
215 (include "power5.md")
216 (include "power6.md")
217 (include "power7.md")
218 (include "power8.md")
219 (include "cell.md")
220 (include "xfpu.md")
221 (include "a2.md")
222 (include "titan.md")
224 (include "predicates.md")
225 (include "constraints.md")
227 (include "darwin.md")
229 \f
230 ;; Mode iterators
232 ; This mode iterator allows :GPR to be used to indicate the allowable size
233 ; of whole values in GPRs.
234 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
236 ; Any supported integer mode.
237 (define_mode_iterator INT [QI HI SI DI TI PTI])
239 ; Any supported integer mode that fits in one register.
240 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
242 ; extend modes for DImode
243 (define_mode_iterator QHSI [QI HI SI])
245 ; QImode or HImode for small atomic ops
246 (define_mode_iterator QHI [QI HI])
248 ; HImode or SImode for sign extended fusion ops
249 (define_mode_iterator HSI [HI SI])
251 ; SImode or DImode, even if DImode doesn't fit in GPRs.
252 (define_mode_iterator SDI [SI DI])
254 ; The size of a pointer. Also, the size of the value that a record-condition
255 ; (one with a '.') will compare; and the size used for arithmetic carries.
256 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
258 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
259 ; PTImode is GPR only)
260 (define_mode_iterator TI2 [TI PTI])
262 ; Any hardware-supported floating-point mode
263 (define_mode_iterator FP [
264 (SF "TARGET_HARD_FLOAT
265 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
266 (DF "TARGET_HARD_FLOAT
267 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
268 (TF "!TARGET_IEEEQUAD
269 && TARGET_HARD_FLOAT
270 && (TARGET_FPRS || TARGET_E500_DOUBLE)
271 && TARGET_LONG_DOUBLE_128")
272 (DD "TARGET_DFP")
273 (TD "TARGET_DFP")])
275 ; Any fma capable floating-point mode.
276 (define_mode_iterator FMA_F [
277 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
278 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
279 || VECTOR_UNIT_VSX_P (DFmode)")
280 (V2SF "TARGET_PAIRED_FLOAT")
281 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
282 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
283 ])
285 ; Floating point move iterators to combine binary and decimal moves
286 (define_mode_iterator FMOVE32 [SF SD])
287 (define_mode_iterator FMOVE64 [DF DD])
288 (define_mode_iterator FMOVE64X [DI DF DD])
289 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
290 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
292 ; Iterators for 128 bit types for direct move
293 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
294 (V16QI "")
295 (V8HI "")
296 (V4SI "")
297 (V4SF "")
298 (V2DI "")
299 (V2DF "")])
301 ; Whether a floating point move is ok, don't allow SD without hardware FP
302 (define_mode_attr fmove_ok [(SF "")
303 (DF "")
304 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
305 (DD "")])
307 ; Convert REAL_VALUE to the appropriate bits
308 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
309 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
310 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
311 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
313 ; Definitions for load to 32-bit fpr register
314 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
315 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
316 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
317 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
319 ; Definitions for store from 32-bit fpr register
320 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
321 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
322 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
323 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
325 ; Definitions for 32-bit fpr direct move
326 (define_mode_attr f32_dm [(SF "wn") (SD "wm")])
328 ; These modes do not fit in integer registers in 32-bit mode.
329 ; but on e500v2, the gpr are 64 bit registers
330 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
332 ; Iterator for reciprocal estimate instructions
333 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
335 ; Iterator for just SF/DF
336 (define_mode_iterator SFDF [SF DF])
338 ; Conditional returns.
339 (define_code_iterator any_return [return simple_return])
340 (define_code_attr return_pred [(return "direct_return ()")
341 (simple_return "1")])
342 (define_code_attr return_str [(return "") (simple_return "simple_")])
344 ; Various instructions that come in SI and DI forms.
345 ; A generic w/d attribute, for things like cmpw/cmpd.
346 (define_mode_attr wd [(QI "b")
347 (HI "h")
348 (SI "w")
349 (DI "d")
350 (V16QI "b")
351 (V8HI "h")
352 (V4SI "w")
353 (V2DI "d")])
355 ; DImode bits
356 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
358 ;; ISEL/ISEL64 target selection
359 (define_mode_attr sel [(SI "") (DI "64")])
361 ;; Suffix for reload patterns
362 (define_mode_attr ptrsize [(SI "32bit")
363 (DI "64bit")])
365 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
366 (DI "TARGET_64BIT")])
368 (define_mode_attr mptrsize [(SI "si")
369 (DI "di")])
371 (define_mode_attr ptrload [(SI "lwz")
372 (DI "ld")])
374 (define_mode_attr ptrm [(SI "m")
375 (DI "Y")])
377 (define_mode_attr rreg [(SF "f")
378 (DF "ws")
379 (V4SF "wf")
380 (V2DF "wd")])
382 (define_mode_attr rreg2 [(SF "f")
383 (DF "d")])
385 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
386 (DF "TARGET_FCFID")])
388 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
389 (DF "TARGET_E500_DOUBLE")])
391 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
392 (DF "TARGET_DOUBLE_FLOAT")])
394 ;; Mode iterator for logical operations on 128-bit types
395 (define_mode_iterator BOOL_128 [TI
396 PTI
397 (V16QI "TARGET_ALTIVEC")
398 (V8HI "TARGET_ALTIVEC")
399 (V4SI "TARGET_ALTIVEC")
400 (V4SF "TARGET_ALTIVEC")
401 (V2DI "TARGET_ALTIVEC")
402 (V2DF "TARGET_ALTIVEC")])
404 ;; For the GPRs we use 3 constraints for register outputs, two that are the
405 ;; same as the output register, and a third where the output register is an
406 ;; early clobber, so we don't have to deal with register overlaps. For the
407 ;; vector types, we prefer to use the vector registers. For TI mode, allow
408 ;; either.
410 ;; Mode attribute for boolean operation register constraints for output
411 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
412 (PTI "&r,r,r")
413 (V16QI "wa,v,&?r,?r,?r")
414 (V8HI "wa,v,&?r,?r,?r")
415 (V4SI "wa,v,&?r,?r,?r")
416 (V4SF "wa,v,&?r,?r,?r")
417 (V2DI "wa,v,&?r,?r,?r")
418 (V2DF "wa,v,&?r,?r,?r")])
420 ;; Mode attribute for boolean operation register constraints for operand1
421 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
422 (PTI "r,0,r")
423 (V16QI "wa,v,r,0,r")
424 (V8HI "wa,v,r,0,r")
425 (V4SI "wa,v,r,0,r")
426 (V4SF "wa,v,r,0,r")
427 (V2DI "wa,v,r,0,r")
428 (V2DF "wa,v,r,0,r")])
430 ;; Mode attribute for boolean operation register constraints for operand2
431 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
432 (PTI "r,r,0")
433 (V16QI "wa,v,r,r,0")
434 (V8HI "wa,v,r,r,0")
435 (V4SI "wa,v,r,r,0")
436 (V4SF "wa,v,r,r,0")
437 (V2DI "wa,v,r,r,0")
438 (V2DF "wa,v,r,r,0")])
440 ;; Mode attribute for boolean operation register constraints for operand1
441 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
442 ;; is used for operand1 or operand2
443 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
444 (PTI "r,0,0")
445 (V16QI "wa,v,r,0,0")
446 (V8HI "wa,v,r,0,0")
447 (V4SI "wa,v,r,0,0")
448 (V4SF "wa,v,r,0,0")
449 (V2DI "wa,v,r,0,0")
450 (V2DF "wa,v,r,0,0")])
452 ;; Mode attribute for the clobber of CC0 for AND expansion.
453 ;; For the 128-bit types, we never do AND immediate, but we need to
454 ;; get the correct number of X's for the number of operands.
455 (define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
456 (PTI "X,X,X")
457 (V16QI "X,X,X,X,X")
458 (V8HI "X,X,X,X,X")
459 (V4SI "X,X,X,X,X")
460 (V4SF "X,X,X,X,X")
461 (V2DI "X,X,X,X,X")
462 (V2DF "X,X,X,X,X")])
464 \f
465 ;; Start with fixed-point load and store insns. Here we put only the more
466 ;; complex forms. Basic data transfer is done later.
468 (define_expand "zero_extend<mode>di2"
469 [(set (match_operand:DI 0 "gpc_reg_operand" "")
470 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
471 "TARGET_POWERPC64"
472 "")
474 (define_insn "*zero_extend<mode>di2_internal1"
475 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
476 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
477 "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
478 "@
479 l<wd>z%U1%X1 %0,%1
480 rldicl %0,%1,0,<dbits>"
481 [(set_attr_alternative "type"
482 [(if_then_else
483 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
484 (const_string "load_ux")
485 (if_then_else
486 (match_test "update_address_mem (operands[1], VOIDmode)")
487 (const_string "load_u")
488 (const_string "load")))
489 (const_string "*")])])
491 (define_insn "*zero_extend<mode>di2_internal2"
492 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
493 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
494 (const_int 0)))
495 (clobber (match_scratch:DI 2 "=r,r"))]
496 "TARGET_64BIT"
497 "@
498 rldicl. %2,%1,0,<dbits>
499 #"
500 [(set_attr "type" "compare")
501 (set_attr "length" "4,8")])
503 (define_split
504 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
505 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
506 (const_int 0)))
507 (clobber (match_scratch:DI 2 ""))]
508 "TARGET_POWERPC64 && reload_completed"
509 [(set (match_dup 2)
510 (zero_extend:DI (match_dup 1)))
511 (set (match_dup 0)
512 (compare:CC (match_dup 2)
513 (const_int 0)))]
514 "")
516 (define_insn "*zero_extend<mode>di2_internal3"
517 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
518 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
519 (const_int 0)))
520 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
521 (zero_extend:DI (match_dup 1)))]
522 "TARGET_64BIT"
523 "@
524 rldicl. %0,%1,0,<dbits>
525 #"
526 [(set_attr "type" "compare")
527 (set_attr "length" "4,8")])
529 (define_split
530 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
531 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
532 (const_int 0)))
533 (set (match_operand:DI 0 "gpc_reg_operand" "")
534 (zero_extend:DI (match_dup 1)))]
535 "TARGET_POWERPC64 && reload_completed"
536 [(set (match_dup 0)
537 (zero_extend:DI (match_dup 1)))
538 (set (match_dup 2)
539 (compare:CC (match_dup 0)
540 (const_int 0)))]
541 "")
543 (define_insn "*zero_extendsidi2_lfiwzx"
544 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
545 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
546 "TARGET_POWERPC64 && TARGET_LFIWZX"
547 "@
548 lwz%U1%X1 %0,%1
549 rldicl %0,%1,0,32
550 mtvsrwz %x0,%1
551 lfiwzx %0,%y1
552 lxsiwzx %x0,%y1"
553 [(set_attr_alternative "type"
554 [(if_then_else
555 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
556 (const_string "load_ux")
557 (if_then_else
558 (match_test "update_address_mem (operands[1], VOIDmode)")
559 (const_string "load_u")
560 (const_string "load")))
561 (const_string "*")
562 (const_string "mffgpr")
563 (const_string "fpload")
564 (const_string "fpload")])])
566 (define_insn "extendqidi2"
567 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
568 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
569 "TARGET_POWERPC64"
570 "extsb %0,%1"
571 [(set_attr "type" "exts")])
573 (define_insn ""
574 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
575 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
576 (const_int 0)))
577 (clobber (match_scratch:DI 2 "=r,r"))]
578 "TARGET_64BIT"
579 "@
580 extsb. %2,%1
581 #"
582 [(set_attr "type" "compare")
583 (set_attr "length" "4,8")])
585 (define_split
586 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
587 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
588 (const_int 0)))
589 (clobber (match_scratch:DI 2 ""))]
590 "TARGET_POWERPC64 && reload_completed"
591 [(set (match_dup 2)
592 (sign_extend:DI (match_dup 1)))
593 (set (match_dup 0)
594 (compare:CC (match_dup 2)
595 (const_int 0)))]
596 "")
598 (define_insn ""
599 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
600 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
601 (const_int 0)))
602 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
603 (sign_extend:DI (match_dup 1)))]
604 "TARGET_64BIT"
605 "@
606 extsb. %0,%1
607 #"
608 [(set_attr "type" "compare")
609 (set_attr "length" "4,8")])
611 (define_split
612 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
613 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
614 (const_int 0)))
615 (set (match_operand:DI 0 "gpc_reg_operand" "")
616 (sign_extend:DI (match_dup 1)))]
617 "TARGET_POWERPC64 && reload_completed"
618 [(set (match_dup 0)
619 (sign_extend:DI (match_dup 1)))
620 (set (match_dup 2)
621 (compare:CC (match_dup 0)
622 (const_int 0)))]
623 "")
625 (define_expand "extendhidi2"
626 [(set (match_operand:DI 0 "gpc_reg_operand" "")
627 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
628 "TARGET_POWERPC64"
629 "")
631 (define_insn ""
632 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
633 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
634 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
635 "@
636 lha%U1%X1 %0,%1
637 extsh %0,%1"
638 [(set_attr_alternative "type"
639 [(if_then_else
640 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
641 (const_string "load_ext_ux")
642 (if_then_else
643 (match_test "update_address_mem (operands[1], VOIDmode)")
644 (const_string "load_ext_u")
645 (const_string "load_ext")))
646 (const_string "exts")])])
648 (define_insn ""
649 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
650 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
651 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
652 "extsh %0,%1"
653 [(set_attr "type" "exts")])
655 (define_insn ""
656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
657 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
658 (const_int 0)))
659 (clobber (match_scratch:DI 2 "=r,r"))]
660 "TARGET_64BIT"
661 "@
662 extsh. %2,%1
663 #"
664 [(set_attr "type" "compare")
665 (set_attr "length" "4,8")])
667 (define_split
668 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
669 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
670 (const_int 0)))
671 (clobber (match_scratch:DI 2 ""))]
672 "TARGET_POWERPC64 && reload_completed"
673 [(set (match_dup 2)
674 (sign_extend:DI (match_dup 1)))
675 (set (match_dup 0)
676 (compare:CC (match_dup 2)
677 (const_int 0)))]
678 "")
680 (define_insn ""
681 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
682 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
683 (const_int 0)))
684 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
685 (sign_extend:DI (match_dup 1)))]
686 "TARGET_64BIT"
687 "@
688 extsh. %0,%1
689 #"
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
693 (define_split
694 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
695 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
696 (const_int 0)))
697 (set (match_operand:DI 0 "gpc_reg_operand" "")
698 (sign_extend:DI (match_dup 1)))]
699 "TARGET_POWERPC64 && reload_completed"
700 [(set (match_dup 0)
701 (sign_extend:DI (match_dup 1)))
702 (set (match_dup 2)
703 (compare:CC (match_dup 0)
704 (const_int 0)))]
705 "")
707 (define_expand "extendsidi2"
708 [(set (match_operand:DI 0 "gpc_reg_operand" "")
709 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
710 "TARGET_POWERPC64"
711 "")
713 (define_insn "*extendsidi2_lfiwax"
714 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
715 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))]
716 "TARGET_POWERPC64 && TARGET_LFIWAX"
717 "@
718 lwa%U1%X1 %0,%1
719 extsw %0,%1
720 mtvsrwa %x0,%1
721 lfiwax %0,%y1
722 lxsiwax %x0,%y1"
723 [(set_attr_alternative "type"
724 [(if_then_else
725 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
726 (const_string "load_ext_ux")
727 (if_then_else
728 (match_test "update_address_mem (operands[1], VOIDmode)")
729 (const_string "load_ext_u")
730 (const_string "load_ext")))
731 (const_string "exts")
732 (const_string "mffgpr")
733 (const_string "fpload")
734 (const_string "fpload")])])
736 (define_insn "*extendsidi2_nocell"
737 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
738 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
739 "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
740 "@
741 lwa%U1%X1 %0,%1
742 extsw %0,%1"
743 [(set_attr_alternative "type"
744 [(if_then_else
745 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
746 (const_string "load_ext_ux")
747 (if_then_else
748 (match_test "update_address_mem (operands[1], VOIDmode)")
749 (const_string "load_ext_u")
750 (const_string "load_ext")))
751 (const_string "exts")])])
753 (define_insn "*extendsidi2_nocell"
754 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
755 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
756 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
757 "extsw %0,%1"
758 [(set_attr "type" "exts")])
760 (define_insn ""
761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
762 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
763 (const_int 0)))
764 (clobber (match_scratch:DI 2 "=r,r"))]
765 "TARGET_64BIT"
766 "@
767 extsw. %2,%1
768 #"
769 [(set_attr "type" "compare")
770 (set_attr "length" "4,8")])
772 (define_split
773 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
774 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
775 (const_int 0)))
776 (clobber (match_scratch:DI 2 ""))]
777 "TARGET_POWERPC64 && reload_completed"
778 [(set (match_dup 2)
779 (sign_extend:DI (match_dup 1)))
780 (set (match_dup 0)
781 (compare:CC (match_dup 2)
782 (const_int 0)))]
783 "")
785 (define_insn ""
786 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
787 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
788 (const_int 0)))
789 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
790 (sign_extend:DI (match_dup 1)))]
791 "TARGET_64BIT"
792 "@
793 extsw. %0,%1
794 #"
795 [(set_attr "type" "compare")
796 (set_attr "length" "4,8")])
798 (define_split
799 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
800 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
801 (const_int 0)))
802 (set (match_operand:DI 0 "gpc_reg_operand" "")
803 (sign_extend:DI (match_dup 1)))]
804 "TARGET_POWERPC64 && reload_completed"
805 [(set (match_dup 0)
806 (sign_extend:DI (match_dup 1)))
807 (set (match_dup 2)
808 (compare:CC (match_dup 0)
809 (const_int 0)))]
810 "")
812 (define_expand "zero_extendqisi2"
813 [(set (match_operand:SI 0 "gpc_reg_operand" "")
814 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
815 ""
816 "")
818 (define_insn ""
819 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
820 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
821 ""
822 "@
823 lbz%U1%X1 %0,%1
824 rlwinm %0,%1,0,0xff"
825 [(set_attr_alternative "type"
826 [(if_then_else
827 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
828 (const_string "load_ux")
829 (if_then_else
830 (match_test "update_address_mem (operands[1], VOIDmode)")
831 (const_string "load_u")
832 (const_string "load")))
833 (const_string "*")])])
835 (define_insn ""
836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
837 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
838 (const_int 0)))
839 (clobber (match_scratch:SI 2 "=r,r"))]
840 ""
841 "@
842 andi. %2,%1,0xff
843 #"
844 [(set_attr "type" "fast_compare,compare")
845 (set_attr "length" "4,8")])
847 (define_split
848 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
849 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
850 (const_int 0)))
851 (clobber (match_scratch:SI 2 ""))]
852 "reload_completed"
853 [(set (match_dup 2)
854 (zero_extend:SI (match_dup 1)))
855 (set (match_dup 0)
856 (compare:CC (match_dup 2)
857 (const_int 0)))]
858 "")
860 (define_insn ""
861 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
862 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
863 (const_int 0)))
864 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
865 (zero_extend:SI (match_dup 1)))]
866 ""
867 "@
868 andi. %0,%1,0xff
869 #"
870 [(set_attr "type" "fast_compare,compare")
871 (set_attr "length" "4,8")])
873 (define_split
874 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
875 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
876 (const_int 0)))
877 (set (match_operand:SI 0 "gpc_reg_operand" "")
878 (zero_extend:SI (match_dup 1)))]
879 "reload_completed"
880 [(set (match_dup 0)
881 (zero_extend:SI (match_dup 1)))
882 (set (match_dup 2)
883 (compare:CC (match_dup 0)
884 (const_int 0)))]
885 "")
887 (define_insn "extendqisi2"
888 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
889 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
890 ""
891 "extsb %0,%1"
892 [(set_attr "type" "exts")])
894 (define_insn ""
895 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
896 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
897 (const_int 0)))
898 (clobber (match_scratch:SI 2 "=r,r"))]
899 ""
900 "@
901 extsb. %2,%1
902 #"
903 [(set_attr "type" "compare")
904 (set_attr "length" "4,8")])
906 (define_split
907 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
908 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
909 (const_int 0)))
910 (clobber (match_scratch:SI 2 ""))]
911 "reload_completed"
912 [(set (match_dup 2)
913 (sign_extend:SI (match_dup 1)))
914 (set (match_dup 0)
915 (compare:CC (match_dup 2)
916 (const_int 0)))]
917 "")
919 (define_insn ""
920 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
921 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
922 (const_int 0)))
923 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
924 (sign_extend:SI (match_dup 1)))]
925 ""
926 "@
927 extsb. %0,%1
928 #"
929 [(set_attr "type" "compare")
930 (set_attr "length" "4,8")])
932 (define_split
933 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
934 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
935 (const_int 0)))
936 (set (match_operand:SI 0 "gpc_reg_operand" "")
937 (sign_extend:SI (match_dup 1)))]
938 "reload_completed"
939 [(set (match_dup 0)
940 (sign_extend:SI (match_dup 1)))
941 (set (match_dup 2)
942 (compare:CC (match_dup 0)
943 (const_int 0)))]
944 "")
946 (define_insn ""
947 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
948 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
949 ""
950 "@
951 lbz%U1%X1 %0,%1
952 rlwinm %0,%1,0,0xff"
953 [(set_attr_alternative "type"
954 [(if_then_else
955 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
956 (const_string "load_ux")
957 (if_then_else
958 (match_test "update_address_mem (operands[1], VOIDmode)")
959 (const_string "load_u")
960 (const_string "load")))
961 (const_string "*")])])
963 (define_insn ""
964 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
965 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
966 (const_int 0)))
967 (clobber (match_scratch:HI 2 "=r,r"))]
968 ""
969 "@
970 andi. %2,%1,0xff
971 #"
972 [(set_attr "type" "fast_compare,compare")
973 (set_attr "length" "4,8")])
975 (define_split
976 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
977 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
978 (const_int 0)))
979 (clobber (match_scratch:HI 2 ""))]
980 "reload_completed"
981 [(set (match_dup 2)
982 (zero_extend:HI (match_dup 1)))
983 (set (match_dup 0)
984 (compare:CC (match_dup 2)
985 (const_int 0)))]
986 "")
988 (define_insn ""
989 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
990 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
991 (const_int 0)))
992 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
993 (zero_extend:HI (match_dup 1)))]
994 ""
995 "@
996 andi. %0,%1,0xff
997 #"
998 [(set_attr "type" "fast_compare,compare")
999 (set_attr "length" "4,8")])
1001 (define_split
1002 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1003 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1004 (const_int 0)))
1005 (set (match_operand:HI 0 "gpc_reg_operand" "")
1006 (zero_extend:HI (match_dup 1)))]
1007 "reload_completed"
1008 [(set (match_dup 0)
1009 (zero_extend:HI (match_dup 1)))
1010 (set (match_dup 2)
1011 (compare:CC (match_dup 0)
1012 (const_int 0)))]
1013 "")
1015 (define_insn "extendqihi2"
1016 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1017 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1018 ""
1019 "extsb %0,%1"
1020 [(set_attr "type" "exts")])
1022 (define_insn ""
1023 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1024 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1025 (const_int 0)))
1026 (clobber (match_scratch:HI 2 "=r,r"))]
1027 ""
1028 "@
1029 extsb. %2,%1
1030 #"
1031 [(set_attr "type" "compare")
1032 (set_attr "length" "4,8")])
1034 (define_split
1035 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1036 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1037 (const_int 0)))
1038 (clobber (match_scratch:HI 2 ""))]
1039 "reload_completed"
1040 [(set (match_dup 2)
1041 (sign_extend:HI (match_dup 1)))
1042 (set (match_dup 0)
1043 (compare:CC (match_dup 2)
1044 (const_int 0)))]
1045 "")
1047 (define_insn ""
1048 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1049 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1050 (const_int 0)))
1051 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1052 (sign_extend:HI (match_dup 1)))]
1053 ""
1054 "@
1055 extsb. %0,%1
1056 #"
1057 [(set_attr "type" "compare")
1058 (set_attr "length" "4,8")])
1060 (define_split
1061 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1062 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1063 (const_int 0)))
1064 (set (match_operand:HI 0 "gpc_reg_operand" "")
1065 (sign_extend:HI (match_dup 1)))]
1066 "reload_completed"
1067 [(set (match_dup 0)
1068 (sign_extend:HI (match_dup 1)))
1069 (set (match_dup 2)
1070 (compare:CC (match_dup 0)
1071 (const_int 0)))]
1072 "")
1074 (define_expand "zero_extendhisi2"
1075 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1076 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1077 ""
1078 "")
1080 (define_insn ""
1081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1082 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1083 ""
1084 "@
1085 lhz%U1%X1 %0,%1
1086 rlwinm %0,%1,0,0xffff"
1087 [(set_attr_alternative "type"
1088 [(if_then_else
1089 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1090 (const_string "load_ux")
1091 (if_then_else
1092 (match_test "update_address_mem (operands[1], VOIDmode)")
1093 (const_string "load_u")
1094 (const_string "load")))
1095 (const_string "*")])])
1097 (define_insn ""
1098 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1099 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1100 (const_int 0)))
1101 (clobber (match_scratch:SI 2 "=r,r"))]
1102 ""
1103 "@
1104 andi. %2,%1,0xffff
1105 #"
1106 [(set_attr "type" "fast_compare,compare")
1107 (set_attr "length" "4,8")])
1109 (define_split
1110 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1111 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1112 (const_int 0)))
1113 (clobber (match_scratch:SI 2 ""))]
1114 "reload_completed"
1115 [(set (match_dup 2)
1116 (zero_extend:SI (match_dup 1)))
1117 (set (match_dup 0)
1118 (compare:CC (match_dup 2)
1119 (const_int 0)))]
1120 "")
1122 (define_insn ""
1123 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1124 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1125 (const_int 0)))
1126 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1127 (zero_extend:SI (match_dup 1)))]
1128 ""
1129 "@
1130 andi. %0,%1,0xffff
1131 #"
1132 [(set_attr "type" "fast_compare,compare")
1133 (set_attr "length" "4,8")])
1135 (define_split
1136 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1137 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1138 (const_int 0)))
1139 (set (match_operand:SI 0 "gpc_reg_operand" "")
1140 (zero_extend:SI (match_dup 1)))]
1141 "reload_completed"
1142 [(set (match_dup 0)
1143 (zero_extend:SI (match_dup 1)))
1144 (set (match_dup 2)
1145 (compare:CC (match_dup 0)
1146 (const_int 0)))]
1147 "")
1149 (define_expand "extendhisi2"
1150 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1151 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1152 ""
1153 "")
1155 (define_insn ""
1156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1157 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1158 "rs6000_gen_cell_microcode"
1159 "@
1160 lha%U1%X1 %0,%1
1161 extsh %0,%1"
1162 [(set_attr_alternative "type"
1163 [(if_then_else
1164 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1165 (const_string "load_ext_ux")
1166 (if_then_else
1167 (match_test "update_address_mem (operands[1], VOIDmode)")
1168 (const_string "load_ext_u")
1169 (const_string "load_ext")))
1170 (const_string "exts")])])
1172 (define_insn ""
1173 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1174 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1175 "!rs6000_gen_cell_microcode"
1176 "extsh %0,%1"
1177 [(set_attr "type" "exts")])
1179 (define_insn ""
1180 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1181 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1182 (const_int 0)))
1183 (clobber (match_scratch:SI 2 "=r,r"))]
1184 ""
1185 "@
1186 extsh. %2,%1
1187 #"
1188 [(set_attr "type" "compare")
1189 (set_attr "length" "4,8")])
1191 (define_split
1192 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1193 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1194 (const_int 0)))
1195 (clobber (match_scratch:SI 2 ""))]
1196 "reload_completed"
1197 [(set (match_dup 2)
1198 (sign_extend:SI (match_dup 1)))
1199 (set (match_dup 0)
1200 (compare:CC (match_dup 2)
1201 (const_int 0)))]
1202 "")
1204 (define_insn ""
1205 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1206 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1207 (const_int 0)))
1208 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1209 (sign_extend:SI (match_dup 1)))]
1210 ""
1211 "@
1212 extsh. %0,%1
1213 #"
1214 [(set_attr "type" "compare")
1215 (set_attr "length" "4,8")])
1217 (define_split
1218 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1219 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1220 (const_int 0)))
1221 (set (match_operand:SI 0 "gpc_reg_operand" "")
1222 (sign_extend:SI (match_dup 1)))]
1223 "reload_completed"
1224 [(set (match_dup 0)
1225 (sign_extend:SI (match_dup 1)))
1226 (set (match_dup 2)
1227 (compare:CC (match_dup 0)
1228 (const_int 0)))]
1229 "")
1230 \f
1231 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1233 (define_insn "*macchwc"
1234 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1235 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1236 (match_operand:SI 2 "gpc_reg_operand" "r")
1237 (const_int 16))
1238 (sign_extend:SI
1239 (match_operand:HI 1 "gpc_reg_operand" "r")))
1240 (match_operand:SI 4 "gpc_reg_operand" "0"))
1241 (const_int 0)))
1242 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 (plus:SI (mult:SI (ashiftrt:SI
1244 (match_dup 2)
1245 (const_int 16))
1246 (sign_extend:SI
1247 (match_dup 1)))
1248 (match_dup 4)))]
1249 "TARGET_MULHW"
1250 "macchw. %0,%1,%2"
1251 [(set_attr "type" "imul3")])
1253 (define_insn "*macchw"
1254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 (plus:SI (mult:SI (ashiftrt:SI
1256 (match_operand:SI 2 "gpc_reg_operand" "r")
1257 (const_int 16))
1258 (sign_extend:SI
1259 (match_operand:HI 1 "gpc_reg_operand" "r")))
1260 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1261 "TARGET_MULHW"
1262 "macchw %0,%1,%2"
1263 [(set_attr "type" "imul3")])
1265 (define_insn "*macchwuc"
1266 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1267 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1268 (match_operand:SI 2 "gpc_reg_operand" "r")
1269 (const_int 16))
1270 (zero_extend:SI
1271 (match_operand:HI 1 "gpc_reg_operand" "r")))
1272 (match_operand:SI 4 "gpc_reg_operand" "0"))
1273 (const_int 0)))
1274 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (plus:SI (mult:SI (lshiftrt:SI
1276 (match_dup 2)
1277 (const_int 16))
1278 (zero_extend:SI
1279 (match_dup 1)))
1280 (match_dup 4)))]
1281 "TARGET_MULHW"
1282 "macchwu. %0,%1,%2"
1283 [(set_attr "type" "imul3")])
1285 (define_insn "*macchwu"
1286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1287 (plus:SI (mult:SI (lshiftrt:SI
1288 (match_operand:SI 2 "gpc_reg_operand" "r")
1289 (const_int 16))
1290 (zero_extend:SI
1291 (match_operand:HI 1 "gpc_reg_operand" "r")))
1292 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1293 "TARGET_MULHW"
1294 "macchwu %0,%1,%2"
1295 [(set_attr "type" "imul3")])
1297 (define_insn "*machhwc"
1298 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1299 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1300 (match_operand:SI 1 "gpc_reg_operand" "%r")
1301 (const_int 16))
1302 (ashiftrt:SI
1303 (match_operand:SI 2 "gpc_reg_operand" "r")
1304 (const_int 16)))
1305 (match_operand:SI 4 "gpc_reg_operand" "0"))
1306 (const_int 0)))
1307 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1308 (plus:SI (mult:SI (ashiftrt:SI
1309 (match_dup 1)
1310 (const_int 16))
1311 (ashiftrt:SI
1312 (match_dup 2)
1313 (const_int 16)))
1314 (match_dup 4)))]
1315 "TARGET_MULHW"
1316 "machhw. %0,%1,%2"
1317 [(set_attr "type" "imul3")])
1319 (define_insn "*machhw"
1320 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1321 (plus:SI (mult:SI (ashiftrt:SI
1322 (match_operand:SI 1 "gpc_reg_operand" "%r")
1323 (const_int 16))
1324 (ashiftrt:SI
1325 (match_operand:SI 2 "gpc_reg_operand" "r")
1326 (const_int 16)))
1327 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1328 "TARGET_MULHW"
1329 "machhw %0,%1,%2"
1330 [(set_attr "type" "imul3")])
1332 (define_insn "*machhwuc"
1333 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1334 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1335 (match_operand:SI 1 "gpc_reg_operand" "%r")
1336 (const_int 16))
1337 (lshiftrt:SI
1338 (match_operand:SI 2 "gpc_reg_operand" "r")
1339 (const_int 16)))
1340 (match_operand:SI 4 "gpc_reg_operand" "0"))
1341 (const_int 0)))
1342 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1343 (plus:SI (mult:SI (lshiftrt:SI
1344 (match_dup 1)
1345 (const_int 16))
1346 (lshiftrt:SI
1347 (match_dup 2)
1348 (const_int 16)))
1349 (match_dup 4)))]
1350 "TARGET_MULHW"
1351 "machhwu. %0,%1,%2"
1352 [(set_attr "type" "imul3")])
1354 (define_insn "*machhwu"
1355 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (plus:SI (mult:SI (lshiftrt:SI
1357 (match_operand:SI 1 "gpc_reg_operand" "%r")
1358 (const_int 16))
1359 (lshiftrt:SI
1360 (match_operand:SI 2 "gpc_reg_operand" "r")
1361 (const_int 16)))
1362 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1363 "TARGET_MULHW"
1364 "machhwu %0,%1,%2"
1365 [(set_attr "type" "imul3")])
1367 (define_insn "*maclhwc"
1368 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1369 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1370 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1371 (sign_extend:SI
1372 (match_operand:HI 2 "gpc_reg_operand" "r")))
1373 (match_operand:SI 4 "gpc_reg_operand" "0"))
1374 (const_int 0)))
1375 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1376 (plus:SI (mult:SI (sign_extend:SI
1377 (match_dup 1))
1378 (sign_extend:SI
1379 (match_dup 2)))
1380 (match_dup 4)))]
1381 "TARGET_MULHW"
1382 "maclhw. %0,%1,%2"
1383 [(set_attr "type" "imul3")])
1385 (define_insn "*maclhw"
1386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1387 (plus:SI (mult:SI (sign_extend:SI
1388 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1389 (sign_extend:SI
1390 (match_operand:HI 2 "gpc_reg_operand" "r")))
1391 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1392 "TARGET_MULHW"
1393 "maclhw %0,%1,%2"
1394 [(set_attr "type" "imul3")])
1396 (define_insn "*maclhwuc"
1397 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1398 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1399 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1400 (zero_extend:SI
1401 (match_operand:HI 2 "gpc_reg_operand" "r")))
1402 (match_operand:SI 4 "gpc_reg_operand" "0"))
1403 (const_int 0)))
1404 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1405 (plus:SI (mult:SI (zero_extend:SI
1406 (match_dup 1))
1407 (zero_extend:SI
1408 (match_dup 2)))
1409 (match_dup 4)))]
1410 "TARGET_MULHW"
1411 "maclhwu. %0,%1,%2"
1412 [(set_attr "type" "imul3")])
1414 (define_insn "*maclhwu"
1415 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1416 (plus:SI (mult:SI (zero_extend:SI
1417 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1418 (zero_extend:SI
1419 (match_operand:HI 2 "gpc_reg_operand" "r")))
1420 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1421 "TARGET_MULHW"
1422 "maclhwu %0,%1,%2"
1423 [(set_attr "type" "imul3")])
1425 (define_insn "*nmacchwc"
1426 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1427 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1428 (mult:SI (ashiftrt:SI
1429 (match_operand:SI 2 "gpc_reg_operand" "r")
1430 (const_int 16))
1431 (sign_extend:SI
1432 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1433 (const_int 0)))
1434 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1435 (minus:SI (match_dup 4)
1436 (mult:SI (ashiftrt:SI
1437 (match_dup 2)
1438 (const_int 16))
1439 (sign_extend:SI
1440 (match_dup 1)))))]
1441 "TARGET_MULHW"
1442 "nmacchw. %0,%1,%2"
1443 [(set_attr "type" "imul3")])
1445 (define_insn "*nmacchw"
1446 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1447 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1448 (mult:SI (ashiftrt:SI
1449 (match_operand:SI 2 "gpc_reg_operand" "r")
1450 (const_int 16))
1451 (sign_extend:SI
1452 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1453 "TARGET_MULHW"
1454 "nmacchw %0,%1,%2"
1455 [(set_attr "type" "imul3")])
1457 (define_insn "*nmachhwc"
1458 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1459 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1460 (mult:SI (ashiftrt:SI
1461 (match_operand:SI 1 "gpc_reg_operand" "%r")
1462 (const_int 16))
1463 (ashiftrt:SI
1464 (match_operand:SI 2 "gpc_reg_operand" "r")
1465 (const_int 16))))
1466 (const_int 0)))
1467 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1468 (minus:SI (match_dup 4)
1469 (mult:SI (ashiftrt:SI
1470 (match_dup 1)
1471 (const_int 16))
1472 (ashiftrt:SI
1473 (match_dup 2)
1474 (const_int 16)))))]
1475 "TARGET_MULHW"
1476 "nmachhw. %0,%1,%2"
1477 [(set_attr "type" "imul3")])
1479 (define_insn "*nmachhw"
1480 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1481 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1482 (mult:SI (ashiftrt:SI
1483 (match_operand:SI 1 "gpc_reg_operand" "%r")
1484 (const_int 16))
1485 (ashiftrt:SI
1486 (match_operand:SI 2 "gpc_reg_operand" "r")
1487 (const_int 16)))))]
1488 "TARGET_MULHW"
1489 "nmachhw %0,%1,%2"
1490 [(set_attr "type" "imul3")])
1492 (define_insn "*nmaclhwc"
1493 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1494 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1495 (mult:SI (sign_extend:SI
1496 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1497 (sign_extend:SI
1498 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1499 (const_int 0)))
1500 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1501 (minus:SI (match_dup 4)
1502 (mult:SI (sign_extend:SI
1503 (match_dup 1))
1504 (sign_extend:SI
1505 (match_dup 2)))))]
1506 "TARGET_MULHW"
1507 "nmaclhw. %0,%1,%2"
1508 [(set_attr "type" "imul3")])
1510 (define_insn "*nmaclhw"
1511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1512 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1513 (mult:SI (sign_extend:SI
1514 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1515 (sign_extend:SI
1516 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1517 "TARGET_MULHW"
1518 "nmaclhw %0,%1,%2"
1519 [(set_attr "type" "imul3")])
1521 (define_insn "*mulchwc"
1522 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1523 (compare:CC (mult:SI (ashiftrt:SI
1524 (match_operand:SI 2 "gpc_reg_operand" "r")
1525 (const_int 16))
1526 (sign_extend:SI
1527 (match_operand:HI 1 "gpc_reg_operand" "r")))
1528 (const_int 0)))
1529 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1530 (mult:SI (ashiftrt:SI
1531 (match_dup 2)
1532 (const_int 16))
1533 (sign_extend:SI
1534 (match_dup 1))))]
1535 "TARGET_MULHW"
1536 "mulchw. %0,%1,%2"
1537 [(set_attr "type" "imul3")])
1539 (define_insn "*mulchw"
1540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1541 (mult:SI (ashiftrt:SI
1542 (match_operand:SI 2 "gpc_reg_operand" "r")
1543 (const_int 16))
1544 (sign_extend:SI
1545 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1546 "TARGET_MULHW"
1547 "mulchw %0,%1,%2"
1548 [(set_attr "type" "imul3")])
1550 (define_insn "*mulchwuc"
1551 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1552 (compare:CC (mult:SI (lshiftrt:SI
1553 (match_operand:SI 2 "gpc_reg_operand" "r")
1554 (const_int 16))
1555 (zero_extend:SI
1556 (match_operand:HI 1 "gpc_reg_operand" "r")))
1557 (const_int 0)))
1558 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1559 (mult:SI (lshiftrt:SI
1560 (match_dup 2)
1561 (const_int 16))
1562 (zero_extend:SI
1563 (match_dup 1))))]
1564 "TARGET_MULHW"
1565 "mulchwu. %0,%1,%2"
1566 [(set_attr "type" "imul3")])
1568 (define_insn "*mulchwu"
1569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1570 (mult:SI (lshiftrt:SI
1571 (match_operand:SI 2 "gpc_reg_operand" "r")
1572 (const_int 16))
1573 (zero_extend:SI
1574 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1575 "TARGET_MULHW"
1576 "mulchwu %0,%1,%2"
1577 [(set_attr "type" "imul3")])
1579 (define_insn "*mulhhwc"
1580 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1581 (compare:CC (mult:SI (ashiftrt:SI
1582 (match_operand:SI 1 "gpc_reg_operand" "%r")
1583 (const_int 16))
1584 (ashiftrt:SI
1585 (match_operand:SI 2 "gpc_reg_operand" "r")
1586 (const_int 16)))
1587 (const_int 0)))
1588 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1589 (mult:SI (ashiftrt:SI
1590 (match_dup 1)
1591 (const_int 16))
1592 (ashiftrt:SI
1593 (match_dup 2)
1594 (const_int 16))))]
1595 "TARGET_MULHW"
1596 "mulhhw. %0,%1,%2"
1597 [(set_attr "type" "imul3")])
1599 (define_insn "*mulhhw"
1600 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1601 (mult:SI (ashiftrt:SI
1602 (match_operand:SI 1 "gpc_reg_operand" "%r")
1603 (const_int 16))
1604 (ashiftrt:SI
1605 (match_operand:SI 2 "gpc_reg_operand" "r")
1606 (const_int 16))))]
1607 "TARGET_MULHW"
1608 "mulhhw %0,%1,%2"
1609 [(set_attr "type" "imul3")])
1611 (define_insn "*mulhhwuc"
1612 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1613 (compare:CC (mult:SI (lshiftrt:SI
1614 (match_operand:SI 1 "gpc_reg_operand" "%r")
1615 (const_int 16))
1616 (lshiftrt:SI
1617 (match_operand:SI 2 "gpc_reg_operand" "r")
1618 (const_int 16)))
1619 (const_int 0)))
1620 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1621 (mult:SI (lshiftrt:SI
1622 (match_dup 1)
1623 (const_int 16))
1624 (lshiftrt:SI
1625 (match_dup 2)
1626 (const_int 16))))]
1627 "TARGET_MULHW"
1628 "mulhhwu. %0,%1,%2"
1629 [(set_attr "type" "imul3")])
1631 (define_insn "*mulhhwu"
1632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1633 (mult:SI (lshiftrt:SI
1634 (match_operand:SI 1 "gpc_reg_operand" "%r")
1635 (const_int 16))
1636 (lshiftrt:SI
1637 (match_operand:SI 2 "gpc_reg_operand" "r")
1638 (const_int 16))))]
1639 "TARGET_MULHW"
1640 "mulhhwu %0,%1,%2"
1641 [(set_attr "type" "imul3")])
1643 (define_insn "*mullhwc"
1644 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1645 (compare:CC (mult:SI (sign_extend:SI
1646 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1647 (sign_extend:SI
1648 (match_operand:HI 2 "gpc_reg_operand" "r")))
1649 (const_int 0)))
1650 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1651 (mult:SI (sign_extend:SI
1652 (match_dup 1))
1653 (sign_extend:SI
1654 (match_dup 2))))]
1655 "TARGET_MULHW"
1656 "mullhw. %0,%1,%2"
1657 [(set_attr "type" "imul3")])
1659 (define_insn "*mullhw"
1660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1661 (mult:SI (sign_extend:SI
1662 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1663 (sign_extend:SI
1664 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1665 "TARGET_MULHW"
1666 "mullhw %0,%1,%2"
1667 [(set_attr "type" "imul3")])
1669 (define_insn "*mullhwuc"
1670 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1671 (compare:CC (mult:SI (zero_extend:SI
1672 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1673 (zero_extend:SI
1674 (match_operand:HI 2 "gpc_reg_operand" "r")))
1675 (const_int 0)))
1676 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1677 (mult:SI (zero_extend:SI
1678 (match_dup 1))
1679 (zero_extend:SI
1680 (match_dup 2))))]
1681 "TARGET_MULHW"
1682 "mullhwu. %0,%1,%2"
1683 [(set_attr "type" "imul3")])
1685 (define_insn "*mullhwu"
1686 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1687 (mult:SI (zero_extend:SI
1688 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1689 (zero_extend:SI
1690 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1691 "TARGET_MULHW"
1692 "mullhwu %0,%1,%2"
1693 [(set_attr "type" "imul3")])
1694 \f
1695 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1696 (define_insn "dlmzb"
1697 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1698 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1699 (match_operand:SI 2 "gpc_reg_operand" "r")]
1700 UNSPEC_DLMZB_CR))
1701 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1702 (unspec:SI [(match_dup 1)
1703 (match_dup 2)]
1704 UNSPEC_DLMZB))]
1705 "TARGET_DLMZB"
1706 "dlmzb. %0,%1,%2")
1708 (define_expand "strlensi"
1709 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1710 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1711 (match_operand:QI 2 "const_int_operand" "")
1712 (match_operand 3 "const_int_operand" "")]
1713 UNSPEC_DLMZB_STRLEN))
1714 (clobber (match_scratch:CC 4 "=x"))]
1715 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1716 {
1717 rtx result = operands[0];
1718 rtx src = operands[1];
1719 rtx search_char = operands[2];
1720 rtx align = operands[3];
1721 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1722 rtx loop_label, end_label, mem, cr0, cond;
1723 if (search_char != const0_rtx
1724 || GET_CODE (align) != CONST_INT
1725 || INTVAL (align) < 8)
1726 FAIL;
1727 word1 = gen_reg_rtx (SImode);
1728 word2 = gen_reg_rtx (SImode);
1729 scratch_dlmzb = gen_reg_rtx (SImode);
1730 scratch_string = gen_reg_rtx (Pmode);
1731 loop_label = gen_label_rtx ();
1732 end_label = gen_label_rtx ();
1733 addr = force_reg (Pmode, XEXP (src, 0));
1734 emit_move_insn (scratch_string, addr);
1735 emit_label (loop_label);
1736 mem = change_address (src, SImode, scratch_string);
1737 emit_move_insn (word1, mem);
1738 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1739 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1740 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1741 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1742 emit_jump_insn (gen_rtx_SET (VOIDmode,
1743 pc_rtx,
1744 gen_rtx_IF_THEN_ELSE (VOIDmode,
1745 cond,
1746 gen_rtx_LABEL_REF
1747 (VOIDmode,
1748 end_label),
1749 pc_rtx)));
1750 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1751 emit_jump_insn (gen_rtx_SET (VOIDmode,
1752 pc_rtx,
1753 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1754 emit_barrier ();
1755 emit_label (end_label);
1756 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1757 emit_insn (gen_subsi3 (result, scratch_string, addr));
1758 emit_insn (gen_subsi3 (result, result, const1_rtx));
1759 DONE;
1760 })
1761 \f
1762 ;; Fixed-point arithmetic insns.
1764 (define_expand "add<mode>3"
1765 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1766 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1767 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1768 ""
1769 {
1770 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1771 {
1772 if (non_short_cint_operand (operands[2], DImode))
1773 FAIL;
1774 }
1775 else if (GET_CODE (operands[2]) == CONST_INT
1776 && ! add_operand (operands[2], <MODE>mode))
1777 {
1778 rtx tmp = ((!can_create_pseudo_p ()
1779 || rtx_equal_p (operands[0], operands[1]))
1780 ? operands[0] : gen_reg_rtx (<MODE>mode));
1782 HOST_WIDE_INT val = INTVAL (operands[2]);
1783 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1784 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1786 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1787 FAIL;
1789 /* The ordering here is important for the prolog expander.
1790 When space is allocated from the stack, adding 'low' first may
1791 produce a temporary deallocation (which would be bad). */
1792 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1793 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1794 DONE;
1795 }
1796 })
1798 ;; Discourage ai/addic because of carry but provide it in an alternative
1799 ;; allowing register zero as source.
1800 (define_insn "*add<mode>3_internal1"
1801 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1802 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1803 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1804 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1805 "@
1806 add %0,%1,%2
1807 addi %0,%1,%2
1808 addic %0,%1,%2
1809 addis %0,%1,%v2"
1810 [(set_attr "length" "4,4,4,4")])
1812 (define_insn "addsi3_high"
1813 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1814 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1815 (high:SI (match_operand 2 "" ""))))]
1816 "TARGET_MACHO && !TARGET_64BIT"
1817 "addis %0,%1,ha16(%2)"
1818 [(set_attr "length" "4")])
1820 (define_insn "*add<mode>3_internal2"
1821 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1822 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1823 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1824 (const_int 0)))
1825 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1826 ""
1827 "@
1828 add. %3,%1,%2
1829 addic. %3,%1,%2
1830 #
1831 #"
1832 [(set_attr "type" "fast_compare,compare,compare,compare")
1833 (set_attr "length" "4,4,8,8")])
1835 (define_split
1836 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1837 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1838 (match_operand:GPR 2 "reg_or_short_operand" ""))
1839 (const_int 0)))
1840 (clobber (match_scratch:GPR 3 ""))]
1841 "reload_completed"
1842 [(set (match_dup 3)
1843 (plus:GPR (match_dup 1)
1844 (match_dup 2)))
1845 (set (match_dup 0)
1846 (compare:CC (match_dup 3)
1847 (const_int 0)))]
1848 "")
1850 (define_insn "*add<mode>3_internal3"
1851 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1852 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1853 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1854 (const_int 0)))
1855 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1856 (plus:P (match_dup 1)
1857 (match_dup 2)))]
1858 ""
1859 "@
1860 add. %0,%1,%2
1861 addic. %0,%1,%2
1862 #
1863 #"
1864 [(set_attr "type" "fast_compare,compare,compare,compare")
1865 (set_attr "length" "4,4,8,8")])
1867 (define_split
1868 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1869 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1870 (match_operand:P 2 "reg_or_short_operand" ""))
1871 (const_int 0)))
1872 (set (match_operand:P 0 "gpc_reg_operand" "")
1873 (plus:P (match_dup 1) (match_dup 2)))]
1874 "reload_completed"
1875 [(set (match_dup 0)
1876 (plus:P (match_dup 1)
1877 (match_dup 2)))
1878 (set (match_dup 3)
1879 (compare:CC (match_dup 0)
1880 (const_int 0)))]
1881 "")
1883 ;; Split an add that we can't do in one insn into two insns, each of which
1884 ;; does one 16-bit part. This is used by combine. Note that the low-order
1885 ;; add should be last in case the result gets used in an address.
1887 (define_split
1888 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1889 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1890 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1891 ""
1892 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1893 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1894 {
1895 HOST_WIDE_INT val = INTVAL (operands[2]);
1896 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1897 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1899 operands[4] = GEN_INT (low);
1900 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1901 operands[3] = GEN_INT (rest);
1902 else if (can_create_pseudo_p ())
1903 {
1904 operands[3] = gen_reg_rtx (DImode);
1905 emit_move_insn (operands[3], operands[2]);
1906 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1907 DONE;
1908 }
1909 else
1910 FAIL;
1911 })
1913 (define_expand "one_cmpl<mode>2"
1914 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1915 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1916 ""
1917 {
1918 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1919 {
1920 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
1921 DONE;
1922 }
1923 })
1925 (define_insn "*one_cmpl<mode>2"
1926 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1927 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1928 ""
1929 "nor %0,%1,%1")
1931 (define_insn ""
1932 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1933 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1934 (const_int 0)))
1935 (clobber (match_scratch:P 2 "=r,r"))]
1936 ""
1937 "@
1938 nor. %2,%1,%1
1939 #"
1940 [(set_attr "type" "fast_compare,compare")
1941 (set_attr "length" "4,8")])
1943 (define_split
1944 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1945 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1946 (const_int 0)))
1947 (clobber (match_scratch:P 2 ""))]
1948 "reload_completed"
1949 [(set (match_dup 2)
1950 (not:P (match_dup 1)))
1951 (set (match_dup 0)
1952 (compare:CC (match_dup 2)
1953 (const_int 0)))]
1954 "")
1956 (define_insn ""
1957 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1958 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1959 (const_int 0)))
1960 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1961 (not:P (match_dup 1)))]
1962 ""
1963 "@
1964 nor. %0,%1,%1
1965 #"
1966 [(set_attr "type" "fast_compare,compare")
1967 (set_attr "length" "4,8")])
1969 (define_split
1970 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1971 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1972 (const_int 0)))
1973 (set (match_operand:P 0 "gpc_reg_operand" "")
1974 (not:P (match_dup 1)))]
1975 "reload_completed"
1976 [(set (match_dup 0)
1977 (not:P (match_dup 1)))
1978 (set (match_dup 2)
1979 (compare:CC (match_dup 0)
1980 (const_int 0)))]
1981 "")
1983 (define_insn ""
1984 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1985 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1986 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1987 ""
1988 "@
1989 subf %0,%2,%1
1990 subfic %0,%2,%1")
1992 (define_insn ""
1993 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1994 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1995 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1996 (const_int 0)))
1997 (clobber (match_scratch:P 3 "=r,r"))]
1998 ""
1999 "@
2000 subf. %3,%2,%1
2001 #"
2002 [(set_attr "type" "fast_compare")
2003 (set_attr "length" "4,8")])
2005 (define_split
2006 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2007 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2008 (match_operand:P 2 "gpc_reg_operand" ""))
2009 (const_int 0)))
2010 (clobber (match_scratch:P 3 ""))]
2011 "reload_completed"
2012 [(set (match_dup 3)
2013 (minus:P (match_dup 1)
2014 (match_dup 2)))
2015 (set (match_dup 0)
2016 (compare:CC (match_dup 3)
2017 (const_int 0)))]
2018 "")
2020 (define_insn ""
2021 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2022 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2023 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2024 (const_int 0)))
2025 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2026 (minus:P (match_dup 1)
2027 (match_dup 2)))]
2028 ""
2029 "@
2030 subf. %0,%2,%1
2031 #"
2032 [(set_attr "type" "fast_compare")
2033 (set_attr "length" "4,8")])
2035 (define_split
2036 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2037 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2038 (match_operand:P 2 "gpc_reg_operand" ""))
2039 (const_int 0)))
2040 (set (match_operand:P 0 "gpc_reg_operand" "")
2041 (minus:P (match_dup 1)
2042 (match_dup 2)))]
2043 "reload_completed"
2044 [(set (match_dup 0)
2045 (minus:P (match_dup 1)
2046 (match_dup 2)))
2047 (set (match_dup 3)
2048 (compare:CC (match_dup 0)
2049 (const_int 0)))]
2050 "")
2052 (define_expand "sub<mode>3"
2053 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2054 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
2055 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
2056 ""
2057 "
2058 {
2059 if (GET_CODE (operands[2]) == CONST_INT)
2060 {
2061 emit_insn (gen_add<mode>3 (operands[0], operands[1],
2062 negate_rtx (<MODE>mode, operands[2])));
2063 DONE;
2064 }
2065 }")
2067 (define_expand "neg<mode>2"
2068 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2069 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2070 ""
2071 "")
2073 (define_insn "*neg<mode>2_internal"
2074 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2075 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2076 ""
2077 "neg %0,%1")
2079 (define_insn ""
2080 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2081 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2082 (const_int 0)))
2083 (clobber (match_scratch:P 2 "=r,r"))]
2084 ""
2085 "@
2086 neg. %2,%1
2087 #"
2088 [(set_attr "type" "fast_compare")
2089 (set_attr "length" "4,8")])
2091 (define_split
2092 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2093 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2094 (const_int 0)))
2095 (clobber (match_scratch:P 2 ""))]
2096 "reload_completed"
2097 [(set (match_dup 2)
2098 (neg:P (match_dup 1)))
2099 (set (match_dup 0)
2100 (compare:CC (match_dup 2)
2101 (const_int 0)))]
2102 "")
2104 (define_insn ""
2105 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2106 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2107 (const_int 0)))
2108 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2109 (neg:P (match_dup 1)))]
2110 ""
2111 "@
2112 neg. %0,%1
2113 #"
2114 [(set_attr "type" "fast_compare")
2115 (set_attr "length" "4,8")])
2117 (define_split
2118 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2119 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2120 (const_int 0)))
2121 (set (match_operand:P 0 "gpc_reg_operand" "")
2122 (neg:P (match_dup 1)))]
2123 "reload_completed"
2124 [(set (match_dup 0)
2125 (neg:P (match_dup 1)))
2126 (set (match_dup 2)
2127 (compare:CC (match_dup 0)
2128 (const_int 0)))]
2129 "")
2131 (define_insn "clz<mode>2"
2132 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2133 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2134 ""
2135 "cntlz<wd> %0,%1"
2136 [(set_attr "type" "cntlz")])
2138 (define_expand "ctz<mode>2"
2139 [(set (match_dup 2)
2140 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2141 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2142 (match_dup 2)))
2143 (clobber (scratch:CC))])
2144 (set (match_dup 4) (clz:GPR (match_dup 3)))
2145 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2146 (minus:GPR (match_dup 5) (match_dup 4)))]
2147 ""
2148 {
2149 operands[2] = gen_reg_rtx (<MODE>mode);
2150 operands[3] = gen_reg_rtx (<MODE>mode);
2151 operands[4] = gen_reg_rtx (<MODE>mode);
2152 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2153 })
2155 (define_expand "ffs<mode>2"
2156 [(set (match_dup 2)
2157 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2158 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2159 (match_dup 2)))
2160 (clobber (scratch:CC))])
2161 (set (match_dup 4) (clz:GPR (match_dup 3)))
2162 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2163 (minus:GPR (match_dup 5) (match_dup 4)))]
2164 ""
2165 {
2166 operands[2] = gen_reg_rtx (<MODE>mode);
2167 operands[3] = gen_reg_rtx (<MODE>mode);
2168 operands[4] = gen_reg_rtx (<MODE>mode);
2169 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2170 })
2172 (define_insn "popcntb<mode>2"
2173 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2174 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2175 UNSPEC_POPCNTB))]
2176 "TARGET_POPCNTB"
2177 "popcntb %0,%1"
2178 [(set_attr "length" "4")
2179 (set_attr "type" "popcnt")])
2181 (define_insn "popcntd<mode>2"
2182 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2183 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2184 "TARGET_POPCNTD"
2185 "popcnt<wd> %0,%1"
2186 [(set_attr "length" "4")
2187 (set_attr "type" "popcnt")])
2189 (define_expand "popcount<mode>2"
2190 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2191 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2192 "TARGET_POPCNTB || TARGET_POPCNTD"
2193 {
2194 rs6000_emit_popcount (operands[0], operands[1]);
2195 DONE;
2196 })
2198 (define_insn "parity<mode>2_cmpb"
2199 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2200 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2201 "TARGET_CMPB && TARGET_POPCNTB"
2202 "prty<wd> %0,%1"
2203 [(set_attr "length" "4")
2204 (set_attr "type" "popcnt")])
2206 (define_expand "parity<mode>2"
2207 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2208 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2209 "TARGET_POPCNTB"
2210 {
2211 rs6000_emit_parity (operands[0], operands[1]);
2212 DONE;
2213 })
2215 ;; Since the hardware zeros the upper part of the register, save generating the
2216 ;; AND immediate if we are converting to unsigned
2217 (define_insn "*bswaphi2_extenddi"
2218 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2219 (zero_extend:DI
2220 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2221 "TARGET_POWERPC64"
2222 "lhbrx %0,%y1"
2223 [(set_attr "length" "4")
2224 (set_attr "type" "load")])
2226 (define_insn "*bswaphi2_extendsi"
2227 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2228 (zero_extend:SI
2229 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2230 ""
2231 "lhbrx %0,%y1"
2232 [(set_attr "length" "4")
2233 (set_attr "type" "load")])
2235 (define_expand "bswaphi2"
2236 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2237 (bswap:HI
2238 (match_operand:HI 1 "reg_or_mem_operand" "")))
2239 (clobber (match_scratch:SI 2 ""))])]
2240 ""
2241 {
2242 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2243 operands[1] = force_reg (HImode, operands[1]);
2244 })
2246 (define_insn "bswaphi2_internal"
2247 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2248 (bswap:HI
2249 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2250 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2251 ""
2252 "@
2253 lhbrx %0,%y1
2254 sthbrx %1,%y0
2255 #"
2256 [(set_attr "length" "4,4,12")
2257 (set_attr "type" "load,store,*")])
2259 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2260 ;; correct for -mlittle as well as -mbig.
2261 (define_split
2262 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2263 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2264 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2265 "reload_completed"
2266 [(set (match_dup 3)
2267 (zero_extract:SI (match_dup 4)
2268 (const_int 8)
2269 (const_int 16)))
2270 (set (match_dup 2)
2271 (and:SI (ashift:SI (match_dup 4)
2272 (const_int 8))
2273 (const_int 65280))) ;; 0xff00
2274 (set (match_dup 3)
2275 (ior:SI (match_dup 3)
2276 (match_dup 2)))]
2277 "
2278 {
2279 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2280 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2281 }")
2283 (define_insn "*bswapsi2_extenddi"
2284 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2285 (zero_extend:DI
2286 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2287 "TARGET_POWERPC64"
2288 "lwbrx %0,%y1"
2289 [(set_attr "length" "4")
2290 (set_attr "type" "load")])
2292 (define_expand "bswapsi2"
2293 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2294 (bswap:SI
2295 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2296 ""
2297 {
2298 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2299 operands[1] = force_reg (SImode, operands[1]);
2300 })
2302 (define_insn "*bswapsi2_internal"
2303 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2304 (bswap:SI
2305 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2306 ""
2307 "@
2308 lwbrx %0,%y1
2309 stwbrx %1,%y0
2310 #"
2311 [(set_attr "length" "4,4,12")
2312 (set_attr "type" "load,store,*")])
2314 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2315 ;; zero_extract insns do not change for -mlittle.
2316 (define_split
2317 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2318 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2319 "reload_completed"
2320 [(set (match_dup 0)
2321 (rotate:SI (match_dup 1) (const_int 8)))
2322 (set (zero_extract:SI (match_dup 0)
2323 (const_int 8)
2324 (const_int 0))
2325 (match_dup 1))
2326 (set (zero_extract:SI (match_dup 0)
2327 (const_int 8)
2328 (const_int 16))
2329 (rotate:SI (match_dup 1)
2330 (const_int 16)))]
2331 "")
2333 (define_expand "bswapdi2"
2334 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2335 (bswap:DI
2336 (match_operand:DI 1 "reg_or_mem_operand" "")))
2337 (clobber (match_scratch:DI 2 ""))
2338 (clobber (match_scratch:DI 3 ""))
2339 (clobber (match_scratch:DI 4 ""))])]
2340 ""
2341 {
2342 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2343 operands[1] = force_reg (DImode, operands[1]);
2345 if (!TARGET_POWERPC64)
2346 {
2347 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2348 that uses 64-bit registers needs the same scratch registers as 64-bit
2349 mode. */
2350 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2351 DONE;
2352 }
2353 })
2355 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2356 (define_insn "*bswapdi2_ldbrx"
2357 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2358 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2359 (clobber (match_scratch:DI 2 "=X,X,&r"))
2360 (clobber (match_scratch:DI 3 "=X,X,&r"))
2361 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2362 "TARGET_POWERPC64 && TARGET_LDBRX
2363 && (REG_P (operands[0]) || REG_P (operands[1]))"
2364 "@
2365 ldbrx %0,%y1
2366 stdbrx %1,%y0
2367 #"
2368 [(set_attr "length" "4,4,36")
2369 (set_attr "type" "load,store,*")])
2371 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2372 (define_insn "*bswapdi2_64bit"
2373 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2374 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2375 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2376 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2377 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2378 "TARGET_POWERPC64 && !TARGET_LDBRX
2379 && (REG_P (operands[0]) || REG_P (operands[1]))
2380 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2381 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2382 "#"
2383 [(set_attr "length" "16,12,36")])
2385 (define_split
2386 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2387 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2388 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2389 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2390 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2391 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2392 [(const_int 0)]
2393 "
2394 {
2395 rtx dest = operands[0];
2396 rtx src = operands[1];
2397 rtx op2 = operands[2];
2398 rtx op3 = operands[3];
2399 rtx op4 = operands[4];
2400 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2401 BYTES_BIG_ENDIAN ? 4 : 0);
2402 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2403 BYTES_BIG_ENDIAN ? 4 : 0);
2404 rtx addr1;
2405 rtx addr2;
2406 rtx word_high;
2407 rtx word_low;
2409 addr1 = XEXP (src, 0);
2410 if (GET_CODE (addr1) == PLUS)
2411 {
2412 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2413 if (TARGET_AVOID_XFORM)
2414 {
2415 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2416 addr2 = op2;
2417 }
2418 else
2419 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2420 }
2421 else if (TARGET_AVOID_XFORM)
2422 {
2423 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2424 addr2 = op2;
2425 }
2426 else
2427 {
2428 emit_move_insn (op2, GEN_INT (4));
2429 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2430 }
2432 if (BYTES_BIG_ENDIAN)
2433 {
2434 word_high = change_address (src, SImode, addr1);
2435 word_low = change_address (src, SImode, addr2);
2436 }
2437 else
2438 {
2439 word_high = change_address (src, SImode, addr2);
2440 word_low = change_address (src, SImode, addr1);
2441 }
2443 emit_insn (gen_bswapsi2 (op3_32, word_low));
2444 emit_insn (gen_bswapsi2 (op4_32, word_high));
2445 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2446 emit_insn (gen_iordi3 (dest, dest, op4));
2447 }")
2449 (define_split
2450 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2451 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2452 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2453 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2454 (clobber (match_operand:DI 4 "" ""))]
2455 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2456 [(const_int 0)]
2457 "
2458 {
2459 rtx dest = operands[0];
2460 rtx src = operands[1];
2461 rtx op2 = operands[2];
2462 rtx op3 = operands[3];
2463 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2464 BYTES_BIG_ENDIAN ? 4 : 0);
2465 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2466 BYTES_BIG_ENDIAN ? 4 : 0);
2467 rtx addr1;
2468 rtx addr2;
2469 rtx word_high;
2470 rtx word_low;
2472 addr1 = XEXP (dest, 0);
2473 if (GET_CODE (addr1) == PLUS)
2474 {
2475 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2476 if (TARGET_AVOID_XFORM)
2477 {
2478 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2479 addr2 = op2;
2480 }
2481 else
2482 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2483 }
2484 else if (TARGET_AVOID_XFORM)
2485 {
2486 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2487 addr2 = op2;
2488 }
2489 else
2490 {
2491 emit_move_insn (op2, GEN_INT (4));
2492 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2493 }
2495 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2496 if (BYTES_BIG_ENDIAN)
2497 {
2498 word_high = change_address (dest, SImode, addr1);
2499 word_low = change_address (dest, SImode, addr2);
2500 }
2501 else
2502 {
2503 word_high = change_address (dest, SImode, addr2);
2504 word_low = change_address (dest, SImode, addr1);
2505 }
2506 emit_insn (gen_bswapsi2 (word_high, src_si));
2507 emit_insn (gen_bswapsi2 (word_low, op3_si));
2508 }")
2510 (define_split
2511 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2512 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2513 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2514 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2515 (clobber (match_operand:DI 4 "" ""))]
2516 "TARGET_POWERPC64 && reload_completed"
2517 [(const_int 0)]
2518 "
2519 {
2520 rtx dest = operands[0];
2521 rtx src = operands[1];
2522 rtx op2 = operands[2];
2523 rtx op3 = operands[3];
2524 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2525 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2526 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2527 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2528 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2530 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2531 emit_insn (gen_bswapsi2 (dest_si, src_si));
2532 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2533 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2534 emit_insn (gen_iordi3 (dest, dest, op3));
2535 }")
2537 (define_insn "bswapdi2_32bit"
2538 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2539 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2540 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2541 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2542 "#"
2543 [(set_attr "length" "16,12,36")])
2545 (define_split
2546 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2547 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2548 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2549 "!TARGET_POWERPC64 && reload_completed"
2550 [(const_int 0)]
2551 "
2552 {
2553 rtx dest = operands[0];
2554 rtx src = operands[1];
2555 rtx op2 = operands[2];
2556 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2557 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2558 rtx addr1;
2559 rtx addr2;
2560 rtx word1;
2561 rtx word2;
2563 addr1 = XEXP (src, 0);
2564 if (GET_CODE (addr1) == PLUS)
2565 {
2566 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2567 if (TARGET_AVOID_XFORM)
2568 {
2569 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2570 addr2 = op2;
2571 }
2572 else
2573 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2574 }
2575 else if (TARGET_AVOID_XFORM)
2576 {
2577 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2578 addr2 = op2;
2579 }
2580 else
2581 {
2582 emit_move_insn (op2, GEN_INT (4));
2583 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2584 }
2586 word1 = change_address (src, SImode, addr1);
2587 word2 = change_address (src, SImode, addr2);
2589 emit_insn (gen_bswapsi2 (dest2, word1));
2590 emit_insn (gen_bswapsi2 (dest1, word2));
2591 }")
2593 (define_split
2594 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2595 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2596 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2597 "!TARGET_POWERPC64 && reload_completed"
2598 [(const_int 0)]
2599 "
2600 {
2601 rtx dest = operands[0];
2602 rtx src = operands[1];
2603 rtx op2 = operands[2];
2604 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2605 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2606 rtx addr1;
2607 rtx addr2;
2608 rtx word1;
2609 rtx word2;
2611 addr1 = XEXP (dest, 0);
2612 if (GET_CODE (addr1) == PLUS)
2613 {
2614 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2615 if (TARGET_AVOID_XFORM)
2616 {
2617 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2618 addr2 = op2;
2619 }
2620 else
2621 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2622 }
2623 else if (TARGET_AVOID_XFORM)
2624 {
2625 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2626 addr2 = op2;
2627 }
2628 else
2629 {
2630 emit_move_insn (op2, GEN_INT (4));
2631 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2632 }
2634 word1 = change_address (dest, SImode, addr1);
2635 word2 = change_address (dest, SImode, addr2);
2637 emit_insn (gen_bswapsi2 (word2, src1));
2638 emit_insn (gen_bswapsi2 (word1, src2));
2639 }")
2641 (define_split
2642 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2643 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2644 (clobber (match_operand:SI 2 "" ""))]
2645 "!TARGET_POWERPC64 && reload_completed"
2646 [(const_int 0)]
2647 "
2648 {
2649 rtx dest = operands[0];
2650 rtx src = operands[1];
2651 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2652 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2653 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2654 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2656 emit_insn (gen_bswapsi2 (dest1, src2));
2657 emit_insn (gen_bswapsi2 (dest2, src1));
2658 }")
2660 (define_insn "mulsi3"
2661 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2662 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2663 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2664 ""
2665 "@
2666 mullw %0,%1,%2
2667 mulli %0,%1,%2"
2668 [(set (attr "type")
2669 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2670 (const_string "imul3")
2671 (match_operand:SI 2 "short_cint_operand" "")
2672 (const_string "imul2")]
2673 (const_string "imul")))])
2675 (define_insn "*mulsi3_internal1"
2676 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2677 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2678 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2679 (const_int 0)))
2680 (clobber (match_scratch:SI 3 "=r,r"))]
2681 ""
2682 "@
2683 mullw. %3,%1,%2
2684 #"
2685 [(set_attr "type" "imul_compare")
2686 (set_attr "length" "4,8")])
2688 (define_split
2689 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2690 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2691 (match_operand:SI 2 "gpc_reg_operand" ""))
2692 (const_int 0)))
2693 (clobber (match_scratch:SI 3 ""))]
2694 "reload_completed"
2695 [(set (match_dup 3)
2696 (mult:SI (match_dup 1) (match_dup 2)))
2697 (set (match_dup 0)
2698 (compare:CC (match_dup 3)
2699 (const_int 0)))]
2700 "")
2702 (define_insn "*mulsi3_internal2"
2703 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2704 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2705 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2706 (const_int 0)))
2707 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2708 (mult:SI (match_dup 1) (match_dup 2)))]
2709 ""
2710 "@
2711 mullw. %0,%1,%2
2712 #"
2713 [(set_attr "type" "imul_compare")
2714 (set_attr "length" "4,8")])
2716 (define_split
2717 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2718 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2719 (match_operand:SI 2 "gpc_reg_operand" ""))
2720 (const_int 0)))
2721 (set (match_operand:SI 0 "gpc_reg_operand" "")
2722 (mult:SI (match_dup 1) (match_dup 2)))]
2723 "reload_completed"
2724 [(set (match_dup 0)
2725 (mult:SI (match_dup 1) (match_dup 2)))
2726 (set (match_dup 3)
2727 (compare:CC (match_dup 0)
2728 (const_int 0)))]
2729 "")
2732 (define_insn "udiv<mode>3"
2733 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2734 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2735 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2736 ""
2737 "div<wd>u %0,%1,%2"
2738 [(set (attr "type")
2739 (cond [(match_operand:SI 0 "" "")
2740 (const_string "idiv")]
2741 (const_string "ldiv")))])
2744 ;; For powers of two we can do srai/aze for divide and then adjust for
2745 ;; modulus. If it isn't a power of two, force operands into register and do
2746 ;; a normal divide.
2747 (define_expand "div<mode>3"
2748 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2749 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2750 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2751 ""
2752 {
2753 if (GET_CODE (operands[2]) != CONST_INT
2754 || INTVAL (operands[2]) <= 0
2755 || exact_log2 (INTVAL (operands[2])) < 0)
2756 operands[2] = force_reg (<MODE>mode, operands[2]);
2757 })
2759 (define_insn "*div<mode>3"
2760 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2761 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2762 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2763 ""
2764 "div<wd> %0,%1,%2"
2765 [(set (attr "type")
2766 (cond [(match_operand:SI 0 "" "")
2767 (const_string "idiv")]
2768 (const_string "ldiv")))])
2770 (define_expand "mod<mode>3"
2771 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2772 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2773 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2774 ""
2775 "
2776 {
2777 int i;
2778 rtx temp1;
2779 rtx temp2;
2781 if (GET_CODE (operands[2]) != CONST_INT
2782 || INTVAL (operands[2]) <= 0
2783 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2784 FAIL;
2786 temp1 = gen_reg_rtx (<MODE>mode);
2787 temp2 = gen_reg_rtx (<MODE>mode);
2789 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2790 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2791 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2792 DONE;
2793 }")
2795 (define_insn ""
2796 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2797 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2798 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2799 ""
2800 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2801 [(set_attr "type" "two")
2802 (set_attr "length" "8")])
2804 (define_insn ""
2805 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2806 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2807 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2808 (const_int 0)))
2809 (clobber (match_scratch:P 3 "=r,r"))]
2810 ""
2811 "@
2812 sra<wd>i %3,%1,%p2\;addze. %3,%3
2813 #"
2814 [(set_attr "type" "compare")
2815 (set_attr "length" "8,12")
2816 (set_attr "cell_micro" "not")])
2818 (define_split
2819 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2820 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2821 (match_operand:GPR 2 "exact_log2_cint_operand"
2822 ""))
2823 (const_int 0)))
2824 (clobber (match_scratch:GPR 3 ""))]
2825 "reload_completed"
2826 [(set (match_dup 3)
2827 (div:<MODE> (match_dup 1) (match_dup 2)))
2828 (set (match_dup 0)
2829 (compare:CC (match_dup 3)
2830 (const_int 0)))]
2831 "")
2833 (define_insn ""
2834 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2835 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2836 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2837 (const_int 0)))
2838 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2839 (div:P (match_dup 1) (match_dup 2)))]
2840 ""
2841 "@
2842 sra<wd>i %0,%1,%p2\;addze. %0,%0
2843 #"
2844 [(set_attr "type" "compare")
2845 (set_attr "length" "8,12")
2846 (set_attr "cell_micro" "not")])
2848 (define_split
2849 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2850 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2851 (match_operand:GPR 2 "exact_log2_cint_operand"
2852 ""))
2853 (const_int 0)))
2854 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2855 (div:GPR (match_dup 1) (match_dup 2)))]
2856 "reload_completed"
2857 [(set (match_dup 0)
2858 (div:<MODE> (match_dup 1) (match_dup 2)))
2859 (set (match_dup 3)
2860 (compare:CC (match_dup 0)
2861 (const_int 0)))]
2862 "")
2863 \f
2864 ;; Logical instructions
2865 ;; The logical instructions are mostly combined by using match_operator,
2866 ;; but the plain AND insns are somewhat different because there is no
2867 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2868 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2870 (define_expand "andsi3"
2871 [(parallel
2872 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2873 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2874 (match_operand:SI 2 "and_operand" "")))
2875 (clobber (match_scratch:CC 3 ""))])]
2876 ""
2877 "")
2879 (define_insn "andsi3_mc"
2880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2881 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2882 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2883 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2884 "rs6000_gen_cell_microcode"
2885 "@
2886 and %0,%1,%2
2887 rlwinm %0,%1,0,%m2,%M2
2888 andi. %0,%1,%b2
2889 andis. %0,%1,%u2"
2890 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2892 (define_insn "andsi3_nomc"
2893 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2894 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2895 (match_operand:SI 2 "and_operand" "?r,T")))
2896 (clobber (match_scratch:CC 3 "=X,X"))]
2897 "!rs6000_gen_cell_microcode"
2898 "@
2899 and %0,%1,%2
2900 rlwinm %0,%1,0,%m2,%M2")
2902 (define_insn "andsi3_internal0_nomc"
2903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2904 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2905 (match_operand:SI 2 "and_operand" "?r,T")))]
2906 "!rs6000_gen_cell_microcode"
2907 "@
2908 and %0,%1,%2
2909 rlwinm %0,%1,0,%m2,%M2")
2912 ;; Note to set cr's other than cr0 we do the and immediate and then
2913 ;; the test again -- this avoids a mfcr which on the higher end
2914 ;; machines causes an execution serialization
2916 (define_insn "*andsi3_internal2_mc"
2917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2918 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2919 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2920 (const_int 0)))
2921 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2922 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2923 "TARGET_32BIT && rs6000_gen_cell_microcode"
2924 "@
2925 and. %3,%1,%2
2926 andi. %3,%1,%b2
2927 andis. %3,%1,%u2
2928 rlwinm. %3,%1,0,%m2,%M2
2929 #
2930 #
2931 #
2932 #"
2933 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2934 compare,compare,compare,compare")
2935 (set_attr "length" "4,4,4,4,8,8,8,8")])
2937 (define_insn "*andsi3_internal3_mc"
2938 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2939 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2940 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2941 (const_int 0)))
2942 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2943 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2944 "TARGET_64BIT && rs6000_gen_cell_microcode"
2945 "@
2946 #
2947 andi. %3,%1,%b2
2948 andis. %3,%1,%u2
2949 rlwinm. %3,%1,0,%m2,%M2
2950 #
2951 #
2952 #
2953 #"
2954 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2955 compare,compare,compare")
2956 (set_attr "length" "8,4,4,4,8,8,8,8")])
2958 (define_split
2959 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2960 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2961 (match_operand:GPR 2 "and_operand" ""))
2962 (const_int 0)))
2963 (clobber (match_scratch:GPR 3 ""))
2964 (clobber (match_scratch:CC 4 ""))]
2965 "reload_completed"
2966 [(parallel [(set (match_dup 3)
2967 (and:<MODE> (match_dup 1)
2968 (match_dup 2)))
2969 (clobber (match_dup 4))])
2970 (set (match_dup 0)
2971 (compare:CC (match_dup 3)
2972 (const_int 0)))]
2973 "")
2975 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2976 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2978 (define_split
2979 [(set (match_operand:CC 0 "cc_reg_operand" "")
2980 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2981 (match_operand:SI 2 "gpc_reg_operand" ""))
2982 (const_int 0)))
2983 (clobber (match_scratch:SI 3 ""))
2984 (clobber (match_scratch:CC 4 ""))]
2985 "TARGET_POWERPC64 && reload_completed"
2986 [(parallel [(set (match_dup 3)
2987 (and:SI (match_dup 1)
2988 (match_dup 2)))
2989 (clobber (match_dup 4))])
2990 (set (match_dup 0)
2991 (compare:CC (match_dup 3)
2992 (const_int 0)))]
2993 "")
2995 (define_insn "*andsi3_internal4"
2996 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2997 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2998 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2999 (const_int 0)))
3000 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3001 (and:SI (match_dup 1)
3002 (match_dup 2)))
3003 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3004 "TARGET_32BIT && rs6000_gen_cell_microcode"
3005 "@
3006 and. %0,%1,%2
3007 andi. %0,%1,%b2
3008 andis. %0,%1,%u2
3009 rlwinm. %0,%1,0,%m2,%M2
3010 #
3011 #
3012 #
3013 #"
3014 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3015 compare,compare,compare,compare")
3016 (set_attr "length" "4,4,4,4,8,8,8,8")])
3018 (define_insn "*andsi3_internal5_mc"
3019 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3020 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3021 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3022 (const_int 0)))
3023 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3024 (and:SI (match_dup 1)
3025 (match_dup 2)))
3026 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3027 "TARGET_64BIT && rs6000_gen_cell_microcode"
3028 "@
3029 #
3030 andi. %0,%1,%b2
3031 andis. %0,%1,%u2
3032 rlwinm. %0,%1,0,%m2,%M2
3033 #
3034 #
3035 #
3036 #"
3037 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3038 compare,compare,compare")
3039 (set_attr "length" "8,4,4,4,8,8,8,8")])
3041 (define_split
3042 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3043 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3044 (match_operand:SI 2 "and_operand" ""))
3045 (const_int 0)))
3046 (set (match_operand:SI 0 "gpc_reg_operand" "")
3047 (and:SI (match_dup 1)
3048 (match_dup 2)))
3049 (clobber (match_scratch:CC 4 ""))]
3050 "reload_completed"
3051 [(parallel [(set (match_dup 0)
3052 (and:SI (match_dup 1)
3053 (match_dup 2)))
3054 (clobber (match_dup 4))])
3055 (set (match_dup 3)
3056 (compare:CC (match_dup 0)
3057 (const_int 0)))]
3058 "")
3060 (define_split
3061 [(set (match_operand:CC 3 "cc_reg_operand" "")
3062 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3063 (match_operand:SI 2 "gpc_reg_operand" ""))
3064 (const_int 0)))
3065 (set (match_operand:SI 0 "gpc_reg_operand" "")
3066 (and:SI (match_dup 1)
3067 (match_dup 2)))
3068 (clobber (match_scratch:CC 4 ""))]
3069 "TARGET_POWERPC64 && reload_completed"
3070 [(parallel [(set (match_dup 0)
3071 (and:SI (match_dup 1)
3072 (match_dup 2)))
3073 (clobber (match_dup 4))])
3074 (set (match_dup 3)
3075 (compare:CC (match_dup 0)
3076 (const_int 0)))]
3077 "")
3079 ;; Handle the PowerPC64 rlwinm corner case
3081 (define_insn_and_split "*andsi3_internal6"
3082 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3083 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3084 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3085 "TARGET_POWERPC64"
3086 "#"
3087 "TARGET_POWERPC64"
3088 [(set (match_dup 0)
3089 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3090 (match_dup 4)))
3091 (set (match_dup 0)
3092 (rotate:SI (match_dup 0) (match_dup 5)))]
3093 "
3094 {
3095 int mb = extract_MB (operands[2]);
3096 int me = extract_ME (operands[2]);
3097 operands[3] = GEN_INT (me + 1);
3098 operands[5] = GEN_INT (32 - (me + 1));
3099 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3100 }"
3101 [(set_attr "length" "8")])
3103 (define_expand "iorsi3"
3104 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3105 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3106 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3107 ""
3108 "
3109 {
3110 if (GET_CODE (operands[2]) == CONST_INT
3111 && ! logical_operand (operands[2], SImode))
3112 {
3113 HOST_WIDE_INT value = INTVAL (operands[2]);
3114 rtx tmp = ((!can_create_pseudo_p ()
3115 || rtx_equal_p (operands[0], operands[1]))
3116 ? operands[0] : gen_reg_rtx (SImode));
3118 emit_insn (gen_iorsi3 (tmp, operands[1],
3119 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3120 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3121 DONE;
3122 }
3123 }")
3125 (define_expand "xorsi3"
3126 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3127 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3128 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3129 ""
3130 "
3131 {
3132 if (GET_CODE (operands[2]) == CONST_INT
3133 && ! logical_operand (operands[2], SImode))
3134 {
3135 HOST_WIDE_INT value = INTVAL (operands[2]);
3136 rtx tmp = ((!can_create_pseudo_p ()
3137 || rtx_equal_p (operands[0], operands[1]))
3138 ? operands[0] : gen_reg_rtx (SImode));
3140 emit_insn (gen_xorsi3 (tmp, operands[1],
3141 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3142 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3143 DONE;
3144 }
3145 }")
3147 (define_insn "*boolsi3_internal1"
3148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3149 (match_operator:SI 3 "boolean_or_operator"
3150 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3151 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3152 ""
3153 "@
3154 %q3 %0,%1,%2
3155 %q3i %0,%1,%b2
3156 %q3is %0,%1,%u2")
3158 (define_insn "*boolsi3_internal2"
3159 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3160 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3161 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3162 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3163 (const_int 0)))
3164 (clobber (match_scratch:SI 3 "=r,r"))]
3165 "TARGET_32BIT"
3166 "@
3167 %q4. %3,%1,%2
3168 #"
3169 [(set_attr "type" "fast_compare,compare")
3170 (set_attr "length" "4,8")])
3172 (define_split
3173 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3174 (compare:CC (match_operator:SI 4 "boolean_operator"
3175 [(match_operand:SI 1 "gpc_reg_operand" "")
3176 (match_operand:SI 2 "gpc_reg_operand" "")])
3177 (const_int 0)))
3178 (clobber (match_scratch:SI 3 ""))]
3179 "TARGET_32BIT && reload_completed"
3180 [(set (match_dup 3) (match_dup 4))
3181 (set (match_dup 0)
3182 (compare:CC (match_dup 3)
3183 (const_int 0)))]
3184 "")
3186 (define_insn "*boolsi3_internal3"
3187 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3188 (compare:CC (match_operator:SI 4 "boolean_operator"
3189 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3190 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3191 (const_int 0)))
3192 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3193 (match_dup 4))]
3194 "TARGET_32BIT"
3195 "@
3196 %q4. %0,%1,%2
3197 #"
3198 [(set_attr "type" "fast_compare,compare")
3199 (set_attr "length" "4,8")])
3201 (define_split
3202 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3203 (compare:CC (match_operator:SI 4 "boolean_operator"
3204 [(match_operand:SI 1 "gpc_reg_operand" "")
3205 (match_operand:SI 2 "gpc_reg_operand" "")])
3206 (const_int 0)))
3207 (set (match_operand:SI 0 "gpc_reg_operand" "")
3208 (match_dup 4))]
3209 "TARGET_32BIT && reload_completed"
3210 [(set (match_dup 0) (match_dup 4))
3211 (set (match_dup 3)
3212 (compare:CC (match_dup 0)
3213 (const_int 0)))]
3214 "")
3216 ;; Split a logical operation that we can't do in one insn into two insns,
3217 ;; each of which does one 16-bit part. This is used by combine.
3219 (define_split
3220 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3221 (match_operator:SI 3 "boolean_or_operator"
3222 [(match_operand:SI 1 "gpc_reg_operand" "")
3223 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3224 ""
3225 [(set (match_dup 0) (match_dup 4))
3226 (set (match_dup 0) (match_dup 5))]
3227 "
3228 {
3229 rtx i;
3230 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3231 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3232 operands[1], i);
3233 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3234 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3235 operands[0], i);
3236 }")
3238 (define_insn "*boolcsi3_internal1"
3239 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3240 (match_operator:SI 3 "boolean_operator"
3241 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3242 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3243 ""
3244 "%q3 %0,%2,%1")
3246 (define_insn "*boolcsi3_internal2"
3247 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3248 (compare:CC (match_operator:SI 4 "boolean_operator"
3249 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3250 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3251 (const_int 0)))
3252 (clobber (match_scratch:SI 3 "=r,r"))]
3253 "TARGET_32BIT"
3254 "@
3255 %q4. %3,%2,%1
3256 #"
3257 [(set_attr "type" "compare")
3258 (set_attr "length" "4,8")])
3260 (define_split
3261 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3262 (compare:CC (match_operator:SI 4 "boolean_operator"
3263 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3264 (match_operand:SI 2 "gpc_reg_operand" "")])
3265 (const_int 0)))
3266 (clobber (match_scratch:SI 3 ""))]
3267 "TARGET_32BIT && reload_completed"
3268 [(set (match_dup 3) (match_dup 4))
3269 (set (match_dup 0)
3270 (compare:CC (match_dup 3)
3271 (const_int 0)))]
3272 "")
3274 (define_insn "*boolcsi3_internal3"
3275 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3276 (compare:CC (match_operator:SI 4 "boolean_operator"
3277 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3278 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3279 (const_int 0)))
3280 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3281 (match_dup 4))]
3282 "TARGET_32BIT"
3283 "@
3284 %q4. %0,%2,%1
3285 #"
3286 [(set_attr "type" "compare")
3287 (set_attr "length" "4,8")])
3289 (define_split
3290 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3291 (compare:CC (match_operator:SI 4 "boolean_operator"
3292 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3293 (match_operand:SI 2 "gpc_reg_operand" "")])
3294 (const_int 0)))
3295 (set (match_operand:SI 0 "gpc_reg_operand" "")
3296 (match_dup 4))]
3297 "TARGET_32BIT && reload_completed"
3298 [(set (match_dup 0) (match_dup 4))
3299 (set (match_dup 3)
3300 (compare:CC (match_dup 0)
3301 (const_int 0)))]
3302 "")
3304 (define_insn "*boolccsi3_internal1"
3305 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3306 (match_operator:SI 3 "boolean_operator"
3307 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3308 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3309 ""
3310 "%q3 %0,%1,%2")
3312 (define_insn "*boolccsi3_internal2"
3313 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3314 (compare:CC (match_operator:SI 4 "boolean_operator"
3315 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3316 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3317 (const_int 0)))
3318 (clobber (match_scratch:SI 3 "=r,r"))]
3319 "TARGET_32BIT"
3320 "@
3321 %q4. %3,%1,%2
3322 #"
3323 [(set_attr "type" "fast_compare,compare")
3324 (set_attr "length" "4,8")])
3326 (define_split
3327 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3328 (compare:CC (match_operator:SI 4 "boolean_operator"
3329 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3330 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3331 (const_int 0)))
3332 (clobber (match_scratch:SI 3 ""))]
3333 "TARGET_32BIT && reload_completed"
3334 [(set (match_dup 3) (match_dup 4))
3335 (set (match_dup 0)
3336 (compare:CC (match_dup 3)
3337 (const_int 0)))]
3338 "")
3340 (define_insn "*boolccsi3_internal3"
3341 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3342 (compare:CC (match_operator:SI 4 "boolean_operator"
3343 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3344 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3345 (const_int 0)))
3346 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3347 (match_dup 4))]
3348 "TARGET_32BIT"
3349 "@
3350 %q4. %0,%1,%2
3351 #"
3352 [(set_attr "type" "fast_compare,compare")
3353 (set_attr "length" "4,8")])
3355 (define_split
3356 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3357 (compare:CC (match_operator:SI 4 "boolean_operator"
3358 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3359 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3360 (const_int 0)))
3361 (set (match_operand:SI 0 "gpc_reg_operand" "")
3362 (match_dup 4))]
3363 "TARGET_32BIT && reload_completed"
3364 [(set (match_dup 0) (match_dup 4))
3365 (set (match_dup 3)
3366 (compare:CC (match_dup 0)
3367 (const_int 0)))]
3368 "")
3369 \f
3370 ;; Rotate and shift insns, in all their variants. These support shifts,
3371 ;; field inserts and extracts, and various combinations thereof.
3372 (define_expand "insv"
3373 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3374 (match_operand:SI 1 "const_int_operand" "")
3375 (match_operand:SI 2 "const_int_operand" ""))
3376 (match_operand 3 "gpc_reg_operand" ""))]
3377 ""
3378 "
3379 {
3380 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3381 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3382 compiler if the address of the structure is taken later. Likewise, do
3383 not handle invalid E500 subregs. */
3384 if (GET_CODE (operands[0]) == SUBREG
3385 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3386 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3387 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3388 FAIL;
3390 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3391 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3392 operands[3]));
3393 else
3394 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3395 operands[3]));
3396 DONE;
3397 }")
3399 (define_insn "insvsi_internal"
3400 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3401 (match_operand:SI 1 "const_int_operand" "i")
3402 (match_operand:SI 2 "const_int_operand" "i"))
3403 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3404 ""
3405 "*
3406 {
3407 int start = INTVAL (operands[2]) & 31;
3408 int size = INTVAL (operands[1]) & 31;
3410 operands[4] = GEN_INT (32 - start - size);
3411 operands[1] = GEN_INT (start + size - 1);
3412 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3413 }"
3414 [(set_attr "type" "insert_word")])
3416 (define_insn "*insvsi_internal1"
3417 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3418 (match_operand:SI 1 "const_int_operand" "i")
3419 (match_operand:SI 2 "const_int_operand" "i"))
3420 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3421 (match_operand:SI 4 "const_int_operand" "i")))]
3422 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3423 "*
3424 {
3425 int shift = INTVAL (operands[4]) & 31;
3426 int start = INTVAL (operands[2]) & 31;
3427 int size = INTVAL (operands[1]) & 31;
3429 operands[4] = GEN_INT (shift - start - size);
3430 operands[1] = GEN_INT (start + size - 1);
3431 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3432 }"
3433 [(set_attr "type" "insert_word")])
3435 (define_insn "*insvsi_internal2"
3436 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3437 (match_operand:SI 1 "const_int_operand" "i")
3438 (match_operand:SI 2 "const_int_operand" "i"))
3439 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3440 (match_operand:SI 4 "const_int_operand" "i")))]
3441 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3442 "*
3443 {
3444 int shift = INTVAL (operands[4]) & 31;
3445 int start = INTVAL (operands[2]) & 31;
3446 int size = INTVAL (operands[1]) & 31;
3448 operands[4] = GEN_INT (32 - shift - start - size);
3449 operands[1] = GEN_INT (start + size - 1);
3450 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3451 }"
3452 [(set_attr "type" "insert_word")])
3454 (define_insn "*insvsi_internal3"
3455 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3456 (match_operand:SI 1 "const_int_operand" "i")
3457 (match_operand:SI 2 "const_int_operand" "i"))
3458 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3459 (match_operand:SI 4 "const_int_operand" "i")))]
3460 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3461 "*
3462 {
3463 int shift = INTVAL (operands[4]) & 31;
3464 int start = INTVAL (operands[2]) & 31;
3465 int size = INTVAL (operands[1]) & 31;
3467 operands[4] = GEN_INT (32 - shift - start - size);
3468 operands[1] = GEN_INT (start + size - 1);
3469 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3470 }"
3471 [(set_attr "type" "insert_word")])
3473 (define_insn "*insvsi_internal4"
3474 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3475 (match_operand:SI 1 "const_int_operand" "i")
3476 (match_operand:SI 2 "const_int_operand" "i"))
3477 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3478 (match_operand:SI 4 "const_int_operand" "i")
3479 (match_operand:SI 5 "const_int_operand" "i")))]
3480 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3481 "*
3482 {
3483 int extract_start = INTVAL (operands[5]) & 31;
3484 int extract_size = INTVAL (operands[4]) & 31;
3485 int insert_start = INTVAL (operands[2]) & 31;
3486 int insert_size = INTVAL (operands[1]) & 31;
3488 /* Align extract field with insert field */
3489 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3490 operands[1] = GEN_INT (insert_start + insert_size - 1);
3491 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3492 }"
3493 [(set_attr "type" "insert_word")])
3495 ;; combine patterns for rlwimi
3496 (define_insn "*insvsi_internal5"
3497 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3498 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3499 (match_operand:SI 1 "mask_operand" "i"))
3500 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3501 (match_operand:SI 2 "const_int_operand" "i"))
3502 (match_operand:SI 5 "mask_operand" "i"))))]
3503 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3504 "*
3505 {
3506 int me = extract_ME(operands[5]);
3507 int mb = extract_MB(operands[5]);
3508 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3509 operands[2] = GEN_INT(mb);
3510 operands[1] = GEN_INT(me);
3511 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3512 }"
3513 [(set_attr "type" "insert_word")])
3515 (define_insn "*insvsi_internal6"
3516 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3517 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3518 (match_operand:SI 2 "const_int_operand" "i"))
3519 (match_operand:SI 5 "mask_operand" "i"))
3520 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3521 (match_operand:SI 1 "mask_operand" "i"))))]
3522 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3523 "*
3524 {
3525 int me = extract_ME(operands[5]);
3526 int mb = extract_MB(operands[5]);
3527 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3528 operands[2] = GEN_INT(mb);
3529 operands[1] = GEN_INT(me);
3530 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3531 }"
3532 [(set_attr "type" "insert_word")])
3534 (define_insn "insvdi_internal"
3535 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3536 (match_operand:SI 1 "const_int_operand" "i")
3537 (match_operand:SI 2 "const_int_operand" "i"))
3538 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3539 "TARGET_POWERPC64"
3540 "*
3541 {
3542 int start = INTVAL (operands[2]) & 63;
3543 int size = INTVAL (operands[1]) & 63;
3545 operands[1] = GEN_INT (64 - start - size);
3546 return \"rldimi %0,%3,%H1,%H2\";
3547 }"
3548 [(set_attr "type" "insert_dword")])
3550 (define_insn "*insvdi_internal2"
3551 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3552 (match_operand:SI 1 "const_int_operand" "i")
3553 (match_operand:SI 2 "const_int_operand" "i"))
3554 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3555 (match_operand:SI 4 "const_int_operand" "i")))]
3556 "TARGET_POWERPC64
3557 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3558 "*
3559 {
3560 int shift = INTVAL (operands[4]) & 63;
3561 int start = (INTVAL (operands[2]) & 63) - 32;
3562 int size = INTVAL (operands[1]) & 63;
3564 operands[4] = GEN_INT (64 - shift - start - size);
3565 operands[2] = GEN_INT (start);
3566 operands[1] = GEN_INT (start + size - 1);
3567 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3568 }")
3570 (define_insn "*insvdi_internal3"
3571 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3572 (match_operand:SI 1 "const_int_operand" "i")
3573 (match_operand:SI 2 "const_int_operand" "i"))
3574 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3575 (match_operand:SI 4 "const_int_operand" "i")))]
3576 "TARGET_POWERPC64
3577 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3578 "*
3579 {
3580 int shift = INTVAL (operands[4]) & 63;
3581 int start = (INTVAL (operands[2]) & 63) - 32;
3582 int size = INTVAL (operands[1]) & 63;
3584 operands[4] = GEN_INT (64 - shift - start - size);
3585 operands[2] = GEN_INT (start);
3586 operands[1] = GEN_INT (start + size - 1);
3587 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3588 }")
3590 (define_expand "extzv"
3591 [(set (match_operand 0 "gpc_reg_operand" "")
3592 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3593 (match_operand:SI 2 "const_int_operand" "")
3594 (match_operand:SI 3 "const_int_operand" "")))]
3595 ""
3596 "
3597 {
3598 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3599 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3600 compiler if the address of the structure is taken later. */
3601 if (GET_CODE (operands[0]) == SUBREG
3602 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3603 FAIL;
3605 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3606 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3607 operands[3]));
3608 else
3609 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3610 operands[3]));
3611 DONE;
3612 }")
3614 (define_insn "extzvsi_internal"
3615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3616 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3617 (match_operand:SI 2 "const_int_operand" "i")
3618 (match_operand:SI 3 "const_int_operand" "i")))]
3619 ""
3620 "*
3621 {
3622 int start = INTVAL (operands[3]) & 31;
3623 int size = INTVAL (operands[2]) & 31;
3625 if (start + size >= 32)
3626 operands[3] = const0_rtx;
3627 else
3628 operands[3] = GEN_INT (start + size);
3629 return \"rlwinm %0,%1,%3,%s2,31\";
3630 }")
3632 (define_insn "*extzvsi_internal1"
3633 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3634 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3635 (match_operand:SI 2 "const_int_operand" "i,i")
3636 (match_operand:SI 3 "const_int_operand" "i,i"))
3637 (const_int 0)))
3638 (clobber (match_scratch:SI 4 "=r,r"))]
3639 ""
3640 "*
3641 {
3642 int start = INTVAL (operands[3]) & 31;
3643 int size = INTVAL (operands[2]) & 31;
3645 /* Force split for non-cc0 compare. */
3646 if (which_alternative == 1)
3647 return \"#\";
3649 /* If the bit-field being tested fits in the upper or lower half of a
3650 word, it is possible to use andiu. or andil. to test it. This is
3651 useful because the condition register set-use delay is smaller for
3652 andi[ul]. than for rlinm. This doesn't work when the starting bit
3653 position is 0 because the LT and GT bits may be set wrong. */
3655 if ((start > 0 && start + size <= 16) || start >= 16)
3656 {
3657 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3658 - (1 << (16 - (start & 15) - size))));
3659 if (start < 16)
3660 return \"andis. %4,%1,%3\";
3661 else
3662 return \"andi. %4,%1,%3\";
3663 }
3665 if (start + size >= 32)
3666 operands[3] = const0_rtx;
3667 else
3668 operands[3] = GEN_INT (start + size);
3669 return \"rlwinm. %4,%1,%3,%s2,31\";
3670 }"
3671 [(set_attr "type" "delayed_compare")
3672 (set_attr "length" "4,8")])
3674 (define_split
3675 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3676 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3677 (match_operand:SI 2 "const_int_operand" "")
3678 (match_operand:SI 3 "const_int_operand" ""))
3679 (const_int 0)))
3680 (clobber (match_scratch:SI 4 ""))]
3681 "reload_completed"
3682 [(set (match_dup 4)
3683 (zero_extract:SI (match_dup 1) (match_dup 2)
3684 (match_dup 3)))
3685 (set (match_dup 0)
3686 (compare:CC (match_dup 4)
3687 (const_int 0)))]
3688 "")
3690 (define_insn "*extzvsi_internal2"
3691 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3692 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3693 (match_operand:SI 2 "const_int_operand" "i,i")
3694 (match_operand:SI 3 "const_int_operand" "i,i"))
3695 (const_int 0)))
3696 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3697 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3698 ""
3699 "*
3700 {
3701 int start = INTVAL (operands[3]) & 31;
3702 int size = INTVAL (operands[2]) & 31;
3704 /* Force split for non-cc0 compare. */
3705 if (which_alternative == 1)
3706 return \"#\";
3708 /* Since we are using the output value, we can't ignore any need for
3709 a shift. The bit-field must end at the LSB. */
3710 if (start >= 16 && start + size == 32)
3711 {
3712 operands[3] = GEN_INT ((1 << size) - 1);
3713 return \"andi. %0,%1,%3\";
3714 }
3716 if (start + size >= 32)
3717 operands[3] = const0_rtx;
3718 else
3719 operands[3] = GEN_INT (start + size);
3720 return \"rlwinm. %0,%1,%3,%s2,31\";
3721 }"
3722 [(set_attr "type" "delayed_compare")
3723 (set_attr "length" "4,8")])
3725 (define_split
3726 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3727 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3728 (match_operand:SI 2 "const_int_operand" "")
3729 (match_operand:SI 3 "const_int_operand" ""))
3730 (const_int 0)))
3731 (set (match_operand:SI 0 "gpc_reg_operand" "")
3732 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3733 "reload_completed"
3734 [(set (match_dup 0)
3735 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3736 (set (match_dup 4)
3737 (compare:CC (match_dup 0)
3738 (const_int 0)))]
3739 "")
3741 (define_insn "extzvdi_internal"
3742 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3743 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3744 (match_operand:SI 2 "const_int_operand" "i")
3745 (match_operand:SI 3 "const_int_operand" "i")))]
3746 "TARGET_POWERPC64"
3747 "*
3748 {
3749 int start = INTVAL (operands[3]) & 63;
3750 int size = INTVAL (operands[2]) & 63;
3752 if (start + size >= 64)
3753 operands[3] = const0_rtx;
3754 else
3755 operands[3] = GEN_INT (start + size);
3756 operands[2] = GEN_INT (64 - size);
3757 return \"rldicl %0,%1,%3,%2\";
3758 }")
3760 (define_insn "*extzvdi_internal1"
3761 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3762 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3763 (match_operand:SI 2 "const_int_operand" "i")
3764 (match_operand:SI 3 "const_int_operand" "i"))
3765 (const_int 0)))
3766 (clobber (match_scratch:DI 4 "=r"))]
3767 "TARGET_64BIT && rs6000_gen_cell_microcode"
3768 "*
3769 {
3770 int start = INTVAL (operands[3]) & 63;
3771 int size = INTVAL (operands[2]) & 63;
3773 if (start + size >= 64)
3774 operands[3] = const0_rtx;
3775 else
3776 operands[3] = GEN_INT (start + size);
3777 operands[2] = GEN_INT (64 - size);
3778 return \"rldicl. %4,%1,%3,%2\";
3779 }"
3780 [(set_attr "type" "compare")])
3782 (define_insn "*extzvdi_internal2"
3783 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3784 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3785 (match_operand:SI 2 "const_int_operand" "i")
3786 (match_operand:SI 3 "const_int_operand" "i"))
3787 (const_int 0)))
3788 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3789 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3790 "TARGET_64BIT && rs6000_gen_cell_microcode"
3791 "*
3792 {
3793 int start = INTVAL (operands[3]) & 63;
3794 int size = INTVAL (operands[2]) & 63;
3796 if (start + size >= 64)
3797 operands[3] = const0_rtx;
3798 else
3799 operands[3] = GEN_INT (start + size);
3800 operands[2] = GEN_INT (64 - size);
3801 return \"rldicl. %0,%1,%3,%2\";
3802 }"
3803 [(set_attr "type" "compare")])
3805 (define_insn "rotlsi3"
3806 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3807 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3808 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3809 ""
3810 "@
3811 rlwnm %0,%1,%2,0xffffffff
3812 rlwinm %0,%1,%h2,0xffffffff"
3813 [(set_attr "type" "var_shift_rotate,integer")])
3815 (define_insn "*rotlsi3_64"
3816 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3817 (zero_extend:DI
3818 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3819 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3820 "TARGET_64BIT"
3821 "@
3822 rlwnm %0,%1,%2,0xffffffff
3823 rlwinm %0,%1,%h2,0xffffffff"
3824 [(set_attr "type" "var_shift_rotate,integer")])
3826 (define_insn "*rotlsi3_internal2"
3827 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3828 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3829 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3830 (const_int 0)))
3831 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3832 ""
3833 "@
3834 rlwnm. %3,%1,%2,0xffffffff
3835 rlwinm. %3,%1,%h2,0xffffffff
3836 #
3837 #"
3838 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3839 (set_attr "length" "4,4,8,8")])
3841 (define_split
3842 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3843 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3844 (match_operand:SI 2 "reg_or_cint_operand" ""))
3845 (const_int 0)))
3846 (clobber (match_scratch:SI 3 ""))]
3847 "reload_completed"
3848 [(set (match_dup 3)
3849 (rotate:SI (match_dup 1) (match_dup 2)))
3850 (set (match_dup 0)
3851 (compare:CC (match_dup 3)
3852 (const_int 0)))]
3853 "")
3855 (define_insn "*rotlsi3_internal3"
3856 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3857 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3858 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3859 (const_int 0)))
3860 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3861 (rotate:SI (match_dup 1) (match_dup 2)))]
3862 ""
3863 "@
3864 rlwnm. %0,%1,%2,0xffffffff
3865 rlwinm. %0,%1,%h2,0xffffffff
3866 #
3867 #"
3868 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3869 (set_attr "length" "4,4,8,8")])
3871 (define_split
3872 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3873 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3874 (match_operand:SI 2 "reg_or_cint_operand" ""))
3875 (const_int 0)))
3876 (set (match_operand:SI 0 "gpc_reg_operand" "")
3877 (rotate:SI (match_dup 1) (match_dup 2)))]
3878 "reload_completed"
3879 [(set (match_dup 0)
3880 (rotate:SI (match_dup 1) (match_dup 2)))
3881 (set (match_dup 3)
3882 (compare:CC (match_dup 0)
3883 (const_int 0)))]
3884 "")
3886 (define_insn "*rotlsi3_internal4"
3887 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3888 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3889 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3890 (match_operand:SI 3 "mask_operand" "n,n")))]
3891 ""
3892 "@
3893 rlwnm %0,%1,%2,%m3,%M3
3894 rlwinm %0,%1,%h2,%m3,%M3"
3895 [(set_attr "type" "var_shift_rotate,integer")])
3897 (define_insn "*rotlsi3_internal5"
3898 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3899 (compare:CC (and:SI
3900 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3901 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3902 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3903 (const_int 0)))
3904 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3905 ""
3906 "@
3907 rlwnm. %4,%1,%2,%m3,%M3
3908 rlwinm. %4,%1,%h2,%m3,%M3
3909 #
3910 #"
3911 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3912 (set_attr "length" "4,4,8,8")])
3914 (define_split
3915 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3916 (compare:CC (and:SI
3917 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3918 (match_operand:SI 2 "reg_or_cint_operand" ""))
3919 (match_operand:SI 3 "mask_operand" ""))
3920 (const_int 0)))
3921 (clobber (match_scratch:SI 4 ""))]
3922 "reload_completed"
3923 [(set (match_dup 4)
3924 (and:SI (rotate:SI (match_dup 1)
3925 (match_dup 2))
3926 (match_dup 3)))
3927 (set (match_dup 0)
3928 (compare:CC (match_dup 4)
3929 (const_int 0)))]
3930 "")
3932 (define_insn "*rotlsi3_internal6"
3933 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3934 (compare:CC (and:SI
3935 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3936 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3937 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3938 (const_int 0)))
3939 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3940 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3941 ""
3942 "@
3943 rlwnm. %0,%1,%2,%m3,%M3
3944 rlwinm. %0,%1,%h2,%m3,%M3
3945 #
3946 #"
3947 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3948 (set_attr "length" "4,4,8,8")])
3950 (define_split
3951 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3952 (compare:CC (and:SI
3953 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3954 (match_operand:SI 2 "reg_or_cint_operand" ""))
3955 (match_operand:SI 3 "mask_operand" ""))
3956 (const_int 0)))
3957 (set (match_operand:SI 0 "gpc_reg_operand" "")
3958 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3959 "reload_completed"
3960 [(set (match_dup 0)
3961 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3962 (set (match_dup 4)
3963 (compare:CC (match_dup 0)
3964 (const_int 0)))]
3965 "")
3967 (define_insn "*rotlsi3_internal7le"
3968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3969 (zero_extend:SI
3970 (subreg:QI
3971 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3972 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3973 "!BYTES_BIG_ENDIAN"
3974 "rlw%I2nm %0,%1,%h2,0xff"
3975 [(set (attr "cell_micro")
3976 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3977 (const_string "not")
3978 (const_string "always")))])
3980 (define_insn "*rotlsi3_internal7be"
3981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3982 (zero_extend:SI
3983 (subreg:QI
3984 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3985 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3986 "BYTES_BIG_ENDIAN"
3987 "rlw%I2nm %0,%1,%h2,0xff"
3988 [(set (attr "cell_micro")
3989 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3990 (const_string "not")
3991 (const_string "always")))])
3993 (define_insn "*rotlsi3_internal8le"
3994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3995 (compare:CC (zero_extend:SI
3996 (subreg:QI
3997 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3998 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3999 (const_int 0)))
4000 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4001 "!BYTES_BIG_ENDIAN"
4002 "@
4003 rlwnm. %3,%1,%2,0xff
4004 rlwinm. %3,%1,%h2,0xff
4005 #
4006 #"
4007 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4008 (set_attr "length" "4,4,8,8")])
4010 (define_insn "*rotlsi3_internal8be"
4011 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4012 (compare:CC (zero_extend:SI
4013 (subreg:QI
4014 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4015 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
4016 (const_int 0)))
4017 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4018 "BYTES_BIG_ENDIAN"
4019 "@
4020 rlwnm. %3,%1,%2,0xff
4021 rlwinm. %3,%1,%h2,0xff
4022 #
4023 #"
4024 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4025 (set_attr "length" "4,4,8,8")])
4027 (define_split
4028 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4029 (compare:CC (zero_extend:SI
4030 (subreg:QI
4031 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4032 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4033 (const_int 0)))
4034 (clobber (match_scratch:SI 3 ""))]
4035 "!BYTES_BIG_ENDIAN && reload_completed"
4036 [(set (match_dup 3)
4037 (zero_extend:SI (subreg:QI
4038 (rotate:SI (match_dup 1)
4039 (match_dup 2)) 0)))
4040 (set (match_dup 0)
4041 (compare:CC (match_dup 3)
4042 (const_int 0)))]
4043 "")
4045 (define_split
4046 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4047 (compare:CC (zero_extend:SI
4048 (subreg:QI
4049 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4050 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4051 (const_int 0)))
4052 (clobber (match_scratch:SI 3 ""))]
4053 "BYTES_BIG_ENDIAN && reload_completed"
4054 [(set (match_dup 3)
4055 (zero_extend:SI (subreg:QI
4056 (rotate:SI (match_dup 1)
4057 (match_dup 2)) 3)))
4058 (set (match_dup 0)
4059 (compare:CC (match_dup 3)
4060 (const_int 0)))]
4061 "")
4063 (define_insn "*rotlsi3_internal9le"
4064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4065 (compare:CC (zero_extend:SI
4066 (subreg:QI
4067 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4068 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4069 (const_int 0)))
4070 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4071 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4072 "!BYTES_BIG_ENDIAN"
4073 "@
4074 rlwnm. %0,%1,%2,0xff
4075 rlwinm. %0,%1,%h2,0xff
4076 #
4077 #"
4078 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4079 (set_attr "length" "4,4,8,8")])
4081 (define_insn "*rotlsi3_internal9be"
4082 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4083 (compare:CC (zero_extend:SI
4084 (subreg:QI
4085 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4086 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
4087 (const_int 0)))
4088 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4089 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4090 "BYTES_BIG_ENDIAN"
4091 "@
4092 rlwnm. %0,%1,%2,0xff
4093 rlwinm. %0,%1,%h2,0xff
4094 #
4095 #"
4096 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4097 (set_attr "length" "4,4,8,8")])
4099 (define_split
4100 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4101 (compare:CC (zero_extend:SI
4102 (subreg:QI
4103 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4104 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4105 (const_int 0)))
4106 (set (match_operand:SI 0 "gpc_reg_operand" "")
4107 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4108 "!BYTES_BIG_ENDIAN && reload_completed"
4109 [(set (match_dup 0)
4110 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4111 (set (match_dup 3)
4112 (compare:CC (match_dup 0)
4113 (const_int 0)))]
4114 "")
4116 (define_split
4117 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4118 (compare:CC (zero_extend:SI
4119 (subreg:QI
4120 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4121 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4122 (const_int 0)))
4123 (set (match_operand:SI 0 "gpc_reg_operand" "")
4124 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4125 "BYTES_BIG_ENDIAN && reload_completed"
4126 [(set (match_dup 0)
4127 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
4128 (set (match_dup 3)
4129 (compare:CC (match_dup 0)
4130 (const_int 0)))]
4131 "")
4133 (define_insn "*rotlsi3_internal10le"
4134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4135 (zero_extend:SI
4136 (subreg:HI
4137 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4138 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4139 "!BYTES_BIG_ENDIAN"
4140 "@
4141 rlwnm %0,%1,%2,0xffff
4142 rlwinm %0,%1,%h2,0xffff"
4143 [(set_attr "type" "var_shift_rotate,integer")])
4145 (define_insn "*rotlsi3_internal10be"
4146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4147 (zero_extend:SI
4148 (subreg:HI
4149 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4150 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]
4151 "BYTES_BIG_ENDIAN"
4152 "@
4153 rlwnm %0,%1,%2,0xffff
4154 rlwinm %0,%1,%h2,0xffff"
4155 [(set_attr "type" "var_shift_rotate,integer")])
4157 (define_insn "*rotlsi3_internal11le"
4158 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4159 (compare:CC (zero_extend:SI
4160 (subreg:HI
4161 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4162 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4163 (const_int 0)))
4164 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4165 "!BYTES_BIG_ENDIAN"
4166 "@
4167 rlwnm. %3,%1,%2,0xffff
4168 rlwinm. %3,%1,%h2,0xffff
4169 #
4170 #"
4171 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4172 (set_attr "length" "4,4,8,8")])
4174 (define_insn "*rotlsi3_internal11be"
4175 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4176 (compare:CC (zero_extend:SI
4177 (subreg:HI
4178 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4179 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4180 (const_int 0)))
4181 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4182 "BYTES_BIG_ENDIAN"
4183 "@
4184 rlwnm. %3,%1,%2,0xffff
4185 rlwinm. %3,%1,%h2,0xffff
4186 #
4187 #"
4188 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4189 (set_attr "length" "4,4,8,8")])
4191 (define_split
4192 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4193 (compare:CC (zero_extend:SI
4194 (subreg:HI
4195 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4196 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4197 (const_int 0)))
4198 (clobber (match_scratch:SI 3 ""))]
4199 "!BYTES_BIG_ENDIAN && reload_completed"
4200 [(set (match_dup 3)
4201 (zero_extend:SI (subreg:HI
4202 (rotate:SI (match_dup 1)
4203 (match_dup 2)) 0)))
4204 (set (match_dup 0)
4205 (compare:CC (match_dup 3)
4206 (const_int 0)))]
4207 "")
4209 (define_split
4210 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4211 (compare:CC (zero_extend:SI
4212 (subreg:HI
4213 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4214 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4215 (const_int 0)))
4216 (clobber (match_scratch:SI 3 ""))]
4217 "BYTES_BIG_ENDIAN && reload_completed"
4218 [(set (match_dup 3)
4219 (zero_extend:SI (subreg:HI
4220 (rotate:SI (match_dup 1)
4221 (match_dup 2)) 2)))
4222 (set (match_dup 0)
4223 (compare:CC (match_dup 3)
4224 (const_int 0)))]
4225 "")
4227 (define_insn "*rotlsi3_internal12le"
4228 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4229 (compare:CC (zero_extend:SI
4230 (subreg:HI
4231 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4232 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4233 (const_int 0)))
4234 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4235 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4236 "!BYTES_BIG_ENDIAN"
4237 "@
4238 rlwnm. %0,%1,%2,0xffff
4239 rlwinm. %0,%1,%h2,0xffff
4240 #
4241 #"
4242 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4243 (set_attr "length" "4,4,8,8")])
4245 (define_insn "*rotlsi3_internal12be"
4246 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4247 (compare:CC (zero_extend:SI
4248 (subreg:HI
4249 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4250 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4251 (const_int 0)))
4252 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4253 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4254 "BYTES_BIG_ENDIAN"
4255 "@
4256 rlwnm. %0,%1,%2,0xffff
4257 rlwinm. %0,%1,%h2,0xffff
4258 #
4259 #"
4260 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4261 (set_attr "length" "4,4,8,8")])
4263 (define_split
4264 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4265 (compare:CC (zero_extend:SI
4266 (subreg:HI
4267 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4268 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4269 (const_int 0)))
4270 (set (match_operand:SI 0 "gpc_reg_operand" "")
4271 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4272 "!BYTES_BIG_ENDIAN && reload_completed"
4273 [(set (match_dup 0)
4274 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4275 (set (match_dup 3)
4276 (compare:CC (match_dup 0)
4277 (const_int 0)))]
4278 "")
4280 (define_split
4281 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4282 (compare:CC (zero_extend:SI
4283 (subreg:HI
4284 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4285 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4286 (const_int 0)))
4287 (set (match_operand:SI 0 "gpc_reg_operand" "")
4288 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4289 "BYTES_BIG_ENDIAN && reload_completed"
4290 [(set (match_dup 0)
4291 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4292 (set (match_dup 3)
4293 (compare:CC (match_dup 0)
4294 (const_int 0)))]
4295 "")
4297 (define_insn "ashlsi3"
4298 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4299 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4300 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4301 ""
4302 "@
4303 slw %0,%1,%2
4304 slwi %0,%1,%h2"
4305 [(set_attr "type" "var_shift_rotate,shift")])
4307 (define_insn "*ashlsi3_64"
4308 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4309 (zero_extend:DI
4310 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4311 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4312 "TARGET_POWERPC64"
4313 "@
4314 slw %0,%1,%2
4315 slwi %0,%1,%h2"
4316 [(set_attr "type" "var_shift_rotate,shift")])
4318 (define_insn ""
4319 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4320 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4321 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4322 (const_int 0)))
4323 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4324 "TARGET_32BIT"
4325 "@
4326 slw. %3,%1,%2
4327 slwi. %3,%1,%h2
4328 #
4329 #"
4330 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4331 (set_attr "length" "4,4,8,8")])
4333 (define_split
4334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4335 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4336 (match_operand:SI 2 "reg_or_cint_operand" ""))
4337 (const_int 0)))
4338 (clobber (match_scratch:SI 3 ""))]
4339 "TARGET_32BIT && reload_completed"
4340 [(set (match_dup 3)
4341 (ashift:SI (match_dup 1) (match_dup 2)))
4342 (set (match_dup 0)
4343 (compare:CC (match_dup 3)
4344 (const_int 0)))]
4345 "")
4347 (define_insn ""
4348 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4349 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4350 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4351 (const_int 0)))
4352 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4353 (ashift:SI (match_dup 1) (match_dup 2)))]
4354 "TARGET_32BIT"
4355 "@
4356 slw. %0,%1,%2
4357 slwi. %0,%1,%h2
4358 #
4359 #"
4360 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4361 (set_attr "length" "4,4,8,8")])
4363 (define_split
4364 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4365 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4366 (match_operand:SI 2 "reg_or_cint_operand" ""))
4367 (const_int 0)))
4368 (set (match_operand:SI 0 "gpc_reg_operand" "")
4369 (ashift:SI (match_dup 1) (match_dup 2)))]
4370 "TARGET_32BIT && reload_completed"
4371 [(set (match_dup 0)
4372 (ashift:SI (match_dup 1) (match_dup 2)))
4373 (set (match_dup 3)
4374 (compare:CC (match_dup 0)
4375 (const_int 0)))]
4376 "")
4378 (define_insn "rlwinm"
4379 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4380 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4381 (match_operand:SI 2 "const_int_operand" "i"))
4382 (match_operand:SI 3 "mask_operand" "n")))]
4383 "includes_lshift_p (operands[2], operands[3])"
4384 "rlwinm %0,%1,%h2,%m3,%M3")
4386 (define_insn ""
4387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4388 (compare:CC
4389 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4390 (match_operand:SI 2 "const_int_operand" "i,i"))
4391 (match_operand:SI 3 "mask_operand" "n,n"))
4392 (const_int 0)))
4393 (clobber (match_scratch:SI 4 "=r,r"))]
4394 "includes_lshift_p (operands[2], operands[3])"
4395 "@
4396 rlwinm. %4,%1,%h2,%m3,%M3
4397 #"
4398 [(set_attr "type" "delayed_compare")
4399 (set_attr "length" "4,8")])
4401 (define_split
4402 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4403 (compare:CC
4404 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4405 (match_operand:SI 2 "const_int_operand" ""))
4406 (match_operand:SI 3 "mask_operand" ""))
4407 (const_int 0)))
4408 (clobber (match_scratch:SI 4 ""))]
4409 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4410 [(set (match_dup 4)
4411 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4412 (match_dup 3)))
4413 (set (match_dup 0)
4414 (compare:CC (match_dup 4)
4415 (const_int 0)))]
4416 "")
4418 (define_insn ""
4419 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4420 (compare:CC
4421 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4422 (match_operand:SI 2 "const_int_operand" "i,i"))
4423 (match_operand:SI 3 "mask_operand" "n,n"))
4424 (const_int 0)))
4425 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4426 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4427 "includes_lshift_p (operands[2], operands[3])"
4428 "@
4429 rlwinm. %0,%1,%h2,%m3,%M3
4430 #"
4431 [(set_attr "type" "delayed_compare")
4432 (set_attr "length" "4,8")])
4434 (define_split
4435 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4436 (compare:CC
4437 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4438 (match_operand:SI 2 "const_int_operand" ""))
4439 (match_operand:SI 3 "mask_operand" ""))
4440 (const_int 0)))
4441 (set (match_operand:SI 0 "gpc_reg_operand" "")
4442 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4443 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4444 [(set (match_dup 0)
4445 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4446 (set (match_dup 4)
4447 (compare:CC (match_dup 0)
4448 (const_int 0)))]
4449 "")
4451 (define_insn "lshrsi3"
4452 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4453 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4454 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4455 ""
4456 "@
4457 mr %0,%1
4458 srw %0,%1,%2
4459 srwi %0,%1,%h2"
4460 [(set_attr "type" "integer,var_shift_rotate,shift")])
4462 (define_insn "*lshrsi3_64"
4463 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4464 (zero_extend:DI
4465 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4466 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4467 "TARGET_POWERPC64"
4468 "@
4469 srw %0,%1,%2
4470 srwi %0,%1,%h2"
4471 [(set_attr "type" "var_shift_rotate,shift")])
4473 (define_insn ""
4474 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4475 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4476 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4477 (const_int 0)))
4478 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4479 "TARGET_32BIT"
4480 "@
4481 mr. %1,%1
4482 srw. %3,%1,%2
4483 srwi. %3,%1,%h2
4484 #
4485 #
4486 #"
4487 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4488 (set_attr "length" "4,4,4,8,8,8")])
4490 (define_split
4491 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4492 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4493 (match_operand:SI 2 "reg_or_cint_operand" ""))
4494 (const_int 0)))
4495 (clobber (match_scratch:SI 3 ""))]
4496 "TARGET_32BIT && reload_completed"
4497 [(set (match_dup 3)
4498 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4499 (set (match_dup 0)
4500 (compare:CC (match_dup 3)
4501 (const_int 0)))]
4502 "")
4504 (define_insn ""
4505 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4506 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4507 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4508 (const_int 0)))
4509 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4510 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4511 "TARGET_32BIT"
4512 "@
4513 mr. %0,%1
4514 srw. %0,%1,%2
4515 srwi. %0,%1,%h2
4516 #
4517 #
4518 #"
4519 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4520 (set_attr "length" "4,4,4,8,8,8")])
4522 (define_split
4523 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4524 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4525 (match_operand:SI 2 "reg_or_cint_operand" ""))
4526 (const_int 0)))
4527 (set (match_operand:SI 0 "gpc_reg_operand" "")
4528 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4529 "TARGET_32BIT && reload_completed"
4530 [(set (match_dup 0)
4531 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4532 (set (match_dup 3)
4533 (compare:CC (match_dup 0)
4534 (const_int 0)))]
4535 "")
4537 (define_insn ""
4538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4539 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4540 (match_operand:SI 2 "const_int_operand" "i"))
4541 (match_operand:SI 3 "mask_operand" "n")))]
4542 "includes_rshift_p (operands[2], operands[3])"
4543 "rlwinm %0,%1,%s2,%m3,%M3")
4545 (define_insn ""
4546 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4547 (compare:CC
4548 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4549 (match_operand:SI 2 "const_int_operand" "i,i"))
4550 (match_operand:SI 3 "mask_operand" "n,n"))
4551 (const_int 0)))
4552 (clobber (match_scratch:SI 4 "=r,r"))]
4553 "includes_rshift_p (operands[2], operands[3])"
4554 "@
4555 rlwinm. %4,%1,%s2,%m3,%M3
4556 #"
4557 [(set_attr "type" "delayed_compare")
4558 (set_attr "length" "4,8")])
4560 (define_split
4561 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4562 (compare:CC
4563 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4564 (match_operand:SI 2 "const_int_operand" ""))
4565 (match_operand:SI 3 "mask_operand" ""))
4566 (const_int 0)))
4567 (clobber (match_scratch:SI 4 ""))]
4568 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4569 [(set (match_dup 4)
4570 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4571 (match_dup 3)))
4572 (set (match_dup 0)
4573 (compare:CC (match_dup 4)
4574 (const_int 0)))]
4575 "")
4577 (define_insn ""
4578 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4579 (compare:CC
4580 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4581 (match_operand:SI 2 "const_int_operand" "i,i"))
4582 (match_operand:SI 3 "mask_operand" "n,n"))
4583 (const_int 0)))
4584 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4585 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4586 "includes_rshift_p (operands[2], operands[3])"
4587 "@
4588 rlwinm. %0,%1,%s2,%m3,%M3
4589 #"
4590 [(set_attr "type" "delayed_compare")
4591 (set_attr "length" "4,8")])
4593 (define_split
4594 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4595 (compare:CC
4596 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4597 (match_operand:SI 2 "const_int_operand" ""))
4598 (match_operand:SI 3 "mask_operand" ""))
4599 (const_int 0)))
4600 (set (match_operand:SI 0 "gpc_reg_operand" "")
4601 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4602 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4603 [(set (match_dup 0)
4604 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4605 (set (match_dup 4)
4606 (compare:CC (match_dup 0)
4607 (const_int 0)))]
4608 "")
4610 (define_insn "*lshiftrt_internal1le"
4611 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4612 (zero_extend:SI
4613 (subreg:QI
4614 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4615 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4616 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4617 "rlwinm %0,%1,%s2,0xff")
4619 (define_insn "*lshiftrt_internal1be"
4620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4621 (zero_extend:SI
4622 (subreg:QI
4623 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4624 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4625 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4626 "rlwinm %0,%1,%s2,0xff")
4628 (define_insn "*lshiftrt_internal2le"
4629 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4630 (compare:CC
4631 (zero_extend:SI
4632 (subreg:QI
4633 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4634 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4635 (const_int 0)))
4636 (clobber (match_scratch:SI 3 "=r,r"))]
4637 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4638 "@
4639 rlwinm. %3,%1,%s2,0xff
4640 #"
4641 [(set_attr "type" "delayed_compare")
4642 (set_attr "length" "4,8")])
4644 (define_insn "*lshiftrt_internal2be"
4645 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4646 (compare:CC
4647 (zero_extend:SI
4648 (subreg:QI
4649 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4650 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4651 (const_int 0)))
4652 (clobber (match_scratch:SI 3 "=r,r"))]
4653 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4654 "@
4655 rlwinm. %3,%1,%s2,0xff
4656 #"
4657 [(set_attr "type" "delayed_compare")
4658 (set_attr "length" "4,8")])
4660 (define_split
4661 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4662 (compare:CC
4663 (zero_extend:SI
4664 (subreg:QI
4665 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4666 (match_operand:SI 2 "const_int_operand" "")) 0))
4667 (const_int 0)))
4668 (clobber (match_scratch:SI 3 ""))]
4669 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4670 [(set (match_dup 3)
4671 (zero_extend:SI (subreg:QI
4672 (lshiftrt:SI (match_dup 1)
4673 (match_dup 2)) 0)))
4674 (set (match_dup 0)
4675 (compare:CC (match_dup 3)
4676 (const_int 0)))]
4677 "")
4679 (define_split
4680 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4681 (compare:CC
4682 (zero_extend:SI
4683 (subreg:QI
4684 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4685 (match_operand:SI 2 "const_int_operand" "")) 3))
4686 (const_int 0)))
4687 (clobber (match_scratch:SI 3 ""))]
4688 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4689 [(set (match_dup 3)
4690 (zero_extend:SI (subreg:QI
4691 (lshiftrt:SI (match_dup 1)
4692 (match_dup 2)) 3)))
4693 (set (match_dup 0)
4694 (compare:CC (match_dup 3)
4695 (const_int 0)))]
4696 "")
4698 (define_insn "*lshiftrt_internal3le"
4699 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4700 (compare:CC
4701 (zero_extend:SI
4702 (subreg:QI
4703 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4704 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4705 (const_int 0)))
4706 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4707 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4708 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4709 "@
4710 rlwinm. %0,%1,%s2,0xff
4711 #"
4712 [(set_attr "type" "delayed_compare")
4713 (set_attr "length" "4,8")])
4715 (define_insn "*lshiftrt_internal3be"
4716 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4717 (compare:CC
4718 (zero_extend:SI
4719 (subreg:QI
4720 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4721 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4722 (const_int 0)))
4723 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4724 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4725 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4726 "@
4727 rlwinm. %0,%1,%s2,0xff
4728 #"
4729 [(set_attr "type" "delayed_compare")
4730 (set_attr "length" "4,8")])
4732 (define_split
4733 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4734 (compare:CC
4735 (zero_extend:SI
4736 (subreg:QI
4737 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4738 (match_operand:SI 2 "const_int_operand" "")) 0))
4739 (const_int 0)))
4740 (set (match_operand:SI 0 "gpc_reg_operand" "")
4741 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4742 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4743 [(set (match_dup 0)
4744 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4745 (set (match_dup 3)
4746 (compare:CC (match_dup 0)
4747 (const_int 0)))]
4748 "")
4750 (define_split
4751 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4752 (compare:CC
4753 (zero_extend:SI
4754 (subreg:QI
4755 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4756 (match_operand:SI 2 "const_int_operand" "")) 3))
4757 (const_int 0)))
4758 (set (match_operand:SI 0 "gpc_reg_operand" "")
4759 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4760 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4761 [(set (match_dup 0)
4762 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4763 (set (match_dup 3)
4764 (compare:CC (match_dup 0)
4765 (const_int 0)))]
4766 "")
4768 (define_insn "*lshiftrt_internal4le"
4769 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4770 (zero_extend:SI
4771 (subreg:HI
4772 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4773 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4774 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4775 "rlwinm %0,%1,%s2,0xffff")
4777 (define_insn "*lshiftrt_internal4be"
4778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4779 (zero_extend:SI
4780 (subreg:HI
4781 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4782 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4783 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4784 "rlwinm %0,%1,%s2,0xffff")
4786 (define_insn "*lshiftrt_internal5le"
4787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4788 (compare:CC
4789 (zero_extend:SI
4790 (subreg:HI
4791 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4792 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4793 (const_int 0)))
4794 (clobber (match_scratch:SI 3 "=r,r"))]
4795 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4796 "@
4797 rlwinm. %3,%1,%s2,0xffff
4798 #"
4799 [(set_attr "type" "delayed_compare")
4800 (set_attr "length" "4,8")])
4802 (define_insn "*lshiftrt_internal5be"
4803 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4804 (compare:CC
4805 (zero_extend:SI
4806 (subreg:HI
4807 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4808 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4809 (const_int 0)))
4810 (clobber (match_scratch:SI 3 "=r,r"))]
4811 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4812 "@
4813 rlwinm. %3,%1,%s2,0xffff
4814 #"
4815 [(set_attr "type" "delayed_compare")
4816 (set_attr "length" "4,8")])
4818 (define_split
4819 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4820 (compare:CC
4821 (zero_extend:SI
4822 (subreg:HI
4823 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4824 (match_operand:SI 2 "const_int_operand" "")) 0))
4825 (const_int 0)))
4826 (clobber (match_scratch:SI 3 ""))]
4827 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4828 [(set (match_dup 3)
4829 (zero_extend:SI (subreg:HI
4830 (lshiftrt:SI (match_dup 1)
4831 (match_dup 2)) 0)))
4832 (set (match_dup 0)
4833 (compare:CC (match_dup 3)
4834 (const_int 0)))]
4835 "")
4837 (define_split
4838 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4839 (compare:CC
4840 (zero_extend:SI
4841 (subreg:HI
4842 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4843 (match_operand:SI 2 "const_int_operand" "")) 2))
4844 (const_int 0)))
4845 (clobber (match_scratch:SI 3 ""))]
4846 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4847 [(set (match_dup 3)
4848 (zero_extend:SI (subreg:HI
4849 (lshiftrt:SI (match_dup 1)
4850 (match_dup 2)) 2)))
4851 (set (match_dup 0)
4852 (compare:CC (match_dup 3)
4853 (const_int 0)))]
4854 "")
4856 (define_insn "*lshiftrt_internal5le"
4857 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4858 (compare:CC
4859 (zero_extend:SI
4860 (subreg:HI
4861 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4862 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4863 (const_int 0)))
4864 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4865 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4866 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4867 "@
4868 rlwinm. %0,%1,%s2,0xffff
4869 #"
4870 [(set_attr "type" "delayed_compare")
4871 (set_attr "length" "4,8")])
4873 (define_insn "*lshiftrt_internal5be"
4874 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4875 (compare:CC
4876 (zero_extend:SI
4877 (subreg:HI
4878 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4879 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4880 (const_int 0)))
4881 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4882 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4883 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4884 "@
4885 rlwinm. %0,%1,%s2,0xffff
4886 #"
4887 [(set_attr "type" "delayed_compare")
4888 (set_attr "length" "4,8")])
4890 (define_split
4891 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4892 (compare:CC
4893 (zero_extend:SI
4894 (subreg:HI
4895 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4896 (match_operand:SI 2 "const_int_operand" "")) 0))
4897 (const_int 0)))
4898 (set (match_operand:SI 0 "gpc_reg_operand" "")
4899 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4900 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4901 [(set (match_dup 0)
4902 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4903 (set (match_dup 3)
4904 (compare:CC (match_dup 0)
4905 (const_int 0)))]
4906 "")
4908 (define_split
4909 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4910 (compare:CC
4911 (zero_extend:SI
4912 (subreg:HI
4913 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4914 (match_operand:SI 2 "const_int_operand" "")) 2))
4915 (const_int 0)))
4916 (set (match_operand:SI 0 "gpc_reg_operand" "")
4917 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4918 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4919 [(set (match_dup 0)
4920 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4921 (set (match_dup 3)
4922 (compare:CC (match_dup 0)
4923 (const_int 0)))]
4924 "")
4926 (define_insn "ashrsi3"
4927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4928 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4929 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4930 ""
4931 "@
4932 sraw %0,%1,%2
4933 srawi %0,%1,%h2"
4934 [(set_attr "type" "var_shift_rotate,shift")])
4936 (define_insn "*ashrsi3_64"
4937 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4938 (sign_extend:DI
4939 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4940 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4941 "TARGET_POWERPC64"
4942 "@
4943 sraw %0,%1,%2
4944 srawi %0,%1,%h2"
4945 [(set_attr "type" "var_shift_rotate,shift")])
4947 (define_insn ""
4948 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4949 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4950 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4951 (const_int 0)))
4952 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4953 ""
4954 "@
4955 sraw. %3,%1,%2
4956 srawi. %3,%1,%h2
4957 #
4958 #"
4959 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4960 (set_attr "length" "4,4,8,8")])
4962 (define_split
4963 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4964 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4965 (match_operand:SI 2 "reg_or_cint_operand" ""))
4966 (const_int 0)))
4967 (clobber (match_scratch:SI 3 ""))]
4968 "reload_completed"
4969 [(set (match_dup 3)
4970 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4971 (set (match_dup 0)
4972 (compare:CC (match_dup 3)
4973 (const_int 0)))]
4974 "")
4976 (define_insn ""
4977 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4978 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4979 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4980 (const_int 0)))
4981 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4982 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4983 ""
4984 "@
4985 sraw. %0,%1,%2
4986 srawi. %0,%1,%h2
4987 #
4988 #"
4989 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4990 (set_attr "length" "4,4,8,8")])
4991 \f
4992 ;; Builtins to replace a division to generate FRE reciprocal estimate
4993 ;; instructions and the necessary fixup instructions
4994 (define_expand "recip<mode>3"
4995 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4996 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4997 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4998 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4999 {
5000 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5001 DONE;
5002 })
5004 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5005 ;; hardware division. This is only done before register allocation and with
5006 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5007 (define_split
5008 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5009 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5010 (match_operand 2 "gpc_reg_operand" "")))]
5011 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5012 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5013 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5014 [(const_int 0)]
5015 {
5016 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5017 DONE;
5018 })
5020 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5021 ;; appropriate fixup.
5022 (define_expand "rsqrt<mode>2"
5023 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5024 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5025 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5026 {
5027 rs6000_emit_swrsqrt (operands[0], operands[1]);
5028 DONE;
5029 })
5030 \f
5031 (define_split
5032 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5033 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5034 (match_operand:SI 2 "reg_or_cint_operand" ""))
5035 (const_int 0)))
5036 (set (match_operand:SI 0 "gpc_reg_operand" "")
5037 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5038 "reload_completed"
5039 [(set (match_dup 0)
5040 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5041 (set (match_dup 3)
5042 (compare:CC (match_dup 0)
5043 (const_int 0)))]
5044 "")
5046 ;; Floating-point insns, excluding normal data motion.
5047 ;;
5048 ;; PowerPC has a full set of single-precision floating point instructions.
5049 ;;
5050 ;; For the POWER architecture, we pretend that we have both SFmode and
5051 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5052 ;; The only conversions we will do will be when storing to memory. In that
5053 ;; case, we will use the "frsp" instruction before storing.
5054 ;;
5055 ;; Note that when we store into a single-precision memory location, we need to
5056 ;; use the frsp insn first. If the register being stored isn't dead, we
5057 ;; need a scratch register for the frsp. But this is difficult when the store
5058 ;; is done by reload. It is not incorrect to do the frsp on the register in
5059 ;; this case, we just lose precision that we would have otherwise gotten but
5060 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5062 (define_expand "extendsfdf2"
5063 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5064 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5065 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5066 "")
5068 (define_insn_and_split "*extendsfdf2_fpr"
5069 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,wy,?wy,wv")
5070 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wz,Z")))]
5071 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5072 "@
5073 #
5074 fmr %0,%1
5075 lfs%U1%X1 %0,%1
5076 #
5077 xxlor %x0,%x1,%x1
5078 lxsspx %x0,%y1"
5079 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5080 [(const_int 0)]
5081 {
5082 emit_note (NOTE_INSN_DELETED);
5083 DONE;
5084 }
5085 [(set_attr_alternative "type"
5086 [(const_string "fp")
5087 (const_string "fp")
5088 (if_then_else
5089 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
5090 (const_string "fpload_ux")
5091 (if_then_else
5092 (match_test "update_address_mem (operands[1], VOIDmode)")
5093 (const_string "fpload_u")
5094 (const_string "fpload")))
5095 (const_string "fp")
5096 (const_string "vecsimple")
5097 (if_then_else
5098 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
5099 (const_string "fpload_ux")
5100 (if_then_else
5101 (match_test "update_address_mem (operands[1], VOIDmode)")
5102 (const_string "fpload_u")
5103 (const_string "fpload")))])])
5105 (define_expand "truncdfsf2"
5106 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5107 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5108 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5109 "")
5111 (define_insn "*truncdfsf2_fpr"
5112 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5113 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5114 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5115 "frsp %0,%1"
5116 [(set_attr "type" "fp")])
5118 (define_expand "negsf2"
5119 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5120 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5121 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5122 "")
5124 (define_insn "*negsf2"
5125 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5126 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5127 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5128 "fneg %0,%1"
5129 [(set_attr "type" "fp")])
5131 (define_expand "abssf2"
5132 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5133 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5134 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5135 "")
5137 (define_insn "*abssf2"
5138 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5139 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5140 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5141 "fabs %0,%1"
5142 [(set_attr "type" "fp")])
5144 (define_insn ""
5145 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5146 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5147 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5148 "fnabs %0,%1"
5149 [(set_attr "type" "fp")])
5151 (define_expand "addsf3"
5152 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5153 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5154 (match_operand:SF 2 "gpc_reg_operand" "")))]
5155 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5156 "")
5158 (define_insn ""
5159 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5160 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5161 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5162 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5163 "fadds %0,%1,%2"
5164 [(set_attr "type" "fp")
5165 (set_attr "fp_type" "fp_addsub_s")])
5167 (define_expand "subsf3"
5168 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5169 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5170 (match_operand:SF 2 "gpc_reg_operand" "")))]
5171 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5172 "")
5174 (define_insn ""
5175 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5176 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5177 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5178 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5179 "fsubs %0,%1,%2"
5180 [(set_attr "type" "fp")
5181 (set_attr "fp_type" "fp_addsub_s")])
5183 (define_expand "mulsf3"
5184 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5185 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5186 (match_operand:SF 2 "gpc_reg_operand" "")))]
5187 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5188 "")
5190 (define_insn ""
5191 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5192 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5193 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5194 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5195 "fmuls %0,%1,%2"
5196 [(set_attr "type" "fp")
5197 (set_attr "fp_type" "fp_mul_s")])
5199 (define_expand "divsf3"
5200 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5201 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5202 (match_operand:SF 2 "gpc_reg_operand" "")))]
5203 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5204 "")
5206 (define_insn ""
5207 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5208 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5209 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5210 "TARGET_HARD_FLOAT && TARGET_FPRS
5211 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5212 "fdivs %0,%1,%2"
5213 [(set_attr "type" "sdiv")])
5215 (define_insn "fres"
5216 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5217 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5218 "TARGET_FRES"
5219 "fres %0,%1"
5220 [(set_attr "type" "fp")])
5222 ; builtin fmaf support
5223 (define_insn "*fmasf4_fpr"
5224 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5225 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5226 (match_operand:SF 2 "gpc_reg_operand" "f")
5227 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5228 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5229 "fmadds %0,%1,%2,%3"
5230 [(set_attr "type" "fp")
5231 (set_attr "fp_type" "fp_maddsub_s")])
5233 (define_insn "*fmssf4_fpr"
5234 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5235 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5236 (match_operand:SF 2 "gpc_reg_operand" "f")
5237 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5238 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5239 "fmsubs %0,%1,%2,%3"
5240 [(set_attr "type" "fp")
5241 (set_attr "fp_type" "fp_maddsub_s")])
5243 (define_insn "*nfmasf4_fpr"
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5245 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5246 (match_operand:SF 2 "gpc_reg_operand" "f")
5247 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5248 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5249 "fnmadds %0,%1,%2,%3"
5250 [(set_attr "type" "fp")
5251 (set_attr "fp_type" "fp_maddsub_s")])
5253 (define_insn "*nfmssf4_fpr"
5254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5255 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5256 (match_operand:SF 2 "gpc_reg_operand" "f")
5257 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5258 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5259 "fnmsubs %0,%1,%2,%3"
5260 [(set_attr "type" "fp")
5261 (set_attr "fp_type" "fp_maddsub_s")])
5263 (define_expand "sqrtsf2"
5264 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5265 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5266 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
5267 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5268 && !TARGET_SIMPLE_FPU"
5269 "")
5271 (define_insn ""
5272 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5273 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5274 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5275 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5276 "fsqrts %0,%1"
5277 [(set_attr "type" "ssqrt")])
5279 (define_insn "*rsqrtsf_internal1"
5280 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5281 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5282 UNSPEC_RSQRT))]
5283 "TARGET_FRSQRTES"
5284 "frsqrtes %0,%1"
5285 [(set_attr "type" "fp")])
5287 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5288 ;; builtins.c and optabs.c that are not correct for IBM long double
5289 ;; when little-endian.
5290 (define_expand "signbittf2"
5291 [(set (match_dup 2)
5292 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5293 (set (match_dup 3)
5294 (subreg:DI (match_dup 2) 0))
5295 (set (match_dup 4)
5296 (match_dup 5))
5297 (set (match_operand:SI 0 "gpc_reg_operand" "")
5298 (match_dup 6))]
5299 "!TARGET_IEEEQUAD
5300 && TARGET_HARD_FLOAT
5301 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5302 && TARGET_LONG_DOUBLE_128"
5303 {
5304 operands[2] = gen_reg_rtx (DFmode);
5305 operands[3] = gen_reg_rtx (DImode);
5306 if (TARGET_POWERPC64)
5307 {
5308 operands[4] = gen_reg_rtx (DImode);
5309 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5310 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5311 WORDS_BIG_ENDIAN ? 4 : 0);
5312 }
5313 else
5314 {
5315 operands[4] = gen_reg_rtx (SImode);
5316 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5317 WORDS_BIG_ENDIAN ? 0 : 4);
5318 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5319 }
5320 })
5322 (define_expand "copysign<mode>3"
5323 [(set (match_dup 3)
5324 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5325 (set (match_dup 4)
5326 (neg:SFDF (abs:SFDF (match_dup 1))))
5327 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5328 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5329 (match_dup 5))
5330 (match_dup 3)
5331 (match_dup 4)))]
5332 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5333 && ((TARGET_PPC_GFXOPT
5334 && !HONOR_NANS (<MODE>mode)
5335 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5336 || TARGET_CMPB
5337 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5338 {
5339 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5340 {
5341 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5342 operands[2]));
5343 DONE;
5344 }
5346 operands[3] = gen_reg_rtx (<MODE>mode);
5347 operands[4] = gen_reg_rtx (<MODE>mode);
5348 operands[5] = CONST0_RTX (<MODE>mode);
5349 })
5351 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5352 ;; compiler from optimizing -0.0
5353 (define_insn "copysign<mode>3_fcpsgn"
5354 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5355 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
5356 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
5357 UNSPEC_COPYSIGN))]
5358 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5359 "fcpsgn %0,%2,%1"
5360 [(set_attr "type" "fp")])
5362 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5363 ;; fsel instruction and some auxiliary computations. Then we just have a
5364 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5365 ;; combine.
5366 (define_expand "smaxsf3"
5367 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5368 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5369 (match_operand:SF 2 "gpc_reg_operand" ""))
5370 (match_dup 1)
5371 (match_dup 2)))]
5372 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5373 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5374 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5376 (define_expand "sminsf3"
5377 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5378 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5379 (match_operand:SF 2 "gpc_reg_operand" ""))
5380 (match_dup 2)
5381 (match_dup 1)))]
5382 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5383 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5384 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5386 (define_split
5387 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5388 (match_operator:SF 3 "min_max_operator"
5389 [(match_operand:SF 1 "gpc_reg_operand" "")
5390 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5391 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5392 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5393 [(const_int 0)]
5394 "
5395 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5396 operands[1], operands[2]);
5397 DONE;
5398 }")
5400 (define_expand "mov<mode>cc"
5401 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5402 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5403 (match_operand:GPR 2 "gpc_reg_operand" "")
5404 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5405 "TARGET_ISEL<sel>"
5406 "
5407 {
5408 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5409 DONE;
5410 else
5411 FAIL;
5412 }")
5414 ;; We use the BASE_REGS for the isel input operands because, if rA is
5415 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5416 ;; because we may switch the operands and rB may end up being rA.
5417 ;;
5418 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5419 ;; leave out the mode in operand 4 and use one pattern, but reload can
5420 ;; change the mode underneath our feet and then gets confused trying
5421 ;; to reload the value.
5422 (define_insn "isel_signed_<mode>"
5423 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5424 (if_then_else:GPR
5425 (match_operator 1 "scc_comparison_operator"
5426 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5427 (const_int 0)])
5428 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5429 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5430 "TARGET_ISEL<sel>"
5431 "*
5432 { return output_isel (operands); }"
5433 [(set_attr "type" "isel")
5434 (set_attr "length" "4")])
5436 (define_insn "isel_unsigned_<mode>"
5437 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5438 (if_then_else:GPR
5439 (match_operator 1 "scc_comparison_operator"
5440 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5441 (const_int 0)])
5442 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5443 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5444 "TARGET_ISEL<sel>"
5445 "*
5446 { return output_isel (operands); }"
5447 [(set_attr "type" "isel")
5448 (set_attr "length" "4")])
5450 ;; These patterns can be useful for combine; they let combine know that
5451 ;; isel can handle reversed comparisons so long as the operands are
5452 ;; registers.
5454 (define_insn "*isel_reversed_signed_<mode>"
5455 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5456 (if_then_else:GPR
5457 (match_operator 1 "scc_rev_comparison_operator"
5458 [(match_operand:CC 4 "cc_reg_operand" "y")
5459 (const_int 0)])
5460 (match_operand:GPR 2 "gpc_reg_operand" "b")
5461 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5462 "TARGET_ISEL<sel>"
5463 "*
5464 { return output_isel (operands); }"
5465 [(set_attr "type" "isel")
5466 (set_attr "length" "4")])
5468 (define_insn "*isel_reversed_unsigned_<mode>"
5469 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5470 (if_then_else:GPR
5471 (match_operator 1 "scc_rev_comparison_operator"
5472 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5473 (const_int 0)])
5474 (match_operand:GPR 2 "gpc_reg_operand" "b")
5475 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5476 "TARGET_ISEL<sel>"
5477 "*
5478 { return output_isel (operands); }"
5479 [(set_attr "type" "isel")
5480 (set_attr "length" "4")])
5482 (define_expand "movsfcc"
5483 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5484 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5485 (match_operand:SF 2 "gpc_reg_operand" "")
5486 (match_operand:SF 3 "gpc_reg_operand" "")))]
5487 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5488 "
5489 {
5490 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5491 DONE;
5492 else
5493 FAIL;
5494 }")
5496 (define_insn "*fselsfsf4"
5497 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5498 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5499 (match_operand:SF 4 "zero_fp_constant" "F"))
5500 (match_operand:SF 2 "gpc_reg_operand" "f")
5501 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5502 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5503 "fsel %0,%1,%2,%3"
5504 [(set_attr "type" "fp")])
5506 (define_insn "*fseldfsf4"
5507 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5508 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5509 (match_operand:DF 4 "zero_fp_constant" "F"))
5510 (match_operand:SF 2 "gpc_reg_operand" "f")
5511 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5512 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5513 "fsel %0,%1,%2,%3"
5514 [(set_attr "type" "fp")])
5516 (define_expand "negdf2"
5517 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5518 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5519 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5520 "")
5522 (define_insn "*negdf2_fpr"
5523 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5524 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5525 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5526 && !VECTOR_UNIT_VSX_P (DFmode)"
5527 "fneg %0,%1"
5528 [(set_attr "type" "fp")])
5530 (define_expand "absdf2"
5531 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5532 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5533 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5534 "")
5536 (define_insn "*absdf2_fpr"
5537 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5538 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5539 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5540 && !VECTOR_UNIT_VSX_P (DFmode)"
5541 "fabs %0,%1"
5542 [(set_attr "type" "fp")])
5544 (define_insn "*nabsdf2_fpr"
5545 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5546 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5547 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5548 && !VECTOR_UNIT_VSX_P (DFmode)"
5549 "fnabs %0,%1"
5550 [(set_attr "type" "fp")])
5552 (define_expand "adddf3"
5553 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5554 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5555 (match_operand:DF 2 "gpc_reg_operand" "")))]
5556 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5557 "")
5559 (define_insn "*adddf3_fpr"
5560 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5561 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5562 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5563 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5564 && !VECTOR_UNIT_VSX_P (DFmode)"
5565 "fadd %0,%1,%2"
5566 [(set_attr "type" "fp")
5567 (set_attr "fp_type" "fp_addsub_d")])
5569 (define_expand "subdf3"
5570 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5571 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5572 (match_operand:DF 2 "gpc_reg_operand" "")))]
5573 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5574 "")
5576 (define_insn "*subdf3_fpr"
5577 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5578 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5579 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5580 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5581 && !VECTOR_UNIT_VSX_P (DFmode)"
5582 "fsub %0,%1,%2"
5583 [(set_attr "type" "fp")
5584 (set_attr "fp_type" "fp_addsub_d")])
5586 (define_expand "muldf3"
5587 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5588 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5589 (match_operand:DF 2 "gpc_reg_operand" "")))]
5590 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5591 "")
5593 (define_insn "*muldf3_fpr"
5594 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5595 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5596 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5597 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5598 && !VECTOR_UNIT_VSX_P (DFmode)"
5599 "fmul %0,%1,%2"
5600 [(set_attr "type" "dmul")
5601 (set_attr "fp_type" "fp_mul_d")])
5603 (define_expand "divdf3"
5604 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5605 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5606 (match_operand:DF 2 "gpc_reg_operand" "")))]
5607 "TARGET_HARD_FLOAT
5608 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5609 && !TARGET_SIMPLE_FPU"
5610 "")
5612 (define_insn "*divdf3_fpr"
5613 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5614 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5615 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5616 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
5617 && !VECTOR_UNIT_VSX_P (DFmode)"
5618 "fdiv %0,%1,%2"
5619 [(set_attr "type" "ddiv")])
5621 (define_insn "*fred_fpr"
5622 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5623 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5624 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
5625 "fre %0,%1"
5626 [(set_attr "type" "fp")])
5628 (define_insn "*rsqrtdf_internal1"
5629 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5630 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
5631 UNSPEC_RSQRT))]
5632 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
5633 "frsqrte %0,%1"
5634 [(set_attr "type" "fp")])
5636 ; builtin fma support
5637 (define_insn "*fmadf4_fpr"
5638 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5639 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5640 (match_operand:DF 2 "gpc_reg_operand" "f")
5641 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5642 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5643 && VECTOR_UNIT_NONE_P (DFmode)"
5644 "fmadd %0,%1,%2,%3"
5645 [(set_attr "type" "fp")
5646 (set_attr "fp_type" "fp_maddsub_d")])
5648 (define_insn "*fmsdf4_fpr"
5649 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5650 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5651 (match_operand:DF 2 "gpc_reg_operand" "f")
5652 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5654 && VECTOR_UNIT_NONE_P (DFmode)"
5655 "fmsub %0,%1,%2,%3"
5656 [(set_attr "type" "fp")
5657 (set_attr "fp_type" "fp_maddsub_d")])
5659 (define_insn "*nfmadf4_fpr"
5660 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5661 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5662 (match_operand:DF 2 "gpc_reg_operand" "f")
5663 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5664 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5665 && VECTOR_UNIT_NONE_P (DFmode)"
5666 "fnmadd %0,%1,%2,%3"
5667 [(set_attr "type" "fp")
5668 (set_attr "fp_type" "fp_maddsub_d")])
5670 (define_insn "*nfmsdf4_fpr"
5671 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5672 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5673 (match_operand:DF 2 "gpc_reg_operand" "f")
5674 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
5675 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5676 && VECTOR_UNIT_NONE_P (DFmode)"
5677 "fnmsub %0,%1,%2,%3"
5678 [(set_attr "type" "fp")
5679 (set_attr "fp_type" "fp_maddsub_d")])
5681 (define_expand "sqrtdf2"
5682 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5683 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5684 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5685 "")
5687 (define_insn "*sqrtdf2_fpr"
5688 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5689 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5690 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5691 && !VECTOR_UNIT_VSX_P (DFmode)"
5692 "fsqrt %0,%1"
5693 [(set_attr "type" "dsqrt")])
5695 ;; The conditional move instructions allow us to perform max and min
5696 ;; operations even when
5698 (define_expand "smaxdf3"
5699 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5700 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5701 (match_operand:DF 2 "gpc_reg_operand" ""))
5702 (match_dup 1)
5703 (match_dup 2)))]
5704 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5705 && !flag_trapping_math"
5706 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5708 (define_expand "smindf3"
5709 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5710 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5711 (match_operand:DF 2 "gpc_reg_operand" ""))
5712 (match_dup 2)
5713 (match_dup 1)))]
5714 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5715 && !flag_trapping_math"
5716 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5718 (define_split
5719 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5720 (match_operator:DF 3 "min_max_operator"
5721 [(match_operand:DF 1 "gpc_reg_operand" "")
5722 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5723 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5724 && !flag_trapping_math"
5725 [(const_int 0)]
5726 "
5727 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5728 operands[1], operands[2]);
5729 DONE;
5730 }")
5732 (define_expand "movdfcc"
5733 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5734 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5735 (match_operand:DF 2 "gpc_reg_operand" "")
5736 (match_operand:DF 3 "gpc_reg_operand" "")))]
5737 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5738 "
5739 {
5740 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5741 DONE;
5742 else
5743 FAIL;
5744 }")
5746 (define_insn "*fseldfdf4"
5747 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5748 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5749 (match_operand:DF 4 "zero_fp_constant" "F"))
5750 (match_operand:DF 2 "gpc_reg_operand" "d")
5751 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5752 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5753 "fsel %0,%1,%2,%3"
5754 [(set_attr "type" "fp")])
5756 (define_insn "*fselsfdf4"
5757 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5758 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5759 (match_operand:SF 4 "zero_fp_constant" "F"))
5760 (match_operand:DF 2 "gpc_reg_operand" "d")
5761 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5762 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5763 "fsel %0,%1,%2,%3"
5764 [(set_attr "type" "fp")])
5765 \f
5766 ;; Conversions to and from floating-point.
5768 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5769 ; don't want to support putting SImode in FPR registers.
5770 (define_insn "lfiwax"
5771 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5772 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5773 UNSPEC_LFIWAX))]
5774 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5775 "@
5776 lfiwax %0,%y1
5777 lxsiwax %x0,%y1
5778 mtvsrwa %x0,%1"
5779 [(set_attr "type" "fpload,fpload,mffgpr")])
5781 ; This split must be run before register allocation because it allocates the
5782 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5783 ; it earlier to allow for the combiner to merge insns together where it might
5784 ; not be needed and also in case the insns are deleted as dead code.
5786 (define_insn_and_split "floatsi<mode>2_lfiwax"
5787 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5788 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5789 (clobber (match_scratch:DI 2 "=d"))]
5790 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5791 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5792 "#"
5793 ""
5794 [(pc)]
5795 "
5796 {
5797 rtx dest = operands[0];
5798 rtx src = operands[1];
5799 rtx tmp;
5801 if (!MEM_P (src) && TARGET_POWERPC64
5802 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5803 tmp = convert_to_mode (DImode, src, false);
5804 else
5805 {
5806 tmp = operands[2];
5807 if (GET_CODE (tmp) == SCRATCH)
5808 tmp = gen_reg_rtx (DImode);
5809 if (MEM_P (src))
5810 {
5811 src = rs6000_address_for_fpconvert (src);
5812 emit_insn (gen_lfiwax (tmp, src));
5813 }
5814 else
5815 {
5816 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5817 emit_move_insn (stack, src);
5818 emit_insn (gen_lfiwax (tmp, stack));
5819 }
5820 }
5821 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5822 DONE;
5823 }"
5824 [(set_attr "length" "12")
5825 (set_attr "type" "fpload")])
5827 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5828 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5829 (float:SFDF
5830 (sign_extend:DI
5831 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5832 (clobber (match_scratch:DI 2 "=0,d"))]
5833 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5834 && <SI_CONVERT_FP>"
5835 "#"
5836 ""
5837 [(pc)]
5838 "
5839 {
5840 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5841 if (GET_CODE (operands[2]) == SCRATCH)
5842 operands[2] = gen_reg_rtx (DImode);
5843 emit_insn (gen_lfiwax (operands[2], operands[1]));
5844 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5845 DONE;
5846 }"
5847 [(set_attr "length" "8")
5848 (set_attr "type" "fpload")])
5850 (define_insn "lfiwzx"
5851 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5852 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5853 UNSPEC_LFIWZX))]
5854 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5855 "@
5856 lfiwzx %0,%y1
5857 lxsiwzx %x0,%y1
5858 mtvsrwz %x0,%1"
5859 [(set_attr "type" "fpload,fpload,mftgpr")])
5861 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5862 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5863 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5864 (clobber (match_scratch:DI 2 "=d"))]
5865 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5866 && <SI_CONVERT_FP>"
5867 "#"
5868 ""
5869 [(pc)]
5870 "
5871 {
5872 rtx dest = operands[0];
5873 rtx src = operands[1];
5874 rtx tmp;
5876 if (!MEM_P (src) && TARGET_POWERPC64
5877 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5878 tmp = convert_to_mode (DImode, src, true);
5879 else
5880 {
5881 tmp = operands[2];
5882 if (GET_CODE (tmp) == SCRATCH)
5883 tmp = gen_reg_rtx (DImode);
5884 if (MEM_P (src))
5885 {
5886 src = rs6000_address_for_fpconvert (src);
5887 emit_insn (gen_lfiwzx (tmp, src));
5888 }
5889 else
5890 {
5891 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5892 emit_move_insn (stack, src);
5893 emit_insn (gen_lfiwzx (tmp, stack));
5894 }
5895 }
5896 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5897 DONE;
5898 }"
5899 [(set_attr "length" "12")
5900 (set_attr "type" "fpload")])
5902 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5903 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5904 (unsigned_float:SFDF
5905 (zero_extend:DI
5906 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5907 (clobber (match_scratch:DI 2 "=0,d"))]
5908 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5909 && <SI_CONVERT_FP>"
5910 "#"
5911 ""
5912 [(pc)]
5913 "
5914 {
5915 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5916 if (GET_CODE (operands[2]) == SCRATCH)
5917 operands[2] = gen_reg_rtx (DImode);
5918 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5919 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5920 DONE;
5921 }"
5922 [(set_attr "length" "8")
5923 (set_attr "type" "fpload")])
5925 ; For each of these conversions, there is a define_expand, a define_insn
5926 ; with a '#' template, and a define_split (with C code). The idea is
5927 ; to allow constant folding with the template of the define_insn,
5928 ; then to have the insns split later (between sched1 and final).
5930 (define_expand "floatsidf2"
5931 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5932 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5933 (use (match_dup 2))
5934 (use (match_dup 3))
5935 (clobber (match_dup 4))
5936 (clobber (match_dup 5))
5937 (clobber (match_dup 6))])]
5938 "TARGET_HARD_FLOAT
5939 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5940 "
5941 {
5942 if (TARGET_E500_DOUBLE)
5943 {
5944 if (!REG_P (operands[1]))
5945 operands[1] = force_reg (SImode, operands[1]);
5946 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5947 DONE;
5948 }
5949 else if (TARGET_LFIWAX && TARGET_FCFID)
5950 {
5951 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5952 DONE;
5953 }
5954 else if (TARGET_FCFID)
5955 {
5956 rtx dreg = operands[1];
5957 if (!REG_P (dreg))
5958 dreg = force_reg (SImode, dreg);
5959 dreg = convert_to_mode (DImode, dreg, false);
5960 emit_insn (gen_floatdidf2 (operands[0], dreg));
5961 DONE;
5962 }
5964 if (!REG_P (operands[1]))
5965 operands[1] = force_reg (SImode, operands[1]);
5966 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5967 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5968 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5969 operands[5] = gen_reg_rtx (DFmode);
5970 operands[6] = gen_reg_rtx (SImode);
5971 }")
5973 (define_insn_and_split "*floatsidf2_internal"
5974 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5975 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5976 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5977 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5978 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5979 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5980 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5981 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5982 "#"
5983 ""
5984 [(pc)]
5985 "
5986 {
5987 rtx lowword, highword;
5988 gcc_assert (MEM_P (operands[4]));
5989 highword = adjust_address (operands[4], SImode, 0);
5990 lowword = adjust_address (operands[4], SImode, 4);
5991 if (! WORDS_BIG_ENDIAN)
5992 {
5993 rtx tmp;
5994 tmp = highword; highword = lowword; lowword = tmp;
5995 }
5997 emit_insn (gen_xorsi3 (operands[6], operands[1],
5998 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5999 emit_move_insn (lowword, operands[6]);
6000 emit_move_insn (highword, operands[2]);
6001 emit_move_insn (operands[5], operands[4]);
6002 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6003 DONE;
6004 }"
6005 [(set_attr "length" "24")
6006 (set_attr "type" "fp")])
6008 ;; If we don't have a direct conversion to single precision, don't enable this
6009 ;; conversion for 32-bit without fast math, because we don't have the insn to
6010 ;; generate the fixup swizzle to avoid double rounding problems.
6011 (define_expand "floatunssisf2"
6012 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6013 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6014 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6015 && (!TARGET_FPRS
6016 || (TARGET_FPRS
6017 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
6018 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6019 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6020 "
6021 {
6022 if (!TARGET_FPRS)
6023 {
6024 if (!REG_P (operands[1]))
6025 operands[1] = force_reg (SImode, operands[1]);
6026 }
6027 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
6028 {
6029 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
6030 DONE;
6031 }
6032 else
6033 {
6034 rtx dreg = operands[1];
6035 if (!REG_P (dreg))
6036 dreg = force_reg (SImode, dreg);
6037 dreg = convert_to_mode (DImode, dreg, true);
6038 emit_insn (gen_floatdisf2 (operands[0], dreg));
6039 DONE;
6040 }
6041 }")
6043 (define_expand "floatunssidf2"
6044 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6045 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6046 (use (match_dup 2))
6047 (use (match_dup 3))
6048 (clobber (match_dup 4))
6049 (clobber (match_dup 5))])]
6050 "TARGET_HARD_FLOAT
6051 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6052 "
6053 {
6054 if (TARGET_E500_DOUBLE)
6055 {
6056 if (!REG_P (operands[1]))
6057 operands[1] = force_reg (SImode, operands[1]);
6058 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6059 DONE;
6060 }
6061 else if (TARGET_LFIWZX && TARGET_FCFID)
6062 {
6063 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
6064 DONE;
6065 }
6066 else if (TARGET_FCFID)
6067 {
6068 rtx dreg = operands[1];
6069 if (!REG_P (dreg))
6070 dreg = force_reg (SImode, dreg);
6071 dreg = convert_to_mode (DImode, dreg, true);
6072 emit_insn (gen_floatdidf2 (operands[0], dreg));
6073 DONE;
6074 }
6076 if (!REG_P (operands[1]))
6077 operands[1] = force_reg (SImode, operands[1]);
6078 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6079 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6080 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6081 operands[5] = gen_reg_rtx (DFmode);
6082 }")
6084 (define_insn_and_split "*floatunssidf2_internal"
6085 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6086 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6087 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6088 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6089 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6090 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6091 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6092 && !(TARGET_FCFID && TARGET_POWERPC64)"
6093 "#"
6094 ""
6095 [(pc)]
6096 "
6097 {
6098 rtx lowword, highword;
6099 gcc_assert (MEM_P (operands[4]));
6100 highword = adjust_address (operands[4], SImode, 0);
6101 lowword = adjust_address (operands[4], SImode, 4);
6102 if (! WORDS_BIG_ENDIAN)
6103 {
6104 rtx tmp;
6105 tmp = highword; highword = lowword; lowword = tmp;
6106 }
6108 emit_move_insn (lowword, operands[1]);
6109 emit_move_insn (highword, operands[2]);
6110 emit_move_insn (operands[5], operands[4]);
6111 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6112 DONE;
6113 }"
6114 [(set_attr "length" "20")
6115 (set_attr "type" "fp")])
6117 (define_expand "fix_trunc<mode>si2"
6118 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6119 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6120 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
6121 "
6122 {
6123 if (!<E500_CONVERT>)
6124 {
6125 rtx tmp, stack;
6127 if (TARGET_STFIWX)
6128 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6129 else
6130 {
6131 tmp = gen_reg_rtx (DImode);
6132 stack = rs6000_allocate_stack_temp (DImode, true, false);
6133 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
6134 tmp, stack));
6135 }
6136 DONE;
6137 }
6138 }")
6140 ; Like the convert to float patterns, this insn must be split before
6141 ; register allocation so that it can allocate the memory slot if it
6142 ; needed
6143 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6144 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6145 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6146 (clobber (match_scratch:DI 2 "=d"))]
6147 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6148 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6149 && TARGET_STFIWX && can_create_pseudo_p ()"
6150 "#"
6151 ""
6152 [(pc)]
6153 {
6154 rtx dest = operands[0];
6155 rtx src = operands[1];
6156 rtx tmp = operands[2];
6158 if (GET_CODE (tmp) == SCRATCH)
6159 tmp = gen_reg_rtx (DImode);
6161 emit_insn (gen_fctiwz_<mode> (tmp, src));
6162 if (MEM_P (dest))
6163 {
6164 dest = rs6000_address_for_fpconvert (dest);
6165 emit_insn (gen_stfiwx (dest, tmp));
6166 DONE;
6167 }
6168 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6169 {
6170 dest = gen_lowpart (DImode, dest);
6171 emit_move_insn (dest, tmp);
6172 DONE;
6173 }
6174 else
6175 {
6176 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6177 emit_insn (gen_stfiwx (stack, tmp));
6178 emit_move_insn (dest, stack);
6179 DONE;
6180 }
6181 }
6182 [(set_attr "length" "12")
6183 (set_attr "type" "fp")])
6185 (define_insn_and_split "fix_trunc<mode>si2_internal"
6186 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6187 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6188 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6189 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6190 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6191 "#"
6192 ""
6193 [(pc)]
6194 "
6195 {
6196 rtx lowword;
6197 gcc_assert (MEM_P (operands[3]));
6198 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6200 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6201 emit_move_insn (operands[3], operands[2]);
6202 emit_move_insn (operands[0], lowword);
6203 DONE;
6204 }"
6205 [(set_attr "length" "16")
6206 (set_attr "type" "fp")])
6208 (define_expand "fix_trunc<mode>di2"
6209 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6210 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6211 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6212 && TARGET_FCFID"
6213 "")
6215 (define_insn "*fix_trunc<mode>di2_fctidz"
6216 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6217 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6218 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6219 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6220 "fctidz %0,%1"
6221 [(set_attr "type" "fp")])
6223 (define_expand "fixuns_trunc<mode>si2"
6224 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6225 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6226 "TARGET_HARD_FLOAT
6227 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6228 || <E500_CONVERT>)"
6229 "
6230 {
6231 if (!<E500_CONVERT>)
6232 {
6233 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6234 DONE;
6235 }
6236 }")
6238 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6239 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6240 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6241 (clobber (match_scratch:DI 2 "=d"))]
6242 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6243 && TARGET_STFIWX && can_create_pseudo_p ()"
6244 "#"
6245 ""
6246 [(pc)]
6247 {
6248 rtx dest = operands[0];
6249 rtx src = operands[1];
6250 rtx tmp = operands[2];
6252 if (GET_CODE (tmp) == SCRATCH)
6253 tmp = gen_reg_rtx (DImode);
6255 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6256 if (MEM_P (dest))
6257 {
6258 dest = rs6000_address_for_fpconvert (dest);
6259 emit_insn (gen_stfiwx (dest, tmp));
6260 DONE;
6261 }
6262 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6263 {
6264 dest = gen_lowpart (DImode, dest);
6265 emit_move_insn (dest, tmp);
6266 DONE;
6267 }
6268 else
6269 {
6270 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6271 emit_insn (gen_stfiwx (stack, tmp));
6272 emit_move_insn (dest, stack);
6273 DONE;
6274 }
6275 }
6276 [(set_attr "length" "12")
6277 (set_attr "type" "fp")])
6279 (define_expand "fixuns_trunc<mode>di2"
6280 [(set (match_operand:DI 0 "register_operand" "")
6281 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6282 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6283 "")
6285 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6286 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6287 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6288 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6289 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6290 "fctiduz %0,%1"
6291 [(set_attr "type" "fp")])
6293 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6294 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6295 ; because the first makes it clear that operand 0 is not live
6296 ; before the instruction.
6297 (define_insn "fctiwz_<mode>"
6298 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6299 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6300 UNSPEC_FCTIWZ))]
6301 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6302 "fctiwz %0,%1"
6303 [(set_attr "type" "fp")])
6305 (define_insn "fctiwuz_<mode>"
6306 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6307 (unspec:DI [(unsigned_fix:SI
6308 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6309 UNSPEC_FCTIWUZ))]
6310 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6311 "fctiwuz %0,%1"
6312 [(set_attr "type" "fp")])
6314 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6315 ;; since the friz instruction does not truncate the value if the floating
6316 ;; point value is < LONG_MIN or > LONG_MAX.
6317 (define_insn "*friz"
6318 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6319 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6320 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6321 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6322 && !flag_trapping_math && TARGET_FRIZ"
6323 "friz %0,%1"
6324 [(set_attr "type" "fp")])
6326 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6327 ;; load to properly sign extend the value, but at least doing a store, load
6328 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6329 ;; if we have 32-bit memory ops
6330 (define_insn_and_split "*round32<mode>2_fprs"
6331 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6332 (float:SFDF
6333 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6334 (clobber (match_scratch:DI 2 "=d"))
6335 (clobber (match_scratch:DI 3 "=d"))]
6336 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6337 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6338 && can_create_pseudo_p ()"
6339 "#"
6340 ""
6341 [(pc)]
6342 {
6343 rtx dest = operands[0];
6344 rtx src = operands[1];
6345 rtx tmp1 = operands[2];
6346 rtx tmp2 = operands[3];
6347 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6349 if (GET_CODE (tmp1) == SCRATCH)
6350 tmp1 = gen_reg_rtx (DImode);
6351 if (GET_CODE (tmp2) == SCRATCH)
6352 tmp2 = gen_reg_rtx (DImode);
6354 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6355 emit_insn (gen_stfiwx (stack, tmp1));
6356 emit_insn (gen_lfiwax (tmp2, stack));
6357 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6358 DONE;
6359 }
6360 [(set_attr "type" "fpload")
6361 (set_attr "length" "16")])
6363 (define_insn_and_split "*roundu32<mode>2_fprs"
6364 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6365 (unsigned_float:SFDF
6366 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6367 (clobber (match_scratch:DI 2 "=d"))
6368 (clobber (match_scratch:DI 3 "=d"))]
6369 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6370 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6371 && can_create_pseudo_p ()"
6372 "#"
6373 ""
6374 [(pc)]
6375 {
6376 rtx dest = operands[0];
6377 rtx src = operands[1];
6378 rtx tmp1 = operands[2];
6379 rtx tmp2 = operands[3];
6380 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6382 if (GET_CODE (tmp1) == SCRATCH)
6383 tmp1 = gen_reg_rtx (DImode);
6384 if (GET_CODE (tmp2) == SCRATCH)
6385 tmp2 = gen_reg_rtx (DImode);
6387 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6388 emit_insn (gen_stfiwx (stack, tmp1));
6389 emit_insn (gen_lfiwzx (tmp2, stack));
6390 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6391 DONE;
6392 }
6393 [(set_attr "type" "fpload")
6394 (set_attr "length" "16")])
6396 ;; No VSX equivalent to fctid
6397 (define_insn "lrint<mode>di2"
6398 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6399 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6400 UNSPEC_FCTID))]
6401 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6402 "fctid %0,%1"
6403 [(set_attr "type" "fp")])
6405 (define_expand "btrunc<mode>2"
6406 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6407 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6408 UNSPEC_FRIZ))]
6409 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6410 "")
6412 (define_insn "*btrunc<mode>2_fpr"
6413 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6414 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6415 UNSPEC_FRIZ))]
6416 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6417 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6418 "friz %0,%1"
6419 [(set_attr "type" "fp")])
6421 (define_expand "ceil<mode>2"
6422 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6423 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6424 UNSPEC_FRIP))]
6425 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6426 "")
6428 (define_insn "*ceil<mode>2_fpr"
6429 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6430 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6431 UNSPEC_FRIP))]
6432 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6433 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6434 "frip %0,%1"
6435 [(set_attr "type" "fp")])
6437 (define_expand "floor<mode>2"
6438 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6439 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6440 UNSPEC_FRIM))]
6441 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6442 "")
6444 (define_insn "*floor<mode>2_fpr"
6445 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6446 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6447 UNSPEC_FRIM))]
6448 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6449 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6450 "frim %0,%1"
6451 [(set_attr "type" "fp")])
6453 ;; No VSX equivalent to frin
6454 (define_insn "round<mode>2"
6455 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6456 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6457 UNSPEC_FRIN))]
6458 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6459 "frin %0,%1"
6460 [(set_attr "type" "fp")])
6462 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6463 (define_insn "stfiwx"
6464 [(set (match_operand:SI 0 "memory_operand" "=Z")
6465 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6466 UNSPEC_STFIWX))]
6467 "TARGET_PPC_GFXOPT"
6468 "stfiwx %1,%y0"
6469 [(set_attr "type" "fpstore")])
6471 ;; If we don't have a direct conversion to single precision, don't enable this
6472 ;; conversion for 32-bit without fast math, because we don't have the insn to
6473 ;; generate the fixup swizzle to avoid double rounding problems.
6474 (define_expand "floatsisf2"
6475 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6476 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6477 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6478 && (!TARGET_FPRS
6479 || (TARGET_FPRS
6480 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6481 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6482 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6483 "
6484 {
6485 if (!TARGET_FPRS)
6486 {
6487 if (!REG_P (operands[1]))
6488 operands[1] = force_reg (SImode, operands[1]);
6489 }
6490 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6491 {
6492 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6493 DONE;
6494 }
6495 else if (TARGET_FCFID && TARGET_LFIWAX)
6496 {
6497 rtx dfreg = gen_reg_rtx (DFmode);
6498 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6499 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6500 DONE;
6501 }
6502 else
6503 {
6504 rtx dreg = operands[1];
6505 if (!REG_P (dreg))
6506 dreg = force_reg (SImode, dreg);
6507 dreg = convert_to_mode (DImode, dreg, false);
6508 emit_insn (gen_floatdisf2 (operands[0], dreg));
6509 DONE;
6510 }
6511 }")
6513 (define_expand "floatdidf2"
6514 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6515 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6516 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6517 "")
6519 (define_insn "*floatdidf2_fpr"
6520 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6521 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6522 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6523 && !VECTOR_UNIT_VSX_P (DFmode)"
6524 "fcfid %0,%1"
6525 [(set_attr "type" "fp")])
6527 ; Allow the combiner to merge source memory operands to the conversion so that
6528 ; the optimizer/register allocator doesn't try to load the value too early in a
6529 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6530 ; hit. We will split after reload to avoid the trip through the GPRs
6532 (define_insn_and_split "*floatdidf2_mem"
6533 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6534 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6535 (clobber (match_scratch:DI 2 "=d"))]
6536 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6537 "#"
6538 "&& reload_completed"
6539 [(set (match_dup 2) (match_dup 1))
6540 (set (match_dup 0) (float:DF (match_dup 2)))]
6541 ""
6542 [(set_attr "length" "8")
6543 (set_attr "type" "fpload")])
6545 (define_expand "floatunsdidf2"
6546 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6547 (unsigned_float:DF
6548 (match_operand:DI 1 "gpc_reg_operand" "")))]
6549 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6550 "")
6552 (define_insn "*floatunsdidf2_fcfidu"
6553 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6554 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6555 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6556 "fcfidu %0,%1"
6557 [(set_attr "type" "fp")
6558 (set_attr "length" "4")])
6560 (define_insn_and_split "*floatunsdidf2_mem"
6561 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6562 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6563 (clobber (match_scratch:DI 2 "=d"))]
6564 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6565 "#"
6566 "&& reload_completed"
6567 [(set (match_dup 2) (match_dup 1))
6568 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6569 ""
6570 [(set_attr "length" "8")
6571 (set_attr "type" "fpload")])
6573 (define_expand "floatdisf2"
6574 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6575 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6576 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6577 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6578 "
6579 {
6580 if (!TARGET_FCFIDS)
6581 {
6582 rtx val = operands[1];
6583 if (!flag_unsafe_math_optimizations)
6584 {
6585 rtx label = gen_label_rtx ();
6586 val = gen_reg_rtx (DImode);
6587 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6588 emit_label (label);
6589 }
6590 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6591 DONE;
6592 }
6593 }")
6595 (define_insn "floatdisf2_fcfids"
6596 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6597 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6598 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6599 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6600 "fcfids %0,%1"
6601 [(set_attr "type" "fp")])
6603 (define_insn_and_split "*floatdisf2_mem"
6604 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6605 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6606 (clobber (match_scratch:DI 2 "=f"))]
6607 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6608 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6609 "#"
6610 "&& reload_completed"
6611 [(pc)]
6612 "
6613 {
6614 emit_move_insn (operands[2], operands[1]);
6615 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6616 DONE;
6617 }"
6618 [(set_attr "length" "8")])
6620 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6621 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6622 ;; from double rounding.
6623 ;; Instead of creating a new cpu type for two FP operations, just use fp
6624 (define_insn_and_split "floatdisf2_internal1"
6625 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6626 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6627 (clobber (match_scratch:DF 2 "=d"))]
6628 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6629 "#"
6630 "&& reload_completed"
6631 [(set (match_dup 2)
6632 (float:DF (match_dup 1)))
6633 (set (match_dup 0)
6634 (float_truncate:SF (match_dup 2)))]
6635 ""
6636 [(set_attr "length" "8")
6637 (set_attr "type" "fp")])
6639 ;; Twiddles bits to avoid double rounding.
6640 ;; Bits that might be truncated when converting to DFmode are replaced
6641 ;; by a bit that won't be lost at that stage, but is below the SFmode
6642 ;; rounding position.
6643 (define_expand "floatdisf2_internal2"
6644 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6645 (const_int 53)))
6646 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6647 (const_int 2047)))
6648 (clobber (scratch:CC))])
6649 (set (match_dup 3) (plus:DI (match_dup 3)
6650 (const_int 1)))
6651 (set (match_dup 0) (plus:DI (match_dup 0)
6652 (const_int 2047)))
6653 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6654 (const_int 2)))
6655 (set (match_dup 0) (ior:DI (match_dup 0)
6656 (match_dup 1)))
6657 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6658 (const_int -2048)))
6659 (clobber (scratch:CC))])
6660 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6661 (label_ref (match_operand:DI 2 "" ""))
6662 (pc)))
6663 (set (match_dup 0) (match_dup 1))]
6664 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6665 "
6666 {
6667 operands[3] = gen_reg_rtx (DImode);
6668 operands[4] = gen_reg_rtx (CCUNSmode);
6669 }")
6671 (define_expand "floatunsdisf2"
6672 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6673 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6674 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6675 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6676 "")
6678 (define_insn "floatunsdisf2_fcfidus"
6679 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6680 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6681 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6682 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6683 "fcfidus %0,%1"
6684 [(set_attr "type" "fp")])
6686 (define_insn_and_split "*floatunsdisf2_mem"
6687 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6688 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6689 (clobber (match_scratch:DI 2 "=f"))]
6690 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6691 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6692 "#"
6693 "&& reload_completed"
6694 [(pc)]
6695 "
6696 {
6697 emit_move_insn (operands[2], operands[1]);
6698 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6699 DONE;
6700 }"
6701 [(set_attr "length" "8")
6702 (set_attr "type" "fpload")])
6703 \f
6704 ;; Define the DImode operations that can be done in a small number
6705 ;; of instructions. The & constraints are to prevent the register
6706 ;; allocator from allocating registers that overlap with the inputs
6707 ;; (for example, having an input in 7,8 and an output in 6,7). We
6708 ;; also allow for the output being the same as one of the inputs.
6710 (define_insn "*adddi3_noppc64"
6711 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6712 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6713 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6714 "! TARGET_POWERPC64"
6715 "*
6716 {
6717 if (WORDS_BIG_ENDIAN)
6718 return (GET_CODE (operands[2])) != CONST_INT
6719 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6720 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6721 else
6722 return (GET_CODE (operands[2])) != CONST_INT
6723 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6724 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6725 }"
6726 [(set_attr "type" "two")
6727 (set_attr "length" "8")])
6729 (define_insn "*subdi3_noppc64"
6730 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6731 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6732 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6733 "! TARGET_POWERPC64"
6734 "*
6735 {
6736 if (WORDS_BIG_ENDIAN)
6737 return (GET_CODE (operands[1]) != CONST_INT)
6738 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6739 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6740 else
6741 return (GET_CODE (operands[1]) != CONST_INT)
6742 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6743 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6744 }"
6745 [(set_attr "type" "two")
6746 (set_attr "length" "8")])
6748 (define_insn "*negdi2_noppc64"
6749 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6750 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6751 "! TARGET_POWERPC64"
6752 "*
6753 {
6754 return (WORDS_BIG_ENDIAN)
6755 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6756 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6757 }"
6758 [(set_attr "type" "two")
6759 (set_attr "length" "8")])
6761 (define_insn "mulsidi3"
6762 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6763 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6764 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6765 "! TARGET_POWERPC64"
6766 {
6767 return (WORDS_BIG_ENDIAN)
6768 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6769 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6770 }
6771 [(set_attr "type" "imul")
6772 (set_attr "length" "8")])
6774 (define_split
6775 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6776 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6777 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6778 "! TARGET_POWERPC64 && reload_completed"
6779 [(set (match_dup 3)
6780 (truncate:SI
6781 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6782 (sign_extend:DI (match_dup 2)))
6783 (const_int 32))))
6784 (set (match_dup 4)
6785 (mult:SI (match_dup 1)
6786 (match_dup 2)))]
6787 "
6788 {
6789 int endian = (WORDS_BIG_ENDIAN == 0);
6790 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6791 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6792 }")
6794 (define_insn "umulsidi3"
6795 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6796 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6797 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6798 "! TARGET_POWERPC64"
6799 "*
6800 {
6801 return (WORDS_BIG_ENDIAN)
6802 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6803 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6804 }"
6805 [(set_attr "type" "imul")
6806 (set_attr "length" "8")])
6808 (define_split
6809 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6810 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6811 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6812 "! TARGET_POWERPC64 && reload_completed"
6813 [(set (match_dup 3)
6814 (truncate:SI
6815 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6816 (zero_extend:DI (match_dup 2)))
6817 (const_int 32))))
6818 (set (match_dup 4)
6819 (mult:SI (match_dup 1)
6820 (match_dup 2)))]
6821 "
6822 {
6823 int endian = (WORDS_BIG_ENDIAN == 0);
6824 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6825 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6826 }")
6828 (define_insn "smulsi3_highpart"
6829 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6830 (truncate:SI
6831 (lshiftrt:DI (mult:DI (sign_extend:DI
6832 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6833 (sign_extend:DI
6834 (match_operand:SI 2 "gpc_reg_operand" "r")))
6835 (const_int 32))))]
6836 ""
6837 "mulhw %0,%1,%2"
6838 [(set_attr "type" "imul")])
6840 (define_insn "umulsi3_highpart"
6841 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6842 (truncate:SI
6843 (lshiftrt:DI (mult:DI (zero_extend:DI
6844 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6845 (zero_extend:DI
6846 (match_operand:SI 2 "gpc_reg_operand" "r")))
6847 (const_int 32))))]
6848 ""
6849 "mulhwu %0,%1,%2"
6850 [(set_attr "type" "imul")])
6852 ;; Shift by a variable amount is too complex to be worth open-coding. We
6853 ;; just handle shifts by constants.
6854 (define_insn "ashrdi3_no_power"
6855 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6856 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6857 (match_operand:SI 2 "const_int_operand" "M,i")))]
6858 "!TARGET_POWERPC64"
6859 "*
6860 {
6861 switch (which_alternative)
6862 {
6863 default:
6864 gcc_unreachable ();
6865 case 0:
6866 if (WORDS_BIG_ENDIAN)
6867 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6868 else
6869 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6870 case 1:
6871 if (WORDS_BIG_ENDIAN)
6872 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6873 else
6874 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6875 }
6876 }"
6877 [(set_attr "type" "two,three")
6878 (set_attr "length" "8,12")])
6880 (define_insn "*ashrdisi3_noppc64be"
6881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6882 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6883 (const_int 32)) 4))]
6884 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6885 "*
6886 {
6887 if (REGNO (operands[0]) == REGNO (operands[1]))
6888 return \"\";
6889 else
6890 return \"mr %0,%1\";
6891 }"
6892 [(set_attr "length" "4")])
6894 \f
6895 ;; PowerPC64 DImode operations.
6897 (define_insn "muldi3"
6898 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6899 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6900 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6901 "TARGET_POWERPC64"
6902 "@
6903 mulld %0,%1,%2
6904 mulli %0,%1,%2"
6905 [(set (attr "type")
6906 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6907 (const_string "imul3")
6908 (match_operand:SI 2 "short_cint_operand" "")
6909 (const_string "imul2")]
6910 (const_string "lmul")))])
6912 (define_insn "*muldi3_internal1"
6913 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6914 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6915 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6916 (const_int 0)))
6917 (clobber (match_scratch:DI 3 "=r,r"))]
6918 "TARGET_POWERPC64"
6919 "@
6920 mulld. %3,%1,%2
6921 #"
6922 [(set_attr "type" "lmul_compare")
6923 (set_attr "length" "4,8")])
6925 (define_split
6926 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6927 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6928 (match_operand:DI 2 "gpc_reg_operand" ""))
6929 (const_int 0)))
6930 (clobber (match_scratch:DI 3 ""))]
6931 "TARGET_POWERPC64 && reload_completed"
6932 [(set (match_dup 3)
6933 (mult:DI (match_dup 1) (match_dup 2)))
6934 (set (match_dup 0)
6935 (compare:CC (match_dup 3)
6936 (const_int 0)))]
6937 "")
6939 (define_insn "*muldi3_internal2"
6940 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6941 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6942 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6943 (const_int 0)))
6944 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6945 (mult:DI (match_dup 1) (match_dup 2)))]
6946 "TARGET_POWERPC64"
6947 "@
6948 mulld. %0,%1,%2
6949 #"
6950 [(set_attr "type" "lmul_compare")
6951 (set_attr "length" "4,8")])
6953 (define_split
6954 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6955 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6956 (match_operand:DI 2 "gpc_reg_operand" ""))
6957 (const_int 0)))
6958 (set (match_operand:DI 0 "gpc_reg_operand" "")
6959 (mult:DI (match_dup 1) (match_dup 2)))]
6960 "TARGET_POWERPC64 && reload_completed"
6961 [(set (match_dup 0)
6962 (mult:DI (match_dup 1) (match_dup 2)))
6963 (set (match_dup 3)
6964 (compare:CC (match_dup 0)
6965 (const_int 0)))]
6966 "")
6968 (define_insn "smuldi3_highpart"
6969 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6970 (truncate:DI
6971 (lshiftrt:TI (mult:TI (sign_extend:TI
6972 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6973 (sign_extend:TI
6974 (match_operand:DI 2 "gpc_reg_operand" "r")))
6975 (const_int 64))))]
6976 "TARGET_POWERPC64"
6977 "mulhd %0,%1,%2"
6978 [(set_attr "type" "lmul")])
6980 (define_insn "umuldi3_highpart"
6981 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6982 (truncate:DI
6983 (lshiftrt:TI (mult:TI (zero_extend:TI
6984 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6985 (zero_extend:TI
6986 (match_operand:DI 2 "gpc_reg_operand" "r")))
6987 (const_int 64))))]
6988 "TARGET_POWERPC64"
6989 "mulhdu %0,%1,%2"
6990 [(set_attr "type" "lmul")])
6992 (define_expand "mulditi3"
6993 [(set (match_operand:TI 0 "gpc_reg_operand")
6994 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6995 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6996 "TARGET_POWERPC64"
6997 {
6998 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6999 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
7000 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
7001 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
7002 emit_move_insn (gen_highpart (DImode, operands[0]), h);
7003 DONE;
7004 })
7006 (define_expand "umulditi3"
7007 [(set (match_operand:TI 0 "gpc_reg_operand")
7008 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
7009 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
7010 "TARGET_POWERPC64"
7011 {
7012 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
7013 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
7014 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
7015 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
7016 emit_move_insn (gen_highpart (DImode, operands[0]), h);
7017 DONE;
7018 })
7020 (define_insn "rotldi3"
7021 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7022 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7023 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7024 "TARGET_POWERPC64"
7025 "@
7026 rldcl %0,%1,%2,0
7027 rldicl %0,%1,%H2,0"
7028 [(set_attr "type" "var_shift_rotate,integer")])
7030 (define_insn "*rotldi3_internal2"
7031 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7032 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7033 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7034 (const_int 0)))
7035 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7036 "TARGET_64BIT"
7037 "@
7038 rldcl. %3,%1,%2,0
7039 rldicl. %3,%1,%H2,0
7040 #
7041 #"
7042 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7043 (set_attr "length" "4,4,8,8")])
7045 (define_split
7046 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7047 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7048 (match_operand:DI 2 "reg_or_cint_operand" ""))
7049 (const_int 0)))
7050 (clobber (match_scratch:DI 3 ""))]
7051 "TARGET_POWERPC64 && reload_completed"
7052 [(set (match_dup 3)
7053 (rotate:DI (match_dup 1) (match_dup 2)))
7054 (set (match_dup 0)
7055 (compare:CC (match_dup 3)
7056 (const_int 0)))]
7057 "")
7059 (define_insn "*rotldi3_internal3"
7060 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7061 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7062 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7063 (const_int 0)))
7064 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7065 (rotate:DI (match_dup 1) (match_dup 2)))]
7066 "TARGET_64BIT"
7067 "@
7068 rldcl. %0,%1,%2,0
7069 rldicl. %0,%1,%H2,0
7070 #
7071 #"
7072 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7073 (set_attr "length" "4,4,8,8")])
7075 (define_split
7076 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7077 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7078 (match_operand:DI 2 "reg_or_cint_operand" ""))
7079 (const_int 0)))
7080 (set (match_operand:DI 0 "gpc_reg_operand" "")
7081 (rotate:DI (match_dup 1) (match_dup 2)))]
7082 "TARGET_POWERPC64 && reload_completed"
7083 [(set (match_dup 0)
7084 (rotate:DI (match_dup 1) (match_dup 2)))
7085 (set (match_dup 3)
7086 (compare:CC (match_dup 0)
7087 (const_int 0)))]
7088 "")
7090 (define_insn "*rotldi3_internal4"
7091 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7092 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7093 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7094 (match_operand:DI 3 "mask64_operand" "n,n")))]
7095 "TARGET_POWERPC64"
7096 "@
7097 rldc%B3 %0,%1,%2,%S3
7098 rldic%B3 %0,%1,%H2,%S3"
7099 [(set_attr "type" "var_shift_rotate,integer")])
7101 (define_insn "*rotldi3_internal5"
7102 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7103 (compare:CC (and:DI
7104 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7105 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7106 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7107 (const_int 0)))
7108 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7109 "TARGET_64BIT"
7110 "@
7111 rldc%B3. %4,%1,%2,%S3
7112 rldic%B3. %4,%1,%H2,%S3
7113 #
7114 #"
7115 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7116 (set_attr "length" "4,4,8,8")])
7118 (define_split
7119 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7120 (compare:CC (and:DI
7121 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7122 (match_operand:DI 2 "reg_or_cint_operand" ""))
7123 (match_operand:DI 3 "mask64_operand" ""))
7124 (const_int 0)))
7125 (clobber (match_scratch:DI 4 ""))]
7126 "TARGET_POWERPC64 && reload_completed"
7127 [(set (match_dup 4)
7128 (and:DI (rotate:DI (match_dup 1)
7129 (match_dup 2))
7130 (match_dup 3)))
7131 (set (match_dup 0)
7132 (compare:CC (match_dup 4)
7133 (const_int 0)))]
7134 "")
7136 (define_insn "*rotldi3_internal6"
7137 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7138 (compare:CC (and:DI
7139 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7140 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7141 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7142 (const_int 0)))
7143 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7144 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7145 "TARGET_64BIT"
7146 "@
7147 rldc%B3. %0,%1,%2,%S3
7148 rldic%B3. %0,%1,%H2,%S3
7149 #
7150 #"
7151 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7152 (set_attr "length" "4,4,8,8")])
7154 (define_split
7155 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7156 (compare:CC (and:DI
7157 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7158 (match_operand:DI 2 "reg_or_cint_operand" ""))
7159 (match_operand:DI 3 "mask64_operand" ""))
7160 (const_int 0)))
7161 (set (match_operand:DI 0 "gpc_reg_operand" "")
7162 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7163 "TARGET_POWERPC64 && reload_completed"
7164 [(set (match_dup 0)
7165 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7166 (set (match_dup 4)
7167 (compare:CC (match_dup 0)
7168 (const_int 0)))]
7169 "")
7171 (define_insn "*rotldi3_internal7le"
7172 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7173 (zero_extend:DI
7174 (subreg:QI
7175 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7176 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7177 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7178 "@
7179 rldcl %0,%1,%2,56
7180 rldicl %0,%1,%H2,56"
7181 [(set_attr "type" "var_shift_rotate,integer")])
7183 (define_insn "*rotldi3_internal7be"
7184 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7185 (zero_extend:DI
7186 (subreg:QI
7187 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7188 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]
7189 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7190 "@
7191 rldcl %0,%1,%2,56
7192 rldicl %0,%1,%H2,56"
7193 [(set_attr "type" "var_shift_rotate,integer")])
7195 (define_insn "*rotldi3_internal8le"
7196 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7197 (compare:CC (zero_extend:DI
7198 (subreg:QI
7199 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7200 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7201 (const_int 0)))
7202 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7203 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7204 "@
7205 rldcl. %3,%1,%2,56
7206 rldicl. %3,%1,%H2,56
7207 #
7208 #"
7209 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7210 (set_attr "length" "4,4,8,8")])
7212 (define_insn "*rotldi3_internal8be"
7213 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7214 (compare:CC (zero_extend:DI
7215 (subreg:QI
7216 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7217 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7218 (const_int 0)))
7219 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7220 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7221 "@
7222 rldcl. %3,%1,%2,56
7223 rldicl. %3,%1,%H2,56
7224 #
7225 #"
7226 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7227 (set_attr "length" "4,4,8,8")])
7229 (define_split
7230 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7231 (compare:CC (zero_extend:DI
7232 (subreg:QI
7233 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7234 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7235 (const_int 0)))
7236 (clobber (match_scratch:DI 3 ""))]
7237 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7238 [(set (match_dup 3)
7239 (zero_extend:DI (subreg:QI
7240 (rotate:DI (match_dup 1)
7241 (match_dup 2)) 0)))
7242 (set (match_dup 0)
7243 (compare:CC (match_dup 3)
7244 (const_int 0)))]
7245 "")
7247 (define_split
7248 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7249 (compare:CC (zero_extend:DI
7250 (subreg:QI
7251 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7252 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7253 (const_int 0)))
7254 (clobber (match_scratch:DI 3 ""))]
7255 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7256 [(set (match_dup 3)
7257 (zero_extend:DI (subreg:QI
7258 (rotate:DI (match_dup 1)
7259 (match_dup 2)) 7)))
7260 (set (match_dup 0)
7261 (compare:CC (match_dup 3)
7262 (const_int 0)))]
7263 "")
7265 (define_insn "*rotldi3_internal9le"
7266 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7267 (compare:CC (zero_extend:DI
7268 (subreg:QI
7269 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7270 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7271 (const_int 0)))
7272 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7273 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7274 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7275 "@
7276 rldcl. %0,%1,%2,56
7277 rldicl. %0,%1,%H2,56
7278 #
7279 #"
7280 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7281 (set_attr "length" "4,4,8,8")])
7283 (define_insn "*rotldi3_internal9be"
7284 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7285 (compare:CC (zero_extend:DI
7286 (subreg:QI
7287 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7288 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7289 (const_int 0)))
7290 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7291 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7292 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7293 "@
7294 rldcl. %0,%1,%2,56
7295 rldicl. %0,%1,%H2,56
7296 #
7297 #"
7298 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7299 (set_attr "length" "4,4,8,8")])
7301 (define_split
7302 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7303 (compare:CC (zero_extend:DI
7304 (subreg:QI
7305 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7306 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7307 (const_int 0)))
7308 (set (match_operand:DI 0 "gpc_reg_operand" "")
7309 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7310 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7311 [(set (match_dup 0)
7312 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7313 (set (match_dup 3)
7314 (compare:CC (match_dup 0)
7315 (const_int 0)))]
7316 "")
7318 (define_split
7319 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7320 (compare:CC (zero_extend:DI
7321 (subreg:QI
7322 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7323 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7324 (const_int 0)))
7325 (set (match_operand:DI 0 "gpc_reg_operand" "")
7326 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7327 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7328 [(set (match_dup 0)
7329 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
7330 (set (match_dup 3)
7331 (compare:CC (match_dup 0)
7332 (const_int 0)))]
7333 "")
7335 (define_insn "*rotldi3_internal10le"
7336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7337 (zero_extend:DI
7338 (subreg:HI
7339 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7340 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7341 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7342 "@
7343 rldcl %0,%1,%2,48
7344 rldicl %0,%1,%H2,48"
7345 [(set_attr "type" "var_shift_rotate,integer")])
7347 (define_insn "*rotldi3_internal10be"
7348 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7349 (zero_extend:DI
7350 (subreg:HI
7351 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7352 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]
7353 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7354 "@
7355 rldcl %0,%1,%2,48
7356 rldicl %0,%1,%H2,48"
7357 [(set_attr "type" "var_shift_rotate,integer")])
7359 (define_insn "*rotldi3_internal11le"
7360 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7361 (compare:CC (zero_extend:DI
7362 (subreg:HI
7363 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7364 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7365 (const_int 0)))
7366 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7367 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7368 "@
7369 rldcl. %3,%1,%2,48
7370 rldicl. %3,%1,%H2,48
7371 #
7372 #"
7373 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7374 (set_attr "length" "4,4,8,8")])
7376 (define_insn "*rotldi3_internal11be"
7377 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7378 (compare:CC (zero_extend:DI
7379 (subreg:HI
7380 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7381 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7382 (const_int 0)))
7383 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7384 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7385 "@
7386 rldcl. %3,%1,%2,48
7387 rldicl. %3,%1,%H2,48
7388 #
7389 #"
7390 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7391 (set_attr "length" "4,4,8,8")])
7393 (define_split
7394 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7395 (compare:CC (zero_extend:DI
7396 (subreg:HI
7397 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7398 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7399 (const_int 0)))
7400 (clobber (match_scratch:DI 3 ""))]
7401 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7402 [(set (match_dup 3)
7403 (zero_extend:DI (subreg:HI
7404 (rotate:DI (match_dup 1)
7405 (match_dup 2)) 0)))
7406 (set (match_dup 0)
7407 (compare:CC (match_dup 3)
7408 (const_int 0)))]
7409 "")
7411 (define_split
7412 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7413 (compare:CC (zero_extend:DI
7414 (subreg:HI
7415 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7416 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7417 (const_int 0)))
7418 (clobber (match_scratch:DI 3 ""))]
7419 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7420 [(set (match_dup 3)
7421 (zero_extend:DI (subreg:HI
7422 (rotate:DI (match_dup 1)
7423 (match_dup 2)) 6)))
7424 (set (match_dup 0)
7425 (compare:CC (match_dup 3)
7426 (const_int 0)))]
7427 "")
7429 (define_insn "*rotldi3_internal12le"
7430 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7431 (compare:CC (zero_extend:DI
7432 (subreg:HI
7433 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7434 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7435 (const_int 0)))
7436 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7437 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7438 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7439 "@
7440 rldcl. %0,%1,%2,48
7441 rldicl. %0,%1,%H2,48
7442 #
7443 #"
7444 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7445 (set_attr "length" "4,4,8,8")])
7447 (define_insn "*rotldi3_internal12be"
7448 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7449 (compare:CC (zero_extend:DI
7450 (subreg:HI
7451 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7452 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7453 (const_int 0)))
7454 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7455 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7456 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7457 "@
7458 rldcl. %0,%1,%2,48
7459 rldicl. %0,%1,%H2,48
7460 #
7461 #"
7462 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7463 (set_attr "length" "4,4,8,8")])
7465 (define_split
7466 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7467 (compare:CC (zero_extend:DI
7468 (subreg:HI
7469 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7470 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7471 (const_int 0)))
7472 (set (match_operand:DI 0 "gpc_reg_operand" "")
7473 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7474 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7475 [(set (match_dup 0)
7476 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7477 (set (match_dup 3)
7478 (compare:CC (match_dup 0)
7479 (const_int 0)))]
7480 "")
7482 (define_split
7483 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7484 (compare:CC (zero_extend:DI
7485 (subreg:HI
7486 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7487 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7488 (const_int 0)))
7489 (set (match_operand:DI 0 "gpc_reg_operand" "")
7490 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7491 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7492 [(set (match_dup 0)
7493 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7494 (set (match_dup 3)
7495 (compare:CC (match_dup 0)
7496 (const_int 0)))]
7497 "")
7499 (define_insn "*rotldi3_internal13le"
7500 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7501 (zero_extend:DI
7502 (subreg:SI
7503 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7504 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7505 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7506 "@
7507 rldcl %0,%1,%2,32
7508 rldicl %0,%1,%H2,32"
7509 [(set_attr "type" "var_shift_rotate,integer")])
7511 (define_insn "*rotldi3_internal13be"
7512 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7513 (zero_extend:DI
7514 (subreg:SI
7515 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7516 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]
7517 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7518 "@
7519 rldcl %0,%1,%2,32
7520 rldicl %0,%1,%H2,32"
7521 [(set_attr "type" "var_shift_rotate,integer")])
7523 (define_insn "*rotldi3_internal14le"
7524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7525 (compare:CC (zero_extend:DI
7526 (subreg:SI
7527 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7528 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7529 (const_int 0)))
7530 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7531 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7532 "@
7533 rldcl. %3,%1,%2,32
7534 rldicl. %3,%1,%H2,32
7535 #
7536 #"
7537 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7538 (set_attr "length" "4,4,8,8")])
7540 (define_insn "*rotldi3_internal14be"
7541 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7542 (compare:CC (zero_extend:DI
7543 (subreg:SI
7544 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7545 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7546 (const_int 0)))
7547 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7548 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7549 "@
7550 rldcl. %3,%1,%2,32
7551 rldicl. %3,%1,%H2,32
7552 #
7553 #"
7554 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7555 (set_attr "length" "4,4,8,8")])
7557 (define_split
7558 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7559 (compare:CC (zero_extend:DI
7560 (subreg:SI
7561 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7562 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7563 (const_int 0)))
7564 (clobber (match_scratch:DI 3 ""))]
7565 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7566 [(set (match_dup 3)
7567 (zero_extend:DI (subreg:SI
7568 (rotate:DI (match_dup 1)
7569 (match_dup 2)) 0)))
7570 (set (match_dup 0)
7571 (compare:CC (match_dup 3)
7572 (const_int 0)))]
7573 "")
7575 (define_split
7576 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7577 (compare:CC (zero_extend:DI
7578 (subreg:SI
7579 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7580 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7581 (const_int 0)))
7582 (clobber (match_scratch:DI 3 ""))]
7583 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7584 [(set (match_dup 3)
7585 (zero_extend:DI (subreg:SI
7586 (rotate:DI (match_dup 1)
7587 (match_dup 2)) 4)))
7588 (set (match_dup 0)
7589 (compare:CC (match_dup 3)
7590 (const_int 0)))]
7591 "")
7593 (define_insn "*rotldi3_internal15le"
7594 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7595 (compare:CC (zero_extend:DI
7596 (subreg:SI
7597 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7598 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7599 (const_int 0)))
7600 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7601 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7602 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7603 "@
7604 rldcl. %0,%1,%2,32
7605 rldicl. %0,%1,%H2,32
7606 #
7607 #"
7608 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7609 (set_attr "length" "4,4,8,8")])
7611 (define_insn "*rotldi3_internal15be"
7612 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7613 (compare:CC (zero_extend:DI
7614 (subreg:SI
7615 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7616 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7617 (const_int 0)))
7618 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7619 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7620 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7621 "@
7622 rldcl. %0,%1,%2,32
7623 rldicl. %0,%1,%H2,32
7624 #
7625 #"
7626 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7627 (set_attr "length" "4,4,8,8")])
7629 (define_split
7630 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7631 (compare:CC (zero_extend:DI
7632 (subreg:SI
7633 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7634 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7635 (const_int 0)))
7636 (set (match_operand:DI 0 "gpc_reg_operand" "")
7637 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7638 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7639 [(set (match_dup 0)
7640 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7641 (set (match_dup 3)
7642 (compare:CC (match_dup 0)
7643 (const_int 0)))]
7644 "")
7646 (define_split
7647 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7648 (compare:CC (zero_extend:DI
7649 (subreg:SI
7650 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7651 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7652 (const_int 0)))
7653 (set (match_operand:DI 0 "gpc_reg_operand" "")
7654 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7655 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7656 [(set (match_dup 0)
7657 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7658 (set (match_dup 3)
7659 (compare:CC (match_dup 0)
7660 (const_int 0)))]
7661 "")
7663 (define_expand "ashldi3"
7664 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7665 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7666 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7667 "TARGET_POWERPC64"
7668 "")
7670 (define_insn "*ashldi3_internal1"
7671 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7672 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7673 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7674 "TARGET_POWERPC64"
7675 "@
7676 sld %0,%1,%2
7677 sldi %0,%1,%H2"
7678 [(set_attr "type" "var_shift_rotate,shift")])
7680 (define_insn "*ashldi3_internal2"
7681 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7682 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7683 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7684 (const_int 0)))
7685 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7686 "TARGET_64BIT"
7687 "@
7688 sld. %3,%1,%2
7689 sldi. %3,%1,%H2
7690 #
7691 #"
7692 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7693 (set_attr "length" "4,4,8,8")])
7695 (define_split
7696 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7697 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7698 (match_operand:SI 2 "reg_or_cint_operand" ""))
7699 (const_int 0)))
7700 (clobber (match_scratch:DI 3 ""))]
7701 "TARGET_POWERPC64 && reload_completed"
7702 [(set (match_dup 3)
7703 (ashift:DI (match_dup 1) (match_dup 2)))
7704 (set (match_dup 0)
7705 (compare:CC (match_dup 3)
7706 (const_int 0)))]
7707 "")
7709 (define_insn "*ashldi3_internal3"
7710 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7711 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7712 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7713 (const_int 0)))
7714 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7715 (ashift:DI (match_dup 1) (match_dup 2)))]
7716 "TARGET_64BIT"
7717 "@
7718 sld. %0,%1,%2
7719 sldi. %0,%1,%H2
7720 #
7721 #"
7722 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7723 (set_attr "length" "4,4,8,8")])
7725 (define_split
7726 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7727 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7728 (match_operand:SI 2 "reg_or_cint_operand" ""))
7729 (const_int 0)))
7730 (set (match_operand:DI 0 "gpc_reg_operand" "")
7731 (ashift:DI (match_dup 1) (match_dup 2)))]
7732 "TARGET_POWERPC64 && reload_completed"
7733 [(set (match_dup 0)
7734 (ashift:DI (match_dup 1) (match_dup 2)))
7735 (set (match_dup 3)
7736 (compare:CC (match_dup 0)
7737 (const_int 0)))]
7738 "")
7740 (define_insn "*ashldi3_internal4"
7741 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7742 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7743 (match_operand:SI 2 "const_int_operand" "i"))
7744 (match_operand:DI 3 "const_int_operand" "n")))]
7745 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7746 "rldic %0,%1,%H2,%W3")
7748 (define_insn "ashldi3_internal5"
7749 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7750 (compare:CC
7751 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7752 (match_operand:SI 2 "const_int_operand" "i,i"))
7753 (match_operand:DI 3 "const_int_operand" "n,n"))
7754 (const_int 0)))
7755 (clobber (match_scratch:DI 4 "=r,r"))]
7756 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7757 "@
7758 rldic. %4,%1,%H2,%W3
7759 #"
7760 [(set_attr "type" "compare")
7761 (set_attr "length" "4,8")])
7763 (define_split
7764 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7765 (compare:CC
7766 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7767 (match_operand:SI 2 "const_int_operand" ""))
7768 (match_operand:DI 3 "const_int_operand" ""))
7769 (const_int 0)))
7770 (clobber (match_scratch:DI 4 ""))]
7771 "TARGET_POWERPC64 && reload_completed
7772 && includes_rldic_lshift_p (operands[2], operands[3])"
7773 [(set (match_dup 4)
7774 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7775 (match_dup 3)))
7776 (set (match_dup 0)
7777 (compare:CC (match_dup 4)
7778 (const_int 0)))]
7779 "")
7781 (define_insn "*ashldi3_internal6"
7782 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7783 (compare:CC
7784 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7785 (match_operand:SI 2 "const_int_operand" "i,i"))
7786 (match_operand:DI 3 "const_int_operand" "n,n"))
7787 (const_int 0)))
7788 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7789 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7790 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7791 "@
7792 rldic. %0,%1,%H2,%W3
7793 #"
7794 [(set_attr "type" "compare")
7795 (set_attr "length" "4,8")])
7797 (define_split
7798 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7799 (compare:CC
7800 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7801 (match_operand:SI 2 "const_int_operand" ""))
7802 (match_operand:DI 3 "const_int_operand" ""))
7803 (const_int 0)))
7804 (set (match_operand:DI 0 "gpc_reg_operand" "")
7805 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7806 "TARGET_POWERPC64 && reload_completed
7807 && includes_rldic_lshift_p (operands[2], operands[3])"
7808 [(set (match_dup 0)
7809 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7810 (match_dup 3)))
7811 (set (match_dup 4)
7812 (compare:CC (match_dup 0)
7813 (const_int 0)))]
7814 "")
7816 (define_insn "*ashldi3_internal7"
7817 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7818 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7819 (match_operand:SI 2 "const_int_operand" "i"))
7820 (match_operand:DI 3 "mask64_operand" "n")))]
7821 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7822 "rldicr %0,%1,%H2,%S3")
7824 (define_insn "ashldi3_internal8"
7825 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7826 (compare:CC
7827 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7828 (match_operand:SI 2 "const_int_operand" "i,i"))
7829 (match_operand:DI 3 "mask64_operand" "n,n"))
7830 (const_int 0)))
7831 (clobber (match_scratch:DI 4 "=r,r"))]
7832 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7833 "@
7834 rldicr. %4,%1,%H2,%S3
7835 #"
7836 [(set_attr "type" "compare")
7837 (set_attr "length" "4,8")])
7839 (define_split
7840 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7841 (compare:CC
7842 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7843 (match_operand:SI 2 "const_int_operand" ""))
7844 (match_operand:DI 3 "mask64_operand" ""))
7845 (const_int 0)))
7846 (clobber (match_scratch:DI 4 ""))]
7847 "TARGET_POWERPC64 && reload_completed
7848 && includes_rldicr_lshift_p (operands[2], operands[3])"
7849 [(set (match_dup 4)
7850 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7851 (match_dup 3)))
7852 (set (match_dup 0)
7853 (compare:CC (match_dup 4)
7854 (const_int 0)))]
7855 "")
7857 (define_insn "*ashldi3_internal9"
7858 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7859 (compare:CC
7860 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7861 (match_operand:SI 2 "const_int_operand" "i,i"))
7862 (match_operand:DI 3 "mask64_operand" "n,n"))
7863 (const_int 0)))
7864 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7865 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7866 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7867 "@
7868 rldicr. %0,%1,%H2,%S3
7869 #"
7870 [(set_attr "type" "compare")
7871 (set_attr "length" "4,8")])
7873 (define_split
7874 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7875 (compare:CC
7876 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7877 (match_operand:SI 2 "const_int_operand" ""))
7878 (match_operand:DI 3 "mask64_operand" ""))
7879 (const_int 0)))
7880 (set (match_operand:DI 0 "gpc_reg_operand" "")
7881 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7882 "TARGET_POWERPC64 && reload_completed
7883 && includes_rldicr_lshift_p (operands[2], operands[3])"
7884 [(set (match_dup 0)
7885 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7886 (match_dup 3)))
7887 (set (match_dup 4)
7888 (compare:CC (match_dup 0)
7889 (const_int 0)))]
7890 "")
7892 (define_expand "lshrdi3"
7893 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7894 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7895 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7896 "TARGET_POWERPC64"
7897 "")
7899 (define_insn "*lshrdi3_internal1"
7900 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7901 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7902 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7903 "TARGET_POWERPC64"
7904 "@
7905 srd %0,%1,%2
7906 srdi %0,%1,%H2"
7907 [(set_attr "type" "var_shift_rotate,shift")])
7909 (define_insn "*lshrdi3_internal2"
7910 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7911 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7912 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7913 (const_int 0)))
7914 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7915 "TARGET_64BIT "
7916 "@
7917 srd. %3,%1,%2
7918 srdi. %3,%1,%H2
7919 #
7920 #"
7921 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7922 (set_attr "length" "4,4,8,8")])
7924 (define_split
7925 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7926 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7927 (match_operand:SI 2 "reg_or_cint_operand" ""))
7928 (const_int 0)))
7929 (clobber (match_scratch:DI 3 ""))]
7930 "TARGET_POWERPC64 && reload_completed"
7931 [(set (match_dup 3)
7932 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7933 (set (match_dup 0)
7934 (compare:CC (match_dup 3)
7935 (const_int 0)))]
7936 "")
7938 (define_insn "*lshrdi3_internal3"
7939 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7940 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7941 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7942 (const_int 0)))
7943 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7944 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7945 "TARGET_64BIT"
7946 "@
7947 srd. %0,%1,%2
7948 srdi. %0,%1,%H2
7949 #
7950 #"
7951 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7952 (set_attr "length" "4,4,8,8")])
7954 (define_split
7955 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7956 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7957 (match_operand:SI 2 "reg_or_cint_operand" ""))
7958 (const_int 0)))
7959 (set (match_operand:DI 0 "gpc_reg_operand" "")
7960 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7961 "TARGET_POWERPC64 && reload_completed"
7962 [(set (match_dup 0)
7963 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7964 (set (match_dup 3)
7965 (compare:CC (match_dup 0)
7966 (const_int 0)))]
7967 "")
7969 (define_expand "ashrdi3"
7970 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7971 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7972 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7973 ""
7974 "
7975 {
7976 if (TARGET_POWERPC64)
7977 ;
7978 else if (GET_CODE (operands[2]) == CONST_INT)
7979 {
7980 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7981 DONE;
7982 }
7983 else
7984 FAIL;
7985 }")
7987 (define_insn "*ashrdi3_internal1"
7988 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7989 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7990 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7991 "TARGET_POWERPC64"
7992 "@
7993 srad %0,%1,%2
7994 sradi %0,%1,%H2"
7995 [(set_attr "type" "var_shift_rotate,shift")])
7997 (define_insn "*ashrdi3_internal2"
7998 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7999 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8000 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8001 (const_int 0)))
8002 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8003 "TARGET_64BIT"
8004 "@
8005 srad. %3,%1,%2
8006 sradi. %3,%1,%H2
8007 #
8008 #"
8009 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8010 (set_attr "length" "4,4,8,8")])
8012 (define_split
8013 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8014 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8015 (match_operand:SI 2 "reg_or_cint_operand" ""))
8016 (const_int 0)))
8017 (clobber (match_scratch:DI 3 ""))]
8018 "TARGET_POWERPC64 && reload_completed"
8019 [(set (match_dup 3)
8020 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8021 (set (match_dup 0)
8022 (compare:CC (match_dup 3)
8023 (const_int 0)))]
8024 "")
8026 (define_insn "*ashrdi3_internal3"
8027 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8028 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8029 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8030 (const_int 0)))
8031 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8032 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8033 "TARGET_64BIT"
8034 "@
8035 srad. %0,%1,%2
8036 sradi. %0,%1,%H2
8037 #
8038 #"
8039 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8040 (set_attr "length" "4,4,8,8")])
8042 (define_split
8043 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8044 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8045 (match_operand:SI 2 "reg_or_cint_operand" ""))
8046 (const_int 0)))
8047 (set (match_operand:DI 0 "gpc_reg_operand" "")
8048 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8049 "TARGET_POWERPC64 && reload_completed"
8050 [(set (match_dup 0)
8051 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8052 (set (match_dup 3)
8053 (compare:CC (match_dup 0)
8054 (const_int 0)))]
8055 "")
8057 (define_expand "anddi3"
8058 [(parallel
8059 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8060 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8061 (match_operand:DI 2 "reg_or_cint_operand" "")))
8062 (clobber (match_scratch:CC 3 ""))])]
8063 ""
8064 {
8065 if (!TARGET_POWERPC64)
8066 {
8067 rtx cc = gen_rtx_SCRATCH (CCmode);
8068 rs6000_split_logical (operands, AND, false, false, false, cc);
8069 DONE;
8070 }
8071 else if (!and64_2_operand (operands[2], DImode))
8072 operands[2] = force_reg (DImode, operands[2]);
8073 })
8075 (define_insn "anddi3_mc"
8076 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8077 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8078 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8079 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8080 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8081 "@
8082 and %0,%1,%2
8083 rldic%B2 %0,%1,0,%S2
8084 rlwinm %0,%1,0,%m2,%M2
8085 andi. %0,%1,%b2
8086 andis. %0,%1,%u2
8087 #"
8088 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8089 (set_attr "length" "4,4,4,4,4,8")])
8091 (define_insn "anddi3_nomc"
8092 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8093 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8094 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8095 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8096 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8097 "@
8098 and %0,%1,%2
8099 rldic%B2 %0,%1,0,%S2
8100 rlwinm %0,%1,0,%m2,%M2
8101 #"
8102 [(set_attr "length" "4,4,4,8")])
8104 (define_split
8105 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8106 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8107 (match_operand:DI 2 "mask64_2_operand" "")))
8108 (clobber (match_scratch:CC 3 ""))]
8109 "TARGET_POWERPC64
8110 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8111 && !mask_operand (operands[2], DImode)
8112 && !mask64_operand (operands[2], DImode)"
8113 [(set (match_dup 0)
8114 (and:DI (rotate:DI (match_dup 1)
8115 (match_dup 4))
8116 (match_dup 5)))
8117 (set (match_dup 0)
8118 (and:DI (rotate:DI (match_dup 0)
8119 (match_dup 6))
8120 (match_dup 7)))]
8121 {
8122 build_mask64_2_operands (operands[2], &operands[4]);
8123 })
8125 (define_insn "*anddi3_internal2_mc"
8126 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8127 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8128 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8129 (const_int 0)))
8130 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8131 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8132 "TARGET_64BIT && rs6000_gen_cell_microcode"
8133 "@
8134 and. %3,%1,%2
8135 rldic%B2. %3,%1,0,%S2
8136 rlwinm. %3,%1,0,%m2,%M2
8137 andi. %3,%1,%b2
8138 andis. %3,%1,%u2
8139 #
8140 #
8141 #
8142 #
8143 #
8144 #
8145 #"
8146 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8147 fast_compare,compare,compare,compare,compare,compare,\
8148 compare,compare")
8149 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8151 (define_split
8152 [(set (match_operand:CC 0 "cc_reg_operand" "")
8153 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8154 (match_operand:DI 2 "mask64_2_operand" ""))
8155 (const_int 0)))
8156 (clobber (match_scratch:DI 3 ""))
8157 (clobber (match_scratch:CC 4 ""))]
8158 "TARGET_64BIT && reload_completed
8159 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8160 && !mask_operand (operands[2], DImode)
8161 && !mask64_operand (operands[2], DImode)"
8162 [(set (match_dup 3)
8163 (and:DI (rotate:DI (match_dup 1)
8164 (match_dup 5))
8165 (match_dup 6)))
8166 (parallel [(set (match_dup 0)
8167 (compare:CC (and:DI (rotate:DI (match_dup 3)
8168 (match_dup 7))
8169 (match_dup 8))
8170 (const_int 0)))
8171 (clobber (match_dup 3))])]
8172 "
8173 {
8174 build_mask64_2_operands (operands[2], &operands[5]);
8175 }")
8177 (define_insn "*anddi3_internal3_mc"
8178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8179 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8180 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8181 (const_int 0)))
8182 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8183 (and:DI (match_dup 1) (match_dup 2)))
8184 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8185 "TARGET_64BIT && rs6000_gen_cell_microcode"
8186 "@
8187 and. %0,%1,%2
8188 rldic%B2. %0,%1,0,%S2
8189 rlwinm. %0,%1,0,%m2,%M2
8190 andi. %0,%1,%b2
8191 andis. %0,%1,%u2
8192 #
8193 #
8194 #
8195 #
8196 #
8197 #
8198 #"
8199 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8200 fast_compare,compare,compare,compare,compare,compare,\
8201 compare,compare")
8202 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8204 (define_split
8205 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8206 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8207 (match_operand:DI 2 "and64_2_operand" ""))
8208 (const_int 0)))
8209 (set (match_operand:DI 0 "gpc_reg_operand" "")
8210 (and:DI (match_dup 1) (match_dup 2)))
8211 (clobber (match_scratch:CC 4 ""))]
8212 "TARGET_64BIT && reload_completed"
8213 [(parallel [(set (match_dup 0)
8214 (and:DI (match_dup 1) (match_dup 2)))
8215 (clobber (match_dup 4))])
8216 (set (match_dup 3)
8217 (compare:CC (match_dup 0)
8218 (const_int 0)))]
8219 "")
8221 (define_split
8222 [(set (match_operand:CC 3 "cc_reg_operand" "")
8223 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8224 (match_operand:DI 2 "mask64_2_operand" ""))
8225 (const_int 0)))
8226 (set (match_operand:DI 0 "gpc_reg_operand" "")
8227 (and:DI (match_dup 1) (match_dup 2)))
8228 (clobber (match_scratch:CC 4 ""))]
8229 "TARGET_64BIT && reload_completed
8230 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8231 && !mask_operand (operands[2], DImode)
8232 && !mask64_operand (operands[2], DImode)"
8233 [(set (match_dup 0)
8234 (and:DI (rotate:DI (match_dup 1)
8235 (match_dup 5))
8236 (match_dup 6)))
8237 (parallel [(set (match_dup 3)
8238 (compare:CC (and:DI (rotate:DI (match_dup 0)
8239 (match_dup 7))
8240 (match_dup 8))
8241 (const_int 0)))
8242 (set (match_dup 0)
8243 (and:DI (rotate:DI (match_dup 0)
8244 (match_dup 7))
8245 (match_dup 8)))])]
8246 "
8247 {
8248 build_mask64_2_operands (operands[2], &operands[5]);
8249 }")
8251 (define_expand "iordi3"
8252 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8253 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8254 (match_operand:DI 2 "reg_or_cint_operand" "")))]
8255 ""
8256 {
8257 if (!TARGET_POWERPC64)
8258 {
8259 rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
8260 DONE;
8261 }
8262 else if (!reg_or_logical_cint_operand (operands[2], DImode))
8263 operands[2] = force_reg (DImode, operands[2]);
8264 else if (non_logical_cint_operand (operands[2], DImode))
8265 {
8266 HOST_WIDE_INT value;
8267 rtx tmp = ((!can_create_pseudo_p ()
8268 || rtx_equal_p (operands[0], operands[1]))
8269 ? operands[0] : gen_reg_rtx (DImode));
8271 value = INTVAL (operands[2]);
8272 emit_insn (gen_iordi3 (tmp, operands[1],
8273 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8275 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8276 DONE;
8277 }
8278 })
8280 (define_expand "xordi3"
8281 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8282 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8283 (match_operand:DI 2 "reg_or_cint_operand" "")))]
8284 ""
8285 {
8286 if (!TARGET_POWERPC64)
8287 {
8288 rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
8289 DONE;
8290 }
8291 else if (!reg_or_logical_cint_operand (operands[2], DImode))
8292 operands[2] = force_reg (DImode, operands[2]);
8293 if (non_logical_cint_operand (operands[2], DImode))
8294 {
8295 HOST_WIDE_INT value;
8296 rtx tmp = ((!can_create_pseudo_p ()
8297 || rtx_equal_p (operands[0], operands[1]))
8298 ? operands[0] : gen_reg_rtx (DImode));
8300 value = INTVAL (operands[2]);
8301 emit_insn (gen_xordi3 (tmp, operands[1],
8302 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8304 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8305 DONE;
8306 }
8307 })
8309 (define_insn "*booldi3_internal1"
8310 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8311 (match_operator:DI 3 "boolean_or_operator"
8312 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8313 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8314 "TARGET_POWERPC64"
8315 "@
8316 %q3 %0,%1,%2
8317 %q3i %0,%1,%b2
8318 %q3is %0,%1,%u2")
8320 (define_insn "*booldi3_internal2"
8321 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8322 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8323 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8324 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8325 (const_int 0)))
8326 (clobber (match_scratch:DI 3 "=r,r"))]
8327 "TARGET_64BIT"
8328 "@
8329 %q4. %3,%1,%2
8330 #"
8331 [(set_attr "type" "fast_compare,compare")
8332 (set_attr "length" "4,8")])
8334 (define_split
8335 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8336 (compare:CC (match_operator:DI 4 "boolean_operator"
8337 [(match_operand:DI 1 "gpc_reg_operand" "")
8338 (match_operand:DI 2 "gpc_reg_operand" "")])
8339 (const_int 0)))
8340 (clobber (match_scratch:DI 3 ""))]
8341 "TARGET_POWERPC64 && reload_completed"
8342 [(set (match_dup 3) (match_dup 4))
8343 (set (match_dup 0)
8344 (compare:CC (match_dup 3)
8345 (const_int 0)))]
8346 "")
8348 (define_insn "*booldi3_internal3"
8349 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8350 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8351 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8352 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8353 (const_int 0)))
8354 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8355 (match_dup 4))]
8356 "TARGET_64BIT"
8357 "@
8358 %q4. %0,%1,%2
8359 #"
8360 [(set_attr "type" "fast_compare,compare")
8361 (set_attr "length" "4,8")])
8363 (define_split
8364 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8365 (compare:CC (match_operator:DI 4 "boolean_operator"
8366 [(match_operand:DI 1 "gpc_reg_operand" "")
8367 (match_operand:DI 2 "gpc_reg_operand" "")])
8368 (const_int 0)))
8369 (set (match_operand:DI 0 "gpc_reg_operand" "")
8370 (match_dup 4))]
8371 "TARGET_POWERPC64 && reload_completed"
8372 [(set (match_dup 0) (match_dup 4))
8373 (set (match_dup 3)
8374 (compare:CC (match_dup 0)
8375 (const_int 0)))]
8376 "")
8378 ;; Split a logical operation that we can't do in one insn into two insns,
8379 ;; each of which does one 16-bit part. This is used by combine.
8381 (define_split
8382 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8383 (match_operator:DI 3 "boolean_or_operator"
8384 [(match_operand:DI 1 "gpc_reg_operand" "")
8385 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8386 "TARGET_POWERPC64"
8387 [(set (match_dup 0) (match_dup 4))
8388 (set (match_dup 0) (match_dup 5))]
8389 "
8390 {
8391 rtx i3,i4;
8393 i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
8394 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8395 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8396 operands[1], i3);
8397 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8398 operands[0], i4);
8399 }")
8401 (define_insn "*boolcdi3_internal1"
8402 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8403 (match_operator:DI 3 "boolean_operator"
8404 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8405 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8406 "TARGET_POWERPC64"
8407 "%q3 %0,%2,%1")
8409 (define_insn "*boolcdi3_internal2"
8410 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8411 (compare:CC (match_operator:DI 4 "boolean_operator"
8412 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8413 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8414 (const_int 0)))
8415 (clobber (match_scratch:DI 3 "=r,r"))]
8416 "TARGET_64BIT"
8417 "@
8418 %q4. %3,%2,%1
8419 #"
8420 [(set_attr "type" "fast_compare,compare")
8421 (set_attr "length" "4,8")])
8423 (define_split
8424 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8425 (compare:CC (match_operator:DI 4 "boolean_operator"
8426 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8427 (match_operand:DI 2 "gpc_reg_operand" "")])
8428 (const_int 0)))
8429 (clobber (match_scratch:DI 3 ""))]
8430 "TARGET_POWERPC64 && reload_completed"
8431 [(set (match_dup 3) (match_dup 4))
8432 (set (match_dup 0)
8433 (compare:CC (match_dup 3)
8434 (const_int 0)))]
8435 "")
8437 (define_insn "*boolcdi3_internal3"
8438 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8439 (compare:CC (match_operator:DI 4 "boolean_operator"
8440 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8441 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8442 (const_int 0)))
8443 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8444 (match_dup 4))]
8445 "TARGET_64BIT"
8446 "@
8447 %q4. %0,%2,%1
8448 #"
8449 [(set_attr "type" "fast_compare,compare")
8450 (set_attr "length" "4,8")])
8452 (define_split
8453 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8454 (compare:CC (match_operator:DI 4 "boolean_operator"
8455 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8456 (match_operand:DI 2 "gpc_reg_operand" "")])
8457 (const_int 0)))
8458 (set (match_operand:DI 0 "gpc_reg_operand" "")
8459 (match_dup 4))]
8460 "TARGET_POWERPC64 && reload_completed"
8461 [(set (match_dup 0) (match_dup 4))
8462 (set (match_dup 3)
8463 (compare:CC (match_dup 0)
8464 (const_int 0)))]
8465 "")
8467 (define_insn "*boolccdi3_internal1"
8468 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8469 (match_operator:DI 3 "boolean_operator"
8470 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8471 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8472 "TARGET_POWERPC64"
8473 "%q3 %0,%1,%2")
8475 (define_insn "*boolccdi3_internal2"
8476 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8477 (compare:CC (match_operator:DI 4 "boolean_operator"
8478 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8479 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8480 (const_int 0)))
8481 (clobber (match_scratch:DI 3 "=r,r"))]
8482 "TARGET_64BIT"
8483 "@
8484 %q4. %3,%1,%2
8485 #"
8486 [(set_attr "type" "fast_compare,compare")
8487 (set_attr "length" "4,8")])
8489 (define_split
8490 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8491 (compare:CC (match_operator:DI 4 "boolean_operator"
8492 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8493 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8494 (const_int 0)))
8495 (clobber (match_scratch:DI 3 ""))]
8496 "TARGET_POWERPC64 && reload_completed"
8497 [(set (match_dup 3) (match_dup 4))
8498 (set (match_dup 0)
8499 (compare:CC (match_dup 3)
8500 (const_int 0)))]
8501 "")
8503 (define_insn "*boolccdi3_internal3"
8504 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8505 (compare:CC (match_operator:DI 4 "boolean_operator"
8506 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8507 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8508 (const_int 0)))
8509 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8510 (match_dup 4))]
8511 "TARGET_64BIT"
8512 "@
8513 %q4. %0,%1,%2
8514 #"
8515 [(set_attr "type" "fast_compare,compare")
8516 (set_attr "length" "4,8")])
8518 (define_split
8519 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8520 (compare:CC (match_operator:DI 4 "boolean_operator"
8521 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8522 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8523 (const_int 0)))
8524 (set (match_operand:DI 0 "gpc_reg_operand" "")
8525 (match_dup 4))]
8526 "TARGET_POWERPC64 && reload_completed"
8527 [(set (match_dup 0) (match_dup 4))
8528 (set (match_dup 3)
8529 (compare:CC (match_dup 0)
8530 (const_int 0)))]
8531 "")
8533 ;; Eqv operation.
8534 (define_insn "*eqv<mode>3"
8535 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
8536 (not:GPR
8537 (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
8538 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
8539 ""
8540 "eqv %0,%1,%2"
8541 [(set_attr "type" "integer")
8542 (set_attr "length" "4")])
8544 \f
8545 ;; 128-bit logical operations expanders
8547 (define_expand "and<mode>3"
8548 [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8549 (and:BOOL_128
8550 (match_operand:BOOL_128 1 "vlogical_operand" "")
8551 (match_operand:BOOL_128 2 "vlogical_operand" "")))
8552 (clobber (match_scratch:CC 3 ""))])]
8553 ""
8554 "")
8556 (define_expand "ior<mode>3"
8557 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8558 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8559 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8560 ""
8561 "")
8563 (define_expand "xor<mode>3"
8564 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8565 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8566 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8567 ""
8568 "")
8570 (define_expand "one_cmpl<mode>2"
8571 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8572 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8573 ""
8574 "")
8576 (define_expand "nor<mode>3"
8577 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8578 (and:BOOL_128
8579 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8580 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8581 ""
8582 "")
8584 (define_expand "andc<mode>3"
8585 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8586 (and:BOOL_128
8587 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8588 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8589 ""
8590 "")
8592 ;; Power8 vector logical instructions.
8593 (define_expand "eqv<mode>3"
8594 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8595 (not:BOOL_128
8596 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8597 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8598 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8599 "")
8601 ;; Rewrite nand into canonical form
8602 (define_expand "nand<mode>3"
8603 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8604 (ior:BOOL_128
8605 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8606 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8607 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8608 "")
8610 ;; The canonical form is to have the negated element first, so we need to
8611 ;; reverse arguments.
8612 (define_expand "orc<mode>3"
8613 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8614 (ior:BOOL_128
8615 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8616 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8617 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8618 "")
8620 ;; 128-bit logical operations insns and split operations
8621 (define_insn_and_split "*and<mode>3_internal"
8622 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8623 (and:BOOL_128
8624 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8625 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))
8626 (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]
8627 ""
8628 {
8629 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8630 return "xxland %x0,%x1,%x2";
8632 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8633 return "vand %0,%1,%2";
8635 return "#";
8636 }
8637 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8638 [(const_int 0)]
8639 {
8640 rs6000_split_logical (operands, AND, false, false, false, operands[3]);
8641 DONE;
8642 }
8643 [(set (attr "type")
8644 (if_then_else
8645 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8646 (const_string "vecsimple")
8647 (const_string "integer")))
8648 (set (attr "length")
8649 (if_then_else
8650 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8651 (const_string "4")
8652 (if_then_else
8653 (match_test "TARGET_POWERPC64")
8654 (const_string "8")
8655 (const_string "16"))))])
8657 ;; 128-bit IOR/XOR
8658 (define_insn_and_split "*bool<mode>3_internal"
8659 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8660 (match_operator:BOOL_128 3 "boolean_or_operator"
8661 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8662 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8663 ""
8664 {
8665 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8666 return "xxl%q3 %x0,%x1,%x2";
8668 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8669 return "v%q3 %0,%1,%2";
8671 return "#";
8672 }
8673 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8674 [(const_int 0)]
8675 {
8676 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,
8677 NULL_RTX);
8678 DONE;
8679 }
8680 [(set (attr "type")
8681 (if_then_else
8682 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8683 (const_string "vecsimple")
8684 (const_string "integer")))
8685 (set (attr "length")
8686 (if_then_else
8687 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8688 (const_string "4")
8689 (if_then_else
8690 (match_test "TARGET_POWERPC64")
8691 (const_string "8")
8692 (const_string "16"))))])
8694 ;; 128-bit ANDC/ORC
8695 (define_insn_and_split "*boolc<mode>3_internal1"
8696 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8697 (match_operator:BOOL_128 3 "boolean_operator"
8698 [(not:BOOL_128
8699 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
8700 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8701 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8702 {
8703 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8704 return "xxl%q3 %x0,%x1,%x2";
8706 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8707 return "v%q3 %0,%1,%2";
8709 return "#";
8710 }
8711 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8712 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8713 [(const_int 0)]
8714 {
8715 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8716 NULL_RTX);
8717 DONE;
8718 }
8719 [(set (attr "type")
8720 (if_then_else
8721 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8722 (const_string "vecsimple")
8723 (const_string "integer")))
8724 (set (attr "length")
8725 (if_then_else
8726 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8727 (const_string "4")
8728 (if_then_else
8729 (match_test "TARGET_POWERPC64")
8730 (const_string "8")
8731 (const_string "16"))))])
8733 (define_insn_and_split "*boolc<mode>3_internal2"
8734 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8735 (match_operator:TI2 3 "boolean_operator"
8736 [(not:TI2
8737 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8738 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
8739 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8740 "#"
8741 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8742 [(const_int 0)]
8743 {
8744 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8745 NULL_RTX);
8746 DONE;
8747 }
8748 [(set_attr "type" "integer")
8749 (set (attr "length")
8750 (if_then_else
8751 (match_test "TARGET_POWERPC64")
8752 (const_string "8")
8753 (const_string "16")))])
8755 ;; 128-bit NAND/NOR
8756 (define_insn_and_split "*boolcc<mode>3_internal1"
8757 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8758 (match_operator:BOOL_128 3 "boolean_operator"
8759 [(not:BOOL_128
8760 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
8761 (not:BOOL_128
8762 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
8763 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8764 {
8765 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8766 return "xxl%q3 %x0,%x1,%x2";
8768 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8769 return "v%q3 %0,%1,%2";
8771 return "#";
8772 }
8773 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8774 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8775 [(const_int 0)]
8776 {
8777 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8778 NULL_RTX);
8779 DONE;
8780 }
8781 [(set (attr "type")
8782 (if_then_else
8783 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8784 (const_string "vecsimple")
8785 (const_string "integer")))
8786 (set (attr "length")
8787 (if_then_else
8788 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8789 (const_string "4")
8790 (if_then_else
8791 (match_test "TARGET_POWERPC64")
8792 (const_string "8")
8793 (const_string "16"))))])
8795 (define_insn_and_split "*boolcc<mode>3_internal2"
8796 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8797 (match_operator:TI2 3 "boolean_operator"
8798 [(not:TI2
8799 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8800 (not:TI2
8801 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
8802 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8803 "#"
8804 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8805 [(const_int 0)]
8806 {
8807 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8808 NULL_RTX);
8809 DONE;
8810 }
8811 [(set_attr "type" "integer")
8812 (set (attr "length")
8813 (if_then_else
8814 (match_test "TARGET_POWERPC64")
8815 (const_string "8")
8816 (const_string "16")))])
8819 ;; 128-bit EQV
8820 (define_insn_and_split "*eqv<mode>3_internal1"
8821 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8822 (not:BOOL_128
8823 (xor:BOOL_128
8824 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
8825 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
8826 "TARGET_P8_VECTOR"
8827 {
8828 if (vsx_register_operand (operands[0], <MODE>mode))
8829 return "xxleqv %x0,%x1,%x2";
8831 return "#";
8832 }
8833 "TARGET_P8_VECTOR && reload_completed
8834 && int_reg_operand (operands[0], <MODE>mode)"
8835 [(const_int 0)]
8836 {
8837 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8838 DONE;
8839 }
8840 [(set (attr "type")
8841 (if_then_else
8842 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8843 (const_string "vecsimple")
8844 (const_string "integer")))
8845 (set (attr "length")
8846 (if_then_else
8847 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8848 (const_string "4")
8849 (if_then_else
8850 (match_test "TARGET_POWERPC64")
8851 (const_string "8")
8852 (const_string "16"))))])
8854 (define_insn_and_split "*eqv<mode>3_internal2"
8855 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8856 (not:TI2
8857 (xor:TI2
8858 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
8859 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
8860 "!TARGET_P8_VECTOR"
8861 "#"
8862 "reload_completed && !TARGET_P8_VECTOR"
8863 [(const_int 0)]
8864 {
8865 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8866 DONE;
8867 }
8868 [(set_attr "type" "integer")
8869 (set (attr "length")
8870 (if_then_else
8871 (match_test "TARGET_POWERPC64")
8872 (const_string "8")
8873 (const_string "16")))])
8875 ;; 128-bit one's complement
8876 (define_insn_and_split "*one_cmpl<mode>3_internal"
8877 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8878 (not:BOOL_128
8879 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
8880 ""
8881 {
8882 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8883 return "xxlnor %x0,%x1,%x1";
8885 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8886 return "vnor %0,%1,%1";
8888 return "#";
8889 }
8890 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8891 [(const_int 0)]
8892 {
8893 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
8894 DONE;
8895 }
8896 [(set (attr "type")
8897 (if_then_else
8898 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8899 (const_string "vecsimple")
8900 (const_string "integer")))
8901 (set (attr "length")
8902 (if_then_else
8903 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8904 (const_string "4")
8905 (if_then_else
8906 (match_test "TARGET_POWERPC64")
8907 (const_string "8")
8908 (const_string "16"))))])
8910 \f
8911 ;; Now define ways of moving data around.
8913 ;; Set up a register with a value from the GOT table
8915 (define_expand "movsi_got"
8916 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8917 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8918 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8919 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8920 "
8921 {
8922 if (GET_CODE (operands[1]) == CONST)
8923 {
8924 rtx offset = const0_rtx;
8925 HOST_WIDE_INT value;
8927 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8928 value = INTVAL (offset);
8929 if (value != 0)
8930 {
8931 rtx tmp = (!can_create_pseudo_p ()
8932 ? operands[0]
8933 : gen_reg_rtx (Pmode));
8934 emit_insn (gen_movsi_got (tmp, operands[1]));
8935 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8936 DONE;
8937 }
8938 }
8940 operands[2] = rs6000_got_register (operands[1]);
8941 }")
8943 (define_insn "*movsi_got_internal"
8944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8945 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8946 (match_operand:SI 2 "gpc_reg_operand" "b")]
8947 UNSPEC_MOVSI_GOT))]
8948 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8949 "lwz %0,%a1@got(%2)"
8950 [(set_attr "type" "load")])
8952 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8953 ;; didn't get allocated to a hard register.
8954 (define_split
8955 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8956 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8957 (match_operand:SI 2 "memory_operand" "")]
8958 UNSPEC_MOVSI_GOT))]
8959 "DEFAULT_ABI == ABI_V4
8960 && flag_pic == 1
8961 && (reload_in_progress || reload_completed)"
8962 [(set (match_dup 0) (match_dup 2))
8963 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8964 UNSPEC_MOVSI_GOT))]
8965 "")
8967 ;; For SI, we special-case integers that can't be loaded in one insn. We
8968 ;; do the load 16-bits at a time. We could do this by loading from memory,
8969 ;; and this is even supposed to be faster, but it is simpler not to get
8970 ;; integers in the TOC.
8971 (define_insn "movsi_low"
8972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8973 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8974 (match_operand 2 "" ""))))]
8975 "TARGET_MACHO && ! TARGET_64BIT"
8976 "lwz %0,lo16(%2)(%1)"
8977 [(set_attr "type" "load")
8978 (set_attr "length" "4")])
8980 (define_insn "*movsi_internal1"
8981 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
8982 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
8983 "!TARGET_SINGLE_FPU &&
8984 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8985 "@
8986 mr %0,%1
8987 la %0,%a1
8988 lwz%U1%X1 %0,%1
8989 stw%U0%X0 %1,%0
8990 li %0,%1
8991 lis %0,%v1
8992 #
8993 mf%1 %0
8994 mt%0 %1
8995 mt%0 %1
8996 nop"
8997 [(set_attr_alternative "type"
8998 [(const_string "*")
8999 (const_string "*")
9000 (if_then_else
9001 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9002 (const_string "load_ux")
9003 (if_then_else
9004 (match_test "update_address_mem (operands[1], VOIDmode)")
9005 (const_string "load_u")
9006 (const_string "load")))
9007 (if_then_else
9008 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9009 (const_string "store_ux")
9010 (if_then_else
9011 (match_test "update_address_mem (operands[0], VOIDmode)")
9012 (const_string "store_u")
9013 (const_string "store")))
9014 (const_string "*")
9015 (const_string "*")
9016 (const_string "*")
9017 (const_string "mfjmpr")
9018 (const_string "mtjmpr")
9019 (const_string "*")
9020 (const_string "*")])
9022 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
9024 (define_insn "*movsi_internal1_single"
9025 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
9026 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
9027 "TARGET_SINGLE_FPU &&
9028 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9029 "@
9030 mr %0,%1
9031 la %0,%a1
9032 lwz%U1%X1 %0,%1
9033 stw%U0%X0 %1,%0
9034 li %0,%1
9035 lis %0,%v1
9036 #
9037 mf%1 %0
9038 mt%0 %1
9039 mt%0 %1
9040 nop
9041 stfs%U0%X0 %1,%0
9042 lfs%U1%X1 %0,%1"
9043 [(set_attr_alternative "type"
9044 [(const_string "*")
9045 (const_string "*")
9046 (if_then_else
9047 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9048 (const_string "load_ux")
9049 (if_then_else
9050 (match_test "update_address_mem (operands[1], VOIDmode)")
9051 (const_string "load_u")
9052 (const_string "load")))
9053 (if_then_else
9054 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9055 (const_string "store_ux")
9056 (if_then_else
9057 (match_test "update_address_mem (operands[0], VOIDmode)")
9058 (const_string "store_u")
9059 (const_string "store")))
9060 (const_string "*")
9061 (const_string "*")
9062 (const_string "*")
9063 (const_string "mfjmpr")
9064 (const_string "mtjmpr")
9065 (const_string "*")
9066 (const_string "*")
9067 (if_then_else
9068 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9069 (const_string "fpstore_ux")
9070 (if_then_else
9071 (match_test "update_address_mem (operands[0], VOIDmode)")
9072 (const_string "fpstore_u")
9073 (const_string "fpstore")))
9074 (if_then_else
9075 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9076 (const_string "fpload_ux")
9077 (if_then_else
9078 (match_test "update_address_mem (operands[1], VOIDmode)")
9079 (const_string "fpload_u")
9080 (const_string "fpload")))])
9081 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
9083 ;; Split a load of a large constant into the appropriate two-insn
9084 ;; sequence.
9086 (define_split
9087 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9088 (match_operand:SI 1 "const_int_operand" ""))]
9089 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
9090 && (INTVAL (operands[1]) & 0xffff) != 0"
9091 [(set (match_dup 0)
9092 (match_dup 2))
9093 (set (match_dup 0)
9094 (ior:SI (match_dup 0)
9095 (match_dup 3)))]
9096 "
9097 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
9099 if (tem == operands[0])
9100 DONE;
9101 else
9102 FAIL;
9103 }")
9105 (define_insn "*mov<mode>_internal2"
9106 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
9107 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
9108 (const_int 0)))
9109 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
9110 ""
9111 "@
9112 cmp<wd>i %2,%0,0
9113 mr. %0,%1
9114 #"
9115 [(set_attr "type" "cmp,fast_compare,cmp")
9116 (set_attr "length" "4,4,8")])
9118 (define_split
9119 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9120 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9121 (const_int 0)))
9122 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
9123 "reload_completed"
9124 [(set (match_dup 0) (match_dup 1))
9125 (set (match_dup 2)
9126 (compare:CC (match_dup 0)
9127 (const_int 0)))]
9128 "")
9129 \f
9130 (define_insn "*movhi_internal"
9131 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
9132 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
9133 "gpc_reg_operand (operands[0], HImode)
9134 || gpc_reg_operand (operands[1], HImode)"
9135 "@
9136 mr %0,%1
9137 lhz%U1%X1 %0,%1
9138 sth%U0%X0 %1,%0
9139 li %0,%w1
9140 mf%1 %0
9141 mt%0 %1
9142 nop"
9143 [(set_attr_alternative "type"
9144 [(const_string "*")
9145 (if_then_else
9146 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9147 (const_string "load_ux")
9148 (if_then_else
9149 (match_test "update_address_mem (operands[1], VOIDmode)")
9150 (const_string "load_u")
9151 (const_string "load")))
9152 (if_then_else
9153 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9154 (const_string "store_ux")
9155 (if_then_else
9156 (match_test "update_address_mem (operands[0], VOIDmode)")
9157 (const_string "store_u")
9158 (const_string "store")))
9159 (const_string "*")
9160 (const_string "mfjmpr")
9161 (const_string "mtjmpr")
9162 (const_string "*")])])
9164 (define_expand "mov<mode>"
9165 [(set (match_operand:INT 0 "general_operand" "")
9166 (match_operand:INT 1 "any_operand" ""))]
9167 ""
9168 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9170 (define_insn "*movqi_internal"
9171 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
9172 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
9173 "gpc_reg_operand (operands[0], QImode)
9174 || gpc_reg_operand (operands[1], QImode)"
9175 "@
9176 mr %0,%1
9177 lbz%U1%X1 %0,%1
9178 stb%U0%X0 %1,%0
9179 li %0,%1
9180 mf%1 %0
9181 mt%0 %1
9182 nop"
9183 [(set_attr_alternative "type"
9184 [(const_string "*")
9185 (if_then_else
9186 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9187 (const_string "load_ux")
9188 (if_then_else
9189 (match_test "update_address_mem (operands[1], VOIDmode)")
9190 (const_string "load_u")
9191 (const_string "load")))
9192 (if_then_else
9193 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9194 (const_string "store_ux")
9195 (if_then_else
9196 (match_test "update_address_mem (operands[0], VOIDmode)")
9197 (const_string "store_u")
9198 (const_string "store")))
9199 (const_string "*")
9200 (const_string "mfjmpr")
9201 (const_string "mtjmpr")
9202 (const_string "*")])])
9203 \f
9204 ;; Here is how to move condition codes around. When we store CC data in
9205 ;; an integer register or memory, we store just the high-order 4 bits.
9206 ;; This lets us not shift in the most common case of CR0.
9207 (define_expand "movcc"
9208 [(set (match_operand:CC 0 "nonimmediate_operand" "")
9209 (match_operand:CC 1 "nonimmediate_operand" ""))]
9210 ""
9211 "")
9213 (define_insn "*movcc_internal1"
9214 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
9215 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
9216 "register_operand (operands[0], CCmode)
9217 || register_operand (operands[1], CCmode)"
9218 "@
9219 mcrf %0,%1
9220 mtcrf 128,%1
9221 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
9222 crxor %0,%0,%0
9223 mfcr %0%Q1
9224 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
9225 mr %0,%1
9226 li %0,%1
9227 mf%1 %0
9228 mt%0 %1
9229 lwz%U1%X1 %0,%1
9230 stw%U0%X0 %1,%0"
9231 [(set (attr "type")
9232 (cond [(eq_attr "alternative" "0,3")
9233 (const_string "cr_logical")
9234 (eq_attr "alternative" "1,2")
9235 (const_string "mtcr")
9236 (eq_attr "alternative" "6,7")
9237 (const_string "integer")
9238 (eq_attr "alternative" "8")
9239 (const_string "mfjmpr")
9240 (eq_attr "alternative" "9")
9241 (const_string "mtjmpr")
9242 (eq_attr "alternative" "10")
9243 (if_then_else
9244 (match_test "update_indexed_address_mem (operands[1],
9245 VOIDmode)")
9246 (const_string "load_ux")
9247 (if_then_else
9248 (match_test "update_address_mem (operands[1], VOIDmode)")
9249 (const_string "load_u")
9250 (const_string "load")))
9251 (eq_attr "alternative" "11")
9252 (if_then_else
9253 (match_test "update_indexed_address_mem (operands[0],
9254 VOIDmode)")
9255 (const_string "store_ux")
9256 (if_then_else
9257 (match_test "update_address_mem (operands[0], VOIDmode)")
9258 (const_string "store_u")
9259 (const_string "store")))
9260 (match_test "TARGET_MFCRF")
9261 (const_string "mfcrf")
9262 ]
9263 (const_string "mfcr")))
9264 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
9265 \f
9266 ;; For floating-point, we normally deal with the floating-point registers
9267 ;; unless -msoft-float is used. The sole exception is that parameter passing
9268 ;; can produce floating-point values in fixed-point registers. Unless the
9269 ;; value is a simple constant or already in memory, we deal with this by
9270 ;; allocating memory and copying the value explicitly via that memory location.
9272 ;; Move 32-bit binary/decimal floating point
9273 (define_expand "mov<mode>"
9274 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
9275 (match_operand:FMOVE32 1 "any_operand" ""))]
9276 "<fmove_ok>"
9277 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9279 (define_split
9280 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
9281 (match_operand:FMOVE32 1 "const_double_operand" ""))]
9282 "reload_completed
9283 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9284 || (GET_CODE (operands[0]) == SUBREG
9285 && GET_CODE (SUBREG_REG (operands[0])) == REG
9286 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9287 [(set (match_dup 2) (match_dup 3))]
9288 "
9289 {
9290 long l;
9291 REAL_VALUE_TYPE rv;
9293 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9294 <real_value_to_target> (rv, l);
9296 if (! TARGET_POWERPC64)
9297 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
9298 else
9299 operands[2] = gen_lowpart (SImode, operands[0]);
9301 operands[3] = gen_int_mode (l, SImode);
9302 }")
9304 (define_insn "mov<mode>_hardfloat"
9305 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
9306 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
9307 "(gpc_reg_operand (operands[0], <MODE>mode)
9308 || gpc_reg_operand (operands[1], <MODE>mode))
9309 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9310 "@
9311 mr %0,%1
9312 lwz%U1%X1 %0,%1
9313 stw%U0%X0 %1,%0
9314 fmr %0,%1
9315 xxlor %x0,%x1,%x1
9316 xxlxor %x0,%x0,%x0
9317 <f32_li>
9318 <f32_si>
9319 <f32_lv>
9320 <f32_sv>
9321 mtvsrwz %x0,%1
9322 mfvsrwz %0,%x1
9323 mt%0 %1
9324 mf%1 %0
9325 nop
9326 #
9327 #"
9328 [(set_attr_alternative "type"
9329 [(const_string "*")
9330 (if_then_else
9331 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9332 (const_string "load_ux")
9333 (if_then_else
9334 (match_test "update_address_mem (operands[1], VOIDmode)")
9335 (const_string "load_u")
9336 (const_string "load")))
9337 (if_then_else
9338 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9339 (const_string "store_ux")
9340 (if_then_else
9341 (match_test "update_address_mem (operands[0], VOIDmode)")
9342 (const_string "store_u")
9343 (const_string "store")))
9344 (const_string "fp")
9345 (const_string "vecsimple")
9346 (const_string "vecsimple")
9347 (if_then_else
9348 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9349 (const_string "fpload_ux")
9350 (if_then_else
9351 (match_test "update_address_mem (operands[1], VOIDmode)")
9352 (const_string "fpload_u")
9353 (const_string "fpload")))
9354 (if_then_else
9355 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9356 (const_string "fpstore_ux")
9357 (if_then_else
9358 (match_test "update_address_mem (operands[0], VOIDmode)")
9359 (const_string "fpstore_u")
9360 (const_string "fpstore")))
9361 (const_string "fpload")
9362 (const_string "fpstore")
9363 (const_string "mftgpr")
9364 (const_string "mffgpr")
9365 (const_string "mtjmpr")
9366 (const_string "mfjmpr")
9367 (const_string "*")
9368 (const_string "*")
9369 (const_string "*")])
9370 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
9372 (define_insn "*mov<mode>_softfloat"
9373 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
9374 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
9375 "(gpc_reg_operand (operands[0], <MODE>mode)
9376 || gpc_reg_operand (operands[1], <MODE>mode))
9377 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9378 "@
9379 mr %0,%1
9380 mt%0 %1
9381 mf%1 %0
9382 lwz%U1%X1 %0,%1
9383 stw%U0%X0 %1,%0
9384 li %0,%1
9385 lis %0,%v1
9386 #
9387 #
9388 nop"
9389 [(set_attr_alternative "type"
9390 [(const_string "*")
9391 (const_string "mtjmpr")
9392 (const_string "mfjmpr")
9393 (if_then_else
9394 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9395 (const_string "load_ux")
9396 (if_then_else
9397 (match_test "update_address_mem (operands[1], VOIDmode)")
9398 (const_string "load_u")
9399 (const_string "load")))
9400 (if_then_else
9401 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9402 (const_string "store_ux")
9403 (if_then_else
9404 (match_test "update_address_mem (operands[0], VOIDmode)")
9405 (const_string "store_u")
9406 (const_string "store")))
9407 (const_string "*")
9408 (const_string "*")
9409 (const_string "*")
9410 (const_string "*")
9411 (const_string "*")])
9412 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
9414 \f
9415 ;; Move 64-bit binary/decimal floating point
9416 (define_expand "mov<mode>"
9417 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
9418 (match_operand:FMOVE64 1 "any_operand" ""))]
9419 ""
9420 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9422 (define_split
9423 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9424 (match_operand:FMOVE64 1 "const_int_operand" ""))]
9425 "! TARGET_POWERPC64 && reload_completed
9426 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9427 || (GET_CODE (operands[0]) == SUBREG
9428 && GET_CODE (SUBREG_REG (operands[0])) == REG
9429 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9430 [(set (match_dup 2) (match_dup 4))
9431 (set (match_dup 3) (match_dup 1))]
9432 "
9433 {
9434 int endian = (WORDS_BIG_ENDIAN == 0);
9435 HOST_WIDE_INT value = INTVAL (operands[1]);
9437 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
9438 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
9439 operands[4] = GEN_INT (value >> 32);
9440 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9441 }")
9443 (define_split
9444 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9445 (match_operand:FMOVE64 1 "const_double_operand" ""))]
9446 "! TARGET_POWERPC64 && reload_completed
9447 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9448 || (GET_CODE (operands[0]) == SUBREG
9449 && GET_CODE (SUBREG_REG (operands[0])) == REG
9450 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9451 [(set (match_dup 2) (match_dup 4))
9452 (set (match_dup 3) (match_dup 5))]
9453 "
9454 {
9455 int endian = (WORDS_BIG_ENDIAN == 0);
9456 long l[2];
9457 REAL_VALUE_TYPE rv;
9459 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9460 <real_value_to_target> (rv, l);
9462 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
9463 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
9464 operands[4] = gen_int_mode (l[endian], SImode);
9465 operands[5] = gen_int_mode (l[1 - endian], SImode);
9466 }")
9468 (define_split
9469 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9470 (match_operand:FMOVE64 1 "const_double_operand" ""))]
9471 "TARGET_POWERPC64 && reload_completed
9472 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9473 || (GET_CODE (operands[0]) == SUBREG
9474 && GET_CODE (SUBREG_REG (operands[0])) == REG
9475 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9476 [(set (match_dup 2) (match_dup 3))]
9477 "
9478 {
9479 int endian = (WORDS_BIG_ENDIAN == 0);
9480 long l[2];
9481 REAL_VALUE_TYPE rv;
9482 HOST_WIDE_INT val;
9484 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9485 <real_value_to_target> (rv, l);
9487 operands[2] = gen_lowpart (DImode, operands[0]);
9488 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9489 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9490 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9492 operands[3] = gen_int_mode (val, DImode);
9493 }")
9495 ;; Don't have reload use general registers to load a constant. It is
9496 ;; less efficient than loading the constant into an FP register, since
9497 ;; it will probably be used there.
9499 ;; The move constraints are ordered to prefer floating point registers before
9500 ;; general purpose registers to avoid doing a store and a load to get the value
9501 ;; into a floating point register when it is needed for a floating point
9502 ;; operation. Prefer traditional floating point registers over VSX registers,
9503 ;; since the D-form version of the memory instructions does not need a GPR for
9504 ;; reloading.
9506 (define_insn "*mov<mode>_hardfloat32"
9507 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
9508 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
9509 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9510 && (gpc_reg_operand (operands[0], <MODE>mode)
9511 || gpc_reg_operand (operands[1], <MODE>mode))"
9512 "@
9513 stfd%U0%X0 %1,%0
9514 lfd%U1%X1 %0,%1
9515 fmr %0,%1
9516 lxsd%U1x %x0,%y1
9517 stxsd%U0x %x1,%y0
9518 xxlor %x0,%x1,%x1
9519 xxlxor %x0,%x0,%x0
9520 #
9521 #
9522 #
9523 #
9524 #
9525 #"
9526 [(set_attr_alternative "type"
9527 [(if_then_else
9528 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9529 (const_string "fpstore_ux")
9530 (if_then_else
9531 (match_test "update_address_mem (operands[0], VOIDmode)")
9532 (const_string "fpstore_u")
9533 (const_string "fpstore")))
9534 (if_then_else
9535 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9536 (const_string "fpload_ux")
9537 (if_then_else
9538 (match_test "update_address_mem (operands[1], VOIDmode)")
9539 (const_string "fpload_u")
9540 (const_string "fpload")))
9541 (const_string "fp")
9542 (if_then_else
9543 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9544 (const_string "fpload_ux")
9545 (const_string "fpload"))
9546 (if_then_else
9547 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9548 (const_string "fpstore_ux")
9549 (const_string "fpstore"))
9550 (const_string "vecsimple")
9551 (const_string "vecsimple")
9552 (const_string "store")
9553 (const_string "load")
9554 (const_string "two")
9555 (const_string "fp")
9556 (const_string "fp")
9557 (const_string "*")])
9558 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
9560 (define_insn "*mov<mode>_softfloat32"
9561 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
9562 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
9563 "! TARGET_POWERPC64
9564 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9565 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9566 && (gpc_reg_operand (operands[0], <MODE>mode)
9567 || gpc_reg_operand (operands[1], <MODE>mode))"
9568 "#"
9569 [(set_attr "type" "store,load,two,*,*,*")
9570 (set_attr "length" "8,8,8,8,12,16")])
9572 ; ld/std require word-aligned displacements -> 'Y' constraint.
9573 ; List Y->r and r->Y before r->r for reload.
9574 (define_insn "*mov<mode>_hardfloat64"
9575 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
9576 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
9577 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9578 && (gpc_reg_operand (operands[0], <MODE>mode)
9579 || gpc_reg_operand (operands[1], <MODE>mode))"
9580 "@
9581 stfd%U0%X0 %1,%0
9582 lfd%U1%X1 %0,%1
9583 fmr %0,%1
9584 lxsd%U1x %x0,%y1
9585 stxsd%U0x %x1,%y0
9586 xxlor %x0,%x1,%x1
9587 xxlxor %x0,%x0,%x0
9588 std%U0%X0 %1,%0
9589 ld%U1%X1 %0,%1
9590 mr %0,%1
9591 mt%0 %1
9592 mf%1 %0
9593 nop
9594 #
9595 #
9596 #
9597 mftgpr %0,%1
9598 mffgpr %0,%1
9599 mfvsrd %0,%x1
9600 mtvsrd %x0,%1"
9601 [(set_attr_alternative "type"
9602 [(if_then_else
9603 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9604 (const_string "fpstore_ux")
9605 (if_then_else
9606 (match_test "update_address_mem (operands[0], VOIDmode)")
9607 (const_string "fpstore_u")
9608 (const_string "fpstore")))
9609 (if_then_else
9610 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9611 (const_string "fpload_ux")
9612 (if_then_else
9613 (match_test "update_address_mem (operands[1], VOIDmode)")
9614 (const_string "fpload_u")
9615 (const_string "fpload")))
9616 (const_string "fp")
9617 (if_then_else
9618 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9619 (const_string "fpload_ux")
9620 (const_string "fpload"))
9621 (if_then_else
9622 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9623 (const_string "fpstore_ux")
9624 (const_string "fpstore"))
9625 (const_string "vecsimple")
9626 (const_string "vecsimple")
9627 (if_then_else
9628 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9629 (const_string "store_ux")
9630 (if_then_else
9631 (match_test "update_address_mem (operands[0], VOIDmode)")
9632 (const_string "store_u")
9633 (const_string "store")))
9634 (if_then_else
9635 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9636 (const_string "load_ux")
9637 (if_then_else
9638 (match_test "update_address_mem (operands[1], VOIDmode)")
9639 (const_string "load_u")
9640 (const_string "load")))
9641 (const_string "*")
9642 (const_string "mtjmpr")
9643 (const_string "mfjmpr")
9644 (const_string "*")
9645 (const_string "*")
9646 (const_string "*")
9647 (const_string "*")
9648 (const_string "mftgpr")
9649 (const_string "mffgpr")
9650 (const_string "mftgpr")
9651 (const_string "mffgpr")])
9652 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
9654 (define_insn "*mov<mode>_softfloat64"
9655 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
9656 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
9657 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9658 && (gpc_reg_operand (operands[0], <MODE>mode)
9659 || gpc_reg_operand (operands[1], <MODE>mode))"
9660 "@
9661 std%U0%X0 %1,%0
9662 ld%U1%X1 %0,%1
9663 mr %0,%1
9664 mt%0 %1
9665 mf%1 %0
9666 #
9667 #
9668 #
9669 nop"
9670 [(set_attr_alternative "type"
9671 [(if_then_else
9672 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9673 (const_string "store_ux")
9674 (if_then_else
9675 (match_test "update_address_mem (operands[0], VOIDmode)")
9676 (const_string "store_u")
9677 (const_string "store")))
9678 (if_then_else
9679 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9680 (const_string "load_ux")
9681 (if_then_else
9682 (match_test "update_address_mem (operands[1], VOIDmode)")
9683 (const_string "load_u")
9684 (const_string "load")))
9685 (const_string "*")
9686 (const_string "mtjmpr")
9687 (const_string "mfjmpr")
9688 (const_string "*")
9689 (const_string "*")
9690 (const_string "*")
9691 (const_string "*")])
9692 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9693 \f
9694 (define_expand "mov<mode>"
9695 [(set (match_operand:FMOVE128 0 "general_operand" "")
9696 (match_operand:FMOVE128 1 "any_operand" ""))]
9697 ""
9698 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9700 ;; It's important to list Y->r and r->Y before r->r because otherwise
9701 ;; reload, given m->r, will try to pick r->r and reload it, which
9702 ;; doesn't make progress.
9703 (define_insn_and_split "*mov<mode>_internal"
9704 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9705 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
9706 "TARGET_HARD_FLOAT && TARGET_FPRS
9707 && (gpc_reg_operand (operands[0], <MODE>mode)
9708 || gpc_reg_operand (operands[1], <MODE>mode))"
9709 "#"
9710 "&& reload_completed"
9711 [(pc)]
9712 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9713 [(set_attr "length" "8,8,8,20,20,16")])
9715 (define_insn_and_split "*mov<mode>_softfloat"
9716 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
9717 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
9718 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
9719 && (gpc_reg_operand (operands[0], <MODE>mode)
9720 || gpc_reg_operand (operands[1], <MODE>mode))"
9721 "#"
9722 "&& reload_completed"
9723 [(pc)]
9724 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9725 [(set_attr "length" "20,20,16")])
9727 (define_expand "extenddftf2"
9728 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9729 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9730 "!TARGET_IEEEQUAD
9731 && TARGET_HARD_FLOAT
9732 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9733 && TARGET_LONG_DOUBLE_128"
9734 {
9735 if (TARGET_E500_DOUBLE)
9736 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9737 else
9738 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9739 DONE;
9740 })
9742 (define_expand "extenddftf2_fprs"
9743 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9744 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9745 (use (match_dup 2))])]
9746 "!TARGET_IEEEQUAD
9747 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9748 && TARGET_LONG_DOUBLE_128"
9749 {
9750 operands[2] = CONST0_RTX (DFmode);
9751 /* Generate GOT reference early for SVR4 PIC. */
9752 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9753 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9754 })
9756 (define_insn_and_split "*extenddftf2_internal"
9757 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
9758 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
9759 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
9760 "!TARGET_IEEEQUAD
9761 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9762 && TARGET_LONG_DOUBLE_128"
9763 "#"
9764 "&& reload_completed"
9765 [(pc)]
9766 {
9767 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9768 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9769 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9770 operands[1]);
9771 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9772 operands[2]);
9773 DONE;
9774 })
9776 (define_expand "extendsftf2"
9777 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9778 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9779 "!TARGET_IEEEQUAD
9780 && TARGET_HARD_FLOAT
9781 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9782 && TARGET_LONG_DOUBLE_128"
9783 {
9784 rtx tmp = gen_reg_rtx (DFmode);
9785 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9786 emit_insn (gen_extenddftf2 (operands[0], tmp));
9787 DONE;
9788 })
9790 (define_expand "trunctfdf2"
9791 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9792 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9793 "!TARGET_IEEEQUAD
9794 && TARGET_HARD_FLOAT
9795 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9796 && TARGET_LONG_DOUBLE_128"
9797 "")
9799 (define_insn_and_split "trunctfdf2_internal1"
9800 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9801 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9802 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9803 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9804 "@
9805 #
9806 fmr %0,%1"
9807 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9808 [(const_int 0)]
9809 {
9810 emit_note (NOTE_INSN_DELETED);
9811 DONE;
9812 }
9813 [(set_attr "type" "fp")])
9815 (define_insn "trunctfdf2_internal2"
9816 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9817 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9818 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9819 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9820 && TARGET_LONG_DOUBLE_128"
9821 "fadd %0,%1,%L1"
9822 [(set_attr "type" "fp")
9823 (set_attr "fp_type" "fp_addsub_d")])
9825 (define_expand "trunctfsf2"
9826 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9827 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9828 "!TARGET_IEEEQUAD
9829 && TARGET_HARD_FLOAT
9830 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9831 && TARGET_LONG_DOUBLE_128"
9832 {
9833 if (TARGET_E500_DOUBLE)
9834 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9835 else
9836 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9837 DONE;
9838 })
9840 (define_insn_and_split "trunctfsf2_fprs"
9841 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9842 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9843 (clobber (match_scratch:DF 2 "=d"))]
9844 "!TARGET_IEEEQUAD
9845 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9846 && TARGET_LONG_DOUBLE_128"
9847 "#"
9848 "&& reload_completed"
9849 [(set (match_dup 2)
9850 (float_truncate:DF (match_dup 1)))
9851 (set (match_dup 0)
9852 (float_truncate:SF (match_dup 2)))]
9853 "")
9855 (define_expand "floatsitf2"
9856 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9857 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9858 "!TARGET_IEEEQUAD
9859 && TARGET_HARD_FLOAT
9860 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9861 && TARGET_LONG_DOUBLE_128"
9862 {
9863 rtx tmp = gen_reg_rtx (DFmode);
9864 expand_float (tmp, operands[1], false);
9865 emit_insn (gen_extenddftf2 (operands[0], tmp));
9866 DONE;
9867 })
9869 ; fadd, but rounding towards zero.
9870 ; This is probably not the optimal code sequence.
9871 (define_insn "fix_trunc_helper"
9872 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9873 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9874 UNSPEC_FIX_TRUNC_TF))
9875 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9876 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9877 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9878 [(set_attr "type" "fp")
9879 (set_attr "length" "20")])
9881 (define_expand "fix_trunctfsi2"
9882 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9883 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9884 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
9885 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
9886 {
9887 if (TARGET_E500_DOUBLE)
9888 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9889 else
9890 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9891 DONE;
9892 })
9894 (define_expand "fix_trunctfsi2_fprs"
9895 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9896 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9897 (clobber (match_dup 2))
9898 (clobber (match_dup 3))
9899 (clobber (match_dup 4))
9900 (clobber (match_dup 5))])]
9901 "!TARGET_IEEEQUAD
9902 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9903 {
9904 operands[2] = gen_reg_rtx (DFmode);
9905 operands[3] = gen_reg_rtx (DFmode);
9906 operands[4] = gen_reg_rtx (DImode);
9907 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9908 })
9910 (define_insn_and_split "*fix_trunctfsi2_internal"
9911 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9912 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9913 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9914 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9915 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9916 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9917 "!TARGET_IEEEQUAD
9918 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9919 "#"
9920 ""
9921 [(pc)]
9922 {
9923 rtx lowword;
9924 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9926 gcc_assert (MEM_P (operands[5]));
9927 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9929 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9930 emit_move_insn (operands[5], operands[4]);
9931 emit_move_insn (operands[0], lowword);
9932 DONE;
9933 })
9935 (define_expand "negtf2"
9936 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9937 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9938 "!TARGET_IEEEQUAD
9939 && TARGET_HARD_FLOAT
9940 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9941 && TARGET_LONG_DOUBLE_128"
9942 "")
9944 (define_insn "negtf2_internal"
9945 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9946 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9947 "!TARGET_IEEEQUAD
9948 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9949 "*
9950 {
9951 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9952 return \"fneg %L0,%L1\;fneg %0,%1\";
9953 else
9954 return \"fneg %0,%1\;fneg %L0,%L1\";
9955 }"
9956 [(set_attr "type" "fp")
9957 (set_attr "length" "8")])
9959 (define_expand "abstf2"
9960 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9961 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9962 "!TARGET_IEEEQUAD
9963 && TARGET_HARD_FLOAT
9964 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9965 && TARGET_LONG_DOUBLE_128"
9966 "
9967 {
9968 rtx label = gen_label_rtx ();
9969 if (TARGET_E500_DOUBLE)
9970 {
9971 if (flag_finite_math_only && !flag_trapping_math)
9972 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9973 else
9974 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9975 }
9976 else
9977 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9978 emit_label (label);
9979 DONE;
9980 }")
9982 (define_expand "abstf2_internal"
9983 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9984 (match_operand:TF 1 "gpc_reg_operand" ""))
9985 (set (match_dup 3) (match_dup 5))
9986 (set (match_dup 5) (abs:DF (match_dup 5)))
9987 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9988 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9989 (label_ref (match_operand 2 "" ""))
9990 (pc)))
9991 (set (match_dup 6) (neg:DF (match_dup 6)))]
9992 "!TARGET_IEEEQUAD
9993 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9994 && TARGET_LONG_DOUBLE_128"
9995 "
9996 {
9997 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9998 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9999 operands[3] = gen_reg_rtx (DFmode);
10000 operands[4] = gen_reg_rtx (CCFPmode);
10001 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
10002 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
10003 }")
10004 \f
10005 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
10006 ;; must have 3 arguments, and scratch register constraint must be a single
10007 ;; constraint.
10009 ;; Reload patterns to support gpr load/store with misaligned mem.
10010 ;; and multiple gpr load/store at offset >= 0xfffc
10011 (define_expand "reload_<mode>_store"
10012 [(parallel [(match_operand 0 "memory_operand" "=m")
10013 (match_operand 1 "gpc_reg_operand" "r")
10014 (match_operand:GPR 2 "register_operand" "=&b")])]
10015 ""
10016 {
10017 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
10018 DONE;
10019 })
10021 (define_expand "reload_<mode>_load"
10022 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
10023 (match_operand 1 "memory_operand" "m")
10024 (match_operand:GPR 2 "register_operand" "=b")])]
10025 ""
10026 {
10027 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
10028 DONE;
10029 })
10031 \f
10032 ;; Power8 merge instructions to allow direct move to/from floating point
10033 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
10034 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
10035 ;; value, since it is allocated in reload and not all of the flow information
10036 ;; is setup for it. We have two patterns to do the two moves between gprs and
10037 ;; fprs. There isn't a dependancy between the two, but we could potentially
10038 ;; schedule other instructions between the two instructions. TFmode is
10039 ;; currently limited to traditional FPR registers. If/when this is changed, we
10040 ;; will need to revist %L to make sure it works with VSX registers, or add an
10041 ;; %x version of %L.
10043 (define_insn "p8_fmrgow_<mode>"
10044 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
10045 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
10046 UNSPEC_P8V_FMRGOW))]
10047 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10048 "fmrgow %0,%1,%L1"
10049 [(set_attr "type" "vecperm")])
10051 (define_insn "p8_mtvsrwz_1"
10052 [(set (match_operand:TF 0 "register_operand" "=d")
10053 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
10054 UNSPEC_P8V_MTVSRWZ))]
10055 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10056 "mtvsrwz %x0,%1"
10057 [(set_attr "type" "mftgpr")])
10059 (define_insn "p8_mtvsrwz_2"
10060 [(set (match_operand:TF 0 "register_operand" "+d")
10061 (unspec:TF [(match_dup 0)
10062 (match_operand:SI 1 "register_operand" "r")]
10063 UNSPEC_P8V_MTVSRWZ))]
10064 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10065 "mtvsrwz %L0,%1"
10066 [(set_attr "type" "mftgpr")])
10068 (define_insn_and_split "reload_fpr_from_gpr<mode>"
10069 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
10070 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
10071 UNSPEC_P8V_RELOAD_FROM_GPR))
10072 (clobber (match_operand:TF 2 "register_operand" "=d"))]
10073 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10074 "#"
10075 "&& reload_completed"
10076 [(const_int 0)]
10077 {
10078 rtx dest = operands[0];
10079 rtx src = operands[1];
10080 rtx tmp = operands[2];
10081 rtx gpr_hi_reg = gen_highpart (SImode, src);
10082 rtx gpr_lo_reg = gen_lowpart (SImode, src);
10084 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
10085 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
10086 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
10087 DONE;
10088 }
10089 [(set_attr "length" "12")
10090 (set_attr "type" "three")])
10092 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
10093 (define_insn "p8_mtvsrd_1"
10094 [(set (match_operand:TF 0 "register_operand" "=ws")
10095 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
10096 UNSPEC_P8V_MTVSRD))]
10097 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10098 "mtvsrd %0,%1"
10099 [(set_attr "type" "mftgpr")])
10101 (define_insn "p8_mtvsrd_2"
10102 [(set (match_operand:TF 0 "register_operand" "+ws")
10103 (unspec:TF [(match_dup 0)
10104 (match_operand:DI 1 "register_operand" "r")]
10105 UNSPEC_P8V_MTVSRD))]
10106 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10107 "mtvsrd %L0,%1"
10108 [(set_attr "type" "mftgpr")])
10110 (define_insn "p8_xxpermdi_<mode>"
10111 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
10112 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
10113 UNSPEC_P8V_XXPERMDI))]
10114 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10115 "xxpermdi %x0,%1,%L1,0"
10116 [(set_attr "type" "vecperm")])
10118 (define_insn_and_split "reload_vsx_from_gpr<mode>"
10119 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
10120 (unspec:FMOVE128_GPR
10121 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
10122 UNSPEC_P8V_RELOAD_FROM_GPR))
10123 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
10124 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10125 "#"
10126 "&& reload_completed"
10127 [(const_int 0)]
10128 {
10129 rtx dest = operands[0];
10130 rtx src = operands[1];
10131 rtx tmp = operands[2];
10132 rtx gpr_hi_reg = gen_highpart (DImode, src);
10133 rtx gpr_lo_reg = gen_lowpart (DImode, src);
10135 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
10136 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
10137 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
10138 }
10139 [(set_attr "length" "12")
10140 (set_attr "type" "three")])
10142 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
10143 ;; type is stored internally as double precision in the VSX registers, we have
10144 ;; to convert it from the vector format.
10146 (define_insn_and_split "reload_vsx_from_gprsf"
10147 [(set (match_operand:SF 0 "register_operand" "=wa")
10148 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
10149 UNSPEC_P8V_RELOAD_FROM_GPR))
10150 (clobber (match_operand:DI 2 "register_operand" "=r"))]
10151 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
10152 "#"
10153 "&& reload_completed"
10154 [(const_int 0)]
10155 {
10156 rtx op0 = operands[0];
10157 rtx op1 = operands[1];
10158 rtx op2 = operands[2];
10159 rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);
10160 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
10162 /* Move SF value to upper 32-bits for xscvspdpn. */
10163 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
10164 emit_move_insn (op0_di, op2);
10165 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
10166 DONE;
10167 }
10168 [(set_attr "length" "8")
10169 (set_attr "type" "two")])
10171 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
10172 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
10173 ;; and then doing a move of that.
10174 (define_insn "p8_mfvsrd_3_<mode>"
10175 [(set (match_operand:DF 0 "register_operand" "=r")
10176 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
10177 UNSPEC_P8V_RELOAD_FROM_VSX))]
10178 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
10179 "mfvsrd %0,%x1"
10180 [(set_attr "type" "mftgpr")])
10182 (define_insn_and_split "reload_gpr_from_vsx<mode>"
10183 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
10184 (unspec:FMOVE128_GPR
10185 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
10186 UNSPEC_P8V_RELOAD_FROM_VSX))
10187 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
10188 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
10189 "#"
10190 "&& reload_completed"
10191 [(const_int 0)]
10192 {
10193 rtx dest = operands[0];
10194 rtx src = operands[1];
10195 rtx tmp = operands[2];
10196 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
10197 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
10199 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
10200 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
10201 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
10202 }
10203 [(set_attr "length" "12")
10204 (set_attr "type" "three")])
10206 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
10207 ;; type is stored internally as double precision, we have to convert it to the
10208 ;; vector format.
10210 (define_insn_and_split "reload_gpr_from_vsxsf"
10211 [(set (match_operand:SF 0 "register_operand" "=r")
10212 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
10213 UNSPEC_P8V_RELOAD_FROM_VSX))
10214 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
10215 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
10216 "#"
10217 "&& reload_completed"
10218 [(const_int 0)]
10219 {
10220 rtx op0 = operands[0];
10221 rtx op1 = operands[1];
10222 rtx op2 = operands[2];
10223 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
10225 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
10226 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
10227 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
10228 DONE;
10229 }
10230 [(set_attr "length" "12")
10231 (set_attr "type" "three")])
10233 (define_insn "p8_mfvsrd_4_disf"
10234 [(set (match_operand:DI 0 "register_operand" "=r")
10235 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
10236 UNSPEC_P8V_RELOAD_FROM_VSX))]
10237 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
10238 "mfvsrd %0,%x1"
10239 [(set_attr "type" "mftgpr")])
10241 \f
10242 ;; Next come the multi-word integer load and store and the load and store
10243 ;; multiple insns.
10245 ;; List r->r after r->Y, otherwise reload will try to reload a
10246 ;; non-offsettable address by using r->r which won't make progress.
10247 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
10248 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
10249 (define_insn "*movdi_internal32"
10250 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
10251 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
10252 "! TARGET_POWERPC64
10253 && (gpc_reg_operand (operands[0], DImode)
10254 || gpc_reg_operand (operands[1], DImode))"
10255 "@
10256 #
10257 #
10258 #
10259 stfd%U0%X0 %1,%0
10260 lfd%U1%X1 %0,%1
10261 fmr %0,%1
10262 #
10263 xxlxor %x0,%x0,%x0"
10264 [(set_attr_alternative "type"
10265 [(const_string "store")
10266 (const_string "load")
10267 (const_string "*")
10268 (if_then_else
10269 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10270 (const_string "fpstore_ux")
10271 (if_then_else
10272 (match_test "update_address_mem (operands[0], VOIDmode)")
10273 (const_string "fpstore_u")
10274 (const_string "fpstore")))
10275 (if_then_else
10276 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10277 (const_string "fpload_ux")
10278 (if_then_else
10279 (match_test "update_address_mem (operands[1], VOIDmode)")
10280 (const_string "fpload_u")
10281 (const_string "fpload")))
10282 (const_string "fp")
10283 (const_string "*")
10284 (const_string "vecsimple")])])
10286 (define_split
10287 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10288 (match_operand:DI 1 "const_int_operand" ""))]
10289 "! TARGET_POWERPC64 && reload_completed
10290 && gpr_or_gpr_p (operands[0], operands[1])
10291 && !direct_move_p (operands[0], operands[1])"
10292 [(set (match_dup 2) (match_dup 4))
10293 (set (match_dup 3) (match_dup 1))]
10294 "
10295 {
10296 HOST_WIDE_INT value = INTVAL (operands[1]);
10297 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10298 DImode);
10299 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10300 DImode);
10301 operands[4] = GEN_INT (value >> 32);
10302 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
10303 }")
10305 (define_split
10306 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
10307 (match_operand:DIFD 1 "input_operand" ""))]
10308 "reload_completed && !TARGET_POWERPC64
10309 && gpr_or_gpr_p (operands[0], operands[1])
10310 && !direct_move_p (operands[0], operands[1])"
10311 [(pc)]
10312 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10314 (define_insn "*movdi_internal64"
10315 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,?Z,?wv,?wa,r,*h,*h,?wa,r,?*wg,r,?*wm")
10316 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,wv,Z,wa,*h,r,0,O,*wg,r,*wm,r"))]
10317 "TARGET_POWERPC64
10318 && (gpc_reg_operand (operands[0], DImode)
10319 || gpc_reg_operand (operands[1], DImode))"
10320 "@
10321 std%U0%X0 %1,%0
10322 ld%U1%X1 %0,%1
10323 mr %0,%1
10324 li %0,%1
10325 lis %0,%v1
10326 #
10327 stfd%U0%X0 %1,%0
10328 lfd%U1%X1 %0,%1
10329 fmr %0,%1
10330 stxsd%U0x %x1,%y0
10331 lxsd%U1x %x0,%y1
10332 xxlor %x0,%x1,%x1
10333 mf%1 %0
10334 mt%0 %1
10335 nop
10336 xxlxor %x0,%x0,%x0
10337 mftgpr %0,%1
10338 mffgpr %0,%1
10339 mfvsrd %0,%x1
10340 mtvsrd %x0,%1"
10341 [(set_attr_alternative "type"
10342 [(if_then_else
10343 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10344 (const_string "store_ux")
10345 (if_then_else
10346 (match_test "update_address_mem (operands[0], VOIDmode)")
10347 (const_string "store_u")
10348 (const_string "store")))
10349 (if_then_else
10350 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10351 (const_string "load_ux")
10352 (if_then_else
10353 (match_test "update_address_mem (operands[1], VOIDmode)")
10354 (const_string "load_u")
10355 (const_string "load")))
10356 (const_string "*")
10357 (const_string "*")
10358 (const_string "*")
10359 (const_string "*")
10360 (if_then_else
10361 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10362 (const_string "fpstore_ux")
10363 (if_then_else
10364 (match_test "update_address_mem (operands[0], VOIDmode)")
10365 (const_string "fpstore_u")
10366 (const_string "fpstore")))
10367 (if_then_else
10368 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10369 (const_string "fpload_ux")
10370 (if_then_else
10371 (match_test "update_address_mem (operands[1], VOIDmode)")
10372 (const_string "fpload_u")
10373 (const_string "fpload")))
10374 (const_string "fp")
10375 (if_then_else
10376 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10377 (const_string "fpstore_ux")
10378 (const_string "fpstore"))
10379 (if_then_else
10380 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10381 (const_string "fpload_ux")
10382 (const_string "fpload"))
10383 (const_string "vecsimple")
10384 (const_string "mfjmpr")
10385 (const_string "mtjmpr")
10386 (const_string "*")
10387 (const_string "vecsimple")
10388 (const_string "mftgpr")
10389 (const_string "mffgpr")
10390 (const_string "mftgpr")
10391 (const_string "mffgpr")])
10392 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4,4,4,4")])
10394 ;; Generate all one-bits and clear left or right.
10395 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
10396 (define_split
10397 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10398 (match_operand:DI 1 "mask64_operand" ""))]
10399 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10400 [(set (match_dup 0) (const_int -1))
10401 (set (match_dup 0)
10402 (and:DI (rotate:DI (match_dup 0)
10403 (const_int 0))
10404 (match_dup 1)))]
10405 "")
10407 ;; Split a load of a large constant into the appropriate five-instruction
10408 ;; sequence. Handle anything in a constant number of insns.
10409 ;; When non-easy constants can go in the TOC, this should use
10410 ;; easy_fp_constant predicate.
10411 (define_split
10412 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10413 (match_operand:DI 1 "const_int_operand" ""))]
10414 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10415 [(set (match_dup 0) (match_dup 2))
10416 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10417 "
10418 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10420 if (tem == operands[0])
10421 DONE;
10422 else
10423 FAIL;
10424 }")
10426 (define_split
10427 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10428 (match_operand:DI 1 "const_double_operand" ""))]
10429 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10430 [(set (match_dup 0) (match_dup 2))
10431 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10432 "
10433 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10435 if (tem == operands[0])
10436 DONE;
10437 else
10438 FAIL;
10439 }")
10440 \f
10441 ;; TImode/PTImode is similar, except that we usually want to compute the
10442 ;; address into a register and use lsi/stsi (the exception is during reload).
10444 (define_insn "*mov<mode>_string"
10445 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
10446 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
10447 "! TARGET_POWERPC64
10448 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
10449 && (gpc_reg_operand (operands[0], <MODE>mode)
10450 || gpc_reg_operand (operands[1], <MODE>mode))"
10451 "*
10452 {
10453 switch (which_alternative)
10454 {
10455 default:
10456 gcc_unreachable ();
10457 case 0:
10458 if (TARGET_STRING)
10459 return \"stswi %1,%P0,16\";
10460 case 1:
10461 return \"#\";
10462 case 2:
10463 /* If the address is not used in the output, we can use lsi. Otherwise,
10464 fall through to generating four loads. */
10465 if (TARGET_STRING
10466 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10467 return \"lswi %0,%P1,16\";
10468 /* ... fall through ... */
10469 case 3:
10470 case 4:
10471 case 5:
10472 return \"#\";
10473 }
10474 }"
10475 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
10476 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
10477 (const_string "always")
10478 (const_string "conditional")))])
10480 (define_insn "*mov<mode>_ppc64"
10481 [(set (match_operand:TI2 0 "nonimmediate_operand" "=Y,r,r,r")
10482 (match_operand:TI2 1 "input_operand" "r,Y,r,F"))]
10483 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
10484 && (gpc_reg_operand (operands[0], <MODE>mode)
10485 || gpc_reg_operand (operands[1], <MODE>mode)))"
10486 {
10487 return rs6000_output_move_128bit (operands);
10488 }
10489 [(set_attr "type" "store,load,*,*")
10490 (set_attr "length" "8")])
10492 (define_split
10493 [(set (match_operand:TI2 0 "int_reg_operand" "")
10494 (match_operand:TI2 1 "const_double_operand" ""))]
10495 "TARGET_POWERPC64
10496 && (VECTOR_MEM_NONE_P (<MODE>mode)
10497 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
10498 [(set (match_dup 2) (match_dup 4))
10499 (set (match_dup 3) (match_dup 5))]
10500 "
10501 {
10502 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10503 <MODE>mode);
10504 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10505 <MODE>mode);
10506 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10507 {
10508 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10509 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10510 }
10511 else if (GET_CODE (operands[1]) == CONST_INT)
10512 {
10513 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10514 operands[5] = operands[1];
10515 }
10516 else
10517 FAIL;
10518 }")
10520 (define_split
10521 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
10522 (match_operand:TI2 1 "input_operand" ""))]
10523 "reload_completed
10524 && gpr_or_gpr_p (operands[0], operands[1])
10525 && !direct_move_p (operands[0], operands[1])
10526 && !quad_load_store_p (operands[0], operands[1])"
10527 [(pc)]
10528 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10529 \f
10530 (define_expand "load_multiple"
10531 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10532 (match_operand:SI 1 "" ""))
10533 (use (match_operand:SI 2 "" ""))])]
10534 "TARGET_STRING && !TARGET_POWERPC64"
10535 "
10536 {
10537 int regno;
10538 int count;
10539 rtx op1;
10540 int i;
10542 /* Support only loading a constant number of fixed-point registers from
10543 memory and only bother with this if more than two; the machine
10544 doesn't support more than eight. */
10545 if (GET_CODE (operands[2]) != CONST_INT
10546 || INTVAL (operands[2]) <= 2
10547 || INTVAL (operands[2]) > 8
10548 || GET_CODE (operands[1]) != MEM
10549 || GET_CODE (operands[0]) != REG
10550 || REGNO (operands[0]) >= 32)
10551 FAIL;
10553 count = INTVAL (operands[2]);
10554 regno = REGNO (operands[0]);
10556 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10557 op1 = replace_equiv_address (operands[1],
10558 force_reg (SImode, XEXP (operands[1], 0)));
10560 for (i = 0; i < count; i++)
10561 XVECEXP (operands[3], 0, i)
10562 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10563 adjust_address_nv (op1, SImode, i * 4));
10564 }")
10566 (define_insn "*ldmsi8"
10567 [(match_parallel 0 "load_multiple_operation"
10568 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10569 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10570 (set (match_operand:SI 3 "gpc_reg_operand" "")
10571 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10572 (set (match_operand:SI 4 "gpc_reg_operand" "")
10573 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10574 (set (match_operand:SI 5 "gpc_reg_operand" "")
10575 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10576 (set (match_operand:SI 6 "gpc_reg_operand" "")
10577 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10578 (set (match_operand:SI 7 "gpc_reg_operand" "")
10579 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10580 (set (match_operand:SI 8 "gpc_reg_operand" "")
10581 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10582 (set (match_operand:SI 9 "gpc_reg_operand" "")
10583 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10584 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10585 "*
10586 { return rs6000_output_load_multiple (operands); }"
10587 [(set_attr "type" "load_ux")
10588 (set_attr "length" "32")])
10590 (define_insn "*ldmsi7"
10591 [(match_parallel 0 "load_multiple_operation"
10592 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10593 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10594 (set (match_operand:SI 3 "gpc_reg_operand" "")
10595 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10596 (set (match_operand:SI 4 "gpc_reg_operand" "")
10597 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10598 (set (match_operand:SI 5 "gpc_reg_operand" "")
10599 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10600 (set (match_operand:SI 6 "gpc_reg_operand" "")
10601 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10602 (set (match_operand:SI 7 "gpc_reg_operand" "")
10603 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10604 (set (match_operand:SI 8 "gpc_reg_operand" "")
10605 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10606 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10607 "*
10608 { return rs6000_output_load_multiple (operands); }"
10609 [(set_attr "type" "load_ux")
10610 (set_attr "length" "32")])
10612 (define_insn "*ldmsi6"
10613 [(match_parallel 0 "load_multiple_operation"
10614 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10615 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10616 (set (match_operand:SI 3 "gpc_reg_operand" "")
10617 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10618 (set (match_operand:SI 4 "gpc_reg_operand" "")
10619 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10620 (set (match_operand:SI 5 "gpc_reg_operand" "")
10621 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10622 (set (match_operand:SI 6 "gpc_reg_operand" "")
10623 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10624 (set (match_operand:SI 7 "gpc_reg_operand" "")
10625 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10626 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10627 "*
10628 { return rs6000_output_load_multiple (operands); }"
10629 [(set_attr "type" "load_ux")
10630 (set_attr "length" "32")])
10632 (define_insn "*ldmsi5"
10633 [(match_parallel 0 "load_multiple_operation"
10634 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10635 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10636 (set (match_operand:SI 3 "gpc_reg_operand" "")
10637 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10638 (set (match_operand:SI 4 "gpc_reg_operand" "")
10639 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10640 (set (match_operand:SI 5 "gpc_reg_operand" "")
10641 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10642 (set (match_operand:SI 6 "gpc_reg_operand" "")
10643 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10644 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10645 "*
10646 { return rs6000_output_load_multiple (operands); }"
10647 [(set_attr "type" "load_ux")
10648 (set_attr "length" "32")])
10650 (define_insn "*ldmsi4"
10651 [(match_parallel 0 "load_multiple_operation"
10652 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10653 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10654 (set (match_operand:SI 3 "gpc_reg_operand" "")
10655 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10656 (set (match_operand:SI 4 "gpc_reg_operand" "")
10657 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10658 (set (match_operand:SI 5 "gpc_reg_operand" "")
10659 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10660 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10661 "*
10662 { return rs6000_output_load_multiple (operands); }"
10663 [(set_attr "type" "load_ux")
10664 (set_attr "length" "32")])
10666 (define_insn "*ldmsi3"
10667 [(match_parallel 0 "load_multiple_operation"
10668 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10669 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10670 (set (match_operand:SI 3 "gpc_reg_operand" "")
10671 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10672 (set (match_operand:SI 4 "gpc_reg_operand" "")
10673 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10674 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10675 "*
10676 { return rs6000_output_load_multiple (operands); }"
10677 [(set_attr "type" "load_ux")
10678 (set_attr "length" "32")])
10680 (define_expand "store_multiple"
10681 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10682 (match_operand:SI 1 "" ""))
10683 (clobber (scratch:SI))
10684 (use (match_operand:SI 2 "" ""))])]
10685 "TARGET_STRING && !TARGET_POWERPC64"
10686 "
10687 {
10688 int regno;
10689 int count;
10690 rtx to;
10691 rtx op0;
10692 int i;
10694 /* Support only storing a constant number of fixed-point registers to
10695 memory and only bother with this if more than two; the machine
10696 doesn't support more than eight. */
10697 if (GET_CODE (operands[2]) != CONST_INT
10698 || INTVAL (operands[2]) <= 2
10699 || INTVAL (operands[2]) > 8
10700 || GET_CODE (operands[0]) != MEM
10701 || GET_CODE (operands[1]) != REG
10702 || REGNO (operands[1]) >= 32)
10703 FAIL;
10705 count = INTVAL (operands[2]);
10706 regno = REGNO (operands[1]);
10708 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10709 to = force_reg (SImode, XEXP (operands[0], 0));
10710 op0 = replace_equiv_address (operands[0], to);
10712 XVECEXP (operands[3], 0, 0)
10713 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10714 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10715 gen_rtx_SCRATCH (SImode));
10717 for (i = 1; i < count; i++)
10718 XVECEXP (operands[3], 0, i + 1)
10719 = gen_rtx_SET (VOIDmode,
10720 adjust_address_nv (op0, SImode, i * 4),
10721 gen_rtx_REG (SImode, regno + i));
10722 }")
10724 (define_insn "*stmsi8"
10725 [(match_parallel 0 "store_multiple_operation"
10726 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10727 (match_operand:SI 2 "gpc_reg_operand" "r"))
10728 (clobber (match_scratch:SI 3 "=X"))
10729 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10730 (match_operand:SI 4 "gpc_reg_operand" "r"))
10731 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10732 (match_operand:SI 5 "gpc_reg_operand" "r"))
10733 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10734 (match_operand:SI 6 "gpc_reg_operand" "r"))
10735 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10736 (match_operand:SI 7 "gpc_reg_operand" "r"))
10737 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10738 (match_operand:SI 8 "gpc_reg_operand" "r"))
10739 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10740 (match_operand:SI 9 "gpc_reg_operand" "r"))
10741 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10742 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10743 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
10744 "stswi %2,%1,%O0"
10745 [(set_attr "type" "store_ux")
10746 (set_attr "cell_micro" "always")])
10748 (define_insn "*stmsi7"
10749 [(match_parallel 0 "store_multiple_operation"
10750 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10751 (match_operand:SI 2 "gpc_reg_operand" "r"))
10752 (clobber (match_scratch:SI 3 "=X"))
10753 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10754 (match_operand:SI 4 "gpc_reg_operand" "r"))
10755 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10756 (match_operand:SI 5 "gpc_reg_operand" "r"))
10757 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10758 (match_operand:SI 6 "gpc_reg_operand" "r"))
10759 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10760 (match_operand:SI 7 "gpc_reg_operand" "r"))
10761 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10762 (match_operand:SI 8 "gpc_reg_operand" "r"))
10763 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10764 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10765 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10766 "stswi %2,%1,%O0"
10767 [(set_attr "type" "store_ux")
10768 (set_attr "cell_micro" "always")])
10770 (define_insn "*stmsi6"
10771 [(match_parallel 0 "store_multiple_operation"
10772 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10773 (match_operand:SI 2 "gpc_reg_operand" "r"))
10774 (clobber (match_scratch:SI 3 "=X"))
10775 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10776 (match_operand:SI 4 "gpc_reg_operand" "r"))
10777 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10778 (match_operand:SI 5 "gpc_reg_operand" "r"))
10779 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10780 (match_operand:SI 6 "gpc_reg_operand" "r"))
10781 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10782 (match_operand:SI 7 "gpc_reg_operand" "r"))
10783 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10784 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10785 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10786 "stswi %2,%1,%O0"
10787 [(set_attr "type" "store_ux")
10788 (set_attr "cell_micro" "always")])
10790 (define_insn "*stmsi5"
10791 [(match_parallel 0 "store_multiple_operation"
10792 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10793 (match_operand:SI 2 "gpc_reg_operand" "r"))
10794 (clobber (match_scratch:SI 3 "=X"))
10795 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10796 (match_operand:SI 4 "gpc_reg_operand" "r"))
10797 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10798 (match_operand:SI 5 "gpc_reg_operand" "r"))
10799 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10800 (match_operand:SI 6 "gpc_reg_operand" "r"))
10801 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10802 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10803 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10804 "stswi %2,%1,%O0"
10805 [(set_attr "type" "store_ux")
10806 (set_attr "cell_micro" "always")])
10808 (define_insn "*stmsi4"
10809 [(match_parallel 0 "store_multiple_operation"
10810 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10811 (match_operand:SI 2 "gpc_reg_operand" "r"))
10812 (clobber (match_scratch:SI 3 "=X"))
10813 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10814 (match_operand:SI 4 "gpc_reg_operand" "r"))
10815 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10816 (match_operand:SI 5 "gpc_reg_operand" "r"))
10817 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10818 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10819 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10820 "stswi %2,%1,%O0"
10821 [(set_attr "type" "store_ux")
10822 (set_attr "cell_micro" "always")])
10824 (define_insn "*stmsi3"
10825 [(match_parallel 0 "store_multiple_operation"
10826 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10827 (match_operand:SI 2 "gpc_reg_operand" "r"))
10828 (clobber (match_scratch:SI 3 "=X"))
10829 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10830 (match_operand:SI 4 "gpc_reg_operand" "r"))
10831 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10832 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10833 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10834 "stswi %2,%1,%O0"
10835 [(set_attr "type" "store_ux")
10836 (set_attr "cell_micro" "always")])
10837 \f
10838 (define_expand "setmemsi"
10839 [(parallel [(set (match_operand:BLK 0 "" "")
10840 (match_operand 2 "const_int_operand" ""))
10841 (use (match_operand:SI 1 "" ""))
10842 (use (match_operand:SI 3 "" ""))])]
10843 ""
10844 "
10845 {
10846 /* If value to set is not zero, use the library routine. */
10847 if (operands[2] != const0_rtx)
10848 FAIL;
10850 if (expand_block_clear (operands))
10851 DONE;
10852 else
10853 FAIL;
10854 }")
10856 ;; String/block move insn.
10857 ;; Argument 0 is the destination
10858 ;; Argument 1 is the source
10859 ;; Argument 2 is the length
10860 ;; Argument 3 is the alignment
10862 (define_expand "movmemsi"
10863 [(parallel [(set (match_operand:BLK 0 "" "")
10864 (match_operand:BLK 1 "" ""))
10865 (use (match_operand:SI 2 "" ""))
10866 (use (match_operand:SI 3 "" ""))])]
10867 ""
10868 "
10869 {
10870 if (expand_block_move (operands))
10871 DONE;
10872 else
10873 FAIL;
10874 }")
10876 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10877 ;; register allocator doesn't have a clue about allocating 8 word registers.
10878 ;; rD/rS = r5 is preferred, efficient form.
10879 (define_expand "movmemsi_8reg"
10880 [(parallel [(set (match_operand 0 "" "")
10881 (match_operand 1 "" ""))
10882 (use (match_operand 2 "" ""))
10883 (use (match_operand 3 "" ""))
10884 (clobber (reg:SI 5))
10885 (clobber (reg:SI 6))
10886 (clobber (reg:SI 7))
10887 (clobber (reg:SI 8))
10888 (clobber (reg:SI 9))
10889 (clobber (reg:SI 10))
10890 (clobber (reg:SI 11))
10891 (clobber (reg:SI 12))
10892 (clobber (match_scratch:SI 4 ""))])]
10893 "TARGET_STRING"
10894 "")
10896 (define_insn ""
10897 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10898 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10899 (use (match_operand:SI 2 "immediate_operand" "i"))
10900 (use (match_operand:SI 3 "immediate_operand" "i"))
10901 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10902 (clobber (reg:SI 6))
10903 (clobber (reg:SI 7))
10904 (clobber (reg:SI 8))
10905 (clobber (reg:SI 9))
10906 (clobber (reg:SI 10))
10907 (clobber (reg:SI 11))
10908 (clobber (reg:SI 12))
10909 (clobber (match_scratch:SI 5 "=X"))]
10910 "TARGET_STRING
10911 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10912 || INTVAL (operands[2]) == 0)
10913 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10914 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10915 && REGNO (operands[4]) == 5"
10916 "lswi %4,%1,%2\;stswi %4,%0,%2"
10917 [(set_attr "type" "store_ux")
10918 (set_attr "cell_micro" "always")
10919 (set_attr "length" "8")])
10921 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10922 ;; register allocator doesn't have a clue about allocating 6 word registers.
10923 ;; rD/rS = r5 is preferred, efficient form.
10924 (define_expand "movmemsi_6reg"
10925 [(parallel [(set (match_operand 0 "" "")
10926 (match_operand 1 "" ""))
10927 (use (match_operand 2 "" ""))
10928 (use (match_operand 3 "" ""))
10929 (clobber (reg:SI 5))
10930 (clobber (reg:SI 6))
10931 (clobber (reg:SI 7))
10932 (clobber (reg:SI 8))
10933 (clobber (reg:SI 9))
10934 (clobber (reg:SI 10))
10935 (clobber (match_scratch:SI 4 ""))])]
10936 "TARGET_STRING"
10937 "")
10939 (define_insn ""
10940 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10941 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10942 (use (match_operand:SI 2 "immediate_operand" "i"))
10943 (use (match_operand:SI 3 "immediate_operand" "i"))
10944 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10945 (clobber (reg:SI 6))
10946 (clobber (reg:SI 7))
10947 (clobber (reg:SI 8))
10948 (clobber (reg:SI 9))
10949 (clobber (reg:SI 10))
10950 (clobber (match_scratch:SI 5 "=X"))]
10951 "TARGET_STRING
10952 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10953 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10954 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10955 && REGNO (operands[4]) == 5"
10956 "lswi %4,%1,%2\;stswi %4,%0,%2"
10957 [(set_attr "type" "store_ux")
10958 (set_attr "cell_micro" "always")
10959 (set_attr "length" "8")])
10961 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10962 ;; problems with TImode.
10963 ;; rD/rS = r5 is preferred, efficient form.
10964 (define_expand "movmemsi_4reg"
10965 [(parallel [(set (match_operand 0 "" "")
10966 (match_operand 1 "" ""))
10967 (use (match_operand 2 "" ""))
10968 (use (match_operand 3 "" ""))
10969 (clobber (reg:SI 5))
10970 (clobber (reg:SI 6))
10971 (clobber (reg:SI 7))
10972 (clobber (reg:SI 8))
10973 (clobber (match_scratch:SI 4 ""))])]
10974 "TARGET_STRING"
10975 "")
10977 (define_insn ""
10978 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10979 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10980 (use (match_operand:SI 2 "immediate_operand" "i"))
10981 (use (match_operand:SI 3 "immediate_operand" "i"))
10982 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10983 (clobber (reg:SI 6))
10984 (clobber (reg:SI 7))
10985 (clobber (reg:SI 8))
10986 (clobber (match_scratch:SI 5 "=X"))]
10987 "TARGET_STRING
10988 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10989 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10990 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10991 && REGNO (operands[4]) == 5"
10992 "lswi %4,%1,%2\;stswi %4,%0,%2"
10993 [(set_attr "type" "store_ux")
10994 (set_attr "cell_micro" "always")
10995 (set_attr "length" "8")])
10997 ;; Move up to 8 bytes at a time.
10998 (define_expand "movmemsi_2reg"
10999 [(parallel [(set (match_operand 0 "" "")
11000 (match_operand 1 "" ""))
11001 (use (match_operand 2 "" ""))
11002 (use (match_operand 3 "" ""))
11003 (clobber (match_scratch:DI 4 ""))
11004 (clobber (match_scratch:SI 5 ""))])]
11005 "TARGET_STRING && ! TARGET_POWERPC64"
11006 "")
11008 (define_insn ""
11009 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11010 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11011 (use (match_operand:SI 2 "immediate_operand" "i"))
11012 (use (match_operand:SI 3 "immediate_operand" "i"))
11013 (clobber (match_scratch:DI 4 "=&r"))
11014 (clobber (match_scratch:SI 5 "=X"))]
11015 "TARGET_STRING && ! TARGET_POWERPC64
11016 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11017 "lswi %4,%1,%2\;stswi %4,%0,%2"
11018 [(set_attr "type" "store_ux")
11019 (set_attr "cell_micro" "always")
11020 (set_attr "length" "8")])
11022 ;; Move up to 4 bytes at a time.
11023 (define_expand "movmemsi_1reg"
11024 [(parallel [(set (match_operand 0 "" "")
11025 (match_operand 1 "" ""))
11026 (use (match_operand 2 "" ""))
11027 (use (match_operand 3 "" ""))
11028 (clobber (match_scratch:SI 4 ""))
11029 (clobber (match_scratch:SI 5 ""))])]
11030 "TARGET_STRING"
11031 "")
11033 (define_insn ""
11034 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11035 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11036 (use (match_operand:SI 2 "immediate_operand" "i"))
11037 (use (match_operand:SI 3 "immediate_operand" "i"))
11038 (clobber (match_scratch:SI 4 "=&r"))
11039 (clobber (match_scratch:SI 5 "=X"))]
11040 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11041 "lswi %4,%1,%2\;stswi %4,%0,%2"
11042 [(set_attr "type" "store_ux")
11043 (set_attr "cell_micro" "always")
11044 (set_attr "length" "8")])
11045 \f
11046 ;; Define insns that do load or store with update. Some of these we can
11047 ;; get by using pre-decrement or pre-increment, but the hardware can also
11048 ;; do cases where the increment is not the size of the object.
11049 ;;
11050 ;; In all these cases, we use operands 0 and 1 for the register being
11051 ;; incremented because those are the operands that local-alloc will
11052 ;; tie and these are the pair most likely to be tieable (and the ones
11053 ;; that will benefit the most).
11055 (define_insn "*movdi_update1"
11056 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
11057 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
11058 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
11059 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
11060 (plus:DI (match_dup 1) (match_dup 2)))]
11061 "TARGET_POWERPC64 && TARGET_UPDATE
11062 && (!avoiding_indexed_address_p (DImode)
11063 || !gpc_reg_operand (operands[2], DImode))"
11064 "@
11065 ldux %3,%0,%2
11066 ldu %3,%2(%0)"
11067 [(set_attr "type" "load_ux,load_u")])
11069 (define_insn "movdi_<mode>_update"
11070 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11071 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11072 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11073 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11074 (plus:P (match_dup 1) (match_dup 2)))]
11075 "TARGET_POWERPC64 && TARGET_UPDATE
11076 && (!avoiding_indexed_address_p (Pmode)
11077 || !gpc_reg_operand (operands[2], Pmode)
11078 || (REG_P (operands[0])
11079 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11080 "@
11081 stdux %3,%0,%2
11082 stdu %3,%2(%0)"
11083 [(set_attr "type" "store_ux,store_u")])
11085 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
11086 ;; needed for stack allocation, even if the user passes -mno-update.
11087 (define_insn "movdi_<mode>_update_stack"
11088 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11089 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11090 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11091 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11092 (plus:P (match_dup 1) (match_dup 2)))]
11093 "TARGET_POWERPC64"
11094 "@
11095 stdux %3,%0,%2
11096 stdu %3,%2(%0)"
11097 [(set_attr "type" "store_ux,store_u")])
11099 (define_insn "*movsi_update1"
11100 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11101 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11102 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11103 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11104 (plus:SI (match_dup 1) (match_dup 2)))]
11105 "TARGET_UPDATE
11106 && (!avoiding_indexed_address_p (SImode)
11107 || !gpc_reg_operand (operands[2], SImode))"
11108 "@
11109 lwzux %3,%0,%2
11110 lwzu %3,%2(%0)"
11111 [(set_attr "type" "load_ux,load_u")])
11113 (define_insn "*movsi_update2"
11114 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
11115 (sign_extend:DI
11116 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
11117 (match_operand:DI 2 "gpc_reg_operand" "r")))))
11118 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
11119 (plus:DI (match_dup 1) (match_dup 2)))]
11120 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
11121 && !avoiding_indexed_address_p (DImode)"
11122 "lwaux %3,%0,%2"
11123 [(set_attr "type" "load_ext_ux")])
11125 (define_insn "movsi_update"
11126 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11127 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11128 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11129 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11130 (plus:SI (match_dup 1) (match_dup 2)))]
11131 "TARGET_UPDATE
11132 && (!avoiding_indexed_address_p (SImode)
11133 || !gpc_reg_operand (operands[2], SImode)
11134 || (REG_P (operands[0])
11135 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11136 "@
11137 stwux %3,%0,%2
11138 stwu %3,%2(%0)"
11139 [(set_attr "type" "store_ux,store_u")])
11141 ;; This is an unconditional pattern; needed for stack allocation, even
11142 ;; if the user passes -mno-update.
11143 (define_insn "movsi_update_stack"
11144 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11145 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11146 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11147 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11148 (plus:SI (match_dup 1) (match_dup 2)))]
11149 ""
11150 "@
11151 stwux %3,%0,%2
11152 stwu %3,%2(%0)"
11153 [(set_attr "type" "store_ux,store_u")])
11155 (define_insn "*movhi_update1"
11156 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
11157 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11158 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11159 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11160 (plus:SI (match_dup 1) (match_dup 2)))]
11161 "TARGET_UPDATE
11162 && (!avoiding_indexed_address_p (SImode)
11163 || !gpc_reg_operand (operands[2], SImode))"
11164 "@
11165 lhzux %3,%0,%2
11166 lhzu %3,%2(%0)"
11167 [(set_attr "type" "load_ux,load_u")])
11169 (define_insn "*movhi_update2"
11170 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11171 (zero_extend:SI
11172 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11173 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11174 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11175 (plus:SI (match_dup 1) (match_dup 2)))]
11176 "TARGET_UPDATE
11177 && (!avoiding_indexed_address_p (SImode)
11178 || !gpc_reg_operand (operands[2], SImode))"
11179 "@
11180 lhzux %3,%0,%2
11181 lhzu %3,%2(%0)"
11182 [(set_attr "type" "load_ux,load_u")])
11184 (define_insn "*movhi_update3"
11185 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11186 (sign_extend:SI
11187 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11188 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11189 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11190 (plus:SI (match_dup 1) (match_dup 2)))]
11191 "TARGET_UPDATE && rs6000_gen_cell_microcode
11192 && (!avoiding_indexed_address_p (SImode)
11193 || !gpc_reg_operand (operands[2], SImode))"
11194 "@
11195 lhaux %3,%0,%2
11196 lhau %3,%2(%0)"
11197 [(set_attr "type" "load_ext_ux,load_ext_u")])
11199 (define_insn "*movhi_update4"
11200 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11201 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11202 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
11203 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11204 (plus:SI (match_dup 1) (match_dup 2)))]
11205 "TARGET_UPDATE
11206 && (!avoiding_indexed_address_p (SImode)
11207 || !gpc_reg_operand (operands[2], SImode))"
11208 "@
11209 sthux %3,%0,%2
11210 sthu %3,%2(%0)"
11211 [(set_attr "type" "store_ux,store_u")])
11213 (define_insn "*movqi_update1"
11214 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
11215 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11216 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11217 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11218 (plus:SI (match_dup 1) (match_dup 2)))]
11219 "TARGET_UPDATE
11220 && (!avoiding_indexed_address_p (SImode)
11221 || !gpc_reg_operand (operands[2], SImode))"
11222 "@
11223 lbzux %3,%0,%2
11224 lbzu %3,%2(%0)"
11225 [(set_attr "type" "load_ux,load_u")])
11227 (define_insn "*movqi_update2"
11228 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11229 (zero_extend:SI
11230 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11231 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11232 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11233 (plus:SI (match_dup 1) (match_dup 2)))]
11234 "TARGET_UPDATE
11235 && (!avoiding_indexed_address_p (SImode)
11236 || !gpc_reg_operand (operands[2], SImode))"
11237 "@
11238 lbzux %3,%0,%2
11239 lbzu %3,%2(%0)"
11240 [(set_attr "type" "load_ux,load_u")])
11242 (define_insn "*movqi_update3"
11243 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11244 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11245 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
11246 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11247 (plus:SI (match_dup 1) (match_dup 2)))]
11248 "TARGET_UPDATE
11249 && (!avoiding_indexed_address_p (SImode)
11250 || !gpc_reg_operand (operands[2], SImode))"
11251 "@
11252 stbux %3,%0,%2
11253 stbu %3,%2(%0)"
11254 [(set_attr "type" "store_ux,store_u")])
11256 (define_insn "*movsf_update1"
11257 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
11258 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11259 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11260 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11261 (plus:SI (match_dup 1) (match_dup 2)))]
11262 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11263 && (!avoiding_indexed_address_p (SImode)
11264 || !gpc_reg_operand (operands[2], SImode))"
11265 "@
11266 lfsux %3,%0,%2
11267 lfsu %3,%2(%0)"
11268 [(set_attr "type" "fpload_ux,fpload_u")])
11270 (define_insn "*movsf_update2"
11271 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11272 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11273 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
11274 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11275 (plus:SI (match_dup 1) (match_dup 2)))]
11276 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11277 && (!avoiding_indexed_address_p (SImode)
11278 || !gpc_reg_operand (operands[2], SImode))"
11279 "@
11280 stfsux %3,%0,%2
11281 stfsu %3,%2(%0)"
11282 [(set_attr "type" "fpstore_ux,fpstore_u")])
11284 (define_insn "*movsf_update3"
11285 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
11286 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11287 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11288 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11289 (plus:SI (match_dup 1) (match_dup 2)))]
11290 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11291 && (!avoiding_indexed_address_p (SImode)
11292 || !gpc_reg_operand (operands[2], SImode))"
11293 "@
11294 lwzux %3,%0,%2
11295 lwzu %3,%2(%0)"
11296 [(set_attr "type" "load_ux,load_u")])
11298 (define_insn "*movsf_update4"
11299 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11300 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11301 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
11302 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11303 (plus:SI (match_dup 1) (match_dup 2)))]
11304 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11305 && (!avoiding_indexed_address_p (SImode)
11306 || !gpc_reg_operand (operands[2], SImode))"
11307 "@
11308 stwux %3,%0,%2
11309 stwu %3,%2(%0)"
11310 [(set_attr "type" "store_ux,store_u")])
11312 (define_insn "*movdf_update1"
11313 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
11314 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11315 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11316 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11317 (plus:SI (match_dup 1) (match_dup 2)))]
11318 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11319 && (!avoiding_indexed_address_p (SImode)
11320 || !gpc_reg_operand (operands[2], SImode))"
11321 "@
11322 lfdux %3,%0,%2
11323 lfdu %3,%2(%0)"
11324 [(set_attr "type" "fpload_ux,fpload_u")])
11326 (define_insn "*movdf_update2"
11327 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11328 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11329 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
11330 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11331 (plus:SI (match_dup 1) (match_dup 2)))]
11332 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11333 && (!avoiding_indexed_address_p (SImode)
11334 || !gpc_reg_operand (operands[2], SImode))"
11335 "@
11336 stfdux %3,%0,%2
11337 stfdu %3,%2(%0)"
11338 [(set_attr "type" "fpstore_ux,fpstore_u")])
11341 ;; After inserting conditional returns we can sometimes have
11342 ;; unnecessary register moves. Unfortunately we cannot have a
11343 ;; modeless peephole here, because some single SImode sets have early
11344 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11345 ;; sequences, using get_attr_length here will smash the operands
11346 ;; array. Neither is there an early_cobbler_p predicate.
11347 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11348 (define_peephole2
11349 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11350 (match_operand:DF 1 "any_operand" ""))
11351 (set (match_operand:DF 2 "gpc_reg_operand" "")
11352 (match_dup 0))]
11353 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11354 && peep2_reg_dead_p (2, operands[0])"
11355 [(set (match_dup 2) (match_dup 1))])
11357 (define_peephole2
11358 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11359 (match_operand:SF 1 "any_operand" ""))
11360 (set (match_operand:SF 2 "gpc_reg_operand" "")
11361 (match_dup 0))]
11362 "peep2_reg_dead_p (2, operands[0])"
11363 [(set (match_dup 2) (match_dup 1))])
11365 \f
11366 ;; TLS support.
11368 ;; Mode attributes for different ABIs.
11369 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11370 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11371 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11372 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11374 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11375 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11376 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11377 (match_operand 4 "" "g")))
11378 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11379 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11380 UNSPEC_TLSGD)
11381 (clobber (reg:SI LR_REGNO))]
11382 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11383 {
11384 if (TARGET_CMODEL != CMODEL_SMALL)
11385 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
11386 "bl %z3\;nop";
11387 else
11388 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
11389 }
11390 "&& TARGET_TLS_MARKERS"
11391 [(set (match_dup 0)
11392 (unspec:TLSmode [(match_dup 1)
11393 (match_dup 2)]
11394 UNSPEC_TLSGD))
11395 (parallel [(set (match_dup 0)
11396 (call (mem:TLSmode (match_dup 3))
11397 (match_dup 4)))
11398 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11399 (clobber (reg:SI LR_REGNO))])]
11400 ""
11401 [(set_attr "type" "two")
11402 (set (attr "length")
11403 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11404 (const_int 16)
11405 (const_int 12)))])
11407 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11408 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11409 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11410 (match_operand 4 "" "g")))
11411 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11412 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11413 UNSPEC_TLSGD)
11414 (clobber (reg:SI LR_REGNO))]
11415 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11416 {
11417 if (flag_pic)
11418 {
11419 if (TARGET_SECURE_PLT && flag_pic == 2)
11420 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11421 else
11422 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11423 }
11424 else
11425 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11426 }
11427 "&& TARGET_TLS_MARKERS"
11428 [(set (match_dup 0)
11429 (unspec:TLSmode [(match_dup 1)
11430 (match_dup 2)]
11431 UNSPEC_TLSGD))
11432 (parallel [(set (match_dup 0)
11433 (call (mem:TLSmode (match_dup 3))
11434 (match_dup 4)))
11435 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11436 (clobber (reg:SI LR_REGNO))])]
11437 ""
11438 [(set_attr "type" "two")
11439 (set_attr "length" "8")])
11441 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11442 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11443 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11444 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11445 UNSPEC_TLSGD))]
11446 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11447 "addi %0,%1,%2@got@tlsgd"
11448 "&& TARGET_CMODEL != CMODEL_SMALL"
11449 [(set (match_dup 3)
11450 (high:TLSmode
11451 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
11452 (set (match_dup 0)
11453 (lo_sum:TLSmode (match_dup 3)
11454 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
11455 "
11456 {
11457 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11458 }"
11459 [(set (attr "length")
11460 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11461 (const_int 8)
11462 (const_int 4)))])
11464 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11465 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11466 (high:TLSmode
11467 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11468 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11469 UNSPEC_TLSGD)))]
11470 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11471 "addis %0,%1,%2@got@tlsgd@ha"
11472 [(set_attr "length" "4")])
11474 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11475 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11476 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11477 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11478 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11479 UNSPEC_TLSGD)))]
11480 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11481 "addi %0,%1,%2@got@tlsgd@l"
11482 [(set_attr "length" "4")])
11484 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11485 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11486 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11487 (match_operand 2 "" "g")))
11488 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11489 UNSPEC_TLSGD)
11490 (clobber (reg:SI LR_REGNO))]
11491 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11492 "bl %z1(%3@tlsgd)\;nop"
11493 [(set_attr "type" "branch")
11494 (set_attr "length" "8")])
11496 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11497 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11498 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11499 (match_operand 2 "" "g")))
11500 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11501 UNSPEC_TLSGD)
11502 (clobber (reg:SI LR_REGNO))]
11503 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11504 {
11505 if (flag_pic)
11506 {
11507 if (TARGET_SECURE_PLT && flag_pic == 2)
11508 return "bl %z1+32768(%3@tlsgd)@plt";
11509 return "bl %z1(%3@tlsgd)@plt";
11510 }
11511 return "bl %z1(%3@tlsgd)";
11512 }
11513 [(set_attr "type" "branch")
11514 (set_attr "length" "4")])
11516 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11517 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11518 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11519 (match_operand 3 "" "g")))
11520 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11521 UNSPEC_TLSLD)
11522 (clobber (reg:SI LR_REGNO))]
11523 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11524 {
11525 if (TARGET_CMODEL != CMODEL_SMALL)
11526 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
11527 "bl %z2\;nop";
11528 else
11529 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
11530 }
11531 "&& TARGET_TLS_MARKERS"
11532 [(set (match_dup 0)
11533 (unspec:TLSmode [(match_dup 1)]
11534 UNSPEC_TLSLD))
11535 (parallel [(set (match_dup 0)
11536 (call (mem:TLSmode (match_dup 2))
11537 (match_dup 3)))
11538 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11539 (clobber (reg:SI LR_REGNO))])]
11540 ""
11541 [(set_attr "type" "two")
11542 (set (attr "length")
11543 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11544 (const_int 16)
11545 (const_int 12)))])
11547 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11548 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11549 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11550 (match_operand 3 "" "g")))
11551 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11552 UNSPEC_TLSLD)
11553 (clobber (reg:SI LR_REGNO))]
11554 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11555 {
11556 if (flag_pic)
11557 {
11558 if (TARGET_SECURE_PLT && flag_pic == 2)
11559 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11560 else
11561 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11562 }
11563 else
11564 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11565 }
11566 "&& TARGET_TLS_MARKERS"
11567 [(set (match_dup 0)
11568 (unspec:TLSmode [(match_dup 1)]
11569 UNSPEC_TLSLD))
11570 (parallel [(set (match_dup 0)
11571 (call (mem:TLSmode (match_dup 2))
11572 (match_dup 3)))
11573 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11574 (clobber (reg:SI LR_REGNO))])]
11575 ""
11576 [(set_attr "length" "8")])
11578 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11579 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11580 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11581 UNSPEC_TLSLD))]
11582 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11583 "addi %0,%1,%&@got@tlsld"
11584 "&& TARGET_CMODEL != CMODEL_SMALL"
11585 [(set (match_dup 2)
11586 (high:TLSmode
11587 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
11588 (set (match_dup 0)
11589 (lo_sum:TLSmode (match_dup 2)
11590 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
11591 "
11592 {
11593 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11594 }"
11595 [(set (attr "length")
11596 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11597 (const_int 8)
11598 (const_int 4)))])
11600 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11601 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11602 (high:TLSmode
11603 (unspec:TLSmode [(const_int 0)
11604 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11605 UNSPEC_TLSLD)))]
11606 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11607 "addis %0,%1,%&@got@tlsld@ha"
11608 [(set_attr "length" "4")])
11610 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11611 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11612 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11613 (unspec:TLSmode [(const_int 0)
11614 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
11615 UNSPEC_TLSLD)))]
11616 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11617 "addi %0,%1,%&@got@tlsld@l"
11618 [(set_attr "length" "4")])
11620 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11621 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11622 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11623 (match_operand 2 "" "g")))
11624 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11625 (clobber (reg:SI LR_REGNO))]
11626 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11627 "bl %z1(%&@tlsld)\;nop"
11628 [(set_attr "type" "branch")
11629 (set_attr "length" "8")])
11631 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11632 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11633 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11634 (match_operand 2 "" "g")))
11635 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11636 (clobber (reg:SI LR_REGNO))]
11637 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11638 {
11639 if (flag_pic)
11640 {
11641 if (TARGET_SECURE_PLT && flag_pic == 2)
11642 return "bl %z1+32768(%&@tlsld)@plt";
11643 return "bl %z1(%&@tlsld)@plt";
11644 }
11645 return "bl %z1(%&@tlsld)";
11646 }
11647 [(set_attr "type" "branch")
11648 (set_attr "length" "4")])
11650 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11651 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11652 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11653 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11654 UNSPEC_TLSDTPREL))]
11655 "HAVE_AS_TLS"
11656 "addi %0,%1,%2@dtprel")
11658 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11659 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11660 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11661 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11662 UNSPEC_TLSDTPRELHA))]
11663 "HAVE_AS_TLS"
11664 "addis %0,%1,%2@dtprel@ha")
11666 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11667 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11668 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11669 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11670 UNSPEC_TLSDTPRELLO))]
11671 "HAVE_AS_TLS"
11672 "addi %0,%1,%2@dtprel@l")
11674 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11675 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11676 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11677 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11678 UNSPEC_TLSGOTDTPREL))]
11679 "HAVE_AS_TLS"
11680 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11681 "&& TARGET_CMODEL != CMODEL_SMALL"
11682 [(set (match_dup 3)
11683 (high:TLSmode
11684 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
11685 (set (match_dup 0)
11686 (lo_sum:TLSmode (match_dup 3)
11687 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11688 "
11689 {
11690 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11691 }"
11692 [(set (attr "length")
11693 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11694 (const_int 8)
11695 (const_int 4)))])
11697 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11698 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11699 (high:TLSmode
11700 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11701 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11702 UNSPEC_TLSGOTDTPREL)))]
11703 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11704 "addis %0,%1,%2@got@dtprel@ha"
11705 [(set_attr "length" "4")])
11707 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11708 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11709 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11710 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11711 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11712 UNSPEC_TLSGOTDTPREL)))]
11713 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11714 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11715 [(set_attr "length" "4")])
11717 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11718 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11719 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11720 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11721 UNSPEC_TLSTPREL))]
11722 "HAVE_AS_TLS"
11723 "addi %0,%1,%2@tprel")
11725 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11726 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11727 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11728 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11729 UNSPEC_TLSTPRELHA))]
11730 "HAVE_AS_TLS"
11731 "addis %0,%1,%2@tprel@ha")
11733 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11734 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11735 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11736 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11737 UNSPEC_TLSTPRELLO))]
11738 "HAVE_AS_TLS"
11739 "addi %0,%1,%2@tprel@l")
11741 ;; "b" output constraint here and on tls_tls input to support linker tls
11742 ;; optimization. The linker may edit the instructions emitted by a
11743 ;; tls_got_tprel/tls_tls pair to addis,addi.
11744 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11745 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11746 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11747 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11748 UNSPEC_TLSGOTTPREL))]
11749 "HAVE_AS_TLS"
11750 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11751 "&& TARGET_CMODEL != CMODEL_SMALL"
11752 [(set (match_dup 3)
11753 (high:TLSmode
11754 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
11755 (set (match_dup 0)
11756 (lo_sum:TLSmode (match_dup 3)
11757 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11758 "
11759 {
11760 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11761 }"
11762 [(set (attr "length")
11763 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11764 (const_int 8)
11765 (const_int 4)))])
11767 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11768 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11769 (high:TLSmode
11770 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11771 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11772 UNSPEC_TLSGOTTPREL)))]
11773 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11774 "addis %0,%1,%2@got@tprel@ha"
11775 [(set_attr "length" "4")])
11777 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11778 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11779 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11780 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11781 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11782 UNSPEC_TLSGOTTPREL)))]
11783 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11784 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11785 [(set_attr "length" "4")])
11787 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11788 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11789 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11790 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11791 UNSPEC_TLSTLS))]
11792 "TARGET_ELF && HAVE_AS_TLS"
11793 "add %0,%1,%2@tls")
11795 (define_expand "tls_get_tpointer"
11796 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11797 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
11798 "TARGET_XCOFF && HAVE_AS_TLS"
11799 "
11800 {
11801 emit_insn (gen_tls_get_tpointer_internal ());
11802 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
11803 DONE;
11804 }")
11806 (define_insn "tls_get_tpointer_internal"
11807 [(set (reg:SI 3)
11808 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
11809 (clobber (reg:SI LR_REGNO))]
11810 "TARGET_XCOFF && HAVE_AS_TLS"
11811 "bla __get_tpointer")
11813 (define_expand "tls_get_addr<mode>"
11814 [(set (match_operand:P 0 "gpc_reg_operand" "")
11815 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
11816 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
11817 "TARGET_XCOFF && HAVE_AS_TLS"
11818 "
11819 {
11820 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
11821 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
11822 emit_insn (gen_tls_get_addr_internal<mode> ());
11823 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
11824 DONE;
11825 }")
11827 (define_insn "tls_get_addr_internal<mode>"
11828 [(set (reg:P 3)
11829 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
11830 (clobber (reg:P 0))
11831 (clobber (reg:P 4))
11832 (clobber (reg:P 5))
11833 (clobber (reg:P 11))
11834 (clobber (reg:CC CR0_REGNO))
11835 (clobber (reg:P LR_REGNO))]
11836 "TARGET_XCOFF && HAVE_AS_TLS"
11837 "bla __tls_get_addr")
11838 \f
11839 ;; Next come insns related to the calling sequence.
11840 ;;
11841 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11842 ;; We move the back-chain and decrement the stack pointer.
11844 (define_expand "allocate_stack"
11845 [(set (match_operand 0 "gpc_reg_operand" "")
11846 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11847 (set (reg 1)
11848 (minus (reg 1) (match_dup 1)))]
11849 ""
11850 "
11851 { rtx chain = gen_reg_rtx (Pmode);
11852 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11853 rtx neg_op0;
11854 rtx insn, par, set, mem;
11856 emit_move_insn (chain, stack_bot);
11858 /* Check stack bounds if necessary. */
11859 if (crtl->limit_stack)
11860 {
11861 rtx available;
11862 available = expand_binop (Pmode, sub_optab,
11863 stack_pointer_rtx, stack_limit_rtx,
11864 NULL_RTX, 1, OPTAB_WIDEN);
11865 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11866 }
11868 if (GET_CODE (operands[1]) != CONST_INT
11869 || INTVAL (operands[1]) < -32767
11870 || INTVAL (operands[1]) > 32768)
11871 {
11872 neg_op0 = gen_reg_rtx (Pmode);
11873 if (TARGET_32BIT)
11874 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11875 else
11876 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11877 }
11878 else
11879 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11881 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11882 : gen_movdi_di_update_stack))
11883 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11884 chain));
11885 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11886 it now and set the alias set/attributes. The above gen_*_update
11887 calls will generate a PARALLEL with the MEM set being the first
11888 operation. */
11889 par = PATTERN (insn);
11890 gcc_assert (GET_CODE (par) == PARALLEL);
11891 set = XVECEXP (par, 0, 0);
11892 gcc_assert (GET_CODE (set) == SET);
11893 mem = SET_DEST (set);
11894 gcc_assert (MEM_P (mem));
11895 MEM_NOTRAP_P (mem) = 1;
11896 set_mem_alias_set (mem, get_frame_alias_set ());
11898 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11899 DONE;
11900 }")
11902 ;; These patterns say how to save and restore the stack pointer. We need not
11903 ;; save the stack pointer at function level since we are careful to
11904 ;; preserve the backchain. At block level, we have to restore the backchain
11905 ;; when we restore the stack pointer.
11906 ;;
11907 ;; For nonlocal gotos, we must save both the stack pointer and its
11908 ;; backchain and restore both. Note that in the nonlocal case, the
11909 ;; save area is a memory location.
11911 (define_expand "save_stack_function"
11912 [(match_operand 0 "any_operand" "")
11913 (match_operand 1 "any_operand" "")]
11914 ""
11915 "DONE;")
11917 (define_expand "restore_stack_function"
11918 [(match_operand 0 "any_operand" "")
11919 (match_operand 1 "any_operand" "")]
11920 ""
11921 "DONE;")
11923 ;; Adjust stack pointer (op0) to a new value (op1).
11924 ;; First copy old stack backchain to new location, and ensure that the
11925 ;; scheduler won't reorder the sp assignment before the backchain write.
11926 (define_expand "restore_stack_block"
11927 [(set (match_dup 2) (match_dup 3))
11928 (set (match_dup 4) (match_dup 2))
11929 (match_dup 5)
11930 (set (match_operand 0 "register_operand" "")
11931 (match_operand 1 "register_operand" ""))]
11932 ""
11933 "
11934 {
11935 rtvec p;
11937 operands[1] = force_reg (Pmode, operands[1]);
11938 operands[2] = gen_reg_rtx (Pmode);
11939 operands[3] = gen_frame_mem (Pmode, operands[0]);
11940 operands[4] = gen_frame_mem (Pmode, operands[1]);
11941 p = rtvec_alloc (1);
11942 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11943 gen_frame_mem (BLKmode, operands[0]),
11944 const0_rtx);
11945 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
11946 }")
11948 (define_expand "save_stack_nonlocal"
11949 [(set (match_dup 3) (match_dup 4))
11950 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11951 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11952 ""
11953 "
11954 {
11955 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11957 /* Copy the backchain to the first word, sp to the second. */
11958 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11959 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11960 operands[3] = gen_reg_rtx (Pmode);
11961 operands[4] = gen_frame_mem (Pmode, operands[1]);
11962 }")
11964 (define_expand "restore_stack_nonlocal"
11965 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11966 (set (match_dup 3) (match_dup 4))
11967 (set (match_dup 5) (match_dup 2))
11968 (match_dup 6)
11969 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11970 ""
11971 "
11972 {
11973 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11974 rtvec p;
11976 /* Restore the backchain from the first word, sp from the second. */
11977 operands[2] = gen_reg_rtx (Pmode);
11978 operands[3] = gen_reg_rtx (Pmode);
11979 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11980 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11981 operands[5] = gen_frame_mem (Pmode, operands[3]);
11982 p = rtvec_alloc (1);
11983 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11984 gen_frame_mem (BLKmode, operands[0]),
11985 const0_rtx);
11986 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
11987 }")
11988 \f
11989 ;; TOC register handling.
11991 ;; Code to initialize the TOC register...
11993 (define_insn "load_toc_aix_si"
11994 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11995 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11996 (use (reg:SI 2))])]
11997 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11998 "*
11999 {
12000 char buf[30];
12001 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12002 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12003 operands[2] = gen_rtx_REG (Pmode, 2);
12004 return \"lwz %0,%1(%2)\";
12005 }"
12006 [(set_attr "type" "load")])
12008 (define_insn "load_toc_aix_di"
12009 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12010 (unspec:DI [(const_int 0)] UNSPEC_TOC))
12011 (use (reg:DI 2))])]
12012 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
12013 "*
12014 {
12015 char buf[30];
12016 #ifdef TARGET_RELOCATABLE
12017 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
12018 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
12019 #else
12020 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12021 #endif
12022 if (TARGET_ELF)
12023 strcat (buf, \"@toc\");
12024 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12025 operands[2] = gen_rtx_REG (Pmode, 2);
12026 return \"ld %0,%1(%2)\";
12027 }"
12028 [(set_attr "type" "load")])
12030 (define_insn "load_toc_v4_pic_si"
12031 [(set (reg:SI LR_REGNO)
12032 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
12033 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
12034 "bl _GLOBAL_OFFSET_TABLE_@local-4"
12035 [(set_attr "type" "branch")
12036 (set_attr "length" "4")])
12038 (define_expand "load_toc_v4_PIC_1"
12039 [(parallel [(set (reg:SI LR_REGNO)
12040 (match_operand:SI 0 "immediate_operand" "s"))
12041 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
12042 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
12043 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12044 "")
12046 (define_insn "load_toc_v4_PIC_1_normal"
12047 [(set (reg:SI LR_REGNO)
12048 (match_operand:SI 0 "immediate_operand" "s"))
12049 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12050 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
12051 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12052 "bcl 20,31,%0\\n%0:"
12053 [(set_attr "type" "branch")
12054 (set_attr "length" "4")])
12056 (define_insn "load_toc_v4_PIC_1_476"
12057 [(set (reg:SI LR_REGNO)
12058 (match_operand:SI 0 "immediate_operand" "s"))
12059 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12060 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
12061 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12062 "*
12063 {
12064 char name[32];
12065 static char templ[32];
12067 get_ppc476_thunk_name (name);
12068 sprintf (templ, \"bl %s\\n%%0:\", name);
12069 return templ;
12070 }"
12071 [(set_attr "type" "branch")
12072 (set_attr "length" "4")])
12074 (define_expand "load_toc_v4_PIC_1b"
12075 [(parallel [(set (reg:SI LR_REGNO)
12076 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12077 (label_ref (match_operand 1 "" ""))]
12078 UNSPEC_TOCPTR))
12079 (match_dup 1)])]
12080 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12081 "")
12083 (define_insn "load_toc_v4_PIC_1b_normal"
12084 [(set (reg:SI LR_REGNO)
12085 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12086 (label_ref (match_operand 1 "" ""))]
12087 UNSPEC_TOCPTR))
12088 (match_dup 1)]
12089 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12090 "bcl 20,31,$+8\;.long %0-$"
12091 [(set_attr "type" "branch")
12092 (set_attr "length" "8")])
12094 (define_insn "load_toc_v4_PIC_1b_476"
12095 [(set (reg:SI LR_REGNO)
12096 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12097 (label_ref (match_operand 1 "" ""))]
12098 UNSPEC_TOCPTR))
12099 (match_dup 1)]
12100 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12101 "*
12102 {
12103 char name[32];
12104 static char templ[32];
12106 get_ppc476_thunk_name (name);
12107 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
12108 return templ;
12109 }"
12110 [(set_attr "type" "branch")
12111 (set_attr "length" "16")])
12113 (define_insn "load_toc_v4_PIC_2"
12114 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12115 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12116 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
12117 (match_operand:SI 3 "immediate_operand" "s")))))]
12118 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12119 "lwz %0,%2-%3(%1)"
12120 [(set_attr "type" "load")])
12122 (define_insn "load_toc_v4_PIC_3b"
12123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12124 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12125 (high:SI
12126 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12127 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
12128 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12129 "addis %0,%1,%2-%3@ha")
12131 (define_insn "load_toc_v4_PIC_3c"
12132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12133 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12134 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12135 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
12136 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12137 "addi %0,%1,%2-%3@l")
12139 ;; If the TOC is shared over a translation unit, as happens with all
12140 ;; the kinds of PIC that we support, we need to restore the TOC
12141 ;; pointer only when jumping over units of translation.
12142 ;; On Darwin, we need to reload the picbase.
12144 (define_expand "builtin_setjmp_receiver"
12145 [(use (label_ref (match_operand 0 "" "")))]
12146 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12147 || (TARGET_TOC && TARGET_MINIMAL_TOC)
12148 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
12149 "
12150 {
12151 #if TARGET_MACHO
12152 if (DEFAULT_ABI == ABI_DARWIN)
12153 {
12154 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
12155 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12156 rtx tmplabrtx;
12157 char tmplab[20];
12159 crtl->uses_pic_offset_table = 1;
12160 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
12161 CODE_LABEL_NUMBER (operands[0]));
12162 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
12164 emit_insn (gen_load_macho_picbase (tmplabrtx));
12165 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
12166 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
12167 }
12168 else
12169 #endif
12170 rs6000_emit_load_toc_table (FALSE);
12171 DONE;
12172 }")
12174 ;; Largetoc support
12175 (define_insn "*largetoc_high"
12176 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
12177 (high:DI
12178 (unspec [(match_operand:DI 1 "" "")
12179 (match_operand:DI 2 "gpc_reg_operand" "b")]
12180 UNSPEC_TOCREL)))]
12181 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12182 "addis %0,%2,%1@toc@ha")
12184 (define_insn "*largetoc_high_aix<mode>"
12185 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
12186 (high:P
12187 (unspec [(match_operand:P 1 "" "")
12188 (match_operand:P 2 "gpc_reg_operand" "b")]
12189 UNSPEC_TOCREL)))]
12190 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
12191 "addis %0,%1@u(%2)")
12193 (define_insn "*largetoc_high_plus"
12194 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
12195 (high:DI
12196 (plus:DI
12197 (unspec [(match_operand:DI 1 "" "")
12198 (match_operand:DI 2 "gpc_reg_operand" "b")]
12199 UNSPEC_TOCREL)
12200 (match_operand:DI 3 "add_cint_operand" "n"))))]
12201 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12202 "addis %0,%2,%1+%3@toc@ha")
12204 (define_insn "*largetoc_high_plus_aix<mode>"
12205 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
12206 (high:P
12207 (plus:P
12208 (unspec [(match_operand:P 1 "" "")
12209 (match_operand:P 2 "gpc_reg_operand" "b")]
12210 UNSPEC_TOCREL)
12211 (match_operand:P 3 "add_cint_operand" "n"))))]
12212 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
12213 "addis %0,%1+%3@u(%2)")
12215 (define_insn "*largetoc_low"
12216 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12217 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
12218 (match_operand:DI 2 "" "")))]
12219 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12220 "@
12221 addi %0,%1,%2@l
12222 addic %0,%1,%2@l")
12224 (define_insn "*largetoc_low_aix<mode>"
12225 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12226 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
12227 (match_operand:P 2 "" "")))]
12228 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
12229 "la %0,%2@l(%1)")
12231 (define_insn_and_split "*tocref<mode>"
12232 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
12233 (match_operand:P 1 "small_toc_ref" "R"))]
12234 "TARGET_TOC"
12235 "la %0,%a1"
12236 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
12237 [(set (match_dup 0) (high:P (match_dup 1)))
12238 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
12240 ;; Elf specific ways of loading addresses for non-PIC code.
12241 ;; The output of this could be r0, but we make a very strong
12242 ;; preference for a base register because it will usually
12243 ;; be needed there.
12244 (define_insn "elf_high"
12245 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
12246 (high:SI (match_operand 1 "" "")))]
12247 "TARGET_ELF && ! TARGET_64BIT"
12248 "lis %0,%1@ha")
12250 (define_insn "elf_low"
12251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12252 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
12253 (match_operand 2 "" "")))]
12254 "TARGET_ELF && ! TARGET_64BIT"
12255 "@
12256 la %0,%2@l(%1)
12257 addic %0,%1,%K2")
12258 \f
12259 ;; Call and call_value insns
12260 (define_expand "call"
12261 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12262 (match_operand 1 "" ""))
12263 (use (match_operand 2 "" ""))
12264 (clobber (reg:SI LR_REGNO))])]
12265 ""
12266 "
12267 {
12268 #if TARGET_MACHO
12269 if (MACHOPIC_INDIRECT)
12270 operands[0] = machopic_indirect_call_target (operands[0]);
12271 #endif
12273 gcc_assert (GET_CODE (operands[0]) == MEM);
12274 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12276 operands[0] = XEXP (operands[0], 0);
12278 if (GET_CODE (operands[0]) != SYMBOL_REF
12279 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
12280 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
12281 {
12282 if (INTVAL (operands[2]) & CALL_LONG)
12283 operands[0] = rs6000_longcall_ref (operands[0]);
12285 switch (DEFAULT_ABI)
12286 {
12287 case ABI_V4:
12288 case ABI_DARWIN:
12289 operands[0] = force_reg (Pmode, operands[0]);
12290 break;
12292 case ABI_AIX:
12293 /* AIX function pointers are really pointers to a three word
12294 area. */
12295 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
12296 DONE;
12298 default:
12299 gcc_unreachable ();
12300 }
12301 }
12302 }")
12304 (define_expand "call_value"
12305 [(parallel [(set (match_operand 0 "" "")
12306 (call (mem:SI (match_operand 1 "address_operand" ""))
12307 (match_operand 2 "" "")))
12308 (use (match_operand 3 "" ""))
12309 (clobber (reg:SI LR_REGNO))])]
12310 ""
12311 "
12312 {
12313 #if TARGET_MACHO
12314 if (MACHOPIC_INDIRECT)
12315 operands[1] = machopic_indirect_call_target (operands[1]);
12316 #endif
12318 gcc_assert (GET_CODE (operands[1]) == MEM);
12319 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12321 operands[1] = XEXP (operands[1], 0);
12323 if (GET_CODE (operands[1]) != SYMBOL_REF
12324 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
12325 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
12326 {
12327 if (INTVAL (operands[3]) & CALL_LONG)
12328 operands[1] = rs6000_longcall_ref (operands[1]);
12330 switch (DEFAULT_ABI)
12331 {
12332 case ABI_V4:
12333 case ABI_DARWIN:
12334 operands[1] = force_reg (Pmode, operands[1]);
12335 break;
12337 case ABI_AIX:
12338 /* AIX function pointers are really pointers to a three word
12339 area. */
12340 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
12341 DONE;
12343 default:
12344 gcc_unreachable ();
12345 }
12346 }
12347 }")
12349 ;; Call to function in current module. No TOC pointer reload needed.
12350 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12351 ;; either the function was not prototyped, or it was prototyped as a
12352 ;; variable argument function. It is > 0 if FP registers were passed
12353 ;; and < 0 if they were not.
12355 (define_insn "*call_local32"
12356 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12357 (match_operand 1 "" "g,g"))
12358 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12359 (clobber (reg:SI LR_REGNO))]
12360 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12361 "*
12362 {
12363 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12364 output_asm_insn (\"crxor 6,6,6\", operands);
12366 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12367 output_asm_insn (\"creqv 6,6,6\", operands);
12369 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12370 }"
12371 [(set_attr "type" "branch")
12372 (set_attr "length" "4,8")])
12374 (define_insn "*call_local64"
12375 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12376 (match_operand 1 "" "g,g"))
12377 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12378 (clobber (reg:SI LR_REGNO))]
12379 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12380 "*
12381 {
12382 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12383 output_asm_insn (\"crxor 6,6,6\", operands);
12385 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12386 output_asm_insn (\"creqv 6,6,6\", operands);
12388 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12389 }"
12390 [(set_attr "type" "branch")
12391 (set_attr "length" "4,8")])
12393 (define_insn "*call_value_local32"
12394 [(set (match_operand 0 "" "")
12395 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12396 (match_operand 2 "" "g,g")))
12397 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12398 (clobber (reg:SI LR_REGNO))]
12399 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12400 "*
12401 {
12402 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12403 output_asm_insn (\"crxor 6,6,6\", operands);
12405 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12406 output_asm_insn (\"creqv 6,6,6\", operands);
12408 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12409 }"
12410 [(set_attr "type" "branch")
12411 (set_attr "length" "4,8")])
12414 (define_insn "*call_value_local64"
12415 [(set (match_operand 0 "" "")
12416 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12417 (match_operand 2 "" "g,g")))
12418 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12419 (clobber (reg:SI LR_REGNO))]
12420 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12421 "*
12422 {
12423 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12424 output_asm_insn (\"crxor 6,6,6\", operands);
12426 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12427 output_asm_insn (\"creqv 6,6,6\", operands);
12429 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12430 }"
12431 [(set_attr "type" "branch")
12432 (set_attr "length" "4,8")])
12434 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
12435 ;; Operand0 is the addresss of the function to call
12436 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
12437 ;; Operand2 is the location in the function descriptor to load r2 from
12438 ;; Operand3 is the stack location to hold the current TOC pointer
12440 (define_insn "call_indirect_aix<ptrsize>"
12441 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12442 (match_operand 1 "" "g,g"))
12443 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12444 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12445 (use (reg:P STATIC_CHAIN_REGNUM))
12446 (clobber (reg:P LR_REGNO))]
12447 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12448 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12449 [(set_attr "type" "jmpreg")
12450 (set_attr "length" "12")])
12452 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
12453 ;; Operand0 is the addresss of the function to call
12454 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
12455 ;; Operand2 is the location in the function descriptor to load r2 from
12456 ;; Operand3 is the stack location to hold the current TOC pointer
12458 (define_insn "call_indirect_aix<ptrsize>_nor11"
12459 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12460 (match_operand 1 "" "g,g"))
12461 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12462 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12463 (clobber (reg:P LR_REGNO))]
12464 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12465 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12466 [(set_attr "type" "jmpreg")
12467 (set_attr "length" "12")])
12469 ;; Operand0 is the return result of the function
12470 ;; Operand1 is the addresss of the function to call
12471 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
12472 ;; Operand3 is the location in the function descriptor to load r2 from
12473 ;; Operand4 is the stack location to hold the current TOC pointer
12475 (define_insn "call_value_indirect_aix<ptrsize>"
12476 [(set (match_operand 0 "" "")
12477 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12478 (match_operand 2 "" "g,g")))
12479 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12480 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
12481 (use (reg:P STATIC_CHAIN_REGNUM))
12482 (clobber (reg:P LR_REGNO))]
12483 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12484 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12485 [(set_attr "type" "jmpreg")
12486 (set_attr "length" "12")])
12488 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
12489 ;; Operand0 is the return result of the function
12490 ;; Operand1 is the addresss of the function to call
12491 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
12492 ;; Operand3 is the location in the function descriptor to load r2 from
12493 ;; Operand4 is the stack location to hold the current TOC pointer
12495 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
12496 [(set (match_operand 0 "" "")
12497 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12498 (match_operand 2 "" "g,g")))
12499 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12500 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
12501 (clobber (reg:P LR_REGNO))]
12502 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12503 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12504 [(set_attr "type" "jmpreg")
12505 (set_attr "length" "12")])
12507 ;; Call to function which may be in another module. Restore the TOC
12508 ;; pointer (r2) after the call unless this is System V.
12509 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12510 ;; either the function was not prototyped, or it was prototyped as a
12511 ;; variable argument function. It is > 0 if FP registers were passed
12512 ;; and < 0 if they were not.
12514 (define_insn "*call_nonlocal_aix32"
12515 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12516 (match_operand 1 "" "g"))
12517 (use (match_operand:SI 2 "immediate_operand" "O"))
12518 (clobber (reg:SI LR_REGNO))]
12519 "TARGET_32BIT
12520 && DEFAULT_ABI == ABI_AIX
12521 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12522 "bl %z0\;nop"
12523 [(set_attr "type" "branch")
12524 (set_attr "length" "8")])
12526 (define_insn "*call_nonlocal_aix64"
12527 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12528 (match_operand 1 "" "g"))
12529 (use (match_operand:SI 2 "immediate_operand" "O"))
12530 (clobber (reg:SI LR_REGNO))]
12531 "TARGET_64BIT
12532 && DEFAULT_ABI == ABI_AIX
12533 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12534 "bl %z0\;nop"
12535 [(set_attr "type" "branch")
12536 (set_attr "length" "8")])
12538 (define_insn "*call_value_nonlocal_aix32"
12539 [(set (match_operand 0 "" "")
12540 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12541 (match_operand 2 "" "g")))
12542 (use (match_operand:SI 3 "immediate_operand" "O"))
12543 (clobber (reg:SI LR_REGNO))]
12544 "TARGET_32BIT
12545 && DEFAULT_ABI == ABI_AIX
12546 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12547 "bl %z1\;nop"
12548 [(set_attr "type" "branch")
12549 (set_attr "length" "8")])
12551 (define_insn "*call_value_nonlocal_aix64"
12552 [(set (match_operand 0 "" "")
12553 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12554 (match_operand 2 "" "g")))
12555 (use (match_operand:SI 3 "immediate_operand" "O"))
12556 (clobber (reg:SI LR_REGNO))]
12557 "TARGET_64BIT
12558 && DEFAULT_ABI == ABI_AIX
12559 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12560 "bl %z1\;nop"
12561 [(set_attr "type" "branch")
12562 (set_attr "length" "8")])
12564 ;; A function pointer under System V is just a normal pointer
12565 ;; operands[0] is the function pointer
12566 ;; operands[1] is the stack size to clean up
12567 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12568 ;; which indicates how to set cr1
12570 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12571 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12572 (match_operand 1 "" "g,g,g,g"))
12573 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12574 (clobber (reg:SI LR_REGNO))]
12575 "DEFAULT_ABI == ABI_V4
12576 || DEFAULT_ABI == ABI_DARWIN"
12577 {
12578 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12579 output_asm_insn ("crxor 6,6,6", operands);
12581 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12582 output_asm_insn ("creqv 6,6,6", operands);
12584 return "b%T0l";
12585 }
12586 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12587 (set_attr "length" "4,4,8,8")])
12589 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12590 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12591 (match_operand 1 "" "g,g"))
12592 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12593 (clobber (reg:SI LR_REGNO))]
12594 "(DEFAULT_ABI == ABI_DARWIN
12595 || (DEFAULT_ABI == ABI_V4
12596 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12597 {
12598 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12599 output_asm_insn ("crxor 6,6,6", operands);
12601 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12602 output_asm_insn ("creqv 6,6,6", operands);
12604 #if TARGET_MACHO
12605 return output_call(insn, operands, 0, 2);
12606 #else
12607 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12608 {
12609 gcc_assert (!TARGET_SECURE_PLT);
12610 return "bl %z0@plt";
12611 }
12612 else
12613 return "bl %z0";
12614 #endif
12615 }
12616 "DEFAULT_ABI == ABI_V4
12617 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12618 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12619 [(parallel [(call (mem:SI (match_dup 0))
12620 (match_dup 1))
12621 (use (match_dup 2))
12622 (use (match_dup 3))
12623 (clobber (reg:SI LR_REGNO))])]
12624 {
12625 operands[3] = pic_offset_table_rtx;
12626 }
12627 [(set_attr "type" "branch,branch")
12628 (set_attr "length" "4,8")])
12630 (define_insn "*call_nonlocal_sysv_secure<mode>"
12631 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12632 (match_operand 1 "" "g,g"))
12633 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12634 (use (match_operand:SI 3 "register_operand" "r,r"))
12635 (clobber (reg:SI LR_REGNO))]
12636 "(DEFAULT_ABI == ABI_V4
12637 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12638 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12639 {
12640 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12641 output_asm_insn ("crxor 6,6,6", operands);
12643 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12644 output_asm_insn ("creqv 6,6,6", operands);
12646 if (flag_pic == 2)
12647 /* The magic 32768 offset here and in the other sysv call insns
12648 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12649 See sysv4.h:toc_section. */
12650 return "bl %z0+32768@plt";
12651 else
12652 return "bl %z0@plt";
12653 }
12654 [(set_attr "type" "branch,branch")
12655 (set_attr "length" "4,8")])
12657 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12658 [(set (match_operand 0 "" "")
12659 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12660 (match_operand 2 "" "g,g,g,g")))
12661 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12662 (clobber (reg:SI LR_REGNO))]
12663 "DEFAULT_ABI == ABI_V4
12664 || DEFAULT_ABI == ABI_DARWIN"
12665 {
12666 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12667 output_asm_insn ("crxor 6,6,6", operands);
12669 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12670 output_asm_insn ("creqv 6,6,6", operands);
12672 return "b%T1l";
12673 }
12674 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12675 (set_attr "length" "4,4,8,8")])
12677 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12678 [(set (match_operand 0 "" "")
12679 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12680 (match_operand 2 "" "g,g")))
12681 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12682 (clobber (reg:SI LR_REGNO))]
12683 "(DEFAULT_ABI == ABI_DARWIN
12684 || (DEFAULT_ABI == ABI_V4
12685 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12686 {
12687 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12688 output_asm_insn ("crxor 6,6,6", operands);
12690 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12691 output_asm_insn ("creqv 6,6,6", operands);
12693 #if TARGET_MACHO
12694 return output_call(insn, operands, 1, 3);
12695 #else
12696 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12697 {
12698 gcc_assert (!TARGET_SECURE_PLT);
12699 return "bl %z1@plt";
12700 }
12701 else
12702 return "bl %z1";
12703 #endif
12704 }
12705 "DEFAULT_ABI == ABI_V4
12706 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12707 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12708 [(parallel [(set (match_dup 0)
12709 (call (mem:SI (match_dup 1))
12710 (match_dup 2)))
12711 (use (match_dup 3))
12712 (use (match_dup 4))
12713 (clobber (reg:SI LR_REGNO))])]
12714 {
12715 operands[4] = pic_offset_table_rtx;
12716 }
12717 [(set_attr "type" "branch,branch")
12718 (set_attr "length" "4,8")])
12720 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12721 [(set (match_operand 0 "" "")
12722 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12723 (match_operand 2 "" "g,g")))
12724 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12725 (use (match_operand:SI 4 "register_operand" "r,r"))
12726 (clobber (reg:SI LR_REGNO))]
12727 "(DEFAULT_ABI == ABI_V4
12728 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12729 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12730 {
12731 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12732 output_asm_insn ("crxor 6,6,6", operands);
12734 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12735 output_asm_insn ("creqv 6,6,6", operands);
12737 if (flag_pic == 2)
12738 return "bl %z1+32768@plt";
12739 else
12740 return "bl %z1@plt";
12741 }
12742 [(set_attr "type" "branch,branch")
12743 (set_attr "length" "4,8")])
12745 ;; Call subroutine returning any type.
12746 (define_expand "untyped_call"
12747 [(parallel [(call (match_operand 0 "" "")
12748 (const_int 0))
12749 (match_operand 1 "" "")
12750 (match_operand 2 "" "")])]
12751 ""
12752 "
12753 {
12754 int i;
12756 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12758 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12759 {
12760 rtx set = XVECEXP (operands[2], 0, i);
12761 emit_move_insn (SET_DEST (set), SET_SRC (set));
12762 }
12764 /* The optimizer does not know that the call sets the function value
12765 registers we stored in the result block. We avoid problems by
12766 claiming that all hard registers are used and clobbered at this
12767 point. */
12768 emit_insn (gen_blockage ());
12770 DONE;
12771 }")
12773 ;; sibling call patterns
12774 (define_expand "sibcall"
12775 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12776 (match_operand 1 "" ""))
12777 (use (match_operand 2 "" ""))
12778 (use (reg:SI LR_REGNO))
12779 (simple_return)])]
12780 ""
12781 "
12782 {
12783 #if TARGET_MACHO
12784 if (MACHOPIC_INDIRECT)
12785 operands[0] = machopic_indirect_call_target (operands[0]);
12786 #endif
12788 gcc_assert (GET_CODE (operands[0]) == MEM);
12789 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12791 operands[0] = XEXP (operands[0], 0);
12792 }")
12794 ;; this and similar patterns must be marked as using LR, otherwise
12795 ;; dataflow will try to delete the store into it. This is true
12796 ;; even when the actual reg to jump to is in CTR, when LR was
12797 ;; saved and restored around the PIC-setting BCL.
12798 (define_insn "*sibcall_local32"
12799 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12800 (match_operand 1 "" "g,g"))
12801 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12802 (use (reg:SI LR_REGNO))
12803 (simple_return)]
12804 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12805 "*
12806 {
12807 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12808 output_asm_insn (\"crxor 6,6,6\", operands);
12810 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12811 output_asm_insn (\"creqv 6,6,6\", operands);
12813 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12814 }"
12815 [(set_attr "type" "branch")
12816 (set_attr "length" "4,8")])
12818 (define_insn "*sibcall_local64"
12819 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12820 (match_operand 1 "" "g,g"))
12821 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12822 (use (reg:SI LR_REGNO))
12823 (simple_return)]
12824 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12825 "*
12826 {
12827 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12828 output_asm_insn (\"crxor 6,6,6\", operands);
12830 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12831 output_asm_insn (\"creqv 6,6,6\", operands);
12833 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12834 }"
12835 [(set_attr "type" "branch")
12836 (set_attr "length" "4,8")])
12838 (define_insn "*sibcall_value_local32"
12839 [(set (match_operand 0 "" "")
12840 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12841 (match_operand 2 "" "g,g")))
12842 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12843 (use (reg:SI LR_REGNO))
12844 (simple_return)]
12845 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12846 "*
12847 {
12848 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12849 output_asm_insn (\"crxor 6,6,6\", operands);
12851 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12852 output_asm_insn (\"creqv 6,6,6\", operands);
12854 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12855 }"
12856 [(set_attr "type" "branch")
12857 (set_attr "length" "4,8")])
12860 (define_insn "*sibcall_value_local64"
12861 [(set (match_operand 0 "" "")
12862 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12863 (match_operand 2 "" "g,g")))
12864 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12865 (use (reg:SI LR_REGNO))
12866 (simple_return)]
12867 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12868 "*
12869 {
12870 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12871 output_asm_insn (\"crxor 6,6,6\", operands);
12873 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12874 output_asm_insn (\"creqv 6,6,6\", operands);
12876 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12877 }"
12878 [(set_attr "type" "branch")
12879 (set_attr "length" "4,8")])
12881 (define_insn "*sibcall_nonlocal_aix<mode>"
12882 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12883 (match_operand 1 "" "g,g"))
12884 (use (match_operand:SI 2 "immediate_operand" "O,O"))
12885 (use (reg:SI LR_REGNO))
12886 (simple_return)]
12887 "DEFAULT_ABI == ABI_AIX
12888 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12889 "@
12890 b %z0
12891 b%T0"
12892 [(set_attr "type" "branch")
12893 (set_attr "length" "4")])
12895 (define_insn "*sibcall_value_nonlocal_aix<mode>"
12896 [(set (match_operand 0 "" "")
12897 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12898 (match_operand 2 "" "g,g")))
12899 (use (match_operand:SI 3 "immediate_operand" "O,O"))
12900 (use (reg:SI LR_REGNO))
12901 (simple_return)]
12902 "DEFAULT_ABI == ABI_AIX
12903 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12904 "@
12905 b %z1
12906 b%T1"
12907 [(set_attr "type" "branch")
12908 (set_attr "length" "4")])
12910 (define_insn "*sibcall_nonlocal_sysv<mode>"
12911 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12912 (match_operand 1 "" ""))
12913 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12914 (use (reg:SI LR_REGNO))
12915 (simple_return)]
12916 "(DEFAULT_ABI == ABI_DARWIN
12917 || DEFAULT_ABI == ABI_V4)
12918 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12919 "*
12920 {
12921 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12922 output_asm_insn (\"crxor 6,6,6\", operands);
12924 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12925 output_asm_insn (\"creqv 6,6,6\", operands);
12927 if (which_alternative >= 2)
12928 return \"b%T0\";
12929 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12930 {
12931 gcc_assert (!TARGET_SECURE_PLT);
12932 return \"b %z0@plt\";
12933 }
12934 else
12935 return \"b %z0\";
12936 }"
12937 [(set_attr "type" "branch")
12938 (set_attr "length" "4,8,4,8")])
12940 (define_expand "sibcall_value"
12941 [(parallel [(set (match_operand 0 "register_operand" "")
12942 (call (mem:SI (match_operand 1 "address_operand" ""))
12943 (match_operand 2 "" "")))
12944 (use (match_operand 3 "" ""))
12945 (use (reg:SI LR_REGNO))
12946 (simple_return)])]
12947 ""
12948 "
12949 {
12950 #if TARGET_MACHO
12951 if (MACHOPIC_INDIRECT)
12952 operands[1] = machopic_indirect_call_target (operands[1]);
12953 #endif
12955 gcc_assert (GET_CODE (operands[1]) == MEM);
12956 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12958 operands[1] = XEXP (operands[1], 0);
12959 }")
12961 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12962 [(set (match_operand 0 "" "")
12963 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12964 (match_operand 2 "" "")))
12965 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12966 (use (reg:SI LR_REGNO))
12967 (simple_return)]
12968 "(DEFAULT_ABI == ABI_DARWIN
12969 || DEFAULT_ABI == ABI_V4)
12970 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12971 "*
12972 {
12973 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12974 output_asm_insn (\"crxor 6,6,6\", operands);
12976 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12977 output_asm_insn (\"creqv 6,6,6\", operands);
12979 if (which_alternative >= 2)
12980 return \"b%T1\";
12981 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12982 {
12983 gcc_assert (!TARGET_SECURE_PLT);
12984 return \"b %z1@plt\";
12985 }
12986 else
12987 return \"b %z1\";
12988 }"
12989 [(set_attr "type" "branch")
12990 (set_attr "length" "4,8,4,8")])
12992 (define_expand "sibcall_epilogue"
12993 [(use (const_int 0))]
12994 ""
12995 {
12996 if (!TARGET_SCHED_PROLOG)
12997 emit_insn (gen_blockage ());
12998 rs6000_emit_epilogue (TRUE);
12999 DONE;
13000 })
13002 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13003 ;; all of memory. This blocks insns from being moved across this point.
13005 (define_insn "blockage"
13006 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
13007 ""
13008 "")
13010 (define_expand "probe_stack"
13011 [(set (match_operand 0 "memory_operand" "=m")
13012 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
13013 ""
13014 {
13015 if (TARGET_64BIT)
13016 emit_insn (gen_probe_stack_di (operands[0]));
13017 else
13018 emit_insn (gen_probe_stack_si (operands[0]));
13019 DONE;
13020 })
13022 (define_insn "probe_stack_<mode>"
13023 [(set (match_operand:P 0 "memory_operand" "=m")
13024 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
13025 ""
13026 {
13027 operands[1] = gen_rtx_REG (Pmode, 0);
13028 return "st<wd>%U0%X0 %1,%0";
13029 }
13030 [(set (attr "type")
13031 (if_then_else
13032 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
13033 (const_string "store_ux")
13034 (if_then_else
13035 (match_test "update_address_mem (operands[0], VOIDmode)")
13036 (const_string "store_u")
13037 (const_string "store"))))
13038 (set_attr "length" "4")])
13040 (define_insn "probe_stack_range<P:mode>"
13041 [(set (match_operand:P 0 "register_operand" "=r")
13042 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
13043 (match_operand:P 2 "register_operand" "r")]
13044 UNSPECV_PROBE_STACK_RANGE))]
13045 ""
13046 "* return output_probe_stack_range (operands[0], operands[2]);"
13047 [(set_attr "type" "three")])
13048 \f
13049 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
13050 ;; signed & unsigned, and one type of branch.
13051 ;;
13052 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
13053 ;; insns, and branches.
13055 (define_expand "cbranch<mode>4"
13056 [(use (match_operator 0 "rs6000_cbranch_operator"
13057 [(match_operand:GPR 1 "gpc_reg_operand" "")
13058 (match_operand:GPR 2 "reg_or_short_operand" "")]))
13059 (use (match_operand 3 ""))]
13060 ""
13061 "
13062 {
13063 /* Take care of the possibility that operands[2] might be negative but
13064 this might be a logical operation. That insn doesn't exist. */
13065 if (GET_CODE (operands[2]) == CONST_INT
13066 && INTVAL (operands[2]) < 0)
13067 {
13068 operands[2] = force_reg (<MODE>mode, operands[2]);
13069 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
13070 GET_MODE (operands[0]),
13071 operands[1], operands[2]);
13072 }
13074 rs6000_emit_cbranch (<MODE>mode, operands);
13075 DONE;
13076 }")
13078 (define_expand "cbranch<mode>4"
13079 [(use (match_operator 0 "rs6000_cbranch_operator"
13080 [(match_operand:FP 1 "gpc_reg_operand" "")
13081 (match_operand:FP 2 "gpc_reg_operand" "")]))
13082 (use (match_operand 3 ""))]
13083 ""
13084 "
13085 {
13086 rs6000_emit_cbranch (<MODE>mode, operands);
13087 DONE;
13088 }")
13090 (define_expand "cstore<mode>4"
13091 [(use (match_operator 1 "rs6000_cbranch_operator"
13092 [(match_operand:GPR 2 "gpc_reg_operand" "")
13093 (match_operand:GPR 3 "reg_or_short_operand" "")]))
13094 (clobber (match_operand:SI 0 "register_operand"))]
13095 ""
13096 "
13097 {
13098 /* Take care of the possibility that operands[3] might be negative but
13099 this might be a logical operation. That insn doesn't exist. */
13100 if (GET_CODE (operands[3]) == CONST_INT
13101 && INTVAL (operands[3]) < 0)
13102 {
13103 operands[3] = force_reg (<MODE>mode, operands[3]);
13104 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
13105 GET_MODE (operands[1]),
13106 operands[2], operands[3]);
13107 }
13109 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
13110 For SEQ, likewise, except that comparisons with zero should be done
13111 with an scc insns. However, due to the order that combine see the
13112 resulting insns, we must, in fact, allow SEQ for integers. Fail in
13113 the cases we don't want to handle or are best handled by portable
13114 code. */
13115 if (GET_CODE (operands[1]) == NE)
13116 FAIL;
13117 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
13118 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
13119 && operands[3] == const0_rtx)
13120 FAIL;
13121 rs6000_emit_sCOND (<MODE>mode, operands);
13122 DONE;
13123 }")
13125 (define_expand "cstore<mode>4"
13126 [(use (match_operator 1 "rs6000_cbranch_operator"
13127 [(match_operand:FP 2 "gpc_reg_operand" "")
13128 (match_operand:FP 3 "gpc_reg_operand" "")]))
13129 (clobber (match_operand:SI 0 "register_operand"))]
13130 ""
13131 "
13132 {
13133 rs6000_emit_sCOND (<MODE>mode, operands);
13134 DONE;
13135 }")
13138 (define_expand "stack_protect_set"
13139 [(match_operand 0 "memory_operand" "")
13140 (match_operand 1 "memory_operand" "")]
13141 ""
13142 {
13143 #ifdef TARGET_THREAD_SSP_OFFSET
13144 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13145 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13146 operands[1] = gen_rtx_MEM (Pmode, addr);
13147 #endif
13148 if (TARGET_64BIT)
13149 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
13150 else
13151 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
13152 DONE;
13153 })
13155 (define_insn "stack_protect_setsi"
13156 [(set (match_operand:SI 0 "memory_operand" "=m")
13157 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13158 (set (match_scratch:SI 2 "=&r") (const_int 0))]
13159 "TARGET_32BIT"
13160 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
13161 [(set_attr "type" "three")
13162 (set_attr "length" "12")])
13164 (define_insn "stack_protect_setdi"
13165 [(set (match_operand:DI 0 "memory_operand" "=Y")
13166 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
13167 (set (match_scratch:DI 2 "=&r") (const_int 0))]
13168 "TARGET_64BIT"
13169 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
13170 [(set_attr "type" "three")
13171 (set_attr "length" "12")])
13173 (define_expand "stack_protect_test"
13174 [(match_operand 0 "memory_operand" "")
13175 (match_operand 1 "memory_operand" "")
13176 (match_operand 2 "" "")]
13177 ""
13178 {
13179 rtx test, op0, op1;
13180 #ifdef TARGET_THREAD_SSP_OFFSET
13181 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13182 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13183 operands[1] = gen_rtx_MEM (Pmode, addr);
13184 #endif
13185 op0 = operands[0];
13186 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
13187 test = gen_rtx_EQ (VOIDmode, op0, op1);
13188 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
13189 DONE;
13190 })
13192 (define_insn "stack_protect_testsi"
13193 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13194 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
13195 (match_operand:SI 2 "memory_operand" "m,m")]
13196 UNSPEC_SP_TEST))
13197 (set (match_scratch:SI 4 "=r,r") (const_int 0))
13198 (clobber (match_scratch:SI 3 "=&r,&r"))]
13199 "TARGET_32BIT"
13200 "@
13201 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
13202 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
13203 [(set_attr "length" "16,20")])
13205 (define_insn "stack_protect_testdi"
13206 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13207 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
13208 (match_operand:DI 2 "memory_operand" "Y,Y")]
13209 UNSPEC_SP_TEST))
13210 (set (match_scratch:DI 4 "=r,r") (const_int 0))
13211 (clobber (match_scratch:DI 3 "=&r,&r"))]
13212 "TARGET_64BIT"
13213 "@
13214 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
13215 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
13216 [(set_attr "length" "16,20")])
13218 \f
13219 ;; Here are the actual compare insns.
13220 (define_insn "*cmp<mode>_internal1"
13221 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13222 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
13223 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
13224 ""
13225 "cmp<wd>%I2 %0,%1,%2"
13226 [(set_attr "type" "cmp")])
13228 ;; If we are comparing a register for equality with a large constant,
13229 ;; we can do this with an XOR followed by a compare. But this is profitable
13230 ;; only if the large constant is only used for the comparison (and in this
13231 ;; case we already have a register to reuse as scratch).
13232 ;;
13233 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
13234 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
13236 (define_peephole2
13237 [(set (match_operand:SI 0 "register_operand")
13238 (match_operand:SI 1 "logical_const_operand" ""))
13239 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
13240 [(match_dup 0)
13241 (match_operand:SI 2 "logical_const_operand" "")]))
13242 (set (match_operand:CC 4 "cc_reg_operand" "")
13243 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
13244 (match_dup 0)))
13245 (set (pc)
13246 (if_then_else (match_operator 6 "equality_operator"
13247 [(match_dup 4) (const_int 0)])
13248 (match_operand 7 "" "")
13249 (match_operand 8 "" "")))]
13250 "peep2_reg_dead_p (3, operands[0])
13251 && peep2_reg_dead_p (4, operands[4])"
13252 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
13253 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
13254 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
13256 {
13257 /* Get the constant we are comparing against, and see what it looks like
13258 when sign-extended from 16 to 32 bits. Then see what constant we could
13259 XOR with SEXTC to get the sign-extended value. */
13260 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
13261 SImode,
13262 operands[1], operands[2]);
13263 HOST_WIDE_INT c = INTVAL (cnst);
13264 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
13265 HOST_WIDE_INT xorv = c ^ sextc;
13267 operands[9] = GEN_INT (xorv);
13268 operands[10] = GEN_INT (sextc);
13269 })
13271 (define_insn "*cmpsi_internal2"
13272 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13273 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13274 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
13275 ""
13276 "cmplw%I2 %0,%1,%b2"
13277 [(set_attr "type" "cmp")])
13279 (define_insn "*cmpdi_internal2"
13280 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13281 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
13282 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
13283 ""
13284 "cmpld%I2 %0,%1,%b2"
13285 [(set_attr "type" "cmp")])
13287 ;; The following two insns don't exist as single insns, but if we provide
13288 ;; them, we can swap an add and compare, which will enable us to overlap more
13289 ;; of the required delay between a compare and branch. We generate code for
13290 ;; them by splitting.
13292 (define_insn ""
13293 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13294 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
13295 (match_operand:SI 2 "short_cint_operand" "i")))
13296 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13297 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13298 ""
13299 "#"
13300 [(set_attr "length" "8")])
13302 (define_insn ""
13303 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
13304 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13305 (match_operand:SI 2 "u_short_cint_operand" "i")))
13306 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13307 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13308 ""
13309 "#"
13310 [(set_attr "length" "8")])
13312 (define_split
13313 [(set (match_operand:CC 3 "cc_reg_operand" "")
13314 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
13315 (match_operand:SI 2 "short_cint_operand" "")))
13316 (set (match_operand:SI 0 "gpc_reg_operand" "")
13317 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13318 ""
13319 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
13320 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13322 (define_split
13323 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
13324 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
13325 (match_operand:SI 2 "u_short_cint_operand" "")))
13326 (set (match_operand:SI 0 "gpc_reg_operand" "")
13327 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13328 ""
13329 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
13330 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13332 (define_insn "*cmpsf_internal1"
13333 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13334 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
13335 (match_operand:SF 2 "gpc_reg_operand" "f")))]
13336 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
13337 "fcmpu %0,%1,%2"
13338 [(set_attr "type" "fpcompare")])
13340 (define_insn "*cmpdf_internal1"
13341 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13342 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
13343 (match_operand:DF 2 "gpc_reg_operand" "d")))]
13344 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
13345 && !VECTOR_UNIT_VSX_P (DFmode)"
13346 "fcmpu %0,%1,%2"
13347 [(set_attr "type" "fpcompare")])
13349 ;; Only need to compare second words if first words equal
13350 (define_insn "*cmptf_internal1"
13351 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13352 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13353 (match_operand:TF 2 "gpc_reg_operand" "d")))]
13354 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
13355 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13356 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
13357 [(set_attr "type" "fpcompare")
13358 (set_attr "length" "12")])
13360 (define_insn_and_split "*cmptf_internal2"
13361 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13362 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13363 (match_operand:TF 2 "gpc_reg_operand" "d")))
13364 (clobber (match_scratch:DF 3 "=d"))
13365 (clobber (match_scratch:DF 4 "=d"))
13366 (clobber (match_scratch:DF 5 "=d"))
13367 (clobber (match_scratch:DF 6 "=d"))
13368 (clobber (match_scratch:DF 7 "=d"))
13369 (clobber (match_scratch:DF 8 "=d"))
13370 (clobber (match_scratch:DF 9 "=d"))
13371 (clobber (match_scratch:DF 10 "=d"))
13372 (clobber (match_scratch:GPR 11 "=b"))]
13373 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
13374 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13375 "#"
13376 "&& reload_completed"
13377 [(set (match_dup 3) (match_dup 14))
13378 (set (match_dup 4) (match_dup 15))
13379 (set (match_dup 9) (abs:DF (match_dup 5)))
13380 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13381 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13382 (label_ref (match_dup 12))
13383 (pc)))
13384 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13385 (set (pc) (label_ref (match_dup 13)))
13386 (match_dup 12)
13387 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13388 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13389 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13390 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13391 (match_dup 13)]
13392 {
13393 REAL_VALUE_TYPE rv;
13394 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
13395 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
13397 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13398 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13399 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13400 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13401 operands[12] = gen_label_rtx ();
13402 operands[13] = gen_label_rtx ();
13403 real_inf (&rv);
13404 operands[14] = force_const_mem (DFmode,
13405 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13406 operands[15] = force_const_mem (DFmode,
13407 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13408 DFmode));
13409 if (TARGET_TOC)
13410 {
13411 rtx tocref;
13412 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13413 operands[14] = gen_const_mem (DFmode, tocref);
13414 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13415 operands[15] = gen_const_mem (DFmode, tocref);
13416 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13417 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13418 }
13419 })
13420 \f
13421 ;; Now we have the scc insns. We can do some combinations because of the
13422 ;; way the machine works.
13423 ;;
13424 ;; Note that this is probably faster if we can put an insn between the
13425 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13426 ;; cases the insns below which don't use an intermediate CR field will
13427 ;; be used instead.
13428 (define_insn ""
13429 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13430 (match_operator:SI 1 "scc_comparison_operator"
13431 [(match_operand 2 "cc_reg_operand" "y")
13432 (const_int 0)]))]
13433 ""
13434 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
13435 [(set (attr "type")
13436 (cond [(match_test "TARGET_MFCRF")
13437 (const_string "mfcrf")
13438 ]
13439 (const_string "mfcr")))
13440 (set_attr "length" "8")])
13442 ;; Same as above, but get the GT bit.
13443 (define_insn "move_from_CR_gt_bit"
13444 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13445 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13446 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13447 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
13448 [(set_attr "type" "mfcr")
13449 (set_attr "length" "8")])
13451 ;; Same as above, but get the OV/ORDERED bit.
13452 (define_insn "move_from_CR_ov_bit"
13453 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13454 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
13455 UNSPEC_MV_CR_OV))]
13456 "TARGET_ISEL"
13457 "mfcr %0\;rlwinm %0,%0,%t1,1"
13458 [(set_attr "type" "mfcr")
13459 (set_attr "length" "8")])
13461 (define_insn ""
13462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13463 (match_operator:DI 1 "scc_comparison_operator"
13464 [(match_operand 2 "cc_reg_operand" "y")
13465 (const_int 0)]))]
13466 "TARGET_POWERPC64"
13467 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
13468 [(set (attr "type")
13469 (cond [(match_test "TARGET_MFCRF")
13470 (const_string "mfcrf")
13471 ]
13472 (const_string "mfcr")))
13473 (set_attr "length" "8")])
13475 (define_insn ""
13476 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13477 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13478 [(match_operand 2 "cc_reg_operand" "y,y")
13479 (const_int 0)])
13480 (const_int 0)))
13481 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13482 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13483 "TARGET_32BIT"
13484 "@
13485 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
13486 #"
13487 [(set_attr "type" "delayed_compare")
13488 (set_attr "length" "8,16")])
13490 (define_split
13491 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13492 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13493 [(match_operand 2 "cc_reg_operand" "")
13494 (const_int 0)])
13495 (const_int 0)))
13496 (set (match_operand:SI 3 "gpc_reg_operand" "")
13497 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13498 "TARGET_32BIT && reload_completed"
13499 [(set (match_dup 3)
13500 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13501 (set (match_dup 0)
13502 (compare:CC (match_dup 3)
13503 (const_int 0)))]
13504 "")
13506 (define_insn ""
13507 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13508 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13509 [(match_operand 2 "cc_reg_operand" "y")
13510 (const_int 0)])
13511 (match_operand:SI 3 "const_int_operand" "n")))]
13512 ""
13513 "*
13514 {
13515 int is_bit = ccr_bit (operands[1], 1);
13516 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13517 int count;
13519 if (is_bit >= put_bit)
13520 count = is_bit - put_bit;
13521 else
13522 count = 32 - (put_bit - is_bit);
13524 operands[4] = GEN_INT (count);
13525 operands[5] = GEN_INT (put_bit);
13527 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
13528 }"
13529 [(set (attr "type")
13530 (cond [(match_test "TARGET_MFCRF")
13531 (const_string "mfcrf")
13532 ]
13533 (const_string "mfcr")))
13534 (set_attr "length" "8")])
13536 (define_insn ""
13537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13538 (compare:CC
13539 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13540 [(match_operand 2 "cc_reg_operand" "y,y")
13541 (const_int 0)])
13542 (match_operand:SI 3 "const_int_operand" "n,n"))
13543 (const_int 0)))
13544 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13545 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13546 (match_dup 3)))]
13547 ""
13548 "*
13549 {
13550 int is_bit = ccr_bit (operands[1], 1);
13551 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13552 int count;
13554 /* Force split for non-cc0 compare. */
13555 if (which_alternative == 1)
13556 return \"#\";
13558 if (is_bit >= put_bit)
13559 count = is_bit - put_bit;
13560 else
13561 count = 32 - (put_bit - is_bit);
13563 operands[5] = GEN_INT (count);
13564 operands[6] = GEN_INT (put_bit);
13566 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
13567 }"
13568 [(set_attr "type" "delayed_compare")
13569 (set_attr "length" "8,16")])
13571 (define_split
13572 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13573 (compare:CC
13574 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13575 [(match_operand 2 "cc_reg_operand" "")
13576 (const_int 0)])
13577 (match_operand:SI 3 "const_int_operand" ""))
13578 (const_int 0)))
13579 (set (match_operand:SI 4 "gpc_reg_operand" "")
13580 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13581 (match_dup 3)))]
13582 "reload_completed"
13583 [(set (match_dup 4)
13584 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13585 (match_dup 3)))
13586 (set (match_dup 0)
13587 (compare:CC (match_dup 4)
13588 (const_int 0)))]
13589 "")
13591 ;; There is a 3 cycle delay between consecutive mfcr instructions
13592 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13594 (define_peephole
13595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13596 (match_operator:SI 1 "scc_comparison_operator"
13597 [(match_operand 2 "cc_reg_operand" "y")
13598 (const_int 0)]))
13599 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13600 (match_operator:SI 4 "scc_comparison_operator"
13601 [(match_operand 5 "cc_reg_operand" "y")
13602 (const_int 0)]))]
13603 "REGNO (operands[2]) != REGNO (operands[5])"
13604 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13605 [(set_attr "type" "mfcr")
13606 (set_attr "length" "12")])
13608 (define_peephole
13609 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13610 (match_operator:DI 1 "scc_comparison_operator"
13611 [(match_operand 2 "cc_reg_operand" "y")
13612 (const_int 0)]))
13613 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13614 (match_operator:DI 4 "scc_comparison_operator"
13615 [(match_operand 5 "cc_reg_operand" "y")
13616 (const_int 0)]))]
13617 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13618 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13619 [(set_attr "type" "mfcr")
13620 (set_attr "length" "12")])
13622 ;; There are some scc insns that can be done directly, without a compare.
13623 ;; These are faster because they don't involve the communications between
13624 ;; the FXU and branch units. In fact, we will be replacing all of the
13625 ;; integer scc insns here or in the portable methods in emit_store_flag.
13626 ;;
13627 ;; Also support (neg (scc ..)) since that construct is used to replace
13628 ;; branches, (plus (scc ..) ..) since that construct is common and
13629 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13630 ;; cases where it is no more expensive than (neg (scc ..)).
13632 ;; Have reload force a constant into a register for the simple insns that
13633 ;; otherwise won't accept constants. We do this because it is faster than
13634 ;; the cmp/mfcr sequence we would otherwise generate.
13636 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13637 (DI "rKJI")])
13639 (define_insn_and_split "*eq<mode>"
13640 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13641 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13642 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13643 ""
13644 "#"
13645 ""
13646 [(set (match_dup 0)
13647 (clz:GPR (match_dup 3)))
13648 (set (match_dup 0)
13649 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13650 {
13651 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13652 {
13653 /* Use output operand as intermediate. */
13654 operands[3] = operands[0];
13656 if (logical_operand (operands[2], <MODE>mode))
13657 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13658 gen_rtx_XOR (<MODE>mode,
13659 operands[1], operands[2])));
13660 else
13661 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13662 gen_rtx_PLUS (<MODE>mode, operands[1],
13663 negate_rtx (<MODE>mode,
13664 operands[2]))));
13665 }
13666 else
13667 operands[3] = operands[1];
13669 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13670 })
13672 (define_insn_and_split "*eq<mode>_compare"
13673 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13674 (compare:CC
13675 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13676 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13677 (const_int 0)))
13678 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13679 (eq:P (match_dup 1) (match_dup 2)))]
13680 "optimize_size"
13681 "#"
13682 "optimize_size"
13683 [(set (match_dup 0)
13684 (clz:P (match_dup 4)))
13685 (parallel [(set (match_dup 3)
13686 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13687 (const_int 0)))
13688 (set (match_dup 0)
13689 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13690 {
13691 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13692 {
13693 /* Use output operand as intermediate. */
13694 operands[4] = operands[0];
13696 if (logical_operand (operands[2], <MODE>mode))
13697 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13698 gen_rtx_XOR (<MODE>mode,
13699 operands[1], operands[2])));
13700 else
13701 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13702 gen_rtx_PLUS (<MODE>mode, operands[1],
13703 negate_rtx (<MODE>mode,
13704 operands[2]))));
13705 }
13706 else
13707 operands[4] = operands[1];
13709 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13710 })
13712 ;; We have insns of the form shown by the first define_insn below. If
13713 ;; there is something inside the comparison operation, we must split it.
13714 (define_split
13715 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13716 (plus:SI (match_operator 1 "comparison_operator"
13717 [(match_operand:SI 2 "" "")
13718 (match_operand:SI 3
13719 "reg_or_cint_operand" "")])
13720 (match_operand:SI 4 "gpc_reg_operand" "")))
13721 (clobber (match_operand:SI 5 "register_operand" ""))]
13722 "! gpc_reg_operand (operands[2], SImode)"
13723 [(set (match_dup 5) (match_dup 2))
13724 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
13725 (match_dup 4)))])
13727 (define_insn "*plus_eqsi"
13728 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13729 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13730 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13731 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13732 "TARGET_32BIT"
13733 "@
13734 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
13735 subfic %0,%1,0\;addze %0,%3
13736 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
13737 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
13738 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
13739 [(set_attr "type" "three,two,three,three,three")
13740 (set_attr "length" "12,8,12,12,12")])
13742 (define_insn "*compare_plus_eqsi"
13743 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13744 (compare:CC
13745 (plus:SI
13746 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13747 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13748 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13749 (const_int 0)))
13750 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13751 "TARGET_32BIT && optimize_size"
13752 "@
13753 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13754 subfic %4,%1,0\;addze. %4,%3
13755 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
13756 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
13757 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13758 #
13759 #
13760 #
13761 #
13762 #"
13763 [(set_attr "type" "compare")
13764 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13766 (define_split
13767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13768 (compare:CC
13769 (plus:SI
13770 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13771 (match_operand:SI 2 "scc_eq_operand" ""))
13772 (match_operand:SI 3 "gpc_reg_operand" ""))
13773 (const_int 0)))
13774 (clobber (match_scratch:SI 4 ""))]
13775 "TARGET_32BIT && optimize_size && reload_completed"
13776 [(set (match_dup 4)
13777 (plus:SI (eq:SI (match_dup 1)
13778 (match_dup 2))
13779 (match_dup 3)))
13780 (set (match_dup 0)
13781 (compare:CC (match_dup 4)
13782 (const_int 0)))]
13783 "")
13785 (define_insn "*plus_eqsi_compare"
13786 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13787 (compare:CC
13788 (plus:SI
13789 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13790 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13791 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13792 (const_int 0)))
13793 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13794 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13795 "TARGET_32BIT && optimize_size"
13796 "@
13797 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13798 subfic %0,%1,0\;addze. %0,%3
13799 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
13800 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
13801 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13802 #
13803 #
13804 #
13805 #
13806 #"
13807 [(set_attr "type" "compare")
13808 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13810 (define_split
13811 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13812 (compare:CC
13813 (plus:SI
13814 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13815 (match_operand:SI 2 "scc_eq_operand" ""))
13816 (match_operand:SI 3 "gpc_reg_operand" ""))
13817 (const_int 0)))
13818 (set (match_operand:SI 0 "gpc_reg_operand" "")
13819 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13820 "TARGET_32BIT && optimize_size && reload_completed"
13821 [(set (match_dup 0)
13822 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13823 (set (match_dup 4)
13824 (compare:CC (match_dup 0)
13825 (const_int 0)))]
13826 "")
13828 (define_insn "*neg_eq0<mode>"
13829 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13830 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13831 (const_int 0))))]
13832 ""
13833 "addic %0,%1,-1\;subfe %0,%0,%0"
13834 [(set_attr "type" "two")
13835 (set_attr "length" "8")])
13837 (define_insn_and_split "*neg_eq<mode>"
13838 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13839 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13840 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13841 ""
13842 "#"
13843 ""
13844 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13845 {
13846 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13847 {
13848 /* Use output operand as intermediate. */
13849 operands[3] = operands[0];
13851 if (logical_operand (operands[2], <MODE>mode))
13852 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13853 gen_rtx_XOR (<MODE>mode,
13854 operands[1], operands[2])));
13855 else
13856 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13857 gen_rtx_PLUS (<MODE>mode, operands[1],
13858 negate_rtx (<MODE>mode,
13859 operands[2]))));
13860 }
13861 else
13862 operands[3] = operands[1];
13863 })
13865 (define_insn "*ne0_<mode>"
13866 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13867 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13868 (const_int 0)))
13869 (clobber (match_scratch:P 2 "=&r"))]
13870 "!(TARGET_32BIT && TARGET_ISEL)"
13871 "addic %2,%1,-1\;subfe %0,%2,%1"
13872 [(set_attr "type" "two")
13873 (set_attr "length" "8")])
13875 (define_insn "*plus_ne0_<mode>"
13876 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13877 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13878 (const_int 0))
13879 (match_operand:P 2 "gpc_reg_operand" "r")))
13880 (clobber (match_scratch:P 3 "=&r"))]
13881 ""
13882 "addic %3,%1,-1\;addze %0,%2"
13883 [(set_attr "type" "two")
13884 (set_attr "length" "8")])
13886 (define_insn "*compare_plus_ne0_<mode>"
13887 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13888 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13889 (const_int 0))
13890 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13891 (const_int 0)))
13892 (clobber (match_scratch:P 3 "=&r,&r"))
13893 (clobber (match_scratch:P 4 "=X,&r"))]
13894 ""
13895 "@
13896 addic %3,%1,-1\;addze. %3,%2
13897 #"
13898 [(set_attr "type" "compare")
13899 (set_attr "length" "8,12")])
13901 (define_split
13902 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13903 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13904 (const_int 0))
13905 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13906 (clobber (match_scratch:P 3 ""))
13907 (clobber (match_scratch:P 4 ""))]
13908 "reload_completed"
13909 [(parallel [(set (match_dup 3)
13910 (plus:P (ne:P (match_dup 1)
13911 (const_int 0))
13912 (match_dup 2)))
13913 (clobber (match_dup 4))])
13914 (set (match_dup 0)
13915 (compare:CC (match_dup 3)
13916 (const_int 0)))]
13917 "")
13919 ; For combine.
13920 (define_insn "*compare_plus_ne0_<mode>_1"
13921 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13922 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13923 (const_int 0))
13924 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
13925 (clobber (match_scratch:P 3 "=&r,&r"))
13926 (clobber (match_scratch:P 4 "=X,&r"))]
13927 ""
13928 "@
13929 addic %3,%1,-1\;addze. %3,%2
13930 #"
13931 [(set_attr "type" "compare")
13932 (set_attr "length" "8,12")])
13934 (define_split
13935 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
13936 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13937 (const_int 0))
13938 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13939 (clobber (match_scratch:P 3 ""))
13940 (clobber (match_scratch:P 4 ""))]
13941 "reload_completed"
13942 [(parallel [(set (match_dup 3)
13943 (plus:P (ne:P (match_dup 1)
13944 (const_int 0))
13945 (match_dup 2)))
13946 (clobber (match_dup 4))])
13947 (set (match_dup 0)
13948 (compare:CC (match_dup 3)
13949 (const_int 0)))]
13950 "")
13952 (define_insn "*plus_ne0_<mode>_compare"
13953 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13954 (compare:CC
13955 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13956 (const_int 0))
13957 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13958 (const_int 0)))
13959 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13960 (plus:P (ne:P (match_dup 1)
13961 (const_int 0))
13962 (match_dup 2)))
13963 (clobber (match_scratch:P 3 "=&r,&r"))]
13964 ""
13965 "@
13966 addic %3,%1,-1\;addze. %0,%2
13967 #"
13968 [(set_attr "type" "compare")
13969 (set_attr "length" "8,12")])
13971 (define_split
13972 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13973 (compare:CC
13974 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
13975 (const_int 0))
13976 (match_operand:P 2 "gpc_reg_operand" ""))
13977 (const_int 0)))
13978 (set (match_operand:P 0 "gpc_reg_operand" "")
13979 (plus:P (ne:P (match_dup 1)
13980 (const_int 0))
13981 (match_dup 2)))
13982 (clobber (match_scratch:P 3 ""))]
13983 "reload_completed"
13984 [(parallel [(set (match_dup 0)
13985 (plus:P (ne:P (match_dup 1)
13986 (const_int 0))
13987 (match_dup 2)))
13988 (clobber (match_dup 3))])
13989 (set (match_dup 4)
13990 (compare:CC (match_dup 0)
13991 (const_int 0)))]
13992 "")
13994 (define_insn "*leu<mode>"
13995 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13996 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13997 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13998 ""
13999 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
14000 [(set_attr "type" "three")
14001 (set_attr "length" "12")])
14003 (define_insn "*leu<mode>_compare"
14004 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14005 (compare:CC
14006 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14007 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14008 (const_int 0)))
14009 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14010 (leu:P (match_dup 1) (match_dup 2)))]
14011 ""
14012 "@
14013 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
14014 #"
14015 [(set_attr "type" "compare")
14016 (set_attr "length" "12,16")])
14018 (define_split
14019 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14020 (compare:CC
14021 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
14022 (match_operand:P 2 "reg_or_short_operand" ""))
14023 (const_int 0)))
14024 (set (match_operand:P 0 "gpc_reg_operand" "")
14025 (leu:P (match_dup 1) (match_dup 2)))]
14026 "reload_completed"
14027 [(set (match_dup 0)
14028 (leu:P (match_dup 1) (match_dup 2)))
14029 (set (match_dup 3)
14030 (compare:CC (match_dup 0)
14031 (const_int 0)))]
14032 "")
14034 (define_insn "*plus_leu<mode>"
14035 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14036 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14037 (match_operand:P 2 "reg_or_short_operand" "rI"))
14038 (match_operand:P 3 "gpc_reg_operand" "r")))]
14039 ""
14040 "subf%I2c %0,%1,%2\;addze %0,%3"
14041 [(set_attr "type" "two")
14042 (set_attr "length" "8")])
14044 (define_insn ""
14045 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14046 (compare:CC
14047 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14048 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14049 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14050 (const_int 0)))
14051 (clobber (match_scratch:SI 4 "=&r,&r"))]
14052 "TARGET_32BIT"
14053 "@
14054 subf%I2c %4,%1,%2\;addze. %4,%3
14055 #"
14056 [(set_attr "type" "compare")
14057 (set_attr "length" "8,12")])
14059 (define_split
14060 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14061 (compare:CC
14062 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14063 (match_operand:SI 2 "reg_or_short_operand" ""))
14064 (match_operand:SI 3 "gpc_reg_operand" ""))
14065 (const_int 0)))
14066 (clobber (match_scratch:SI 4 ""))]
14067 "TARGET_32BIT && reload_completed"
14068 [(set (match_dup 4)
14069 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
14070 (match_dup 3)))
14071 (set (match_dup 0)
14072 (compare:CC (match_dup 4)
14073 (const_int 0)))]
14074 "")
14076 (define_insn ""
14077 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14078 (compare:CC
14079 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14080 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14081 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14082 (const_int 0)))
14083 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14084 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14085 "TARGET_32BIT"
14086 "@
14087 subf%I2c %0,%1,%2\;addze. %0,%3
14088 #"
14089 [(set_attr "type" "compare")
14090 (set_attr "length" "8,12")])
14092 (define_split
14093 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14094 (compare:CC
14095 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14096 (match_operand:SI 2 "reg_or_short_operand" ""))
14097 (match_operand:SI 3 "gpc_reg_operand" ""))
14098 (const_int 0)))
14099 (set (match_operand:SI 0 "gpc_reg_operand" "")
14100 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14101 "TARGET_32BIT && reload_completed"
14102 [(set (match_dup 0)
14103 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14104 (set (match_dup 4)
14105 (compare:CC (match_dup 0)
14106 (const_int 0)))]
14107 "")
14109 (define_insn "*neg_leu<mode>"
14110 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14111 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14112 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14113 ""
14114 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
14115 [(set_attr "type" "three")
14116 (set_attr "length" "12")])
14118 (define_insn "*and_neg_leu<mode>"
14119 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14120 (and:P (neg:P
14121 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14122 (match_operand:P 2 "reg_or_short_operand" "rI")))
14123 (match_operand:P 3 "gpc_reg_operand" "r")))]
14124 ""
14125 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
14126 [(set_attr "type" "three")
14127 (set_attr "length" "12")])
14129 (define_insn ""
14130 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14131 (compare:CC
14132 (and:SI (neg:SI
14133 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14134 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14135 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14136 (const_int 0)))
14137 (clobber (match_scratch:SI 4 "=&r,&r"))]
14138 "TARGET_32BIT"
14139 "@
14140 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
14141 #"
14142 [(set_attr "type" "compare")
14143 (set_attr "length" "12,16")])
14145 (define_split
14146 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14147 (compare:CC
14148 (and:SI (neg:SI
14149 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14150 (match_operand:SI 2 "reg_or_short_operand" "")))
14151 (match_operand:SI 3 "gpc_reg_operand" ""))
14152 (const_int 0)))
14153 (clobber (match_scratch:SI 4 ""))]
14154 "TARGET_32BIT && reload_completed"
14155 [(set (match_dup 4)
14156 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14157 (match_dup 3)))
14158 (set (match_dup 0)
14159 (compare:CC (match_dup 4)
14160 (const_int 0)))]
14161 "")
14163 (define_insn ""
14164 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14165 (compare:CC
14166 (and:SI (neg:SI
14167 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14168 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14169 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14170 (const_int 0)))
14171 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14172 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14173 "TARGET_32BIT"
14174 "@
14175 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
14176 #"
14177 [(set_attr "type" "compare")
14178 (set_attr "length" "12,16")])
14180 (define_split
14181 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14182 (compare:CC
14183 (and:SI (neg:SI
14184 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14185 (match_operand:SI 2 "reg_or_short_operand" "")))
14186 (match_operand:SI 3 "gpc_reg_operand" ""))
14187 (const_int 0)))
14188 (set (match_operand:SI 0 "gpc_reg_operand" "")
14189 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14190 "TARGET_32BIT && reload_completed"
14191 [(set (match_dup 0)
14192 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14193 (match_dup 3)))
14194 (set (match_dup 4)
14195 (compare:CC (match_dup 0)
14196 (const_int 0)))]
14197 "")
14199 (define_insn_and_split "*ltu<mode>"
14200 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14201 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14202 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14203 ""
14204 "#"
14205 ""
14206 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14207 (set (match_dup 0) (neg:P (match_dup 0)))]
14208 "")
14210 (define_insn_and_split "*ltu<mode>_compare"
14211 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14212 (compare:CC
14213 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14214 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14215 (const_int 0)))
14216 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14217 (ltu:P (match_dup 1) (match_dup 2)))]
14218 ""
14219 "#"
14220 ""
14221 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14222 (parallel [(set (match_dup 3)
14223 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14224 (set (match_dup 0) (neg:P (match_dup 0)))])]
14225 "")
14227 (define_insn_and_split "*plus_ltu<mode>"
14228 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14229 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14230 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14231 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14232 ""
14233 "#"
14234 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14235 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14236 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14237 "")
14239 (define_insn_and_split "*plus_ltu<mode>_compare"
14240 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14241 (compare:CC
14242 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14243 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14244 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14245 (const_int 0)))
14246 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14247 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14248 ""
14249 "#"
14250 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14251 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14252 (parallel [(set (match_dup 4)
14253 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14254 (const_int 0)))
14255 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14256 "")
14258 (define_insn "*neg_ltu<mode>"
14259 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14260 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14261 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14262 ""
14263 "@
14264 subfc %0,%2,%1\;subfe %0,%0,%0
14265 addic %0,%1,%n2\;subfe %0,%0,%0"
14266 [(set_attr "type" "two")
14267 (set_attr "length" "8")])
14269 (define_insn "*geu<mode>"
14270 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14271 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14272 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14273 ""
14274 "@
14275 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
14276 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
14277 [(set_attr "type" "three")
14278 (set_attr "length" "12")])
14280 (define_insn "*geu<mode>_compare"
14281 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14282 (compare:CC
14283 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14284 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14285 (const_int 0)))
14286 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14287 (geu:P (match_dup 1) (match_dup 2)))]
14288 ""
14289 "@
14290 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
14291 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
14292 #
14293 #"
14294 [(set_attr "type" "compare")
14295 (set_attr "length" "12,12,16,16")])
14297 (define_split
14298 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14299 (compare:CC
14300 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14301 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14302 (const_int 0)))
14303 (set (match_operand:P 0 "gpc_reg_operand" "")
14304 (geu:P (match_dup 1) (match_dup 2)))]
14305 "reload_completed"
14306 [(set (match_dup 0)
14307 (geu:P (match_dup 1) (match_dup 2)))
14308 (set (match_dup 3)
14309 (compare:CC (match_dup 0)
14310 (const_int 0)))]
14311 "")
14313 (define_insn "*plus_geu<mode>"
14314 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14315 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14316 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14317 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14318 ""
14319 "@
14320 subfc %0,%2,%1\;addze %0,%3
14321 addic %0,%1,%n2\;addze %0,%3"
14322 [(set_attr "type" "two")
14323 (set_attr "length" "8")])
14325 (define_insn ""
14326 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14327 (compare:CC
14328 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14329 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14330 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14331 (const_int 0)))
14332 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14333 "TARGET_32BIT"
14334 "@
14335 subfc %4,%2,%1\;addze. %4,%3
14336 addic %4,%1,%n2\;addze. %4,%3
14337 #
14338 #"
14339 [(set_attr "type" "compare")
14340 (set_attr "length" "8,8,12,12")])
14342 (define_split
14343 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14344 (compare:CC
14345 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14346 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14347 (match_operand:SI 3 "gpc_reg_operand" ""))
14348 (const_int 0)))
14349 (clobber (match_scratch:SI 4 ""))]
14350 "TARGET_32BIT && reload_completed"
14351 [(set (match_dup 4)
14352 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14353 (match_dup 3)))
14354 (set (match_dup 0)
14355 (compare:CC (match_dup 4)
14356 (const_int 0)))]
14357 "")
14359 (define_insn ""
14360 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14361 (compare:CC
14362 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14363 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14364 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14365 (const_int 0)))
14366 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14367 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14368 "TARGET_32BIT"
14369 "@
14370 subfc %0,%2,%1\;addze. %0,%3
14371 addic %0,%1,%n2\;addze. %0,%3
14372 #
14373 #"
14374 [(set_attr "type" "compare")
14375 (set_attr "length" "8,8,12,12")])
14377 (define_split
14378 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14379 (compare:CC
14380 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14381 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14382 (match_operand:SI 3 "gpc_reg_operand" ""))
14383 (const_int 0)))
14384 (set (match_operand:SI 0 "gpc_reg_operand" "")
14385 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14386 "TARGET_32BIT && reload_completed"
14387 [(set (match_dup 0)
14388 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14389 (set (match_dup 4)
14390 (compare:CC (match_dup 0)
14391 (const_int 0)))]
14392 "")
14394 (define_insn "*neg_geu<mode>"
14395 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14396 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14397 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14398 ""
14399 "@
14400 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
14401 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
14402 [(set_attr "type" "three")
14403 (set_attr "length" "12")])
14405 (define_insn "*and_neg_geu<mode>"
14406 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14407 (and:P (neg:P
14408 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14409 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14410 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14411 ""
14412 "@
14413 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
14414 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
14415 [(set_attr "type" "three")
14416 (set_attr "length" "12")])
14418 (define_insn ""
14419 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14420 (compare:CC
14421 (and:SI (neg:SI
14422 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14423 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14424 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14425 (const_int 0)))
14426 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14427 "TARGET_32BIT"
14428 "@
14429 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
14430 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
14431 #
14432 #"
14433 [(set_attr "type" "compare")
14434 (set_attr "length" "12,12,16,16")])
14436 (define_split
14437 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14438 (compare:CC
14439 (and:SI (neg:SI
14440 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14441 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14442 (match_operand:SI 3 "gpc_reg_operand" ""))
14443 (const_int 0)))
14444 (clobber (match_scratch:SI 4 ""))]
14445 "TARGET_32BIT && reload_completed"
14446 [(set (match_dup 4)
14447 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14448 (match_dup 3)))
14449 (set (match_dup 0)
14450 (compare:CC (match_dup 4)
14451 (const_int 0)))]
14452 "")
14454 (define_insn ""
14455 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14456 (compare:CC
14457 (and:SI (neg:SI
14458 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14459 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14460 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14461 (const_int 0)))
14462 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14463 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14464 "TARGET_32BIT"
14465 "@
14466 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
14467 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
14468 #
14469 #"
14470 [(set_attr "type" "compare")
14471 (set_attr "length" "12,12,16,16")])
14473 (define_split
14474 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14475 (compare:CC
14476 (and:SI (neg:SI
14477 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14478 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14479 (match_operand:SI 3 "gpc_reg_operand" ""))
14480 (const_int 0)))
14481 (set (match_operand:SI 0 "gpc_reg_operand" "")
14482 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14483 "TARGET_32BIT && reload_completed"
14484 [(set (match_dup 0)
14485 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14486 (set (match_dup 4)
14487 (compare:CC (match_dup 0)
14488 (const_int 0)))]
14489 "")
14491 (define_insn "*plus_gt0<mode>"
14492 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14493 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14494 (const_int 0))
14495 (match_operand:P 2 "gpc_reg_operand" "r")))]
14496 ""
14497 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
14498 [(set_attr "type" "three")
14499 (set_attr "length" "12")])
14501 (define_insn ""
14502 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14503 (compare:CC
14504 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14505 (const_int 0))
14506 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14507 (const_int 0)))
14508 (clobber (match_scratch:SI 3 "=&r,&r"))]
14509 "TARGET_32BIT"
14510 "@
14511 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14512 #"
14513 [(set_attr "type" "compare")
14514 (set_attr "length" "12,16")])
14516 (define_split
14517 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14518 (compare:CC
14519 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14520 (const_int 0))
14521 (match_operand:SI 2 "gpc_reg_operand" ""))
14522 (const_int 0)))
14523 (clobber (match_scratch:SI 3 ""))]
14524 "TARGET_32BIT && reload_completed"
14525 [(set (match_dup 3)
14526 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14527 (match_dup 2)))
14528 (set (match_dup 0)
14529 (compare:CC (match_dup 3)
14530 (const_int 0)))]
14531 "")
14533 (define_insn ""
14534 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14535 (compare:CC
14536 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14537 (const_int 0))
14538 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14539 (const_int 0)))
14540 (clobber (match_scratch:DI 3 "=&r,&r"))]
14541 "TARGET_64BIT"
14542 "@
14543 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14544 #"
14545 [(set_attr "type" "compare")
14546 (set_attr "length" "12,16")])
14548 (define_split
14549 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14550 (compare:CC
14551 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14552 (const_int 0))
14553 (match_operand:DI 2 "gpc_reg_operand" ""))
14554 (const_int 0)))
14555 (clobber (match_scratch:DI 3 ""))]
14556 "TARGET_64BIT && reload_completed"
14557 [(set (match_dup 3)
14558 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14559 (match_dup 2)))
14560 (set (match_dup 0)
14561 (compare:CC (match_dup 3)
14562 (const_int 0)))]
14563 "")
14565 (define_insn ""
14566 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14567 (compare:CC
14568 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14569 (const_int 0))
14570 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14571 (const_int 0)))
14572 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14573 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14574 "TARGET_32BIT"
14575 "@
14576 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14577 #"
14578 [(set_attr "type" "compare")
14579 (set_attr "length" "12,16")])
14581 (define_split
14582 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14583 (compare:CC
14584 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14585 (const_int 0))
14586 (match_operand:SI 2 "gpc_reg_operand" ""))
14587 (const_int 0)))
14588 (set (match_operand:SI 0 "gpc_reg_operand" "")
14589 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14590 "TARGET_32BIT && reload_completed"
14591 [(set (match_dup 0)
14592 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14593 (set (match_dup 3)
14594 (compare:CC (match_dup 0)
14595 (const_int 0)))]
14596 "")
14598 (define_insn ""
14599 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14600 (compare:CC
14601 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14602 (const_int 0))
14603 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14604 (const_int 0)))
14605 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14606 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14607 "TARGET_64BIT"
14608 "@
14609 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14610 #"
14611 [(set_attr "type" "compare")
14612 (set_attr "length" "12,16")])
14614 (define_split
14615 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14616 (compare:CC
14617 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14618 (const_int 0))
14619 (match_operand:DI 2 "gpc_reg_operand" ""))
14620 (const_int 0)))
14621 (set (match_operand:DI 0 "gpc_reg_operand" "")
14622 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14623 "TARGET_64BIT && reload_completed"
14624 [(set (match_dup 0)
14625 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14626 (set (match_dup 3)
14627 (compare:CC (match_dup 0)
14628 (const_int 0)))]
14629 "")
14631 (define_insn_and_split "*gtu<mode>"
14632 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14633 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14634 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14635 ""
14636 "#"
14637 ""
14638 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14639 (set (match_dup 0) (neg:P (match_dup 0)))]
14640 "")
14642 (define_insn_and_split "*gtu<mode>_compare"
14643 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14644 (compare:CC
14645 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14646 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14647 (const_int 0)))
14648 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14649 (gtu:P (match_dup 1) (match_dup 2)))]
14650 ""
14651 "#"
14652 ""
14653 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14654 (parallel [(set (match_dup 3)
14655 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14656 (set (match_dup 0) (neg:P (match_dup 0)))])]
14657 "")
14659 (define_insn_and_split "*plus_gtu<mode>"
14660 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14661 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14662 (match_operand:P 2 "reg_or_short_operand" "rI"))
14663 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14664 ""
14665 "#"
14666 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14667 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14668 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14669 "")
14671 (define_insn_and_split "*plus_gtu<mode>_compare"
14672 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14673 (compare:CC
14674 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14675 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14676 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14677 (const_int 0)))
14678 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14679 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14680 ""
14681 "#"
14682 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14683 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14684 (parallel [(set (match_dup 4)
14685 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14686 (const_int 0)))
14687 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14688 "")
14690 (define_insn "*neg_gtu<mode>"
14691 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14692 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14693 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14694 ""
14695 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
14696 [(set_attr "type" "two")
14697 (set_attr "length" "8")])
14699 \f
14700 ;; Define both directions of branch and return. If we need a reload
14701 ;; register, we'd rather use CR0 since it is much easier to copy a
14702 ;; register CC value to there.
14704 (define_insn ""
14705 [(set (pc)
14706 (if_then_else (match_operator 1 "branch_comparison_operator"
14707 [(match_operand 2
14708 "cc_reg_operand" "y")
14709 (const_int 0)])
14710 (label_ref (match_operand 0 "" ""))
14711 (pc)))]
14712 ""
14713 "*
14714 {
14715 return output_cbranch (operands[1], \"%l0\", 0, insn);
14716 }"
14717 [(set_attr "type" "branch")])
14719 (define_insn ""
14720 [(set (pc)
14721 (if_then_else (match_operator 0 "branch_comparison_operator"
14722 [(match_operand 1
14723 "cc_reg_operand" "y")
14724 (const_int 0)])
14725 (any_return)
14726 (pc)))]
14727 "<return_pred>"
14728 "*
14729 {
14730 return output_cbranch (operands[0], NULL, 0, insn);
14731 }"
14732 [(set_attr "type" "jmpreg")
14733 (set_attr "length" "4")])
14735 (define_insn ""
14736 [(set (pc)
14737 (if_then_else (match_operator 1 "branch_comparison_operator"
14738 [(match_operand 2
14739 "cc_reg_operand" "y")
14740 (const_int 0)])
14741 (pc)
14742 (label_ref (match_operand 0 "" ""))))]
14743 ""
14744 "*
14745 {
14746 return output_cbranch (operands[1], \"%l0\", 1, insn);
14747 }"
14748 [(set_attr "type" "branch")])
14750 (define_insn ""
14751 [(set (pc)
14752 (if_then_else (match_operator 0 "branch_comparison_operator"
14753 [(match_operand 1
14754 "cc_reg_operand" "y")
14755 (const_int 0)])
14756 (pc)
14757 (any_return)))]
14758 "<return_pred>"
14759 "*
14760 {
14761 return output_cbranch (operands[0], NULL, 1, insn);
14762 }"
14763 [(set_attr "type" "jmpreg")
14764 (set_attr "length" "4")])
14766 ;; Logic on condition register values.
14768 ; This pattern matches things like
14769 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14770 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14771 ; (const_int 1)))
14772 ; which are generated by the branch logic.
14773 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14775 (define_insn "*cceq_ior_compare"
14776 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14777 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14778 [(match_operator:SI 2
14779 "branch_positive_comparison_operator"
14780 [(match_operand 3
14781 "cc_reg_operand" "y,y")
14782 (const_int 0)])
14783 (match_operator:SI 4
14784 "branch_positive_comparison_operator"
14785 [(match_operand 5
14786 "cc_reg_operand" "0,y")
14787 (const_int 0)])])
14788 (const_int 1)))]
14789 ""
14790 "cr%q1 %E0,%j2,%j4"
14791 [(set_attr "type" "cr_logical,delayed_cr")])
14793 ; Why is the constant -1 here, but 1 in the previous pattern?
14794 ; Because ~1 has all but the low bit set.
14795 (define_insn ""
14796 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14797 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14798 [(not:SI (match_operator:SI 2
14799 "branch_positive_comparison_operator"
14800 [(match_operand 3
14801 "cc_reg_operand" "y,y")
14802 (const_int 0)]))
14803 (match_operator:SI 4
14804 "branch_positive_comparison_operator"
14805 [(match_operand 5
14806 "cc_reg_operand" "0,y")
14807 (const_int 0)])])
14808 (const_int -1)))]
14809 ""
14810 "cr%q1 %E0,%j2,%j4"
14811 [(set_attr "type" "cr_logical,delayed_cr")])
14813 (define_insn "*cceq_rev_compare"
14814 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14815 (compare:CCEQ (match_operator:SI 1
14816 "branch_positive_comparison_operator"
14817 [(match_operand 2
14818 "cc_reg_operand" "0,y")
14819 (const_int 0)])
14820 (const_int 0)))]
14821 ""
14822 "crnot %E0,%j1"
14823 [(set_attr "type" "cr_logical,delayed_cr")])
14825 ;; If we are comparing the result of two comparisons, this can be done
14826 ;; using creqv or crxor.
14828 (define_insn_and_split ""
14829 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14830 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14831 [(match_operand 2 "cc_reg_operand" "y")
14832 (const_int 0)])
14833 (match_operator 3 "branch_comparison_operator"
14834 [(match_operand 4 "cc_reg_operand" "y")
14835 (const_int 0)])))]
14836 ""
14837 "#"
14838 ""
14839 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14840 (match_dup 5)))]
14841 "
14842 {
14843 int positive_1, positive_2;
14845 positive_1 = branch_positive_comparison_operator (operands[1],
14846 GET_MODE (operands[1]));
14847 positive_2 = branch_positive_comparison_operator (operands[3],
14848 GET_MODE (operands[3]));
14850 if (! positive_1)
14851 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14852 GET_CODE (operands[1])),
14853 SImode,
14854 operands[2], const0_rtx);
14855 else if (GET_MODE (operands[1]) != SImode)
14856 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14857 operands[2], const0_rtx);
14859 if (! positive_2)
14860 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14861 GET_CODE (operands[3])),
14862 SImode,
14863 operands[4], const0_rtx);
14864 else if (GET_MODE (operands[3]) != SImode)
14865 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14866 operands[4], const0_rtx);
14868 if (positive_1 == positive_2)
14869 {
14870 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14871 operands[5] = constm1_rtx;
14872 }
14873 else
14874 {
14875 operands[5] = const1_rtx;
14876 }
14877 }")
14879 ;; Unconditional branch and return.
14881 (define_insn "jump"
14882 [(set (pc)
14883 (label_ref (match_operand 0 "" "")))]
14884 ""
14885 "b %l0"
14886 [(set_attr "type" "branch")])
14888 (define_insn "<return_str>return"
14889 [(any_return)]
14890 "<return_pred>"
14891 "blr"
14892 [(set_attr "type" "jmpreg")])
14894 (define_expand "indirect_jump"
14895 [(set (pc) (match_operand 0 "register_operand" ""))])
14897 (define_insn "*indirect_jump<mode>"
14898 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14899 ""
14900 "@
14901 bctr
14902 blr"
14903 [(set_attr "type" "jmpreg")])
14905 ;; Table jump for switch statements:
14906 (define_expand "tablejump"
14907 [(use (match_operand 0 "" ""))
14908 (use (label_ref (match_operand 1 "" "")))]
14909 ""
14910 "
14911 {
14912 if (TARGET_32BIT)
14913 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14914 else
14915 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14916 DONE;
14917 }")
14919 (define_expand "tablejumpsi"
14920 [(set (match_dup 3)
14921 (plus:SI (match_operand:SI 0 "" "")
14922 (match_dup 2)))
14923 (parallel [(set (pc) (match_dup 3))
14924 (use (label_ref (match_operand 1 "" "")))])]
14925 "TARGET_32BIT"
14926 "
14927 { operands[0] = force_reg (SImode, operands[0]);
14928 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14929 operands[3] = gen_reg_rtx (SImode);
14930 }")
14932 (define_expand "tablejumpdi"
14933 [(set (match_dup 4)
14934 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14935 (set (match_dup 3)
14936 (plus:DI (match_dup 4)
14937 (match_dup 2)))
14938 (parallel [(set (pc) (match_dup 3))
14939 (use (label_ref (match_operand 1 "" "")))])]
14940 "TARGET_64BIT"
14941 "
14942 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14943 operands[3] = gen_reg_rtx (DImode);
14944 operands[4] = gen_reg_rtx (DImode);
14945 }")
14947 (define_insn "*tablejump<mode>_internal1"
14948 [(set (pc)
14949 (match_operand:P 0 "register_operand" "c,*l"))
14950 (use (label_ref (match_operand 1 "" "")))]
14951 ""
14952 "@
14953 bctr
14954 blr"
14955 [(set_attr "type" "jmpreg")])
14957 (define_insn "nop"
14958 [(const_int 0)]
14959 ""
14960 "nop")
14962 (define_insn "group_ending_nop"
14963 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
14964 ""
14965 "*
14966 {
14967 if (rs6000_cpu_attr == CPU_POWER6)
14968 return \"ori 1,1,0\";
14969 return \"ori 2,2,0\";
14970 }")
14971 \f
14972 ;; Define the subtract-one-and-jump insns, starting with the template
14973 ;; so loop.c knows what to generate.
14975 (define_expand "doloop_end"
14976 [(use (match_operand 0 "" "")) ; loop pseudo
14977 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14978 (use (match_operand 2 "" "")) ; max iterations
14979 (use (match_operand 3 "" "")) ; loop level
14980 (use (match_operand 4 "" "")) ; label
14981 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
14982 ""
14983 "
14984 {
14985 /* Only use this on innermost loops. */
14986 if (INTVAL (operands[3]) > 1)
14987 FAIL;
14988 if (TARGET_64BIT)
14989 {
14990 if (GET_MODE (operands[0]) != DImode)
14991 FAIL;
14992 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14993 }
14994 else
14995 {
14996 if (GET_MODE (operands[0]) != SImode)
14997 FAIL;
14998 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14999 }
15000 DONE;
15001 }")
15003 (define_expand "ctr<mode>"
15004 [(parallel [(set (pc)
15005 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15006 (const_int 1))
15007 (label_ref (match_operand 1 "" ""))
15008 (pc)))
15009 (set (match_dup 0)
15010 (plus:P (match_dup 0)
15011 (const_int -1)))
15012 (clobber (match_scratch:CC 2 ""))
15013 (clobber (match_scratch:P 3 ""))])]
15014 ""
15015 "")
15017 ;; We need to be able to do this for any operand, including MEM, or we
15018 ;; will cause reload to blow up since we don't allow output reloads on
15019 ;; JUMP_INSNs.
15020 ;; For the length attribute to be calculated correctly, the
15021 ;; label MUST be operand 0.
15023 (define_insn "*ctr<mode>_internal1"
15024 [(set (pc)
15025 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15026 (const_int 1))
15027 (label_ref (match_operand 0 "" ""))
15028 (pc)))
15029 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
15030 (plus:P (match_dup 1)
15031 (const_int -1)))
15032 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15033 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15034 ""
15035 "*
15036 {
15037 if (which_alternative != 0)
15038 return \"#\";
15039 else if (get_attr_length (insn) == 4)
15040 return \"bdnz %l0\";
15041 else
15042 return \"bdz $+8\;b %l0\";
15043 }"
15044 [(set_attr "type" "branch")
15045 (set_attr "length" "*,12,16,16")])
15047 (define_insn "*ctr<mode>_internal2"
15048 [(set (pc)
15049 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15050 (const_int 1))
15051 (pc)
15052 (label_ref (match_operand 0 "" ""))))
15053 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
15054 (plus:P (match_dup 1)
15055 (const_int -1)))
15056 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15057 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15058 ""
15059 "*
15060 {
15061 if (which_alternative != 0)
15062 return \"#\";
15063 else if (get_attr_length (insn) == 4)
15064 return \"bdz %l0\";
15065 else
15066 return \"bdnz $+8\;b %l0\";
15067 }"
15068 [(set_attr "type" "branch")
15069 (set_attr "length" "*,12,16,16")])
15071 ;; Similar but use EQ
15073 (define_insn "*ctr<mode>_internal5"
15074 [(set (pc)
15075 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15076 (const_int 1))
15077 (label_ref (match_operand 0 "" ""))
15078 (pc)))
15079 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
15080 (plus:P (match_dup 1)
15081 (const_int -1)))
15082 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15083 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15084 ""
15085 "*
15086 {
15087 if (which_alternative != 0)
15088 return \"#\";
15089 else if (get_attr_length (insn) == 4)
15090 return \"bdz %l0\";
15091 else
15092 return \"bdnz $+8\;b %l0\";
15093 }"
15094 [(set_attr "type" "branch")
15095 (set_attr "length" "*,12,16,16")])
15097 (define_insn "*ctr<mode>_internal6"
15098 [(set (pc)
15099 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15100 (const_int 1))
15101 (pc)
15102 (label_ref (match_operand 0 "" ""))))
15103 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
15104 (plus:P (match_dup 1)
15105 (const_int -1)))
15106 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15107 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15108 ""
15109 "*
15110 {
15111 if (which_alternative != 0)
15112 return \"#\";
15113 else if (get_attr_length (insn) == 4)
15114 return \"bdnz %l0\";
15115 else
15116 return \"bdz $+8\;b %l0\";
15117 }"
15118 [(set_attr "type" "branch")
15119 (set_attr "length" "*,12,16,16")])
15121 ;; Now the splitters if we could not allocate the CTR register
15123 (define_split
15124 [(set (pc)
15125 (if_then_else (match_operator 2 "comparison_operator"
15126 [(match_operand:P 1 "gpc_reg_operand" "")
15127 (const_int 1)])
15128 (match_operand 5 "" "")
15129 (match_operand 6 "" "")))
15130 (set (match_operand:P 0 "gpc_reg_operand" "")
15131 (plus:P (match_dup 1) (const_int -1)))
15132 (clobber (match_scratch:CC 3 ""))
15133 (clobber (match_scratch:P 4 ""))]
15134 "reload_completed"
15135 [(parallel [(set (match_dup 3)
15136 (compare:CC (plus:P (match_dup 1)
15137 (const_int -1))
15138 (const_int 0)))
15139 (set (match_dup 0)
15140 (plus:P (match_dup 1)
15141 (const_int -1)))])
15142 (set (pc) (if_then_else (match_dup 7)
15143 (match_dup 5)
15144 (match_dup 6)))]
15145 "
15146 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15147 operands[3], const0_rtx); }")
15149 (define_split
15150 [(set (pc)
15151 (if_then_else (match_operator 2 "comparison_operator"
15152 [(match_operand:P 1 "gpc_reg_operand" "")
15153 (const_int 1)])
15154 (match_operand 5 "" "")
15155 (match_operand 6 "" "")))
15156 (set (match_operand:P 0 "nonimmediate_operand" "")
15157 (plus:P (match_dup 1) (const_int -1)))
15158 (clobber (match_scratch:CC 3 ""))
15159 (clobber (match_scratch:P 4 ""))]
15160 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15161 [(parallel [(set (match_dup 3)
15162 (compare:CC (plus:P (match_dup 1)
15163 (const_int -1))
15164 (const_int 0)))
15165 (set (match_dup 4)
15166 (plus:P (match_dup 1)
15167 (const_int -1)))])
15168 (set (match_dup 0)
15169 (match_dup 4))
15170 (set (pc) (if_then_else (match_dup 7)
15171 (match_dup 5)
15172 (match_dup 6)))]
15173 "
15174 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15175 operands[3], const0_rtx); }")
15176 \f
15177 (define_insn "trap"
15178 [(trap_if (const_int 1) (const_int 0))]
15179 ""
15180 "trap"
15181 [(set_attr "type" "trap")])
15183 (define_expand "ctrap<mode>4"
15184 [(trap_if (match_operator 0 "ordered_comparison_operator"
15185 [(match_operand:GPR 1 "register_operand")
15186 (match_operand:GPR 2 "reg_or_short_operand")])
15187 (match_operand 3 "zero_constant" ""))]
15188 ""
15189 "")
15191 (define_insn ""
15192 [(trap_if (match_operator 0 "ordered_comparison_operator"
15193 [(match_operand:GPR 1 "register_operand" "r")
15194 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15195 (const_int 0))]
15196 ""
15197 "t<wd>%V0%I2 %1,%2"
15198 [(set_attr "type" "trap")])
15199 \f
15200 ;; Insns related to generating the function prologue and epilogue.
15202 (define_expand "prologue"
15203 [(use (const_int 0))]
15204 ""
15205 {
15206 rs6000_emit_prologue ();
15207 if (!TARGET_SCHED_PROLOG)
15208 emit_insn (gen_blockage ());
15209 DONE;
15210 })
15212 (define_insn "*movesi_from_cr_one"
15213 [(match_parallel 0 "mfcr_operation"
15214 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15215 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15216 (match_operand 3 "immediate_operand" "n")]
15217 UNSPEC_MOVESI_FROM_CR))])]
15218 "TARGET_MFCRF"
15219 "*
15220 {
15221 int mask = 0;
15222 int i;
15223 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15224 {
15225 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15226 operands[4] = GEN_INT (mask);
15227 output_asm_insn (\"mfcr %1,%4\", operands);
15228 }
15229 return \"\";
15230 }"
15231 [(set_attr "type" "mfcrf")])
15233 (define_insn "movesi_from_cr"
15234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15235 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15236 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15237 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15238 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15239 UNSPEC_MOVESI_FROM_CR))]
15240 ""
15241 "mfcr %0"
15242 [(set_attr "type" "mfcr")])
15244 (define_insn "*stmw"
15245 [(match_parallel 0 "stmw_operation"
15246 [(set (match_operand:SI 1 "memory_operand" "=m")
15247 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15248 "TARGET_MULTIPLE"
15249 "stmw %2,%1"
15250 [(set_attr "type" "store_ux")])
15252 ; The following comment applies to:
15253 ; save_gpregs_*
15254 ; save_fpregs_*
15255 ; restore_gpregs*
15256 ; return_and_restore_gpregs*
15257 ; return_and_restore_fpregs*
15258 ; return_and_restore_fpregs_aix*
15259 ;
15260 ; The out-of-line save / restore functions expects one input argument.
15261 ; Since those are not standard call_insn's, we must avoid using
15262 ; MATCH_OPERAND for that argument. That way the register rename
15263 ; optimization will not try to rename this register.
15264 ; Each pattern is repeated for each possible register number used in
15265 ; various ABIs (r11, r1, and for some functions r12)
15267 (define_insn "*save_gpregs_<mode>_r11"
15268 [(match_parallel 0 "any_parallel_operand"
15269 [(clobber (reg:P 65))
15270 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15271 (use (reg:P 11))
15272 (set (match_operand:P 2 "memory_operand" "=m")
15273 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15274 ""
15275 "bl %1"
15276 [(set_attr "type" "branch")
15277 (set_attr "length" "4")])
15279 (define_insn "*save_gpregs_<mode>_r12"
15280 [(match_parallel 0 "any_parallel_operand"
15281 [(clobber (reg:P 65))
15282 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15283 (use (reg:P 12))
15284 (set (match_operand:P 2 "memory_operand" "=m")
15285 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15286 ""
15287 "bl %1"
15288 [(set_attr "type" "branch")
15289 (set_attr "length" "4")])
15291 (define_insn "*save_gpregs_<mode>_r1"
15292 [(match_parallel 0 "any_parallel_operand"
15293 [(clobber (reg:P 65))
15294 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15295 (use (reg:P 1))
15296 (set (match_operand:P 2 "memory_operand" "=m")
15297 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15298 ""
15299 "bl %1"
15300 [(set_attr "type" "branch")
15301 (set_attr "length" "4")])
15303 (define_insn "*save_fpregs_<mode>_r11"
15304 [(match_parallel 0 "any_parallel_operand"
15305 [(clobber (reg:P 65))
15306 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15307 (use (reg:P 11))
15308 (set (match_operand:DF 2 "memory_operand" "=m")
15309 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15310 ""
15311 "bl %1"
15312 [(set_attr "type" "branch")
15313 (set_attr "length" "4")])
15315 (define_insn "*save_fpregs_<mode>_r12"
15316 [(match_parallel 0 "any_parallel_operand"
15317 [(clobber (reg:P 65))
15318 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15319 (use (reg:P 12))
15320 (set (match_operand:DF 2 "memory_operand" "=m")
15321 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15322 ""
15323 "bl %1"
15324 [(set_attr "type" "branch")
15325 (set_attr "length" "4")])
15327 (define_insn "*save_fpregs_<mode>_r1"
15328 [(match_parallel 0 "any_parallel_operand"
15329 [(clobber (reg:P 65))
15330 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15331 (use (reg:P 1))
15332 (set (match_operand:DF 2 "memory_operand" "=m")
15333 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15334 ""
15335 "bl %1"
15336 [(set_attr "type" "branch")
15337 (set_attr "length" "4")])
15339 ; This is to explain that changes to the stack pointer should
15340 ; not be moved over loads from or stores to stack memory.
15341 (define_insn "stack_tie"
15342 [(match_parallel 0 "tie_operand"
15343 [(set (mem:BLK (reg 1)) (const_int 0))])]
15344 ""
15345 ""
15346 [(set_attr "length" "0")])
15348 (define_expand "epilogue"
15349 [(use (const_int 0))]
15350 ""
15351 {
15352 if (!TARGET_SCHED_PROLOG)
15353 emit_insn (gen_blockage ());
15354 rs6000_emit_epilogue (FALSE);
15355 DONE;
15356 })
15358 ; On some processors, doing the mtcrf one CC register at a time is
15359 ; faster (like on the 604e). On others, doing them all at once is
15360 ; faster; for instance, on the 601 and 750.
15362 (define_expand "movsi_to_cr_one"
15363 [(set (match_operand:CC 0 "cc_reg_operand" "")
15364 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15365 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15366 ""
15367 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15369 (define_insn "*movsi_to_cr"
15370 [(match_parallel 0 "mtcrf_operation"
15371 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15372 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15373 (match_operand 3 "immediate_operand" "n")]
15374 UNSPEC_MOVESI_TO_CR))])]
15375 ""
15376 "*
15377 {
15378 int mask = 0;
15379 int i;
15380 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15381 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15382 operands[4] = GEN_INT (mask);
15383 return \"mtcrf %4,%2\";
15384 }"
15385 [(set_attr "type" "mtcr")])
15387 (define_insn "*mtcrfsi"
15388 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15389 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15390 (match_operand 2 "immediate_operand" "n")]
15391 UNSPEC_MOVESI_TO_CR))]
15392 "GET_CODE (operands[0]) == REG
15393 && CR_REGNO_P (REGNO (operands[0]))
15394 && GET_CODE (operands[2]) == CONST_INT
15395 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15396 "mtcrf %R0,%1"
15397 [(set_attr "type" "mtcr")])
15399 ; The load-multiple instructions have similar properties.
15400 ; Note that "load_multiple" is a name known to the machine-independent
15401 ; code that actually corresponds to the PowerPC load-string.
15403 (define_insn "*lmw"
15404 [(match_parallel 0 "lmw_operation"
15405 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15406 (match_operand:SI 2 "memory_operand" "m"))])]
15407 "TARGET_MULTIPLE"
15408 "lmw %1,%2"
15409 [(set_attr "type" "load_ux")
15410 (set_attr "cell_micro" "always")])
15412 (define_insn "*return_internal_<mode>"
15413 [(simple_return)
15414 (use (match_operand:P 0 "register_operand" "lc"))]
15415 ""
15416 "b%T0"
15417 [(set_attr "type" "jmpreg")])
15419 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15420 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15422 ; The following comment applies to:
15423 ; save_gpregs_*
15424 ; save_fpregs_*
15425 ; restore_gpregs*
15426 ; return_and_restore_gpregs*
15427 ; return_and_restore_fpregs*
15428 ; return_and_restore_fpregs_aix*
15429 ;
15430 ; The out-of-line save / restore functions expects one input argument.
15431 ; Since those are not standard call_insn's, we must avoid using
15432 ; MATCH_OPERAND for that argument. That way the register rename
15433 ; optimization will not try to rename this register.
15434 ; Each pattern is repeated for each possible register number used in
15435 ; various ABIs (r11, r1, and for some functions r12)
15437 (define_insn "*restore_gpregs_<mode>_r11"
15438 [(match_parallel 0 "any_parallel_operand"
15439 [(clobber (match_operand:P 1 "register_operand" "=l"))
15440 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15441 (use (reg:P 11))
15442 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15443 (match_operand:P 4 "memory_operand" "m"))])]
15444 ""
15445 "bl %2"
15446 [(set_attr "type" "branch")
15447 (set_attr "length" "4")])
15449 (define_insn "*restore_gpregs_<mode>_r12"
15450 [(match_parallel 0 "any_parallel_operand"
15451 [(clobber (match_operand:P 1 "register_operand" "=l"))
15452 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15453 (use (reg:P 12))
15454 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15455 (match_operand:P 4 "memory_operand" "m"))])]
15456 ""
15457 "bl %2"
15458 [(set_attr "type" "branch")
15459 (set_attr "length" "4")])
15461 (define_insn "*restore_gpregs_<mode>_r1"
15462 [(match_parallel 0 "any_parallel_operand"
15463 [(clobber (match_operand:P 1 "register_operand" "=l"))
15464 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15465 (use (reg:P 1))
15466 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15467 (match_operand:P 4 "memory_operand" "m"))])]
15468 ""
15469 "bl %2"
15470 [(set_attr "type" "branch")
15471 (set_attr "length" "4")])
15473 (define_insn "*return_and_restore_gpregs_<mode>_r11"
15474 [(match_parallel 0 "any_parallel_operand"
15475 [(return)
15476 (clobber (match_operand:P 1 "register_operand" "=l"))
15477 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15478 (use (reg:P 11))
15479 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15480 (match_operand:P 4 "memory_operand" "m"))])]
15481 ""
15482 "b %2"
15483 [(set_attr "type" "branch")
15484 (set_attr "length" "4")])
15486 (define_insn "*return_and_restore_gpregs_<mode>_r12"
15487 [(match_parallel 0 "any_parallel_operand"
15488 [(return)
15489 (clobber (match_operand:P 1 "register_operand" "=l"))
15490 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15491 (use (reg:P 12))
15492 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15493 (match_operand:P 4 "memory_operand" "m"))])]
15494 ""
15495 "b %2"
15496 [(set_attr "type" "branch")
15497 (set_attr "length" "4")])
15499 (define_insn "*return_and_restore_gpregs_<mode>_r1"
15500 [(match_parallel 0 "any_parallel_operand"
15501 [(return)
15502 (clobber (match_operand:P 1 "register_operand" "=l"))
15503 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15504 (use (reg:P 1))
15505 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15506 (match_operand:P 4 "memory_operand" "m"))])]
15507 ""
15508 "b %2"
15509 [(set_attr "type" "branch")
15510 (set_attr "length" "4")])
15512 (define_insn "*return_and_restore_fpregs_<mode>_r11"
15513 [(match_parallel 0 "any_parallel_operand"
15514 [(return)
15515 (clobber (match_operand:P 1 "register_operand" "=l"))
15516 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15517 (use (reg:P 11))
15518 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15519 (match_operand:DF 4 "memory_operand" "m"))])]
15520 ""
15521 "b %2"
15522 [(set_attr "type" "branch")
15523 (set_attr "length" "4")])
15525 (define_insn "*return_and_restore_fpregs_<mode>_r12"
15526 [(match_parallel 0 "any_parallel_operand"
15527 [(return)
15528 (clobber (match_operand:P 1 "register_operand" "=l"))
15529 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15530 (use (reg:P 12))
15531 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15532 (match_operand:DF 4 "memory_operand" "m"))])]
15533 ""
15534 "b %2"
15535 [(set_attr "type" "branch")
15536 (set_attr "length" "4")])
15538 (define_insn "*return_and_restore_fpregs_<mode>_r1"
15539 [(match_parallel 0 "any_parallel_operand"
15540 [(return)
15541 (clobber (match_operand:P 1 "register_operand" "=l"))
15542 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15543 (use (reg:P 1))
15544 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15545 (match_operand:DF 4 "memory_operand" "m"))])]
15546 ""
15547 "b %2"
15548 [(set_attr "type" "branch")
15549 (set_attr "length" "4")])
15551 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
15552 [(match_parallel 0 "any_parallel_operand"
15553 [(return)
15554 (use (match_operand:P 1 "register_operand" "l"))
15555 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15556 (use (reg:P 11))
15557 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15558 (match_operand:DF 4 "memory_operand" "m"))])]
15559 ""
15560 "b %2"
15561 [(set_attr "type" "branch")
15562 (set_attr "length" "4")])
15564 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
15565 [(match_parallel 0 "any_parallel_operand"
15566 [(return)
15567 (use (match_operand:P 1 "register_operand" "l"))
15568 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15569 (use (reg:P 1))
15570 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15571 (match_operand:DF 4 "memory_operand" "m"))])]
15572 ""
15573 "b %2"
15574 [(set_attr "type" "branch")
15575 (set_attr "length" "4")])
15577 ; This is used in compiling the unwind routines.
15578 (define_expand "eh_return"
15579 [(use (match_operand 0 "general_operand" ""))]
15580 ""
15581 "
15582 {
15583 if (TARGET_32BIT)
15584 emit_insn (gen_eh_set_lr_si (operands[0]));
15585 else
15586 emit_insn (gen_eh_set_lr_di (operands[0]));
15587 DONE;
15588 }")
15590 ; We can't expand this before we know where the link register is stored.
15591 (define_insn "eh_set_lr_<mode>"
15592 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15593 UNSPECV_EH_RR)
15594 (clobber (match_scratch:P 1 "=&b"))]
15595 ""
15596 "#")
15598 (define_split
15599 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15600 (clobber (match_scratch 1 ""))]
15601 "reload_completed"
15602 [(const_int 0)]
15603 "
15604 {
15605 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15606 DONE;
15607 }")
15609 (define_insn "prefetch"
15610 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15611 (match_operand:SI 1 "const_int_operand" "n")
15612 (match_operand:SI 2 "const_int_operand" "n"))]
15613 ""
15614 "*
15615 {
15616 if (GET_CODE (operands[0]) == REG)
15617 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15618 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15619 }"
15620 [(set_attr "type" "load")])
15621 \f
15622 (define_insn "bpermd_<mode>"
15623 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15624 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15625 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15626 "TARGET_POPCNTD"
15627 "bpermd %0,%1,%2"
15628 [(set_attr "type" "popcnt")])
15630 \f
15631 ;; Builtin fma support. Handle
15632 ;; Note that the conditions for expansion are in the FMA_F iterator.
15634 (define_expand "fma<mode>4"
15635 [(set (match_operand:FMA_F 0 "register_operand" "")
15636 (fma:FMA_F
15637 (match_operand:FMA_F 1 "register_operand" "")
15638 (match_operand:FMA_F 2 "register_operand" "")
15639 (match_operand:FMA_F 3 "register_operand" "")))]
15640 ""
15641 "")
15643 ; Altivec only has fma and nfms.
15644 (define_expand "fms<mode>4"
15645 [(set (match_operand:FMA_F 0 "register_operand" "")
15646 (fma:FMA_F
15647 (match_operand:FMA_F 1 "register_operand" "")
15648 (match_operand:FMA_F 2 "register_operand" "")
15649 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
15650 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15651 "")
15653 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
15654 (define_expand "fnma<mode>4"
15655 [(set (match_operand:FMA_F 0 "register_operand" "")
15656 (neg:FMA_F
15657 (fma:FMA_F
15658 (match_operand:FMA_F 1 "register_operand" "")
15659 (match_operand:FMA_F 2 "register_operand" "")
15660 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15661 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
15662 "")
15664 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
15665 (define_expand "fnms<mode>4"
15666 [(set (match_operand:FMA_F 0 "register_operand" "")
15667 (neg:FMA_F
15668 (fma:FMA_F
15669 (match_operand:FMA_F 1 "register_operand" "")
15670 (match_operand:FMA_F 2 "register_operand" "")
15671 (match_operand:FMA_F 3 "register_operand" ""))))]
15672 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15673 "")
15675 ; Not an official optab name, but used from builtins.
15676 (define_expand "nfma<mode>4"
15677 [(set (match_operand:FMA_F 0 "register_operand" "")
15678 (neg:FMA_F
15679 (fma:FMA_F
15680 (match_operand:FMA_F 1 "register_operand" "")
15681 (match_operand:FMA_F 2 "register_operand" "")
15682 (match_operand:FMA_F 3 "register_operand" ""))))]
15683 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15684 "")
15686 ; Not an official optab name, but used from builtins.
15687 (define_expand "nfms<mode>4"
15688 [(set (match_operand:FMA_F 0 "register_operand" "")
15689 (neg:FMA_F
15690 (fma:FMA_F
15691 (match_operand:FMA_F 1 "register_operand" "")
15692 (match_operand:FMA_F 2 "register_operand" "")
15693 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15694 ""
15695 "")
15697 (define_expand "rs6000_get_timebase"
15698 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
15699 ""
15700 {
15701 if (TARGET_POWERPC64)
15702 emit_insn (gen_rs6000_mftb_di (operands[0]));
15703 else
15704 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
15705 DONE;
15706 })
15708 (define_insn "rs6000_get_timebase_ppc32"
15709 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
15710 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
15711 (clobber (match_scratch:SI 1 "=r"))
15712 (clobber (match_scratch:CC 2 "=y"))]
15713 "!TARGET_POWERPC64"
15714 {
15715 if (WORDS_BIG_ENDIAN)
15716 if (TARGET_MFCRF)
15717 {
15718 return "mfspr %0,269\;"
15719 "mfspr %L0,268\;"
15720 "mfspr %1,269\;"
15721 "cmpw %2,%0,%1\;"
15722 "bne- %2,$-16";
15723 }
15724 else
15725 {
15726 return "mftbu %0\;"
15727 "mftb %L0\;"
15728 "mftbu %1\;"
15729 "cmpw %2,%0,%1\;"
15730 "bne- %2,$-16";
15731 }
15732 else
15733 if (TARGET_MFCRF)
15734 {
15735 return "mfspr %L0,269\;"
15736 "mfspr %0,268\;"
15737 "mfspr %1,269\;"
15738 "cmpw %2,%L0,%1\;"
15739 "bne- %2,$-16";
15740 }
15741 else
15742 {
15743 return "mftbu %L0\;"
15744 "mftb %0\;"
15745 "mftbu %1\;"
15746 "cmpw %2,%L0,%1\;"
15747 "bne- %2,$-16";
15748 }
15749 }
15750 [(set_attr "length" "20")])
15752 (define_insn "rs6000_mftb_<mode>"
15753 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15754 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
15755 ""
15756 {
15757 if (TARGET_MFCRF)
15758 return "mfspr %0,268";
15759 else
15760 return "mftb %0";
15761 })
15763 \f
15764 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
15765 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
15766 ;; register that is being loaded. The fused ops must be physically adjacent.
15768 ;; We use define_peephole for the actual addis/load, and the register used to
15769 ;; hold the addis value must be the same as the register being loaded. We use
15770 ;; define_peephole2 to change the register used for addis to be the register
15771 ;; being loaded, since we can look at whether it is dead after the load insn.
15773 (define_peephole
15774 [(set (match_operand:P 0 "base_reg_operand" "")
15775 (match_operand:P 1 "fusion_gpr_addis" ""))
15776 (set (match_operand:INT1 2 "base_reg_operand" "")
15777 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15778 "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
15779 {
15780 return emit_fusion_gpr_load (operands);
15781 }
15782 [(set_attr "type" "load")
15783 (set_attr "length" "8")])
15785 (define_peephole2
15786 [(set (match_operand:P 0 "base_reg_operand" "")
15787 (match_operand:P 1 "fusion_gpr_addis" ""))
15788 (set (match_operand:INT1 2 "base_reg_operand" "")
15789 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15790 "TARGET_P8_FUSION
15791 && (REGNO (operands[0]) != REGNO (operands[2])
15792 || GET_CODE (operands[3]) == SIGN_EXTEND)
15793 && fusion_gpr_load_p (operands, true)"
15794 [(const_int 0)]
15795 {
15796 expand_fusion_gpr_load (operands);
15797 DONE;
15798 })
15800 \f
15802 (include "sync.md")
15803 (include "vector.md")
15804 (include "vsx.md")
15805 (include "altivec.md")
15806 (include "spe.md")
15807 (include "dfp.md")
15808 (include "paired.md")
15809 (include "crypto.md")
15810 (include "htm.md")