gcc/config/rs6000/rs6000-c.c

   1 /* Subroutines for the C front end on the PowerPC architecture.
   2    Copyright (C) 2002-2017 Free Software Foundation, Inc.
   3
   4    Contributed by Zack Weinberg <zack@codesourcery.com>
   5    and Paolo Bonzini <bonzini@gnu.org>
   6
   7    This file is part of GCC.
   8
   9    GCC is free software; you can redistribute it and/or modify it
  10    under the terms of the GNU General Public License as published
  11    by the Free Software Foundation; either version 3, or (at your
  12    option) any later version.
  13
  14    GCC is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GCC; see the file COPYING3.  If not see
  21    <http://www.gnu.org/licenses/>.  */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "coretypes.h"
  26 #include "target.h"
  27 #include "c-family/c-common.h"
  28 #include "memmodel.h"
  29 #include "tm_p.h"
  30 #include "stringpool.h"
  31 #include "stor-layout.h"
  32 #include "c-family/c-pragma.h"
  33 #include "langhooks.h"
  34 #include "c/c-tree.h"
  35
  36
  37
  38 /* Handle the machine specific pragma longcall.  Its syntax is
  39
  40    # pragma longcall ( TOGGLE )
  41
  42    where TOGGLE is either 0 or 1.
  43
  44    rs6000_default_long_calls is set to the value of TOGGLE, changing
  45    whether or not new function declarations receive a longcall
  46    attribute by default.  */
  47
  48 #define SYNTAX_ERROR(gmsgid) do {                                       \
  49   warning (OPT_Wpragmas, gmsgid);                                       \
  50   warning (OPT_Wpragmas, "ignoring malformed #pragma longcall");        \
  51   return;                                                               \
  52 } while (0)
  53
  54 void
  55 rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED)
  56 {
  57   tree x, n;
  58
  59   /* If we get here, generic code has already scanned the directive
  60      leader and the word "longcall".  */
  61
  62   if (pragma_lex (&x) != CPP_OPEN_PAREN)
  63     SYNTAX_ERROR ("missing open paren");
  64   if (pragma_lex (&n) != CPP_NUMBER)
  65     SYNTAX_ERROR ("missing number");
  66   if (pragma_lex (&x) != CPP_CLOSE_PAREN)
  67     SYNTAX_ERROR ("missing close paren");
  68
  69   if (n != integer_zero_node && n != integer_one_node)
  70     SYNTAX_ERROR ("number must be 0 or 1");
  71
  72   if (pragma_lex (&x) != CPP_EOF)
  73     warning (OPT_Wpragmas, "junk at end of #pragma longcall");
  74
  75   rs6000_default_long_calls = (n == integer_one_node);
  76 }
  77
  78 /* Handle defining many CPP flags based on TARGET_xxx.  As a general
  79    policy, rather than trying to guess what flags a user might want a
  80    #define for, it's better to define a flag for everything.  */
  81
  82 #define builtin_define(TXT) cpp_define (pfile, TXT)
  83 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
  84
  85 /* Keep the AltiVec keywords handy for fast comparisons.  */
  86 static GTY(()) tree __vector_keyword;
  87 static GTY(()) tree vector_keyword;
  88 static GTY(()) tree __pixel_keyword;
  89 static GTY(()) tree pixel_keyword;
  90 static GTY(()) tree __bool_keyword;
  91 static GTY(()) tree bool_keyword;
  92 static GTY(()) tree _Bool_keyword;
  93 static GTY(()) tree __int128_type;
  94 static GTY(()) tree __uint128_type;
  95
  96 /* Preserved across calls.  */
  97 static tree expand_bool_pixel;
  98
  99 static cpp_hashnode *
 100 altivec_categorize_keyword (const cpp_token *tok)
 101 {
 102   if (tok->type == CPP_NAME)
 103     {
 104       cpp_hashnode *ident = tok->val.node.node;
 105
 106       if (ident == C_CPP_HASHNODE (vector_keyword))
 107         return C_CPP_HASHNODE (__vector_keyword);
 108
 109       if (ident == C_CPP_HASHNODE (pixel_keyword))
 110         return C_CPP_HASHNODE (__pixel_keyword);
 111
 112       if (ident == C_CPP_HASHNODE (bool_keyword))
 113         return C_CPP_HASHNODE (__bool_keyword);
 114
 115       if (ident == C_CPP_HASHNODE (_Bool_keyword))
 116         return C_CPP_HASHNODE (__bool_keyword);
 117
 118       return ident;
 119     }
 120
 121   return 0;
 122 }
 123
 124 static void
 125 init_vector_keywords (void)
 126 {
 127   /* Keywords without two leading underscores are context-sensitive, and hence
 128      implemented as conditional macros, controlled by the
 129      rs6000_macro_to_expand() function below.  If we have ISA 2.07 64-bit
 130      support, record the __int128_t and __uint128_t types.  */
 131
 132   __vector_keyword = get_identifier ("__vector");
 133   C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
 134
 135   __pixel_keyword = get_identifier ("__pixel");
 136   C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL;
 137
 138   __bool_keyword = get_identifier ("__bool");
 139   C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL;
 140
 141   vector_keyword = get_identifier ("vector");
 142   C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL;
 143
 144   pixel_keyword = get_identifier ("pixel");
 145   C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL;
 146
 147   bool_keyword = get_identifier ("bool");
 148   C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL;
 149
 150   _Bool_keyword = get_identifier ("_Bool");
 151   C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
 152
 153   if (TARGET_VADDUQM)
 154     {
 155       __int128_type = get_identifier ("__int128_t");
 156       __uint128_type = get_identifier ("__uint128_t");
 157     }
 158 }
 159
 160 /* Helper function to find out which RID_INT_N_* code is the one for
 161    __int128, if any.  Returns RID_MAX+1 if none apply, which is safe
 162    (for our purposes, since we always expect to have __int128) to
 163    compare against.  */
 164 static int
 165 rid_int128(void)
 166 {
 167   int i;
 168
 169   for (i = 0; i < NUM_INT_N_ENTS; i ++)
 170     if (int_n_enabled_p[i]
 171         && int_n_data[i].bitsize == 128)
 172       return RID_INT_N_0 + i;
 173
 174   return RID_MAX + 1;
 175 }
 176
 177 /* Called to decide whether a conditional macro should be expanded.
 178    Since we have exactly one such macro (i.e, 'vector'), we do not
 179    need to examine the 'tok' parameter.  */
 180
 181 static cpp_hashnode *
 182 rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
 183 {
 184   cpp_hashnode *expand_this = tok->val.node.node;
 185   cpp_hashnode *ident;
 186
 187   /* If the current machine does not have altivec, don't look for the
 188      keywords.  */
 189   if (!TARGET_ALTIVEC)
 190     return NULL;
 191
 192   ident = altivec_categorize_keyword (tok);
 193
 194   if (ident != expand_this)
 195     expand_this = NULL;
 196
 197   if (ident == C_CPP_HASHNODE (__vector_keyword))
 198     {
 199       int idx = 0;
 200       do
 201         tok = cpp_peek_token (pfile, idx++);
 202       while (tok->type == CPP_PADDING);
 203       ident = altivec_categorize_keyword (tok);
 204
 205       if (ident == C_CPP_HASHNODE (__pixel_keyword))
 206         {
 207           expand_this = C_CPP_HASHNODE (__vector_keyword);
 208           expand_bool_pixel = __pixel_keyword;
 209         }
 210       else if (ident == C_CPP_HASHNODE (__bool_keyword))
 211         {
 212           expand_this = C_CPP_HASHNODE (__vector_keyword);
 213           expand_bool_pixel = __bool_keyword;
 214         }
 215       /* The boost libraries have code with Iterator::vector vector in it.  If
 216          we allow the normal handling, this module will be called recursively,
 217          and the vector will be skipped.; */
 218       else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword)))
 219         {
 220           enum rid rid_code = (enum rid)(ident->rid_code);
 221           enum node_type itype = ident->type;
 222           /* If there is a function-like macro, check if it is going to be
 223              invoked with or without arguments.  Without following ( treat
 224              it like non-macro, otherwise the following cpp_get_token eats
 225              what should be preserved.  */
 226           if (itype == NT_MACRO && cpp_fun_like_macro_p (ident))
 227             {
 228               int idx2 = idx;
 229               do
 230                 tok = cpp_peek_token (pfile, idx2++);
 231               while (tok->type == CPP_PADDING);
 232               if (tok->type != CPP_OPEN_PAREN)
 233                 itype = NT_VOID;
 234             }
 235           if (itype == NT_MACRO)
 236             {
 237               do
 238                 (void) cpp_get_token (pfile);
 239               while (--idx > 0);
 240               do
 241                 tok = cpp_peek_token (pfile, idx++);
 242               while (tok->type == CPP_PADDING);
 243               ident = altivec_categorize_keyword (tok);
 244               if (ident == C_CPP_HASHNODE (__pixel_keyword))
 245                 {
 246                   expand_this = C_CPP_HASHNODE (__vector_keyword);
 247                   expand_bool_pixel = __pixel_keyword;
 248                   rid_code = RID_MAX;
 249                 }
 250               else if (ident == C_CPP_HASHNODE (__bool_keyword))
 251                 {
 252                   expand_this = C_CPP_HASHNODE (__vector_keyword);
 253                   expand_bool_pixel = __bool_keyword;
 254                   rid_code = RID_MAX;
 255                 }
 256               else if (ident)
 257                 rid_code = (enum rid)(ident->rid_code);
 258             }
 259
 260           if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
 261               || rid_code == RID_SHORT || rid_code == RID_SIGNED
 262               || rid_code == RID_INT || rid_code == RID_CHAR
 263               || rid_code == RID_FLOAT
 264               || (rid_code == RID_DOUBLE && TARGET_VSX)
 265               || (rid_code == rid_int128 () && TARGET_VADDUQM))
 266             {
 267               expand_this = C_CPP_HASHNODE (__vector_keyword);
 268               /* If the next keyword is bool or pixel, it
 269                  will need to be expanded as well.  */
 270               do
 271                 tok = cpp_peek_token (pfile, idx++);
 272               while (tok->type == CPP_PADDING);
 273               ident = altivec_categorize_keyword (tok);
 274
 275               if (ident == C_CPP_HASHNODE (__pixel_keyword))
 276                 expand_bool_pixel = __pixel_keyword;
 277               else if (ident == C_CPP_HASHNODE (__bool_keyword))
 278                 expand_bool_pixel = __bool_keyword;
 279               else
 280                 {
 281                   /* Try two tokens down, too.  */
 282                   do
 283                     tok = cpp_peek_token (pfile, idx++);
 284                   while (tok->type == CPP_PADDING);
 285                   ident = altivec_categorize_keyword (tok);
 286                   if (ident == C_CPP_HASHNODE (__pixel_keyword))
 287                     expand_bool_pixel = __pixel_keyword;
 288                   else if (ident == C_CPP_HASHNODE (__bool_keyword))
 289                     expand_bool_pixel = __bool_keyword;
 290                 }
 291             }
 292
 293           /* Support vector __int128_t, but we don't need to worry about bool
 294              or pixel on this type.  */
 295           else if (TARGET_VADDUQM
 296                    && (ident == C_CPP_HASHNODE (__int128_type)
 297                        || ident == C_CPP_HASHNODE (__uint128_type)))
 298             expand_this = C_CPP_HASHNODE (__vector_keyword);
 299         }
 300     }
 301   else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))
 302     {
 303       expand_this = C_CPP_HASHNODE (__pixel_keyword);
 304       expand_bool_pixel = 0;
 305     }
 306   else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword))
 307     {
 308       expand_this = C_CPP_HASHNODE (__bool_keyword);
 309       expand_bool_pixel = 0;
 310     }
 311
 312   return expand_this;
 313 }
 314
 315
 316 /* Define or undefine a single macro.  */
 317
 318 static void
 319 rs6000_define_or_undefine_macro (bool define_p, const char *name)
 320 {
 321   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 322     fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name);
 323
 324   if (define_p)
 325     cpp_define (parse_in, name);
 326   else
 327     cpp_undef (parse_in, name);
 328 }
 329
 330 /* Define or undefine macros based on the current target.  If the user does
 331    #pragma GCC target, we need to adjust the macros dynamically.  Note, some of
 332    the options needed for builtins have been moved to separate variables, so
 333    have both the target flags and the builtin flags as arguments.  */
 334
 335 void
 336 rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
 337                              HOST_WIDE_INT bu_mask)
 338 {
 339   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 340     fprintf (stderr,
 341              "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX
 342              ", " HOST_WIDE_INT_PRINT_HEX ")\n",
 343              (define_p) ? "define" : "undef",
 344              flags, bu_mask);
 345
 346   /* Each of the flags mentioned below controls whether certain
 347      preprocessor macros will be automatically defined when
 348      preprocessing source files for compilation by this compiler.
 349      While most of these flags can be enabled or disabled
 350      explicitly by specifying certain command-line options when
 351      invoking the compiler, there are also many ways in which these
 352      flags are enabled or disabled implicitly, based on compiler
 353      defaults, configuration choices, and on the presence of certain
 354      related command-line options.  Many, but not all, of these
 355      implicit behaviors can be found in file "rs6000.c", the
 356      rs6000_option_override_internal() function.
 357
 358      In general, each of the flags may be automatically enabled in
 359      any of the following conditions:
 360
 361      1. If no -mcpu target is specified on the command line and no
 362         --with-cpu target is specified to the configure command line
 363         and the TARGET_DEFAULT macro for this default cpu host
 364         includes the flag, and the flag has not been explicitly disabled
 365         by command-line options.
 366
 367      2. If the target specified with -mcpu=target on the command line, or
 368         in the absence of a -mcpu=target command-line option, if the
 369         target specified using --with-cpu=target on the configure
 370         command line, is disqualified because the associated binary
 371         tools (e.g. the assembler) lack support for the requested cpu,
 372         and the TARGET_DEFAULT macro for this default cpu host
 373         includes the flag, and the flag has not been explicitly disabled
 374         by command-line options.
 375
 376      3. If either of the above two conditions apply except that the
 377         TARGET_DEFAULT macro is defined to equal zero, and
 378         TARGET_POWERPC64 and
 379         a) BYTES_BIG_ENDIAN and the flag to be enabled is either
 380            MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64"
 381            target), or
 382         b) !BYTES_BIG_ENDIAN and the flag to be enabled is either
 383            MASK_POWERPC64 or it is one of the flags included in
 384            ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target).
 385
 386      4. If a cpu has been requested with a -mcpu=target command-line option
 387         and this cpu has not been disqualified due to shortcomings of the
 388         binary tools, and the set of flags associated with the requested cpu
 389         include the flag to be enabled.  See rs6000-cpus.def for macro
 390         definitions that represent various ABI standards
 391         (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of
 392         the specific flags that are associated with each of the cpu
 393         choices that can be specified as the target of a -mcpu=target
 394         compile option, or as the the target of a --with-cpu=target
 395         configure option.  Target flags that are specified in either
 396         of these two ways are considered "implicit" since the flags
 397         are not mentioned specifically by name.
 398
 399         Additional documentation describing behavior specific to
 400         particular flags is provided below, immediately preceding the
 401         use of each relevant flag.
 402
 403      5. If there is no -mcpu=target command-line option, and the cpu
 404         requested by a --with-cpu=target command-line option has not
 405         been disqualified due to shortcomings of the binary tools, and
 406         the set of flags associated with the specified target include
 407         the flag to be enabled.  See the notes immediately above for a
 408         summary of the flags associated with particular cpu
 409         definitions.  */
 410
 411   /* rs6000_isa_flags based options.  */
 412   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
 413   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 414     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
 415   if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
 416     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
 417   if ((flags & OPTION_MASK_POWERPC64) != 0)
 418     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
 419   if ((flags & OPTION_MASK_MFCRF) != 0)
 420     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
 421   if ((flags & OPTION_MASK_POPCNTB) != 0)
 422     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
 423   if ((flags & OPTION_MASK_FPRND) != 0)
 424     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
 425   if ((flags & OPTION_MASK_CMPB) != 0)
 426     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
 427   if ((flags & OPTION_MASK_MFPGPR) != 0)
 428     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
 429   if ((flags & OPTION_MASK_POPCNTD) != 0)
 430     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
 431   /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
 432      turned on in the following condition:
 433      1. TARGET_P9_DFORM_SCALAR or TARGET_P9_DFORM_VECTOR are enabled
 434         and OPTION_MASK_DIRECT_MOVE is not explicitly disabled.
 435         Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
 436         have been turned on explicitly.
 437      Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
 438      turned off in any of the following conditions:
 439      1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
 440         disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
 441         enabled.
 442      2. TARGET_VSX is off.  */
 443   if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
 444     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
 445   if ((flags & OPTION_MASK_MODULO) != 0)
 446     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
 447   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
 448     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
 449   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
 450     rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
 451   /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on
 452      in any of the following conditions:
 453      1. The command line specifies either -maltivec=le or -maltivec=be.
 454      2. The operating system is Darwin and it is configured for 64
 455         bit.  (See darwin_rs6000_override_options.)
 456      3. The operating system is Darwin and the operating system
 457         version is 10.5 or higher and the user has not explicitly
 458         disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and
 459         the compiler is not producing code for integration within the
 460         kernel.  (See darwin_rs6000_override_options.)
 461      Note that the OPTION_MASK_ALTIVEC flag is automatically turned
 462      off in any of the following conditions:
 463      1. The operating system does not support saving of AltiVec
 464         registers (OS_MISSING_ALTIVEC).
 465      2. If an inner context (as introduced by
 466         __attribute__((__target__())) or #pragma GCC target()
 467         requests a target that normally enables the
 468         OPTION_MASK_ALTIVEC flag but the outer-most "main target"
 469         does not support the rs6000_altivec_abi, this flag is
 470         turned off for the inner context unless OPTION_MASK_ALTIVEC
 471         was explicitly enabled for the inner context.  */
 472   if ((flags & OPTION_MASK_ALTIVEC) != 0)
 473     {
 474       const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
 475       rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
 476       rs6000_define_or_undefine_macro (define_p, vec_str);
 477
 478           /* Define this when supporting context-sensitive keywords.  */
 479       if (!flag_iso)
 480         rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
 481     }
 482   /* Note that the OPTION_MASK_VSX flag is automatically turned on in
 483      the following conditions:
 484      1. TARGET_P8_VECTOR is explicitly turned on and the OPTION_MASK_VSX
 485         was not explicitly turned off.  Hereafter, the OPTION_MASK_VSX
 486         flag is considered to have been explicitly turned on.
 487      Note that the OPTION_MASK_VSX flag is automatically turned off in
 488      the following conditions:
 489      1. The operating system does not support saving of AltiVec
 490         registers (OS_MISSING_ALTIVEC).
 491      2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT,
 492         or TARGET_DOUBLE_FLOAT are turned off.  Hereafter, the
 493         OPTION_MASK_VSX flag is considered to have been turned off
 494         explicitly.
 495      3. If TARGET_PAIRED_FLOAT was enabled.  Hereafter, the
 496         OPTION_MASK_VSX flag is considered to have been turned off
 497         explicitly.
 498      4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
 499         compilation context, or if it is turned on by any means in an
 500         inner compilation context.  Hereafter, the OPTION_MASK_VSX
 501         flag is considered to have been turned off explicitly.
 502      5. If TARGET_ALTIVEC was explicitly disabled.  Hereafter, the
 503         OPTION_MASK_VSX flag is considered to have been turned off
 504         explicitly.
 505      6. If an inner context (as introduced by
 506         __attribute__((__target__())) or #pragma GCC target()
 507         requests a target that normally enables the
 508         OPTION_MASK_VSX flag but the outer-most "main target"
 509         does not support the rs6000_altivec_abi, this flag is
 510         turned off for the inner context unless OPTION_MASK_VSX
 511         was explicitly enabled for the inner context.  */
 512   if ((flags & OPTION_MASK_VSX) != 0)
 513     rs6000_define_or_undefine_macro (define_p, "__VSX__");
 514   if ((flags & OPTION_MASK_HTM) != 0)
 515     {
 516       rs6000_define_or_undefine_macro (define_p, "__HTM__");
 517       /* Tell the user that our HTM insn patterns act as memory barriers.  */
 518       rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
 519     }
 520   /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
 521      on in the following conditions:
 522      1. TARGET_P9_VECTOR is explicitly turned on and
 523         OPTION_MASK_P8_VECTOR is not explicitly turned off.
 524         Hereafter, the OPTION_MASK_P8_VECTOR flag is considered to
 525         have been turned off explicitly.
 526      Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
 527      off in the following conditions:
 528      1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX
 529         were turned off explicitly and OPTION_MASK_P8_VECTOR flag was
 530         not turned on explicitly.
 531      2. If TARGET_ALTIVEC is turned off.  Hereafter, the
 532         OPTION_MASK_P8_VECTOR flag is considered to have been turned off
 533         explicitly.
 534      3. If TARGET_VSX is turned off and OPTION_MASK_P8_VECTOR was not
 535         explicitly enabled.  If TARGET_VSX is explicitly enabled, the
 536         OPTION_MASK_P8_VECTOR flag is hereafter also considered to
 537         have been turned off explicitly.  */
 538   if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 539     rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
 540   /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned
 541      off in the following conditions:
 542      1. If TARGET_P8_VECTOR is turned off and OPTION_MASK_P9_VECTOR is
 543         not turned on explicitly. Hereafter, if OPTION_MASK_P8_VECTOR
 544         was turned on explicitly, the OPTION_MASK_P9_VECTOR flag is
 545         also considered to have been turned off explicitly.
 546      Note that the OPTION_MASK_P9_VECTOR is automatically turned on
 547      in the following conditions:
 548      1. If TARGET_P9_DFORM_SCALAR or TARGET_P9_DFORM_VECTOR and
 549         OPTION_MASK_P9_VECTOR was not turned off explicitly.
 550         Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to
 551         have been turned on explicitly.  */
 552   if ((flags & OPTION_MASK_P9_VECTOR) != 0)
 553     rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__");
 554   /* Note that the OPTION_MASK_QUAD_MEMORY flag is automatically
 555      turned off in the following conditions:
 556      1. If TARGET_POWERPC64 is turned off.
 557      2. If WORDS_BIG_ENDIAN is false (non-atomic quad memory
 558         load/store are disabled on little endian).  */
 559   if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
 560     rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
 561   /* Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is automatically
 562      turned off in the following conditions:
 563      1. If TARGET_POWERPC64 is turned off.
 564      Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is
 565      automatically turned on in the following conditions:
 566      1. If TARGET_QUAD_MEMORY and this flag was not explicitly
 567         disabled.  */
 568   if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
 569     rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
 570   /* Note that the OPTION_MASK_CRYPTO flag is automatically turned off
 571      in the following conditions:
 572      1. If any of TARGET_HARD_FLOAT or TARGET_ALTIVEC or TARGET_VSX
 573         are turned off explicitly and OPTION_MASK_CRYPTO is not turned
 574         on explicitly.
 575      2. If TARGET_ALTIVEC is turned off.  */
 576   if ((flags & OPTION_MASK_CRYPTO) != 0)
 577     rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
 578
 579   /* options from the builtin masks.  */
 580   /* Note that RS6000_BTM_PAIRED is enabled only if
 581      TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired).  */
 582   if ((bu_mask & RS6000_BTM_PAIRED) != 0)
 583     rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
 584   /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
 585      PROCESSOR_CELL) (e.g. -mcpu=cell).  */
 586   if ((bu_mask & RS6000_BTM_CELL) != 0)
 587     rs6000_define_or_undefine_macro (define_p, "__PPU__");
 588 }
 589
 590 void
 591 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 592 {
 593   /* Define all of the common macros.  */
 594   rs6000_target_modify_macros (true, rs6000_isa_flags,
 595                                rs6000_builtin_mask_calculate ());
 596
 597   if (TARGET_FRE)
 598     builtin_define ("__RECIP__");
 599   if (TARGET_FRES)
 600     builtin_define ("__RECIPF__");
 601   if (TARGET_FRSQRTE)
 602     builtin_define ("__RSQRTE__");
 603   if (TARGET_FRSQRTES)
 604     builtin_define ("__RSQRTEF__");
 605   if (TARGET_FLOAT128_KEYWORD)
 606     builtin_define ("__FLOAT128__");
 607   if (TARGET_FLOAT128_TYPE)
 608     builtin_define ("__FLOAT128_TYPE__");
 609   if (TARGET_FLOAT128_HW)
 610     builtin_define ("__FLOAT128_HARDWARE__");
 611   if (TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (TFmode))
 612     builtin_define ("__ibm128=long double");
 613 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
 614   builtin_define ("__BUILTIN_CPU_SUPPORTS__");
 615 #endif
 616
 617   /* We needed to create a keyword if -mfloat128-type was used but not -mfloat,
 618      so we used __ieee128.  If -mfloat128 was used, create a #define back to
 619      the real keyword in case somebody used it.  */
 620   if (TARGET_FLOAT128_KEYWORD)
 621     builtin_define ("__ieee128=__float128");
 622
 623   if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
 624     {
 625       /* Define the AltiVec syntactic elements.  */
 626       builtin_define ("__vector=__attribute__((altivec(vector__)))");
 627       builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short");
 628       builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned");
 629
 630       if (!flag_iso)
 631         {
 632           builtin_define ("vector=vector");
 633           builtin_define ("pixel=pixel");
 634           builtin_define ("bool=bool");
 635           builtin_define ("_Bool=_Bool");
 636           init_vector_keywords ();
 637
 638           /* Enable context-sensitive macros.  */
 639           cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
 640         }
 641     }
 642   if (!TARGET_HARD_FLOAT
 643       || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
 644     builtin_define ("_SOFT_DOUBLE");
 645   /* Used by lwarx/stwcx. errata work-around.  */
 646   if (rs6000_cpu == PROCESSOR_PPC405)
 647     builtin_define ("__PPC405__");
 648   /* Used by libstdc++.  */
 649   if (TARGET_NO_LWSYNC)
 650     builtin_define ("__NO_LWSYNC__");
 651
 652   if (TARGET_EXTRA_BUILTINS)
 653     {
 654       /* For the VSX builtin functions identical to Altivec functions, just map
 655          the altivec builtin into the vsx version (the altivec functions
 656          generate VSX code if -mvsx).  */
 657       builtin_define ("__builtin_vsx_xxland=__builtin_vec_and");
 658       builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc");
 659       builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor");
 660       builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or");
 661       builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor");
 662       builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel");
 663       builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm");
 664
 665       /* Also map the a and m versions of the multiply/add instructions to the
 666          builtin for people blindly going off the instruction manual.  */
 667       builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp");
 668       builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp");
 669       builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp");
 670       builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp");
 671       builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp");
 672       builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp");
 673       builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp");
 674       builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp");
 675       builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp");
 676       builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp");
 677       builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp");
 678       builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp");
 679       builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp");
 680       builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp");
 681       builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
 682       builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
 683     }
 684
 685   /* Tell users they can use __builtin_bswap{16,64}.  */
 686   builtin_define ("__HAVE_BSWAP__");
 687
 688   /* May be overridden by target configuration.  */
 689   RS6000_CPU_CPP_ENDIAN_BUILTINS();
 690
 691   if (TARGET_LONG_DOUBLE_128)
 692     {
 693       builtin_define ("__LONG_DOUBLE_128__");
 694       builtin_define ("__LONGDOUBLE128");
 695
 696       if (TARGET_IEEEQUAD)
 697         builtin_define ("__LONG_DOUBLE_IEEE128__");
 698       else
 699         builtin_define ("__LONG_DOUBLE_IBM128__");
 700     }
 701
 702   switch (TARGET_CMODEL)
 703     {
 704       /* Deliberately omit __CMODEL_SMALL__ since that was the default
 705          before --mcmodel support was added.  */
 706     case CMODEL_MEDIUM:
 707       builtin_define ("__CMODEL_MEDIUM__");
 708       break;
 709     case CMODEL_LARGE:
 710       builtin_define ("__CMODEL_LARGE__");
 711       break;
 712     default:
 713       break;
 714     }
 715
 716   switch (rs6000_current_abi)
 717     {
 718     case ABI_V4:
 719       builtin_define ("_CALL_SYSV");
 720       break;
 721     case ABI_AIX:
 722       builtin_define ("_CALL_AIXDESC");
 723       builtin_define ("_CALL_AIX");
 724       builtin_define ("_CALL_ELF=1");
 725       break;
 726     case ABI_ELFv2:
 727       builtin_define ("_CALL_ELF=2");
 728       break;
 729     case ABI_DARWIN:
 730       builtin_define ("_CALL_DARWIN");
 731       break;
 732     default:
 733       break;
 734     }
 735
 736   /* Vector element order.  */
 737   if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
 738     builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__");
 739   else
 740     builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
 741
 742   /* Let the compiled code know if 'f' class registers will not be available.  */
 743   if (TARGET_SOFT_FLOAT)
 744     builtin_define ("__NO_FPRS__");
 745
 746   /* Whether aggregates passed by value are aligned to a 16 byte boundary
 747      if their alignment is 16 bytes or larger.  */
 748   if ((TARGET_MACHO && rs6000_darwin64_abi)
 749       || DEFAULT_ABI == ABI_ELFv2
 750       || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
 751     builtin_define ("__STRUCT_PARM_ALIGN__=16");
 752
 753   /* Generate defines for Xilinx FPU. */
 754   if (rs6000_xilinx_fpu)
 755     {
 756       builtin_define ("_XFPU");
 757       if (rs6000_single_float && ! rs6000_double_float)
 758         {
 759           if (rs6000_simple_fpu)
 760             builtin_define ("_XFPU_SP_LITE");
 761           else
 762             builtin_define ("_XFPU_SP_FULL");
 763         }
 764       if (rs6000_double_float)
 765         {
 766           if (rs6000_simple_fpu)
 767             builtin_define ("_XFPU_DP_LITE");
 768           else
 769             builtin_define ("_XFPU_DP_FULL");
 770         }
 771     }
 772 }
 773
 774 \f
 775 struct altivec_builtin_types
 776 {
 777   enum rs6000_builtins code;
 778   enum rs6000_builtins overloaded_code;
 779   signed char ret_type;
 780   signed char op1;
 781   signed char op2;
 782   signed char op3;
 783 };
 784
 785 const struct altivec_builtin_types altivec_overloaded_builtins[] = {
 786   /* Unary AltiVec/VSX builtins.  */
 787   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
 788     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
 789   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
 790     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
 791   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
 792     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
 793   { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
 794     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
 795   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
 796     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 797   { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
 798     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 799   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
 800     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
 801   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
 802     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
 803   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
 804     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
 805   { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
 806     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 807   { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
 808     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 809   { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
 810     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 811   { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
 812     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 813   { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
 814     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 815   { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
 816     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 817   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 818     RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
 819   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 820     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
 821   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 822     RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
 823   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 824     RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
 825   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 826     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
 827   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 828     RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
 829   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 830     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
 831   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 832     RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
 833   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 834     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
 835   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 836     RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
 837   { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
 838     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 839   { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
 840     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 841   { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
 842     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 843   { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
 844     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 845   { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
 846     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 847   { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
 848     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 849   { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
 850     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 851   { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
 852     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 853   { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
 854     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 855   { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
 856     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 857   { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
 858     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 859   { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
 860     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 861   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
 862     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 863   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
 864     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 865   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
 866     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 867   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
 868     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 869   { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
 870     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 871   { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
 872     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 873   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
 874     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 875   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
 876     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 877   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
 878     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 879   { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
 880     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 881   { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
 882     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 883   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
 884     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
 885   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
 886     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 887   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
 888     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 889   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
 890     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 891   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
 892     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 893   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
 894     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 895   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
 896     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 897   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
 898     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 899   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
 900     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 901   { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
 902     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 903   { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
 904     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 905   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
 906     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
 907   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
 908     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 909   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
 910     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 911   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
 912     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 913   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
 914     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 915   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
 916     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 917
 918   /* Binary AltiVec/VSX builtins.  */
 919   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 920     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
 921   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 922     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
 923   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 924     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
 925   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 926     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
 927   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 928     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
 929   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 930     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
 931   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 932     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
 933   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 934     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
 935   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 936     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
 937   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 938     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 939   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 940     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
 941   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 942     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 943   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 944     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
 945   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 946     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
 947   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 948     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
 949   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 950     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 951   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 952     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
 953   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 954     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 955   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 956     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
 957   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 958     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
 959   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 960     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
 961   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 962     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
 963   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 964     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
 965   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 966     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
 967   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
 968     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 969   { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
 970     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 971   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
 972     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
 973   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
 974     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
 975     RS6000_BTI_unsigned_V1TI, 0 },
 976   { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
 977     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 978   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 979     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
 980   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 981     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 982   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 983     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
 984   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 985     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 986   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 987     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
 988   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 989     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
 990   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 991     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 992   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 993     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
 994   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
 995     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
 996   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
 997     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 998   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
 999     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1000   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1001     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1002   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1003     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1004   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1005     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1006   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1007     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1008   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1009     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1010   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1011     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1012   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1013     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1014   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1015     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1016   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1017     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1018   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1019     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1020   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1021     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1022   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1023     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1024   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1025     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1026   { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1027     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1028   { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1029     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1030     RS6000_BTI_unsigned_V4SI, 0 },
1031   { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1032     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1033     RS6000_BTI_unsigned_V1TI, 0 },
1034   { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1035     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1036   { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1037     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1038     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
1039   { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1040     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
1041   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1042     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1043   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1044     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1045   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1046     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1047   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1048     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1049   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1050     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1051   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1052     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1053   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1054     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1055   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1056     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1057   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1058     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1059   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1060     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1061   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1062     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1063   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1064     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1065   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1066     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1067   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1068     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1069   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1070     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1071   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1072     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1073   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1074     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1075   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1076     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1077   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1078     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1079   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1080     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1081   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1082     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1083   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1084     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1085   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1086     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1087   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1088     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1089   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1090     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1091   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1092     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1093   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1094     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1095   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1096     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1097   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1098     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1099   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1100     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1101   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1102     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1103   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1104     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1105   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1106     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1107   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1108     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1109   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1110     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1111   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1112     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1113   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1114     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1115   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1116     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1117   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1118     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1119   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1120     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1121   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1122     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1123   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1124     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1125   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1126     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1127   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1128     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1129   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1130     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1131   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1132     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1133   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1134     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1135   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1136     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1137   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1138     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1139   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1140     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1141   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1142     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1143   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1144     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1145   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1146     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1147   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1148     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1149   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1150     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1151   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1152     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1153   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1154     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1155   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1156     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1157   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1158     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1159   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1160     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1161   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1162     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1163   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1164     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1165   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1166     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1167   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1168     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1169   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1170     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1171   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1172     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1173   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1174     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1175   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1176     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1177   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1178     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1179   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1180     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1181   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1182     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1183   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1184     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1185   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1186     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1187   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1188     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1189   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1190     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1191   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1192     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1193   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1194     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1195   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1196     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1197   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1198     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1199   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1200     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1201   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1202     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1203   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1204     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1205   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1206     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1207   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1208     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1209   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1210     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1211   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1212     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1213   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1214     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1215   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1216     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1217   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1218     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1219   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1220     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1221   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1222     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1223   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1224     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1225   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1226     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1227   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1228     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1229   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1230     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1231   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1232     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1233   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1234     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1235   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1236     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1237   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1238     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1239   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1240     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1241   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1242     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1243   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1244     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1245   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1246     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1247   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1248     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1249   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1250     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1251   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1252     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1253   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1254     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1255   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1256     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1257   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1258     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1259   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
1260     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1261   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
1262     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1263   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
1264     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1265   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
1266     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1267   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
1268     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1269   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
1270     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1271   { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
1272     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1273   { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
1274     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1275   { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
1276     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1277   { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
1278     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1279   { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
1280     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1281   { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
1282     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1283   { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
1284     RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1285   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1286     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1287   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1288     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1289   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1290     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1291   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1292     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1293   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1294     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1295   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1296     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1297   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1298     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1299   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1300     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1301   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1302     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1303   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1304     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1305   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1306     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1307   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1308     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1309   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
1310     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1311   { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
1312     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1313   { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
1314     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1315
1316   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1317     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1318   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1319     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1320
1321   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1322     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1323   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1324     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1325
1326   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1327     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1328   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1329     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1330
1331   { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
1332     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1333   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
1334     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1335   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
1336     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1337   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
1338     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1339     RS6000_BTI_unsigned_V16QI, 0},
1340   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
1341     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1342   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
1343     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1344     RS6000_BTI_unsigned_V8HI, 0},
1345   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
1346     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1347   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
1348     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1349     RS6000_BTI_unsigned_V4SI, 0},
1350   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
1351     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1352   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
1353     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1354     RS6000_BTI_unsigned_V2DI, 0},
1355   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
1356     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1357   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
1358     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1359   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
1360     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1361   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
1362     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1363   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
1364     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1365   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
1366     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1367   { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
1368     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1369   { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
1370     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1371   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
1372     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1373   { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
1374     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1375   { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
1376     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1377   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1378     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1379   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1380     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1381   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1382     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1383   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1384     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1385   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1386     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1387   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1388     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1389   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1390     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1391   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1392     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1393   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1394     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1395   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1396     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1397   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1398     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1399   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1400     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1401   { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
1402     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1403   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
1404     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1405   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
1406     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1407   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
1408     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1409     RS6000_BTI_unsigned_V16QI, 0},
1410   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
1411     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1412   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
1413     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1414     RS6000_BTI_unsigned_V8HI, 0},
1415   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
1416     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1417   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
1418     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1419     RS6000_BTI_unsigned_V4SI, 0},
1420   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
1421     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1422   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
1423     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1424     RS6000_BTI_unsigned_V2DI, 0},
1425   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
1426     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1427   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
1428     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1429   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
1430     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1431   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
1432     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1433   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
1434     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1435   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
1436     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1437   { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
1438     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1439   { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
1440     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1441   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
1442     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1443   { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
1444     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1445   { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
1446     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1447   { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
1448     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1449   { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
1450     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1451   { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
1452     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1453   { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
1454     RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
1455   { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
1456     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
1457   { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
1458     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1459   { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
1460     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1461   { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
1462     RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1463   { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
1464     RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1465   { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
1466     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1467   { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
1468     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1469   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
1470     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1471   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
1472     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1473   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
1474     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1475   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
1476     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1477   { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
1478     RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
1479   { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1480     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1481
1482   { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
1483     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1484   { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
1485     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1486   { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
1487     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1488
1489   { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
1490     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1491   { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
1492     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1493   { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
1494     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1495
1496   { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI,
1497     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1498   { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI,
1499     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1500   { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF,
1501     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1502
1503   { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI,
1504     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1505   { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI,
1506     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1507   { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF,
1508     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1509
1510   { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1511     RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1512   { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1513     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1514   { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_FLOAT2_V2DI,
1515     RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1516   { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_UNS_FLOAT2_V2DI,
1517     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1518     RS6000_BTI_unsigned_V2DI, 0 },
1519   { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1520     RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1521   { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1522     RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1523   { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI,
1524     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1525   { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF,
1526     RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1527   { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1528     RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1529   { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1530     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1531
1532   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1533     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1534   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1535     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1536   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1537     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1538     ~RS6000_BTI_unsigned_V2DI, 0 },
1539   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1540     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1541   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1542     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1543   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1544     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1545   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1546     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1547   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1548     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1549   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1550     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1551   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1552     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1553   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1554     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1555   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1556     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1557   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1558     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1559   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1560     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1561   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1562     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1563   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1564     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1565   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1566     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1567   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1568     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1569   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1570     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1571   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1572     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1573   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1574     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1575   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1576     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1577   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1578     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1579   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1580     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1581   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1582     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1583   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1584     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1585   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1586     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1587   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1588     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1589   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1590     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1591   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1592     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1593   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1594     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1595   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1596     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1597   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1598     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1599   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1600     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1601   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1602     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1603   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1604     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1605   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1606     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1607   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1608     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1609   { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1610     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1611   { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1612     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1613   { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1614     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1615   { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1616     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1617   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1618     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1619   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1620     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1621   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1622     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1623   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1624     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1625   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1626     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1627   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1628     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1629   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1630     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1631   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1632     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1633   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1634     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1635   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1636     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1637   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1638     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1639   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1640     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1641   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1642     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1643   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1644     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1645   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1646     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1647   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1648     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1649   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1650     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1651   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1652     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1653   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1654     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1655     ~RS6000_BTI_unsigned_V16QI, 0 },
1656   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1657     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1658   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1659     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1660   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1661     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1662   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1663     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1664     ~RS6000_BTI_unsigned_V2DI, 0 },
1665   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1666     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1667   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1668     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1669   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1670     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1671   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1672     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1673   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1674     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1675   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1676     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1677   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1678     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1679   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1680     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1681   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1682     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1683   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1684     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1685   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1686     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1687   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1688     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1689   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1690     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1691   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1692     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1693   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1694     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1695     ~RS6000_BTI_unsigned_long_long, 0 },
1696   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1697     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1698   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1699     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1700   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1701     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1702   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1703     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1704   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1705     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1706   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1707     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1708   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1709     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1710   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1711     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1712   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1713     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1714   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1715     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1716   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1717     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1718   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1719     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1720   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1721     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1722   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1723     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1724     ~RS6000_BTI_unsigned_long_long, 0 },
1725   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1726     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1727   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1728     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1729   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1730     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1731   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1732     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1733   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1734     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1735   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1736     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1737   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1738     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1739   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1740     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1741   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1742     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1743   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1744     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1745   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1746     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1747   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1748     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1749   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1750     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1751   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1752     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1753   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1754     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1755   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1756     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1757   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1758     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1759   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1760     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1761   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1762     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1763   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1764     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1765   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1766     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1767   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1768     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1769   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1770     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1771   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1772     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1773   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1774     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1775   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1776     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1777   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1778     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1779   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1780     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1781   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1782     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1783   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1784     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1785   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1786     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1787   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1788     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1789   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1790     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1791   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1792     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1793   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1794     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1795   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1796     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1797   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1798     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1799   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1800     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1801   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1802     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1803   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1804     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1805   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1806     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1807   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1808     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1809   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1810     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1811   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1812     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1813   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1814     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1815   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1816     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1817   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1818     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1819   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1820     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1821   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1822     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1823   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1824     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1825   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1826     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1827   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1828     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1829   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1830     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1831   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1832     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1833   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1834     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1835   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1836     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1837   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1838     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1839   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1840     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1841   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1842     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1843   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1844     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1845   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1846     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1847   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1848     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1849   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1850     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1851   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1852     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1853   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1854     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1855   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1856     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1857   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1858     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1859   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1860     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1861   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1862     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1863   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1864     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1865   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1866     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1867   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1868     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1869   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1870     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1871   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1872     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1873   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1874     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1875   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1876     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1877   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1878     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1879   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1880     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1881   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1882     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1883   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1884     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1885   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1886     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1887   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1888     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1889   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1890     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1891   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1892     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1893   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1894     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1895   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1896     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1897   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1898     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1899   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1900     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1901   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1902     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1903   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1904     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1905   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1906     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1907   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1908     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1909   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1910     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1911   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1912     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1913   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1914     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1915   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1916     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1917   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
1918     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1919   { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
1920     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1921   { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
1922     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1923   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1924     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1925   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1926     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1927   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1928     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1929   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1930     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1931   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1932     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1933   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1934     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1935   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1936     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1937   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1938     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1939   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1940     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1941   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1942     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1943   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1944     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1945   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1946     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1947   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1948     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1949   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1950     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1951   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1952     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1953   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1954     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1955   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1956     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1957   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1958     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1959   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1960     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1961   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1962     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1963   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1964     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1965   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1966     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1967   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1968     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1969   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1970     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1971   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1972     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1973   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1974     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1975   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1976     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1977   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1978     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1979   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1980     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1981   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1982     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1983   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1984     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1985   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1986     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1987   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1988     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1989   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1990     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1991   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1992     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1993   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
1994     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1995   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1996     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1997   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1998     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1999   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2000     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2001   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2002     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2003   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2004     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2005   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2006     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2007   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2008     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2009   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2010     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2011   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2012     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2013   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2014     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2015   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2016     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2017   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2018     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2019   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2020     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2021   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2022     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2023   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2024     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2025   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2026     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2027   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2028     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2029   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2030     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2031   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2032     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2033   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2034     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2035   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2036     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2037   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2038     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2039   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2040     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2041   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2042     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2043   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2044     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2045   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2046     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2047   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2048     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2049   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2050     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2051   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2052     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2053   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
2054     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2055   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2056     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2057   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2058     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2059   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2060     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2061   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2062     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2063   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2064     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2065   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2066     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2067   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2068     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2069   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2070     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2071   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2072     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2073   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2074     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2075   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2076     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2077   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2078     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2079   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2080     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2081   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2082     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2083   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2084     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2085   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2086     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2087   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2088     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2089   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2090     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2091   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2092     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2093   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2094     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2095   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2096     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2097   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2098     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2099   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2100     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2101   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2102     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2103   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2104     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2105   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2106     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2107   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2108     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2109   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2110     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2111   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2112     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2113   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2114     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2115   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2116     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2117   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2118     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2119   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2120     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2121   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2122     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2123   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2124     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2125   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2126     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2127   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2128     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2129   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2130     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2131   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2132     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2133   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2134     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2135   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2136     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2137   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2138     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2139   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
2140     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2141   { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
2142     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2143   { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
2144     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2145   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2146     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2147   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2148     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2149   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2150     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2151   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2152     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2153   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2154     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2155   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2156     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2157   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2158     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2159   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2160     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2161   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2162     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2163   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2164     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2165   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2166     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2167   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2168     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2169   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2170     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2171   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2172     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2173   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2174     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2175   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2176     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2177   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2178     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2179   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2180     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2181   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2182     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2183   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2184     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2185   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2186     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2187   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2188     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2189   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2190     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2191   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2192     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2193   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
2194     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2195   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
2196     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2197   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
2198     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2199   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2200     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2201   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESW,
2202     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2203   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUW,
2204     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2205     RS6000_BTI_unsigned_V4SI, 0 },
2206   { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
2207     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2208   { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
2209     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2210   { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
2211     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2212   { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
2213     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2214   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
2215     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2216   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
2217     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2218   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
2219     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2220   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSW,
2221     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2222   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUW,
2223     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2224     RS6000_BTI_unsigned_V4SI, 0 },
2225   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2226     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2227   { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
2228     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2229   { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
2230     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2231   { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
2232     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2233   { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
2234     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2235   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
2236     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2237   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
2238     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2239   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
2240     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2241   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
2242     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2243   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
2244     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2245   { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
2246     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2247   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
2248     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2249   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
2250     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2251
2252   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V16QI,
2253     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2254   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V8HI,
2255     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2256   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SI,
2257     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2258   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DI,
2259     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2260   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SF,
2261     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2262   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DF,
2263     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2264
2265   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2266     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2267   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2268     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2269   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2270     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2271   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2272     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2273   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2274     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2275   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2276     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2277   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2278     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2279   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2280     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2281   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2282     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2283   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2284     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2285   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2286     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2287   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2288     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2289   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2290     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2291   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2292     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2293   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2294     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2295   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2296     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2297   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2298     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2299   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2300     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2301   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2302     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2303   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2304     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
2305   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2306     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
2307   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2308     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2309   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2310     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
2311   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2312     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
2313   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2314     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2315   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2316     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2317   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2318     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2319   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2320     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2321   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2322     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2323   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2324     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2325   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2326     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2327   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2328     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2329   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2330     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2331   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2332     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2333   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2334     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2335   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2336     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2337   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2338     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2339   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2340     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2341   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2342     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2343   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2344     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2345   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2346     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2347   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2348     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2349   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2350     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2351   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2352     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2353   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2354     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2355   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2356     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2357   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2358     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2359   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2360     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2361   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2362     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2363   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2364     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2365   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2366     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2367   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2368     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2369   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2370     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2371   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2372     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2373   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2374     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2375   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2376     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2377   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2378     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2379   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2380     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2381   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2382     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2383   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2384     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2385   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2386     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2387   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2388     RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2389
2390   { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
2391     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2392
2393   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2394     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2395   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2396     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2397   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2398     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2399   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2400     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2401   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2402     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2403   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2404     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2405   { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2406     RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2407   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2408     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2409   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2410     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2411   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2412     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2413   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2414     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2415   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2416     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2417   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2418     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2419   { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2420     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2421   { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2422     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2423   { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2424     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2425   { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2426     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2427   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2428     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2429   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2430     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2431   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2432     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2433   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2434     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2435   { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2436     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2437   { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2438     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2439   { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2440     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2441   { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2442     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2443   { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2444     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2445   { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2446     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2447   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2448     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2449   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2450     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2451   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2452     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2453   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2454     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2455   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2456     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2457   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2458     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2459   { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2460     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2461   { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2462     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2463   { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2464     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2465   { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2466     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2467   { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2468     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2469   { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2470     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2471   { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2472     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2473   { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2474     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2475   { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2476     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2477     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2478   { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2479     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2480     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2481   { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2482     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2483     RS6000_BTI_unsigned_V4SI, 0 },
2484   { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2485     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2486     RS6000_BTI_unsigned_V2DI, 0 },
2487   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2488     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2489   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2490     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2491   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2492     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2493   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2494     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2495   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2496     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2497   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2498     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2499   { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2500     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2501   { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2502     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2503   { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2504     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2505   { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2506     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2507   { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2508     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2509   { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2510     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2511   { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2512     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2513   { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2514     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2515   { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2516     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2517   { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2518     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2519   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2520     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2521   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2522     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2523   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2524     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2525   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2526     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2527   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2528     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2529   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2530     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2531   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2532     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2533   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2534     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2535   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2536     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2537   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2538     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2539   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2540     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2541   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2542     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2543   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2544     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2545   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2546     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2547   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2548     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2549   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2550     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2551   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2552     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2553   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2554     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2555   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2556     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2557   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2558     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2559   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2560     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2561   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2562     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2563   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2564     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2565   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2566     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2567   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2568     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2569   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2570     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2571   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2572     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2573   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2574     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2575   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2576     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2577   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2578     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2579   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2580     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2581   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2582     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2583   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2584     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2585   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2586     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2587   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2588     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2589   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2590     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2591   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2592     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2593   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2594     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2595   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2596     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2597   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2598     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2599   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2600     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2601   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2602     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2603   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2604     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2605   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2606     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2607   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2608     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2609   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2610     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2611   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2612     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2613   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2614     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2615   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2616     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2617   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2618     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2619   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2620     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2621   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2622     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2623   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2624     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2625   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2626     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2627   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2628     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2629   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2630     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2631   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2632     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2633   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2634     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2635   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2636     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2637   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2638     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2639   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2640     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2641   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2642     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2643   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2644     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2645   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2646     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2647   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2648     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2649   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2650     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2651   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2652     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2653   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2654     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2655   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2656     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2657   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2658     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2659   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2660     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2661   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2662     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2663   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2664     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2665   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2666     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2667   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2668     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2669   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2670     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2671   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2672     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2673   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2674     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2675   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2676     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2677   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2678     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2679   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2680     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2681   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2682     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2683   { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2684     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2685   { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2686     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2687   { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2688     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2689   { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2690     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2691   { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2692     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2693   { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2694     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2695   { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2696     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2697   { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2698     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2699   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2700     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2701   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2702     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2703   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2704     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2705   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2706     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2707   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2708     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2709   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2710     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2711   { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2712     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2713   { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2714     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2715   { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2716     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2717   { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2718     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2719   { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2720     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2721   { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2722     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2723   { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2724     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2725   { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2726     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2727   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2728     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2729   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2730     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2731   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2732     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2733   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2734     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2735   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2736     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2737   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2738     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2739   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2740     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2741   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2742     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2743   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2744     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2745   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2746     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2747   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2748     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2749   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2750     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2751   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2752     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2753   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2754     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2755   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2756     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2757   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2758     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2759   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2760     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2761   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2762     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2763   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2764     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2765   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2766     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2767   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2768     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2769   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2770     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2771   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2772     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2773   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2774     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2775   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2776     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2777   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2778     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2779   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2780     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2781   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2782     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2783   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2784     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2785   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2786     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2787   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2788     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2789   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2790     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2791   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2792     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2793   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2794     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2795   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2796     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2797   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2798     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2799   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2800     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2801   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2802     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2803   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2804     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2805   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2806     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2807   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2808     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2809   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2810     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2811   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2812     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2813   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2814     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2815   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2816     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2817   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2818     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2819   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2820     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2821   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2822     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2823   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2824     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2825   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2826     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2827   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2828     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2829   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2830     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2831   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2832     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2833   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2834     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2835   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2836     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2837   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2838     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2839   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2840     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2841   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2842     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2843   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2844     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2845   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2846     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2847   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2848     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2849   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2850     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2851   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2852     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2853   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2854     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2855   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2856     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2857   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2858     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2859   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2860     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2861   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2862     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2863   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2864     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2865   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2866     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2867   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
2868     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2869   { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
2870     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2871   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2872     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2873   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2874     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2875     RS6000_BTI_unsigned_V1TI, 0 },
2876   { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
2877     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2878   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2879     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2880   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2881     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2882   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2883     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2884   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2885     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2886   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2887     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2888   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2889     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2890   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2891     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2892   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2893     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2894   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2895     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2896   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2897     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2898   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2899     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2900   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2901     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2902   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2903     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2904   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2905     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2906   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2907     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2908   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2909     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2910   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2911     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2912   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2913     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2914   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2915     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2916   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2917     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2918   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2919     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2920   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2921     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2922   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2923     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2924   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2925     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2926
2927   { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2928     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2929   { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2930     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2931   { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2932     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2933     RS6000_BTI_unsigned_V1TI, 0 },
2934   { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2935     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2936
2937   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2938     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2939   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2940     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2941   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2942     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2943   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2944     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2945   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2946     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2947   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2948     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2949   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2950     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2951   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2952     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2953   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2954     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2955   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2956     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2957   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2958     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2959   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2960     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2961   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2962     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2963   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2964     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2965   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2966     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2967   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2968     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2969   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2970     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2971   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2972     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2973   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2974     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2975   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2976     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2977   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2978     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2979   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2980     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2981   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2982     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2983   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2984     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2985   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2986     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2987   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2988     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2989   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2990     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2991   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2992     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2993   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2994     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2995   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2996     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2997   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2998     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2999   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3000     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3001   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3002     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3003   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3004     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3005   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3006     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3007   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3008     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3009   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3010     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3011   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3012     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3013   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3014     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3015   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3016     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3017   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3018     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3019   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3020     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3021   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
3022     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3023   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
3024     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3025   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
3026     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3027   { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
3028     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3029   { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
3030     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3031   { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
3032     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3033   { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
3034     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3035   { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
3036     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3037   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF,
3038     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3039   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF,
3040     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3041   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3042     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3043   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3044     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3045   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3046     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3047     ~RS6000_BTI_unsigned_V2DI, 0 },
3048   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3049     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3050     ~RS6000_BTI_unsigned_long_long, 0 },
3051   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF,
3052     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3053   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF,
3054     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3055   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3056     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3057   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3058     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3059   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3060     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3061   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3062     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3063   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3064     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3065   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3066     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3067   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3068     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3069   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3070     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3071   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3072     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3073   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3074     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3075   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3076     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3077     ~RS6000_BTI_unsigned_V16QI, 0 },
3078   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3079     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3080   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3081     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3082   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3083     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
3084   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3085     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
3086   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3087     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3088   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3089     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
3090   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3091     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
3092   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3093     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3094   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3095     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3096   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3097     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3098   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3099     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3100   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3101     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3102   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3103     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3104   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3105     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
3106   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3107     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
3108   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3109     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3110   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3111     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3112   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3113     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3114   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3115     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3116   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3117     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3118   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3119     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3120   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3121     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
3122   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3123     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3124   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3125     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3126   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3127     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3128   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3129     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3130   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3131     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3132   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3133     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3134   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3135     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3136   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3137     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
3138   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3139     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3140   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3141     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3142   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3143     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3144   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3145     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3146   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3147     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3148
3149   /* Ternary AltiVec/VSX builtins.  */
3150   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3151     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3152   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3153     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3154   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3155     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3156   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3157     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3158   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3159     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3160   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3161     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3162   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3163     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3164   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3165     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3166   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3167     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3168   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3169     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3170   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3171     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3172   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3173     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3174   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3175     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3176   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3177     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3178   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3179     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3180   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3181     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3182   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3183     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3184   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3185     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3186   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3187     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3188   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3189     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3190   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3191     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3192   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3193     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3194   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3195     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3196   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3197     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3198   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3199     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3200   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3201     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3202   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3203     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3204   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3205     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3206   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3207     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3208   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3209     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3210   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3211     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3212   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3213     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3214   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3215     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3216   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3217     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3218   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3219     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3220   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3221     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3222   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3223     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3224   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3225     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3226   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3227     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3228   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3229     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3230   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3231     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3232   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3233     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3234   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3235     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3236   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3237     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3238   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3239     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3240   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3241     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3242   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3243     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3244   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3245     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3246   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3247     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3248   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3249     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3250   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3251     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3252   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3253     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3254   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3255     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3256   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3257     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3258   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3259     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3260   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3261     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3262   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3263     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3264   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3265     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3266   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3267     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3268   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3269     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3270   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3271     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3272   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3273     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3274   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3275     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3276   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3277     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3278   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3279     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3280   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3281     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3282   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3283     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3284   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3285     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3286   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3287     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3288   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3289     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3290   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3291     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3292   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3293     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3294   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3295     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3296   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3297     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3298   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3299     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3300   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3301     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3302   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3303     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3304   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3305     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3306   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3307     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3308   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3309     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3310   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3311     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3312   { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3313     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3314   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3315     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3316   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3317     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3318   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3319     RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3320   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3321     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3322   { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3323     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3324   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3325     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3326   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3327     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3328   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3329     RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3330   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3331     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3332   { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3333     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3334   { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3335     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3336   { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3337     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3338   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3339     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3340   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3341     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3342   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3343     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3344   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3345     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3346   { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3347     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3348   { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3349     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3350   { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3351     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3352   { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3353     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3354   { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3355     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3356   { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3357     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3358   { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3359     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3360   { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3361     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3362   { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3363     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3364   { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3365     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3366   { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3367     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3368   { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3369     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3370   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3371     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3372   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3373     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3374   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3375     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3376   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3377     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3378     RS6000_BTI_unsigned_V16QI },
3379   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3380     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3381   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3382     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3383   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3384     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3385   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3386     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3387   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3388     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3389   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3390     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3391   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3392     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3393   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3394     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3395   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3396     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3397   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3398     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3399   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3400     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3401   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3402     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3403   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3404     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3405   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3406     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3407   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3408     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3409   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3410     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3411   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3412     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3413   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3414     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3415   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3416     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3417   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3418     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3419   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3420     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3421   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3422     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3423   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3424     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3425   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3426     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3427     RS6000_BTI_bool_V2DI },
3428   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3429     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3430     RS6000_BTI_unsigned_V2DI },
3431   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3432     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3433   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3434     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3435   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3436     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3437   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3438     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3439   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3440     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3441   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3442     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3443   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3444     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3445   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3446     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3447   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3448     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3449   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3450     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3451   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3452     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3453   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3454     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3455   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3456     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3457   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3458     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3459   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3460     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3461   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3462     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3463   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3464     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3465   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3466     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3467   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3468     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3469   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3470     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3471   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3472     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3473   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3474     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3475   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3476     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3477   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3478     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3479   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3480     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_NOT_OPAQUE },
3481   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3482     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE },
3483   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3484     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3485   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3486     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE },
3487   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3488     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_NOT_OPAQUE },
3489   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3490     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_NOT_OPAQUE },
3491   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3492     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3493   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3494     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
3495   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3496     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
3497   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3498     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3499   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3500     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3501     RS6000_BTI_NOT_OPAQUE },
3502   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3503     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3504     RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
3505   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3506     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3507     RS6000_BTI_NOT_OPAQUE },
3508   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3509     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3510     RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE },
3511   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3512     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3513     RS6000_BTI_NOT_OPAQUE },
3514   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3515     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3516     RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE },
3517   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3518     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3519     RS6000_BTI_NOT_OPAQUE },
3520   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3521     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3522     RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE },
3523   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3524     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3525   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3526     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3527   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3528     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3529     ~RS6000_BTI_unsigned_V2DI },
3530   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3531     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3532     ~RS6000_BTI_bool_V2DI },
3533   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3534     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3535   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3536     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3537   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3538     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3539   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3540     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3541   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3542     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3543   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3544     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3545   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3546     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3547   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3548     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3549   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3550     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3551   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3552     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3553   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3554     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3555   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3556     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3557   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3558     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3559   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3560     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3561   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3562     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3563   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3564     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3565   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3566     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3567   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3568     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3569   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3570     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3571   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3572     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3573   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3574     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3575   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3576     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3577   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3578     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3579   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3580     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3581   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3582     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3583   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3584     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3585   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3586     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3587   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3588     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3589   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3590     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3591   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3592     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3593   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3594     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3595   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3596     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3597   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3598     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3599   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3600     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3601   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3602     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3603   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3604     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3605   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3606     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3607   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3608     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3609   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3610     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3611   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3612     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3613   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3614     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3615   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3616     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3617   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3618     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3619   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3620     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3621   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3622     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3623   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3624     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3625   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3626     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3627   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3628     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3629   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3630     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3631   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3632     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3633   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3634     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3635   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3636     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3637   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3638     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3639   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3640     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3641   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3642     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3643   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3644     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3645   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3646     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3647   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3648     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3649   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3650     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3651   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3652     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3653   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3654     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3655   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3656     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3657   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3658     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3659   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3660     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3661   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3662     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3663   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3664     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3665   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3666     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3667   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3668     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3669   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3670     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3671   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3672     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3673   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3674     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3675   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3676     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3677   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3678     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3679   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3680     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3681   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3682     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3683   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3684     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3685   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3686     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3687   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3688     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3689   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3690     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3691   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3692     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3693   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3694     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3695   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3696     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3697   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3698     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3699   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3700     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3701   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3702     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3703   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3704     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3705   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3706     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3707     ~RS6000_BTI_unsigned_V2DI },
3708   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3709     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3710     ~RS6000_BTI_bool_V2DI },
3711   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3712     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3713   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3714     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3715   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3716     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3717   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3718     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3719   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3720     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3721   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3722     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3723   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3724     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3725   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3726     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3727   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3728     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3729   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3730     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3731   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3732     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3733   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3734     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3735   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3736     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3737   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3738     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3739   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3740     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3741   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3742     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3743   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3744     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3745   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3746     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3747   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3748     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3749   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3750     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3751   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3752     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3753   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3754     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3755   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3756     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3757   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3758     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3759   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3760     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3761   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3762     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3763   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3764     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3765   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3766     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3767   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3768     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3769   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3770     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3771   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3772     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3773   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3774     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3775   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3776     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3777   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3778     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3779   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3780     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3781   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3782     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3783   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3784     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3785   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3786     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3787   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3788     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3789   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3790     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3791   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3792     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3793   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3794     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3795   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3796     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3797   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3798     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3799   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3800     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3801   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3802     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3803   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3804     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3805   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3806     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3807   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3808     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3809   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3810     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3811   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3812     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3813   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3814     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3815   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3816     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3817   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3818     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3819   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3820     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3821   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3822     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3823   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3824     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3825   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3826     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3827   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3828     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3829   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3830     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3831   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3832     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3833   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3834     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3835   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3836     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3837   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3838     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3839   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3840     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3841   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3842     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3843   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3844     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3845   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3846     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3847   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3848     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3849   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3850     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3851   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3852     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3853   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3854     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3855   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF,
3856     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3857   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF,
3858     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3859   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3860     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3861   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3862     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
3863     ~RS6000_BTI_long_long },
3864   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3865     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3866     ~RS6000_BTI_unsigned_V2DI },
3867   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3868     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3869     ~RS6000_BTI_unsigned_long_long },
3870   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF,
3871     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3872   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF,
3873     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3874   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3875     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3876   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3877     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3878   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3879     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3880     ~RS6000_BTI_unsigned_V4SI },
3881   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3882     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3883     ~RS6000_BTI_UINTSI },
3884   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3885     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3886   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3887     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3888   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3889     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3890     ~RS6000_BTI_unsigned_V8HI },
3891   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3892     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3893     ~RS6000_BTI_UINTHI },
3894   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3895     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3896   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3897     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3898   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3899     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3900     ~RS6000_BTI_unsigned_V16QI },
3901   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3902     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3903     ~RS6000_BTI_UINTQI },
3904   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3905     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3906   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3907     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3908     RS6000_BTI_NOT_OPAQUE },
3909   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3910     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3911   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3912     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3913     RS6000_BTI_NOT_OPAQUE },
3914   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3915     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3916   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3917     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3918     RS6000_BTI_NOT_OPAQUE },
3919   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3920     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
3921   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3922     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3923     RS6000_BTI_NOT_OPAQUE },
3924   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
3925     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3926   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
3927     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3928   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
3929     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3930   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3931     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
3932   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3933     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3934     RS6000_BTI_NOT_OPAQUE },
3935   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
3936     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3937   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3938     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3939   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3940     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3941     RS6000_BTI_NOT_OPAQUE },
3942   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3943     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3944   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3945     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3946     RS6000_BTI_NOT_OPAQUE },
3947   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3948     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3949   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3950     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3951     RS6000_BTI_NOT_OPAQUE },
3952
3953   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3954     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3955   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3956     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3957   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3958     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3959   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3960     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3961     ~RS6000_BTI_unsigned_V2DI, 0 },
3962   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3963     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
3964   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3965     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3966   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3967     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3968   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3969     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
3970   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3971     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3972   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3973     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3974   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3975     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
3976   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3977     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3978     ~RS6000_BTI_unsigned_V4SI, 0 },
3979   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3980     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3981   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3982     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3983     ~RS6000_BTI_unsigned_long, 0 },
3984   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3985     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
3986   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3987     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
3988   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3989     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3990   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3991     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3992   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3993     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3994     ~RS6000_BTI_unsigned_V8HI, 0 },
3995   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3996     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3997   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3998     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
3999   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4000     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
4001   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4002     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
4003   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4004     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4005     ~RS6000_BTI_unsigned_V16QI, 0 },
4006   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4007     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4008
4009   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4010     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4011   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4012     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4013   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4014     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4015   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4016     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4017     ~RS6000_BTI_unsigned_V2DI },
4018   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4019     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4020     ~RS6000_BTI_bool_V2DI },
4021   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4022     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4023   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4024     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4025   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4026     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4027   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4028     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4029   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4030     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4031     ~RS6000_BTI_unsigned_V4SI },
4032   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4033     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4034     ~RS6000_BTI_UINTSI },
4035   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4036     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4037     ~RS6000_BTI_bool_V4SI },
4038   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4039     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4040     ~RS6000_BTI_UINTSI },
4041   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4042     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4043     ~RS6000_BTI_INTSI },
4044   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4045     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4046   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4047     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4048   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4049     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4050     ~RS6000_BTI_unsigned_V8HI },
4051   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4052     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4053     ~RS6000_BTI_UINTHI },
4054   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4055     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4056     ~RS6000_BTI_bool_V8HI },
4057   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4058     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4059     ~RS6000_BTI_UINTHI },
4060   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4061     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4062     ~RS6000_BTI_INTHI },
4063   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4064     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4065   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4066     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4067   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4068     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4069     ~RS6000_BTI_unsigned_V16QI },
4070   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4071     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4072     ~RS6000_BTI_UINTQI },
4073   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4074     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4075     ~RS6000_BTI_bool_V16QI },
4076   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4077     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4078     ~RS6000_BTI_UINTQI },
4079   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4080     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4081     ~RS6000_BTI_INTQI },
4082   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4083     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
4084     ~RS6000_BTI_pixel_V8HI },
4085
4086   /* Predicates.  */
4087   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4088     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4089   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4090     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4091   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4092     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4093   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4094     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4095   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4096     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4097   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4098     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4099   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4100     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4101   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4102     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4103   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4104     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4105   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4106     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4107   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4108     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4109   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4110     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4111   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4112     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4113   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4114     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4115   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4116     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4117   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4118     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4119   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4120     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4121   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4122     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4123   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4124     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4125   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4126     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4127   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4128     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4129   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4130     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4131   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4132     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4133   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4134     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4135   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
4136     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4137   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
4138     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4139
4140
4141   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4142     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4143   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4144     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4145   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4146     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4147   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4148     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4149   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4150     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4151   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4152     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4153   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4154     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4155   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4156     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4157   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4158     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4159   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4160     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4161   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4162     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4163   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4164     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4165   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4166     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4167   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4168     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4169   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4170     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4171   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4172     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4173   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4174     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4175   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4176     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4177   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4178     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4179   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4180     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4181   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4182     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4183   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4184     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4185   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4186     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4187   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4188     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4189   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4190     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4191   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4192     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4193   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4194     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4195   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4196     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4197   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4198     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4199   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4200     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4201   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4202     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4203
4204
4205   /* cmpge is the same as cmpgt for all cases except floating point.
4206      There is further code to deal with this special case in
4207      altivec_build_resolved_builtin.  */
4208   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4209     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4210   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4211     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4212   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4213     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4214   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4215     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4216   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4217     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4218   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4219     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4220   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4221     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4222   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4223     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4224   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4225     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4226   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4227     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4228   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4229     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4230   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4231     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4232   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4233     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4234   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4235     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4236   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4237     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4238   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4239     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4240   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4241     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4242   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4243     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4244   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4245     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4246   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4247     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4248   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4249     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4250   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4251     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4252   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4253     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4254   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4255     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4256   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4257     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4258   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4259     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4260
4261   /* Power8 vector overloaded functions.  */
4262   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4263     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4264   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4265     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4266   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4267     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4268   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4269     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4270   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4271     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4272     RS6000_BTI_unsigned_V16QI, 0 },
4273   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4274     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4275     RS6000_BTI_bool_V16QI, 0 },
4276   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4277     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4278     RS6000_BTI_unsigned_V16QI, 0 },
4279   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4280     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4281   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4282     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4283   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4284     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4285   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4286     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4287   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4288     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4289     RS6000_BTI_unsigned_V8HI, 0 },
4290   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4291     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4292     RS6000_BTI_bool_V8HI, 0 },
4293   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4294     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4295     RS6000_BTI_unsigned_V8HI, 0 },
4296   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4297     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4298   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4299     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4300   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4301     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4302   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4303     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4304   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4305     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4306     RS6000_BTI_unsigned_V4SI, 0 },
4307   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4308     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4309     RS6000_BTI_bool_V4SI, 0 },
4310   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4311     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4312     RS6000_BTI_unsigned_V4SI, 0 },
4313   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4314     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4315   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4316     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4317   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4318     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4319   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4320     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4321   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4322     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4323     RS6000_BTI_unsigned_V2DI, 0 },
4324   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4325     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4326     RS6000_BTI_bool_V2DI, 0 },
4327   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4328     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4329     RS6000_BTI_unsigned_V2DI, 0 },
4330   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4331     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4332   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4333     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4334
4335   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4336     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4337   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4338     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4339   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4340     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4341   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4342     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4343     RS6000_BTI_unsigned_V16QI, 0 },
4344   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4345     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4346     RS6000_BTI_bool_V16QI, 0 },
4347   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4348     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4349     RS6000_BTI_unsigned_V16QI, 0 },
4350   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4351     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4352   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4353     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4354   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4355     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4356   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4357     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4358   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4359     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4360     RS6000_BTI_unsigned_V8HI, 0 },
4361   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4362     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4363     RS6000_BTI_bool_V8HI, 0 },
4364   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4365     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4366     RS6000_BTI_unsigned_V8HI, 0 },
4367   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4368     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4369   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4370     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4371   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4372     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4373   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4374     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4375   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4376     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4377     RS6000_BTI_unsigned_V4SI, 0 },
4378   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4379     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4380     RS6000_BTI_bool_V4SI, 0 },
4381   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4382     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4383     RS6000_BTI_unsigned_V4SI, 0 },
4384   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4385     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4386   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4387     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4388   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4389     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4390   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4391     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4392   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4393     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4394     RS6000_BTI_unsigned_V2DI, 0 },
4395   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4396     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4397     RS6000_BTI_bool_V2DI, 0 },
4398   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4399     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4400     RS6000_BTI_unsigned_V2DI, 0 },
4401   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4402     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4403   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4404     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4405   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4406     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4407
4408   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4409     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4410   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4411     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4412   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4413     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4414   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4415     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4416     RS6000_BTI_unsigned_V16QI, 0 },
4417   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4418     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4419     RS6000_BTI_bool_V16QI, 0 },
4420   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4421     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4422     RS6000_BTI_unsigned_V16QI, 0 },
4423   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4424     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4425   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4426     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4427   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4428     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4429   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4430     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4431   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4432     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4433     RS6000_BTI_unsigned_V8HI, 0 },
4434   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4435     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4436     RS6000_BTI_bool_V8HI, 0 },
4437   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4438     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4439     RS6000_BTI_unsigned_V8HI, 0 },
4440   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4441     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4442   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4443     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4444   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4445     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4446   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4447     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4448   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4449     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4450     RS6000_BTI_unsigned_V4SI, 0 },
4451   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4452     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4453     RS6000_BTI_bool_V4SI, 0 },
4454   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4455     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4456     RS6000_BTI_unsigned_V4SI, 0 },
4457   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4458     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4459   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4460     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4461   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4462     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4463   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4464     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4465   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4466     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4467     RS6000_BTI_unsigned_V2DI, 0 },
4468   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4469     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4470     RS6000_BTI_bool_V2DI, 0 },
4471   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4472     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4473     RS6000_BTI_unsigned_V2DI, 0 },
4474   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4475     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4476   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4477     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4478   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4479     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4480
4481   { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4482     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4483   { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4484     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4485     RS6000_BTI_unsigned_V1TI, 0 },
4486
4487   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4488     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4489   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4490     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4491   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4492     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4493   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4494     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4495   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4496     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4497   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4498     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4499
4500   { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4501     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4502   { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4503     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4504     RS6000_BTI_unsigned_V1TI, 0 },
4505
4506   { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4507     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4508     RS6000_BTI_unsigned_V16QI, 0 },
4509   { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4510     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4511     RS6000_BTI_unsigned_V16QI, 0 },
4512   { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4513     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4514     RS6000_BTI_unsigned_V16QI, 0 },
4515
4516   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4517     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4518     RS6000_BTI_unsigned_V16QI, 0 },
4519   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4520     RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4521   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4522     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4523     RS6000_BTI_unsigned_V16QI, 0 },
4524   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4525     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4526     RS6000_BTI_unsigned_V16QI, 0 },
4527
4528   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4529     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4530   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4531     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4532   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4533     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4534   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4535     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4536   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4537     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4538   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4539     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4540   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4541     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4542   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4543     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4544
4545   { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4546     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4547   { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4548     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4549
4550   { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4551     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4552   { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4553     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4554
4555   { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4556     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4557   { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4558     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4559
4560   { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4561     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4562   { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4563     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4564
4565   { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4566     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4567   { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4568     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4569
4570   { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4571     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4572   { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4573     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4574
4575   { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4576     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4577   { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4578     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4579
4580   { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4581     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4582   { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4583     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4584
4585   { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4586     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4587   { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4588     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4589
4590   { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4591     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4592   { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4593     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4594
4595   { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4596     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4597   { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4598     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4599
4600   { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4601     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4602   { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4603     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4604
4605   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4606     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4607   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4608     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4609   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4610     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4611   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4612     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4613   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4614     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4615   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4616     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4617   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4618     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4619   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4620     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4621
4622   { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4623     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4624   { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4625     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4626
4627   { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4628     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4629   { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4630     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4631
4632   { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4633     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4634   { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4635     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4636
4637   { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4638     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4639   { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4640     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4641
4642   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4643     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4644     RS6000_BTI_unsigned_V16QI, 0 },
4645   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4646     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4647     RS6000_BTI_unsigned_V8HI, 0 },
4648   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4649     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4650     RS6000_BTI_unsigned_V4SI, 0 },
4651
4652   { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4653     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4654     RS6000_BTI_unsigned_V16QI, 0 },
4655
4656   { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4657     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4658     RS6000_BTI_unsigned_V8HI, 0 },
4659
4660   { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
4661     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4662     RS6000_BTI_unsigned_V4SI, 0 },
4663
4664   { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
4665     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4666   { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
4667     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4668
4669   { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
4670     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4671   { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
4672     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4673
4674   { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
4675     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4676   { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
4677     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4678
4679   { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
4680     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4681   { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
4682     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4683
4684   { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
4685     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4686   { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
4687     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4688
4689   { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
4690     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4691   { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
4692     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4693
4694   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4695     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4696   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4697     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4698
4699   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4700     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4701   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4702     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4703
4704   { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4705     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4706   { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4707     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4708
4709   { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4710     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4711   { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4712     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4713
4714   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
4715     RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4716   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
4717     RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4718   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP,
4719     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4720
4721   { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
4722     RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4723   { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
4724     RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4725   { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP,
4726     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4727
4728   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
4729     RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4730   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
4731     RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4732   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP,
4733     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4734
4735   { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
4736     RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4737   { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
4738     RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4739   { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP,
4740     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4741
4742   { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
4743     RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
4744   { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP,
4745     RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 },
4746
4747   { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
4748     RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
4749   { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP,
4750     RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 },
4751
4752   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
4753     RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
4754   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
4755     RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
4756
4757   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP,
4758     RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 },
4759   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
4760     RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
4761
4762   { P9V_BUILTIN_VEC_VSCEDPGT, P9V_BUILTIN_VSCEDPGT,
4763     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4764   { P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VSCEDPLT,
4765     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4766   { P9V_BUILTIN_VEC_VSCEDPEQ, P9V_BUILTIN_VSCEDPEQ,
4767     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4768   { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,
4769     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4770
4771   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4772     RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4773     RS6000_BTI_unsigned_long_long, 0 },
4774   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4775     RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4776     RS6000_BTI_unsigned_long_long, 0 },
4777
4778   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4779     RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4780     RS6000_BTI_unsigned_long_long, 0 },
4781   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4782     RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4783     RS6000_BTI_unsigned_long_long, 0 },
4784
4785   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4786     RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4787     RS6000_BTI_unsigned_long_long, 0 },
4788   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4789     RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4790     RS6000_BTI_unsigned_long_long, 0 },
4791
4792   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4793     RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4794     RS6000_BTI_unsigned_long_long, 0 },
4795   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4796     RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4797     RS6000_BTI_unsigned_long_long, 0 },
4798
4799   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4800     RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4801     RS6000_BTI_unsigned_long_long, 0 },
4802   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4803     RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4804     RS6000_BTI_unsigned_long_long, 0 },
4805
4806   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4807     RS6000_BTI_V2DF, ~RS6000_BTI_double,
4808     RS6000_BTI_unsigned_long_long, 0 },
4809   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4810     RS6000_BTI_V4SF, ~RS6000_BTI_float,
4811     RS6000_BTI_unsigned_long_long, 0 },
4812   /* At an appropriate future time, add support for the
4813      RS6000_BTI_Float16 (exact name to be determined) type here.  */
4814
4815   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4816     RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4817     RS6000_BTI_unsigned_long_long },
4818   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4819     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4820     RS6000_BTI_unsigned_long_long },
4821
4822   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4823     RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4824     RS6000_BTI_unsigned_long_long },
4825   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4826     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4827     RS6000_BTI_unsigned_long_long },
4828
4829   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4830     RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4831     RS6000_BTI_unsigned_long_long },
4832   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4833     RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4834     RS6000_BTI_unsigned_long_long },
4835
4836   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4837     RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4838     RS6000_BTI_unsigned_long_long },
4839   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4840     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4841     RS6000_BTI_unsigned_long_long },
4842
4843   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4844     RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4845     RS6000_BTI_unsigned_long_long },
4846   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4847     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4848     RS6000_BTI_unsigned_long_long },
4849
4850   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4851     RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
4852     RS6000_BTI_unsigned_long_long },
4853   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4854     RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
4855     RS6000_BTI_unsigned_long_long },
4856   /* At an appropriate future time, add support for the
4857      RS6000_BTI_Float16 (exact name to be determined) type here.  */
4858
4859   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4860     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
4861     RS6000_BTI_bool_V16QI, 0 },
4862   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4863     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4864     RS6000_BTI_V16QI, 0 },
4865   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4866     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
4867     RS6000_BTI_unsigned_V16QI, 0 },
4868
4869   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4870     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
4871     RS6000_BTI_bool_V8HI, 0 },
4872   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4873     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
4874     RS6000_BTI_V8HI, 0 },
4875   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4876     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
4877     RS6000_BTI_unsigned_V8HI, 0 },
4878
4879   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4880     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
4881     RS6000_BTI_bool_V4SI, 0 },
4882   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4883     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
4884     RS6000_BTI_V4SI, 0 },
4885   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4886     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
4887     RS6000_BTI_unsigned_V4SI, 0 },
4888
4889   /* The following 2 entries have been deprecated.  */
4890   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4891     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4892     RS6000_BTI_unsigned_V16QI, 0 },
4893   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4894     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4895     RS6000_BTI_bool_V16QI, 0 },
4896   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4897     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4898     RS6000_BTI_unsigned_V16QI, 0 },
4899
4900   /* The following 2 entries have been deprecated.  */
4901   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4902     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4903     RS6000_BTI_V16QI, 0 },
4904   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4905     RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4906     RS6000_BTI_bool_V16QI, 0 },
4907   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4908     RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4909   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4910     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4911     RS6000_BTI_bool_V16QI, 0 },
4912
4913   /* The following 2 entries have been deprecated.  */
4914   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4915     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4916     RS6000_BTI_unsigned_V8HI, 0 },
4917   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4918     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4919     RS6000_BTI_bool_V8HI, 0 },
4920   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4921     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4922     RS6000_BTI_unsigned_V8HI, 0 },
4923   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4924     RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4925
4926   /* The following 2 entries have been deprecated.  */
4927   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4928     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4929     RS6000_BTI_V8HI, 0 },
4930   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4931     RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4932     RS6000_BTI_bool_V8HI, 0 },
4933   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4934     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4935     RS6000_BTI_bool_V8HI, 0 },
4936   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4937     RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4938     RS6000_BTI_pixel_V8HI, 0 },
4939
4940   /* The following 2 entries have been deprecated.  */
4941   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4942     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4943     RS6000_BTI_unsigned_V4SI, 0 },
4944   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4945     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4946     RS6000_BTI_bool_V4SI, 0 },
4947   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4948     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4949     RS6000_BTI_unsigned_V4SI, 0 },
4950
4951   /* The following 2 entries have been deprecated.  */
4952   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4953     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4954     RS6000_BTI_V4SI, 0 },
4955   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4956     RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4957     RS6000_BTI_bool_V4SI, 0 },
4958   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4959     RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4960   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4961     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4962     RS6000_BTI_bool_V4SI, 0 },
4963
4964   /* The following 2 entries have been deprecated.  */
4965   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4966     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4967     RS6000_BTI_unsigned_V2DI, 0 },
4968   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4969     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4970     RS6000_BTI_bool_V2DI, 0 },
4971   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4972     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4973     RS6000_BTI_unsigned_V2DI, 0
4974   },
4975
4976   /* The following 2 entries have been deprecated.  */
4977   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4978     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4979     RS6000_BTI_V2DI, 0 },
4980   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4981     RS6000_BTI_INTSI, RS6000_BTI_V2DI,
4982     RS6000_BTI_bool_V2DI, 0 },
4983   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4984     RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4985   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4986     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4987     RS6000_BTI_bool_V2DI, 0 },
4988
4989   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
4990     RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4991   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
4992     RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4993
4994   /* The following 2 entries have been deprecated.  */
4995   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4996     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4997     RS6000_BTI_unsigned_V16QI, 0 },
4998   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4999     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5000     RS6000_BTI_bool_V16QI, 0 },
5001   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5002     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5003     RS6000_BTI_unsigned_V16QI, 0 },
5004
5005   /* The following 2 entries have been deprecated.  */
5006   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5007     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5008     RS6000_BTI_V16QI, 0 },
5009   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5010     RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5011     RS6000_BTI_bool_V16QI, 0 },
5012   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5013     RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5014   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5015     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5016     RS6000_BTI_bool_V16QI, 0 },
5017
5018   /* The following 2 entries have been deprecated.  */
5019   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5020     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5021     RS6000_BTI_unsigned_V8HI, 0 },
5022   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5023     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5024     RS6000_BTI_bool_V8HI, 0 },
5025   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5026     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5027     RS6000_BTI_unsigned_V8HI, 0 },
5028   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5029     RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5030
5031   /* The following 2 entries have been deprecated.  */
5032   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5033     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5034     RS6000_BTI_V8HI, 0 },
5035   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5036     RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5037     RS6000_BTI_bool_V8HI, 0 },
5038   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5039     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5040     RS6000_BTI_bool_V8HI, 0 },
5041   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5042     RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5043     RS6000_BTI_pixel_V8HI, 0 },
5044
5045   /* The following 2 entries have been deprecated.  */
5046   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5047     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5048     RS6000_BTI_unsigned_V4SI, 0 },
5049   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5050     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5051     RS6000_BTI_bool_V4SI, 0 },
5052   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5053     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5054     RS6000_BTI_unsigned_V4SI, 0 },
5055
5056   /* The following 2 entries have been deprecated.  */
5057   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5058     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5059     RS6000_BTI_V4SI, 0 },
5060   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5061     RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5062     RS6000_BTI_bool_V4SI, 0 },
5063   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5064     RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5065   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5066     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5067     RS6000_BTI_bool_V4SI, 0 },
5068
5069   /* The following 2 entries have been deprecated.  */
5070   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5071     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5072     RS6000_BTI_unsigned_V2DI, 0 },
5073   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5074     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5075     RS6000_BTI_bool_V2DI, 0 },
5076   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5077     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5078     RS6000_BTI_unsigned_V2DI, 0
5079   },
5080
5081   /* The following 2 entries have been deprecated.  */
5082   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5083     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5084     RS6000_BTI_V2DI, 0 },
5085   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5086     RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5087     RS6000_BTI_bool_V2DI, 0 },
5088   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5089     RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5090   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5091     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5092     RS6000_BTI_bool_V2DI, 0 },
5093
5094   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
5095     RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5096   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
5097     RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5098
5099   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5100     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5101     RS6000_BTI_unsigned_V16QI },
5102   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5103     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
5104
5105   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5106     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5107     RS6000_BTI_unsigned_V8HI },
5108   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5109     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
5110
5111   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5112     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5113     RS6000_BTI_unsigned_V4SI },
5114   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5115     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
5116
5117   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5118     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5119     RS6000_BTI_V16QI, 0 },
5120   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5121     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5122     RS6000_BTI_unsigned_V16QI, 0 },
5123
5124   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5125     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5126     RS6000_BTI_V8HI, 0 },
5127   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5128     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5129     RS6000_BTI_unsigned_V8HI, 0 },
5130
5131   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5132     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5133     RS6000_BTI_V4SI, 0 },
5134   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5135     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5136     RS6000_BTI_unsigned_V4SI, 0 },
5137
5138   { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5139     RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5140   { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5141     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5142
5143   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
5144     RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5145   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
5146     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5147
5148   { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
5149     RS6000_BTI_INTDI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
5150   { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
5151     RS6000_BTI_INTDI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI, 0 },
5152
5153   { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5154     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5155   { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5156     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5157
5158   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5159     RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5160     RS6000_BTI_V16QI, 0 },
5161   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5162     RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5163     RS6000_BTI_unsigned_V16QI, 0 },
5164
5165   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5166     RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5167     RS6000_BTI_V8HI, 0 },
5168   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5169     RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5170     RS6000_BTI_unsigned_V8HI, 0 },
5171
5172   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5173     RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5174     RS6000_BTI_V4SI, 0 },
5175   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5176     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5177     RS6000_BTI_unsigned_V4SI, 0 },
5178   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5179     RS6000_BTI_float, RS6000_BTI_UINTSI,
5180     RS6000_BTI_V4SF, 0 },
5181
5182   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5183     RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5184     RS6000_BTI_V16QI, 0 },
5185   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5186     RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5187     RS6000_BTI_unsigned_V16QI, 0 },
5188
5189   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5190     RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5191     RS6000_BTI_V8HI, 0 },
5192   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5193     RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5194     RS6000_BTI_unsigned_V8HI, 0 },
5195
5196   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5197     RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5198     RS6000_BTI_V4SI, 0 },
5199   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5200     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5201     RS6000_BTI_unsigned_V4SI, 0 },
5202   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5203     RS6000_BTI_float, RS6000_BTI_UINTSI,
5204     RS6000_BTI_V4SF, 0 },
5205
5206   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5207     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5208   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5209     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5210
5211   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5212     RS6000_BTI_V16QI, RS6000_BTI_V4SI,
5213     RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
5214   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5215     RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI,
5216     RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
5217   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5218     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5219     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
5220   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5221     RS6000_BTI_V16QI, RS6000_BTI_INTDI,
5222     RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5223   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5224     RS6000_BTI_V16QI, RS6000_BTI_UINTDI,
5225     RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5226   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5227     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTDI,
5228     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5229   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5230     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI,
5231     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5232
5233   { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5234     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5235   { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5236     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5237     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5238
5239   { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5240     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5241   { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5242     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5243     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5244
5245   { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5246     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5247   { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5248     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5249     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5250
5251   { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5252     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5253   { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5254     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5255     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5256
5257   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5258     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5259   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5260     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5261   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5262     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5263
5264   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5265     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5266   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5267     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5268   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5269     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5270
5271   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5272     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5273     RS6000_BTI_unsigned_V2DI, 0 },
5274   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5275     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5276     RS6000_BTI_bool_V2DI, 0 },
5277   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5278     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5279     RS6000_BTI_unsigned_V2DI, 0 },
5280
5281   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5282     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5283     RS6000_BTI_unsigned_V2DI, 0 },
5284   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5285     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5286     RS6000_BTI_bool_V2DI, 0 },
5287   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5288     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5289     RS6000_BTI_unsigned_V2DI, 0 },
5290
5291   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5292     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5293   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5294     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5295     RS6000_BTI_unsigned_V4SI, 0 },
5296   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5297     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5298
5299   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5300     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5301   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5302     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5303     RS6000_BTI_unsigned_V4SI, 0 },
5304   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5305     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5306
5307   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5308     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5309     RS6000_BTI_unsigned_V16QI, 0 },
5310   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5311     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5312     RS6000_BTI_unsigned_V8HI, 0 },
5313   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5314     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5315     RS6000_BTI_unsigned_V4SI, 0 },
5316   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5317     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5318     RS6000_BTI_unsigned_V2DI, 0 },
5319
5320   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5321     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5322   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5323     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5324   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5325     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5326   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5327     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5328   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5329     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5330   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5331     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5332   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5333     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5334   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5335     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5336
5337   { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5338     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5339   { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5340     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5341
5342   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5343     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5344   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5345     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5346
5347   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5348     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5349   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5350     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5351
5352   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5353     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5354   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5355     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5356
5357   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5358     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5359   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5360     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5361
5362   { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5363     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5364   { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5365     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5366
5367   { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5368     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5369   { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5370     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5371
5372   { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5373     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5374   { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5375     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5376
5377   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5378     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5379   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5380     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5381   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5382     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5383   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5384     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5385   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5386     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5387   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5388     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5389   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5390     RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5391   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5392     RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5393
5394   { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5395     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5396   { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5397     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5398
5399   { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5400     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5401   { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5402     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5403
5404   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5405     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5406   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5407     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5408   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5409     RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5410   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5411     RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5412
5413   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5414     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5415   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5416     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5417   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5418     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5419   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5420     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5421   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5422     RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
5423   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5424     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5425
5426   { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5427     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5428   { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5429     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5430   { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5431     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5432
5433   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5434     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5435   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5436     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5437   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5438     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5439
5440   { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5441     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5442
5443   { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5444     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5445
5446   { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5447     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5448
5449   { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5450     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5451   { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5452     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5453
5454   { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5455     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5456   { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5457     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5458
5459   { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5460     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5461   { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5462     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5463
5464   { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5465     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5466   { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5467     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5468
5469   { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5470     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5471   { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5472     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5473     RS6000_BTI_unsigned_V1TI, 0 },
5474
5475   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5476     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5477   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5478     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5479   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5480     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5481   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5482     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5483   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5484     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5485   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5486     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5487
5488   { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5489     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5490   { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5491     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5492     RS6000_BTI_unsigned_V1TI, 0 },
5493
5494   { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5495     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5496   { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5497     RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5498
5499   { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5500     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5501   { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5502     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5503
5504   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5505     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5506   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5507     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5508
5509   { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5510     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5511     RS6000_BTI_unsigned_V16QI, 0 },
5512   { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5513     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5514     RS6000_BTI_unsigned_V16QI, 0 },
5515
5516   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5517     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5518   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5519     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5520   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5521     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5522   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
5523     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5524   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
5525     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5526   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5527     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5528   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5529     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5530   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DF,
5531     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5532   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5533     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5534   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5535     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5536   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5537     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5538   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SF,
5539     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5540   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5541     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5542   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5543     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5544   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5545     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5546
5547   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5548     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5549   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5550     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5551   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5552     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5553   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5554     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5555   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5556     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5557   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5558     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5559   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5560     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5561   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5562     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5563   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
5564     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5565   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
5566     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5567   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5568     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5569   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5570     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5571   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5572     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5573   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5574     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5575
5576   { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF,
5577     RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 },
5578   { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF,
5579     RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5580   { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5581     RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5582   { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5583     RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5584   { VSX_BUILTIN_VEC_VSIGNED2, VSX_BUILTIN_VEC_VSIGNED2_V2DF,
5585     RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5586
5587   { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5588     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5589   { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5590     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5591   { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5592     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5593   { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5594     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5595   { VSX_BUILTIN_VEC_VUNSIGNED2, VSX_BUILTIN_VEC_VUNSIGNED2_V2DF,
5596     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5597     RS6000_BTI_V2DF, 0 },
5598
5599   /* Crypto builtins.  */
5600   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5601     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5602     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5603   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5604     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5605     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5606   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5607     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5608     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5609   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5610     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5611     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5612
5613   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5614     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5615     RS6000_BTI_unsigned_V16QI, 0 },
5616   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5617     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5618     RS6000_BTI_unsigned_V8HI, 0 },
5619   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5620     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5621     RS6000_BTI_unsigned_V4SI, 0 },
5622   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5623     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5624     RS6000_BTI_unsigned_V2DI, 0 },
5625
5626   { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5627     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5628     RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5629   { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5630     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5631     RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5632
5633   { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
5634 };
5635 \f
5636
5637 /* Convert a type stored into a struct altivec_builtin_types as ID,
5638    into a tree.  The types are in rs6000_builtin_types: negative values
5639    create a pointer type for the type associated to ~ID.  Note it is
5640    a logical NOT, rather than a negation, otherwise you cannot represent
5641    a pointer type for ID 0.  */
5642
5643 static inline tree
5644 rs6000_builtin_type (int id)
5645 {
5646   tree t;
5647   t = rs6000_builtin_types[id < 0 ? ~id : id];
5648   return id < 0 ? build_pointer_type (t) : t;
5649 }
5650
5651 /* Check whether the type of an argument, T, is compatible with a
5652    type ID stored into a struct altivec_builtin_types.  Integer
5653    types are considered compatible; otherwise, the language hook
5654    lang_hooks.types_compatible_p makes the decision.  */
5655
5656 static inline bool
5657 rs6000_builtin_type_compatible (tree t, int id)
5658 {
5659   tree builtin_type;
5660   builtin_type = rs6000_builtin_type (id);
5661   if (t == error_mark_node)
5662     return false;
5663   if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type))
5664     return true;
5665   else
5666     return lang_hooks.types_compatible_p (t, builtin_type);
5667 }
5668
5669
5670 /* In addition to calling fold_convert for EXPR of type TYPE, also
5671    call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be
5672    hiding there (PR47197).  */
5673
5674 static tree
5675 fully_fold_convert (tree type, tree expr)
5676 {
5677   tree result = fold_convert (type, expr);
5678   bool maybe_const = true;
5679
5680   if (!c_dialect_cxx ())
5681     result = c_fully_fold (result, false, &maybe_const);
5682
5683   return result;
5684 }
5685
5686 /* Build a tree for a function call to an Altivec non-overloaded builtin.
5687    The overloaded builtin that matched the types and args is described
5688    by DESC.  The N arguments are given in ARGS, respectively.
5689
5690    Actually the only thing it does is calling fold_convert on ARGS, with
5691    a small exception for vec_{all,any}_{ge,le} predicates. */
5692
5693 static tree
5694 altivec_build_resolved_builtin (tree *args, int n,
5695                                 const struct altivec_builtin_types *desc)
5696 {
5697   tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code];
5698   tree ret_type = rs6000_builtin_type (desc->ret_type);
5699   tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl));
5700   tree arg_type[3];
5701   tree call;
5702
5703   int i;
5704   for (i = 0; i < n; i++)
5705     arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes);
5706
5707   /* The AltiVec overloading implementation is overall gross, but this
5708      is particularly disgusting.  The vec_{all,any}_{ge,le} builtins
5709      are completely different for floating-point vs. integer vector
5710      types, because the former has vcmpgefp, but the latter should use
5711      vcmpgtXX.
5712
5713      In practice, the second and third arguments are swapped, and the
5714      condition (LT vs. EQ, which is recognizable by bit 1 of the first
5715      argument) is reversed.  Patch the arguments here before building
5716      the resolved CALL_EXPR.  */
5717   if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P
5718       && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P
5719       && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P)
5720     {
5721       tree t;
5722       t = args[2], args[2] = args[1], args[1] = t;
5723       t = arg_type[2], arg_type[2] = arg_type[1], arg_type[1] = t;
5724
5725       args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0],
5726                              build_int_cst (NULL_TREE, 2));
5727     }
5728
5729   switch (n)
5730     {
5731     case 0:
5732       call = build_call_expr (impl_fndecl, 0);
5733       break;
5734     case 1:
5735       call = build_call_expr (impl_fndecl, 1,
5736                               fully_fold_convert (arg_type[0], args[0]));
5737       break;
5738     case 2:
5739       call = build_call_expr (impl_fndecl, 2,
5740                               fully_fold_convert (arg_type[0], args[0]),
5741                               fully_fold_convert (arg_type[1], args[1]));
5742       break;
5743     case 3:
5744       call = build_call_expr (impl_fndecl, 3,
5745                               fully_fold_convert (arg_type[0], args[0]),
5746                               fully_fold_convert (arg_type[1], args[1]),
5747                               fully_fold_convert (arg_type[2], args[2]));
5748       break;
5749     default:
5750       gcc_unreachable ();
5751     }
5752   return fold_convert (ret_type, call);
5753 }
5754
5755 /* Implementation of the resolve_overloaded_builtin target hook, to
5756    support Altivec's overloaded builtins.  */
5757
5758 tree
5759 altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
5760                                     void *passed_arglist)
5761 {
5762   vec<tree, va_gc> *arglist = static_cast<vec<tree, va_gc> *> (passed_arglist);
5763   unsigned int nargs = vec_safe_length (arglist);
5764   enum rs6000_builtins fcode
5765     = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
5766   tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl));
5767   tree types[3], args[3];
5768   const struct altivec_builtin_types *desc;
5769   unsigned int n;
5770
5771   if (!rs6000_overloaded_builtin_p (fcode))
5772     return NULL_TREE;
5773
5774   if (TARGET_DEBUG_BUILTIN)
5775     fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n",
5776              (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)));
5777
5778   /* vec_lvsl and vec_lvsr are deprecated for use with LE element order.  */
5779   if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG)
5780     warning (OPT_Wdeprecated,
5781              "vec_lvsl is deprecated for little endian; use "
5782              "assignment for unaligned loads and stores");
5783   else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG)
5784     warning (OPT_Wdeprecated,
5785              "vec_lvsr is deprecated for little endian; use "
5786              "assignment for unaligned loads and stores");
5787
5788   if (fcode == ALTIVEC_BUILTIN_VEC_MUL)
5789     {
5790       /* vec_mul needs to be special cased because there are no instructions
5791          for it for the {un}signed char, {un}signed short, and {un}signed int
5792          types.  */
5793       if (nargs != 2)
5794         {
5795           error ("vec_mul only accepts 2 arguments");
5796           return error_mark_node;
5797         }
5798
5799       tree arg0 = (*arglist)[0];
5800       tree arg0_type = TREE_TYPE (arg0);
5801       tree arg1 = (*arglist)[1];
5802       tree arg1_type = TREE_TYPE (arg1);
5803
5804       /* Both arguments must be vectors and the types must be compatible.  */
5805       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5806         goto bad;
5807       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
5808         goto bad;
5809
5810       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5811         {
5812           case QImode:
5813           case HImode:
5814           case SImode:
5815           case DImode:
5816           case TImode:
5817             {
5818               /* For scalar types just use a multiply expression.  */
5819               return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0,
5820                                       fold_convert (TREE_TYPE (arg0), arg1));
5821             }
5822           case SFmode:
5823             {
5824               /* For floats use the xvmulsp instruction directly.  */
5825               tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP];
5826               return build_call_expr (call, 2, arg0, arg1);
5827             }
5828           case DFmode:
5829             {
5830               /* For doubles use the xvmuldp instruction directly.  */
5831               tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP];
5832               return build_call_expr (call, 2, arg0, arg1);
5833             }
5834           /* Other types are errors.  */
5835           default:
5836             goto bad;
5837         }
5838     }
5839
5840   if (fcode == ALTIVEC_BUILTIN_VEC_CMPNE)
5841     {
5842       /* vec_cmpne needs to be special cased because there are no instructions
5843          for it (prior to power 9).  */
5844       if (nargs != 2)
5845         {
5846           error ("vec_cmpne only accepts 2 arguments");
5847           return error_mark_node;
5848         }
5849
5850       tree arg0 = (*arglist)[0];
5851       tree arg0_type = TREE_TYPE (arg0);
5852       tree arg1 = (*arglist)[1];
5853       tree arg1_type = TREE_TYPE (arg1);
5854
5855       /* Power9 instructions provide the most efficient implementation of
5856          ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode
5857          or SFmode or DFmode.  */
5858       if (!TARGET_P9_VECTOR
5859           || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
5860           || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode)
5861           || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode)
5862           || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode))
5863         {
5864           /* Both arguments must be vectors and the types must be compatible.  */
5865           if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5866             goto bad;
5867           if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
5868             goto bad;
5869
5870           switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5871             {
5872               /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
5873                  vec_cmpeq (va, vb)).  */
5874               /* Note:  vec_nand also works but opt changes vec_nand's
5875                  to vec_nor's anyway.  */
5876             case QImode:
5877             case HImode:
5878             case SImode:
5879             case DImode:
5880             case TImode:
5881             case SFmode:
5882             case DFmode:
5883               {
5884                 /* call = vec_cmpeq (va, vb)
5885                    result = vec_nor (call, call).  */
5886                 vec<tree, va_gc> *params = make_tree_vector ();
5887                 vec_safe_push (params, arg0);
5888                 vec_safe_push (params, arg1);
5889                 tree call = altivec_resolve_overloaded_builtin
5890                   (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ],
5891                    params);
5892                 /* Use save_expr to ensure that operands used more than once
5893                    that may have side effects (like calls) are only evaluated
5894                    once.  */
5895                 call = save_expr (call);
5896                 params = make_tree_vector ();
5897                 vec_safe_push (params, call);
5898                 vec_safe_push (params, call);
5899                 return altivec_resolve_overloaded_builtin
5900                   (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params);
5901               }
5902               /* Other types are errors.  */
5903             default:
5904               goto bad;
5905             }
5906         }
5907       /* else, fall through and process the Power9 alternative below */
5908     }
5909
5910   if (fcode == ALTIVEC_BUILTIN_VEC_ADDE
5911       || fcode == ALTIVEC_BUILTIN_VEC_SUBE)
5912     {
5913       /* vec_adde needs to be special cased because there is no instruction
5914           for the {un}signed int version.  */
5915       if (nargs != 3)
5916         {
5917           const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDE ?
5918             "vec_adde": "vec_sube";
5919           error ("%s only accepts 3 arguments", name);
5920           return error_mark_node;
5921         }
5922
5923       tree arg0 = (*arglist)[0];
5924       tree arg0_type = TREE_TYPE (arg0);
5925       tree arg1 = (*arglist)[1];
5926       tree arg1_type = TREE_TYPE (arg1);
5927       tree arg2 = (*arglist)[2];
5928       tree arg2_type = TREE_TYPE (arg2);
5929
5930       /* All 3 arguments must be vectors of (signed or unsigned) (int or
5931          __int128) and the types must be compatible.  */
5932       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5933         goto bad;
5934       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type) ||
5935           !lang_hooks.types_compatible_p (arg1_type, arg2_type))
5936         goto bad;
5937
5938       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5939         {
5940           /* For {un}signed ints,
5941              vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb),
5942                                                    vec_and (carryv, 1)).
5943              vec_sube (va, vb, carryv) == vec_sub (vec_sub (va, vb),
5944                                                    vec_and (carryv, 1)).  */
5945           case SImode:
5946             {
5947               tree add_sub_builtin;
5948
5949               vec<tree, va_gc> *params = make_tree_vector ();
5950               vec_safe_push (params, arg0);
5951               vec_safe_push (params, arg1);
5952
5953               if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
5954                 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
5955               else
5956                 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
5957
5958               tree call = altivec_resolve_overloaded_builtin (loc,
5959                                                               add_sub_builtin,
5960                                                               params);
5961               tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
5962               tree ones_vector = build_vector_from_val (arg0_type, const1);
5963               tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
5964                                                arg2, ones_vector);
5965               params = make_tree_vector ();
5966               vec_safe_push (params, call);
5967               vec_safe_push (params, and_expr);
5968               return altivec_resolve_overloaded_builtin (loc, add_sub_builtin,
5969                                                          params);
5970             }
5971           /* For {un}signed __int128s use the vaddeuqm instruction
5972                 directly.  */
5973           case TImode:
5974             {
5975                tree bii;
5976
5977                if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
5978                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM];
5979
5980                else
5981                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBEUQM];
5982
5983                return altivec_resolve_overloaded_builtin (loc, bii, arglist);
5984             }
5985
5986           /* Types other than {un}signed int and {un}signed __int128
5987                 are errors.  */
5988           default:
5989             goto bad;
5990         }
5991     }
5992
5993   if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC
5994       || fcode == ALTIVEC_BUILTIN_VEC_SUBEC)
5995     {
5996       /* vec_addec and vec_subec needs to be special cased because there is
5997          no instruction for the {un}signed int version.  */
5998       if (nargs != 3)
5999         {
6000           const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDEC ?
6001             "vec_addec": "vec_subec";
6002           error ("%s only accepts 3 arguments", name);
6003           return error_mark_node;
6004         }
6005
6006       tree arg0 = (*arglist)[0];
6007       tree arg0_type = TREE_TYPE (arg0);
6008       tree arg1 = (*arglist)[1];
6009       tree arg1_type = TREE_TYPE (arg1);
6010       tree arg2 = (*arglist)[2];
6011       tree arg2_type = TREE_TYPE (arg2);
6012
6013       /* All 3 arguments must be vectors of (signed or unsigned) (int or
6014          __int128) and the types must be compatible.  */
6015       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6016         goto bad;
6017       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type) ||
6018           !lang_hooks.types_compatible_p (arg1_type, arg2_type))
6019         goto bad;
6020
6021       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6022         {
6023           /* For {un}signed ints,
6024               vec_addec (va, vb, carryv) ==
6025                                 vec_or (vec_addc (va, vb),
6026                                         vec_addc (vec_add (va, vb),
6027                                                   vec_and (carryv, 0x1))).  */
6028           case SImode:
6029             {
6030             /* Use save_expr to ensure that operands used more than once
6031                 that may have side effects (like calls) are only evaluated
6032                 once.  */
6033             tree as_builtin;
6034             tree as_c_builtin;
6035
6036             arg0 = save_expr (arg0);
6037             arg1 = save_expr (arg1);
6038             vec<tree, va_gc> *params = make_tree_vector ();
6039             vec_safe_push (params, arg0);
6040             vec_safe_push (params, arg1);
6041
6042             if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6043               as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADDC];
6044             else
6045               as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUBC];
6046
6047             tree call1 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
6048                                                              params);
6049             params = make_tree_vector ();
6050             vec_safe_push (params, arg0);
6051             vec_safe_push (params, arg1);
6052
6053
6054             if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6055               as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
6056             else
6057               as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
6058
6059             tree call2 = altivec_resolve_overloaded_builtin (loc, as_builtin,
6060                                                              params);
6061             tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
6062             tree ones_vector = build_vector_from_val (arg0_type, const1);
6063             tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
6064                                              arg2, ones_vector);
6065             params = make_tree_vector ();
6066             vec_safe_push (params, call2);
6067             vec_safe_push (params, and_expr);
6068             call2 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
6069                                                         params);
6070             params = make_tree_vector ();
6071             vec_safe_push (params, call1);
6072             vec_safe_push (params, call2);
6073             tree or_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_OR];
6074             return altivec_resolve_overloaded_builtin (loc, or_builtin,
6075                                                        params);
6076             }
6077           /* For {un}signed __int128s use the vaddecuq/vsubbecuq
6078              instructions.  */
6079           case TImode:
6080             {
6081                tree bii;
6082
6083                if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6084                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ];
6085
6086                else
6087                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBECUQ];
6088
6089                return altivec_resolve_overloaded_builtin (loc, bii, arglist);
6090             }
6091           /* Types other than {un}signed int and {un}signed __int128
6092                 are errors.  */
6093           default:
6094             goto bad;
6095         }
6096     }
6097
6098   /* For now treat vec_splats and vec_promote as the same.  */
6099   if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS
6100       || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)
6101     {
6102       tree type, arg;
6103       int size;
6104       int i;
6105       bool unsigned_p;
6106       vec<constructor_elt, va_gc> *vec;
6107       const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote";
6108
6109       if (nargs == 0)
6110         {
6111           error ("%s only accepts %d arguments", name, (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)+1 );
6112           return error_mark_node;
6113         }
6114       if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1)
6115         {
6116           error ("%s only accepts 1 argument", name);
6117           return error_mark_node;
6118         }
6119       if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2)
6120         {
6121           error ("%s only accepts 2 arguments", name);
6122           return error_mark_node;
6123         }
6124       /* Ignore promote's element argument.  */
6125       if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE
6126           && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1])))
6127         goto bad;
6128
6129       arg = (*arglist)[0];
6130       type = TREE_TYPE (arg);
6131       if (!SCALAR_FLOAT_TYPE_P (type)
6132           && !INTEGRAL_TYPE_P (type))
6133         goto bad;
6134       unsigned_p = TYPE_UNSIGNED (type);
6135       switch (TYPE_MODE (type))
6136         {
6137           case TImode:
6138             type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
6139             size = 1;
6140             break;
6141           case DImode:
6142             type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
6143             size = 2;
6144             break;
6145           case SImode:
6146             type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
6147             size = 4;
6148             break;
6149           case HImode:
6150             type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
6151             size = 8;
6152             break;
6153           case QImode:
6154             type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
6155             size = 16;
6156             break;
6157           case SFmode: type = V4SF_type_node; size = 4; break;
6158           case DFmode: type = V2DF_type_node; size = 2; break;
6159           default:
6160             goto bad;
6161         }
6162       arg = save_expr (fold_convert (TREE_TYPE (type), arg));
6163       vec_alloc (vec, size);
6164       for(i = 0; i < size; i++)
6165         {
6166           constructor_elt elt = {NULL_TREE, arg};
6167           vec->quick_push (elt);
6168         }
6169         return build_constructor (type, vec);
6170     }
6171
6172   /* For now use pointer tricks to do the extraction, unless we are on VSX
6173      extracting a double from a constant offset.  */
6174   if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)
6175     {
6176       tree arg1;
6177       tree arg1_type;
6178       tree arg2;
6179       tree arg1_inner_type;
6180       tree decl, stmt;
6181       tree innerptrtype;
6182       machine_mode mode;
6183
6184       /* No second argument. */
6185       if (nargs != 2)
6186         {
6187           error ("vec_extract only accepts 2 arguments");
6188           return error_mark_node;
6189         }
6190
6191       arg2 = (*arglist)[1];
6192       arg1 = (*arglist)[0];
6193       arg1_type = TREE_TYPE (arg1);
6194
6195       if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6196         goto bad;
6197       if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6198         goto bad;
6199
6200       /* If we are targeting little-endian, but -maltivec=be has been
6201          specified to override the element order, adjust the element
6202          number accordingly.  */
6203       if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6204         {
6205           unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6206           arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6207                                   build_int_cstu (TREE_TYPE (arg2), last_elem),
6208                                   arg2);
6209         }
6210
6211       /* See if we can optimize vec_extracts with the current VSX instruction
6212          set.  */
6213       mode = TYPE_MODE (arg1_type);
6214       if (VECTOR_MEM_VSX_P (mode))
6215
6216         {
6217           tree call = NULL_TREE;
6218           int nunits = GET_MODE_NUNITS (mode);
6219
6220           /* If the second argument is an integer constant, if the value is in
6221              the expected range, generate the built-in code if we can.  We need
6222              64-bit and direct move to extract the small integer vectors.  */
6223           if (TREE_CODE (arg2) == INTEGER_CST && wi::ltu_p (arg2, nunits))
6224             {
6225               switch (mode)
6226                 {
6227                 default:
6228                   break;
6229
6230                 case V1TImode:
6231                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
6232                   break;
6233
6234                 case V2DFmode:
6235                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6236                   break;
6237
6238                 case V2DImode:
6239                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6240                   break;
6241
6242                 case V4SFmode:
6243                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6244                   break;
6245
6246                 case V4SImode:
6247                   if (TARGET_DIRECT_MOVE_64BIT)
6248                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6249                   break;
6250
6251                 case V8HImode:
6252                   if (TARGET_DIRECT_MOVE_64BIT)
6253                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6254                   break;
6255
6256                 case V16QImode:
6257                   if (TARGET_DIRECT_MOVE_64BIT)
6258                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6259                   break;
6260                 }
6261             }
6262
6263           /* If the second argument is variable, we can optimize it if we are
6264              generating 64-bit code on a machine with direct move.  */
6265           else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT)
6266             {
6267               switch (mode)
6268                 {
6269                 default:
6270                   break;
6271
6272                 case V2DFmode:
6273                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6274                   break;
6275
6276                 case V2DImode:
6277                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6278                   break;
6279
6280                 case V4SFmode:
6281                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6282                   break;
6283
6284                 case V4SImode:
6285                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6286                   break;
6287
6288                 case V8HImode:
6289                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6290                   break;
6291
6292                 case V16QImode:
6293                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6294                   break;
6295                 }
6296             }
6297
6298           if (call)
6299             return build_call_expr (call, 2, arg1, arg2);
6300         }
6301
6302       /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */
6303       arg1_inner_type = TREE_TYPE (arg1_type);
6304       arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6305                               build_int_cst (TREE_TYPE (arg2),
6306                                              TYPE_VECTOR_SUBPARTS (arg1_type)
6307                                              - 1), 0);
6308       decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6309       DECL_EXTERNAL (decl) = 0;
6310       TREE_PUBLIC (decl) = 0;
6311       DECL_CONTEXT (decl) = current_function_decl;
6312       TREE_USED (decl) = 1;
6313       TREE_TYPE (decl) = arg1_type;
6314       TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6315       if (c_dialect_cxx ())
6316         {
6317           stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6318                          NULL_TREE, NULL_TREE);
6319           SET_EXPR_LOCATION (stmt, loc);
6320         }
6321       else
6322         {
6323           DECL_INITIAL (decl) = arg1;
6324           stmt = build1 (DECL_EXPR, arg1_type, decl);
6325           TREE_ADDRESSABLE (decl) = 1;
6326           SET_EXPR_LOCATION (stmt, loc);
6327           stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6328         }
6329
6330       innerptrtype = build_pointer_type (arg1_inner_type);
6331
6332       stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6333       stmt = convert (innerptrtype, stmt);
6334       stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6335       stmt = build_indirect_ref (loc, stmt, RO_NULL);
6336
6337       return stmt;
6338     }
6339
6340   /* For now use pointer tricks to do the insertion, unless we are on VSX
6341      inserting a double to a constant offset..  */
6342   if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)
6343     {
6344       tree arg0;
6345       tree arg1;
6346       tree arg2;
6347       tree arg1_type;
6348       tree arg1_inner_type;
6349       tree decl, stmt;
6350       tree innerptrtype;
6351       machine_mode mode;
6352
6353       /* No second or third arguments. */
6354       if (nargs != 3)
6355         {
6356           error ("vec_insert only accepts 3 arguments");
6357           return error_mark_node;
6358         }
6359
6360       arg0 = (*arglist)[0];
6361       arg1 = (*arglist)[1];
6362       arg1_type = TREE_TYPE (arg1);
6363       arg2 = (*arglist)[2];
6364
6365       if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6366         goto bad;
6367       if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6368         goto bad;
6369
6370       /* If we are targeting little-endian, but -maltivec=be has been
6371          specified to override the element order, adjust the element
6372          number accordingly.  */
6373       if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6374         {
6375           unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6376           arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6377                                   build_int_cstu (TREE_TYPE (arg2), last_elem),
6378                                   arg2);
6379         }
6380
6381       /* If we can use the VSX xxpermdi instruction, use that for insert.  */
6382       mode = TYPE_MODE (arg1_type);
6383       if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)
6384           && TREE_CODE (arg2) == INTEGER_CST
6385           && wi::ltu_p (arg2, 2))
6386         {
6387           tree call = NULL_TREE;
6388
6389           if (mode == V2DFmode)
6390             call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF];
6391           else if (mode == V2DImode)
6392             call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI];
6393
6394           /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6395              reversed.  */
6396           if (call)
6397             return build_call_expr (call, 3, arg1, arg0, arg2);
6398         }
6399       else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)
6400                && TREE_CODE (arg2) == INTEGER_CST
6401                && wi::eq_p (arg2, 0))
6402         {
6403           tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];
6404
6405           /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6406              reversed.  */
6407           return build_call_expr (call, 3, arg1, arg0, arg2);
6408         }
6409
6410       /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */
6411       arg1_inner_type = TREE_TYPE (arg1_type);
6412       arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6413                               build_int_cst (TREE_TYPE (arg2),
6414                                              TYPE_VECTOR_SUBPARTS (arg1_type)
6415                                              - 1), 0);
6416       decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6417       DECL_EXTERNAL (decl) = 0;
6418       TREE_PUBLIC (decl) = 0;
6419       DECL_CONTEXT (decl) = current_function_decl;
6420       TREE_USED (decl) = 1;
6421       TREE_TYPE (decl) = arg1_type;
6422       TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6423       if (c_dialect_cxx ())
6424         {
6425           stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6426                          NULL_TREE, NULL_TREE);
6427           SET_EXPR_LOCATION (stmt, loc);
6428         }
6429       else
6430         {
6431           DECL_INITIAL (decl) = arg1;
6432           stmt = build1 (DECL_EXPR, arg1_type, decl);
6433           TREE_ADDRESSABLE (decl) = 1;
6434           SET_EXPR_LOCATION (stmt, loc);
6435           stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6436         }
6437
6438       innerptrtype = build_pointer_type (arg1_inner_type);
6439
6440       stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6441       stmt = convert (innerptrtype, stmt);
6442       stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6443       stmt = build_indirect_ref (loc, stmt, RO_NULL);
6444       stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt,
6445                      convert (TREE_TYPE (stmt), arg0));
6446       stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl);
6447       return stmt;
6448     }
6449
6450   /* Expand vec_ld into an expression that masks the address and
6451      performs the load.  We need to expand this early to allow
6452      the best aliasing, as by the time we get into RTL we no longer
6453      are able to honor __restrict__, for example.  We may want to
6454      consider this for all memory access built-ins.
6455
6456      When -maltivec=be is specified, or the wrong number of arguments
6457      is provided, simply punt to existing built-in processing.  */
6458   if (fcode == ALTIVEC_BUILTIN_VEC_LD
6459       && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
6460       && nargs == 2)
6461     {
6462       tree arg0 = (*arglist)[0];
6463       tree arg1 = (*arglist)[1];
6464
6465       /* Strip qualifiers like "const" from the pointer arg.  */
6466       tree arg1_type = TREE_TYPE (arg1);
6467       tree inner_type = TREE_TYPE (arg1_type);
6468       if (TYPE_QUALS (TREE_TYPE (arg1_type)) != 0)
6469         {
6470           arg1_type = build_pointer_type (build_qualified_type (inner_type,
6471                                                                 0));
6472           arg1 = fold_convert (arg1_type, arg1);
6473         }
6474
6475       /* Construct the masked address.  Let existing error handling take
6476          over if we don't have a constant offset.  */
6477       arg0 = fold (arg0);
6478
6479       if (TREE_CODE (arg0) == INTEGER_CST)
6480         {
6481           if (!ptrofftype_p (TREE_TYPE (arg0)))
6482             arg0 = build1 (NOP_EXPR, sizetype, arg0);
6483
6484           tree arg1_type = TREE_TYPE (arg1);
6485           if (TREE_CODE (arg1_type) == ARRAY_TYPE)
6486             {
6487               arg1_type = TYPE_POINTER_TO (TREE_TYPE (arg1_type));
6488               tree const0 = build_int_cstu (sizetype, 0);
6489               tree arg1_elt0 = build_array_ref (loc, arg1, const0);
6490               arg1 = build1 (ADDR_EXPR, arg1_type, arg1_elt0);
6491             }
6492
6493           tree addr = fold_build2_loc (loc, POINTER_PLUS_EXPR, arg1_type,
6494                                        arg1, arg0);
6495           tree aligned = fold_build2_loc (loc, BIT_AND_EXPR, arg1_type, addr,
6496                                           build_int_cst (arg1_type, -16));
6497
6498           /* Find the built-in to get the return type so we can convert
6499              the result properly (or fall back to default handling if the
6500              arguments aren't compatible).  */
6501           for (desc = altivec_overloaded_builtins;
6502                desc->code && desc->code != fcode; desc++)
6503             continue;
6504
6505           for (; desc->code == fcode; desc++)
6506             if (rs6000_builtin_type_compatible (TREE_TYPE (arg0), desc->op1)
6507                 && (rs6000_builtin_type_compatible (TREE_TYPE (arg1),
6508                                                     desc->op2)))
6509               {
6510                 tree ret_type = rs6000_builtin_type (desc->ret_type);
6511                 if (TYPE_MODE (ret_type) == V2DImode)
6512                   /* Type-based aliasing analysis thinks vector long
6513                      and vector long long are different and will put them
6514                      in distinct alias classes.  Force our return type
6515                      to be a may-alias type to avoid this.  */
6516                   ret_type
6517                     = build_pointer_type_for_mode (ret_type, Pmode,
6518                                                    true/*can_alias_all*/);
6519                 else
6520                   ret_type = build_pointer_type (ret_type);
6521                 aligned = build1 (NOP_EXPR, ret_type, aligned);
6522                 tree ret_val = build_indirect_ref (loc, aligned, RO_NULL);
6523                 return ret_val;
6524               }
6525         }
6526     }
6527
6528   /* Similarly for stvx.  */
6529   if (fcode == ALTIVEC_BUILTIN_VEC_ST
6530       && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
6531       && nargs == 3)
6532     {
6533       tree arg0 = (*arglist)[0];
6534       tree arg1 = (*arglist)[1];
6535       tree arg2 = (*arglist)[2];
6536
6537       /* Construct the masked address.  Let existing error handling take
6538          over if we don't have a constant offset.  */
6539       arg1 = fold (arg1);
6540
6541       if (TREE_CODE (arg1) == INTEGER_CST)
6542         {
6543           if (!ptrofftype_p (TREE_TYPE (arg1)))
6544             arg1 = build1 (NOP_EXPR, sizetype, arg1);
6545
6546           tree arg2_type = TREE_TYPE (arg2);
6547           if (TREE_CODE (arg2_type) == ARRAY_TYPE)
6548             {
6549               arg2_type = TYPE_POINTER_TO (TREE_TYPE (arg2_type));
6550               tree const0 = build_int_cstu (sizetype, 0);
6551               tree arg2_elt0 = build_array_ref (loc, arg2, const0);
6552               arg2 = build1 (ADDR_EXPR, arg2_type, arg2_elt0);
6553             }
6554
6555           tree addr = fold_build2_loc (loc, POINTER_PLUS_EXPR, arg2_type,
6556                                        arg2, arg1);
6557           tree aligned = fold_build2_loc (loc, BIT_AND_EXPR, arg2_type, addr,
6558                                           build_int_cst (arg2_type, -16));
6559
6560           /* Find the built-in to make sure a compatible one exists; if not
6561              we fall back to default handling to get the error message.  */
6562           for (desc = altivec_overloaded_builtins;
6563                desc->code && desc->code != fcode; desc++)
6564             continue;
6565
6566           for (; desc->code == fcode; desc++)
6567             if (rs6000_builtin_type_compatible (TREE_TYPE (arg0), desc->op1)
6568                 && rs6000_builtin_type_compatible (TREE_TYPE (arg1), desc->op2)
6569                 && rs6000_builtin_type_compatible (TREE_TYPE (arg2),
6570                                                    desc->op3))
6571               {
6572                 tree arg0_type = TREE_TYPE (arg0);
6573                 if (TYPE_MODE (arg0_type) == V2DImode)
6574                   /* Type-based aliasing analysis thinks vector long
6575                      and vector long long are different and will put them
6576                      in distinct alias classes.  Force our address type
6577                      to be a may-alias type to avoid this.  */
6578                   arg0_type
6579                     = build_pointer_type_for_mode (arg0_type, Pmode,
6580                                                    true/*can_alias_all*/);
6581                 else
6582                   arg0_type = build_pointer_type (arg0_type);
6583                 aligned = build1 (NOP_EXPR, arg0_type, aligned);
6584                 tree stg = build_indirect_ref (loc, aligned, RO_NULL);
6585                 tree retval = build2 (MODIFY_EXPR, TREE_TYPE (stg), stg,
6586                                       convert (TREE_TYPE (stg), arg0));
6587                 return retval;
6588               }
6589         }
6590     }
6591
6592   for (n = 0;
6593        !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs;
6594        fnargs = TREE_CHAIN (fnargs), n++)
6595     {
6596       tree decl_type = TREE_VALUE (fnargs);
6597       tree arg = (*arglist)[n];
6598       tree type;
6599
6600       if (arg == error_mark_node)
6601         return error_mark_node;
6602
6603       if (n >= 3)
6604         abort ();
6605
6606       arg = default_conversion (arg);
6607
6608       /* The C++ front-end converts float * to const void * using
6609          NOP_EXPR<const void *> (NOP_EXPR<void *> (x)).  */
6610       type = TREE_TYPE (arg);
6611       if (POINTER_TYPE_P (type)
6612           && TREE_CODE (arg) == NOP_EXPR
6613           && lang_hooks.types_compatible_p (TREE_TYPE (arg),
6614                                             const_ptr_type_node)
6615           && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)),
6616                                             ptr_type_node))
6617         {
6618           arg = TREE_OPERAND (arg, 0);
6619           type = TREE_TYPE (arg);
6620         }
6621
6622       /* Remove the const from the pointers to simplify the overload
6623          matching further down.  */
6624       if (POINTER_TYPE_P (decl_type)
6625           && POINTER_TYPE_P (type)
6626           && TYPE_QUALS (TREE_TYPE (type)) != 0)
6627         {
6628           if (TYPE_READONLY (TREE_TYPE (type))
6629               && !TYPE_READONLY (TREE_TYPE (decl_type)))
6630             warning (0, "passing arg %d of %qE discards qualifiers from "
6631                         "pointer target type", n + 1, fndecl);
6632           type = build_pointer_type (build_qualified_type (TREE_TYPE (type),
6633                                                            0));
6634           arg = fold_convert (type, arg);
6635         }
6636
6637       args[n] = arg;
6638       types[n] = type;
6639     }
6640
6641   /* If the number of arguments did not match the prototype, return NULL
6642      and the generic code will issue the appropriate error message.  */
6643   if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs)
6644     return NULL;
6645
6646   if (n == 0)
6647     abort ();
6648
6649   if (fcode == ALTIVEC_BUILTIN_VEC_STEP)
6650     {
6651       if (TREE_CODE (types[0]) != VECTOR_TYPE)
6652         goto bad;
6653
6654       return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0]));
6655     }
6656
6657   {
6658     bool unsupported_builtin = false;
6659     for (desc = altivec_overloaded_builtins;
6660          desc->code && desc->code != fcode; desc++)
6661       continue;
6662
6663     /* Need to special case __builtin_cmp because the overloaded forms
6664        of this function take (unsigned int, unsigned int) or (unsigned
6665        long long int, unsigned long long int).  Since C conventions
6666        allow the respective argument types to be implicitly coerced into
6667        each other, the default handling does not provide adequate
6668        discrimination between the desired forms of the function.  */
6669     if (fcode == P6_OV_BUILTIN_CMPB)
6670       {
6671         int overloaded_code;
6672         machine_mode arg1_mode = TYPE_MODE (types[0]);
6673         machine_mode arg2_mode = TYPE_MODE (types[1]);
6674
6675         if (nargs != 2)
6676           {
6677             error ("__builtin_cmpb only accepts 2 arguments");
6678             return error_mark_node;
6679           }
6680
6681         /* If any supplied arguments are wider than 32 bits, resolve to
6682            64-bit variant of built-in function.  */
6683         if ((GET_MODE_PRECISION (arg1_mode) > 32)
6684             || (GET_MODE_PRECISION (arg2_mode) > 32))
6685           {
6686             /* Assure all argument and result types are compatible with
6687                the built-in function represented by P6_BUILTIN_CMPB.  */
6688             overloaded_code = P6_BUILTIN_CMPB;
6689           }
6690         else
6691           {
6692             /* Assure all argument and result types are compatible with
6693                the built-in function represented by P6_BUILTIN_CMPB_32.  */
6694             overloaded_code = P6_BUILTIN_CMPB_32;
6695           }
6696
6697         while (desc->code && desc->code == fcode &&
6698                desc->overloaded_code != overloaded_code)
6699           desc++;
6700
6701         if (desc->code && (desc->code == fcode)
6702             && rs6000_builtin_type_compatible (types[0], desc->op1)
6703             && rs6000_builtin_type_compatible (types[1], desc->op2))
6704           {
6705             if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6706               return altivec_build_resolved_builtin (args, n, desc);
6707             else
6708               unsupported_builtin = true;
6709           }
6710       }
6711     else if (fcode == P9V_BUILTIN_VEC_VSIEDP)
6712       {
6713         int overloaded_code;
6714         int arg1_mode = TYPE_MODE (types[0]);
6715
6716         if (nargs != 2)
6717           {
6718             error ("scalar_insert_exp only accepts 2 arguments");
6719             return error_mark_node;
6720           }
6721
6722         /* If supplied first argument is wider than 64 bits, resolve to
6723            128-bit variant of built-in function.  */
6724         if (GET_MODE_PRECISION (arg1_mode) > 64)
6725           {
6726             /* If first argument is of float variety, choose variant
6727                that expects __ieee128 argument.  Otherwise, expect
6728                __int128 argument.  */
6729             if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
6730               overloaded_code = P9V_BUILTIN_VSIEQPF;
6731             else
6732               overloaded_code = P9V_BUILTIN_VSIEQP;
6733           }
6734         else
6735           {
6736             /* If first argument is of float variety, choose variant
6737                that expects double argument.  Otherwise, expect
6738                long long int argument.  */
6739             if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
6740               overloaded_code = P9V_BUILTIN_VSIEDPF;
6741             else
6742               overloaded_code = P9V_BUILTIN_VSIEDP;
6743           }
6744         while (desc->code && desc->code == fcode &&
6745                desc->overloaded_code != overloaded_code)
6746           desc++;
6747         if (desc->code && (desc->code == fcode)
6748             && rs6000_builtin_type_compatible (types[0], desc->op1)
6749             && rs6000_builtin_type_compatible (types[1], desc->op2))
6750           {
6751             if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6752               return altivec_build_resolved_builtin (args, n, desc);
6753             else
6754               unsupported_builtin = true;
6755           }
6756       }
6757     else
6758       {
6759         /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in
6760            the opX fields.  */
6761         for (; desc->code == fcode; desc++)
6762           {
6763             if ((desc->op1 == RS6000_BTI_NOT_OPAQUE
6764                  || rs6000_builtin_type_compatible (types[0], desc->op1))
6765                 && (desc->op2 == RS6000_BTI_NOT_OPAQUE
6766                     || rs6000_builtin_type_compatible (types[1], desc->op2))
6767                 && (desc->op3 == RS6000_BTI_NOT_OPAQUE
6768                     || rs6000_builtin_type_compatible (types[2], desc->op3)))
6769               {
6770                 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6771                   return altivec_build_resolved_builtin (args, n, desc);
6772                 else
6773                   unsupported_builtin = true;
6774               }
6775           }
6776       }
6777
6778     if (unsupported_builtin)
6779       {
6780         const char *name = rs6000_overloaded_builtin_name (fcode);
6781         error ("Builtin function %s not supported in this compiler configuration",
6782                name);
6783         return error_mark_node;
6784       }
6785   }
6786  bad:
6787     {
6788       const char *name = rs6000_overloaded_builtin_name (fcode);
6789       error ("invalid parameter combination for AltiVec intrinsic %s", name);
6790       return error_mark_node;
6791     }
6792 }