| blob | d8332e3457084eb25c75c78666d692da9ee387a9 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 ;; MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; UNSPEC usage
27 ;;
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
54 (UNSPEC_STFIWX 32)
55 (UNSPEC_POPCNTB 33)
56 (UNSPEC_FRES 34)
57 (UNSPEC_SP_SET 35)
58 (UNSPEC_SP_TEST 36)
59 (UNSPEC_SYNC 37)
60 (UNSPEC_LWSYNC 38)
61 (UNSPEC_ISYNC 39)
62 (UNSPEC_SYNC_OP 40)
63 (UNSPEC_ATOMIC 41)
64 (UNSPEC_CMPXCHG 42)
65 (UNSPEC_XCHG 43)
66 (UNSPEC_AND 44)
67 ])
69 ;;
70 ;; UNSPEC_VOLATILE usage
71 ;;
73 (define_constants
74 [(UNSPECV_BLOCK 0)
75 (UNSPECV_LL 1) ; load-locked
76 (UNSPECV_SC 2) ; store-conditional
77 (UNSPECV_EH_RR 9) ; eh_reg_restore
78 ])
79 \f
80 ;; Define an insn type attribute. This is used in function unit delay
81 ;; computations.
82 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
83 (const_string "integer"))
85 ;; Length (in bytes).
86 ; '(pc)' in the following doesn't include the instruction itself; it is
87 ; calculated as if the instruction had zero size.
88 (define_attr "length" ""
89 (if_then_else (eq_attr "type" "branch")
90 (if_then_else (and (ge (minus (match_dup 0) (pc))
91 (const_int -32768))
92 (lt (minus (match_dup 0) (pc))
93 (const_int 32764)))
94 (const_int 4)
95 (const_int 8))
96 (const_int 4)))
98 ;; Processor type -- this attribute must exactly match the processor_type
99 ;; enumeration in rs6000.h.
101 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
102 (const (symbol_ref "rs6000_cpu_attr")))
104 (automata_option "ndfa")
106 (include "rios1.md")
107 (include "rios2.md")
108 (include "rs64.md")
109 (include "mpc.md")
110 (include "40x.md")
111 (include "440.md")
112 (include "603.md")
113 (include "6xx.md")
114 (include "7xx.md")
115 (include "7450.md")
116 (include "8540.md")
117 (include "power4.md")
118 (include "power5.md")
120 (include "predicates.md")
122 (include "darwin.md")
124 \f
125 ;; Mode macros
127 ; This mode macro allows :GPR to be used to indicate the allowable size
128 ; of whole values in GPRs.
129 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
131 ; Any supported integer mode.
132 (define_mode_macro INT [QI HI SI DI TI])
134 ; Any supported integer mode that fits in one register.
135 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
137 ; extend modes for DImode
138 (define_mode_macro QHSI [QI HI SI])
140 ; SImode or DImode, even if DImode doesn't fit in GPRs.
141 (define_mode_macro SDI [SI DI])
143 ; The size of a pointer. Also, the size of the value that a record-condition
144 ; (one with a '.') will compare.
145 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
147 ; Any hardware-supported floating-point mode
148 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
149 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
150 (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
151 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
153 ; Various instructions that come in SI and DI forms.
154 ; A generic w/d attribute, for things like cmpw/cmpd.
155 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
157 ; DImode bits
158 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
160 \f
161 ;; Start with fixed-point load and store insns. Here we put only the more
162 ;; complex forms. Basic data transfer is done later.
164 (define_expand "zero_extend<mode>di2"
165 [(set (match_operand:DI 0 "gpc_reg_operand" "")
166 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
167 "TARGET_POWERPC64"
168 "")
170 (define_insn "*zero_extend<mode>di2_internal1"
171 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
172 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
173 "TARGET_POWERPC64"
174 "@
175 l<wd>z%U1%X1 %0,%1
176 rldicl %0,%1,0,<dbits>"
177 [(set_attr "type" "load,*")])
179 (define_insn "*zero_extend<mode>di2_internal2"
180 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
181 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
182 (const_int 0)))
183 (clobber (match_scratch:DI 2 "=r,r"))]
184 "TARGET_64BIT"
185 "@
186 rldicl. %2,%1,0,<dbits>
187 #"
188 [(set_attr "type" "compare")
189 (set_attr "length" "4,8")])
191 (define_split
192 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
193 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
194 (const_int 0)))
195 (clobber (match_scratch:DI 2 ""))]
196 "TARGET_POWERPC64 && reload_completed"
197 [(set (match_dup 2)
198 (zero_extend:DI (match_dup 1)))
199 (set (match_dup 0)
200 (compare:CC (match_dup 2)
201 (const_int 0)))]
202 "")
204 (define_insn "*zero_extend<mode>di2_internal3"
205 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
206 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
207 (const_int 0)))
208 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
209 (zero_extend:DI (match_dup 1)))]
210 "TARGET_64BIT"
211 "@
212 rldicl. %0,%1,0,<dbits>
213 #"
214 [(set_attr "type" "compare")
215 (set_attr "length" "4,8")])
217 (define_split
218 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
219 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
220 (const_int 0)))
221 (set (match_operand:DI 0 "gpc_reg_operand" "")
222 (zero_extend:DI (match_dup 1)))]
223 "TARGET_POWERPC64 && reload_completed"
224 [(set (match_dup 0)
225 (zero_extend:DI (match_dup 1)))
226 (set (match_dup 2)
227 (compare:CC (match_dup 0)
228 (const_int 0)))]
229 "")
231 (define_insn "extendqidi2"
232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
233 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
234 "TARGET_POWERPC64"
235 "extsb %0,%1")
237 (define_insn ""
238 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
239 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
240 (const_int 0)))
241 (clobber (match_scratch:DI 2 "=r,r"))]
242 "TARGET_64BIT"
243 "@
244 extsb. %2,%1
245 #"
246 [(set_attr "type" "compare")
247 (set_attr "length" "4,8")])
249 (define_split
250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
251 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
252 (const_int 0)))
253 (clobber (match_scratch:DI 2 ""))]
254 "TARGET_POWERPC64 && reload_completed"
255 [(set (match_dup 2)
256 (sign_extend:DI (match_dup 1)))
257 (set (match_dup 0)
258 (compare:CC (match_dup 2)
259 (const_int 0)))]
260 "")
262 (define_insn ""
263 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
264 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
265 (const_int 0)))
266 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
267 (sign_extend:DI (match_dup 1)))]
268 "TARGET_64BIT"
269 "@
270 extsb. %0,%1
271 #"
272 [(set_attr "type" "compare")
273 (set_attr "length" "4,8")])
275 (define_split
276 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
277 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
278 (const_int 0)))
279 (set (match_operand:DI 0 "gpc_reg_operand" "")
280 (sign_extend:DI (match_dup 1)))]
281 "TARGET_POWERPC64 && reload_completed"
282 [(set (match_dup 0)
283 (sign_extend:DI (match_dup 1)))
284 (set (match_dup 2)
285 (compare:CC (match_dup 0)
286 (const_int 0)))]
287 "")
289 (define_expand "extendhidi2"
290 [(set (match_operand:DI 0 "gpc_reg_operand" "")
291 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
292 "TARGET_POWERPC64"
293 "")
295 (define_insn ""
296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
297 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
298 "TARGET_POWERPC64"
299 "@
300 lha%U1%X1 %0,%1
301 extsh %0,%1"
302 [(set_attr "type" "load_ext,*")])
304 (define_insn ""
305 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
306 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
307 (const_int 0)))
308 (clobber (match_scratch:DI 2 "=r,r"))]
309 "TARGET_64BIT"
310 "@
311 extsh. %2,%1
312 #"
313 [(set_attr "type" "compare")
314 (set_attr "length" "4,8")])
316 (define_split
317 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
318 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
319 (const_int 0)))
320 (clobber (match_scratch:DI 2 ""))]
321 "TARGET_POWERPC64 && reload_completed"
322 [(set (match_dup 2)
323 (sign_extend:DI (match_dup 1)))
324 (set (match_dup 0)
325 (compare:CC (match_dup 2)
326 (const_int 0)))]
327 "")
329 (define_insn ""
330 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
331 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
332 (const_int 0)))
333 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
334 (sign_extend:DI (match_dup 1)))]
335 "TARGET_64BIT"
336 "@
337 extsh. %0,%1
338 #"
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
342 (define_split
343 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
344 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
345 (const_int 0)))
346 (set (match_operand:DI 0 "gpc_reg_operand" "")
347 (sign_extend:DI (match_dup 1)))]
348 "TARGET_POWERPC64 && reload_completed"
349 [(set (match_dup 0)
350 (sign_extend:DI (match_dup 1)))
351 (set (match_dup 2)
352 (compare:CC (match_dup 0)
353 (const_int 0)))]
354 "")
356 (define_expand "extendsidi2"
357 [(set (match_operand:DI 0 "gpc_reg_operand" "")
358 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
359 "TARGET_POWERPC64"
360 "")
362 (define_insn ""
363 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
364 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
365 "TARGET_POWERPC64"
366 "@
367 lwa%U1%X1 %0,%1
368 extsw %0,%1"
369 [(set_attr "type" "load_ext,*")])
371 (define_insn ""
372 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
373 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
374 (const_int 0)))
375 (clobber (match_scratch:DI 2 "=r,r"))]
376 "TARGET_64BIT"
377 "@
378 extsw. %2,%1
379 #"
380 [(set_attr "type" "compare")
381 (set_attr "length" "4,8")])
383 (define_split
384 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
385 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
386 (const_int 0)))
387 (clobber (match_scratch:DI 2 ""))]
388 "TARGET_POWERPC64 && reload_completed"
389 [(set (match_dup 2)
390 (sign_extend:DI (match_dup 1)))
391 (set (match_dup 0)
392 (compare:CC (match_dup 2)
393 (const_int 0)))]
394 "")
396 (define_insn ""
397 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
398 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
399 (const_int 0)))
400 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
401 (sign_extend:DI (match_dup 1)))]
402 "TARGET_64BIT"
403 "@
404 extsw. %0,%1
405 #"
406 [(set_attr "type" "compare")
407 (set_attr "length" "4,8")])
409 (define_split
410 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
411 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
412 (const_int 0)))
413 (set (match_operand:DI 0 "gpc_reg_operand" "")
414 (sign_extend:DI (match_dup 1)))]
415 "TARGET_POWERPC64 && reload_completed"
416 [(set (match_dup 0)
417 (sign_extend:DI (match_dup 1)))
418 (set (match_dup 2)
419 (compare:CC (match_dup 0)
420 (const_int 0)))]
421 "")
423 (define_expand "zero_extendqisi2"
424 [(set (match_operand:SI 0 "gpc_reg_operand" "")
425 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
426 ""
427 "")
429 (define_insn ""
430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
431 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
432 ""
433 "@
434 lbz%U1%X1 %0,%1
435 {rlinm|rlwinm} %0,%1,0,0xff"
436 [(set_attr "type" "load,*")])
438 (define_insn ""
439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
440 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
441 (const_int 0)))
442 (clobber (match_scratch:SI 2 "=r,r"))]
443 ""
444 "@
445 {andil.|andi.} %2,%1,0xff
446 #"
447 [(set_attr "type" "compare")
448 (set_attr "length" "4,8")])
450 (define_split
451 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
452 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
453 (const_int 0)))
454 (clobber (match_scratch:SI 2 ""))]
455 "reload_completed"
456 [(set (match_dup 2)
457 (zero_extend:SI (match_dup 1)))
458 (set (match_dup 0)
459 (compare:CC (match_dup 2)
460 (const_int 0)))]
461 "")
463 (define_insn ""
464 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
465 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
466 (const_int 0)))
467 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
468 (zero_extend:SI (match_dup 1)))]
469 ""
470 "@
471 {andil.|andi.} %0,%1,0xff
472 #"
473 [(set_attr "type" "compare")
474 (set_attr "length" "4,8")])
476 (define_split
477 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
478 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
479 (const_int 0)))
480 (set (match_operand:SI 0 "gpc_reg_operand" "")
481 (zero_extend:SI (match_dup 1)))]
482 "reload_completed"
483 [(set (match_dup 0)
484 (zero_extend:SI (match_dup 1)))
485 (set (match_dup 2)
486 (compare:CC (match_dup 0)
487 (const_int 0)))]
488 "")
490 (define_expand "extendqisi2"
491 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
492 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
493 ""
494 "
495 {
496 if (TARGET_POWERPC)
497 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
498 else if (TARGET_POWER)
499 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
500 else
501 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
502 DONE;
503 }")
505 (define_insn "extendqisi2_ppc"
506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
507 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
508 "TARGET_POWERPC"
509 "extsb %0,%1")
511 (define_insn ""
512 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
513 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
514 (const_int 0)))
515 (clobber (match_scratch:SI 2 "=r,r"))]
516 "TARGET_POWERPC"
517 "@
518 extsb. %2,%1
519 #"
520 [(set_attr "type" "compare")
521 (set_attr "length" "4,8")])
523 (define_split
524 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
525 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
526 (const_int 0)))
527 (clobber (match_scratch:SI 2 ""))]
528 "TARGET_POWERPC && reload_completed"
529 [(set (match_dup 2)
530 (sign_extend:SI (match_dup 1)))
531 (set (match_dup 0)
532 (compare:CC (match_dup 2)
533 (const_int 0)))]
534 "")
536 (define_insn ""
537 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
538 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
539 (const_int 0)))
540 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
541 (sign_extend:SI (match_dup 1)))]
542 "TARGET_POWERPC"
543 "@
544 extsb. %0,%1
545 #"
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
549 (define_split
550 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
551 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
552 (const_int 0)))
553 (set (match_operand:SI 0 "gpc_reg_operand" "")
554 (sign_extend:SI (match_dup 1)))]
555 "TARGET_POWERPC && reload_completed"
556 [(set (match_dup 0)
557 (sign_extend:SI (match_dup 1)))
558 (set (match_dup 2)
559 (compare:CC (match_dup 0)
560 (const_int 0)))]
561 "")
563 (define_expand "extendqisi2_power"
564 [(parallel [(set (match_dup 2)
565 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
566 (const_int 24)))
567 (clobber (scratch:SI))])
568 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
569 (ashiftrt:SI (match_dup 2)
570 (const_int 24)))
571 (clobber (scratch:SI))])]
572 "TARGET_POWER"
573 "
574 { operands[1] = gen_lowpart (SImode, operands[1]);
575 operands[2] = gen_reg_rtx (SImode); }")
577 (define_expand "extendqisi2_no_power"
578 [(set (match_dup 2)
579 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
580 (const_int 24)))
581 (set (match_operand:SI 0 "gpc_reg_operand" "")
582 (ashiftrt:SI (match_dup 2)
583 (const_int 24)))]
584 "! TARGET_POWER && ! TARGET_POWERPC"
585 "
586 { operands[1] = gen_lowpart (SImode, operands[1]);
587 operands[2] = gen_reg_rtx (SImode); }")
589 (define_expand "zero_extendqihi2"
590 [(set (match_operand:HI 0 "gpc_reg_operand" "")
591 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
592 ""
593 "")
595 (define_insn ""
596 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
597 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
598 ""
599 "@
600 lbz%U1%X1 %0,%1
601 {rlinm|rlwinm} %0,%1,0,0xff"
602 [(set_attr "type" "load,*")])
604 (define_insn ""
605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
607 (const_int 0)))
608 (clobber (match_scratch:HI 2 "=r,r"))]
609 ""
610 "@
611 {andil.|andi.} %2,%1,0xff
612 #"
613 [(set_attr "type" "compare")
614 (set_attr "length" "4,8")])
616 (define_split
617 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
618 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (clobber (match_scratch:HI 2 ""))]
621 "reload_completed"
622 [(set (match_dup 2)
623 (zero_extend:HI (match_dup 1)))
624 (set (match_dup 0)
625 (compare:CC (match_dup 2)
626 (const_int 0)))]
627 "")
629 (define_insn ""
630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
632 (const_int 0)))
633 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
634 (zero_extend:HI (match_dup 1)))]
635 ""
636 "@
637 {andil.|andi.} %0,%1,0xff
638 #"
639 [(set_attr "type" "compare")
640 (set_attr "length" "4,8")])
642 (define_split
643 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
644 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
645 (const_int 0)))
646 (set (match_operand:HI 0 "gpc_reg_operand" "")
647 (zero_extend:HI (match_dup 1)))]
648 "reload_completed"
649 [(set (match_dup 0)
650 (zero_extend:HI (match_dup 1)))
651 (set (match_dup 2)
652 (compare:CC (match_dup 0)
653 (const_int 0)))]
654 "")
656 (define_expand "extendqihi2"
657 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
658 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
659 ""
660 "
661 {
662 if (TARGET_POWERPC)
663 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
664 else if (TARGET_POWER)
665 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
666 else
667 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
668 DONE;
669 }")
671 (define_insn "extendqihi2_ppc"
672 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
673 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
674 "TARGET_POWERPC"
675 "extsb %0,%1")
677 (define_insn ""
678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
679 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
680 (const_int 0)))
681 (clobber (match_scratch:HI 2 "=r,r"))]
682 "TARGET_POWERPC"
683 "@
684 extsb. %2,%1
685 #"
686 [(set_attr "type" "compare")
687 (set_attr "length" "4,8")])
689 (define_split
690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
691 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
692 (const_int 0)))
693 (clobber (match_scratch:HI 2 ""))]
694 "TARGET_POWERPC && reload_completed"
695 [(set (match_dup 2)
696 (sign_extend:HI (match_dup 1)))
697 (set (match_dup 0)
698 (compare:CC (match_dup 2)
699 (const_int 0)))]
700 "")
702 (define_insn ""
703 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
704 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
705 (const_int 0)))
706 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
707 (sign_extend:HI (match_dup 1)))]
708 "TARGET_POWERPC"
709 "@
710 extsb. %0,%1
711 #"
712 [(set_attr "type" "compare")
713 (set_attr "length" "4,8")])
715 (define_split
716 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
717 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
718 (const_int 0)))
719 (set (match_operand:HI 0 "gpc_reg_operand" "")
720 (sign_extend:HI (match_dup 1)))]
721 "TARGET_POWERPC && reload_completed"
722 [(set (match_dup 0)
723 (sign_extend:HI (match_dup 1)))
724 (set (match_dup 2)
725 (compare:CC (match_dup 0)
726 (const_int 0)))]
727 "")
729 (define_expand "extendqihi2_power"
730 [(parallel [(set (match_dup 2)
731 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
732 (const_int 24)))
733 (clobber (scratch:SI))])
734 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
735 (ashiftrt:SI (match_dup 2)
736 (const_int 24)))
737 (clobber (scratch:SI))])]
738 "TARGET_POWER"
739 "
740 { operands[0] = gen_lowpart (SImode, operands[0]);
741 operands[1] = gen_lowpart (SImode, operands[1]);
742 operands[2] = gen_reg_rtx (SImode); }")
744 (define_expand "extendqihi2_no_power"
745 [(set (match_dup 2)
746 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
747 (const_int 24)))
748 (set (match_operand:HI 0 "gpc_reg_operand" "")
749 (ashiftrt:SI (match_dup 2)
750 (const_int 24)))]
751 "! TARGET_POWER && ! TARGET_POWERPC"
752 "
753 { operands[0] = gen_lowpart (SImode, operands[0]);
754 operands[1] = gen_lowpart (SImode, operands[1]);
755 operands[2] = gen_reg_rtx (SImode); }")
757 (define_expand "zero_extendhisi2"
758 [(set (match_operand:SI 0 "gpc_reg_operand" "")
759 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
760 ""
761 "")
763 (define_insn ""
764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
765 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
766 ""
767 "@
768 lhz%U1%X1 %0,%1
769 {rlinm|rlwinm} %0,%1,0,0xffff"
770 [(set_attr "type" "load,*")])
772 (define_insn ""
773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
774 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
775 (const_int 0)))
776 (clobber (match_scratch:SI 2 "=r,r"))]
777 ""
778 "@
779 {andil.|andi.} %2,%1,0xffff
780 #"
781 [(set_attr "type" "compare")
782 (set_attr "length" "4,8")])
784 (define_split
785 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
786 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
787 (const_int 0)))
788 (clobber (match_scratch:SI 2 ""))]
789 "reload_completed"
790 [(set (match_dup 2)
791 (zero_extend:SI (match_dup 1)))
792 (set (match_dup 0)
793 (compare:CC (match_dup 2)
794 (const_int 0)))]
795 "")
797 (define_insn ""
798 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
799 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
800 (const_int 0)))
801 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
802 (zero_extend:SI (match_dup 1)))]
803 ""
804 "@
805 {andil.|andi.} %0,%1,0xffff
806 #"
807 [(set_attr "type" "compare")
808 (set_attr "length" "4,8")])
810 (define_split
811 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
812 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
813 (const_int 0)))
814 (set (match_operand:SI 0 "gpc_reg_operand" "")
815 (zero_extend:SI (match_dup 1)))]
816 "reload_completed"
817 [(set (match_dup 0)
818 (zero_extend:SI (match_dup 1)))
819 (set (match_dup 2)
820 (compare:CC (match_dup 0)
821 (const_int 0)))]
822 "")
824 (define_expand "extendhisi2"
825 [(set (match_operand:SI 0 "gpc_reg_operand" "")
826 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
827 ""
828 "")
830 (define_insn ""
831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
832 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
833 ""
834 "@
835 lha%U1%X1 %0,%1
836 {exts|extsh} %0,%1"
837 [(set_attr "type" "load_ext,*")])
839 (define_insn ""
840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
841 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
842 (const_int 0)))
843 (clobber (match_scratch:SI 2 "=r,r"))]
844 ""
845 "@
846 {exts.|extsh.} %2,%1
847 #"
848 [(set_attr "type" "compare")
849 (set_attr "length" "4,8")])
851 (define_split
852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
853 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
854 (const_int 0)))
855 (clobber (match_scratch:SI 2 ""))]
856 "reload_completed"
857 [(set (match_dup 2)
858 (sign_extend:SI (match_dup 1)))
859 (set (match_dup 0)
860 (compare:CC (match_dup 2)
861 (const_int 0)))]
862 "")
864 (define_insn ""
865 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
866 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
867 (const_int 0)))
868 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
869 (sign_extend:SI (match_dup 1)))]
870 ""
871 "@
872 {exts.|extsh.} %0,%1
873 #"
874 [(set_attr "type" "compare")
875 (set_attr "length" "4,8")])
876 \f
877 (define_split
878 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
879 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
880 (const_int 0)))
881 (set (match_operand:SI 0 "gpc_reg_operand" "")
882 (sign_extend:SI (match_dup 1)))]
883 "reload_completed"
884 [(set (match_dup 0)
885 (sign_extend:SI (match_dup 1)))
886 (set (match_dup 2)
887 (compare:CC (match_dup 0)
888 (const_int 0)))]
889 "")
891 ;; Fixed-point arithmetic insns.
893 (define_expand "add<mode>3"
894 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
895 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
896 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
897 ""
898 "
899 {
900 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
901 {
902 if (non_short_cint_operand (operands[2], DImode))
903 FAIL;
904 }
905 else if (GET_CODE (operands[2]) == CONST_INT
906 && ! add_operand (operands[2], <MODE>mode))
907 {
908 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
909 ? operands[0] : gen_reg_rtx (<MODE>mode));
911 HOST_WIDE_INT val = INTVAL (operands[2]);
912 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
913 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
915 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
916 FAIL;
918 /* The ordering here is important for the prolog expander.
919 When space is allocated from the stack, adding 'low' first may
920 produce a temporary deallocation (which would be bad). */
921 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
922 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
923 DONE;
924 }
925 }")
927 ;; Discourage ai/addic because of carry but provide it in an alternative
928 ;; allowing register zero as source.
929 (define_insn "*add<mode>3_internal1"
930 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
931 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
932 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
933 ""
934 "@
935 {cax|add} %0,%1,%2
936 {cal %0,%2(%1)|addi %0,%1,%2}
937 {ai|addic} %0,%1,%2
938 {cau|addis} %0,%1,%v2"
939 [(set_attr "length" "4,4,4,4")])
941 (define_insn "addsi3_high"
942 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
943 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
944 (high:SI (match_operand 2 "" ""))))]
945 "TARGET_MACHO && !TARGET_64BIT"
946 "{cau|addis} %0,%1,ha16(%2)"
947 [(set_attr "length" "4")])
949 (define_insn "*add<mode>3_internal2"
950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
951 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
952 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
953 (const_int 0)))
954 (clobber (match_scratch:P 3 "=r,r,r,r"))]
955 ""
956 "@
957 {cax.|add.} %3,%1,%2
958 {ai.|addic.} %3,%1,%2
959 #
960 #"
961 [(set_attr "type" "fast_compare,compare,compare,compare")
962 (set_attr "length" "4,4,8,8")])
964 (define_split
965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
966 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
967 (match_operand:GPR 2 "reg_or_short_operand" ""))
968 (const_int 0)))
969 (clobber (match_scratch:GPR 3 ""))]
970 "reload_completed"
971 [(set (match_dup 3)
972 (plus:GPR (match_dup 1)
973 (match_dup 2)))
974 (set (match_dup 0)
975 (compare:CC (match_dup 3)
976 (const_int 0)))]
977 "")
979 (define_insn "*add<mode>3_internal3"
980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
981 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
982 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
983 (const_int 0)))
984 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
985 (plus:P (match_dup 1)
986 (match_dup 2)))]
987 ""
988 "@
989 {cax.|add.} %0,%1,%2
990 {ai.|addic.} %0,%1,%2
991 #
992 #"
993 [(set_attr "type" "fast_compare,compare,compare,compare")
994 (set_attr "length" "4,4,8,8")])
996 (define_split
997 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
998 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
999 (match_operand:P 2 "reg_or_short_operand" ""))
1000 (const_int 0)))
1001 (set (match_operand:P 0 "gpc_reg_operand" "")
1002 (plus:P (match_dup 1) (match_dup 2)))]
1003 "reload_completed"
1004 [(set (match_dup 0)
1005 (plus:P (match_dup 1)
1006 (match_dup 2)))
1007 (set (match_dup 3)
1008 (compare:CC (match_dup 0)
1009 (const_int 0)))]
1010 "")
1012 ;; Split an add that we can't do in one insn into two insns, each of which
1013 ;; does one 16-bit part. This is used by combine. Note that the low-order
1014 ;; add should be last in case the result gets used in an address.
1016 (define_split
1017 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1018 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1019 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1020 ""
1021 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1022 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1023 "
1024 {
1025 HOST_WIDE_INT val = INTVAL (operands[2]);
1026 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1027 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1029 operands[4] = GEN_INT (low);
1030 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1031 operands[3] = GEN_INT (rest);
1032 else if (! no_new_pseudos)
1033 {
1034 operands[3] = gen_reg_rtx (DImode);
1035 emit_move_insn (operands[3], operands[2]);
1036 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1037 DONE;
1038 }
1039 else
1040 FAIL;
1041 }")
1043 (define_insn "one_cmpl<mode>2"
1044 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1045 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1046 ""
1047 "nor %0,%1,%1")
1049 (define_insn ""
1050 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1051 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1052 (const_int 0)))
1053 (clobber (match_scratch:P 2 "=r,r"))]
1054 ""
1055 "@
1056 nor. %2,%1,%1
1057 #"
1058 [(set_attr "type" "compare")
1059 (set_attr "length" "4,8")])
1061 (define_split
1062 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1063 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1064 (const_int 0)))
1065 (clobber (match_scratch:P 2 ""))]
1066 "reload_completed"
1067 [(set (match_dup 2)
1068 (not:P (match_dup 1)))
1069 (set (match_dup 0)
1070 (compare:CC (match_dup 2)
1071 (const_int 0)))]
1072 "")
1074 (define_insn ""
1075 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1076 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1077 (const_int 0)))
1078 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1079 (not:P (match_dup 1)))]
1080 ""
1081 "@
1082 nor. %0,%1,%1
1083 #"
1084 [(set_attr "type" "compare")
1085 (set_attr "length" "4,8")])
1087 (define_split
1088 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1089 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1090 (const_int 0)))
1091 (set (match_operand:P 0 "gpc_reg_operand" "")
1092 (not:P (match_dup 1)))]
1093 "reload_completed"
1094 [(set (match_dup 0)
1095 (not:P (match_dup 1)))
1096 (set (match_dup 2)
1097 (compare:CC (match_dup 0)
1098 (const_int 0)))]
1099 "")
1101 (define_insn ""
1102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1103 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1104 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1105 "! TARGET_POWERPC"
1106 "{sf%I1|subf%I1c} %0,%2,%1")
1108 (define_insn ""
1109 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1110 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1111 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1112 "TARGET_POWERPC"
1113 "@
1114 subf %0,%2,%1
1115 subfic %0,%2,%1")
1117 (define_insn ""
1118 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1119 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1120 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1121 (const_int 0)))
1122 (clobber (match_scratch:SI 3 "=r,r"))]
1123 "! TARGET_POWERPC"
1124 "@
1125 {sf.|subfc.} %3,%2,%1
1126 #"
1127 [(set_attr "type" "compare")
1128 (set_attr "length" "4,8")])
1130 (define_insn ""
1131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1132 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1133 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1134 (const_int 0)))
1135 (clobber (match_scratch:P 3 "=r,r"))]
1136 "TARGET_POWERPC"
1137 "@
1138 subf. %3,%2,%1
1139 #"
1140 [(set_attr "type" "fast_compare")
1141 (set_attr "length" "4,8")])
1143 (define_split
1144 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1145 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1146 (match_operand:P 2 "gpc_reg_operand" ""))
1147 (const_int 0)))
1148 (clobber (match_scratch:P 3 ""))]
1149 "reload_completed"
1150 [(set (match_dup 3)
1151 (minus:P (match_dup 1)
1152 (match_dup 2)))
1153 (set (match_dup 0)
1154 (compare:CC (match_dup 3)
1155 (const_int 0)))]
1156 "")
1158 (define_insn ""
1159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1160 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1161 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1162 (const_int 0)))
1163 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1164 (minus:SI (match_dup 1) (match_dup 2)))]
1165 "! TARGET_POWERPC"
1166 "@
1167 {sf.|subfc.} %0,%2,%1
1168 #"
1169 [(set_attr "type" "compare")
1170 (set_attr "length" "4,8")])
1172 (define_insn ""
1173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1174 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1175 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1176 (const_int 0)))
1177 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1178 (minus:P (match_dup 1)
1179 (match_dup 2)))]
1180 "TARGET_POWERPC"
1181 "@
1182 subf. %0,%2,%1
1183 #"
1184 [(set_attr "type" "fast_compare")
1185 (set_attr "length" "4,8")])
1187 (define_split
1188 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1189 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1190 (match_operand:P 2 "gpc_reg_operand" ""))
1191 (const_int 0)))
1192 (set (match_operand:P 0 "gpc_reg_operand" "")
1193 (minus:P (match_dup 1)
1194 (match_dup 2)))]
1195 "reload_completed"
1196 [(set (match_dup 0)
1197 (minus:P (match_dup 1)
1198 (match_dup 2)))
1199 (set (match_dup 3)
1200 (compare:CC (match_dup 0)
1201 (const_int 0)))]
1202 "")
1204 (define_expand "sub<mode>3"
1205 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1206 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1207 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1208 ""
1209 "
1210 {
1211 if (GET_CODE (operands[2]) == CONST_INT)
1212 {
1213 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1214 negate_rtx (<MODE>mode, operands[2])));
1215 DONE;
1216 }
1217 }")
1219 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1220 ;; instruction and some auxiliary computations. Then we just have a single
1221 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1222 ;; combine.
1224 (define_expand "sminsi3"
1225 [(set (match_dup 3)
1226 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1227 (match_operand:SI 2 "reg_or_short_operand" ""))
1228 (const_int 0)
1229 (minus:SI (match_dup 2) (match_dup 1))))
1230 (set (match_operand:SI 0 "gpc_reg_operand" "")
1231 (minus:SI (match_dup 2) (match_dup 3)))]
1232 "TARGET_POWER || TARGET_ISEL"
1233 "
1234 {
1235 if (TARGET_ISEL)
1236 {
1237 operands[2] = force_reg (SImode, operands[2]);
1238 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1239 DONE;
1240 }
1242 operands[3] = gen_reg_rtx (SImode);
1243 }")
1245 (define_split
1246 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1247 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1248 (match_operand:SI 2 "reg_or_short_operand" "")))
1249 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1250 "TARGET_POWER"
1251 [(set (match_dup 3)
1252 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1253 (const_int 0)
1254 (minus:SI (match_dup 2) (match_dup 1))))
1255 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1256 "")
1258 (define_expand "smaxsi3"
1259 [(set (match_dup 3)
1260 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1261 (match_operand:SI 2 "reg_or_short_operand" ""))
1262 (const_int 0)
1263 (minus:SI (match_dup 2) (match_dup 1))))
1264 (set (match_operand:SI 0 "gpc_reg_operand" "")
1265 (plus:SI (match_dup 3) (match_dup 1)))]
1266 "TARGET_POWER || TARGET_ISEL"
1267 "
1268 {
1269 if (TARGET_ISEL)
1270 {
1271 operands[2] = force_reg (SImode, operands[2]);
1272 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1273 DONE;
1274 }
1275 operands[3] = gen_reg_rtx (SImode);
1276 }")
1278 (define_split
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1280 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1281 (match_operand:SI 2 "reg_or_short_operand" "")))
1282 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1283 "TARGET_POWER"
1284 [(set (match_dup 3)
1285 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1286 (const_int 0)
1287 (minus:SI (match_dup 2) (match_dup 1))))
1288 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1289 "")
1291 (define_expand "uminsi3"
1292 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1293 (match_dup 5)))
1294 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1295 (match_dup 5)))
1296 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1297 (const_int 0)
1298 (minus:SI (match_dup 4) (match_dup 3))))
1299 (set (match_operand:SI 0 "gpc_reg_operand" "")
1300 (minus:SI (match_dup 2) (match_dup 3)))]
1301 "TARGET_POWER || TARGET_ISEL"
1302 "
1303 {
1304 if (TARGET_ISEL)
1305 {
1306 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1307 DONE;
1308 }
1309 operands[3] = gen_reg_rtx (SImode);
1310 operands[4] = gen_reg_rtx (SImode);
1311 operands[5] = GEN_INT (-2147483647 - 1);
1312 }")
1314 (define_expand "umaxsi3"
1315 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1316 (match_dup 5)))
1317 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1318 (match_dup 5)))
1319 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1320 (const_int 0)
1321 (minus:SI (match_dup 4) (match_dup 3))))
1322 (set (match_operand:SI 0 "gpc_reg_operand" "")
1323 (plus:SI (match_dup 3) (match_dup 1)))]
1324 "TARGET_POWER || TARGET_ISEL"
1325 "
1326 {
1327 if (TARGET_ISEL)
1328 {
1329 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1330 DONE;
1331 }
1332 operands[3] = gen_reg_rtx (SImode);
1333 operands[4] = gen_reg_rtx (SImode);
1334 operands[5] = GEN_INT (-2147483647 - 1);
1335 }")
1337 (define_insn ""
1338 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1339 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1340 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1341 (const_int 0)
1342 (minus:SI (match_dup 2) (match_dup 1))))]
1343 "TARGET_POWER"
1344 "doz%I2 %0,%1,%2")
1346 (define_insn ""
1347 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1348 (compare:CC
1349 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1350 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1351 (const_int 0)
1352 (minus:SI (match_dup 2) (match_dup 1)))
1353 (const_int 0)))
1354 (clobber (match_scratch:SI 3 "=r,r"))]
1355 "TARGET_POWER"
1356 "@
1357 doz%I2. %3,%1,%2
1358 #"
1359 [(set_attr "type" "delayed_compare")
1360 (set_attr "length" "4,8")])
1362 (define_split
1363 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1364 (compare:CC
1365 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1366 (match_operand:SI 2 "reg_or_short_operand" ""))
1367 (const_int 0)
1368 (minus:SI (match_dup 2) (match_dup 1)))
1369 (const_int 0)))
1370 (clobber (match_scratch:SI 3 ""))]
1371 "TARGET_POWER && reload_completed"
1372 [(set (match_dup 3)
1373 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1374 (const_int 0)
1375 (minus:SI (match_dup 2) (match_dup 1))))
1376 (set (match_dup 0)
1377 (compare:CC (match_dup 3)
1378 (const_int 0)))]
1379 "")
1381 (define_insn ""
1382 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1383 (compare:CC
1384 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1385 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1386 (const_int 0)
1387 (minus:SI (match_dup 2) (match_dup 1)))
1388 (const_int 0)))
1389 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1390 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1391 (const_int 0)
1392 (minus:SI (match_dup 2) (match_dup 1))))]
1393 "TARGET_POWER"
1394 "@
1395 doz%I2. %0,%1,%2
1396 #"
1397 [(set_attr "type" "delayed_compare")
1398 (set_attr "length" "4,8")])
1400 (define_split
1401 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1402 (compare:CC
1403 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1404 (match_operand:SI 2 "reg_or_short_operand" ""))
1405 (const_int 0)
1406 (minus:SI (match_dup 2) (match_dup 1)))
1407 (const_int 0)))
1408 (set (match_operand:SI 0 "gpc_reg_operand" "")
1409 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1410 (const_int 0)
1411 (minus:SI (match_dup 2) (match_dup 1))))]
1412 "TARGET_POWER && reload_completed"
1413 [(set (match_dup 0)
1414 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1415 (const_int 0)
1416 (minus:SI (match_dup 2) (match_dup 1))))
1417 (set (match_dup 3)
1418 (compare:CC (match_dup 0)
1419 (const_int 0)))]
1420 "")
1422 ;; We don't need abs with condition code because such comparisons should
1423 ;; never be done.
1424 (define_expand "abssi2"
1425 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1426 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1427 ""
1428 "
1429 {
1430 if (TARGET_ISEL)
1431 {
1432 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1433 DONE;
1434 }
1435 else if (! TARGET_POWER)
1436 {
1437 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1438 DONE;
1439 }
1440 }")
1442 (define_insn "*abssi2_power"
1443 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1444 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1445 "TARGET_POWER"
1446 "abs %0,%1")
1448 (define_insn_and_split "abssi2_isel"
1449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1450 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1451 (clobber (match_scratch:SI 2 "=&b"))
1452 (clobber (match_scratch:CC 3 "=y"))]
1453 "TARGET_ISEL"
1454 "#"
1455 "&& reload_completed"
1456 [(set (match_dup 2) (neg:SI (match_dup 1)))
1457 (set (match_dup 3)
1458 (compare:CC (match_dup 1)
1459 (const_int 0)))
1460 (set (match_dup 0)
1461 (if_then_else:SI (ge (match_dup 3)
1462 (const_int 0))
1463 (match_dup 1)
1464 (match_dup 2)))]
1465 "")
1467 (define_insn_and_split "abssi2_nopower"
1468 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1469 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1470 (clobber (match_scratch:SI 2 "=&r,&r"))]
1471 "! TARGET_POWER && ! TARGET_ISEL"
1472 "#"
1473 "&& reload_completed"
1474 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1475 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1476 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1477 "")
1479 (define_insn "*nabs_power"
1480 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1481 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1482 "TARGET_POWER"
1483 "nabs %0,%1")
1485 (define_insn_and_split "*nabs_nopower"
1486 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1487 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1488 (clobber (match_scratch:SI 2 "=&r,&r"))]
1489 "! TARGET_POWER"
1490 "#"
1491 "&& reload_completed"
1492 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1493 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1494 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1495 "")
1497 (define_expand "neg<mode>2"
1498 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1499 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1500 ""
1501 "")
1503 (define_insn "*neg<mode>2_internal"
1504 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1505 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1506 ""
1507 "neg %0,%1")
1509 (define_insn ""
1510 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1511 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1512 (const_int 0)))
1513 (clobber (match_scratch:P 2 "=r,r"))]
1514 ""
1515 "@
1516 neg. %2,%1
1517 #"
1518 [(set_attr "type" "fast_compare")
1519 (set_attr "length" "4,8")])
1521 (define_split
1522 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1523 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1524 (const_int 0)))
1525 (clobber (match_scratch:P 2 ""))]
1526 "reload_completed"
1527 [(set (match_dup 2)
1528 (neg:P (match_dup 1)))
1529 (set (match_dup 0)
1530 (compare:CC (match_dup 2)
1531 (const_int 0)))]
1532 "")
1534 (define_insn ""
1535 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1536 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1537 (const_int 0)))
1538 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1539 (neg:P (match_dup 1)))]
1540 ""
1541 "@
1542 neg. %0,%1
1543 #"
1544 [(set_attr "type" "fast_compare")
1545 (set_attr "length" "4,8")])
1547 (define_split
1548 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1549 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1550 (const_int 0)))
1551 (set (match_operand:P 0 "gpc_reg_operand" "")
1552 (neg:P (match_dup 1)))]
1553 "reload_completed"
1554 [(set (match_dup 0)
1555 (neg:P (match_dup 1)))
1556 (set (match_dup 2)
1557 (compare:CC (match_dup 0)
1558 (const_int 0)))]
1559 "")
1561 (define_insn "clz<mode>2"
1562 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1563 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1564 ""
1565 "{cntlz|cntlz<wd>} %0,%1")
1567 (define_expand "ctz<mode>2"
1568 [(set (match_dup 2)
1569 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1570 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1571 (match_dup 2)))
1572 (clobber (scratch:CC))])
1573 (set (match_dup 4) (clz:GPR (match_dup 3)))
1574 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1575 (minus:GPR (match_dup 5) (match_dup 4)))]
1576 ""
1577 {
1578 operands[2] = gen_reg_rtx (<MODE>mode);
1579 operands[3] = gen_reg_rtx (<MODE>mode);
1580 operands[4] = gen_reg_rtx (<MODE>mode);
1581 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1582 })
1584 (define_expand "ffs<mode>2"
1585 [(set (match_dup 2)
1586 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1587 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1588 (match_dup 2)))
1589 (clobber (scratch:CC))])
1590 (set (match_dup 4) (clz:GPR (match_dup 3)))
1591 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1592 (minus:GPR (match_dup 5) (match_dup 4)))]
1593 ""
1594 {
1595 operands[2] = gen_reg_rtx (<MODE>mode);
1596 operands[3] = gen_reg_rtx (<MODE>mode);
1597 operands[4] = gen_reg_rtx (<MODE>mode);
1598 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1599 })
1601 (define_expand "popcount<mode>2"
1602 [(set (match_dup 2)
1603 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1604 UNSPEC_POPCNTB))
1605 (set (match_dup 3)
1606 (mult:GPR (match_dup 2) (match_dup 4)))
1607 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1608 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1609 "TARGET_POPCNTB"
1610 {
1611 operands[2] = gen_reg_rtx (<MODE>mode);
1612 operands[3] = gen_reg_rtx (<MODE>mode);
1613 operands[4] = force_reg (<MODE>mode,
1614 <MODE>mode == SImode
1615 ? GEN_INT (0x01010101)
1616 : GEN_INT ((HOST_WIDE_INT)
1617 0x01010101 << 32 | 0x01010101));
1618 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1619 })
1621 (define_insn "popcntb<mode>2"
1622 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1623 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1624 UNSPEC_POPCNTB))]
1625 "TARGET_POPCNTB"
1626 "popcntb %0,%1")
1628 (define_expand "mulsi3"
1629 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1630 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1631 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1632 ""
1633 "
1634 {
1635 if (TARGET_POWER)
1636 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1637 else
1638 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1639 DONE;
1640 }")
1642 (define_insn "mulsi3_mq"
1643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1644 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1645 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1646 (clobber (match_scratch:SI 3 "=q,q"))]
1647 "TARGET_POWER"
1648 "@
1649 {muls|mullw} %0,%1,%2
1650 {muli|mulli} %0,%1,%2"
1651 [(set (attr "type")
1652 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1653 (const_string "imul3")
1654 (match_operand:SI 2 "short_cint_operand" "")
1655 (const_string "imul2")]
1656 (const_string "imul")))])
1658 (define_insn "mulsi3_no_mq"
1659 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1660 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1661 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1662 "! TARGET_POWER"
1663 "@
1664 {muls|mullw} %0,%1,%2
1665 {muli|mulli} %0,%1,%2"
1666 [(set (attr "type")
1667 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1668 (const_string "imul3")
1669 (match_operand:SI 2 "short_cint_operand" "")
1670 (const_string "imul2")]
1671 (const_string "imul")))])
1673 (define_insn "*mulsi3_mq_internal1"
1674 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1675 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1676 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1677 (const_int 0)))
1678 (clobber (match_scratch:SI 3 "=r,r"))
1679 (clobber (match_scratch:SI 4 "=q,q"))]
1680 "TARGET_POWER"
1681 "@
1682 {muls.|mullw.} %3,%1,%2
1683 #"
1684 [(set_attr "type" "imul_compare")
1685 (set_attr "length" "4,8")])
1687 (define_split
1688 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1689 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1690 (match_operand:SI 2 "gpc_reg_operand" ""))
1691 (const_int 0)))
1692 (clobber (match_scratch:SI 3 ""))
1693 (clobber (match_scratch:SI 4 ""))]
1694 "TARGET_POWER && reload_completed"
1695 [(parallel [(set (match_dup 3)
1696 (mult:SI (match_dup 1) (match_dup 2)))
1697 (clobber (match_dup 4))])
1698 (set (match_dup 0)
1699 (compare:CC (match_dup 3)
1700 (const_int 0)))]
1701 "")
1703 (define_insn "*mulsi3_no_mq_internal1"
1704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1705 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1706 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1707 (const_int 0)))
1708 (clobber (match_scratch:SI 3 "=r,r"))]
1709 "! TARGET_POWER"
1710 "@
1711 {muls.|mullw.} %3,%1,%2
1712 #"
1713 [(set_attr "type" "imul_compare")
1714 (set_attr "length" "4,8")])
1716 (define_split
1717 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1718 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1719 (match_operand:SI 2 "gpc_reg_operand" ""))
1720 (const_int 0)))
1721 (clobber (match_scratch:SI 3 ""))]
1722 "! TARGET_POWER && reload_completed"
1723 [(set (match_dup 3)
1724 (mult:SI (match_dup 1) (match_dup 2)))
1725 (set (match_dup 0)
1726 (compare:CC (match_dup 3)
1727 (const_int 0)))]
1728 "")
1730 (define_insn "*mulsi3_mq_internal2"
1731 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1732 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1733 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1734 (const_int 0)))
1735 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1736 (mult:SI (match_dup 1) (match_dup 2)))
1737 (clobber (match_scratch:SI 4 "=q,q"))]
1738 "TARGET_POWER"
1739 "@
1740 {muls.|mullw.} %0,%1,%2
1741 #"
1742 [(set_attr "type" "imul_compare")
1743 (set_attr "length" "4,8")])
1745 (define_split
1746 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1747 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1748 (match_operand:SI 2 "gpc_reg_operand" ""))
1749 (const_int 0)))
1750 (set (match_operand:SI 0 "gpc_reg_operand" "")
1751 (mult:SI (match_dup 1) (match_dup 2)))
1752 (clobber (match_scratch:SI 4 ""))]
1753 "TARGET_POWER && reload_completed"
1754 [(parallel [(set (match_dup 0)
1755 (mult:SI (match_dup 1) (match_dup 2)))
1756 (clobber (match_dup 4))])
1757 (set (match_dup 3)
1758 (compare:CC (match_dup 0)
1759 (const_int 0)))]
1760 "")
1762 (define_insn "*mulsi3_no_mq_internal2"
1763 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1764 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1765 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1766 (const_int 0)))
1767 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1768 (mult:SI (match_dup 1) (match_dup 2)))]
1769 "! TARGET_POWER"
1770 "@
1771 {muls.|mullw.} %0,%1,%2
1772 #"
1773 [(set_attr "type" "imul_compare")
1774 (set_attr "length" "4,8")])
1776 (define_split
1777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1778 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1779 (match_operand:SI 2 "gpc_reg_operand" ""))
1780 (const_int 0)))
1781 (set (match_operand:SI 0 "gpc_reg_operand" "")
1782 (mult:SI (match_dup 1) (match_dup 2)))]
1783 "! TARGET_POWER && reload_completed"
1784 [(set (match_dup 0)
1785 (mult:SI (match_dup 1) (match_dup 2)))
1786 (set (match_dup 3)
1787 (compare:CC (match_dup 0)
1788 (const_int 0)))]
1789 "")
1791 ;; Operand 1 is divided by operand 2; quotient goes to operand
1792 ;; 0 and remainder to operand 3.
1793 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1795 (define_expand "divmodsi4"
1796 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1797 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1798 (match_operand:SI 2 "gpc_reg_operand" "")))
1799 (set (match_operand:SI 3 "register_operand" "")
1800 (mod:SI (match_dup 1) (match_dup 2)))])]
1801 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1802 "
1803 {
1804 if (! TARGET_POWER && ! TARGET_POWERPC)
1805 {
1806 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1807 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1808 emit_insn (gen_divss_call ());
1809 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1810 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1811 DONE;
1812 }
1813 }")
1815 (define_insn "*divmodsi4_internal"
1816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1817 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1818 (match_operand:SI 2 "gpc_reg_operand" "r")))
1819 (set (match_operand:SI 3 "register_operand" "=q")
1820 (mod:SI (match_dup 1) (match_dup 2)))]
1821 "TARGET_POWER"
1822 "divs %0,%1,%2"
1823 [(set_attr "type" "idiv")])
1825 (define_expand "udiv<mode>3"
1826 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1827 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1828 (match_operand:GPR 2 "gpc_reg_operand" "")))]
1829 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1830 "
1831 {
1832 if (! TARGET_POWER && ! TARGET_POWERPC)
1833 {
1834 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1835 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1836 emit_insn (gen_quous_call ());
1837 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1838 DONE;
1839 }
1840 else if (TARGET_POWER)
1841 {
1842 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1843 DONE;
1844 }
1845 }")
1847 (define_insn "udivsi3_mq"
1848 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1849 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1850 (match_operand:SI 2 "gpc_reg_operand" "r")))
1851 (clobber (match_scratch:SI 3 "=q"))]
1852 "TARGET_POWERPC && TARGET_POWER"
1853 "divwu %0,%1,%2"
1854 [(set_attr "type" "idiv")])
1856 (define_insn "*udivsi3_no_mq"
1857 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1858 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1859 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1860 "TARGET_POWERPC && ! TARGET_POWER"
1861 "div<wd>u %0,%1,%2"
1862 [(set_attr "type" "idiv")])
1864 ;; For powers of two we can do srai/aze for divide and then adjust for
1865 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1866 ;; used; for PowerPC, force operands into register and do a normal divide;
1867 ;; for AIX common-mode, use quoss call on register operands.
1868 (define_expand "div<mode>3"
1869 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1870 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1871 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1872 ""
1873 "
1874 {
1875 if (GET_CODE (operands[2]) == CONST_INT
1876 && INTVAL (operands[2]) > 0
1877 && exact_log2 (INTVAL (operands[2])) >= 0)
1878 ;
1879 else if (TARGET_POWERPC)
1880 {
1881 operands[2] = force_reg (SImode, operands[2]);
1882 if (TARGET_POWER)
1883 {
1884 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1885 DONE;
1886 }
1887 }
1888 else if (TARGET_POWER)
1889 FAIL;
1890 else
1891 {
1892 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1893 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1894 emit_insn (gen_quoss_call ());
1895 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1896 DONE;
1897 }
1898 }")
1900 (define_insn "divsi3_mq"
1901 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1902 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1903 (match_operand:SI 2 "gpc_reg_operand" "r")))
1904 (clobber (match_scratch:SI 3 "=q"))]
1905 "TARGET_POWERPC && TARGET_POWER"
1906 "divw %0,%1,%2"
1907 [(set_attr "type" "idiv")])
1909 (define_insn "*div<mode>3_no_mq"
1910 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1911 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1912 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1913 "TARGET_POWERPC && ! TARGET_POWER"
1914 "div<wd> %0,%1,%2"
1915 [(set_attr "type" "idiv")])
1917 (define_expand "mod<mode>3"
1918 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
1919 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
1920 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
1921 ""
1922 "
1923 {
1924 int i;
1925 rtx temp1;
1926 rtx temp2;
1928 if (GET_CODE (operands[2]) != CONST_INT
1929 || INTVAL (operands[2]) <= 0
1930 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1931 FAIL;
1933 temp1 = gen_reg_rtx (<MODE>mode);
1934 temp2 = gen_reg_rtx (<MODE>mode);
1936 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
1937 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
1938 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
1939 DONE;
1940 }")
1942 (define_insn ""
1943 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1944 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1945 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
1946 ""
1947 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
1948 [(set_attr "type" "two")
1949 (set_attr "length" "8")])
1951 (define_insn ""
1952 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1953 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1954 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
1955 (const_int 0)))
1956 (clobber (match_scratch:P 3 "=r,r"))]
1957 ""
1958 "@
1959 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
1960 #"
1961 [(set_attr "type" "compare")
1962 (set_attr "length" "8,12")])
1964 (define_split
1965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1966 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1967 (match_operand:GPR 2 "exact_log2_cint_operand"
1968 ""))
1969 (const_int 0)))
1970 (clobber (match_scratch:GPR 3 ""))]
1971 "reload_completed"
1972 [(set (match_dup 3)
1973 (div:<MODE> (match_dup 1) (match_dup 2)))
1974 (set (match_dup 0)
1975 (compare:CC (match_dup 3)
1976 (const_int 0)))]
1977 "")
1979 (define_insn ""
1980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1981 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1982 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
1983 (const_int 0)))
1984 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1985 (div:P (match_dup 1) (match_dup 2)))]
1986 ""
1987 "@
1988 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
1989 #"
1990 [(set_attr "type" "compare")
1991 (set_attr "length" "8,12")])
1993 (define_split
1994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1995 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1996 (match_operand:GPR 2 "exact_log2_cint_operand"
1997 ""))
1998 (const_int 0)))
1999 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2000 (div:GPR (match_dup 1) (match_dup 2)))]
2001 "reload_completed"
2002 [(set (match_dup 0)
2003 (div:<MODE> (match_dup 1) (match_dup 2)))
2004 (set (match_dup 3)
2005 (compare:CC (match_dup 0)
2006 (const_int 0)))]
2007 "")
2009 (define_insn ""
2010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2011 (udiv:SI
2012 (plus:DI (ashift:DI
2013 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2014 (const_int 32))
2015 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2016 (match_operand:SI 3 "gpc_reg_operand" "r")))
2017 (set (match_operand:SI 2 "register_operand" "=*q")
2018 (umod:SI
2019 (plus:DI (ashift:DI
2020 (zero_extend:DI (match_dup 1)) (const_int 32))
2021 (zero_extend:DI (match_dup 4)))
2022 (match_dup 3)))]
2023 "TARGET_POWER"
2024 "div %0,%1,%3"
2025 [(set_attr "type" "idiv")])
2027 ;; To do unsigned divide we handle the cases of the divisor looking like a
2028 ;; negative number. If it is a constant that is less than 2**31, we don't
2029 ;; have to worry about the branches. So make a few subroutines here.
2030 ;;
2031 ;; First comes the normal case.
2032 (define_expand "udivmodsi4_normal"
2033 [(set (match_dup 4) (const_int 0))
2034 (parallel [(set (match_operand:SI 0 "" "")
2035 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2036 (const_int 32))
2037 (zero_extend:DI (match_operand:SI 1 "" "")))
2038 (match_operand:SI 2 "" "")))
2039 (set (match_operand:SI 3 "" "")
2040 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2041 (const_int 32))
2042 (zero_extend:DI (match_dup 1)))
2043 (match_dup 2)))])]
2044 "TARGET_POWER"
2045 "
2046 { operands[4] = gen_reg_rtx (SImode); }")
2048 ;; This handles the branches.
2049 (define_expand "udivmodsi4_tests"
2050 [(set (match_operand:SI 0 "" "") (const_int 0))
2051 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2052 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2053 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2054 (label_ref (match_operand:SI 4 "" "")) (pc)))
2055 (set (match_dup 0) (const_int 1))
2056 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2057 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2058 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2059 (label_ref (match_dup 4)) (pc)))]
2060 "TARGET_POWER"
2061 "
2062 { operands[5] = gen_reg_rtx (CCUNSmode);
2063 operands[6] = gen_reg_rtx (CCmode);
2064 }")
2066 (define_expand "udivmodsi4"
2067 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2068 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2069 (match_operand:SI 2 "reg_or_cint_operand" "")))
2070 (set (match_operand:SI 3 "gpc_reg_operand" "")
2071 (umod:SI (match_dup 1) (match_dup 2)))])]
2072 ""
2073 "
2074 {
2075 rtx label = 0;
2077 if (! TARGET_POWER)
2078 {
2079 if (! TARGET_POWERPC)
2080 {
2081 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2082 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2083 emit_insn (gen_divus_call ());
2084 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2085 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2086 DONE;
2087 }
2088 else
2089 FAIL;
2090 }
2092 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2093 {
2094 operands[2] = force_reg (SImode, operands[2]);
2095 label = gen_label_rtx ();
2096 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2097 operands[3], label));
2098 }
2099 else
2100 operands[2] = force_reg (SImode, operands[2]);
2102 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2103 operands[3]));
2104 if (label)
2105 emit_label (label);
2107 DONE;
2108 }")
2110 ;; AIX architecture-independent common-mode multiply (DImode),
2111 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2112 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2113 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2114 ;; assumed unused if generating common-mode, so ignore.
2115 (define_insn "mulh_call"
2116 [(set (reg:SI 3)
2117 (truncate:SI
2118 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2119 (sign_extend:DI (reg:SI 4)))
2120 (const_int 32))))
2121 (clobber (match_scratch:SI 0 "=l"))]
2122 "! TARGET_POWER && ! TARGET_POWERPC"
2123 "bla __mulh"
2124 [(set_attr "type" "imul")])
2126 (define_insn "mull_call"
2127 [(set (reg:DI 3)
2128 (mult:DI (sign_extend:DI (reg:SI 3))
2129 (sign_extend:DI (reg:SI 4))))
2130 (clobber (match_scratch:SI 0 "=l"))
2131 (clobber (reg:SI 0))]
2132 "! TARGET_POWER && ! TARGET_POWERPC"
2133 "bla __mull"
2134 [(set_attr "type" "imul")])
2136 (define_insn "divss_call"
2137 [(set (reg:SI 3)
2138 (div:SI (reg:SI 3) (reg:SI 4)))
2139 (set (reg:SI 4)
2140 (mod:SI (reg:SI 3) (reg:SI 4)))
2141 (clobber (match_scratch:SI 0 "=l"))
2142 (clobber (reg:SI 0))]
2143 "! TARGET_POWER && ! TARGET_POWERPC"
2144 "bla __divss"
2145 [(set_attr "type" "idiv")])
2147 (define_insn "divus_call"
2148 [(set (reg:SI 3)
2149 (udiv:SI (reg:SI 3) (reg:SI 4)))
2150 (set (reg:SI 4)
2151 (umod:SI (reg:SI 3) (reg:SI 4)))
2152 (clobber (match_scratch:SI 0 "=l"))
2153 (clobber (reg:SI 0))
2154 (clobber (match_scratch:CC 1 "=x"))
2155 (clobber (reg:CC 69))]
2156 "! TARGET_POWER && ! TARGET_POWERPC"
2157 "bla __divus"
2158 [(set_attr "type" "idiv")])
2160 (define_insn "quoss_call"
2161 [(set (reg:SI 3)
2162 (div:SI (reg:SI 3) (reg:SI 4)))
2163 (clobber (match_scratch:SI 0 "=l"))]
2164 "! TARGET_POWER && ! TARGET_POWERPC"
2165 "bla __quoss"
2166 [(set_attr "type" "idiv")])
2168 (define_insn "quous_call"
2169 [(set (reg:SI 3)
2170 (udiv:SI (reg:SI 3) (reg:SI 4)))
2171 (clobber (match_scratch:SI 0 "=l"))
2172 (clobber (reg:SI 0))
2173 (clobber (match_scratch:CC 1 "=x"))
2174 (clobber (reg:CC 69))]
2175 "! TARGET_POWER && ! TARGET_POWERPC"
2176 "bla __quous"
2177 [(set_attr "type" "idiv")])
2178 \f
2179 ;; Logical instructions
2180 ;; The logical instructions are mostly combined by using match_operator,
2181 ;; but the plain AND insns are somewhat different because there is no
2182 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2183 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2185 (define_insn "andsi3"
2186 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2187 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2188 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2189 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2190 ""
2191 "@
2192 and %0,%1,%2
2193 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2194 {andil.|andi.} %0,%1,%b2
2195 {andiu.|andis.} %0,%1,%u2"
2196 [(set_attr "type" "*,*,compare,compare")])
2198 ;; Note to set cr's other than cr0 we do the and immediate and then
2199 ;; the test again -- this avoids a mfcr which on the higher end
2200 ;; machines causes an execution serialization
2202 (define_insn "*andsi3_internal2"
2203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2204 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2205 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2206 (const_int 0)))
2207 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2208 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2209 "TARGET_32BIT"
2210 "@
2211 and. %3,%1,%2
2212 {andil.|andi.} %3,%1,%b2
2213 {andiu.|andis.} %3,%1,%u2
2214 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2215 #
2216 #
2217 #
2218 #"
2219 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2220 (set_attr "length" "4,4,4,4,8,8,8,8")])
2222 (define_insn "*andsi3_internal3"
2223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2224 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2225 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2226 (const_int 0)))
2227 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2228 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2229 "TARGET_64BIT"
2230 "@
2231 #
2232 {andil.|andi.} %3,%1,%b2
2233 {andiu.|andis.} %3,%1,%u2
2234 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2235 #
2236 #
2237 #
2238 #"
2239 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2240 (set_attr "length" "8,4,4,4,8,8,8,8")])
2242 (define_split
2243 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2244 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2245 (match_operand:GPR 2 "and_operand" ""))
2246 (const_int 0)))
2247 (clobber (match_scratch:GPR 3 ""))
2248 (clobber (match_scratch:CC 4 ""))]
2249 "reload_completed"
2250 [(parallel [(set (match_dup 3)
2251 (and:<MODE> (match_dup 1)
2252 (match_dup 2)))
2253 (clobber (match_dup 4))])
2254 (set (match_dup 0)
2255 (compare:CC (match_dup 3)
2256 (const_int 0)))]
2257 "")
2259 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2260 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2262 (define_split
2263 [(set (match_operand:CC 0 "cc_reg_operand" "")
2264 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2265 (match_operand:SI 2 "gpc_reg_operand" ""))
2266 (const_int 0)))
2267 (clobber (match_scratch:SI 3 ""))
2268 (clobber (match_scratch:CC 4 ""))]
2269 "TARGET_POWERPC64 && reload_completed"
2270 [(parallel [(set (match_dup 3)
2271 (and:SI (match_dup 1)
2272 (match_dup 2)))
2273 (clobber (match_dup 4))])
2274 (set (match_dup 0)
2275 (compare:CC (match_dup 3)
2276 (const_int 0)))]
2277 "")
2279 (define_insn "*andsi3_internal4"
2280 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2281 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2282 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2283 (const_int 0)))
2284 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2285 (and:SI (match_dup 1)
2286 (match_dup 2)))
2287 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2288 "TARGET_32BIT"
2289 "@
2290 and. %0,%1,%2
2291 {andil.|andi.} %0,%1,%b2
2292 {andiu.|andis.} %0,%1,%u2
2293 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2294 #
2295 #
2296 #
2297 #"
2298 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2299 (set_attr "length" "4,4,4,4,8,8,8,8")])
2301 (define_insn "*andsi3_internal5"
2302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2303 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2304 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2305 (const_int 0)))
2306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2307 (and:SI (match_dup 1)
2308 (match_dup 2)))
2309 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2310 "TARGET_64BIT"
2311 "@
2312 #
2313 {andil.|andi.} %0,%1,%b2
2314 {andiu.|andis.} %0,%1,%u2
2315 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2316 #
2317 #
2318 #
2319 #"
2320 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2321 (set_attr "length" "8,4,4,4,8,8,8,8")])
2323 (define_split
2324 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2326 (match_operand:SI 2 "and_operand" ""))
2327 (const_int 0)))
2328 (set (match_operand:SI 0 "gpc_reg_operand" "")
2329 (and:SI (match_dup 1)
2330 (match_dup 2)))
2331 (clobber (match_scratch:CC 4 ""))]
2332 "reload_completed"
2333 [(parallel [(set (match_dup 0)
2334 (and:SI (match_dup 1)
2335 (match_dup 2)))
2336 (clobber (match_dup 4))])
2337 (set (match_dup 3)
2338 (compare:CC (match_dup 0)
2339 (const_int 0)))]
2340 "")
2342 (define_split
2343 [(set (match_operand:CC 3 "cc_reg_operand" "")
2344 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2345 (match_operand:SI 2 "gpc_reg_operand" ""))
2346 (const_int 0)))
2347 (set (match_operand:SI 0 "gpc_reg_operand" "")
2348 (and:SI (match_dup 1)
2349 (match_dup 2)))
2350 (clobber (match_scratch:CC 4 ""))]
2351 "TARGET_POWERPC64 && reload_completed"
2352 [(parallel [(set (match_dup 0)
2353 (and:SI (match_dup 1)
2354 (match_dup 2)))
2355 (clobber (match_dup 4))])
2356 (set (match_dup 3)
2357 (compare:CC (match_dup 0)
2358 (const_int 0)))]
2359 "")
2361 ;; Handle the PowerPC64 rlwinm corner case
2363 (define_insn_and_split "*andsi3_internal6"
2364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2365 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2366 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2367 "TARGET_POWERPC64"
2368 "#"
2369 "TARGET_POWERPC64"
2370 [(set (match_dup 0)
2371 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2372 (match_dup 4)))
2373 (set (match_dup 0)
2374 (rotate:SI (match_dup 0) (match_dup 5)))]
2375 "
2376 {
2377 int mb = extract_MB (operands[2]);
2378 int me = extract_ME (operands[2]);
2379 operands[3] = GEN_INT (me + 1);
2380 operands[5] = GEN_INT (32 - (me + 1));
2381 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2382 }"
2383 [(set_attr "length" "8")])
2385 (define_expand "iorsi3"
2386 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2387 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2388 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2389 ""
2390 "
2391 {
2392 if (GET_CODE (operands[2]) == CONST_INT
2393 && ! logical_operand (operands[2], SImode))
2394 {
2395 HOST_WIDE_INT value = INTVAL (operands[2]);
2396 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2397 ? operands[0] : gen_reg_rtx (SImode));
2399 emit_insn (gen_iorsi3 (tmp, operands[1],
2400 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2401 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2402 DONE;
2403 }
2404 }")
2406 (define_expand "xorsi3"
2407 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2408 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2409 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2410 ""
2411 "
2412 {
2413 if (GET_CODE (operands[2]) == CONST_INT
2414 && ! logical_operand (operands[2], SImode))
2415 {
2416 HOST_WIDE_INT value = INTVAL (operands[2]);
2417 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2418 ? operands[0] : gen_reg_rtx (SImode));
2420 emit_insn (gen_xorsi3 (tmp, operands[1],
2421 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2422 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2423 DONE;
2424 }
2425 }")
2427 (define_insn "*boolsi3_internal1"
2428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2429 (match_operator:SI 3 "boolean_or_operator"
2430 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2431 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2432 ""
2433 "@
2434 %q3 %0,%1,%2
2435 {%q3il|%q3i} %0,%1,%b2
2436 {%q3iu|%q3is} %0,%1,%u2")
2438 (define_insn "*boolsi3_internal2"
2439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2440 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2441 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2442 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2443 (const_int 0)))
2444 (clobber (match_scratch:SI 3 "=r,r"))]
2445 "TARGET_32BIT"
2446 "@
2447 %q4. %3,%1,%2
2448 #"
2449 [(set_attr "type" "compare")
2450 (set_attr "length" "4,8")])
2452 (define_split
2453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2454 (compare:CC (match_operator:SI 4 "boolean_operator"
2455 [(match_operand:SI 1 "gpc_reg_operand" "")
2456 (match_operand:SI 2 "gpc_reg_operand" "")])
2457 (const_int 0)))
2458 (clobber (match_scratch:SI 3 ""))]
2459 "TARGET_32BIT && reload_completed"
2460 [(set (match_dup 3) (match_dup 4))
2461 (set (match_dup 0)
2462 (compare:CC (match_dup 3)
2463 (const_int 0)))]
2464 "")
2466 (define_insn "*boolsi3_internal3"
2467 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2468 (compare:CC (match_operator:SI 4 "boolean_operator"
2469 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2470 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2471 (const_int 0)))
2472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2473 (match_dup 4))]
2474 "TARGET_32BIT"
2475 "@
2476 %q4. %0,%1,%2
2477 #"
2478 [(set_attr "type" "compare")
2479 (set_attr "length" "4,8")])
2481 (define_split
2482 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2483 (compare:CC (match_operator:SI 4 "boolean_operator"
2484 [(match_operand:SI 1 "gpc_reg_operand" "")
2485 (match_operand:SI 2 "gpc_reg_operand" "")])
2486 (const_int 0)))
2487 (set (match_operand:SI 0 "gpc_reg_operand" "")
2488 (match_dup 4))]
2489 "TARGET_32BIT && reload_completed"
2490 [(set (match_dup 0) (match_dup 4))
2491 (set (match_dup 3)
2492 (compare:CC (match_dup 0)
2493 (const_int 0)))]
2494 "")
2496 ;; Split a logical operation that we can't do in one insn into two insns,
2497 ;; each of which does one 16-bit part. This is used by combine.
2499 (define_split
2500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2501 (match_operator:SI 3 "boolean_or_operator"
2502 [(match_operand:SI 1 "gpc_reg_operand" "")
2503 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2504 ""
2505 [(set (match_dup 0) (match_dup 4))
2506 (set (match_dup 0) (match_dup 5))]
2507 "
2508 {
2509 rtx i;
2510 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2511 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2512 operands[1], i);
2513 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2514 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2515 operands[0], i);
2516 }")
2518 (define_insn "*boolcsi3_internal1"
2519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2520 (match_operator:SI 3 "boolean_operator"
2521 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2522 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2523 ""
2524 "%q3 %0,%2,%1")
2526 (define_insn "*boolcsi3_internal2"
2527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2528 (compare:CC (match_operator:SI 4 "boolean_operator"
2529 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2530 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2531 (const_int 0)))
2532 (clobber (match_scratch:SI 3 "=r,r"))]
2533 "TARGET_32BIT"
2534 "@
2535 %q4. %3,%2,%1
2536 #"
2537 [(set_attr "type" "compare")
2538 (set_attr "length" "4,8")])
2540 (define_split
2541 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2542 (compare:CC (match_operator:SI 4 "boolean_operator"
2543 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2544 (match_operand:SI 2 "gpc_reg_operand" "")])
2545 (const_int 0)))
2546 (clobber (match_scratch:SI 3 ""))]
2547 "TARGET_32BIT && reload_completed"
2548 [(set (match_dup 3) (match_dup 4))
2549 (set (match_dup 0)
2550 (compare:CC (match_dup 3)
2551 (const_int 0)))]
2552 "")
2554 (define_insn "*boolcsi3_internal3"
2555 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2556 (compare:CC (match_operator:SI 4 "boolean_operator"
2557 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2558 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2559 (const_int 0)))
2560 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2561 (match_dup 4))]
2562 "TARGET_32BIT"
2563 "@
2564 %q4. %0,%2,%1
2565 #"
2566 [(set_attr "type" "compare")
2567 (set_attr "length" "4,8")])
2569 (define_split
2570 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2571 (compare:CC (match_operator:SI 4 "boolean_operator"
2572 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2573 (match_operand:SI 2 "gpc_reg_operand" "")])
2574 (const_int 0)))
2575 (set (match_operand:SI 0 "gpc_reg_operand" "")
2576 (match_dup 4))]
2577 "TARGET_32BIT && reload_completed"
2578 [(set (match_dup 0) (match_dup 4))
2579 (set (match_dup 3)
2580 (compare:CC (match_dup 0)
2581 (const_int 0)))]
2582 "")
2584 (define_insn "*boolccsi3_internal1"
2585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2586 (match_operator:SI 3 "boolean_operator"
2587 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2588 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2589 ""
2590 "%q3 %0,%1,%2")
2592 (define_insn "*boolccsi3_internal2"
2593 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2594 (compare:CC (match_operator:SI 4 "boolean_operator"
2595 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2596 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2597 (const_int 0)))
2598 (clobber (match_scratch:SI 3 "=r,r"))]
2599 "TARGET_32BIT"
2600 "@
2601 %q4. %3,%1,%2
2602 #"
2603 [(set_attr "type" "compare")
2604 (set_attr "length" "4,8")])
2606 (define_split
2607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2608 (compare:CC (match_operator:SI 4 "boolean_operator"
2609 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2610 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2611 (const_int 0)))
2612 (clobber (match_scratch:SI 3 ""))]
2613 "TARGET_32BIT && reload_completed"
2614 [(set (match_dup 3) (match_dup 4))
2615 (set (match_dup 0)
2616 (compare:CC (match_dup 3)
2617 (const_int 0)))]
2618 "")
2620 (define_insn "*boolccsi3_internal3"
2621 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2622 (compare:CC (match_operator:SI 4 "boolean_operator"
2623 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2624 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2625 (const_int 0)))
2626 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2627 (match_dup 4))]
2628 "TARGET_32BIT"
2629 "@
2630 %q4. %0,%1,%2
2631 #"
2632 [(set_attr "type" "compare")
2633 (set_attr "length" "4,8")])
2635 (define_split
2636 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2637 (compare:CC (match_operator:SI 4 "boolean_operator"
2638 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2639 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2640 (const_int 0)))
2641 (set (match_operand:SI 0 "gpc_reg_operand" "")
2642 (match_dup 4))]
2643 "TARGET_32BIT && reload_completed"
2644 [(set (match_dup 0) (match_dup 4))
2645 (set (match_dup 3)
2646 (compare:CC (match_dup 0)
2647 (const_int 0)))]
2648 "")
2650 ;; maskir insn. We need four forms because things might be in arbitrary
2651 ;; orders. Don't define forms that only set CR fields because these
2652 ;; would modify an input register.
2654 (define_insn "*maskir_internal1"
2655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2656 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2657 (match_operand:SI 1 "gpc_reg_operand" "0"))
2658 (and:SI (match_dup 2)
2659 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2660 "TARGET_POWER"
2661 "maskir %0,%3,%2")
2663 (define_insn "*maskir_internal2"
2664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2665 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2666 (match_operand:SI 1 "gpc_reg_operand" "0"))
2667 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2668 (match_dup 2))))]
2669 "TARGET_POWER"
2670 "maskir %0,%3,%2")
2672 (define_insn "*maskir_internal3"
2673 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2674 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2675 (match_operand:SI 3 "gpc_reg_operand" "r"))
2676 (and:SI (not:SI (match_dup 2))
2677 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2678 "TARGET_POWER"
2679 "maskir %0,%3,%2")
2681 (define_insn "*maskir_internal4"
2682 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2683 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2684 (match_operand:SI 2 "gpc_reg_operand" "r"))
2685 (and:SI (not:SI (match_dup 2))
2686 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2687 "TARGET_POWER"
2688 "maskir %0,%3,%2")
2690 (define_insn "*maskir_internal5"
2691 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2692 (compare:CC
2693 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2694 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2695 (and:SI (match_dup 2)
2696 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2697 (const_int 0)))
2698 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2699 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2700 (and:SI (match_dup 2) (match_dup 3))))]
2701 "TARGET_POWER"
2702 "@
2703 maskir. %0,%3,%2
2704 #"
2705 [(set_attr "type" "compare")
2706 (set_attr "length" "4,8")])
2708 (define_split
2709 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2710 (compare:CC
2711 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2712 (match_operand:SI 1 "gpc_reg_operand" ""))
2713 (and:SI (match_dup 2)
2714 (match_operand:SI 3 "gpc_reg_operand" "")))
2715 (const_int 0)))
2716 (set (match_operand:SI 0 "gpc_reg_operand" "")
2717 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2718 (and:SI (match_dup 2) (match_dup 3))))]
2719 "TARGET_POWER && reload_completed"
2720 [(set (match_dup 0)
2721 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2722 (and:SI (match_dup 2) (match_dup 3))))
2723 (set (match_dup 4)
2724 (compare:CC (match_dup 0)
2725 (const_int 0)))]
2726 "")
2728 (define_insn "*maskir_internal6"
2729 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2730 (compare:CC
2731 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2732 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2733 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2734 (match_dup 2)))
2735 (const_int 0)))
2736 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2737 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2738 (and:SI (match_dup 3) (match_dup 2))))]
2739 "TARGET_POWER"
2740 "@
2741 maskir. %0,%3,%2
2742 #"
2743 [(set_attr "type" "compare")
2744 (set_attr "length" "4,8")])
2746 (define_split
2747 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2748 (compare:CC
2749 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2750 (match_operand:SI 1 "gpc_reg_operand" ""))
2751 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2752 (match_dup 2)))
2753 (const_int 0)))
2754 (set (match_operand:SI 0 "gpc_reg_operand" "")
2755 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2756 (and:SI (match_dup 3) (match_dup 2))))]
2757 "TARGET_POWER && reload_completed"
2758 [(set (match_dup 0)
2759 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2760 (and:SI (match_dup 3) (match_dup 2))))
2761 (set (match_dup 4)
2762 (compare:CC (match_dup 0)
2763 (const_int 0)))]
2764 "")
2766 (define_insn "*maskir_internal7"
2767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2768 (compare:CC
2769 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2770 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2771 (and:SI (not:SI (match_dup 2))
2772 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2773 (const_int 0)))
2774 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2775 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2776 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2777 "TARGET_POWER"
2778 "@
2779 maskir. %0,%3,%2
2780 #"
2781 [(set_attr "type" "compare")
2782 (set_attr "length" "4,8")])
2784 (define_split
2785 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2786 (compare:CC
2787 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2788 (match_operand:SI 3 "gpc_reg_operand" ""))
2789 (and:SI (not:SI (match_dup 2))
2790 (match_operand:SI 1 "gpc_reg_operand" "")))
2791 (const_int 0)))
2792 (set (match_operand:SI 0 "gpc_reg_operand" "")
2793 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2794 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2795 "TARGET_POWER && reload_completed"
2796 [(set (match_dup 0)
2797 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2798 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2799 (set (match_dup 4)
2800 (compare:CC (match_dup 0)
2801 (const_int 0)))]
2802 "")
2804 (define_insn "*maskir_internal8"
2805 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2806 (compare:CC
2807 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2808 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2809 (and:SI (not:SI (match_dup 2))
2810 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2811 (const_int 0)))
2812 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2813 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2814 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2815 "TARGET_POWER"
2816 "@
2817 maskir. %0,%3,%2
2818 #"
2819 [(set_attr "type" "compare")
2820 (set_attr "length" "4,8")])
2822 (define_split
2823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2824 (compare:CC
2825 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2826 (match_operand:SI 2 "gpc_reg_operand" ""))
2827 (and:SI (not:SI (match_dup 2))
2828 (match_operand:SI 1 "gpc_reg_operand" "")))
2829 (const_int 0)))
2830 (set (match_operand:SI 0 "gpc_reg_operand" "")
2831 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2832 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2833 "TARGET_POWER && reload_completed"
2834 [(set (match_dup 0)
2835 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2836 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2837 (set (match_dup 4)
2838 (compare:CC (match_dup 0)
2839 (const_int 0)))]
2840 "")
2841 \f
2842 ;; Rotate and shift insns, in all their variants. These support shifts,
2843 ;; field inserts and extracts, and various combinations thereof.
2844 (define_expand "insv"
2845 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2846 (match_operand:SI 1 "const_int_operand" "")
2847 (match_operand:SI 2 "const_int_operand" ""))
2848 (match_operand 3 "gpc_reg_operand" ""))]
2849 ""
2850 "
2851 {
2852 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2853 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2854 compiler if the address of the structure is taken later. */
2855 if (GET_CODE (operands[0]) == SUBREG
2856 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2857 FAIL;
2859 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2860 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2861 else
2862 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2863 DONE;
2864 }")
2866 (define_insn "insvsi"
2867 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2868 (match_operand:SI 1 "const_int_operand" "i")
2869 (match_operand:SI 2 "const_int_operand" "i"))
2870 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2871 ""
2872 "*
2873 {
2874 int start = INTVAL (operands[2]) & 31;
2875 int size = INTVAL (operands[1]) & 31;
2877 operands[4] = GEN_INT (32 - start - size);
2878 operands[1] = GEN_INT (start + size - 1);
2879 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2880 }"
2881 [(set_attr "type" "insert_word")])
2883 (define_insn "*insvsi_internal1"
2884 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2885 (match_operand:SI 1 "const_int_operand" "i")
2886 (match_operand:SI 2 "const_int_operand" "i"))
2887 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2888 (match_operand:SI 4 "const_int_operand" "i")))]
2889 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2890 "*
2891 {
2892 int shift = INTVAL (operands[4]) & 31;
2893 int start = INTVAL (operands[2]) & 31;
2894 int size = INTVAL (operands[1]) & 31;
2896 operands[4] = GEN_INT (shift - start - size);
2897 operands[1] = GEN_INT (start + size - 1);
2898 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2899 }"
2900 [(set_attr "type" "insert_word")])
2902 (define_insn "*insvsi_internal2"
2903 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2904 (match_operand:SI 1 "const_int_operand" "i")
2905 (match_operand:SI 2 "const_int_operand" "i"))
2906 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2907 (match_operand:SI 4 "const_int_operand" "i")))]
2908 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2909 "*
2910 {
2911 int shift = INTVAL (operands[4]) & 31;
2912 int start = INTVAL (operands[2]) & 31;
2913 int size = INTVAL (operands[1]) & 31;
2915 operands[4] = GEN_INT (32 - shift - start - size);
2916 operands[1] = GEN_INT (start + size - 1);
2917 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2918 }"
2919 [(set_attr "type" "insert_word")])
2921 (define_insn "*insvsi_internal3"
2922 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2923 (match_operand:SI 1 "const_int_operand" "i")
2924 (match_operand:SI 2 "const_int_operand" "i"))
2925 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2926 (match_operand:SI 4 "const_int_operand" "i")))]
2927 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2928 "*
2929 {
2930 int shift = INTVAL (operands[4]) & 31;
2931 int start = INTVAL (operands[2]) & 31;
2932 int size = INTVAL (operands[1]) & 31;
2934 operands[4] = GEN_INT (32 - shift - start - size);
2935 operands[1] = GEN_INT (start + size - 1);
2936 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2937 }"
2938 [(set_attr "type" "insert_word")])
2940 (define_insn "*insvsi_internal4"
2941 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2942 (match_operand:SI 1 "const_int_operand" "i")
2943 (match_operand:SI 2 "const_int_operand" "i"))
2944 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2945 (match_operand:SI 4 "const_int_operand" "i")
2946 (match_operand:SI 5 "const_int_operand" "i")))]
2947 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2948 "*
2949 {
2950 int extract_start = INTVAL (operands[5]) & 31;
2951 int extract_size = INTVAL (operands[4]) & 31;
2952 int insert_start = INTVAL (operands[2]) & 31;
2953 int insert_size = INTVAL (operands[1]) & 31;
2955 /* Align extract field with insert field */
2956 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2957 operands[1] = GEN_INT (insert_start + insert_size - 1);
2958 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2959 }"
2960 [(set_attr "type" "insert_word")])
2962 ;; combine patterns for rlwimi
2963 (define_insn "*insvsi_internal5"
2964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2965 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2966 (match_operand:SI 1 "mask_operand" "i"))
2967 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2968 (match_operand:SI 2 "const_int_operand" "i"))
2969 (match_operand:SI 5 "mask_operand" "i"))))]
2970 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2971 "*
2972 {
2973 int me = extract_ME(operands[5]);
2974 int mb = extract_MB(operands[5]);
2975 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
2976 operands[2] = GEN_INT(mb);
2977 operands[1] = GEN_INT(me);
2978 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2979 }"
2980 [(set_attr "type" "insert_word")])
2982 (define_insn "*insvsi_internal6"
2983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2984 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2985 (match_operand:SI 2 "const_int_operand" "i"))
2986 (match_operand:SI 5 "mask_operand" "i"))
2987 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2988 (match_operand:SI 1 "mask_operand" "i"))))]
2989 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2990 "*
2991 {
2992 int me = extract_ME(operands[5]);
2993 int mb = extract_MB(operands[5]);
2994 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
2995 operands[2] = GEN_INT(mb);
2996 operands[1] = GEN_INT(me);
2997 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2998 }"
2999 [(set_attr "type" "insert_word")])
3001 (define_insn "insvdi"
3002 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3003 (match_operand:SI 1 "const_int_operand" "i")
3004 (match_operand:SI 2 "const_int_operand" "i"))
3005 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3006 "TARGET_POWERPC64"
3007 "*
3008 {
3009 int start = INTVAL (operands[2]) & 63;
3010 int size = INTVAL (operands[1]) & 63;
3012 operands[1] = GEN_INT (64 - start - size);
3013 return \"rldimi %0,%3,%H1,%H2\";
3014 }")
3016 (define_insn "*insvdi_internal2"
3017 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3018 (match_operand:SI 1 "const_int_operand" "i")
3019 (match_operand:SI 2 "const_int_operand" "i"))
3020 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3021 (match_operand:SI 4 "const_int_operand" "i")))]
3022 "TARGET_POWERPC64
3023 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3024 "*
3025 {
3026 int shift = INTVAL (operands[4]) & 63;
3027 int start = (INTVAL (operands[2]) & 63) - 32;
3028 int size = INTVAL (operands[1]) & 63;
3030 operands[4] = GEN_INT (64 - shift - start - size);
3031 operands[2] = GEN_INT (start);
3032 operands[1] = GEN_INT (start + size - 1);
3033 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3034 }")
3036 (define_insn "*insvdi_internal3"
3037 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3038 (match_operand:SI 1 "const_int_operand" "i")
3039 (match_operand:SI 2 "const_int_operand" "i"))
3040 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3041 (match_operand:SI 4 "const_int_operand" "i")))]
3042 "TARGET_POWERPC64
3043 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3044 "*
3045 {
3046 int shift = INTVAL (operands[4]) & 63;
3047 int start = (INTVAL (operands[2]) & 63) - 32;
3048 int size = INTVAL (operands[1]) & 63;
3050 operands[4] = GEN_INT (64 - shift - start - size);
3051 operands[2] = GEN_INT (start);
3052 operands[1] = GEN_INT (start + size - 1);
3053 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3054 }")
3056 (define_expand "extzv"
3057 [(set (match_operand 0 "gpc_reg_operand" "")
3058 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3059 (match_operand:SI 2 "const_int_operand" "")
3060 (match_operand:SI 3 "const_int_operand" "")))]
3061 ""
3062 "
3063 {
3064 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3065 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3066 compiler if the address of the structure is taken later. */
3067 if (GET_CODE (operands[0]) == SUBREG
3068 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3069 FAIL;
3071 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3072 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3073 else
3074 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3075 DONE;
3076 }")
3078 (define_insn "extzvsi"
3079 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3080 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3081 (match_operand:SI 2 "const_int_operand" "i")
3082 (match_operand:SI 3 "const_int_operand" "i")))]
3083 ""
3084 "*
3085 {
3086 int start = INTVAL (operands[3]) & 31;
3087 int size = INTVAL (operands[2]) & 31;
3089 if (start + size >= 32)
3090 operands[3] = const0_rtx;
3091 else
3092 operands[3] = GEN_INT (start + size);
3093 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3094 }")
3096 (define_insn "*extzvsi_internal1"
3097 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3098 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3099 (match_operand:SI 2 "const_int_operand" "i,i")
3100 (match_operand:SI 3 "const_int_operand" "i,i"))
3101 (const_int 0)))
3102 (clobber (match_scratch:SI 4 "=r,r"))]
3103 ""
3104 "*
3105 {
3106 int start = INTVAL (operands[3]) & 31;
3107 int size = INTVAL (operands[2]) & 31;
3109 /* Force split for non-cc0 compare. */
3110 if (which_alternative == 1)
3111 return \"#\";
3113 /* If the bit-field being tested fits in the upper or lower half of a
3114 word, it is possible to use andiu. or andil. to test it. This is
3115 useful because the condition register set-use delay is smaller for
3116 andi[ul]. than for rlinm. This doesn't work when the starting bit
3117 position is 0 because the LT and GT bits may be set wrong. */
3119 if ((start > 0 && start + size <= 16) || start >= 16)
3120 {
3121 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3122 - (1 << (16 - (start & 15) - size))));
3123 if (start < 16)
3124 return \"{andiu.|andis.} %4,%1,%3\";
3125 else
3126 return \"{andil.|andi.} %4,%1,%3\";
3127 }
3129 if (start + size >= 32)
3130 operands[3] = const0_rtx;
3131 else
3132 operands[3] = GEN_INT (start + size);
3133 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3134 }"
3135 [(set_attr "type" "compare")
3136 (set_attr "length" "4,8")])
3138 (define_split
3139 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3140 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3141 (match_operand:SI 2 "const_int_operand" "")
3142 (match_operand:SI 3 "const_int_operand" ""))
3143 (const_int 0)))
3144 (clobber (match_scratch:SI 4 ""))]
3145 "reload_completed"
3146 [(set (match_dup 4)
3147 (zero_extract:SI (match_dup 1) (match_dup 2)
3148 (match_dup 3)))
3149 (set (match_dup 0)
3150 (compare:CC (match_dup 4)
3151 (const_int 0)))]
3152 "")
3154 (define_insn "*extzvsi_internal2"
3155 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3156 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3157 (match_operand:SI 2 "const_int_operand" "i,i")
3158 (match_operand:SI 3 "const_int_operand" "i,i"))
3159 (const_int 0)))
3160 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3161 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3162 ""
3163 "*
3164 {
3165 int start = INTVAL (operands[3]) & 31;
3166 int size = INTVAL (operands[2]) & 31;
3168 /* Force split for non-cc0 compare. */
3169 if (which_alternative == 1)
3170 return \"#\";
3172 /* Since we are using the output value, we can't ignore any need for
3173 a shift. The bit-field must end at the LSB. */
3174 if (start >= 16 && start + size == 32)
3175 {
3176 operands[3] = GEN_INT ((1 << size) - 1);
3177 return \"{andil.|andi.} %0,%1,%3\";
3178 }
3180 if (start + size >= 32)
3181 operands[3] = const0_rtx;
3182 else
3183 operands[3] = GEN_INT (start + size);
3184 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3185 }"
3186 [(set_attr "type" "compare")
3187 (set_attr "length" "4,8")])
3189 (define_split
3190 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3191 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3192 (match_operand:SI 2 "const_int_operand" "")
3193 (match_operand:SI 3 "const_int_operand" ""))
3194 (const_int 0)))
3195 (set (match_operand:SI 0 "gpc_reg_operand" "")
3196 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3197 "reload_completed"
3198 [(set (match_dup 0)
3199 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3200 (set (match_dup 4)
3201 (compare:CC (match_dup 0)
3202 (const_int 0)))]
3203 "")
3205 (define_insn "extzvdi"
3206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3207 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3208 (match_operand:SI 2 "const_int_operand" "i")
3209 (match_operand:SI 3 "const_int_operand" "i")))]
3210 "TARGET_POWERPC64"
3211 "*
3212 {
3213 int start = INTVAL (operands[3]) & 63;
3214 int size = INTVAL (operands[2]) & 63;
3216 if (start + size >= 64)
3217 operands[3] = const0_rtx;
3218 else
3219 operands[3] = GEN_INT (start + size);
3220 operands[2] = GEN_INT (64 - size);
3221 return \"rldicl %0,%1,%3,%2\";
3222 }")
3224 (define_insn "*extzvdi_internal1"
3225 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3226 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3227 (match_operand:SI 2 "const_int_operand" "i")
3228 (match_operand:SI 3 "const_int_operand" "i"))
3229 (const_int 0)))
3230 (clobber (match_scratch:DI 4 "=r"))]
3231 "TARGET_64BIT"
3232 "*
3233 {
3234 int start = INTVAL (operands[3]) & 63;
3235 int size = INTVAL (operands[2]) & 63;
3237 if (start + size >= 64)
3238 operands[3] = const0_rtx;
3239 else
3240 operands[3] = GEN_INT (start + size);
3241 operands[2] = GEN_INT (64 - size);
3242 return \"rldicl. %4,%1,%3,%2\";
3243 }"
3244 [(set_attr "type" "compare")])
3246 (define_insn "*extzvdi_internal2"
3247 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3248 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3249 (match_operand:SI 2 "const_int_operand" "i")
3250 (match_operand:SI 3 "const_int_operand" "i"))
3251 (const_int 0)))
3252 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3253 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3254 "TARGET_64BIT"
3255 "*
3256 {
3257 int start = INTVAL (operands[3]) & 63;
3258 int size = INTVAL (operands[2]) & 63;
3260 if (start + size >= 64)
3261 operands[3] = const0_rtx;
3262 else
3263 operands[3] = GEN_INT (start + size);
3264 operands[2] = GEN_INT (64 - size);
3265 return \"rldicl. %0,%1,%3,%2\";
3266 }"
3267 [(set_attr "type" "compare")])
3269 (define_insn "rotlsi3"
3270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3271 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3272 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3273 ""
3274 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3276 (define_insn "*rotlsi3_internal2"
3277 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3278 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3279 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3280 (const_int 0)))
3281 (clobber (match_scratch:SI 3 "=r,r"))]
3282 ""
3283 "@
3284 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3285 #"
3286 [(set_attr "type" "delayed_compare")
3287 (set_attr "length" "4,8")])
3289 (define_split
3290 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3291 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3292 (match_operand:SI 2 "reg_or_cint_operand" ""))
3293 (const_int 0)))
3294 (clobber (match_scratch:SI 3 ""))]
3295 "reload_completed"
3296 [(set (match_dup 3)
3297 (rotate:SI (match_dup 1) (match_dup 2)))
3298 (set (match_dup 0)
3299 (compare:CC (match_dup 3)
3300 (const_int 0)))]
3301 "")
3303 (define_insn "*rotlsi3_internal3"
3304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3305 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3306 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3307 (const_int 0)))
3308 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3309 (rotate:SI (match_dup 1) (match_dup 2)))]
3310 ""
3311 "@
3312 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3313 #"
3314 [(set_attr "type" "delayed_compare")
3315 (set_attr "length" "4,8")])
3317 (define_split
3318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3319 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3320 (match_operand:SI 2 "reg_or_cint_operand" ""))
3321 (const_int 0)))
3322 (set (match_operand:SI 0 "gpc_reg_operand" "")
3323 (rotate:SI (match_dup 1) (match_dup 2)))]
3324 "reload_completed"
3325 [(set (match_dup 0)
3326 (rotate:SI (match_dup 1) (match_dup 2)))
3327 (set (match_dup 3)
3328 (compare:CC (match_dup 0)
3329 (const_int 0)))]
3330 "")
3332 (define_insn "*rotlsi3_internal4"
3333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3334 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3335 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3336 (match_operand:SI 3 "mask_operand" "n")))]
3337 ""
3338 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3340 (define_insn "*rotlsi3_internal5"
3341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3342 (compare:CC (and:SI
3343 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3344 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3345 (match_operand:SI 3 "mask_operand" "n,n"))
3346 (const_int 0)))
3347 (clobber (match_scratch:SI 4 "=r,r"))]
3348 ""
3349 "@
3350 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3351 #"
3352 [(set_attr "type" "delayed_compare")
3353 (set_attr "length" "4,8")])
3355 (define_split
3356 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3357 (compare:CC (and:SI
3358 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3359 (match_operand:SI 2 "reg_or_cint_operand" ""))
3360 (match_operand:SI 3 "mask_operand" ""))
3361 (const_int 0)))
3362 (clobber (match_scratch:SI 4 ""))]
3363 "reload_completed"
3364 [(set (match_dup 4)
3365 (and:SI (rotate:SI (match_dup 1)
3366 (match_dup 2))
3367 (match_dup 3)))
3368 (set (match_dup 0)
3369 (compare:CC (match_dup 4)
3370 (const_int 0)))]
3371 "")
3373 (define_insn "*rotlsi3_internal6"
3374 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3375 (compare:CC (and:SI
3376 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3377 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3378 (match_operand:SI 3 "mask_operand" "n,n"))
3379 (const_int 0)))
3380 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3381 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3382 ""
3383 "@
3384 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3385 #"
3386 [(set_attr "type" "delayed_compare")
3387 (set_attr "length" "4,8")])
3389 (define_split
3390 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3391 (compare:CC (and:SI
3392 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3393 (match_operand:SI 2 "reg_or_cint_operand" ""))
3394 (match_operand:SI 3 "mask_operand" ""))
3395 (const_int 0)))
3396 (set (match_operand:SI 0 "gpc_reg_operand" "")
3397 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3398 "reload_completed"
3399 [(set (match_dup 0)
3400 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3401 (set (match_dup 4)
3402 (compare:CC (match_dup 0)
3403 (const_int 0)))]
3404 "")
3406 (define_insn "*rotlsi3_internal7"
3407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3408 (zero_extend:SI
3409 (subreg:QI
3410 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3411 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3412 ""
3413 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3415 (define_insn "*rotlsi3_internal8"
3416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3417 (compare:CC (zero_extend:SI
3418 (subreg:QI
3419 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3420 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3421 (const_int 0)))
3422 (clobber (match_scratch:SI 3 "=r,r"))]
3423 ""
3424 "@
3425 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3426 #"
3427 [(set_attr "type" "delayed_compare")
3428 (set_attr "length" "4,8")])
3430 (define_split
3431 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3432 (compare:CC (zero_extend:SI
3433 (subreg:QI
3434 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3435 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3436 (const_int 0)))
3437 (clobber (match_scratch:SI 3 ""))]
3438 "reload_completed"
3439 [(set (match_dup 3)
3440 (zero_extend:SI (subreg:QI
3441 (rotate:SI (match_dup 1)
3442 (match_dup 2)) 0)))
3443 (set (match_dup 0)
3444 (compare:CC (match_dup 3)
3445 (const_int 0)))]
3446 "")
3448 (define_insn "*rotlsi3_internal9"
3449 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3450 (compare:CC (zero_extend:SI
3451 (subreg:QI
3452 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3453 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3454 (const_int 0)))
3455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3456 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3457 ""
3458 "@
3459 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3460 #"
3461 [(set_attr "type" "delayed_compare")
3462 (set_attr "length" "4,8")])
3464 (define_split
3465 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3466 (compare:CC (zero_extend:SI
3467 (subreg:QI
3468 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3469 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3470 (const_int 0)))
3471 (set (match_operand:SI 0 "gpc_reg_operand" "")
3472 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3473 "reload_completed"
3474 [(set (match_dup 0)
3475 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3476 (set (match_dup 3)
3477 (compare:CC (match_dup 0)
3478 (const_int 0)))]
3479 "")
3481 (define_insn "*rotlsi3_internal10"
3482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3483 (zero_extend:SI
3484 (subreg:HI
3485 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3486 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3487 ""
3488 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3490 (define_insn "*rotlsi3_internal11"
3491 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3492 (compare:CC (zero_extend:SI
3493 (subreg:HI
3494 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3495 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3496 (const_int 0)))
3497 (clobber (match_scratch:SI 3 "=r,r"))]
3498 ""
3499 "@
3500 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3501 #"
3502 [(set_attr "type" "delayed_compare")
3503 (set_attr "length" "4,8")])
3505 (define_split
3506 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3507 (compare:CC (zero_extend:SI
3508 (subreg:HI
3509 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3510 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3511 (const_int 0)))
3512 (clobber (match_scratch:SI 3 ""))]
3513 "reload_completed"
3514 [(set (match_dup 3)
3515 (zero_extend:SI (subreg:HI
3516 (rotate:SI (match_dup 1)
3517 (match_dup 2)) 0)))
3518 (set (match_dup 0)
3519 (compare:CC (match_dup 3)
3520 (const_int 0)))]
3521 "")
3523 (define_insn "*rotlsi3_internal12"
3524 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3525 (compare:CC (zero_extend:SI
3526 (subreg:HI
3527 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3528 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3529 (const_int 0)))
3530 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3531 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3532 ""
3533 "@
3534 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3535 #"
3536 [(set_attr "type" "delayed_compare")
3537 (set_attr "length" "4,8")])
3539 (define_split
3540 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3541 (compare:CC (zero_extend:SI
3542 (subreg:HI
3543 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3544 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3545 (const_int 0)))
3546 (set (match_operand:SI 0 "gpc_reg_operand" "")
3547 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3548 "reload_completed"
3549 [(set (match_dup 0)
3550 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3551 (set (match_dup 3)
3552 (compare:CC (match_dup 0)
3553 (const_int 0)))]
3554 "")
3556 ;; Note that we use "sle." instead of "sl." so that we can set
3557 ;; SHIFT_COUNT_TRUNCATED.
3559 (define_expand "ashlsi3"
3560 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3561 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3562 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3563 ""
3564 "
3565 {
3566 if (TARGET_POWER)
3567 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3568 else
3569 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3570 DONE;
3571 }")
3573 (define_insn "ashlsi3_power"
3574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3575 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3576 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3577 (clobber (match_scratch:SI 3 "=q,X"))]
3578 "TARGET_POWER"
3579 "@
3580 sle %0,%1,%2
3581 {sli|slwi} %0,%1,%h2")
3583 (define_insn "ashlsi3_no_power"
3584 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3585 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3586 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3587 "! TARGET_POWER"
3588 "{sl|slw}%I2 %0,%1,%h2")
3590 (define_insn ""
3591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3592 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3593 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3594 (const_int 0)))
3595 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3596 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3597 "TARGET_POWER"
3598 "@
3599 sle. %3,%1,%2
3600 {sli.|slwi.} %3,%1,%h2
3601 #
3602 #"
3603 [(set_attr "type" "delayed_compare")
3604 (set_attr "length" "4,4,8,8")])
3606 (define_split
3607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3608 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3609 (match_operand:SI 2 "reg_or_cint_operand" ""))
3610 (const_int 0)))
3611 (clobber (match_scratch:SI 3 ""))
3612 (clobber (match_scratch:SI 4 ""))]
3613 "TARGET_POWER && reload_completed"
3614 [(parallel [(set (match_dup 3)
3615 (ashift:SI (match_dup 1) (match_dup 2)))
3616 (clobber (match_dup 4))])
3617 (set (match_dup 0)
3618 (compare:CC (match_dup 3)
3619 (const_int 0)))]
3620 "")
3622 (define_insn ""
3623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3624 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3625 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3626 (const_int 0)))
3627 (clobber (match_scratch:SI 3 "=r,r"))]
3628 "! TARGET_POWER && TARGET_32BIT"
3629 "@
3630 {sl|slw}%I2. %3,%1,%h2
3631 #"
3632 [(set_attr "type" "delayed_compare")
3633 (set_attr "length" "4,8")])
3635 (define_split
3636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3637 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "reg_or_cint_operand" ""))
3639 (const_int 0)))
3640 (clobber (match_scratch:SI 3 ""))]
3641 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3642 [(set (match_dup 3)
3643 (ashift:SI (match_dup 1) (match_dup 2)))
3644 (set (match_dup 0)
3645 (compare:CC (match_dup 3)
3646 (const_int 0)))]
3647 "")
3649 (define_insn ""
3650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3651 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3652 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3653 (const_int 0)))
3654 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3655 (ashift:SI (match_dup 1) (match_dup 2)))
3656 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3657 "TARGET_POWER"
3658 "@
3659 sle. %0,%1,%2
3660 {sli.|slwi.} %0,%1,%h2
3661 #
3662 #"
3663 [(set_attr "type" "delayed_compare")
3664 (set_attr "length" "4,4,8,8")])
3666 (define_split
3667 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3668 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3669 (match_operand:SI 2 "reg_or_cint_operand" ""))
3670 (const_int 0)))
3671 (set (match_operand:SI 0 "gpc_reg_operand" "")
3672 (ashift:SI (match_dup 1) (match_dup 2)))
3673 (clobber (match_scratch:SI 4 ""))]
3674 "TARGET_POWER && reload_completed"
3675 [(parallel [(set (match_dup 0)
3676 (ashift:SI (match_dup 1) (match_dup 2)))
3677 (clobber (match_dup 4))])
3678 (set (match_dup 3)
3679 (compare:CC (match_dup 0)
3680 (const_int 0)))]
3681 "")
3683 (define_insn ""
3684 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3685 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3686 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3687 (const_int 0)))
3688 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3689 (ashift:SI (match_dup 1) (match_dup 2)))]
3690 "! TARGET_POWER && TARGET_32BIT"
3691 "@
3692 {sl|slw}%I2. %0,%1,%h2
3693 #"
3694 [(set_attr "type" "delayed_compare")
3695 (set_attr "length" "4,8")])
3697 (define_split
3698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3699 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3700 (match_operand:SI 2 "reg_or_cint_operand" ""))
3701 (const_int 0)))
3702 (set (match_operand:SI 0 "gpc_reg_operand" "")
3703 (ashift:SI (match_dup 1) (match_dup 2)))]
3704 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3705 [(set (match_dup 0)
3706 (ashift:SI (match_dup 1) (match_dup 2)))
3707 (set (match_dup 3)
3708 (compare:CC (match_dup 0)
3709 (const_int 0)))]
3710 "")
3712 (define_insn "rlwinm"
3713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3714 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3715 (match_operand:SI 2 "const_int_operand" "i"))
3716 (match_operand:SI 3 "mask_operand" "n")))]
3717 "includes_lshift_p (operands[2], operands[3])"
3718 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3720 (define_insn ""
3721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3722 (compare:CC
3723 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3724 (match_operand:SI 2 "const_int_operand" "i,i"))
3725 (match_operand:SI 3 "mask_operand" "n,n"))
3726 (const_int 0)))
3727 (clobber (match_scratch:SI 4 "=r,r"))]
3728 "includes_lshift_p (operands[2], operands[3])"
3729 "@
3730 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3731 #"
3732 [(set_attr "type" "delayed_compare")
3733 (set_attr "length" "4,8")])
3735 (define_split
3736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3737 (compare:CC
3738 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3739 (match_operand:SI 2 "const_int_operand" ""))
3740 (match_operand:SI 3 "mask_operand" ""))
3741 (const_int 0)))
3742 (clobber (match_scratch:SI 4 ""))]
3743 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3744 [(set (match_dup 4)
3745 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3746 (match_dup 3)))
3747 (set (match_dup 0)
3748 (compare:CC (match_dup 4)
3749 (const_int 0)))]
3750 "")
3752 (define_insn ""
3753 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3754 (compare:CC
3755 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3756 (match_operand:SI 2 "const_int_operand" "i,i"))
3757 (match_operand:SI 3 "mask_operand" "n,n"))
3758 (const_int 0)))
3759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3760 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3761 "includes_lshift_p (operands[2], operands[3])"
3762 "@
3763 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3764 #"
3765 [(set_attr "type" "delayed_compare")
3766 (set_attr "length" "4,8")])
3768 (define_split
3769 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3770 (compare:CC
3771 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3772 (match_operand:SI 2 "const_int_operand" ""))
3773 (match_operand:SI 3 "mask_operand" ""))
3774 (const_int 0)))
3775 (set (match_operand:SI 0 "gpc_reg_operand" "")
3776 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3777 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3778 [(set (match_dup 0)
3779 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3780 (set (match_dup 4)
3781 (compare:CC (match_dup 0)
3782 (const_int 0)))]
3783 "")
3785 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3786 ;; "sli x,x,0".
3787 (define_expand "lshrsi3"
3788 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3789 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3790 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3791 ""
3792 "
3793 {
3794 if (TARGET_POWER)
3795 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3796 else
3797 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3798 DONE;
3799 }")
3801 (define_insn "lshrsi3_power"
3802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3803 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3804 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3805 (clobber (match_scratch:SI 3 "=q,X,X"))]
3806 "TARGET_POWER"
3807 "@
3808 sre %0,%1,%2
3809 mr %0,%1
3810 {s%A2i|s%A2wi} %0,%1,%h2")
3812 (define_insn "lshrsi3_no_power"
3813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3814 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3815 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3816 "! TARGET_POWER"
3817 "@
3818 mr %0,%1
3819 {sr|srw}%I2 %0,%1,%h2")
3821 (define_insn ""
3822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3823 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3824 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3825 (const_int 0)))
3826 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3827 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3828 "TARGET_POWER"
3829 "@
3830 sre. %3,%1,%2
3831 mr. %1,%1
3832 {s%A2i.|s%A2wi.} %3,%1,%h2
3833 #
3834 #
3835 #"
3836 [(set_attr "type" "delayed_compare")
3837 (set_attr "length" "4,4,4,8,8,8")])
3839 (define_split
3840 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3841 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3842 (match_operand:SI 2 "reg_or_cint_operand" ""))
3843 (const_int 0)))
3844 (clobber (match_scratch:SI 3 ""))
3845 (clobber (match_scratch:SI 4 ""))]
3846 "TARGET_POWER && reload_completed"
3847 [(parallel [(set (match_dup 3)
3848 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3849 (clobber (match_dup 4))])
3850 (set (match_dup 0)
3851 (compare:CC (match_dup 3)
3852 (const_int 0)))]
3853 "")
3855 (define_insn ""
3856 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3857 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3858 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3859 (const_int 0)))
3860 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3861 "! TARGET_POWER && TARGET_32BIT"
3862 "@
3863 mr. %1,%1
3864 {sr|srw}%I2. %3,%1,%h2
3865 #
3866 #"
3867 [(set_attr "type" "delayed_compare")
3868 (set_attr "length" "4,4,8,8")])
3870 (define_split
3871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3872 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3873 (match_operand:SI 2 "reg_or_cint_operand" ""))
3874 (const_int 0)))
3875 (clobber (match_scratch:SI 3 ""))]
3876 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3877 [(set (match_dup 3)
3878 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3879 (set (match_dup 0)
3880 (compare:CC (match_dup 3)
3881 (const_int 0)))]
3882 "")
3884 (define_insn ""
3885 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3886 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3887 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3888 (const_int 0)))
3889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3890 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3891 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3892 "TARGET_POWER"
3893 "@
3894 sre. %0,%1,%2
3895 mr. %0,%1
3896 {s%A2i.|s%A2wi.} %0,%1,%h2
3897 #
3898 #
3899 #"
3900 [(set_attr "type" "delayed_compare")
3901 (set_attr "length" "4,4,4,8,8,8")])
3903 (define_split
3904 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3905 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3906 (match_operand:SI 2 "reg_or_cint_operand" ""))
3907 (const_int 0)))
3908 (set (match_operand:SI 0 "gpc_reg_operand" "")
3909 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3910 (clobber (match_scratch:SI 4 ""))]
3911 "TARGET_POWER && reload_completed"
3912 [(parallel [(set (match_dup 0)
3913 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3914 (clobber (match_dup 4))])
3915 (set (match_dup 3)
3916 (compare:CC (match_dup 0)
3917 (const_int 0)))]
3918 "")
3920 (define_insn ""
3921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3922 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3923 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3924 (const_int 0)))
3925 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3926 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3927 "! TARGET_POWER && TARGET_32BIT"
3928 "@
3929 mr. %0,%1
3930 {sr|srw}%I2. %0,%1,%h2
3931 #
3932 #"
3933 [(set_attr "type" "delayed_compare")
3934 (set_attr "length" "4,4,8,8")])
3936 (define_split
3937 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3938 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3939 (match_operand:SI 2 "reg_or_cint_operand" ""))
3940 (const_int 0)))
3941 (set (match_operand:SI 0 "gpc_reg_operand" "")
3942 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3943 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3944 [(set (match_dup 0)
3945 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3946 (set (match_dup 3)
3947 (compare:CC (match_dup 0)
3948 (const_int 0)))]
3949 "")
3951 (define_insn ""
3952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3953 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3954 (match_operand:SI 2 "const_int_operand" "i"))
3955 (match_operand:SI 3 "mask_operand" "n")))]
3956 "includes_rshift_p (operands[2], operands[3])"
3957 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3959 (define_insn ""
3960 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3961 (compare:CC
3962 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3963 (match_operand:SI 2 "const_int_operand" "i,i"))
3964 (match_operand:SI 3 "mask_operand" "n,n"))
3965 (const_int 0)))
3966 (clobber (match_scratch:SI 4 "=r,r"))]
3967 "includes_rshift_p (operands[2], operands[3])"
3968 "@
3969 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3970 #"
3971 [(set_attr "type" "delayed_compare")
3972 (set_attr "length" "4,8")])
3974 (define_split
3975 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3976 (compare:CC
3977 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3978 (match_operand:SI 2 "const_int_operand" ""))
3979 (match_operand:SI 3 "mask_operand" ""))
3980 (const_int 0)))
3981 (clobber (match_scratch:SI 4 ""))]
3982 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3983 [(set (match_dup 4)
3984 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3985 (match_dup 3)))
3986 (set (match_dup 0)
3987 (compare:CC (match_dup 4)
3988 (const_int 0)))]
3989 "")
3991 (define_insn ""
3992 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3993 (compare:CC
3994 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3995 (match_operand:SI 2 "const_int_operand" "i,i"))
3996 (match_operand:SI 3 "mask_operand" "n,n"))
3997 (const_int 0)))
3998 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3999 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4000 "includes_rshift_p (operands[2], operands[3])"
4001 "@
4002 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4003 #"
4004 [(set_attr "type" "delayed_compare")
4005 (set_attr "length" "4,8")])
4007 (define_split
4008 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4009 (compare:CC
4010 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4011 (match_operand:SI 2 "const_int_operand" ""))
4012 (match_operand:SI 3 "mask_operand" ""))
4013 (const_int 0)))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4016 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4017 [(set (match_dup 0)
4018 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4019 (set (match_dup 4)
4020 (compare:CC (match_dup 0)
4021 (const_int 0)))]
4022 "")
4024 (define_insn ""
4025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4026 (zero_extend:SI
4027 (subreg:QI
4028 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4029 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4030 "includes_rshift_p (operands[2], GEN_INT (255))"
4031 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4033 (define_insn ""
4034 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4035 (compare:CC
4036 (zero_extend:SI
4037 (subreg:QI
4038 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4039 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4040 (const_int 0)))
4041 (clobber (match_scratch:SI 3 "=r,r"))]
4042 "includes_rshift_p (operands[2], GEN_INT (255))"
4043 "@
4044 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4045 #"
4046 [(set_attr "type" "delayed_compare")
4047 (set_attr "length" "4,8")])
4049 (define_split
4050 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4051 (compare:CC
4052 (zero_extend:SI
4053 (subreg:QI
4054 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4055 (match_operand:SI 2 "const_int_operand" "")) 0))
4056 (const_int 0)))
4057 (clobber (match_scratch:SI 3 ""))]
4058 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4059 [(set (match_dup 3)
4060 (zero_extend:SI (subreg:QI
4061 (lshiftrt:SI (match_dup 1)
4062 (match_dup 2)) 0)))
4063 (set (match_dup 0)
4064 (compare:CC (match_dup 3)
4065 (const_int 0)))]
4066 "")
4068 (define_insn ""
4069 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4070 (compare:CC
4071 (zero_extend:SI
4072 (subreg:QI
4073 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4074 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4075 (const_int 0)))
4076 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4077 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4078 "includes_rshift_p (operands[2], GEN_INT (255))"
4079 "@
4080 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4081 #"
4082 [(set_attr "type" "delayed_compare")
4083 (set_attr "length" "4,8")])
4085 (define_split
4086 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4087 (compare:CC
4088 (zero_extend:SI
4089 (subreg:QI
4090 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4091 (match_operand:SI 2 "const_int_operand" "")) 0))
4092 (const_int 0)))
4093 (set (match_operand:SI 0 "gpc_reg_operand" "")
4094 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4095 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4096 [(set (match_dup 0)
4097 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4098 (set (match_dup 3)
4099 (compare:CC (match_dup 0)
4100 (const_int 0)))]
4101 "")
4103 (define_insn ""
4104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4105 (zero_extend:SI
4106 (subreg:HI
4107 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4108 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4109 "includes_rshift_p (operands[2], GEN_INT (65535))"
4110 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4112 (define_insn ""
4113 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4114 (compare:CC
4115 (zero_extend:SI
4116 (subreg:HI
4117 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4118 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4119 (const_int 0)))
4120 (clobber (match_scratch:SI 3 "=r,r"))]
4121 "includes_rshift_p (operands[2], GEN_INT (65535))"
4122 "@
4123 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4124 #"
4125 [(set_attr "type" "delayed_compare")
4126 (set_attr "length" "4,8")])
4128 (define_split
4129 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4130 (compare:CC
4131 (zero_extend:SI
4132 (subreg:HI
4133 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "const_int_operand" "")) 0))
4135 (const_int 0)))
4136 (clobber (match_scratch:SI 3 ""))]
4137 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4138 [(set (match_dup 3)
4139 (zero_extend:SI (subreg:HI
4140 (lshiftrt:SI (match_dup 1)
4141 (match_dup 2)) 0)))
4142 (set (match_dup 0)
4143 (compare:CC (match_dup 3)
4144 (const_int 0)))]
4145 "")
4147 (define_insn ""
4148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4149 (compare:CC
4150 (zero_extend:SI
4151 (subreg:HI
4152 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4153 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4154 (const_int 0)))
4155 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4156 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4157 "includes_rshift_p (operands[2], GEN_INT (65535))"
4158 "@
4159 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4160 #"
4161 [(set_attr "type" "delayed_compare")
4162 (set_attr "length" "4,8")])
4164 (define_split
4165 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4166 (compare:CC
4167 (zero_extend:SI
4168 (subreg:HI
4169 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4170 (match_operand:SI 2 "const_int_operand" "")) 0))
4171 (const_int 0)))
4172 (set (match_operand:SI 0 "gpc_reg_operand" "")
4173 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4174 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4175 [(set (match_dup 0)
4176 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4177 (set (match_dup 3)
4178 (compare:CC (match_dup 0)
4179 (const_int 0)))]
4180 "")
4182 (define_insn ""
4183 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4184 (const_int 1)
4185 (match_operand:SI 1 "gpc_reg_operand" "r"))
4186 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4187 (const_int 31)))]
4188 "TARGET_POWER"
4189 "rrib %0,%1,%2")
4191 (define_insn ""
4192 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4193 (const_int 1)
4194 (match_operand:SI 1 "gpc_reg_operand" "r"))
4195 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4196 (const_int 31)))]
4197 "TARGET_POWER"
4198 "rrib %0,%1,%2")
4200 (define_insn ""
4201 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4202 (const_int 1)
4203 (match_operand:SI 1 "gpc_reg_operand" "r"))
4204 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4205 (const_int 1)
4206 (const_int 0)))]
4207 "TARGET_POWER"
4208 "rrib %0,%1,%2")
4210 (define_expand "ashrsi3"
4211 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4212 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4213 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4214 ""
4215 "
4216 {
4217 if (TARGET_POWER)
4218 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4219 else
4220 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4221 DONE;
4222 }")
4224 (define_insn "ashrsi3_power"
4225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4226 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4227 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4228 (clobber (match_scratch:SI 3 "=q,X"))]
4229 "TARGET_POWER"
4230 "@
4231 srea %0,%1,%2
4232 {srai|srawi} %0,%1,%h2")
4234 (define_insn "ashrsi3_no_power"
4235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4236 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4237 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4238 "! TARGET_POWER"
4239 "{sra|sraw}%I2 %0,%1,%h2")
4241 (define_insn ""
4242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4243 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4244 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4245 (const_int 0)))
4246 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4247 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4248 "TARGET_POWER"
4249 "@
4250 srea. %3,%1,%2
4251 {srai.|srawi.} %3,%1,%h2
4252 #
4253 #"
4254 [(set_attr "type" "delayed_compare")
4255 (set_attr "length" "4,4,8,8")])
4257 (define_split
4258 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4259 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4260 (match_operand:SI 2 "reg_or_cint_operand" ""))
4261 (const_int 0)))
4262 (clobber (match_scratch:SI 3 ""))
4263 (clobber (match_scratch:SI 4 ""))]
4264 "TARGET_POWER && reload_completed"
4265 [(parallel [(set (match_dup 3)
4266 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4267 (clobber (match_dup 4))])
4268 (set (match_dup 0)
4269 (compare:CC (match_dup 3)
4270 (const_int 0)))]
4271 "")
4273 (define_insn ""
4274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4275 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4276 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4277 (const_int 0)))
4278 (clobber (match_scratch:SI 3 "=r,r"))]
4279 "! TARGET_POWER"
4280 "@
4281 {sra|sraw}%I2. %3,%1,%h2
4282 #"
4283 [(set_attr "type" "delayed_compare")
4284 (set_attr "length" "4,8")])
4286 (define_split
4287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4288 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4289 (match_operand:SI 2 "reg_or_cint_operand" ""))
4290 (const_int 0)))
4291 (clobber (match_scratch:SI 3 ""))]
4292 "! TARGET_POWER && reload_completed"
4293 [(set (match_dup 3)
4294 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4295 (set (match_dup 0)
4296 (compare:CC (match_dup 3)
4297 (const_int 0)))]
4298 "")
4300 (define_insn ""
4301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4302 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4303 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4304 (const_int 0)))
4305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4306 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4307 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4308 "TARGET_POWER"
4309 "@
4310 srea. %0,%1,%2
4311 {srai.|srawi.} %0,%1,%h2
4312 #
4313 #"
4314 [(set_attr "type" "delayed_compare")
4315 (set_attr "length" "4,4,8,8")])
4317 (define_split
4318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4319 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4320 (match_operand:SI 2 "reg_or_cint_operand" ""))
4321 (const_int 0)))
4322 (set (match_operand:SI 0 "gpc_reg_operand" "")
4323 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4324 (clobber (match_scratch:SI 4 ""))]
4325 "TARGET_POWER && reload_completed"
4326 [(parallel [(set (match_dup 0)
4327 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4328 (clobber (match_dup 4))])
4329 (set (match_dup 3)
4330 (compare:CC (match_dup 0)
4331 (const_int 0)))]
4332 "")
4334 (define_insn ""
4335 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4336 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4337 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4338 (const_int 0)))
4339 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4340 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4341 "! TARGET_POWER"
4342 "@
4343 {sra|sraw}%I2. %0,%1,%h2
4344 #"
4345 [(set_attr "type" "delayed_compare")
4346 (set_attr "length" "4,8")])
4347 \f
4348 (define_split
4349 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4350 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4351 (match_operand:SI 2 "reg_or_cint_operand" ""))
4352 (const_int 0)))
4353 (set (match_operand:SI 0 "gpc_reg_operand" "")
4354 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4355 "! TARGET_POWER && reload_completed"
4356 [(set (match_dup 0)
4357 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4358 (set (match_dup 3)
4359 (compare:CC (match_dup 0)
4360 (const_int 0)))]
4361 "")
4363 ;; Floating-point insns, excluding normal data motion.
4364 ;;
4365 ;; PowerPC has a full set of single-precision floating point instructions.
4366 ;;
4367 ;; For the POWER architecture, we pretend that we have both SFmode and
4368 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4369 ;; The only conversions we will do will be when storing to memory. In that
4370 ;; case, we will use the "frsp" instruction before storing.
4371 ;;
4372 ;; Note that when we store into a single-precision memory location, we need to
4373 ;; use the frsp insn first. If the register being stored isn't dead, we
4374 ;; need a scratch register for the frsp. But this is difficult when the store
4375 ;; is done by reload. It is not incorrect to do the frsp on the register in
4376 ;; this case, we just lose precision that we would have otherwise gotten but
4377 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4379 (define_expand "extendsfdf2"
4380 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4381 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4382 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4383 "")
4385 (define_insn_and_split "*extendsfdf2_fpr"
4386 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4387 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4388 "TARGET_HARD_FLOAT && TARGET_FPRS"
4389 "@
4390 #
4391 fmr %0,%1
4392 lfs%U1%X1 %0,%1"
4393 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4394 [(const_int 0)]
4395 {
4396 emit_note (NOTE_INSN_DELETED);
4397 DONE;
4398 }
4399 [(set_attr "type" "fp,fp,fpload")])
4401 (define_expand "truncdfsf2"
4402 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4403 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4404 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4405 "")
4407 (define_insn "*truncdfsf2_fpr"
4408 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4409 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4410 "TARGET_HARD_FLOAT && TARGET_FPRS"
4411 "frsp %0,%1"
4412 [(set_attr "type" "fp")])
4414 (define_insn "aux_truncdfsf2"
4415 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4416 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4417 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4418 "frsp %0,%1"
4419 [(set_attr "type" "fp")])
4421 (define_expand "negsf2"
4422 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4423 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4424 "TARGET_HARD_FLOAT"
4425 "")
4427 (define_insn "*negsf2"
4428 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4429 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4430 "TARGET_HARD_FLOAT && TARGET_FPRS"
4431 "fneg %0,%1"
4432 [(set_attr "type" "fp")])
4434 (define_expand "abssf2"
4435 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4436 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4437 "TARGET_HARD_FLOAT"
4438 "")
4440 (define_insn "*abssf2"
4441 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4442 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4443 "TARGET_HARD_FLOAT && TARGET_FPRS"
4444 "fabs %0,%1"
4445 [(set_attr "type" "fp")])
4447 (define_insn ""
4448 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4449 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4450 "TARGET_HARD_FLOAT && TARGET_FPRS"
4451 "fnabs %0,%1"
4452 [(set_attr "type" "fp")])
4454 (define_expand "addsf3"
4455 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4456 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4457 (match_operand:SF 2 "gpc_reg_operand" "")))]
4458 "TARGET_HARD_FLOAT"
4459 "")
4461 (define_insn ""
4462 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4463 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4464 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4465 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4466 "fadds %0,%1,%2"
4467 [(set_attr "type" "fp")])
4469 (define_insn ""
4470 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4471 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4472 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4473 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4474 "{fa|fadd} %0,%1,%2"
4475 [(set_attr "type" "fp")])
4477 (define_expand "subsf3"
4478 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4479 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4480 (match_operand:SF 2 "gpc_reg_operand" "")))]
4481 "TARGET_HARD_FLOAT"
4482 "")
4484 (define_insn ""
4485 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4486 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4487 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4488 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4489 "fsubs %0,%1,%2"
4490 [(set_attr "type" "fp")])
4492 (define_insn ""
4493 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4494 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4495 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4496 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4497 "{fs|fsub} %0,%1,%2"
4498 [(set_attr "type" "fp")])
4500 (define_expand "mulsf3"
4501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4502 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4503 (match_operand:SF 2 "gpc_reg_operand" "")))]
4504 "TARGET_HARD_FLOAT"
4505 "")
4507 (define_insn ""
4508 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4509 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4510 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4511 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4512 "fmuls %0,%1,%2"
4513 [(set_attr "type" "fp")])
4515 (define_insn ""
4516 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4517 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4518 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4519 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4520 "{fm|fmul} %0,%1,%2"
4521 [(set_attr "type" "dmul")])
4523 (define_insn "fres"
4524 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4525 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4526 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4527 "fres %0,%1"
4528 [(set_attr "type" "fp")])
4530 (define_expand "divsf3"
4531 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4532 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4533 (match_operand:SF 2 "gpc_reg_operand" "")))]
4534 "TARGET_HARD_FLOAT"
4535 {
4536 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
4537 && flag_finite_math_only && !flag_trapping_math)
4538 {
4539 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
4540 DONE;
4541 }
4542 })
4544 (define_insn ""
4545 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4546 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4547 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4548 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4549 "fdivs %0,%1,%2"
4550 [(set_attr "type" "sdiv")])
4552 (define_insn ""
4553 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4554 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4555 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4556 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4557 "{fd|fdiv} %0,%1,%2"
4558 [(set_attr "type" "ddiv")])
4560 (define_insn ""
4561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4562 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4563 (match_operand:SF 2 "gpc_reg_operand" "f"))
4564 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4565 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4566 "fmadds %0,%1,%2,%3"
4567 [(set_attr "type" "fp")])
4569 (define_insn ""
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f"))
4573 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4574 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4575 "{fma|fmadd} %0,%1,%2,%3"
4576 [(set_attr "type" "dmul")])
4578 (define_insn ""
4579 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4580 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4581 (match_operand:SF 2 "gpc_reg_operand" "f"))
4582 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4583 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4584 "fmsubs %0,%1,%2,%3"
4585 [(set_attr "type" "fp")])
4587 (define_insn ""
4588 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4589 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4590 (match_operand:SF 2 "gpc_reg_operand" "f"))
4591 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4592 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4593 "{fms|fmsub} %0,%1,%2,%3"
4594 [(set_attr "type" "dmul")])
4596 (define_insn ""
4597 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4598 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4599 (match_operand:SF 2 "gpc_reg_operand" "f"))
4600 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4601 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4602 && HONOR_SIGNED_ZEROS (SFmode)"
4603 "fnmadds %0,%1,%2,%3"
4604 [(set_attr "type" "fp")])
4606 (define_insn ""
4607 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4608 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4609 (match_operand:SF 2 "gpc_reg_operand" "f"))
4610 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4611 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4612 && ! HONOR_SIGNED_ZEROS (SFmode)"
4613 "fnmadds %0,%1,%2,%3"
4614 [(set_attr "type" "fp")])
4616 (define_insn ""
4617 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4618 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4619 (match_operand:SF 2 "gpc_reg_operand" "f"))
4620 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4621 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4622 "{fnma|fnmadd} %0,%1,%2,%3"
4623 [(set_attr "type" "dmul")])
4625 (define_insn ""
4626 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4627 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4628 (match_operand:SF 2 "gpc_reg_operand" "f"))
4629 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4630 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4631 && ! HONOR_SIGNED_ZEROS (SFmode)"
4632 "{fnma|fnmadd} %0,%1,%2,%3"
4633 [(set_attr "type" "dmul")])
4635 (define_insn ""
4636 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4637 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4638 (match_operand:SF 2 "gpc_reg_operand" "f"))
4639 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4640 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4641 && HONOR_SIGNED_ZEROS (SFmode)"
4642 "fnmsubs %0,%1,%2,%3"
4643 [(set_attr "type" "fp")])
4645 (define_insn ""
4646 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4647 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4648 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4649 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4650 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4651 && ! HONOR_SIGNED_ZEROS (SFmode)"
4652 "fnmsubs %0,%1,%2,%3"
4653 [(set_attr "type" "fp")])
4655 (define_insn ""
4656 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4657 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4658 (match_operand:SF 2 "gpc_reg_operand" "f"))
4659 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4660 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4661 "{fnms|fnmsub} %0,%1,%2,%3"
4662 [(set_attr "type" "dmul")])
4664 (define_insn ""
4665 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4666 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4667 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4668 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4669 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4670 && ! HONOR_SIGNED_ZEROS (SFmode)"
4671 "{fnms|fnmsub} %0,%1,%2,%3"
4672 [(set_attr "type" "fp")])
4674 (define_expand "sqrtsf2"
4675 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4676 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4677 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4678 "")
4680 (define_insn ""
4681 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4682 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4683 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4684 "fsqrts %0,%1"
4685 [(set_attr "type" "ssqrt")])
4687 (define_insn ""
4688 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4689 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4690 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4691 "fsqrt %0,%1"
4692 [(set_attr "type" "dsqrt")])
4694 (define_expand "copysignsf3"
4695 [(set (match_dup 3)
4696 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4697 (set (match_dup 4)
4698 (neg:SF (abs:SF (match_dup 1))))
4699 (set (match_operand:SF 0 "gpc_reg_operand" "")
4700 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4701 (match_dup 5))
4702 (match_dup 3)
4703 (match_dup 4)))]
4704 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4705 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4706 {
4707 operands[3] = gen_reg_rtx (SFmode);
4708 operands[4] = gen_reg_rtx (SFmode);
4709 operands[5] = CONST0_RTX (SFmode);
4710 })
4712 (define_expand "copysigndf3"
4713 [(set (match_dup 3)
4714 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4715 (set (match_dup 4)
4716 (neg:DF (abs:DF (match_dup 1))))
4717 (set (match_operand:DF 0 "gpc_reg_operand" "")
4718 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4719 (match_dup 5))
4720 (match_dup 3)
4721 (match_dup 4)))]
4722 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4723 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4724 {
4725 operands[3] = gen_reg_rtx (DFmode);
4726 operands[4] = gen_reg_rtx (DFmode);
4727 operands[5] = CONST0_RTX (DFmode);
4728 })
4730 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4731 ;; fsel instruction and some auxiliary computations. Then we just have a
4732 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4733 ;; combine.
4734 (define_expand "smaxsf3"
4735 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4736 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4737 (match_operand:SF 2 "gpc_reg_operand" ""))
4738 (match_dup 1)
4739 (match_dup 2)))]
4740 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4741 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4743 (define_expand "sminsf3"
4744 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4745 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4746 (match_operand:SF 2 "gpc_reg_operand" ""))
4747 (match_dup 2)
4748 (match_dup 1)))]
4749 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4750 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4752 (define_split
4753 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4754 (match_operator:SF 3 "min_max_operator"
4755 [(match_operand:SF 1 "gpc_reg_operand" "")
4756 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4757 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4758 [(const_int 0)]
4759 "
4760 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4761 operands[1], operands[2]);
4762 DONE;
4763 }")
4765 (define_expand "movsicc"
4766 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4767 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4768 (match_operand:SI 2 "gpc_reg_operand" "")
4769 (match_operand:SI 3 "gpc_reg_operand" "")))]
4770 "TARGET_ISEL"
4771 "
4772 {
4773 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4774 DONE;
4775 else
4776 FAIL;
4777 }")
4779 ;; We use the BASE_REGS for the isel input operands because, if rA is
4780 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4781 ;; because we may switch the operands and rB may end up being rA.
4782 ;;
4783 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4784 ;; leave out the mode in operand 4 and use one pattern, but reload can
4785 ;; change the mode underneath our feet and then gets confused trying
4786 ;; to reload the value.
4787 (define_insn "isel_signed"
4788 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4789 (if_then_else:SI
4790 (match_operator 1 "comparison_operator"
4791 [(match_operand:CC 4 "cc_reg_operand" "y")
4792 (const_int 0)])
4793 (match_operand:SI 2 "gpc_reg_operand" "b")
4794 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4795 "TARGET_ISEL"
4796 "*
4797 { return output_isel (operands); }"
4798 [(set_attr "length" "4")])
4800 (define_insn "isel_unsigned"
4801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4802 (if_then_else:SI
4803 (match_operator 1 "comparison_operator"
4804 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4805 (const_int 0)])
4806 (match_operand:SI 2 "gpc_reg_operand" "b")
4807 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4808 "TARGET_ISEL"
4809 "*
4810 { return output_isel (operands); }"
4811 [(set_attr "length" "4")])
4813 (define_expand "movsfcc"
4814 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4815 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4816 (match_operand:SF 2 "gpc_reg_operand" "")
4817 (match_operand:SF 3 "gpc_reg_operand" "")))]
4818 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4819 "
4820 {
4821 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4822 DONE;
4823 else
4824 FAIL;
4825 }")
4827 (define_insn "*fselsfsf4"
4828 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4829 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4830 (match_operand:SF 4 "zero_fp_constant" "F"))
4831 (match_operand:SF 2 "gpc_reg_operand" "f")
4832 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4833 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4834 "fsel %0,%1,%2,%3"
4835 [(set_attr "type" "fp")])
4837 (define_insn "*fseldfsf4"
4838 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4839 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4840 (match_operand:DF 4 "zero_fp_constant" "F"))
4841 (match_operand:SF 2 "gpc_reg_operand" "f")
4842 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4843 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4844 "fsel %0,%1,%2,%3"
4845 [(set_attr "type" "fp")])
4847 (define_expand "negdf2"
4848 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4849 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4850 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4851 "")
4853 (define_insn "*negdf2_fpr"
4854 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4855 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4856 "TARGET_HARD_FLOAT && TARGET_FPRS"
4857 "fneg %0,%1"
4858 [(set_attr "type" "fp")])
4860 (define_expand "absdf2"
4861 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4862 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4863 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4864 "")
4866 (define_insn "*absdf2_fpr"
4867 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4868 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4869 "TARGET_HARD_FLOAT && TARGET_FPRS"
4870 "fabs %0,%1"
4871 [(set_attr "type" "fp")])
4873 (define_insn "*nabsdf2_fpr"
4874 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4875 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4876 "TARGET_HARD_FLOAT && TARGET_FPRS"
4877 "fnabs %0,%1"
4878 [(set_attr "type" "fp")])
4880 (define_expand "adddf3"
4881 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4882 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4883 (match_operand:DF 2 "gpc_reg_operand" "")))]
4884 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4885 "")
4887 (define_insn "*adddf3_fpr"
4888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4889 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4890 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4891 "TARGET_HARD_FLOAT && TARGET_FPRS"
4892 "{fa|fadd} %0,%1,%2"
4893 [(set_attr "type" "fp")])
4895 (define_expand "subdf3"
4896 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4897 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4898 (match_operand:DF 2 "gpc_reg_operand" "")))]
4899 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4900 "")
4902 (define_insn "*subdf3_fpr"
4903 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4904 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4905 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4906 "TARGET_HARD_FLOAT && TARGET_FPRS"
4907 "{fs|fsub} %0,%1,%2"
4908 [(set_attr "type" "fp")])
4910 (define_expand "muldf3"
4911 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4912 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4913 (match_operand:DF 2 "gpc_reg_operand" "")))]
4914 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4915 "")
4917 (define_insn "*muldf3_fpr"
4918 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4919 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4920 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4921 "TARGET_HARD_FLOAT && TARGET_FPRS"
4922 "{fm|fmul} %0,%1,%2"
4923 [(set_attr "type" "dmul")])
4925 (define_insn "fred"
4926 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4927 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4928 "TARGET_POPCNTB && flag_finite_math_only"
4929 "fre %0,%1"
4930 [(set_attr "type" "fp")])
4932 (define_expand "divdf3"
4933 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4934 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4935 (match_operand:DF 2 "gpc_reg_operand" "")))]
4936 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4937 {
4938 if (swdiv && !optimize_size && TARGET_POPCNTB
4939 && flag_finite_math_only && !flag_trapping_math)
4940 {
4941 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
4942 DONE;
4943 }
4944 })
4946 (define_insn "*divdf3_fpr"
4947 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4948 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4949 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4950 "TARGET_HARD_FLOAT && TARGET_FPRS"
4951 "{fd|fdiv} %0,%1,%2"
4952 [(set_attr "type" "ddiv")])
4954 (define_insn ""
4955 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4956 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4957 (match_operand:DF 2 "gpc_reg_operand" "f"))
4958 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4959 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4960 "{fma|fmadd} %0,%1,%2,%3"
4961 [(set_attr "type" "dmul")])
4963 (define_insn ""
4964 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4965 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4966 (match_operand:DF 2 "gpc_reg_operand" "f"))
4967 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4968 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4969 "{fms|fmsub} %0,%1,%2,%3"
4970 [(set_attr "type" "dmul")])
4972 (define_insn ""
4973 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4974 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4975 (match_operand:DF 2 "gpc_reg_operand" "f"))
4976 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4977 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4978 && HONOR_SIGNED_ZEROS (DFmode)"
4979 "{fnma|fnmadd} %0,%1,%2,%3"
4980 [(set_attr "type" "dmul")])
4982 (define_insn ""
4983 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4984 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4985 (match_operand:DF 2 "gpc_reg_operand" "f"))
4986 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4987 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4988 && ! HONOR_SIGNED_ZEROS (DFmode)"
4989 "{fnma|fnmadd} %0,%1,%2,%3"
4990 [(set_attr "type" "dmul")])
4992 (define_insn ""
4993 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4994 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4995 (match_operand:DF 2 "gpc_reg_operand" "f"))
4996 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4997 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4998 && HONOR_SIGNED_ZEROS (DFmode)"
4999 "{fnms|fnmsub} %0,%1,%2,%3"
5000 [(set_attr "type" "dmul")])
5002 (define_insn ""
5003 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5004 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5005 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5006 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5007 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5008 && ! HONOR_SIGNED_ZEROS (DFmode)"
5009 "{fnms|fnmsub} %0,%1,%2,%3"
5010 [(set_attr "type" "dmul")])
5012 (define_insn "sqrtdf2"
5013 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5014 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5015 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5016 "fsqrt %0,%1"
5017 [(set_attr "type" "dsqrt")])
5019 ;; The conditional move instructions allow us to perform max and min
5020 ;; operations even when
5022 (define_expand "smaxdf3"
5023 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5024 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5025 (match_operand:DF 2 "gpc_reg_operand" ""))
5026 (match_dup 1)
5027 (match_dup 2)))]
5028 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5029 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5031 (define_expand "smindf3"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5033 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5034 (match_operand:DF 2 "gpc_reg_operand" ""))
5035 (match_dup 2)
5036 (match_dup 1)))]
5037 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5038 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5040 (define_split
5041 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5042 (match_operator:DF 3 "min_max_operator"
5043 [(match_operand:DF 1 "gpc_reg_operand" "")
5044 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5045 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5046 [(const_int 0)]
5047 "
5048 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5049 operands[1], operands[2]);
5050 DONE;
5051 }")
5053 (define_expand "movdfcc"
5054 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5055 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5056 (match_operand:DF 2 "gpc_reg_operand" "")
5057 (match_operand:DF 3 "gpc_reg_operand" "")))]
5058 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5059 "
5060 {
5061 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5062 DONE;
5063 else
5064 FAIL;
5065 }")
5067 (define_insn "*fseldfdf4"
5068 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5069 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5070 (match_operand:DF 4 "zero_fp_constant" "F"))
5071 (match_operand:DF 2 "gpc_reg_operand" "f")
5072 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5073 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5074 "fsel %0,%1,%2,%3"
5075 [(set_attr "type" "fp")])
5077 (define_insn "*fselsfdf4"
5078 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5079 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5080 (match_operand:SF 4 "zero_fp_constant" "F"))
5081 (match_operand:DF 2 "gpc_reg_operand" "f")
5082 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5083 "TARGET_PPC_GFXOPT"
5084 "fsel %0,%1,%2,%3"
5085 [(set_attr "type" "fp")])
5086 \f
5087 ;; Conversions to and from floating-point.
5089 (define_expand "fixuns_truncsfsi2"
5090 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5091 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5092 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5093 "")
5095 (define_expand "fix_truncsfsi2"
5096 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5097 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5098 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5099 "")
5101 ; For each of these conversions, there is a define_expand, a define_insn
5102 ; with a '#' template, and a define_split (with C code). The idea is
5103 ; to allow constant folding with the template of the define_insn,
5104 ; then to have the insns split later (between sched1 and final).
5106 (define_expand "floatsidf2"
5107 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5108 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5109 (use (match_dup 2))
5110 (use (match_dup 3))
5111 (clobber (match_dup 4))
5112 (clobber (match_dup 5))
5113 (clobber (match_dup 6))])]
5114 "TARGET_HARD_FLOAT && TARGET_FPRS"
5115 "
5116 {
5117 if (TARGET_E500_DOUBLE)
5118 {
5119 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5120 DONE;
5121 }
5122 if (TARGET_POWERPC64)
5123 {
5124 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5125 rtx t1 = gen_reg_rtx (DImode);
5126 rtx t2 = gen_reg_rtx (DImode);
5127 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5128 DONE;
5129 }
5131 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5132 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5133 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5134 operands[5] = gen_reg_rtx (DFmode);
5135 operands[6] = gen_reg_rtx (SImode);
5136 }")
5138 (define_insn_and_split "*floatsidf2_internal"
5139 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5140 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5141 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5142 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5143 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5144 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5145 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5146 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5147 "#"
5148 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5149 [(pc)]
5150 "
5151 {
5152 rtx lowword, highword;
5153 gcc_assert (MEM_P (operands[4]));
5154 highword = adjust_address (operands[4], SImode, 0);
5155 lowword = adjust_address (operands[4], SImode, 4);
5156 if (! WORDS_BIG_ENDIAN)
5157 {
5158 rtx tmp;
5159 tmp = highword; highword = lowword; lowword = tmp;
5160 }
5162 emit_insn (gen_xorsi3 (operands[6], operands[1],
5163 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5164 emit_move_insn (lowword, operands[6]);
5165 emit_move_insn (highword, operands[2]);
5166 emit_move_insn (operands[5], operands[4]);
5167 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5168 DONE;
5169 }"
5170 [(set_attr "length" "24")])
5172 (define_expand "floatunssisf2"
5173 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5174 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5175 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5176 "")
5178 (define_expand "floatunssidf2"
5179 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5180 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5181 (use (match_dup 2))
5182 (use (match_dup 3))
5183 (clobber (match_dup 4))
5184 (clobber (match_dup 5))])]
5185 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5186 "
5187 {
5188 if (TARGET_E500_DOUBLE)
5189 {
5190 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5191 DONE;
5192 }
5193 if (TARGET_POWERPC64)
5194 {
5195 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5196 rtx t1 = gen_reg_rtx (DImode);
5197 rtx t2 = gen_reg_rtx (DImode);
5198 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5199 t1, t2));
5200 DONE;
5201 }
5203 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5204 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5205 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5206 operands[5] = gen_reg_rtx (DFmode);
5207 }")
5209 (define_insn_and_split "*floatunssidf2_internal"
5210 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5211 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5212 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5213 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5214 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5215 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5216 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5217 "#"
5218 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5219 [(pc)]
5220 "
5221 {
5222 rtx lowword, highword;
5223 gcc_assert (MEM_P (operands[4]));
5224 highword = adjust_address (operands[4], SImode, 0);
5225 lowword = adjust_address (operands[4], SImode, 4);
5226 if (! WORDS_BIG_ENDIAN)
5227 {
5228 rtx tmp;
5229 tmp = highword; highword = lowword; lowword = tmp;
5230 }
5232 emit_move_insn (lowword, operands[1]);
5233 emit_move_insn (highword, operands[2]);
5234 emit_move_insn (operands[5], operands[4]);
5235 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5236 DONE;
5237 }"
5238 [(set_attr "length" "20")])
5240 (define_expand "fix_truncdfsi2"
5241 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5242 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5243 (clobber (match_dup 2))
5244 (clobber (match_dup 3))])]
5245 "(TARGET_POWER2 || TARGET_POWERPC)
5246 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5247 "
5248 {
5249 if (TARGET_E500_DOUBLE)
5250 {
5251 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5252 DONE;
5253 }
5254 operands[2] = gen_reg_rtx (DImode);
5255 if (TARGET_PPC_GFXOPT)
5256 {
5257 rtx orig_dest = operands[0];
5258 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5259 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5260 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5261 operands[2]));
5262 if (operands[0] != orig_dest)
5263 emit_move_insn (orig_dest, operands[0]);
5264 DONE;
5265 }
5266 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5267 }")
5269 (define_insn_and_split "*fix_truncdfsi2_internal"
5270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5271 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5272 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5273 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5274 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5275 "#"
5276 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5277 [(pc)]
5278 "
5279 {
5280 rtx lowword;
5281 gcc_assert (MEM_P (operands[3]));
5282 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5284 emit_insn (gen_fctiwz (operands[2], operands[1]));
5285 emit_move_insn (operands[3], operands[2]);
5286 emit_move_insn (operands[0], lowword);
5287 DONE;
5288 }"
5289 [(set_attr "length" "16")])
5291 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5292 [(set (match_operand:SI 0 "memory_operand" "=Z")
5293 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5294 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5295 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5296 && TARGET_PPC_GFXOPT"
5297 "#"
5298 "&& 1"
5299 [(pc)]
5300 "
5301 {
5302 emit_insn (gen_fctiwz (operands[2], operands[1]));
5303 emit_insn (gen_stfiwx (operands[0], operands[2]));
5304 DONE;
5305 }"
5306 [(set_attr "length" "16")])
5308 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5309 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5310 ; because the first makes it clear that operand 0 is not live
5311 ; before the instruction.
5312 (define_insn "fctiwz"
5313 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5314 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5315 UNSPEC_FCTIWZ))]
5316 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5317 "{fcirz|fctiwz} %0,%1"
5318 [(set_attr "type" "fp")])
5320 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5321 (define_insn "stfiwx"
5322 [(set (match_operand:SI 0 "memory_operand" "=Z")
5323 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5324 UNSPEC_STFIWX))]
5325 "TARGET_PPC_GFXOPT"
5326 "stfiwx %1,%y0"
5327 [(set_attr "type" "fpstore")])
5329 (define_expand "floatsisf2"
5330 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5331 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5332 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5333 "")
5335 (define_insn "floatdidf2"
5336 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5337 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5338 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5339 "fcfid %0,%1"
5340 [(set_attr "type" "fp")])
5342 (define_insn_and_split "floatsidf_ppc64"
5343 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5344 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5345 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5346 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5347 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5348 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5349 "#"
5350 "&& 1"
5351 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5352 (set (match_dup 2) (match_dup 3))
5353 (set (match_dup 4) (match_dup 2))
5354 (set (match_dup 0) (float:DF (match_dup 4)))]
5355 "")
5357 (define_insn_and_split "floatunssidf_ppc64"
5358 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5359 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5360 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5361 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5362 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5363 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5364 "#"
5365 "&& 1"
5366 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5367 (set (match_dup 2) (match_dup 3))
5368 (set (match_dup 4) (match_dup 2))
5369 (set (match_dup 0) (float:DF (match_dup 4)))]
5370 "")
5372 (define_insn "fix_truncdfdi2"
5373 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5374 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5375 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5376 "fctidz %0,%1"
5377 [(set_attr "type" "fp")])
5379 (define_expand "floatdisf2"
5380 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5381 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5382 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5383 "
5384 {
5385 rtx val = operands[1];
5386 if (!flag_unsafe_math_optimizations)
5387 {
5388 rtx label = gen_label_rtx ();
5389 val = gen_reg_rtx (DImode);
5390 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5391 emit_label (label);
5392 }
5393 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5394 DONE;
5395 }")
5397 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5398 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5399 ;; from double rounding.
5400 (define_insn_and_split "floatdisf2_internal1"
5401 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5402 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5403 (clobber (match_scratch:DF 2 "=f"))]
5404 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5405 "#"
5406 "&& reload_completed"
5407 [(set (match_dup 2)
5408 (float:DF (match_dup 1)))
5409 (set (match_dup 0)
5410 (float_truncate:SF (match_dup 2)))]
5411 "")
5413 ;; Twiddles bits to avoid double rounding.
5414 ;; Bits that might be truncated when converting to DFmode are replaced
5415 ;; by a bit that won't be lost at that stage, but is below the SFmode
5416 ;; rounding position.
5417 (define_expand "floatdisf2_internal2"
5418 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5419 (const_int 53)))
5420 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5421 (const_int 2047)))
5422 (clobber (scratch:CC))])
5423 (set (match_dup 3) (plus:DI (match_dup 3)
5424 (const_int 1)))
5425 (set (match_dup 0) (plus:DI (match_dup 0)
5426 (const_int 2047)))
5427 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5428 (const_int 3)))
5429 (set (match_dup 0) (ior:DI (match_dup 0)
5430 (match_dup 1)))
5431 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5432 (const_int -2048)))
5433 (clobber (scratch:CC))])
5434 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5435 (label_ref (match_operand:DI 2 "" ""))
5436 (pc)))
5437 (set (match_dup 0) (match_dup 1))]
5438 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5439 "
5440 {
5441 operands[3] = gen_reg_rtx (DImode);
5442 operands[4] = gen_reg_rtx (CCUNSmode);
5443 }")
5444 \f
5445 ;; Define the DImode operations that can be done in a small number
5446 ;; of instructions. The & constraints are to prevent the register
5447 ;; allocator from allocating registers that overlap with the inputs
5448 ;; (for example, having an input in 7,8 and an output in 6,7). We
5449 ;; also allow for the output being the same as one of the inputs.
5451 (define_insn "*adddi3_noppc64"
5452 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5453 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5454 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5455 "! TARGET_POWERPC64"
5456 "*
5457 {
5458 if (WORDS_BIG_ENDIAN)
5459 return (GET_CODE (operands[2])) != CONST_INT
5460 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5461 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5462 else
5463 return (GET_CODE (operands[2])) != CONST_INT
5464 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5465 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5466 }"
5467 [(set_attr "type" "two")
5468 (set_attr "length" "8")])
5470 (define_insn "*subdi3_noppc64"
5471 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5472 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5473 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5474 "! TARGET_POWERPC64"
5475 "*
5476 {
5477 if (WORDS_BIG_ENDIAN)
5478 return (GET_CODE (operands[1]) != CONST_INT)
5479 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5480 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5481 else
5482 return (GET_CODE (operands[1]) != CONST_INT)
5483 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5484 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5485 }"
5486 [(set_attr "type" "two")
5487 (set_attr "length" "8")])
5489 (define_insn "*negdi2_noppc64"
5490 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5491 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5492 "! TARGET_POWERPC64"
5493 "*
5494 {
5495 return (WORDS_BIG_ENDIAN)
5496 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5497 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5498 }"
5499 [(set_attr "type" "two")
5500 (set_attr "length" "8")])
5502 (define_expand "mulsidi3"
5503 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5504 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5505 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5506 "! TARGET_POWERPC64"
5507 "
5508 {
5509 if (! TARGET_POWER && ! TARGET_POWERPC)
5510 {
5511 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5512 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5513 emit_insn (gen_mull_call ());
5514 if (WORDS_BIG_ENDIAN)
5515 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5516 else
5517 {
5518 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5519 gen_rtx_REG (SImode, 3));
5520 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5521 gen_rtx_REG (SImode, 4));
5522 }
5523 DONE;
5524 }
5525 else if (TARGET_POWER)
5526 {
5527 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5528 DONE;
5529 }
5530 }")
5532 (define_insn "mulsidi3_mq"
5533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5534 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5535 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5536 (clobber (match_scratch:SI 3 "=q"))]
5537 "TARGET_POWER"
5538 "mul %0,%1,%2\;mfmq %L0"
5539 [(set_attr "type" "imul")
5540 (set_attr "length" "8")])
5542 (define_insn "*mulsidi3_no_mq"
5543 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5544 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5545 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5546 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5547 "*
5548 {
5549 return (WORDS_BIG_ENDIAN)
5550 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5551 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5552 }"
5553 [(set_attr "type" "imul")
5554 (set_attr "length" "8")])
5556 (define_split
5557 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5558 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5559 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5560 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5561 [(set (match_dup 3)
5562 (truncate:SI
5563 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5564 (sign_extend:DI (match_dup 2)))
5565 (const_int 32))))
5566 (set (match_dup 4)
5567 (mult:SI (match_dup 1)
5568 (match_dup 2)))]
5569 "
5570 {
5571 int endian = (WORDS_BIG_ENDIAN == 0);
5572 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5573 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5574 }")
5576 (define_expand "umulsidi3"
5577 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5578 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5579 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5580 "TARGET_POWERPC && ! TARGET_POWERPC64"
5581 "
5582 {
5583 if (TARGET_POWER)
5584 {
5585 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5586 DONE;
5587 }
5588 }")
5590 (define_insn "umulsidi3_mq"
5591 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5592 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5593 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5594 (clobber (match_scratch:SI 3 "=q"))]
5595 "TARGET_POWERPC && TARGET_POWER"
5596 "*
5597 {
5598 return (WORDS_BIG_ENDIAN)
5599 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5600 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5601 }"
5602 [(set_attr "type" "imul")
5603 (set_attr "length" "8")])
5605 (define_insn "*umulsidi3_no_mq"
5606 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5607 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5608 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5609 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5610 "*
5611 {
5612 return (WORDS_BIG_ENDIAN)
5613 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5614 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5615 }"
5616 [(set_attr "type" "imul")
5617 (set_attr "length" "8")])
5619 (define_split
5620 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5621 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5622 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5623 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5624 [(set (match_dup 3)
5625 (truncate:SI
5626 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5627 (zero_extend:DI (match_dup 2)))
5628 (const_int 32))))
5629 (set (match_dup 4)
5630 (mult:SI (match_dup 1)
5631 (match_dup 2)))]
5632 "
5633 {
5634 int endian = (WORDS_BIG_ENDIAN == 0);
5635 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5636 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5637 }")
5639 (define_expand "smulsi3_highpart"
5640 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5641 (truncate:SI
5642 (lshiftrt:DI (mult:DI (sign_extend:DI
5643 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5644 (sign_extend:DI
5645 (match_operand:SI 2 "gpc_reg_operand" "r")))
5646 (const_int 32))))]
5647 ""
5648 "
5649 {
5650 if (! TARGET_POWER && ! TARGET_POWERPC)
5651 {
5652 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5653 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5654 emit_insn (gen_mulh_call ());
5655 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5656 DONE;
5657 }
5658 else if (TARGET_POWER)
5659 {
5660 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5661 DONE;
5662 }
5663 }")
5665 (define_insn "smulsi3_highpart_mq"
5666 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5667 (truncate:SI
5668 (lshiftrt:DI (mult:DI (sign_extend:DI
5669 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5670 (sign_extend:DI
5671 (match_operand:SI 2 "gpc_reg_operand" "r")))
5672 (const_int 32))))
5673 (clobber (match_scratch:SI 3 "=q"))]
5674 "TARGET_POWER"
5675 "mul %0,%1,%2"
5676 [(set_attr "type" "imul")])
5678 (define_insn "*smulsi3_highpart_no_mq"
5679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5680 (truncate:SI
5681 (lshiftrt:DI (mult:DI (sign_extend:DI
5682 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5683 (sign_extend:DI
5684 (match_operand:SI 2 "gpc_reg_operand" "r")))
5685 (const_int 32))))]
5686 "TARGET_POWERPC && ! TARGET_POWER"
5687 "mulhw %0,%1,%2"
5688 [(set_attr "type" "imul")])
5690 (define_expand "umulsi3_highpart"
5691 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5692 (truncate:SI
5693 (lshiftrt:DI (mult:DI (zero_extend:DI
5694 (match_operand:SI 1 "gpc_reg_operand" ""))
5695 (zero_extend:DI
5696 (match_operand:SI 2 "gpc_reg_operand" "")))
5697 (const_int 32))))]
5698 "TARGET_POWERPC"
5699 "
5700 {
5701 if (TARGET_POWER)
5702 {
5703 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5704 DONE;
5705 }
5706 }")
5708 (define_insn "umulsi3_highpart_mq"
5709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5710 (truncate:SI
5711 (lshiftrt:DI (mult:DI (zero_extend:DI
5712 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5713 (zero_extend:DI
5714 (match_operand:SI 2 "gpc_reg_operand" "r")))
5715 (const_int 32))))
5716 (clobber (match_scratch:SI 3 "=q"))]
5717 "TARGET_POWERPC && TARGET_POWER"
5718 "mulhwu %0,%1,%2"
5719 [(set_attr "type" "imul")])
5721 (define_insn "*umulsi3_highpart_no_mq"
5722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5723 (truncate:SI
5724 (lshiftrt:DI (mult:DI (zero_extend:DI
5725 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5726 (zero_extend:DI
5727 (match_operand:SI 2 "gpc_reg_operand" "r")))
5728 (const_int 32))))]
5729 "TARGET_POWERPC && ! TARGET_POWER"
5730 "mulhwu %0,%1,%2"
5731 [(set_attr "type" "imul")])
5733 ;; If operands 0 and 2 are in the same register, we have a problem. But
5734 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5735 ;; why we have the strange constraints below.
5736 (define_insn "ashldi3_power"
5737 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5738 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5739 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5740 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5741 "TARGET_POWER"
5742 "@
5743 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5744 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5745 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5746 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5747 [(set_attr "length" "8")])
5749 (define_insn "lshrdi3_power"
5750 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5751 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5752 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5753 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5754 "TARGET_POWER"
5755 "@
5756 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5757 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5758 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5759 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5760 [(set_attr "length" "8")])
5762 ;; Shift by a variable amount is too complex to be worth open-coding. We
5763 ;; just handle shifts by constants.
5764 (define_insn "ashrdi3_power"
5765 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5766 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5767 (match_operand:SI 2 "const_int_operand" "M,i")))
5768 (clobber (match_scratch:SI 3 "=X,q"))]
5769 "TARGET_POWER"
5770 "@
5771 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5772 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5773 [(set_attr "length" "8")])
5775 (define_insn "ashrdi3_no_power"
5776 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5777 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5778 (match_operand:SI 2 "const_int_operand" "M,i")))]
5779 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5780 "@
5781 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5782 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5783 [(set_attr "type" "two,three")
5784 (set_attr "length" "8,12")])
5786 (define_insn "*ashrdisi3_noppc64"
5787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5788 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5789 (const_int 32)) 4))]
5790 "TARGET_32BIT && !TARGET_POWERPC64"
5791 "*
5792 {
5793 if (REGNO (operands[0]) == REGNO (operands[1]))
5794 return \"\";
5795 else
5796 return \"mr %0,%1\";
5797 }"
5798 [(set_attr "length" "4")])
5800 \f
5801 ;; PowerPC64 DImode operations.
5803 (define_insn_and_split "absdi2"
5804 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5805 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5806 (clobber (match_scratch:DI 2 "=&r,&r"))]
5807 "TARGET_POWERPC64"
5808 "#"
5809 "&& reload_completed"
5810 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5811 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5812 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5813 "")
5815 (define_insn_and_split "*nabsdi2"
5816 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5817 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5818 (clobber (match_scratch:DI 2 "=&r,&r"))]
5819 "TARGET_POWERPC64"
5820 "#"
5821 "&& reload_completed"
5822 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5823 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5824 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5825 "")
5827 (define_insn "muldi3"
5828 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5829 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5830 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5831 "TARGET_POWERPC64"
5832 "mulld %0,%1,%2"
5833 [(set_attr "type" "lmul")])
5835 (define_insn "*muldi3_internal1"
5836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5837 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5838 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5839 (const_int 0)))
5840 (clobber (match_scratch:DI 3 "=r,r"))]
5841 "TARGET_POWERPC64"
5842 "@
5843 mulld. %3,%1,%2
5844 #"
5845 [(set_attr "type" "lmul_compare")
5846 (set_attr "length" "4,8")])
5848 (define_split
5849 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5850 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5851 (match_operand:DI 2 "gpc_reg_operand" ""))
5852 (const_int 0)))
5853 (clobber (match_scratch:DI 3 ""))]
5854 "TARGET_POWERPC64 && reload_completed"
5855 [(set (match_dup 3)
5856 (mult:DI (match_dup 1) (match_dup 2)))
5857 (set (match_dup 0)
5858 (compare:CC (match_dup 3)
5859 (const_int 0)))]
5860 "")
5862 (define_insn "*muldi3_internal2"
5863 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5864 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5865 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5866 (const_int 0)))
5867 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5868 (mult:DI (match_dup 1) (match_dup 2)))]
5869 "TARGET_POWERPC64"
5870 "@
5871 mulld. %0,%1,%2
5872 #"
5873 [(set_attr "type" "lmul_compare")
5874 (set_attr "length" "4,8")])
5876 (define_split
5877 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5878 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5879 (match_operand:DI 2 "gpc_reg_operand" ""))
5880 (const_int 0)))
5881 (set (match_operand:DI 0 "gpc_reg_operand" "")
5882 (mult:DI (match_dup 1) (match_dup 2)))]
5883 "TARGET_POWERPC64 && reload_completed"
5884 [(set (match_dup 0)
5885 (mult:DI (match_dup 1) (match_dup 2)))
5886 (set (match_dup 3)
5887 (compare:CC (match_dup 0)
5888 (const_int 0)))]
5889 "")
5891 (define_insn "smuldi3_highpart"
5892 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5893 (truncate:DI
5894 (lshiftrt:TI (mult:TI (sign_extend:TI
5895 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5896 (sign_extend:TI
5897 (match_operand:DI 2 "gpc_reg_operand" "r")))
5898 (const_int 64))))]
5899 "TARGET_POWERPC64"
5900 "mulhd %0,%1,%2"
5901 [(set_attr "type" "lmul")])
5903 (define_insn "umuldi3_highpart"
5904 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5905 (truncate:DI
5906 (lshiftrt:TI (mult:TI (zero_extend:TI
5907 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5908 (zero_extend:TI
5909 (match_operand:DI 2 "gpc_reg_operand" "r")))
5910 (const_int 64))))]
5911 "TARGET_POWERPC64"
5912 "mulhdu %0,%1,%2"
5913 [(set_attr "type" "lmul")])
5915 (define_insn "rotldi3"
5916 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5917 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5918 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
5919 "TARGET_POWERPC64"
5920 "rld%I2cl %0,%1,%H2,0")
5922 (define_insn "*rotldi3_internal2"
5923 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5924 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5925 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5926 (const_int 0)))
5927 (clobber (match_scratch:DI 3 "=r,r"))]
5928 "TARGET_64BIT"
5929 "@
5930 rld%I2cl. %3,%1,%H2,0
5931 #"
5932 [(set_attr "type" "delayed_compare")
5933 (set_attr "length" "4,8")])
5935 (define_split
5936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5937 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
5938 (match_operand:DI 2 "reg_or_cint_operand" ""))
5939 (const_int 0)))
5940 (clobber (match_scratch:DI 3 ""))]
5941 "TARGET_POWERPC64 && reload_completed"
5942 [(set (match_dup 3)
5943 (rotate:DI (match_dup 1) (match_dup 2)))
5944 (set (match_dup 0)
5945 (compare:CC (match_dup 3)
5946 (const_int 0)))]
5947 "")
5949 (define_insn "*rotldi3_internal3"
5950 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5951 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5952 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5953 (const_int 0)))
5954 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5955 (rotate:DI (match_dup 1) (match_dup 2)))]
5956 "TARGET_64BIT"
5957 "@
5958 rld%I2cl. %0,%1,%H2,0
5959 #"
5960 [(set_attr "type" "delayed_compare")
5961 (set_attr "length" "4,8")])
5963 (define_split
5964 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5965 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
5966 (match_operand:DI 2 "reg_or_cint_operand" ""))
5967 (const_int 0)))
5968 (set (match_operand:DI 0 "gpc_reg_operand" "")
5969 (rotate:DI (match_dup 1) (match_dup 2)))]
5970 "TARGET_POWERPC64 && reload_completed"
5971 [(set (match_dup 0)
5972 (rotate:DI (match_dup 1) (match_dup 2)))
5973 (set (match_dup 3)
5974 (compare:CC (match_dup 0)
5975 (const_int 0)))]
5976 "")
5978 (define_insn "*rotldi3_internal4"
5979 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5980 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5981 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
5982 (match_operand:DI 3 "mask64_operand" "n")))]
5983 "TARGET_POWERPC64"
5984 "rld%I2c%B3 %0,%1,%H2,%S3")
5986 (define_insn "*rotldi3_internal5"
5987 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5988 (compare:CC (and:DI
5989 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5990 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5991 (match_operand:DI 3 "mask64_operand" "n,n"))
5992 (const_int 0)))
5993 (clobber (match_scratch:DI 4 "=r,r"))]
5994 "TARGET_64BIT"
5995 "@
5996 rld%I2c%B3. %4,%1,%H2,%S3
5997 #"
5998 [(set_attr "type" "delayed_compare")
5999 (set_attr "length" "4,8")])
6001 (define_split
6002 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6003 (compare:CC (and:DI
6004 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6005 (match_operand:DI 2 "reg_or_cint_operand" ""))
6006 (match_operand:DI 3 "mask64_operand" ""))
6007 (const_int 0)))
6008 (clobber (match_scratch:DI 4 ""))]
6009 "TARGET_POWERPC64 && reload_completed"
6010 [(set (match_dup 4)
6011 (and:DI (rotate:DI (match_dup 1)
6012 (match_dup 2))
6013 (match_dup 3)))
6014 (set (match_dup 0)
6015 (compare:CC (match_dup 4)
6016 (const_int 0)))]
6017 "")
6019 (define_insn "*rotldi3_internal6"
6020 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6021 (compare:CC (and:DI
6022 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6023 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6024 (match_operand:DI 3 "mask64_operand" "n,n"))
6025 (const_int 0)))
6026 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6027 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6028 "TARGET_64BIT"
6029 "@
6030 rld%I2c%B3. %0,%1,%H2,%S3
6031 #"
6032 [(set_attr "type" "delayed_compare")
6033 (set_attr "length" "4,8")])
6035 (define_split
6036 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6037 (compare:CC (and:DI
6038 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6039 (match_operand:DI 2 "reg_or_cint_operand" ""))
6040 (match_operand:DI 3 "mask64_operand" ""))
6041 (const_int 0)))
6042 (set (match_operand:DI 0 "gpc_reg_operand" "")
6043 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6044 "TARGET_POWERPC64 && reload_completed"
6045 [(set (match_dup 0)
6046 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6047 (set (match_dup 4)
6048 (compare:CC (match_dup 0)
6049 (const_int 0)))]
6050 "")
6052 (define_insn "*rotldi3_internal7"
6053 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6054 (zero_extend:DI
6055 (subreg:QI
6056 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6057 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6058 "TARGET_POWERPC64"
6059 "rld%I2cl %0,%1,%H2,56")
6061 (define_insn "*rotldi3_internal8"
6062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6063 (compare:CC (zero_extend:DI
6064 (subreg:QI
6065 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6066 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6067 (const_int 0)))
6068 (clobber (match_scratch:DI 3 "=r,r"))]
6069 "TARGET_64BIT"
6070 "@
6071 rld%I2cl. %3,%1,%H2,56
6072 #"
6073 [(set_attr "type" "delayed_compare")
6074 (set_attr "length" "4,8")])
6076 (define_split
6077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6078 (compare:CC (zero_extend:DI
6079 (subreg:QI
6080 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6081 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6082 (const_int 0)))
6083 (clobber (match_scratch:DI 3 ""))]
6084 "TARGET_POWERPC64 && reload_completed"
6085 [(set (match_dup 3)
6086 (zero_extend:DI (subreg:QI
6087 (rotate:DI (match_dup 1)
6088 (match_dup 2)) 0)))
6089 (set (match_dup 0)
6090 (compare:CC (match_dup 3)
6091 (const_int 0)))]
6092 "")
6094 (define_insn "*rotldi3_internal9"
6095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6096 (compare:CC (zero_extend:DI
6097 (subreg:QI
6098 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6099 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6100 (const_int 0)))
6101 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6102 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6103 "TARGET_64BIT"
6104 "@
6105 rld%I2cl. %0,%1,%H2,56
6106 #"
6107 [(set_attr "type" "delayed_compare")
6108 (set_attr "length" "4,8")])
6110 (define_split
6111 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6112 (compare:CC (zero_extend:DI
6113 (subreg:QI
6114 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6115 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6116 (const_int 0)))
6117 (set (match_operand:DI 0 "gpc_reg_operand" "")
6118 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6119 "TARGET_POWERPC64 && reload_completed"
6120 [(set (match_dup 0)
6121 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6122 (set (match_dup 3)
6123 (compare:CC (match_dup 0)
6124 (const_int 0)))]
6125 "")
6127 (define_insn "*rotldi3_internal10"
6128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6129 (zero_extend:DI
6130 (subreg:HI
6131 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6132 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6133 "TARGET_POWERPC64"
6134 "rld%I2cl %0,%1,%H2,48")
6136 (define_insn "*rotldi3_internal11"
6137 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6138 (compare:CC (zero_extend:DI
6139 (subreg:HI
6140 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6141 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6142 (const_int 0)))
6143 (clobber (match_scratch:DI 3 "=r,r"))]
6144 "TARGET_64BIT"
6145 "@
6146 rld%I2cl. %3,%1,%H2,48
6147 #"
6148 [(set_attr "type" "delayed_compare")
6149 (set_attr "length" "4,8")])
6151 (define_split
6152 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6153 (compare:CC (zero_extend:DI
6154 (subreg:HI
6155 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6156 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6157 (const_int 0)))
6158 (clobber (match_scratch:DI 3 ""))]
6159 "TARGET_POWERPC64 && reload_completed"
6160 [(set (match_dup 3)
6161 (zero_extend:DI (subreg:HI
6162 (rotate:DI (match_dup 1)
6163 (match_dup 2)) 0)))
6164 (set (match_dup 0)
6165 (compare:CC (match_dup 3)
6166 (const_int 0)))]
6167 "")
6169 (define_insn "*rotldi3_internal12"
6170 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6171 (compare:CC (zero_extend:DI
6172 (subreg:HI
6173 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6174 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6175 (const_int 0)))
6176 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6177 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6178 "TARGET_64BIT"
6179 "@
6180 rld%I2cl. %0,%1,%H2,48
6181 #"
6182 [(set_attr "type" "delayed_compare")
6183 (set_attr "length" "4,8")])
6185 (define_split
6186 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6187 (compare:CC (zero_extend:DI
6188 (subreg:HI
6189 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6190 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6191 (const_int 0)))
6192 (set (match_operand:DI 0 "gpc_reg_operand" "")
6193 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6194 "TARGET_POWERPC64 && reload_completed"
6195 [(set (match_dup 0)
6196 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6197 (set (match_dup 3)
6198 (compare:CC (match_dup 0)
6199 (const_int 0)))]
6200 "")
6202 (define_insn "*rotldi3_internal13"
6203 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6204 (zero_extend:DI
6205 (subreg:SI
6206 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6207 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6208 "TARGET_POWERPC64"
6209 "rld%I2cl %0,%1,%H2,32")
6211 (define_insn "*rotldi3_internal14"
6212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6213 (compare:CC (zero_extend:DI
6214 (subreg:SI
6215 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6216 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6217 (const_int 0)))
6218 (clobber (match_scratch:DI 3 "=r,r"))]
6219 "TARGET_64BIT"
6220 "@
6221 rld%I2cl. %3,%1,%H2,32
6222 #"
6223 [(set_attr "type" "delayed_compare")
6224 (set_attr "length" "4,8")])
6226 (define_split
6227 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6228 (compare:CC (zero_extend:DI
6229 (subreg:SI
6230 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6231 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6232 (const_int 0)))
6233 (clobber (match_scratch:DI 3 ""))]
6234 "TARGET_POWERPC64 && reload_completed"
6235 [(set (match_dup 3)
6236 (zero_extend:DI (subreg:SI
6237 (rotate:DI (match_dup 1)
6238 (match_dup 2)) 0)))
6239 (set (match_dup 0)
6240 (compare:CC (match_dup 3)
6241 (const_int 0)))]
6242 "")
6244 (define_insn "*rotldi3_internal15"
6245 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6246 (compare:CC (zero_extend:DI
6247 (subreg:SI
6248 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6249 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6250 (const_int 0)))
6251 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6252 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6253 "TARGET_64BIT"
6254 "@
6255 rld%I2cl. %0,%1,%H2,32
6256 #"
6257 [(set_attr "type" "delayed_compare")
6258 (set_attr "length" "4,8")])
6260 (define_split
6261 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6262 (compare:CC (zero_extend:DI
6263 (subreg:SI
6264 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6265 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6266 (const_int 0)))
6267 (set (match_operand:DI 0 "gpc_reg_operand" "")
6268 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6269 "TARGET_POWERPC64 && reload_completed"
6270 [(set (match_dup 0)
6271 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6272 (set (match_dup 3)
6273 (compare:CC (match_dup 0)
6274 (const_int 0)))]
6275 "")
6277 (define_expand "ashldi3"
6278 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6279 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6280 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6281 "TARGET_POWERPC64 || TARGET_POWER"
6282 "
6283 {
6284 if (TARGET_POWERPC64)
6285 ;
6286 else if (TARGET_POWER)
6287 {
6288 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6289 DONE;
6290 }
6291 else
6292 FAIL;
6293 }")
6295 (define_insn "*ashldi3_internal1"
6296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6297 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6298 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6299 "TARGET_POWERPC64"
6300 "sld%I2 %0,%1,%H2")
6302 (define_insn "*ashldi3_internal2"
6303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6304 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6305 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6306 (const_int 0)))
6307 (clobber (match_scratch:DI 3 "=r,r"))]
6308 "TARGET_64BIT"
6309 "@
6310 sld%I2. %3,%1,%H2
6311 #"
6312 [(set_attr "type" "delayed_compare")
6313 (set_attr "length" "4,8")])
6315 (define_split
6316 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6317 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6318 (match_operand:SI 2 "reg_or_cint_operand" ""))
6319 (const_int 0)))
6320 (clobber (match_scratch:DI 3 ""))]
6321 "TARGET_POWERPC64 && reload_completed"
6322 [(set (match_dup 3)
6323 (ashift:DI (match_dup 1) (match_dup 2)))
6324 (set (match_dup 0)
6325 (compare:CC (match_dup 3)
6326 (const_int 0)))]
6327 "")
6329 (define_insn "*ashldi3_internal3"
6330 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6331 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6332 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6333 (const_int 0)))
6334 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6335 (ashift:DI (match_dup 1) (match_dup 2)))]
6336 "TARGET_64BIT"
6337 "@
6338 sld%I2. %0,%1,%H2
6339 #"
6340 [(set_attr "type" "delayed_compare")
6341 (set_attr "length" "4,8")])
6343 (define_split
6344 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6345 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6346 (match_operand:SI 2 "reg_or_cint_operand" ""))
6347 (const_int 0)))
6348 (set (match_operand:DI 0 "gpc_reg_operand" "")
6349 (ashift:DI (match_dup 1) (match_dup 2)))]
6350 "TARGET_POWERPC64 && reload_completed"
6351 [(set (match_dup 0)
6352 (ashift:DI (match_dup 1) (match_dup 2)))
6353 (set (match_dup 3)
6354 (compare:CC (match_dup 0)
6355 (const_int 0)))]
6356 "")
6358 (define_insn "*ashldi3_internal4"
6359 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6360 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6361 (match_operand:SI 2 "const_int_operand" "i"))
6362 (match_operand:DI 3 "const_int_operand" "n")))]
6363 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6364 "rldic %0,%1,%H2,%W3")
6366 (define_insn "ashldi3_internal5"
6367 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6368 (compare:CC
6369 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6370 (match_operand:SI 2 "const_int_operand" "i,i"))
6371 (match_operand:DI 3 "const_int_operand" "n,n"))
6372 (const_int 0)))
6373 (clobber (match_scratch:DI 4 "=r,r"))]
6374 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6375 "@
6376 rldic. %4,%1,%H2,%W3
6377 #"
6378 [(set_attr "type" "delayed_compare")
6379 (set_attr "length" "4,8")])
6381 (define_split
6382 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6383 (compare:CC
6384 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6385 (match_operand:SI 2 "const_int_operand" ""))
6386 (match_operand:DI 3 "const_int_operand" ""))
6387 (const_int 0)))
6388 (clobber (match_scratch:DI 4 ""))]
6389 "TARGET_POWERPC64 && reload_completed
6390 && includes_rldic_lshift_p (operands[2], operands[3])"
6391 [(set (match_dup 4)
6392 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6393 (match_dup 3)))
6394 (set (match_dup 0)
6395 (compare:CC (match_dup 4)
6396 (const_int 0)))]
6397 "")
6399 (define_insn "*ashldi3_internal6"
6400 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6401 (compare:CC
6402 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6403 (match_operand:SI 2 "const_int_operand" "i,i"))
6404 (match_operand:DI 3 "const_int_operand" "n,n"))
6405 (const_int 0)))
6406 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6407 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6408 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6409 "@
6410 rldic. %0,%1,%H2,%W3
6411 #"
6412 [(set_attr "type" "delayed_compare")
6413 (set_attr "length" "4,8")])
6415 (define_split
6416 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6417 (compare:CC
6418 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6419 (match_operand:SI 2 "const_int_operand" ""))
6420 (match_operand:DI 3 "const_int_operand" ""))
6421 (const_int 0)))
6422 (set (match_operand:DI 0 "gpc_reg_operand" "")
6423 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6424 "TARGET_POWERPC64 && reload_completed
6425 && includes_rldic_lshift_p (operands[2], operands[3])"
6426 [(set (match_dup 0)
6427 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6428 (match_dup 3)))
6429 (set (match_dup 4)
6430 (compare:CC (match_dup 0)
6431 (const_int 0)))]
6432 "")
6434 (define_insn "*ashldi3_internal7"
6435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6436 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6437 (match_operand:SI 2 "const_int_operand" "i"))
6438 (match_operand:DI 3 "mask64_operand" "n")))]
6439 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6440 "rldicr %0,%1,%H2,%S3")
6442 (define_insn "ashldi3_internal8"
6443 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6444 (compare:CC
6445 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6446 (match_operand:SI 2 "const_int_operand" "i,i"))
6447 (match_operand:DI 3 "mask64_operand" "n,n"))
6448 (const_int 0)))
6449 (clobber (match_scratch:DI 4 "=r,r"))]
6450 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6451 "@
6452 rldicr. %4,%1,%H2,%S3
6453 #"
6454 [(set_attr "type" "delayed_compare")
6455 (set_attr "length" "4,8")])
6457 (define_split
6458 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6459 (compare:CC
6460 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6461 (match_operand:SI 2 "const_int_operand" ""))
6462 (match_operand:DI 3 "mask64_operand" ""))
6463 (const_int 0)))
6464 (clobber (match_scratch:DI 4 ""))]
6465 "TARGET_POWERPC64 && reload_completed
6466 && includes_rldicr_lshift_p (operands[2], operands[3])"
6467 [(set (match_dup 4)
6468 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6469 (match_dup 3)))
6470 (set (match_dup 0)
6471 (compare:CC (match_dup 4)
6472 (const_int 0)))]
6473 "")
6475 (define_insn "*ashldi3_internal9"
6476 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6477 (compare:CC
6478 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6479 (match_operand:SI 2 "const_int_operand" "i,i"))
6480 (match_operand:DI 3 "mask64_operand" "n,n"))
6481 (const_int 0)))
6482 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6483 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6484 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6485 "@
6486 rldicr. %0,%1,%H2,%S3
6487 #"
6488 [(set_attr "type" "delayed_compare")
6489 (set_attr "length" "4,8")])
6491 (define_split
6492 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6493 (compare:CC
6494 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6495 (match_operand:SI 2 "const_int_operand" ""))
6496 (match_operand:DI 3 "mask64_operand" ""))
6497 (const_int 0)))
6498 (set (match_operand:DI 0 "gpc_reg_operand" "")
6499 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6500 "TARGET_POWERPC64 && reload_completed
6501 && includes_rldicr_lshift_p (operands[2], operands[3])"
6502 [(set (match_dup 0)
6503 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6504 (match_dup 3)))
6505 (set (match_dup 4)
6506 (compare:CC (match_dup 0)
6507 (const_int 0)))]
6508 "")
6510 (define_expand "lshrdi3"
6511 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6512 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6513 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6514 "TARGET_POWERPC64 || TARGET_POWER"
6515 "
6516 {
6517 if (TARGET_POWERPC64)
6518 ;
6519 else if (TARGET_POWER)
6520 {
6521 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6522 DONE;
6523 }
6524 else
6525 FAIL;
6526 }")
6528 (define_insn "*lshrdi3_internal1"
6529 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6530 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6531 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6532 "TARGET_POWERPC64"
6533 "srd%I2 %0,%1,%H2")
6535 (define_insn "*lshrdi3_internal2"
6536 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6537 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6538 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6539 (const_int 0)))
6540 (clobber (match_scratch:DI 3 "=r,r"))]
6541 "TARGET_64BIT "
6542 "@
6543 srd%I2. %3,%1,%H2
6544 #"
6545 [(set_attr "type" "delayed_compare")
6546 (set_attr "length" "4,8")])
6548 (define_split
6549 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6550 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6551 (match_operand:SI 2 "reg_or_cint_operand" ""))
6552 (const_int 0)))
6553 (clobber (match_scratch:DI 3 ""))]
6554 "TARGET_POWERPC64 && reload_completed"
6555 [(set (match_dup 3)
6556 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6557 (set (match_dup 0)
6558 (compare:CC (match_dup 3)
6559 (const_int 0)))]
6560 "")
6562 (define_insn "*lshrdi3_internal3"
6563 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6564 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6565 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6566 (const_int 0)))
6567 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6568 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6569 "TARGET_64BIT"
6570 "@
6571 srd%I2. %0,%1,%H2
6572 #"
6573 [(set_attr "type" "delayed_compare")
6574 (set_attr "length" "4,8")])
6576 (define_split
6577 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6578 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6579 (match_operand:SI 2 "reg_or_cint_operand" ""))
6580 (const_int 0)))
6581 (set (match_operand:DI 0 "gpc_reg_operand" "")
6582 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6583 "TARGET_POWERPC64 && reload_completed"
6584 [(set (match_dup 0)
6585 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6586 (set (match_dup 3)
6587 (compare:CC (match_dup 0)
6588 (const_int 0)))]
6589 "")
6591 (define_expand "ashrdi3"
6592 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6593 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6594 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6595 "WORDS_BIG_ENDIAN"
6596 "
6597 {
6598 if (TARGET_POWERPC64)
6599 ;
6600 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6601 {
6602 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6603 DONE;
6604 }
6605 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6606 && WORDS_BIG_ENDIAN)
6607 {
6608 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6609 DONE;
6610 }
6611 else
6612 FAIL;
6613 }")
6615 (define_insn "*ashrdi3_internal1"
6616 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6617 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6618 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6619 "TARGET_POWERPC64"
6620 "srad%I2 %0,%1,%H2")
6622 (define_insn "*ashrdi3_internal2"
6623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6624 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6625 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6626 (const_int 0)))
6627 (clobber (match_scratch:DI 3 "=r,r"))]
6628 "TARGET_64BIT"
6629 "@
6630 srad%I2. %3,%1,%H2
6631 #"
6632 [(set_attr "type" "delayed_compare")
6633 (set_attr "length" "4,8")])
6635 (define_split
6636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6637 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6638 (match_operand:SI 2 "reg_or_cint_operand" ""))
6639 (const_int 0)))
6640 (clobber (match_scratch:DI 3 ""))]
6641 "TARGET_POWERPC64 && reload_completed"
6642 [(set (match_dup 3)
6643 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6644 (set (match_dup 0)
6645 (compare:CC (match_dup 3)
6646 (const_int 0)))]
6647 "")
6649 (define_insn "*ashrdi3_internal3"
6650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6651 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6652 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6653 (const_int 0)))
6654 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6655 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6656 "TARGET_64BIT"
6657 "@
6658 srad%I2. %0,%1,%H2
6659 #"
6660 [(set_attr "type" "delayed_compare")
6661 (set_attr "length" "4,8")])
6663 (define_split
6664 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6665 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6666 (match_operand:SI 2 "reg_or_cint_operand" ""))
6667 (const_int 0)))
6668 (set (match_operand:DI 0 "gpc_reg_operand" "")
6669 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6670 "TARGET_POWERPC64 && reload_completed"
6671 [(set (match_dup 0)
6672 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6673 (set (match_dup 3)
6674 (compare:CC (match_dup 0)
6675 (const_int 0)))]
6676 "")
6678 (define_insn "anddi3"
6679 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6680 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6681 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6682 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6683 "TARGET_POWERPC64"
6684 "@
6685 and %0,%1,%2
6686 rldic%B2 %0,%1,0,%S2
6687 rlwinm %0,%1,0,%m2,%M2
6688 andi. %0,%1,%b2
6689 andis. %0,%1,%u2
6690 #"
6691 [(set_attr "type" "*,*,*,compare,compare,*")
6692 (set_attr "length" "4,4,4,4,4,8")])
6694 (define_split
6695 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6696 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6697 (match_operand:DI 2 "mask64_2_operand" "")))
6698 (clobber (match_scratch:CC 3 ""))]
6699 "TARGET_POWERPC64
6700 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6701 && !mask_operand (operands[2], DImode)
6702 && !mask64_operand (operands[2], DImode)"
6703 [(set (match_dup 0)
6704 (and:DI (rotate:DI (match_dup 1)
6705 (match_dup 4))
6706 (match_dup 5)))
6707 (set (match_dup 0)
6708 (and:DI (rotate:DI (match_dup 0)
6709 (match_dup 6))
6710 (match_dup 7)))]
6711 {
6712 build_mask64_2_operands (operands[2], &operands[4]);
6713 })
6715 (define_insn "*anddi3_internal2"
6716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
6717 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
6718 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
6719 (const_int 0)))
6720 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
6721 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
6722 "TARGET_64BIT"
6723 "@
6724 and. %3,%1,%2
6725 rldic%B2. %3,%1,0,%S2
6726 rlwinm. %3,%1,0,%m2,%M2
6727 andi. %3,%1,%b2
6728 andis. %3,%1,%u2
6729 #
6730 #
6731 #
6732 #
6733 #
6734 #
6735 #"
6736 [(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare")
6737 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
6739 (define_split
6740 [(set (match_operand:CC 0 "cc_reg_operand" "")
6741 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6742 (match_operand:DI 2 "mask64_2_operand" ""))
6743 (const_int 0)))
6744 (clobber (match_scratch:DI 3 ""))
6745 (clobber (match_scratch:CC 4 ""))]
6746 "TARGET_64BIT && reload_completed
6747 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6748 && !mask_operand (operands[2], DImode)
6749 && !mask64_operand (operands[2], DImode)"
6750 [(set (match_dup 3)
6751 (and:DI (rotate:DI (match_dup 1)
6752 (match_dup 5))
6753 (match_dup 6)))
6754 (parallel [(set (match_dup 0)
6755 (compare:CC (and:DI (rotate:DI (match_dup 3)
6756 (match_dup 7))
6757 (match_dup 8))
6758 (const_int 0)))
6759 (clobber (match_dup 3))])]
6760 "
6761 {
6762 build_mask64_2_operands (operands[2], &operands[5]);
6763 }")
6765 (define_insn "*anddi3_internal3"
6766 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
6767 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
6768 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
6769 (const_int 0)))
6770 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
6771 (and:DI (match_dup 1) (match_dup 2)))
6772 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
6773 "TARGET_64BIT"
6774 "@
6775 and. %0,%1,%2
6776 rldic%B2. %0,%1,0,%S2
6777 rlwinm. %0,%1,0,%m2,%M2
6778 andi. %0,%1,%b2
6779 andis. %0,%1,%u2
6780 #
6781 #
6782 #
6783 #
6784 #
6785 #
6786 #"
6787 [(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare")
6788 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
6790 (define_split
6791 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6792 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6793 (match_operand:DI 2 "and64_2_operand" ""))
6794 (const_int 0)))
6795 (set (match_operand:DI 0 "gpc_reg_operand" "")
6796 (and:DI (match_dup 1) (match_dup 2)))
6797 (clobber (match_scratch:CC 4 ""))]
6798 "TARGET_64BIT && reload_completed"
6799 [(parallel [(set (match_dup 0)
6800 (and:DI (match_dup 1) (match_dup 2)))
6801 (clobber (match_dup 4))])
6802 (set (match_dup 3)
6803 (compare:CC (match_dup 0)
6804 (const_int 0)))]
6805 "")
6807 (define_split
6808 [(set (match_operand:CC 3 "cc_reg_operand" "")
6809 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6810 (match_operand:DI 2 "mask64_2_operand" ""))
6811 (const_int 0)))
6812 (set (match_operand:DI 0 "gpc_reg_operand" "")
6813 (and:DI (match_dup 1) (match_dup 2)))
6814 (clobber (match_scratch:CC 4 ""))]
6815 "TARGET_64BIT && reload_completed
6816 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6817 && !mask_operand (operands[2], DImode)
6818 && !mask64_operand (operands[2], DImode)"
6819 [(set (match_dup 0)
6820 (and:DI (rotate:DI (match_dup 1)
6821 (match_dup 5))
6822 (match_dup 6)))
6823 (parallel [(set (match_dup 3)
6824 (compare:CC (and:DI (rotate:DI (match_dup 0)
6825 (match_dup 7))
6826 (match_dup 8))
6827 (const_int 0)))
6828 (set (match_dup 0)
6829 (and:DI (rotate:DI (match_dup 0)
6830 (match_dup 7))
6831 (match_dup 8)))])]
6832 "
6833 {
6834 build_mask64_2_operands (operands[2], &operands[5]);
6835 }")
6837 (define_expand "iordi3"
6838 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6839 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
6840 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6841 "TARGET_POWERPC64"
6842 "
6843 {
6844 if (non_logical_cint_operand (operands[2], DImode))
6845 {
6846 HOST_WIDE_INT value;
6847 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6848 ? operands[0] : gen_reg_rtx (DImode));
6850 if (GET_CODE (operands[2]) == CONST_INT)
6851 {
6852 value = INTVAL (operands[2]);
6853 emit_insn (gen_iordi3 (tmp, operands[1],
6854 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6855 }
6856 else
6857 {
6858 value = CONST_DOUBLE_LOW (operands[2]);
6859 emit_insn (gen_iordi3 (tmp, operands[1],
6860 immed_double_const (value
6861 & (~ (HOST_WIDE_INT) 0xffff),
6862 0, DImode)));
6863 }
6865 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6866 DONE;
6867 }
6868 }")
6870 (define_expand "xordi3"
6871 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6872 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
6873 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6874 "TARGET_POWERPC64"
6875 "
6876 {
6877 if (non_logical_cint_operand (operands[2], DImode))
6878 {
6879 HOST_WIDE_INT value;
6880 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6881 ? operands[0] : gen_reg_rtx (DImode));
6883 if (GET_CODE (operands[2]) == CONST_INT)
6884 {
6885 value = INTVAL (operands[2]);
6886 emit_insn (gen_xordi3 (tmp, operands[1],
6887 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6888 }
6889 else
6890 {
6891 value = CONST_DOUBLE_LOW (operands[2]);
6892 emit_insn (gen_xordi3 (tmp, operands[1],
6893 immed_double_const (value
6894 & (~ (HOST_WIDE_INT) 0xffff),
6895 0, DImode)));
6896 }
6898 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6899 DONE;
6900 }
6901 }")
6903 (define_insn "*booldi3_internal1"
6904 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
6905 (match_operator:DI 3 "boolean_or_operator"
6906 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
6907 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
6908 "TARGET_POWERPC64"
6909 "@
6910 %q3 %0,%1,%2
6911 %q3i %0,%1,%b2
6912 %q3is %0,%1,%u2")
6914 (define_insn "*booldi3_internal2"
6915 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6916 (compare:CC (match_operator:DI 4 "boolean_or_operator"
6917 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
6918 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
6919 (const_int 0)))
6920 (clobber (match_scratch:DI 3 "=r,r"))]
6921 "TARGET_64BIT"
6922 "@
6923 %q4. %3,%1,%2
6924 #"
6925 [(set_attr "type" "compare")
6926 (set_attr "length" "4,8")])
6928 (define_split
6929 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6930 (compare:CC (match_operator:DI 4 "boolean_operator"
6931 [(match_operand:DI 1 "gpc_reg_operand" "")
6932 (match_operand:DI 2 "gpc_reg_operand" "")])
6933 (const_int 0)))
6934 (clobber (match_scratch:DI 3 ""))]
6935 "TARGET_POWERPC64 && reload_completed"
6936 [(set (match_dup 3) (match_dup 4))
6937 (set (match_dup 0)
6938 (compare:CC (match_dup 3)
6939 (const_int 0)))]
6940 "")
6942 (define_insn "*booldi3_internal3"
6943 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6944 (compare:CC (match_operator:DI 4 "boolean_operator"
6945 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
6946 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
6947 (const_int 0)))
6948 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6949 (match_dup 4))]
6950 "TARGET_64BIT"
6951 "@
6952 %q4. %0,%1,%2
6953 #"
6954 [(set_attr "type" "compare")
6955 (set_attr "length" "4,8")])
6957 (define_split
6958 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6959 (compare:CC (match_operator:DI 4 "boolean_operator"
6960 [(match_operand:DI 1 "gpc_reg_operand" "")
6961 (match_operand:DI 2 "gpc_reg_operand" "")])
6962 (const_int 0)))
6963 (set (match_operand:DI 0 "gpc_reg_operand" "")
6964 (match_dup 4))]
6965 "TARGET_POWERPC64 && reload_completed"
6966 [(set (match_dup 0) (match_dup 4))
6967 (set (match_dup 3)
6968 (compare:CC (match_dup 0)
6969 (const_int 0)))]
6970 "")
6972 ;; Split a logical operation that we can't do in one insn into two insns,
6973 ;; each of which does one 16-bit part. This is used by combine.
6975 (define_split
6976 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6977 (match_operator:DI 3 "boolean_or_operator"
6978 [(match_operand:DI 1 "gpc_reg_operand" "")
6979 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
6980 "TARGET_POWERPC64"
6981 [(set (match_dup 0) (match_dup 4))
6982 (set (match_dup 0) (match_dup 5))]
6983 "
6984 {
6985 rtx i3,i4;
6987 if (GET_CODE (operands[2]) == CONST_DOUBLE)
6988 {
6989 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
6990 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
6991 0, DImode);
6992 i4 = GEN_INT (value & 0xffff);
6993 }
6994 else
6995 {
6996 i3 = GEN_INT (INTVAL (operands[2])
6997 & (~ (HOST_WIDE_INT) 0xffff));
6998 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
6999 }
7000 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7001 operands[1], i3);
7002 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7003 operands[0], i4);
7004 }")
7006 (define_insn "*boolcdi3_internal1"
7007 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7008 (match_operator:DI 3 "boolean_operator"
7009 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7010 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7011 "TARGET_POWERPC64"
7012 "%q3 %0,%2,%1")
7014 (define_insn "*boolcdi3_internal2"
7015 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7016 (compare:CC (match_operator:DI 4 "boolean_operator"
7017 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7018 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7019 (const_int 0)))
7020 (clobber (match_scratch:DI 3 "=r,r"))]
7021 "TARGET_64BIT"
7022 "@
7023 %q4. %3,%2,%1
7024 #"
7025 [(set_attr "type" "compare")
7026 (set_attr "length" "4,8")])
7028 (define_split
7029 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7030 (compare:CC (match_operator:DI 4 "boolean_operator"
7031 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7032 (match_operand:DI 2 "gpc_reg_operand" "")])
7033 (const_int 0)))
7034 (clobber (match_scratch:DI 3 ""))]
7035 "TARGET_POWERPC64 && reload_completed"
7036 [(set (match_dup 3) (match_dup 4))
7037 (set (match_dup 0)
7038 (compare:CC (match_dup 3)
7039 (const_int 0)))]
7040 "")
7042 (define_insn "*boolcdi3_internal3"
7043 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7044 (compare:CC (match_operator:DI 4 "boolean_operator"
7045 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7046 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7047 (const_int 0)))
7048 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7049 (match_dup 4))]
7050 "TARGET_64BIT"
7051 "@
7052 %q4. %0,%2,%1
7053 #"
7054 [(set_attr "type" "compare")
7055 (set_attr "length" "4,8")])
7057 (define_split
7058 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7059 (compare:CC (match_operator:DI 4 "boolean_operator"
7060 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7061 (match_operand:DI 2 "gpc_reg_operand" "")])
7062 (const_int 0)))
7063 (set (match_operand:DI 0 "gpc_reg_operand" "")
7064 (match_dup 4))]
7065 "TARGET_POWERPC64 && reload_completed"
7066 [(set (match_dup 0) (match_dup 4))
7067 (set (match_dup 3)
7068 (compare:CC (match_dup 0)
7069 (const_int 0)))]
7070 "")
7072 (define_insn "*boolccdi3_internal1"
7073 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7074 (match_operator:DI 3 "boolean_operator"
7075 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7076 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7077 "TARGET_POWERPC64"
7078 "%q3 %0,%1,%2")
7080 (define_insn "*boolccdi3_internal2"
7081 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7082 (compare:CC (match_operator:DI 4 "boolean_operator"
7083 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7084 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7085 (const_int 0)))
7086 (clobber (match_scratch:DI 3 "=r,r"))]
7087 "TARGET_64BIT"
7088 "@
7089 %q4. %3,%1,%2
7090 #"
7091 [(set_attr "type" "compare")
7092 (set_attr "length" "4,8")])
7094 (define_split
7095 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7096 (compare:CC (match_operator:DI 4 "boolean_operator"
7097 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7098 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7099 (const_int 0)))
7100 (clobber (match_scratch:DI 3 ""))]
7101 "TARGET_POWERPC64 && reload_completed"
7102 [(set (match_dup 3) (match_dup 4))
7103 (set (match_dup 0)
7104 (compare:CC (match_dup 3)
7105 (const_int 0)))]
7106 "")
7108 (define_insn "*boolccdi3_internal3"
7109 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7110 (compare:CC (match_operator:DI 4 "boolean_operator"
7111 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7112 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7113 (const_int 0)))
7114 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7115 (match_dup 4))]
7116 "TARGET_64BIT"
7117 "@
7118 %q4. %0,%1,%2
7119 #"
7120 [(set_attr "type" "compare")
7121 (set_attr "length" "4,8")])
7123 (define_split
7124 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7125 (compare:CC (match_operator:DI 4 "boolean_operator"
7126 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7127 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7128 (const_int 0)))
7129 (set (match_operand:DI 0 "gpc_reg_operand" "")
7130 (match_dup 4))]
7131 "TARGET_POWERPC64 && reload_completed"
7132 [(set (match_dup 0) (match_dup 4))
7133 (set (match_dup 3)
7134 (compare:CC (match_dup 0)
7135 (const_int 0)))]
7136 "")
7137 \f
7138 ;; Now define ways of moving data around.
7140 ;; Set up a register with a value from the GOT table
7142 (define_expand "movsi_got"
7143 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7144 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7145 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7146 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7147 "
7148 {
7149 if (GET_CODE (operands[1]) == CONST)
7150 {
7151 rtx offset = const0_rtx;
7152 HOST_WIDE_INT value;
7154 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7155 value = INTVAL (offset);
7156 if (value != 0)
7157 {
7158 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7159 emit_insn (gen_movsi_got (tmp, operands[1]));
7160 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7161 DONE;
7162 }
7163 }
7165 operands[2] = rs6000_got_register (operands[1]);
7166 }")
7168 (define_insn "*movsi_got_internal"
7169 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7170 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7171 (match_operand:SI 2 "gpc_reg_operand" "b")]
7172 UNSPEC_MOVSI_GOT))]
7173 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7174 "{l|lwz} %0,%a1@got(%2)"
7175 [(set_attr "type" "load")])
7177 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7178 ;; didn't get allocated to a hard register.
7179 (define_split
7180 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7181 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7182 (match_operand:SI 2 "memory_operand" "")]
7183 UNSPEC_MOVSI_GOT))]
7184 "DEFAULT_ABI == ABI_V4
7185 && flag_pic == 1
7186 && (reload_in_progress || reload_completed)"
7187 [(set (match_dup 0) (match_dup 2))
7188 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7189 UNSPEC_MOVSI_GOT))]
7190 "")
7192 ;; For SI, we special-case integers that can't be loaded in one insn. We
7193 ;; do the load 16-bits at a time. We could do this by loading from memory,
7194 ;; and this is even supposed to be faster, but it is simpler not to get
7195 ;; integers in the TOC.
7196 (define_insn "movsi_low"
7197 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7198 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7199 (match_operand 2 "" ""))))]
7200 "TARGET_MACHO && ! TARGET_64BIT"
7201 "{l|lwz} %0,lo16(%2)(%1)"
7202 [(set_attr "type" "load")
7203 (set_attr "length" "4")])
7205 (define_insn "*movsi_internal1"
7206 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7207 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7208 "gpc_reg_operand (operands[0], SImode)
7209 || gpc_reg_operand (operands[1], SImode)"
7210 "@
7211 mr %0,%1
7212 {cal|la} %0,%a1
7213 {l%U1%X1|lwz%U1%X1} %0,%1
7214 {st%U0%X0|stw%U0%X0} %1,%0
7215 {lil|li} %0,%1
7216 {liu|lis} %0,%v1
7217 #
7218 {cal|la} %0,%a1
7219 mf%1 %0
7220 mt%0 %1
7221 mt%0 %1
7222 mt%0 %1
7223 {cror 0,0,0|nop}"
7224 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7225 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7227 ;; Split a load of a large constant into the appropriate two-insn
7228 ;; sequence.
7230 (define_split
7231 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7232 (match_operand:SI 1 "const_int_operand" ""))]
7233 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7234 && (INTVAL (operands[1]) & 0xffff) != 0"
7235 [(set (match_dup 0)
7236 (match_dup 2))
7237 (set (match_dup 0)
7238 (ior:SI (match_dup 0)
7239 (match_dup 3)))]
7240 "
7241 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7243 if (tem == operands[0])
7244 DONE;
7245 else
7246 FAIL;
7247 }")
7249 (define_insn "*mov<mode>_internal2"
7250 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7251 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7252 (const_int 0)))
7253 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7254 ""
7255 "@
7256 {cmpi|cmp<wd>i} %2,%0,0
7257 mr. %0,%1
7258 #"
7259 [(set_attr "type" "cmp,compare,cmp")
7260 (set_attr "length" "4,4,8")])
7262 (define_split
7263 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7264 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7265 (const_int 0)))
7266 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7267 "reload_completed"
7268 [(set (match_dup 0) (match_dup 1))
7269 (set (match_dup 2)
7270 (compare:CC (match_dup 0)
7271 (const_int 0)))]
7272 "")
7273 \f
7274 (define_insn "*movhi_internal"
7275 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7276 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7277 "gpc_reg_operand (operands[0], HImode)
7278 || gpc_reg_operand (operands[1], HImode)"
7279 "@
7280 mr %0,%1
7281 lhz%U1%X1 %0,%1
7282 sth%U0%X0 %1,%0
7283 {lil|li} %0,%w1
7284 mf%1 %0
7285 mt%0 %1
7286 mt%0 %1
7287 {cror 0,0,0|nop}"
7288 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7290 (define_expand "mov<mode>"
7291 [(set (match_operand:INT 0 "general_operand" "")
7292 (match_operand:INT 1 "any_operand" ""))]
7293 ""
7294 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7296 (define_insn "*movqi_internal"
7297 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7298 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7299 "gpc_reg_operand (operands[0], QImode)
7300 || gpc_reg_operand (operands[1], QImode)"
7301 "@
7302 mr %0,%1
7303 lbz%U1%X1 %0,%1
7304 stb%U0%X0 %1,%0
7305 {lil|li} %0,%1
7306 mf%1 %0
7307 mt%0 %1
7308 mt%0 %1
7309 {cror 0,0,0|nop}"
7310 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7311 \f
7312 ;; Here is how to move condition codes around. When we store CC data in
7313 ;; an integer register or memory, we store just the high-order 4 bits.
7314 ;; This lets us not shift in the most common case of CR0.
7315 (define_expand "movcc"
7316 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7317 (match_operand:CC 1 "nonimmediate_operand" ""))]
7318 ""
7319 "")
7321 (define_insn "*movcc_internal1"
7322 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7323 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7324 "register_operand (operands[0], CCmode)
7325 || register_operand (operands[1], CCmode)"
7326 "@
7327 mcrf %0,%1
7328 mtcrf 128,%1
7329 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7330 mfcr %0%Q1
7331 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7332 mr %0,%1
7333 mf%1 %0
7334 mt%0 %1
7335 mt%0 %1
7336 {l%U1%X1|lwz%U1%X1} %0,%1
7337 {st%U0%U1|stw%U0%U1} %1,%0"
7338 [(set (attr "type")
7339 (cond [(eq_attr "alternative" "0")
7340 (const_string "cr_logical")
7341 (eq_attr "alternative" "1,2")
7342 (const_string "mtcr")
7343 (eq_attr "alternative" "5,7")
7344 (const_string "integer")
7345 (eq_attr "alternative" "6")
7346 (const_string "mfjmpr")
7347 (eq_attr "alternative" "8")
7348 (const_string "mtjmpr")
7349 (eq_attr "alternative" "9")
7350 (const_string "load")
7351 (eq_attr "alternative" "10")
7352 (const_string "store")
7353 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7354 (const_string "mfcrf")
7355 ]
7356 (const_string "mfcr")))
7357 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7358 \f
7359 ;; For floating-point, we normally deal with the floating-point registers
7360 ;; unless -msoft-float is used. The sole exception is that parameter passing
7361 ;; can produce floating-point values in fixed-point registers. Unless the
7362 ;; value is a simple constant or already in memory, we deal with this by
7363 ;; allocating memory and copying the value explicitly via that memory location.
7364 (define_expand "movsf"
7365 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7366 (match_operand:SF 1 "any_operand" ""))]
7367 ""
7368 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7370 (define_split
7371 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7372 (match_operand:SF 1 "const_double_operand" ""))]
7373 "reload_completed
7374 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7375 || (GET_CODE (operands[0]) == SUBREG
7376 && GET_CODE (SUBREG_REG (operands[0])) == REG
7377 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7378 [(set (match_dup 2) (match_dup 3))]
7379 "
7380 {
7381 long l;
7382 REAL_VALUE_TYPE rv;
7384 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7385 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7387 if (! TARGET_POWERPC64)
7388 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7389 else
7390 operands[2] = gen_lowpart (SImode, operands[0]);
7392 operands[3] = gen_int_mode (l, SImode);
7393 }")
7395 (define_insn "*movsf_hardfloat"
7396 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7397 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7398 "(gpc_reg_operand (operands[0], SFmode)
7399 || gpc_reg_operand (operands[1], SFmode))
7400 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7401 "@
7402 mr %0,%1
7403 {l%U1%X1|lwz%U1%X1} %0,%1
7404 {st%U0%X0|stw%U0%X0} %1,%0
7405 fmr %0,%1
7406 lfs%U1%X1 %0,%1
7407 stfs%U0%X0 %1,%0
7408 mt%0 %1
7409 mt%0 %1
7410 mf%1 %0
7411 {cror 0,0,0|nop}
7412 #
7413 #"
7414 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7415 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7417 (define_insn "*movsf_softfloat"
7418 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7419 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7420 "(gpc_reg_operand (operands[0], SFmode)
7421 || gpc_reg_operand (operands[1], SFmode))
7422 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7423 "@
7424 mr %0,%1
7425 mt%0 %1
7426 mt%0 %1
7427 mf%1 %0
7428 {l%U1%X1|lwz%U1%X1} %0,%1
7429 {st%U0%X0|stw%U0%X0} %1,%0
7430 {lil|li} %0,%1
7431 {liu|lis} %0,%v1
7432 {cal|la} %0,%a1
7433 #
7434 #
7435 {cror 0,0,0|nop}"
7436 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7437 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7439 \f
7440 (define_expand "movdf"
7441 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7442 (match_operand:DF 1 "any_operand" ""))]
7443 ""
7444 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7446 (define_split
7447 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7448 (match_operand:DF 1 "const_int_operand" ""))]
7449 "! TARGET_POWERPC64 && reload_completed
7450 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7451 || (GET_CODE (operands[0]) == SUBREG
7452 && GET_CODE (SUBREG_REG (operands[0])) == REG
7453 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7454 [(set (match_dup 2) (match_dup 4))
7455 (set (match_dup 3) (match_dup 1))]
7456 "
7457 {
7458 int endian = (WORDS_BIG_ENDIAN == 0);
7459 HOST_WIDE_INT value = INTVAL (operands[1]);
7461 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7462 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7463 #if HOST_BITS_PER_WIDE_INT == 32
7464 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7465 #else
7466 operands[4] = GEN_INT (value >> 32);
7467 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7468 #endif
7469 }")
7471 (define_split
7472 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7473 (match_operand:DF 1 "const_double_operand" ""))]
7474 "! TARGET_POWERPC64 && reload_completed
7475 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7476 || (GET_CODE (operands[0]) == SUBREG
7477 && GET_CODE (SUBREG_REG (operands[0])) == REG
7478 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7479 [(set (match_dup 2) (match_dup 4))
7480 (set (match_dup 3) (match_dup 5))]
7481 "
7482 {
7483 int endian = (WORDS_BIG_ENDIAN == 0);
7484 long l[2];
7485 REAL_VALUE_TYPE rv;
7487 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7488 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7490 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7491 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7492 operands[4] = gen_int_mode (l[endian], SImode);
7493 operands[5] = gen_int_mode (l[1 - endian], SImode);
7494 }")
7496 (define_split
7497 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7498 (match_operand:DF 1 "easy_fp_constant" ""))]
7499 "TARGET_POWERPC64 && reload_completed
7500 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7501 || (GET_CODE (operands[0]) == SUBREG
7502 && GET_CODE (SUBREG_REG (operands[0])) == REG
7503 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7504 [(set (match_dup 2) (match_dup 3))]
7505 "
7506 {
7507 int endian = (WORDS_BIG_ENDIAN == 0);
7508 long l[2];
7509 REAL_VALUE_TYPE rv;
7510 #if HOST_BITS_PER_WIDE_INT >= 64
7511 HOST_WIDE_INT val;
7512 #endif
7514 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7515 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7517 operands[2] = gen_lowpart (DImode, operands[0]);
7518 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7519 #if HOST_BITS_PER_WIDE_INT >= 64
7520 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7521 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7523 operands[3] = gen_int_mode (val, DImode);
7524 #else
7525 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7526 #endif
7527 }")
7529 ;; Don't have reload use general registers to load a constant. First,
7530 ;; it might not work if the output operand is the equivalent of
7531 ;; a non-offsettable memref, but also it is less efficient than loading
7532 ;; the constant into an FP register, since it will probably be used there.
7533 ;; The "??" is a kludge until we can figure out a more reasonable way
7534 ;; of handling these non-offsettable values.
7535 (define_insn "*movdf_hardfloat32"
7536 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7537 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7538 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7539 && (gpc_reg_operand (operands[0], DFmode)
7540 || gpc_reg_operand (operands[1], DFmode))"
7541 "*
7542 {
7543 switch (which_alternative)
7544 {
7545 default:
7546 gcc_unreachable ();
7547 case 0:
7548 /* We normally copy the low-numbered register first. However, if
7549 the first register operand 0 is the same as the second register
7550 of operand 1, we must copy in the opposite order. */
7551 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7552 return \"mr %L0,%L1\;mr %0,%1\";
7553 else
7554 return \"mr %0,%1\;mr %L0,%L1\";
7555 case 1:
7556 if (GET_CODE (operands[1]) == MEM
7557 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7558 reload_completed || reload_in_progress)
7559 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0))
7560 || GET_CODE (XEXP (operands[1], 0)) == REG
7561 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7562 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7563 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7564 {
7565 /* If the low-address word is used in the address, we must load
7566 it last. Otherwise, load it first. Note that we cannot have
7567 auto-increment in that case since the address register is
7568 known to be dead. */
7569 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7570 operands[1], 0))
7571 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7572 else
7573 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7574 }
7575 else
7576 {
7577 rtx addreg;
7579 addreg = find_addr_reg (XEXP (operands[1], 0));
7580 if (refers_to_regno_p (REGNO (operands[0]),
7581 REGNO (operands[0]) + 1,
7582 operands[1], 0))
7583 {
7584 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7585 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7586 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7587 return \"{lx|lwzx} %0,%1\";
7588 }
7589 else
7590 {
7591 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7592 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7593 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7594 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7595 return \"\";
7596 }
7597 }
7598 case 2:
7599 if (GET_CODE (operands[0]) == MEM
7600 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7601 reload_completed || reload_in_progress)
7602 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0))
7603 || GET_CODE (XEXP (operands[0], 0)) == REG
7604 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7605 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7606 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7607 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7608 else
7609 {
7610 rtx addreg;
7612 addreg = find_addr_reg (XEXP (operands[0], 0));
7613 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7614 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7615 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7616 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7617 return \"\";
7618 }
7619 case 3:
7620 return \"fmr %0,%1\";
7621 case 4:
7622 return \"lfd%U1%X1 %0,%1\";
7623 case 5:
7624 return \"stfd%U0%X0 %1,%0\";
7625 case 6:
7626 case 7:
7627 case 8:
7628 return \"#\";
7629 }
7630 }"
7631 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7632 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7634 (define_insn "*movdf_softfloat32"
7635 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7636 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7637 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7638 && (gpc_reg_operand (operands[0], DFmode)
7639 || gpc_reg_operand (operands[1], DFmode))"
7640 "*
7641 {
7642 switch (which_alternative)
7643 {
7644 default:
7645 gcc_unreachable ();
7646 case 0:
7647 /* We normally copy the low-numbered register first. However, if
7648 the first register operand 0 is the same as the second register of
7649 operand 1, we must copy in the opposite order. */
7650 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7651 return \"mr %L0,%L1\;mr %0,%1\";
7652 else
7653 return \"mr %0,%1\;mr %L0,%L1\";
7654 case 1:
7655 /* If the low-address word is used in the address, we must load
7656 it last. Otherwise, load it first. Note that we cannot have
7657 auto-increment in that case since the address register is
7658 known to be dead. */
7659 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7660 operands[1], 0))
7661 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7662 else
7663 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7664 case 2:
7665 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7666 case 3:
7667 case 4:
7668 case 5:
7669 return \"#\";
7670 }
7671 }"
7672 [(set_attr "type" "two,load,store,*,*,*")
7673 (set_attr "length" "8,8,8,8,12,16")])
7675 ; ld/std require word-aligned displacements -> 'Y' constraint.
7676 ; List Y->r and r->Y before r->r for reload.
7677 (define_insn "*movdf_hardfloat64"
7678 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
7679 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7680 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7681 && (gpc_reg_operand (operands[0], DFmode)
7682 || gpc_reg_operand (operands[1], DFmode))"
7683 "@
7684 std%U0%X0 %1,%0
7685 ld%U1%X1 %0,%1
7686 mr %0,%1
7687 fmr %0,%1
7688 lfd%U1%X1 %0,%1
7689 stfd%U0%X0 %1,%0
7690 mt%0 %1
7691 mf%1 %0
7692 {cror 0,0,0|nop}
7693 #
7694 #
7695 #"
7696 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
7697 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7699 (define_insn "*movdf_softfloat64"
7700 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7701 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7702 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7703 && (gpc_reg_operand (operands[0], DFmode)
7704 || gpc_reg_operand (operands[1], DFmode))"
7705 "@
7706 ld%U1%X1 %0,%1
7707 std%U0%X0 %1,%0
7708 mr %0,%1
7709 mt%0 %1
7710 mf%1 %0
7711 #
7712 #
7713 #
7714 {cror 0,0,0|nop}"
7715 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
7716 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7717 \f
7718 (define_expand "movtf"
7719 [(set (match_operand:TF 0 "general_operand" "")
7720 (match_operand:TF 1 "any_operand" ""))]
7721 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7722 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7723 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7725 ; It's important to list the o->f and f->o moves before f->f because
7726 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7727 ; which doesn't make progress. Likewise r->Y must be before r->r.
7728 (define_insn_and_split "*movtf_internal"
7729 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7730 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7731 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7732 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7733 && (gpc_reg_operand (operands[0], TFmode)
7734 || gpc_reg_operand (operands[1], TFmode))"
7735 "#"
7736 "&& reload_completed"
7737 [(pc)]
7738 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7739 [(set_attr "length" "8,8,8,20,20,16")])
7741 (define_expand "extenddftf2"
7742 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7743 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7744 (use (match_dup 2))])]
7745 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7746 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7747 {
7748 operands[2] = CONST0_RTX (DFmode);
7749 })
7751 (define_insn_and_split "*extenddftf2_internal"
7752 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
7753 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
7754 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
7755 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7756 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7757 "#"
7758 "&& reload_completed"
7759 [(pc)]
7760 {
7761 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7762 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7763 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
7764 operands[1]);
7765 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
7766 operands[2]);
7767 DONE;
7768 })
7770 (define_expand "extendsftf2"
7771 [(set (match_operand:TF 0 "nonimmediate_operand" "")
7772 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
7773 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7774 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7775 {
7776 rtx tmp = gen_reg_rtx (DFmode);
7777 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
7778 emit_insn (gen_extenddftf2 (operands[0], tmp));
7779 DONE;
7780 })
7782 (define_expand "trunctfdf2"
7783 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7784 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
7785 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7786 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7787 "")
7789 (define_insn_and_split "trunctfdf2_internal1"
7790 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
7791 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
7792 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
7793 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7794 "@
7795 #
7796 fmr %0,%1"
7797 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
7798 [(const_int 0)]
7799 {
7800 emit_note (NOTE_INSN_DELETED);
7801 DONE;
7802 }
7803 [(set_attr "type" "fp")])
7805 (define_insn "trunctfdf2_internal2"
7806 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7807 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7808 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
7809 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7810 "fadd %0,%1,%L1"
7811 [(set_attr "type" "fp")])
7813 (define_insn_and_split "trunctfsf2"
7814 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7815 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
7816 (clobber (match_scratch:DF 2 "=f"))]
7817 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7818 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7819 "#"
7820 "&& reload_completed"
7821 [(set (match_dup 2)
7822 (float_truncate:DF (match_dup 1)))
7823 (set (match_dup 0)
7824 (float_truncate:SF (match_dup 2)))]
7825 "")
7827 (define_expand "floatsitf2"
7828 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7829 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
7830 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7831 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7832 {
7833 rtx tmp = gen_reg_rtx (DFmode);
7834 expand_float (tmp, operands[1], false);
7835 emit_insn (gen_extenddftf2 (operands[0], tmp));
7836 DONE;
7837 })
7839 ; fadd, but rounding towards zero.
7840 ; This is probably not the optimal code sequence.
7841 (define_insn "fix_trunc_helper"
7842 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7843 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
7844 UNSPEC_FIX_TRUNC_TF))
7845 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
7846 "TARGET_HARD_FLOAT && TARGET_FPRS"
7847 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
7848 [(set_attr "type" "fp")
7849 (set_attr "length" "20")])
7851 (define_expand "fix_trunctfsi2"
7852 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
7853 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
7854 (clobber (match_dup 2))
7855 (clobber (match_dup 3))
7856 (clobber (match_dup 4))
7857 (clobber (match_dup 5))])]
7858 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7859 && (TARGET_POWER2 || TARGET_POWERPC)
7860 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7861 {
7862 operands[2] = gen_reg_rtx (DFmode);
7863 operands[3] = gen_reg_rtx (DFmode);
7864 operands[4] = gen_reg_rtx (DImode);
7865 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
7866 })
7868 (define_insn_and_split "*fix_trunctfsi2_internal"
7869 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7870 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
7871 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
7872 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
7873 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
7874 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
7875 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7876 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7877 "#"
7878 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
7879 [(pc)]
7880 {
7881 rtx lowword;
7882 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
7884 gcc_assert (MEM_P (operands[5]));
7885 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
7887 emit_insn (gen_fctiwz (operands[4], operands[2]));
7888 emit_move_insn (operands[5], operands[4]);
7889 emit_move_insn (operands[0], lowword);
7890 DONE;
7891 })
7893 (define_insn "negtf2"
7894 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7895 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7896 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7897 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7898 "*
7899 {
7900 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7901 return \"fneg %L0,%L1\;fneg %0,%1\";
7902 else
7903 return \"fneg %0,%1\;fneg %L0,%L1\";
7904 }"
7905 [(set_attr "type" "fp")
7906 (set_attr "length" "8")])
7908 (define_expand "abstf2"
7909 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7910 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7911 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7912 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7913 "
7914 {
7915 rtx label = gen_label_rtx ();
7916 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
7917 emit_label (label);
7918 DONE;
7919 }")
7921 (define_expand "abstf2_internal"
7922 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7923 (match_operand:TF 1 "gpc_reg_operand" "f"))
7924 (set (match_dup 3) (match_dup 5))
7925 (set (match_dup 5) (abs:DF (match_dup 5)))
7926 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
7927 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
7928 (label_ref (match_operand 2 "" ""))
7929 (pc)))
7930 (set (match_dup 6) (neg:DF (match_dup 6)))]
7931 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7932 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7933 "
7934 {
7935 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7936 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7937 operands[3] = gen_reg_rtx (DFmode);
7938 operands[4] = gen_reg_rtx (CCFPmode);
7939 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
7940 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
7941 }")
7942 \f
7943 ;; Next come the multi-word integer load and store and the load and store
7944 ;; multiple insns.
7946 ; List r->r after r->"o<>", otherwise reload will try to reload a
7947 ; non-offsettable address by using r->r which won't make progress.
7948 (define_insn "*movdi_internal32"
7949 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
7950 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
7951 "! TARGET_POWERPC64
7952 && (gpc_reg_operand (operands[0], DImode)
7953 || gpc_reg_operand (operands[1], DImode))"
7954 "@
7955 #
7956 #
7957 #
7958 fmr %0,%1
7959 lfd%U1%X1 %0,%1
7960 stfd%U0%X0 %1,%0
7961 #"
7962 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
7964 (define_split
7965 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7966 (match_operand:DI 1 "const_int_operand" ""))]
7967 "! TARGET_POWERPC64 && reload_completed"
7968 [(set (match_dup 2) (match_dup 4))
7969 (set (match_dup 3) (match_dup 1))]
7970 "
7971 {
7972 HOST_WIDE_INT value = INTVAL (operands[1]);
7973 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7974 DImode);
7975 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7976 DImode);
7977 #if HOST_BITS_PER_WIDE_INT == 32
7978 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7979 #else
7980 operands[4] = GEN_INT (value >> 32);
7981 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7982 #endif
7983 }")
7985 (define_split
7986 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7987 (match_operand:DI 1 "input_operand" ""))]
7988 "reload_completed && !TARGET_POWERPC64
7989 && gpr_or_gpr_p (operands[0], operands[1])"
7990 [(pc)]
7991 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
7993 (define_insn "*movdi_internal64"
7994 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
7995 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
7996 "TARGET_POWERPC64
7997 && (gpc_reg_operand (operands[0], DImode)
7998 || gpc_reg_operand (operands[1], DImode))"
7999 "@
8000 mr %0,%1
8001 ld%U1%X1 %0,%1
8002 std%U0%X0 %1,%0
8003 li %0,%1
8004 lis %0,%v1
8005 #
8006 {cal|la} %0,%a1
8007 fmr %0,%1
8008 lfd%U1%X1 %0,%1
8009 stfd%U0%X0 %1,%0
8010 mf%1 %0
8011 mt%0 %1
8012 {cror 0,0,0|nop}"
8013 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8014 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8016 ;; immediate value valid for a single instruction hiding in a const_double
8017 (define_insn ""
8018 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8019 (match_operand:DI 1 "const_double_operand" "F"))]
8020 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8021 && GET_CODE (operands[1]) == CONST_DOUBLE
8022 && num_insns_constant (operands[1], DImode) == 1"
8023 "*
8024 {
8025 return ((unsigned HOST_WIDE_INT)
8026 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8027 ? \"li %0,%1\" : \"lis %0,%v1\";
8028 }")
8030 ;; Generate all one-bits and clear left or right.
8031 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8032 (define_split
8033 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8034 (match_operand:DI 1 "mask64_operand" ""))]
8035 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8036 [(set (match_dup 0) (const_int -1))
8037 (set (match_dup 0)
8038 (and:DI (rotate:DI (match_dup 0)
8039 (const_int 0))
8040 (match_dup 1)))]
8041 "")
8043 ;; Split a load of a large constant into the appropriate five-instruction
8044 ;; sequence. Handle anything in a constant number of insns.
8045 ;; When non-easy constants can go in the TOC, this should use
8046 ;; easy_fp_constant predicate.
8047 (define_split
8048 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8049 (match_operand:DI 1 "const_int_operand" ""))]
8050 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8051 [(set (match_dup 0) (match_dup 2))
8052 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8053 "
8054 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8056 if (tem == operands[0])
8057 DONE;
8058 else
8059 FAIL;
8060 }")
8062 (define_split
8063 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8064 (match_operand:DI 1 "const_double_operand" ""))]
8065 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8066 [(set (match_dup 0) (match_dup 2))
8067 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8068 "
8069 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8071 if (tem == operands[0])
8072 DONE;
8073 else
8074 FAIL;
8075 }")
8076 \f
8077 ;; TImode is similar, except that we usually want to compute the address into
8078 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8079 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8081 ;; We say that MQ is clobbered in the last alternative because the first
8082 ;; alternative would never get used otherwise since it would need a reload
8083 ;; while the 2nd alternative would not. We put memory cases first so they
8084 ;; are preferred. Otherwise, we'd try to reload the output instead of
8085 ;; giving the SCRATCH mq.
8087 (define_insn "*movti_power"
8088 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8089 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8090 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8091 "TARGET_POWER && ! TARGET_POWERPC64
8092 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8093 "*
8094 {
8095 switch (which_alternative)
8096 {
8097 default:
8098 gcc_unreachable ();
8100 case 0:
8101 if (TARGET_STRING)
8102 return \"{stsi|stswi} %1,%P0,16\";
8103 case 1:
8104 case 2:
8105 return \"#\";
8106 case 3:
8107 /* If the address is not used in the output, we can use lsi. Otherwise,
8108 fall through to generating four loads. */
8109 if (TARGET_STRING
8110 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8111 return \"{lsi|lswi} %0,%P1,16\";
8112 /* ... fall through ... */
8113 case 4:
8114 case 5:
8115 return \"#\";
8116 }
8117 }"
8118 [(set_attr "type" "store,store,*,load,load,*")])
8120 (define_insn "*movti_string"
8121 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8122 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8123 "! TARGET_POWER && ! TARGET_POWERPC64
8124 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8125 "*
8126 {
8127 switch (which_alternative)
8128 {
8129 default:
8130 gcc_unreachable ();
8131 case 0:
8132 if (TARGET_STRING)
8133 return \"{stsi|stswi} %1,%P0,16\";
8134 case 1:
8135 case 2:
8136 return \"#\";
8137 case 3:
8138 /* If the address is not used in the output, we can use lsi. Otherwise,
8139 fall through to generating four loads. */
8140 if (TARGET_STRING
8141 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8142 return \"{lsi|lswi} %0,%P1,16\";
8143 /* ... fall through ... */
8144 case 4:
8145 case 5:
8146 return \"#\";
8147 }
8148 }"
8149 [(set_attr "type" "store,store,*,load,load,*")])
8151 (define_insn "*movti_ppc64"
8152 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8153 (match_operand:TI 1 "input_operand" "r,r,m"))]
8154 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8155 || gpc_reg_operand (operands[1], TImode))"
8156 "#"
8157 [(set_attr "type" "*,load,store")])
8159 (define_split
8160 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8161 (match_operand:TI 1 "const_double_operand" ""))]
8162 "TARGET_POWERPC64"
8163 [(set (match_dup 2) (match_dup 4))
8164 (set (match_dup 3) (match_dup 5))]
8165 "
8166 {
8167 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8168 TImode);
8169 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8170 TImode);
8171 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8172 {
8173 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8174 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8175 }
8176 else if (GET_CODE (operands[1]) == CONST_INT)
8177 {
8178 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8179 operands[5] = operands[1];
8180 }
8181 else
8182 FAIL;
8183 }")
8185 (define_split
8186 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8187 (match_operand:TI 1 "input_operand" ""))]
8188 "reload_completed
8189 && gpr_or_gpr_p (operands[0], operands[1])"
8190 [(pc)]
8191 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8192 \f
8193 (define_expand "load_multiple"
8194 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8195 (match_operand:SI 1 "" ""))
8196 (use (match_operand:SI 2 "" ""))])]
8197 "TARGET_STRING && !TARGET_POWERPC64"
8198 "
8199 {
8200 int regno;
8201 int count;
8202 rtx op1;
8203 int i;
8205 /* Support only loading a constant number of fixed-point registers from
8206 memory and only bother with this if more than two; the machine
8207 doesn't support more than eight. */
8208 if (GET_CODE (operands[2]) != CONST_INT
8209 || INTVAL (operands[2]) <= 2
8210 || INTVAL (operands[2]) > 8
8211 || GET_CODE (operands[1]) != MEM
8212 || GET_CODE (operands[0]) != REG
8213 || REGNO (operands[0]) >= 32)
8214 FAIL;
8216 count = INTVAL (operands[2]);
8217 regno = REGNO (operands[0]);
8219 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8220 op1 = replace_equiv_address (operands[1],
8221 force_reg (SImode, XEXP (operands[1], 0)));
8223 for (i = 0; i < count; i++)
8224 XVECEXP (operands[3], 0, i)
8225 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8226 adjust_address_nv (op1, SImode, i * 4));
8227 }")
8229 (define_insn "*ldmsi8"
8230 [(match_parallel 0 "load_multiple_operation"
8231 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8232 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8233 (set (match_operand:SI 3 "gpc_reg_operand" "")
8234 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8235 (set (match_operand:SI 4 "gpc_reg_operand" "")
8236 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8237 (set (match_operand:SI 5 "gpc_reg_operand" "")
8238 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8239 (set (match_operand:SI 6 "gpc_reg_operand" "")
8240 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8241 (set (match_operand:SI 7 "gpc_reg_operand" "")
8242 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8243 (set (match_operand:SI 8 "gpc_reg_operand" "")
8244 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8245 (set (match_operand:SI 9 "gpc_reg_operand" "")
8246 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8247 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8248 "*
8249 { return rs6000_output_load_multiple (operands); }"
8250 [(set_attr "type" "load")
8251 (set_attr "length" "32")])
8253 (define_insn "*ldmsi7"
8254 [(match_parallel 0 "load_multiple_operation"
8255 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8256 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8257 (set (match_operand:SI 3 "gpc_reg_operand" "")
8258 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8259 (set (match_operand:SI 4 "gpc_reg_operand" "")
8260 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8261 (set (match_operand:SI 5 "gpc_reg_operand" "")
8262 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8263 (set (match_operand:SI 6 "gpc_reg_operand" "")
8264 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8265 (set (match_operand:SI 7 "gpc_reg_operand" "")
8266 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8267 (set (match_operand:SI 8 "gpc_reg_operand" "")
8268 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8269 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8270 "*
8271 { return rs6000_output_load_multiple (operands); }"
8272 [(set_attr "type" "load")
8273 (set_attr "length" "32")])
8275 (define_insn "*ldmsi6"
8276 [(match_parallel 0 "load_multiple_operation"
8277 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8278 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8279 (set (match_operand:SI 3 "gpc_reg_operand" "")
8280 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8281 (set (match_operand:SI 4 "gpc_reg_operand" "")
8282 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8283 (set (match_operand:SI 5 "gpc_reg_operand" "")
8284 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8285 (set (match_operand:SI 6 "gpc_reg_operand" "")
8286 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8287 (set (match_operand:SI 7 "gpc_reg_operand" "")
8288 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8289 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8290 "*
8291 { return rs6000_output_load_multiple (operands); }"
8292 [(set_attr "type" "load")
8293 (set_attr "length" "32")])
8295 (define_insn "*ldmsi5"
8296 [(match_parallel 0 "load_multiple_operation"
8297 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8298 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8299 (set (match_operand:SI 3 "gpc_reg_operand" "")
8300 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8301 (set (match_operand:SI 4 "gpc_reg_operand" "")
8302 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8303 (set (match_operand:SI 5 "gpc_reg_operand" "")
8304 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8305 (set (match_operand:SI 6 "gpc_reg_operand" "")
8306 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8307 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8308 "*
8309 { return rs6000_output_load_multiple (operands); }"
8310 [(set_attr "type" "load")
8311 (set_attr "length" "32")])
8313 (define_insn "*ldmsi4"
8314 [(match_parallel 0 "load_multiple_operation"
8315 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8316 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8317 (set (match_operand:SI 3 "gpc_reg_operand" "")
8318 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8319 (set (match_operand:SI 4 "gpc_reg_operand" "")
8320 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8321 (set (match_operand:SI 5 "gpc_reg_operand" "")
8322 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8323 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8324 "*
8325 { return rs6000_output_load_multiple (operands); }"
8326 [(set_attr "type" "load")
8327 (set_attr "length" "32")])
8329 (define_insn "*ldmsi3"
8330 [(match_parallel 0 "load_multiple_operation"
8331 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8332 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8333 (set (match_operand:SI 3 "gpc_reg_operand" "")
8334 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8335 (set (match_operand:SI 4 "gpc_reg_operand" "")
8336 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8337 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8338 "*
8339 { return rs6000_output_load_multiple (operands); }"
8340 [(set_attr "type" "load")
8341 (set_attr "length" "32")])
8343 (define_expand "store_multiple"
8344 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8345 (match_operand:SI 1 "" ""))
8346 (clobber (scratch:SI))
8347 (use (match_operand:SI 2 "" ""))])]
8348 "TARGET_STRING && !TARGET_POWERPC64"
8349 "
8350 {
8351 int regno;
8352 int count;
8353 rtx to;
8354 rtx op0;
8355 int i;
8357 /* Support only storing a constant number of fixed-point registers to
8358 memory and only bother with this if more than two; the machine
8359 doesn't support more than eight. */
8360 if (GET_CODE (operands[2]) != CONST_INT
8361 || INTVAL (operands[2]) <= 2
8362 || INTVAL (operands[2]) > 8
8363 || GET_CODE (operands[0]) != MEM
8364 || GET_CODE (operands[1]) != REG
8365 || REGNO (operands[1]) >= 32)
8366 FAIL;
8368 count = INTVAL (operands[2]);
8369 regno = REGNO (operands[1]);
8371 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8372 to = force_reg (SImode, XEXP (operands[0], 0));
8373 op0 = replace_equiv_address (operands[0], to);
8375 XVECEXP (operands[3], 0, 0)
8376 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8377 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8378 gen_rtx_SCRATCH (SImode));
8380 for (i = 1; i < count; i++)
8381 XVECEXP (operands[3], 0, i + 1)
8382 = gen_rtx_SET (VOIDmode,
8383 adjust_address_nv (op0, SImode, i * 4),
8384 gen_rtx_REG (SImode, regno + i));
8385 }")
8387 (define_insn "*store_multiple_power"
8388 [(match_parallel 0 "store_multiple_operation"
8389 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8390 (match_operand:SI 2 "gpc_reg_operand" "r"))
8391 (clobber (match_scratch:SI 3 "=q"))])]
8392 "TARGET_STRING && TARGET_POWER"
8393 "{stsi|stswi} %2,%P1,%O0"
8394 [(set_attr "type" "store")])
8396 (define_insn "*stmsi8"
8397 [(match_parallel 0 "store_multiple_operation"
8398 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8399 (match_operand:SI 2 "gpc_reg_operand" "r"))
8400 (clobber (match_scratch:SI 3 "X"))
8401 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8402 (match_operand:SI 4 "gpc_reg_operand" "r"))
8403 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8404 (match_operand:SI 5 "gpc_reg_operand" "r"))
8405 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8406 (match_operand:SI 6 "gpc_reg_operand" "r"))
8407 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8408 (match_operand:SI 7 "gpc_reg_operand" "r"))
8409 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8410 (match_operand:SI 8 "gpc_reg_operand" "r"))
8411 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8412 (match_operand:SI 9 "gpc_reg_operand" "r"))
8413 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8414 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8415 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8416 "{stsi|stswi} %2,%1,%O0"
8417 [(set_attr "type" "store")])
8419 (define_insn "*stmsi7"
8420 [(match_parallel 0 "store_multiple_operation"
8421 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8422 (match_operand:SI 2 "gpc_reg_operand" "r"))
8423 (clobber (match_scratch:SI 3 "X"))
8424 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8425 (match_operand:SI 4 "gpc_reg_operand" "r"))
8426 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8427 (match_operand:SI 5 "gpc_reg_operand" "r"))
8428 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8429 (match_operand:SI 6 "gpc_reg_operand" "r"))
8430 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8431 (match_operand:SI 7 "gpc_reg_operand" "r"))
8432 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8433 (match_operand:SI 8 "gpc_reg_operand" "r"))
8434 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8435 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8436 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8437 "{stsi|stswi} %2,%1,%O0"
8438 [(set_attr "type" "store")])
8440 (define_insn "*stmsi6"
8441 [(match_parallel 0 "store_multiple_operation"
8442 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8443 (match_operand:SI 2 "gpc_reg_operand" "r"))
8444 (clobber (match_scratch:SI 3 "X"))
8445 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8446 (match_operand:SI 4 "gpc_reg_operand" "r"))
8447 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8448 (match_operand:SI 5 "gpc_reg_operand" "r"))
8449 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8450 (match_operand:SI 6 "gpc_reg_operand" "r"))
8451 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8452 (match_operand:SI 7 "gpc_reg_operand" "r"))
8453 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8454 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8455 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8456 "{stsi|stswi} %2,%1,%O0"
8457 [(set_attr "type" "store")])
8459 (define_insn "*stmsi5"
8460 [(match_parallel 0 "store_multiple_operation"
8461 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8462 (match_operand:SI 2 "gpc_reg_operand" "r"))
8463 (clobber (match_scratch:SI 3 "X"))
8464 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8465 (match_operand:SI 4 "gpc_reg_operand" "r"))
8466 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8467 (match_operand:SI 5 "gpc_reg_operand" "r"))
8468 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8469 (match_operand:SI 6 "gpc_reg_operand" "r"))
8470 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8471 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8472 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8473 "{stsi|stswi} %2,%1,%O0"
8474 [(set_attr "type" "store")])
8476 (define_insn "*stmsi4"
8477 [(match_parallel 0 "store_multiple_operation"
8478 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8479 (match_operand:SI 2 "gpc_reg_operand" "r"))
8480 (clobber (match_scratch:SI 3 "X"))
8481 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8482 (match_operand:SI 4 "gpc_reg_operand" "r"))
8483 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8484 (match_operand:SI 5 "gpc_reg_operand" "r"))
8485 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8486 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8487 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8488 "{stsi|stswi} %2,%1,%O0"
8489 [(set_attr "type" "store")])
8491 (define_insn "*stmsi3"
8492 [(match_parallel 0 "store_multiple_operation"
8493 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8494 (match_operand:SI 2 "gpc_reg_operand" "r"))
8495 (clobber (match_scratch:SI 3 "X"))
8496 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8497 (match_operand:SI 4 "gpc_reg_operand" "r"))
8498 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8499 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8500 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8501 "{stsi|stswi} %2,%1,%O0"
8502 [(set_attr "type" "store")])
8503 \f
8504 (define_expand "setmemsi"
8505 [(parallel [(set (match_operand:BLK 0 "" "")
8506 (match_operand 2 "const_int_operand" ""))
8507 (use (match_operand:SI 1 "" ""))
8508 (use (match_operand:SI 3 "" ""))])]
8509 ""
8510 "
8511 {
8512 /* If value to set is not zero, use the library routine. */
8513 if (operands[2] != const0_rtx)
8514 FAIL;
8516 if (expand_block_clear (operands))
8517 DONE;
8518 else
8519 FAIL;
8520 }")
8522 ;; String/block move insn.
8523 ;; Argument 0 is the destination
8524 ;; Argument 1 is the source
8525 ;; Argument 2 is the length
8526 ;; Argument 3 is the alignment
8528 (define_expand "movmemsi"
8529 [(parallel [(set (match_operand:BLK 0 "" "")
8530 (match_operand:BLK 1 "" ""))
8531 (use (match_operand:SI 2 "" ""))
8532 (use (match_operand:SI 3 "" ""))])]
8533 ""
8534 "
8535 {
8536 if (expand_block_move (operands))
8537 DONE;
8538 else
8539 FAIL;
8540 }")
8542 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8543 ;; register allocator doesn't have a clue about allocating 8 word registers.
8544 ;; rD/rS = r5 is preferred, efficient form.
8545 (define_expand "movmemsi_8reg"
8546 [(parallel [(set (match_operand 0 "" "")
8547 (match_operand 1 "" ""))
8548 (use (match_operand 2 "" ""))
8549 (use (match_operand 3 "" ""))
8550 (clobber (reg:SI 5))
8551 (clobber (reg:SI 6))
8552 (clobber (reg:SI 7))
8553 (clobber (reg:SI 8))
8554 (clobber (reg:SI 9))
8555 (clobber (reg:SI 10))
8556 (clobber (reg:SI 11))
8557 (clobber (reg:SI 12))
8558 (clobber (match_scratch:SI 4 ""))])]
8559 "TARGET_STRING"
8560 "")
8562 (define_insn ""
8563 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8564 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8565 (use (match_operand:SI 2 "immediate_operand" "i"))
8566 (use (match_operand:SI 3 "immediate_operand" "i"))
8567 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8568 (clobber (reg:SI 6))
8569 (clobber (reg:SI 7))
8570 (clobber (reg:SI 8))
8571 (clobber (reg:SI 9))
8572 (clobber (reg:SI 10))
8573 (clobber (reg:SI 11))
8574 (clobber (reg:SI 12))
8575 (clobber (match_scratch:SI 5 "=q"))]
8576 "TARGET_STRING && TARGET_POWER
8577 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8578 || INTVAL (operands[2]) == 0)
8579 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8580 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8581 && REGNO (operands[4]) == 5"
8582 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8583 [(set_attr "type" "load")
8584 (set_attr "length" "8")])
8586 (define_insn ""
8587 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8588 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8589 (use (match_operand:SI 2 "immediate_operand" "i"))
8590 (use (match_operand:SI 3 "immediate_operand" "i"))
8591 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8592 (clobber (reg:SI 6))
8593 (clobber (reg:SI 7))
8594 (clobber (reg:SI 8))
8595 (clobber (reg:SI 9))
8596 (clobber (reg:SI 10))
8597 (clobber (reg:SI 11))
8598 (clobber (reg:SI 12))
8599 (clobber (match_scratch:SI 5 "X"))]
8600 "TARGET_STRING && ! TARGET_POWER
8601 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8602 || INTVAL (operands[2]) == 0)
8603 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8604 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8605 && REGNO (operands[4]) == 5"
8606 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8607 [(set_attr "type" "load")
8608 (set_attr "length" "8")])
8610 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8611 ;; register allocator doesn't have a clue about allocating 6 word registers.
8612 ;; rD/rS = r5 is preferred, efficient form.
8613 (define_expand "movmemsi_6reg"
8614 [(parallel [(set (match_operand 0 "" "")
8615 (match_operand 1 "" ""))
8616 (use (match_operand 2 "" ""))
8617 (use (match_operand 3 "" ""))
8618 (clobber (reg:SI 5))
8619 (clobber (reg:SI 6))
8620 (clobber (reg:SI 7))
8621 (clobber (reg:SI 8))
8622 (clobber (reg:SI 9))
8623 (clobber (reg:SI 10))
8624 (clobber (match_scratch:SI 4 ""))])]
8625 "TARGET_STRING"
8626 "")
8628 (define_insn ""
8629 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8630 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8631 (use (match_operand:SI 2 "immediate_operand" "i"))
8632 (use (match_operand:SI 3 "immediate_operand" "i"))
8633 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8634 (clobber (reg:SI 6))
8635 (clobber (reg:SI 7))
8636 (clobber (reg:SI 8))
8637 (clobber (reg:SI 9))
8638 (clobber (reg:SI 10))
8639 (clobber (match_scratch:SI 5 "=q"))]
8640 "TARGET_STRING && TARGET_POWER
8641 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8642 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8643 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8644 && REGNO (operands[4]) == 5"
8645 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8646 [(set_attr "type" "load")
8647 (set_attr "length" "8")])
8649 (define_insn ""
8650 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8651 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8652 (use (match_operand:SI 2 "immediate_operand" "i"))
8653 (use (match_operand:SI 3 "immediate_operand" "i"))
8654 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8655 (clobber (reg:SI 6))
8656 (clobber (reg:SI 7))
8657 (clobber (reg:SI 8))
8658 (clobber (reg:SI 9))
8659 (clobber (reg:SI 10))
8660 (clobber (match_scratch:SI 5 "X"))]
8661 "TARGET_STRING && ! TARGET_POWER
8662 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8663 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8664 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8665 && REGNO (operands[4]) == 5"
8666 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8667 [(set_attr "type" "load")
8668 (set_attr "length" "8")])
8670 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8671 ;; problems with TImode.
8672 ;; rD/rS = r5 is preferred, efficient form.
8673 (define_expand "movmemsi_4reg"
8674 [(parallel [(set (match_operand 0 "" "")
8675 (match_operand 1 "" ""))
8676 (use (match_operand 2 "" ""))
8677 (use (match_operand 3 "" ""))
8678 (clobber (reg:SI 5))
8679 (clobber (reg:SI 6))
8680 (clobber (reg:SI 7))
8681 (clobber (reg:SI 8))
8682 (clobber (match_scratch:SI 4 ""))])]
8683 "TARGET_STRING"
8684 "")
8686 (define_insn ""
8687 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8688 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8689 (use (match_operand:SI 2 "immediate_operand" "i"))
8690 (use (match_operand:SI 3 "immediate_operand" "i"))
8691 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8692 (clobber (reg:SI 6))
8693 (clobber (reg:SI 7))
8694 (clobber (reg:SI 8))
8695 (clobber (match_scratch:SI 5 "=q"))]
8696 "TARGET_STRING && TARGET_POWER
8697 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8698 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8699 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8700 && REGNO (operands[4]) == 5"
8701 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8702 [(set_attr "type" "load")
8703 (set_attr "length" "8")])
8705 (define_insn ""
8706 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8707 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8708 (use (match_operand:SI 2 "immediate_operand" "i"))
8709 (use (match_operand:SI 3 "immediate_operand" "i"))
8710 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8711 (clobber (reg:SI 6))
8712 (clobber (reg:SI 7))
8713 (clobber (reg:SI 8))
8714 (clobber (match_scratch:SI 5 "X"))]
8715 "TARGET_STRING && ! TARGET_POWER
8716 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8717 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8718 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8719 && REGNO (operands[4]) == 5"
8720 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8721 [(set_attr "type" "load")
8722 (set_attr "length" "8")])
8724 ;; Move up to 8 bytes at a time.
8725 (define_expand "movmemsi_2reg"
8726 [(parallel [(set (match_operand 0 "" "")
8727 (match_operand 1 "" ""))
8728 (use (match_operand 2 "" ""))
8729 (use (match_operand 3 "" ""))
8730 (clobber (match_scratch:DI 4 ""))
8731 (clobber (match_scratch:SI 5 ""))])]
8732 "TARGET_STRING && ! TARGET_POWERPC64"
8733 "")
8735 (define_insn ""
8736 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8737 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8738 (use (match_operand:SI 2 "immediate_operand" "i"))
8739 (use (match_operand:SI 3 "immediate_operand" "i"))
8740 (clobber (match_scratch:DI 4 "=&r"))
8741 (clobber (match_scratch:SI 5 "=q"))]
8742 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8743 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8744 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8745 [(set_attr "type" "load")
8746 (set_attr "length" "8")])
8748 (define_insn ""
8749 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8750 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8751 (use (match_operand:SI 2 "immediate_operand" "i"))
8752 (use (match_operand:SI 3 "immediate_operand" "i"))
8753 (clobber (match_scratch:DI 4 "=&r"))
8754 (clobber (match_scratch:SI 5 "X"))]
8755 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8756 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8757 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8758 [(set_attr "type" "load")
8759 (set_attr "length" "8")])
8761 ;; Move up to 4 bytes at a time.
8762 (define_expand "movmemsi_1reg"
8763 [(parallel [(set (match_operand 0 "" "")
8764 (match_operand 1 "" ""))
8765 (use (match_operand 2 "" ""))
8766 (use (match_operand 3 "" ""))
8767 (clobber (match_scratch:SI 4 ""))
8768 (clobber (match_scratch:SI 5 ""))])]
8769 "TARGET_STRING"
8770 "")
8772 (define_insn ""
8773 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8774 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8775 (use (match_operand:SI 2 "immediate_operand" "i"))
8776 (use (match_operand:SI 3 "immediate_operand" "i"))
8777 (clobber (match_scratch:SI 4 "=&r"))
8778 (clobber (match_scratch:SI 5 "=q"))]
8779 "TARGET_STRING && TARGET_POWER
8780 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8781 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8782 [(set_attr "type" "load")
8783 (set_attr "length" "8")])
8785 (define_insn ""
8786 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8787 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8788 (use (match_operand:SI 2 "immediate_operand" "i"))
8789 (use (match_operand:SI 3 "immediate_operand" "i"))
8790 (clobber (match_scratch:SI 4 "=&r"))
8791 (clobber (match_scratch:SI 5 "X"))]
8792 "TARGET_STRING && ! TARGET_POWER
8793 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8794 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8795 [(set_attr "type" "load")
8796 (set_attr "length" "8")])
8797 \f
8798 ;; Define insns that do load or store with update. Some of these we can
8799 ;; get by using pre-decrement or pre-increment, but the hardware can also
8800 ;; do cases where the increment is not the size of the object.
8801 ;;
8802 ;; In all these cases, we use operands 0 and 1 for the register being
8803 ;; incremented because those are the operands that local-alloc will
8804 ;; tie and these are the pair most likely to be tieable (and the ones
8805 ;; that will benefit the most).
8807 (define_insn "*movdi_update1"
8808 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8809 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8810 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
8811 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8812 (plus:DI (match_dup 1) (match_dup 2)))]
8813 "TARGET_POWERPC64 && TARGET_UPDATE"
8814 "@
8815 ldux %3,%0,%2
8816 ldu %3,%2(%0)"
8817 [(set_attr "type" "load_ux,load_u")])
8819 (define_insn "movdi_<mode>_update"
8820 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
8821 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
8822 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8823 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
8824 (plus:P (match_dup 1) (match_dup 2)))]
8825 "TARGET_POWERPC64 && TARGET_UPDATE"
8826 "@
8827 stdux %3,%0,%2
8828 stdu %3,%2(%0)"
8829 [(set_attr "type" "store_ux,store_u")])
8831 (define_insn "*movsi_update1"
8832 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8833 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8834 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8835 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8836 (plus:SI (match_dup 1) (match_dup 2)))]
8837 "TARGET_UPDATE"
8838 "@
8839 {lux|lwzux} %3,%0,%2
8840 {lu|lwzu} %3,%2(%0)"
8841 [(set_attr "type" "load_ux,load_u")])
8843 (define_insn "*movsi_update2"
8844 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8845 (sign_extend:DI
8846 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8847 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8848 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8849 (plus:DI (match_dup 1) (match_dup 2)))]
8850 "TARGET_POWERPC64"
8851 "lwaux %3,%0,%2"
8852 [(set_attr "type" "load_ext_ux")])
8854 (define_insn "movsi_update"
8855 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8856 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8857 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8858 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8859 (plus:SI (match_dup 1) (match_dup 2)))]
8860 "TARGET_UPDATE"
8861 "@
8862 {stux|stwux} %3,%0,%2
8863 {stu|stwu} %3,%2(%0)"
8864 [(set_attr "type" "store_ux,store_u")])
8866 (define_insn "*movhi_update1"
8867 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8868 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8869 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8870 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8871 (plus:SI (match_dup 1) (match_dup 2)))]
8872 "TARGET_UPDATE"
8873 "@
8874 lhzux %3,%0,%2
8875 lhzu %3,%2(%0)"
8876 [(set_attr "type" "load_ux,load_u")])
8878 (define_insn "*movhi_update2"
8879 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8880 (zero_extend:SI
8881 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8882 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8883 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8884 (plus:SI (match_dup 1) (match_dup 2)))]
8885 "TARGET_UPDATE"
8886 "@
8887 lhzux %3,%0,%2
8888 lhzu %3,%2(%0)"
8889 [(set_attr "type" "load_ux,load_u")])
8891 (define_insn "*movhi_update3"
8892 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8893 (sign_extend:SI
8894 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8895 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8896 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8897 (plus:SI (match_dup 1) (match_dup 2)))]
8898 "TARGET_UPDATE"
8899 "@
8900 lhaux %3,%0,%2
8901 lhau %3,%2(%0)"
8902 [(set_attr "type" "load_ext_ux,load_ext_u")])
8904 (define_insn "*movhi_update4"
8905 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8906 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8907 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
8908 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8909 (plus:SI (match_dup 1) (match_dup 2)))]
8910 "TARGET_UPDATE"
8911 "@
8912 sthux %3,%0,%2
8913 sthu %3,%2(%0)"
8914 [(set_attr "type" "store_ux,store_u")])
8916 (define_insn "*movqi_update1"
8917 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
8918 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8919 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8920 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8921 (plus:SI (match_dup 1) (match_dup 2)))]
8922 "TARGET_UPDATE"
8923 "@
8924 lbzux %3,%0,%2
8925 lbzu %3,%2(%0)"
8926 [(set_attr "type" "load_ux,load_u")])
8928 (define_insn "*movqi_update2"
8929 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8930 (zero_extend:SI
8931 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8932 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8933 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8934 (plus:SI (match_dup 1) (match_dup 2)))]
8935 "TARGET_UPDATE"
8936 "@
8937 lbzux %3,%0,%2
8938 lbzu %3,%2(%0)"
8939 [(set_attr "type" "load_ux,load_u")])
8941 (define_insn "*movqi_update3"
8942 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8943 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8944 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
8945 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8946 (plus:SI (match_dup 1) (match_dup 2)))]
8947 "TARGET_UPDATE"
8948 "@
8949 stbux %3,%0,%2
8950 stbu %3,%2(%0)"
8951 [(set_attr "type" "store_ux,store_u")])
8953 (define_insn "*movsf_update1"
8954 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
8955 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8956 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8957 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8958 (plus:SI (match_dup 1) (match_dup 2)))]
8959 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
8960 "@
8961 lfsux %3,%0,%2
8962 lfsu %3,%2(%0)"
8963 [(set_attr "type" "fpload_ux,fpload_u")])
8965 (define_insn "*movsf_update2"
8966 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8967 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8968 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
8969 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8970 (plus:SI (match_dup 1) (match_dup 2)))]
8971 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
8972 "@
8973 stfsux %3,%0,%2
8974 stfsu %3,%2(%0)"
8975 [(set_attr "type" "fpstore_ux,fpstore_u")])
8977 (define_insn "*movsf_update3"
8978 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
8979 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8980 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8981 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8982 (plus:SI (match_dup 1) (match_dup 2)))]
8983 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
8984 "@
8985 {lux|lwzux} %3,%0,%2
8986 {lu|lwzu} %3,%2(%0)"
8987 [(set_attr "type" "load_ux,load_u")])
8989 (define_insn "*movsf_update4"
8990 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8991 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8992 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
8993 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8994 (plus:SI (match_dup 1) (match_dup 2)))]
8995 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
8996 "@
8997 {stux|stwux} %3,%0,%2
8998 {stu|stwu} %3,%2(%0)"
8999 [(set_attr "type" "store_ux,store_u")])
9001 (define_insn "*movdf_update1"
9002 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9003 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9004 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9005 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9006 (plus:SI (match_dup 1) (match_dup 2)))]
9007 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9008 "@
9009 lfdux %3,%0,%2
9010 lfdu %3,%2(%0)"
9011 [(set_attr "type" "fpload_ux,fpload_u")])
9013 (define_insn "*movdf_update2"
9014 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9015 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9016 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9017 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9018 (plus:SI (match_dup 1) (match_dup 2)))]
9019 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9020 "@
9021 stfdux %3,%0,%2
9022 stfdu %3,%2(%0)"
9023 [(set_attr "type" "fpstore_ux,fpstore_u")])
9025 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9027 (define_insn "*lfq_power2"
9028 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9029 (match_operand:V2DF 1 "memory_operand" ""))]
9030 "TARGET_POWER2
9031 && TARGET_HARD_FLOAT && TARGET_FPRS"
9032 "lfq%U1%X1 %0,%1")
9034 (define_peephole2
9035 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9036 (match_operand:DF 1 "memory_operand" ""))
9037 (set (match_operand:DF 2 "gpc_reg_operand" "")
9038 (match_operand:DF 3 "memory_operand" ""))]
9039 "TARGET_POWER2
9040 && TARGET_HARD_FLOAT && TARGET_FPRS
9041 && registers_ok_for_quad_peep (operands[0], operands[2])
9042 && mems_ok_for_quad_peep (operands[1], operands[3])"
9043 [(set (match_dup 0)
9044 (match_dup 1))]
9045 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9046 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9048 (define_insn "*stfq_power2"
9049 [(set (match_operand:V2DF 0 "memory_operand" "")
9050 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9051 "TARGET_POWER2
9052 && TARGET_HARD_FLOAT && TARGET_FPRS"
9053 "stfq%U0%X0 %1,%0")
9056 (define_peephole2
9057 [(set (match_operand:DF 0 "memory_operand" "")
9058 (match_operand:DF 1 "gpc_reg_operand" ""))
9059 (set (match_operand:DF 2 "memory_operand" "")
9060 (match_operand:DF 3 "gpc_reg_operand" ""))]
9061 "TARGET_POWER2
9062 && TARGET_HARD_FLOAT && TARGET_FPRS
9063 && registers_ok_for_quad_peep (operands[1], operands[3])
9064 && mems_ok_for_quad_peep (operands[0], operands[2])"
9065 [(set (match_dup 0)
9066 (match_dup 1))]
9067 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9068 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9070 ;; after inserting conditional returns we can sometimes have
9071 ;; unnecessary register moves. Unfortunately we cannot have a
9072 ;; modeless peephole here, because some single SImode sets have early
9073 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9074 ;; sequences, using get_attr_length here will smash the operands
9075 ;; array. Neither is there an early_cobbler_p predicate.
9076 (define_peephole2
9077 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9078 (match_operand:DF 1 "any_operand" ""))
9079 (set (match_operand:DF 2 "gpc_reg_operand" "")
9080 (match_dup 0))]
9081 "peep2_reg_dead_p (2, operands[0])"
9082 [(set (match_dup 2) (match_dup 1))])
9084 (define_peephole2
9085 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9086 (match_operand:SF 1 "any_operand" ""))
9087 (set (match_operand:SF 2 "gpc_reg_operand" "")
9088 (match_dup 0))]
9089 "peep2_reg_dead_p (2, operands[0])"
9090 [(set (match_dup 2) (match_dup 1))])
9092 \f
9093 ;; TLS support.
9095 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9096 (define_insn "tls_gd_32"
9097 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9098 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9099 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9100 UNSPEC_TLSGD))]
9101 "HAVE_AS_TLS && !TARGET_64BIT"
9102 "addi %0,%1,%2@got@tlsgd")
9104 (define_insn "tls_gd_64"
9105 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9106 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9107 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9108 UNSPEC_TLSGD))]
9109 "HAVE_AS_TLS && TARGET_64BIT"
9110 "addi %0,%1,%2@got@tlsgd")
9112 (define_insn "tls_ld_32"
9113 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9114 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9115 UNSPEC_TLSLD))]
9116 "HAVE_AS_TLS && !TARGET_64BIT"
9117 "addi %0,%1,%&@got@tlsld")
9119 (define_insn "tls_ld_64"
9120 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9121 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9122 UNSPEC_TLSLD))]
9123 "HAVE_AS_TLS && TARGET_64BIT"
9124 "addi %0,%1,%&@got@tlsld")
9126 (define_insn "tls_dtprel_32"
9127 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9128 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9129 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9130 UNSPEC_TLSDTPREL))]
9131 "HAVE_AS_TLS && !TARGET_64BIT"
9132 "addi %0,%1,%2@dtprel")
9134 (define_insn "tls_dtprel_64"
9135 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9136 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9137 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9138 UNSPEC_TLSDTPREL))]
9139 "HAVE_AS_TLS && TARGET_64BIT"
9140 "addi %0,%1,%2@dtprel")
9142 (define_insn "tls_dtprel_ha_32"
9143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9144 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9145 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9146 UNSPEC_TLSDTPRELHA))]
9147 "HAVE_AS_TLS && !TARGET_64BIT"
9148 "addis %0,%1,%2@dtprel@ha")
9150 (define_insn "tls_dtprel_ha_64"
9151 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9152 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9153 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9154 UNSPEC_TLSDTPRELHA))]
9155 "HAVE_AS_TLS && TARGET_64BIT"
9156 "addis %0,%1,%2@dtprel@ha")
9158 (define_insn "tls_dtprel_lo_32"
9159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9160 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9161 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9162 UNSPEC_TLSDTPRELLO))]
9163 "HAVE_AS_TLS && !TARGET_64BIT"
9164 "addi %0,%1,%2@dtprel@l")
9166 (define_insn "tls_dtprel_lo_64"
9167 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9168 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9169 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9170 UNSPEC_TLSDTPRELLO))]
9171 "HAVE_AS_TLS && TARGET_64BIT"
9172 "addi %0,%1,%2@dtprel@l")
9174 (define_insn "tls_got_dtprel_32"
9175 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9176 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9177 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9178 UNSPEC_TLSGOTDTPREL))]
9179 "HAVE_AS_TLS && !TARGET_64BIT"
9180 "lwz %0,%2@got@dtprel(%1)")
9182 (define_insn "tls_got_dtprel_64"
9183 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9184 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9185 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9186 UNSPEC_TLSGOTDTPREL))]
9187 "HAVE_AS_TLS && TARGET_64BIT"
9188 "ld %0,%2@got@dtprel(%1)")
9190 (define_insn "tls_tprel_32"
9191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9192 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9193 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9194 UNSPEC_TLSTPREL))]
9195 "HAVE_AS_TLS && !TARGET_64BIT"
9196 "addi %0,%1,%2@tprel")
9198 (define_insn "tls_tprel_64"
9199 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9200 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9201 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9202 UNSPEC_TLSTPREL))]
9203 "HAVE_AS_TLS && TARGET_64BIT"
9204 "addi %0,%1,%2@tprel")
9206 (define_insn "tls_tprel_ha_32"
9207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9208 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9209 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9210 UNSPEC_TLSTPRELHA))]
9211 "HAVE_AS_TLS && !TARGET_64BIT"
9212 "addis %0,%1,%2@tprel@ha")
9214 (define_insn "tls_tprel_ha_64"
9215 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9216 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9217 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9218 UNSPEC_TLSTPRELHA))]
9219 "HAVE_AS_TLS && TARGET_64BIT"
9220 "addis %0,%1,%2@tprel@ha")
9222 (define_insn "tls_tprel_lo_32"
9223 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9224 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9225 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9226 UNSPEC_TLSTPRELLO))]
9227 "HAVE_AS_TLS && !TARGET_64BIT"
9228 "addi %0,%1,%2@tprel@l")
9230 (define_insn "tls_tprel_lo_64"
9231 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9232 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9233 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9234 UNSPEC_TLSTPRELLO))]
9235 "HAVE_AS_TLS && TARGET_64BIT"
9236 "addi %0,%1,%2@tprel@l")
9238 ;; "b" output constraint here and on tls_tls input to support linker tls
9239 ;; optimization. The linker may edit the instructions emitted by a
9240 ;; tls_got_tprel/tls_tls pair to addis,addi.
9241 (define_insn "tls_got_tprel_32"
9242 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9243 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9244 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9245 UNSPEC_TLSGOTTPREL))]
9246 "HAVE_AS_TLS && !TARGET_64BIT"
9247 "lwz %0,%2@got@tprel(%1)")
9249 (define_insn "tls_got_tprel_64"
9250 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9251 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9252 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9253 UNSPEC_TLSGOTTPREL))]
9254 "HAVE_AS_TLS && TARGET_64BIT"
9255 "ld %0,%2@got@tprel(%1)")
9257 (define_insn "tls_tls_32"
9258 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9259 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9260 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9261 UNSPEC_TLSTLS))]
9262 "HAVE_AS_TLS && !TARGET_64BIT"
9263 "add %0,%1,%2@tls")
9265 (define_insn "tls_tls_64"
9266 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9267 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9268 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9269 UNSPEC_TLSTLS))]
9270 "HAVE_AS_TLS && TARGET_64BIT"
9271 "add %0,%1,%2@tls")
9272 \f
9273 ;; Next come insns related to the calling sequence.
9274 ;;
9275 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9276 ;; We move the back-chain and decrement the stack pointer.
9278 (define_expand "allocate_stack"
9279 [(set (match_operand 0 "gpc_reg_operand" "=r")
9280 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9281 (set (reg 1)
9282 (minus (reg 1) (match_dup 1)))]
9283 ""
9284 "
9285 { rtx chain = gen_reg_rtx (Pmode);
9286 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9287 rtx neg_op0;
9289 emit_move_insn (chain, stack_bot);
9291 /* Check stack bounds if necessary. */
9292 if (current_function_limit_stack)
9293 {
9294 rtx available;
9295 available = expand_binop (Pmode, sub_optab,
9296 stack_pointer_rtx, stack_limit_rtx,
9297 NULL_RTX, 1, OPTAB_WIDEN);
9298 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9299 }
9301 if (GET_CODE (operands[1]) != CONST_INT
9302 || INTVAL (operands[1]) < -32767
9303 || INTVAL (operands[1]) > 32768)
9304 {
9305 neg_op0 = gen_reg_rtx (Pmode);
9306 if (TARGET_32BIT)
9307 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9308 else
9309 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9310 }
9311 else
9312 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9314 if (TARGET_UPDATE)
9315 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9316 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9318 else
9319 {
9320 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9321 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9322 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9323 }
9325 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9326 DONE;
9327 }")
9329 ;; These patterns say how to save and restore the stack pointer. We need not
9330 ;; save the stack pointer at function level since we are careful to
9331 ;; preserve the backchain. At block level, we have to restore the backchain
9332 ;; when we restore the stack pointer.
9333 ;;
9334 ;; For nonlocal gotos, we must save both the stack pointer and its
9335 ;; backchain and restore both. Note that in the nonlocal case, the
9336 ;; save area is a memory location.
9338 (define_expand "save_stack_function"
9339 [(match_operand 0 "any_operand" "")
9340 (match_operand 1 "any_operand" "")]
9341 ""
9342 "DONE;")
9344 (define_expand "restore_stack_function"
9345 [(match_operand 0 "any_operand" "")
9346 (match_operand 1 "any_operand" "")]
9347 ""
9348 "DONE;")
9350 (define_expand "restore_stack_block"
9351 [(use (match_operand 0 "register_operand" ""))
9352 (set (match_dup 2) (match_dup 3))
9353 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9354 (set (match_dup 3) (match_dup 2))]
9355 ""
9356 "
9357 {
9358 operands[2] = gen_reg_rtx (Pmode);
9359 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9360 }")
9362 (define_expand "save_stack_nonlocal"
9363 [(match_operand 0 "memory_operand" "")
9364 (match_operand 1 "register_operand" "")]
9365 ""
9366 "
9367 {
9368 rtx temp = gen_reg_rtx (Pmode);
9369 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9371 /* Copy the backchain to the first word, sp to the second. */
9372 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9373 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9374 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9375 operands[1]);
9376 DONE;
9377 }")
9379 (define_expand "restore_stack_nonlocal"
9380 [(match_operand 0 "register_operand" "")
9381 (match_operand 1 "memory_operand" "")]
9382 ""
9383 "
9384 {
9385 rtx temp = gen_reg_rtx (Pmode);
9386 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9388 /* Restore the backchain from the first word, sp from the second. */
9389 emit_move_insn (temp,
9390 adjust_address_nv (operands[1], Pmode, 0));
9391 emit_move_insn (operands[0],
9392 adjust_address_nv (operands[1], Pmode, units_per_word));
9393 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9394 DONE;
9395 }")
9396 \f
9397 ;; TOC register handling.
9399 ;; Code to initialize the TOC register...
9401 (define_insn "load_toc_aix_si"
9402 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9403 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9404 (use (reg:SI 2))])]
9405 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9406 "*
9407 {
9408 char buf[30];
9409 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9410 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9411 operands[2] = gen_rtx_REG (Pmode, 2);
9412 return \"{l|lwz} %0,%1(%2)\";
9413 }"
9414 [(set_attr "type" "load")])
9416 (define_insn "load_toc_aix_di"
9417 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9418 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9419 (use (reg:DI 2))])]
9420 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9421 "*
9422 {
9423 char buf[30];
9424 #ifdef TARGET_RELOCATABLE
9425 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9426 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9427 #else
9428 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9429 #endif
9430 if (TARGET_ELF)
9431 strcat (buf, \"@toc\");
9432 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9433 operands[2] = gen_rtx_REG (Pmode, 2);
9434 return \"ld %0,%1(%2)\";
9435 }"
9436 [(set_attr "type" "load")])
9438 (define_insn "load_toc_v4_pic_si"
9439 [(set (match_operand:SI 0 "register_operand" "=l")
9440 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9441 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9442 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9443 [(set_attr "type" "branch")
9444 (set_attr "length" "4")])
9446 (define_insn "load_toc_v4_PIC_1"
9447 [(set (match_operand:SI 0 "register_operand" "=l")
9448 (match_operand:SI 1 "immediate_operand" "s"))
9449 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9450 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9451 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9452 "bcl 20,31,%1\\n%1:"
9453 [(set_attr "type" "branch")
9454 (set_attr "length" "4")])
9456 (define_insn "load_toc_v4_PIC_1b"
9457 [(set (match_operand:SI 0 "register_operand" "=l")
9458 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9459 UNSPEC_TOCPTR))]
9460 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9461 "bcl 20,31,$+8\\n\\t.long %1-$"
9462 [(set_attr "type" "branch")
9463 (set_attr "length" "8")])
9465 (define_insn "load_toc_v4_PIC_2"
9466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9467 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9468 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9469 (match_operand:SI 3 "immediate_operand" "s")))))]
9470 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9471 "{l|lwz} %0,%2-%3(%1)"
9472 [(set_attr "type" "load")])
9474 (define_insn "load_toc_v4_PIC_3b"
9475 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9476 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9477 (high:SI
9478 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9479 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9480 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9481 "{cau|addis} %0,%1,%2-%3@ha")
9483 (define_insn "load_toc_v4_PIC_3c"
9484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9485 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9486 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9487 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9488 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9489 "{cal|addi} %0,%1,%2-%3@l")
9491 ;; If the TOC is shared over a translation unit, as happens with all
9492 ;; the kinds of PIC that we support, we need to restore the TOC
9493 ;; pointer only when jumping over units of translation.
9494 ;; On Darwin, we need to reload the picbase.
9496 (define_expand "builtin_setjmp_receiver"
9497 [(use (label_ref (match_operand 0 "" "")))]
9498 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9499 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9500 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9501 "
9502 {
9503 #if TARGET_MACHO
9504 if (DEFAULT_ABI == ABI_DARWIN)
9505 {
9506 const char *picbase = machopic_function_base_name ();
9507 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9508 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9509 rtx tmplabrtx;
9510 char tmplab[20];
9512 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9513 CODE_LABEL_NUMBER (operands[0]));
9514 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9516 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9517 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9518 }
9519 else
9520 #endif
9521 rs6000_emit_load_toc_table (FALSE);
9522 DONE;
9523 }")
9525 ;; Elf specific ways of loading addresses for non-PIC code.
9526 ;; The output of this could be r0, but we make a very strong
9527 ;; preference for a base register because it will usually
9528 ;; be needed there.
9529 (define_insn "elf_high"
9530 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9531 (high:SI (match_operand 1 "" "")))]
9532 "TARGET_ELF && ! TARGET_64BIT"
9533 "{liu|lis} %0,%1@ha")
9535 (define_insn "elf_low"
9536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9537 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9538 (match_operand 2 "" "")))]
9539 "TARGET_ELF && ! TARGET_64BIT"
9540 "@
9541 {cal|la} %0,%2@l(%1)
9542 {ai|addic} %0,%1,%K2")
9543 \f
9544 ;; A function pointer under AIX is a pointer to a data area whose first word
9545 ;; contains the actual address of the function, whose second word contains a
9546 ;; pointer to its TOC, and whose third word contains a value to place in the
9547 ;; static chain register (r11). Note that if we load the static chain, our
9548 ;; "trampoline" need not have any executable code.
9550 (define_expand "call_indirect_aix32"
9551 [(set (match_dup 2)
9552 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9553 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9554 (reg:SI 2))
9555 (set (reg:SI 2)
9556 (mem:SI (plus:SI (match_dup 0)
9557 (const_int 4))))
9558 (set (reg:SI 11)
9559 (mem:SI (plus:SI (match_dup 0)
9560 (const_int 8))))
9561 (parallel [(call (mem:SI (match_dup 2))
9562 (match_operand 1 "" ""))
9563 (use (reg:SI 2))
9564 (use (reg:SI 11))
9565 (set (reg:SI 2)
9566 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9567 (clobber (scratch:SI))])]
9568 "TARGET_32BIT"
9569 "
9570 { operands[2] = gen_reg_rtx (SImode); }")
9572 (define_expand "call_indirect_aix64"
9573 [(set (match_dup 2)
9574 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9575 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9576 (reg:DI 2))
9577 (set (reg:DI 2)
9578 (mem:DI (plus:DI (match_dup 0)
9579 (const_int 8))))
9580 (set (reg:DI 11)
9581 (mem:DI (plus:DI (match_dup 0)
9582 (const_int 16))))
9583 (parallel [(call (mem:SI (match_dup 2))
9584 (match_operand 1 "" ""))
9585 (use (reg:DI 2))
9586 (use (reg:DI 11))
9587 (set (reg:DI 2)
9588 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9589 (clobber (scratch:SI))])]
9590 "TARGET_64BIT"
9591 "
9592 { operands[2] = gen_reg_rtx (DImode); }")
9594 (define_expand "call_value_indirect_aix32"
9595 [(set (match_dup 3)
9596 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9597 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9598 (reg:SI 2))
9599 (set (reg:SI 2)
9600 (mem:SI (plus:SI (match_dup 1)
9601 (const_int 4))))
9602 (set (reg:SI 11)
9603 (mem:SI (plus:SI (match_dup 1)
9604 (const_int 8))))
9605 (parallel [(set (match_operand 0 "" "")
9606 (call (mem:SI (match_dup 3))
9607 (match_operand 2 "" "")))
9608 (use (reg:SI 2))
9609 (use (reg:SI 11))
9610 (set (reg:SI 2)
9611 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9612 (clobber (scratch:SI))])]
9613 "TARGET_32BIT"
9614 "
9615 { operands[3] = gen_reg_rtx (SImode); }")
9617 (define_expand "call_value_indirect_aix64"
9618 [(set (match_dup 3)
9619 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9620 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9621 (reg:DI 2))
9622 (set (reg:DI 2)
9623 (mem:DI (plus:DI (match_dup 1)
9624 (const_int 8))))
9625 (set (reg:DI 11)
9626 (mem:DI (plus:DI (match_dup 1)
9627 (const_int 16))))
9628 (parallel [(set (match_operand 0 "" "")
9629 (call (mem:SI (match_dup 3))
9630 (match_operand 2 "" "")))
9631 (use (reg:DI 2))
9632 (use (reg:DI 11))
9633 (set (reg:DI 2)
9634 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9635 (clobber (scratch:SI))])]
9636 "TARGET_64BIT"
9637 "
9638 { operands[3] = gen_reg_rtx (DImode); }")
9640 ;; Now the definitions for the call and call_value insns
9641 (define_expand "call"
9642 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9643 (match_operand 1 "" ""))
9644 (use (match_operand 2 "" ""))
9645 (clobber (scratch:SI))])]
9646 ""
9647 "
9648 {
9649 #if TARGET_MACHO
9650 if (MACHOPIC_INDIRECT)
9651 operands[0] = machopic_indirect_call_target (operands[0]);
9652 #endif
9654 gcc_assert (GET_CODE (operands[0]) == MEM);
9655 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
9657 operands[0] = XEXP (operands[0], 0);
9659 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9660 && flag_pic
9661 && GET_CODE (operands[0]) == SYMBOL_REF
9662 && !SYMBOL_REF_LOCAL_P (operands[0]))
9663 {
9664 rtx call;
9665 rtvec tmp;
9667 tmp = gen_rtvec (3,
9668 gen_rtx_CALL (VOIDmode,
9669 gen_rtx_MEM (SImode, operands[0]),
9670 operands[1]),
9671 gen_rtx_USE (VOIDmode, operands[2]),
9672 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9673 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9674 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9675 DONE;
9676 }
9678 if (GET_CODE (operands[0]) != SYMBOL_REF
9679 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
9680 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
9681 {
9682 if (INTVAL (operands[2]) & CALL_LONG)
9683 operands[0] = rs6000_longcall_ref (operands[0]);
9685 switch (DEFAULT_ABI)
9686 {
9687 case ABI_V4:
9688 case ABI_DARWIN:
9689 operands[0] = force_reg (Pmode, operands[0]);
9690 break;
9692 case ABI_AIX:
9693 /* AIX function pointers are really pointers to a three word
9694 area. */
9695 emit_call_insn (TARGET_32BIT
9696 ? gen_call_indirect_aix32 (force_reg (SImode,
9697 operands[0]),
9698 operands[1])
9699 : gen_call_indirect_aix64 (force_reg (DImode,
9700 operands[0]),
9701 operands[1]));
9702 DONE;
9704 default:
9705 gcc_unreachable ();
9706 }
9707 }
9708 }")
9710 (define_expand "call_value"
9711 [(parallel [(set (match_operand 0 "" "")
9712 (call (mem:SI (match_operand 1 "address_operand" ""))
9713 (match_operand 2 "" "")))
9714 (use (match_operand 3 "" ""))
9715 (clobber (scratch:SI))])]
9716 ""
9717 "
9718 {
9719 #if TARGET_MACHO
9720 if (MACHOPIC_INDIRECT)
9721 operands[1] = machopic_indirect_call_target (operands[1]);
9722 #endif
9724 gcc_assert (GET_CODE (operands[1]) == MEM);
9725 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
9727 operands[1] = XEXP (operands[1], 0);
9729 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9730 && flag_pic
9731 && GET_CODE (operands[1]) == SYMBOL_REF
9732 && !SYMBOL_REF_LOCAL_P (operands[1]))
9733 {
9734 rtx call;
9735 rtvec tmp;
9737 tmp = gen_rtvec (3,
9738 gen_rtx_SET (VOIDmode,
9739 operands[0],
9740 gen_rtx_CALL (VOIDmode,
9741 gen_rtx_MEM (SImode,
9742 operands[1]),
9743 operands[2])),
9744 gen_rtx_USE (VOIDmode, operands[3]),
9745 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9746 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9747 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9748 DONE;
9749 }
9751 if (GET_CODE (operands[1]) != SYMBOL_REF
9752 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
9753 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
9754 {
9755 if (INTVAL (operands[3]) & CALL_LONG)
9756 operands[1] = rs6000_longcall_ref (operands[1]);
9758 switch (DEFAULT_ABI)
9759 {
9760 case ABI_V4:
9761 case ABI_DARWIN:
9762 operands[1] = force_reg (Pmode, operands[1]);
9763 break;
9765 case ABI_AIX:
9766 /* AIX function pointers are really pointers to a three word
9767 area. */
9768 emit_call_insn (TARGET_32BIT
9769 ? gen_call_value_indirect_aix32 (operands[0],
9770 force_reg (SImode,
9771 operands[1]),
9772 operands[2])
9773 : gen_call_value_indirect_aix64 (operands[0],
9774 force_reg (DImode,
9775 operands[1]),
9776 operands[2]));
9777 DONE;
9779 default:
9780 gcc_unreachable ();
9781 }
9782 }
9783 }")
9785 ;; Call to function in current module. No TOC pointer reload needed.
9786 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9787 ;; either the function was not prototyped, or it was prototyped as a
9788 ;; variable argument function. It is > 0 if FP registers were passed
9789 ;; and < 0 if they were not.
9791 (define_insn "*call_local32"
9792 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9793 (match_operand 1 "" "g,g"))
9794 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9795 (clobber (match_scratch:SI 3 "=l,l"))]
9796 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9797 "*
9798 {
9799 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9800 output_asm_insn (\"crxor 6,6,6\", operands);
9802 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9803 output_asm_insn (\"creqv 6,6,6\", operands);
9805 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9806 }"
9807 [(set_attr "type" "branch")
9808 (set_attr "length" "4,8")])
9810 (define_insn "*call_local64"
9811 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9812 (match_operand 1 "" "g,g"))
9813 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9814 (clobber (match_scratch:SI 3 "=l,l"))]
9815 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9816 "*
9817 {
9818 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9819 output_asm_insn (\"crxor 6,6,6\", operands);
9821 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9822 output_asm_insn (\"creqv 6,6,6\", operands);
9824 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9825 }"
9826 [(set_attr "type" "branch")
9827 (set_attr "length" "4,8")])
9829 (define_insn "*call_value_local32"
9830 [(set (match_operand 0 "" "")
9831 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9832 (match_operand 2 "" "g,g")))
9833 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9834 (clobber (match_scratch:SI 4 "=l,l"))]
9835 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9836 "*
9837 {
9838 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9839 output_asm_insn (\"crxor 6,6,6\", operands);
9841 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9842 output_asm_insn (\"creqv 6,6,6\", operands);
9844 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9845 }"
9846 [(set_attr "type" "branch")
9847 (set_attr "length" "4,8")])
9850 (define_insn "*call_value_local64"
9851 [(set (match_operand 0 "" "")
9852 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9853 (match_operand 2 "" "g,g")))
9854 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9855 (clobber (match_scratch:SI 4 "=l,l"))]
9856 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9857 "*
9858 {
9859 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9860 output_asm_insn (\"crxor 6,6,6\", operands);
9862 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9863 output_asm_insn (\"creqv 6,6,6\", operands);
9865 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9866 }"
9867 [(set_attr "type" "branch")
9868 (set_attr "length" "4,8")])
9870 ;; Call to function which may be in another module. Restore the TOC
9871 ;; pointer (r2) after the call unless this is System V.
9872 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9873 ;; either the function was not prototyped, or it was prototyped as a
9874 ;; variable argument function. It is > 0 if FP registers were passed
9875 ;; and < 0 if they were not.
9877 (define_insn "*call_indirect_nonlocal_aix32"
9878 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
9879 (match_operand 1 "" "g,g"))
9880 (use (reg:SI 2))
9881 (use (reg:SI 11))
9882 (set (reg:SI 2)
9883 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9884 (clobber (match_scratch:SI 2 "=l,l"))]
9885 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9886 "b%T0l\;{l|lwz} 2,20(1)"
9887 [(set_attr "type" "jmpreg")
9888 (set_attr "length" "8")])
9890 (define_insn "*call_nonlocal_aix32"
9891 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
9892 (match_operand 1 "" "g"))
9893 (use (match_operand:SI 2 "immediate_operand" "O"))
9894 (clobber (match_scratch:SI 3 "=l"))]
9895 "TARGET_32BIT
9896 && DEFAULT_ABI == ABI_AIX
9897 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9898 "bl %z0\;%."
9899 [(set_attr "type" "branch")
9900 (set_attr "length" "8")])
9902 (define_insn "*call_indirect_nonlocal_aix64"
9903 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
9904 (match_operand 1 "" "g,g"))
9905 (use (reg:DI 2))
9906 (use (reg:DI 11))
9907 (set (reg:DI 2)
9908 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9909 (clobber (match_scratch:SI 2 "=l,l"))]
9910 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9911 "b%T0l\;ld 2,40(1)"
9912 [(set_attr "type" "jmpreg")
9913 (set_attr "length" "8")])
9915 (define_insn "*call_nonlocal_aix64"
9916 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
9917 (match_operand 1 "" "g"))
9918 (use (match_operand:SI 2 "immediate_operand" "O"))
9919 (clobber (match_scratch:SI 3 "=l"))]
9920 "TARGET_64BIT
9921 && DEFAULT_ABI == ABI_AIX
9922 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9923 "bl %z0\;%."
9924 [(set_attr "type" "branch")
9925 (set_attr "length" "8")])
9927 (define_insn "*call_value_indirect_nonlocal_aix32"
9928 [(set (match_operand 0 "" "")
9929 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
9930 (match_operand 2 "" "g,g")))
9931 (use (reg:SI 2))
9932 (use (reg:SI 11))
9933 (set (reg:SI 2)
9934 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9935 (clobber (match_scratch:SI 3 "=l,l"))]
9936 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9937 "b%T1l\;{l|lwz} 2,20(1)"
9938 [(set_attr "type" "jmpreg")
9939 (set_attr "length" "8")])
9941 (define_insn "*call_value_nonlocal_aix32"
9942 [(set (match_operand 0 "" "")
9943 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
9944 (match_operand 2 "" "g")))
9945 (use (match_operand:SI 3 "immediate_operand" "O"))
9946 (clobber (match_scratch:SI 4 "=l"))]
9947 "TARGET_32BIT
9948 && DEFAULT_ABI == ABI_AIX
9949 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9950 "bl %z1\;%."
9951 [(set_attr "type" "branch")
9952 (set_attr "length" "8")])
9954 (define_insn "*call_value_indirect_nonlocal_aix64"
9955 [(set (match_operand 0 "" "")
9956 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
9957 (match_operand 2 "" "g,g")))
9958 (use (reg:DI 2))
9959 (use (reg:DI 11))
9960 (set (reg:DI 2)
9961 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9962 (clobber (match_scratch:SI 3 "=l,l"))]
9963 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9964 "b%T1l\;ld 2,40(1)"
9965 [(set_attr "type" "jmpreg")
9966 (set_attr "length" "8")])
9968 (define_insn "*call_value_nonlocal_aix64"
9969 [(set (match_operand 0 "" "")
9970 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
9971 (match_operand 2 "" "g")))
9972 (use (match_operand:SI 3 "immediate_operand" "O"))
9973 (clobber (match_scratch:SI 4 "=l"))]
9974 "TARGET_64BIT
9975 && DEFAULT_ABI == ABI_AIX
9976 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9977 "bl %z1\;%."
9978 [(set_attr "type" "branch")
9979 (set_attr "length" "8")])
9981 ;; A function pointer under System V is just a normal pointer
9982 ;; operands[0] is the function pointer
9983 ;; operands[1] is the stack size to clean up
9984 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
9985 ;; which indicates how to set cr1
9987 (define_insn "*call_indirect_nonlocal_sysv"
9988 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
9989 (match_operand 1 "" "g,g,g,g"))
9990 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
9991 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
9992 "DEFAULT_ABI == ABI_V4
9993 || DEFAULT_ABI == ABI_DARWIN"
9994 {
9995 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9996 output_asm_insn ("crxor 6,6,6", operands);
9998 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9999 output_asm_insn ("creqv 6,6,6", operands);
10001 return "b%T0l";
10002 }
10003 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10004 (set_attr "length" "4,4,8,8")])
10006 (define_insn "*call_nonlocal_sysv"
10007 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10008 (match_operand 1 "" "g,g"))
10009 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10010 (clobber (match_scratch:SI 3 "=l,l"))]
10011 "(DEFAULT_ABI == ABI_DARWIN
10012 || (DEFAULT_ABI == ABI_V4
10013 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10014 {
10015 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10016 output_asm_insn ("crxor 6,6,6", operands);
10018 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10019 output_asm_insn ("creqv 6,6,6", operands);
10021 #if TARGET_MACHO
10022 return output_call(insn, operands, 0, 2);
10023 #else
10024 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10025 {
10026 if (TARGET_SECURE_PLT && flag_pic == 2)
10027 /* The magic 32768 offset here and in the other sysv call insns
10028 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10029 See sysv4.h:toc_section. */
10030 return "bl %z0+32768@plt";
10031 else
10032 return "bl %z0@plt";
10033 }
10034 else
10035 return "bl %z0";
10036 #endif
10037 }
10038 [(set_attr "type" "branch,branch")
10039 (set_attr "length" "4,8")])
10041 (define_insn "*call_value_indirect_nonlocal_sysv"
10042 [(set (match_operand 0 "" "")
10043 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10044 (match_operand 2 "" "g,g,g,g")))
10045 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10046 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10047 "DEFAULT_ABI == ABI_V4
10048 || DEFAULT_ABI == ABI_DARWIN"
10049 {
10050 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10051 output_asm_insn ("crxor 6,6,6", operands);
10053 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10054 output_asm_insn ("creqv 6,6,6", operands);
10056 return "b%T1l";
10057 }
10058 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10059 (set_attr "length" "4,4,8,8")])
10061 (define_insn "*call_value_nonlocal_sysv"
10062 [(set (match_operand 0 "" "")
10063 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10064 (match_operand 2 "" "g,g")))
10065 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10066 (clobber (match_scratch:SI 4 "=l,l"))]
10067 "(DEFAULT_ABI == ABI_DARWIN
10068 || (DEFAULT_ABI == ABI_V4
10069 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10070 {
10071 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10072 output_asm_insn ("crxor 6,6,6", operands);
10074 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10075 output_asm_insn ("creqv 6,6,6", operands);
10077 #if TARGET_MACHO
10078 return output_call(insn, operands, 1, 3);
10079 #else
10080 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10081 {
10082 if (TARGET_SECURE_PLT && flag_pic == 2)
10083 return "bl %z1+32768@plt";
10084 else
10085 return "bl %z1@plt";
10086 }
10087 else
10088 return "bl %z1";
10089 #endif
10090 }
10091 [(set_attr "type" "branch,branch")
10092 (set_attr "length" "4,8")])
10094 ;; Call subroutine returning any type.
10095 (define_expand "untyped_call"
10096 [(parallel [(call (match_operand 0 "" "")
10097 (const_int 0))
10098 (match_operand 1 "" "")
10099 (match_operand 2 "" "")])]
10100 ""
10101 "
10102 {
10103 int i;
10105 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10107 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10108 {
10109 rtx set = XVECEXP (operands[2], 0, i);
10110 emit_move_insn (SET_DEST (set), SET_SRC (set));
10111 }
10113 /* The optimizer does not know that the call sets the function value
10114 registers we stored in the result block. We avoid problems by
10115 claiming that all hard registers are used and clobbered at this
10116 point. */
10117 emit_insn (gen_blockage ());
10119 DONE;
10120 }")
10122 ;; sibling call patterns
10123 (define_expand "sibcall"
10124 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10125 (match_operand 1 "" ""))
10126 (use (match_operand 2 "" ""))
10127 (use (match_operand 3 "" ""))
10128 (return)])]
10129 ""
10130 "
10131 {
10132 #if TARGET_MACHO
10133 if (MACHOPIC_INDIRECT)
10134 operands[0] = machopic_indirect_call_target (operands[0]);
10135 #endif
10137 gcc_assert (GET_CODE (operands[0]) == MEM);
10138 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10140 operands[0] = XEXP (operands[0], 0);
10141 operands[3] = gen_reg_rtx (SImode);
10143 }")
10145 ;; this and similar patterns must be marked as using LR, otherwise
10146 ;; dataflow will try to delete the store into it. This is true
10147 ;; even when the actual reg to jump to is in CTR, when LR was
10148 ;; saved and restored around the PIC-setting BCL.
10149 (define_insn "*sibcall_local32"
10150 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10151 (match_operand 1 "" "g,g"))
10152 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10153 (use (match_operand:SI 3 "register_operand" "l,l"))
10154 (return)]
10155 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10156 "*
10157 {
10158 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10159 output_asm_insn (\"crxor 6,6,6\", operands);
10161 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10162 output_asm_insn (\"creqv 6,6,6\", operands);
10164 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10165 }"
10166 [(set_attr "type" "branch")
10167 (set_attr "length" "4,8")])
10169 (define_insn "*sibcall_local64"
10170 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10171 (match_operand 1 "" "g,g"))
10172 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10173 (use (match_operand:SI 3 "register_operand" "l,l"))
10174 (return)]
10175 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10176 "*
10177 {
10178 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10179 output_asm_insn (\"crxor 6,6,6\", operands);
10181 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10182 output_asm_insn (\"creqv 6,6,6\", operands);
10184 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10185 }"
10186 [(set_attr "type" "branch")
10187 (set_attr "length" "4,8")])
10189 (define_insn "*sibcall_value_local32"
10190 [(set (match_operand 0 "" "")
10191 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10192 (match_operand 2 "" "g,g")))
10193 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10194 (use (match_operand:SI 4 "register_operand" "l,l"))
10195 (return)]
10196 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10197 "*
10198 {
10199 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10200 output_asm_insn (\"crxor 6,6,6\", operands);
10202 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10203 output_asm_insn (\"creqv 6,6,6\", operands);
10205 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10206 }"
10207 [(set_attr "type" "branch")
10208 (set_attr "length" "4,8")])
10211 (define_insn "*sibcall_value_local64"
10212 [(set (match_operand 0 "" "")
10213 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10214 (match_operand 2 "" "g,g")))
10215 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10216 (use (match_operand:SI 4 "register_operand" "l,l"))
10217 (return)]
10218 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10219 "*
10220 {
10221 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10222 output_asm_insn (\"crxor 6,6,6\", operands);
10224 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10225 output_asm_insn (\"creqv 6,6,6\", operands);
10227 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10228 }"
10229 [(set_attr "type" "branch")
10230 (set_attr "length" "4,8")])
10232 (define_insn "*sibcall_nonlocal_aix32"
10233 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10234 (match_operand 1 "" "g"))
10235 (use (match_operand:SI 2 "immediate_operand" "O"))
10236 (use (match_operand:SI 3 "register_operand" "l"))
10237 (return)]
10238 "TARGET_32BIT
10239 && DEFAULT_ABI == ABI_AIX
10240 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10241 "b %z0"
10242 [(set_attr "type" "branch")
10243 (set_attr "length" "4")])
10245 (define_insn "*sibcall_nonlocal_aix64"
10246 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10247 (match_operand 1 "" "g"))
10248 (use (match_operand:SI 2 "immediate_operand" "O"))
10249 (use (match_operand:SI 3 "register_operand" "l"))
10250 (return)]
10251 "TARGET_64BIT
10252 && DEFAULT_ABI == ABI_AIX
10253 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10254 "b %z0"
10255 [(set_attr "type" "branch")
10256 (set_attr "length" "4")])
10258 (define_insn "*sibcall_value_nonlocal_aix32"
10259 [(set (match_operand 0 "" "")
10260 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10261 (match_operand 2 "" "g")))
10262 (use (match_operand:SI 3 "immediate_operand" "O"))
10263 (use (match_operand:SI 4 "register_operand" "l"))
10264 (return)]
10265 "TARGET_32BIT
10266 && DEFAULT_ABI == ABI_AIX
10267 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10268 "b %z1"
10269 [(set_attr "type" "branch")
10270 (set_attr "length" "4")])
10272 (define_insn "*sibcall_value_nonlocal_aix64"
10273 [(set (match_operand 0 "" "")
10274 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10275 (match_operand 2 "" "g")))
10276 (use (match_operand:SI 3 "immediate_operand" "O"))
10277 (use (match_operand:SI 4 "register_operand" "l"))
10278 (return)]
10279 "TARGET_64BIT
10280 && DEFAULT_ABI == ABI_AIX
10281 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10282 "b %z1"
10283 [(set_attr "type" "branch")
10284 (set_attr "length" "4")])
10286 (define_insn "*sibcall_nonlocal_sysv"
10287 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10288 (match_operand 1 "" ""))
10289 (use (match_operand 2 "immediate_operand" "O,n"))
10290 (use (match_operand:SI 3 "register_operand" "l,l"))
10291 (return)]
10292 "(DEFAULT_ABI == ABI_DARWIN
10293 || DEFAULT_ABI == ABI_V4)
10294 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10295 "*
10296 {
10297 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10298 output_asm_insn (\"crxor 6,6,6\", operands);
10300 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10301 output_asm_insn (\"creqv 6,6,6\", operands);
10303 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10304 {
10305 if (TARGET_SECURE_PLT && flag_pic == 2)
10306 return \"b %z0+32768@plt\";
10307 else
10308 return \"b %z0@plt\";
10309 }
10310 else
10311 return \"b %z0\";
10312 }"
10313 [(set_attr "type" "branch,branch")
10314 (set_attr "length" "4,8")])
10316 (define_expand "sibcall_value"
10317 [(parallel [(set (match_operand 0 "register_operand" "")
10318 (call (mem:SI (match_operand 1 "address_operand" ""))
10319 (match_operand 2 "" "")))
10320 (use (match_operand 3 "" ""))
10321 (use (match_operand 4 "" ""))
10322 (return)])]
10323 ""
10324 "
10325 {
10326 #if TARGET_MACHO
10327 if (MACHOPIC_INDIRECT)
10328 operands[1] = machopic_indirect_call_target (operands[1]);
10329 #endif
10331 gcc_assert (GET_CODE (operands[1]) == MEM);
10332 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10334 operands[1] = XEXP (operands[1], 0);
10335 operands[4] = gen_reg_rtx (SImode);
10337 }")
10339 (define_insn "*sibcall_value_nonlocal_sysv"
10340 [(set (match_operand 0 "" "")
10341 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10342 (match_operand 2 "" "")))
10343 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10344 (use (match_operand:SI 4 "register_operand" "l,l"))
10345 (return)]
10346 "(DEFAULT_ABI == ABI_DARWIN
10347 || DEFAULT_ABI == ABI_V4)
10348 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10349 "*
10350 {
10351 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10352 output_asm_insn (\"crxor 6,6,6\", operands);
10354 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10355 output_asm_insn (\"creqv 6,6,6\", operands);
10357 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10358 {
10359 if (TARGET_SECURE_PLT && flag_pic == 2)
10360 return \"b %z1+32768@plt\";
10361 else
10362 return \"b %z1@plt\";
10363 }
10364 else
10365 return \"b %z1\";
10366 }"
10367 [(set_attr "type" "branch,branch")
10368 (set_attr "length" "4,8")])
10370 (define_expand "sibcall_epilogue"
10371 [(use (const_int 0))]
10372 "TARGET_SCHED_PROLOG"
10373 "
10374 {
10375 rs6000_emit_epilogue (TRUE);
10376 DONE;
10377 }")
10379 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10380 ;; all of memory. This blocks insns from being moved across this point.
10382 (define_insn "blockage"
10383 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10384 ""
10385 "")
10386 \f
10387 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10388 ;; signed & unsigned, and one type of branch.
10389 ;;
10390 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10391 ;; insns, and branches. We store the operands of compares until we see
10392 ;; how it is used.
10393 (define_expand "cmp<mode>"
10394 [(set (cc0)
10395 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
10396 (match_operand:GPR 1 "reg_or_short_operand" "")))]
10397 ""
10398 "
10399 {
10400 /* Take care of the possibility that operands[1] might be negative but
10401 this might be a logical operation. That insn doesn't exist. */
10402 if (GET_CODE (operands[1]) == CONST_INT
10403 && INTVAL (operands[1]) < 0)
10404 operands[1] = force_reg (<MODE>mode, operands[1]);
10406 rs6000_compare_op0 = operands[0];
10407 rs6000_compare_op1 = operands[1];
10408 rs6000_compare_fp_p = 0;
10409 DONE;
10410 }")
10412 (define_expand "cmp<mode>"
10413 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
10414 (match_operand:FP 1 "gpc_reg_operand" "")))]
10415 ""
10416 "
10417 {
10418 rs6000_compare_op0 = operands[0];
10419 rs6000_compare_op1 = operands[1];
10420 rs6000_compare_fp_p = 1;
10421 DONE;
10422 }")
10424 (define_expand "beq"
10425 [(use (match_operand 0 "" ""))]
10426 ""
10427 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10429 (define_expand "bne"
10430 [(use (match_operand 0 "" ""))]
10431 ""
10432 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10434 (define_expand "bge"
10435 [(use (match_operand 0 "" ""))]
10436 ""
10437 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10439 (define_expand "bgt"
10440 [(use (match_operand 0 "" ""))]
10441 ""
10442 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10444 (define_expand "ble"
10445 [(use (match_operand 0 "" ""))]
10446 ""
10447 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10449 (define_expand "blt"
10450 [(use (match_operand 0 "" ""))]
10451 ""
10452 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10454 (define_expand "bgeu"
10455 [(use (match_operand 0 "" ""))]
10456 ""
10457 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10459 (define_expand "bgtu"
10460 [(use (match_operand 0 "" ""))]
10461 ""
10462 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10464 (define_expand "bleu"
10465 [(use (match_operand 0 "" ""))]
10466 ""
10467 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10469 (define_expand "bltu"
10470 [(use (match_operand 0 "" ""))]
10471 ""
10472 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10474 (define_expand "bunordered"
10475 [(use (match_operand 0 "" ""))]
10476 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10477 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10479 (define_expand "bordered"
10480 [(use (match_operand 0 "" ""))]
10481 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10482 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10484 (define_expand "buneq"
10485 [(use (match_operand 0 "" ""))]
10486 ""
10487 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10489 (define_expand "bunge"
10490 [(use (match_operand 0 "" ""))]
10491 ""
10492 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10494 (define_expand "bungt"
10495 [(use (match_operand 0 "" ""))]
10496 ""
10497 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10499 (define_expand "bunle"
10500 [(use (match_operand 0 "" ""))]
10501 ""
10502 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10504 (define_expand "bunlt"
10505 [(use (match_operand 0 "" ""))]
10506 ""
10507 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10509 (define_expand "bltgt"
10510 [(use (match_operand 0 "" ""))]
10511 ""
10512 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10514 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10515 ;; For SEQ, likewise, except that comparisons with zero should be done
10516 ;; with an scc insns. However, due to the order that combine see the
10517 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10518 ;; the cases we don't want to handle.
10519 (define_expand "seq"
10520 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10521 ""
10522 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10524 (define_expand "sne"
10525 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10526 ""
10527 "
10528 {
10529 if (! rs6000_compare_fp_p)
10530 FAIL;
10532 rs6000_emit_sCOND (NE, operands[0]);
10533 DONE;
10534 }")
10536 ;; A >= 0 is best done the portable way for A an integer.
10537 (define_expand "sge"
10538 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10539 ""
10540 "
10541 {
10542 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10543 FAIL;
10545 rs6000_emit_sCOND (GE, operands[0]);
10546 DONE;
10547 }")
10549 ;; A > 0 is best done using the portable sequence, so fail in that case.
10550 (define_expand "sgt"
10551 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10552 ""
10553 "
10554 {
10555 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10556 FAIL;
10558 rs6000_emit_sCOND (GT, operands[0]);
10559 DONE;
10560 }")
10562 ;; A <= 0 is best done the portable way for A an integer.
10563 (define_expand "sle"
10564 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10565 ""
10566 "
10567 {
10568 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10569 FAIL;
10571 rs6000_emit_sCOND (LE, operands[0]);
10572 DONE;
10573 }")
10575 ;; A < 0 is best done in the portable way for A an integer.
10576 (define_expand "slt"
10577 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10578 ""
10579 "
10580 {
10581 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10582 FAIL;
10584 rs6000_emit_sCOND (LT, operands[0]);
10585 DONE;
10586 }")
10588 (define_expand "sgeu"
10589 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10590 ""
10591 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10593 (define_expand "sgtu"
10594 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10595 ""
10596 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10598 (define_expand "sleu"
10599 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10600 ""
10601 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10603 (define_expand "sltu"
10604 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10605 ""
10606 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10608 (define_expand "sunordered"
10609 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10610 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10611 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
10613 (define_expand "sordered"
10614 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10615 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10616 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
10618 (define_expand "suneq"
10619 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10620 ""
10621 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
10623 (define_expand "sunge"
10624 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10625 ""
10626 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
10628 (define_expand "sungt"
10629 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10630 ""
10631 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
10633 (define_expand "sunle"
10634 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10635 ""
10636 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
10638 (define_expand "sunlt"
10639 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10640 ""
10641 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
10643 (define_expand "sltgt"
10644 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10645 ""
10646 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
10648 (define_expand "stack_protect_set"
10649 [(match_operand 0 "memory_operand" "")
10650 (match_operand 1 "memory_operand" "")]
10651 ""
10652 {
10653 #ifdef TARGET_THREAD_SSP_OFFSET
10654 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10655 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10656 operands[1] = gen_rtx_MEM (Pmode, addr);
10657 #endif
10658 if (TARGET_64BIT)
10659 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10660 else
10661 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10662 DONE;
10663 })
10665 (define_insn "stack_protect_setsi"
10666 [(set (match_operand:SI 0 "memory_operand" "=m")
10667 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10668 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10669 "TARGET_32BIT"
10670 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
10671 [(set_attr "type" "three")
10672 (set_attr "length" "12")])
10674 (define_insn "stack_protect_setdi"
10675 [(set (match_operand:DI 0 "memory_operand" "=m")
10676 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10677 (set (match_scratch:DI 2 "=&r") (const_int 0))]
10678 "TARGET_64BIT"
10679 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
10680 [(set_attr "type" "three")
10681 (set_attr "length" "12")])
10683 (define_expand "stack_protect_test"
10684 [(match_operand 0 "memory_operand" "")
10685 (match_operand 1 "memory_operand" "")
10686 (match_operand 2 "" "")]
10687 ""
10688 {
10689 #ifdef TARGET_THREAD_SSP_OFFSET
10690 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10691 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10692 operands[1] = gen_rtx_MEM (Pmode, addr);
10693 #endif
10694 rs6000_compare_op0 = operands[0];
10695 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
10696 UNSPEC_SP_TEST);
10697 rs6000_compare_fp_p = 0;
10698 emit_jump_insn (gen_beq (operands[2]));
10699 DONE;
10700 })
10702 (define_insn "stack_protect_testsi"
10703 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10704 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
10705 (match_operand:SI 2 "memory_operand" "m,m")]
10706 UNSPEC_SP_TEST))
10707 (set (match_scratch:SI 4 "=r,r") (const_int 0))
10708 (clobber (match_scratch:SI 3 "=&r,&r"))]
10709 "TARGET_32BIT"
10710 "@
10711 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10712 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10713 [(set_attr "length" "16,20")])
10715 (define_insn "stack_protect_testdi"
10716 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10717 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
10718 (match_operand:DI 2 "memory_operand" "m,m")]
10719 UNSPEC_SP_TEST))
10720 (set (match_scratch:DI 4 "=r,r") (const_int 0))
10721 (clobber (match_scratch:DI 3 "=&r,&r"))]
10722 "TARGET_64BIT"
10723 "@
10724 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10725 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10726 [(set_attr "length" "16,20")])
10728 \f
10729 ;; Here are the actual compare insns.
10730 (define_insn "*cmp<mode>_internal1"
10731 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10732 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
10733 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
10734 ""
10735 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
10736 [(set_attr "type" "cmp")])
10738 ;; If we are comparing a register for equality with a large constant,
10739 ;; we can do this with an XOR followed by a compare. But this is profitable
10740 ;; only if the large constant is only used for the comparison (and in this
10741 ;; case we already have a register to reuse as scratch).
10742 ;;
10743 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
10744 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
10746 (define_peephole2
10747 [(set (match_operand:SI 0 "register_operand")
10748 (match_operand:SI 1 "logical_operand" ""))
10749 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
10750 [(match_dup 0)
10751 (match_operand:SI 2 "logical_operand" "")]))
10752 (set (match_operand:CC 4 "cc_reg_operand" "")
10753 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
10754 (match_dup 0)))
10755 (set (pc)
10756 (if_then_else (match_operator 6 "equality_operator"
10757 [(match_dup 4) (const_int 0)])
10758 (match_operand 7 "" "")
10759 (match_operand 8 "" "")))]
10760 "peep2_reg_dead_p (3, operands[0])
10761 && peep2_reg_dead_p (4, operands[4])"
10762 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
10763 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
10764 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
10766 {
10767 /* Get the constant we are comparing against, and see what it looks like
10768 when sign-extended from 16 to 32 bits. Then see what constant we could
10769 XOR with SEXTC to get the sign-extended value. */
10770 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
10771 SImode,
10772 operands[1], operands[2]);
10773 HOST_WIDE_INT c = INTVAL (cnst);
10774 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10775 HOST_WIDE_INT xorv = c ^ sextc;
10777 operands[9] = GEN_INT (xorv);
10778 operands[10] = GEN_INT (sextc);
10779 })
10781 (define_insn "*cmpsi_internal2"
10782 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10783 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10784 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10785 ""
10786 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10787 [(set_attr "type" "cmp")])
10789 (define_insn "*cmpdi_internal2"
10790 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10791 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10792 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10793 ""
10794 "cmpld%I2 %0,%1,%b2"
10795 [(set_attr "type" "cmp")])
10797 ;; The following two insns don't exist as single insns, but if we provide
10798 ;; them, we can swap an add and compare, which will enable us to overlap more
10799 ;; of the required delay between a compare and branch. We generate code for
10800 ;; them by splitting.
10802 (define_insn ""
10803 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10804 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10805 (match_operand:SI 2 "short_cint_operand" "i")))
10806 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10807 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10808 ""
10809 "#"
10810 [(set_attr "length" "8")])
10812 (define_insn ""
10813 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10814 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10815 (match_operand:SI 2 "u_short_cint_operand" "i")))
10816 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10817 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10818 ""
10819 "#"
10820 [(set_attr "length" "8")])
10822 (define_split
10823 [(set (match_operand:CC 3 "cc_reg_operand" "")
10824 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10825 (match_operand:SI 2 "short_cint_operand" "")))
10826 (set (match_operand:SI 0 "gpc_reg_operand" "")
10827 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10828 ""
10829 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10830 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10832 (define_split
10833 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10834 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10835 (match_operand:SI 2 "u_short_cint_operand" "")))
10836 (set (match_operand:SI 0 "gpc_reg_operand" "")
10837 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10838 ""
10839 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10840 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10842 (define_insn "*cmpsf_internal1"
10843 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10844 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10845 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10846 "TARGET_HARD_FLOAT && TARGET_FPRS"
10847 "fcmpu %0,%1,%2"
10848 [(set_attr "type" "fpcompare")])
10850 (define_insn "*cmpdf_internal1"
10851 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10852 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10853 (match_operand:DF 2 "gpc_reg_operand" "f")))]
10854 "TARGET_HARD_FLOAT && TARGET_FPRS"
10855 "fcmpu %0,%1,%2"
10856 [(set_attr "type" "fpcompare")])
10858 ;; Only need to compare second words if first words equal
10859 (define_insn "*cmptf_internal1"
10860 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10861 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10862 (match_operand:TF 2 "gpc_reg_operand" "f")))]
10863 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
10864 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10865 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
10866 [(set_attr "type" "fpcompare")
10867 (set_attr "length" "12")])
10869 (define_insn_and_split "*cmptf_internal2"
10870 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10871 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10872 (match_operand:TF 2 "gpc_reg_operand" "f")))
10873 (clobber (match_scratch:DF 3 "=f"))
10874 (clobber (match_scratch:DF 4 "=f"))
10875 (clobber (match_scratch:DF 5 "=f"))
10876 (clobber (match_scratch:DF 6 "=f"))
10877 (clobber (match_scratch:DF 7 "=f"))
10878 (clobber (match_scratch:DF 8 "=f"))
10879 (clobber (match_scratch:DF 9 "=f"))
10880 (clobber (match_scratch:DF 10 "=f"))]
10881 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
10882 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10883 "#"
10884 "&& reload_completed"
10885 [(set (match_dup 3) (match_dup 13))
10886 (set (match_dup 4) (match_dup 14))
10887 (set (match_dup 9) (abs:DF (match_dup 5)))
10888 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
10889 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
10890 (label_ref (match_dup 11))
10891 (pc)))
10892 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
10893 (set (pc) (label_ref (match_dup 12)))
10894 (match_dup 11)
10895 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
10896 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
10897 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
10898 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
10899 (match_dup 12)]
10900 {
10901 REAL_VALUE_TYPE rv;
10902 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10903 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10905 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
10906 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
10907 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
10908 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
10909 operands[11] = gen_label_rtx ();
10910 operands[12] = gen_label_rtx ();
10911 real_inf (&rv);
10912 operands[13] = force_const_mem (DFmode,
10913 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
10914 operands[14] = force_const_mem (DFmode,
10915 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
10916 DFmode));
10917 if (TARGET_TOC)
10918 {
10919 operands[13] = gen_const_mem (DFmode,
10920 create_TOC_reference (XEXP (operands[13], 0)));
10921 operands[14] = gen_const_mem (DFmode,
10922 create_TOC_reference (XEXP (operands[14], 0)));
10923 set_mem_alias_set (operands[13], get_TOC_alias_set ());
10924 set_mem_alias_set (operands[14], get_TOC_alias_set ());
10925 }
10926 })
10927 \f
10928 ;; Now we have the scc insns. We can do some combinations because of the
10929 ;; way the machine works.
10930 ;;
10931 ;; Note that this is probably faster if we can put an insn between the
10932 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
10933 ;; cases the insns below which don't use an intermediate CR field will
10934 ;; be used instead.
10935 (define_insn ""
10936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10937 (match_operator:SI 1 "scc_comparison_operator"
10938 [(match_operand 2 "cc_reg_operand" "y")
10939 (const_int 0)]))]
10940 ""
10941 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10942 [(set (attr "type")
10943 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10944 (const_string "mfcrf")
10945 ]
10946 (const_string "mfcr")))
10947 (set_attr "length" "8")])
10949 ;; Same as above, but get the GT bit.
10950 (define_insn "move_from_CR_gt_bit"
10951 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10952 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
10953 "TARGET_E500"
10954 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
10955 [(set_attr "type" "mfcr")
10956 (set_attr "length" "8")])
10958 ;; Same as above, but get the OV/ORDERED bit.
10959 (define_insn "move_from_CR_ov_bit"
10960 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10961 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
10962 "TARGET_ISEL"
10963 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
10964 [(set_attr "type" "mfcr")
10965 (set_attr "length" "8")])
10967 (define_insn ""
10968 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10969 (match_operator:DI 1 "scc_comparison_operator"
10970 [(match_operand 2 "cc_reg_operand" "y")
10971 (const_int 0)]))]
10972 "TARGET_POWERPC64"
10973 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10974 [(set (attr "type")
10975 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10976 (const_string "mfcrf")
10977 ]
10978 (const_string "mfcr")))
10979 (set_attr "length" "8")])
10981 (define_insn ""
10982 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10983 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10984 [(match_operand 2 "cc_reg_operand" "y,y")
10985 (const_int 0)])
10986 (const_int 0)))
10987 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10988 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10989 "TARGET_32BIT"
10990 "@
10991 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
10992 #"
10993 [(set_attr "type" "delayed_compare")
10994 (set_attr "length" "8,16")])
10996 (define_split
10997 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10998 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10999 [(match_operand 2 "cc_reg_operand" "")
11000 (const_int 0)])
11001 (const_int 0)))
11002 (set (match_operand:SI 3 "gpc_reg_operand" "")
11003 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11004 "TARGET_32BIT && reload_completed"
11005 [(set (match_dup 3)
11006 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11007 (set (match_dup 0)
11008 (compare:CC (match_dup 3)
11009 (const_int 0)))]
11010 "")
11012 (define_insn ""
11013 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11014 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11015 [(match_operand 2 "cc_reg_operand" "y")
11016 (const_int 0)])
11017 (match_operand:SI 3 "const_int_operand" "n")))]
11018 ""
11019 "*
11020 {
11021 int is_bit = ccr_bit (operands[1], 1);
11022 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11023 int count;
11025 if (is_bit >= put_bit)
11026 count = is_bit - put_bit;
11027 else
11028 count = 32 - (put_bit - is_bit);
11030 operands[4] = GEN_INT (count);
11031 operands[5] = GEN_INT (put_bit);
11033 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11034 }"
11035 [(set (attr "type")
11036 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11037 (const_string "mfcrf")
11038 ]
11039 (const_string "mfcr")))
11040 (set_attr "length" "8")])
11042 (define_insn ""
11043 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11044 (compare:CC
11045 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11046 [(match_operand 2 "cc_reg_operand" "y,y")
11047 (const_int 0)])
11048 (match_operand:SI 3 "const_int_operand" "n,n"))
11049 (const_int 0)))
11050 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11051 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11052 (match_dup 3)))]
11053 ""
11054 "*
11055 {
11056 int is_bit = ccr_bit (operands[1], 1);
11057 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11058 int count;
11060 /* Force split for non-cc0 compare. */
11061 if (which_alternative == 1)
11062 return \"#\";
11064 if (is_bit >= put_bit)
11065 count = is_bit - put_bit;
11066 else
11067 count = 32 - (put_bit - is_bit);
11069 operands[5] = GEN_INT (count);
11070 operands[6] = GEN_INT (put_bit);
11072 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11073 }"
11074 [(set_attr "type" "delayed_compare")
11075 (set_attr "length" "8,16")])
11077 (define_split
11078 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11079 (compare:CC
11080 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11081 [(match_operand 2 "cc_reg_operand" "")
11082 (const_int 0)])
11083 (match_operand:SI 3 "const_int_operand" ""))
11084 (const_int 0)))
11085 (set (match_operand:SI 4 "gpc_reg_operand" "")
11086 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11087 (match_dup 3)))]
11088 "reload_completed"
11089 [(set (match_dup 4)
11090 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11091 (match_dup 3)))
11092 (set (match_dup 0)
11093 (compare:CC (match_dup 4)
11094 (const_int 0)))]
11095 "")
11097 ;; There is a 3 cycle delay between consecutive mfcr instructions
11098 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11100 (define_peephole
11101 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11102 (match_operator:SI 1 "scc_comparison_operator"
11103 [(match_operand 2 "cc_reg_operand" "y")
11104 (const_int 0)]))
11105 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11106 (match_operator:SI 4 "scc_comparison_operator"
11107 [(match_operand 5 "cc_reg_operand" "y")
11108 (const_int 0)]))]
11109 "REGNO (operands[2]) != REGNO (operands[5])"
11110 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11111 [(set_attr "type" "mfcr")
11112 (set_attr "length" "12")])
11114 (define_peephole
11115 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11116 (match_operator:DI 1 "scc_comparison_operator"
11117 [(match_operand 2 "cc_reg_operand" "y")
11118 (const_int 0)]))
11119 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11120 (match_operator:DI 4 "scc_comparison_operator"
11121 [(match_operand 5 "cc_reg_operand" "y")
11122 (const_int 0)]))]
11123 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11124 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11125 [(set_attr "type" "mfcr")
11126 (set_attr "length" "12")])
11128 ;; There are some scc insns that can be done directly, without a compare.
11129 ;; These are faster because they don't involve the communications between
11130 ;; the FXU and branch units. In fact, we will be replacing all of the
11131 ;; integer scc insns here or in the portable methods in emit_store_flag.
11132 ;;
11133 ;; Also support (neg (scc ..)) since that construct is used to replace
11134 ;; branches, (plus (scc ..) ..) since that construct is common and
11135 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11136 ;; cases where it is no more expensive than (neg (scc ..)).
11138 ;; Have reload force a constant into a register for the simple insns that
11139 ;; otherwise won't accept constants. We do this because it is faster than
11140 ;; the cmp/mfcr sequence we would otherwise generate.
11142 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11143 (DI "rKJI")])
11145 (define_insn_and_split "*eq<mode>"
11146 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11147 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11148 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11149 ""
11150 "#"
11151 ""
11152 [(set (match_dup 0)
11153 (clz:GPR (match_dup 3)))
11154 (set (match_dup 0)
11155 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11156 {
11157 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11158 {
11159 /* Use output operand as intermediate. */
11160 operands[3] = operands[0];
11162 if (logical_operand (operands[2], <MODE>mode))
11163 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11164 gen_rtx_XOR (<MODE>mode,
11165 operands[1], operands[2])));
11166 else
11167 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11168 gen_rtx_PLUS (<MODE>mode, operands[1],
11169 negate_rtx (<MODE>mode,
11170 operands[2]))));
11171 }
11172 else
11173 operands[3] = operands[1];
11175 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11176 })
11178 (define_insn_and_split "*eq<mode>_compare"
11179 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11180 (compare:CC
11181 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11182 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11183 (const_int 0)))
11184 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11185 (eq:P (match_dup 1) (match_dup 2)))]
11186 "optimize_size"
11187 "#"
11188 "optimize_size"
11189 [(set (match_dup 0)
11190 (clz:P (match_dup 4)))
11191 (parallel [(set (match_dup 3)
11192 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11193 (const_int 0)))
11194 (set (match_dup 0)
11195 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11196 {
11197 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11198 {
11199 /* Use output operand as intermediate. */
11200 operands[4] = operands[0];
11202 if (logical_operand (operands[2], <MODE>mode))
11203 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11204 gen_rtx_XOR (<MODE>mode,
11205 operands[1], operands[2])));
11206 else
11207 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11208 gen_rtx_PLUS (<MODE>mode, operands[1],
11209 negate_rtx (<MODE>mode,
11210 operands[2]))));
11211 }
11212 else
11213 operands[4] = operands[1];
11215 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11216 })
11218 ;; We have insns of the form shown by the first define_insn below. If
11219 ;; there is something inside the comparison operation, we must split it.
11220 (define_split
11221 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11222 (plus:SI (match_operator 1 "comparison_operator"
11223 [(match_operand:SI 2 "" "")
11224 (match_operand:SI 3
11225 "reg_or_cint_operand" "")])
11226 (match_operand:SI 4 "gpc_reg_operand" "")))
11227 (clobber (match_operand:SI 5 "register_operand" ""))]
11228 "! gpc_reg_operand (operands[2], SImode)"
11229 [(set (match_dup 5) (match_dup 2))
11230 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11231 (match_dup 4)))])
11233 (define_insn "*plus_eqsi"
11234 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11235 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11236 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11237 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11238 "TARGET_32BIT && optimize_size"
11239 "@
11240 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11241 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11242 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11243 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11244 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11245 [(set_attr "type" "three,two,three,three,three")
11246 (set_attr "length" "12,8,12,12,12")])
11248 (define_insn "*compare_plus_eqsi"
11249 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11250 (compare:CC
11251 (plus:SI
11252 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11253 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11254 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11255 (const_int 0)))
11256 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11257 "TARGET_32BIT && optimize_size"
11258 "@
11259 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11260 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11261 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11262 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11263 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11264 #
11265 #
11266 #
11267 #
11268 #"
11269 [(set_attr "type" "compare")
11270 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11272 (define_split
11273 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11274 (compare:CC
11275 (plus:SI
11276 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11277 (match_operand:SI 2 "scc_eq_operand" ""))
11278 (match_operand:SI 3 "gpc_reg_operand" ""))
11279 (const_int 0)))
11280 (clobber (match_scratch:SI 4 ""))]
11281 "TARGET_32BIT && optimize_size && reload_completed"
11282 [(set (match_dup 4)
11283 (plus:SI (eq:SI (match_dup 1)
11284 (match_dup 2))
11285 (match_dup 3)))
11286 (set (match_dup 0)
11287 (compare:CC (match_dup 4)
11288 (const_int 0)))]
11289 "")
11291 (define_insn "*plus_eqsi_compare"
11292 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11293 (compare:CC
11294 (plus:SI
11295 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11296 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11297 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11298 (const_int 0)))
11299 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11300 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11301 "TARGET_32BIT && optimize_size"
11302 "@
11303 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11304 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11305 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11306 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11307 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11308 #
11309 #
11310 #
11311 #
11312 #"
11313 [(set_attr "type" "compare")
11314 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11316 (define_split
11317 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11318 (compare:CC
11319 (plus:SI
11320 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11321 (match_operand:SI 2 "scc_eq_operand" ""))
11322 (match_operand:SI 3 "gpc_reg_operand" ""))
11323 (const_int 0)))
11324 (set (match_operand:SI 0 "gpc_reg_operand" "")
11325 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11326 "TARGET_32BIT && optimize_size && reload_completed"
11327 [(set (match_dup 0)
11328 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11329 (set (match_dup 4)
11330 (compare:CC (match_dup 0)
11331 (const_int 0)))]
11332 "")
11334 (define_insn "*neg_eq0<mode>"
11335 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11336 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11337 (const_int 0))))]
11338 "optimize_size"
11339 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
11340 [(set_attr "type" "two")
11341 (set_attr "length" "8")])
11343 (define_insn_and_split "*neg_eq<mode>"
11344 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11345 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11346 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11347 "optimize_size"
11348 "#"
11349 "optimize_size"
11350 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11351 {
11352 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11353 {
11354 /* Use output operand as intermediate. */
11355 operands[3] = operands[0];
11357 if (logical_operand (operands[2], <MODE>mode))
11358 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11359 gen_rtx_XOR (<MODE>mode,
11360 operands[1], operands[2])));
11361 else
11362 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11363 gen_rtx_PLUS (<MODE>mode, operands[1],
11364 negate_rtx (<MODE>mode,
11365 operands[2]))));
11366 }
11367 else
11368 operands[3] = operands[1];
11369 })
11371 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11372 ;; since it nabs/sr is just as fast.
11373 (define_insn "*ne0si"
11374 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11375 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11376 (const_int 31)))
11377 (clobber (match_scratch:SI 2 "=&r"))]
11378 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11379 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11380 [(set_attr "type" "two")
11381 (set_attr "length" "8")])
11383 (define_insn "*ne0di"
11384 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11385 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11386 (const_int 63)))
11387 (clobber (match_scratch:DI 2 "=&r"))]
11388 "TARGET_64BIT"
11389 "addic %2,%1,-1\;subfe %0,%2,%1"
11390 [(set_attr "type" "two")
11391 (set_attr "length" "8")])
11393 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11394 (define_insn "*plus_ne0si"
11395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11396 (plus:SI (lshiftrt:SI
11397 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11398 (const_int 31))
11399 (match_operand:SI 2 "gpc_reg_operand" "r")))
11400 (clobber (match_scratch:SI 3 "=&r"))]
11401 "TARGET_32BIT"
11402 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11403 [(set_attr "type" "two")
11404 (set_attr "length" "8")])
11406 (define_insn "*plus_ne0di"
11407 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11408 (plus:DI (lshiftrt:DI
11409 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11410 (const_int 63))
11411 (match_operand:DI 2 "gpc_reg_operand" "r")))
11412 (clobber (match_scratch:DI 3 "=&r"))]
11413 "TARGET_64BIT"
11414 "addic %3,%1,-1\;addze %0,%2"
11415 [(set_attr "type" "two")
11416 (set_attr "length" "8")])
11418 (define_insn "*compare_plus_ne0si"
11419 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11420 (compare:CC
11421 (plus:SI (lshiftrt:SI
11422 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11423 (const_int 31))
11424 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11425 (const_int 0)))
11426 (clobber (match_scratch:SI 3 "=&r,&r"))
11427 (clobber (match_scratch:SI 4 "=X,&r"))]
11428 "TARGET_32BIT"
11429 "@
11430 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11431 #"
11432 [(set_attr "type" "compare")
11433 (set_attr "length" "8,12")])
11435 (define_split
11436 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11437 (compare:CC
11438 (plus:SI (lshiftrt:SI
11439 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11440 (const_int 31))
11441 (match_operand:SI 2 "gpc_reg_operand" ""))
11442 (const_int 0)))
11443 (clobber (match_scratch:SI 3 ""))
11444 (clobber (match_scratch:SI 4 ""))]
11445 "TARGET_32BIT && reload_completed"
11446 [(parallel [(set (match_dup 3)
11447 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11448 (const_int 31))
11449 (match_dup 2)))
11450 (clobber (match_dup 4))])
11451 (set (match_dup 0)
11452 (compare:CC (match_dup 3)
11453 (const_int 0)))]
11454 "")
11456 (define_insn "*compare_plus_ne0di"
11457 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11458 (compare:CC
11459 (plus:DI (lshiftrt:DI
11460 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11461 (const_int 63))
11462 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11463 (const_int 0)))
11464 (clobber (match_scratch:DI 3 "=&r,&r"))]
11465 "TARGET_64BIT"
11466 "@
11467 addic %3,%1,-1\;addze. %3,%2
11468 #"
11469 [(set_attr "type" "compare")
11470 (set_attr "length" "8,12")])
11472 (define_split
11473 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11474 (compare:CC
11475 (plus:DI (lshiftrt:DI
11476 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11477 (const_int 63))
11478 (match_operand:DI 2 "gpc_reg_operand" ""))
11479 (const_int 0)))
11480 (clobber (match_scratch:DI 3 ""))]
11481 "TARGET_64BIT && reload_completed"
11482 [(set (match_dup 3)
11483 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11484 (const_int 63))
11485 (match_dup 2)))
11486 (set (match_dup 0)
11487 (compare:CC (match_dup 3)
11488 (const_int 0)))]
11489 "")
11491 (define_insn "*plus_ne0si_compare"
11492 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11493 (compare:CC
11494 (plus:SI (lshiftrt:SI
11495 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11496 (const_int 31))
11497 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11498 (const_int 0)))
11499 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11500 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11501 (match_dup 2)))
11502 (clobber (match_scratch:SI 3 "=&r,&r"))]
11503 "TARGET_32BIT"
11504 "@
11505 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11506 #"
11507 [(set_attr "type" "compare")
11508 (set_attr "length" "8,12")])
11510 (define_split
11511 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11512 (compare:CC
11513 (plus:SI (lshiftrt:SI
11514 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11515 (const_int 31))
11516 (match_operand:SI 2 "gpc_reg_operand" ""))
11517 (const_int 0)))
11518 (set (match_operand:SI 0 "gpc_reg_operand" "")
11519 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11520 (match_dup 2)))
11521 (clobber (match_scratch:SI 3 ""))]
11522 "TARGET_32BIT && reload_completed"
11523 [(parallel [(set (match_dup 0)
11524 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11525 (match_dup 2)))
11526 (clobber (match_dup 3))])
11527 (set (match_dup 4)
11528 (compare:CC (match_dup 0)
11529 (const_int 0)))]
11530 "")
11532 (define_insn "*plus_ne0di_compare"
11533 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11534 (compare:CC
11535 (plus:DI (lshiftrt:DI
11536 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11537 (const_int 63))
11538 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11539 (const_int 0)))
11540 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11541 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11542 (match_dup 2)))
11543 (clobber (match_scratch:DI 3 "=&r,&r"))]
11544 "TARGET_64BIT"
11545 "@
11546 addic %3,%1,-1\;addze. %0,%2
11547 #"
11548 [(set_attr "type" "compare")
11549 (set_attr "length" "8,12")])
11551 (define_split
11552 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11553 (compare:CC
11554 (plus:DI (lshiftrt:DI
11555 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11556 (const_int 63))
11557 (match_operand:DI 2 "gpc_reg_operand" ""))
11558 (const_int 0)))
11559 (set (match_operand:DI 0 "gpc_reg_operand" "")
11560 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11561 (match_dup 2)))
11562 (clobber (match_scratch:DI 3 ""))]
11563 "TARGET_64BIT && reload_completed"
11564 [(parallel [(set (match_dup 0)
11565 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11566 (match_dup 2)))
11567 (clobber (match_dup 3))])
11568 (set (match_dup 4)
11569 (compare:CC (match_dup 0)
11570 (const_int 0)))]
11571 "")
11573 (define_insn ""
11574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11575 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11576 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11577 (clobber (match_scratch:SI 3 "=r,X"))]
11578 "TARGET_POWER"
11579 "@
11580 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11581 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11582 [(set_attr "length" "12")])
11584 (define_insn ""
11585 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11586 (compare:CC
11587 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11588 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11589 (const_int 0)))
11590 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11591 (le:SI (match_dup 1) (match_dup 2)))
11592 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11593 "TARGET_POWER"
11594 "@
11595 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11596 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11597 #
11598 #"
11599 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11600 (set_attr "length" "12,12,16,16")])
11602 (define_split
11603 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11604 (compare:CC
11605 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11606 (match_operand:SI 2 "reg_or_short_operand" ""))
11607 (const_int 0)))
11608 (set (match_operand:SI 0 "gpc_reg_operand" "")
11609 (le:SI (match_dup 1) (match_dup 2)))
11610 (clobber (match_scratch:SI 3 ""))]
11611 "TARGET_POWER && reload_completed"
11612 [(parallel [(set (match_dup 0)
11613 (le:SI (match_dup 1) (match_dup 2)))
11614 (clobber (match_dup 3))])
11615 (set (match_dup 4)
11616 (compare:CC (match_dup 0)
11617 (const_int 0)))]
11618 "")
11620 (define_insn ""
11621 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11622 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11623 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11624 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11625 "TARGET_POWER"
11626 "@
11627 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11628 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11629 [(set_attr "length" "12")])
11631 (define_insn ""
11632 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11633 (compare:CC
11634 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11635 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11636 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11637 (const_int 0)))
11638 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11639 "TARGET_POWER"
11640 "@
11641 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11642 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11643 #
11644 #"
11645 [(set_attr "type" "compare")
11646 (set_attr "length" "12,12,16,16")])
11648 (define_split
11649 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11650 (compare:CC
11651 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11652 (match_operand:SI 2 "reg_or_short_operand" ""))
11653 (match_operand:SI 3 "gpc_reg_operand" ""))
11654 (const_int 0)))
11655 (clobber (match_scratch:SI 4 ""))]
11656 "TARGET_POWER && reload_completed"
11657 [(set (match_dup 4)
11658 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11659 (match_dup 3)))
11660 (set (match_dup 0)
11661 (compare:CC (match_dup 4)
11662 (const_int 0)))]
11663 "")
11665 (define_insn ""
11666 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11667 (compare:CC
11668 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11669 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11670 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11671 (const_int 0)))
11672 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11673 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11674 "TARGET_POWER"
11675 "@
11676 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11677 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11678 #
11679 #"
11680 [(set_attr "type" "compare")
11681 (set_attr "length" "12,12,16,16")])
11683 (define_split
11684 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11685 (compare:CC
11686 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11687 (match_operand:SI 2 "reg_or_short_operand" ""))
11688 (match_operand:SI 3 "gpc_reg_operand" ""))
11689 (const_int 0)))
11690 (set (match_operand:SI 0 "gpc_reg_operand" "")
11691 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11692 "TARGET_POWER && reload_completed"
11693 [(set (match_dup 0)
11694 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11695 (set (match_dup 4)
11696 (compare:CC (match_dup 0)
11697 (const_int 0)))]
11698 "")
11700 (define_insn ""
11701 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11702 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11703 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11704 "TARGET_POWER"
11705 "@
11706 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11707 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11708 [(set_attr "length" "12")])
11710 (define_insn "*leu<mode>"
11711 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11712 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11713 (match_operand:P 2 "reg_or_short_operand" "rI")))]
11714 ""
11715 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11716 [(set_attr "type" "three")
11717 (set_attr "length" "12")])
11719 (define_insn "*leu<mode>_compare"
11720 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11721 (compare:CC
11722 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
11723 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
11724 (const_int 0)))
11725 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
11726 (leu:P (match_dup 1) (match_dup 2)))]
11727 ""
11728 "@
11729 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11730 #"
11731 [(set_attr "type" "compare")
11732 (set_attr "length" "12,16")])
11734 (define_split
11735 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11736 (compare:CC
11737 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
11738 (match_operand:P 2 "reg_or_short_operand" ""))
11739 (const_int 0)))
11740 (set (match_operand:P 0 "gpc_reg_operand" "")
11741 (leu:P (match_dup 1) (match_dup 2)))]
11742 "reload_completed"
11743 [(set (match_dup 0)
11744 (leu:P (match_dup 1) (match_dup 2)))
11745 (set (match_dup 3)
11746 (compare:CC (match_dup 0)
11747 (const_int 0)))]
11748 "")
11750 (define_insn "*plus_leu<mode>"
11751 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
11752 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11753 (match_operand:P 2 "reg_or_short_operand" "rI"))
11754 (match_operand:P 3 "gpc_reg_operand" "r")))]
11755 ""
11756 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11757 [(set_attr "type" "two")
11758 (set_attr "length" "8")])
11760 (define_insn ""
11761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11762 (compare:CC
11763 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11764 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11765 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11766 (const_int 0)))
11767 (clobber (match_scratch:SI 4 "=&r,&r"))]
11768 "TARGET_32BIT"
11769 "@
11770 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11771 #"
11772 [(set_attr "type" "compare")
11773 (set_attr "length" "8,12")])
11775 (define_split
11776 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11777 (compare:CC
11778 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11779 (match_operand:SI 2 "reg_or_short_operand" ""))
11780 (match_operand:SI 3 "gpc_reg_operand" ""))
11781 (const_int 0)))
11782 (clobber (match_scratch:SI 4 ""))]
11783 "TARGET_32BIT && reload_completed"
11784 [(set (match_dup 4)
11785 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11786 (match_dup 3)))
11787 (set (match_dup 0)
11788 (compare:CC (match_dup 4)
11789 (const_int 0)))]
11790 "")
11792 (define_insn ""
11793 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11794 (compare:CC
11795 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11796 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11797 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11798 (const_int 0)))
11799 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11800 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11801 "TARGET_32BIT"
11802 "@
11803 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
11804 #"
11805 [(set_attr "type" "compare")
11806 (set_attr "length" "8,12")])
11808 (define_split
11809 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11810 (compare:CC
11811 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11812 (match_operand:SI 2 "reg_or_short_operand" ""))
11813 (match_operand:SI 3 "gpc_reg_operand" ""))
11814 (const_int 0)))
11815 (set (match_operand:SI 0 "gpc_reg_operand" "")
11816 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11817 "TARGET_32BIT && reload_completed"
11818 [(set (match_dup 0)
11819 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11820 (set (match_dup 4)
11821 (compare:CC (match_dup 0)
11822 (const_int 0)))]
11823 "")
11825 (define_insn "*neg_leu<mode>"
11826 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11827 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11828 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
11829 ""
11830 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11831 [(set_attr "type" "three")
11832 (set_attr "length" "12")])
11834 (define_insn "*and_neg_leu<mode>"
11835 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
11836 (and:P (neg:P
11837 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11838 (match_operand:P 2 "reg_or_short_operand" "rI")))
11839 (match_operand:P 3 "gpc_reg_operand" "r")))]
11840 ""
11841 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
11842 [(set_attr "type" "three")
11843 (set_attr "length" "12")])
11845 (define_insn ""
11846 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11847 (compare:CC
11848 (and:SI (neg:SI
11849 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11850 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11851 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11852 (const_int 0)))
11853 (clobber (match_scratch:SI 4 "=&r,&r"))]
11854 "TARGET_32BIT"
11855 "@
11856 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11857 #"
11858 [(set_attr "type" "compare")
11859 (set_attr "length" "12,16")])
11861 (define_split
11862 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11863 (compare:CC
11864 (and:SI (neg:SI
11865 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11866 (match_operand:SI 2 "reg_or_short_operand" "")))
11867 (match_operand:SI 3 "gpc_reg_operand" ""))
11868 (const_int 0)))
11869 (clobber (match_scratch:SI 4 ""))]
11870 "TARGET_32BIT && reload_completed"
11871 [(set (match_dup 4)
11872 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11873 (match_dup 3)))
11874 (set (match_dup 0)
11875 (compare:CC (match_dup 4)
11876 (const_int 0)))]
11877 "")
11879 (define_insn ""
11880 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11881 (compare:CC
11882 (and:SI (neg:SI
11883 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11884 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11885 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11886 (const_int 0)))
11887 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11888 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
11889 "TARGET_32BIT"
11890 "@
11891 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
11892 #"
11893 [(set_attr "type" "compare")
11894 (set_attr "length" "12,16")])
11896 (define_split
11897 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11898 (compare:CC
11899 (and:SI (neg:SI
11900 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11901 (match_operand:SI 2 "reg_or_short_operand" "")))
11902 (match_operand:SI 3 "gpc_reg_operand" ""))
11903 (const_int 0)))
11904 (set (match_operand:SI 0 "gpc_reg_operand" "")
11905 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
11906 "TARGET_32BIT && reload_completed"
11907 [(set (match_dup 0)
11908 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11909 (match_dup 3)))
11910 (set (match_dup 4)
11911 (compare:CC (match_dup 0)
11912 (const_int 0)))]
11913 "")
11915 (define_insn ""
11916 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11917 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11918 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11919 "TARGET_POWER"
11920 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11921 [(set_attr "length" "12")])
11923 (define_insn ""
11924 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11925 (compare:CC
11926 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11927 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11928 (const_int 0)))
11929 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11930 (lt:SI (match_dup 1) (match_dup 2)))]
11931 "TARGET_POWER"
11932 "@
11933 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11934 #"
11935 [(set_attr "type" "delayed_compare")
11936 (set_attr "length" "12,16")])
11938 (define_split
11939 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11940 (compare:CC
11941 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11942 (match_operand:SI 2 "reg_or_short_operand" ""))
11943 (const_int 0)))
11944 (set (match_operand:SI 0 "gpc_reg_operand" "")
11945 (lt:SI (match_dup 1) (match_dup 2)))]
11946 "TARGET_POWER && reload_completed"
11947 [(set (match_dup 0)
11948 (lt:SI (match_dup 1) (match_dup 2)))
11949 (set (match_dup 3)
11950 (compare:CC (match_dup 0)
11951 (const_int 0)))]
11952 "")
11954 (define_insn ""
11955 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11956 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11957 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11958 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11959 "TARGET_POWER"
11960 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
11961 [(set_attr "length" "12")])
11963 (define_insn ""
11964 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11965 (compare:CC
11966 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11967 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11968 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11969 (const_int 0)))
11970 (clobber (match_scratch:SI 4 "=&r,&r"))]
11971 "TARGET_POWER"
11972 "@
11973 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11974 #"
11975 [(set_attr "type" "compare")
11976 (set_attr "length" "12,16")])
11978 (define_split
11979 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11980 (compare:CC
11981 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11982 (match_operand:SI 2 "reg_or_short_operand" ""))
11983 (match_operand:SI 3 "gpc_reg_operand" ""))
11984 (const_int 0)))
11985 (clobber (match_scratch:SI 4 ""))]
11986 "TARGET_POWER && reload_completed"
11987 [(set (match_dup 4)
11988 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
11989 (match_dup 3)))
11990 (set (match_dup 0)
11991 (compare:CC (match_dup 4)
11992 (const_int 0)))]
11993 "")
11995 (define_insn ""
11996 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11997 (compare:CC
11998 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11999 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12000 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12001 (const_int 0)))
12002 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12003 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12004 "TARGET_POWER"
12005 "@
12006 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12007 #"
12008 [(set_attr "type" "compare")
12009 (set_attr "length" "12,16")])
12011 (define_split
12012 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12013 (compare:CC
12014 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12015 (match_operand:SI 2 "reg_or_short_operand" ""))
12016 (match_operand:SI 3 "gpc_reg_operand" ""))
12017 (const_int 0)))
12018 (set (match_operand:SI 0 "gpc_reg_operand" "")
12019 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12020 "TARGET_POWER && reload_completed"
12021 [(set (match_dup 0)
12022 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12023 (set (match_dup 4)
12024 (compare:CC (match_dup 0)
12025 (const_int 0)))]
12026 "")
12028 (define_insn ""
12029 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12030 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12031 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12032 "TARGET_POWER"
12033 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12034 [(set_attr "length" "12")])
12036 (define_insn_and_split "*ltu<mode>"
12037 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12038 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12039 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12040 ""
12041 "#"
12042 ""
12043 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12044 (set (match_dup 0) (neg:P (match_dup 0)))]
12045 "")
12047 (define_insn_and_split "*ltu<mode>_compare"
12048 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12049 (compare:CC
12050 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12051 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12052 (const_int 0)))
12053 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12054 (ltu:P (match_dup 1) (match_dup 2)))]
12055 ""
12056 "#"
12057 ""
12058 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12059 (parallel [(set (match_dup 3)
12060 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12061 (set (match_dup 0) (neg:P (match_dup 0)))])]
12062 "")
12064 (define_insn_and_split "*plus_ltu<mode>"
12065 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12066 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12067 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12068 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12069 ""
12070 "#"
12071 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12072 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12073 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12074 "")
12076 (define_insn_and_split "*plus_ltu<mode>_compare"
12077 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12078 (compare:CC
12079 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12080 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12081 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12082 (const_int 0)))
12083 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12084 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12085 ""
12086 "#"
12087 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12088 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12089 (parallel [(set (match_dup 4)
12090 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12091 (const_int 0)))
12092 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12093 "")
12095 (define_insn "*neg_ltu<mode>"
12096 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12097 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12098 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12099 ""
12100 "@
12101 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12102 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12103 [(set_attr "type" "two")
12104 (set_attr "length" "8")])
12106 (define_insn ""
12107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12108 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12109 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12110 (clobber (match_scratch:SI 3 "=r"))]
12111 "TARGET_POWER"
12112 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12113 [(set_attr "length" "12")])
12115 (define_insn ""
12116 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12117 (compare:CC
12118 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12119 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12120 (const_int 0)))
12121 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12122 (ge:SI (match_dup 1) (match_dup 2)))
12123 (clobber (match_scratch:SI 3 "=r,r"))]
12124 "TARGET_POWER"
12125 "@
12126 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12127 #"
12128 [(set_attr "type" "compare")
12129 (set_attr "length" "12,16")])
12131 (define_split
12132 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12133 (compare:CC
12134 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12135 (match_operand:SI 2 "reg_or_short_operand" ""))
12136 (const_int 0)))
12137 (set (match_operand:SI 0 "gpc_reg_operand" "")
12138 (ge:SI (match_dup 1) (match_dup 2)))
12139 (clobber (match_scratch:SI 3 ""))]
12140 "TARGET_POWER && reload_completed"
12141 [(parallel [(set (match_dup 0)
12142 (ge:SI (match_dup 1) (match_dup 2)))
12143 (clobber (match_dup 3))])
12144 (set (match_dup 4)
12145 (compare:CC (match_dup 0)
12146 (const_int 0)))]
12147 "")
12149 (define_insn ""
12150 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12151 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12152 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12153 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12154 "TARGET_POWER"
12155 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12156 [(set_attr "length" "12")])
12158 (define_insn ""
12159 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12160 (compare:CC
12161 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12162 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12163 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12164 (const_int 0)))
12165 (clobber (match_scratch:SI 4 "=&r,&r"))]
12166 "TARGET_POWER"
12167 "@
12168 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12169 #"
12170 [(set_attr "type" "compare")
12171 (set_attr "length" "12,16")])
12173 (define_split
12174 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12175 (compare:CC
12176 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12177 (match_operand:SI 2 "reg_or_short_operand" ""))
12178 (match_operand:SI 3 "gpc_reg_operand" ""))
12179 (const_int 0)))
12180 (clobber (match_scratch:SI 4 ""))]
12181 "TARGET_POWER && reload_completed"
12182 [(set (match_dup 4)
12183 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12184 (match_dup 3)))
12185 (set (match_dup 0)
12186 (compare:CC (match_dup 4)
12187 (const_int 0)))]
12188 "")
12190 (define_insn ""
12191 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12192 (compare:CC
12193 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12194 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12195 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12196 (const_int 0)))
12197 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12198 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12199 "TARGET_POWER"
12200 "@
12201 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12202 #"
12203 [(set_attr "type" "compare")
12204 (set_attr "length" "12,16")])
12206 (define_split
12207 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12208 (compare:CC
12209 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12210 (match_operand:SI 2 "reg_or_short_operand" ""))
12211 (match_operand:SI 3 "gpc_reg_operand" ""))
12212 (const_int 0)))
12213 (set (match_operand:SI 0 "gpc_reg_operand" "")
12214 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12215 "TARGET_POWER && reload_completed"
12216 [(set (match_dup 0)
12217 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12218 (set (match_dup 4)
12219 (compare:CC (match_dup 0)
12220 (const_int 0)))]
12221 "")
12223 (define_insn ""
12224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12225 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12226 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12227 "TARGET_POWER"
12228 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12229 [(set_attr "length" "12")])
12231 (define_insn "*geu<mode>"
12232 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12233 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12234 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12235 ""
12236 "@
12237 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12238 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12239 [(set_attr "type" "three")
12240 (set_attr "length" "12")])
12242 (define_insn "*geu<mode>_compare"
12243 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12244 (compare:CC
12245 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12246 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12247 (const_int 0)))
12248 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12249 (geu:P (match_dup 1) (match_dup 2)))]
12250 ""
12251 "@
12252 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12253 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12254 #
12255 #"
12256 [(set_attr "type" "compare")
12257 (set_attr "length" "12,12,16,16")])
12259 (define_split
12260 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12261 (compare:CC
12262 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12263 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12264 (const_int 0)))
12265 (set (match_operand:P 0 "gpc_reg_operand" "")
12266 (geu:P (match_dup 1) (match_dup 2)))]
12267 "reload_completed"
12268 [(set (match_dup 0)
12269 (geu:P (match_dup 1) (match_dup 2)))
12270 (set (match_dup 3)
12271 (compare:CC (match_dup 0)
12272 (const_int 0)))]
12273 "")
12275 (define_insn "*plus_geu<mode>"
12276 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12277 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12278 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12279 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12280 ""
12281 "@
12282 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12283 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12284 [(set_attr "type" "two")
12285 (set_attr "length" "8")])
12287 (define_insn ""
12288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12289 (compare:CC
12290 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12291 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12292 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12293 (const_int 0)))
12294 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12295 "TARGET_32BIT"
12296 "@
12297 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12298 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12299 #
12300 #"
12301 [(set_attr "type" "compare")
12302 (set_attr "length" "8,8,12,12")])
12304 (define_split
12305 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12306 (compare:CC
12307 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12308 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12309 (match_operand:SI 3 "gpc_reg_operand" ""))
12310 (const_int 0)))
12311 (clobber (match_scratch:SI 4 ""))]
12312 "TARGET_32BIT && reload_completed"
12313 [(set (match_dup 4)
12314 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12315 (match_dup 3)))
12316 (set (match_dup 0)
12317 (compare:CC (match_dup 4)
12318 (const_int 0)))]
12319 "")
12321 (define_insn ""
12322 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12323 (compare:CC
12324 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12325 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12326 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12327 (const_int 0)))
12328 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12329 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12330 "TARGET_32BIT"
12331 "@
12332 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12333 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12334 #
12335 #"
12336 [(set_attr "type" "compare")
12337 (set_attr "length" "8,8,12,12")])
12339 (define_split
12340 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12341 (compare:CC
12342 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12343 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12344 (match_operand:SI 3 "gpc_reg_operand" ""))
12345 (const_int 0)))
12346 (set (match_operand:SI 0 "gpc_reg_operand" "")
12347 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12348 "TARGET_32BIT && reload_completed"
12349 [(set (match_dup 0)
12350 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12351 (set (match_dup 4)
12352 (compare:CC (match_dup 0)
12353 (const_int 0)))]
12354 "")
12356 (define_insn "*neg_geu<mode>"
12357 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12358 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12359 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12360 ""
12361 "@
12362 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12363 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12364 [(set_attr "type" "three")
12365 (set_attr "length" "12")])
12367 (define_insn "*and_neg_geu<mode>"
12368 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12369 (and:P (neg:P
12370 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12371 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12372 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12373 ""
12374 "@
12375 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12376 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12377 [(set_attr "type" "three")
12378 (set_attr "length" "12")])
12380 (define_insn ""
12381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12382 (compare:CC
12383 (and:SI (neg:SI
12384 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12385 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12386 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12387 (const_int 0)))
12388 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12389 "TARGET_32BIT"
12390 "@
12391 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12392 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12393 #
12394 #"
12395 [(set_attr "type" "compare")
12396 (set_attr "length" "12,12,16,16")])
12398 (define_split
12399 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12400 (compare:CC
12401 (and:SI (neg:SI
12402 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12403 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12404 (match_operand:SI 3 "gpc_reg_operand" ""))
12405 (const_int 0)))
12406 (clobber (match_scratch:SI 4 ""))]
12407 "TARGET_32BIT && reload_completed"
12408 [(set (match_dup 4)
12409 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12410 (match_dup 3)))
12411 (set (match_dup 0)
12412 (compare:CC (match_dup 4)
12413 (const_int 0)))]
12414 "")
12416 (define_insn ""
12417 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12418 (compare:CC
12419 (and:SI (neg:SI
12420 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12421 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12422 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12423 (const_int 0)))
12424 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12425 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12426 "TARGET_32BIT"
12427 "@
12428 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12429 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12430 #
12431 #"
12432 [(set_attr "type" "compare")
12433 (set_attr "length" "12,12,16,16")])
12435 (define_split
12436 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12437 (compare:CC
12438 (and:SI (neg:SI
12439 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12440 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12441 (match_operand:SI 3 "gpc_reg_operand" ""))
12442 (const_int 0)))
12443 (set (match_operand:SI 0 "gpc_reg_operand" "")
12444 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12445 "TARGET_32BIT && reload_completed"
12446 [(set (match_dup 0)
12447 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12448 (set (match_dup 4)
12449 (compare:CC (match_dup 0)
12450 (const_int 0)))]
12451 "")
12453 (define_insn ""
12454 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12455 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12456 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12457 "TARGET_POWER"
12458 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12459 [(set_attr "length" "12")])
12461 (define_insn ""
12462 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12463 (compare:CC
12464 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12465 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12466 (const_int 0)))
12467 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12468 (gt:SI (match_dup 1) (match_dup 2)))]
12469 "TARGET_POWER"
12470 "@
12471 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12472 #"
12473 [(set_attr "type" "delayed_compare")
12474 (set_attr "length" "12,16")])
12476 (define_split
12477 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12478 (compare:CC
12479 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12480 (match_operand:SI 2 "reg_or_short_operand" ""))
12481 (const_int 0)))
12482 (set (match_operand:SI 0 "gpc_reg_operand" "")
12483 (gt:SI (match_dup 1) (match_dup 2)))]
12484 "TARGET_POWER && reload_completed"
12485 [(set (match_dup 0)
12486 (gt:SI (match_dup 1) (match_dup 2)))
12487 (set (match_dup 3)
12488 (compare:CC (match_dup 0)
12489 (const_int 0)))]
12490 "")
12492 (define_insn "*plus_gt0<mode>"
12493 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12494 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12495 (const_int 0))
12496 (match_operand:P 2 "gpc_reg_operand" "r")))]
12497 ""
12498 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12499 [(set_attr "type" "three")
12500 (set_attr "length" "12")])
12502 (define_insn ""
12503 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12504 (compare:CC
12505 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12506 (const_int 0))
12507 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12508 (const_int 0)))
12509 (clobber (match_scratch:SI 3 "=&r,&r"))]
12510 "TARGET_32BIT"
12511 "@
12512 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12513 #"
12514 [(set_attr "type" "compare")
12515 (set_attr "length" "12,16")])
12517 (define_split
12518 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12519 (compare:CC
12520 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12521 (const_int 0))
12522 (match_operand:SI 2 "gpc_reg_operand" ""))
12523 (const_int 0)))
12524 (clobber (match_scratch:SI 3 ""))]
12525 "TARGET_32BIT && reload_completed"
12526 [(set (match_dup 3)
12527 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12528 (match_dup 2)))
12529 (set (match_dup 0)
12530 (compare:CC (match_dup 3)
12531 (const_int 0)))]
12532 "")
12534 (define_insn ""
12535 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12536 (compare:CC
12537 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12538 (const_int 0))
12539 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12540 (const_int 0)))
12541 (clobber (match_scratch:DI 3 "=&r,&r"))]
12542 "TARGET_64BIT"
12543 "@
12544 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12545 #"
12546 [(set_attr "type" "compare")
12547 (set_attr "length" "12,16")])
12549 (define_split
12550 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12551 (compare:CC
12552 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12553 (const_int 0))
12554 (match_operand:DI 2 "gpc_reg_operand" ""))
12555 (const_int 0)))
12556 (clobber (match_scratch:DI 3 ""))]
12557 "TARGET_64BIT && reload_completed"
12558 [(set (match_dup 3)
12559 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12560 (match_dup 2)))
12561 (set (match_dup 0)
12562 (compare:CC (match_dup 3)
12563 (const_int 0)))]
12564 "")
12566 (define_insn ""
12567 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12568 (compare:CC
12569 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12570 (const_int 0))
12571 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12572 (const_int 0)))
12573 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12574 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12575 "TARGET_32BIT"
12576 "@
12577 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
12578 #"
12579 [(set_attr "type" "compare")
12580 (set_attr "length" "12,16")])
12582 (define_split
12583 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12584 (compare:CC
12585 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12586 (const_int 0))
12587 (match_operand:SI 2 "gpc_reg_operand" ""))
12588 (const_int 0)))
12589 (set (match_operand:SI 0 "gpc_reg_operand" "")
12590 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12591 "TARGET_32BIT && reload_completed"
12592 [(set (match_dup 0)
12593 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12594 (set (match_dup 3)
12595 (compare:CC (match_dup 0)
12596 (const_int 0)))]
12597 "")
12599 (define_insn ""
12600 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12601 (compare:CC
12602 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12603 (const_int 0))
12604 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12605 (const_int 0)))
12606 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12607 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12608 "TARGET_64BIT"
12609 "@
12610 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12611 #"
12612 [(set_attr "type" "compare")
12613 (set_attr "length" "12,16")])
12615 (define_split
12616 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12617 (compare:CC
12618 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12619 (const_int 0))
12620 (match_operand:DI 2 "gpc_reg_operand" ""))
12621 (const_int 0)))
12622 (set (match_operand:DI 0 "gpc_reg_operand" "")
12623 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12624 "TARGET_64BIT && reload_completed"
12625 [(set (match_dup 0)
12626 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12627 (set (match_dup 3)
12628 (compare:CC (match_dup 0)
12629 (const_int 0)))]
12630 "")
12632 (define_insn ""
12633 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12634 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12635 (match_operand:SI 2 "reg_or_short_operand" "r"))
12636 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12637 "TARGET_POWER"
12638 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12639 [(set_attr "length" "12")])
12641 (define_insn ""
12642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12643 (compare:CC
12644 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12645 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12646 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12647 (const_int 0)))
12648 (clobber (match_scratch:SI 4 "=&r,&r"))]
12649 "TARGET_POWER"
12650 "@
12651 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12652 #"
12653 [(set_attr "type" "compare")
12654 (set_attr "length" "12,16")])
12656 (define_split
12657 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12658 (compare:CC
12659 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12660 (match_operand:SI 2 "reg_or_short_operand" ""))
12661 (match_operand:SI 3 "gpc_reg_operand" ""))
12662 (const_int 0)))
12663 (clobber (match_scratch:SI 4 ""))]
12664 "TARGET_POWER && reload_completed"
12665 [(set (match_dup 4)
12666 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12667 (set (match_dup 0)
12668 (compare:CC (match_dup 4)
12669 (const_int 0)))]
12670 "")
12672 (define_insn ""
12673 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12674 (compare:CC
12675 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12676 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12677 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12678 (const_int 0)))
12679 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12680 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12681 "TARGET_POWER"
12682 "@
12683 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12684 #"
12685 [(set_attr "type" "compare")
12686 (set_attr "length" "12,16")])
12688 (define_split
12689 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12690 (compare:CC
12691 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12692 (match_operand:SI 2 "reg_or_short_operand" ""))
12693 (match_operand:SI 3 "gpc_reg_operand" ""))
12694 (const_int 0)))
12695 (set (match_operand:SI 0 "gpc_reg_operand" "")
12696 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12697 "TARGET_POWER && reload_completed"
12698 [(set (match_dup 0)
12699 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12700 (set (match_dup 4)
12701 (compare:CC (match_dup 0)
12702 (const_int 0)))]
12703 "")
12705 (define_insn ""
12706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12707 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12708 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12709 "TARGET_POWER"
12710 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12711 [(set_attr "length" "12")])
12713 (define_insn_and_split "*gtu<mode>"
12714 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12715 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12716 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12717 ""
12718 "#"
12719 ""
12720 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12721 (set (match_dup 0) (neg:P (match_dup 0)))]
12722 "")
12724 (define_insn_and_split "*gtu<mode>_compare"
12725 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12726 (compare:CC
12727 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12728 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12729 (const_int 0)))
12730 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12731 (gtu:P (match_dup 1) (match_dup 2)))]
12732 ""
12733 "#"
12734 ""
12735 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12736 (parallel [(set (match_dup 3)
12737 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12738 (set (match_dup 0) (neg:P (match_dup 0)))])]
12739 "")
12741 (define_insn_and_split "*plus_gtu<mode>"
12742 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12743 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12744 (match_operand:P 2 "reg_or_short_operand" "rI"))
12745 (match_operand:P 3 "reg_or_short_operand" "rI")))]
12746 ""
12747 "#"
12748 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12749 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12750 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12751 "")
12753 (define_insn_and_split "*plus_gtu<mode>_compare"
12754 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12755 (compare:CC
12756 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12757 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
12758 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12759 (const_int 0)))
12760 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12761 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12762 ""
12763 "#"
12764 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12765 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12766 (parallel [(set (match_dup 4)
12767 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12768 (const_int 0)))
12769 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12770 "")
12772 (define_insn "*neg_gtu<mode>"
12773 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12774 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12775 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12776 ""
12777 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
12778 [(set_attr "type" "two")
12779 (set_attr "length" "8")])
12781 \f
12782 ;; Define both directions of branch and return. If we need a reload
12783 ;; register, we'd rather use CR0 since it is much easier to copy a
12784 ;; register CC value to there.
12786 (define_insn ""
12787 [(set (pc)
12788 (if_then_else (match_operator 1 "branch_comparison_operator"
12789 [(match_operand 2
12790 "cc_reg_operand" "y")
12791 (const_int 0)])
12792 (label_ref (match_operand 0 "" ""))
12793 (pc)))]
12794 ""
12795 "*
12796 {
12797 return output_cbranch (operands[1], \"%l0\", 0, insn);
12798 }"
12799 [(set_attr "type" "branch")])
12801 (define_insn ""
12802 [(set (pc)
12803 (if_then_else (match_operator 0 "branch_comparison_operator"
12804 [(match_operand 1
12805 "cc_reg_operand" "y")
12806 (const_int 0)])
12807 (return)
12808 (pc)))]
12809 "direct_return ()"
12810 "*
12811 {
12812 return output_cbranch (operands[0], NULL, 0, insn);
12813 }"
12814 [(set_attr "type" "branch")
12815 (set_attr "length" "4")])
12817 (define_insn ""
12818 [(set (pc)
12819 (if_then_else (match_operator 1 "branch_comparison_operator"
12820 [(match_operand 2
12821 "cc_reg_operand" "y")
12822 (const_int 0)])
12823 (pc)
12824 (label_ref (match_operand 0 "" ""))))]
12825 ""
12826 "*
12827 {
12828 return output_cbranch (operands[1], \"%l0\", 1, insn);
12829 }"
12830 [(set_attr "type" "branch")])
12832 (define_insn ""
12833 [(set (pc)
12834 (if_then_else (match_operator 0 "branch_comparison_operator"
12835 [(match_operand 1
12836 "cc_reg_operand" "y")
12837 (const_int 0)])
12838 (pc)
12839 (return)))]
12840 "direct_return ()"
12841 "*
12842 {
12843 return output_cbranch (operands[0], NULL, 1, insn);
12844 }"
12845 [(set_attr "type" "branch")
12846 (set_attr "length" "4")])
12848 ;; Logic on condition register values.
12850 ; This pattern matches things like
12851 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12852 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12853 ; (const_int 1)))
12854 ; which are generated by the branch logic.
12855 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
12857 (define_insn "*cceq_ior_compare"
12858 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12859 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12860 [(match_operator:SI 2
12861 "branch_positive_comparison_operator"
12862 [(match_operand 3
12863 "cc_reg_operand" "y,y")
12864 (const_int 0)])
12865 (match_operator:SI 4
12866 "branch_positive_comparison_operator"
12867 [(match_operand 5
12868 "cc_reg_operand" "0,y")
12869 (const_int 0)])])
12870 (const_int 1)))]
12871 ""
12872 "cr%q1 %E0,%j2,%j4"
12873 [(set_attr "type" "cr_logical,delayed_cr")])
12875 ; Why is the constant -1 here, but 1 in the previous pattern?
12876 ; Because ~1 has all but the low bit set.
12877 (define_insn ""
12878 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12879 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12880 [(not:SI (match_operator:SI 2
12881 "branch_positive_comparison_operator"
12882 [(match_operand 3
12883 "cc_reg_operand" "y,y")
12884 (const_int 0)]))
12885 (match_operator:SI 4
12886 "branch_positive_comparison_operator"
12887 [(match_operand 5
12888 "cc_reg_operand" "0,y")
12889 (const_int 0)])])
12890 (const_int -1)))]
12891 ""
12892 "cr%q1 %E0,%j2,%j4"
12893 [(set_attr "type" "cr_logical,delayed_cr")])
12895 (define_insn "*cceq_rev_compare"
12896 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12897 (compare:CCEQ (match_operator:SI 1
12898 "branch_positive_comparison_operator"
12899 [(match_operand 2
12900 "cc_reg_operand" "0,y")
12901 (const_int 0)])
12902 (const_int 0)))]
12903 ""
12904 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
12905 [(set_attr "type" "cr_logical,delayed_cr")])
12907 ;; If we are comparing the result of two comparisons, this can be done
12908 ;; using creqv or crxor.
12910 (define_insn_and_split ""
12911 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12912 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12913 [(match_operand 2 "cc_reg_operand" "y")
12914 (const_int 0)])
12915 (match_operator 3 "branch_comparison_operator"
12916 [(match_operand 4 "cc_reg_operand" "y")
12917 (const_int 0)])))]
12918 ""
12919 "#"
12920 ""
12921 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12922 (match_dup 5)))]
12923 "
12924 {
12925 int positive_1, positive_2;
12927 positive_1 = branch_positive_comparison_operator (operands[1],
12928 GET_MODE (operands[1]));
12929 positive_2 = branch_positive_comparison_operator (operands[3],
12930 GET_MODE (operands[3]));
12932 if (! positive_1)
12933 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
12934 GET_CODE (operands[1])),
12935 SImode,
12936 operands[2], const0_rtx);
12937 else if (GET_MODE (operands[1]) != SImode)
12938 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
12939 operands[2], const0_rtx);
12941 if (! positive_2)
12942 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
12943 GET_CODE (operands[3])),
12944 SImode,
12945 operands[4], const0_rtx);
12946 else if (GET_MODE (operands[3]) != SImode)
12947 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
12948 operands[4], const0_rtx);
12950 if (positive_1 == positive_2)
12951 {
12952 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12953 operands[5] = constm1_rtx;
12954 }
12955 else
12956 {
12957 operands[5] = const1_rtx;
12958 }
12959 }")
12961 ;; Unconditional branch and return.
12963 (define_insn "jump"
12964 [(set (pc)
12965 (label_ref (match_operand 0 "" "")))]
12966 ""
12967 "b %l0"
12968 [(set_attr "type" "branch")])
12970 (define_insn "return"
12971 [(return)]
12972 "direct_return ()"
12973 "{br|blr}"
12974 [(set_attr "type" "jmpreg")])
12976 (define_expand "indirect_jump"
12977 [(set (pc) (match_operand 0 "register_operand" ""))])
12979 (define_insn "*indirect_jump<mode>"
12980 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
12981 ""
12982 "@
12983 bctr
12984 {br|blr}"
12985 [(set_attr "type" "jmpreg")])
12987 ;; Table jump for switch statements:
12988 (define_expand "tablejump"
12989 [(use (match_operand 0 "" ""))
12990 (use (label_ref (match_operand 1 "" "")))]
12991 ""
12992 "
12993 {
12994 if (TARGET_32BIT)
12995 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
12996 else
12997 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
12998 DONE;
12999 }")
13001 (define_expand "tablejumpsi"
13002 [(set (match_dup 3)
13003 (plus:SI (match_operand:SI 0 "" "")
13004 (match_dup 2)))
13005 (parallel [(set (pc) (match_dup 3))
13006 (use (label_ref (match_operand 1 "" "")))])]
13007 "TARGET_32BIT"
13008 "
13009 { operands[0] = force_reg (SImode, operands[0]);
13010 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13011 operands[3] = gen_reg_rtx (SImode);
13012 }")
13014 (define_expand "tablejumpdi"
13015 [(set (match_dup 4)
13016 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13017 (set (match_dup 3)
13018 (plus:DI (match_dup 4)
13019 (match_dup 2)))
13020 (parallel [(set (pc) (match_dup 3))
13021 (use (label_ref (match_operand 1 "" "")))])]
13022 "TARGET_64BIT"
13023 "
13024 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13025 operands[3] = gen_reg_rtx (DImode);
13026 operands[4] = gen_reg_rtx (DImode);
13027 }")
13029 (define_insn "*tablejump<mode>_internal1"
13030 [(set (pc)
13031 (match_operand:P 0 "register_operand" "c,*l"))
13032 (use (label_ref (match_operand 1 "" "")))]
13033 ""
13034 "@
13035 bctr
13036 {br|blr}"
13037 [(set_attr "type" "jmpreg")])
13039 (define_insn "nop"
13040 [(const_int 0)]
13041 ""
13042 "{cror 0,0,0|nop}")
13043 \f
13044 ;; Define the subtract-one-and-jump insns, starting with the template
13045 ;; so loop.c knows what to generate.
13047 (define_expand "doloop_end"
13048 [(use (match_operand 0 "" "")) ; loop pseudo
13049 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13050 (use (match_operand 2 "" "")) ; max iterations
13051 (use (match_operand 3 "" "")) ; loop level
13052 (use (match_operand 4 "" ""))] ; label
13053 ""
13054 "
13055 {
13056 /* Only use this on innermost loops. */
13057 if (INTVAL (operands[3]) > 1)
13058 FAIL;
13059 if (TARGET_64BIT)
13060 {
13061 if (GET_MODE (operands[0]) != DImode)
13062 FAIL;
13063 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13064 }
13065 else
13066 {
13067 if (GET_MODE (operands[0]) != SImode)
13068 FAIL;
13069 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13070 }
13071 DONE;
13072 }")
13074 (define_expand "ctr<mode>"
13075 [(parallel [(set (pc)
13076 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13077 (const_int 1))
13078 (label_ref (match_operand 1 "" ""))
13079 (pc)))
13080 (set (match_dup 0)
13081 (plus:P (match_dup 0)
13082 (const_int -1)))
13083 (clobber (match_scratch:CC 2 ""))
13084 (clobber (match_scratch:P 3 ""))])]
13085 ""
13086 "")
13088 ;; We need to be able to do this for any operand, including MEM, or we
13089 ;; will cause reload to blow up since we don't allow output reloads on
13090 ;; JUMP_INSNs.
13091 ;; For the length attribute to be calculated correctly, the
13092 ;; label MUST be operand 0.
13094 (define_insn "*ctr<mode>_internal1"
13095 [(set (pc)
13096 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13097 (const_int 1))
13098 (label_ref (match_operand 0 "" ""))
13099 (pc)))
13100 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13101 (plus:P (match_dup 1)
13102 (const_int -1)))
13103 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13104 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13105 ""
13106 "*
13107 {
13108 if (which_alternative != 0)
13109 return \"#\";
13110 else if (get_attr_length (insn) == 4)
13111 return \"{bdn|bdnz} %l0\";
13112 else
13113 return \"bdz $+8\;b %l0\";
13114 }"
13115 [(set_attr "type" "branch")
13116 (set_attr "length" "*,12,16,16")])
13118 (define_insn "*ctr<mode>_internal2"
13119 [(set (pc)
13120 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13121 (const_int 1))
13122 (pc)
13123 (label_ref (match_operand 0 "" ""))))
13124 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13125 (plus:P (match_dup 1)
13126 (const_int -1)))
13127 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13128 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13129 ""
13130 "*
13131 {
13132 if (which_alternative != 0)
13133 return \"#\";
13134 else if (get_attr_length (insn) == 4)
13135 return \"bdz %l0\";
13136 else
13137 return \"{bdn|bdnz} $+8\;b %l0\";
13138 }"
13139 [(set_attr "type" "branch")
13140 (set_attr "length" "*,12,16,16")])
13142 ;; Similar but use EQ
13144 (define_insn "*ctr<mode>_internal5"
13145 [(set (pc)
13146 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13147 (const_int 1))
13148 (label_ref (match_operand 0 "" ""))
13149 (pc)))
13150 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13151 (plus:P (match_dup 1)
13152 (const_int -1)))
13153 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13154 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13155 ""
13156 "*
13157 {
13158 if (which_alternative != 0)
13159 return \"#\";
13160 else if (get_attr_length (insn) == 4)
13161 return \"bdz %l0\";
13162 else
13163 return \"{bdn|bdnz} $+8\;b %l0\";
13164 }"
13165 [(set_attr "type" "branch")
13166 (set_attr "length" "*,12,16,16")])
13168 (define_insn "*ctr<mode>_internal6"
13169 [(set (pc)
13170 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13171 (const_int 1))
13172 (pc)
13173 (label_ref (match_operand 0 "" ""))))
13174 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13175 (plus:P (match_dup 1)
13176 (const_int -1)))
13177 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13178 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13179 ""
13180 "*
13181 {
13182 if (which_alternative != 0)
13183 return \"#\";
13184 else if (get_attr_length (insn) == 4)
13185 return \"{bdn|bdnz} %l0\";
13186 else
13187 return \"bdz $+8\;b %l0\";
13188 }"
13189 [(set_attr "type" "branch")
13190 (set_attr "length" "*,12,16,16")])
13192 ;; Now the splitters if we could not allocate the CTR register
13194 (define_split
13195 [(set (pc)
13196 (if_then_else (match_operator 2 "comparison_operator"
13197 [(match_operand:P 1 "gpc_reg_operand" "")
13198 (const_int 1)])
13199 (match_operand 5 "" "")
13200 (match_operand 6 "" "")))
13201 (set (match_operand:P 0 "gpc_reg_operand" "")
13202 (plus:P (match_dup 1) (const_int -1)))
13203 (clobber (match_scratch:CC 3 ""))
13204 (clobber (match_scratch:P 4 ""))]
13205 "reload_completed"
13206 [(parallel [(set (match_dup 3)
13207 (compare:CC (plus:P (match_dup 1)
13208 (const_int -1))
13209 (const_int 0)))
13210 (set (match_dup 0)
13211 (plus:P (match_dup 1)
13212 (const_int -1)))])
13213 (set (pc) (if_then_else (match_dup 7)
13214 (match_dup 5)
13215 (match_dup 6)))]
13216 "
13217 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13218 operands[3], const0_rtx); }")
13220 (define_split
13221 [(set (pc)
13222 (if_then_else (match_operator 2 "comparison_operator"
13223 [(match_operand:P 1 "gpc_reg_operand" "")
13224 (const_int 1)])
13225 (match_operand 5 "" "")
13226 (match_operand 6 "" "")))
13227 (set (match_operand:P 0 "nonimmediate_operand" "")
13228 (plus:P (match_dup 1) (const_int -1)))
13229 (clobber (match_scratch:CC 3 ""))
13230 (clobber (match_scratch:P 4 ""))]
13231 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13232 [(parallel [(set (match_dup 3)
13233 (compare:CC (plus:P (match_dup 1)
13234 (const_int -1))
13235 (const_int 0)))
13236 (set (match_dup 4)
13237 (plus:P (match_dup 1)
13238 (const_int -1)))])
13239 (set (match_dup 0)
13240 (match_dup 4))
13241 (set (pc) (if_then_else (match_dup 7)
13242 (match_dup 5)
13243 (match_dup 6)))]
13244 "
13245 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13246 operands[3], const0_rtx); }")
13247 \f
13248 (define_insn "trap"
13249 [(trap_if (const_int 1) (const_int 0))]
13250 ""
13251 "{t 31,0,0|trap}")
13253 (define_expand "conditional_trap"
13254 [(trap_if (match_operator 0 "trap_comparison_operator"
13255 [(match_dup 2) (match_dup 3)])
13256 (match_operand 1 "const_int_operand" ""))]
13257 ""
13258 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13259 operands[2] = rs6000_compare_op0;
13260 operands[3] = rs6000_compare_op1;")
13262 (define_insn ""
13263 [(trap_if (match_operator 0 "trap_comparison_operator"
13264 [(match_operand:GPR 1 "register_operand" "r")
13265 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13266 (const_int 0))]
13267 ""
13268 "{t|t<wd>}%V0%I2 %1,%2")
13269 \f
13270 ;; Insns related to generating the function prologue and epilogue.
13272 (define_expand "prologue"
13273 [(use (const_int 0))]
13274 "TARGET_SCHED_PROLOG"
13275 "
13276 {
13277 rs6000_emit_prologue ();
13278 DONE;
13279 }")
13281 (define_insn "*movesi_from_cr_one"
13282 [(match_parallel 0 "mfcr_operation"
13283 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13284 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13285 (match_operand 3 "immediate_operand" "n")]
13286 UNSPEC_MOVESI_FROM_CR))])]
13287 "TARGET_MFCRF"
13288 "*
13289 {
13290 int mask = 0;
13291 int i;
13292 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13293 {
13294 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13295 operands[4] = GEN_INT (mask);
13296 output_asm_insn (\"mfcr %1,%4\", operands);
13297 }
13298 return \"\";
13299 }"
13300 [(set_attr "type" "mfcrf")])
13302 (define_insn "movesi_from_cr"
13303 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13304 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13305 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13306 UNSPEC_MOVESI_FROM_CR))]
13307 ""
13308 "mfcr %0"
13309 [(set_attr "type" "mfcr")])
13311 (define_insn "*stmw"
13312 [(match_parallel 0 "stmw_operation"
13313 [(set (match_operand:SI 1 "memory_operand" "=m")
13314 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13315 "TARGET_MULTIPLE"
13316 "{stm|stmw} %2,%1")
13318 (define_insn "*save_fpregs_<mode>"
13319 [(match_parallel 0 "any_parallel_operand"
13320 [(clobber (match_operand:P 1 "register_operand" "=l"))
13321 (use (match_operand:P 2 "call_operand" "s"))
13322 (set (match_operand:DF 3 "memory_operand" "=m")
13323 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13324 ""
13325 "bl %z2"
13326 [(set_attr "type" "branch")
13327 (set_attr "length" "4")])
13329 ; These are to explain that changes to the stack pointer should
13330 ; not be moved over stores to stack memory.
13331 (define_insn "stack_tie"
13332 [(set (match_operand:BLK 0 "memory_operand" "+m")
13333 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
13334 ""
13335 ""
13336 [(set_attr "length" "0")])
13339 (define_expand "epilogue"
13340 [(use (const_int 0))]
13341 "TARGET_SCHED_PROLOG"
13342 "
13343 {
13344 rs6000_emit_epilogue (FALSE);
13345 DONE;
13346 }")
13348 ; On some processors, doing the mtcrf one CC register at a time is
13349 ; faster (like on the 604e). On others, doing them all at once is
13350 ; faster; for instance, on the 601 and 750.
13352 (define_expand "movsi_to_cr_one"
13353 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13354 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13355 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13356 ""
13357 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13359 (define_insn "*movsi_to_cr"
13360 [(match_parallel 0 "mtcrf_operation"
13361 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13362 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13363 (match_operand 3 "immediate_operand" "n")]
13364 UNSPEC_MOVESI_TO_CR))])]
13365 ""
13366 "*
13367 {
13368 int mask = 0;
13369 int i;
13370 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13371 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13372 operands[4] = GEN_INT (mask);
13373 return \"mtcrf %4,%2\";
13374 }"
13375 [(set_attr "type" "mtcr")])
13377 (define_insn "*mtcrfsi"
13378 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13379 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13380 (match_operand 2 "immediate_operand" "n")]
13381 UNSPEC_MOVESI_TO_CR))]
13382 "GET_CODE (operands[0]) == REG
13383 && CR_REGNO_P (REGNO (operands[0]))
13384 && GET_CODE (operands[2]) == CONST_INT
13385 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13386 "mtcrf %R0,%1"
13387 [(set_attr "type" "mtcr")])
13389 ; The load-multiple instructions have similar properties.
13390 ; Note that "load_multiple" is a name known to the machine-independent
13391 ; code that actually corresponds to the powerpc load-string.
13393 (define_insn "*lmw"
13394 [(match_parallel 0 "lmw_operation"
13395 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13396 (match_operand:SI 2 "memory_operand" "m"))])]
13397 "TARGET_MULTIPLE"
13398 "{lm|lmw} %1,%2")
13400 (define_insn "*return_internal_<mode>"
13401 [(return)
13402 (use (match_operand:P 0 "register_operand" "lc"))]
13403 ""
13404 "b%T0"
13405 [(set_attr "type" "jmpreg")])
13407 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13408 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13410 (define_insn "*return_and_restore_fpregs_<mode>"
13411 [(match_parallel 0 "any_parallel_operand"
13412 [(return)
13413 (use (match_operand:P 1 "register_operand" "l"))
13414 (use (match_operand:P 2 "call_operand" "s"))
13415 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13416 (match_operand:DF 4 "memory_operand" "m"))])]
13417 ""
13418 "b %z2")
13420 ; This is used in compiling the unwind routines.
13421 (define_expand "eh_return"
13422 [(use (match_operand 0 "general_operand" ""))]
13423 ""
13424 "
13425 {
13426 if (TARGET_32BIT)
13427 emit_insn (gen_eh_set_lr_si (operands[0]));
13428 else
13429 emit_insn (gen_eh_set_lr_di (operands[0]));
13430 DONE;
13431 }")
13433 ; We can't expand this before we know where the link register is stored.
13434 (define_insn "eh_set_lr_<mode>"
13435 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13436 UNSPECV_EH_RR)
13437 (clobber (match_scratch:P 1 "=&b"))]
13438 ""
13439 "#")
13441 (define_split
13442 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13443 (clobber (match_scratch 1 ""))]
13444 "reload_completed"
13445 [(const_int 0)]
13446 "
13447 {
13448 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13449 DONE;
13450 }")
13452 (define_insn "prefetch"
13453 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13454 (match_operand:SI 1 "const_int_operand" "n")
13455 (match_operand:SI 2 "const_int_operand" "n"))]
13456 "TARGET_POWERPC"
13457 "*
13458 {
13459 if (GET_CODE (operands[0]) == REG)
13460 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13461 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13462 }"
13463 [(set_attr "type" "load")])
13464 \f
13466 (include "sync.md")
13467 (include "altivec.md")
13468 (include "spe.md")