| blob | ce0702edecb0038b3ca56e0e62b4bfba963ca316 |
1 /* Subroutines for insn-output.cc for Renesas H8/300.
2 Copyright (C) 1992-2022 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
54 /* This file should be included last. */
57 /* Classifies a h8300_src_operand or h8300_dst_operand.
59 H8OP_IMMEDIATE
60 A constant operand of some sort.
62 H8OP_REGISTER
63 An ordinary register.
65 H8OP_MEM_ABSOLUTE
66 A memory reference with a constant address.
68 H8OP_MEM_BASE
69 A memory reference with a register as its address.
71 H8OP_MEM_COMPLEX
72 Some other kind of memory reference. */
73 enum h8300_operand_class
74 {
75 H8OP_IMMEDIATE,
76 H8OP_REGISTER,
77 H8OP_MEM_ABSOLUTE,
78 H8OP_MEM_BASE,
79 H8OP_MEM_COMPLEX,
80 NUM_H8OPS
81 };
83 /* For a general two-operand instruction, element [X][Y] gives
84 the length of the opcode fields when the first operand has class
85 (X + 1) and the second has class Y. */
88 /* Forward declarations. */
125 /* CPU_TYPE, says what cpu we're compiling for. */
128 /* True if a #pragma interrupt has been seen for the current function. */
131 /* True if a #pragma saveall has been seen for the current function. */
143 /* Points to one of the above. */
144 /* ??? The above could be put in an array indexed by CPU_TYPE. */
147 /* Various operations needed by the following, indexed by CPU_TYPE. */
151 /* Value of MOVE_RATIO. */
153 \f
154 /* See below where shifts are handled for explanation of this enum. */
156 enum shift_alg
157 {
158 SHIFT_INLINE,
159 SHIFT_ROT_AND,
160 SHIFT_SPECIAL,
161 SHIFT_LOOP
162 };
164 /* Symbols of the various shifts which can be used as indices. */
166 enum shift_type
167 {
169 };
171 /* Macros to keep the shift algorithm tables small. */
172 #define INL SHIFT_INLINE
173 #define ROT SHIFT_ROT_AND
174 #define LOP SHIFT_LOOP
175 #define SPC SHIFT_SPECIAL
177 /* The shift algorithms for each machine, mode, shift type, and shift
178 count are defined below. The three tables below correspond to
179 QImode, HImode, and SImode, respectively. Each table is organized
180 by, in the order of indices, machine, shift type, and shift count. */
183 {
184 /* TARGET_H8300H */
185 /* 0 1 2 3 4 5 6 7 */
189 },
190 {
191 /* TARGET_H8300S */
192 /* 0 1 2 3 4 5 6 7 */
196 }
197 };
200 {
201 /* TARGET_H8300H */
202 /* 0 1 2 3 4 5 6 7 */
203 /* 8 9 10 11 12 13 14 15 */
210 },
211 {
212 /* TARGET_H8300S */
213 /* 0 1 2 3 4 5 6 7 */
214 /* 8 9 10 11 12 13 14 15 */
221 }
222 };
225 {
226 /* TARGET_H8300H */
227 /* 0 1 2 3 4 5 6 7 */
228 /* 8 9 10 11 12 13 14 15 */
229 /* 16 17 18 19 20 21 22 23 */
230 /* 24 25 26 27 28 29 30 31 */
243 },
244 {
245 /* TARGET_H8300S */
246 /* 0 1 2 3 4 5 6 7 */
247 /* 8 9 10 11 12 13 14 15 */
248 /* 16 17 18 19 20 21 22 23 */
249 /* 24 25 26 27 28 29 30 31 */
262 }
263 };
265 #undef INL
266 #undef ROT
267 #undef LOP
268 #undef SPC
270 enum h8_cpu
271 {
272 H8_300H,
273 H8_S
274 };
276 /* Initialize various cpu specific globals at start up. */
278 static void
280 {
285 /* For this we treat the H8/300H and H8S the same. */
292 /* If we're compiling for the H8/S, then turn off H8/300H. */
297 {
300 }
303 {
306 }
309 {
312 }
315 {
318 }
320 #ifdef H8300_LINUX
322 {
325 }
326 #endif
328 /* Some of the shifts are optimized for speed by default.
329 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
330 If optimizing for size, change shift_alg for those shift to
331 SHIFT_LOOP. */
333 {
334 /* H8/300H */
379 /* H8S */
411 }
413 /* Work out a value for MOVE_RATIO. */
415 {
416 /* Memory-memory moves are quite expensive without the
417 h8sx instructions. */
419 }
421 {
422 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
423 sometimes be as short as two individual memory-to-memory moves,
424 but since they use all the call-saved registers, it seems better
425 to allow up to three moves here. */
427 }
429 {
430 /* In this case we don't use movmd sequences since they tend
431 to be longer than calls to memcpy(). Memory-to-memory
432 moves are cheaper than for !TARGET_H8300SX, so it makes
433 sense to have a slightly higher threshold. */
435 }
436 else
437 {
438 /* We use movmd sequences for some moves since it can be quicker
439 than calling memcpy(). The sequences will need to save and
440 restore er6 though, so bump up the cost. */
442 }
444 /* This target defaults to strict volatile bitfields. */
447 }
449 /* Return the byte register name for a register rtx X. B should be 0
450 if you want a lower byte register. B should be 1 if you want an
451 upper byte register. */
455 {
459 };
464 }
466 /* REGNO must be saved/restored across calls if this macro is true. */
468 #define WORD_REG_USED(regno) \
469 (regno < SP_REG \
471 && ! TREE_THIS_VOLATILE (current_function_decl) \
472 && (h8300_saveall_function_p (current_function_decl) \
474 || (df_regs_ever_live_p (regno) \
475 && !call_used_or_fixed_reg_p (regno)) \
477 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
479 || (h8300_current_function_interrupt_function_p () \
480 && df_regs_ever_live_p (regno)) \
481 /* Save call clobbered registers in non-leaf interrupt \
483 || (h8300_current_function_interrupt_function_p () \
484 && call_used_or_fixed_reg_p (regno) \
485 && !crtl->is_leaf)))
487 /* We use this to wrap all emitted insns in the prologue. */
490 {
494 }
496 /* Mark all the subexpressions of the PARALLEL rtx PAR as
497 frame-related. Return PAR.
499 dwarf2out.cc:dwarf2out_frame_debug_expr ignores sub-expressions of a
500 PARALLEL rtx other than the first if they do not have the
501 FRAME_RELATED flag set on them. */
502 static rtx
504 {
512 }
514 /* Output assembly language to FILE for the operation OP with operand size
515 SIZE to adjust the stack pointer. */
517 static void
519 {
520 /* If the frame size is 0, we don't have anything to do. */
524 /* The stack adjustment made here is further optimized by the
525 splitter. In case of H8/300, the splitter always splits the
526 addition emitted here to make the adjustment interrupt-safe.
527 FIXME: We don't always tag those, because we don't know what
528 the splitter will do. */
530 {
532 stack_pointer_rtx,
536 }
537 else
540 }
542 /* Round up frame size SIZE. */
544 static HOST_WIDE_INT
546 {
549 }
551 /* Compute which registers to push/pop.
552 Return a bit vector of registers. */
554 static unsigned int
556 {
560 /* Construct a bit vector of registers to be pushed/popped. */
562 {
565 }
567 /* Don't push/pop the frame pointer as it is treated separately. */
572 }
574 /* Emit an insn to push register RN. */
576 static rtx
578 {
580 rtx x;
584 else
589 }
591 /* Emit an insn to pop register RN. */
593 static rtx
595 {
597 rtx x;
601 else
606 }
608 /* Emit an instruction to push or pop NREGS consecutive registers
609 starting at register REGNO. POP_P selects a pop rather than a
610 push and RETURN_P is true if the instruction should return.
612 It must be possible to do the requested operation in a single
613 instruction. If NREGS == 1 && !RETURN_P, use a normal push
614 or pop insn. Otherwise emit a parallel of the form:
616 (parallel
617 [(return) ;; if RETURN_P
618 (save or restore REGNO)
619 (save or restore REGNO + 1)
620 ...
621 (save or restore REGNO + NREGS - 1)
622 (set sp (plus sp (const_int adjust)))] */
624 static void
626 {
628 rtvec vec;
631 /* See whether we can use a simple push or pop. */
633 {
636 else
639 }
641 /* We need one element for the return insn, if present, one for each
642 register, and one for stack adjustment. */
647 /* Add the return instruction. */
649 {
651 i++;
652 }
654 /* Add the register moves. */
656 {
660 {
661 /* Register REGNO + NREGS - 1 is popped first. Before the
662 stack adjustment, its slot is at address @sp. */
666 }
667 else
668 {
669 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
672 }
674 }
676 /* Add the stack adjustment. */
686 else
688 }
690 /* Return true if X has the value sp + OFFSET. */
692 static int
694 {
702 }
704 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
705 something that may be an ldm or stm instruction. If it fits
706 the required template, return the register it loads or stores,
707 otherwise return -1.
709 LOAD_P is true if X should be a load, false if it should be a store.
710 NREGS is the number of registers that the whole instruction is expected
711 to load or store. INDEX is the index of the register that X should
712 load or store, relative to the lowest-numbered register. */
714 static int
716 {
721 else
731 }
733 /* Return true if the elements of VEC starting at FIRST describe an
734 ldm or stm instruction (LOAD_P says which). */
736 int
738 {
739 rtx last;
742 /* There must be a stack adjustment, a register move, and at least one
743 other operation (a return or another register move). */
747 /* Get the range of registers to be pushed or popped. */
751 /* Check that the call to h8300_ldm_stm_regno succeeded and
752 that we're only dealing with GPRs. */
756 /* 2-register h8s instructions must start with an even-numbered register.
757 3- and 4-register instructions must start with er0 or er4. */
759 {
764 }
766 /* Check the other loads or stores. */
772 /* Check the stack adjustment. */
778 }
780 /* This is what the stack looks like after the prolog of
781 a function with a frame has been set up:
783 <args>
784 PC
785 FP <- fp
786 <locals>
787 <saved registers> <- sp
789 This is what the stack looks like after the prolog of
790 a function which doesn't have a frame:
792 <args>
793 PC
794 <locals>
795 <saved registers> <- sp
796 */
798 /* Generate RTL code for the function prologue. */
800 void
802 {
807 /* If the current function has the OS_Task attribute set, then
808 we have a naked prologue. */
813 /* The monitor function act as normal functions, which means it
814 can accept parameters and return values. In addition to this,
815 interrupts are masked in prologue and return with "rte" in epilogue. */
819 {
820 /* Push fp. */
823 }
825 /* Push the rest of the registers in ascending order. */
828 {
831 {
833 {
834 /* See how many registers we can push at the same time. */
846 }
849 }
850 }
852 /* Leave room for locals. */
856 current_function_static_stack_size
860 }
862 /* Return nonzero if we can use "rts" for the function currently being
863 compiled. */
865 int
867 {
869 && !frame_pointer_needed
872 }
874 /* Generate RTL code for the function epilogue. */
876 void
878 {
882 HOST_WIDE_INT frame_size;
886 /* OS_Task epilogues are nearly naked -- they just have an
887 rts instruction. */
893 /* Deallocate locals. */
896 /* Pop the saved registers in descending order. */
899 {
902 {
904 {
905 /* See how many registers we can pop at the same time. */
917 }
919 /* See if this pop would be the last insn before the return.
920 If so, use rte/l or rts/l instead of pop or ldm.l. */
922 && !sibcall_p
923 && !frame_pointer_needed
929 }
930 }
932 /* Pop frame pointer if we had one. */
934 {
938 }
942 }
944 /* Return nonzero if the current function is an interrupt
945 function. */
947 int
949 {
951 }
953 int
955 {
957 }
959 /* Output assembly code for the start of the file. */
961 static void
963 {
972 }
974 /* Output assembly language code for the end of file. */
976 static void
978 {
980 }
981 \f
982 /* Split an add of a small constant into two adds/subs insns.
984 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
985 instead of adds/subs. */
987 void
989 {
993 HOST_WIDE_INT amount;
996 /* Force VAL to be positive so that we do not have to consider the
997 sign. */
999 {
1002 }
1005 {
1016 }
1018 /* Try different amounts in descending order. */
1020 {
1023 }
1026 }
1028 /* Handle machine specific pragmas for compatibility with existing
1029 compilers for the H8/300.
1031 pragma saveall generates prologue/epilogue code which saves and
1032 restores all the registers on function entry.
1034 pragma interrupt saves and restores all registers, and exits with
1035 an rte instruction rather than an rts. A pointer to a function
1036 with this attribute may be safely used in an interrupt vector. */
1038 void
1040 {
1042 }
1044 void
1046 {
1048 }
1050 /* If the next function argument ARG is to be passed in a register, return
1051 a reg RTX for the hard register in which to pass the argument. CUM
1052 represents the state after the last argument. If the argument is to
1053 be pushed, NULL_RTX is returned.
1055 On the H8/300 all normal args are pushed, unless -mquickcall in which
1056 case the first 3 arguments are passed in registers. */
1058 static rtx
1060 {
1080 };
1086 /* Never pass unnamed arguments in registers. */
1090 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1094 /* If calling hand written assembler, use 4 regs of args. */
1096 {
1101 /* See if this libcall is one of the hand coded ones. */
1103 ;
1107 }
1110 {
1115 }
1118 }
1120 /* Update the data in CUM to advance over argument ARG. */
1122 static void
1125 {
1130 }
1132 \f
1133 /* Implements TARGET_REGISTER_MOVE_COST.
1135 Any SI register-to-register move may need to be reloaded,
1136 so inmplement h8300_register_move_cost to return > 2 so that reload never
1137 shortcuts. */
1139 static int
1142 {
1145 else
1147 }
1149 /* Compute the cost of an and insn. */
1151 static int
1153 {
1168 }
1170 /* Compute the cost of a shift insn. */
1172 static int
1174 {
1186 }
1188 /* Worker function for TARGET_RTX_COSTS. */
1190 static bool
1193 {
1197 {
1198 /* Estimate the number of execution states needed to calculate
1199 the address. */
1205 else
1208 }
1211 {
1213 {
1217 {
1218 /* Constant operands need the same number of processor
1219 states as register operands. Although we could try to
1220 use a size-based cost for !speed, the lack of
1221 of a mode makes the results very unpredictable. */
1224 }
1226 {
1228 {
1242 }
1243 }
1246 }
1252 {
1253 /* See comment for CONST_INT. */
1256 }
1286 /* We say that MOD and DIV are so expensive because otherwise we'll
1287 generate some really horrible code for division of a power of two. */
1294 {
1306 }
1313 {
1325 }
1333 {
1336 }
1338 {
1341 }
1349 else
1356 }
1357 }
1358 \f
1359 /* Documentation for the machine specific operand escapes:
1361 'E' like s but negative.
1362 'F' like t but negative.
1363 'G' constant just the negative
1364 'R' print operand as a byte:8 address if appropriate, else fall back to
1365 'X' handling.
1366 'S' print operand as a long word
1367 'T' print operand as a word
1368 'V' find the set bit, and print its number.
1369 'W' find the clear bit, and print its number.
1370 'X' print operand as a byte
1371 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1372 If this operand isn't a register, fall back to 'R' handling.
1373 'Z' print int & 7.
1374 'c' print the opcode corresponding to rtl
1375 'e' first word of 32-bit value - if reg, then least reg. if mem
1376 then least. if const then most sig word
1377 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1378 then +2. if const then least sig word
1379 'j' print operand as condition code.
1380 'k' print operand as reverse condition code.
1381 'm' convert an integer operand to a size suffix (.b, .w or .l)
1382 'o' print an integer without a leading '#'
1383 's' print as low byte of 16-bit value
1384 't' print as high byte of 16-bit value
1385 'w' print as low byte of 32-bit value
1386 'x' print as 2nd byte of 32-bit value
1387 'y' print as 3rd byte of 32-bit value
1388 'z' print as msb of 32-bit value
1389 */
1391 /* Return assembly language string which identifies a comparison type. */
1395 {
1397 {
1420 }
1421 }
1423 /* Print operand X using operand code CODE to assembly language output file
1424 FILE. */
1426 static void
1428 {
1429 /* This is used for communication between codes V,W,Z and Y. */
1433 {
1437 else
1442 {
1451 }
1455 {
1464 }
1473 else
1479 else
1486 else
1495 else
1504 else
1511 else
1521 {
1533 }
1537 {
1548 {
1553 }
1557 }
1561 {
1573 {
1578 }
1581 }
1588 else
1596 else
1602 {
1617 }
1627 else
1635 else
1643 else
1651 else
1659 else
1667 else
1672 def:
1674 {
1677 {
1683 #endif
1694 }
1698 {
1704 /* Add a length suffix to constant addresses. Although this
1705 is often unnecessary, it helps to avoid ambiguity in the
1706 syntax of mova. If we wrote an insn like:
1708 mova/w.l @(1,@foo.b),er0
1710 then .b would be considered part of the symbol name.
1711 Adding a length after foo will avoid this. */
1714 {
1716 /* Used for mov.b and bit operations. */
1718 {
1721 }
1723 /* FALLTHRU */
1725 /* We should not get here if we are processing bit
1726 operations on H8/300 or H8/300H because 'U'
1727 constraint does not allow bit operations on the
1728 tiny area on these machines. */
1735 else
1740 }
1741 }
1752 {
1757 }
1760 }
1761 }
1762 }
1764 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1766 static bool
1768 {
1770 }
1772 /* Output assembly language output for the address ADDR to FILE. */
1774 static void
1776 {
1777 rtx index;
1781 {
1807 {
1808 /* reg,foo */
1812 {
1831 }
1832 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1833 }
1834 else
1835 {
1836 /* foo+k */
1840 }
1845 {
1849 }
1854 }
1855 }
1856 \f
1857 /* Output all insn addresses and their sizes into the assembly language
1858 output file. This is helpful for debugging whether the length attributes
1859 in the md file are correct. This is not meant to be a user selectable
1860 option. */
1862 void
1865 {
1866 /* This holds the last insn address. */
1872 {
1876 }
1877 }
1879 /* Prepare for an SI sized move. */
1881 int
1883 {
1887 {
1889 {
1893 }
1894 }
1896 }
1898 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1899 Frame pointer elimination is automatically handled.
1901 For the h8300, if frame pointer elimination is being done, we would like to
1902 convert ap and rp into sp, not fp.
1904 All other eliminations are valid. */
1906 static bool
1908 {
1910 }
1912 /* Conditionally modify register usage based on target flags. */
1914 static void
1916 {
1919 }
1921 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1922 Define the offset between two registers, one to be eliminated, and
1923 the other its replacement, at the start of a routine. */
1925 int
1927 {
1928 /* The number of bytes that the return address takes on the stack. */
1931 /* The number of bytes that the saved frame pointer takes on the stack. */
1934 /* The number of bytes that the saved registers, excluding the frame
1935 pointer, take on the stack. */
1938 /* The number of bytes that the locals takes on the stack. */
1947 /* Adjust saved_regs_size because the above loop took the frame
1948 pointer int account. */
1952 {
1955 {
1964 }
1968 {
1977 }
1981 }
1983 }
1985 /* Worker function for RETURN_ADDR_RTX. */
1987 rtx
1989 {
1990 rtx ret;
1997 else
2001 UNITS_PER_WORD)));
2004 }
2007 machine_mode
2009 {
2023 }
2025 \f
2026 /* Given that X occurs in an address of the form (plus X constant),
2027 return the part of X that is expected to be a register. There are
2028 four kinds of addressing mode to recognize:
2030 @(dd,Rn)
2031 @(dd,RnL.b)
2032 @(dd,Rn.w)
2033 @(dd,ERn.l)
2035 If SIZE is nonnull, and the address is one of the last three forms,
2036 set *SIZE to the index multiplication factor. Set it to 0 for
2037 plain @(dd,Rn) addresses.
2039 MODE is the mode of the value being accessed. It can be VOIDmode
2040 if the address is known to be valid, but its mode is unknown. */
2042 static rtx
2044 {
2056 {
2058 {
2059 /* When accessing byte-sized values, the index can be
2060 a zero-extended QImode or HImode register. */
2063 }
2064 else
2065 {
2066 /* We're looking for addresses of the form:
2068 (mult X I)
2069 or (mult (zero_extend X) I)
2071 where I is the size of the operand being accessed.
2072 The canonical form of the second expression is:
2074 (and (mult (subreg X) I) J)
2076 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2077 rtx index;
2084 {
2087 }
2088 else
2089 {
2092 }
2098 }
2099 }
2102 }
2103 \f
2104 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2106 On the H8/300, the predecrement and postincrement address depend thus
2107 (the amount of decrement or increment being the length of the operand). */
2109 static bool
2111 addr_space_t as ATTRIBUTE_UNUSED)
2112 {
2118 }
2119 \f
2121 {
2122 /* #xx Rs @aa @Rs @xx */
2127 };
2130 {
2131 /* #xx Rs @aa @Rs @xx */
2136 };
2139 {
2140 /* #xx Rs @aa @Rs @xx */
2145 };
2147 #define logicb_length_table addb_length_table
2148 #define logicw_length_table addw_length_table
2151 {
2152 /* #xx Rs @aa @Rs @xx */
2157 };
2160 {
2161 /* #xx Rs @aa @Rs @xx */
2166 };
2168 #define movw_length_table movb_length_table
2171 {
2172 /* #xx Rs @aa @Rs @xx */
2177 };
2179 /* Return the size of the given address or displacement constant. */
2181 static unsigned int
2183 {
2184 /* Check for (@d:16,Reg). */
2189 /* Check for (@d:16,Reg) in cases where the displacement is
2190 an absolute address. */
2195 }
2197 /* Return the size of a displacement field in address ADDR, which should
2198 have the form (plus X constant). SIZE is the number of bytes being
2199 accessed. */
2201 static unsigned int
2203 {
2204 rtx offset;
2208 /* Check for @(d:2,Reg). */
2217 }
2219 /* Store the class of operand OP in *OPCLASS and return the length of any
2220 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2221 can be null if only the length is needed. */
2223 static unsigned int
2225 {
2232 {
2235 /* Byte-sized immediates are stored in the opcode fields. */
2239 /* If this is a 32-bit instruction, see whether the constant
2240 will fit into a 16-bit immediate field. */
2248 }
2250 {
2253 {
2256 }
2258 {
2261 }
2263 {
2266 }
2268 {
2271 }
2272 }
2276 }
2278 /* Return the length of the instruction described by TABLE given that
2279 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2280 and OP2 must be an h8300_src_operand. */
2282 static unsigned int
2284 {
2292 }
2294 /* Return the length of a unary instruction such as neg or not given that
2295 its operand is OP. */
2297 unsigned int
2299 {
2306 {
2321 }
2322 }
2324 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2326 static unsigned int
2328 {
2336 {
2347 }
2348 }
2350 /* Likewise bitfield load and store instructions. */
2352 static unsigned int
2354 {
2366 {
2374 }
2375 }
2377 /* Calculate the length of general binary instruction INSN using TABLE. */
2379 static unsigned int
2381 {
2382 rtx set;
2383 rtx pattern;
2393 else
2400 else
2401 {
2405 table);
2406 }
2407 }
2409 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2410 memory reference and either (1) it has the form @(d:16,Rn) or
2411 (2) its address has the code given by INC_CODE. */
2413 static bool
2415 {
2416 rtx addr;
2431 }
2433 /* Calculate the length of move instruction INSN using the given length
2434 table. Although the tables are correct for most cases, there is some
2435 irregularity in the length of mov.b and mov.w. The following forms:
2437 mov @ERs+, Rd
2438 mov @(d:16,ERs), Rd
2439 mov Rs, @-ERd
2440 mov Rs, @(d:16,ERd)
2442 are two bytes shorter than most other "mov Rs, @complex" or
2443 "mov @complex,Rd" combinations. */
2445 static unsigned int
2447 {
2456 }
2458 /* Return the length of a mova instruction with the given operands.
2459 DEST is the register destination, SRC is the source address and
2460 OFFSET is the 16-bit or 32-bit displacement. */
2462 static unsigned int
2464 {
2473 }
2475 /* Compute the length of INSN based on its length_table attribute.
2476 OPERANDS is the array of its operands. */
2478 unsigned int
2480 {
2482 {
2530 }
2531 }
2533 /* Return true if LHS and RHS are memory references that can be mapped
2534 to the same h8sx assembly operand. LHS appears as the destination of
2535 an instruction and RHS appears as a source.
2537 Three cases are allowed:
2539 - RHS is @+Rn or @-Rn, LHS is @Rn
2540 - RHS is @Rn, LHS is @Rn+ or @Rn-
2541 - RHS and LHS have the same address and neither has side effects. */
2543 bool
2545 {
2547 {
2559 }
2561 }
2563 /* Return true if OPERANDS[1] can be mapped to the same assembly
2564 operand as OPERANDS[0]. */
2566 bool
2568 {
2577 }
2578 \f
2579 /* Return the length of mov instruction. */
2581 unsigned int
2583 {
2584 /* If the mov instruction involves a memory operand, we compute the
2585 length, assuming the largest addressing mode is used, and then
2586 adjust later in the function. Otherwise, we compute and return
2587 the exact length in one step. */
2591 rtx addr;
2597 else
2603 {
2608 /* The eightbit addressing is available only in QImode, so
2609 go ahead and take care of it. */
2618 {
2626 }
2633 {
2635 {
2638 else
2640 }
2643 {
2653 {
2664 }
2665 }
2667 }
2674 {
2682 }
2689 }
2691 /* Adjust the length based on the addressing mode used.
2692 Specifically, we subtract the difference between the actual
2693 length and the longest one, which is @(d:24,ERs). */
2695 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2700 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2704 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2705 longest. */
2713 /* @aa:16 is 4 bytes shorter than the longest. */
2717 /* @aa:24 is 2 bytes shorter than the longest. */
2722 }
2723 \f
2724 /* Output an addition insn. */
2728 {
2735 {
2743 /* See if we can finish with 2 bytes. */
2746 {
2747 /* INC/DEC set the flags, but adds/subs do not. So if we
2748 need flags, use the former and not the latter. */
2752 else
2757 else
2762 else
2767 else
2770 /* These six cases have optimized paths when we do not
2771 need flags. Otherwise we let them fallthru. */
2776 /* FALLTHRU */
2782 /* FALLTHRU */
2787 {
2790 }
2792 /* FALLTHRU */
2797 {
2800 }
2802 /* FALLTHRU */
2804 }
2806 /* See if we can finish with 4 bytes. */
2808 {
2811 }
2812 }
2815 {
2818 }
2820 }
2822 /* ??? It would be much easier to add the h8sx stuff if a single function
2823 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
2824 /* Compute the length of an addition insn. */
2826 unsigned int
2828 {
2835 {
2843 /* See if we can finish with 2 bytes. */
2846 {
2853 else
2862 else
2870 /* FALLTHRU */
2877 /* FALLTHRU */
2879 }
2881 /* See if we can finish with 4 bytes. */
2884 }
2890 else
2893 }
2895 /* Compute which flag bits are valid after an addition insn. */
2897 enum attr_old_cc
2899 {
2906 {
2914 /* See if we can finish with 2 bytes. */
2917 {
2935 }
2937 /* See if we can finish with 4 bytes. */
2940 }
2943 }
2944 \f
2945 /* Output a logical insn. */
2949 {
2950 /* Pretend that every byte is affected if both operands are registers. */
2953 /* Always use the full instruction if the
2954 first operand is in memory. It is better
2955 to use define_splits to generate the shorter
2956 sequence where valid. */
2959 /* The determinant of the algorithm. If we perform an AND, 0
2960 affects a bit. Otherwise, 1 affects a bit. */
2962 /* Break up DET into pieces. */
2969 /* The name of an insn. */
2973 /* INSN is the current insn, we examine its overall form to see if we're
2974 supposed to set or clobber the condition codes.
2976 This is important to know. If we are setting condition codes, then we
2977 must do the operation in MODE and not in some smaller size.
2979 The key is to look at the second object in the PARALLEL. If it is not
2980 a CLOBBER, then we care about the condition codes. */
2987 {
2999 }
3002 {
3008 /* First, see if we can (or must) finish with one insn. */
3011 {
3014 }
3015 else
3016 {
3017 /* Take care of the lower byte. */
3019 {
3022 }
3023 /* Take care of the upper byte. */
3025 {
3028 }
3029 }
3032 /* Determine if the lower half can be taken care of in no more
3033 than two bytes. */
3038 /* Determine if the upper half can be taken care of in no more
3039 than two bytes. */
3043 /* Check if doing everything with one insn is no worse than
3044 using multiple insns. */
3050 {
3053 }
3054 else
3055 {
3056 /* Take care of the lower and upper words individually. For
3057 each word, we try different methods in the order of
3059 1) the special insn (in case of AND or XOR),
3060 2) the word-wise insn, and
3061 3) The byte-wise insn. */
3065 operands);
3067 {
3070 }
3071 else
3072 {
3074 {
3077 }
3079 {
3082 }
3083 }
3088 operands);
3092 {
3094 }
3097 {
3099 }
3100 else
3101 {
3103 {
3106 }
3107 }
3108 }
3112 }
3114 }
3116 /* Compute the length of a logical insn. */
3118 unsigned int
3120 {
3121 /* Pretend that every byte is affected if both operands are registers. */
3124 /* Always use the full instruction if the
3125 first operand is in memory. It is better
3126 to use define_splits to generate the shorter
3127 sequence where valid. */
3130 /* The determinant of the algorithm. If we perform an AND, 0
3131 affects a bit. Otherwise, 1 affects a bit. */
3133 /* Break up DET into pieces. */
3140 /* Insn length. */
3143 /* INSN is the current insn, we examine its overall form to see if we're
3144 supposed to set or clobber the condition codes.
3146 This is important to know. If we are setting condition codes, then we
3147 must do the operation in MODE and not in some smaller size.
3149 The key is to look at the second object in the PARALLEL. If it is not
3150 a CLOBBER, then we care about the condition codes. */
3153 {
3158 }
3161 {
3166 /* First, see if we can finish with one insn. */
3169 {
3172 }
3173 else
3174 {
3175 /* Take care of the lower byte. */
3179 /* Take care of the upper byte. */
3182 }
3185 /* Determine if the lower half can be taken care of in no more
3186 than two bytes. */
3191 /* Determine if the upper half can be taken care of in no more
3192 than two bytes. */
3196 /* Check if doing everything with one insn is no worse than
3197 using multiple insns. */
3203 {
3206 }
3207 else
3208 {
3209 /* Take care of the lower and upper words individually. For
3210 each word, we try different methods in the order of
3212 1) the special insn (in case of AND or XOR),
3213 2) the word-wise insn, and
3214 3) The byte-wise insn. */
3216 {
3218 }
3220 {
3222 }
3223 else
3224 {
3230 }
3233 {
3235 }
3239 {
3241 }
3243 {
3245 }
3246 else
3247 {
3250 }
3251 }
3255 }
3257 }
3259 #if 0
3260 \f
3261 /* Expand a conditional store. */
3263 void
3265 {
3270 rtx tmp;
3277 }
3278 #endif
3279 \f
3280 /* Shifts.
3282 We devote a fair bit of code to getting efficient shifts since we
3283 can only shift one bit at a time on the H8/300 and H8/300H and only
3284 one or two bits at a time on the H8S.
3286 All shift code falls into one of the following ways of
3287 implementation:
3289 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3290 when a straight line shift is about the same size or smaller than
3291 a loop.
3293 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3294 off the bits we don't need. This is used when only a few of the
3295 bits in the original value will survive in the shifted value.
3297 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3298 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3299 shifts can be added if the shift count is slightly more than 8 or
3300 16. This case also includes other oddballs that are not worth
3301 explaining here.
3303 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3305 For each shift count, we try to use code that has no trade-off
3306 between code size and speed whenever possible.
3308 If the trade-off is unavoidable, we try to be reasonable.
3309 Specifically, the fastest version is one instruction longer than
3310 the shortest version, we take the fastest version. We also provide
3311 the use a way to switch back to the shortest version with -Os.
3313 For the details of the shift algorithms for various shift counts,
3314 refer to shift_alg_[qhs]i. */
3316 /* Classify a shift with the given mode and code. OP is the shift amount. */
3318 enum h8sx_shift_type
3320 {
3325 {
3328 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3332 /* Reject out-of-range shift amounts. */
3336 /* Power-of-2 shifts are effectively unary operations. */
3358 }
3359 }
3361 /* Return the asm template for a single h8sx shift instruction.
3362 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3363 is the source and OPERANDS[3] is the shift. SUFFIX is the
3364 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3365 prefix for the destination operand. */
3369 {
3374 {
3390 {
3391 /* This is really a right rotate. */
3395 }
3400 }
3403 else
3406 }
3408 /* Emit code to do shifts. */
3410 bool
3412 {
3414 {
3424 }
3426 /* Need a loop to get all the bits we want - we generate the
3427 code at emit time, but need to allocate a scratch reg now. */
3430 ;
3436 else
3446 }
3448 /* Symbols of the various modes which can be used as indices. */
3450 enum shift_mode
3451 {
3453 };
3455 /* For single bit shift insns, record assembler and what bits of the
3456 condition code are valid afterwards (represented as various OLD_CC_FOO
3457 bits, 0 means CC isn't left in a usable state). */
3459 struct shift_insn
3460 {
3463 };
3465 /* Assembler instruction shift table.
3467 These tables are used to look up the basic shifts.
3468 They are indexed by cpu, shift_type, and mode. */
3471 {
3472 /* H8/300 */
3473 {
3474 /* SHIFT_ASHIFT */
3475 {
3479 },
3480 /* SHIFT_LSHIFTRT */
3481 {
3485 },
3486 /* SHIFT_ASHIFTRT */
3487 {
3491 }
3492 },
3493 /* H8/300H */
3494 {
3495 /* SHIFT_ASHIFT */
3496 {
3500 },
3501 /* SHIFT_LSHIFTRT */
3502 {
3506 },
3507 /* SHIFT_ASHIFTRT */
3508 {
3512 }
3513 }
3514 };
3517 {
3518 /* SHIFT_ASHIFT */
3519 {
3523 },
3524 /* SHIFT_LSHIFTRT */
3525 {
3529 },
3530 /* SHIFT_ASHIFTRT */
3531 {
3535 }
3536 };
3538 /* Rotates are organized by which shift they'll be used in implementing.
3539 There's no need to record whether the cc is valid afterwards because
3540 it is the AND insn that will decide this. */
3543 {
3544 /* H8/300 */
3545 {
3546 /* SHIFT_ASHIFT */
3547 {
3550 0
3551 },
3552 /* SHIFT_LSHIFTRT */
3553 {
3556 0
3557 },
3558 /* SHIFT_ASHIFTRT */
3559 {
3562 0
3563 }
3564 },
3565 /* H8/300H */
3566 {
3567 /* SHIFT_ASHIFT */
3568 {
3572 },
3573 /* SHIFT_LSHIFTRT */
3574 {
3578 },
3579 /* SHIFT_ASHIFTRT */
3580 {
3584 }
3585 }
3586 };
3589 {
3590 /* SHIFT_ASHIFT */
3591 {
3595 },
3596 /* SHIFT_LSHIFTRT */
3597 {
3601 },
3602 /* SHIFT_ASHIFTRT */
3603 {
3607 }
3608 };
3611 /* Shift algorithm. */
3614 /* The number of bits to be shifted by shift1 and shift2. Valid
3615 when ALG is SHIFT_SPECIAL. */
3618 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3621 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3622 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3625 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3626 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3629 /* CC status for SHIFT_INLINE. */
3632 /* CC status for SHIFT_SPECIAL. */
3634 };
3640 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3641 best algorithm for doing the shift. The assembler code is stored
3642 in the pointers in INFO. We achieve the maximum efficiency in most
3643 cases.
3645 We first determine the strategy of the shift algorithm by a table
3646 lookup. If that tells us to use a hand crafted assembly code, we
3647 go into the big switch statement to find what that is. Otherwise,
3648 we resort to a generic way, such as inlining. In either case, the
3649 result is returned through INFO. */
3651 static void
3654 {
3659 else
3662 /* Find the shift algorithm. */
3665 {
3683 }
3685 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
3687 {
3690 /* Fall through. */
3693 /* It is up to the caller to know that looping clobbers cc. */
3706 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3713 }
3715 /* Here we only deal with SHIFT_SPECIAL. */
3717 {
3719 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3720 through the entire value. */
3727 {
3729 {
3739 }
3740 }
3743 {
3747 {
3759 }
3760 }
3762 {
3764 {
3771 {
3772 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3774 }
3778 }
3779 }
3781 {
3783 {
3793 }
3794 }
3799 {
3801 {
3803 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%s3,%t3\n\tmov.b\t%t0,%s3\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f3,%e0";
3806 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%t0,%s0\n\tmov.b\t%s3,%t0\n\tmov.b\t%t3,%s3\n\textu.w\t%f3\n\tmov.w\t%f3,%e0";
3809 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%t0,%s0\n\tmov.b\t%s3,%t0\n\tmov.b\t%t3,%s3\n\texts.w\t%f3\n\tmov.w\t%f3,%e0";
3811 }
3812 }
3814 {
3815 /* The basic idea here is to use the shift-by-16 idiom to make things
3816 small and efficient. Of course, that loses one bit that we need,
3817 so we stuff the bit into C, shift by 16, then rotate the bit
3818 back in. */
3820 {
3833 }
3834 }
3836 {
3840 {
3852 }
3853 }
3855 {
3857 {
3859 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3862 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3869 }
3870 }
3872 {
3876 {
3888 }
3889 }
3891 {
3893 {
3896 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3897 else
3902 {
3903 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3905 }
3906 else
3914 }
3915 }
3917 {
3919 {
3922 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3923 else
3928 {
3931 }
3932 else
3933 {
3936 }
3943 }
3944 }
3946 {
3948 {
3952 else
3958 else
3966 }
3967 }
3969 {
3971 {
3984 }
3985 }
3990 }
3992 end:
3995 }
3997 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3998 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4000 int
4002 {
4009 /* Find out the target CPU. */
4012 else
4015 /* Find the shift algorithm. */
4017 {
4038 }
4040 /* On H8/300H, count == 8 uses a scratch register. */
4054 }
4056 /* Output the assembler code for doing shifts. */
4060 {
4068 loopend_lab++;
4071 {
4083 }
4086 {
4098 }
4100 /* This case must be taken care of by one of the two splitters
4101 that convert a variable shift into a loop. */
4106 /* If the count is negative, make it 0. */
4109 /* If the count is too big, truncate it.
4110 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4111 do the intuitive thing. */
4118 {
4121 /* Fall through. */
4126 /* Emit two bit shifts first. */
4128 {
4131 }
4133 /* Now emit one bit shifts for any residual. */
4139 {
4146 /* Not all possibilities of rotate are supported. They shouldn't
4147 be generated, but let's watch for 'em. */
4150 /* Emit two bit rotates first. */
4152 {
4155 }
4157 /* Now single bit rotates for any residual. */
4161 /* Now mask off the high bits. */
4163 {
4174 }
4178 }
4181 /* A loop to shift by a "large" constant value.
4182 If we have shift-by-2 insns, use them. */
4184 {
4193 }
4194 else
4195 {
4202 }
4207 }
4208 }
4210 /* Count the number of assembly instructions in a string TEMPL. */
4212 static unsigned int
4214 {
4219 count++;
4222 }
4224 /* Compute the length of a shift insn. */
4226 unsigned int
4228 {
4236 {
4248 }
4251 {
4263 }
4266 {
4267 /* Get the assembler code to do one shift. */
4271 }
4272 else
4273 {
4276 /* If the count is negative, make it 0. */
4279 /* If the count is too big, truncate it.
4280 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4281 do the intuitive thing. */
4288 {
4292 /* Every assembly instruction used in SHIFT_SPECIAL case
4293 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4294 see xor.l, we just pretend that xor.l counts as two insns
4295 so that the insn length will be computed correctly. */
4297 wlength++;
4299 /* Fall through. */
4305 {
4308 }
4315 {
4318 /* Not all possibilities of rotate are supported. They shouldn't
4319 be generated, but let's watch for 'em. */
4323 {
4326 }
4330 /* Now mask off the high bits. */
4332 {
4344 }
4346 }
4349 /* A loop to shift by a "large" constant value.
4350 If we have shift-by-2 insns, use them. */
4352 {
4356 }
4357 else
4358 {
4360 }
4365 }
4366 }
4367 }
4369 /* Compute which flag bits are valid after a shift insn. */
4371 int
4373 {
4381 {
4393 }
4396 {
4408 }
4410 /* This case must be taken care of by one of the two splitters
4411 that convert a variable shift into a loop. */
4416 /* If the count is negative, make it 0. */
4419 /* If the count is too big, truncate it.
4420 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4421 do the intuitive thing. */
4428 {
4434 /* Fall through. */
4441 /* This case always ends with an and instruction. */
4445 /* A loop to shift by a "large" constant value.
4446 If we have shift-by-2 insns, use them. */
4448 {
4453 }
4458 }
4459 }
4460 \f
4461 /* A rotation by a non-constant will cause a loop to be generated, in
4462 which a rotation by one bit is used. A rotation by a constant,
4463 including the one in the loop, will be taken care of by
4464 output_a_rotate () at the insn emit time. */
4466 int
4468 {
4477 /* We rotate in place. */
4481 {
4486 /* If the rotate amount is less than or equal to 0,
4487 we go out of the loop. */
4491 /* Initialize the loop counter. */
4496 /* Rotate by one bit. */
4498 {
4510 }
4512 /* Decrement the counter by 1. */
4515 /* If the loop counter is nonzero, we go back to the beginning
4516 of the loop. */
4518 start_label);
4521 }
4522 else
4523 {
4524 /* Rotate by AMOUNT bits. */
4526 {
4538 }
4539 }
4542 }
4544 /* Output a rotate insn. */
4548 {
4561 {
4573 }
4576 {
4585 }
4589 /* Clean up AMOUNT. */
4595 /* Determine the faster direction. After this phase, amount will be
4596 at most a half of GET_MODE_BITSIZE (mode). */
4598 {
4599 /* Flip the direction. */
4601 rotate_type =
4603 }
4605 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4606 boost up the rotation. */
4611 {
4613 {
4615 /* This code works on any family. */
4621 /* This code works on the H8/300H and H8S. */
4628 }
4630 /* Adjust AMOUNT and flip the direction. */
4632 rotate_type =
4634 }
4636 /* Output rotate insns. */
4638 {
4641 else
4646 }
4649 }
4651 /* Compute the length of a rotate insn. */
4653 unsigned int
4655 {
4666 /* Clean up AMOUNT. */
4672 /* Determine the faster direction. After this phase, amount
4673 will be at most a half of GET_MODE_BITSIZE (mode). */
4675 /* Flip the direction. */
4678 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4679 boost up the rotation. */
4684 {
4685 /* Adjust AMOUNT and flip the direction. */
4688 }
4690 /* We use 2-bit rotations on the H8S. */
4694 /* The H8/300 uses three insns to rotate one bit, taking 6
4695 length. */
4699 }
4700 \f
4701 /* Fix the operands of a gen_xxx so that it could become a bit
4702 operating insn. */
4704 int
4706 {
4707 /* The bit_operand predicate accepts any memory during RTL generation, but
4708 only 'U' memory afterwards, so if this is a MEM operand, we must force
4709 it to be valid for 'U' by reloading the address. */
4714 {
4715 /* OK to have a memory dest. */
4718 {
4724 }
4728 {
4734 }
4736 }
4738 /* Dest and src op must be register. */
4741 {
4744 {
4756 }
4758 }
4760 }
4762 /* Return nonzero if FUNC is an interrupt function as specified
4763 by the "interrupt" attribute. */
4765 static int
4767 {
4768 tree a;
4775 }
4777 /* Return nonzero if FUNC is a saveall function as specified by the
4778 "saveall" attribute. */
4780 static int
4782 {
4783 tree a;
4790 }
4792 /* Return nonzero if FUNC is an OS_Task function as specified
4793 by the "OS_Task" attribute. */
4795 static int
4797 {
4798 tree a;
4805 }
4807 /* Return nonzero if FUNC is a monitor function as specified
4808 by the "monitor" attribute. */
4810 static int
4812 {
4813 tree a;
4820 }
4822 /* Return nonzero if FUNC is a function that should be called
4823 through the function vector. */
4825 int
4827 {
4828 tree a;
4835 }
4837 /* Return nonzero if DECL is a variable that's in the eight bit
4838 data area. */
4840 int
4842 {
4843 tree a;
4850 }
4852 /* Return nonzero if DECL is a variable that's in the tiny
4853 data area. */
4855 int
4857 {
4858 tree a;
4865 }
4867 /* Generate an 'interrupt_handler' attribute for decls. We convert
4868 all the pragmas to corresponding attributes. */
4870 static void
4872 {
4874 {
4876 {
4879 /* Add an 'interrupt_handler' attribute. */
4882 }
4885 {
4888 /* Add an 'saveall' attribute. */
4891 }
4892 }
4893 }
4895 /* Supported attributes:
4897 interrupt_handler: output a prologue and epilogue suitable for an
4898 interrupt handler.
4900 saveall: output a prologue and epilogue that saves and restores
4901 all registers except the stack pointer.
4903 function_vector: This function should be called through the
4904 function vector.
4906 eightbit_data: This variable lives in the 8-bit data area and can
4907 be referenced with 8-bit absolute memory addresses.
4909 tiny_data: This variable lives in the tiny data area and can be
4910 referenced with 16-bit absolute memory references. */
4913 {
4914 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
4915 affects_type_identity, handler, exclude } */
4931 };
4934 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4935 struct attribute_spec.handler. */
4936 static tree
4938 tree args ATTRIBUTE_UNUSED,
4941 {
4943 {
4945 name);
4947 }
4950 }
4952 /* Handle an "eightbit_data" attribute; arguments as in
4953 struct attribute_spec.handler. */
4954 static tree
4956 tree args ATTRIBUTE_UNUSED,
4959 {
4963 {
4965 }
4966 else
4967 {
4969 name);
4971 }
4974 }
4976 /* Handle an "tiny_data" attribute; arguments as in
4977 struct attribute_spec.handler. */
4978 static tree
4980 tree args ATTRIBUTE_UNUSED,
4983 {
4987 {
4989 }
4990 else
4991 {
4993 name);
4995 }
4998 }
5000 /* Mark function vectors, and various small data objects. */
5002 static void
5004 {
5014 {
5019 }
5023 }
5025 /* Output a single-bit extraction. */
5029 {
5030 /* Determine if we can clear the destination first. */
5037 /* Output the bit load or bit inverse load. */
5040 else
5046 /* Perform the bit store. */
5049 /* All done. */
5051 }
5053 /* Delayed-branch scheduling is more effective if we have some idea
5054 how long each instruction will be. Use a shorten_branches pass
5055 to get an initial estimate. */
5057 static void
5059 {
5062 }
5064 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5065 which is a special case of the 'R' operand. */
5067 int
5069 {
5070 /* The ranges of the 8-bit area. */
5080 /* We accept symbols declared with eightbit_data. */
5099 }
5101 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5102 on H8/300H and H8S. */
5104 int
5106 {
5107 /* The ranges of the 16-bit area. */
5120 {
5122 /* In the normal mode, any symbol fits in the 16-bit absolute
5123 address range. We also accept symbols declared with
5124 tiny_data. */
5131 || (TARGET_H8300H
5133 || (TARGET_H8300S
5141 }
5143 }
5145 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5146 locations that can be accessed as a 16-bit word. */
5148 int
5150 {
5155 {
5158 }
5162 {
5165 }
5166 else
5170 {
5173 }
5177 {
5180 }
5181 else
5191 }
5193 /* Return nonzero if we have the same comparison insn as I3 two insns
5194 before I3. I3 is assumed to be a comparison insn. */
5196 int
5198 {
5201 /* Make sure we have a sequence of three insns. */
5211 }
5213 /* Return nonzero if we have the same comparison insn as I1 two insns
5214 after I1. I1 is assumed to be a comparison insn. */
5216 int
5218 {
5221 /* Make sure we have a sequence of three insns. */
5231 }
5233 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5234 (or pops) N registers. OPERANDS are assumed to be an array of
5235 registers. */
5237 int
5239 {
5241 {
5261 }
5262 }
5264 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5266 int
5269 {
5270 /* Interrupt functions can only use registers that have already been
5271 saved by the prologue, even if they would normally be
5272 call-clobbered. */
5279 }
5281 /* Returns true if register REGNO is safe to be allocated as a scratch
5282 register in the current function. */
5284 static bool
5286 {
5292 }
5295 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5297 static int
5299 {
5300 /* Strip off SUBREG if any. */
5305 && (strict
5308 }
5310 /* Return nozero if X is a legitimate address. On the H8/300, a
5311 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5312 CONSTANT_ADDRESS. */
5314 static bool
5316 {
5317 /* The register indirect addresses like @er0 is always valid. */
5339 }
5341 /* Implement TARGET_HARD_REGNO_MODE_OK. */
5343 static bool
5345 {
5346 /* MAC register can only be of SImode. Otherwise, anything
5347 goes. */
5349 }
5351 /* Implement TARGET_MODES_TIEABLE_P. */
5353 static bool
5355 {
5363 }
5365 /* Helper function for the move patterns. Make sure a move is legitimate. */
5367 bool
5369 {
5372 /* Validate that at least one operand is a register. */
5374 {
5379 }
5381 {
5384 }
5385 else
5388 /* Validate that auto-inc doesn't affect OTHER. */
5395 else
5397 }
5398 \f
5399 /* Perform target dependent optabs initialization. */
5400 static void
5402 {
5408 }
5409 \f
5410 /* Worker function for TARGET_FUNCTION_VALUE.
5412 On the H8 the return value is in R0/R1. */
5414 static rtx
5416 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5418 {
5420 }
5422 /* Worker function for TARGET_LIBCALL_VALUE.
5424 On the H8 the return value is in R0/R1. */
5426 static rtx
5428 {
5430 }
5432 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5434 On the H8, R0 is the only register thus used. */
5436 static bool
5438 {
5440 }
5442 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5444 static bool
5446 {
5449 }
5450 \f
5451 /* We emit the entire trampoline here. Depending on the pointer size,
5452 we use a different trampoline.
5454 Pmode == HImode
5455 vvvv context
5456 1 0000 7903xxxx mov.w #0x1234,r3
5457 2 0004 5A00xxxx jmp @0x1234
5458 ^^^^ function
5460 Pmode == SImode
5461 vvvvvvvv context
5462 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5463 3 0006 5Axxxxxx jmp @0x123456
5464 ^^^^^^ function
5465 */
5467 static void
5469 {
5471 rtx mem;
5474 {
5483 }
5484 else
5485 {
5486 rtx tem;
5498 }
5499 }
5501 /* Implement PUSH_ROUNDING.
5503 On the H8/300, @-sp really pushes a byte if you ask it to - but that's
5504 dangerous, so we claim that it always pushes a word, then we catch
5505 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output.
5507 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4
5508 and doing a similar thing. */
5510 poly_int64
5512 {
5514 }
5516 static bool
5518 {
5519 /* If either the caller or target are special, then assume sibling
5520 calls are not OK. */
5533 }
5535 /* Return TRUE if OP is a PRE_INC or PRE_DEC
5536 instruction using REG, FALSE otherwise. */
5538 bool
5540 {
5541 /* OP must be a MEM. */
5545 /* The address must be a PRE_INC or PRE_DEC. */
5550 /* It must be a register that is being incremented
5551 or decremented. */
5556 /* Finally, check that the register number matches. */
5558 }
5560 \f
5561 /* Initialize the GCC target structure. */
5562 #undef TARGET_ATTRIBUTE_TABLE
5563 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5565 #undef TARGET_ASM_ALIGNED_HI_OP
5568 #undef TARGET_ASM_FILE_START
5569 #define TARGET_ASM_FILE_START h8300_file_start
5570 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5571 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5573 #undef TARGET_ASM_FILE_END
5574 #define TARGET_ASM_FILE_END h8300_file_end
5576 #undef TARGET_PRINT_OPERAND
5577 #define TARGET_PRINT_OPERAND h8300_print_operand
5578 #undef TARGET_PRINT_OPERAND_ADDRESS
5579 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
5580 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
5581 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
5583 #undef TARGET_ENCODE_SECTION_INFO
5584 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5586 #undef TARGET_INSERT_ATTRIBUTES
5587 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5589 #undef TARGET_REGISTER_MOVE_COST
5590 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
5592 #undef TARGET_RTX_COSTS
5593 #define TARGET_RTX_COSTS h8300_rtx_costs
5595 #undef TARGET_INIT_LIBFUNCS
5596 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5598 #undef TARGET_FUNCTION_VALUE
5599 #define TARGET_FUNCTION_VALUE h8300_function_value
5601 #undef TARGET_LIBCALL_VALUE
5602 #define TARGET_LIBCALL_VALUE h8300_libcall_value
5604 #undef TARGET_FUNCTION_VALUE_REGNO_P
5605 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
5607 #undef TARGET_RETURN_IN_MEMORY
5608 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5610 #undef TARGET_FUNCTION_ARG
5611 #define TARGET_FUNCTION_ARG h8300_function_arg
5613 #undef TARGET_FUNCTION_ARG_ADVANCE
5614 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
5616 #undef TARGET_MACHINE_DEPENDENT_REORG
5617 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5619 #undef TARGET_HARD_REGNO_SCRATCH_OK
5620 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5622 #undef TARGET_HARD_REGNO_MODE_OK
5623 #define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
5625 #undef TARGET_MODES_TIEABLE_P
5626 #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p
5628 #undef TARGET_LRA_P
5629 #define TARGET_LRA_P hook_bool_void_false
5631 #undef TARGET_LEGITIMATE_ADDRESS_P
5632 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5634 #undef TARGET_CAN_ELIMINATE
5635 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5637 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5638 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
5640 #undef TARGET_TRAMPOLINE_INIT
5641 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5643 #undef TARGET_OPTION_OVERRIDE
5644 #define TARGET_OPTION_OVERRIDE h8300_option_override
5646 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
5647 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
5649 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
5650 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
5652 #undef TARGET_FLAGS_REGNUM
5653 #define TARGET_FLAGS_REGNUM 12
5655 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5656 #define TARGET_FUNCTION_OK_FOR_SIBCALL h8300_ok_for_sibcall_p