1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn
) >= new_insn_uid_start
273 && curr_insn_set
!= NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set
))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
276 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
282 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
283 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
284 lra_no_alloc_regs
)));
287 common_class
= ira_reg_class_subset
[rclass
][cl
];
288 if (new_class
!= NULL
)
289 *new_class
= common_class
;
290 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
293 /* Check that there are enough allocatable regs. */
294 class_size
= ira_class_hard_regs_num
[common_class
];
295 for (i
= 0; i
< class_size
; i
++)
297 hard_regno
= ira_class_hard_regs
[common_class
][i
];
298 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
301 for (j
= 0; j
< nregs
; j
++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
303 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno
) == NO_REGS
;
320 /* Initiate equivalences for LRA. As we keep original equivalences
321 before any elimination, we need to make copies otherwise any change
322 in insns might change the equivalences. */
324 lra_init_equiv (void)
326 ira_expand_reg_equiv ();
327 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
331 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
332 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
333 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
334 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
338 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
340 /* Update equivalence for REGNO. We need to this as the equivalence
341 might contain other pseudos which are changed by their
344 update_equiv (int regno
)
348 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
349 ira_reg_equiv
[regno
].memory
350 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
352 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
353 ira_reg_equiv
[regno
].invariant
354 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
358 /* If we have decided to substitute X with another value, return that
359 value, otherwise return X. */
366 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
367 || ! ira_reg_equiv
[regno
].defined_p
368 || ! ira_reg_equiv
[regno
].profitable_p
369 || lra_get_regno_hard_regno (regno
) >= 0)
371 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
373 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
375 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
380 /* If we have decided to substitute X with the equivalent value,
381 return that value after elimination for INSN, otherwise return
384 get_equiv_with_elimination (rtx x
, rtx insn
)
386 rtx res
= get_equiv (x
);
388 if (x
== res
|| CONSTANT_P (res
))
390 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
393 /* Set up curr_operand_mode. */
395 init_curr_operand_mode (void)
397 int nop
= curr_static_id
->n_operands
;
398 for (int i
= 0; i
< nop
; i
++)
400 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
401 if (mode
== VOIDmode
)
403 /* The .md mode for address operands is the mode of the
404 addressed value rather than the mode of the address itself. */
405 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
408 mode
= curr_static_id
->operand
[i
].mode
;
410 curr_operand_mode
[i
] = mode
;
416 /* The page contains code to reuse input reloads. */
418 /* Structure describes input reload of the current insns. */
421 /* Reloaded value. */
423 /* Reload pseudo used. */
427 /* The number of elements in the following array. */
428 static int curr_insn_input_reloads_num
;
429 /* Array containing info about input reloads. It is used to find the
430 same input reload and reuse the reload pseudo in this case. */
431 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
433 /* Initiate data concerning reuse of input reloads for the current
436 init_curr_insn_input_reloads (void)
438 curr_insn_input_reloads_num
= 0;
441 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
442 created input reload pseudo (only if TYPE is not OP_OUT). The
443 result pseudo is returned through RESULT_REG. Return TRUE if we
444 created a new pseudo, FALSE if we reused the already created input
445 reload pseudo. Use TITLE to describe new registers for debug
448 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
449 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
452 enum reg_class new_class
;
457 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
460 /* Prevent reuse value of expression with side effects,
461 e.g. volatile memory. */
462 if (! side_effects_p (original
))
463 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
464 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
465 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
467 rtx reg
= curr_insn_input_reloads
[i
].reg
;
469 /* If input is equal to original and both are VOIDmode,
470 GET_MODE (reg) might be still different from mode.
471 Ensure we don't return *result_reg with wrong mode. */
472 if (GET_MODE (reg
) != mode
)
474 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
476 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
477 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
481 if (lra_dump_file
!= NULL
)
483 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
484 dump_value_slim (lra_dump_file
, original
, 1);
486 if (new_class
!= lra_get_allocno_class (regno
))
487 lra_change_class (regno
, new_class
, ", change to", false);
488 if (lra_dump_file
!= NULL
)
489 fprintf (lra_dump_file
, "\n");
492 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
493 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
494 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
495 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
501 /* The page contains code to extract memory address parts. */
503 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
505 ok_for_index_p_nonstrict (rtx reg
)
507 unsigned regno
= REGNO (reg
);
509 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
512 /* A version of regno_ok_for_base_p for use here, when all pseudos
513 should count as OK. Arguments as for regno_ok_for_base_p. */
515 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
516 enum rtx_code outer_code
, enum rtx_code index_code
)
518 unsigned regno
= REGNO (reg
);
520 if (regno
>= FIRST_PSEUDO_REGISTER
)
522 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
527 /* The page contains major code to choose the current insn alternative
528 and generate reloads for it. */
530 /* Return the offset from REGNO of the least significant register
533 This function is used to tell whether two registers satisfy
534 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
536 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
537 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
539 lra_constraint_offset (int regno
, enum machine_mode mode
)
541 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
542 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
543 && SCALAR_INT_MODE_P (mode
))
544 return hard_regno_nregs
[regno
][mode
] - 1;
548 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
549 if they are the same hard reg, and has special hacks for
550 auto-increment and auto-decrement. This is specifically intended for
551 process_alt_operands to use in determining whether two operands
552 match. X is the operand whose number is the lower of the two.
554 It is supposed that X is the output operand and Y is the input
555 operand. Y_HARD_REGNO is the final hard regno of register Y or
556 register in subreg Y as we know it now. Otherwise, it is a
559 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
562 RTX_CODE code
= GET_CODE (x
);
567 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
568 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
572 i
= get_hard_regno (x
);
576 if ((j
= y_hard_regno
) < 0)
579 i
+= lra_constraint_offset (i
, GET_MODE (x
));
580 j
+= lra_constraint_offset (j
, GET_MODE (y
));
585 /* If two operands must match, because they are really a single
586 operand of an assembler insn, then two post-increments are invalid
587 because the assembler insn would increment only once. On the
588 other hand, a post-increment matches ordinary indexing if the
589 post-increment is the output operand. */
590 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
591 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
593 /* Two pre-increments are invalid because the assembler insn would
594 increment only once. On the other hand, a pre-increment matches
595 ordinary indexing if the pre-increment is the input operand. */
596 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
597 || GET_CODE (y
) == PRE_MODIFY
)
598 return operands_match_p (x
, XEXP (y
, 0), -1);
602 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
603 && x
== SUBREG_REG (y
))
605 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
606 && SUBREG_REG (x
) == y
)
609 /* Now we have disposed of all the cases in which different rtx
611 if (code
!= GET_CODE (y
))
614 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
615 if (GET_MODE (x
) != GET_MODE (y
))
624 return XEXP (x
, 0) == XEXP (y
, 0);
626 return XSTR (x
, 0) == XSTR (y
, 0);
632 /* Compare the elements. If any pair of corresponding elements fail
633 to match, return false for the whole things. */
635 fmt
= GET_RTX_FORMAT (code
);
636 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
642 if (XWINT (x
, i
) != XWINT (y
, i
))
647 if (XINT (x
, i
) != XINT (y
, i
))
652 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
661 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
663 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
665 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
671 /* It is believed that rtx's at this level will never
672 contain anything but integers and other rtx's, except for
673 within LABEL_REFs and SYMBOL_REFs. */
681 /* True if X is a constant that can be forced into the constant pool.
682 MODE is the mode of the operand, or VOIDmode if not known. */
683 #define CONST_POOL_OK_P(MODE, X) \
684 ((MODE) != VOIDmode \
686 && GET_CODE (X) != HIGH \
687 && !targetm.cannot_force_const_mem (MODE, X))
689 /* True if C is a non-empty register class that has too few registers
690 to be safely used as a reload target class. */
691 #define SMALL_REGISTER_CLASS_P(C) \
692 (reg_class_size [(C)] == 1 \
693 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
695 /* If REG is a reload pseudo, try to make its class satisfying CL. */
697 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
699 enum reg_class rclass
;
701 /* Do not make more accurate class from reloads generated. They are
702 mostly moves with a lot of constraints. Making more accurate
703 class may results in very narrow class and impossibility of find
704 registers for several reloads of one insn. */
705 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
707 if (GET_CODE (reg
) == SUBREG
)
708 reg
= SUBREG_REG (reg
);
709 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
711 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
712 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
715 /* Generate reloads for matching OUT and INS (array of input operand
716 numbers with end marker -1) with reg class GOAL_CLASS. Add input
717 and output reloads correspondingly to the lists *BEFORE and *AFTER.
718 OUT might be negative. In this case we generate input reloads for
719 matched input operands INS. */
721 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
722 rtx
*before
, rtx
*after
)
725 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
726 enum machine_mode inmode
, outmode
;
727 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
728 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
730 inmode
= curr_operand_mode
[ins
[0]];
731 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
732 push_to_sequence (*before
);
733 if (inmode
!= outmode
)
735 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
738 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
740 if (SCALAR_INT_MODE_P (inmode
))
741 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
743 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
744 LRA_SUBREG_P (new_out_reg
) = 1;
745 /* If the input reg is dying here, we can use the same hard
746 register for REG and IN_RTX. We do it only for original
747 pseudos as reload pseudos can die although original
748 pseudos still live where reload pseudos dies. */
749 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
750 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
751 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
756 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
758 if (SCALAR_INT_MODE_P (outmode
))
759 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
761 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
762 /* NEW_IN_REG is non-paradoxical subreg. We don't want
763 NEW_OUT_REG living above. We add clobber clause for
764 this. This is just a temporary clobber. We can remove
765 it at the end of LRA work. */
766 clobber
= emit_clobber (new_out_reg
);
767 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
768 LRA_SUBREG_P (new_in_reg
) = 1;
769 if (GET_CODE (in_rtx
) == SUBREG
)
771 rtx subreg_reg
= SUBREG_REG (in_rtx
);
773 /* If SUBREG_REG is dying here and sub-registers IN_RTX
774 and NEW_IN_REG are similar, we can use the same hard
775 register for REG and SUBREG_REG. */
776 if (REG_P (subreg_reg
)
777 && (int) REGNO (subreg_reg
) < lra_new_regno_start
778 && GET_MODE (subreg_reg
) == outmode
779 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
780 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
781 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
787 /* Pseudos have values -- see comments for lra_reg_info.
788 Different pseudos with the same value do not conflict even if
789 they live in the same place. When we create a pseudo we
790 assign value of original pseudo (if any) from which we
791 created the new pseudo. If we create the pseudo from the
792 input pseudo, the new pseudo will no conflict with the input
793 pseudo which is wrong when the input pseudo lives after the
794 insn and as the new pseudo value is changed by the insn
795 output. Therefore we create the new pseudo from the output.
797 We cannot reuse the current output register because we might
798 have a situation like "a <- a op b", where the constraints
799 force the second input operand ("b") to match the output
800 operand ("a"). "b" must then be copied into a new register
801 so that it doesn't clobber the current value of "a". */
803 new_in_reg
= new_out_reg
804 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
807 /* In operand can be got from transformations before processing insn
808 constraints. One example of such transformations is subreg
809 reloading (see function simplify_operand_subreg). The new
810 pseudos created by the transformations might have inaccurate
811 class (ALL_REGS) and we should make their classes more
813 narrow_reload_pseudo_class (in_rtx
, goal_class
);
814 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
815 *before
= get_insns ();
817 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
820 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
821 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
822 *curr_id
->operand_loc
[in
] = new_in_reg
;
824 lra_update_dups (curr_id
, ins
);
827 /* See a comment for the input operand above. */
828 narrow_reload_pseudo_class (out_rtx
, goal_class
);
829 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
832 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
834 *after
= get_insns ();
837 *curr_id
->operand_loc
[out
] = new_out_reg
;
838 lra_update_dup (curr_id
, out
);
841 /* Return register class which is union of all reg classes in insn
842 constraint alternative string starting with P. */
843 static enum reg_class
844 reg_class_from_constraints (const char *p
)
847 enum reg_class op_class
= NO_REGS
;
850 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
857 op_class
= (reg_class_subunion
858 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
864 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
868 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
870 #ifdef EXTRA_CONSTRAINT_STR
871 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
873 = (reg_class_subunion
874 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
881 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
884 while ((p
+= len
), c
);
888 /* If OP is a register, return the class of the register as per
889 get_reg_class, otherwise return NO_REGS. */
890 static inline enum reg_class
891 get_op_class (rtx op
)
893 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
896 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
897 otherwise. If modes of MEM_PSEUDO and VAL are different, use
898 SUBREG for VAL to make them equal. */
900 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
902 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
904 /* Usually size of mem_pseudo is greater than val size but in
905 rare cases it can be less as it can be defined by target
906 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
909 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
910 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
912 LRA_SUBREG_P (val
) = 1;
916 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
917 LRA_SUBREG_P (mem_pseudo
) = 1;
921 ? gen_move_insn (mem_pseudo
, val
)
922 : gen_move_insn (val
, mem_pseudo
));
925 /* Process a special case insn (register move), return true if we
926 don't need to process it anymore. INSN should be a single set
927 insn. Set up that RTL was changed through CHANGE_P and macro
928 SECONDARY_MEMORY_NEEDED says to use secondary memory through
931 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
934 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
935 enum reg_class dclass
, sclass
, secondary_class
;
936 enum machine_mode sreg_mode
;
937 secondary_reload_info sri
;
939 lra_assert (curr_insn_set
!= NULL_RTX
);
940 dreg
= dest
= SET_DEST (curr_insn_set
);
941 sreg
= src
= SET_SRC (curr_insn_set
);
942 if (GET_CODE (dest
) == SUBREG
)
943 dreg
= SUBREG_REG (dest
);
944 if (GET_CODE (src
) == SUBREG
)
945 sreg
= SUBREG_REG (src
);
946 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
948 sclass
= dclass
= NO_REGS
;
950 dclass
= get_reg_class (REGNO (dreg
));
951 if (dclass
== ALL_REGS
)
952 /* ALL_REGS is used for new pseudos created by transformations
953 like reload of SUBREG_REG (see function
954 simplify_operand_subreg). We don't know their class yet. We
955 should figure out the class from processing the insn
956 constraints not in this fast path function. Even if ALL_REGS
957 were a right class for the pseudo, secondary_... hooks usually
958 are not define for ALL_REGS. */
960 sreg_mode
= GET_MODE (sreg
);
963 sclass
= get_reg_class (REGNO (sreg
));
964 if (sclass
== ALL_REGS
)
965 /* See comments above. */
967 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
969 #ifdef SECONDARY_MEMORY_NEEDED
970 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
971 #ifdef SECONDARY_MEMORY_NEEDED_MODE
972 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
973 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
981 if (! REG_P (dreg
) || ! REG_P (sreg
))
984 sri
.icode
= CODE_FOR_nothing
;
986 secondary_class
= NO_REGS
;
987 /* Set up hard register for a reload pseudo for hook
988 secondary_reload because some targets just ignore unassigned
989 pseudos in the hook. */
990 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
992 dregno
= REGNO (dreg
);
993 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
997 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
999 sregno
= REGNO (sreg
);
1000 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1004 if (sclass
!= NO_REGS
)
1006 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1007 (reg_class_t
) sclass
,
1008 GET_MODE (src
), &sri
);
1009 if (sclass
== NO_REGS
1010 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1011 && dclass
!= NO_REGS
))
1013 enum reg_class old_sclass
= secondary_class
;
1014 secondary_reload_info old_sri
= sri
;
1016 sri
.prev_sri
= NULL
;
1017 sri
.icode
= CODE_FOR_nothing
;
1020 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1021 (reg_class_t
) dclass
,
1023 /* Check the target hook consistency. */
1025 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1026 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1027 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1030 reg_renumber
[sregno
] = -1;
1032 reg_renumber
[dregno
] = -1;
1033 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1037 if (secondary_class
!= NO_REGS
)
1038 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1042 if (old_sreg
!= sreg
)
1043 sreg
= copy_rtx (sreg
);
1044 if (sri
.icode
== CODE_FOR_nothing
)
1045 lra_emit_move (new_reg
, sreg
);
1048 enum reg_class scratch_class
;
1050 scratch_class
= (reg_class_from_constraints
1051 (insn_data
[sri
.icode
].operand
[2].constraint
));
1052 scratch_reg
= (lra_create_new_reg_with_unique_value
1053 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1054 scratch_class
, "scratch"));
1055 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1056 sreg
, scratch_reg
));
1058 before
= get_insns ();
1060 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1061 if (new_reg
!= NULL_RTX
)
1063 if (GET_CODE (src
) == SUBREG
)
1064 SUBREG_REG (src
) = new_reg
;
1066 SET_SRC (curr_insn_set
) = new_reg
;
1070 if (lra_dump_file
!= NULL
)
1072 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1073 dump_insn_slim (lra_dump_file
, curr_insn
);
1075 lra_set_insn_deleted (curr_insn
);
1081 /* The following data describe the result of process_alt_operands.
1082 The data are used in curr_insn_transform to generate reloads. */
1084 /* The chosen reg classes which should be used for the corresponding
1086 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1087 /* True if the operand should be the same as another operand and that
1088 other operand does not need a reload. */
1089 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1090 /* True if the operand does not need a reload. */
1091 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1092 /* True if the operand can be offsetable memory. */
1093 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1094 /* The number of an operand to which given operand can be matched to. */
1095 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1096 /* The number of elements in the following array. */
1097 static int goal_alt_dont_inherit_ops_num
;
1098 /* Numbers of operands whose reload pseudos should not be inherited. */
1099 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1100 /* True if the insn commutative operands should be swapped. */
1101 static bool goal_alt_swapped
;
1102 /* The chosen insn alternative. */
1103 static int goal_alt_number
;
1105 /* The following five variables are used to choose the best insn
1106 alternative. They reflect final characteristics of the best
1109 /* Number of necessary reloads and overall cost reflecting the
1110 previous value and other unpleasantness of the best alternative. */
1111 static int best_losers
, best_overall
;
1112 /* Overall number hard registers used for reloads. For example, on
1113 some targets we need 2 general registers to reload DFmode and only
1114 one floating point register. */
1115 static int best_reload_nregs
;
1116 /* Overall number reflecting distances of previous reloading the same
1117 value. The distances are counted from the current BB start. It is
1118 used to improve inheritance chances. */
1119 static int best_reload_sum
;
1121 /* True if the current insn should have no correspondingly input or
1123 static bool no_input_reloads_p
, no_output_reloads_p
;
1125 /* True if we swapped the commutative operands in the current
1127 static int curr_swapped
;
1129 /* Arrange for address element *LOC to be a register of class CL.
1130 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1131 automodified value; handle that case by adding the required output
1132 reloads to list AFTER. Return true if the RTL was changed. */
1134 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1137 enum reg_class rclass
, new_class
;
1140 enum machine_mode mode
;
1141 bool before_p
= false;
1143 loc
= strip_subreg (loc
);
1145 mode
= GET_MODE (reg
);
1148 /* Always reload memory in an address even if the target supports
1150 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1155 regno
= REGNO (reg
);
1156 rclass
= get_reg_class (regno
);
1157 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1159 if (lra_dump_file
!= NULL
)
1161 fprintf (lra_dump_file
,
1162 "Changing pseudo %d in address of insn %u on equiv ",
1163 REGNO (reg
), INSN_UID (curr_insn
));
1164 dump_value_slim (lra_dump_file
, *loc
, 1);
1165 fprintf (lra_dump_file
, "\n");
1167 *loc
= copy_rtx (*loc
);
1169 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1172 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1173 mode
, reg
, cl
, "address", &new_reg
))
1176 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1178 lra_change_class (regno
, new_class
, " Change to", true);
1186 push_to_sequence (*before
);
1187 lra_emit_move (new_reg
, reg
);
1188 *before
= get_insns ();
1195 lra_emit_move (reg
, new_reg
);
1197 *after
= get_insns ();
1203 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1204 the insn to be inserted before curr insn. AFTER returns the
1205 the insn to be inserted after curr insn. ORIGREG and NEWREG
1206 are the original reg and new reg for reload. */
1208 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1212 push_to_sequence (*before
);
1213 lra_emit_move (newreg
, origreg
);
1214 *before
= get_insns ();
1220 lra_emit_move (origreg
, newreg
);
1222 *after
= get_insns ();
1227 /* Make reloads for subreg in operand NOP with internal subreg mode
1228 REG_MODE, add new reloads for further processing. Return true if
1229 any reload was generated. */
1231 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1235 enum machine_mode mode
;
1237 rtx operand
= *curr_id
->operand_loc
[nop
];
1238 enum reg_class regclass
;
1241 before
= after
= NULL_RTX
;
1243 if (GET_CODE (operand
) != SUBREG
)
1246 mode
= GET_MODE (operand
);
1247 reg
= SUBREG_REG (operand
);
1248 type
= curr_static_id
->operand
[nop
].type
;
1249 /* If we change address for paradoxical subreg of memory, the
1250 address might violate the necessary alignment or the access might
1251 be slow. So take this into consideration. We should not worry
1252 about access beyond allocated memory for paradoxical memory
1253 subregs as we don't substitute such equiv memory (see processing
1254 equivalences in function lra_constraints) and because for spilled
1255 pseudos we allocate stack memory enough for the biggest
1256 corresponding paradoxical subreg. */
1258 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1259 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1260 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1262 alter_subreg (curr_id
->operand_loc
[nop
], false);
1265 /* Put constant into memory when we have mixed modes. It generates
1266 a better code in most cases as it does not need a secondary
1267 reload memory. It also prevents LRA looping when LRA is using
1268 secondary reload memory again and again. */
1269 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1270 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1272 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1273 alter_subreg (curr_id
->operand_loc
[nop
], false);
1276 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1277 if there may be a problem accessing OPERAND in the outer
1280 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1281 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1282 /* Don't reload paradoxical subregs because we could be looping
1283 having repeatedly final regno out of hard regs range. */
1284 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1285 >= hard_regno_nregs
[hard_regno
][mode
])
1286 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1287 SUBREG_BYTE (operand
), mode
) < 0
1288 /* Don't reload subreg for matching reload. It is actually
1289 valid subreg in LRA. */
1290 && ! LRA_SUBREG_P (operand
))
1291 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1293 /* The class will be defined later in curr_insn_transform. */
1294 enum reg_class rclass
1295 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1297 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1298 rclass
, "subreg reg", &new_reg
))
1300 bool insert_before
, insert_after
;
1301 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1303 insert_before
= (type
!= OP_OUT
1304 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1305 insert_after
= (type
!= OP_IN
);
1306 insert_move_for_subreg (insert_before
? &before
: NULL
,
1307 insert_after
? &after
: NULL
,
1310 SUBREG_REG (operand
) = new_reg
;
1311 lra_process_new_insns (curr_insn
, before
, after
,
1312 "Inserting subreg reload");
1315 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1316 IRA allocates hardreg to the inner pseudo reg according to its mode
1317 instead of the outermode, so the size of the hardreg may not be enough
1318 to contain the outermode operand, in that case we may need to insert
1319 reload for the reg. For the following two types of paradoxical subreg,
1320 we need to insert reload:
1321 1. If the op_type is OP_IN, and the hardreg could not be paired with
1322 other hardreg to contain the outermode operand
1323 (checked by in_hard_reg_set_p), we need to insert the reload.
1324 2. If the op_type is OP_OUT or OP_INOUT.
1326 Here is a paradoxical subreg example showing how the reload is generated:
1328 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1329 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1331 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1332 here, if reg107 is assigned to hardreg R15, because R15 is the last
1333 hardreg, compiler cannot find another hardreg to pair with R15 to
1334 contain TImode data. So we insert a TImode reload reg180 for it.
1335 After reload is inserted:
1337 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1338 (reg:DI 107 [ __comp ])) -1
1339 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1340 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1342 Two reload hard registers will be allocated to reg180 to save TImode data
1344 else if (REG_P (reg
)
1345 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1346 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1347 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1348 < hard_regno_nregs
[hard_regno
][mode
])
1349 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1351 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1354 /* The class will be defined later in curr_insn_transform. */
1355 enum reg_class rclass
1356 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1358 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1359 rclass
, "paradoxical subreg", &new_reg
))
1362 bool insert_before
, insert_after
;
1364 PUT_MODE (new_reg
, mode
);
1365 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1366 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1368 insert_before
= (type
!= OP_OUT
);
1369 insert_after
= (type
!= OP_IN
);
1370 insert_move_for_subreg (insert_before
? &before
: NULL
,
1371 insert_after
? &after
: NULL
,
1374 SUBREG_REG (operand
) = new_reg
;
1375 lra_process_new_insns (curr_insn
, before
, after
,
1376 "Inserting paradoxical subreg reload");
1382 /* Return TRUE if X refers for a hard register from SET. */
1384 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1386 int i
, j
, x_hard_regno
;
1387 enum machine_mode mode
;
1393 code
= GET_CODE (x
);
1394 mode
= GET_MODE (x
);
1398 code
= GET_CODE (x
);
1399 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1400 mode
= GET_MODE (x
);
1405 x_hard_regno
= get_hard_regno (x
);
1406 return (x_hard_regno
>= 0
1407 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1411 struct address_info ad
;
1413 decompose_mem_address (&ad
, x
);
1414 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1416 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1419 fmt
= GET_RTX_FORMAT (code
);
1420 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1424 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1427 else if (fmt
[i
] == 'E')
1429 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1430 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1437 /* Return true if OP is a spilled pseudo. */
1439 spilled_pseudo_p (rtx op
)
1442 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1445 /* Return true if X is a general constant. */
1447 general_constant_p (rtx x
)
1449 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1453 reg_in_class_p (rtx reg
, enum reg_class cl
)
1456 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1457 return in_class_p (reg
, cl
, NULL
);
1460 /* Major function to choose the current insn alternative and what
1461 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1462 negative we should consider only this alternative. Return false if
1463 we can not choose the alternative or find how to reload the
1466 process_alt_operands (int only_alternative
)
1469 int nop
, overall
, nalt
;
1470 int n_alternatives
= curr_static_id
->n_alternatives
;
1471 int n_operands
= curr_static_id
->n_operands
;
1472 /* LOSERS counts the operands that don't fit this alternative and
1473 would require loading. */
1475 /* REJECT is a count of how undesirable this alternative says it is
1476 if any reloading is required. If the alternative matches exactly
1477 then REJECT is ignored, but otherwise it gets this much counted
1478 against it in addition to the reloading needed. */
1480 /* The number of elements in the following array. */
1481 int early_clobbered_regs_num
;
1482 /* Numbers of operands which are early clobber registers. */
1483 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1484 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1485 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1486 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1487 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1488 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1489 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1490 /* The number of elements in the following array. */
1491 int curr_alt_dont_inherit_ops_num
;
1492 /* Numbers of operands whose reload pseudos should not be inherited. */
1493 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1495 /* The register when the operand is a subreg of register, otherwise the
1497 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1498 /* The register if the operand is a register or subreg of register,
1500 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1501 int hard_regno
[MAX_RECOG_OPERANDS
];
1502 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1503 int reload_nregs
, reload_sum
;
1507 /* Calculate some data common for all alternatives to speed up the
1509 for (nop
= 0; nop
< n_operands
; nop
++)
1513 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1514 /* The real hard regno of the operand after the allocation. */
1515 hard_regno
[nop
] = get_hard_regno (op
);
1517 operand_reg
[nop
] = reg
= op
;
1518 biggest_mode
[nop
] = GET_MODE (op
);
1519 if (GET_CODE (op
) == SUBREG
)
1521 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1522 if (GET_MODE_SIZE (biggest_mode
[nop
])
1523 < GET_MODE_SIZE (GET_MODE (reg
)))
1524 biggest_mode
[nop
] = GET_MODE (reg
);
1527 operand_reg
[nop
] = NULL_RTX
;
1528 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1529 || ((int) REGNO (reg
)
1530 == lra_get_elimination_hard_regno (REGNO (reg
))))
1531 no_subreg_reg_operand
[nop
] = reg
;
1533 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1534 /* Just use natural mode for elimination result. It should
1535 be enough for extra constraints hooks. */
1536 = regno_reg_rtx
[hard_regno
[nop
]];
1539 /* The constraints are made of several alternatives. Each operand's
1540 constraint looks like foo,bar,... with commas separating the
1541 alternatives. The first alternatives for all operands go
1542 together, the second alternatives go together, etc.
1544 First loop over alternatives. */
1545 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1547 /* Loop over operands for one constraint alternative. */
1548 #if HAVE_ATTR_enabled
1549 if (curr_id
->alternative_enabled_p
!= NULL
1550 && ! curr_id
->alternative_enabled_p
[nalt
])
1554 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1558 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1559 for (nop
= 0; nop
< n_operands
; nop
++)
1561 int inc
= (curr_static_id
1562 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1563 if (lra_dump_file
!= NULL
&& inc
!= 0)
1564 fprintf (lra_dump_file
,
1565 " Staticly defined alt reject+=%d\n", inc
);
1568 early_clobbered_regs_num
= 0;
1570 for (nop
= 0; nop
< n_operands
; nop
++)
1574 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1575 bool win
, did_match
, offmemok
, early_clobber_p
;
1576 /* false => this operand can be reloaded somehow for this
1579 /* true => this operand can be reloaded if the alternative
1582 /* True if a constant forced into memory would be OK for
1585 enum reg_class this_alternative
, this_costly_alternative
;
1586 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1587 bool this_alternative_match_win
, this_alternative_win
;
1588 bool this_alternative_offmemok
;
1590 enum machine_mode mode
;
1592 opalt_num
= nalt
* n_operands
+ nop
;
1593 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1595 /* Fast track for no constraints at all. */
1596 curr_alt
[nop
] = NO_REGS
;
1597 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1598 curr_alt_win
[nop
] = true;
1599 curr_alt_match_win
[nop
] = false;
1600 curr_alt_offmemok
[nop
] = false;
1601 curr_alt_matches
[nop
] = -1;
1605 op
= no_subreg_reg_operand
[nop
];
1606 mode
= curr_operand_mode
[nop
];
1608 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1611 early_clobber_p
= false;
1612 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1614 this_costly_alternative
= this_alternative
= NO_REGS
;
1615 /* We update set of possible hard regs besides its class
1616 because reg class might be inaccurate. For example,
1617 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1618 is translated in HI_REGS because classes are merged by
1619 pairs and there is no accurate intermediate class. */
1620 CLEAR_HARD_REG_SET (this_alternative_set
);
1621 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1622 this_alternative_win
= false;
1623 this_alternative_match_win
= false;
1624 this_alternative_offmemok
= false;
1625 this_alternative_matches
= -1;
1627 /* An empty constraint should be excluded by the fast
1629 lra_assert (*p
!= 0 && *p
!= ',');
1631 /* Scan this alternative's specs for this operand; set WIN
1632 if the operand fits any letter in this alternative.
1633 Otherwise, clear BADOP if this operand could fit some
1634 letter after reloads, or set WINREG if this operand could
1635 fit after reloads provided the constraint allows some
1640 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1649 case '=': case '+': case '?': case '*': case '!':
1650 case ' ': case '\t':
1654 /* We only support one commutative marker, the first
1655 one. We already set commutative above. */
1659 early_clobber_p
= true;
1663 /* Ignore rest of this alternative. */
1667 case '0': case '1': case '2': case '3': case '4':
1668 case '5': case '6': case '7': case '8': case '9':
1673 m
= strtoul (p
, &end
, 10);
1676 lra_assert (nop
> m
);
1678 this_alternative_matches
= m
;
1679 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1680 /* We are supposed to match a previous operand.
1681 If we do, we win if that one did. If we do
1682 not, count both of the operands as losers.
1683 (This is too conservative, since most of the
1684 time only a single reload insn will be needed
1685 to make the two operands win. As a result,
1686 this alternative may be rejected when it is
1687 actually desirable.) */
1689 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1690 *curr_id
->operand_loc
[m
], m_hregno
))
1692 /* We should reject matching of an early
1693 clobber operand if the matching operand is
1694 not dying in the insn. */
1695 if (! curr_static_id
->operand
[m
].early_clobber
1696 || operand_reg
[nop
] == NULL_RTX
1697 || (find_regno_note (curr_insn
, REG_DEAD
,
1699 || REGNO (op
) == REGNO (operand_reg
[m
])))
1704 /* If we are matching a non-offsettable
1705 address where an offsettable address was
1706 expected, then we must reject this
1707 combination, because we can't reload
1709 if (curr_alt_offmemok
[m
]
1710 && MEM_P (*curr_id
->operand_loc
[m
])
1711 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1716 /* Operands don't match. Both operands must
1717 allow a reload register, otherwise we
1718 cannot make them match. */
1719 if (curr_alt
[m
] == NO_REGS
)
1721 /* Retroactively mark the operand we had to
1722 match as a loser, if it wasn't already and
1723 it wasn't matched to a register constraint
1724 (e.g it might be matched by memory). */
1726 && (operand_reg
[m
] == NULL_RTX
1727 || hard_regno
[m
] < 0))
1731 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1732 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1735 /* We prefer no matching alternatives because
1736 it gives more freedom in RA. */
1737 if (operand_reg
[nop
] == NULL_RTX
1738 || (find_regno_note (curr_insn
, REG_DEAD
,
1739 REGNO (operand_reg
[nop
]))
1742 if (lra_dump_file
!= NULL
)
1745 " %d Matching alt: reject+=2\n",
1750 /* If we have to reload this operand and some
1751 previous operand also had to match the same
1752 thing as this operand, we don't know how to do
1754 if (!match_p
|| !curr_alt_win
[m
])
1756 for (i
= 0; i
< nop
; i
++)
1757 if (curr_alt_matches
[i
] == m
)
1765 /* This can be fixed with reloads if the operand
1766 we are supposed to match can be fixed with
1769 this_alternative
= curr_alt
[m
];
1770 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1771 winreg
= this_alternative
!= NO_REGS
;
1776 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1778 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1779 IOR_HARD_REG_SET (this_alternative_set
,
1780 reg_class_contents
[cl
]);
1783 this_costly_alternative
1784 = reg_class_subunion
[this_costly_alternative
][cl
];
1785 IOR_HARD_REG_SET (this_costly_alternative_set
,
1786 reg_class_contents
[cl
]);
1792 case TARGET_MEM_CONSTRAINT
:
1793 if (MEM_P (op
) || spilled_pseudo_p (op
))
1795 /* We can put constant or pseudo value into memory
1796 to satisfy the constraint. */
1797 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1804 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1805 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1811 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1812 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1816 /* Memory op whose address is not offsettable. */
1819 && ! offsettable_nonstrict_memref_p (op
))
1823 /* Memory operand whose address is offsettable. */
1826 && offsettable_nonstrict_memref_p (op
))
1827 || spilled_pseudo_p (op
))
1829 /* We can put constant or pseudo value into memory
1830 or make memory address offsetable to satisfy the
1832 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1840 if (GET_CODE (op
) == CONST_DOUBLE
1841 || (GET_CODE (op
) == CONST_VECTOR
1842 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1848 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1849 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1854 if (CONST_SCALAR_INT_P (op
))
1858 if (general_constant_p (op
))
1863 if (CONST_SCALAR_INT_P (op
))
1875 if (CONST_INT_P (op
)
1876 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1881 /* This constraint should be excluded by the fast
1888 || general_constant_p (op
)
1889 || spilled_pseudo_p (op
))
1891 /* Drop through into 'r' case. */
1895 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1896 IOR_HARD_REG_SET (this_alternative_set
,
1897 reg_class_contents
[GENERAL_REGS
]);
1900 this_costly_alternative
1901 = (reg_class_subunion
1902 [this_costly_alternative
][GENERAL_REGS
]);
1903 IOR_HARD_REG_SET (this_costly_alternative_set
,
1904 reg_class_contents
[GENERAL_REGS
]);
1909 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1911 #ifdef EXTRA_CONSTRAINT_STR
1912 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1914 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1916 else if (spilled_pseudo_p (op
))
1919 /* If we didn't already win, we can reload
1920 constants via force_const_mem or put the
1921 pseudo value into memory, or make other
1922 memory by reloading the address like for
1924 if (CONST_POOL_OK_P (mode
, op
)
1925 || MEM_P (op
) || REG_P (op
))
1931 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1933 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1936 /* If we didn't already win, we can reload
1937 the address into a base register. */
1938 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1941 = reg_class_subunion
[this_alternative
][cl
];
1942 IOR_HARD_REG_SET (this_alternative_set
,
1943 reg_class_contents
[cl
]);
1946 this_costly_alternative
1947 = (reg_class_subunion
1948 [this_costly_alternative
][cl
]);
1949 IOR_HARD_REG_SET (this_costly_alternative_set
,
1950 reg_class_contents
[cl
]);
1956 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1962 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1963 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1964 IOR_HARD_REG_SET (this_alternative_set
,
1965 reg_class_contents
[cl
]);
1968 this_costly_alternative
1969 = reg_class_subunion
[this_costly_alternative
][cl
];
1970 IOR_HARD_REG_SET (this_costly_alternative_set
,
1971 reg_class_contents
[cl
]);
1974 if (mode
== BLKmode
)
1979 if (hard_regno
[nop
] >= 0
1980 && in_hard_reg_set_p (this_alternative_set
,
1981 mode
, hard_regno
[nop
]))
1983 else if (hard_regno
[nop
] < 0
1984 && in_class_p (op
, this_alternative
, NULL
))
1989 if (c
!= ' ' && c
!= '\t')
1990 costly_p
= c
== '*';
1992 while ((p
+= len
), c
);
1994 scratch_p
= (operand_reg
[nop
] != NULL_RTX
1995 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
1996 /* Record which operands fit this alternative. */
1999 this_alternative_win
= true;
2000 if (operand_reg
[nop
] != NULL_RTX
)
2002 if (hard_regno
[nop
] >= 0)
2004 if (in_hard_reg_set_p (this_costly_alternative_set
,
2005 mode
, hard_regno
[nop
]))
2007 if (lra_dump_file
!= NULL
)
2008 fprintf (lra_dump_file
,
2009 " %d Costly set: reject++\n",
2016 /* Prefer won reg to spilled pseudo under other
2017 equal conditions for possibe inheritance. */
2020 if (lra_dump_file
!= NULL
)
2023 " %d Non pseudo reload: reject++\n",
2027 if (in_class_p (operand_reg
[nop
],
2028 this_costly_alternative
, NULL
))
2030 if (lra_dump_file
!= NULL
)
2033 " %d Non pseudo costly reload:"
2039 /* We simulate the behaviour of old reload here.
2040 Although scratches need hard registers and it
2041 might result in spilling other pseudos, no reload
2042 insns are generated for the scratches. So it
2043 might cost something but probably less than old
2044 reload pass believes. */
2047 if (lra_dump_file
!= NULL
)
2048 fprintf (lra_dump_file
,
2049 " %d Scratch win: reject+=2\n",
2056 this_alternative_match_win
= true;
2059 int const_to_mem
= 0;
2062 /* Never do output reload of stack pointer. It makes
2063 impossible to do elimination when SP is changed in
2065 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2066 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2069 /* If this alternative asks for a specific reg class, see if there
2070 is at least one allocatable register in that class. */
2072 = (this_alternative
== NO_REGS
2073 || (hard_reg_set_subset_p
2074 (reg_class_contents
[this_alternative
],
2075 lra_no_alloc_regs
)));
2077 /* For asms, verify that the class for this alternative is possible
2078 for the mode that is specified. */
2079 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2082 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2083 if (HARD_REGNO_MODE_OK (i
, mode
)
2084 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2087 if (i
== FIRST_PSEUDO_REGISTER
)
2091 /* If this operand accepts a register, and if the
2092 register class has at least one allocatable register,
2093 then this operand can be reloaded. */
2094 if (winreg
&& !no_regs_p
)
2099 if (lra_dump_file
!= NULL
)
2100 fprintf (lra_dump_file
,
2101 " alt=%d: Bad operand -- refuse\n",
2106 this_alternative_offmemok
= offmemok
;
2107 if (this_costly_alternative
!= NO_REGS
)
2109 if (lra_dump_file
!= NULL
)
2110 fprintf (lra_dump_file
,
2111 " %d Costly loser: reject++\n", nop
);
2114 /* If the operand is dying, has a matching constraint,
2115 and satisfies constraints of the matched operand
2116 which failed to satisfy the own constraints, we do
2117 not need to generate a reload insn for this
2119 if (!(this_alternative_matches
>= 0
2120 && !curr_alt_win
[this_alternative_matches
]
2122 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2123 && (hard_regno
[nop
] >= 0
2124 ? in_hard_reg_set_p (this_alternative_set
,
2125 mode
, hard_regno
[nop
])
2126 : in_class_p (op
, this_alternative
, NULL
))))
2128 /* Strict_low_part requires to reload the register
2129 not the sub-register. In this case we should
2130 check that a final reload hard reg can hold the
2132 if (curr_static_id
->operand
[nop
].strict_low
2134 && hard_regno
[nop
] < 0
2135 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2136 && ira_class_hard_regs_num
[this_alternative
] > 0
2137 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2138 [this_alternative
][0],
2140 (*curr_id
->operand_loc
[nop
])))
2142 if (lra_dump_file
!= NULL
)
2145 " alt=%d: Strict low subreg reload -- refuse\n",
2151 if (operand_reg
[nop
] != NULL_RTX
2152 /* Output operands and matched input operands are
2153 not inherited. The following conditions do not
2154 exactly describe the previous statement but they
2155 are pretty close. */
2156 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2157 && (this_alternative_matches
< 0
2158 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2160 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2164 if (last_reload
> bb_reload_num
)
2165 reload_sum
+= last_reload
- bb_reload_num
;
2167 /* If this is a constant that is reloaded into the
2168 desired class by copying it to memory first, count
2169 that as another reload. This is consistent with
2170 other code and is required to avoid choosing another
2171 alternative when the constant is moved into memory.
2172 Note that the test here is precisely the same as in
2173 the code below that calls force_const_mem. */
2174 if (CONST_POOL_OK_P (mode
, op
)
2175 && ((targetm
.preferred_reload_class
2176 (op
, this_alternative
) == NO_REGS
)
2177 || no_input_reloads_p
))
2184 /* Alternative loses if it requires a type of reload not
2185 permitted for this insn. We can always reload
2186 objects with a REG_UNUSED note. */
2187 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2188 && no_output_reloads_p
2189 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2190 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2191 && no_input_reloads_p
&& ! const_to_mem
)
2192 || (this_alternative_matches
>= 0
2193 && (no_input_reloads_p
|| no_output_reloads_p
)))
2195 if (lra_dump_file
!= NULL
)
2198 " alt=%d: No input/otput reload -- refuse\n",
2203 /* Check strong discouragement of reload of non-constant
2204 into class THIS_ALTERNATIVE. */
2205 if (! CONSTANT_P (op
) && ! no_regs_p
2206 && (targetm
.preferred_reload_class
2207 (op
, this_alternative
) == NO_REGS
2208 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2209 && (targetm
.preferred_output_reload_class
2210 (op
, this_alternative
) == NO_REGS
))))
2212 if (lra_dump_file
!= NULL
)
2213 fprintf (lra_dump_file
,
2214 " %d Non-prefered reload: reject+=%d\n",
2215 nop
, LRA_MAX_REJECT
);
2216 reject
+= LRA_MAX_REJECT
;
2219 if (! (MEM_P (op
) && offmemok
)
2220 && ! (const_to_mem
&& constmemok
))
2222 /* We prefer to reload pseudos over reloading other
2223 things, since such reloads may be able to be
2224 eliminated later. So bump REJECT in other cases.
2225 Don't do this in the case where we are forcing a
2226 constant into memory and it will then win since
2227 we don't want to have a different alternative
2229 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2231 if (lra_dump_file
!= NULL
)
2234 " %d Non-pseudo reload: reject+=2\n",
2241 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2243 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2245 if (lra_dump_file
!= NULL
)
2248 " %d Small class reload: reject+=%d\n",
2249 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2250 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2254 /* We are trying to spill pseudo into memory. It is
2255 usually more costly than moving to a hard register
2256 although it might takes the same number of
2258 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2260 if (lra_dump_file
!= NULL
)
2263 " %d Spill pseudo in memory: reject+=3\n",
2268 #ifdef SECONDARY_MEMORY_NEEDED
2269 /* If reload requires moving value through secondary
2270 memory, it will need one more insn at least. */
2271 if (this_alternative
!= NO_REGS
2272 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2273 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2274 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2276 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2277 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2281 /* Input reloads can be inherited more often than output
2282 reloads can be removed, so penalize output
2284 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2286 if (lra_dump_file
!= NULL
)
2289 " %d Non input pseudo reload: reject++\n",
2295 if (early_clobber_p
&& ! scratch_p
)
2297 if (lra_dump_file
!= NULL
)
2298 fprintf (lra_dump_file
,
2299 " %d Early clobber: reject++\n", nop
);
2302 /* ??? We check early clobbers after processing all operands
2303 (see loop below) and there we update the costs more.
2304 Should we update the cost (may be approximately) here
2305 because of early clobber register reloads or it is a rare
2306 or non-important thing to be worth to do it. */
2307 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2308 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2310 if (lra_dump_file
!= NULL
)
2311 fprintf (lra_dump_file
,
2312 " alt=%d,overall=%d,losers=%d -- refuse\n",
2313 nalt
, overall
, losers
);
2317 curr_alt
[nop
] = this_alternative
;
2318 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2319 curr_alt_win
[nop
] = this_alternative_win
;
2320 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2321 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2322 curr_alt_matches
[nop
] = this_alternative_matches
;
2324 if (this_alternative_matches
>= 0
2325 && !did_match
&& !this_alternative_win
)
2326 curr_alt_win
[this_alternative_matches
] = false;
2328 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2329 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2331 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2332 /* Prevent processing non-move insns. */
2333 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2334 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2335 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2336 && REG_P (no_subreg_reg_operand
[0])
2337 && REG_P (no_subreg_reg_operand
[1])
2338 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2339 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2340 || (! curr_alt_win
[0] && curr_alt_win
[1]
2341 && REG_P (no_subreg_reg_operand
[1])
2342 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2343 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2344 && REG_P (no_subreg_reg_operand
[0])
2345 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2346 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2347 no_subreg_reg_operand
[1])
2348 || (targetm
.preferred_reload_class
2349 (no_subreg_reg_operand
[1],
2350 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2351 /* If it is a result of recent elimination in move
2352 insn we can transform it into an add still by
2353 using this alternative. */
2354 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2356 /* We have a move insn and a new reload insn will be similar
2357 to the current insn. We should avoid such situation as it
2358 results in LRA cycling. */
2359 overall
+= LRA_MAX_REJECT
;
2362 curr_alt_dont_inherit_ops_num
= 0;
2363 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2365 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2366 HARD_REG_SET temp_set
;
2368 i
= early_clobbered_nops
[nop
];
2369 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2370 || hard_regno
[i
] < 0)
2372 lra_assert (operand_reg
[i
] != NULL_RTX
);
2373 clobbered_hard_regno
= hard_regno
[i
];
2374 CLEAR_HARD_REG_SET (temp_set
);
2375 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2376 first_conflict_j
= last_conflict_j
= -1;
2377 for (j
= 0; j
< n_operands
; j
++)
2379 /* We don't want process insides of match_operator and
2380 match_parallel because otherwise we would process
2381 their operands once again generating a wrong
2383 || curr_static_id
->operand
[j
].is_operator
)
2385 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2386 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2388 /* If we don't reload j-th operand, check conflicts. */
2389 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2390 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2392 if (first_conflict_j
< 0)
2393 first_conflict_j
= j
;
2394 last_conflict_j
= j
;
2396 if (last_conflict_j
< 0)
2398 /* If earlyclobber operand conflicts with another
2399 non-matching operand which is actually the same register
2400 as the earlyclobber operand, it is better to reload the
2401 another operand as an operand matching the earlyclobber
2402 operand can be also the same. */
2403 if (first_conflict_j
== last_conflict_j
2404 && operand_reg
[last_conflict_j
]
2405 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2406 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2408 curr_alt_win
[last_conflict_j
] = false;
2409 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2412 /* Early clobber was already reflected in REJECT. */
2413 lra_assert (reject
> 0);
2414 if (lra_dump_file
!= NULL
)
2417 " %d Conflict early clobber reload: reject--\n",
2420 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2424 /* We need to reload early clobbered register and the
2425 matched registers. */
2426 for (j
= 0; j
< n_operands
; j
++)
2427 if (curr_alt_matches
[j
] == i
)
2429 curr_alt_match_win
[j
] = false;
2431 overall
+= LRA_LOSER_COST_FACTOR
;
2433 if (! curr_alt_match_win
[i
])
2434 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2437 /* Remember pseudos used for match reloads are never
2439 lra_assert (curr_alt_matches
[i
] >= 0);
2440 curr_alt_win
[curr_alt_matches
[i
]] = false;
2442 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2444 /* Early clobber was already reflected in REJECT. */
2445 lra_assert (reject
> 0);
2446 if (lra_dump_file
!= NULL
)
2449 " %d Matched conflict early clobber reloads:"
2453 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2456 if (lra_dump_file
!= NULL
)
2457 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2458 nalt
, overall
, losers
, reload_nregs
);
2460 /* If this alternative can be made to work by reloading, and it
2461 needs less reloading than the others checked so far, record
2462 it as the chosen goal for reloading. */
2463 if ((best_losers
!= 0 && losers
== 0)
2464 || (((best_losers
== 0 && losers
== 0)
2465 || (best_losers
!= 0 && losers
!= 0))
2466 && (best_overall
> overall
2467 || (best_overall
== overall
2468 /* If the cost of the reloads is the same,
2469 prefer alternative which requires minimal
2470 number of reload regs. */
2471 && (reload_nregs
< best_reload_nregs
2472 || (reload_nregs
== best_reload_nregs
2473 && (best_reload_sum
< reload_sum
2474 || (best_reload_sum
== reload_sum
2475 && nalt
< goal_alt_number
))))))))
2477 for (nop
= 0; nop
< n_operands
; nop
++)
2479 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2480 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2481 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2482 goal_alt
[nop
] = curr_alt
[nop
];
2483 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2485 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2486 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2487 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2488 goal_alt_swapped
= curr_swapped
;
2489 best_overall
= overall
;
2490 best_losers
= losers
;
2491 best_reload_nregs
= reload_nregs
;
2492 best_reload_sum
= reload_sum
;
2493 goal_alt_number
= nalt
;
2496 /* Everything is satisfied. Do not process alternatives
2505 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2506 space AS, and check that each pseudo has the proper kind of hard
2509 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2510 rtx addr
, addr_space_t as
)
2512 #ifdef GO_IF_LEGITIMATE_ADDRESS
2513 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2514 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2520 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2524 /* Return whether address AD is valid. */
2527 valid_address_p (struct address_info
*ad
)
2529 /* Some ports do not check displacements for eliminable registers,
2530 so we replace them temporarily with the elimination target. */
2531 rtx saved_base_reg
= NULL_RTX
;
2532 rtx saved_index_reg
= NULL_RTX
;
2533 rtx
*base_term
= strip_subreg (ad
->base_term
);
2534 rtx
*index_term
= strip_subreg (ad
->index_term
);
2535 if (base_term
!= NULL
)
2537 saved_base_reg
= *base_term
;
2538 lra_eliminate_reg_if_possible (base_term
);
2539 if (ad
->base_term2
!= NULL
)
2540 *ad
->base_term2
= *ad
->base_term
;
2542 if (index_term
!= NULL
)
2544 saved_index_reg
= *index_term
;
2545 lra_eliminate_reg_if_possible (index_term
);
2547 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2548 if (saved_base_reg
!= NULL_RTX
)
2550 *base_term
= saved_base_reg
;
2551 if (ad
->base_term2
!= NULL
)
2552 *ad
->base_term2
= *ad
->base_term
;
2554 if (saved_index_reg
!= NULL_RTX
)
2555 *index_term
= saved_index_reg
;
2559 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2561 base_plus_disp_to_reg (struct address_info
*ad
)
2566 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2567 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2568 get_index_code (ad
));
2569 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2571 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2575 /* Return true if we can add a displacement to address AD, even if that
2576 makes the address invalid. The fix-up code requires any new address
2577 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2579 can_add_disp_p (struct address_info
*ad
)
2581 return (!ad
->autoinc_p
2582 && ad
->segment
== NULL
2583 && ad
->base
== ad
->base_term
2584 && ad
->disp
== ad
->disp_term
);
2587 /* Make equiv substitution in address AD. Return true if a substitution
2590 equiv_address_substitution (struct address_info
*ad
)
2592 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2593 HOST_WIDE_INT disp
, scale
;
2596 base_term
= strip_subreg (ad
->base_term
);
2597 if (base_term
== NULL
)
2598 base_reg
= new_base_reg
= NULL_RTX
;
2601 base_reg
= *base_term
;
2602 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2604 index_term
= strip_subreg (ad
->index_term
);
2605 if (index_term
== NULL
)
2606 index_reg
= new_index_reg
= NULL_RTX
;
2609 index_reg
= *index_term
;
2610 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2612 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2616 if (lra_dump_file
!= NULL
)
2618 fprintf (lra_dump_file
, "Changing address in insn %d ",
2619 INSN_UID (curr_insn
));
2620 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2622 if (base_reg
!= new_base_reg
)
2624 if (REG_P (new_base_reg
))
2626 *base_term
= new_base_reg
;
2629 else if (GET_CODE (new_base_reg
) == PLUS
2630 && REG_P (XEXP (new_base_reg
, 0))
2631 && CONST_INT_P (XEXP (new_base_reg
, 1))
2632 && can_add_disp_p (ad
))
2634 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2635 *base_term
= XEXP (new_base_reg
, 0);
2638 if (ad
->base_term2
!= NULL
)
2639 *ad
->base_term2
= *ad
->base_term
;
2641 if (index_reg
!= new_index_reg
)
2643 if (REG_P (new_index_reg
))
2645 *index_term
= new_index_reg
;
2648 else if (GET_CODE (new_index_reg
) == PLUS
2649 && REG_P (XEXP (new_index_reg
, 0))
2650 && CONST_INT_P (XEXP (new_index_reg
, 1))
2651 && can_add_disp_p (ad
)
2652 && (scale
= get_index_scale (ad
)))
2654 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2655 *index_term
= XEXP (new_index_reg
, 0);
2661 if (ad
->disp
!= NULL
)
2662 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2665 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2666 update_address (ad
);
2670 if (lra_dump_file
!= NULL
)
2673 fprintf (lra_dump_file
, " -- no change\n");
2676 fprintf (lra_dump_file
, " on equiv ");
2677 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2678 fprintf (lra_dump_file
, "\n");
2684 /* Major function to make reloads for an address in operand NOP.
2685 The supported cases are:
2687 1) an address that existed before LRA started, at which point it
2688 must have been valid. These addresses are subject to elimination
2689 and may have become invalid due to the elimination offset being out
2692 2) an address created by forcing a constant to memory
2693 (force_const_to_mem). The initial form of these addresses might
2694 not be valid, and it is this function's job to make them valid.
2696 3) a frame address formed from a register and a (possibly zero)
2697 constant offset. As above, these addresses might not be valid and
2698 this function must make them so.
2700 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2701 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2702 address. Return true for any RTL change. */
2704 process_address (int nop
, rtx
*before
, rtx
*after
)
2706 struct address_info ad
;
2708 rtx op
= *curr_id
->operand_loc
[nop
];
2709 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2712 if (constraint
[0] == 'p'
2713 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2714 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2715 else if (MEM_P (op
))
2716 decompose_mem_address (&ad
, op
);
2717 else if (GET_CODE (op
) == SUBREG
2718 && MEM_P (SUBREG_REG (op
)))
2719 decompose_mem_address (&ad
, SUBREG_REG (op
));
2722 change_p
= equiv_address_substitution (&ad
);
2723 if (ad
.base_term
!= NULL
2724 && (process_addr_reg
2725 (ad
.base_term
, before
,
2727 && !(REG_P (*ad
.base_term
)
2728 && find_regno_note (curr_insn
, REG_DEAD
,
2729 REGNO (*ad
.base_term
)) != NULL_RTX
)
2731 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2732 get_index_code (&ad
)))))
2735 if (ad
.base_term2
!= NULL
)
2736 *ad
.base_term2
= *ad
.base_term
;
2738 if (ad
.index_term
!= NULL
2739 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2742 #ifdef EXTRA_CONSTRAINT_STR
2743 /* Target hooks sometimes reject extra constraint addresses -- use
2744 EXTRA_CONSTRAINT_STR for the validation. */
2745 if (constraint
[0] != 'p'
2746 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2747 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2751 /* There are three cases where the shape of *AD.INNER may now be invalid:
2753 1) the original address was valid, but either elimination or
2754 equiv_address_substitution was applied and that made
2755 the address invalid.
2757 2) the address is an invalid symbolic address created by
2760 3) the address is a frame address with an invalid offset.
2762 All these cases involve a non-autoinc address, so there is no
2763 point revalidating other types. */
2764 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2767 /* Any index existed before LRA started, so we can assume that the
2768 presence and shape of the index is valid. */
2769 push_to_sequence (*before
);
2770 lra_assert (ad
.disp
== ad
.disp_term
);
2771 if (ad
.base
== NULL
)
2773 if (ad
.index
== NULL
)
2776 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2778 rtx addr
= *ad
.inner
;
2780 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2784 rtx last
= get_last_insn ();
2786 /* addr => lo_sum (new_base, addr), case (2) above. */
2787 insn
= emit_insn (gen_rtx_SET
2789 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2790 code
= recog_memoized (insn
);
2793 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2794 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2796 /* Try to put lo_sum into register. */
2797 insn
= emit_insn (gen_rtx_SET
2799 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2800 code
= recog_memoized (insn
);
2803 *ad
.inner
= new_reg
;
2804 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2814 delete_insns_since (last
);
2819 /* addr => new_base, case (2) above. */
2820 lra_emit_move (new_reg
, addr
);
2821 *ad
.inner
= new_reg
;
2826 /* index * scale + disp => new base + index * scale,
2828 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2829 GET_CODE (*ad
.index
));
2831 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2832 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2833 lra_emit_move (new_reg
, *ad
.disp
);
2834 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2835 new_reg
, *ad
.index
);
2838 else if (ad
.index
== NULL
)
2842 rtx set
, insns
, last_insn
;
2843 /* base + disp => new base, cases (1) and (3) above. */
2844 /* Another option would be to reload the displacement into an
2845 index register. However, postreload has code to optimize
2846 address reloads that have the same base and different
2847 displacements, so reloading into an index register would
2848 not necessarily be a win. */
2850 new_reg
= base_plus_disp_to_reg (&ad
);
2851 insns
= get_insns ();
2852 last_insn
= get_last_insn ();
2853 /* If we generated at least two insns, try last insn source as
2854 an address. If we succeed, we generate one less insn. */
2855 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2856 && GET_CODE (SET_SRC (set
)) == PLUS
2857 && REG_P (XEXP (SET_SRC (set
), 0))
2858 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2860 *ad
.inner
= SET_SRC (set
);
2861 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2863 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2864 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2865 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2866 get_index_code (&ad
));
2867 regno
= REGNO (*ad
.base_term
);
2868 if (regno
>= FIRST_PSEUDO_REGISTER
2869 && cl
!= lra_get_allocno_class (regno
))
2870 lra_change_class (regno
, cl
, " Change to", true);
2871 new_reg
= SET_SRC (set
);
2872 delete_insns_since (PREV_INSN (last_insn
));
2877 *ad
.inner
= new_reg
;
2881 /* base + scale * index + disp => new base + scale * index,
2883 new_reg
= base_plus_disp_to_reg (&ad
);
2884 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2885 new_reg
, *ad
.index
);
2887 *before
= get_insns ();
2892 /* Emit insns to reload VALUE into a new register. VALUE is an
2893 auto-increment or auto-decrement RTX whose operand is a register or
2894 memory location; so reloading involves incrementing that location.
2895 IN is either identical to VALUE, or some cheaper place to reload
2896 value being incremented/decremented from.
2898 INC_AMOUNT is the number to increment or decrement by (always
2899 positive and ignored for POST_MODIFY/PRE_MODIFY).
2901 Return pseudo containing the result. */
2903 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2905 /* REG or MEM to be copied and incremented. */
2906 rtx incloc
= XEXP (value
, 0);
2907 /* Nonzero if increment after copying. */
2908 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2909 || GET_CODE (value
) == POST_MODIFY
);
2914 rtx real_in
= in
== value
? incloc
: in
;
2918 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2920 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2921 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2922 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2923 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2924 inc
= XEXP (XEXP (value
, 1), 1);
2928 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2929 inc_amount
= -inc_amount
;
2931 inc
= GEN_INT (inc_amount
);
2934 if (! post
&& REG_P (incloc
))
2937 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2940 if (real_in
!= result
)
2942 /* First copy the location to the result register. */
2943 lra_assert (REG_P (result
));
2944 emit_insn (gen_move_insn (result
, real_in
));
2947 /* We suppose that there are insns to add/sub with the constant
2948 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2949 old reload worked with this assumption. If the assumption
2950 becomes wrong, we should use approach in function
2951 base_plus_disp_to_reg. */
2954 /* See if we can directly increment INCLOC. */
2955 last
= get_last_insn ();
2956 add_insn
= emit_insn (plus_p
2957 ? gen_add2_insn (incloc
, inc
)
2958 : gen_sub2_insn (incloc
, inc
));
2960 code
= recog_memoized (add_insn
);
2963 if (! post
&& result
!= incloc
)
2964 emit_insn (gen_move_insn (result
, incloc
));
2967 delete_insns_since (last
);
2970 /* If couldn't do the increment directly, must increment in RESULT.
2971 The way we do this depends on whether this is pre- or
2972 post-increment. For pre-increment, copy INCLOC to the reload
2973 register, increment it there, then save back. */
2976 if (real_in
!= result
)
2977 emit_insn (gen_move_insn (result
, real_in
));
2979 emit_insn (gen_add2_insn (result
, inc
));
2981 emit_insn (gen_sub2_insn (result
, inc
));
2982 if (result
!= incloc
)
2983 emit_insn (gen_move_insn (incloc
, result
));
2989 Because this might be a jump insn or a compare, and because
2990 RESULT may not be available after the insn in an input
2991 reload, we must do the incrementing before the insn being
2994 We have already copied IN to RESULT. Increment the copy in
2995 RESULT, save that back, then decrement RESULT so it has
2996 the original value. */
2998 emit_insn (gen_add2_insn (result
, inc
));
3000 emit_insn (gen_sub2_insn (result
, inc
));
3001 emit_insn (gen_move_insn (incloc
, result
));
3002 /* Restore non-modified value for the result. We prefer this
3003 way because it does not require an additional hard
3007 if (CONST_INT_P (inc
))
3008 emit_insn (gen_add2_insn (result
,
3009 gen_int_mode (-INTVAL (inc
),
3010 GET_MODE (result
))));
3012 emit_insn (gen_sub2_insn (result
, inc
));
3015 emit_insn (gen_add2_insn (result
, inc
));
3020 /* Return true if the current move insn does not need processing as we
3021 already know that it satisfies its constraints. */
3023 simple_move_p (void)
3026 enum reg_class dclass
, sclass
;
3028 lra_assert (curr_insn_set
!= NULL_RTX
);
3029 dest
= SET_DEST (curr_insn_set
);
3030 src
= SET_SRC (curr_insn_set
);
3031 return ((dclass
= get_op_class (dest
)) != NO_REGS
3032 && (sclass
= get_op_class (src
)) != NO_REGS
3033 /* The backend guarantees that register moves of cost 2
3034 never need reloads. */
3035 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3038 /* Swap operands NOP and NOP + 1. */
3040 swap_operands (int nop
)
3042 enum machine_mode mode
= curr_operand_mode
[nop
];
3043 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3044 curr_operand_mode
[nop
+ 1] = mode
;
3045 rtx x
= *curr_id
->operand_loc
[nop
];
3046 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3047 *curr_id
->operand_loc
[nop
+ 1] = x
;
3048 /* Swap the duplicates too. */
3049 lra_update_dup (curr_id
, nop
);
3050 lra_update_dup (curr_id
, nop
+ 1);
3053 /* Main entry point of the constraint code: search the body of the
3054 current insn to choose the best alternative. It is mimicking insn
3055 alternative cost calculation model of former reload pass. That is
3056 because machine descriptions were written to use this model. This
3057 model can be changed in future. Make commutative operand exchange
3060 Return true if some RTL changes happened during function call. */
3062 curr_insn_transform (void)
3068 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3069 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3072 /* Flag that the insn has been changed through a transformation. */
3075 #ifdef SECONDARY_MEMORY_NEEDED
3078 int max_regno_before
;
3079 int reused_alternative_num
;
3081 curr_insn_set
= single_set (curr_insn
);
3082 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3085 no_input_reloads_p
= no_output_reloads_p
= false;
3086 goal_alt_number
= -1;
3087 change_p
= sec_mem_p
= false;
3088 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3089 reloads; neither are insns that SET cc0. Insns that use CC0 are
3090 not allowed to have any input reloads. */
3091 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3092 no_output_reloads_p
= true;
3095 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3096 no_input_reloads_p
= true;
3097 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3098 no_output_reloads_p
= true;
3101 n_operands
= curr_static_id
->n_operands
;
3102 n_alternatives
= curr_static_id
->n_alternatives
;
3104 /* Just return "no reloads" if insn has no operands with
3106 if (n_operands
== 0 || n_alternatives
== 0)
3109 max_regno_before
= max_reg_num ();
3111 for (i
= 0; i
< n_operands
; i
++)
3113 goal_alt_matched
[i
][0] = -1;
3114 goal_alt_matches
[i
] = -1;
3117 commutative
= curr_static_id
->commutative
;
3119 /* Now see what we need for pseudos that didn't get hard regs or got
3120 the wrong kind of hard reg. For this, we must consider all the
3121 operands together against the register constraints. */
3123 best_losers
= best_overall
= INT_MAX
;
3124 best_reload_sum
= 0;
3126 curr_swapped
= false;
3127 goal_alt_swapped
= false;
3129 /* Make equivalence substitution and memory subreg elimination
3130 before address processing because an address legitimacy can
3131 depend on memory mode. */
3132 for (i
= 0; i
< n_operands
; i
++)
3134 rtx op
= *curr_id
->operand_loc
[i
];
3135 rtx subst
, old
= op
;
3136 bool op_change_p
= false;
3138 if (GET_CODE (old
) == SUBREG
)
3139 old
= SUBREG_REG (old
);
3140 subst
= get_equiv_with_elimination (old
, curr_insn
);
3143 subst
= copy_rtx (subst
);
3144 lra_assert (REG_P (old
));
3145 if (GET_CODE (op
) == SUBREG
)
3146 SUBREG_REG (op
) = subst
;
3148 *curr_id
->operand_loc
[i
] = subst
;
3149 if (lra_dump_file
!= NULL
)
3151 fprintf (lra_dump_file
,
3152 "Changing pseudo %d in operand %i of insn %u on equiv ",
3153 REGNO (old
), i
, INSN_UID (curr_insn
));
3154 dump_value_slim (lra_dump_file
, subst
, 1);
3155 fprintf (lra_dump_file
, "\n");
3157 op_change_p
= change_p
= true;
3159 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3162 lra_update_dup (curr_id
, i
);
3166 /* Reload address registers and displacements. We do it before
3167 finding an alternative because of memory constraints. */
3168 before
= after
= NULL_RTX
;
3169 for (i
= 0; i
< n_operands
; i
++)
3170 if (! curr_static_id
->operand
[i
].is_operator
3171 && process_address (i
, &before
, &after
))
3174 lra_update_dup (curr_id
, i
);
3178 /* If we've changed the instruction then any alternative that
3179 we chose previously may no longer be valid. */
3180 lra_set_used_insn_alternative (curr_insn
, -1);
3182 if (curr_insn_set
!= NULL_RTX
3183 && check_and_process_move (&change_p
, &sec_mem_p
))
3188 reused_alternative_num
= curr_id
->used_insn_alternative
;
3189 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3190 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3191 reused_alternative_num
, INSN_UID (curr_insn
));
3193 if (process_alt_operands (reused_alternative_num
))
3196 /* If insn is commutative (it's safe to exchange a certain pair of
3197 operands) then we need to try each alternative twice, the second
3198 time matching those two operands as if we had exchanged them. To
3199 do this, really exchange them in operands.
3201 If we have just tried the alternatives the second time, return
3202 operands to normal and drop through. */
3204 if (reused_alternative_num
< 0 && commutative
>= 0)
3206 curr_swapped
= !curr_swapped
;
3209 swap_operands (commutative
);
3213 swap_operands (commutative
);
3216 if (! alt_p
&& ! sec_mem_p
)
3218 /* No alternative works with reloads?? */
3219 if (INSN_CODE (curr_insn
) >= 0)
3220 fatal_insn ("unable to generate reloads for:", curr_insn
);
3221 error_for_asm (curr_insn
,
3222 "inconsistent operand constraints in an %<asm%>");
3223 /* Avoid further trouble with this insn. */
3224 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3225 lra_invalidate_insn_data (curr_insn
);
3229 /* If the best alternative is with operands 1 and 2 swapped, swap
3230 them. Update the operand numbers of any reloads already
3233 if (goal_alt_swapped
)
3235 if (lra_dump_file
!= NULL
)
3236 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3237 INSN_UID (curr_insn
));
3239 /* Swap the duplicates too. */
3240 swap_operands (commutative
);
3244 #ifdef SECONDARY_MEMORY_NEEDED
3245 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3246 too conservatively. So we use the secondary memory only if there
3247 is no any alternative without reloads. */
3248 use_sec_mem_p
= false;
3250 use_sec_mem_p
= true;
3253 for (i
= 0; i
< n_operands
; i
++)
3254 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3256 use_sec_mem_p
= i
< n_operands
;
3261 rtx new_reg
, src
, dest
, rld
;
3262 enum machine_mode sec_mode
, rld_mode
;
3264 lra_assert (sec_mem_p
);
3265 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3266 && curr_static_id
->operand
[1].type
== OP_IN
);
3267 dest
= *curr_id
->operand_loc
[0];
3268 src
= *curr_id
->operand_loc
[1];
3269 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3271 rld_mode
= GET_MODE (rld
);
3272 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3273 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3275 sec_mode
= rld_mode
;
3277 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3278 NO_REGS
, "secondary");
3279 /* If the mode is changed, it should be wider. */
3280 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3281 if (sec_mode
!= rld_mode
)
3283 /* If the target says specifically to use another mode for
3284 secondary memory moves we can not reuse the original
3286 after
= emit_spill_move (false, new_reg
, dest
);
3287 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3288 "Inserting the sec. move");
3289 /* We may have non null BEFORE here (e.g. after address
3291 push_to_sequence (before
);
3292 before
= emit_spill_move (true, new_reg
, src
);
3294 before
= get_insns ();
3296 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3297 lra_set_insn_deleted (curr_insn
);
3299 else if (dest
== rld
)
3301 *curr_id
->operand_loc
[0] = new_reg
;
3302 after
= emit_spill_move (false, new_reg
, dest
);
3303 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3304 "Inserting the sec. move");
3308 *curr_id
->operand_loc
[1] = new_reg
;
3309 /* See comments above. */
3310 push_to_sequence (before
);
3311 before
= emit_spill_move (true, new_reg
, src
);
3313 before
= get_insns ();
3315 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3316 "Inserting the sec. move");
3318 lra_update_insn_regno_info (curr_insn
);
3323 lra_assert (goal_alt_number
>= 0);
3324 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3326 if (lra_dump_file
!= NULL
)
3330 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3331 goal_alt_number
, INSN_UID (curr_insn
));
3332 for (i
= 0; i
< n_operands
; i
++)
3334 p
= (curr_static_id
->operand_alternative
3335 [goal_alt_number
* n_operands
+ i
].constraint
);
3338 fprintf (lra_dump_file
, " (%d) ", i
);
3339 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3340 fputc (*p
, lra_dump_file
);
3342 if (INSN_CODE (curr_insn
) >= 0
3343 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3344 fprintf (lra_dump_file
, " {%s}", p
);
3345 if (curr_id
->sp_offset
!= 0)
3346 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3347 curr_id
->sp_offset
);
3348 fprintf (lra_dump_file
, "\n");
3351 /* Right now, for any pair of operands I and J that are required to
3352 match, with J < I, goal_alt_matches[I] is J. Add I to
3353 goal_alt_matched[J]. */
3355 for (i
= 0; i
< n_operands
; i
++)
3356 if ((j
= goal_alt_matches
[i
]) >= 0)
3358 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3360 /* We allow matching one output operand and several input
3363 || (curr_static_id
->operand
[j
].type
== OP_OUT
3364 && curr_static_id
->operand
[i
].type
== OP_IN
3365 && (curr_static_id
->operand
3366 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3367 goal_alt_matched
[j
][k
] = i
;
3368 goal_alt_matched
[j
][k
+ 1] = -1;
3371 for (i
= 0; i
< n_operands
; i
++)
3372 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3374 /* Any constants that aren't allowed and can't be reloaded into
3375 registers are here changed into memory references. */
3376 for (i
= 0; i
< n_operands
; i
++)
3377 if (goal_alt_win
[i
])
3380 enum reg_class new_class
;
3381 rtx reg
= *curr_id
->operand_loc
[i
];
3383 if (GET_CODE (reg
) == SUBREG
)
3384 reg
= SUBREG_REG (reg
);
3386 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3388 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3390 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3393 lra_change_class (regno
, new_class
, " Change to", true);
3399 const char *constraint
;
3401 rtx op
= *curr_id
->operand_loc
[i
];
3402 rtx subreg
= NULL_RTX
;
3403 enum machine_mode mode
= curr_operand_mode
[i
];
3405 if (GET_CODE (op
) == SUBREG
)
3408 op
= SUBREG_REG (op
);
3409 mode
= GET_MODE (op
);
3412 if (CONST_POOL_OK_P (mode
, op
)
3413 && ((targetm
.preferred_reload_class
3414 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3415 || no_input_reloads_p
))
3417 rtx tem
= force_const_mem (mode
, op
);
3420 if (subreg
!= NULL_RTX
)
3421 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3423 *curr_id
->operand_loc
[i
] = tem
;
3424 lra_update_dup (curr_id
, i
);
3425 process_address (i
, &before
, &after
);
3427 /* If the alternative accepts constant pool refs directly
3428 there will be no reload needed at all. */
3429 if (subreg
!= NULL_RTX
)
3431 /* Skip alternatives before the one requested. */
3432 constraint
= (curr_static_id
->operand_alternative
3433 [goal_alt_number
* n_operands
+ i
].constraint
);
3435 (c
= *constraint
) && c
!= ',' && c
!= '#';
3436 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3438 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3440 #ifdef EXTRA_CONSTRAINT_STR
3441 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3442 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3446 if (c
== '\0' || c
== ',' || c
== '#')
3449 goal_alt_win
[i
] = true;
3453 for (i
= 0; i
< n_operands
; i
++)
3456 bool optional_p
= false;
3458 rtx op
= *curr_id
->operand_loc
[i
];
3460 if (goal_alt_win
[i
])
3462 if (goal_alt
[i
] == NO_REGS
3464 /* When we assign NO_REGS it means that we will not
3465 assign a hard register to the scratch pseudo by
3466 assigment pass and the scratch pseudo will be
3467 spilled. Spilled scratch pseudos are transformed
3468 back to scratches at the LRA end. */
3469 && lra_former_scratch_operand_p (curr_insn
, i
))
3471 int regno
= REGNO (op
);
3472 lra_change_class (regno
, NO_REGS
, " Change to", true);
3473 if (lra_get_regno_hard_regno (regno
) >= 0)
3474 /* We don't have to mark all insn affected by the
3475 spilled pseudo as there is only one such insn, the
3477 reg_renumber
[regno
] = -1;
3479 /* We can do an optional reload. If the pseudo got a hard
3480 reg, we might improve the code through inheritance. If
3481 it does not get a hard register we coalesce memory/memory
3482 moves later. Ignore move insns to avoid cycling. */
3484 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3485 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3486 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3487 && regno
< new_regno_start
3488 && ! lra_former_scratch_p (regno
)
3489 && reg_renumber
[regno
] < 0
3490 && (curr_insn_set
== NULL_RTX
3491 || !((REG_P (SET_SRC (curr_insn_set
))
3492 || MEM_P (SET_SRC (curr_insn_set
))
3493 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3494 && (REG_P (SET_DEST (curr_insn_set
))
3495 || MEM_P (SET_DEST (curr_insn_set
))
3496 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3502 /* Operands that match previous ones have already been handled. */
3503 if (goal_alt_matches
[i
] >= 0)
3506 /* We should not have an operand with a non-offsettable address
3507 appearing where an offsettable address will do. It also may
3508 be a case when the address should be special in other words
3509 not a general one (e.g. it needs no index reg). */
3510 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3512 enum reg_class rclass
;
3513 rtx
*loc
= &XEXP (op
, 0);
3514 enum rtx_code code
= GET_CODE (*loc
);
3516 push_to_sequence (before
);
3517 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3519 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3520 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3521 /* This value does not matter for MODIFY. */
3522 GET_MODE_SIZE (GET_MODE (op
)));
3523 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3524 "offsetable address", &new_reg
))
3525 lra_emit_move (new_reg
, *loc
);
3526 before
= get_insns ();
3529 lra_update_dup (curr_id
, i
);
3531 else if (goal_alt_matched
[i
][0] == -1)
3533 enum machine_mode mode
;
3535 int hard_regno
, byte
;
3536 enum op_type type
= curr_static_id
->operand
[i
].type
;
3538 loc
= curr_id
->operand_loc
[i
];
3539 mode
= curr_operand_mode
[i
];
3540 if (GET_CODE (*loc
) == SUBREG
)
3542 reg
= SUBREG_REG (*loc
);
3543 byte
= SUBREG_BYTE (*loc
);
3545 /* Strict_low_part requires reload the register not
3546 the sub-register. */
3547 && (curr_static_id
->operand
[i
].strict_low
3548 || (GET_MODE_SIZE (mode
)
3549 <= GET_MODE_SIZE (GET_MODE (reg
))
3551 = get_try_hard_regno (REGNO (reg
))) >= 0
3552 && (simplify_subreg_regno
3554 GET_MODE (reg
), byte
, mode
) < 0)
3555 && (goal_alt
[i
] == NO_REGS
3556 || (simplify_subreg_regno
3557 (ira_class_hard_regs
[goal_alt
[i
]][0],
3558 GET_MODE (reg
), byte
, mode
) >= 0)))))
3560 loc
= &SUBREG_REG (*loc
);
3561 mode
= GET_MODE (*loc
);
3565 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3568 push_to_sequence (before
);
3569 lra_emit_move (new_reg
, old
);
3570 before
= get_insns ();
3575 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3578 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3580 after
= get_insns ();
3584 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3585 if (goal_alt_dont_inherit_ops
[j
] == i
)
3587 lra_set_regno_unique_value (REGNO (new_reg
));
3590 lra_update_dup (curr_id
, i
);
3592 else if (curr_static_id
->operand
[i
].type
== OP_IN
3593 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3596 /* generate reloads for input and matched outputs. */
3597 match_inputs
[0] = i
;
3598 match_inputs
[1] = -1;
3599 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3600 goal_alt
[i
], &before
, &after
);
3602 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3603 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3605 /* Generate reloads for output and matched inputs. */
3606 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3607 else if (curr_static_id
->operand
[i
].type
== OP_IN
3608 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3611 /* Generate reloads for matched inputs. */
3612 match_inputs
[0] = i
;
3613 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3614 match_inputs
[j
+ 1] = k
;
3615 match_inputs
[j
+ 1] = -1;
3616 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3619 /* We must generate code in any case when function
3620 process_alt_operands decides that it is possible. */
3624 lra_assert (REG_P (op
));
3626 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3627 if (GET_CODE (op
) == SUBREG
)
3628 op
= SUBREG_REG (op
);
3629 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3630 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3631 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3632 if (lra_dump_file
!= NULL
)
3633 fprintf (lra_dump_file
,
3634 " Making reload reg %d for reg %d optional\n",
3638 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3639 || max_regno_before
!= max_reg_num ())
3643 lra_update_operator_dups (curr_id
);
3644 /* Something changes -- process the insn. */
3645 lra_update_insn_regno_info (curr_insn
);
3647 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3651 /* Return true if X is in LIST. */
3653 in_list_p (rtx x
, rtx list
)
3655 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3656 if (XEXP (list
, 0) == x
)
3661 /* Return true if X contains an allocatable hard register (if
3662 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3664 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3670 code
= GET_CODE (x
);
3673 int regno
= REGNO (x
);
3674 HARD_REG_SET alloc_regs
;
3678 if (regno
>= FIRST_PSEUDO_REGISTER
)
3679 regno
= lra_get_regno_hard_regno (regno
);
3682 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3683 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3687 if (regno
< FIRST_PSEUDO_REGISTER
)
3691 return lra_get_regno_hard_regno (regno
) < 0;
3694 fmt
= GET_RTX_FORMAT (code
);
3695 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3699 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3702 else if (fmt
[i
] == 'E')
3704 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3705 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3712 /* Process all regs in location *LOC and change them on equivalent
3713 substitution. Return true if any change was done. */
3715 loc_equivalence_change_p (rtx
*loc
)
3717 rtx subst
, reg
, x
= *loc
;
3718 bool result
= false;
3719 enum rtx_code code
= GET_CODE (x
);
3725 reg
= SUBREG_REG (x
);
3726 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3727 && GET_MODE (subst
) == VOIDmode
)
3729 /* We cannot reload debug location. Simplify subreg here
3730 while we know the inner mode. */
3731 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3732 GET_MODE (reg
), SUBREG_BYTE (x
));
3736 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3742 /* Scan all the operand sub-expressions. */
3743 fmt
= GET_RTX_FORMAT (code
);
3744 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3747 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3748 else if (fmt
[i
] == 'E')
3749 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3751 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3756 /* Similar to loc_equivalence_change_p, but for use as
3757 simplify_replace_fn_rtx callback. DATA is insn for which the
3758 elimination is done. If it null we don't do the elimination. */
3760 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3765 rtx subst
= (data
== NULL
3766 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx
) data
));
3773 /* Maximum number of generated reload insns per an insn. It is for
3774 preventing this pass cycling in a bug case. */
3775 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3777 /* The current iteration number of this LRA pass. */
3778 int lra_constraint_iter
;
3780 /* The current iteration number of this LRA pass after the last spill
3782 int lra_constraint_iter_after_spill
;
3784 /* True if we substituted equiv which needs checking register
3785 allocation correctness because the equivalent value contains
3786 allocatable hard registers or when we restore multi-register
3788 bool lra_risky_transformations_p
;
3790 /* Return true if REGNO is referenced in more than one block. */
3792 multi_block_pseudo_p (int regno
)
3794 basic_block bb
= NULL
;
3798 if (regno
< FIRST_PSEUDO_REGISTER
)
3801 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3803 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3804 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3809 /* Return true if LIST contains a deleted insn. */
3811 contains_deleted_insn_p (rtx list
)
3813 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3814 if (NOTE_P (XEXP (list
, 0))
3815 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3820 /* Return true if X contains a pseudo dying in INSN. */
3822 dead_pseudo_p (rtx x
, rtx insn
)
3829 return (insn
!= NULL_RTX
3830 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3831 code
= GET_CODE (x
);
3832 fmt
= GET_RTX_FORMAT (code
);
3833 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3837 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3840 else if (fmt
[i
] == 'E')
3842 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3843 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3850 /* Return true if INSN contains a dying pseudo in INSN right hand
3853 insn_rhs_dead_pseudo_p (rtx insn
)
3855 rtx set
= single_set (insn
);
3857 gcc_assert (set
!= NULL
);
3858 return dead_pseudo_p (SET_SRC (set
), insn
);
3861 /* Return true if any init insn of REGNO contains a dying pseudo in
3862 insn right hand side. */
3864 init_insn_rhs_dead_pseudo_p (int regno
)
3866 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3871 return insn_rhs_dead_pseudo_p (insns
);
3872 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3873 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3878 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3879 reverse only if we have one init insn with given REGNO as a
3882 reverse_equiv_p (int regno
)
3886 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3888 if (! INSN_P (XEXP (insns
, 0))
3889 || XEXP (insns
, 1) != NULL_RTX
)
3891 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3893 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3896 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3897 call this function only for non-reverse equivalence. */
3899 contains_reloaded_insn_p (int regno
)
3902 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3904 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3905 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3906 || ! REG_P (SET_DEST (set
))
3907 || (int) REGNO (SET_DEST (set
)) != regno
)
3912 /* Entry function of LRA constraint pass. Return true if the
3913 constraint pass did change the code. */
3915 lra_constraints (bool first_p
)
3918 int i
, hard_regno
, new_insns_num
;
3919 unsigned int min_len
, new_min_len
, uid
;
3920 rtx set
, x
, reg
, dest_reg
;
3921 basic_block last_bb
;
3922 bitmap_head equiv_insn_bitmap
;
3925 lra_constraint_iter
++;
3926 if (lra_dump_file
!= NULL
)
3927 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3928 lra_constraint_iter
);
3929 lra_constraint_iter_after_spill
++;
3930 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3932 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3933 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3935 lra_risky_transformations_p
= false;
3936 new_insn_uid_start
= get_max_uid ();
3937 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3938 /* Mark used hard regs for target stack size calulations. */
3939 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3940 if (lra_reg_info
[i
].nrefs
!= 0
3941 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3945 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3946 for (j
= 0; j
< nregs
; j
++)
3947 df_set_regs_ever_live (hard_regno
+ j
, true);
3949 /* Do elimination before the equivalence processing as we can spill
3950 some pseudos during elimination. */
3951 lra_eliminate (false, first_p
);
3952 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3953 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3954 if (lra_reg_info
[i
].nrefs
!= 0)
3956 ira_reg_equiv
[i
].profitable_p
= true;
3957 reg
= regno_reg_rtx
[i
];
3958 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
3960 bool pseudo_p
= contains_reg_p (x
, false, false);
3962 /* After RTL transformation, we can not guarantee that
3963 pseudo in the substitution was not reloaded which might
3964 make equivalence invalid. For example, in reverse
3971 the memory address register was reloaded before the 2nd
3973 if ((! first_p
&& pseudo_p
)
3974 /* We don't use DF for compilation speed sake. So it
3975 is problematic to update live info when we use an
3976 equivalence containing pseudos in more than one
3978 || (pseudo_p
&& multi_block_pseudo_p (i
))
3979 /* If an init insn was deleted for some reason, cancel
3980 the equiv. We could update the equiv insns after
3981 transformations including an equiv insn deletion
3982 but it is not worthy as such cases are extremely
3984 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
3985 /* If it is not a reverse equivalence, we check that a
3986 pseudo in rhs of the init insn is not dying in the
3987 insn. Otherwise, the live info at the beginning of
3988 the corresponding BB might be wrong after we
3989 removed the insn. When the equiv can be a
3990 constant, the right hand side of the init insn can
3992 || (! reverse_equiv_p (i
)
3993 && (init_insn_rhs_dead_pseudo_p (i
)
3994 /* If we reloaded the pseudo in an equivalence
3995 init insn, we can not remove the equiv init
3996 insns and the init insns might write into
3997 const memory in this case. */
3998 || contains_reloaded_insn_p (i
)))
3999 /* Prevent access beyond equivalent memory for
4000 paradoxical subregs. */
4002 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4003 > GET_MODE_SIZE (GET_MODE (x
)))))
4004 ira_reg_equiv
[i
].defined_p
= false;
4005 if (contains_reg_p (x
, false, true))
4006 ira_reg_equiv
[i
].profitable_p
= false;
4007 if (get_equiv (reg
) != reg
)
4008 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4011 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4013 /* We should add all insns containing pseudos which should be
4014 substituted by their equivalences. */
4015 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4016 lra_push_insn_by_uid (uid
);
4017 min_len
= lra_insn_stack_length ();
4021 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4023 curr_insn
= lra_pop_insn ();
4025 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4026 if (curr_bb
!= last_bb
)
4029 bb_reload_num
= lra_curr_reload_num
;
4031 if (min_len
> new_min_len
)
4033 min_len
= new_min_len
;
4036 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4038 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4039 MAX_RELOAD_INSNS_NUMBER
);
4041 if (DEBUG_INSN_P (curr_insn
))
4043 /* We need to check equivalence in debug insn and change
4044 pseudo to the equivalent value if necessary. */
4045 curr_id
= lra_get_insn_recog_data (curr_insn
);
4046 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4048 rtx old
= *curr_id
->operand_loc
[0];
4049 *curr_id
->operand_loc
[0]
4050 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4051 loc_equivalence_callback
, curr_insn
);
4052 if (old
!= *curr_id
->operand_loc
[0])
4054 lra_update_insn_regno_info (curr_insn
);
4059 else if (INSN_P (curr_insn
))
4061 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4063 dest_reg
= SET_DEST (set
);
4064 /* The equivalence pseudo could be set up as SUBREG in a
4065 case when it is a call restore insn in a mode
4066 different from the pseudo mode. */
4067 if (GET_CODE (dest_reg
) == SUBREG
)
4068 dest_reg
= SUBREG_REG (dest_reg
);
4069 if ((REG_P (dest_reg
)
4070 && (x
= get_equiv (dest_reg
)) != dest_reg
4071 /* Remove insns which set up a pseudo whose value
4072 can not be changed. Such insns might be not in
4073 init_insns because we don't update equiv data
4074 during insn transformations.
4076 As an example, let suppose that a pseudo got
4077 hard register and on the 1st pass was not
4078 changed to equivalent constant. We generate an
4079 additional insn setting up the pseudo because of
4080 secondary memory movement. Then the pseudo is
4081 spilled and we use the equiv constant. In this
4082 case we should remove the additional insn and
4083 this insn is not init_insns list. */
4084 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4085 /* Check that this is actually an insn setting
4086 up the equivalence. */
4087 || in_list_p (curr_insn
,
4089 [REGNO (dest_reg
)].init_insns
)))
4090 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4091 && in_list_p (curr_insn
,
4093 [REGNO (SET_SRC (set
))].init_insns
)))
4095 /* This is equiv init insn of pseudo which did not get a
4096 hard register -- remove the insn. */
4097 if (lra_dump_file
!= NULL
)
4099 fprintf (lra_dump_file
,
4100 " Removing equiv init insn %i (freq=%d)\n",
4101 INSN_UID (curr_insn
),
4102 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4103 dump_insn_slim (lra_dump_file
, curr_insn
);
4105 if (contains_reg_p (x
, true, false))
4106 lra_risky_transformations_p
= true;
4107 lra_set_insn_deleted (curr_insn
);
4111 curr_id
= lra_get_insn_recog_data (curr_insn
);
4112 curr_static_id
= curr_id
->insn_static_data
;
4113 init_curr_insn_input_reloads ();
4114 init_curr_operand_mode ();
4115 if (curr_insn_transform ())
4117 /* Check non-transformed insns too for equiv change as USE
4118 or CLOBBER don't need reloads but can contain pseudos
4119 being changed on their equivalences. */
4120 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4121 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4123 lra_update_insn_regno_info (curr_insn
);
4128 bitmap_clear (&equiv_insn_bitmap
);
4129 /* If we used a new hard regno, changed_p should be true because the
4130 hard reg is assigned to a new pseudo. */
4131 #ifdef ENABLE_CHECKING
4134 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4135 if (lra_reg_info
[i
].nrefs
!= 0
4136 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4138 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4140 for (j
= 0; j
< nregs
; j
++)
4141 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4148 /* Initiate the LRA constraint pass. It is done once per
4151 lra_constraints_init (void)
4155 /* Finalize the LRA constraint pass. It is done once per
4158 lra_constraints_finish (void)
4164 /* This page contains code to do inheritance/split
4167 /* Number of reloads passed so far in current EBB. */
4168 static int reloads_num
;
4170 /* Number of calls passed so far in current EBB. */
4171 static int calls_num
;
4173 /* Current reload pseudo check for validity of elements in
4175 static int curr_usage_insns_check
;
4177 /* Info about last usage of registers in EBB to do inheritance/split
4178 transformation. Inheritance transformation is done from a spilled
4179 pseudo and split transformations from a hard register or a pseudo
4180 assigned to a hard register. */
4183 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4184 value INSNS is valid. The insns is chain of optional debug insns
4185 and a finishing non-debug insn using the corresponding reg. The
4186 value is also used to mark the registers which are set up in the
4187 current insn. The negated insn uid is used for this. */
4189 /* Value of global reloads_num at the last insn in INSNS. */
4191 /* Value of global reloads_nums at the last insn in INSNS. */
4193 /* It can be true only for splitting. And it means that the restore
4194 insn should be put after insn given by the following member. */
4196 /* Next insns in the current EBB which use the original reg and the
4197 original reg value is not changed between the current insn and
4198 the next insns. In order words, e.g. for inheritance, if we need
4199 to use the original reg value again in the next insns we can try
4200 to use the value in a hard register from a reload insn of the
4205 /* Map: regno -> corresponding pseudo usage insns. */
4206 static struct usage_insns
*usage_insns
;
4209 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4211 usage_insns
[regno
].check
= curr_usage_insns_check
;
4212 usage_insns
[regno
].insns
= insn
;
4213 usage_insns
[regno
].reloads_num
= reloads_num
;
4214 usage_insns
[regno
].calls_num
= calls_num
;
4215 usage_insns
[regno
].after_p
= after_p
;
4218 /* The function is used to form list REGNO usages which consists of
4219 optional debug insns finished by a non-debug insn using REGNO.
4220 RELOADS_NUM is current number of reload insns processed so far. */
4222 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4224 rtx next_usage_insns
;
4226 if (usage_insns
[regno
].check
== curr_usage_insns_check
4227 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4228 && DEBUG_INSN_P (insn
))
4230 /* Check that we did not add the debug insn yet. */
4231 if (next_usage_insns
!= insn
4232 && (GET_CODE (next_usage_insns
) != INSN_LIST
4233 || XEXP (next_usage_insns
, 0) != insn
))
4234 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4237 else if (NONDEBUG_INSN_P (insn
))
4238 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4240 usage_insns
[regno
].check
= 0;
4243 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4244 register NEW_REG. Return true if any change was made. */
4246 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4249 bool result
= false;
4257 code
= GET_CODE (x
);
4258 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4260 enum machine_mode mode
= GET_MODE (*loc
);
4261 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4263 if (mode
!= inner_mode
)
4265 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4266 || ! SCALAR_INT_MODE_P (inner_mode
))
4267 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4269 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4275 /* Scan all the operand sub-expressions. */
4276 fmt
= GET_RTX_FORMAT (code
);
4277 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4281 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4284 else if (fmt
[i
] == 'E')
4286 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4287 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4294 /* Return first non-debug insn in list USAGE_INSNS. */
4296 skip_usage_debug_insns (rtx usage_insns
)
4300 /* Skip debug insns. */
4301 for (insn
= usage_insns
;
4302 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4303 insn
= XEXP (insn
, 1))
4308 /* Return true if we need secondary memory moves for insn in
4309 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4312 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4313 rtx usage_insns ATTRIBUTE_UNUSED
)
4315 #ifndef SECONDARY_MEMORY_NEEDED
4318 rtx insn
, set
, dest
;
4321 if (inher_cl
== ALL_REGS
4322 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4324 lra_assert (INSN_P (insn
));
4325 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4327 dest
= SET_DEST (set
);
4330 lra_assert (inher_cl
!= NO_REGS
);
4331 cl
= get_reg_class (REGNO (dest
));
4332 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4333 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4337 /* Registers involved in inheritance/split in the current EBB
4338 (inheritance/split pseudos and original registers). */
4339 static bitmap_head check_only_regs
;
4341 /* Do inheritance transformations for insn INSN, which defines (if
4342 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4343 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4344 form as the "insns" field of usage_insns. Return true if we
4345 succeed in such transformation.
4347 The transformations look like:
4350 ... p <- i (new insn)
4352 <- ... p ... <- ... i ...
4354 ... i <- p (new insn)
4355 <- ... p ... <- ... i ...
4357 <- ... p ... <- ... i ...
4358 where p is a spilled original pseudo and i is a new inheritance pseudo.
4361 The inheritance pseudo has the smallest class of two classes CL and
4362 class of ORIGINAL REGNO. */
4364 inherit_reload_reg (bool def_p
, int original_regno
,
4365 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4367 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4368 rtx original_reg
= regno_reg_rtx
[original_regno
];
4369 rtx new_reg
, new_insns
, usage_insn
;
4371 lra_assert (! usage_insns
[original_regno
].after_p
);
4372 if (lra_dump_file
!= NULL
)
4373 fprintf (lra_dump_file
,
4374 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4375 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4377 if (lra_dump_file
!= NULL
)
4379 fprintf (lra_dump_file
,
4380 " Rejecting inheritance for %d "
4381 "because of disjoint classes %s and %s\n",
4382 original_regno
, reg_class_names
[cl
],
4383 reg_class_names
[rclass
]);
4384 fprintf (lra_dump_file
,
4385 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4389 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4390 /* We don't use a subset of two classes because it can be
4391 NO_REGS. This transformation is still profitable in most
4392 cases even if the classes are not intersected as register
4393 move is probably cheaper than a memory load. */
4394 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4396 if (lra_dump_file
!= NULL
)
4397 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4398 reg_class_names
[cl
], reg_class_names
[rclass
]);
4402 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4404 /* Reject inheritance resulting in secondary memory moves.
4405 Otherwise, there is a danger in LRA cycling. Also such
4406 transformation will be unprofitable. */
4407 if (lra_dump_file
!= NULL
)
4409 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4410 rtx set
= single_set (insn
);
4412 lra_assert (set
!= NULL_RTX
);
4414 rtx dest
= SET_DEST (set
);
4416 lra_assert (REG_P (dest
));
4417 fprintf (lra_dump_file
,
4418 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4419 "as secondary mem is needed\n",
4420 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4421 original_regno
, reg_class_names
[rclass
]);
4422 fprintf (lra_dump_file
,
4423 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4427 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4428 rclass
, "inheritance");
4431 emit_move_insn (original_reg
, new_reg
);
4433 emit_move_insn (new_reg
, original_reg
);
4434 new_insns
= get_insns ();
4436 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4438 if (lra_dump_file
!= NULL
)
4440 fprintf (lra_dump_file
,
4441 " Rejecting inheritance %d->%d "
4442 "as it results in 2 or more insns:\n",
4443 original_regno
, REGNO (new_reg
));
4444 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4445 fprintf (lra_dump_file
,
4446 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4450 substitute_pseudo (&insn
, original_regno
, new_reg
);
4451 lra_update_insn_regno_info (insn
);
4453 /* We now have a new usage insn for original regno. */
4454 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4455 if (lra_dump_file
!= NULL
)
4456 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4457 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4458 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4459 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4460 bitmap_set_bit (&check_only_regs
, original_regno
);
4461 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4463 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4464 "Add original<-inheritance");
4466 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4467 "Add inheritance<-original");
4468 while (next_usage_insns
!= NULL_RTX
)
4470 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4472 usage_insn
= next_usage_insns
;
4473 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4474 next_usage_insns
= NULL
;
4478 usage_insn
= XEXP (next_usage_insns
, 0);
4479 lra_assert (DEBUG_INSN_P (usage_insn
));
4480 next_usage_insns
= XEXP (next_usage_insns
, 1);
4482 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4483 lra_update_insn_regno_info (usage_insn
);
4484 if (lra_dump_file
!= NULL
)
4486 fprintf (lra_dump_file
,
4487 " Inheritance reuse change %d->%d (bb%d):\n",
4488 original_regno
, REGNO (new_reg
),
4489 BLOCK_FOR_INSN (usage_insn
)->index
);
4490 dump_insn_slim (lra_dump_file
, usage_insn
);
4493 if (lra_dump_file
!= NULL
)
4494 fprintf (lra_dump_file
,
4495 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4499 /* Return true if we need a caller save/restore for pseudo REGNO which
4500 was assigned to a hard register. */
4502 need_for_call_save_p (int regno
)
4504 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4505 return (usage_insns
[regno
].calls_num
< calls_num
4506 && (overlaps_hard_reg_set_p
4508 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4509 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4510 PSEUDO_REGNO_MODE (regno
))));
4513 /* Global registers occurring in the current EBB. */
4514 static bitmap_head ebb_global_regs
;
4516 /* Return true if we need a split for hard register REGNO or pseudo
4517 REGNO which was assigned to a hard register.
4518 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4519 used for reloads since the EBB end. It is an approximation of the
4520 used hard registers in the split range. The exact value would
4521 require expensive calculations. If we were aggressive with
4522 splitting because of the approximation, the split pseudo will save
4523 the same hard register assignment and will be removed in the undo
4524 pass. We still need the approximation because too aggressive
4525 splitting would result in too inaccurate cost calculation in the
4526 assignment pass because of too many generated moves which will be
4527 probably removed in the undo pass. */
4529 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4531 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4533 lra_assert (hard_regno
>= 0);
4534 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4535 /* Don't split eliminable hard registers, otherwise we can
4536 split hard registers like hard frame pointer, which
4537 lives on BB start/end according to DF-infrastructure,
4538 when there is a pseudo assigned to the register and
4539 living in the same BB. */
4540 && (regno
>= FIRST_PSEUDO_REGISTER
4541 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4542 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4543 /* Don't split call clobbered hard regs living through
4544 calls, otherwise we might have a check problem in the
4545 assign sub-pass as in the most cases (exception is a
4546 situation when lra_risky_transformations_p value is
4547 true) the assign pass assumes that all pseudos living
4548 through calls are assigned to call saved hard regs. */
4549 && (regno
>= FIRST_PSEUDO_REGISTER
4550 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4551 || usage_insns
[regno
].calls_num
== calls_num
)
4552 /* We need at least 2 reloads to make pseudo splitting
4553 profitable. We should provide hard regno splitting in
4554 any case to solve 1st insn scheduling problem when
4555 moving hard register definition up might result in
4556 impossibility to find hard register for reload pseudo of
4557 small register class. */
4558 && (usage_insns
[regno
].reloads_num
4559 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4560 && (regno
< FIRST_PSEUDO_REGISTER
4561 /* For short living pseudos, spilling + inheritance can
4562 be considered a substitution for splitting.
4563 Therefore we do not splitting for local pseudos. It
4564 decreases also aggressiveness of splitting. The
4565 minimal number of references is chosen taking into
4566 account that for 2 references splitting has no sense
4567 as we can just spill the pseudo. */
4568 || (regno
>= FIRST_PSEUDO_REGISTER
4569 && lra_reg_info
[regno
].nrefs
> 3
4570 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4571 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4574 /* Return class for the split pseudo created from original pseudo with
4575 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4576 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4577 results in no secondary memory movements. */
4578 static enum reg_class
4579 choose_split_class (enum reg_class allocno_class
,
4580 int hard_regno ATTRIBUTE_UNUSED
,
4581 enum machine_mode mode ATTRIBUTE_UNUSED
)
4583 #ifndef SECONDARY_MEMORY_NEEDED
4584 return allocno_class
;
4587 enum reg_class cl
, best_cl
= NO_REGS
;
4588 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4589 = REGNO_REG_CLASS (hard_regno
);
4591 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4592 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4593 return allocno_class
;
4595 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4597 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4598 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4599 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4600 && (best_cl
== NO_REGS
4601 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4607 /* Do split transformations for insn INSN, which defines or uses
4608 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4609 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4610 "insns" field of usage_insns.
4612 The transformations look like:
4615 ... s <- p (new insn -- save)
4617 ... p <- s (new insn -- restore)
4618 <- ... p ... <- ... p ...
4620 <- ... p ... <- ... p ...
4621 ... s <- p (new insn -- save)
4623 ... p <- s (new insn -- restore)
4624 <- ... p ... <- ... p ...
4626 where p is an original pseudo got a hard register or a hard
4627 register and s is a new split pseudo. The save is put before INSN
4628 if BEFORE_P is true. Return true if we succeed in such
4631 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4633 enum reg_class rclass
;
4635 int hard_regno
, nregs
;
4636 rtx new_reg
, save
, restore
, usage_insn
;
4640 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4642 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4643 hard_regno
= original_regno
;
4644 call_save_p
= false;
4649 hard_regno
= reg_renumber
[original_regno
];
4650 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4651 rclass
= lra_get_allocno_class (original_regno
);
4652 original_reg
= regno_reg_rtx
[original_regno
];
4653 call_save_p
= need_for_call_save_p (original_regno
);
4655 original_reg
= regno_reg_rtx
[original_regno
];
4656 lra_assert (hard_regno
>= 0);
4657 if (lra_dump_file
!= NULL
)
4658 fprintf (lra_dump_file
,
4659 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4662 enum machine_mode mode
= GET_MODE (original_reg
);
4664 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4665 hard_regno_nregs
[hard_regno
][mode
],
4667 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4671 rclass
= choose_split_class (rclass
, hard_regno
,
4672 GET_MODE (original_reg
));
4673 if (rclass
== NO_REGS
)
4675 if (lra_dump_file
!= NULL
)
4677 fprintf (lra_dump_file
,
4678 " Rejecting split of %d(%s): "
4679 "no good reg class for %d(%s)\n",
4681 reg_class_names
[lra_get_allocno_class (original_regno
)],
4683 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4686 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4690 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4692 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4694 save
= emit_spill_move (true, new_reg
, original_reg
);
4695 if (NEXT_INSN (save
) != NULL_RTX
)
4697 lra_assert (! call_save_p
);
4698 if (lra_dump_file
!= NULL
)
4702 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4703 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4704 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4705 fprintf (lra_dump_file
,
4706 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4710 restore
= emit_spill_move (false, new_reg
, original_reg
);
4711 if (NEXT_INSN (restore
) != NULL_RTX
)
4713 lra_assert (! call_save_p
);
4714 if (lra_dump_file
!= NULL
)
4716 fprintf (lra_dump_file
,
4717 " Rejecting split %d->%d "
4718 "resulting in > 2 %s restore insns:\n",
4719 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4720 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4721 fprintf (lra_dump_file
,
4722 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4726 after_p
= usage_insns
[original_regno
].after_p
;
4727 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4728 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4729 bitmap_set_bit (&check_only_regs
, original_regno
);
4730 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4733 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4735 usage_insn
= next_usage_insns
;
4738 usage_insn
= XEXP (next_usage_insns
, 0);
4739 lra_assert (DEBUG_INSN_P (usage_insn
));
4740 next_usage_insns
= XEXP (next_usage_insns
, 1);
4741 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4742 lra_update_insn_regno_info (usage_insn
);
4743 if (lra_dump_file
!= NULL
)
4745 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4746 original_regno
, REGNO (new_reg
));
4747 dump_insn_slim (lra_dump_file
, usage_insn
);
4750 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4751 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4752 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4753 after_p
? restore
: NULL_RTX
,
4755 ? "Add reg<-save" : "Add reg<-split");
4756 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4757 before_p
? NULL_RTX
: save
,
4759 ? "Add save<-reg" : "Add split<-reg");
4761 /* If we are trying to split multi-register. We should check
4762 conflicts on the next assignment sub-pass. IRA can allocate on
4763 sub-register levels, LRA do this on pseudos level right now and
4764 this discrepancy may create allocation conflicts after
4766 lra_risky_transformations_p
= true;
4767 if (lra_dump_file
!= NULL
)
4768 fprintf (lra_dump_file
,
4769 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4773 /* Recognize that we need a split transformation for insn INSN, which
4774 defines or uses REGNO in its insn biggest MODE (we use it only if
4775 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4776 hard registers which might be used for reloads since the EBB end.
4777 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4778 uid before starting INSN processing. Return true if we succeed in
4779 such transformation. */
4781 split_if_necessary (int regno
, enum machine_mode mode
,
4782 HARD_REG_SET potential_reload_hard_regs
,
4783 bool before_p
, rtx insn
, int max_uid
)
4787 rtx next_usage_insns
;
4789 if (regno
< FIRST_PSEUDO_REGISTER
)
4790 nregs
= hard_regno_nregs
[regno
][mode
];
4791 for (i
= 0; i
< nregs
; i
++)
4792 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4793 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4794 /* To avoid processing the register twice or more. */
4795 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4796 && INSN_UID (next_usage_insns
) < max_uid
)
4797 || (GET_CODE (next_usage_insns
) == INSN_LIST
4798 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4799 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4800 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4805 /* Check only registers living at the current program point in the
4807 static bitmap_head live_regs
;
4809 /* Update live info in EBB given by its HEAD and TAIL insns after
4810 inheritance/split transformation. The function removes dead moves
4813 update_ebb_live_info (rtx head
, rtx tail
)
4820 basic_block last_bb
, prev_bb
, curr_bb
;
4822 struct lra_insn_reg
*reg
;
4826 last_bb
= BLOCK_FOR_INSN (tail
);
4828 for (curr_insn
= tail
;
4829 curr_insn
!= PREV_INSN (head
);
4830 curr_insn
= prev_insn
)
4832 prev_insn
= PREV_INSN (curr_insn
);
4833 /* We need to process empty blocks too. They contain
4834 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4835 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4837 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4838 if (curr_bb
!= prev_bb
)
4840 if (prev_bb
!= NULL
)
4842 /* Update df_get_live_in (prev_bb): */
4843 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4844 if (bitmap_bit_p (&live_regs
, j
))
4845 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4847 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4849 if (curr_bb
!= last_bb
)
4851 /* Update df_get_live_out (curr_bb): */
4852 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4854 live_p
= bitmap_bit_p (&live_regs
, j
);
4856 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4857 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4863 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4865 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4869 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4871 if (! NONDEBUG_INSN_P (curr_insn
))
4873 curr_id
= lra_get_insn_recog_data (curr_insn
);
4875 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4876 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4877 && bitmap_bit_p (&check_only_regs
, regno
)
4878 && ! bitmap_bit_p (&live_regs
, regno
))
4880 /* See which defined values die here. */
4881 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4882 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4883 bitmap_clear_bit (&live_regs
, reg
->regno
);
4884 /* Mark each used value as live. */
4885 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4886 if (reg
->type
!= OP_OUT
4887 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4888 bitmap_set_bit (&live_regs
, reg
->regno
);
4889 /* It is quite important to remove dead move insns because it
4890 means removing dead store. We don't need to process them for
4894 if (lra_dump_file
!= NULL
)
4896 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4897 dump_insn_slim (lra_dump_file
, curr_insn
);
4899 lra_set_insn_deleted (curr_insn
);
4904 /* The structure describes info to do an inheritance for the current
4905 insn. We need to collect such info first before doing the
4906 transformations because the transformations change the insn
4907 internal representation. */
4910 /* Original regno. */
4912 /* Subsequent insns which can inherit original reg value. */
4916 /* Array containing all info for doing inheritance from the current
4918 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4920 /* Number elements in the previous array. */
4921 static int to_inherit_num
;
4923 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4924 structure to_inherit. */
4926 add_to_inherit (int regno
, rtx insns
)
4930 for (i
= 0; i
< to_inherit_num
; i
++)
4931 if (to_inherit
[i
].regno
== regno
)
4933 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4934 to_inherit
[to_inherit_num
].regno
= regno
;
4935 to_inherit
[to_inherit_num
++].insns
= insns
;
4938 /* Return the last non-debug insn in basic block BB, or the block begin
4941 get_last_insertion_point (basic_block bb
)
4945 FOR_BB_INSNS_REVERSE (bb
, insn
)
4946 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4951 /* Set up RES by registers living on edges FROM except the edge (FROM,
4952 TO) or by registers set up in a jump insn in BB FROM. */
4954 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4957 struct lra_insn_reg
*reg
;
4961 lra_assert (to
!= NULL
);
4963 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4965 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4966 last
= get_last_insertion_point (from
);
4967 if (! JUMP_P (last
))
4969 curr_id
= lra_get_insn_recog_data (last
);
4970 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4971 if (reg
->type
!= OP_IN
)
4972 bitmap_set_bit (res
, reg
->regno
);
4975 /* Used as a temporary results of some bitmap calculations. */
4976 static bitmap_head temp_bitmap
;
4978 /* Do inheritance/split transformations in EBB starting with HEAD and
4979 finishing on TAIL. We process EBB insns in the reverse order.
4980 Return true if we did any inheritance/split transformation in the
4983 We should avoid excessive splitting which results in worse code
4984 because of inaccurate cost calculations for spilling new split
4985 pseudos in such case. To achieve this we do splitting only if
4986 register pressure is high in given basic block and there are reload
4987 pseudos requiring hard registers. We could do more register
4988 pressure calculations at any given program point to avoid necessary
4989 splitting even more but it is to expensive and the current approach
4990 works well enough. */
4992 inherit_in_ebb (rtx head
, rtx tail
)
4994 int i
, src_regno
, dst_regno
, nregs
;
4995 bool change_p
, succ_p
;
4996 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4998 struct lra_insn_reg
*reg
;
4999 basic_block last_processed_bb
, curr_bb
= NULL
;
5000 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5004 bool head_p
, after_p
;
5007 curr_usage_insns_check
++;
5008 reloads_num
= calls_num
= 0;
5009 bitmap_clear (&check_only_regs
);
5010 last_processed_bb
= NULL
;
5011 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5012 CLEAR_HARD_REG_SET (live_hard_regs
);
5013 /* We don't process new insns generated in the loop. */
5014 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5016 prev_insn
= PREV_INSN (curr_insn
);
5017 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5018 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5019 if (last_processed_bb
!= curr_bb
)
5021 /* We are at the end of BB. Add qualified living
5022 pseudos for potential splitting. */
5023 to_process
= df_get_live_out (curr_bb
);
5024 if (last_processed_bb
!= NULL
)
5026 /* We are somewhere in the middle of EBB. */
5027 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5029 to_process
= &temp_bitmap
;
5031 last_processed_bb
= curr_bb
;
5032 last_insn
= get_last_insertion_point (curr_bb
);
5033 after_p
= (! JUMP_P (last_insn
)
5034 && (! CALL_P (last_insn
)
5035 || (find_reg_note (last_insn
,
5036 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5037 && ! SIBLING_CALL_P (last_insn
))));
5038 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
5039 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5040 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5041 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5042 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5044 if ((int) j
>= lra_constraint_new_regno_start
)
5046 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5048 if (j
< FIRST_PSEUDO_REGISTER
)
5049 SET_HARD_REG_BIT (live_hard_regs
, j
);
5051 add_to_hard_reg_set (&live_hard_regs
,
5052 PSEUDO_REGNO_MODE (j
),
5054 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5058 src_regno
= dst_regno
= -1;
5059 if (NONDEBUG_INSN_P (curr_insn
)
5060 && (set
= single_set (curr_insn
)) != NULL_RTX
5061 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5063 src_regno
= REGNO (SET_SRC (set
));
5064 dst_regno
= REGNO (SET_DEST (set
));
5066 if (src_regno
< lra_constraint_new_regno_start
5067 && src_regno
>= FIRST_PSEUDO_REGISTER
5068 && reg_renumber
[src_regno
] < 0
5069 && dst_regno
>= lra_constraint_new_regno_start
5070 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5072 /* 'reload_pseudo <- original_pseudo'. */
5075 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5076 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5077 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5078 curr_insn
, next_usage_insns
);
5082 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5083 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5084 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5085 reg_class_contents
[cl
]);
5087 else if (src_regno
>= lra_constraint_new_regno_start
5088 && dst_regno
< lra_constraint_new_regno_start
5089 && dst_regno
>= FIRST_PSEUDO_REGISTER
5090 && reg_renumber
[dst_regno
] < 0
5091 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5092 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5093 && (next_usage_insns
5094 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5097 /* 'original_pseudo <- reload_pseudo'. */
5098 if (! JUMP_P (curr_insn
)
5099 && inherit_reload_reg (true, dst_regno
, cl
,
5100 curr_insn
, next_usage_insns
))
5103 usage_insns
[dst_regno
].check
= 0;
5104 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5105 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5106 reg_class_contents
[cl
]);
5108 else if (INSN_P (curr_insn
))
5111 int max_uid
= get_max_uid ();
5113 curr_id
= lra_get_insn_recog_data (curr_insn
);
5114 curr_static_id
= curr_id
->insn_static_data
;
5116 /* Process insn definitions. */
5117 for (iter
= 0; iter
< 2; iter
++)
5118 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5121 if (reg
->type
!= OP_IN
5122 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5124 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5125 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5126 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5127 && (next_usage_insns
5128 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5130 struct lra_insn_reg
*r
;
5132 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5133 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5135 /* Don't do inheritance if the pseudo is also
5136 used in the insn. */
5138 /* We can not do inheritance right now
5139 because the current insn reg info (chain
5140 regs) can change after that. */
5141 add_to_inherit (dst_regno
, next_usage_insns
);
5143 /* We can not process one reg twice here because of
5144 usage_insns invalidation. */
5145 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5146 || reg_renumber
[dst_regno
] >= 0)
5147 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5151 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5152 potential_reload_hard_regs
,
5153 false, curr_insn
, max_uid
))
5155 CLEAR_HARD_REG_SET (s
);
5156 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5157 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5159 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5160 reg_renumber
[dst_regno
]);
5161 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5163 /* We should invalidate potential inheritance or
5164 splitting for the current insn usages to the next
5165 usage insns (see code below) as the output pseudo
5167 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5168 && reg_renumber
[dst_regno
] < 0)
5169 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5170 && (dst_regno
< FIRST_PSEUDO_REGISTER
5171 || reg_renumber
[dst_regno
] >= 0)))
5173 /* Invalidate and mark definitions. */
5174 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5175 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5178 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5179 for (i
= 0; i
< nregs
; i
++)
5180 usage_insns
[dst_regno
+ i
].check
5181 = -(int) INSN_UID (curr_insn
);
5185 if (! JUMP_P (curr_insn
))
5186 for (i
= 0; i
< to_inherit_num
; i
++)
5187 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5188 ALL_REGS
, curr_insn
,
5189 to_inherit
[i
].insns
))
5191 if (CALL_P (curr_insn
))
5193 rtx cheap
, pat
, dest
, restore
;
5194 int regno
, hard_regno
;
5197 if ((cheap
= find_reg_note (curr_insn
,
5198 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5199 && ((cheap
= XEXP (cheap
, 0)), true)
5200 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5201 && (hard_regno
= reg_renumber
[regno
]) >= 0
5202 /* If there are pending saves/restores, the
5203 optimization is not worth. */
5204 && usage_insns
[regno
].calls_num
== calls_num
- 1
5205 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5207 /* Restore the pseudo from the call result as
5208 REG_RETURNED note says that the pseudo value is
5209 in the call result and the pseudo is an argument
5211 pat
= PATTERN (curr_insn
);
5212 if (GET_CODE (pat
) == PARALLEL
)
5213 pat
= XVECEXP (pat
, 0, 0);
5214 dest
= SET_DEST (pat
);
5216 emit_move_insn (cheap
, copy_rtx (dest
));
5217 restore
= get_insns ();
5219 lra_process_new_insns (curr_insn
, NULL
, restore
,
5220 "Inserting call parameter restore");
5221 /* We don't need to save/restore of the pseudo from
5223 usage_insns
[regno
].calls_num
= calls_num
;
5224 bitmap_set_bit (&check_only_regs
, regno
);
5228 /* Process insn usages. */
5229 for (iter
= 0; iter
< 2; iter
++)
5230 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5233 if ((reg
->type
!= OP_OUT
5234 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5235 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5237 if (src_regno
>= FIRST_PSEUDO_REGISTER
5238 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5240 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5241 && (next_usage_insns
5242 = usage_insns
[src_regno
].insns
) != NULL_RTX
5243 && NONDEBUG_INSN_P (curr_insn
))
5244 add_to_inherit (src_regno
, next_usage_insns
);
5245 else if (usage_insns
[src_regno
].check
5246 != -(int) INSN_UID (curr_insn
))
5247 /* Add usages but only if the reg is not set up
5248 in the same insn. */
5249 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5251 else if (src_regno
< FIRST_PSEUDO_REGISTER
5252 || reg_renumber
[src_regno
] >= 0)
5255 rtx use_insn
= curr_insn
;
5257 before_p
= (JUMP_P (curr_insn
)
5258 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5259 if (NONDEBUG_INSN_P (curr_insn
)
5260 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5261 potential_reload_hard_regs
,
5262 before_p
, curr_insn
, max_uid
))
5265 lra_risky_transformations_p
= true;
5268 usage_insns
[src_regno
].check
= 0;
5270 use_insn
= PREV_INSN (curr_insn
);
5272 if (NONDEBUG_INSN_P (curr_insn
))
5274 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5275 add_to_hard_reg_set (&live_hard_regs
,
5276 reg
->biggest_mode
, src_regno
);
5278 add_to_hard_reg_set (&live_hard_regs
,
5279 PSEUDO_REGNO_MODE (src_regno
),
5280 reg_renumber
[src_regno
]);
5282 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5285 for (i
= 0; i
< to_inherit_num
; i
++)
5287 src_regno
= to_inherit
[i
].regno
;
5288 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5289 curr_insn
, to_inherit
[i
].insns
))
5292 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5295 /* We reached the start of the current basic block. */
5296 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5297 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5299 /* We reached the beginning of the current block -- do
5300 rest of spliting in the current BB. */
5301 to_process
= df_get_live_in (curr_bb
);
5302 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5304 /* We are somewhere in the middle of EBB. */
5305 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5306 curr_bb
, &temp_bitmap
);
5307 to_process
= &temp_bitmap
;
5310 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5312 if ((int) j
>= lra_constraint_new_regno_start
)
5314 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5315 && usage_insns
[j
].check
== curr_usage_insns_check
5316 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5318 if (need_for_split_p (potential_reload_hard_regs
, j
))
5320 if (lra_dump_file
!= NULL
&& head_p
)
5322 fprintf (lra_dump_file
,
5323 " ----------------------------------\n");
5326 if (split_reg (false, j
, bb_note (curr_bb
),
5330 usage_insns
[j
].check
= 0;
5338 /* This value affects EBB forming. If probability of edge from EBB to
5339 a BB is not greater than the following value, we don't add the BB
5341 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5343 /* Current number of inheritance/split iteration. */
5344 int lra_inheritance_iter
;
5346 /* Entry function for inheritance/split pass. */
5348 lra_inheritance (void)
5351 basic_block bb
, start_bb
;
5354 lra_inheritance_iter
++;
5355 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5357 timevar_push (TV_LRA_INHERITANCE
);
5358 if (lra_dump_file
!= NULL
)
5359 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5360 lra_inheritance_iter
);
5361 curr_usage_insns_check
= 0;
5362 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5363 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5364 usage_insns
[i
].check
= 0;
5365 bitmap_initialize (&check_only_regs
, ®_obstack
);
5366 bitmap_initialize (&live_regs
, ®_obstack
);
5367 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5368 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5369 FOR_EACH_BB_FN (bb
, cfun
)
5372 if (lra_dump_file
!= NULL
)
5373 fprintf (lra_dump_file
, "EBB");
5374 /* Form a EBB starting with BB. */
5375 bitmap_clear (&ebb_global_regs
);
5376 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5379 if (lra_dump_file
!= NULL
)
5380 fprintf (lra_dump_file
, " %d", bb
->index
);
5381 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5382 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5384 e
= find_fallthru_edge (bb
->succs
);
5387 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5391 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5392 if (lra_dump_file
!= NULL
)
5393 fprintf (lra_dump_file
, "\n");
5394 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5395 /* Remember that the EBB head and tail can change in
5397 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5399 bitmap_clear (&ebb_global_regs
);
5400 bitmap_clear (&temp_bitmap
);
5401 bitmap_clear (&live_regs
);
5402 bitmap_clear (&check_only_regs
);
5405 timevar_pop (TV_LRA_INHERITANCE
);
5410 /* This page contains code to undo failed inheritance/split
5413 /* Current number of iteration undoing inheritance/split. */
5414 int lra_undo_inheritance_iter
;
5416 /* Fix BB live info LIVE after removing pseudos created on pass doing
5417 inheritance/split which are REMOVED_PSEUDOS. */
5419 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5424 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5425 if (bitmap_clear_bit (live
, regno
))
5426 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5429 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5434 if (GET_CODE (reg
) == SUBREG
)
5435 reg
= SUBREG_REG (reg
);
5441 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5442 return true if we did any change. The undo transformations for
5443 inheritance looks like
5447 p <- i, i <- p, and i <- i3
5448 where p is original pseudo from which inheritance pseudo i was
5449 created, i and i3 are removed inheritance pseudos, i2 is another
5450 not removed inheritance pseudo. All split pseudos or other
5451 occurrences of removed inheritance pseudos are changed on the
5452 corresponding original pseudos.
5454 The function also schedules insns changed and created during
5455 inheritance/split pass for processing by the subsequent constraint
5458 remove_inheritance_pseudos (bitmap remove_pseudos
)
5461 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5462 rtx set
, prev_set
, prev_insn
;
5463 bool change_p
, done_p
;
5465 change_p
= ! bitmap_empty_p (remove_pseudos
);
5466 /* We can not finish the function right away if CHANGE_P is true
5467 because we need to marks insns affected by previous
5468 inheritance/split pass for processing by the subsequent
5470 FOR_EACH_BB_FN (bb
, cfun
)
5472 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5473 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5474 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5476 if (! INSN_P (curr_insn
))
5479 sregno
= dregno
= -1;
5480 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5481 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5483 dregno
= get_regno (SET_DEST (set
));
5484 sregno
= get_regno (SET_SRC (set
));
5487 if (sregno
>= 0 && dregno
>= 0)
5489 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5490 && (lra_reg_info
[sregno
].restore_regno
== dregno
5491 || (bitmap_bit_p (remove_pseudos
, dregno
)
5492 && (lra_reg_info
[sregno
].restore_regno
5493 == lra_reg_info
[dregno
].restore_regno
))))
5494 || (bitmap_bit_p (remove_pseudos
, dregno
)
5495 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5496 /* One of the following cases:
5497 original <- removed inheritance pseudo
5498 removed inherit pseudo <- another removed inherit pseudo
5499 removed inherit pseudo <- original pseudo
5501 removed_split_pseudo <- original_reg
5502 original_reg <- removed_split_pseudo */
5504 if (lra_dump_file
!= NULL
)
5506 fprintf (lra_dump_file
, " Removing %s:\n",
5507 bitmap_bit_p (&lra_split_regs
, sregno
)
5508 || bitmap_bit_p (&lra_split_regs
, dregno
)
5509 ? "split" : "inheritance");
5510 dump_insn_slim (lra_dump_file
, curr_insn
);
5512 lra_set_insn_deleted (curr_insn
);
5515 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5516 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5518 /* Search the following pattern:
5519 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5520 original_pseudo <- inherit_or_split_pseudo1
5521 where the 2nd insn is the current insn and
5522 inherit_or_split_pseudo2 is not removed. If it is found,
5523 change the current insn onto:
5524 original_pseudo <- inherit_or_split_pseudo2. */
5525 for (prev_insn
= PREV_INSN (curr_insn
);
5526 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5527 prev_insn
= PREV_INSN (prev_insn
))
5529 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5530 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5531 /* There should be no subregs in insn we are
5532 searching because only the original reg might
5533 be in subreg when we changed the mode of
5534 load/store for splitting. */
5535 && REG_P (SET_DEST (prev_set
))
5536 && REG_P (SET_SRC (prev_set
))
5537 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5538 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5539 >= FIRST_PSEUDO_REGISTER
)
5540 /* As we consider chain of inheritance or
5541 splitting described in above comment we should
5542 check that sregno and prev_sregno were
5543 inheritance/split pseudos created from the
5544 same original regno. */
5545 && (lra_reg_info
[sregno
].restore_regno
5546 == lra_reg_info
[prev_sregno
].restore_regno
)
5547 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5549 lra_assert (GET_MODE (SET_SRC (prev_set
))
5550 == GET_MODE (regno_reg_rtx
[sregno
]));
5551 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5552 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5554 SET_SRC (set
) = SET_SRC (prev_set
);
5555 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5556 lra_set_used_insn_alternative_by_uid
5557 (INSN_UID (curr_insn
), -1);
5559 if (lra_dump_file
!= NULL
)
5561 fprintf (lra_dump_file
, " Change reload insn:\n");
5562 dump_insn_slim (lra_dump_file
, curr_insn
);
5569 struct lra_insn_reg
*reg
;
5570 bool restored_regs_p
= false;
5571 bool kept_regs_p
= false;
5573 curr_id
= lra_get_insn_recog_data (curr_insn
);
5574 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5577 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5578 if (restore_regno
>= 0)
5580 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5582 substitute_pseudo (&curr_insn
, regno
,
5583 regno_reg_rtx
[restore_regno
]);
5584 restored_regs_p
= true;
5590 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5592 /* The instruction has changed since the previous
5593 constraints pass. */
5594 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5595 lra_set_used_insn_alternative_by_uid
5596 (INSN_UID (curr_insn
), -1);
5598 else if (restored_regs_p
)
5599 /* The instruction has been restored to the form that
5600 it had during the previous constraints pass. */
5601 lra_update_insn_regno_info (curr_insn
);
5602 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5604 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5605 dump_insn_slim (lra_dump_file
, curr_insn
);
5613 /* If optional reload pseudos failed to get a hard register or was not
5614 inherited, it is better to remove optional reloads. We do this
5615 transformation after undoing inheritance to figure out necessity to
5616 remove optional reloads easier. Return true if we do any
5619 undo_optional_reloads (void)
5621 bool change_p
, keep_p
;
5622 unsigned int regno
, uid
;
5623 bitmap_iterator bi
, bi2
;
5624 rtx insn
, set
, src
, dest
;
5625 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5627 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5628 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5629 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5632 /* Keep optional reloads from previous subpasses. */
5633 if (lra_reg_info
[regno
].restore_regno
< 0
5634 /* If the original pseudo changed its allocation, just
5635 removing the optional pseudo is dangerous as the original
5636 pseudo will have longer live range. */
5637 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5639 else if (reg_renumber
[regno
] >= 0)
5640 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5642 insn
= lra_insn_recog_data
[uid
]->insn
;
5643 if ((set
= single_set (insn
)) == NULL_RTX
)
5645 src
= SET_SRC (set
);
5646 dest
= SET_DEST (set
);
5647 if (! REG_P (src
) || ! REG_P (dest
))
5649 if (REGNO (dest
) == regno
5650 /* Ignore insn for optional reloads itself. */
5651 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5652 /* Check only inheritance on last inheritance pass. */
5653 && (int) REGNO (src
) >= new_regno_start
5654 /* Check that the optional reload was inherited. */
5655 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5663 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5664 if (lra_dump_file
!= NULL
)
5665 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5668 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5669 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5670 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5672 if (lra_dump_file
!= NULL
)
5673 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5674 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5675 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5677 insn
= lra_insn_recog_data
[uid
]->insn
;
5678 if ((set
= single_set (insn
)) != NULL_RTX
)
5680 src
= SET_SRC (set
);
5681 dest
= SET_DEST (set
);
5682 if (REG_P (src
) && REG_P (dest
)
5683 && ((REGNO (src
) == regno
5684 && (lra_reg_info
[regno
].restore_regno
5685 == (int) REGNO (dest
)))
5686 || (REGNO (dest
) == regno
5687 && (lra_reg_info
[regno
].restore_regno
5688 == (int) REGNO (src
)))))
5690 if (lra_dump_file
!= NULL
)
5692 fprintf (lra_dump_file
, " Deleting move %u\n",
5694 dump_insn_slim (lra_dump_file
, insn
);
5696 lra_set_insn_deleted (insn
);
5699 /* We should not worry about generation memory-memory
5700 moves here as if the corresponding inheritance did
5701 not work (inheritance pseudo did not get a hard reg),
5702 we remove the inheritance pseudo and the optional
5705 substitute_pseudo (&insn
, regno
,
5706 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5707 lra_update_insn_regno_info (insn
);
5708 if (lra_dump_file
!= NULL
)
5710 fprintf (lra_dump_file
,
5711 " Restoring original insn:\n");
5712 dump_insn_slim (lra_dump_file
, insn
);
5716 /* Clear restore_regnos. */
5717 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5718 lra_reg_info
[regno
].restore_regno
= -1;
5719 bitmap_clear (&insn_bitmap
);
5720 bitmap_clear (&removed_optional_reload_pseudos
);
5724 /* Entry function for undoing inheritance/split transformation. Return true
5725 if we did any RTL change in this pass. */
5727 lra_undo_inheritance (void)
5730 int restore_regno
, hard_regno
;
5731 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5732 bitmap_head remove_pseudos
;
5736 lra_undo_inheritance_iter
++;
5737 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5739 if (lra_dump_file
!= NULL
)
5740 fprintf (lra_dump_file
,
5741 "\n********** Undoing inheritance #%d: **********\n\n",
5742 lra_undo_inheritance_iter
);
5743 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5744 n_inherit
= n_all_inherit
= 0;
5745 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5746 if (lra_reg_info
[regno
].restore_regno
>= 0)
5749 if (reg_renumber
[regno
] < 0
5750 /* If the original pseudo changed its allocation, just
5751 removing inheritance is dangerous as for changing
5752 allocation we used shorter live-ranges. */
5753 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5754 bitmap_set_bit (&remove_pseudos
, regno
);
5758 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5759 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5760 n_inherit
, n_all_inherit
,
5761 (double) n_inherit
/ n_all_inherit
* 100);
5762 n_split
= n_all_split
= 0;
5763 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5764 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5767 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5768 ? reg_renumber
[restore_regno
] : restore_regno
);
5769 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5770 bitmap_set_bit (&remove_pseudos
, regno
);
5774 if (lra_dump_file
!= NULL
)
5775 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5776 regno
, restore_regno
);
5779 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5780 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5781 n_split
, n_all_split
,
5782 (double) n_split
/ n_all_split
* 100);
5783 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5784 bitmap_clear (&remove_pseudos
);
5785 /* Clear restore_regnos. */
5786 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5787 lra_reg_info
[regno
].restore_regno
= -1;
5788 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5789 lra_reg_info
[regno
].restore_regno
= -1;
5790 change_p
= undo_optional_reloads () || change_p
;