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1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
30 as possible
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
37 generated;
38 o Some pseudos might be spilled to assign hard registers to
39 new reload pseudos;
40 o Recalculating spilled pseudo values (rematerialization);
41 o Changing spilled pseudos to stack memory or their equivalences;
42 o Allocation stack memory changes the address displacement and
43 new iteration is needed.
45 Here is block diagram of LRA passes:
47 ------------------------
48 --------------- | Undo inheritance for | ---------------
49 | Memory-memory | | spilled pseudos, | | New (and old) |
50 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
51 --------------- | the same hard regs, | | assignment |
52 Start | | and optional reloads | ---------------
53 | | ------------------------ ^
54 V | ---------------- |
55 ----------- V | Update virtual | |
56 | Remove |----> ------------>| register | |
57 | scratches | ^ | displacements | |
58 ----------- | ---------------- |
59 | | |
60 | V New |
61 | ------------ pseudos -------------------
62 | |Constraints:| or insns | Inheritance/split |
63 | | RTL |--------->| transformations |
64 | | transfor- | | in EBB scope |
65 | substi- | mations | -------------------
66 | tutions ------------
67 | | No change
68 ---------------- V
69 | Spilled pseudo | -------------------
70 | to memory |<----| Rematerialization |
71 | substitution | -------------------
72 ----------------
73 | No susbtitions
75 -------------------------
76 | Hard regs substitution, |
77 | devirtalization, and |------> Finish
78 | restoring scratches got |
79 | memory |
80 -------------------------
82 To speed up the process:
83 o We process only insns affected by changes on previous
84 iterations;
85 o We don't use DFA-infrastructure because it results in much slower
86 compiler speed than a special IR described below does;
87 o We use a special insn representation for quick access to insn
88 info which is always *synchronized* with the current RTL;
89 o Insn IR is minimized by memory. It is divided on three parts:
90 o one specific for each insn in RTL (only operand locations);
91 o one common for all insns in RTL with the same insn code
92 (different operand attributes from machine descriptions);
93 o one oriented for maintenance of live info (list of pseudos).
94 o Pseudo data:
95 o all insns where the pseudo is referenced;
96 o live info (conflicting hard regs, live ranges, # of
97 references etc);
98 o data used for assigning (preferred hard regs, costs etc).
100 This file contains LRA driver, LRA utility functions and data, and
101 code for dealing with scratches. */
103 #include "config.h"
104 #include "system.h"
105 #include "coretypes.h"
106 #include "backend.h"
107 #include "target.h"
108 #include "rtl.h"
109 #include "tree.h"
110 #include "predict.h"
111 #include "df.h"
112 #include "memmodel.h"
113 #include "tm_p.h"
114 #include "optabs.h"
115 #include "regs.h"
116 #include "ira.h"
117 #include "recog.h"
118 #include "expr.h"
119 #include "cfgrtl.h"
120 #include "cfgbuild.h"
121 #include "lra.h"
122 #include "lra-int.h"
123 #include "print-rtl.h"
125 /* Dump bitmap SET with TITLE and BB INDEX. */
126 void
127 lra_dump_bitmap_with_title (const char *title, bitmap set, int index)
129 unsigned int i;
130 int count;
131 bitmap_iterator bi;
132 static const int max_nums_on_line = 10;
134 if (bitmap_empty_p (set))
135 return;
136 fprintf (lra_dump_file, " %s %d:", title, index);
137 fprintf (lra_dump_file, "\n");
138 count = max_nums_on_line + 1;
139 EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi)
141 if (count > max_nums_on_line)
143 fprintf (lra_dump_file, "\n ");
144 count = 0;
146 fprintf (lra_dump_file, " %4u", i);
147 count++;
149 fprintf (lra_dump_file, "\n");
152 /* Hard registers currently not available for allocation. It can
153 changed after some hard registers become not eliminable. */
154 HARD_REG_SET lra_no_alloc_regs;
156 static int get_new_reg_value (void);
157 static void expand_reg_info (void);
158 static void invalidate_insn_recog_data (int);
159 static int get_insn_freq (rtx_insn *);
160 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t,
161 rtx_insn *, int);
163 /* Expand all regno related info needed for LRA. */
164 static void
165 expand_reg_data (int old)
167 resize_reg_info ();
168 expand_reg_info ();
169 ira_expand_reg_equiv ();
170 for (int i = (int) max_reg_num () - 1; i >= old; i--)
171 lra_change_class (i, ALL_REGS, " Set", true);
174 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
175 or of VOIDmode, use MD_MODE for the new reg. Initialize its
176 register class to RCLASS. Print message about assigning class
177 RCLASS containing new register name TITLE unless it is NULL. Use
178 attributes of ORIGINAL if it is a register. The created register
179 will have unique held value. */
181 lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original,
182 enum reg_class rclass, const char *title)
184 machine_mode mode;
185 rtx new_reg;
187 if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode)
188 mode = md_mode;
189 lra_assert (mode != VOIDmode);
190 new_reg = gen_reg_rtx (mode);
191 if (original == NULL_RTX || ! REG_P (original))
193 if (lra_dump_file != NULL)
194 fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg));
196 else
198 if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER)
199 ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original);
200 REG_USERVAR_P (new_reg) = REG_USERVAR_P (original);
201 REG_POINTER (new_reg) = REG_POINTER (original);
202 REG_ATTRS (new_reg) = REG_ATTRS (original);
203 if (lra_dump_file != NULL)
204 fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i",
205 REGNO (new_reg), REGNO (original));
207 if (lra_dump_file != NULL)
209 if (title != NULL)
210 fprintf (lra_dump_file, ", assigning class %s to%s%s r%d",
211 reg_class_names[rclass], *title == '\0' ? "" : " ",
212 title, REGNO (new_reg));
213 fprintf (lra_dump_file, "\n");
215 expand_reg_data (max_reg_num ());
216 setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass);
217 return new_reg;
220 /* Analogous to the previous function but also inherits value of
221 ORIGINAL. */
223 lra_create_new_reg (machine_mode md_mode, rtx original,
224 enum reg_class rclass, const char *title)
226 rtx new_reg;
228 new_reg
229 = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title);
230 if (original != NULL_RTX && REG_P (original))
231 lra_assign_reg_val (REGNO (original), REGNO (new_reg));
232 return new_reg;
235 /* Set up for REGNO unique hold value. */
236 void
237 lra_set_regno_unique_value (int regno)
239 lra_reg_info[regno].val = get_new_reg_value ();
242 /* Invalidate INSN related info used by LRA. The info should never be
243 used after that. */
244 void
245 lra_invalidate_insn_data (rtx_insn *insn)
247 lra_invalidate_insn_regno_info (insn);
248 invalidate_insn_recog_data (INSN_UID (insn));
251 /* Mark INSN deleted and invalidate the insn related info used by
252 LRA. */
253 void
254 lra_set_insn_deleted (rtx_insn *insn)
256 lra_invalidate_insn_data (insn);
257 SET_INSN_DELETED (insn);
260 /* Delete an unneeded INSN and any previous insns who sole purpose is
261 loading data that is dead in INSN. */
262 void
263 lra_delete_dead_insn (rtx_insn *insn)
265 rtx_insn *prev = prev_real_insn (insn);
266 rtx prev_dest;
268 /* If the previous insn sets a register that dies in our insn,
269 delete it too. */
270 if (prev && GET_CODE (PATTERN (prev)) == SET
271 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
272 && reg_mentioned_p (prev_dest, PATTERN (insn))
273 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
274 && ! side_effects_p (SET_SRC (PATTERN (prev))))
275 lra_delete_dead_insn (prev);
277 lra_set_insn_deleted (insn);
280 /* Emit insn x = y + z. Return NULL if we failed to do it.
281 Otherwise, return the insn. We don't use gen_add3_insn as it might
282 clobber CC. */
283 static rtx_insn *
284 emit_add3_insn (rtx x, rtx y, rtx z)
286 rtx_insn *last;
288 last = get_last_insn ();
290 if (have_addptr3_insn (x, y, z))
292 rtx_insn *insn = gen_addptr3_insn (x, y, z);
294 /* If the target provides an "addptr" pattern it hopefully does
295 for a reason. So falling back to the normal add would be
296 a bug. */
297 lra_assert (insn != NULL_RTX);
298 emit_insn (insn);
299 return insn;
302 rtx_insn *insn = emit_insn (gen_rtx_SET (x, gen_rtx_PLUS (GET_MODE (y),
303 y, z)));
304 if (recog_memoized (insn) < 0)
306 delete_insns_since (last);
307 insn = NULL;
309 return insn;
312 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
313 last resort. */
314 static rtx_insn *
315 emit_add2_insn (rtx x, rtx y)
317 rtx_insn *insn = emit_add3_insn (x, x, y);
318 if (insn == NULL_RTX)
320 insn = gen_add2_insn (x, y);
321 if (insn != NULL_RTX)
322 emit_insn (insn);
324 return insn;
327 /* Target checks operands through operand predicates to recognize an
328 insn. We should have a special precaution to generate add insns
329 which are frequent results of elimination.
331 Emit insns for x = y + z. X can be used to store intermediate
332 values and should be not in Y and Z when we use X to store an
333 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
334 + disp] where base and index are registers, disp and scale are
335 constants. Y should contain base if it is present, Z should
336 contain disp if any. index[*scale] can be part of Y or Z. */
337 void
338 lra_emit_add (rtx x, rtx y, rtx z)
340 int old;
341 rtx_insn *last;
342 rtx a1, a2, base, index, disp, scale, index_scale;
343 bool ok_p;
345 rtx_insn *add3_insn = emit_add3_insn (x, y, z);
346 old = max_reg_num ();
347 if (add3_insn != NULL)
349 else
351 disp = a2 = NULL_RTX;
352 if (GET_CODE (y) == PLUS)
354 a1 = XEXP (y, 0);
355 a2 = XEXP (y, 1);
356 disp = z;
358 else
360 a1 = y;
361 if (CONSTANT_P (z))
362 disp = z;
363 else
364 a2 = z;
366 index_scale = scale = NULL_RTX;
367 if (GET_CODE (a1) == MULT)
369 index_scale = a1;
370 index = XEXP (a1, 0);
371 scale = XEXP (a1, 1);
372 base = a2;
374 else if (a2 != NULL_RTX && GET_CODE (a2) == MULT)
376 index_scale = a2;
377 index = XEXP (a2, 0);
378 scale = XEXP (a2, 1);
379 base = a1;
381 else
383 base = a1;
384 index = a2;
386 if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG))
387 || (index != NULL_RTX
388 && ! (REG_P (index) || GET_CODE (index) == SUBREG))
389 || (disp != NULL_RTX && ! CONSTANT_P (disp))
390 || (scale != NULL_RTX && ! CONSTANT_P (scale)))
392 /* Probably we have no 3 op add. Last chance is to use 2-op
393 add insn. To succeed, don't move Z to X as an address
394 segment always comes in Y. Otherwise, we might fail when
395 adding the address segment to register. */
396 lra_assert (x != y && x != z);
397 emit_move_insn (x, y);
398 rtx_insn *insn = emit_add2_insn (x, z);
399 lra_assert (insn != NULL_RTX);
401 else
403 if (index_scale == NULL_RTX)
404 index_scale = index;
405 if (disp == NULL_RTX)
407 /* Generate x = index_scale; x = x + base. */
408 lra_assert (index_scale != NULL_RTX && base != NULL_RTX);
409 emit_move_insn (x, index_scale);
410 rtx_insn *insn = emit_add2_insn (x, base);
411 lra_assert (insn != NULL_RTX);
413 else if (scale == NULL_RTX)
415 /* Try x = base + disp. */
416 lra_assert (base != NULL_RTX);
417 last = get_last_insn ();
418 rtx_insn *move_insn =
419 emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp));
420 if (recog_memoized (move_insn) < 0)
422 delete_insns_since (last);
423 /* Generate x = disp; x = x + base. */
424 emit_move_insn (x, disp);
425 rtx_insn *add2_insn = emit_add2_insn (x, base);
426 lra_assert (add2_insn != NULL_RTX);
428 /* Generate x = x + index. */
429 if (index != NULL_RTX)
431 rtx_insn *insn = emit_add2_insn (x, index);
432 lra_assert (insn != NULL_RTX);
435 else
437 /* Try x = index_scale; x = x + disp; x = x + base. */
438 last = get_last_insn ();
439 rtx_insn *move_insn = emit_move_insn (x, index_scale);
440 ok_p = false;
441 if (recog_memoized (move_insn) >= 0)
443 rtx_insn *insn = emit_add2_insn (x, disp);
444 if (insn != NULL_RTX)
446 if (base == NULL_RTX)
447 ok_p = true;
448 else
450 insn = emit_add2_insn (x, base);
451 if (insn != NULL_RTX)
452 ok_p = true;
456 if (! ok_p)
458 rtx_insn *insn;
460 delete_insns_since (last);
461 /* Generate x = disp; x = x + base; x = x + index_scale. */
462 emit_move_insn (x, disp);
463 if (base != NULL_RTX)
465 insn = emit_add2_insn (x, base);
466 lra_assert (insn != NULL_RTX);
468 insn = emit_add2_insn (x, index_scale);
469 lra_assert (insn != NULL_RTX);
474 /* Functions emit_... can create pseudos -- so expand the pseudo
475 data. */
476 if (old != max_reg_num ())
477 expand_reg_data (old);
480 /* The number of emitted reload insns so far. */
481 int lra_curr_reload_num;
483 /* Emit x := y, processing special case when y = u + v or y = u + v *
484 scale + w through emit_add (Y can be an address which is base +
485 index reg * scale + displacement in general case). X may be used
486 as intermediate result therefore it should be not in Y. */
487 void
488 lra_emit_move (rtx x, rtx y)
490 int old;
492 if (GET_CODE (y) != PLUS)
494 if (rtx_equal_p (x, y))
495 return;
496 old = max_reg_num ();
497 emit_move_insn (x, y);
498 if (REG_P (x))
499 lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num;
500 /* Function emit_move can create pseudos -- so expand the pseudo
501 data. */
502 if (old != max_reg_num ())
503 expand_reg_data (old);
504 return;
506 lra_emit_add (x, XEXP (y, 0), XEXP (y, 1));
509 /* Update insn operands which are duplication of operands whose
510 numbers are in array of NOPS (with end marker -1). The insn is
511 represented by its LRA internal representation ID. */
512 void
513 lra_update_dups (lra_insn_recog_data_t id, signed char *nops)
515 int i, j, nop;
516 struct lra_static_insn_data *static_id = id->insn_static_data;
518 for (i = 0; i < static_id->n_dups; i++)
519 for (j = 0; (nop = nops[j]) >= 0; j++)
520 if (static_id->dup_num[i] == nop)
521 *id->dup_loc[i] = *id->operand_loc[nop];
526 /* This page contains code dealing with info about registers in the
527 insns. */
529 /* Pools for insn reg info. */
530 object_allocator<lra_insn_reg> lra_insn_reg_pool ("insn regs");
532 /* Create LRA insn related info about a reference to REGNO in INSN
533 with TYPE (in/out/inout), biggest reference mode MODE, flag that it
534 is reference through subreg (SUBREG_P), flag that is early
535 clobbered in the insn (EARLY_CLOBBER), and reference to the next
536 insn reg info (NEXT). If REGNO can be early clobbered,
537 alternatives in which it can be early clobbered are given by
538 EARLY_CLOBBER_ALTS. */
539 static struct lra_insn_reg *
540 new_insn_reg (rtx_insn *insn, int regno, enum op_type type,
541 machine_mode mode,
542 bool subreg_p, bool early_clobber,
543 alternative_mask early_clobber_alts,
544 struct lra_insn_reg *next)
546 lra_insn_reg *ir = lra_insn_reg_pool.allocate ();
547 ir->type = type;
548 ir->biggest_mode = mode;
549 if (NONDEBUG_INSN_P (insn)
550 && partial_subreg_p (lra_reg_info[regno].biggest_mode, mode))
551 lra_reg_info[regno].biggest_mode = mode;
552 ir->subreg_p = subreg_p;
553 ir->early_clobber = early_clobber;
554 ir->early_clobber_alts = early_clobber_alts;
555 ir->regno = regno;
556 ir->next = next;
557 return ir;
560 /* Free insn reg info list IR. */
561 static void
562 free_insn_regs (struct lra_insn_reg *ir)
564 struct lra_insn_reg *next_ir;
566 for (; ir != NULL; ir = next_ir)
568 next_ir = ir->next;
569 lra_insn_reg_pool.remove (ir);
573 /* Finish pool for insn reg info. */
574 static void
575 finish_insn_regs (void)
577 lra_insn_reg_pool.release ();
582 /* This page contains code dealing LRA insn info (or in other words
583 LRA internal insn representation). */
585 /* Map INSN_CODE -> the static insn data. This info is valid during
586 all translation unit. */
587 struct lra_static_insn_data *insn_code_data[NUM_INSN_CODES];
589 /* Debug insns are represented as a special insn with one input
590 operand which is RTL expression in var_location. */
592 /* The following data are used as static insn operand data for all
593 debug insns. If structure lra_operand_data is changed, the
594 initializer should be changed too. */
595 static struct lra_operand_data debug_operand_data =
597 NULL, /* alternative */
598 0, /* early_clobber_alts */
599 E_VOIDmode, /* We are not interesting in the operand mode. */
600 OP_IN,
601 0, 0, 0, 0
604 /* The following data are used as static insn data for all debug
605 bind insns. If structure lra_static_insn_data is changed, the
606 initializer should be changed too. */
607 static struct lra_static_insn_data debug_bind_static_data =
609 &debug_operand_data,
610 0, /* Duplication operands #. */
611 -1, /* Commutative operand #. */
612 1, /* Operands #. There is only one operand which is debug RTL
613 expression. */
614 0, /* Duplications #. */
615 0, /* Alternatives #. We are not interesting in alternatives
616 because we does not proceed debug_insns for reloads. */
617 NULL, /* Hard registers referenced in machine description. */
618 NULL /* Descriptions of operands in alternatives. */
621 /* The following data are used as static insn data for all debug
622 marker insns. If structure lra_static_insn_data is changed, the
623 initializer should be changed too. */
624 static struct lra_static_insn_data debug_marker_static_data =
626 &debug_operand_data,
627 0, /* Duplication operands #. */
628 -1, /* Commutative operand #. */
629 0, /* Operands #. There isn't any operand. */
630 0, /* Duplications #. */
631 0, /* Alternatives #. We are not interesting in alternatives
632 because we does not proceed debug_insns for reloads. */
633 NULL, /* Hard registers referenced in machine description. */
634 NULL /* Descriptions of operands in alternatives. */
637 /* Called once per compiler work to initialize some LRA data related
638 to insns. */
639 static void
640 init_insn_code_data_once (void)
642 memset (insn_code_data, 0, sizeof (insn_code_data));
645 /* Called once per compiler work to finalize some LRA data related to
646 insns. */
647 static void
648 finish_insn_code_data_once (void)
650 for (unsigned int i = 0; i < NUM_INSN_CODES; i++)
652 if (insn_code_data[i] != NULL)
653 free (insn_code_data[i]);
657 /* Return static insn data, allocate and setup if necessary. Although
658 dup_num is static data (it depends only on icode), to set it up we
659 need to extract insn first. So recog_data should be valid for
660 normal insn (ICODE >= 0) before the call. */
661 static struct lra_static_insn_data *
662 get_static_insn_data (int icode, int nop, int ndup, int nalt)
664 struct lra_static_insn_data *data;
665 size_t n_bytes;
667 lra_assert (icode < (int) NUM_INSN_CODES);
668 if (icode >= 0 && (data = insn_code_data[icode]) != NULL)
669 return data;
670 lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0);
671 n_bytes = sizeof (struct lra_static_insn_data)
672 + sizeof (struct lra_operand_data) * nop
673 + sizeof (int) * ndup;
674 data = XNEWVAR (struct lra_static_insn_data, n_bytes);
675 data->operand_alternative = NULL;
676 data->n_operands = nop;
677 data->n_dups = ndup;
678 data->n_alternatives = nalt;
679 data->operand = ((struct lra_operand_data *)
680 ((char *) data + sizeof (struct lra_static_insn_data)));
681 data->dup_num = ((int *) ((char *) data->operand
682 + sizeof (struct lra_operand_data) * nop));
683 if (icode >= 0)
685 int i;
687 insn_code_data[icode] = data;
688 for (i = 0; i < nop; i++)
690 data->operand[i].constraint
691 = insn_data[icode].operand[i].constraint;
692 data->operand[i].mode = insn_data[icode].operand[i].mode;
693 data->operand[i].strict_low = insn_data[icode].operand[i].strict_low;
694 data->operand[i].is_operator
695 = insn_data[icode].operand[i].is_operator;
696 data->operand[i].type
697 = (data->operand[i].constraint[0] == '=' ? OP_OUT
698 : data->operand[i].constraint[0] == '+' ? OP_INOUT
699 : OP_IN);
700 data->operand[i].is_address = false;
702 for (i = 0; i < ndup; i++)
703 data->dup_num[i] = recog_data.dup_num[i];
705 return data;
708 /* The current length of the following array. */
709 int lra_insn_recog_data_len;
711 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
712 lra_insn_recog_data_t *lra_insn_recog_data;
714 /* Initialize LRA data about insns. */
715 static void
716 init_insn_recog_data (void)
718 lra_insn_recog_data_len = 0;
719 lra_insn_recog_data = NULL;
722 /* Expand, if necessary, LRA data about insns. */
723 static void
724 check_and_expand_insn_recog_data (int index)
726 int i, old;
728 if (lra_insn_recog_data_len > index)
729 return;
730 old = lra_insn_recog_data_len;
731 lra_insn_recog_data_len = index * 3 / 2 + 1;
732 lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t,
733 lra_insn_recog_data,
734 lra_insn_recog_data_len);
735 for (i = old; i < lra_insn_recog_data_len; i++)
736 lra_insn_recog_data[i] = NULL;
739 /* Finish LRA DATA about insn. */
740 static void
741 free_insn_recog_data (lra_insn_recog_data_t data)
743 if (data->operand_loc != NULL)
744 free (data->operand_loc);
745 if (data->dup_loc != NULL)
746 free (data->dup_loc);
747 if (data->arg_hard_regs != NULL)
748 free (data->arg_hard_regs);
749 if (data->icode < 0 && NONDEBUG_INSN_P (data->insn))
751 if (data->insn_static_data->operand_alternative != NULL)
752 free (const_cast <operand_alternative *>
753 (data->insn_static_data->operand_alternative));
754 free_insn_regs (data->insn_static_data->hard_regs);
755 free (data->insn_static_data);
757 free_insn_regs (data->regs);
758 data->regs = NULL;
759 free (data);
762 /* Pools for copies. */
763 static object_allocator<lra_copy> lra_copy_pool ("lra copies");
765 /* Finish LRA data about all insns. */
766 static void
767 finish_insn_recog_data (void)
769 int i;
770 lra_insn_recog_data_t data;
772 for (i = 0; i < lra_insn_recog_data_len; i++)
773 if ((data = lra_insn_recog_data[i]) != NULL)
774 free_insn_recog_data (data);
775 finish_insn_regs ();
776 lra_copy_pool.release ();
777 lra_insn_reg_pool.release ();
778 free (lra_insn_recog_data);
781 /* Setup info about operands in alternatives of LRA DATA of insn. */
782 static void
783 setup_operand_alternative (lra_insn_recog_data_t data,
784 const operand_alternative *op_alt)
786 int i, j, nop, nalt;
787 int icode = data->icode;
788 struct lra_static_insn_data *static_data = data->insn_static_data;
790 static_data->commutative = -1;
791 nop = static_data->n_operands;
792 nalt = static_data->n_alternatives;
793 static_data->operand_alternative = op_alt;
794 for (i = 0; i < nop; i++)
796 static_data->operand[i].early_clobber_alts = 0;
797 static_data->operand[i].early_clobber = false;
798 static_data->operand[i].is_address = false;
799 if (static_data->operand[i].constraint[0] == '%')
801 /* We currently only support one commutative pair of operands. */
802 if (static_data->commutative < 0)
803 static_data->commutative = i;
804 else
805 lra_assert (icode < 0); /* Asm */
806 /* The last operand should not be marked commutative. */
807 lra_assert (i != nop - 1);
810 for (j = 0; j < nalt; j++)
811 for (i = 0; i < nop; i++, op_alt++)
813 static_data->operand[i].early_clobber |= op_alt->earlyclobber;
814 if (op_alt->earlyclobber)
815 static_data->operand[i].early_clobber_alts |= (alternative_mask) 1 << j;
816 static_data->operand[i].is_address |= op_alt->is_address;
820 /* Recursively process X and collect info about registers, which are
821 not the insn operands, in X with TYPE (in/out/inout) and flag that
822 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
823 to LIST. X is a part of insn given by DATA. Return the result
824 list. */
825 static struct lra_insn_reg *
826 collect_non_operand_hard_regs (rtx_insn *insn, rtx *x,
827 lra_insn_recog_data_t data,
828 struct lra_insn_reg *list,
829 enum op_type type, bool early_clobber)
831 int i, j, regno, last;
832 bool subreg_p;
833 machine_mode mode;
834 struct lra_insn_reg *curr;
835 rtx op = *x;
836 enum rtx_code code = GET_CODE (op);
837 const char *fmt = GET_RTX_FORMAT (code);
839 for (i = 0; i < data->insn_static_data->n_operands; i++)
840 if (! data->insn_static_data->operand[i].is_operator
841 && x == data->operand_loc[i])
842 /* It is an operand loc. Stop here. */
843 return list;
844 for (i = 0; i < data->insn_static_data->n_dups; i++)
845 if (x == data->dup_loc[i])
846 /* It is a dup loc. Stop here. */
847 return list;
848 mode = GET_MODE (op);
849 subreg_p = false;
850 if (code == SUBREG)
852 mode = wider_subreg_mode (op);
853 if (read_modify_subreg_p (op))
854 subreg_p = true;
855 op = SUBREG_REG (op);
856 code = GET_CODE (op);
858 if (REG_P (op))
860 if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)
861 return list;
862 /* Process all regs even unallocatable ones as we need info
863 about all regs for rematerialization pass. */
864 for (last = end_hard_regno (mode, regno); regno < last; regno++)
866 for (curr = list; curr != NULL; curr = curr->next)
867 if (curr->regno == regno && curr->subreg_p == subreg_p
868 && curr->biggest_mode == mode)
870 if (curr->type != type)
871 curr->type = OP_INOUT;
872 if (early_clobber)
874 curr->early_clobber = true;
875 curr->early_clobber_alts = ALL_ALTERNATIVES;
877 break;
879 if (curr == NULL)
881 /* This is a new hard regno or the info can not be
882 integrated into the found structure. */
883 #ifdef STACK_REGS
884 early_clobber
885 = (early_clobber
886 /* This clobber is to inform popping floating
887 point stack only. */
888 && ! (FIRST_STACK_REG <= regno
889 && regno <= LAST_STACK_REG));
890 #endif
891 list = new_insn_reg (data->insn, regno, type, mode, subreg_p,
892 early_clobber,
893 early_clobber ? ALL_ALTERNATIVES : 0, list);
896 return list;
898 switch (code)
900 case SET:
901 list = collect_non_operand_hard_regs (insn, &SET_DEST (op), data,
902 list, OP_OUT, false);
903 list = collect_non_operand_hard_regs (insn, &SET_SRC (op), data,
904 list, OP_IN, false);
905 break;
906 case CLOBBER:
907 /* We treat clobber of non-operand hard registers as early clobber. */
908 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
909 list, OP_OUT, true);
910 break;
911 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
912 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
913 list, OP_INOUT, false);
914 break;
915 case PRE_MODIFY: case POST_MODIFY:
916 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
917 list, OP_INOUT, false);
918 list = collect_non_operand_hard_regs (insn, &XEXP (op, 1), data,
919 list, OP_IN, false);
920 break;
921 default:
922 fmt = GET_RTX_FORMAT (code);
923 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
925 if (fmt[i] == 'e')
926 list = collect_non_operand_hard_regs (insn, &XEXP (op, i), data,
927 list, OP_IN, false);
928 else if (fmt[i] == 'E')
929 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
930 list = collect_non_operand_hard_regs (insn, &XVECEXP (op, i, j),
931 data, list, OP_IN, false);
934 return list;
937 /* Set up and return info about INSN. Set up the info if it is not set up
938 yet. */
939 lra_insn_recog_data_t
940 lra_set_insn_recog_data (rtx_insn *insn)
942 lra_insn_recog_data_t data;
943 int i, n, icode;
944 rtx **locs;
945 unsigned int uid = INSN_UID (insn);
946 struct lra_static_insn_data *insn_static_data;
948 check_and_expand_insn_recog_data (uid);
949 if (DEBUG_INSN_P (insn))
950 icode = -1;
951 else
953 icode = INSN_CODE (insn);
954 if (icode < 0)
955 /* It might be a new simple insn which is not recognized yet. */
956 INSN_CODE (insn) = icode = recog_memoized (insn);
958 data = XNEW (struct lra_insn_recog_data);
959 lra_insn_recog_data[uid] = data;
960 data->insn = insn;
961 data->used_insn_alternative = LRA_UNKNOWN_ALT;
962 data->icode = icode;
963 data->regs = NULL;
964 if (DEBUG_INSN_P (insn))
966 data->dup_loc = NULL;
967 data->arg_hard_regs = NULL;
968 data->preferred_alternatives = ALL_ALTERNATIVES;
969 if (DEBUG_BIND_INSN_P (insn))
971 data->insn_static_data = &debug_bind_static_data;
972 data->operand_loc = XNEWVEC (rtx *, 1);
973 data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn);
975 else if (DEBUG_MARKER_INSN_P (insn))
977 data->insn_static_data = &debug_marker_static_data;
978 data->operand_loc = NULL;
980 return data;
982 if (icode < 0)
984 int nop, nalt;
985 machine_mode operand_mode[MAX_RECOG_OPERANDS];
986 const char *constraints[MAX_RECOG_OPERANDS];
988 nop = asm_noperands (PATTERN (insn));
989 data->operand_loc = data->dup_loc = NULL;
990 nalt = 1;
991 if (nop < 0)
993 /* It is a special insn like USE or CLOBBER. We should
994 recognize any regular insn otherwise LRA can do nothing
995 with this insn. */
996 gcc_assert (GET_CODE (PATTERN (insn)) == USE
997 || GET_CODE (PATTERN (insn)) == CLOBBER
998 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
999 data->insn_static_data = insn_static_data
1000 = get_static_insn_data (-1, 0, 0, nalt);
1002 else
1004 /* expand_asm_operands makes sure there aren't too many
1005 operands. */
1006 lra_assert (nop <= MAX_RECOG_OPERANDS);
1007 if (nop != 0)
1008 data->operand_loc = XNEWVEC (rtx *, nop);
1009 /* Now get the operand values and constraints out of the
1010 insn. */
1011 decode_asm_operands (PATTERN (insn), NULL,
1012 data->operand_loc,
1013 constraints, operand_mode, NULL);
1014 if (nop > 0)
1016 const char *p = recog_data.constraints[0];
1018 for (p = constraints[0]; *p; p++)
1019 nalt += *p == ',';
1021 data->insn_static_data = insn_static_data
1022 = get_static_insn_data (-1, nop, 0, nalt);
1023 for (i = 0; i < nop; i++)
1025 insn_static_data->operand[i].mode = operand_mode[i];
1026 insn_static_data->operand[i].constraint = constraints[i];
1027 insn_static_data->operand[i].strict_low = false;
1028 insn_static_data->operand[i].is_operator = false;
1029 insn_static_data->operand[i].is_address = false;
1032 for (i = 0; i < insn_static_data->n_operands; i++)
1033 insn_static_data->operand[i].type
1034 = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT
1035 : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT
1036 : OP_IN);
1037 data->preferred_alternatives = ALL_ALTERNATIVES;
1038 if (nop > 0)
1040 operand_alternative *op_alt = XCNEWVEC (operand_alternative,
1041 nalt * nop);
1042 preprocess_constraints (nop, nalt, constraints, op_alt,
1043 data->operand_loc);
1044 setup_operand_alternative (data, op_alt);
1047 else
1049 insn_extract (insn);
1050 data->insn_static_data = insn_static_data
1051 = get_static_insn_data (icode, insn_data[icode].n_operands,
1052 insn_data[icode].n_dups,
1053 insn_data[icode].n_alternatives);
1054 n = insn_static_data->n_operands;
1055 if (n == 0)
1056 locs = NULL;
1057 else
1059 locs = XNEWVEC (rtx *, n);
1060 memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *));
1062 data->operand_loc = locs;
1063 n = insn_static_data->n_dups;
1064 if (n == 0)
1065 locs = NULL;
1066 else
1068 locs = XNEWVEC (rtx *, n);
1069 memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *));
1071 data->dup_loc = locs;
1072 data->preferred_alternatives = get_preferred_alternatives (insn);
1073 const operand_alternative *op_alt = preprocess_insn_constraints (icode);
1074 if (!insn_static_data->operand_alternative)
1075 setup_operand_alternative (data, op_alt);
1076 else if (op_alt != insn_static_data->operand_alternative)
1077 insn_static_data->operand_alternative = op_alt;
1079 if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE)
1080 insn_static_data->hard_regs = NULL;
1081 else
1082 insn_static_data->hard_regs
1083 = collect_non_operand_hard_regs (insn, &PATTERN (insn), data,
1084 NULL, OP_IN, false);
1085 data->arg_hard_regs = NULL;
1086 if (CALL_P (insn))
1088 bool use_p;
1089 rtx link;
1090 int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER];
1092 n_hard_regs = 0;
1093 /* Finding implicit hard register usage. We believe it will be
1094 not changed whatever transformations are used. Call insns
1095 are such example. */
1096 for (link = CALL_INSN_FUNCTION_USAGE (insn);
1097 link != NULL_RTX;
1098 link = XEXP (link, 1))
1099 if (((use_p = GET_CODE (XEXP (link, 0)) == USE)
1100 || GET_CODE (XEXP (link, 0)) == CLOBBER)
1101 && REG_P (XEXP (XEXP (link, 0), 0)))
1103 regno = REGNO (XEXP (XEXP (link, 0), 0));
1104 lra_assert (regno < FIRST_PSEUDO_REGISTER);
1105 /* It is an argument register. */
1106 for (i = REG_NREGS (XEXP (XEXP (link, 0), 0)) - 1; i >= 0; i--)
1107 arg_hard_regs[n_hard_regs++]
1108 = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER);
1110 if (n_hard_regs != 0)
1112 arg_hard_regs[n_hard_regs++] = -1;
1113 data->arg_hard_regs = XNEWVEC (int, n_hard_regs);
1114 memcpy (data->arg_hard_regs, arg_hard_regs,
1115 sizeof (int) * n_hard_regs);
1118 /* Some output operand can be recognized only from the context not
1119 from the constraints which are empty in this case. Call insn may
1120 contain a hard register in set destination with empty constraint
1121 and extract_insn treats them as an input. */
1122 for (i = 0; i < insn_static_data->n_operands; i++)
1124 int j;
1125 rtx pat, set;
1126 struct lra_operand_data *operand = &insn_static_data->operand[i];
1128 /* ??? Should we treat 'X' the same way. It looks to me that
1129 'X' means anything and empty constraint means we do not
1130 care. */
1131 if (operand->type != OP_IN || *operand->constraint != '\0'
1132 || operand->is_operator)
1133 continue;
1134 pat = PATTERN (insn);
1135 if (GET_CODE (pat) == SET)
1137 if (data->operand_loc[i] != &SET_DEST (pat))
1138 continue;
1140 else if (GET_CODE (pat) == PARALLEL)
1142 for (j = XVECLEN (pat, 0) - 1; j >= 0; j--)
1144 set = XVECEXP (PATTERN (insn), 0, j);
1145 if (GET_CODE (set) == SET
1146 && &SET_DEST (set) == data->operand_loc[i])
1147 break;
1149 if (j < 0)
1150 continue;
1152 else
1153 continue;
1154 operand->type = OP_OUT;
1156 return data;
1159 /* Return info about insn give by UID. The info should be already set
1160 up. */
1161 static lra_insn_recog_data_t
1162 get_insn_recog_data_by_uid (int uid)
1164 lra_insn_recog_data_t data;
1166 data = lra_insn_recog_data[uid];
1167 lra_assert (data != NULL);
1168 return data;
1171 /* Invalidate all info about insn given by its UID. */
1172 static void
1173 invalidate_insn_recog_data (int uid)
1175 lra_insn_recog_data_t data;
1177 data = lra_insn_recog_data[uid];
1178 lra_assert (data != NULL);
1179 free_insn_recog_data (data);
1180 lra_insn_recog_data[uid] = NULL;
1183 /* Update all the insn info about INSN. It is usually called when
1184 something in the insn was changed. Return the updated info. */
1185 lra_insn_recog_data_t
1186 lra_update_insn_recog_data (rtx_insn *insn)
1188 lra_insn_recog_data_t data;
1189 int n;
1190 unsigned int uid = INSN_UID (insn);
1191 struct lra_static_insn_data *insn_static_data;
1192 poly_int64 sp_offset = 0;
1194 check_and_expand_insn_recog_data (uid);
1195 if ((data = lra_insn_recog_data[uid]) != NULL
1196 && data->icode != INSN_CODE (insn))
1198 sp_offset = data->sp_offset;
1199 invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn));
1200 invalidate_insn_recog_data (uid);
1201 data = NULL;
1203 if (data == NULL)
1205 data = lra_get_insn_recog_data (insn);
1206 /* Initiate or restore SP offset. */
1207 data->sp_offset = sp_offset;
1208 return data;
1210 insn_static_data = data->insn_static_data;
1211 data->used_insn_alternative = LRA_UNKNOWN_ALT;
1212 if (DEBUG_INSN_P (insn))
1213 return data;
1214 if (data->icode < 0)
1216 int nop;
1217 machine_mode operand_mode[MAX_RECOG_OPERANDS];
1218 const char *constraints[MAX_RECOG_OPERANDS];
1220 nop = asm_noperands (PATTERN (insn));
1221 if (nop >= 0)
1223 lra_assert (nop == data->insn_static_data->n_operands);
1224 /* Now get the operand values and constraints out of the
1225 insn. */
1226 decode_asm_operands (PATTERN (insn), NULL,
1227 data->operand_loc,
1228 constraints, operand_mode, NULL);
1230 if (flag_checking)
1231 for (int i = 0; i < nop; i++)
1232 lra_assert
1233 (insn_static_data->operand[i].mode == operand_mode[i]
1234 && insn_static_data->operand[i].constraint == constraints[i]
1235 && ! insn_static_data->operand[i].is_operator);
1238 if (flag_checking)
1239 for (int i = 0; i < insn_static_data->n_operands; i++)
1240 lra_assert
1241 (insn_static_data->operand[i].type
1242 == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT
1243 : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT
1244 : OP_IN));
1246 else
1248 insn_extract (insn);
1249 n = insn_static_data->n_operands;
1250 if (n != 0)
1251 memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *));
1252 n = insn_static_data->n_dups;
1253 if (n != 0)
1254 memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *));
1255 lra_assert (check_bool_attrs (insn));
1257 return data;
1260 /* Set up that INSN is using alternative ALT now. */
1261 void
1262 lra_set_used_insn_alternative (rtx_insn *insn, int alt)
1264 lra_insn_recog_data_t data;
1266 data = lra_get_insn_recog_data (insn);
1267 data->used_insn_alternative = alt;
1270 /* Set up that insn with UID is using alternative ALT now. The insn
1271 info should be already set up. */
1272 void
1273 lra_set_used_insn_alternative_by_uid (int uid, int alt)
1275 lra_insn_recog_data_t data;
1277 check_and_expand_insn_recog_data (uid);
1278 data = lra_insn_recog_data[uid];
1279 lra_assert (data != NULL);
1280 data->used_insn_alternative = alt;
1285 /* This page contains code dealing with common register info and
1286 pseudo copies. */
1288 /* The size of the following array. */
1289 static int reg_info_size;
1290 /* Common info about each register. */
1291 struct lra_reg *lra_reg_info;
1293 HARD_REG_SET hard_regs_spilled_into;
1295 /* Last register value. */
1296 static int last_reg_value;
1298 /* Return new register value. */
1299 static int
1300 get_new_reg_value (void)
1302 return ++last_reg_value;
1305 /* Vec referring to pseudo copies. */
1306 static vec<lra_copy_t> copy_vec;
1308 /* Initialize I-th element of lra_reg_info. */
1309 static inline void
1310 initialize_lra_reg_info_element (int i)
1312 bitmap_initialize (&lra_reg_info[i].insn_bitmap, &reg_obstack);
1313 #ifdef STACK_REGS
1314 lra_reg_info[i].no_stack_p = false;
1315 #endif
1316 CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs);
1317 CLEAR_HARD_REG_SET (lra_reg_info[i].actual_call_used_reg_set);
1318 lra_reg_info[i].preferred_hard_regno1 = -1;
1319 lra_reg_info[i].preferred_hard_regno2 = -1;
1320 lra_reg_info[i].preferred_hard_regno_profit1 = 0;
1321 lra_reg_info[i].preferred_hard_regno_profit2 = 0;
1322 lra_reg_info[i].biggest_mode = VOIDmode;
1323 lra_reg_info[i].live_ranges = NULL;
1324 lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0;
1325 lra_reg_info[i].last_reload = 0;
1326 lra_reg_info[i].restore_rtx = NULL_RTX;
1327 lra_reg_info[i].val = get_new_reg_value ();
1328 lra_reg_info[i].offset = 0;
1329 lra_reg_info[i].copies = NULL;
1332 /* Initialize common reg info and copies. */
1333 static void
1334 init_reg_info (void)
1336 int i;
1338 last_reg_value = 0;
1339 reg_info_size = max_reg_num () * 3 / 2 + 1;
1340 lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size);
1341 for (i = 0; i < reg_info_size; i++)
1342 initialize_lra_reg_info_element (i);
1343 copy_vec.truncate (0);
1344 CLEAR_HARD_REG_SET (hard_regs_spilled_into);
1348 /* Finish common reg info and copies. */
1349 static void
1350 finish_reg_info (void)
1352 int i;
1354 for (i = 0; i < reg_info_size; i++)
1355 bitmap_clear (&lra_reg_info[i].insn_bitmap);
1356 free (lra_reg_info);
1357 reg_info_size = 0;
1360 /* Expand common reg info if it is necessary. */
1361 static void
1362 expand_reg_info (void)
1364 int i, old = reg_info_size;
1366 if (reg_info_size > max_reg_num ())
1367 return;
1368 reg_info_size = max_reg_num () * 3 / 2 + 1;
1369 lra_reg_info = XRESIZEVEC (struct lra_reg, lra_reg_info, reg_info_size);
1370 for (i = old; i < reg_info_size; i++)
1371 initialize_lra_reg_info_element (i);
1374 /* Free all copies. */
1375 void
1376 lra_free_copies (void)
1378 lra_copy_t cp;
1380 while (copy_vec.length () != 0)
1382 cp = copy_vec.pop ();
1383 lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULL;
1384 lra_copy_pool.remove (cp);
1388 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1389 frequency is FREQ. */
1390 void
1391 lra_create_copy (int regno1, int regno2, int freq)
1393 bool regno1_dest_p;
1394 lra_copy_t cp;
1396 lra_assert (regno1 != regno2);
1397 regno1_dest_p = true;
1398 if (regno1 > regno2)
1400 std::swap (regno1, regno2);
1401 regno1_dest_p = false;
1403 cp = lra_copy_pool.allocate ();
1404 copy_vec.safe_push (cp);
1405 cp->regno1_dest_p = regno1_dest_p;
1406 cp->freq = freq;
1407 cp->regno1 = regno1;
1408 cp->regno2 = regno2;
1409 cp->regno1_next = lra_reg_info[regno1].copies;
1410 lra_reg_info[regno1].copies = cp;
1411 cp->regno2_next = lra_reg_info[regno2].copies;
1412 lra_reg_info[regno2].copies = cp;
1413 if (lra_dump_file != NULL)
1414 fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n",
1415 regno1, regno1_dest_p ? "<-" : "->", regno2, freq);
1418 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1419 NULL. */
1420 lra_copy_t
1421 lra_get_copy (int n)
1423 if (n >= (int) copy_vec.length ())
1424 return NULL;
1425 return copy_vec[n];
1430 /* This page contains code dealing with info about registers in
1431 insns. */
1433 /* Process X of INSN recursively and add info (operand type is
1434 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1435 about registers in X to the insn DATA. If X can be early clobbered,
1436 alternatives in which it can be early clobbered are given by
1437 EARLY_CLOBBER_ALTS. */
1438 static void
1439 add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x,
1440 rtx_insn *insn,
1441 enum op_type type, bool early_clobber,
1442 alternative_mask early_clobber_alts)
1444 int i, j, regno;
1445 bool subreg_p;
1446 machine_mode mode;
1447 const char *fmt;
1448 enum rtx_code code;
1449 struct lra_insn_reg *curr;
1451 code = GET_CODE (x);
1452 mode = GET_MODE (x);
1453 subreg_p = false;
1454 if (GET_CODE (x) == SUBREG)
1456 mode = wider_subreg_mode (x);
1457 if (read_modify_subreg_p (x))
1458 subreg_p = true;
1459 x = SUBREG_REG (x);
1460 code = GET_CODE (x);
1462 if (REG_P (x))
1464 regno = REGNO (x);
1465 /* Process all regs even unallocatable ones as we need info about
1466 all regs for rematerialization pass. */
1467 expand_reg_info ();
1468 if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, INSN_UID (insn)))
1470 data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p,
1471 early_clobber, early_clobber_alts,
1472 data->regs);
1473 return;
1475 else
1477 for (curr = data->regs; curr != NULL; curr = curr->next)
1478 if (curr->regno == regno)
1480 if (curr->subreg_p != subreg_p || curr->biggest_mode != mode)
1481 /* The info can not be integrated into the found
1482 structure. */
1483 data->regs = new_insn_reg (data->insn, regno, type, mode,
1484 subreg_p, early_clobber,
1485 early_clobber_alts, data->regs);
1486 else
1488 if (curr->type != type)
1489 curr->type = OP_INOUT;
1490 if (curr->early_clobber != early_clobber)
1491 curr->early_clobber = true;
1492 curr->early_clobber_alts |= early_clobber_alts;
1494 return;
1496 gcc_unreachable ();
1500 switch (code)
1502 case SET:
1503 add_regs_to_insn_regno_info (data, SET_DEST (x), insn, OP_OUT, false, 0);
1504 add_regs_to_insn_regno_info (data, SET_SRC (x), insn, OP_IN, false, 0);
1505 break;
1506 case CLOBBER:
1507 /* We treat clobber of non-operand hard registers as early
1508 clobber. */
1509 add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_OUT,
1510 true, ALL_ALTERNATIVES);
1511 break;
1512 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
1513 add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0);
1514 break;
1515 case PRE_MODIFY: case POST_MODIFY:
1516 add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0);
1517 add_regs_to_insn_regno_info (data, XEXP (x, 1), insn, OP_IN, false, 0);
1518 break;
1519 default:
1520 if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT)
1521 /* Some targets place small structures in registers for return
1522 values of functions, and those registers are wrapped in
1523 PARALLEL that we may see as the destination of a SET. Here
1524 is an example:
1526 (call_insn 13 12 14 2 (set (parallel:BLK [
1527 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1528 (const_int 0 [0]))
1529 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1530 (const_int 8 [0x8]))
1532 (call (mem:QI (symbol_ref:DI (... */
1533 type = OP_IN;
1534 fmt = GET_RTX_FORMAT (code);
1535 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1537 if (fmt[i] == 'e')
1538 add_regs_to_insn_regno_info (data, XEXP (x, i), insn, type, false, 0);
1539 else if (fmt[i] == 'E')
1541 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1542 add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), insn,
1543 type, false, 0);
1549 /* Return execution frequency of INSN. */
1550 static int
1551 get_insn_freq (rtx_insn *insn)
1553 basic_block bb = BLOCK_FOR_INSN (insn);
1555 gcc_checking_assert (bb != NULL);
1556 return REG_FREQ_FROM_BB (bb);
1559 /* Invalidate all reg info of INSN with DATA and execution frequency
1560 FREQ. Update common info about the invalidated registers. */
1561 static void
1562 invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx_insn *insn,
1563 int freq)
1565 int uid;
1566 bool debug_p;
1567 unsigned int i;
1568 struct lra_insn_reg *ir, *next_ir;
1570 uid = INSN_UID (insn);
1571 debug_p = DEBUG_INSN_P (insn);
1572 for (ir = data->regs; ir != NULL; ir = next_ir)
1574 i = ir->regno;
1575 next_ir = ir->next;
1576 lra_insn_reg_pool.remove (ir);
1577 bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid);
1578 if (i >= FIRST_PSEUDO_REGISTER && ! debug_p)
1580 lra_reg_info[i].nrefs--;
1581 lra_reg_info[i].freq -= freq;
1582 lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0);
1585 data->regs = NULL;
1588 /* Invalidate all reg info of INSN. Update common info about the
1589 invalidated registers. */
1590 void
1591 lra_invalidate_insn_regno_info (rtx_insn *insn)
1593 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn,
1594 get_insn_freq (insn));
1597 /* Update common reg info from reg info of insn given by its DATA and
1598 execution frequency FREQ. */
1599 static void
1600 setup_insn_reg_info (lra_insn_recog_data_t data, int freq)
1602 unsigned int i;
1603 struct lra_insn_reg *ir;
1605 for (ir = data->regs; ir != NULL; ir = ir->next)
1606 if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER)
1608 lra_reg_info[i].nrefs++;
1609 lra_reg_info[i].freq += freq;
1613 /* Set up insn reg info of INSN. Update common reg info from reg info
1614 of INSN. */
1615 void
1616 lra_update_insn_regno_info (rtx_insn *insn)
1618 int i, freq;
1619 lra_insn_recog_data_t data;
1620 struct lra_static_insn_data *static_data;
1621 enum rtx_code code;
1622 rtx link;
1624 if (! INSN_P (insn))
1625 return;
1626 data = lra_get_insn_recog_data (insn);
1627 static_data = data->insn_static_data;
1628 freq = NONDEBUG_INSN_P (insn) ? get_insn_freq (insn) : 0;
1629 invalidate_insn_data_regno_info (data, insn, freq);
1630 for (i = static_data->n_operands - 1; i >= 0; i--)
1631 add_regs_to_insn_regno_info (data, *data->operand_loc[i], insn,
1632 static_data->operand[i].type,
1633 static_data->operand[i].early_clobber,
1634 static_data->operand[i].early_clobber_alts);
1635 if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE)
1636 add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), insn,
1637 code == USE ? OP_IN : OP_OUT, false, 0);
1638 if (CALL_P (insn))
1639 /* On some targets call insns can refer to pseudos in memory in
1640 CALL_INSN_FUNCTION_USAGE list. Process them in order to
1641 consider their occurrences in calls for different
1642 transformations (e.g. inheritance) with given pseudos. */
1643 for (link = CALL_INSN_FUNCTION_USAGE (insn);
1644 link != NULL_RTX;
1645 link = XEXP (link, 1))
1646 if (((code = GET_CODE (XEXP (link, 0))) == USE || code == CLOBBER)
1647 && MEM_P (XEXP (XEXP (link, 0), 0)))
1648 add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), insn,
1649 code == USE ? OP_IN : OP_OUT, false, 0);
1650 if (NONDEBUG_INSN_P (insn))
1651 setup_insn_reg_info (data, freq);
1654 /* Return reg info of insn given by it UID. */
1655 struct lra_insn_reg *
1656 lra_get_insn_regs (int uid)
1658 lra_insn_recog_data_t data;
1660 data = get_insn_recog_data_by_uid (uid);
1661 return data->regs;
1666 /* Recursive hash function for RTL X. */
1667 hashval_t
1668 lra_rtx_hash (rtx x)
1670 int i, j;
1671 enum rtx_code code;
1672 const char *fmt;
1673 hashval_t val = 0;
1675 if (x == 0)
1676 return val;
1678 code = GET_CODE (x);
1679 val += (int) code + 4095;
1681 /* Some RTL can be compared nonrecursively. */
1682 switch (code)
1684 case REG:
1685 return val + REGNO (x);
1687 case LABEL_REF:
1688 return iterative_hash_object (XEXP (x, 0), val);
1690 case SYMBOL_REF:
1691 return iterative_hash_object (XSTR (x, 0), val);
1693 case SCRATCH:
1694 case CONST_DOUBLE:
1695 case CONST_INT:
1696 case CONST_VECTOR:
1697 return val;
1699 default:
1700 break;
1703 /* Hash the elements. */
1704 fmt = GET_RTX_FORMAT (code);
1705 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1707 switch (fmt[i])
1709 case 'w':
1710 val += XWINT (x, i);
1711 break;
1713 case 'n':
1714 case 'i':
1715 val += XINT (x, i);
1716 break;
1718 case 'V':
1719 case 'E':
1720 val += XVECLEN (x, i);
1722 for (j = 0; j < XVECLEN (x, i); j++)
1723 val += lra_rtx_hash (XVECEXP (x, i, j));
1724 break;
1726 case 'e':
1727 val += lra_rtx_hash (XEXP (x, i));
1728 break;
1730 case 'S':
1731 case 's':
1732 val += htab_hash_string (XSTR (x, i));
1733 break;
1735 case 'u':
1736 case '0':
1737 case 't':
1738 break;
1740 /* It is believed that rtx's at this level will never
1741 contain anything but integers and other rtx's, except for
1742 within LABEL_REFs and SYMBOL_REFs. */
1743 default:
1744 abort ();
1747 return val;
1752 /* This page contains code dealing with stack of the insns which
1753 should be processed by the next constraint pass. */
1755 /* Bitmap used to put an insn on the stack only in one exemplar. */
1756 static sbitmap lra_constraint_insn_stack_bitmap;
1758 /* The stack itself. */
1759 vec<rtx_insn *> lra_constraint_insn_stack;
1761 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1762 info for INSN, otherwise only update it if INSN is not already on the
1763 stack. */
1764 static inline void
1765 lra_push_insn_1 (rtx_insn *insn, bool always_update)
1767 unsigned int uid = INSN_UID (insn);
1768 if (always_update)
1769 lra_update_insn_regno_info (insn);
1770 if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap))
1771 lra_constraint_insn_stack_bitmap =
1772 sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0);
1773 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid))
1774 return;
1775 bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid);
1776 if (! always_update)
1777 lra_update_insn_regno_info (insn);
1778 lra_constraint_insn_stack.safe_push (insn);
1781 /* Put INSN on the stack. */
1782 void
1783 lra_push_insn (rtx_insn *insn)
1785 lra_push_insn_1 (insn, false);
1788 /* Put INSN on the stack and update its reg info. */
1789 void
1790 lra_push_insn_and_update_insn_regno_info (rtx_insn *insn)
1792 lra_push_insn_1 (insn, true);
1795 /* Put insn with UID on the stack. */
1796 void
1797 lra_push_insn_by_uid (unsigned int uid)
1799 lra_push_insn (lra_insn_recog_data[uid]->insn);
1802 /* Take the last-inserted insns off the stack and return it. */
1803 rtx_insn *
1804 lra_pop_insn (void)
1806 rtx_insn *insn = lra_constraint_insn_stack.pop ();
1807 bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn));
1808 return insn;
1811 /* Return the current size of the insn stack. */
1812 unsigned int
1813 lra_insn_stack_length (void)
1815 return lra_constraint_insn_stack.length ();
1818 /* Push insns FROM to TO (excluding it) going in reverse order. */
1819 static void
1820 push_insns (rtx_insn *from, rtx_insn *to)
1822 rtx_insn *insn;
1824 if (from == NULL_RTX)
1825 return;
1826 for (insn = from; insn != to; insn = PREV_INSN (insn))
1827 if (INSN_P (insn))
1828 lra_push_insn (insn);
1831 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
1832 taken from the next BB insn after LAST or zero if there in such
1833 insn. */
1834 static void
1835 setup_sp_offset (rtx_insn *from, rtx_insn *last)
1837 rtx_insn *before = next_nonnote_nondebug_insn_bb (last);
1838 poly_int64 offset = (before == NULL_RTX || ! INSN_P (before)
1839 ? 0 : lra_get_insn_recog_data (before)->sp_offset);
1841 for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
1842 lra_get_insn_recog_data (insn)->sp_offset = offset;
1845 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1846 insns onto the stack. Print about emitting the insns with
1847 TITLE. */
1848 void
1849 lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after,
1850 const char *title)
1852 rtx_insn *last;
1854 if (before == NULL_RTX && after == NULL_RTX)
1855 return;
1856 if (lra_dump_file != NULL)
1858 dump_insn_slim (lra_dump_file, insn);
1859 if (before != NULL_RTX)
1861 fprintf (lra_dump_file," %s before:\n", title);
1862 dump_rtl_slim (lra_dump_file, before, NULL, -1, 0);
1864 if (after != NULL_RTX)
1866 fprintf (lra_dump_file, " %s after:\n", title);
1867 dump_rtl_slim (lra_dump_file, after, NULL, -1, 0);
1869 fprintf (lra_dump_file, "\n");
1871 if (before != NULL_RTX)
1873 if (cfun->can_throw_non_call_exceptions)
1874 copy_reg_eh_region_note_forward (insn, before, NULL);
1875 emit_insn_before (before, insn);
1876 push_insns (PREV_INSN (insn), PREV_INSN (before));
1877 setup_sp_offset (before, PREV_INSN (insn));
1879 if (after != NULL_RTX)
1881 if (cfun->can_throw_non_call_exceptions)
1882 copy_reg_eh_region_note_forward (insn, after, NULL);
1883 for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last))
1885 emit_insn_after (after, insn);
1886 push_insns (last, insn);
1887 setup_sp_offset (after, last);
1889 if (cfun->can_throw_non_call_exceptions)
1891 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
1892 if (note && !insn_could_throw_p (insn))
1893 remove_note (insn, note);
1898 /* Replace all references to register OLD_REGNO in *LOC with pseudo
1899 register NEW_REG. Try to simplify subreg of constant if SUBREG_P.
1900 DEBUG_P is if LOC is within a DEBUG_INSN. Return true if any
1901 change was made. */
1902 bool
1903 lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p,
1904 bool debug_p)
1906 rtx x = *loc;
1907 bool result = false;
1908 enum rtx_code code;
1909 const char *fmt;
1910 int i, j;
1912 if (x == NULL_RTX)
1913 return false;
1915 code = GET_CODE (x);
1916 if (code == SUBREG && subreg_p)
1918 rtx subst, inner = SUBREG_REG (x);
1919 /* Transform subreg of constant while we still have inner mode
1920 of the subreg. The subreg internal should not be an insn
1921 operand. */
1922 if (REG_P (inner) && (int) REGNO (inner) == old_regno
1923 && CONSTANT_P (new_reg)
1924 && (subst = simplify_subreg (GET_MODE (x), new_reg, GET_MODE (inner),
1925 SUBREG_BYTE (x))) != NULL_RTX)
1927 *loc = subst;
1928 return true;
1932 else if (code == REG && (int) REGNO (x) == old_regno)
1934 machine_mode mode = GET_MODE (x);
1935 machine_mode inner_mode = GET_MODE (new_reg);
1937 if (mode != inner_mode
1938 && ! (CONST_INT_P (new_reg) && SCALAR_INT_MODE_P (mode)))
1940 poly_uint64 offset = 0;
1941 if (partial_subreg_p (mode, inner_mode)
1942 && SCALAR_INT_MODE_P (inner_mode))
1943 offset = subreg_lowpart_offset (mode, inner_mode);
1944 if (debug_p)
1945 new_reg = gen_rtx_raw_SUBREG (mode, new_reg, offset);
1946 else
1947 new_reg = gen_rtx_SUBREG (mode, new_reg, offset);
1949 *loc = new_reg;
1950 return true;
1953 /* Scan all the operand sub-expressions. */
1954 fmt = GET_RTX_FORMAT (code);
1955 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1957 if (fmt[i] == 'e')
1959 if (lra_substitute_pseudo (&XEXP (x, i), old_regno,
1960 new_reg, subreg_p, debug_p))
1961 result = true;
1963 else if (fmt[i] == 'E')
1965 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1966 if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno,
1967 new_reg, subreg_p, debug_p))
1968 result = true;
1971 return result;
1974 /* Call lra_substitute_pseudo within an insn. Try to simplify subreg
1975 of constant if SUBREG_P. This won't update the insn ptr, just the
1976 contents of the insn. */
1977 bool
1978 lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno,
1979 rtx new_reg, bool subreg_p)
1981 rtx loc = insn;
1982 return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p,
1983 DEBUG_INSN_P (insn));
1988 /* This page contains code dealing with scratches (changing them onto
1989 pseudos and restoring them from the pseudos).
1991 We change scratches into pseudos at the beginning of LRA to
1992 simplify dealing with them (conflicts, hard register assignments).
1994 If the pseudo denoting scratch was spilled it means that we do need
1995 a hard register for it. Such pseudos are transformed back to
1996 scratches at the end of LRA. */
1998 /* Description of location of a former scratch operand. */
1999 struct sloc
2001 rtx_insn *insn; /* Insn where the scratch was. */
2002 int nop; /* Number of the operand which was a scratch. */
2005 typedef struct sloc *sloc_t;
2007 /* Locations of the former scratches. */
2008 static vec<sloc_t> scratches;
2010 /* Bitmap of scratch regnos. */
2011 static bitmap_head scratch_bitmap;
2013 /* Bitmap of scratch operands. */
2014 static bitmap_head scratch_operand_bitmap;
2016 /* Return true if pseudo REGNO is made of SCRATCH. */
2017 bool
2018 lra_former_scratch_p (int regno)
2020 return bitmap_bit_p (&scratch_bitmap, regno);
2023 /* Return true if the operand NOP of INSN is a former scratch. */
2024 bool
2025 lra_former_scratch_operand_p (rtx_insn *insn, int nop)
2027 return bitmap_bit_p (&scratch_operand_bitmap,
2028 INSN_UID (insn) * MAX_RECOG_OPERANDS + nop) != 0;
2031 /* Register operand NOP in INSN as a former scratch. It will be
2032 changed to scratch back, if it is necessary, at the LRA end. */
2033 void
2034 lra_register_new_scratch_op (rtx_insn *insn, int nop)
2036 lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
2037 rtx op = *id->operand_loc[nop];
2038 sloc_t loc = XNEW (struct sloc);
2039 lra_assert (REG_P (op));
2040 loc->insn = insn;
2041 loc->nop = nop;
2042 scratches.safe_push (loc);
2043 bitmap_set_bit (&scratch_bitmap, REGNO (op));
2044 bitmap_set_bit (&scratch_operand_bitmap,
2045 INSN_UID (insn) * MAX_RECOG_OPERANDS + nop);
2046 add_reg_note (insn, REG_UNUSED, op);
2049 /* Change scratches onto pseudos and save their location. */
2050 static void
2051 remove_scratches (void)
2053 int i;
2054 bool insn_changed_p;
2055 basic_block bb;
2056 rtx_insn *insn;
2057 rtx reg;
2058 lra_insn_recog_data_t id;
2059 struct lra_static_insn_data *static_id;
2061 scratches.create (get_max_uid ());
2062 bitmap_initialize (&scratch_bitmap, &reg_obstack);
2063 bitmap_initialize (&scratch_operand_bitmap, &reg_obstack);
2064 FOR_EACH_BB_FN (bb, cfun)
2065 FOR_BB_INSNS (bb, insn)
2066 if (INSN_P (insn))
2068 id = lra_get_insn_recog_data (insn);
2069 static_id = id->insn_static_data;
2070 insn_changed_p = false;
2071 for (i = 0; i < static_id->n_operands; i++)
2072 if (GET_CODE (*id->operand_loc[i]) == SCRATCH
2073 && GET_MODE (*id->operand_loc[i]) != VOIDmode)
2075 insn_changed_p = true;
2076 *id->operand_loc[i] = reg
2077 = lra_create_new_reg (static_id->operand[i].mode,
2078 *id->operand_loc[i], ALL_REGS, NULL);
2079 lra_register_new_scratch_op (insn, i);
2080 if (lra_dump_file != NULL)
2081 fprintf (lra_dump_file,
2082 "Removing SCRATCH in insn #%u (nop %d)\n",
2083 INSN_UID (insn), i);
2085 if (insn_changed_p)
2086 /* Because we might use DF right after caller-saves sub-pass
2087 we need to keep DF info up to date. */
2088 df_insn_rescan (insn);
2092 /* Changes pseudos created by function remove_scratches onto scratches. */
2093 static void
2094 restore_scratches (void)
2096 int regno;
2097 unsigned i;
2098 sloc_t loc;
2099 rtx_insn *last = NULL;
2100 lra_insn_recog_data_t id = NULL;
2102 for (i = 0; scratches.iterate (i, &loc); i++)
2104 /* Ignore already deleted insns. */
2105 if (NOTE_P (loc->insn)
2106 && NOTE_KIND (loc->insn) == NOTE_INSN_DELETED)
2107 continue;
2108 if (last != loc->insn)
2110 last = loc->insn;
2111 id = lra_get_insn_recog_data (last);
2113 if (REG_P (*id->operand_loc[loc->nop])
2114 && ((regno = REGNO (*id->operand_loc[loc->nop]))
2115 >= FIRST_PSEUDO_REGISTER)
2116 && lra_get_regno_hard_regno (regno) < 0)
2118 /* It should be only case when scratch register with chosen
2119 constraint 'X' did not get memory or hard register. */
2120 lra_assert (lra_former_scratch_p (regno));
2121 *id->operand_loc[loc->nop]
2122 = gen_rtx_SCRATCH (GET_MODE (*id->operand_loc[loc->nop]));
2123 lra_update_dup (id, loc->nop);
2124 if (lra_dump_file != NULL)
2125 fprintf (lra_dump_file, "Restoring SCRATCH in insn #%u(nop %d)\n",
2126 INSN_UID (loc->insn), loc->nop);
2129 for (i = 0; scratches.iterate (i, &loc); i++)
2130 free (loc);
2131 scratches.release ();
2132 bitmap_clear (&scratch_bitmap);
2133 bitmap_clear (&scratch_operand_bitmap);
2138 /* Function checks RTL for correctness. If FINAL_P is true, it is
2139 done at the end of LRA and the check is more rigorous. */
2140 static void
2141 check_rtl (bool final_p)
2143 basic_block bb;
2144 rtx_insn *insn;
2146 lra_assert (! final_p || reload_completed);
2147 FOR_EACH_BB_FN (bb, cfun)
2148 FOR_BB_INSNS (bb, insn)
2149 if (NONDEBUG_INSN_P (insn)
2150 && GET_CODE (PATTERN (insn)) != USE
2151 && GET_CODE (PATTERN (insn)) != CLOBBER
2152 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
2154 if (final_p)
2156 extract_constrain_insn (insn);
2157 continue;
2159 /* LRA code is based on assumption that all addresses can be
2160 correctly decomposed. LRA can generate reloads for
2161 decomposable addresses. The decomposition code checks the
2162 correctness of the addresses. So we don't need to check
2163 the addresses here. Don't call insn_invalid_p here, it can
2164 change the code at this stage. */
2165 if (recog_memoized (insn) < 0 && asm_noperands (PATTERN (insn)) < 0)
2166 fatal_insn_not_found (insn);
2170 /* Determine if the current function has an exception receiver block
2171 that reaches the exit block via non-exceptional edges */
2172 static bool
2173 has_nonexceptional_receiver (void)
2175 edge e;
2176 edge_iterator ei;
2177 basic_block *tos, *worklist, bb;
2179 /* If we're not optimizing, then just err on the safe side. */
2180 if (!optimize)
2181 return true;
2183 /* First determine which blocks can reach exit via normal paths. */
2184 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
2186 FOR_EACH_BB_FN (bb, cfun)
2187 bb->flags &= ~BB_REACHABLE;
2189 /* Place the exit block on our worklist. */
2190 EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
2191 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
2193 /* Iterate: find everything reachable from what we've already seen. */
2194 while (tos != worklist)
2196 bb = *--tos;
2198 FOR_EACH_EDGE (e, ei, bb->preds)
2199 if (e->flags & EDGE_ABNORMAL)
2201 free (worklist);
2202 return true;
2204 else
2206 basic_block src = e->src;
2208 if (!(src->flags & BB_REACHABLE))
2210 src->flags |= BB_REACHABLE;
2211 *tos++ = src;
2215 free (worklist);
2216 /* No exceptional block reached exit unexceptionally. */
2217 return false;
2221 /* Process recursively X of INSN and add REG_INC notes if necessary. */
2222 static void
2223 add_auto_inc_notes (rtx_insn *insn, rtx x)
2225 enum rtx_code code = GET_CODE (x);
2226 const char *fmt;
2227 int i, j;
2229 if (code == MEM && auto_inc_p (XEXP (x, 0)))
2231 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
2232 return;
2235 /* Scan all X sub-expressions. */
2236 fmt = GET_RTX_FORMAT (code);
2237 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2239 if (fmt[i] == 'e')
2240 add_auto_inc_notes (insn, XEXP (x, i));
2241 else if (fmt[i] == 'E')
2242 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2243 add_auto_inc_notes (insn, XVECEXP (x, i, j));
2248 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2249 We change pseudos by hard registers without notification of DF and
2250 that can make the notes obsolete. DF-infrastructure does not deal
2251 with REG_INC notes -- so we should regenerate them here. */
2252 static void
2253 update_inc_notes (void)
2255 rtx *pnote;
2256 basic_block bb;
2257 rtx_insn *insn;
2259 FOR_EACH_BB_FN (bb, cfun)
2260 FOR_BB_INSNS (bb, insn)
2261 if (NONDEBUG_INSN_P (insn))
2263 pnote = &REG_NOTES (insn);
2264 while (*pnote != 0)
2266 if (REG_NOTE_KIND (*pnote) == REG_DEAD
2267 || REG_NOTE_KIND (*pnote) == REG_UNUSED
2268 || REG_NOTE_KIND (*pnote) == REG_INC)
2269 *pnote = XEXP (*pnote, 1);
2270 else
2271 pnote = &XEXP (*pnote, 1);
2274 if (AUTO_INC_DEC)
2275 add_auto_inc_notes (insn, PATTERN (insn));
2279 /* Set to 1 while in lra. */
2280 int lra_in_progress;
2282 /* Start of pseudo regnos before the LRA. */
2283 int lra_new_regno_start;
2285 /* Start of reload pseudo regnos before the new spill pass. */
2286 int lra_constraint_new_regno_start;
2288 /* Avoid spilling pseudos with regno more than the following value if
2289 it is possible. */
2290 int lra_bad_spill_regno_start;
2292 /* Inheritance pseudo regnos before the new spill pass. */
2293 bitmap_head lra_inheritance_pseudos;
2295 /* Split regnos before the new spill pass. */
2296 bitmap_head lra_split_regs;
2298 /* Reload pseudo regnos before the new assignment pass which still can
2299 be spilled after the assignment pass as memory is also accepted in
2300 insns for the reload pseudos. */
2301 bitmap_head lra_optional_reload_pseudos;
2303 /* Pseudo regnos used for subreg reloads before the new assignment
2304 pass. Such pseudos still can be spilled after the assignment
2305 pass. */
2306 bitmap_head lra_subreg_reload_pseudos;
2308 /* File used for output of LRA debug information. */
2309 FILE *lra_dump_file;
2311 /* True if we should try spill into registers of different classes
2312 instead of memory. */
2313 bool lra_reg_spill_p;
2315 /* Set up value LRA_REG_SPILL_P. */
2316 static void
2317 setup_reg_spill_flag (void)
2319 int cl, mode;
2321 if (targetm.spill_class != NULL)
2322 for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++)
2323 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
2324 if (targetm.spill_class ((enum reg_class) cl,
2325 (machine_mode) mode) != NO_REGS)
2327 lra_reg_spill_p = true;
2328 return;
2330 lra_reg_spill_p = false;
2333 /* True if the current function is too big to use regular algorithms
2334 in LRA. In other words, we should use simpler and faster algorithms
2335 in LRA. It also means we should not worry about generation code
2336 for caller saves. The value is set up in IRA. */
2337 bool lra_simple_p;
2339 /* Major LRA entry function. F is a file should be used to dump LRA
2340 debug info. */
2341 void
2342 lra (FILE *f)
2344 int i;
2345 bool live_p, inserted_p;
2347 lra_dump_file = f;
2349 timevar_push (TV_LRA);
2351 /* Make sure that the last insn is a note. Some subsequent passes
2352 need it. */
2353 emit_note (NOTE_INSN_DELETED);
2355 COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs);
2357 init_reg_info ();
2358 expand_reg_info ();
2360 init_insn_recog_data ();
2362 /* Some quick check on RTL generated by previous passes. */
2363 if (flag_checking)
2364 check_rtl (false);
2366 lra_in_progress = 1;
2368 lra_live_range_iter = lra_coalesce_iter = lra_constraint_iter = 0;
2369 lra_assignment_iter = lra_assignment_iter_after_spill = 0;
2370 lra_inheritance_iter = lra_undo_inheritance_iter = 0;
2371 lra_rematerialization_iter = 0;
2373 setup_reg_spill_flag ();
2375 /* Function remove_scratches can creates new pseudos for clobbers --
2376 so set up lra_constraint_new_regno_start before its call to
2377 permit changing reg classes for pseudos created by this
2378 simplification. */
2379 lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num ();
2380 lra_bad_spill_regno_start = INT_MAX;
2381 remove_scratches ();
2383 /* A function that has a non-local label that can reach the exit
2384 block via non-exceptional paths must save all call-saved
2385 registers. */
2386 if (cfun->has_nonlocal_label && has_nonexceptional_receiver ())
2387 crtl->saves_all_registers = 1;
2389 if (crtl->saves_all_registers)
2390 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2391 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
2392 df_set_regs_ever_live (i, true);
2394 /* We don't DF from now and avoid its using because it is to
2395 expensive when a lot of RTL changes are made. */
2396 df_set_flags (DF_NO_INSN_RESCAN);
2397 lra_constraint_insn_stack.create (get_max_uid ());
2398 lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ());
2399 bitmap_clear (lra_constraint_insn_stack_bitmap);
2400 lra_live_ranges_init ();
2401 lra_constraints_init ();
2402 lra_curr_reload_num = 0;
2403 push_insns (get_last_insn (), NULL);
2404 /* It is needed for the 1st coalescing. */
2405 bitmap_initialize (&lra_inheritance_pseudos, &reg_obstack);
2406 bitmap_initialize (&lra_split_regs, &reg_obstack);
2407 bitmap_initialize (&lra_optional_reload_pseudos, &reg_obstack);
2408 bitmap_initialize (&lra_subreg_reload_pseudos, &reg_obstack);
2409 live_p = false;
2410 if (maybe_ne (get_frame_size (), 0) && crtl->stack_alignment_needed)
2411 /* If we have a stack frame, we must align it now. The stack size
2412 may be a part of the offset computation for register
2413 elimination. */
2414 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
2415 lra_init_equiv ();
2416 for (;;)
2418 for (;;)
2420 bool reloads_p = lra_constraints (lra_constraint_iter == 0);
2421 /* Constraint transformations may result in that eliminable
2422 hard regs become uneliminable and pseudos which use them
2423 should be spilled. It is better to do it before pseudo
2424 assignments.
2426 For example, rs6000 can make
2427 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2428 to use a constant pool. */
2429 lra_eliminate (false, false);
2430 /* We should try to assign hard registers to scratches even
2431 if there were no RTL transformations in lra_constraints.
2432 Also we should check IRA assignments on the first
2433 iteration as they can be wrong because of early clobbers
2434 operands which are ignored in IRA. */
2435 if (! reloads_p && lra_constraint_iter > 1)
2437 /* Stack is not empty here only when there are changes
2438 during the elimination sub-pass. */
2439 if (bitmap_empty_p (lra_constraint_insn_stack_bitmap))
2440 break;
2441 else
2442 /* If there are no reloads but changing due
2443 elimination, restart the constraint sub-pass
2444 first. */
2445 continue;
2447 /* Do inheritance only for regular algorithms. */
2448 if (! lra_simple_p)
2450 if (flag_ipa_ra)
2452 if (live_p)
2453 lra_clear_live_ranges ();
2454 /* As a side-effect of lra_create_live_ranges, we calculate
2455 actual_call_used_reg_set, which is needed during
2456 lra_inheritance. */
2457 lra_create_live_ranges (true, true);
2458 live_p = true;
2460 lra_inheritance ();
2462 if (live_p)
2463 lra_clear_live_ranges ();
2464 bool fails_p;
2467 /* We need live ranges for lra_assign -- so build them.
2468 But don't remove dead insns or change global live
2469 info as we can undo inheritance transformations after
2470 inheritance pseudo assigning. */
2471 lra_create_live_ranges (true, false);
2472 live_p = true;
2473 /* If we don't spill non-reload and non-inheritance
2474 pseudos, there is no sense to run memory-memory move
2475 coalescing. If inheritance pseudos were spilled, the
2476 memory-memory moves involving them will be removed by
2477 pass undoing inheritance. */
2478 if (lra_simple_p)
2479 lra_assign (fails_p);
2480 else
2482 bool spill_p = !lra_assign (fails_p);
2484 if (lra_undo_inheritance ())
2485 live_p = false;
2486 if (spill_p && ! fails_p)
2488 if (! live_p)
2490 lra_create_live_ranges (true, true);
2491 live_p = true;
2493 if (lra_coalesce ())
2494 live_p = false;
2496 if (! live_p)
2497 lra_clear_live_ranges ();
2499 if (fails_p)
2501 /* It is a very rare case. It is the last hope to
2502 split a hard regno live range for a reload
2503 pseudo. */
2504 if (live_p)
2505 lra_clear_live_ranges ();
2506 live_p = false;
2507 if (! lra_split_hard_reg_for ())
2508 break;
2511 while (fails_p);
2513 /* Don't clear optional reloads bitmap until all constraints are
2514 satisfied as we need to differ them from regular reloads. */
2515 bitmap_clear (&lra_optional_reload_pseudos);
2516 bitmap_clear (&lra_subreg_reload_pseudos);
2517 bitmap_clear (&lra_inheritance_pseudos);
2518 bitmap_clear (&lra_split_regs);
2519 if (! live_p)
2521 /* We need full live info for spilling pseudos into
2522 registers instead of memory. */
2523 lra_create_live_ranges (lra_reg_spill_p, true);
2524 live_p = true;
2526 /* We should check necessity for spilling here as the above live
2527 range pass can remove spilled pseudos. */
2528 if (! lra_need_for_spills_p ())
2529 break;
2530 /* Now we know what pseudos should be spilled. Try to
2531 rematerialize them first. */
2532 if (lra_remat ())
2534 /* We need full live info -- see the comment above. */
2535 lra_create_live_ranges (lra_reg_spill_p, true);
2536 live_p = true;
2537 if (! lra_need_for_spills_p ())
2538 break;
2540 lra_spill ();
2541 /* Assignment of stack slots changes elimination offsets for
2542 some eliminations. So update the offsets here. */
2543 lra_eliminate (false, false);
2544 lra_constraint_new_regno_start = max_reg_num ();
2545 if (lra_bad_spill_regno_start == INT_MAX
2546 && lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES
2547 && lra_rematerialization_iter > LRA_MAX_REMATERIALIZATION_PASSES)
2548 /* After switching off inheritance and rematerialization
2549 passes, avoid spilling reload pseudos will be created to
2550 prevent LRA cycling in some complicated cases. */
2551 lra_bad_spill_regno_start = lra_constraint_new_regno_start;
2552 lra_assignment_iter_after_spill = 0;
2554 restore_scratches ();
2555 lra_eliminate (true, false);
2556 lra_final_code_change ();
2557 lra_in_progress = 0;
2558 if (live_p)
2559 lra_clear_live_ranges ();
2560 lra_live_ranges_finish ();
2561 lra_constraints_finish ();
2562 finish_reg_info ();
2563 sbitmap_free (lra_constraint_insn_stack_bitmap);
2564 lra_constraint_insn_stack.release ();
2565 finish_insn_recog_data ();
2566 regstat_free_n_sets_and_refs ();
2567 regstat_free_ri ();
2568 reload_completed = 1;
2569 update_inc_notes ();
2571 inserted_p = fixup_abnormal_edges ();
2573 /* We've possibly turned single trapping insn into multiple ones. */
2574 if (cfun->can_throw_non_call_exceptions)
2576 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
2577 bitmap_ones (blocks);
2578 find_many_sub_basic_blocks (blocks);
2581 if (inserted_p)
2582 commit_edge_insertions ();
2584 /* Replacing pseudos with their memory equivalents might have
2585 created shared rtx. Subsequent passes would get confused
2586 by this, so unshare everything here. */
2587 unshare_all_rtl_again (get_insns ());
2589 if (flag_checking)
2590 check_rtl (true);
2592 timevar_pop (TV_LRA);
2595 /* Called once per compiler to initialize LRA data once. */
2596 void
2597 lra_init_once (void)
2599 init_insn_code_data_once ();
2602 /* Called once per compiler to finish LRA data which are initialize
2603 once. */
2604 void
2605 lra_finish_once (void)
2607 finish_insn_code_data_once ();