libjava/sysdep/sparc/locks.h

   1 // locks.h - Thread synchronization primitives. Sparc implementation.
   2
   3 /* Copyright (C) 2002, 2007  Free Software Foundation
   4
   5    This file is part of libgcj.
   6
   7 This software is copyrighted work licensed under the terms of the
   8 Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
   9 details.  */
  10
  11 #ifndef __SYSDEP_LOCKS_H__
  12 #define __SYSDEP_LOCKS_H__
  13
  14 typedef size_t obj_addr_t;      /* Integer type big enough for object   */
  15                                 /* address.                             */
  16
  17 #ifdef __arch64__
  18 /* Sparc64 implementation, use cas instruction.  */
  19 inline static bool
  20 compare_and_swap(volatile obj_addr_t *addr,
  21                  obj_addr_t old,
  22                  obj_addr_t new_val)
  23 {
  24   __asm__ __volatile__("casx [%2], %3, %0\n\t"
  25                        "membar #StoreLoad | #StoreStore"
  26                        : "=&r" (new_val)
  27                        : "0" (new_val), "r" (addr), "r" (old)
  28                        : "memory");
  29
  30   return (new_val == old) ? true : false;
  31 }
  32
  33 inline static void
  34 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
  35 {
  36   __asm__ __volatile__("membar #StoreStore | #LoadStore" : : : "memory");
  37   *(addr) = new_val;
  38 }
  39
  40 inline static bool
  41 compare_and_swap_release(volatile obj_addr_t *addr, obj_addr_t old,
  42                          obj_addr_t new_val)
  43 {
  44   return compare_and_swap(addr, old, new_val);
  45 }
  46
  47 inline static void
  48 read_barrier()
  49 {
  50   __asm__ __volatile__("membar #LoadLoad | #LoadStore" : : : "memory");
  51 }
  52
  53 inline static void
  54 write_barrier()
  55 {
  56   __asm__ __volatile__("membar #StoreLoad | #StoreStore" : : : "memory");
  57 }
  58 #else
  59 /* Sparc32 implementation, use a spinlock.  */
  60 static unsigned char __cas_lock = 0;
  61
  62 inline static void
  63 __cas_start_atomic(void)
  64 {
  65   unsigned int tmp;
  66   __asm__ __volatile__(
  67 "1:     ldstub  [%1], %0\n"
  68 "       orcc    %0, 0x0, %%g0\n"
  69 "       be      3f\n"
  70 "        nop\n"
  71 "2:     ldub    [%1], %0\n"
  72 "       orcc    %0, 0x0, %%g0\n"
  73 "       bne     2b\n"
  74 "        nop\n"
  75 "3:"    : "=&r" (tmp)
  76         : "r" (&__cas_lock)
  77         : "memory", "cc");
  78 }
  79
  80 inline static void
  81 __cas_end_atomic(void)
  82 {
  83   __asm__ __volatile__(
  84   "stb %%g0, [%0]"
  85   : /* no outputs */
  86   : "r" (&__cas_lock)
  87   : "memory");
  88 }
  89
  90 inline static bool
  91 compare_and_swap(volatile obj_addr_t *addr,
  92                  obj_addr_t old,
  93                  obj_addr_t new_val)
  94 {
  95   bool ret;
  96
  97   __cas_start_atomic ();
  98   if (*addr != old)
  99     {
 100       ret = false;
 101     }
 102   else
 103     {
 104       *addr = new_val;
 105       ret = true;
 106     }
 107   __cas_end_atomic ();
 108
 109   return ret;
 110 }
 111
 112 inline static void
 113 release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
 114 {
 115   /* Technically stbar would be needed here but no sparc32
 116      system actually requires it.  Also the stbar would mean
 117      this code would not work on sparcv7 chips.  */
 118   __asm__ __volatile__("" : : : "memory");
 119   *(addr) = new_val;
 120 }
 121
 122 inline static bool
 123 compare_and_swap_release(volatile obj_addr_t *addr, obj_addr_t old,
 124                          obj_addr_t new_val)
 125 {
 126   return compare_and_swap(addr, old, new_val);
 127 }
 128
 129 inline static void
 130 read_barrier()
 131 {
 132   __asm__ __volatile__ ("" : : : "memory");
 133 }
 134
 135 inline static void
 136 write_barrier()
 137 {
 138   __asm__ __volatile__ ("" : : : "memory");
 139 }
 140 #endif /* __arch64__ */
 141
 142 #endif /* ! __SYSDEP_LOCKS_H__ */