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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
68 #ifndef CHECK_STACK_LIMIT
69 #define CHECK_STACK_LIMIT (-1)
70 #endif
72 /* Return index of given mode in mult and division cost tables. */
73 #define MODE_INDEX(mode) \
74 ((mode) == QImode ? 0 \
75 : (mode) == HImode ? 1 \
76 : (mode) == SImode ? 2 \
77 : (mode) == DImode ? 3 \
78 : 4)
80 /* Processor costs (relative to an add) */
81 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
82 #define COSTS_N_BYTES(N) ((N) * 2)
84 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
86 const
109 in QImode, HImode and SImode.
110 Relative to reg-reg move (2). */
114 in SFmode, DFmode and XFmode */
116 in SFmode, DFmode and XFmode */
119 in SImode and DImode */
121 in SImode and DImode */
124 in SImode, DImode and TImode */
126 in SImode, DImode and TImode */
154 };
156 /* Processor costs (relative to an add) */
157 static const
180 in QImode, HImode and SImode.
181 Relative to reg-reg move (2). */
185 in SFmode, DFmode and XFmode */
187 in SFmode, DFmode and XFmode */
190 in SImode and DImode */
192 in SImode and DImode */
195 in SImode, DImode and TImode */
197 in SImode, DImode and TImode */
211 DUMMY_STRINGOP_ALGS},
213 DUMMY_STRINGOP_ALGS},
225 };
227 static const
250 in QImode, HImode and SImode.
251 Relative to reg-reg move (2). */
255 in SFmode, DFmode and XFmode */
257 in SFmode, DFmode and XFmode */
260 in SImode and DImode */
262 in SImode and DImode */
265 in SImode, DImode and TImode */
267 in SImode, DImode and TImode */
270 shared for code and data, so 4kB is
271 not really precise. */
283 DUMMY_STRINGOP_ALGS},
285 DUMMY_STRINGOP_ALGS},
297 };
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
353 DUMMY_STRINGOP_ALGS},
355 DUMMY_STRINGOP_ALGS},
367 };
369 static const
392 in QImode, HImode and SImode.
393 Relative to reg-reg move (2). */
397 in SFmode, DFmode and XFmode */
399 in SFmode, DFmode and XFmode */
402 in SImode and DImode */
404 in SImode and DImode */
407 in SImode, DImode and TImode */
409 in SImode, DImode and TImode */
422 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
423 (we ensure the alignment). For small blocks inline loop is still a
424 noticeable win, for bigger blocks either rep movsl or rep movsb is
425 way to go. Rep movsb has apparently more expensive startup time in CPU,
426 but after 4K the difference is down in the noise. */
430 DUMMY_STRINGOP_ALGS},
434 DUMMY_STRINGOP_ALGS},
446 };
448 static const
471 in QImode, HImode and SImode.
472 Relative to reg-reg move (2). */
476 in SFmode, DFmode and XFmode */
478 in SFmode, DFmode and XFmode */
482 in SImode and DImode */
484 in SImode and DImode */
487 in SImode, DImode and TImode */
489 in SImode, DImode and TImode */
503 DUMMY_STRINGOP_ALGS},
505 DUMMY_STRINGOP_ALGS},
517 };
519 static const
542 in QImode, HImode and SImode.
543 Relative to reg-reg move (2). */
547 in SFmode, DFmode and XFmode */
549 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
563 have integrated l2 cache, but
564 optimizing for k6 is not important
565 enough to worry about that. */
576 DUMMY_STRINGOP_ALGS},
578 DUMMY_STRINGOP_ALGS},
590 };
592 static const
615 in QImode, HImode and SImode.
616 Relative to reg-reg move (2). */
620 in SFmode, DFmode and XFmode */
622 in SFmode, DFmode and XFmode */
625 in SImode and DImode */
627 in SImode and DImode */
630 in SImode, DImode and TImode */
632 in SImode, DImode and TImode */
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
649 DUMMY_STRINGOP_ALGS},
651 DUMMY_STRINGOP_ALGS},
663 };
665 static const
688 in QImode, HImode and SImode.
689 Relative to reg-reg move (2). */
693 in SFmode, DFmode and XFmode */
695 in SFmode, DFmode and XFmode */
698 in SImode and DImode */
700 in SImode and DImode */
703 in SImode, DImode and TImode */
705 in SImode, DImode and TImode */
710 /* New AMD processors never drop prefetches; if they cannot be performed
711 immediately, they are queued. We set number of simultaneous prefetches
712 to a large constant to reflect this (it probably is not a good idea not
713 to limit number of prefetches at all, as their execution also takes some
714 time). */
723 /* K8 has optimized REP instruction for medium sized blocks, but for very
724 small blocks it is better to use loop. For large blocks, libcall can
725 do nontemporary accesses and beat inline considerably. */
745 };
769 in QImode, HImode and SImode.
770 Relative to reg-reg move (2). */
774 in SFmode, DFmode and XFmode */
776 in SFmode, DFmode and XFmode */
779 in SImode and DImode */
781 in SImode and DImode */
784 in SImode, DImode and TImode */
786 in SImode, DImode and TImode */
788 /* On K8:
789 MOVD reg64, xmmreg Double FSTORE 4
790 MOVD reg32, xmmreg Double FSTORE 4
791 On AMDFAM10:
792 MOVD reg64, xmmreg Double FADD 3
793 1/1 1/1
794 MOVD reg32, xmmreg Double FADD 3
795 1/1 1/1 */
799 /* New AMD processors never drop prefetches; if they cannot be performed
800 immediately, they are queued. We set number of simultaneous prefetches
801 to a large constant to reflect this (it probably is not a good idea not
802 to limit number of prefetches at all, as their execution also takes some
803 time). */
813 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
814 very small blocks it is better to use loop. For large blocks, libcall can
815 do nontemporary accesses and beat inline considerably. */
835 };
859 in QImode, HImode and SImode.
860 Relative to reg-reg move (2). */
864 in SFmode, DFmode and XFmode */
866 in SFmode, DFmode and XFmode */
869 in SImode and DImode */
871 in SImode and DImode */
874 in SImode, DImode and TImode */
876 in SImode, DImode and TImode */
878 /* On K8:
879 MOVD reg64, xmmreg Double FSTORE 4
880 MOVD reg32, xmmreg Double FSTORE 4
881 On AMDFAM10:
882 MOVD reg64, xmmreg Double FADD 3
883 1/1 1/1
884 MOVD reg32, xmmreg Double FADD 3
885 1/1 1/1 */
889 /* New AMD processors never drop prefetches; if they cannot be performed
890 immediately, they are queued. We set number of simultaneous prefetches
891 to a large constant to reflect this (it probably is not a good idea not
892 to limit number of prefetches at all, as their execution also takes some
893 time). */
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
925 };
949 in QImode, HImode and SImode.
950 Relative to reg-reg move (2). */
954 in SFmode, DFmode and XFmode */
956 in SFmode, DFmode and XFmode */
959 in SImode and DImode */
961 in SImode and DImode */
964 in SImode, DImode and TImode */
966 in SImode, DImode and TImode */
968 /* On K8:
969 MOVD reg64, xmmreg Double FSTORE 4
970 MOVD reg32, xmmreg Double FSTORE 4
971 On AMDFAM10:
972 MOVD reg64, xmmreg Double FADD 3
973 1/1 1/1
974 MOVD reg32, xmmreg Double FADD 3
975 1/1 1/1 */
979 /* New AMD processors never drop prefetches; if they cannot be performed
980 immediately, they are queued. We set number of simultaneous prefetches
981 to a large constant to reflect this (it probably is not a good idea not
982 to limit number of prefetches at all, as their execution also takes some
983 time). */
993 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
994 very small blocks it is better to use loop. For large blocks, libcall
995 can do nontemporary accesses and beat inline considerably. */
1015 };
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1044 in SFmode, DFmode and XFmode */
1046 in SFmode, DFmode and XFmode */
1049 in SImode and DImode */
1051 in SImode and DImode */
1054 in SImode, DImode and TImode */
1056 in SImode, DImode and TImode */
1061 /* New AMD processors never drop prefetches; if they cannot be performed
1062 immediately, they are queued. We set number of simultaneous prefetches
1063 to a large constant to reflect this (it probably is not a good idea not
1064 to limit number of prefetches at all, as their execution also takes some
1065 time). */
1075 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1076 very small blocks it is better to use loop. For large blocks, libcall
1077 can do nontemporary accesses and beat inline considerably. */
1097 };
1121 in QImode, HImode and SImode.
1122 Relative to reg-reg move (2). */
1126 in SFmode, DFmode and XFmode */
1128 in SFmode, DFmode and XFmode */
1131 in SImode and DImode */
1133 in SImode and DImode */
1136 in SImode, DImode and TImode */
1138 in SImode, DImode and TImode */
1140 /* On K8:
1141 MOVD reg64, xmmreg Double FSTORE 4
1142 MOVD reg32, xmmreg Double FSTORE 4
1143 On AMDFAM10:
1144 MOVD reg64, xmmreg Double FADD 3
1145 1/1 1/1
1146 MOVD reg32, xmmreg Double FADD 3
1147 1/1 1/1 */
1160 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1161 very small blocks it is better to use loop. For large blocks, libcall can
1162 do nontemporary accesses and beat inline considerably. */
1182 };
1206 in QImode, HImode and SImode.
1207 Relative to reg-reg move (2). */
1211 in SFmode, DFmode and XFmode */
1213 in SFmode, DFmode and XFmode */
1216 in SImode and DImode */
1218 in SImode and DImode */
1221 in SImode, DImode and TImode */
1223 in SImode, DImode and TImode */
1225 /* On K8:
1226 MOVD reg64, xmmreg Double FSTORE 4
1227 MOVD reg32, xmmreg Double FSTORE 4
1228 On AMDFAM10:
1229 MOVD reg64, xmmreg Double FADD 3
1230 1/1 1/1
1231 MOVD reg32, xmmreg Double FADD 3
1232 1/1 1/1 */
1264 };
1266 static const
1289 in QImode, HImode and SImode.
1290 Relative to reg-reg move (2). */
1294 in SFmode, DFmode and XFmode */
1296 in SFmode, DFmode and XFmode */
1299 in SImode and DImode */
1301 in SImode and DImode */
1304 in SImode, DImode and TImode */
1306 in SImode, DImode and TImode */
1320 DUMMY_STRINGOP_ALGS},
1323 DUMMY_STRINGOP_ALGS},
1335 };
1337 static const
1360 in QImode, HImode and SImode.
1361 Relative to reg-reg move (2). */
1365 in SFmode, DFmode and XFmode */
1367 in SFmode, DFmode and XFmode */
1370 in SImode and DImode */
1372 in SImode and DImode */
1375 in SImode, DImode and TImode */
1377 in SImode, DImode and TImode */
1408 };
1410 static const
1433 in QImode, HImode and SImode.
1434 Relative to reg-reg move (2). */
1438 in SFmode, DFmode and XFmode */
1440 in SFmode, DFmode and XFmode */
1443 in SImode and DImode */
1445 in SImode and DImode */
1448 in SImode, DImode and TImode */
1450 in SImode, DImode and TImode */
1481 };
1483 /* Generic64 should produce code tuned for Nocona and K8. */
1484 static const
1487 /* On all chips taken into consideration lea is 2 cycles and more. With
1488 this cost however our current implementation of synth_mult results in
1489 use of unnecessary temporary registers causing regression on several
1490 SPECfp benchmarks. */
1511 in QImode, HImode and SImode.
1512 Relative to reg-reg move (2). */
1516 in SFmode, DFmode and XFmode */
1518 in SFmode, DFmode and XFmode */
1521 in SImode and DImode */
1523 in SImode and DImode */
1526 in SImode, DImode and TImode */
1528 in SImode, DImode and TImode */
1534 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1535 value is increased to perhaps more appropriate value of 5. */
1560 };
1562 /* core_cost should produce code tuned for Core familly of CPUs. */
1563 static const
1566 /* On all chips taken into consideration lea is 2 cycles and more. With
1567 this cost however our current implementation of synth_mult results in
1568 use of unnecessary temporary registers causing regression on several
1569 SPECfp benchmarks. */
1590 in QImode, HImode and SImode.
1591 Relative to reg-reg move (2). */
1595 in SFmode, DFmode and XFmode */
1597 in SFmode, DFmode and XFmode */
1600 in SImode and DImode */
1602 in SImode and DImode */
1605 in SImode, DImode and TImode */
1607 in SImode, DImode and TImode */
1613 /* FIXME perhaps more appropriate value is 5. */
1641 };
1643 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1644 Athlon and K8. */
1645 static const
1668 in QImode, HImode and SImode.
1669 Relative to reg-reg move (2). */
1673 in SFmode, DFmode and XFmode */
1675 in SFmode, DFmode and XFmode */
1678 in SImode and DImode */
1680 in SImode and DImode */
1683 in SImode, DImode and TImode */
1685 in SImode, DImode and TImode */
1700 DUMMY_STRINGOP_ALGS},
1703 DUMMY_STRINGOP_ALGS},
1715 };
1717 /* Set by -mtune. */
1720 /* Set by -mtune or -Os. */
1723 /* Processor feature/optimization bitmasks. */
1724 #define m_386 (1<<PROCESSOR_I386)
1725 #define m_486 (1<<PROCESSOR_I486)
1726 #define m_PENT (1<<PROCESSOR_PENTIUM)
1727 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1728 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1729 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1730 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1731 #define m_CORE2 (1<<PROCESSOR_CORE2)
1732 #define m_COREI7 (1<<PROCESSOR_COREI7)
1733 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1734 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1735 #define m_ATOM (1<<PROCESSOR_ATOM)
1737 #define m_GEODE (1<<PROCESSOR_GEODE)
1738 #define m_K6 (1<<PROCESSOR_K6)
1739 #define m_K6_GEODE (m_K6 | m_GEODE)
1740 #define m_K8 (1<<PROCESSOR_K8)
1741 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1742 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1743 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1744 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1745 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1746 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1747 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1748 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1749 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1750 #define m_BTVER (m_BTVER1 | m_BTVER2)
1751 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1753 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1754 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1756 /* Generic instruction choice should be common subset of supported CPUs
1757 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1758 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1760 /* Feature tests against the various tunings. */
1763 /* Feature tests against the various tunings used to create ix86_tune_features
1764 based on the processor mask. */
1766 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1767 negatively, so enabling for Generic64 seems like good code size
1768 tradeoff. We can't enable it for 32bit generic because it does not
1769 work well with PPro base chips. */
1772 /* X86_TUNE_PUSH_MEMORY */
1775 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1778 /* X86_TUNE_UNROLL_STRLEN */
1781 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1782 on simulation result. But after P4 was made, no performance benefit
1783 was observed with branch hints. It also increases the code size.
1784 As a result, icc never generates branch hints. */
1787 /* X86_TUNE_DOUBLE_WITH_ADD */
1790 /* X86_TUNE_USE_SAHF */
1791 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1793 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1794 partial dependencies. */
1797 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1798 register stalls on Generic32 compilation setting as well. However
1799 in current implementation the partial register stalls are not eliminated
1800 very well - they can be introduced via subregs synthesized by combine
1801 and can happen in caller/callee saving sequences. Because this option
1802 pays back little on PPro based chips and is in conflict with partial reg
1803 dependencies used by Athlon/P4 based chips, it is better to leave it off
1804 for generic32 for now. */
1805 m_PPRO,
1807 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1810 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1811 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1814 /* X86_TUNE_USE_HIMODE_FIOP */
1817 /* X86_TUNE_USE_SIMODE_FIOP */
1820 /* X86_TUNE_USE_MOV0 */
1821 m_K6,
1823 /* X86_TUNE_USE_CLTD */
1826 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1827 m_PENT4,
1829 /* X86_TUNE_SPLIT_LONG_MOVES */
1830 m_PPRO,
1832 /* X86_TUNE_READ_MODIFY_WRITE */
1835 /* X86_TUNE_READ_MODIFY */
1838 /* X86_TUNE_PROMOTE_QIMODE */
1841 /* X86_TUNE_FAST_PREFIX */
1844 /* X86_TUNE_SINGLE_STRINGOP */
1847 /* X86_TUNE_QIMODE_MATH */
1850 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1851 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1852 might be considered for Generic32 if our scheme for avoiding partial
1853 stalls was more effective. */
1856 /* X86_TUNE_PROMOTE_QI_REGS */
1859 /* X86_TUNE_PROMOTE_HI_REGS */
1860 m_PPRO,
1862 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1863 over esp addition. */
1866 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1867 over esp addition. */
1868 m_PENT,
1870 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1871 over esp subtraction. */
1874 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1875 over esp subtraction. */
1878 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1879 for DFmode copies */
1882 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1885 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1886 conflict here in between PPro/Pentium4 based chips that thread 128bit
1887 SSE registers as single units versus K8 based chips that divide SSE
1888 registers to two 64bit halves. This knob promotes all store destinations
1889 to be 128bit to allow register renaming on 128bit SSE units, but usually
1890 results in one extra microop on 64bit SSE units. Experimental results
1891 shows that disabling this option on P4 brings over 20% SPECfp regression,
1892 while enabling it on K8 brings roughly 2.4% regression that can be partly
1893 masked by careful scheduling of moves. */
1896 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1899 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1902 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1903 m_BDVER ,
1905 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1906 are resolved on SSE register parts instead of whole registers, so we may
1907 maintain just lower part of scalar values in proper format leaving the
1908 upper part undefined. */
1909 m_ATHLON_K8,
1911 /* X86_TUNE_SSE_TYPELESS_STORES */
1912 m_AMD_MULTIPLE,
1914 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1917 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1920 /* X86_TUNE_PROLOGUE_USING_MOVE */
1923 /* X86_TUNE_EPILOGUE_USING_MOVE */
1926 /* X86_TUNE_SHIFT1 */
1929 /* X86_TUNE_USE_FFREEP */
1930 m_AMD_MULTIPLE,
1932 /* X86_TUNE_INTER_UNIT_MOVES */
1935 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1938 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1939 than 4 branch instructions in the 16 byte window. */
1942 /* X86_TUNE_SCHEDULE */
1945 /* X86_TUNE_USE_BT */
1948 /* X86_TUNE_USE_INCDEC */
1951 /* X86_TUNE_PAD_RETURNS */
1954 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1955 m_ATOM,
1957 /* X86_TUNE_EXT_80387_CONSTANTS */
1960 /* X86_TUNE_AVOID_VECTOR_DECODE */
1963 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1964 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1967 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1968 vector path on AMD machines. */
1971 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1972 machines. */
1975 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1976 than a MOV. */
1977 m_PENT,
1979 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1980 but one byte longer. */
1981 m_PENT,
1983 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1984 operand that cannot be represented using a modRM byte. The XOR
1985 replacement is long decoded, so this split helps here as well. */
1986 m_K6,
1988 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1989 from FP to FP. */
1992 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1993 from integer to FP. */
1994 m_AMDFAM10,
1996 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1997 with a subsequent conditional jump instruction into a single
1998 compare-and-branch uop. */
1999 m_BDVER,
2001 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2002 will impact LEA instruction selection. */
2003 m_ATOM,
2005 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2006 instructions. */
2009 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2010 at -O3. For the moment, the prefetching seems badly tuned for Intel
2011 chips. */
2014 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2015 the auto-vectorizer. */
2018 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2019 during reassociation of integer computation. */
2020 m_ATOM,
2022 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2023 during reassociation of fp computation. */
2026 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
2027 regs instead of memory. */
2028 m_CORE_ALL,
2030 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
2031 a conditional move. */
2032 m_ATOM
2033 };
2035 /* Feature tests against the various architecture variations. */
2038 /* Feature tests against the various architecture variations, used to create
2039 ix86_arch_features based on the processor mask. */
2041 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2044 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2047 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2050 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2053 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2055 };
2057 static const unsigned int x86_accumulate_outgoing_args
2060 static const unsigned int x86_arch_always_fancy_math_387
2063 static const unsigned int x86_avx256_split_unaligned_load
2066 static const unsigned int x86_avx256_split_unaligned_store
2069 /* In case the average insn count for single function invocation is
2070 lower than this constant, emit fast (but longer) prologue and
2071 epilogue code. */
2072 #define FAST_PROLOGUE_INSN_COUNT 20
2074 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2079 /* Array of the smallest class containing reg number REGNO, indexed by
2080 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2083 {
2084 /* ax, dx, cx, bx */
2086 /* si, di, bp, sp */
2088 /* FP registers */
2091 /* arg pointer */
2092 NON_Q_REGS,
2093 /* flags, fpsr, fpcr, frame */
2095 /* SSE registers */
2098 /* MMX registers */
2101 /* REX registers */
2104 /* SSE REX registers */
2107 };
2109 /* The "default" register map used in 32bit mode. */
2112 {
2120 };
2122 /* The "default" register map used in 64bit mode. */
2125 {
2133 };
2135 /* Define the register numbers to be used in Dwarf debugging information.
2136 The SVR4 reference port C compiler uses the following register numbers
2137 in its Dwarf output code:
2138 0 for %eax (gcc regno = 0)
2139 1 for %ecx (gcc regno = 2)
2140 2 for %edx (gcc regno = 1)
2141 3 for %ebx (gcc regno = 3)
2142 4 for %esp (gcc regno = 7)
2143 5 for %ebp (gcc regno = 6)
2144 6 for %esi (gcc regno = 4)
2145 7 for %edi (gcc regno = 5)
2146 The following three DWARF register numbers are never generated by
2147 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2148 believes these numbers have these meanings.
2149 8 for %eip (no gcc equivalent)
2150 9 for %eflags (gcc regno = 17)
2151 10 for %trapno (no gcc equivalent)
2152 It is not at all clear how we should number the FP stack registers
2153 for the x86 architecture. If the version of SDB on x86/svr4 were
2154 a bit less brain dead with respect to floating-point then we would
2155 have a precedent to follow with respect to DWARF register numbers
2156 for x86 FP registers, but the SDB on x86/svr4 is so completely
2157 broken with respect to FP registers that it is hardly worth thinking
2158 of it as something to strive for compatibility with.
2159 The version of x86/svr4 SDB I have at the moment does (partially)
2160 seem to believe that DWARF register number 11 is associated with
2161 the x86 register %st(0), but that's about all. Higher DWARF
2162 register numbers don't seem to be associated with anything in
2163 particular, and even for DWARF regno 11, SDB only seems to under-
2164 stand that it should say that a variable lives in %st(0) (when
2165 asked via an `=' command) if we said it was in DWARF regno 11,
2166 but SDB still prints garbage when asked for the value of the
2167 variable in question (via a `/' command).
2168 (Also note that the labels SDB prints for various FP stack regs
2169 when doing an `x' command are all wrong.)
2170 Note that these problems generally don't affect the native SVR4
2171 C compiler because it doesn't allow the use of -O with -g and
2172 because when it is *not* optimizing, it allocates a memory
2173 location for each floating-point variable, and the memory
2174 location is what gets described in the DWARF AT_location
2175 attribute for the variable in question.
2176 Regardless of the severe mental illness of the x86/svr4 SDB, we
2177 do something sensible here and we use the following DWARF
2178 register numbers. Note that these are all stack-top-relative
2179 numbers.
2180 11 for %st(0) (gcc regno = 8)
2181 12 for %st(1) (gcc regno = 9)
2182 13 for %st(2) (gcc regno = 10)
2183 14 for %st(3) (gcc regno = 11)
2184 15 for %st(4) (gcc regno = 12)
2185 16 for %st(5) (gcc regno = 13)
2186 17 for %st(6) (gcc regno = 14)
2187 18 for %st(7) (gcc regno = 15)
2188 */
2190 {
2198 };
2200 /* Define parameter passing and return registers. */
2203 {
2205 };
2208 {
2210 };
2213 {
2215 };
2217 /* Define the structure for the machine field in struct function. */
2222 rtx rtl;
2224 };
2226 /* Structure describing stack frame layout.
2227 Stack grows downward:
2229 [arguments]
2230 <- ARG_POINTER
2231 saved pc
2233 saved static chain if ix86_static_chain_on_stack
2235 saved frame pointer if frame_pointer_needed
2236 <- HARD_FRAME_POINTER
2237 [saved regs]
2238 <- regs_save_offset
2239 [padding0]
2241 [saved SSE regs]
2242 <- sse_regs_save_offset
2243 [padding1] |
2244 | <- FRAME_POINTER
2245 [va_arg registers] |
2246 |
2247 [frame] |
2248 |
2249 [padding2] | = to_allocate
2250 <- STACK_POINTER
2251 */
2252 struct ix86_frame
2253 {
2260 /* The offsets relative to ARG_POINTER. */
2261 HOST_WIDE_INT frame_pointer_offset;
2262 HOST_WIDE_INT hard_frame_pointer_offset;
2263 HOST_WIDE_INT stack_pointer_offset;
2264 HOST_WIDE_INT hfp_save_offset;
2265 HOST_WIDE_INT reg_save_offset;
2266 HOST_WIDE_INT sse_reg_save_offset;
2268 /* When save_regs_using_mov is set, emit prologue using
2269 move instead of push instructions. */
2271 };
2273 /* Which cpu are we scheduling for. */
2276 /* Which cpu are we optimizing for. */
2279 /* Which instruction set architecture to use. */
2282 /* True if processor has SSE prefetch instruction. */
2285 /* -mstackrealign option */
2302 /* Preferred alignment for stack boundary in bits. */
2305 /* Alignment for incoming stack boundary in bits specified at
2306 command line. */
2309 /* Default alignment for incoming stack boundary in bits. */
2312 /* Alignment for incoming stack boundary in bits. */
2315 /* Calling abi specific va_list type nodes. */
2319 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2323 /* Fence to use after loop using movnt. */
2324 tree x86_mfence;
2326 /* Register class used for passing given 64bit part of the argument.
2327 These represent classes as documented by the PS ABI, with the exception
2328 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2329 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2331 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2332 whenever possible (upper half does contain padding). */
2333 enum x86_64_reg_class
2334 {
2335 X86_64_NO_CLASS,
2336 X86_64_INTEGER_CLASS,
2337 X86_64_INTEGERSI_CLASS,
2338 X86_64_SSE_CLASS,
2339 X86_64_SSESF_CLASS,
2340 X86_64_SSEDF_CLASS,
2341 X86_64_SSEUP_CLASS,
2342 X86_64_X87_CLASS,
2343 X86_64_X87UP_CLASS,
2344 X86_64_COMPLEX_X87_CLASS,
2345 X86_64_MEMORY_CLASS
2346 };
2348 #define MAX_CLASSES 4
2350 /* Table of constants used by fldpi, fldln2, etc.... */
2354 \f
2359 const_tree);
2371 enum ix86_function_specific_strings
2372 {
2373 IX86_FUNCTION_SPECIFIC_ARCH,
2374 IX86_FUNCTION_SPECIFIC_TUNE,
2375 IX86_FUNCTION_SPECIFIC_MAX
2376 };
2394 \f
2395 #ifndef SUBTARGET32_DEFAULT_CPU
2397 #endif
2399 /* Whether -mtune= or -march= were specified */
2403 /* Vectorization library interface and handlers. */
2409 /* Processor target table, indexed by processor number */
2410 struct ptt
2411 {
2418 };
2421 {
2432 /* Core 2 */
2434 /* Core i7 */
2436 /* Core avx2 */
2447 };
2450 {
2479 "btver2"
2480 };
2481 \f
2482 static bool
2484 {
2486 }
2488 static unsigned int
2490 {
2493 /* vzeroupper instructions are inserted immediately after reload to
2494 account for possible spills from 256bit registers. The pass
2495 reuses mode switching infrastructure by re-running mode insertion
2496 pass, so disable entities that have already been processed. */
2502 /* Call optimize_mode_switching. */
2505 }
2508 {
2509 {
2510 RTL_PASS,
2525 }
2526 };
2528 /* Return true if a red-zone is in use. */
2532 {
2534 }
2535 \f
2536 /* Return a string that documents the current -m options. The caller is
2537 responsible for freeing the string. */
2543 {
2544 struct ix86_target_opts
2545 {
2548 };
2550 /* This table is ordered so that options like -msse4.2 that imply
2551 preceding options while match those first. */
2553 {
2589 };
2591 /* Flag options. */
2593 {
2621 };
2638 /* Add -march= option. */
2640 {
2643 }
2645 /* Add -mtune= option. */
2647 {
2650 }
2652 /* Add -m32/-m64/-mx32. */
2654 {
2657 else
2659 isa &= ~ (OPTION_MASK_ISA_64BIT
2660 | OPTION_MASK_ABI_64
2662 }
2663 else
2667 /* Pick out the options in isa options. */
2669 {
2671 {
2674 }
2675 }
2678 {
2681 isa);
2682 }
2684 /* Add flag options. */
2686 {
2688 {
2691 }
2692 }
2695 {
2698 }
2700 /* Add -fpmath= option. */
2702 {
2705 {
2720 }
2721 }
2723 /* Any options? */
2729 /* Size the string. */
2733 {
2738 }
2740 /* Build the string. */
2745 {
2752 {
2754 line_len++;
2757 {
2761 }
2762 }
2766 {
2770 }
2771 }
2777 }
2779 /* Return true, if profiling code should be emitted before
2780 prologue. Otherwise it returns false.
2781 Note: For x86 with "hotfix" it is sorried. */
2782 static bool
2784 {
2786 }
2788 /* Function that is callable from the debugger to print the current
2789 options. */
2790 void
2792 {
2798 {
2801 }
2802 else
2806 }
2807 \f
2808 /* Override various settings based on options. If MAIN_ARGS_P, the
2809 options are from the command line, otherwise they are from
2810 attributes. */
2812 static void
2814 {
2822 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2823 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2824 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2825 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2826 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2827 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2828 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2829 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2830 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2831 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2832 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2833 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2834 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2835 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2836 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2837 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2838 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2839 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2840 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2841 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2842 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2843 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2844 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2845 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2846 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2847 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2848 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2849 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2850 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2851 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2852 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2853 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2854 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2855 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2856 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2857 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2858 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2859 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2860 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2861 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2863 /* if this reaches 64, need to widen struct pta flags below */
2865 static struct pta
2866 {
2871 }
2873 {
3003 PTA_64BIT
3005 };
3007 /* -mrecip options. */
3008 static struct
3009 {
3012 }
3014 {
3021 };
3025 /* Set up prefix/suffix so the error messages refer to either the command
3026 line argument, or the attribute(target). */
3028 {
3032 }
3033 else
3034 {
3038 }
3040 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3041 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3044 #ifdef TARGET_BI_ARCH
3045 else
3046 {
3047 #if TARGET_BI_ARCH == 1
3048 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3049 is on and OPTION_MASK_ABI_X32 is off. We turn off
3050 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3051 -mx32. */
3054 #else
3055 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3056 on and OPTION_MASK_ABI_64 is off. We turn off
3057 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3058 -m64. */
3061 #endif
3062 }
3063 #endif
3066 {
3067 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3068 OPTION_MASK_ABI_64 for TARGET_X32. */
3071 }
3073 {
3074 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3075 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3078 }
3080 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3081 SUBTARGET_OVERRIDE_OPTIONS;
3082 #endif
3084 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3085 SUBSUBTARGET_OVERRIDE_OPTIONS;
3086 #endif
3088 /* -fPIC is the default for x86_64. */
3092 /* Need to check -mtune=generic first. */
3094 {
3097 /* As special support for cross compilers we read -mtune=native
3098 as -mtune=generic. With native compilers we won't see the
3099 -mtune=native, as it was changed by the driver. */
3101 {
3104 else
3106 }
3107 /* If this call is for setting the option attribute, allow the
3108 generic32/generic64 that was previously set. */
3112 ;
3120 }
3121 else
3122 {
3126 {
3129 }
3131 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3132 need to use a sensible tune option. */
3136 {
3139 else
3141 }
3142 }
3145 {
3146 /* rep; movq isn't available in 32-bit code. */
3149 }
3153 else
3157 {
3163 }
3164 else
3171 {
3173 {
3217 {
3220 }
3228 }
3229 }
3230 else
3231 {
3232 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3233 use of rip-relative addressing. This eliminates fixups that
3234 would otherwise be needed if this object is to be placed in a
3235 DLL, and is essentially just as efficient as direct addressing. */
3242 else
3244 }
3246 {
3249 }
3256 {
3259 /* Default cpu tuning to the architecture. */
3384 }
3399 {
3403 {
3405 {
3407 {
3415 }
3416 else
3419 }
3420 }
3421 else
3422 {
3423 /* Adjust tuning when compiling for 32-bit ABI. */
3425 {
3433 }
3434 }
3435 /* Intel CPUs have always interpreted SSE prefetch instructions as
3436 NOPs; so, we can enable SSE prefetch instructions even when
3437 -mtune (rather than -march) points us to a processor that has them.
3438 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3439 higher processors. */
3444 }
3454 #ifndef USE_IX86_FRAME_POINTER
3455 #define USE_IX86_FRAME_POINTER 0
3456 #endif
3458 #ifndef USE_X86_64_FRAME_POINTER
3459 #define USE_X86_64_FRAME_POINTER 0
3460 #endif
3462 /* Set the default values for switches whose default depends on TARGET_64BIT
3463 in case they weren't overwritten by command line options. */
3465 {
3472 }
3473 else
3474 {
3481 }
3486 else
3489 /* Arrange to set up i386_stack_locals for all functions. */
3492 /* Validate -mregparm= value. */
3494 {
3498 {
3502 }
3503 }
3507 /* Default align_* from the processor table. */
3509 {
3512 }
3514 {
3517 }
3519 {
3521 }
3523 /* Provide default for -mbranch-cost= value. */
3528 {
3531 /* Enable by default the SSE and MMX builtins. Do allow the user to
3532 explicitly disable any of these. In particular, disabling SSE and
3533 MMX for kernel code is extremely useful. */
3535 ix86_isa_flags
3541 }
3542 else
3543 {
3547 ix86_isa_flags
3550 /* i386 ABI does not specify red zone. It still makes sense to use it
3551 when programmer takes care to stack from being destroyed. */
3554 }
3556 /* Keep nonleaf frame pointers. */
3562 /* If we're doing fast math, we don't care about comparison order
3563 wrt NaNs. This lets us use a shorter comparison sequence. */
3567 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3568 since the insns won't need emulation. */
3572 /* Likewise, if the target doesn't have a 387, or we've specified
3573 software floating point, don't use 387 inline intrinsics. */
3577 /* Turn on MMX builtins for -msse. */
3581 /* Enable SSE prefetch. */
3585 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3589 /* Turn on lzcnt instruction for -mabm. */
3593 /* Validate -mpreferred-stack-boundary= value or default it to
3594 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3597 {
3603 {
3607 else
3610 }
3611 else
3612 ix86_preferred_stack_boundary
3614 }
3616 /* Set the default value for -mstackrealign. */
3622 /* Validate -mincoming-stack-boundary= value or default it to
3623 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3626 {
3631 else
3632 {
3633 ix86_user_incoming_stack_boundary
3635 ix86_incoming_stack_boundary
3637 }
3638 }
3640 /* Accept -msseregparm only if at least SSE support is enabled. */
3646 {
3648 {
3650 {
3653 }
3655 {
3658 }
3659 }
3660 }
3661 else
3664 /* If the i387 is disabled, then do not return values in it. */
3668 /* Use external vectorized library in vectorizing intrinsics. */
3671 {
3682 }
3690 /* ??? Unwind info is not correct around the CFG unless either a frame
3691 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3692 unwind info generation to be aware of the CFG and propagating states
3693 around edges. */
3696 && flag_omit_frame_pointer
3698 {
3704 }
3706 /* If stack probes are required, the space used for large function
3707 arguments on the stack must also be probed, so enable
3708 -maccumulate-outgoing-args so this happens in the prologue. */
3711 {
3716 }
3718 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3719 {
3725 }
3727 /* When scheduling description is not available, disable scheduler pass
3728 so it won't slow down the compilation and make x87 code slower. */
3749 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3751 && HAVE_prefetch
3756 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3757 can be optimized to ap = __builtin_next_arg (0). */
3762 {
3765 {
3768 ix86_gen_tls_local_dynamic_base_64
3770 }
3771 else
3772 {
3775 ix86_gen_tls_local_dynamic_base_64
3777 }
3778 }
3779 else
3780 {
3783 }
3786 {
3795 }
3796 else
3797 {
3806 }
3808 #ifdef USE_IX86_CLD
3809 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3812 #endif
3815 {
3820 }
3822 {
3826 }
3828 {
3829 #if defined(PROFILE_BEFORE_PROLOGUE)
3831 #else
3833 #endif
3834 }
3837 {
3838 /* When not optimize for size, enable vzeroupper optimization for
3839 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3840 AVX unaligned load/store. */
3842 {
3852 /* Enable 128-bit AVX instruction generation
3853 for the auto-vectorizer. */
3857 }
3858 }
3859 else
3860 {
3861 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3863 }
3866 {
3873 {
3876 {
3878 q++;
3879 }
3880 else
3885 else
3886 {
3889 {
3892 }
3895 {
3899 }
3900 }
3905 else
3907 }
3908 }
3915 /* Default long double to 64-bit for Bionic. */
3920 /* Save the initial options in case the user does function specific
3921 options. */
3923 target_option_default_node = target_option_current_node
3925 }
3927 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3929 static void
3931 {
3932 static struct register_pass_info insert_vzeroupper_info
3935 };
3940 /* This needs to be done at start up. It's convenient to do it here. */
3942 }
3944 /* Update register usage after having seen the compiler flags. */
3946 static void
3948 {
3952 /* The PIC register, if it exists, is fixed. */
3957 /* For 32-bit targets, squash the REX registers. */
3959 {
3964 }
3966 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3974 {
3975 /* Set/reset conditionally defined registers from
3976 CALL_USED_REGISTERS initializer. */
3980 /* Calculate registers of CLOBBERED_REGS register set
3981 as call used registers from GENERAL_REGS register set. */
3985 }
3987 /* If MMX is disabled, squash the registers. */
3993 /* If SSE is disabled, squash the registers. */
3999 /* If the FPU is disabled, squash the registers. */
4004 }
4006 \f
4007 /* Save the current options */
4009 static void
4011 {
4022 /* The fields are char but the variables are not; make sure the
4023 values fit in the fields. */
4028 }
4030 /* Restore the current options */
4032 static void
4034 {
4050 /* Recreate the arch feature tests if the arch changed */
4052 {
4057 }
4059 /* Recreate the tune optimization tests */
4061 {
4066 }
4067 }
4069 /* Print the current options */
4071 static void
4074 {
4096 {
4099 }
4100 }
4102 \f
4103 /* Inner function to process the attribute((target(...))), take an argument and
4104 set the current options from the argument. If we have a list, recursively go
4105 over the list. */
4107 static bool
4110 {
4114 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4115 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4116 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4117 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4118 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4120 enum ix86_opt_type
4121 {
4122 ix86_opt_unknown,
4123 ix86_opt_yes,
4124 ix86_opt_no,
4125 ix86_opt_str,
4126 ix86_opt_enum,
4127 ix86_opt_isa
4128 };
4130 static const struct
4131 {
4138 /* isa options */
4175 /* enum options */
4178 /* string options */
4182 /* flag options */
4184 OPT_mcld,
4185 MASK_CLD),
4188 OPT_mfancy_math_387,
4189 MASK_NO_FANCY_MATH_387),
4192 OPT_mieee_fp,
4193 MASK_IEEE_FP),
4196 OPT_minline_all_stringops,
4197 MASK_INLINE_ALL_STRINGOPS),
4200 OPT_minline_stringops_dynamically,
4201 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4204 OPT_mno_align_stringops,
4205 MASK_NO_ALIGN_STRINGOPS),
4208 OPT_mrecip,
4209 MASK_RECIP),
4211 };
4213 /* If this is a list, recurse to get the options. */
4215 {
4225 }
4228 {
4231 }
4233 /* Handle multiple arguments separated by commas. */
4237 {
4251 {
4255 }
4256 else
4257 {
4260 }
4262 /* Recognize no-xxx. */
4264 {
4268 }
4269 else
4272 /* Find the option. */
4276 {
4284 {
4289 }
4290 }
4292 /* Process the option. */
4294 {
4297 }
4300 {
4306 }
4309 {
4315 else
4317 }
4320 {
4322 {
4325 }
4326 else
4328 }
4331 {
4339 global_dc);
4340 else
4341 {
4344 }
4345 }
4347 else
4349 }
4352 }
4354 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4356 tree
4358 {
4373 /* Process each of the options on the chain. */
4378 /* If the changed options are different from the default, rerun
4379 ix86_option_override_internal, and then save the options away.
4380 The string options are are attribute options, and will be undone
4381 when we copy the save structure. */
4387 {
4388 /* If we are using the default tune= or arch=, undo the string assigned,
4389 and use the default. */
4400 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4404 {
4407 }
4409 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4412 /* Add any builtin functions with the new isa if any. */
4415 /* Save the current options unless we are validating options for
4416 #pragma. */
4423 /* Free up memory allocated to hold the strings */
4426 }
4429 }
4431 /* Hook to validate attribute((target("string"))). */
4433 static bool
4436 tree args,
4438 {
4442 /* attribute((target("default"))) does nothing, beyond
4443 affecting multi-versioning. */
4454 /* If the function changed the optimization levels as well as setting target
4455 options, start with the optimizations specified. */
4460 /* The target attributes may also change some optimization flags, so update
4461 the optimization options if necessary. */
4470 {
4475 }
4484 }
4486 \f
4487 /* Hook to determine if one function can safely inline another. */
4489 static bool
4491 {
4496 /* If callee has no option attributes, then it is ok to inline. */
4500 /* If caller has no option attributes, but callee does then it is not ok to
4501 inline. */
4505 else
4506 {
4510 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4511 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4512 function. */
4517 /* See if we have the same non-isa options. */
4521 /* See if arch, tune, etc. are the same. */
4534 else
4536 }
4539 }
4541 \f
4542 /* Remember the last target of ix86_set_current_function. */
4545 /* Establish appropriate back-end context for processing the function
4546 FNDECL. The argument might be NULL to indicate processing at top
4547 level, outside of any function scope. */
4548 static void
4550 {
4551 /* Only change the context if the function changes. This hook is called
4552 several times in the course of compiling a function, and we don't want to
4553 slow things down too much or call target_reinit when it isn't safe. */
4555 {
4556 tree old_tree = (ix86_previous_fndecl
4560 tree new_tree = (fndecl
4566 ;
4569 {
4573 }
4576 {
4582 }
4583 }
4584 }
4586 \f
4587 /* Return true if this goes in large data/bss. */
4589 static bool
4591 {
4595 /* Functions are never large data. */
4600 {
4606 }
4607 else
4608 {
4611 /* If this is an incomplete type with size 0, then we can't put it
4612 in data because it might be too big when completed. */
4615 }
4618 }
4620 /* Switch to the appropriate section for output of DECL.
4621 DECL is either a `VAR_DECL' node or a constant of some sort.
4622 RELOC indicates whether forming the initial value of DECL requires
4623 link-time relocations. */
4626 ATTRIBUTE_UNUSED;
4631 {
4634 {
4638 {
4672 /* We don't split these for medium model. Place them into
4673 default sections and hope for best. */
4675 }
4677 {
4678 /* We might get called with string constants, but get_named_section
4679 doesn't like them as they are not DECLs. Also, we need to set
4680 flags in that case. */
4684 }
4685 }
4687 }
4689 /* Build up a unique section name, expressed as a
4690 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4691 RELOC indicates whether the initial value of EXP requires
4692 link-time relocations. */
4694 static void ATTRIBUTE_UNUSED
4696 {
4699 {
4701 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4705 {
4729 /* We don't split these for medium model. Place them into
4730 default sections and hope for best. */
4732 }
4734 {
4741 /* If we're using one_only, then there needs to be a .gnu.linkonce
4742 prefix to the section name. */
4749 }
4750 }
4752 }
4754 #ifdef COMMON_ASM_OP
4755 /* This says how to output assembler code to declare an
4756 uninitialized external linkage data object.
4758 For medium model x86-64 we need to use .largecomm opcode for
4759 large objects. */
4760 void
4764 {
4768 else
4773 }
4774 #endif
4776 /* Utility function for targets to use in implementing
4777 ASM_OUTPUT_ALIGNED_BSS. */
4779 void
4783 {
4787 else
4790 #ifdef ASM_DECLARE_OBJECT_NAME
4793 #else
4794 /* Standard thing is just output label for the object. */
4798 }
4799 \f
4800 /* Decide whether we must probe the stack before any space allocation
4801 on this target. It's essentially TARGET_STACK_PROBE except when
4802 -fstack-check causes the stack to be already probed differently. */
4804 bool
4806 {
4807 /* Do not probe the stack twice if static stack checking is enabled. */
4812 }
4813 \f
4814 /* Decide whether we can make a sibling call to a function. DECL is the
4815 declaration of the function being targeted by the call and EXP is the
4816 CALL_EXPR representing the call. */
4818 static bool
4820 {
4824 /* If we are generating position-independent code, we cannot sibcall
4825 optimize any indirect call, or a direct call to a global function,
4826 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4828 && !TARGET_64BIT
4829 && flag_pic
4833 /* If we need to align the outgoing stack, then sibcalling would
4834 unalign the stack, which may break the called function. */
4840 {
4843 }
4844 else
4845 {
4846 /* We're looking at the CALL_EXPR, we need the type of the function. */
4851 }
4853 /* Check that the return value locations are the same. Like
4854 if we are returning floats on the 80387 register stack, we cannot
4855 make a sibcall from a function that doesn't return a float to a
4856 function that does or, conversely, from a function that does return
4857 a float to a function that doesn't; the necessary stack adjustment
4858 would not be executed. This is also the place we notice
4859 differences in the return value ABI. Note that it is ok for one
4860 of the functions to have void return type as long as the return
4861 value of the other is passed in a register. */
4866 {
4869 }
4871 ;
4876 {
4877 /* The SYSV ABI has more call-clobbered registers;
4878 disallow sibcalls from MS to SYSV. */
4882 }
4883 else
4884 {
4885 /* If this call is indirect, we'll need to be able to use a
4886 call-clobbered register for the address of the target function.
4887 Make sure that all such registers are not used for passing
4888 parameters. Note that DLLIMPORT functions are indirect. */
4891 {
4893 {
4894 /* ??? Need to count the actual number of registers to be used,
4895 not the possible number of registers. Fix later. */
4897 }
4898 }
4899 }
4901 /* Otherwise okay. That also includes certain types of indirect calls. */
4903 }
4905 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4906 and "sseregparm" calling convention attributes;
4907 arguments as in struct attribute_spec.handler. */
4909 static tree
4911 tree args,
4914 {
4919 {
4921 name);
4924 }
4926 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4928 {
4929 tree cst;
4932 {
4934 }
4937 {
4939 }
4943 {
4946 name);
4948 }
4950 {
4954 }
4957 }
4960 {
4961 /* Do not warn when emulating the MS ABI. */
4966 name);
4969 }
4971 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4973 {
4975 {
4977 }
4979 {
4981 }
4983 {
4985 }
4987 {
4989 }
4990 }
4992 /* Can combine stdcall with fastcall (redundant), regparm and
4993 sseregparm. */
4995 {
4997 {
4999 }
5001 {
5003 }
5005 {
5007 }
5008 }
5010 /* Can combine cdecl with regparm and sseregparm. */
5012 {
5014 {
5016 }
5018 {
5020 }
5022 {
5024 }
5025 }
5027 {
5030 name);
5032 {
5034 }
5036 {
5038 }
5040 {
5042 }
5043 }
5045 /* Can combine sseregparm with all attributes. */
5048 }
5050 /* The transactional memory builtins are implicitly regparm or fastcall
5051 depending on the ABI. Override the generic do-nothing attribute that
5052 these builtins were declared with, and replace it with one of the two
5053 attributes that we expect elsewhere. */
5055 static tree
5057 tree args ATTRIBUTE_UNUSED,
5060 {
5061 tree alt;
5063 /* In no case do we want to add the placeholder attribute. */
5066 /* The 64-bit ABI is unchanged for transactional memory. */
5070 /* ??? Is there a better way to validate 32-bit windows? We have
5071 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5074 else
5075 {
5078 }
5082 }
5084 /* This function determines from TYPE the calling-convention. */
5086 unsigned int
5088 {
5091 tree attrs;
5098 {
5108 /* Regparam isn't allowed for thiscall and fastcall. */
5110 {
5115 }
5119 }
5126 || is_stdarg
5132 }
5134 /* Return 0 if the attributes for two types are incompatible, 1 if they
5135 are compatible, and 2 if they are nearly compatible (which causes a
5136 warning to be generated). */
5138 static int
5140 {
5156 }
5157 \f
5158 /* Return the regparm value for a function with the indicated TYPE and DECL.
5159 DECL may be NULL when calling function indirectly
5160 or considering a libcall. */
5162 static int
5164 {
5165 tree attr;
5176 {
5179 {
5182 }
5183 }
5189 /* Use register calling convention for local functions when possible. */
5192 && optimize
5194 {
5195 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5198 {
5201 /* Make sure no regparm register is taken by a
5202 fixed register variable. */
5207 /* We don't want to use regparm(3) for nested functions as
5208 these use a static chain pointer in the third argument. */
5212 /* In 32-bit mode save a register for the split stack. */
5216 /* Each fixed register usage increases register pressure,
5217 so less registers should be used for argument passing.
5218 This functionality can be overriden by an explicit
5219 regparm value. */
5222 globals++;
5224 local_regparm
5229 }
5230 }
5233 }
5235 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5236 DFmode (2) arguments in SSE registers for a function with the
5237 indicated TYPE and DECL. DECL may be NULL when calling function
5238 indirectly or considering a libcall. Otherwise return 0. */
5240 static int
5242 {
5245 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5246 by the sseregparm attribute. */
5249 {
5251 {
5253 {
5257 else
5260 }
5262 }
5265 }
5267 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5268 (and DFmode for SSE2) arguments in SSE registers. */
5271 {
5272 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5276 }
5279 }
5281 /* Return true if EAX is live at the start of the function. Used by
5282 ix86_expand_prologue to determine if we need special help before
5283 calling allocate_stack_worker. */
5285 static bool
5287 {
5288 /* Cheat. Don't bother working forward from ix86_function_regparm
5289 to the function type to whether an actual argument is located in
5290 eax. Instead just look at cfg info, which is still close enough
5291 to correct at this point. This gives false positives for broken
5292 functions that might use uninitialized data that happens to be
5293 allocated in eax, but who cares? */
5295 }
5297 static bool
5299 {
5300 tree attr;
5303 {
5309 /* For 32-bit MS-ABI the default is to keep aggregate
5310 return pointer. */
5313 }
5315 }
5317 /* Value is the number of bytes of arguments automatically
5318 popped when returning from a subroutine call.
5319 FUNDECL is the declaration node of the function (as a tree),
5320 FUNTYPE is the data type of the function (as a tree),
5321 or for a library call it is an identifier node for the subroutine name.
5322 SIZE is the number of bytes of arguments passed on the stack.
5324 On the 80386, the RTD insn may be used to pop them if the number
5325 of args is fixed, but if the number is variable then the caller
5326 must pop them all. RTD can't be used for library calls now
5327 because the library is compiled with the Unix compiler.
5328 Use of RTD is a selectable option, since it is incompatible with
5329 standard Unix calling sequences. If the option is not selected,
5330 the caller must always pop the args.
5332 The attribute stdcall is equivalent to RTD on a per module basis. */
5334 static int
5336 {
5339 /* None of the 64-bit ABIs pop arguments. */
5350 /* Lose any fake structure return argument if it is passed on the stack. */
5353 {
5357 }
5360 }
5362 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5364 static bool
5366 {
5367 /* Check operand constraints in case hard registers were propagated
5368 into insn pattern. This check prevents combine pass from
5369 generating insn patterns with invalid hard register operands.
5370 These invalid insns can eventually confuse reload to error out
5371 with a spill failure. See also PRs 46829 and 46843. */
5373 {
5380 {
5388 /* A unary operator may be accepted by the predicate, but it
5389 is irrelevant for matching constraints. */
5394 {
5402 }
5409 /* Operand has no constraints, anything is OK. */
5413 {
5416 && operands_match_p
5420 {
5423 }
5424 }
5428 }
5429 }
5432 }
5433 \f
5434 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5436 static unsigned HOST_WIDE_INT
5438 {
5441 }
5442 \f
5443 /* Argument support functions. */
5445 /* Return true when register may be used to pass function parameters. */
5446 bool
5448 {
5453 {
5457 else
5463 }
5466 {
5469 }
5470 else
5471 {
5475 }
5477 /* TODO: The function should depend on current function ABI but
5478 builtins.c would need updating then. Therefore we use the
5479 default ABI. */
5481 /* RAX is used as hidden argument to va_arg functions. */
5487 else
5494 }
5496 /* Return if we do not know how to pass TYPE solely in registers. */
5498 static bool
5500 {
5504 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5505 The layout_type routine is crafty and tries to trick us into passing
5506 currently unsupported vector types on the stack by using TImode. */
5509 }
5511 /* It returns the size, in bytes, of the area reserved for arguments passed
5512 in registers for the function represented by fndecl dependent to the used
5513 abi format. */
5514 int
5516 {
5520 else
5525 }
5527 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5528 call abi used. */
5529 enum calling_abi
5531 {
5533 {
5536 {
5539 }
5543 }
5545 }
5547 static bool
5549 {
5551 {
5555 else
5557 }
5559 }
5561 static enum calling_abi
5563 {
5567 }
5569 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5570 call abi used. */
5571 enum calling_abi
5573 {
5577 }
5579 /* Write the extra assembler code needed to declare a function properly. */
5581 void
5583 tree decl)
5584 {
5588 {
5594 }
5596 #ifdef SUBTARGET_ASM_UNWIND_INIT
5598 #endif
5602 /* Output magic byte marker, if hot-patch attribute is set. */
5604 {
5606 {
5607 /* leaq [%rsp + 0], %rsp */
5610 }
5611 else
5612 {
5613 /* movl.s %edi, %edi
5614 push %ebp
5615 movl.s %esp, %ebp */
5618 }
5619 }
5620 }
5622 /* regclass.c */
5625 /* Implementation of call abi switching target hook. Specific to FNDECL
5626 the specific call register sets are set. See also
5627 ix86_conditional_register_usage for more details. */
5628 void
5630 {
5633 else
5635 }
5637 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5638 expensive re-initialization of init_regs each time we switch function context
5639 since this is needed only during RTL expansion. */
5640 static void
5642 {
5646 }
5648 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5649 for a call to a function whose data type is FNTYPE.
5650 For a library call, FNTYPE is 0. */
5652 void
5656 tree fndecl,
5658 {
5664 {
5667 }
5668 else
5669 {
5672 }
5676 /* Set up the number of registers to use for passing arguments. */
5683 {
5685 ? X86_64_REGPARM_MAX
5687 }
5689 {
5692 {
5694 ? X86_64_SSE_REGPARM_MAX
5696 }
5697 }
5704 /* Because type might mismatch in between caller and callee, we need to
5705 use actual type of function for local calls.
5706 FIXME: cgraph_analyze can be told to actually record if function uses
5707 va_start so for local functions maybe_vaarg can be made aggressive
5708 helping K&R code.
5709 FIXME: once typesytem is fixed, we won't need this code anymore. */
5717 {
5718 /* If there are variable arguments, then we won't pass anything
5719 in registers in 32-bit mode. */
5721 {
5729 }
5731 /* Use ecx and edx registers if function has fastcall attribute,
5732 else look for regparm information. */
5734 {
5737 {
5740 }
5742 {
5745 }
5746 else
5748 }
5750 /* Set up the number of SSE registers used for passing SFmode
5751 and DFmode arguments. Warn for mismatching ABI. */
5753 }
5754 }
5756 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5757 But in the case of vector types, it is some vector mode.
5759 When we have only some of our vector isa extensions enabled, then there
5760 are some modes for which vector_mode_supported_p is false. For these
5761 modes, the generic vector support in gcc will choose some non-vector mode
5762 in order to implement the type. By computing the natural mode, we'll
5763 select the proper ABI location for the operand and not depend on whatever
5764 the middle-end decides to do with these vector types.
5766 The midde-end can't deal with the vector types > 16 bytes. In this
5767 case, we return the original mode and warn ABI change if CUM isn't
5768 NULL. */
5770 static enum machine_mode
5772 {
5776 {
5779 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5781 {
5786 else
5789 /* Get the mode which has this inner mode and number of units. */
5793 {
5795 {
5799 && !warnedavx
5801 {
5805 }
5807 }
5809 {
5813 && !warnedsse
5815 {
5819 }
5821 }
5822 else
5824 }
5827 }
5828 }
5831 }
5833 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5834 this may not agree with the mode that the type system has chosen for the
5835 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5836 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5838 static rtx
5841 {
5842 rtx tmp;
5846 else
5847 {
5851 }
5854 }
5856 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5857 of this code is to classify each 8bytes of incoming argument by the register
5858 class and assign registers accordingly. */
5860 /* Return the union class of CLASS1 and CLASS2.
5861 See the x86-64 PS ABI for details. */
5863 static enum x86_64_reg_class
5865 {
5866 /* Rule #1: If both classes are equal, this is the resulting class. */
5870 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5871 the other class. */
5877 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5881 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5889 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5890 MEMORY is used. */
5899 /* Rule #6: Otherwise class SSE is used. */
5901 }
5903 /* Classify the argument of type TYPE and mode MODE.
5904 CLASSES will be filled by the register class used to pass each word
5905 of the operand. The number of words is returned. In case the parameter
5906 should be passed in memory, 0 is returned. As a special case for zero
5907 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5909 BIT_OFFSET is used internally for handling records and specifies offset
5910 of the offset in bits modulo 256 to avoid overflow cases.
5912 See the x86-64 PS ABI for details.
5913 */
5915 static int
5918 {
5919 HOST_WIDE_INT bytes =
5921 int words
5924 /* Variable sized entities are always passed/returned in memory. */
5933 {
5935 tree field;
5938 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5945 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5946 signalize memory class, so handle it as special case. */
5948 {
5951 }
5953 /* Classify each field of record and merge classes. */
5955 {
5957 /* And now merge the fields of structure. */
5959 {
5961 {
5967 /* Bitfields are always classified as integer. Handle them
5968 early, since later code would consider them to be
5969 misaligned integers. */
5971 {
5980 }
5981 else
5982 {
5987 /* Flexible array member is ignored. */
5994 {
5998 {
6001 "the ABI of passing struct with"
6002 " a flexible array member has"
6004 }
6006 }
6008 subclasses,
6018 }
6019 }
6020 }
6024 /* Arrays are handled as small records. */
6025 {
6032 /* The partial classes are now full classes. */
6043 }
6046 /* Unions are similar to RECORD_TYPE but offset is always 0.
6047 */
6049 {
6051 {
6059 bit_offset);
6064 }
6065 }
6070 }
6073 {
6074 /* When size > 16 bytes, if the first one isn't
6075 X86_64_SSE_CLASS or any other ones aren't
6076 X86_64_SSEUP_CLASS, everything should be passed in
6077 memory. */
6084 }
6086 /* Final merger cleanup. */
6088 {
6089 /* If one class is MEMORY, everything should be passed in
6090 memory. */
6094 /* The X86_64_SSEUP_CLASS should be always preceded by
6095 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6099 {
6100 /* The first one should never be X86_64_SSEUP_CLASS. */
6103 }
6105 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6106 everything should be passed in memory. */
6109 {
6112 /* The first one should never be X86_64_X87UP_CLASS. */
6115 {
6118 "the ABI of passing union with long double"
6120 }
6122 }
6123 }
6125 }
6127 /* Compute alignment needed. We align all types to natural boundaries with
6128 exception of XFmode that is aligned to 64bits. */
6130 {
6139 /* Misaligned fields are always returned in memory. */
6142 }
6144 /* for V1xx modes, just use the base mode */
6149 /* Classification of atomic types. */
6151 {
6167 {
6171 {
6174 }
6176 {
6179 }
6181 {
6185 }
6187 {
6190 }
6191 else
6193 }
6200 /* OImode shouldn't be used directly. */
6207 else
6225 else
6226 {
6230 {
6233 "the ABI of passing structure with complex float"
6235 }
6238 }
6247 /* This modes is larger than 16 bytes. */
6290 else
6294 }
6295 }
6297 /* Examine the argument and return set number of register required in each
6298 class. Return 0 iff parameter should be passed in memory. */
6299 static int
6302 {
6312 {
6334 }
6336 }
6338 /* Construct container for the argument used by GCC interface. See
6339 FUNCTION_ARG for the detailed description. */
6341 static rtx
6345 {
6346 /* The following variables hold the static issued_error state. */
6360 rtx ret;
6371 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6372 some less clueful developer tries to use floating-point anyway. */
6374 {
6376 {
6378 {
6381 }
6382 }
6384 {
6387 }
6389 }
6391 /* Likewise, error if the ABI requires us to return values in the
6392 x87 registers and the user specified -mno-80387. */
6398 {
6400 {
6403 }
6405 }
6407 /* First construct simple cases. Avoid SCmode, since we want to use
6408 single register to pass this type. */
6411 {
6426 /* Zero sized array, struct or class. */
6430 }
6457 /* Otherwise figure out the entries of the PARALLEL. */
6459 {
6463 {
6468 /* Merge TImodes on aligned occasions here too. */
6470 tmpmode
6474 else
6476 /* We've requested 24 bytes we
6477 don't have mode for. Use DImode. */
6484 intreg++;
6492 sse_regno++;
6500 sse_regno++;
6505 {
6511 {
6513 i++;
6514 }
6515 else
6528 }
6534 sse_regno++;
6538 }
6539 }
6541 /* Empty aligned struct, union or class. */
6549 }
6551 /* Update the data in CUM to advance over an argument of mode MODE
6552 and data type TYPE. (TYPE is null for libcalls where that information
6553 may not be available.) */
6555 static void
6558 HOST_WIDE_INT words)
6559 {
6561 {
6568 /* FALLTHRU */
6579 {
6582 }
6586 /* OImode shouldn't be used directly. */
6595 /* FALLTHRU */
6611 {
6616 {
6619 }
6620 }
6630 {
6635 {
6638 }
6639 }
6641 }
6642 }
6644 static void
6647 {
6650 /* Unnamed 256bit vector mode parameters are passed on stack. */
6656 {
6661 }
6662 else
6663 {
6667 }
6668 }
6670 static void
6672 HOST_WIDE_INT words)
6673 {
6674 /* Otherwise, this should be passed indirect. */
6679 {
6682 }
6683 }
6685 /* Update the data in CUM to advance over an argument of mode MODE and
6686 data type TYPE. (TYPE is null for libcalls where that information
6687 may not be available.) */
6689 static void
6692 {
6698 else
6709 else
6711 }
6713 /* Define where to put the arguments to a function.
6714 Value is zero to push the argument on the stack,
6715 or a hard register in which to store the argument.
6717 MODE is the argument's machine mode.
6718 TYPE is the data type of the argument (as a tree).
6719 This is null for libcalls where that information may
6720 not be available.
6721 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6722 the preceding args and about the function being called.
6723 NAMED is nonzero if this argument is a named parameter
6724 (otherwise it is an extra parameter matching an ellipsis). */
6726 static rtx
6730 {
6733 /* Avoid the AL settings for the Unix64 ABI. */
6738 {
6745 /* FALLTHRU */
6751 {
6754 /* Fastcall allocates the first two DWORD (SImode) or
6755 smaller arguments to ECX and EDX if it isn't an
6756 aggregate type . */
6758 {
6764 /* ECX not EAX is the first allocated register. */
6767 }
6769 }
6778 /* FALLTHRU */
6780 /* In 32bit, we pass TImode in xmm registers. */
6788 {
6790 {
6794 }
6798 }
6802 /* OImode shouldn't be used directly. */
6812 {
6816 }
6826 {
6828 {
6832 }
6836 }
6838 }
6841 }
6843 static rtx
6846 {
6847 /* Handle a hidden AL argument containing number of registers
6848 for varargs x86-64 functions. */
6852 ? X86_64_SSE_REGPARM_MAX
6857 {
6867 /* Unnamed 256bit vector mode parameters are passed on stack. */
6871 }
6877 }
6879 static rtx
6882 HOST_WIDE_INT bytes)
6883 {
6886 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6887 We use value of -2 to specify that current function call is MSABI. */
6891 /* If we've run out of registers, it goes on the stack. */
6897 /* Only floating point modes are passed in anything but integer regs. */
6899 {
6902 else
6903 {
6906 /* Unnamed floating parameters are passed in both the
6907 SSE and integer registers. */
6913 }
6914 }
6915 /* Handle aggregated types passed in register. */
6917 {
6922 }
6925 }
6927 /* Return where to put the arguments to a function.
6928 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6930 MODE is the argument's machine mode. TYPE is the data type of the
6931 argument. It is null for libcalls where that information may not be
6932 available. CUM gives information about the preceding args and about
6933 the function being called. NAMED is nonzero if this argument is a
6934 named parameter (otherwise it is an extra parameter matching an
6935 ellipsis). */
6937 static rtx
6940 {
6944 rtx arg;
6948 else
6952 /* To simplify the code below, represent vector types with a vector mode
6953 even if MMX/SSE are not active. */
6961 else
6965 }
6967 /* A C expression that indicates when an argument must be passed by
6968 reference. If nonzero for an argument, a copy of that argument is
6969 made in memory and a pointer to the argument is passed instead of
6970 the argument itself. The pointer is passed in whatever way is
6971 appropriate for passing a pointer to that type. */
6973 static bool
6977 {
6980 /* See Windows x64 Software Convention. */
6982 {
6985 {
6986 /* Arrays are passed by reference. */
6991 {
6992 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6993 are passed by reference. */
6995 }
6996 }
6998 /* __m128 is passed by reference. */
7004 }
7005 }
7010 }
7012 /* Return true when TYPE should be 128bit aligned for 32bit argument
7013 passing ABI. XXX: This function is obsolete and is only used for
7014 checking psABI compatibility with previous versions of GCC. */
7016 static bool
7018 {
7030 {
7031 /* Walk the aggregates recursively. */
7033 {
7037 {
7038 tree field;
7040 /* Walk all the structure fields. */
7042 {
7046 }
7048 }
7051 /* Just for use if some languages passes arrays by value. */
7058 }
7059 }
7061 }
7063 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7064 XXX: This function is obsolete and is only used for checking psABI
7065 compatibility with previous versions of GCC. */
7067 static unsigned int
7070 {
7071 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7072 natural boundaries. */
7074 {
7075 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7076 make an exception for SSE modes since these require 128bit
7077 alignment.
7079 The handling here differs from field_alignment. ICC aligns MMX
7080 arguments to 4 byte boundaries, while structure fields are aligned
7081 to 8 byte boundaries. */
7083 {
7086 }
7087 else
7088 {
7091 }
7092 }
7096 }
7098 /* Return true when TYPE should be 128bit aligned for 32bit argument
7099 passing ABI. */
7101 static bool
7103 {
7113 {
7114 /* Walk the aggregates recursively. */
7116 {
7120 {
7121 tree field;
7123 /* Walk all the structure fields. */
7125 field;
7127 {
7131 }
7133 }
7136 /* Just for use if some languages passes arrays by value. */
7143 }
7144 }
7145 else
7149 }
7151 /* Gives the alignment boundary, in bits, of an argument with the
7152 specified mode and type. */
7154 static unsigned int
7156 {
7159 {
7160 /* Since the main variant type is used for call, we convert it to
7161 the main variant type. */
7164 }
7165 else
7169 else
7170 {
7175 {
7176 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7178 {
7181 }
7187 }
7190 && !warned
7192 saved_align))
7193 {
7196 "The ABI for passing parameters with %d-byte"
7199 }
7200 }
7203 }
7205 /* Return true if N is a possible register number of function value. */
7207 static bool
7209 {
7211 {
7216 /* TODO: The function should depend on current function ABI but
7217 builtins.c would need updating then. Therefore we use the
7218 default ABI. */
7230 }
7233 }
7235 /* Define how to find the value returned by a function.
7236 VALTYPE is the data type of the value (as a tree).
7237 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7238 otherwise, FUNC is 0. */
7240 static rtx
7243 {
7246 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7247 we normally prevent this case when mmx is not available. However
7248 some ABIs may require the result to be returned like DImode. */
7252 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7253 we prevent this case when sse is not available. However some ABIs
7254 may require the result to be returned like integer TImode. */
7259 /* 32-byte vector modes in %ymm0. */
7263 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7266 else
7267 /* Most things go in %eax. */
7270 /* Override FP return register with %xmm0 for local functions when
7271 SSE math is enabled or for functions with sseregparm attribute. */
7273 {
7278 }
7280 /* OImode shouldn't be used directly. */
7284 }
7286 static rtx
7288 const_tree valtype)
7289 {
7290 rtx ret;
7292 /* Handle libcalls, which don't provide a type node. */
7294 {
7298 {
7317 }
7320 }
7322 {
7323 /* Pointers are always returned in word_mode. */
7325 }
7331 /* For zero sized structures, construct_container returns NULL, but we
7332 need to keep rest of compiler happy by returning meaningful value. */
7337 }
7339 static rtx
7341 const_tree valtype)
7342 {
7346 {
7348 {
7367 }
7368 }
7370 }
7372 static rtx
7375 {
7387 else
7389 }
7391 static rtx
7394 {
7400 }
7402 /* Pointer function arguments and return values are promoted to
7403 word_mode. */
7405 static enum machine_mode
7409 {
7411 {
7414 }
7416 for_return);
7417 }
7419 /* Return true if a structure, union or array with MODE containing FIELD
7420 should be accessed using BLKmode. */
7422 static bool
7424 {
7425 /* Union with XFmode must be in BLKmode. */
7429 }
7431 rtx
7433 {
7435 }
7437 /* Return true iff type is returned in memory. */
7439 static bool ATTRIBUTE_UNUSED
7441 {
7442 HOST_WIDE_INT size;
7453 {
7454 /* User-created vectors small enough to fit in EAX. */
7458 /* MMX/3dNow values are returned in MM0,
7459 except when it doesn't exits or the ABI prescribes otherwise. */
7463 /* SSE values are returned in XMM0, except when it doesn't exist. */
7467 /* AVX values are returned in YMM0, except when it doesn't exist. */
7470 }
7478 /* OImode shouldn't be used directly. */
7482 }
7484 static bool ATTRIBUTE_UNUSED
7486 {
7489 }
7491 static bool ATTRIBUTE_UNUSED
7493 {
7496 /* __m128 is returned in xmm0. */
7503 /* Otherwise, the size must be exactly in [1248]. */
7505 }
7507 static bool
7509 {
7510 #ifdef SUBTARGET_RETURN_IN_MEMORY
7512 #else
7516 {
7519 else
7521 }
7522 else
7524 #endif
7525 }
7527 /* When returning SSE vector types, we have a choice of either
7528 (1) being abi incompatible with a -march switch, or
7529 (2) generating an error.
7530 Given no good solution, I think the safest thing is one warning.
7531 The user won't be able to use -Werror, but....
7533 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7534 called in response to actually generating a caller or callee that
7535 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7536 via aggregate_value_p for general type probing from tree-ssa. */
7538 static rtx
7540 {
7544 {
7545 /* Look at the return type of the function, not the function type. */
7549 {
7552 {
7556 }
7557 }
7560 {
7562 {
7566 }
7567 }
7568 }
7571 }
7573 \f
7574 /* Create the va_list data type. */
7576 /* Returns the calling convention specific va_list date type.
7577 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7579 static tree
7581 {
7584 /* For i386 we use plain pointer to argument area. */
7594 unsigned_type_node);
7597 unsigned_type_node);
7600 ptr_type_node);
7603 ptr_type_node);
7622 /* The correct type is an array type of one element. */
7624 }
7626 /* Setup the builtin va_list data type and for 64-bit the additional
7627 calling convention specific va_list data types. */
7629 static tree
7631 {
7634 /* Initialize abi specific va_list builtin types. */
7636 {
7637 tree t;
7639 {
7644 }
7645 else
7646 {
7651 }
7653 {
7658 }
7659 else
7660 {
7665 }
7666 }
7669 }
7671 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7673 static void
7675 {
7677 alias_set_type set;
7680 /* GPR size of varargs save area. */
7683 else
7686 /* FPR size of varargs save area. We don't need it if we don't pass
7687 anything in SSE registers. */
7690 else
7704 {
7712 }
7715 {
7719 /* Now emit code to save SSE registers. The AX parameter contains number
7720 of SSE parameter registers used to call this function, though all we
7721 actually check here is the zero/non-zero status. */
7726 label));
7728 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7729 we used movdqa (i.e. TImode) instead? Perhaps even better would
7730 be if we could determine the real mode of the data, via a hook
7731 into pass_stdarg. Ignore all that for now. */
7741 {
7750 }
7753 }
7754 }
7756 static void
7758 {
7762 /* Reset to zero, as there might be a sysv vaarg used
7763 before. */
7768 {
7779 }
7780 }
7782 static void
7786 {
7788 CUMULATIVE_ARGS next_cum;
7789 tree fntype;
7791 /* This argument doesn't appear to be used anymore. Which is good,
7792 because the old code here didn't suppress rtl generation. */
7800 /* For varargs, we do not want to skip the dummy va_dcl argument.
7801 For stdargs, we do want to skip the last named argument. */
7809 else
7811 }
7813 /* Checks if TYPE is of kind va_list char *. */
7815 static bool
7817 {
7818 tree canonic;
7820 /* For 32-bit it is always true. */
7826 }
7828 /* Implement va_start. */
7830 static void
7832 {
7836 tree type;
7837 rtx ovf_rtx;
7841 {
7844 /* When we are splitting the stack, we can't refer to the stack
7845 arguments using internal_arg_pointer, because they may be on
7846 the old stack. The split stack prologue will arrange to
7847 leave a pointer to the old stack arguments in a scratch
7848 register, which we here copy to a pseudo-register. The split
7849 stack prologue can't set the pseudo-register directly because
7850 it (the prologue) runs before any registers have been saved. */
7854 {
7868 }
7869 }
7871 /* Only 64bit target needs something special. */
7873 {
7876 else
7877 {
7886 }
7888 }
7897 /* The following should be folded into the MEM_REF offset. */
7907 /* Count number of gp and fp argument registers used. */
7913 {
7919 }
7922 {
7928 }
7930 /* Find the overflow area. */
7934 else
7944 {
7945 /* Find the register save area.
7946 Prologue of the function save it right above stack frame. */
7954 }
7955 }
7957 /* Implement va_arg. */
7959 static tree
7962 {
7969 rtx container;
7971 tree ptrtype;
7975 /* Only 64bit target needs something special. */
7999 {
8006 /* Unnamed 256bit vector mode parameters are passed on stack. */
8008 {
8011 }
8019 }
8021 /* Pull the value out of the saved registers. */
8026 {
8040 /* In case we are passing structure, verify that it is consecutive block
8041 on the register save area. If not we need to do moves. */
8043 {
8044 /* Verify that all registers are strictly consecutive */
8046 {
8050 {
8055 }
8056 }
8057 else
8058 {
8062 {
8067 }
8068 }
8069 }
8071 {
8074 }
8075 else
8076 {
8079 }
8081 /* First ensure that we fit completely in registers. */
8083 {
8090 }
8092 {
8100 }
8102 /* Compute index to start of area used for integer regs. */
8104 {
8105 /* int_addr = gpr + sav; */
8108 }
8110 {
8111 /* sse_addr = fpr + sav; */
8114 }
8116 {
8120 /* addr = &temp; */
8125 {
8129 tree piece_type;
8130 tree addr_type;
8131 tree daddr_type;
8140 {
8145 }
8149 else
8156 {
8159 }
8160 else
8161 {
8164 }
8171 {
8176 }
8177 else
8178 {
8179 tree copy
8184 }
8186 }
8187 }
8190 {
8194 }
8197 {
8201 }
8206 }
8208 /* ... otherwise out of the overflow area. */
8210 /* When we align parameter on stack for caller, if the parameter
8211 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8212 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8213 here with caller. */
8218 /* Care for on-stack alignment if needed. */
8221 else
8222 {
8227 }
8244 }
8245 \f
8246 /* Return true if OPNUM's MEM should be matched
8247 in movabs* patterns. */
8249 bool
8251 {
8263 }
8264 \f
8265 /* Initialize the table of extra 80387 mathematical constants. */
8267 static void
8269 {
8271 {
8277 };
8281 {
8283 /* Ensure each constant is rounded to XFmode precision. */
8286 }
8289 }
8291 /* Return non-zero if the constant is something that
8292 can be loaded with a special instruction. */
8294 int
8296 {
8299 REAL_VALUE_TYPE r;
8311 /* For XFmode constants, try to find a special 80387 instruction when
8312 optimizing for size or on those CPUs that benefit from them. */
8315 {
8324 }
8326 /* Load of the constant -0.0 or -1.0 will be split as
8327 fldz;fchs or fld1;fchs sequence. */
8334 }
8336 /* Return the opcode of the special instruction to be used to load
8337 the constant X. */
8341 {
8343 {
8363 }
8364 }
8366 /* Return the CONST_DOUBLE representing the 80387 constant that is
8367 loaded by the specified special instruction. The argument IDX
8368 matches the return value from standard_80387_constant_p. */
8370 rtx
8372 {
8379 {
8390 }
8393 XFmode);
8394 }
8396 /* Return 1 if X is all 0s and 2 if x is all 1s
8397 in supported SSE/AVX vector mode. */
8399 int
8401 {
8408 {
8423 }
8426 }
8428 /* Return the opcode of the special instruction to be used to load
8429 the constant X. */
8433 {
8435 {
8438 {
8455 }
8460 else
8465 }
8467 }
8469 /* Returns true if OP contains a symbol reference */
8471 bool
8473 {
8482 {
8484 {
8490 }
8494 }
8497 }
8499 /* Return true if it is appropriate to emit `ret' instructions in the
8500 body of a function. Do this only if the epilogue is simple, needing a
8501 couple of insns. Prior to reloading, we can't tell how many registers
8502 must be saved, so return false then. Return false if there is no frame
8503 marker to de-allocate. */
8505 bool
8507 {
8513 /* Don't allow more than 32k pop, since that's all we can do
8514 with one instruction. */
8521 }
8522 \f
8523 /* Value should be nonzero if functions must have frame pointers.
8524 Zero means the frame pointer need not be set up (and parms may
8525 be accessed via the stack pointer) in functions that seem suitable. */
8527 static bool
8529 {
8530 /* If we accessed previous frames, then the generated code expects
8531 to be able to access the saved ebp value in our frame. */
8535 /* Several x86 os'es need a frame pointer for other reasons,
8536 usually pertaining to setjmp. */
8540 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8544 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8545 allocation is 4GB. */
8549 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8550 turns off the frame pointer by default. Turn it back on now if
8551 we've not got a leaf function. */
8561 }
8563 /* Record that the current function accesses previous call frames. */
8565 void
8567 {
8569 }
8570 \f
8571 #ifndef USE_HIDDEN_LINKONCE
8572 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8573 # define USE_HIDDEN_LINKONCE 1
8574 # else
8575 # define USE_HIDDEN_LINKONCE 0
8576 # endif
8577 #endif
8581 /* Fills in the label name that should be used for a pc thunk for
8582 the given register. */
8584 static void
8586 {
8591 else
8593 }
8596 /* This function generates code for -fpic that loads %ebx with
8597 the return address of the caller and then returns. */
8599 static void
8601 {
8606 {
8608 tree decl;
8624 #if TARGET_MACHO
8626 {
8635 }
8636 else
8637 #endif
8639 {
8650 }
8651 else
8652 {
8655 }
8661 /* Make sure unwind info is emitted for the thunk if needed. */
8664 /* Pad stack IP move with 4 instructions (two NOPs count
8665 as one instruction). */
8667 {
8672 }
8683 }
8687 }
8689 /* Emit code for the SET_GOT patterns. */
8693 {
8699 {
8700 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8705 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8706 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8707 an unadorned address. */
8712 }
8717 {
8722 #if TARGET_MACHO
8723 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8724 is what will be referenced by the Mach-O PIC subsystem. */
8727 #endif
8731 }
8732 else
8733 {
8741 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8742 is what will be referenced by the Mach-O PIC subsystem. */
8743 #if TARGET_MACHO
8746 else
8749 #endif
8750 }
8756 }
8758 /* Generate an "push" pattern for input ARG. */
8760 static rtx
8762 {
8775 stack_pointer_rtx)),
8776 arg);
8777 }
8779 /* Generate an "pop" pattern for input ARG. */
8781 static rtx
8783 {
8788 arg,
8791 stack_pointer_rtx)));
8792 }
8794 /* Return >= 0 if there is an unused call-clobbered register available
8795 for the entire function. */
8797 static unsigned int
8799 {
8803 {
8805 /* Can't use the same register for both PIC and DRAP. */
8808 else
8813 }
8816 }
8818 /* Return TRUE if we need to save REGNO. */
8820 static bool
8822 {
8832 {
8835 {
8841 }
8842 }
8851 }
8853 /* Return number of saved general prupose registers. */
8855 static int
8857 {
8863 nregs ++;
8865 }
8867 /* Return number of saved SSE registrers. */
8869 static int
8871 {
8879 nregs ++;
8881 }
8883 /* Given FROM and TO register numbers, say whether this elimination is
8884 allowed. If stack alignment is needed, we can only replace argument
8885 pointer with hard frame pointer, or replace frame pointer with stack
8886 pointer. Otherwise, frame pointer elimination is automatically
8887 handled and all other eliminations are valid. */
8889 static bool
8891 {
8897 else
8899 }
8901 /* Return the offset between two registers, one to be eliminated, and the other
8902 its replacement, at the start of a routine. */
8904 HOST_WIDE_INT
8906 {
8915 else
8916 {
8924 }
8925 }
8927 /* In a dynamically-aligned function, we can't know the offset from
8928 stack pointer to frame pointer, so we must ensure that setjmp
8929 eliminates fp against the hard fp (%ebp) rather than trying to
8930 index from %esp up to the top of the frame across a gap that is
8931 of unknown (at compile-time) size. */
8932 static rtx
8934 {
8936 }
8938 /* When using -fsplit-stack, the allocation routines set a field in
8939 the TCB to the bottom of the stack plus this much space, measured
8940 in bytes. */
8942 #define SPLIT_STACK_AVAILABLE 256
8944 /* Fill structure ix86_frame about frame of currently computed function. */
8946 static void
8948 {
8950 HOST_WIDE_INT offset;
8953 HOST_WIDE_INT to_allocate;
8961 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8962 function prologues and leaf. */
8966 {
8971 }
8977 /* For SEH we have to limit the amount of code movement into the prologue.
8978 At present we do this via a BLOCKAGE, at which point there's very little
8979 scheduling that can be done, which means that there's very little point
8980 in doing anything except PUSHs. */
8984 /* During reload iteration the amount of registers saved can change.
8985 Recompute the value as needed. Do not recompute when amount of registers
8986 didn't change as reload does multiple calls to the function and does not
8987 expect the decision to change within single iteration. */
8990 {
8996 /* The fast prologue uses move instead of push to save registers. This
8997 is significantly longer, but also executes faster as modern hardware
8998 can execute the moves in parallel, but can't do that for push/pop.
9000 Be careful about choosing what prologue to emit: When function takes
9001 many instructions to execute we may use slow version as well as in
9002 case function is known to be outside hot spot (this is known with
9003 feedback only). Weight the size of function by number of registers
9004 to save as it is cheap to use one or two push instructions but very
9005 slow to use many of them. */
9009 || (flag_branch_probabilities
9012 else
9015 }
9017 frame->save_regs_using_mov
9019 /* If static stack checking is enabled and done with probes,
9020 the registers need to be saved before allocating the frame. */
9023 /* Skip return address. */
9026 /* Skip pushed static chain. */
9030 /* Skip saved base pointer. */
9035 /* The traditional frame pointer location is at the top of the frame. */
9038 /* Register save area */
9042 /* On SEH target, registers are pushed just before the frame pointer
9043 location. */
9047 /* Align and set SSE register save area. */
9049 {
9050 /* The only ABI that has saved SSE registers (Win64) also has a
9051 16-byte aligned default stack, and thus we don't need to be
9052 within the re-aligned local stack frame to save them. */
9056 }
9059 /* The re-aligned stack starts here. Values before this point are not
9060 directly comparable with values below this point. In order to make
9061 sure that no value happens to be the same before and after, force
9062 the alignment computation below to add a non-zero value. */
9066 /* Va-arg area */
9070 /* Align start of frame for local function. */
9079 /* Frame pointer points here. */
9084 /* Add outgoing arguments area. Can be skipped if we eliminated
9085 all the function calls as dead code.
9086 Skipping is however impossible when function calls alloca. Alloca
9087 expander assumes that last crtl->outgoing_args_size
9088 of stack frame are unused. */
9092 {
9095 }
9096 else
9099 /* Align stack boundary. Only needed if we're calling another function
9100 or using alloca. */
9105 /* We've reached end of stack frame. */
9108 /* Size prologue needs to allocate. */
9119 {
9125 }
9126 else
9130 /* The SEH frame pointer location is near the bottom of the frame.
9131 This is enforced by the fact that the difference between the
9132 stack pointer and the frame pointer is limited to 240 bytes in
9133 the unwind data structure. */
9135 {
9136 HOST_WIDE_INT diff;
9138 /* If we can leave the frame pointer where it is, do so. Also, returns
9139 the establisher frame for __builtin_frame_address (0). */
9144 {
9145 /* Ideally we'd determine what portion of the local stack frame
9146 (within the constraint of the lowest 240) is most heavily used.
9147 But without that complication, simply bias the frame pointer
9148 by 128 bytes so as to maximize the amount of the local stack
9149 frame that is addressable with 8-bit offsets. */
9151 }
9152 }
9153 }
9155 /* This is semi-inlined memory_address_length, but simplified
9156 since we know that we're always dealing with reg+offset, and
9157 to avoid having to create and discard all that rtl. */
9161 {
9165 {
9166 /* EBP and R13 cannot be encoded without an offset. */
9168 }
9172 /* ESP and R12 must be encoded with a SIB byte. */
9174 len++;
9177 }
9179 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9180 The valid base registers are taken from CFUN->MACHINE->FS. */
9182 static rtx
9184 {
9190 {
9191 /* Choose the base register most likely to allow the most scheduling
9192 opportunities. Generally FP is valid throughout the function,
9193 while DRAP must be reloaded within the epilogue. But choose either
9194 over the SP due to increased encoding size. */
9197 {
9200 }
9202 {
9205 }
9207 {
9210 }
9211 }
9212 else
9213 {
9214 HOST_WIDE_INT toffset;
9217 /* Choose the base register with the smallest address encoding.
9218 With a tie, choose FP > DRAP > SP. */
9220 {
9224 }
9226 {
9230 {
9234 }
9235 }
9237 {
9241 {
9245 }
9246 }
9247 }
9251 }
9253 /* Emit code to save registers in the prologue. */
9255 static void
9257 {
9259 rtx insn;
9263 {
9266 }
9267 }
9269 /* Emit a single register save at CFA - CFA_OFFSET. */
9271 static void
9273 HOST_WIDE_INT cfa_offset)
9274 {
9282 /* For SSE saves, we need to indicate the 128-bit alignment. */
9293 /* When saving registers into a re-aligned local stack frame, avoid
9294 any tricky guessing by dwarf2out. */
9296 {
9300 {
9301 /* A bit of a hack. We force the DRAP register to be saved in
9302 the re-aligned stack frame, which provides us with a copy
9303 of the CFA that will last past the prologue. Install it. */
9309 }
9310 else
9311 {
9312 /* The frame pointer is a stable reference within the
9313 aligned frame. Use it. */
9320 }
9321 }
9323 /* The memory may not be relative to the current CFA register,
9324 which means that we may need to generate a new pattern for
9325 use by the unwind info. */
9327 {
9332 }
9333 }
9335 /* Emit code to save registers using MOV insns.
9336 First register is stored at CFA - CFA_OFFSET. */
9337 static void
9339 {
9344 {
9347 }
9348 }
9350 /* Emit code to save SSE registers using MOV insns.
9351 First register is stored at CFA - CFA_OFFSET. */
9352 static void
9354 {
9359 {
9362 }
9363 }
9367 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9368 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9369 Don't add the note if the previously saved value will be left untouched
9370 within stack red-zone till return, as unwinders can find the same value
9371 in the register and on the stack. */
9373 static void
9375 {
9381 {
9384 }
9385 else
9386 queued_cfa_restores
9388 }
9390 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9392 static void
9394 {
9395 rtx last;
9399 ;
9404 }
9406 /* Expand prologue or epilogue stack adjustment.
9407 The pattern exist to put a dependency on all ebp-based memory accesses.
9408 STYLE should be negative if instructions should be marked as frame related,
9409 zero if %r11 register is live and cannot be freely used and positive
9410 otherwise. */
9412 static void
9415 {
9417 rtx insn;
9424 else
9425 {
9426 rtx tmp;
9427 /* r11 is used by indirect sibcall return as well, set before the
9428 epilogue and used after the epilogue. */
9431 else
9432 {
9436 }
9442 }
9449 {
9450 rtx r;
9460 }
9462 {
9465 {
9469 }
9470 }
9473 {
9478 {
9481 }
9483 {
9486 }
9487 else
9488 {
9489 /* Else there are two possibilities: SP itself, which we set
9490 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9491 taken care of this by hand along the eh_return path. */
9494 }
9498 }
9499 }
9501 /* Find an available register to be used as dynamic realign argument
9502 pointer regsiter. Such a register will be written in prologue and
9503 used in begin of body, so it must not be
9504 1. parameter passing register.
9505 2. GOT pointer.
9506 We reuse static-chain register if it is available. Otherwise, we
9507 use DI for i386 and R13 for x86-64. We chose R13 since it has
9508 shorter encoding.
9510 Return: the regno of chosen register. */
9512 static unsigned int
9514 {
9518 {
9519 /* Use R13 for nested function or function need static chain.
9520 Since function with tail call may use any caller-saved
9521 registers in epilogue, DRAP must not use caller-saved
9522 register in such case. */
9527 }
9528 else
9529 {
9530 /* Use DI for nested function or function need static chain.
9531 Since function with tail call may use any caller-saved
9532 registers in epilogue, DRAP must not use caller-saved
9533 register in such case. */
9537 /* Reuse static chain register if it isn't used for parameter
9538 passing. */
9540 {
9544 }
9546 }
9547 }
9549 /* Return minimum incoming stack alignment. */
9551 static unsigned int
9553 {
9556 /* Prefer the one specified at command line. */
9559 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9560 if -mstackrealign is used, it isn't used for sibcall check and
9561 estimated stack alignment is 128bit. */
9563 && !TARGET_64BIT
9564 && ix86_force_align_arg_pointer
9567 else
9570 /* Incoming stack alignment can be changed on individual functions
9571 via force_align_arg_pointer attribute. We use the smallest
9572 incoming stack boundary. */
9578 /* The incoming stack frame has to be aligned at least at
9579 parm_stack_boundary. */
9583 /* Stack at entrance of main is aligned by runtime. We use the
9584 smallest incoming stack boundary. */
9592 }
9594 /* Update incoming stack boundary and estimated stack alignment. */
9596 static void
9598 {
9599 ix86_incoming_stack_boundary
9602 /* x86_64 vararg needs 16byte stack alignment for register save
9603 area. */
9608 }
9610 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9611 needed or an rtx for DRAP otherwise. */
9613 static rtx
9615 {
9620 {
9621 /* Assign DRAP to vDRAP and returns vDRAP */
9623 rtx drap_vreg;
9624 rtx arg_ptr;
9637 {
9640 }
9642 }
9643 else
9645 }
9647 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9649 static rtx
9651 {
9653 }
9656 rtx reg;
9658 };
9660 /* Return a short-lived scratch register for use on function entry.
9661 In 32-bit mode, it is valid only after the registers are saved
9662 in the prologue. This register must be released by means of
9663 release_scratch_register_on_entry once it is dead. */
9665 static void
9667 {
9673 {
9674 /* We always use R11 in 64-bit mode. */
9676 }
9677 else
9678 {
9680 bool fastcall_p
9682 bool thiscall_p
9686 int drap_regno
9689 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9690 for the static chain register. */
9694 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9695 for the static chain register. */
9700 /* ecx is the static chain register. */
9702 && !static_chain_p
9707 /* esi is the static chain register. */
9713 else
9714 {
9717 }
9718 }
9722 {
9725 }
9726 }
9728 /* Release a scratch register obtained from the preceding function. */
9730 static void
9732 {
9734 {
9738 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9744 }
9745 }
9747 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9749 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9751 static void
9753 {
9754 /* We skip the probe for the first interval + a small dope of 4 words and
9755 probe that many bytes past the specified size to maintain a protection
9756 area at the botton of the stack. */
9760 /* See if we have a constant small number of probes to generate. If so,
9761 that's the easy case. The run-time loop is made up of 11 insns in the
9762 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9763 for n # of intervals. */
9765 {
9769 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9770 values of N from 1 until it exceeds SIZE. If only one probe is
9771 needed, this will not generate any code. Then adjust and probe
9772 to PROBE_INTERVAL + SIZE. */
9774 {
9776 {
9779 }
9780 else
9787 }
9791 else
9799 /* Adjust back to account for the additional first interval. */
9803 }
9805 /* Otherwise, do the same as above, but in a loop. Note that we must be
9806 extra careful with variables wrapping around because we might be at
9807 the very top (or the very bottom) of the address space and we have
9808 to be able to handle this case properly; in particular, we use an
9809 equality test for the loop condition. */
9810 else
9811 {
9812 HOST_WIDE_INT rounded_size;
9818 /* Step 1: round SIZE to the previous multiple of the interval. */
9823 /* Step 2: compute initial and final value of the loop counter. */
9825 /* SP = SP_0 + PROBE_INTERVAL. */
9830 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9834 stack_pointer_rtx)));
9837 /* Step 3: the loop
9839 while (SP != LAST_ADDR)
9840 {
9841 SP = SP + PROBE_INTERVAL
9842 probe at SP
9843 }
9845 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9846 values of N from 1 until it is equal to ROUNDED_SIZE. */
9851 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9852 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9855 {
9860 }
9862 /* Adjust back to account for the additional first interval. */
9868 }
9872 /* Even if the stack pointer isn't the CFA register, we need to correctly
9873 describe the adjustments made to it, in particular differentiate the
9874 frame-related ones from the frame-unrelated ones. */
9876 {
9889 }
9891 /* Make sure nothing is scheduled before we are done. */
9893 }
9895 /* Adjust the stack pointer up to REG while probing it. */
9899 {
9909 /* Jump to END_LAB if SP == LAST_ADDR. */
9917 /* SP = SP + PROBE_INTERVAL. */
9921 /* Probe at SP. */
9932 }
9934 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9935 inclusive. These are offsets from the current stack pointer. */
9937 static void
9939 {
9940 /* See if we have a constant small number of probes to generate. If so,
9941 that's the easy case. The run-time loop is made up of 7 insns in the
9942 generic case while the compile-time loop is made up of n insns for n #
9943 of intervals. */
9945 {
9946 HOST_WIDE_INT i;
9948 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9949 it exceeds SIZE. If only one probe is needed, this will not
9950 generate any code. Then probe at FIRST + SIZE. */
9957 }
9959 /* Otherwise, do the same as above, but in a loop. Note that we must be
9960 extra careful with variables wrapping around because we might be at
9961 the very top (or the very bottom) of the address space and we have
9962 to be able to handle this case properly; in particular, we use an
9963 equality test for the loop condition. */
9964 else
9965 {
9972 /* Step 1: round SIZE to the previous multiple of the interval. */
9977 /* Step 2: compute initial and final value of the loop counter. */
9979 /* TEST_OFFSET = FIRST. */
9982 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9986 /* Step 3: the loop
9988 while (TEST_ADDR != LAST_ADDR)
9989 {
9990 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9991 probe at TEST_ADDR
9992 }
9994 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
9995 until it is equal to ROUNDED_SIZE. */
10000 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10001 that SIZE is equal to ROUNDED_SIZE. */
10006 stack_pointer_rtx,
10011 }
10013 /* Make sure nothing is scheduled before we are done. */
10015 }
10017 /* Probe a range of stack addresses from REG to END, inclusive. These are
10018 offsets from the current stack pointer. */
10022 {
10032 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10040 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10044 /* Probe at TEST_ADDR. */
10057 }
10059 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10060 to be generated in correct form. */
10061 static void
10063 {
10064 /* Check if stack realign is really needed after reload, and
10065 stores result in cfun */
10066 unsigned int incoming_stack_boundary
10075 {
10076 /* After stack_realign_needed is finalized, we can't no longer
10077 change it. */
10080 }
10082 /* If the only reason for frame_pointer_needed is that we conservatively
10083 assumed stack realignment might be needed, but in the end nothing that
10084 needed the stack alignment had been spilled, clear frame_pointer_needed
10085 and say we don't need stack realignment. */
10088 && frame_pointer_needed
10090 && flag_omit_frame_pointer
10092 && !ix86_current_function_calls_tls_descriptor
10101 {
10103 basic_block bb;
10110 HARD_FRAME_POINTER_REGNUM);
10112 {
10113 rtx insn;
10117 set_up_by_prologue))
10118 {
10122 }
10123 }
10137 }
10141 }
10143 /* Expand the prologue into a bunch of separate insns. */
10145 void
10147 {
10152 HOST_WIDE_INT allocate;
10158 /* DRAP should not coexist with stack_realign_fp */
10163 /* Initialize CFA state for before the prologue. */
10167 /* Track SP offset to the CFA. We continue tracking this after we've
10168 swapped the CFA register away from SP. In the case of re-alignment
10169 this is fudged; we're interested to offsets within the local frame. */
10176 {
10177 /* We should have already generated an error for any use of
10178 ms_hook on a nested function. */
10181 /* Check if profiling is active and we shall use profiling before
10182 prologue variant. If so sorry. */
10187 /* In ix86_asm_output_function_label we emitted:
10188 8b ff movl.s %edi,%edi
10189 55 push %ebp
10190 8b ec movl.s %esp,%ebp
10192 This matches the hookable function prologue in Win32 API
10193 functions in Microsoft Windows XP Service Pack 2 and newer.
10194 Wine uses this to enable Windows apps to hook the Win32 API
10195 functions provided by Wine.
10197 What that means is that we've already set up the frame pointer. */
10201 {
10204 /* We've decided to use the frame pointer already set up.
10205 Describe this to the unwinder by pretending that both
10206 push and mov insns happen right here.
10208 Putting the unwind info here at the end of the ms_hook
10209 is done so that we can make absolutely certain we get
10210 the required byte sequence at the start of the function,
10211 rather than relying on an assembler that can produce
10212 the exact encoding required.
10214 However it does mean (in the unpatched case) that we have
10215 a 1 insn window where the asynchronous unwind info is
10216 incorrect. However, if we placed the unwind info at
10217 its correct location we would have incorrect unwind info
10218 in the patched case. Which is probably all moot since
10219 I don't expect Wine generates dwarf2 unwind info for the
10220 system libraries that use this feature. */
10226 stack_pointer_rtx);
10234 /* Note that gen_push incremented m->fs.cfa_offset, even
10235 though we didn't emit the push insn here. */
10239 }
10240 else
10241 {
10242 /* The frame pointer is not needed so pop %ebp again.
10243 This leaves us with a pristine state. */
10245 }
10246 }
10248 /* The first insn of a function that accepts its static chain on the
10249 stack is to push the register that would be filled in by a direct
10250 call. This insn will be skipped by the trampoline. */
10252 {
10256 /* We don't want to interpret this push insn as a register save,
10257 only as a stack adjustment. The real copy of the register as
10258 a save will be done later, if needed. */
10263 }
10265 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10266 of DRAP is needed and stack realignment is really needed after reload */
10268 {
10271 /* Only need to push parameter pointer reg if it is caller saved. */
10273 {
10274 /* Push arg pointer reg */
10277 }
10279 /* Grab the argument pointer. */
10286 /* Align the stack. */
10288 stack_pointer_rtx,
10292 /* Replicate the return address on the stack so that return
10293 address can be reached via (argp - 1) slot. This is needed
10294 to implement macro RETURN_ADDR_RTX and intrinsic function
10295 expand_builtin_return_addr etc. */
10301 /* For the purposes of frame and register save area addressing,
10302 we've started over with a new frame. */
10305 }
10311 {
10312 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10313 slower on all targets. Also sdb doesn't like it. */
10317 /* Push registers now, before setting the frame pointer
10318 on SEH target. */
10320 && TARGET_SEH
10322 {
10326 }
10329 {
10337 }
10338 }
10341 {
10342 /* If saving registers via PUSH, do so now. */
10344 {
10348 }
10350 /* When using red zone we may start register saving before allocating
10351 the stack frame saving one cycle of the prologue. However, avoid
10352 doing this if we have to probe the stack; at least on x86_64 the
10353 stack probe can turn into a call that clobbers a red zone location. */
10355 && (! TARGET_STACK_PROBE
10357 {
10360 }
10361 }
10364 {
10368 /* The computation of the size of the re-aligned stack frame means
10369 that we must allocate the size of the register save area before
10370 performing the actual alignment. Otherwise we cannot guarantee
10371 that there's enough storage above the realignment point. */
10378 /* Align the stack. */
10380 stack_pointer_rtx,
10383 /* For the purposes of register save area addressing, the stack
10384 pointer is no longer valid. As for the value of sp_offset,
10385 see ix86_compute_frame_layout, which we need to match in order
10386 to pass verification of stack_pointer_offset at the end. */
10389 }
10394 {
10395 /* We start to count from ARG_POINTER. */
10398 /* If it was realigned, take into account the fake frame. */
10400 {
10407 /* This over-estimates by 1 minimal-stack-alignment-unit but
10408 mitigates that by counting in the new return address slot. */
10409 current_function_dynamic_stack_size
10411 }
10414 }
10416 /* On SEH target with very large frame size, allocate an area to save
10417 SSE registers (as the very large allocation won't be described). */
10421 {
10422 HOST_WIDE_INT sse_size =
10427 /* No need to do stack checking as the area will be immediately
10428 written. */
10435 }
10437 /* The stack has already been decremented by the instruction calling us
10438 so probe if the size is non-negative to preserve the protection area. */
10440 {
10441 /* We expect the registers to be saved when probes are used. */
10445 {
10448 }
10449 else
10450 {
10458 else
10460 }
10461 }
10464 ;
10467 {
10471 }
10472 else
10473 {
10486 /* Note that SEH directives need to continue tracking the stack
10487 pointer even after the frame pointer has been set up. */
10489 {
10493 {
10497 }
10498 }
10501 {
10506 {
10510 }
10511 }
10516 /* Use the fact that AX still contains ALLOCATE. */
10518 ? gen_pro_epilogue_adjust_stack_di_sub
10525 {
10533 }
10537 {
10544 }
10546 {
10551 }
10552 }
10555 /* If we havn't already set up the frame pointer, do so now. */
10557 {
10569 }
10580 {
10587 }
10590 {
10592 {
10594 {
10604 label));
10608 }
10609 else
10611 }
10612 else
10613 {
10617 }
10618 }
10620 /* In the pic_reg_used case, make sure that the got load isn't deleted
10621 when mcount needs it. Blockage to avoid call movement across mcount
10622 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10623 note. */
10628 {
10629 /* vDRAP is setup but after reload it turns out stack realign
10630 isn't necessary, here we will emit prologue to setup DRAP
10631 without stack realign adjustment */
10634 }
10636 /* Prevent instructions from being scheduled into register save push
10637 sequence when access to the redzone area is done through frame pointer.
10638 The offset between the frame pointer and the stack pointer is calculated
10639 relative to the value of the stack pointer at the end of the function
10640 prologue, and moving instructions that access redzone area via frame
10641 pointer inside push sequence violates this assumption. */
10645 /* Emit cld instruction if stringops are used in the function. */
10649 /* SEH requires that the prologue end within 256 bytes of the start of
10650 the function. Prevent instruction schedules that would extend that.
10651 Further, prevent alloca modifications to the stack pointer from being
10652 combined with prologue modifications. */
10655 }
10657 /* Emit code to restore REG using a POP insn. */
10659 static void
10661 {
10670 {
10671 /* Previously we'd represented the CFA as an expression
10672 like *(%ebp - 8). We've just popped that value from
10673 the stack, which means we need to reset the CFA to
10674 the drap register. This will remain until we restore
10675 the stack pointer. */
10679 /* This means that the DRAP register is valid for addressing too. */
10682 }
10685 {
10692 }
10694 /* When the frame pointer is the CFA, and we pop it, we are
10695 swapping back to the stack pointer as the CFA. This happens
10696 for stack frames that don't allocate other data, so we assume
10697 the stack pointer is now pointing at the return address, i.e.
10698 the function entry state, which makes the offset be 1 word. */
10700 {
10703 {
10711 }
10712 }
10713 }
10715 /* Emit code to restore saved registers using POP insns. */
10717 static void
10719 {
10725 }
10727 /* Emit code and notes for the LEAVE instruction. */
10729 static void
10731 {
10743 {
10751 }
10754 }
10756 /* Emit code to restore saved registers using MOV insns.
10757 First register is restored from CFA - CFA_OFFSET. */
10758 static void
10761 {
10767 {
10776 {
10777 /* Previously we'd represented the CFA as an expression
10778 like *(%ebp - 8). We've just popped that value from
10779 the stack, which means we need to reset the CFA to
10780 the drap register. This will remain until we restore
10781 the stack pointer. */
10785 /* This means that the DRAP register is valid for addressing. */
10787 }
10788 else
10792 }
10793 }
10795 /* Emit code to restore saved registers using MOV insns.
10796 First register is restored from CFA - CFA_OFFSET. */
10797 static void
10800 {
10805 {
10807 rtx mem;
10817 }
10818 }
10820 /* Restore function stack, frame, and registers. */
10822 void
10824 {
10840 /* The FP must be valid if the frame pointer is present. */
10845 /* We must have *some* valid pointer to the stack frame. */
10848 /* The DRAP is never valid at this point. */
10851 /* See the comment about red zone and frame
10852 pointer usage in ix86_expand_prologue. */
10859 /* Determine the CFA offset of the end of the red-zone. */
10862 {
10863 /* The red-zone begins below the return address. */
10866 /* When the register save area is in the aligned portion of
10867 the stack, determine the maximum runtime displacement that
10868 matches up with the aligned frame. */
10872 }
10874 /* Special care must be taken for the normal return case of a function
10875 using eh_return: the eax and edx registers are marked as saved, but
10876 not restored along this path. Adjust the save location to match. */
10880 /* EH_RETURN requires the use of moves to function properly. */
10883 /* SEH requires the use of pops to identify the epilogue. */
10886 /* If we're only restoring one register and sp is not valid then
10887 using a move instruction to restore the register since it's
10888 less work than reloading sp and popping the register. */
10901 && TARGET_USE_LEAVE
10905 else
10909 {
10910 /* Ensure that the entire register save area is addressable via
10911 the stack pointer, if we will restore via sp. */
10916 {
10920 style,
10922 }
10923 }
10925 /* If there are any SSE registers to restore, then we have to do it
10926 via moves, since there's obviously no pop for SSE regs. */
10932 {
10933 rtx t;
10938 /* eh_return epilogues need %ecx added to the stack pointer. */
10940 {
10943 /* Stack align doesn't work with eh_return. */
10945 /* Neither does regparm nested functions. */
10949 {
10957 /* Note that we use SA as a temporary CFA, as the return
10958 address is at the proper place relative to it. We
10959 pretend this happens at the FP restore insn because
10960 prior to this insn the FP would be stored at the wrong
10961 offset relative to SA, and after this insn we have no
10962 other reasonable register to use for the CFA. We don't
10963 bother resetting the CFA to the SP for the duration of
10964 the return insn. */
10977 }
10978 else
10979 {
10987 {
10991 UNITS_PER_WORD));
10993 }
10994 }
10997 }
10998 }
10999 else
11000 {
11001 /* SEH requires that the function end with (1) a stack adjustment
11002 if necessary, (2) a sequence of pops, and (3) a return or
11003 jump instruction. Prevent insns from the function body from
11004 being scheduled into this sequence. */
11006 {
11007 /* Prevent a catch region from being adjacent to the standard
11008 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11009 several other flags that would be interesting to test are
11010 not yet set up. */
11013 else
11015 }
11017 /* First step is to deallocate the stack frame so that we can
11018 pop the registers. Also do it on SEH target for very large
11019 frame as the emitted instructions aren't allowed by the ABI in
11020 epilogues. */
11022 || (TARGET_SEH
11025 {
11030 }
11032 {
11036 style,
11038 }
11041 }
11043 /* If we used a stack pointer and haven't already got rid of it,
11044 then do so now. */
11046 {
11047 /* If the stack pointer is valid and pointing at the frame
11048 pointer store address, then we only need a pop. */
11051 /* Leave results in shorter dependency chains on CPUs that are
11052 able to grok it fast. */
11057 else
11058 {
11060 hard_frame_pointer_rtx,
11063 }
11064 }
11067 {
11069 rtx insn;
11095 }
11097 /* At this point the stack pointer must be valid, and we must have
11098 restored all of the registers. We may not have deallocated the
11099 entire stack frame. We've delayed this until now because it may
11100 be possible to merge the local stack deallocation with the
11101 deallocation forced by ix86_static_chain_on_stack. */
11106 {
11110 }
11111 else
11114 /* Sibcall epilogues don't want a return instruction. */
11116 {
11119 }
11122 {
11125 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11126 address, do explicit add, and jump indirectly to the caller. */
11129 {
11131 rtx insn;
11133 /* There is no "pascal" calling convention in any 64bit ABI. */
11149 }
11150 else
11152 }
11153 else
11156 /* Restore the state back to the state from the prologue,
11157 so that it's correct for the next epilogue. */
11159 }
11161 /* Reset from the function's potential modifications. */
11163 static void
11165 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11166 {
11169 #if TARGET_MACHO
11170 /* Mach-O doesn't support labels at the end of objects, so if
11171 it looks like we might want one, insert a NOP. */
11172 {
11178 {
11179 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11180 notes only, instead set their CODE_LABEL_NUMBER to -1,
11181 otherwise there would be code generation differences
11182 in between -g and -g0. */
11186 }
11196 }
11197 #endif
11199 }
11201 /* Return a scratch register to use in the split stack prologue. The
11202 split stack prologue is used for -fsplit-stack. It is the first
11203 instructions in the function, even before the regular prologue.
11204 The scratch register can be any caller-saved register which is not
11205 used for parameters or for the static chain. */
11207 static unsigned int
11209 {
11212 else
11213 {
11226 {
11228 {
11232 }
11234 }
11236 {
11240 }
11242 {
11245 else
11246 {
11248 {
11252 }
11254 }
11255 }
11256 else
11257 {
11258 /* FIXME: We could make this work by pushing a register
11259 around the addition and comparison. */
11262 }
11263 }
11264 }
11266 /* A SYMBOL_REF for the function which allocates new stackspace for
11267 -fsplit-stack. */
11271 /* A SYMBOL_REF for the more stack function when using the large
11272 model. */
11276 /* Handle -fsplit-stack. These are the first instructions in the
11277 function, even before the regular prologue. */
11279 void
11281 {
11283 HOST_WIDE_INT allocate;
11288 rtx fn;
11296 /* This is the label we will branch to if we have enough stack
11297 space. We expect the basic block reordering pass to reverse this
11298 branch if optimizing, so that we branch in the unlikely case. */
11301 /* We need to compare the stack pointer minus the frame size with
11302 the stack boundary in the TCB. The stack boundary always gives
11303 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11304 can compare directly. Otherwise we need to do an addition. */
11307 UNSPEC_STACK_CHECK);
11312 else
11313 {
11315 rtx offset;
11317 /* We need a scratch register to hold the stack pointer minus
11318 the required frame size. Since this is the very start of the
11319 function, the scratch register can be any caller-saved
11320 register which is not used for parameters. */
11327 {
11328 /* We don't use ix86_gen_add3 in this case because it will
11329 want to split to lea, but when not optimizing the insn
11330 will not be split after this point. */
11333 offset)));
11334 }
11335 else
11336 {
11339 stack_pointer_rtx));
11340 }
11342 }
11348 /* Mark the jump as very likely to be taken. */
11356 /* Get more stack space. We pass in the desired stack space and the
11357 size of the arguments to copy to the new stack. In 32-bit mode
11358 we push the parameters; __morestack will return on a new stack
11359 anyhow. In 64-bit mode we pass the parameters in r10 and
11360 r11. */
11365 {
11371 /* If this function uses a static chain, it will be in %r10.
11372 Preserve it across the call to __morestack. */
11374 {
11375 rtx rax;
11380 }
11383 {
11384 HOST_WIDE_INT argval;
11387 /* When using the large model we need to load the address
11388 into a register, and we've run out of registers. So we
11389 switch to a different calling convention, and we call a
11390 different function: __morestack_large. We pass the
11391 argument size in the upper 32 bits of r10 and pass the
11392 frame size in the lower 32 bits. */
11397 split_stack_fn_large =
11401 {
11411 UNSPEC_GOT);
11417 }
11418 else
11425 }
11426 else
11427 {
11431 }
11434 }
11435 else
11436 {
11439 }
11445 /* In order to make call/return prediction work right, we now need
11446 to execute a return instruction. See
11447 libgcc/config/i386/morestack.S for the details on how this works.
11449 For flow purposes gcc must not see this as a return
11450 instruction--we need control flow to continue at the subsequent
11451 label. Therefore, we use an unspec. */
11455 /* If we are in 64-bit mode and this function uses a static chain,
11456 we saved %r10 in %rax before calling _morestack. */
11461 /* If this function calls va_start, we need to store a pointer to
11462 the arguments on the old stack, because they may not have been
11463 all copied to the new stack. At this point the old stack can be
11464 found at the frame pointer value used by __morestack, because
11465 __morestack has set that up before calling back to us. Here we
11466 store that pointer in a scratch register, and in
11467 ix86_expand_prologue we store the scratch register in a stack
11468 slot. */
11470 {
11472 rtx frame_reg;
11479 /* 64-bit:
11480 fp -> old fp value
11481 return address within this function
11482 return address of caller of this function
11483 stack arguments
11484 So we add three words to get to the stack arguments.
11486 32-bit:
11487 fp -> old fp value
11488 return address within this function
11489 first argument to __morestack
11490 second argument to __morestack
11491 return address of caller of this function
11492 stack arguments
11493 So we add five words to get to the stack arguments.
11494 */
11505 }
11510 /* If this function calls va_start, we now have to set the scratch
11511 register for the case where we do not call __morestack. In this
11512 case we need to set it based on the stack pointer. */
11514 {
11521 }
11522 }
11524 /* We may have to tell the dataflow pass that the split stack prologue
11525 is initializing a scratch register. */
11527 static void
11529 {
11531 {
11534 }
11535 }
11536 \f
11537 /* Determine if op is suitable SUBREG RTX for address. */
11539 static bool
11541 {
11552 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11553 failures when the register is one word out of a two word structure. */
11557 /* Allow only SUBREGs of non-eliminable hard registers. */
11559 }
11561 /* Extract the parts of an RTL expression that is a valid memory address
11562 for an instruction. Return 0 if the structure of the address is
11563 grossly off. Return -1 if the address contains ASHIFT, so it is not
11564 strictly valid, but still used for computing length of lea instruction. */
11566 int
11568 {
11573 rtx tmp;
11577 /* Allow zero-extended SImode addresses,
11578 they will be emitted with addr32 prefix. */
11580 {
11583 {
11587 }
11590 {
11597 }
11598 }
11600 /* Allow SImode subregs of DImode addresses,
11601 they will be emitted with addr32 prefix. */
11603 {
11606 {
11610 }
11611 }
11616 {
11619 else
11621 }
11623 {
11628 do
11629 {
11634 }
11641 {
11644 {
11669 /* FALLTHRU */
11673 && TARGET_TLS_DIRECT_SEG_REFS
11676 else
11683 /* FALLTHRU */
11690 else
11705 }
11706 }
11707 }
11709 {
11712 }
11714 {
11715 /* We're called for lea too, which implements ashift on occasion. */
11725 }
11727 {
11731 /* Constant addresses are sign extended to 64bit, we have to
11732 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11738 }
11739 else
11743 {
11745 ;
11748 ;
11749 else
11751 }
11753 /* Address override works only on the (%reg) part of %fs:(%reg). */
11759 /* Extract the integral value of scale. */
11761 {
11765 }
11770 /* Avoid useless 0 displacement. */
11774 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11779 {
11780 rtx tmp;
11783 }
11785 /* Special case: %ebp cannot be encoded as a base without a displacement.
11786 Similarly %r13. */
11788 && base_reg
11797 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11798 Avoid this by transforming to [%esi+0].
11799 Reload calls address legitimization without cfun defined, so we need
11800 to test cfun for being non-NULL. */
11806 /* Special case: encode reg+reg instead of reg*2. */
11810 /* Special case: scaling cannot be encoded without base or displacement. */
11821 }
11822 \f
11823 /* Return cost of the memory address x.
11824 For i386, it is better to use a complex address than let gcc copy
11825 the address into a reg and make a new pseudo. But not if the address
11826 requires to two regs - that would mean more pseudos with longer
11827 lifetimes. */
11828 static int
11830 addr_space_t as ATTRIBUTE_UNUSED,
11832 {
11844 /* Attempt to minimize number of registers in the address. */
11850 cost++;
11857 cost++;
11859 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11860 since it's predecode logic can't detect the length of instructions
11861 and it degenerates to vector decoded. Increase cost of such
11862 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11863 to split such addresses or even refuse such addresses at all.
11865 Following addressing modes are affected:
11866 [base+scale*index]
11867 [scale*index+disp]
11868 [base+index]
11870 The first and last case may be avoidable by explicitly coding the zero in
11871 memory address, but I don't have AMD-K6 machine handy to check this
11872 theory. */
11881 }
11882 \f
11883 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11884 this is used for to form addresses to local data when -fPIC is in
11885 use. */
11887 static bool
11889 {
11892 }
11894 /* Determine if a given RTX is a valid constant. We already know this
11895 satisfies CONSTANT_P. */
11897 static bool
11899 {
11901 {
11906 {
11910 }
11915 /* Only some unspecs are valid as "constants". */
11918 {
11934 }
11936 /* We must have drilled down to a symbol. */
11941 /* FALLTHRU */
11944 /* TLS symbols are never valid. */
11948 /* DLLIMPORT symbols are never valid. */
11953 #if TARGET_MACHO
11954 /* mdynamic-no-pic */
11957 #endif
11973 }
11975 /* Otherwise we handle everything else in the move patterns. */
11977 }
11979 /* Determine if it's legal to put X into the constant pool. This
11980 is not possible for the address of thread-local symbols, which
11981 is checked above. */
11983 static bool
11985 {
11986 /* We can always put integral constants and vectors in memory. */
11988 {
11996 }
11998 }
12001 /* Nonzero if the constant value X is a legitimate general operand
12002 when generating PIC code. It is given that flag_pic is on and
12003 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12005 bool
12007 {
12008 rtx inner;
12011 {
12018 /* Only some unspecs are valid as "constants". */
12021 {
12034 }
12035 /* FALLTHRU */
12043 }
12044 }
12046 /* Determine if a given CONST RTX is a valid memory displacement
12047 in PIC mode. */
12049 bool
12051 {
12054 /* In 64bit mode we can allow direct addresses of symbols and labels
12055 when they are not dynamic symbols. */
12057 {
12061 {
12085 /* FALLTHRU */
12088 /* TLS references should always be enclosed in UNSPEC. */
12098 }
12099 }
12105 {
12106 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12107 of GOT tables. We should not need these anyway. */
12119 }
12123 {
12128 }
12137 {
12141 /* We need to check for both symbols and labels because VxWorks loads
12142 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12143 details. */
12147 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12148 While ABI specify also 32bit relocation but we don't produce it in
12149 small PIC model at all. */
12171 }
12174 }
12176 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12177 replace the input X, or the original X if no replacement is called for.
12178 The output parameter *WIN is 1 if the calling macro should goto WIN,
12179 0 if it should not. */
12181 bool
12186 {
12187 /* Reload can generate:
12189 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12190 (reg:DI 97))
12191 (reg:DI 2 cx))
12193 This RTX is rejected from ix86_legitimate_address_p due to
12194 non-strictness of base register 97. Following this rejection,
12195 reload pushes all three components into separate registers,
12196 creating invalid memory address RTX.
12198 Following code reloads only the invalid part of the
12199 memory address RTX. */
12205 {
12211 {
12216 }
12220 {
12225 }
12229 }
12232 }
12234 /* Recognizes RTL expressions that are valid memory addresses for an
12235 instruction. The MODE argument is the machine mode for the MEM
12236 expression that wants to use this address.
12238 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12239 convert common non-canonical forms to canonical form so that they will
12240 be recognized. */
12242 static bool
12245 {
12248 HOST_WIDE_INT scale;
12251 /* Decomposition failed. */
12259 /* Validate base register. */
12261 {
12262 rtx reg;
12268 else
12269 /* Base is not a register. */
12277 /* Base is not valid. */
12279 }
12281 /* Validate index register. */
12283 {
12284 rtx reg;
12290 else
12291 /* Index is not a register. */
12299 /* Index is not valid. */
12301 }
12303 /* Index and base should have the same mode. */
12308 /* Validate scale factor. */
12310 {
12312 /* Scale without index. */
12316 /* Scale is not a valid multiplier. */
12318 }
12320 /* Validate displacement. */
12322 {
12327 {
12328 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12329 used. While ABI specify also 32bit relocations, we don't produce
12330 them at all and use IP relative instead. */
12337 /* 64bit address unspec. */
12357 /* Invalid address unspec. */
12359 }
12362 && (flag_pic
12363 || (TARGET_MACHO
12364 #if TARGET_MACHO
12365 && MACHOPIC_INDIRECT
12367 #endif
12368 )))
12369 {
12371 is_legitimate_pic:
12373 {
12374 /* foo@dtpoff(%rX) is ok. */
12381 /* Non-constant pic memory reference. */
12383 }
12386 /* Displacement is an invalid pic construct. */
12388 #if TARGET_MACHO
12391 /* displacment must be referenced via non_lazy_pointer */
12393 #endif
12395 /* This code used to verify that a symbolic pic displacement
12396 includes the pic_offset_table_rtx register.
12398 While this is good idea, unfortunately these constructs may
12399 be created by "adds using lea" optimization for incorrect
12400 code like:
12402 int a;
12403 int foo(int i)
12404 {
12405 return *(&a+i);
12406 }
12408 This code is nonsensical, but results in addressing
12409 GOT table with pic_offset_table_rtx base. We can't
12410 just refuse it easily, since it gets matched by
12411 "addsi3" pattern, that later gets split to lea in the
12412 case output register differs from input. While this
12413 can be handled by separate addsi pattern for this case
12414 that never results in lea, this seems to be easier and
12415 correct fix for crash to disable this test. */
12416 }
12423 /* Displacement is not constant. */
12427 /* Displacement is out of range. */
12429 }
12431 /* Everything looks valid. */
12433 }
12435 /* Determine if a given RTX is a valid constant address. */
12437 bool
12439 {
12441 }
12442 \f
12443 /* Return a unique alias set for the GOT. */
12445 static alias_set_type
12447 {
12452 }
12454 /* Return a legitimate reference for ORIG (an address) using the
12455 register REG. If REG is 0, a new pseudo is generated.
12457 There are two types of references that must be handled:
12459 1. Global data references must load the address from the GOT, via
12460 the PIC reg. An insn is emitted to do this load, and the reg is
12461 returned.
12463 2. Static data references, constant pool addresses, and code labels
12464 compute the address as an offset from the GOT, whose base is in
12465 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12466 differentiate them from global data objects. The returned
12467 address is the PIC reg + an unspec constant.
12469 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12470 reg also appears in the address. */
12472 static rtx
12474 {
12478 #if TARGET_MACHO
12480 {
12483 /* Use the generic Mach-O PIC machinery. */
12485 }
12486 #endif
12493 {
12494 rtx tmpreg;
12495 /* This symbol may be referenced via a displacement from the PIC
12496 base address (@GOTOFF). */
12503 {
12505 UNSPEC_GOTOFF);
12507 }
12508 else
12513 else
12518 {
12522 }
12524 }
12526 {
12527 /* This symbol may be referenced via a displacement from the PIC
12528 base address (@GOTOFF). */
12535 {
12537 UNSPEC_GOTOFF);
12539 }
12540 else
12546 {
12549 }
12550 }
12552 /* We can't use @GOTOFF for text labels on VxWorks;
12553 see gotoff_operand. */
12555 {
12557 {
12563 {
12566 }
12567 }
12569 /* For x64 PE-COFF there is no GOT table. So we use address
12570 directly. */
12572 {
12580 }
12582 {
12590 /* Use directly gen_movsi, otherwise the address is loaded
12591 into register for CSE. We don't want to CSE this addresses,
12592 instead we CSE addresses from the GOT table, so skip this. */
12595 }
12596 else
12597 {
12598 /* This symbol must be referenced via a load from the
12599 Global Offset Table (@GOT). */
12615 }
12616 }
12617 else
12618 {
12621 {
12623 {
12626 }
12627 else
12629 }
12631 {
12634 /* We must match stuff we generate before. Assume the only
12635 unspecs that can get here are ours. Not that we could do
12636 anything with them anyway.... */
12642 }
12644 {
12647 /* Check first to see if this is a constant offset from a @GOTOFF
12648 symbol reference. */
12651 {
12653 {
12657 UNSPEC_GOTOFF);
12663 {
12666 }
12667 }
12668 else
12669 {
12672 {
12676 }
12677 }
12678 }
12679 else
12680 {
12683 new_rtx
12687 {
12690 {
12693 new_rtx
12695 }
12696 else
12698 }
12699 else
12700 {
12703 {
12706 }
12708 }
12709 }
12710 }
12711 }
12713 }
12714 \f
12715 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12717 static rtx
12719 {
12723 {
12728 }
12734 }
12736 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12740 static rtx
12742 {
12744 {
12750 }
12753 }
12755 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12759 rtx
12761 {
12763 {
12764 ix86_tls_module_base_symbol
12769 }
12772 }
12774 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12775 false if we expect this to be used for a memory address and true if
12776 we expect to load the address into a register. */
12778 static rtx
12780 {
12787 {
12792 {
12795 else
12796 {
12799 }
12800 }
12803 {
12806 else
12816 }
12817 else
12818 {
12822 {
12824 rtx insns;
12827 emit_call_insn
12837 }
12838 else
12840 }
12847 {
12850 else
12851 {
12854 }
12855 }
12858 {
12863 else
12869 }
12870 else
12871 {
12875 {
12880 emit_call_insn
12885 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12886 share the LD_BASE result with other LD model accesses. */
12888 UNSPEC_TLS_LD_BASE);
12892 }
12893 else
12895 }
12903 {
12910 }
12915 {
12917 {
12918 /* The Sun linker took the AMD64 TLS spec literally
12919 and can only handle %rax as destination of the
12920 initial executable code sequence. */
12925 }
12927 /* Generate DImode references to avoid %fs:(%reg32)
12928 problems and linker IE->LE relaxation bug. */
12932 }
12934 {
12939 }
12941 {
12945 }
12946 else
12947 {
12950 }
12960 {
12965 }
12966 else
12967 {
12971 }
12981 {
12985 }
12986 else
12987 {
12991 }
12996 }
12999 }
13001 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13002 to symbol DECL. */
13005 htab_t dllimport_map;
13007 static tree
13009 {
13016 tree to;
13017 rtx rtl;
13061 }
13063 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13064 true if we require the result be a register. */
13066 static rtx
13068 {
13069 tree imp_decl;
13070 rtx x;
13079 }
13081 /* Try machine-dependent ways of modifying an illegitimate address
13082 to be legitimate. If we find one, return the new, valid address.
13083 This macro is used in only one place: `memory_address' in explow.c.
13085 OLDX is the address as it was before break_out_memory_refs was called.
13086 In some cases it is useful to look at this to decide what needs to be done.
13088 It is always safe for this macro to do nothing. It exists to recognize
13089 opportunities to optimize the output.
13091 For the 80386, we handle X+REG by loading X into a register R and
13092 using R+REG. R will go in a general reg and indexing will be used.
13093 However, if REG is a broken-out memory address or multiplication,
13094 nothing needs to be done because REG can certainly go in a general reg.
13096 When -fpic is used, special handling is needed for symbolic references.
13097 See comments by legitimize_pic_address in i386.c for details. */
13099 static rtx
13102 {
13113 {
13117 }
13120 {
13127 {
13130 }
13131 }
13136 #if TARGET_MACHO
13139 #endif
13141 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13145 {
13150 }
13153 {
13154 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13159 {
13165 }
13170 {
13176 }
13178 /* Put multiply first if it isn't already. */
13180 {
13185 }
13187 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13188 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13189 created by virtual register instantiation, register elimination, and
13190 similar optimizations. */
13192 {
13198 }
13200 /* Canonicalize
13201 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13202 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13207 {
13208 rtx constant;
13212 {
13215 }
13217 {
13220 }
13221 else
13225 {
13232 }
13233 }
13239 {
13242 }
13245 {
13248 }
13256 {
13259 }
13265 {
13269 {
13272 }
13276 }
13279 {
13283 {
13286 }
13290 }
13291 }
13294 }
13295 \f
13296 /* Print an integer constant expression in assembler syntax. Addition
13297 and subtraction are the only arithmetic that may appear in these
13298 expressions. FILE is the stdio stream to write to, X is the rtx, and
13299 CODE is the operand print code from the output string. */
13301 static void
13303 {
13307 {
13316 else
13317 {
13320 /* Mark the decl as referenced so that cgraph will
13321 output the function. */
13325 #if TARGET_MACHO
13329 #endif
13331 }
13339 /* FALLTHRU */
13350 /* This used to output parentheses around the expression,
13351 but that does not work on the 386 (either ATT or BSD assembler). */
13357 {
13358 /* We can use %d if the number is <32 bits and positive. */
13363 else
13365 }
13366 else
13367 /* We can't handle floating point constants;
13368 TARGET_PRINT_OPERAND must handle them. */
13373 /* Some assemblers need integer constants to appear first. */
13375 {
13379 }
13380 else
13381 {
13386 }
13401 {
13405 }
13410 {
13429 /* FIXME: This might be @TPOFF in Sun ld too. */
13438 else
13448 else
13454 #if TARGET_MACHO
13459 #endif
13463 }
13468 }
13469 }
13471 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13472 We need to emit DTP-relative relocations. */
13474 static void ATTRIBUTE_UNUSED
13476 {
13481 {
13489 }
13490 }
13492 /* Return true if X is a representation of the PIC register. This copes
13493 with calls from ix86_find_base_term, where the register might have
13494 been replaced by a cselib value. */
13496 static bool
13498 {
13502 else
13504 }
13506 /* Helper function for ix86_delegitimize_address.
13507 Attempt to delegitimize TLS local-exec accesses. */
13509 static rtx
13511 {
13536 {
13541 }
13547 }
13549 /* In the name of slightly smaller debug output, and to cater to
13550 general assembler lossage, recognize PIC+GOTOFF and turn it back
13551 into a direct symbol reference.
13553 On Darwin, this is necessary to avoid a crash, because Darwin
13554 has a different PIC label for each routine but the DWARF debugging
13555 information is not associated with any particular routine, so it's
13556 necessary to remove references to the PIC label from RTL stored by
13557 the DWARF output code. */
13559 static rtx
13561 {
13563 /* addend is NULL or some rtx if x is something+GOTOFF where
13564 something doesn't include the PIC register. */
13566 /* reg_addend is NULL or a multiple of some register. */
13568 /* const_addend is NULL or a const_int. */
13570 /* This is the result, or NULL. */
13579 {
13586 {
13592 }
13601 {
13606 }
13608 }
13615 /* %ebx + GOT/GOTOFF */
13616 ;
13618 {
13619 /* %ebx + %reg * scale + GOT/GOTOFF */
13625 else
13626 {
13629 }
13630 }
13631 else
13637 {
13640 }
13659 {
13660 /* If the rest of original X doesn't involve the PIC register, add
13661 addend and subtract pic_offset_table_rtx. This can happen e.g.
13662 for code like:
13663 leal (%ebx, %ecx, 4), %ecx
13664 ...
13665 movl foo@GOTOFF(%ecx), %edx
13666 in which case we return (%ecx - %ebx) + foo. */
13669 pic_offset_table_rtx),
13670 result);
13671 else
13673 }
13675 {
13679 }
13681 }
13683 /* If X is a machine specific address (i.e. a symbol or label being
13684 referenced as a displacement from the GOT implemented using an
13685 UNSPEC), then return the base term. Otherwise return X. */
13687 rtx
13689 {
13690 rtx term;
13693 {
13707 }
13710 }
13711 \f
13712 static void
13715 {
13719 {
13722 }
13727 {
13730 {
13749 }
13753 {
13772 }
13779 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13780 Those same assemblers have the same but opposite lossage on cmov. */
13785 else
13790 {
13803 }
13811 {
13824 }
13827 /* ??? As above. */
13836 /* ??? As above. */
13841 else
13852 }
13854 }
13856 /* Print the name of register X to FILE based on its machine mode and number.
13857 If CODE is 'w', pretend the mode is HImode.
13858 If CODE is 'b', pretend the mode is QImode.
13859 If CODE is 'k', pretend the mode is SImode.
13860 If CODE is 'q', pretend the mode is DImode.
13861 If CODE is 'x', pretend the mode is V4SFmode.
13862 If CODE is 't', pretend the mode is V8SFmode.
13863 If CODE is 'h', pretend the reg is the 'high' byte register.
13864 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13865 If CODE is 'd', duplicate the operand for AVX instruction.
13866 */
13868 void
13870 {
13879 {
13883 }
13908 else
13911 /* Irritatingly, AMD extended registers use different naming convention
13912 from the normal registers: "r%d[bwd]" */
13914 {
13919 {
13933 /* no suffix */
13938 }
13940 }
13944 {
13947 {
13950 }
13951 /* FALLTHRU */
13957 /* FALLTHRU */
13960 normal:
13975 {
13980 }
13984 }
13988 {
13991 else
13993 }
13994 }
13996 /* Locate some local-dynamic symbol still in use by this function
13997 so that we can print its name in some tls_local_dynamic_base
13998 pattern. */
14000 static int
14002 {
14007 {
14010 }
14013 }
14017 {
14018 rtx insn;
14029 }
14031 /* Meaning of CODE:
14032 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14033 C -- print opcode suffix for set/cmov insn.
14034 c -- like C, but print reversed condition
14035 F,f -- likewise, but for floating-point.
14036 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14037 otherwise nothing
14038 R -- print the prefix for register names.
14039 z -- print the opcode suffix for the size of the current operand.
14040 Z -- likewise, with special suffixes for x87 instructions.
14041 * -- print a star (in certain assembler syntax)
14042 A -- print an absolute memory reference.
14043 E -- print address with DImode register names if TARGET_64BIT.
14044 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14045 s -- print a shift double count, followed by the assemblers argument
14046 delimiter.
14047 b -- print the QImode name of the register for the indicated operand.
14048 %b0 would print %al if operands[0] is reg 0.
14049 w -- likewise, print the HImode name of the register.
14050 k -- likewise, print the SImode name of the register.
14051 q -- likewise, print the DImode name of the register.
14052 x -- likewise, print the V4SFmode name of the register.
14053 t -- likewise, print the V8SFmode name of the register.
14054 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14055 y -- print "st(0)" instead of "st" as a register.
14056 d -- print duplicated register operand for AVX instruction.
14057 D -- print condition for SSE cmp instruction.
14058 P -- if PIC, print an @PLT suffix.
14059 p -- print raw symbol name.
14060 X -- don't print any sort of PIC '@' suffix for a symbol.
14061 & -- print some in-use local-dynamic symbol name.
14062 H -- print a memory address offset by 8; used for sse high-parts
14063 Y -- print condition for XOP pcom* instruction.
14064 + -- print a branch hint as 'cs' or 'ds' prefix
14065 ; -- print a semicolon (after prefixes due to bug in older gas).
14066 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14067 @ -- print a segment register of thread base pointer load
14068 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14069 */
14071 void
14073 {
14075 {
14077 {
14080 {
14086 /* Intel syntax. For absolute addresses, registers should not
14087 be surrounded by braces. */
14089 {
14094 }
14099 }
14105 /* Wrap address in an UNSPEC to declare special handling. */
14143 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14148 {
14162 output_operand_lossage
14165 }
14168 #endif
14173 {
14174 /* Opcodes don't get size suffixes if using Intel opcodes. */
14179 {
14197 output_operand_lossage
14200 }
14201 }
14204 warning
14206 /* FALLTHRU */
14209 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14214 {
14216 {
14218 #ifdef HAVE_AS_IX86_FILDS
14220 #endif
14228 #ifdef HAVE_AS_IX86_FILDQ
14230 #else
14232 #endif
14237 }
14238 }
14240 {
14241 /* 387 opcodes don't get size suffixes
14242 if the operands are registers. */
14247 {
14263 }
14264 }
14265 else
14266 {
14267 output_operand_lossage
14270 }
14272 output_operand_lossage
14292 {
14295 }
14300 {
14351 }
14355 /* Little bit of braindamage here. The SSE compare instructions
14356 does use completely different names for the comparisons that the
14357 fp conditional moves. */
14359 {
14362 {
14365 }
14371 {
14374 }
14380 {
14383 }
14392 {
14395 }
14401 {
14404 }
14410 {
14413 }
14424 }
14429 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14432 #endif
14437 {
14441 }
14445 file);
14450 {
14454 }
14455 /* It doesn't actually matter what mode we use here, as we're
14456 only going to use this for printing. */
14464 #ifdef HAVE_AS_IX86_HLE
14466 #else
14468 #endif
14470 #ifdef HAVE_AS_IX86_HLE
14472 #else
14474 #endif
14475 /* We do not want to print value of the operand. */
14484 {
14489 else
14492 }
14495 {
14496 rtx x;
14505 {
14510 {
14512 bool cputaken
14515 /* Emit hints only in the case default branch prediction
14516 heuristics would fail. */
14518 {
14519 /* We use 3e (DS) prefix for taken branches and
14520 2e (CS) prefix for not taken branches. */
14523 else
14525 }
14526 }
14527 }
14529 }
14532 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14534 #endif
14541 /* The kernel uses a different segment register for performance
14542 reasons; a system call would not have to trash the userspace
14543 segment register, which would be expensive. */
14546 else
14561 }
14562 }
14568 {
14569 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14572 {
14575 {
14584 else
14590 }
14592 /* Check for explicit size override (codes 'b', 'w', 'k',
14593 'q' and 'x') */
14607 }
14610 /* Avoid (%rip) for call operands. */
14616 else
14618 }
14621 {
14622 REAL_VALUE_TYPE r;
14630 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14634 else
14636 }
14639 {
14640 REAL_VALUE_TYPE r;
14649 }
14651 /* These float cases don't actually occur as immediate operands. */
14653 {
14658 }
14660 else
14661 {
14662 /* We have patterns that allow zero sets of memory, for instance.
14663 In 64-bit mode, we should probably support all 8-byte vectors,
14664 since we can in fact encode that into an immediate. */
14666 {
14669 }
14672 {
14674 {
14677 }
14680 {
14683 else
14685 }
14686 }
14691 else
14693 }
14694 }
14696 static bool
14698 {
14701 }
14702 \f
14703 /* Print a memory operand whose address is ADDR. */
14705 static void
14707 {
14716 {
14723 }
14725 {
14729 }
14730 else
14741 {
14752 }
14754 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14756 {
14768 }
14770 {
14771 /* Displacement only requires special attention. */
14774 {
14778 }
14781 else
14783 }
14784 else
14785 {
14786 /* Print SImode register names to force addr32 prefix. */
14788 {
14789 #ifdef ENABLE_CHECKING
14792 {
14803 }
14804 #endif
14807 }
14809 && TARGET_X32
14810 && disp
14813 {
14814 /* X32 runs in 64-bit mode, where displacement, DISP, in
14815 address DISP(%r64), is encoded as 32-bit immediate sign-
14816 extended from 32-bit to 64-bit. For -0x40000300(%r64),
14817 address is %r64 + 0xffffffffbffffd00. When %r64 <
14818 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
14819 which is invalid for x32. The correct address is %r64
14820 - 0x40000300 == 0xf7ffdd64. To properly encode
14821 -0x40000300(%r64) for x32, we zero-extend negative
14822 displacement by forcing addr32 prefix which truncates
14823 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
14824 zero-extend all negative displacements, including -1(%rsp).
14825 However, for small negative displacements, sign-extension
14826 won't cause overflow. We only zero-extend negative
14827 displacements if they < -16*1024*1024, which is also used
14828 to check legitimate address displacements for PIC. */
14830 }
14833 {
14835 {
14840 else
14842 }
14848 {
14853 }
14855 }
14856 else
14857 {
14861 {
14862 /* Pull out the offset of a symbol; print any symbol itself. */
14866 {
14870 }
14878 else
14880 }
14884 {
14887 {
14891 }
14892 }
14895 else
14899 {
14904 }
14906 }
14907 }
14908 }
14910 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14912 static bool
14914 {
14915 rtx op;
14922 {
14925 /* FIXME: This might be @TPOFF in Sun ld. */
14936 else
14948 else
14955 #if TARGET_MACHO
14961 #endif
14964 {
14969 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14971 #else
14973 #endif
14976 }
14981 }
14984 }
14985 \f
14986 /* Split one or more double-mode RTL references into pairs of half-mode
14987 references. The RTL can be REG, offsettable MEM, integer constant, or
14988 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14989 split and "num" is its length. lo_half and hi_half are output arrays
14990 that parallel "operands". */
14992 void
14995 {
15000 {
15009 }
15014 {
15017 /* simplify_subreg refuse to split volatile memory addresses,
15018 but we still have to handle it. */
15020 {
15023 }
15024 else
15025 {
15032 }
15033 }
15034 }
15035 \f
15036 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15037 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15038 is the expression of the binary operation. The output may either be
15039 emitted here, or returned to the caller, like all output_* functions.
15041 There is no guarantee that the operands are the same mode, as they
15042 might be within FLOAT or FLOAT_EXTEND expressions. */
15044 #ifndef SYSV386_COMPAT
15045 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15046 wants to fix the assemblers because that causes incompatibility
15047 with gcc. No-one wants to fix gcc because that causes
15048 incompatibility with assemblers... You can use the option of
15049 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15050 #define SYSV386_COMPAT 1
15051 #endif
15055 {
15061 #ifdef ENABLE_CHECKING
15062 /* Even if we do not want to check the inputs, this documents input
15063 constraints. Which helps in understanding the following code. */
15073 else
15075 #endif
15078 {
15083 else
15092 else
15101 else
15110 else
15117 }
15120 {
15122 {
15126 else
15128 }
15129 else
15130 {
15134 else
15136 }
15138 }
15142 {
15146 {
15150 }
15152 /* know operands[0] == operands[1]. */
15155 {
15158 }
15161 {
15163 /* How is it that we are storing to a dead operand[2]?
15164 Well, presumably operands[1] is dead too. We can't
15165 store the result to st(0) as st(0) gets popped on this
15166 instruction. Instead store to operands[2] (which I
15167 think has to be st(1)). st(1) will be popped later.
15168 gcc <= 2.8.1 didn't have this check and generated
15169 assembly code that the Unixware assembler rejected. */
15171 else
15174 }
15178 else
15185 {
15188 }
15191 {
15194 }
15197 {
15198 #if SYSV386_COMPAT
15199 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15200 derived assemblers, confusingly reverse the direction of
15201 the operation for fsub{r} and fdiv{r} when the
15202 destination register is not st(0). The Intel assembler
15203 doesn't have this brain damage. Read !SYSV386_COMPAT to
15204 figure out what the hardware really does. */
15207 else
15209 #else
15211 /* As above for fmul/fadd, we can't store to st(0). */
15213 else
15215 #endif
15217 }
15220 {
15221 #if SYSV386_COMPAT
15224 else
15226 #else
15229 else
15231 #endif
15233 }
15236 {
15239 else
15242 }
15244 {
15245 #if SYSV386_COMPAT
15247 #else
15249 #endif
15250 }
15251 else
15252 {
15253 #if SYSV386_COMPAT
15255 #else
15257 #endif
15258 }
15263 }
15267 }
15269 /* Check if a 256bit AVX register is referenced inside of EXP. */
15271 static int
15273 {
15284 }
15286 /* Return needed mode for entity in optimize_mode_switching pass. */
15288 static int
15290 {
15292 {
15293 rtx link;
15295 /* Needed mode is set to AVX_U128_CLEAN if there are
15296 no 256bit modes used in function arguments. */
15298 link;
15300 {
15302 {
15307 }
15308 }
15311 }
15313 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15314 changes state only when a 256bit register is written to, but we need
15315 to prevent the compiler from moving optimal insertion point above
15316 eventual read from 256bit register. */
15321 }
15323 /* Return mode that i387 must be switched into
15324 prior to the execution of insn. */
15326 static int
15328 {
15331 /* The mode UNINITIALIZED is used to store control word after a
15332 function call or ASM pattern. The mode ANY specify that function
15333 has no requirements on the control word and make no changes in the
15334 bits we are interested in. */
15348 {
15371 }
15374 }
15376 /* Return mode that entity must be switched into
15377 prior to the execution of insn. */
15379 int
15381 {
15383 {
15393 }
15395 }
15397 /* Check if a 256bit AVX register is referenced in stores. */
15399 static void
15401 {
15403 {
15406 }
15407 }
15409 /* Calculate mode of upper 128bit AVX registers after the insn. */
15411 static int
15413 {
15420 /* We know that state is clean after CALL insn if there are no
15421 256bit registers used in the function return register. */
15423 {
15428 }
15430 /* Otherwise, return current mode. Remember that if insn
15431 references AVX 256bit registers, the mode was already changed
15432 to DIRTY from MODE_NEEDED. */
15434 }
15436 /* Return the mode that an insn results in. */
15438 int
15440 {
15442 {
15452 }
15453 }
15455 static int
15457 {
15458 tree arg;
15460 /* Entry mode is set to AVX_U128_DIRTY if there are
15461 256bit modes used in function arguments. */
15464 {
15469 }
15472 }
15474 /* Return a mode that ENTITY is assumed to be
15475 switched to at function entry. */
15477 int
15479 {
15481 {
15491 }
15492 }
15494 static int
15496 {
15499 /* Exit mode is set to AVX_U128_DIRTY if there are
15500 256bit modes used in the function return register. */
15505 }
15507 /* Return a mode that ENTITY is assumed to be
15508 switched to at function exit. */
15510 int
15512 {
15514 {
15524 }
15525 }
15527 /* Output code to initialize control word copies used by trunc?f?i and
15528 rounding patterns. CURRENT_MODE is set to current control word,
15529 while NEW_MODE is set to new control word. */
15531 static void
15533 {
15535 rtx new_mode;
15546 {
15548 {
15550 /* round toward zero (truncate) */
15556 /* round down toward -oo */
15563 /* round up toward +oo */
15570 /* mask precision exception for nearbyint() */
15577 }
15578 }
15579 else
15580 {
15582 {
15584 /* round toward zero (truncate) */
15590 /* round down toward -oo */
15596 /* round up toward +oo */
15602 /* mask precision exception for nearbyint() */
15609 }
15610 }
15616 }
15618 /* Emit vzeroupper. */
15620 void
15622 {
15625 /* Cancel automatic vzeroupper insertion if there are
15626 live call-saved SSE registers at the insertion point. */
15638 }
15640 /* Generate one or more insns to set ENTITY to MODE. */
15642 void
15644 {
15646 {
15661 }
15662 }
15664 /* Output code for INSN to convert a float to a signed int. OPERANDS
15665 are the insn operands. The output may be [HSD]Imode and the input
15666 operand may be [SDX]Fmode. */
15670 {
15675 /* Jump through a hoop or two for DImode, since the hardware has no
15676 non-popping instruction. We used to do this a different way, but
15677 that was somewhat fragile and broke with post-reload splitters. */
15687 else
15688 {
15693 else
15697 }
15700 }
15702 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15703 have the values zero or one, indicates the ffreep insn's operand
15704 from the OPERANDS array. */
15708 {
15710 #ifdef HAVE_AS_IX86_FFREEP
15712 #else
15713 {
15723 }
15724 #endif
15727 }
15730 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15731 should be used. UNORDERED_P is true when fucom should be used. */
15735 {
15741 {
15744 }
15745 else
15746 {
15749 }
15752 {
15756 else
15758 else
15761 else
15763 }
15770 {
15772 {
15775 }
15776 else
15778 }
15781 && stack_top_dies
15784 {
15785 /* If both the top of the 387 stack dies, and the other operand
15786 is also a stack register that dies, then this must be a
15787 `fcompp' float compare */
15790 {
15791 /* There is no double popping fcomi variant. Fortunately,
15792 eflags is immune from the fstp's cc clobbering. */
15795 else
15798 }
15799 else
15800 {
15803 else
15805 }
15806 }
15807 else
15808 {
15809 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15812 {
15820 NULL,
15821 NULL,
15828 NULL,
15829 NULL,
15830 NULL,
15831 NULL
15832 };
15847 }
15848 }
15850 void
15852 {
15855 #ifdef ASM_QUAD
15858 #else
15860 #endif
15863 }
15865 void
15867 {
15870 #ifdef ASM_QUAD
15873 #else
15875 #endif
15876 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15882 #if TARGET_MACHO
15884 {
15888 }
15889 #endif
15890 else
15893 }
15894 \f
15895 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15896 for the target. */
15898 void
15900 {
15901 rtx tmp;
15903 /* We play register width games, which are only valid after reload. */
15906 /* Avoid HImode and its attendant prefix byte. */
15911 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15913 {
15916 }
15919 }
15921 /* X is an unchanging MEM. If it is a constant pool reference, return
15922 the constant pool rtx, else NULL. */
15924 rtx
15926 {
15933 }
15935 void
15937 {
15945 {
15948 {
15954 }
15958 }
15962 {
15975 {
15982 }
15983 }
15987 {
15989 {
15990 #if TARGET_MACHO
15991 /* dynamic-no-pic */
15993 {
15994 rtx temp = ((reload_in_progress
16002 }
16004 {
16008 }
16011 else
16012 {
16020 }
16021 /* dynamic-no-pic */
16022 #endif
16023 }
16024 else
16025 {
16029 {
16035 }
16036 }
16037 }
16038 else
16039 {
16050 /* Force large constants in 64bit compilation into register
16051 to get them CSEed. */
16063 {
16064 /* If we are loading a floating point constant to a register,
16065 force the value to memory now, since we'll get better code
16066 out the back end. */
16070 {
16075 }
16076 }
16077 }
16080 }
16082 void
16084 {
16088 /* Force constants other than zero into memory. We do not know how
16089 the instructions used to build constants modify the upper 64 bits
16090 of the register, once we have that information we may be able
16091 to handle some of them more efficiently. */
16100 /* We need to check memory alignment for SSE mode since attribute
16101 can make operands unaligned. */
16106 {
16109 /* ix86_expand_vector_move_misalign() does not like constants ... */
16115 /* ... nor both arguments in memory. */
16123 }
16125 /* Make operand1 a register if it isn't already. */
16129 {
16132 }
16135 }
16137 /* Split 32-byte AVX unaligned load and store if needed. */
16139 static void
16141 {
16142 rtx m;
16149 {
16170 }
16173 {
16175 {
16182 }
16183 else
16185 }
16187 {
16189 {
16194 }
16195 else
16197 }
16198 else
16200 }
16202 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16203 straight to ix86_expand_vector_move. */
16204 /* Code generation for scalar reg-reg moves of single and double precision data:
16205 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16206 movaps reg, reg
16207 else
16208 movss reg, reg
16209 if (x86_sse_partial_reg_dependency == true)
16210 movapd reg, reg
16211 else
16212 movsd reg, reg
16214 Code generation for scalar loads of double precision data:
16215 if (x86_sse_split_regs == true)
16216 movlpd mem, reg (gas syntax)
16217 else
16218 movsd mem, reg
16220 Code generation for unaligned packed loads of single precision data
16221 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16222 if (x86_sse_unaligned_move_optimal)
16223 movups mem, reg
16225 if (x86_sse_partial_reg_dependency == true)
16226 {
16227 xorps reg, reg
16228 movlps mem, reg
16229 movhps mem+8, reg
16230 }
16231 else
16232 {
16233 movlps mem, reg
16234 movhps mem+8, reg
16235 }
16237 Code generation for unaligned packed loads of double precision data
16238 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16239 if (x86_sse_unaligned_move_optimal)
16240 movupd mem, reg
16242 if (x86_sse_split_regs == true)
16243 {
16244 movlpd mem, reg
16245 movhpd mem+8, reg
16246 }
16247 else
16248 {
16249 movsd mem, reg
16250 movhpd mem+8, reg
16251 }
16252 */
16254 void
16256 {
16264 {
16266 {
16271 /* FALLTHRU */
16279 }
16282 }
16285 {
16286 /* ??? If we have typed data, then it would appear that using
16287 movdqu is the only way to get unaligned data loaded with
16288 integer type. */
16290 {
16293 /* We will eventually emit movups based on insn attributes. */
16295 }
16297 {
16298 rtx zero;
16301 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16302 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16304 {
16305 /* We will eventually emit movups based on insn attributes. */
16308 }
16310 /* When SSE registers are split into halves, we can avoid
16311 writing to the top half twice. */
16313 {
16316 }
16317 else
16318 {
16319 /* ??? Not sure about the best option for the Intel chips.
16320 The following would seem to satisfy; the register is
16321 entirely cleared, breaking the dependency chain. We
16322 then store to the upper half, with a dependency depth
16323 of one. A rumor has it that Intel recommends two movsd
16324 followed by an unpacklpd, but this is unconfirmed. And
16325 given that the dependency depth of the unpacklpd would
16326 still be one, I'm not sure why this would be better. */
16328 }
16334 }
16335 else
16336 {
16338 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16339 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16341 {
16346 }
16350 else
16360 }
16361 }
16363 {
16365 {
16368 /* We will eventually emit movups based on insn attributes. */
16370 }
16372 {
16374 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16375 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16377 /* We will eventually emit movups based on insn attributes. */
16379 else
16380 {
16385 }
16386 }
16387 else
16388 {
16393 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16394 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16396 {
16399 }
16400 else
16401 {
16406 }
16407 }
16408 }
16409 else
16411 }
16413 /* Expand a push in MODE. This is some mode for which we do not support
16414 proper push instructions, at least from the registers that we expect
16415 the value to live in. */
16417 void
16419 {
16420 rtx tmp;
16430 /* When we push an operand onto stack, it has to be aligned at least
16431 at the function argument boundary. However since we don't have
16432 the argument type, we can't determine the actual argument
16433 boundary. */
16435 }
16437 /* Helper function of ix86_fixup_binary_operands to canonicalize
16438 operand order. Returns true if the operands should be swapped. */
16440 static bool
16442 rtx operands[])
16443 {
16448 /* If the operation is not commutative, we can't do anything. */
16452 /* Highest priority is that src1 should match dst. */
16458 /* Next highest priority is that immediate constants come second. */
16464 /* Lowest priority is that memory references should come second. */
16471 }
16474 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16475 destination to use for the operation. If different from the true
16476 destination in operands[0], a copy operation will be required. */
16478 rtx
16480 rtx operands[])
16481 {
16486 /* Canonicalize operand order. */
16488 {
16489 rtx temp;
16491 /* It is invalid to swap operands of different modes. */
16497 }
16499 /* Both source operands cannot be in memory. */
16501 {
16502 /* Optimization: Only read from memory once. */
16504 {
16507 }
16508 else
16510 }
16512 /* If the destination is memory, and we do not have matching source
16513 operands, do things in registers. */
16517 /* Source 1 cannot be a constant. */
16521 /* Source 1 cannot be a non-matching memory. */
16525 /* Improve address combine. */
16534 }
16536 /* Similarly, but assume that the destination has already been
16537 set up properly. */
16539 void
16542 {
16545 }
16547 /* Attempt to expand a binary operator. Make the expansion closer to the
16548 actual machine, then just general_operand, which will allow 3 separate
16549 memory references (one output, two input) in a single insn. */
16551 void
16553 rtx operands[])
16554 {
16561 /* Emit the instruction. */
16565 {
16566 /* Reload doesn't know about the flags register, and doesn't know that
16567 it doesn't want to clobber it. We can only do this with PLUS. */
16570 }
16574 {
16575 /* This is going to be an LEA; avoid splitting it later. */
16577 }
16578 else
16579 {
16582 }
16584 /* Fix up the destination if needed. */
16587 }
16589 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16590 the given OPERANDS. */
16592 void
16594 rtx operands[])
16595 {
16598 {
16601 }
16603 {
16606 }
16607 /* Optimize (__m128i) d | (__m128i) e and similar code
16608 when d and e are float vectors into float vector logical
16609 insn. In C/C++ without using intrinsics there is no other way
16610 to express vector logical operation on float vectors than
16611 to cast them temporarily to integer vectors. */
16613 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16622 {
16623 rtx dst;
16625 {
16632 {
16635 }
16636 else
16637 {
16642 }
16653 }
16654 }
16663 }
16665 /* Return TRUE or FALSE depending on whether the binary operator meets the
16666 appropriate constraints. */
16668 bool
16671 {
16676 /* Both source operands cannot be in memory. */
16680 /* Canonicalize operand order for commutative operators. */
16682 {
16686 }
16688 /* If the destination is memory, we must have a matching source operand. */
16692 /* Source 1 cannot be a constant. */
16696 /* Source 1 cannot be a non-matching memory. */
16698 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16706 }
16708 /* Attempt to expand a unary operator. Make the expansion closer to the
16709 actual machine, then just general_operand, which will allow 2 separate
16710 memory references (one output, one input) in a single insn. */
16712 void
16714 rtx operands[])
16715 {
16722 /* If the destination is memory, and we do not have matching source
16723 operands, do things in registers. */
16726 {
16729 else
16731 }
16733 /* When source operand is memory, destination must match. */
16737 /* Emit the instruction. */
16741 {
16742 /* Reload doesn't know about the flags register, and doesn't know that
16743 it doesn't want to clobber it. */
16746 }
16747 else
16748 {
16751 }
16753 /* Fix up the destination if needed. */
16756 }
16758 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16759 divisor are within the range [0-255]. */
16761 void
16764 {
16773 {
16786 }
16793 /* Use 8bit unsigned divimod if dividend and divisor are within
16794 the range [0-255]. */
16803 pc_rtx);
16808 /* Generate original signed/unsigned divimod. */
16813 /* Branch to the end. */
16817 /* Generate 8bit unsigned divide. */
16819 /* Don't use operands[0] for result of 8bit divide since not all
16820 registers support QImode ZERO_EXTRACT. */
16827 {
16830 }
16831 else
16832 {
16835 }
16837 /* Extract remainder from AH. */
16841 else
16842 {
16843 /* Need a new scratch register since the old one has result
16844 of 8bit divide. */
16848 }
16851 /* Zero extend quotient from AL. */
16857 }
16859 #define LEA_MAX_STALL (3)
16860 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16862 /* Increase given DISTANCE in half-cycles according to
16863 dependencies between PREV and NEXT instructions.
16864 Add 1 half-cycle if there is no dependency and
16865 go to next cycle if there is some dependecy. */
16867 static unsigned int
16869 {
16886 }
16888 /* Function checks if instruction INSN defines register number
16889 REGNO1 or REGNO2. */
16891 static bool
16893 rtx insn)
16894 {
16902 {
16904 }
16907 }
16909 /* Function checks if instruction INSN uses register number
16910 REGNO as a part of address expression. */
16912 static bool
16914 {
16922 }
16924 /* Search backward for non-agu definition of register number REGNO1
16925 or register number REGNO2 in basic block starting from instruction
16926 START up to head of basic block or instruction INSN.
16928 Function puts true value into *FOUND var if definition was found
16929 and false otherwise.
16931 Distance in half-cycles between START and found instruction or head
16932 of BB is added to DISTANCE and returned. */
16934 static int
16938 {
16948 {
16950 {
16953 {
16956 {
16959 }
16960 }
16963 }
16968 }
16971 }
16973 /* Search backward for non-agu definition of register number REGNO1
16974 or register number REGNO2 in INSN's basic block until
16975 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16976 2. Reach neighbour BBs boundary, or
16977 3. Reach agu definition.
16978 Returns the distance between the non-agu definition point and INSN.
16979 If no definition point, returns -1. */
16981 static int
16983 rtx insn)
16984 {
16995 {
16996 edge e;
16997 edge_iterator ei;
17002 {
17005 }
17011 else
17012 {
17017 {
17018 int bb_dist
17024 {
17031 }
17032 }
17035 }
17036 }
17038 /* get_attr_type may modify recog data. We want to make sure
17039 that recog data is valid for instruction INSN, on which
17040 distance_non_agu_define is called. INSN is unchanged here. */
17047 }
17049 /* Return the distance in half-cycles between INSN and the next
17050 insn that uses register number REGNO in memory address added
17051 to DISTANCE. Return -1 if REGNO0 is set.
17053 Put true value into *FOUND if register usage was found and
17054 false otherwise.
17055 Put true value into *REDEFINED if register redefinition was
17056 found and false otherwise. */
17058 static int
17062 {
17073 {
17075 {
17078 {
17079 /* Return DISTANCE if OP0 is used in memory
17080 address in NEXT. */
17083 }
17086 {
17087 /* Return -1 if OP0 is set in NEXT. */
17090 }
17093 }
17099 }
17102 }
17104 /* Return the distance between INSN and the next insn that uses
17105 register number REGNO0 in memory address. Return -1 if no such
17106 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17108 static int
17110 {
17122 {
17123 edge e;
17124 edge_iterator ei;
17129 {
17132 }
17138 else
17139 {
17145 {
17146 int bb_dist
17151 {
17158 }
17159 }
17162 }
17163 }
17169 }
17171 /* Define this macro to tune LEA priority vs ADD, it take effect when
17172 there is a dilemma of choicing LEA or ADD
17173 Negative value: ADD is more preferred than LEA
17174 Zero: Netrual
17175 Positive value: LEA is more preferred than ADD*/
17176 #define IX86_LEA_PRIORITY 0
17178 /* Return true if usage of lea INSN has performance advantage
17179 over a sequence of instructions. Instructions sequence has
17180 SPLIT_COST cycles higher latency than lea latency. */
17182 static bool
17185 {
17192 {
17193 /* If there is no non AGU operand definition, no AGU
17194 operand usage and split cost is 0 then both lea
17195 and non lea variants have same priority. Currently
17196 we prefer lea for 64 bit code and non lea on 32 bit
17197 code. */
17200 else
17202 }
17204 /* With longer definitions distance lea is more preferable.
17205 Here we change it to take into account splitting cost and
17206 lea priority. */
17209 /* If there is no use in memory addess then we just check
17210 that split cost exceeds AGU stall. */
17214 /* If this insn has both backward non-agu dependence and forward
17215 agu dependence, the one with short distance takes effect. */
17217 }
17219 /* Return true if it is legal to clobber flags by INSN and
17220 false otherwise. */
17222 static bool
17224 {
17227 bitmap live;
17230 {
17232 {
17239 }
17245 }
17249 }
17251 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17252 move and add to avoid AGU stalls. */
17254 bool
17256 {
17259 /* Check if we need to optimize. */
17263 /* Check it is correct to split here. */
17271 /* We need to split only adds with non destructive
17272 destination operand. */
17275 else
17277 }
17279 /* Return true if we should emit lea instruction instead of mov
17280 instruction. */
17282 bool
17284 {
17287 /* Check if we need to optimize. */
17291 /* Use lea for reg to reg moves only. */
17299 }
17301 /* Return true if we need to split lea into a sequence of
17302 instructions to avoid AGU stalls. */
17304 bool
17306 {
17312 /* Check we need to optimize. */
17316 /* Check it is correct to split here. */
17323 /* There should be at least two components in the address. */
17328 /* We should not split into add if non legitimate pic
17329 operand is used as displacement. */
17344 /* Compute how many cycles we will add to execution time
17345 if split lea into a sequence of instructions. */
17347 {
17348 /* Have to use mov instruction if non desctructive
17349 destination form is used. */
17353 /* Have to add index to base if both exist. */
17357 /* Have to use shift and adds if scale is 2 or greater. */
17359 {
17364 else
17366 }
17368 /* Have to use add instruction with immediate if
17369 disp is non zero. */
17373 /* Subtract the price of lea. */
17375 }
17378 }
17380 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17381 matches destination. RTX includes clobber of FLAGS_REG. */
17383 static void
17386 {
17393 }
17395 /* Return true if regno1 def is nearest to the insn. */
17397 static bool
17399 {
17406 {
17408 {
17411 }
17417 }
17419 /* None of the regs is defined in the bb. */
17421 }
17423 /* Split lea instructions into a sequence of instructions
17424 which are executed on ALU to avoid AGU stalls.
17425 It is assumed that it is allowed to clobber flags register
17426 at lea position. */
17428 void
17430 {
17446 {
17449 }
17452 {
17455 }
17461 {
17462 /* Case r1 = r1 + ... */
17464 {
17465 /* If we have a case r1 = r1 + C * r1 then we
17466 should use multiplication which is very
17467 expensive. Assume cost model is wrong if we
17468 have such case here. */
17473 }
17474 else
17475 {
17476 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17480 /* Use shift for scaling. */
17489 }
17490 }
17492 {
17495 }
17496 else
17497 {
17499 {
17502 }
17504 {
17507 }
17508 else
17509 {
17514 else
17515 {
17516 rtx tmp1;
17518 /* Find better operand for SET instruction, depending
17519 on which definition is farther from the insn. */
17522 else
17532 }
17535 }
17539 }
17540 }
17542 /* Return true if it is ok to optimize an ADD operation to LEA
17543 operation to avoid flag register consumation. For most processors,
17544 ADD is faster than LEA. For the processors like ATOM, if the
17545 destination register of LEA holds an actual address which will be
17546 used soon, LEA is better and otherwise ADD is better. */
17548 bool
17550 {
17555 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17563 }
17565 /* Return true if destination reg of SET_BODY is shift count of
17566 USE_BODY. */
17568 static bool
17570 {
17571 rtx set_dest;
17572 rtx shift_rtx;
17575 /* Retrieve destination of SET_BODY. */
17577 {
17586 use_body))
17591 }
17593 /* Retrieve shift count of USE_BODY. */
17595 {
17607 }
17615 {
17618 /* Return true if shift count is dest of SET_BODY. */
17620 {
17621 /* Add check since it can be invoked before register
17622 allocation in pre-reload schedule. */
17628 }
17629 }
17632 }
17634 /* Return true if destination reg of SET_INSN is shift count of
17635 USE_INSN. */
17637 bool
17639 {
17642 }
17644 /* Return TRUE or FALSE depending on whether the unary operator meets the
17645 appropriate constraints. */
17647 bool
17651 {
17652 /* If one of operands is memory, source and destination must match. */
17658 }
17660 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17661 are ok, keeping in mind the possible movddup alternative. */
17663 bool
17665 {
17671 }
17673 /* Post-reload splitter for converting an SF or DFmode value in an
17674 SSE register into an unsigned SImode. */
17676 void
17678 {
17689 /* Load up the value into the low element. We must ensure that the other
17690 elements are valid floats -- zero is the easiest such value. */
17692 {
17695 else
17697 }
17698 else
17699 {
17704 else
17706 }
17726 else
17731 }
17733 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17734 Expects the 64-bit DImode to be supplied in a pair of integral
17735 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17736 -mfpmath=sse, !optimize_size only. */
17738 void
17740 {
17744 rtx x;
17750 {
17753 }
17754 else
17755 {
17759 }
17767 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17770 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17771 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17772 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17773 (0x1.0p84 + double(fp_value_hi_xmm)).
17774 Note these exponents differ by 32. */
17778 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17779 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17788 /* Add the upper and lower DFmode values together. */
17791 else
17792 {
17796 }
17799 }
17801 /* Not used, but eases macroization of patterns. */
17802 void
17804 rtx input ATTRIBUTE_UNUSED)
17805 {
17807 }
17809 /* Convert an unsigned SImode value into a DFmode. Only currently used
17810 for SSE, but applicable anywhere. */
17812 void
17814 {
17815 REAL_VALUE_TYPE TWO31r;
17830 }
17832 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17833 32-bit mode; otherwise we have a direct convert instruction. */
17835 void
17837 {
17838 REAL_VALUE_TYPE TWO32r;
17856 }
17858 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17859 For x86_32, -mfpmath=sse, !optimize_size only. */
17860 void
17862 {
17863 REAL_VALUE_TYPE ONE16r;
17882 }
17884 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17885 a vector of unsigned ints VAL to vector of floats TARGET. */
17887 void
17889 {
17891 REAL_VALUE_TYPE TWO16r;
17898 else
17903 OPTAB_DIRECT);
17914 OPTAB_DIRECT);
17916 OPTAB_DIRECT);
17919 }
17921 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17922 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17923 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17924 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17926 rtx
17928 {
17929 REAL_VALUE_TYPE TWO31r;
17944 {
17950 }
17959 OPTAB_DIRECT);
17960 else
17961 {
17967 OPTAB_DIRECT);
17968 }
17971 }
17973 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17974 then replicate the value for all elements of the vector
17975 register. */
17977 rtx
17979 {
17981 rtvec v;
17985 {
18012 }
18013 }
18015 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18016 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18017 for an SSE register. If VECT is true, then replicate the mask for
18018 all elements of the vector register. If INVERT is true, then create
18019 a mask excluding the sign bit. */
18021 rtx
18023 {
18027 rtx v;
18028 rtx mask;
18030 /* Find the sign bit, sign extended to 2*HWI. */
18032 {
18052 else
18060 {
18063 }
18064 else
18065 {
18066 rtvec vec;
18072 {
18075 }
18076 else
18086 }
18091 }
18096 /* Force this value into the low part of a fp vector constant. */
18105 }
18107 /* Generate code for floating point ABS or NEG. */
18109 void
18111 rtx operands[])
18112 {
18123 {
18129 }
18131 /* NEG and ABS performed with SSE use bitwise mask operations.
18132 Create the appropriate mask now. */
18135 else
18145 {
18147 rtvec par;
18152 else
18153 {
18156 }
18158 }
18159 else
18161 }
18163 /* Expand a copysign operation. Special case operand 0 being a constant. */
18165 void
18167 {
18181 else
18185 {
18192 {
18195 else
18196 {
18200 }
18201 }
18211 else
18215 }
18216 else
18217 {
18227 else
18231 }
18232 }
18234 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18235 be a constant, and so has already been expanded into a vector constant. */
18237 void
18239 {
18255 {
18258 }
18259 }
18261 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18262 so we have to do two masks. */
18264 void
18266 {
18281 {
18282 /* Shouldn't happen often (it's useless, obviously), but when it does
18283 we'd generate incorrect code if we continue below. */
18286 }
18289 {
18300 }
18301 else
18302 {
18304 {
18306 }
18308 {
18312 }
18316 {
18319 }
18321 {
18326 }
18328 }
18332 }
18334 /* Return TRUE or FALSE depending on whether the first SET in INSN
18335 has source and destination with matching CC modes, and that the
18336 CC mode is at least as constrained as REQ_MODE. */
18338 bool
18340 {
18341 rtx set;
18352 {
18362 /* FALLTHRU */
18366 /* FALLTHRU */
18370 /* FALLTHRU */
18384 }
18387 }
18389 /* Generate insn patterns to do an integer compare of OPERANDS. */
18391 static rtx
18393 {
18400 /* This is very simple, but making the interface the same as in the
18401 FP case makes the rest of the code easier. */
18405 /* Return the test that should be put into the flags user, i.e.
18406 the bcc, scc, or cmov instruction. */
18408 }
18410 /* Figure out whether to use ordered or unordered fp comparisons.
18411 Return the appropriate mode to use. */
18413 enum machine_mode
18415 {
18416 /* ??? In order to make all comparisons reversible, we do all comparisons
18417 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18418 all forms trapping and nontrapping comparisons, we can make inequality
18419 comparisons trapping again, since it results in better code when using
18420 FCOM based compares. */
18422 }
18424 enum machine_mode
18426 {
18430 {
18433 }
18436 {
18437 /* Only zero flag is needed. */
18441 /* Codes needing carry flag. */
18444 /* Detect overflow checks. They need just the carry flag. */
18448 else
18452 /* Detect overflow checks. They need just the carry flag. */
18456 else
18458 /* Codes possibly doable only with sign flag when
18459 comparing against zero. */
18464 else
18465 /* For other cases Carry flag is not required. */
18467 /* Codes doable only with sign flag when comparing
18468 against zero, but we miss jump instruction for it
18469 so we need to use relational tests against overflow
18470 that thus needs to be zero. */
18475 else
18477 /* strcmp pattern do (use flags) and combine may ask us for proper
18478 mode. */
18483 }
18484 }
18486 /* Return the fixed registers used for condition codes. */
18488 static bool
18490 {
18494 }
18496 /* If two condition code modes are compatible, return a condition code
18497 mode which is compatible with both. Otherwise, return
18498 VOIDmode. */
18500 static enum machine_mode
18502 {
18519 {
18533 {
18547 }
18551 /* These are only compatible with themselves, which we already
18552 checked above. */
18554 }
18555 }
18558 /* Return a comparison we can do and that it is equivalent to
18559 swap_condition (code) apart possibly from orderedness.
18560 But, never change orderedness if TARGET_IEEE_FP, returning
18561 UNKNOWN in that case if necessary. */
18563 static enum rtx_code
18565 {
18567 {
18578 }
18579 }
18581 /* Return cost of comparison CODE using the best strategy for performance.
18582 All following functions do use number of instructions as a cost metrics.
18583 In future this should be tweaked to compute bytes for optimize_size and
18584 take into account performance of various instructions on various CPUs. */
18586 static int
18588 {
18591 /* The cost of code using bit-twiddling on %ah. */
18593 {
18616 }
18619 {
18626 }
18627 }
18629 /* Return strategy to use for floating-point. We assume that fcomi is always
18630 preferrable where available, since that is also true when looking at size
18631 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18633 enum ix86_fpcmp_strategy
18635 {
18636 /* Do fcomi/sahf based test when profitable. */
18645 }
18647 /* Swap, force into registers, or otherwise massage the two operands
18648 to a fp comparison. The operands are updated in place; the new
18649 comparison code is returned. */
18651 static enum rtx_code
18653 {
18659 /* All of the unordered compare instructions only work on registers.
18660 The same is true of the fcomi compare instructions. The XFmode
18661 compare instructions require registers except when comparing
18662 against zero or when converting operand 1 from fixed point to
18663 floating point. */
18672 {
18675 }
18676 else
18677 {
18678 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18679 things around if they appear profitable, otherwise force op0
18680 into a register. */
18686 {
18689 {
18690 rtx tmp;
18693 }
18694 }
18700 {
18705 {
18708 }
18709 else
18711 }
18712 }
18714 /* Try to rearrange the comparison to make it cheaper. */
18718 {
18719 rtx tmp;
18724 }
18729 }
18731 /* Convert comparison codes we use to represent FP comparison to integer
18732 code that will result in proper branch. Return UNKNOWN if no such code
18733 is available. */
18735 enum rtx_code
18737 {
18739 {
18762 }
18763 }
18765 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18767 static rtx
18769 {
18776 /* Do fcomi/sahf based test when profitable. */
18778 {
18783 tmp);
18791 tmp);
18800 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18807 /* In the unordered case, we have to check C2 for NaN's, which
18808 doesn't happen to work out to anything nice combination-wise.
18809 So do some bit twiddling on the value we've got in AH to come
18810 up with an appropriate set of condition codes. */
18814 {
18818 {
18821 }
18822 else
18823 {
18829 }
18834 {
18839 }
18840 else
18841 {
18844 }
18849 {
18852 }
18853 else
18854 {
18858 }
18863 {
18869 }
18870 else
18871 {
18874 }
18879 {
18884 }
18885 else
18886 {
18889 }
18894 {
18899 }
18900 else
18901 {
18904 }
18918 }
18923 }
18925 /* Return the test that should be put into the flags user, i.e.
18926 the bcc, scc, or cmov instruction. */
18929 const0_rtx);
18930 }
18932 static rtx
18934 {
18935 rtx ret;
18941 {
18944 }
18945 else
18949 }
18951 void
18953 {
18955 rtx tmp;
18958 {
18965 simple:
18969 pc_rtx);
18977 /* Expand DImode branch into multiple compare+branch. */
18978 {
18984 {
18987 }
18994 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
18995 avoid two branches. This costs one extra insn, so disable when
18996 optimizing for size. */
19001 {
19019 }
19021 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19022 op1 is a constant and the low word is zero, then we can just
19023 examine the high word. Similarly for low word -1 and
19024 less-or-equal-than or greater-than. */
19028 {
19031 {
19034 }
19038 {
19041 }
19045 }
19047 /* Otherwise, we need two or three jumps. */
19056 {
19070 }
19072 /*
19073 * a < b =>
19074 * if (hi(a) < hi(b)) goto true;
19075 * if (hi(a) > hi(b)) goto false;
19076 * if (lo(a) < lo(b)) goto true;
19077 * false:
19078 */
19090 }
19095 }
19096 }
19098 /* Split branch based on floating point condition. */
19099 void
19102 {
19103 rtx condition;
19104 rtx i;
19107 {
19112 }
19115 tmp);
19117 /* Remove pushed operand from stack. */
19127 }
19129 void
19131 {
19132 rtx ret;
19139 }
19141 /* Expand comparison setting or clearing carry flag. Return true when
19142 successful and set pop for the operation. */
19143 static bool
19145 {
19149 /* Do not handle double-mode compares that go through special path. */
19154 {
19159 /* Shortcut: following common codes never translate
19160 into carry flag compares. */
19165 /* These comparisons require zero flag; swap operands so they won't. */
19168 {
19173 }
19175 /* Try to expand the comparison and verify that we end up with
19176 carry flag based comparison. This fails to be true only when
19177 we decide to expand comparison using arithmetic that is not
19178 too common scenario. */
19187 else
19196 }
19202 {
19207 /* Convert a==0 into (unsigned)a<1. */
19216 /* Convert a>b into b<a or a>=b-1. */
19220 {
19222 /* Bail out on overflow. We still can swap operands but that
19223 would force loading of the constant into register. */
19228 }
19229 else
19230 {
19235 }
19238 /* Convert a>=0 into (unsigned)a<0x80000000. */
19256 }
19257 /* Swapping operands may cause constant to appear as first operand. */
19259 {
19263 }
19267 }
19269 bool
19271 {
19295 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19296 HImode insns, we'd be swallowed in word prefix ops. */
19302 {
19306 HOST_WIDE_INT diff;
19309 /* Sign bit compares are better done using shifts than we do by using
19310 sbb. */
19313 {
19314 /* Detect overlap between destination and compare sources. */
19318 {
19319 rtx flags;
19328 {
19330 compare_code
19332 }
19334 /* To simplify rest of code, restrict to the GEU case. */
19336 {
19342 }
19343 else
19344 {
19347 reverse_condition_maybe_unordered
19349 else
19352 }
19361 else
19364 }
19365 else
19366 {
19369 else
19370 {
19375 }
19377 }
19380 {
19381 /*
19382 * cmpl op0,op1
19383 * sbbl dest,dest
19384 * [addl dest, ct]
19385 *
19386 * Size 5 - 8.
19387 */
19392 }
19394 {
19395 /*
19396 * cmpl op0,op1
19397 * sbbl dest,dest
19398 * orl $ct, dest
19399 *
19400 * Size 8.
19401 */
19405 }
19407 {
19408 /*
19409 * cmpl op0,op1
19410 * sbbl dest,dest
19411 * notl dest
19412 * [addl dest, cf]
19413 *
19414 * Size 8 - 11.
19415 */
19421 }
19422 else
19423 {
19424 /*
19425 * cmpl op0,op1
19426 * sbbl dest,dest
19427 * [notl dest]
19428 * andl cf - ct, dest
19429 * [addl dest, ct]
19430 *
19431 * Size 8 - 11.
19432 */
19435 {
19439 }
19449 }
19455 }
19458 {
19461 HOST_WIDE_INT tmp;
19466 {
19469 /* We may be reversing unordered compare to normal compare, that
19470 is not valid in general (we may convert non-trapping condition
19471 to trapping one), however on i386 we currently emit all
19472 comparisons unordered. */
19475 }
19476 else
19477 {
19480 }
19481 }
19486 {
19491 {
19496 }
19497 }
19499 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19503 {
19504 /* If lea code below could be used, only optimize
19505 if it results in a 2 insn sequence. */
19511 {
19512 /*
19513 * notl op1 (if necessary)
19514 * sarl $31, op1
19515 * orl cf, op1
19516 */
19518 {
19522 }
19533 }
19534 }
19542 {
19543 /*
19544 * xorl dest,dest
19545 * cmpl op1,op2
19546 * setcc dest
19547 * lea cf(dest*(ct-cf)),dest
19548 *
19549 * Size 14.
19550 *
19551 * This also catches the degenerate setcc-only case.
19552 */
19554 rtx tmp;
19560 /* On x86_64 the lea instruction operates on Pmode, so we need
19561 to get arithmetics done in proper mode to match. */
19564 else
19565 {
19566 rtx out1;
19569 nops++;
19571 {
19573 nops++;
19574 }
19575 }
19577 {
19579 nops++;
19580 }
19582 {
19585 else
19587 }
19592 }
19594 /*
19595 * General case: Jumpful:
19596 * xorl dest,dest cmpl op1, op2
19597 * cmpl op1, op2 movl ct, dest
19598 * setcc dest jcc 1f
19599 * decl dest movl cf, dest
19600 * andl (cf-ct),dest 1:
19601 * addl ct,dest
19602 *
19603 * Size 20. Size 14.
19604 *
19605 * This is reasonably steep, but branch mispredict costs are
19606 * high on modern cpus, so consider failing only if optimizing
19607 * for space.
19608 */
19613 {
19615 {
19622 {
19625 /* We may be reversing unordered compare to normal compare,
19626 that is not valid in general (we may convert non-trapping
19627 condition to trapping one), however on i386 we currently
19628 emit all comparisons unordered. */
19630 }
19631 else
19632 {
19636 }
19637 }
19640 {
19641 /* notl op1 (if needed)
19642 sarl $31, op1
19643 andl (cf-ct), op1
19644 addl ct, op1
19646 For x < 0 (resp. x <= -1) there will be no notl,
19647 so if possible swap the constants to get rid of the
19648 complement.
19649 True/false will be -1/0 while code below (store flag
19650 followed by decrement) is 0/-1, so the constants need
19651 to be exchanged once more. */
19654 {
19657 }
19658 else
19659 {
19663 }
19666 }
19667 else
19668 {
19672 constm1_rtx,
19674 }
19686 }
19687 }
19690 {
19691 /* Try a few things more with specific constants and a variable. */
19693 optab op;
19699 /* If one of the two operands is an interesting constant, load a
19700 constant with the above and mask it in with a logical operation. */
19703 {
19709 else
19711 }
19713 {
19719 else
19721 }
19722 else
19729 /* Recurse to get the constant loaded. */
19733 /* Mask in the interesting variable. */
19735 OPTAB_WIDEN);
19740 }
19742 /*
19743 * For comparison with above,
19744 *
19745 * movl cf,dest
19746 * movl ct,tmp
19747 * cmpl op1,op2
19748 * cmovcc tmp,dest
19749 *
19750 * Size 15.
19751 */
19773 }
19775 /* Swap, force into registers, or otherwise massage the two operands
19776 to an sse comparison with a mask result. Thus we differ a bit from
19777 ix86_prepare_fp_compare_args which expects to produce a flags result.
19779 The DEST operand exists to help determine whether to commute commutative
19780 operators. The POP0/POP1 operands are updated in place. The new
19781 comparison code is returned, or UNKNOWN if not implementable. */
19783 static enum rtx_code
19786 {
19787 rtx tmp;
19790 {
19793 /* AVX supports all the needed comparisons. */
19796 /* We have no LTGT as an operator. We could implement it with
19797 NE & ORDERED, but this requires an extra temporary. It's
19798 not clear that it's worth it. */
19805 /* These are supported directly. */
19812 /* AVX has 3 operand comparisons, no need to swap anything. */
19815 /* For commutative operators, try to canonicalize the destination
19816 operand to be first in the comparison - this helps reload to
19817 avoid extra moves. */
19820 /* FALLTHRU */
19826 /* These are not supported directly before AVX, and furthermore
19827 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19828 comparison operands to transform into something that is
19829 supported. */
19838 }
19841 }
19843 /* Detect conditional moves that exactly match min/max operational
19844 semantics. Note that this is IEEE safe, as long as we don't
19845 interchange the operands.
19847 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19848 and TRUE if the operation is successful and instructions are emitted. */
19850 static bool
19853 {
19856 rtx tmp;
19859 ;
19861 {
19865 }
19866 else
19873 else
19878 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19879 but MODE may be a vector mode and thus not appropriate. */
19881 {
19883 rtvec v;
19888 }
19889 else
19890 {
19893 }
19897 }
19899 /* Expand an sse vector comparison. Return the register with the result. */
19901 static rtx
19904 {
19907 rtx x;
19920 {
19923 }
19924 else
19928 }
19930 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19931 operations. This is used for both scalar and vector conditional moves. */
19933 static void
19935 {
19941 {
19943 }
19945 {
19949 }
19951 {
19956 }
19958 {
19962 }
19964 {
19972 op_true,
19973 op_false)));
19974 }
19975 else
19976 {
19985 {
19999 {
20005 }
20020 {
20026 }
20030 }
20034 else
20035 {
20041 else
20053 }
20054 }
20055 }
20057 /* Expand a floating-point conditional move. Return true if successful. */
20059 bool
20061 {
20069 {
20072 /* Since we've no cmove for sse registers, don't force bad register
20073 allocation just to gain access to it. Deny movcc when the
20074 comparison mode doesn't match the move mode. */
20093 }
20100 /* The floating point conditional move instructions don't directly
20101 support conditions resulting from a signed integer comparison. */
20105 {
20110 }
20117 }
20119 /* Expand a floating-point vector conditional move; a vcond operation
20120 rather than a movcc operation. */
20122 bool
20124 {
20126 rtx cmp;
20131 {
20132 rtx temp;
20134 {
20151 }
20153 OPTAB_DIRECT);
20156 }
20166 }
20168 /* Expand a signed/unsigned integral vector conditional move. */
20170 bool
20172 {
20182 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20183 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20192 {
20196 {
20202 }
20205 {
20211 }
20212 }
20221 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20225 ;
20226 else
20227 {
20228 /* Canonicalize the comparison to EQ, GT, GTU. */
20230 {
20247 /* FALLTHRU */
20257 }
20259 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20261 {
20263 {
20265 /* SSE4.1 supports EQ. */
20272 /* SSE4.2 supports GT/GTU. */
20279 }
20280 }
20282 /* Unsigned parallel compare is not supported by the hardware.
20283 Play some tricks to turn this into a signed comparison
20284 against 0. */
20286 {
20290 {
20295 {
20300 {
20307 }
20308 /* Subtract (-(INT MAX) - 1) from both operands to make
20309 them signed. */
20320 }
20327 /* Perform a parallel unsigned saturating subtraction. */
20340 }
20341 }
20342 }
20344 /* Allow the comparison to be done in one mode, but the movcc to
20345 happen in another mode. */
20347 {
20350 }
20351 else
20352 {
20358 }
20363 }
20365 /* Expand a variable vector permutation. */
20367 void
20369 {
20380 /* Number of elements in the vector. */
20386 {
20388 {
20389 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20390 an constant shuffle operand. With a tiny bit of effort we can
20391 use VPERMD instead. A re-interpretation stall for V4DFmode is
20392 unfortunate but there's no avoiding it.
20393 Similarly for V16HImode we don't have instructions for variable
20394 shuffling, while for V32QImode we can use after preparing suitable
20395 masks vpshufb; vpshufb; vpermq; vpor. */
20398 {
20402 }
20403 else
20404 {
20408 }
20411 /* Replicate the low bits of the V4DImode mask into V8SImode:
20412 mask = { A B C D }
20413 t1 = { A A B B C C D D }. */
20421 else
20424 /* Multiply the shuffle indicies by two. */
20426 OPTAB_DIRECT);
20428 /* Add one to the odd shuffle indicies:
20429 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20431 {
20434 }
20438 OPTAB_DIRECT);
20440 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20445 }
20448 {
20450 /* The VPERMD and VPERMPS instructions already properly ignore
20451 the high bits of the shuffle elements. No need for us to
20452 perform an AND ourselves. */
20455 else
20456 {
20462 }
20469 else
20470 {
20476 }
20480 /* By combining the two 128-bit input vectors into one 256-bit
20481 input vector, we can use VPERMD and VPERMPS for the full
20482 two-operand shuffle. */
20514 /* From mask create two adjusted masks, which contain the same
20515 bits as mask in the low 7 bits of each vector element.
20516 The first mask will have the most significant bit clear
20517 if it requests element from the same 128-bit lane
20518 and MSB set if it requests element from the other 128-bit lane.
20519 The second mask will have the opposite values of the MSB,
20520 and additionally will have its 128-bit lanes swapped.
20521 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20522 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20523 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20524 stands for other 12 bytes. */
20525 /* The bit whether element is from the same lane or the other
20526 lane is bit 4, so shift it up by 3 to the MSB position. */
20530 /* Clear MSB bits from the mask just in case it had them set. */
20532 /* After this t1 will have MSB set for elements from other lane. */
20534 /* Clear bits other than MSB. */
20536 /* Or in the lower bits from mask into t3. */
20538 /* And invert MSB bits in t1, so MSB is set for elements from the same
20539 lane. */
20541 /* Swap 128-bit lanes in t3. */
20546 /* And or in the lower bits from mask into t1. */
20549 {
20550 /* Each of these shuffles will put 0s in places where
20551 element from the other 128-bit lane is needed, otherwise
20552 will shuffle in the requested value. */
20555 /* For t3 the 128-bit lanes are swapped again. */
20560 /* And oring both together leads to the result. */
20563 }
20566 /* Similarly to the above one_operand_shuffle code,
20567 just for repeated twice for each operand. merge_two:
20568 code will merge the two results together. */
20590 }
20591 }
20594 {
20595 /* The XOP VPPERM insn supports three inputs. By ignoring the
20596 one_operand_shuffle special case, we avoid creating another
20597 set of constant vectors in memory. */
20600 /* mask = mask & {2*w-1, ...} */
20602 }
20603 else
20604 {
20605 /* mask = mask & {w-1, ...} */
20607 }
20615 /* For non-QImode operations, convert the word permutation control
20616 into a byte permutation control. */
20618 {
20623 /* Convert mask to vector of chars. */
20626 /* Replicate each of the input bytes into byte positions:
20627 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20628 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20629 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20636 else
20639 /* Convert it into the byte positions by doing
20640 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20646 }
20648 /* The actual shuffle operations all operate on V16QImode. */
20654 {
20656 }
20658 {
20660 }
20661 else
20662 {
20666 /* Shuffle the two input vectors independently. */
20672 merge_two:
20673 /* Then merge them together. The key is whether any given control
20674 element contained a bit set that indicates the second word. */
20678 {
20679 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20680 more shuffle to convert the V2DI input mask into a V4SI
20681 input mask. At which point the masking that expand_int_vcond
20682 will work as desired. */
20690 }
20707 }
20708 }
20710 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20711 true if we should do zero extension, else sign extension. HIGH_P is
20712 true if we want the N/2 high elements, else the low elements. */
20714 void
20716 {
20718 rtx tmp;
20721 {
20727 {
20731 else
20734 extract
20740 else
20743 extract
20749 else
20752 extract
20758 else
20764 else
20770 else
20775 }
20778 {
20781 }
20783 {
20784 /* Shift higher 8 bytes to lower 8 bytes. */
20789 }
20790 else
20794 }
20795 else
20796 {
20800 {
20804 else
20810 else
20816 else
20821 }
20825 else
20830 }
20831 }
20833 /* Expand conditional increment or decrement using adb/sbb instructions.
20834 The default case using setcc followed by the conditional move can be
20835 done by generic code. */
20836 bool
20838 {
20840 rtx flags;
20842 rtx compare_op;
20860 {
20863 }
20866 {
20870 reverse_condition_maybe_unordered
20872 else
20874 }
20878 /* Construct either adc or sbb insn. */
20880 {
20882 {
20897 }
20898 }
20899 else
20900 {
20902 {
20917 }
20918 }
20922 }
20925 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20926 but works for floating pointer parameters and nonoffsetable memories.
20927 For pushes, it returns just stack offsets; the values will be saved
20928 in the right order. Maximally three parts are generated. */
20930 static int
20932 {
20937 else
20943 /* Optimize constant pool reference to immediates. This is used by fp
20944 moves, that force all constants to memory to allow combining. */
20946 {
20950 }
20953 {
20954 /* The only non-offsetable memories we handle are pushes. */
20963 }
20966 {
20968 /* Caution: if we looked through a constant pool memory above,
20969 the operand may actually have a different mode now. That's
20970 ok, since we want to pun this all the way back to an integer. */
20974 }
20977 {
20980 else
20981 {
20985 {
20989 }
20991 {
20996 }
20998 {
20999 REAL_VALUE_TYPE r;
21004 {
21011 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21012 long double may not be 80-bit. */
21021 }
21024 }
21025 else
21027 }
21028 }
21029 else
21030 {
21034 {
21037 {
21041 }
21043 {
21047 }
21049 {
21050 REAL_VALUE_TYPE r;
21056 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21059 = gen_int_mode
21062 DImode);
21063 else
21070 = gen_int_mode
21073 DImode);
21074 else
21076 }
21077 else
21079 }
21080 }
21083 }
21085 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21086 Return false when normal moves are needed; true when all required
21087 insns have been emitted. Operands 2-4 contain the input values
21088 int the correct order; operands 5-7 contain the output values. */
21090 void
21092 {
21100 /* The DFmode expanders may ask us to move double.
21101 For 64bit target this is single move. By hiding the fact
21102 here we simplify i386.md splitters. */
21104 {
21105 /* Optimize constant pool reference to immediates. This is used by
21106 fp moves, that force all constants to memory to allow combining. */
21113 {
21116 }
21117 else
21122 }
21124 /* The only non-offsettable memory we handle is push. */
21127 else
21134 /* When emitting push, take care for source operands on the stack. */
21137 {
21140 /* Compensate for the stack decrement by 4. */
21145 /* src_base refers to the stack pointer and is
21146 automatically decreased by emitted push. */
21150 }
21152 /* We need to do copy in the right order in case an address register
21153 of the source overlaps the destination. */
21155 {
21156 rtx tmp;
21159 {
21163 collisions++;
21164 }
21166 /* Collision in the middle part can be handled by reordering. */
21168 {
21171 }
21175 {
21177 {
21180 }
21181 else
21182 {
21185 }
21186 }
21188 /* If there are more collisions, we can't handle it by reordering.
21189 Do an lea to the last part and use only one colliding move. */
21191 {
21192 rtx base;
21198 /* Handle the case when the last part isn't valid for lea.
21199 Happens in 64-bit mode storing the 12-byte XFmode. */
21206 {
21209 }
21210 }
21211 }
21214 {
21216 {
21218 {
21223 }
21225 {
21228 }
21229 }
21230 else
21231 {
21232 /* In 64bit mode we don't have 32bit push available. In case this is
21233 register, it is OK - we will just use larger counterpart. We also
21234 retype memory - these comes from attempt to avoid REX prefix on
21235 moving of second half of TFmode value. */
21237 {
21239 {
21250 }
21254 }
21255 }
21259 }
21261 /* Choose correct order to not overwrite the source before it is copied. */
21271 {
21273 {
21276 }
21277 }
21278 else
21279 {
21281 {
21284 }
21285 }
21287 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21289 {
21298 }
21304 }
21306 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21307 left shift by a constant, either using a single shift or
21308 a sequence of add instructions. */
21310 static void
21312 {
21318 {
21322 }
21323 else
21324 {
21327 }
21328 }
21330 void
21332 {
21341 {
21346 {
21352 }
21353 else
21354 {
21362 }
21364 }
21371 {
21372 /* Assuming we've chosen a QImode capable registers, then 1 << N
21373 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21375 {
21391 }
21393 /* Otherwise, we can get the same results by manually performing
21394 a bit extract operation on bit 5/6, and then performing the two
21395 shifts. The two methods of getting 0/1 into low/high are exactly
21396 the same size. Avoiding the shift in the bit extract case helps
21397 pentium4 a bit; no one else seems to care much either way. */
21398 else
21399 {
21404 HOST_WIDE_INT bits;
21405 rtx x;
21408 {
21414 }
21415 else
21416 {
21422 }
21426 else
21434 }
21439 }
21442 {
21443 /* For -1 << N, we can avoid the shld instruction, because we
21444 know that we're shifting 0...31/63 ones into a -1. */
21448 else
21450 }
21451 else
21452 {
21460 }
21465 {
21471 }
21472 else
21473 {
21478 }
21479 }
21481 void
21483 {
21493 {
21498 {
21504 }
21506 {
21515 }
21516 else
21517 {
21525 }
21526 }
21527 else
21528 {
21540 {
21548 scratch));
21549 }
21550 else
21551 {
21556 }
21557 }
21558 }
21560 void
21562 {
21572 {
21577 {
21584 }
21585 else
21586 {
21594 }
21595 }
21596 else
21597 {
21609 {
21615 scratch));
21616 }
21617 else
21618 {
21623 }
21624 }
21625 }
21627 /* Predict just emitted jump instruction to be taken with probability PROB. */
21628 static void
21630 {
21634 }
21636 /* Helper function for the string operations below. Dest VARIABLE whether
21637 it is aligned to VALUE bytes. If true, jump to the label. */
21638 static rtx
21640 {
21645 else
21651 else
21654 }
21656 /* Adjust COUNTER by the VALUE. */
21657 static void
21659 {
21664 }
21666 /* Zero extend possibly SImode EXP to Pmode register. */
21667 rtx
21669 {
21671 }
21673 /* Divide COUNTREG by SCALE. */
21674 static rtx
21676 {
21677 rtx sc;
21689 }
21691 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21692 DImode for constant loop counts. */
21694 static enum machine_mode
21696 {
21704 }
21706 /* When SRCPTR is non-NULL, output simple loop to move memory
21707 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21708 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21709 equivalent loop to set memory by VALUE (supposed to be in MODE).
21711 The size is rounded down to whole number of chunk size moved at once.
21712 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21715 static void
21720 {
21725 rtx size;
21726 rtx x_addr;
21727 rtx y_addr;
21736 /* Those two should combine. */
21738 {
21742 }
21752 {
21756 /* When unrolling for chips that reorder memory reads and writes,
21757 we can save registers by using single temporary.
21758 Also using 4 temporaries is overkill in 32bit mode. */
21760 {
21762 {
21764 {
21765 destmem =
21767 srcmem =
21769 }
21771 }
21772 }
21773 else
21774 {
21778 {
21781 {
21782 srcmem =
21784 }
21786 }
21788 {
21790 {
21791 destmem =
21793 }
21795 }
21796 }
21797 }
21798 else
21800 {
21802 destmem =
21805 }
21815 {
21821 else
21823 }
21824 else
21832 {
21837 }
21839 }
21841 /* Output "rep; mov" instruction.
21842 Arguments have same meaning as for previous function */
21843 static void
21846 rtx count,
21848 {
21849 rtx destexp;
21850 rtx srcexp;
21851 rtx countreg;
21852 HOST_WIDE_INT rounded_count;
21854 /* If the size is known, it is shorter to use rep movs. */
21865 {
21872 }
21873 else
21874 {
21877 }
21879 {
21886 }
21887 else
21888 {
21893 }
21896 }
21898 /* Output "rep; stos" instruction.
21899 Arguments have same meaning as for previous function */
21900 static void
21903 rtx orig_value)
21904 {
21905 rtx destexp;
21906 rtx countreg;
21907 HOST_WIDE_INT rounded_count;
21914 {
21918 }
21919 else
21922 {
21927 }
21931 }
21933 static void
21936 {
21940 }
21942 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21943 static void
21946 {
21949 {
21954 {
21956 {
21959 }
21960 else
21963 }
21965 {
21968 else
21969 {
21972 }
21974 }
21976 {
21979 }
21981 {
21984 }
21986 {
21989 }
21991 }
21993 {
21999 }
22001 /* When there are stringops, we can cheaply increase dest and src pointers.
22002 Otherwise we save code size by maintaining offset (zero is readily
22003 available from preceding rep operation) and using x86 addressing modes.
22004 */
22006 {
22008 {
22015 }
22017 {
22024 }
22026 {
22033 }
22034 }
22035 else
22036 {
22038 rtx tmp;
22041 {
22052 }
22054 {
22067 }
22069 {
22078 }
22079 }
22080 }
22082 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22083 static void
22086 {
22087 count =
22093 }
22095 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22096 static void
22098 {
22099 rtx dest;
22102 {
22107 {
22109 {
22114 }
22115 else
22118 }
22120 {
22122 {
22125 }
22126 else
22127 {
22132 }
22134 }
22136 {
22140 }
22142 {
22146 }
22148 {
22152 }
22154 }
22156 {
22159 }
22161 {
22164 {
22168 }
22169 else
22170 {
22176 }
22179 }
22181 {
22184 {
22187 }
22188 else
22189 {
22193 }
22196 }
22198 {
22204 }
22206 {
22212 }
22214 {
22220 }
22221 }
22223 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22224 DESIRED_ALIGNMENT. */
22225 static void
22229 {
22231 {
22239 }
22241 {
22249 }
22251 {
22259 }
22261 }
22263 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22264 ALIGN_BYTES is how many bytes need to be copied. */
22265 static rtx
22268 {
22277 {
22282 }
22284 {
22295 }
22297 {
22303 {
22311 }
22314 }
22320 {
22332 }
22339 }
22341 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22342 DESIRED_ALIGNMENT. */
22343 static void
22346 {
22348 {
22355 }
22357 {
22364 }
22366 {
22373 }
22375 }
22377 /* Set enough from DST to align DST known to by aligned by ALIGN to
22378 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22379 static rtx
22382 {
22386 {
22391 }
22393 {
22400 }
22402 {
22409 }
22416 }
22418 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22419 static enum stringop_alg
22422 {
22425 /* Algorithms using the rep prefix want at least edi and ecx;
22426 additionally, memset wants eax and memcpy wants esi. Don't
22427 consider such algorithms if the user has appropriated those
22428 registers for their own purposes. */
22430 || (memset
22434 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22435 || (alg != rep_prefix_1_byte \
22436 && alg != rep_prefix_4_byte \
22437 && alg != rep_prefix_8_byte))
22440 /* Even if the string operation call is cold, we still might spend a lot
22441 of time processing large blocks. */
22446 else
22454 else
22458 /* rep; movq or rep; movl is the smallest variant. */
22460 {
22463 else
22465 }
22466 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22467 */
22471 {
22475 {
22476 /* We get here if the algorithms that were not libcall-based
22477 were rep-prefix based and we are unable to use rep prefixes
22478 based on global register usage. Break out of the loop and
22479 use the heuristic below. */
22483 {
22488 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22489 last non-libcall inline algorithm. */
22491 {
22492 /* When the current size is best to be copied by a libcall,
22493 but we are still forced to inline, run the heuristic below
22494 that will pick code for medium sized blocks. */
22498 }
22500 {
22503 }
22504 }
22505 }
22507 }
22508 /* When asked to inline the call anyway, try to pick meaningful choice.
22509 We look for maximal size of block that is faster to copy by hand and
22510 take blocks of at most of that size guessing that average size will
22511 be roughly half of the block.
22513 If this turns out to be bad, we might simply specify the preferred
22514 choice in ix86_costs. */
22517 {
22524 {
22531 }
22532 /* If there aren't any usable algorithms, then recursing on
22533 smaller sizes isn't going to find anything. Just return the
22534 simple byte-at-a-time copy loop. */
22536 {
22537 /* Pick something reasonable. */
22541 }
22550 }
22552 #undef ALG_USABLE_P
22553 }
22555 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22556 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22557 static int
22561 {
22564 {
22575 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22576 copying whole cacheline at once. */
22579 else
22583 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22584 copying whole cacheline at once. */
22587 else
22595 }
22604 }
22606 /* Return the smallest power of 2 greater than VAL. */
22607 static int
22609 {
22614 }
22616 /* Expand string move (memcpy) operation. Use i386 string operations
22617 when profitable. expand_setmem contains similar code. The code
22618 depends upon architecture, block size and alignment, but always has
22619 the same overall structure:
22621 1) Prologue guard: Conditional that jumps up to epilogues for small
22622 blocks that can be handled by epilogue alone. This is faster
22623 but also needed for correctness, since prologue assume the block
22624 is larger than the desired alignment.
22626 Optional dynamic check for size and libcall for large
22627 blocks is emitted here too, with -minline-stringops-dynamically.
22629 2) Prologue: copy first few bytes in order to get destination
22630 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22631 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22632 copied. We emit either a jump tree on power of two sized
22633 blocks, or a byte loop.
22635 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22636 with specified algorithm.
22638 4) Epilogue: code copying tail of the block that is too small to be
22639 handled by main body (or up to size guarded by prologue guard). */
22641 bool
22644 {
22645 rtx destreg;
22646 rtx srcreg;
22648 rtx tmp;
22662 /* i386 can do misaligned access on reasonably increased cost. */
22666 /* ALIGN is the minimum of destination and source alignment, but we care here
22667 just about destination alignment. */
22676 /* Make sure we don't need to care about overflow later on. */
22680 /* Step 0: Decide on preferred algorithm, desired alignment and
22681 size of chunks to be copied by main loop. */
22697 {
22722 }
22726 /* Step 1: Prologue guard. */
22728 /* Alignment code needs count to be in register. */
22730 {
22733 {
22734 align_bytes
22738 else
22740 }
22743 }
22746 /* Ensure that alignment prologue won't copy past end of block. */
22748 {
22750 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22751 Make sure it is power of 2. */
22755 {
22757 {
22758 /* If main algorithm works on QImode, no epilogue is needed.
22759 For small sizes just don't align anything. */
22762 else
22764 }
22765 }
22766 else
22767 {
22774 else
22776 }
22777 }
22779 /* Emit code to decide on runtime whether library call or inline should be
22780 used. */
22782 {
22784 {
22786 {
22790 }
22791 }
22792 else
22793 {
22802 }
22803 }
22805 /* Step 2: Alignment prologue. */
22808 {
22810 {
22811 /* Except for the first move in epilogue, we no longer know
22812 constant offset in aliasing info. It don't seems to worth
22813 the pain to maintain it for the first move, so throw away
22814 the info early. */
22818 desired_align);
22819 }
22820 else
22821 {
22822 /* If we know how many bytes need to be stored before dst is
22823 sufficiently aligned, maintain aliasing info accurately. */
22829 }
22835 {
22836 /* It is possible that we copied enough so the main loop will not
22837 execute. */
22847 else
22849 }
22850 }
22852 {
22857 }
22861 /* Step 3: Main loop. */
22864 {
22877 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22878 registers for 4 temporaries anyway. */
22881 expected_size);
22885 DImode);
22889 SImode);
22893 QImode);
22895 }
22896 /* Adjust properly the offset of src and dest memory for aliasing. */
22898 {
22903 }
22904 else
22905 {
22908 }
22910 /* Step 4: Epilogue to copy the remaining bytes. */
22911 epilogue:
22913 {
22914 /* When the main loop is done, COUNT_EXP might hold original count,
22915 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22916 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22917 bytes. Compensate if needed. */
22920 {
22921 tmp =
22924 OPTAB_DIRECT);
22927 }
22930 }
22934 epilogue_size_needed);
22938 }
22940 /* Helper function for memcpy. For QImode value 0xXY produce
22941 0xXYXYXYXY of wide specified by MODE. This is essentially
22942 a * 0x10101010, but we can do slightly better than
22943 synth_mult by unwinding the sequence by hand on CPUs with
22944 slow multiply. */
22945 static rtx
22947 {
22949 rtx tmp;
22956 {
22964 }
22973 nops--;
22978 {
22982 OPTAB_DIRECT);
22983 }
22984 else
22985 {
22991 else
22993 else
22994 {
22997 reg =
22999 }
23009 }
23010 }
23012 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23013 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23014 alignment from ALIGN to DESIRED_ALIGN. */
23015 static rtx
23017 {
23018 rtx promoted_val;
23027 else
23031 }
23033 /* Expand string clear operation (bzero). Use i386 string operations when
23034 profitable. See expand_movmem comment for explanation of individual
23035 steps performed. */
23036 bool
23039 {
23040 rtx destreg;
23042 rtx tmp;
23058 /* i386 can do misaligned access on reasonably increased cost. */
23067 /* Make sure we don't need to care about overflow later on. */
23071 /* Step 0: Decide on preferred algorithm, desired alignment and
23072 size of chunks to be copied by main loop. */
23087 {
23112 }
23115 /* Step 1: Prologue guard. */
23117 /* Alignment code needs count to be in register. */
23119 {
23122 {
23123 align_bytes
23127 else
23129 }
23131 {
23136 }
23137 }
23138 /* Do the cheap promotion to allow better CSE across the
23139 main loop and epilogue (ie one load of the big constant in the
23140 front of all code. */
23144 /* Ensure that alignment prologue won't copy past end of block. */
23146 {
23148 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23149 Make sure it is power of 2. */
23152 /* To improve performance of small blocks, we jump around the VAL
23153 promoting mode. This mean that if the promoted VAL is not constant,
23154 we might not use it in the epilogue and have to use byte
23155 loop variant. */
23159 {
23161 {
23162 /* If main algorithm works on QImode, no epilogue is needed.
23163 For small sizes just don't align anything. */
23166 else
23168 }
23169 }
23170 else
23171 {
23178 else
23180 }
23181 }
23183 {
23192 }
23194 /* Step 2: Alignment prologue. */
23196 /* Do the expensive promotion once we branched off the small blocks. */
23203 {
23205 {
23206 /* Except for the first move in epilogue, we no longer know
23207 constant offset in aliasing info. It don't seems to worth
23208 the pain to maintain it for the first move, so throw away
23209 the info early. */
23212 desired_align);
23213 }
23214 else
23215 {
23216 /* If we know how many bytes need to be stored before dst is
23217 sufficiently aligned, maintain aliasing info accurately. */
23223 }
23229 {
23230 /* It is possible that we copied enough so the main loop will not
23231 execute. */
23241 else
23243 }
23244 }
23246 {
23252 }
23256 /* Step 3: Main loop. */
23259 {
23287 }
23288 /* Adjust properly the offset of src and dest memory for aliasing. */
23292 else
23295 /* Step 4: Epilogue to copy the remaining bytes. */
23298 {
23299 /* When the main loop is done, COUNT_EXP might hold original count,
23300 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23301 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23302 bytes. Compensate if needed. */
23305 {
23306 tmp =
23309 OPTAB_DIRECT);
23312 }
23315 }
23316 epilogue:
23318 {
23321 epilogue_size_needed);
23322 else
23324 epilogue_size_needed);
23325 }
23329 }
23331 /* Expand the appropriate insns for doing strlen if not just doing
23332 repnz; scasb
23334 out = result, initialized with the start address
23335 align_rtx = alignment of the address.
23336 scratch = scratch register, initialized with the startaddress when
23337 not aligned, otherwise undefined
23339 This is just the body. It needs the initializations mentioned above and
23340 some address computing at the end. These things are done in i386.md. */
23342 static void
23344 {
23346 rtx tmp;
23351 rtx mem;
23354 rtx cmp;
23360 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23362 /* Is there a known alignment and is it less than 4? */
23364 {
23367 /* Is there a known alignment and is it not 2? */
23369 {
23373 /* Leave just the 3 lower bits. */
23383 }
23384 else
23385 {
23386 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23387 check if is aligned to 4 - byte. */
23394 }
23398 /* Now compare the bytes. */
23400 /* Compare the first n unaligned byte on a byte per byte basis. */
23404 /* Increment the address. */
23407 /* Not needed with an alignment of 2 */
23409 {
23413 end_0_label);
23418 }
23421 end_0_label);
23424 }
23426 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23427 align this loop. It gives only huge programs, but does not help to
23428 speed up. */
23435 /* This formula yields a nonzero result iff one of the bytes is zero.
23436 This saves three branches inside loop and many cycles. */
23444 align_4_label);
23447 {
23453 /* If zero is not in the first two bytes, move two bytes forward. */
23459 reg,
23460 tmpreg)));
23461 /* Emit lea manually to avoid clobbering of flags. */
23469 reg2,
23470 out)));
23471 }
23472 else
23473 {
23475 /* Is zero in the first two bytes? */
23482 pc_rtx);
23486 /* Not in the first two. Move two bytes forward. */
23492 }
23494 /* Avoid branch in fixing the byte. */
23502 }
23504 /* Expand strlen. */
23506 bool
23508 {
23511 /* The generic case of strlen expander is long. Avoid it's
23512 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23515 && !TARGET_INLINE_ALL_STRINGOPS
23525 {
23526 /* Well it seems that some optimizer does not combine a call like
23527 foo(strlen(bar), strlen(bar));
23528 when the move and the subtraction is done here. It does calculate
23529 the length just once when these instructions are done inside of
23530 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23531 often used and I use one fewer register for the lifetime of
23532 output_strlen_unroll() this is better. */
23538 /* strlensi_unroll_1 returns the address of the zero at the end of
23539 the string, like memchr(), so compute the length by subtracting
23540 the start address. */
23542 }
23543 else
23544 {
23545 rtx unspec;
23547 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23560 /* If .md starts supporting :P, this can be done in .md. */
23566 }
23568 }
23570 /* For given symbol (function) construct code to compute address of it's PLT
23571 entry in large x86-64 PIC model. */
23572 static rtx
23574 {
23587 }
23589 rtx
23591 rtx callarg2,
23593 {
23594 /* We need to represent that SI and DI registers are clobbered
23595 by SYSV calls. */
23601 };
23611 {
23612 #if TARGET_MACHO
23615 #endif
23616 }
23617 else
23618 {
23619 /* Static functions and indirect calls don't need the pic register. */
23624 }
23627 {
23631 }
23641 {
23644 }
23653 {
23657 }
23661 {
23665 UNSPEC_MS_TO_SYSV_CALL);
23673 }
23682 }
23684 /* Output the assembly for a call instruction. */
23688 {
23694 {
23697 /* SEH epilogue detection requires the indirect branch case
23698 to include REX.W. */
23701 else
23706 }
23708 /* SEH unwinding can require an extra nop to be emitted in several
23709 circumstances. Determine if we have one of those. */
23711 {
23712 rtx i;
23715 {
23716 /* If we get to another real insn, we don't need the nop. */
23720 /* If we get to the epilogue note, prevent a catch region from
23721 being adjacent to the standard epilogue sequence. If non-
23722 call-exceptions, we'll have done this during epilogue emission. */
23724 && !flag_non_call_exceptions
23726 {
23729 }
23730 }
23732 /* If we didn't find a real insn following the call, prevent the
23733 unwinder from looking into the next function. */
23736 }
23740 else
23749 }
23750 \f
23751 /* Clear stack slot assignments remembered from previous functions.
23752 This is called from INIT_EXPANDERS once before RTL is emitted for each
23753 function. */
23757 {
23765 }
23767 /* Return a MEM corresponding to a stack slot with mode MODE.
23768 Allocate a new slot if necessary.
23770 The RTL for a function can have several slots available: N is
23771 which slot to use. */
23773 rtx
23775 {
23792 }
23794 static void
23796 {
23802 }
23803 \f
23804 /* Calculate the length of the memory address in the instruction encoding.
23805 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23806 or other prefixes. We never generate addr32 prefix for LEA insn. */
23808 int
23810 {
23827 /* If this is not LEA instruction, add the length of addr32 prefix. */
23832 len++;
23846 /* Rule of thumb:
23847 - esp as the base always wants an index,
23848 - ebp as the base always wants a displacement,
23849 - r12 as the base always wants an index,
23850 - r13 as the base always wants a displacement. */
23852 /* Register Indirect. */
23854 {
23855 /* esp (for its index) and ebp (for its displacement) need
23856 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23857 code. */
23864 len++;
23865 }
23867 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23868 is not disp32, but disp32(%rip), so for disp32
23869 SIB byte is needed, unless print_operand_address
23870 optimizes it into disp32(%rip) or (%rip) is implied
23871 by UNSPEC. */
23873 {
23876 {
23892 len++;
23893 }
23894 }
23895 else
23896 {
23897 /* Find the length of the displacement constant. */
23899 {
23902 else
23904 }
23905 /* ebp always wants a displacement. Similarly r13. */
23907 len++;
23909 /* An index requires the two-byte modrm form.... */
23911 /* ...like esp (or r12), which always wants an index. */
23915 len++;
23916 }
23919 }
23921 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23922 is set, expect that insn have 8bit immediate alternative. */
23923 int
23925 {
23931 {
23936 {
23939 {
23951 }
23953 {
23956 }
23957 }
23959 {
23969 /* Immediates for DImode instructions are encoded
23970 as 32bit sign extended values. */
23976 }
23977 }
23979 }
23981 /* Compute default value for "length_address" attribute. */
23982 int
23984 {
23988 {
23999 }
24004 {
24007 {
24012 constraints++;
24015 ;
24016 /* Skip ignored operands. */
24019 }
24021 }
24023 }
24025 /* Compute default value for "length_vex" attribute. It includes
24026 2 or 3 byte VEX prefix and 1 opcode byte. */
24028 int
24030 {
24033 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24034 byte VEX prefix. */
24038 /* We can always use 2 byte VEX prefix in 32bit. */
24046 {
24047 /* REX.W bit uses 3 byte VEX prefix. */
24051 }
24052 else
24053 {
24054 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24058 }
24061 }
24062 \f
24063 /* Return the maximum number of instructions a cpu can issue. */
24065 static int
24067 {
24069 {
24095 }
24096 }
24098 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24099 by DEP_INSN and nothing set by DEP_INSN. */
24101 static bool
24103 {
24106 /* Simplify the test for uninteresting insns. */
24114 {
24117 }
24122 {
24125 }
24126 else
24132 /* This test is true if the dependent insn reads the flags but
24133 not any other potentially set register. */
24141 }
24143 /* Return true iff USE_INSN has a memory address with operands set by
24144 SET_INSN. */
24146 bool
24148 {
24153 {
24156 }
24158 }
24160 static int
24162 {
24168 /* Anti and output dependencies have zero cost on all CPUs. */
24174 /* If we can't recognize the insns, we can't really do anything. */
24182 {
24184 /* Address Generation Interlock adds a cycle of latency. */
24186 {
24197 }
24201 /* ??? Compares pair with jump/setcc. */
24205 /* Floating point stores require value to be ready one cycle earlier. */
24215 /* INT->FP conversion is expensive. */
24219 /* There is one cycle extra latency between an FP op and a store. */
24227 /* Show ability of reorder buffer to hide latency of load by executing
24228 in parallel with previous instruction in case
24229 previous instruction is not needed to compute the address. */
24232 {
24233 /* Claim moves to take one cycle, as core can issue one load
24234 at time and the next load can start cycle later. */
24239 cost--;
24240 }
24246 /* The esp dependency is resolved before the instruction is really
24247 finished. */
24252 /* INT->FP conversion is expensive. */
24256 /* Show ability of reorder buffer to hide latency of load by executing
24257 in parallel with previous instruction in case
24258 previous instruction is not needed to compute the address. */
24261 {
24262 /* Claim moves to take one cycle, as core can issue one load
24263 at time and the next load can start cycle later. */
24269 else
24271 }
24287 /* Show ability of reorder buffer to hide latency of load by executing
24288 in parallel with previous instruction in case
24289 previous instruction is not needed to compute the address. */
24292 {
24296 /* Because of the difference between the length of integer and
24297 floating unit pipeline preparation stages, the memory operands
24298 for floating point are cheaper.
24300 ??? For Athlon it the difference is most probably 2. */
24303 else
24308 else
24310 }
24314 }
24317 }
24319 /* How many alternative schedules to try. This should be as wide as the
24320 scheduling freedom in the DFA, but no wider. Making this value too
24321 large results extra work for the scheduler. */
24323 static int
24325 {
24327 {
24339 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24340 as many instructions can be executed on a cycle, i.e.,
24341 issue_rate. I wonder why tuning for many CPUs does not do this. */
24344 /* Don't use lookahead for pre-reload schedule to save compile time. */
24349 }
24350 }
24352 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24353 execution. It is applied if
24354 (1) IMUL instruction is on the top of list;
24355 (2) There exists the only producer of independent IMUL instruction in
24356 ready list;
24357 (3) Put found producer on the top of ready list.
24358 Returns issue rate. */
24360 static int
24363 {
24368 sd_iterator_def sd_it;
24369 dep_t dep;
24372 /* Set up issue rate. */
24375 /* Do reodering for Atom only. */
24378 /* Do not perform ready list reodering for pre-reload schedule pass. */
24381 /* Nothing to do if ready list contains only 1 instruction. */
24385 /* Check that IMUL instruction is on the top of ready list. */
24398 /* Search for producer of independent IMUL instruction. */
24400 {
24404 /* Skip IMUL instruction. */
24414 {
24415 rtx con;
24426 {
24427 sd_iterator_def sd_it1;
24428 dep_t dep1;
24429 /* Check if there is no other dependee for IMUL. */
24432 {
24433 rtx pro;
24439 }
24442 }
24443 }
24446 }
24454 /* Put IMUL producer (ready[index]) at the top of ready list. */
24461 }
24463 static bool
24466 /* Returns true if lhs of insn is HW function argument register and set up
24467 is_spilled to true if it is likely spilled HW register. */
24468 static bool
24470 {
24471 rtx dst;
24475 /* Call instructions are not movable, ignore it. */
24486 {
24487 /* Is it likely spilled HW register? */
24492 }
24494 }
24496 /* Add output dependencies for chain of function adjacent arguments if only
24497 there is a move to likely spilled HW register. Return first argument
24498 if at least one dependence was added or NULL otherwise. */
24499 static rtx
24501 {
24502 rtx insn;
24509 /* Find nearest to call argument passing instruction. */
24511 {
24520 }
24524 {
24531 {
24534 }
24536 {
24537 /* Add output depdendence between two function arguments if chain
24538 of output arguments contains likely spilled HW registers. */
24542 }
24543 else
24545 }
24549 }
24551 /* Add output or anti dependency from insn to first_arg to restrict its code
24552 motion. */
24553 static void
24555 {
24556 rtx set;
24557 rtx tmp;
24564 {
24565 /* Add output dependency to the first function argument. */
24568 }
24569 /* Add anti dependency. */
24571 }
24573 /* Avoid cross block motion of function argument through adding dependency
24574 from the first non-jump instruction in bb. */
24575 static void
24577 {
24581 {
24583 {
24586 {
24589 }
24590 }
24594 }
24595 }
24597 /* Hook for pre-reload schedule - avoid motion of function arguments
24598 passed in likely spilled HW registers. */
24599 static void
24601 {
24602 rtx insn;
24610 {
24613 {
24614 /* Add dependee for first argument to predecessors if only
24615 region contains more than one block. */
24619 /* Skip trivial regions and region head blocks that can have
24620 predecessors outside of region. */
24622 {
24623 edge e;
24624 edge_iterator ei;
24625 /* Assume that region is SCC, i.e. all immediate predecessors
24626 of non-head block are in the same region. */
24628 {
24629 /* Avoid creating of loop-carried dependencies through
24630 using topological odering in region. */
24633 }
24634 }
24638 }
24639 }
24642 }
24644 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24645 HW registers to maximum, to schedule them at soon as possible. These are
24646 moves from function argument registers at the top of the function entry
24647 and moves from function return value registers after call. */
24648 static int
24650 {
24651 rtx set;
24661 {
24668 }
24671 }
24673 /* Model decoder of Core 2/i7.
24674 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24675 track the instruction fetch block boundaries and make sure that long
24676 (9+ bytes) instructions are assigned to D0. */
24678 /* Maximum length of an insn that can be handled by
24679 a secondary decoder unit. '8' for Core 2/i7. */
24682 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24683 '16' for Core 2/i7. */
24686 /* Maximum number of instructions decoder can handle per cycle.
24687 '6' for Core 2/i7. */
24691 ix86_first_cycle_multipass_data_t;
24693 const_ix86_first_cycle_multipass_data_t;
24695 /* A variable to store target state across calls to max_issue within
24696 one cycle. */
24700 /* Initialize DATA. */
24701 static void
24703 {
24704 ix86_first_cycle_multipass_data_t data
24711 }
24713 /* Advancing the cycle; reset ifetch block counts. */
24714 static void
24716 {
24723 }
24727 /* Filter out insns from ready_try that the core will not be able to issue
24728 on current cycle due to decoder. */
24729 static void
24730 core2i7_first_cycle_multipass_filter_ready_try
24733 {
24735 {
24736 rtx insn;
24746 (!first_cycle_insn_p
24748 /* ... or it would not fit into the ifetch block ... */
24750 /* ... or the decoder is full already ... */
24752 /* ... mask the insn out. */
24753 {
24758 }
24759 }
24760 }
24762 /* Prepare for a new round of multipass lookahead scheduling. */
24763 static void
24766 {
24767 ix86_first_cycle_multipass_data_t data
24769 const_ix86_first_cycle_multipass_data_t prev_data
24772 /* Restore the state from the end of the previous round. */
24776 /* Filter instructions that cannot be issued on current cycle due to
24777 decoder restrictions. */
24779 first_cycle_insn_p);
24780 }
24782 /* INSN is being issued in current solution. Account for its impact on
24783 the decoder model. */
24784 static void
24787 {
24788 ix86_first_cycle_multipass_data_t data
24790 const_ix86_first_cycle_multipass_data_t prev_data
24800 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24802 {
24805 }
24807 {
24811 }
24814 /* Filter out insns from ready_try that the core will not be able to issue
24815 on current cycle due to decoder. */
24818 }
24820 /* Revert the effect on ready_try. */
24821 static void
24825 {
24826 const_ix86_first_cycle_multipass_data_t data
24829 sbitmap_iterator sbi;
24833 {
24835 }
24836 }
24838 /* Save the result of multipass lookahead scheduling for the next round. */
24839 static void
24841 {
24842 const_ix86_first_cycle_multipass_data_t data
24844 ix86_first_cycle_multipass_data_t next_data
24848 {
24851 }
24852 }
24854 /* Deallocate target data. */
24855 static void
24857 {
24858 ix86_first_cycle_multipass_data_t data
24862 {
24866 }
24867 }
24869 /* Prepare for scheduling pass. */
24870 static void
24874 {
24875 /* Install scheduling hooks for current CPU. Some of these hooks are used
24876 in time-critical parts of the scheduler, so we only set them up when
24877 they are actually used. */
24879 {
24883 /* Do not perform multipass scheduling for pre-reload schedule
24884 to save compile time. */
24886 {
24902 /* Set decoder parameters. */
24907 }
24908 /* ... Fall through ... */
24918 }
24919 }
24921 \f
24922 /* Compute the alignment given to a constant that is being placed in memory.
24923 EXP is the constant and ALIGN is the alignment that the object would
24924 ordinarily have.
24925 The value of this function is used instead of that alignment to align
24926 the object. */
24928 int
24930 {
24933 {
24938 }
24944 }
24946 /* Compute the alignment for a static variable.
24947 TYPE is the data type, and ALIGN is the alignment that
24948 the object would ordinarily have. The value of this function is used
24949 instead of that alignment to align the object. */
24951 int
24953 {
24964 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24965 to 16byte boundary. */
24967 {
24974 }
24977 {
24982 }
24984 {
24991 }
24996 {
25001 }
25004 {
25009 }
25012 }
25014 /* Compute the alignment for a local variable or a stack slot. EXP is
25015 the data type or decl itself, MODE is the widest mode available and
25016 ALIGN is the alignment that the object would ordinarily have. The
25017 value of this macro is used instead of that alignment to align the
25018 object. */
25020 unsigned int
25023 {
25027 {
25030 }
25031 else
25032 {
25035 }
25037 /* Don't do dynamic stack realignment for long long objects with
25038 -mpreferred-stack-boundary=2. */
25047 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25048 register in MODE. We will return the largest alignment of XF
25049 and DF. */
25051 {
25055 }
25057 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25058 to 16byte boundary. Exact wording is:
25060 An array uses the same alignment as its elements, except that a local or
25061 global array variable of length at least 16 bytes or
25062 a C99 variable-length array variable always has alignment of at least 16 bytes.
25064 This was added to allow use of aligned SSE instructions at arrays. This
25065 rule is meant for static storage (where compiler can not do the analysis
25066 by itself). We follow it for automatic variables only when convenient.
25067 We fully control everything in the function compiled and functions from
25068 other unit can not rely on the alignment.
25070 Exclude va_list type. It is the common case of local array where
25071 we can not benefit from the alignment. */
25074 {
25084 }
25086 {
25091 }
25093 {
25099 }
25104 {
25109 }
25112 {
25118 }
25120 }
25122 /* Compute the minimum required alignment for dynamic stack realignment
25123 purposes for a local variable, parameter or a stack slot. EXP is
25124 the data type or decl itself, MODE is its mode and ALIGN is the
25125 alignment that the object would ordinarily have. */
25127 unsigned int
25130 {
25134 {
25137 }
25138 else
25139 {
25142 }
25147 /* Don't do dynamic stack realignment for long long objects with
25148 -mpreferred-stack-boundary=2. */
25155 }
25156 \f
25157 /* Find a location for the static chain incoming to a nested function.
25158 This is a register, unless all free registers are used by arguments. */
25160 static rtx
25162 {
25169 {
25170 /* We always use R10 in 64-bit mode. */
25172 }
25173 else
25174 {
25175 tree fntype;
25178 /* By default in 32-bit mode we use ECX to pass the static chain. */
25184 {
25185 /* Fastcall functions use ecx/edx for arguments, which leaves
25186 us with EAX for the static chain.
25187 Thiscall functions use ecx for arguments, which also
25188 leaves us with EAX for the static chain. */
25190 }
25192 {
25193 /* Thiscall functions use ecx for arguments, which leaves
25194 us with EAX and EDX for the static chain.
25195 We are using for abi-compatibility EAX. */
25197 }
25199 {
25200 /* For regparm 3, we have no free call-clobbered registers in
25201 which to store the static chain. In order to implement this,
25202 we have the trampoline push the static chain to the stack.
25203 However, we can't push a value below the return address when
25204 we call the nested function directly, so we have to use an
25205 alternate entry point. For this we use ESI, and have the
25206 alternate entry point push ESI, so that things appear the
25207 same once we're executing the nested function. */
25209 {
25215 }
25217 }
25218 }
25221 }
25223 /* Emit RTL insns to initialize the variable parts of a trampoline.
25224 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25225 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25226 to be passed to the target function. */
25228 static void
25230 {
25238 {
25241 /* Load the function address to r11. Try to load address using
25242 the shorter movl instead of movabs. We may want to support
25243 movq for kernel mode, but kernel does not use trampolines at
25244 the moment. FNADDR is a 32bit address and may not be in
25245 DImode when ptr_mode == SImode. Always use movl in this
25246 case. */
25249 {
25258 }
25259 else
25260 {
25267 }
25269 /* Load static chain using movabs to r10. Use the shorter movl
25270 instead of movabs when ptr_mode == SImode. */
25272 {
25275 }
25276 else
25277 {
25280 }
25289 /* Jump to r11; the last (unused) byte is a nop, only there to
25290 pad the write out to a single 32-bit store. */
25294 }
25295 else
25296 {
25299 /* Depending on the static chain location, either load a register
25300 with a constant, or push the constant to the stack. All of the
25301 instructions are the same size. */
25304 {
25306 {
25313 }
25314 }
25315 else
25330 /* Compute offset from the end of the jmp to the target function.
25331 In the case in which the trampoline stores the static chain on
25332 the stack, we need to skip the first insn which pushes the
25333 (call-saved) register static chain; this push is 1 byte. */
25340 }
25344 #ifdef HAVE_ENABLE_EXECUTE_STACK
25345 #ifdef CHECK_EXECUTE_STACK_ENABLED
25347 #endif
25350 #endif
25351 }
25352 \f
25353 /* The following file contains several enumerations and data structures
25354 built from the definitions in i386-builtin-types.def. */
25358 /* Table for the ix86 builtin non-function types. */
25361 /* Retrieve an element from the above table, building some of
25362 the types lazily. */
25364 static tree
25366 {
25378 {
25386 }
25387 else
25388 {
25394 else
25402 }
25406 }
25408 /* Table for the ix86 builtin function types. */
25411 /* Retrieve an element from the above table, building some of
25412 the types lazily. */
25414 static tree
25416 {
25417 tree type;
25426 {
25434 {
25437 }
25440 }
25441 else
25442 {
25448 }
25452 }
25455 /* Codes for all the SSE/MMX builtins. */
25456 enum ix86_builtins
25457 {
25458 IX86_BUILTIN_ADDPS,
25459 IX86_BUILTIN_ADDSS,
25460 IX86_BUILTIN_DIVPS,
25461 IX86_BUILTIN_DIVSS,
25462 IX86_BUILTIN_MULPS,
25463 IX86_BUILTIN_MULSS,
25464 IX86_BUILTIN_SUBPS,
25465 IX86_BUILTIN_SUBSS,
25467 IX86_BUILTIN_CMPEQPS,
25468 IX86_BUILTIN_CMPLTPS,
25469 IX86_BUILTIN_CMPLEPS,
25470 IX86_BUILTIN_CMPGTPS,
25471 IX86_BUILTIN_CMPGEPS,
25472 IX86_BUILTIN_CMPNEQPS,
25473 IX86_BUILTIN_CMPNLTPS,
25474 IX86_BUILTIN_CMPNLEPS,
25475 IX86_BUILTIN_CMPNGTPS,
25476 IX86_BUILTIN_CMPNGEPS,
25477 IX86_BUILTIN_CMPORDPS,
25478 IX86_BUILTIN_CMPUNORDPS,
25479 IX86_BUILTIN_CMPEQSS,
25480 IX86_BUILTIN_CMPLTSS,
25481 IX86_BUILTIN_CMPLESS,
25482 IX86_BUILTIN_CMPNEQSS,
25483 IX86_BUILTIN_CMPNLTSS,
25484 IX86_BUILTIN_CMPNLESS,
25485 IX86_BUILTIN_CMPNGTSS,
25486 IX86_BUILTIN_CMPNGESS,
25487 IX86_BUILTIN_CMPORDSS,
25488 IX86_BUILTIN_CMPUNORDSS,
25490 IX86_BUILTIN_COMIEQSS,
25491 IX86_BUILTIN_COMILTSS,
25492 IX86_BUILTIN_COMILESS,
25493 IX86_BUILTIN_COMIGTSS,
25494 IX86_BUILTIN_COMIGESS,
25495 IX86_BUILTIN_COMINEQSS,
25496 IX86_BUILTIN_UCOMIEQSS,
25497 IX86_BUILTIN_UCOMILTSS,
25498 IX86_BUILTIN_UCOMILESS,
25499 IX86_BUILTIN_UCOMIGTSS,
25500 IX86_BUILTIN_UCOMIGESS,
25501 IX86_BUILTIN_UCOMINEQSS,
25503 IX86_BUILTIN_CVTPI2PS,
25504 IX86_BUILTIN_CVTPS2PI,
25505 IX86_BUILTIN_CVTSI2SS,
25506 IX86_BUILTIN_CVTSI642SS,
25507 IX86_BUILTIN_CVTSS2SI,
25508 IX86_BUILTIN_CVTSS2SI64,
25509 IX86_BUILTIN_CVTTPS2PI,
25510 IX86_BUILTIN_CVTTSS2SI,
25511 IX86_BUILTIN_CVTTSS2SI64,
25513 IX86_BUILTIN_MAXPS,
25514 IX86_BUILTIN_MAXSS,
25515 IX86_BUILTIN_MINPS,
25516 IX86_BUILTIN_MINSS,
25518 IX86_BUILTIN_LOADUPS,
25519 IX86_BUILTIN_STOREUPS,
25520 IX86_BUILTIN_MOVSS,
25522 IX86_BUILTIN_MOVHLPS,
25523 IX86_BUILTIN_MOVLHPS,
25524 IX86_BUILTIN_LOADHPS,
25525 IX86_BUILTIN_LOADLPS,
25526 IX86_BUILTIN_STOREHPS,
25527 IX86_BUILTIN_STORELPS,
25529 IX86_BUILTIN_MASKMOVQ,
25530 IX86_BUILTIN_MOVMSKPS,
25531 IX86_BUILTIN_PMOVMSKB,
25533 IX86_BUILTIN_MOVNTPS,
25534 IX86_BUILTIN_MOVNTQ,
25536 IX86_BUILTIN_LOADDQU,
25537 IX86_BUILTIN_STOREDQU,
25539 IX86_BUILTIN_PACKSSWB,
25540 IX86_BUILTIN_PACKSSDW,
25541 IX86_BUILTIN_PACKUSWB,
25543 IX86_BUILTIN_PADDB,
25544 IX86_BUILTIN_PADDW,
25545 IX86_BUILTIN_PADDD,
25546 IX86_BUILTIN_PADDQ,
25547 IX86_BUILTIN_PADDSB,
25548 IX86_BUILTIN_PADDSW,
25549 IX86_BUILTIN_PADDUSB,
25550 IX86_BUILTIN_PADDUSW,
25551 IX86_BUILTIN_PSUBB,
25552 IX86_BUILTIN_PSUBW,
25553 IX86_BUILTIN_PSUBD,
25554 IX86_BUILTIN_PSUBQ,
25555 IX86_BUILTIN_PSUBSB,
25556 IX86_BUILTIN_PSUBSW,
25557 IX86_BUILTIN_PSUBUSB,
25558 IX86_BUILTIN_PSUBUSW,
25560 IX86_BUILTIN_PAND,
25561 IX86_BUILTIN_PANDN,
25562 IX86_BUILTIN_POR,
25563 IX86_BUILTIN_PXOR,
25565 IX86_BUILTIN_PAVGB,
25566 IX86_BUILTIN_PAVGW,
25568 IX86_BUILTIN_PCMPEQB,
25569 IX86_BUILTIN_PCMPEQW,
25570 IX86_BUILTIN_PCMPEQD,
25571 IX86_BUILTIN_PCMPGTB,
25572 IX86_BUILTIN_PCMPGTW,
25573 IX86_BUILTIN_PCMPGTD,
25575 IX86_BUILTIN_PMADDWD,
25577 IX86_BUILTIN_PMAXSW,
25578 IX86_BUILTIN_PMAXUB,
25579 IX86_BUILTIN_PMINSW,
25580 IX86_BUILTIN_PMINUB,
25582 IX86_BUILTIN_PMULHUW,
25583 IX86_BUILTIN_PMULHW,
25584 IX86_BUILTIN_PMULLW,
25586 IX86_BUILTIN_PSADBW,
25587 IX86_BUILTIN_PSHUFW,
25589 IX86_BUILTIN_PSLLW,
25590 IX86_BUILTIN_PSLLD,
25591 IX86_BUILTIN_PSLLQ,
25592 IX86_BUILTIN_PSRAW,
25593 IX86_BUILTIN_PSRAD,
25594 IX86_BUILTIN_PSRLW,
25595 IX86_BUILTIN_PSRLD,
25596 IX86_BUILTIN_PSRLQ,
25597 IX86_BUILTIN_PSLLWI,
25598 IX86_BUILTIN_PSLLDI,
25599 IX86_BUILTIN_PSLLQI,
25600 IX86_BUILTIN_PSRAWI,
25601 IX86_BUILTIN_PSRADI,
25602 IX86_BUILTIN_PSRLWI,
25603 IX86_BUILTIN_PSRLDI,
25604 IX86_BUILTIN_PSRLQI,
25606 IX86_BUILTIN_PUNPCKHBW,
25607 IX86_BUILTIN_PUNPCKHWD,
25608 IX86_BUILTIN_PUNPCKHDQ,
25609 IX86_BUILTIN_PUNPCKLBW,
25610 IX86_BUILTIN_PUNPCKLWD,
25611 IX86_BUILTIN_PUNPCKLDQ,
25613 IX86_BUILTIN_SHUFPS,
25615 IX86_BUILTIN_RCPPS,
25616 IX86_BUILTIN_RCPSS,
25617 IX86_BUILTIN_RSQRTPS,
25618 IX86_BUILTIN_RSQRTPS_NR,
25619 IX86_BUILTIN_RSQRTSS,
25620 IX86_BUILTIN_RSQRTF,
25621 IX86_BUILTIN_SQRTPS,
25622 IX86_BUILTIN_SQRTPS_NR,
25623 IX86_BUILTIN_SQRTSS,
25625 IX86_BUILTIN_UNPCKHPS,
25626 IX86_BUILTIN_UNPCKLPS,
25628 IX86_BUILTIN_ANDPS,
25629 IX86_BUILTIN_ANDNPS,
25630 IX86_BUILTIN_ORPS,
25631 IX86_BUILTIN_XORPS,
25633 IX86_BUILTIN_EMMS,
25634 IX86_BUILTIN_LDMXCSR,
25635 IX86_BUILTIN_STMXCSR,
25636 IX86_BUILTIN_SFENCE,
25638 IX86_BUILTIN_FXSAVE,
25639 IX86_BUILTIN_FXRSTOR,
25640 IX86_BUILTIN_FXSAVE64,
25641 IX86_BUILTIN_FXRSTOR64,
25643 IX86_BUILTIN_XSAVE,
25644 IX86_BUILTIN_XRSTOR,
25645 IX86_BUILTIN_XSAVE64,
25646 IX86_BUILTIN_XRSTOR64,
25648 IX86_BUILTIN_XSAVEOPT,
25649 IX86_BUILTIN_XSAVEOPT64,
25651 /* 3DNow! Original */
25652 IX86_BUILTIN_FEMMS,
25653 IX86_BUILTIN_PAVGUSB,
25654 IX86_BUILTIN_PF2ID,
25655 IX86_BUILTIN_PFACC,
25656 IX86_BUILTIN_PFADD,
25657 IX86_BUILTIN_PFCMPEQ,
25658 IX86_BUILTIN_PFCMPGE,
25659 IX86_BUILTIN_PFCMPGT,
25660 IX86_BUILTIN_PFMAX,
25661 IX86_BUILTIN_PFMIN,
25662 IX86_BUILTIN_PFMUL,
25663 IX86_BUILTIN_PFRCP,
25664 IX86_BUILTIN_PFRCPIT1,
25665 IX86_BUILTIN_PFRCPIT2,
25666 IX86_BUILTIN_PFRSQIT1,
25667 IX86_BUILTIN_PFRSQRT,
25668 IX86_BUILTIN_PFSUB,
25669 IX86_BUILTIN_PFSUBR,
25670 IX86_BUILTIN_PI2FD,
25671 IX86_BUILTIN_PMULHRW,
25673 /* 3DNow! Athlon Extensions */
25674 IX86_BUILTIN_PF2IW,
25675 IX86_BUILTIN_PFNACC,
25676 IX86_BUILTIN_PFPNACC,
25677 IX86_BUILTIN_PI2FW,
25678 IX86_BUILTIN_PSWAPDSI,
25679 IX86_BUILTIN_PSWAPDSF,
25681 /* SSE2 */
25682 IX86_BUILTIN_ADDPD,
25683 IX86_BUILTIN_ADDSD,
25684 IX86_BUILTIN_DIVPD,
25685 IX86_BUILTIN_DIVSD,
25686 IX86_BUILTIN_MULPD,
25687 IX86_BUILTIN_MULSD,
25688 IX86_BUILTIN_SUBPD,
25689 IX86_BUILTIN_SUBSD,
25691 IX86_BUILTIN_CMPEQPD,
25692 IX86_BUILTIN_CMPLTPD,
25693 IX86_BUILTIN_CMPLEPD,
25694 IX86_BUILTIN_CMPGTPD,
25695 IX86_BUILTIN_CMPGEPD,
25696 IX86_BUILTIN_CMPNEQPD,
25697 IX86_BUILTIN_CMPNLTPD,
25698 IX86_BUILTIN_CMPNLEPD,
25699 IX86_BUILTIN_CMPNGTPD,
25700 IX86_BUILTIN_CMPNGEPD,
25701 IX86_BUILTIN_CMPORDPD,
25702 IX86_BUILTIN_CMPUNORDPD,
25703 IX86_BUILTIN_CMPEQSD,
25704 IX86_BUILTIN_CMPLTSD,
25705 IX86_BUILTIN_CMPLESD,
25706 IX86_BUILTIN_CMPNEQSD,
25707 IX86_BUILTIN_CMPNLTSD,
25708 IX86_BUILTIN_CMPNLESD,
25709 IX86_BUILTIN_CMPORDSD,
25710 IX86_BUILTIN_CMPUNORDSD,
25712 IX86_BUILTIN_COMIEQSD,
25713 IX86_BUILTIN_COMILTSD,
25714 IX86_BUILTIN_COMILESD,
25715 IX86_BUILTIN_COMIGTSD,
25716 IX86_BUILTIN_COMIGESD,
25717 IX86_BUILTIN_COMINEQSD,
25718 IX86_BUILTIN_UCOMIEQSD,
25719 IX86_BUILTIN_UCOMILTSD,
25720 IX86_BUILTIN_UCOMILESD,
25721 IX86_BUILTIN_UCOMIGTSD,
25722 IX86_BUILTIN_UCOMIGESD,
25723 IX86_BUILTIN_UCOMINEQSD,
25725 IX86_BUILTIN_MAXPD,
25726 IX86_BUILTIN_MAXSD,
25727 IX86_BUILTIN_MINPD,
25728 IX86_BUILTIN_MINSD,
25730 IX86_BUILTIN_ANDPD,
25731 IX86_BUILTIN_ANDNPD,
25732 IX86_BUILTIN_ORPD,
25733 IX86_BUILTIN_XORPD,
25735 IX86_BUILTIN_SQRTPD,
25736 IX86_BUILTIN_SQRTSD,
25738 IX86_BUILTIN_UNPCKHPD,
25739 IX86_BUILTIN_UNPCKLPD,
25741 IX86_BUILTIN_SHUFPD,
25743 IX86_BUILTIN_LOADUPD,
25744 IX86_BUILTIN_STOREUPD,
25745 IX86_BUILTIN_MOVSD,
25747 IX86_BUILTIN_LOADHPD,
25748 IX86_BUILTIN_LOADLPD,
25750 IX86_BUILTIN_CVTDQ2PD,
25751 IX86_BUILTIN_CVTDQ2PS,
25753 IX86_BUILTIN_CVTPD2DQ,
25754 IX86_BUILTIN_CVTPD2PI,
25755 IX86_BUILTIN_CVTPD2PS,
25756 IX86_BUILTIN_CVTTPD2DQ,
25757 IX86_BUILTIN_CVTTPD2PI,
25759 IX86_BUILTIN_CVTPI2PD,
25760 IX86_BUILTIN_CVTSI2SD,
25761 IX86_BUILTIN_CVTSI642SD,
25763 IX86_BUILTIN_CVTSD2SI,
25764 IX86_BUILTIN_CVTSD2SI64,
25765 IX86_BUILTIN_CVTSD2SS,
25766 IX86_BUILTIN_CVTSS2SD,
25767 IX86_BUILTIN_CVTTSD2SI,
25768 IX86_BUILTIN_CVTTSD2SI64,
25770 IX86_BUILTIN_CVTPS2DQ,
25771 IX86_BUILTIN_CVTPS2PD,
25772 IX86_BUILTIN_CVTTPS2DQ,
25774 IX86_BUILTIN_MOVNTI,
25775 IX86_BUILTIN_MOVNTI64,
25776 IX86_BUILTIN_MOVNTPD,
25777 IX86_BUILTIN_MOVNTDQ,
25779 IX86_BUILTIN_MOVQ128,
25781 /* SSE2 MMX */
25782 IX86_BUILTIN_MASKMOVDQU,
25783 IX86_BUILTIN_MOVMSKPD,
25784 IX86_BUILTIN_PMOVMSKB128,
25786 IX86_BUILTIN_PACKSSWB128,
25787 IX86_BUILTIN_PACKSSDW128,
25788 IX86_BUILTIN_PACKUSWB128,
25790 IX86_BUILTIN_PADDB128,
25791 IX86_BUILTIN_PADDW128,
25792 IX86_BUILTIN_PADDD128,
25793 IX86_BUILTIN_PADDQ128,
25794 IX86_BUILTIN_PADDSB128,
25795 IX86_BUILTIN_PADDSW128,
25796 IX86_BUILTIN_PADDUSB128,
25797 IX86_BUILTIN_PADDUSW128,
25798 IX86_BUILTIN_PSUBB128,
25799 IX86_BUILTIN_PSUBW128,
25800 IX86_BUILTIN_PSUBD128,
25801 IX86_BUILTIN_PSUBQ128,
25802 IX86_BUILTIN_PSUBSB128,
25803 IX86_BUILTIN_PSUBSW128,
25804 IX86_BUILTIN_PSUBUSB128,
25805 IX86_BUILTIN_PSUBUSW128,
25807 IX86_BUILTIN_PAND128,
25808 IX86_BUILTIN_PANDN128,
25809 IX86_BUILTIN_POR128,
25810 IX86_BUILTIN_PXOR128,
25812 IX86_BUILTIN_PAVGB128,
25813 IX86_BUILTIN_PAVGW128,
25815 IX86_BUILTIN_PCMPEQB128,
25816 IX86_BUILTIN_PCMPEQW128,
25817 IX86_BUILTIN_PCMPEQD128,
25818 IX86_BUILTIN_PCMPGTB128,
25819 IX86_BUILTIN_PCMPGTW128,
25820 IX86_BUILTIN_PCMPGTD128,
25822 IX86_BUILTIN_PMADDWD128,
25824 IX86_BUILTIN_PMAXSW128,
25825 IX86_BUILTIN_PMAXUB128,
25826 IX86_BUILTIN_PMINSW128,
25827 IX86_BUILTIN_PMINUB128,
25829 IX86_BUILTIN_PMULUDQ,
25830 IX86_BUILTIN_PMULUDQ128,
25831 IX86_BUILTIN_PMULHUW128,
25832 IX86_BUILTIN_PMULHW128,
25833 IX86_BUILTIN_PMULLW128,
25835 IX86_BUILTIN_PSADBW128,
25836 IX86_BUILTIN_PSHUFHW,
25837 IX86_BUILTIN_PSHUFLW,
25838 IX86_BUILTIN_PSHUFD,
25840 IX86_BUILTIN_PSLLDQI128,
25841 IX86_BUILTIN_PSLLWI128,
25842 IX86_BUILTIN_PSLLDI128,
25843 IX86_BUILTIN_PSLLQI128,
25844 IX86_BUILTIN_PSRAWI128,
25845 IX86_BUILTIN_PSRADI128,
25846 IX86_BUILTIN_PSRLDQI128,
25847 IX86_BUILTIN_PSRLWI128,
25848 IX86_BUILTIN_PSRLDI128,
25849 IX86_BUILTIN_PSRLQI128,
25851 IX86_BUILTIN_PSLLDQ128,
25852 IX86_BUILTIN_PSLLW128,
25853 IX86_BUILTIN_PSLLD128,
25854 IX86_BUILTIN_PSLLQ128,
25855 IX86_BUILTIN_PSRAW128,
25856 IX86_BUILTIN_PSRAD128,
25857 IX86_BUILTIN_PSRLW128,
25858 IX86_BUILTIN_PSRLD128,
25859 IX86_BUILTIN_PSRLQ128,
25861 IX86_BUILTIN_PUNPCKHBW128,
25862 IX86_BUILTIN_PUNPCKHWD128,
25863 IX86_BUILTIN_PUNPCKHDQ128,
25864 IX86_BUILTIN_PUNPCKHQDQ128,
25865 IX86_BUILTIN_PUNPCKLBW128,
25866 IX86_BUILTIN_PUNPCKLWD128,
25867 IX86_BUILTIN_PUNPCKLDQ128,
25868 IX86_BUILTIN_PUNPCKLQDQ128,
25870 IX86_BUILTIN_CLFLUSH,
25871 IX86_BUILTIN_MFENCE,
25872 IX86_BUILTIN_LFENCE,
25873 IX86_BUILTIN_PAUSE,
25875 IX86_BUILTIN_BSRSI,
25876 IX86_BUILTIN_BSRDI,
25877 IX86_BUILTIN_RDPMC,
25878 IX86_BUILTIN_RDTSC,
25879 IX86_BUILTIN_RDTSCP,
25880 IX86_BUILTIN_ROLQI,
25881 IX86_BUILTIN_ROLHI,
25882 IX86_BUILTIN_RORQI,
25883 IX86_BUILTIN_RORHI,
25885 /* SSE3. */
25886 IX86_BUILTIN_ADDSUBPS,
25887 IX86_BUILTIN_HADDPS,
25888 IX86_BUILTIN_HSUBPS,
25889 IX86_BUILTIN_MOVSHDUP,
25890 IX86_BUILTIN_MOVSLDUP,
25891 IX86_BUILTIN_ADDSUBPD,
25892 IX86_BUILTIN_HADDPD,
25893 IX86_BUILTIN_HSUBPD,
25894 IX86_BUILTIN_LDDQU,
25896 IX86_BUILTIN_MONITOR,
25897 IX86_BUILTIN_MWAIT,
25899 /* SSSE3. */
25900 IX86_BUILTIN_PHADDW,
25901 IX86_BUILTIN_PHADDD,
25902 IX86_BUILTIN_PHADDSW,
25903 IX86_BUILTIN_PHSUBW,
25904 IX86_BUILTIN_PHSUBD,
25905 IX86_BUILTIN_PHSUBSW,
25906 IX86_BUILTIN_PMADDUBSW,
25907 IX86_BUILTIN_PMULHRSW,
25908 IX86_BUILTIN_PSHUFB,
25909 IX86_BUILTIN_PSIGNB,
25910 IX86_BUILTIN_PSIGNW,
25911 IX86_BUILTIN_PSIGND,
25912 IX86_BUILTIN_PALIGNR,
25913 IX86_BUILTIN_PABSB,
25914 IX86_BUILTIN_PABSW,
25915 IX86_BUILTIN_PABSD,
25917 IX86_BUILTIN_PHADDW128,
25918 IX86_BUILTIN_PHADDD128,
25919 IX86_BUILTIN_PHADDSW128,
25920 IX86_BUILTIN_PHSUBW128,
25921 IX86_BUILTIN_PHSUBD128,
25922 IX86_BUILTIN_PHSUBSW128,
25923 IX86_BUILTIN_PMADDUBSW128,
25924 IX86_BUILTIN_PMULHRSW128,
25925 IX86_BUILTIN_PSHUFB128,
25926 IX86_BUILTIN_PSIGNB128,
25927 IX86_BUILTIN_PSIGNW128,
25928 IX86_BUILTIN_PSIGND128,
25929 IX86_BUILTIN_PALIGNR128,
25930 IX86_BUILTIN_PABSB128,
25931 IX86_BUILTIN_PABSW128,
25932 IX86_BUILTIN_PABSD128,
25934 /* AMDFAM10 - SSE4A New Instructions. */
25935 IX86_BUILTIN_MOVNTSD,
25936 IX86_BUILTIN_MOVNTSS,
25937 IX86_BUILTIN_EXTRQI,
25938 IX86_BUILTIN_EXTRQ,
25939 IX86_BUILTIN_INSERTQI,
25940 IX86_BUILTIN_INSERTQ,
25942 /* SSE4.1. */
25943 IX86_BUILTIN_BLENDPD,
25944 IX86_BUILTIN_BLENDPS,
25945 IX86_BUILTIN_BLENDVPD,
25946 IX86_BUILTIN_BLENDVPS,
25947 IX86_BUILTIN_PBLENDVB128,
25948 IX86_BUILTIN_PBLENDW128,
25950 IX86_BUILTIN_DPPD,
25951 IX86_BUILTIN_DPPS,
25953 IX86_BUILTIN_INSERTPS128,
25955 IX86_BUILTIN_MOVNTDQA,
25956 IX86_BUILTIN_MPSADBW128,
25957 IX86_BUILTIN_PACKUSDW128,
25958 IX86_BUILTIN_PCMPEQQ,
25959 IX86_BUILTIN_PHMINPOSUW128,
25961 IX86_BUILTIN_PMAXSB128,
25962 IX86_BUILTIN_PMAXSD128,
25963 IX86_BUILTIN_PMAXUD128,
25964 IX86_BUILTIN_PMAXUW128,
25966 IX86_BUILTIN_PMINSB128,
25967 IX86_BUILTIN_PMINSD128,
25968 IX86_BUILTIN_PMINUD128,
25969 IX86_BUILTIN_PMINUW128,
25971 IX86_BUILTIN_PMOVSXBW128,
25972 IX86_BUILTIN_PMOVSXBD128,
25973 IX86_BUILTIN_PMOVSXBQ128,
25974 IX86_BUILTIN_PMOVSXWD128,
25975 IX86_BUILTIN_PMOVSXWQ128,
25976 IX86_BUILTIN_PMOVSXDQ128,
25978 IX86_BUILTIN_PMOVZXBW128,
25979 IX86_BUILTIN_PMOVZXBD128,
25980 IX86_BUILTIN_PMOVZXBQ128,
25981 IX86_BUILTIN_PMOVZXWD128,
25982 IX86_BUILTIN_PMOVZXWQ128,
25983 IX86_BUILTIN_PMOVZXDQ128,
25985 IX86_BUILTIN_PMULDQ128,
25986 IX86_BUILTIN_PMULLD128,
25988 IX86_BUILTIN_ROUNDSD,
25989 IX86_BUILTIN_ROUNDSS,
25991 IX86_BUILTIN_ROUNDPD,
25992 IX86_BUILTIN_ROUNDPS,
25994 IX86_BUILTIN_FLOORPD,
25995 IX86_BUILTIN_CEILPD,
25996 IX86_BUILTIN_TRUNCPD,
25997 IX86_BUILTIN_RINTPD,
25998 IX86_BUILTIN_ROUNDPD_AZ,
26000 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26001 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26002 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26004 IX86_BUILTIN_FLOORPS,
26005 IX86_BUILTIN_CEILPS,
26006 IX86_BUILTIN_TRUNCPS,
26007 IX86_BUILTIN_RINTPS,
26008 IX86_BUILTIN_ROUNDPS_AZ,
26010 IX86_BUILTIN_FLOORPS_SFIX,
26011 IX86_BUILTIN_CEILPS_SFIX,
26012 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26014 IX86_BUILTIN_PTESTZ,
26015 IX86_BUILTIN_PTESTC,
26016 IX86_BUILTIN_PTESTNZC,
26018 IX86_BUILTIN_VEC_INIT_V2SI,
26019 IX86_BUILTIN_VEC_INIT_V4HI,
26020 IX86_BUILTIN_VEC_INIT_V8QI,
26021 IX86_BUILTIN_VEC_EXT_V2DF,
26022 IX86_BUILTIN_VEC_EXT_V2DI,
26023 IX86_BUILTIN_VEC_EXT_V4SF,
26024 IX86_BUILTIN_VEC_EXT_V4SI,
26025 IX86_BUILTIN_VEC_EXT_V8HI,
26026 IX86_BUILTIN_VEC_EXT_V2SI,
26027 IX86_BUILTIN_VEC_EXT_V4HI,
26028 IX86_BUILTIN_VEC_EXT_V16QI,
26029 IX86_BUILTIN_VEC_SET_V2DI,
26030 IX86_BUILTIN_VEC_SET_V4SF,
26031 IX86_BUILTIN_VEC_SET_V4SI,
26032 IX86_BUILTIN_VEC_SET_V8HI,
26033 IX86_BUILTIN_VEC_SET_V4HI,
26034 IX86_BUILTIN_VEC_SET_V16QI,
26036 IX86_BUILTIN_VEC_PACK_SFIX,
26037 IX86_BUILTIN_VEC_PACK_SFIX256,
26039 /* SSE4.2. */
26040 IX86_BUILTIN_CRC32QI,
26041 IX86_BUILTIN_CRC32HI,
26042 IX86_BUILTIN_CRC32SI,
26043 IX86_BUILTIN_CRC32DI,
26045 IX86_BUILTIN_PCMPESTRI128,
26046 IX86_BUILTIN_PCMPESTRM128,
26047 IX86_BUILTIN_PCMPESTRA128,
26048 IX86_BUILTIN_PCMPESTRC128,
26049 IX86_BUILTIN_PCMPESTRO128,
26050 IX86_BUILTIN_PCMPESTRS128,
26051 IX86_BUILTIN_PCMPESTRZ128,
26052 IX86_BUILTIN_PCMPISTRI128,
26053 IX86_BUILTIN_PCMPISTRM128,
26054 IX86_BUILTIN_PCMPISTRA128,
26055 IX86_BUILTIN_PCMPISTRC128,
26056 IX86_BUILTIN_PCMPISTRO128,
26057 IX86_BUILTIN_PCMPISTRS128,
26058 IX86_BUILTIN_PCMPISTRZ128,
26060 IX86_BUILTIN_PCMPGTQ,
26062 /* AES instructions */
26063 IX86_BUILTIN_AESENC128,
26064 IX86_BUILTIN_AESENCLAST128,
26065 IX86_BUILTIN_AESDEC128,
26066 IX86_BUILTIN_AESDECLAST128,
26067 IX86_BUILTIN_AESIMC128,
26068 IX86_BUILTIN_AESKEYGENASSIST128,
26070 /* PCLMUL instruction */
26071 IX86_BUILTIN_PCLMULQDQ128,
26073 /* AVX */
26074 IX86_BUILTIN_ADDPD256,
26075 IX86_BUILTIN_ADDPS256,
26076 IX86_BUILTIN_ADDSUBPD256,
26077 IX86_BUILTIN_ADDSUBPS256,
26078 IX86_BUILTIN_ANDPD256,
26079 IX86_BUILTIN_ANDPS256,
26080 IX86_BUILTIN_ANDNPD256,
26081 IX86_BUILTIN_ANDNPS256,
26082 IX86_BUILTIN_BLENDPD256,
26083 IX86_BUILTIN_BLENDPS256,
26084 IX86_BUILTIN_BLENDVPD256,
26085 IX86_BUILTIN_BLENDVPS256,
26086 IX86_BUILTIN_DIVPD256,
26087 IX86_BUILTIN_DIVPS256,
26088 IX86_BUILTIN_DPPS256,
26089 IX86_BUILTIN_HADDPD256,
26090 IX86_BUILTIN_HADDPS256,
26091 IX86_BUILTIN_HSUBPD256,
26092 IX86_BUILTIN_HSUBPS256,
26093 IX86_BUILTIN_MAXPD256,
26094 IX86_BUILTIN_MAXPS256,
26095 IX86_BUILTIN_MINPD256,
26096 IX86_BUILTIN_MINPS256,
26097 IX86_BUILTIN_MULPD256,
26098 IX86_BUILTIN_MULPS256,
26099 IX86_BUILTIN_ORPD256,
26100 IX86_BUILTIN_ORPS256,
26101 IX86_BUILTIN_SHUFPD256,
26102 IX86_BUILTIN_SHUFPS256,
26103 IX86_BUILTIN_SUBPD256,
26104 IX86_BUILTIN_SUBPS256,
26105 IX86_BUILTIN_XORPD256,
26106 IX86_BUILTIN_XORPS256,
26107 IX86_BUILTIN_CMPSD,
26108 IX86_BUILTIN_CMPSS,
26109 IX86_BUILTIN_CMPPD,
26110 IX86_BUILTIN_CMPPS,
26111 IX86_BUILTIN_CMPPD256,
26112 IX86_BUILTIN_CMPPS256,
26113 IX86_BUILTIN_CVTDQ2PD256,
26114 IX86_BUILTIN_CVTDQ2PS256,
26115 IX86_BUILTIN_CVTPD2PS256,
26116 IX86_BUILTIN_CVTPS2DQ256,
26117 IX86_BUILTIN_CVTPS2PD256,
26118 IX86_BUILTIN_CVTTPD2DQ256,
26119 IX86_BUILTIN_CVTPD2DQ256,
26120 IX86_BUILTIN_CVTTPS2DQ256,
26121 IX86_BUILTIN_EXTRACTF128PD256,
26122 IX86_BUILTIN_EXTRACTF128PS256,
26123 IX86_BUILTIN_EXTRACTF128SI256,
26124 IX86_BUILTIN_VZEROALL,
26125 IX86_BUILTIN_VZEROUPPER,
26126 IX86_BUILTIN_VPERMILVARPD,
26127 IX86_BUILTIN_VPERMILVARPS,
26128 IX86_BUILTIN_VPERMILVARPD256,
26129 IX86_BUILTIN_VPERMILVARPS256,
26130 IX86_BUILTIN_VPERMILPD,
26131 IX86_BUILTIN_VPERMILPS,
26132 IX86_BUILTIN_VPERMILPD256,
26133 IX86_BUILTIN_VPERMILPS256,
26134 IX86_BUILTIN_VPERMIL2PD,
26135 IX86_BUILTIN_VPERMIL2PS,
26136 IX86_BUILTIN_VPERMIL2PD256,
26137 IX86_BUILTIN_VPERMIL2PS256,
26138 IX86_BUILTIN_VPERM2F128PD256,
26139 IX86_BUILTIN_VPERM2F128PS256,
26140 IX86_BUILTIN_VPERM2F128SI256,
26141 IX86_BUILTIN_VBROADCASTSS,
26142 IX86_BUILTIN_VBROADCASTSD256,
26143 IX86_BUILTIN_VBROADCASTSS256,
26144 IX86_BUILTIN_VBROADCASTPD256,
26145 IX86_BUILTIN_VBROADCASTPS256,
26146 IX86_BUILTIN_VINSERTF128PD256,
26147 IX86_BUILTIN_VINSERTF128PS256,
26148 IX86_BUILTIN_VINSERTF128SI256,
26149 IX86_BUILTIN_LOADUPD256,
26150 IX86_BUILTIN_LOADUPS256,
26151 IX86_BUILTIN_STOREUPD256,
26152 IX86_BUILTIN_STOREUPS256,
26153 IX86_BUILTIN_LDDQU256,
26154 IX86_BUILTIN_MOVNTDQ256,
26155 IX86_BUILTIN_MOVNTPD256,
26156 IX86_BUILTIN_MOVNTPS256,
26157 IX86_BUILTIN_LOADDQU256,
26158 IX86_BUILTIN_STOREDQU256,
26159 IX86_BUILTIN_MASKLOADPD,
26160 IX86_BUILTIN_MASKLOADPS,
26161 IX86_BUILTIN_MASKSTOREPD,
26162 IX86_BUILTIN_MASKSTOREPS,
26163 IX86_BUILTIN_MASKLOADPD256,
26164 IX86_BUILTIN_MASKLOADPS256,
26165 IX86_BUILTIN_MASKSTOREPD256,
26166 IX86_BUILTIN_MASKSTOREPS256,
26167 IX86_BUILTIN_MOVSHDUP256,
26168 IX86_BUILTIN_MOVSLDUP256,
26169 IX86_BUILTIN_MOVDDUP256,
26171 IX86_BUILTIN_SQRTPD256,
26172 IX86_BUILTIN_SQRTPS256,
26173 IX86_BUILTIN_SQRTPS_NR256,
26174 IX86_BUILTIN_RSQRTPS256,
26175 IX86_BUILTIN_RSQRTPS_NR256,
26177 IX86_BUILTIN_RCPPS256,
26179 IX86_BUILTIN_ROUNDPD256,
26180 IX86_BUILTIN_ROUNDPS256,
26182 IX86_BUILTIN_FLOORPD256,
26183 IX86_BUILTIN_CEILPD256,
26184 IX86_BUILTIN_TRUNCPD256,
26185 IX86_BUILTIN_RINTPD256,
26186 IX86_BUILTIN_ROUNDPD_AZ256,
26188 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26189 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26190 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26192 IX86_BUILTIN_FLOORPS256,
26193 IX86_BUILTIN_CEILPS256,
26194 IX86_BUILTIN_TRUNCPS256,
26195 IX86_BUILTIN_RINTPS256,
26196 IX86_BUILTIN_ROUNDPS_AZ256,
26198 IX86_BUILTIN_FLOORPS_SFIX256,
26199 IX86_BUILTIN_CEILPS_SFIX256,
26200 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26202 IX86_BUILTIN_UNPCKHPD256,
26203 IX86_BUILTIN_UNPCKLPD256,
26204 IX86_BUILTIN_UNPCKHPS256,
26205 IX86_BUILTIN_UNPCKLPS256,
26207 IX86_BUILTIN_SI256_SI,
26208 IX86_BUILTIN_PS256_PS,
26209 IX86_BUILTIN_PD256_PD,
26210 IX86_BUILTIN_SI_SI256,
26211 IX86_BUILTIN_PS_PS256,
26212 IX86_BUILTIN_PD_PD256,
26214 IX86_BUILTIN_VTESTZPD,
26215 IX86_BUILTIN_VTESTCPD,
26216 IX86_BUILTIN_VTESTNZCPD,
26217 IX86_BUILTIN_VTESTZPS,
26218 IX86_BUILTIN_VTESTCPS,
26219 IX86_BUILTIN_VTESTNZCPS,
26220 IX86_BUILTIN_VTESTZPD256,
26221 IX86_BUILTIN_VTESTCPD256,
26222 IX86_BUILTIN_VTESTNZCPD256,
26223 IX86_BUILTIN_VTESTZPS256,
26224 IX86_BUILTIN_VTESTCPS256,
26225 IX86_BUILTIN_VTESTNZCPS256,
26226 IX86_BUILTIN_PTESTZ256,
26227 IX86_BUILTIN_PTESTC256,
26228 IX86_BUILTIN_PTESTNZC256,
26230 IX86_BUILTIN_MOVMSKPD256,
26231 IX86_BUILTIN_MOVMSKPS256,
26233 /* AVX2 */
26234 IX86_BUILTIN_MPSADBW256,
26235 IX86_BUILTIN_PABSB256,
26236 IX86_BUILTIN_PABSW256,
26237 IX86_BUILTIN_PABSD256,
26238 IX86_BUILTIN_PACKSSDW256,
26239 IX86_BUILTIN_PACKSSWB256,
26240 IX86_BUILTIN_PACKUSDW256,
26241 IX86_BUILTIN_PACKUSWB256,
26242 IX86_BUILTIN_PADDB256,
26243 IX86_BUILTIN_PADDW256,
26244 IX86_BUILTIN_PADDD256,
26245 IX86_BUILTIN_PADDQ256,
26246 IX86_BUILTIN_PADDSB256,
26247 IX86_BUILTIN_PADDSW256,
26248 IX86_BUILTIN_PADDUSB256,
26249 IX86_BUILTIN_PADDUSW256,
26250 IX86_BUILTIN_PALIGNR256,
26251 IX86_BUILTIN_AND256I,
26252 IX86_BUILTIN_ANDNOT256I,
26253 IX86_BUILTIN_PAVGB256,
26254 IX86_BUILTIN_PAVGW256,
26255 IX86_BUILTIN_PBLENDVB256,
26256 IX86_BUILTIN_PBLENDVW256,
26257 IX86_BUILTIN_PCMPEQB256,
26258 IX86_BUILTIN_PCMPEQW256,
26259 IX86_BUILTIN_PCMPEQD256,
26260 IX86_BUILTIN_PCMPEQQ256,
26261 IX86_BUILTIN_PCMPGTB256,
26262 IX86_BUILTIN_PCMPGTW256,
26263 IX86_BUILTIN_PCMPGTD256,
26264 IX86_BUILTIN_PCMPGTQ256,
26265 IX86_BUILTIN_PHADDW256,
26266 IX86_BUILTIN_PHADDD256,
26267 IX86_BUILTIN_PHADDSW256,
26268 IX86_BUILTIN_PHSUBW256,
26269 IX86_BUILTIN_PHSUBD256,
26270 IX86_BUILTIN_PHSUBSW256,
26271 IX86_BUILTIN_PMADDUBSW256,
26272 IX86_BUILTIN_PMADDWD256,
26273 IX86_BUILTIN_PMAXSB256,
26274 IX86_BUILTIN_PMAXSW256,
26275 IX86_BUILTIN_PMAXSD256,
26276 IX86_BUILTIN_PMAXUB256,
26277 IX86_BUILTIN_PMAXUW256,
26278 IX86_BUILTIN_PMAXUD256,
26279 IX86_BUILTIN_PMINSB256,
26280 IX86_BUILTIN_PMINSW256,
26281 IX86_BUILTIN_PMINSD256,
26282 IX86_BUILTIN_PMINUB256,
26283 IX86_BUILTIN_PMINUW256,
26284 IX86_BUILTIN_PMINUD256,
26285 IX86_BUILTIN_PMOVMSKB256,
26286 IX86_BUILTIN_PMOVSXBW256,
26287 IX86_BUILTIN_PMOVSXBD256,
26288 IX86_BUILTIN_PMOVSXBQ256,
26289 IX86_BUILTIN_PMOVSXWD256,
26290 IX86_BUILTIN_PMOVSXWQ256,
26291 IX86_BUILTIN_PMOVSXDQ256,
26292 IX86_BUILTIN_PMOVZXBW256,
26293 IX86_BUILTIN_PMOVZXBD256,
26294 IX86_BUILTIN_PMOVZXBQ256,
26295 IX86_BUILTIN_PMOVZXWD256,
26296 IX86_BUILTIN_PMOVZXWQ256,
26297 IX86_BUILTIN_PMOVZXDQ256,
26298 IX86_BUILTIN_PMULDQ256,
26299 IX86_BUILTIN_PMULHRSW256,
26300 IX86_BUILTIN_PMULHUW256,
26301 IX86_BUILTIN_PMULHW256,
26302 IX86_BUILTIN_PMULLW256,
26303 IX86_BUILTIN_PMULLD256,
26304 IX86_BUILTIN_PMULUDQ256,
26305 IX86_BUILTIN_POR256,
26306 IX86_BUILTIN_PSADBW256,
26307 IX86_BUILTIN_PSHUFB256,
26308 IX86_BUILTIN_PSHUFD256,
26309 IX86_BUILTIN_PSHUFHW256,
26310 IX86_BUILTIN_PSHUFLW256,
26311 IX86_BUILTIN_PSIGNB256,
26312 IX86_BUILTIN_PSIGNW256,
26313 IX86_BUILTIN_PSIGND256,
26314 IX86_BUILTIN_PSLLDQI256,
26315 IX86_BUILTIN_PSLLWI256,
26316 IX86_BUILTIN_PSLLW256,
26317 IX86_BUILTIN_PSLLDI256,
26318 IX86_BUILTIN_PSLLD256,
26319 IX86_BUILTIN_PSLLQI256,
26320 IX86_BUILTIN_PSLLQ256,
26321 IX86_BUILTIN_PSRAWI256,
26322 IX86_BUILTIN_PSRAW256,
26323 IX86_BUILTIN_PSRADI256,
26324 IX86_BUILTIN_PSRAD256,
26325 IX86_BUILTIN_PSRLDQI256,
26326 IX86_BUILTIN_PSRLWI256,
26327 IX86_BUILTIN_PSRLW256,
26328 IX86_BUILTIN_PSRLDI256,
26329 IX86_BUILTIN_PSRLD256,
26330 IX86_BUILTIN_PSRLQI256,
26331 IX86_BUILTIN_PSRLQ256,
26332 IX86_BUILTIN_PSUBB256,
26333 IX86_BUILTIN_PSUBW256,
26334 IX86_BUILTIN_PSUBD256,
26335 IX86_BUILTIN_PSUBQ256,
26336 IX86_BUILTIN_PSUBSB256,
26337 IX86_BUILTIN_PSUBSW256,
26338 IX86_BUILTIN_PSUBUSB256,
26339 IX86_BUILTIN_PSUBUSW256,
26340 IX86_BUILTIN_PUNPCKHBW256,
26341 IX86_BUILTIN_PUNPCKHWD256,
26342 IX86_BUILTIN_PUNPCKHDQ256,
26343 IX86_BUILTIN_PUNPCKHQDQ256,
26344 IX86_BUILTIN_PUNPCKLBW256,
26345 IX86_BUILTIN_PUNPCKLWD256,
26346 IX86_BUILTIN_PUNPCKLDQ256,
26347 IX86_BUILTIN_PUNPCKLQDQ256,
26348 IX86_BUILTIN_PXOR256,
26349 IX86_BUILTIN_MOVNTDQA256,
26350 IX86_BUILTIN_VBROADCASTSS_PS,
26351 IX86_BUILTIN_VBROADCASTSS_PS256,
26352 IX86_BUILTIN_VBROADCASTSD_PD256,
26353 IX86_BUILTIN_VBROADCASTSI256,
26354 IX86_BUILTIN_PBLENDD256,
26355 IX86_BUILTIN_PBLENDD128,
26356 IX86_BUILTIN_PBROADCASTB256,
26357 IX86_BUILTIN_PBROADCASTW256,
26358 IX86_BUILTIN_PBROADCASTD256,
26359 IX86_BUILTIN_PBROADCASTQ256,
26360 IX86_BUILTIN_PBROADCASTB128,
26361 IX86_BUILTIN_PBROADCASTW128,
26362 IX86_BUILTIN_PBROADCASTD128,
26363 IX86_BUILTIN_PBROADCASTQ128,
26364 IX86_BUILTIN_VPERMVARSI256,
26365 IX86_BUILTIN_VPERMDF256,
26366 IX86_BUILTIN_VPERMVARSF256,
26367 IX86_BUILTIN_VPERMDI256,
26368 IX86_BUILTIN_VPERMTI256,
26369 IX86_BUILTIN_VEXTRACT128I256,
26370 IX86_BUILTIN_VINSERT128I256,
26371 IX86_BUILTIN_MASKLOADD,
26372 IX86_BUILTIN_MASKLOADQ,
26373 IX86_BUILTIN_MASKLOADD256,
26374 IX86_BUILTIN_MASKLOADQ256,
26375 IX86_BUILTIN_MASKSTORED,
26376 IX86_BUILTIN_MASKSTOREQ,
26377 IX86_BUILTIN_MASKSTORED256,
26378 IX86_BUILTIN_MASKSTOREQ256,
26379 IX86_BUILTIN_PSLLVV4DI,
26380 IX86_BUILTIN_PSLLVV2DI,
26381 IX86_BUILTIN_PSLLVV8SI,
26382 IX86_BUILTIN_PSLLVV4SI,
26383 IX86_BUILTIN_PSRAVV8SI,
26384 IX86_BUILTIN_PSRAVV4SI,
26385 IX86_BUILTIN_PSRLVV4DI,
26386 IX86_BUILTIN_PSRLVV2DI,
26387 IX86_BUILTIN_PSRLVV8SI,
26388 IX86_BUILTIN_PSRLVV4SI,
26390 IX86_BUILTIN_GATHERSIV2DF,
26391 IX86_BUILTIN_GATHERSIV4DF,
26392 IX86_BUILTIN_GATHERDIV2DF,
26393 IX86_BUILTIN_GATHERDIV4DF,
26394 IX86_BUILTIN_GATHERSIV4SF,
26395 IX86_BUILTIN_GATHERSIV8SF,
26396 IX86_BUILTIN_GATHERDIV4SF,
26397 IX86_BUILTIN_GATHERDIV8SF,
26398 IX86_BUILTIN_GATHERSIV2DI,
26399 IX86_BUILTIN_GATHERSIV4DI,
26400 IX86_BUILTIN_GATHERDIV2DI,
26401 IX86_BUILTIN_GATHERDIV4DI,
26402 IX86_BUILTIN_GATHERSIV4SI,
26403 IX86_BUILTIN_GATHERSIV8SI,
26404 IX86_BUILTIN_GATHERDIV4SI,
26405 IX86_BUILTIN_GATHERDIV8SI,
26407 /* Alternate 4 element gather for the vectorizer where
26408 all operands are 32-byte wide. */
26409 IX86_BUILTIN_GATHERALTSIV4DF,
26410 IX86_BUILTIN_GATHERALTDIV8SF,
26411 IX86_BUILTIN_GATHERALTSIV4DI,
26412 IX86_BUILTIN_GATHERALTDIV8SI,
26414 /* TFmode support builtins. */
26415 IX86_BUILTIN_INFQ,
26416 IX86_BUILTIN_HUGE_VALQ,
26417 IX86_BUILTIN_FABSQ,
26418 IX86_BUILTIN_COPYSIGNQ,
26420 /* Vectorizer support builtins. */
26421 IX86_BUILTIN_CPYSGNPS,
26422 IX86_BUILTIN_CPYSGNPD,
26423 IX86_BUILTIN_CPYSGNPS256,
26424 IX86_BUILTIN_CPYSGNPD256,
26426 /* FMA4 instructions. */
26427 IX86_BUILTIN_VFMADDSS,
26428 IX86_BUILTIN_VFMADDSD,
26429 IX86_BUILTIN_VFMADDPS,
26430 IX86_BUILTIN_VFMADDPD,
26431 IX86_BUILTIN_VFMADDPS256,
26432 IX86_BUILTIN_VFMADDPD256,
26433 IX86_BUILTIN_VFMADDSUBPS,
26434 IX86_BUILTIN_VFMADDSUBPD,
26435 IX86_BUILTIN_VFMADDSUBPS256,
26436 IX86_BUILTIN_VFMADDSUBPD256,
26438 /* FMA3 instructions. */
26439 IX86_BUILTIN_VFMADDSS3,
26440 IX86_BUILTIN_VFMADDSD3,
26442 /* XOP instructions. */
26443 IX86_BUILTIN_VPCMOV,
26444 IX86_BUILTIN_VPCMOV_V2DI,
26445 IX86_BUILTIN_VPCMOV_V4SI,
26446 IX86_BUILTIN_VPCMOV_V8HI,
26447 IX86_BUILTIN_VPCMOV_V16QI,
26448 IX86_BUILTIN_VPCMOV_V4SF,
26449 IX86_BUILTIN_VPCMOV_V2DF,
26450 IX86_BUILTIN_VPCMOV256,
26451 IX86_BUILTIN_VPCMOV_V4DI256,
26452 IX86_BUILTIN_VPCMOV_V8SI256,
26453 IX86_BUILTIN_VPCMOV_V16HI256,
26454 IX86_BUILTIN_VPCMOV_V32QI256,
26455 IX86_BUILTIN_VPCMOV_V8SF256,
26456 IX86_BUILTIN_VPCMOV_V4DF256,
26458 IX86_BUILTIN_VPPERM,
26460 IX86_BUILTIN_VPMACSSWW,
26461 IX86_BUILTIN_VPMACSWW,
26462 IX86_BUILTIN_VPMACSSWD,
26463 IX86_BUILTIN_VPMACSWD,
26464 IX86_BUILTIN_VPMACSSDD,
26465 IX86_BUILTIN_VPMACSDD,
26466 IX86_BUILTIN_VPMACSSDQL,
26467 IX86_BUILTIN_VPMACSSDQH,
26468 IX86_BUILTIN_VPMACSDQL,
26469 IX86_BUILTIN_VPMACSDQH,
26470 IX86_BUILTIN_VPMADCSSWD,
26471 IX86_BUILTIN_VPMADCSWD,
26473 IX86_BUILTIN_VPHADDBW,
26474 IX86_BUILTIN_VPHADDBD,
26475 IX86_BUILTIN_VPHADDBQ,
26476 IX86_BUILTIN_VPHADDWD,
26477 IX86_BUILTIN_VPHADDWQ,
26478 IX86_BUILTIN_VPHADDDQ,
26479 IX86_BUILTIN_VPHADDUBW,
26480 IX86_BUILTIN_VPHADDUBD,
26481 IX86_BUILTIN_VPHADDUBQ,
26482 IX86_BUILTIN_VPHADDUWD,
26483 IX86_BUILTIN_VPHADDUWQ,
26484 IX86_BUILTIN_VPHADDUDQ,
26485 IX86_BUILTIN_VPHSUBBW,
26486 IX86_BUILTIN_VPHSUBWD,
26487 IX86_BUILTIN_VPHSUBDQ,
26489 IX86_BUILTIN_VPROTB,
26490 IX86_BUILTIN_VPROTW,
26491 IX86_BUILTIN_VPROTD,
26492 IX86_BUILTIN_VPROTQ,
26493 IX86_BUILTIN_VPROTB_IMM,
26494 IX86_BUILTIN_VPROTW_IMM,
26495 IX86_BUILTIN_VPROTD_IMM,
26496 IX86_BUILTIN_VPROTQ_IMM,
26498 IX86_BUILTIN_VPSHLB,
26499 IX86_BUILTIN_VPSHLW,
26500 IX86_BUILTIN_VPSHLD,
26501 IX86_BUILTIN_VPSHLQ,
26502 IX86_BUILTIN_VPSHAB,
26503 IX86_BUILTIN_VPSHAW,
26504 IX86_BUILTIN_VPSHAD,
26505 IX86_BUILTIN_VPSHAQ,
26507 IX86_BUILTIN_VFRCZSS,
26508 IX86_BUILTIN_VFRCZSD,
26509 IX86_BUILTIN_VFRCZPS,
26510 IX86_BUILTIN_VFRCZPD,
26511 IX86_BUILTIN_VFRCZPS256,
26512 IX86_BUILTIN_VFRCZPD256,
26514 IX86_BUILTIN_VPCOMEQUB,
26515 IX86_BUILTIN_VPCOMNEUB,
26516 IX86_BUILTIN_VPCOMLTUB,
26517 IX86_BUILTIN_VPCOMLEUB,
26518 IX86_BUILTIN_VPCOMGTUB,
26519 IX86_BUILTIN_VPCOMGEUB,
26520 IX86_BUILTIN_VPCOMFALSEUB,
26521 IX86_BUILTIN_VPCOMTRUEUB,
26523 IX86_BUILTIN_VPCOMEQUW,
26524 IX86_BUILTIN_VPCOMNEUW,
26525 IX86_BUILTIN_VPCOMLTUW,
26526 IX86_BUILTIN_VPCOMLEUW,
26527 IX86_BUILTIN_VPCOMGTUW,
26528 IX86_BUILTIN_VPCOMGEUW,
26529 IX86_BUILTIN_VPCOMFALSEUW,
26530 IX86_BUILTIN_VPCOMTRUEUW,
26532 IX86_BUILTIN_VPCOMEQUD,
26533 IX86_BUILTIN_VPCOMNEUD,
26534 IX86_BUILTIN_VPCOMLTUD,
26535 IX86_BUILTIN_VPCOMLEUD,
26536 IX86_BUILTIN_VPCOMGTUD,
26537 IX86_BUILTIN_VPCOMGEUD,
26538 IX86_BUILTIN_VPCOMFALSEUD,
26539 IX86_BUILTIN_VPCOMTRUEUD,
26541 IX86_BUILTIN_VPCOMEQUQ,
26542 IX86_BUILTIN_VPCOMNEUQ,
26543 IX86_BUILTIN_VPCOMLTUQ,
26544 IX86_BUILTIN_VPCOMLEUQ,
26545 IX86_BUILTIN_VPCOMGTUQ,
26546 IX86_BUILTIN_VPCOMGEUQ,
26547 IX86_BUILTIN_VPCOMFALSEUQ,
26548 IX86_BUILTIN_VPCOMTRUEUQ,
26550 IX86_BUILTIN_VPCOMEQB,
26551 IX86_BUILTIN_VPCOMNEB,
26552 IX86_BUILTIN_VPCOMLTB,
26553 IX86_BUILTIN_VPCOMLEB,
26554 IX86_BUILTIN_VPCOMGTB,
26555 IX86_BUILTIN_VPCOMGEB,
26556 IX86_BUILTIN_VPCOMFALSEB,
26557 IX86_BUILTIN_VPCOMTRUEB,
26559 IX86_BUILTIN_VPCOMEQW,
26560 IX86_BUILTIN_VPCOMNEW,
26561 IX86_BUILTIN_VPCOMLTW,
26562 IX86_BUILTIN_VPCOMLEW,
26563 IX86_BUILTIN_VPCOMGTW,
26564 IX86_BUILTIN_VPCOMGEW,
26565 IX86_BUILTIN_VPCOMFALSEW,
26566 IX86_BUILTIN_VPCOMTRUEW,
26568 IX86_BUILTIN_VPCOMEQD,
26569 IX86_BUILTIN_VPCOMNED,
26570 IX86_BUILTIN_VPCOMLTD,
26571 IX86_BUILTIN_VPCOMLED,
26572 IX86_BUILTIN_VPCOMGTD,
26573 IX86_BUILTIN_VPCOMGED,
26574 IX86_BUILTIN_VPCOMFALSED,
26575 IX86_BUILTIN_VPCOMTRUED,
26577 IX86_BUILTIN_VPCOMEQQ,
26578 IX86_BUILTIN_VPCOMNEQ,
26579 IX86_BUILTIN_VPCOMLTQ,
26580 IX86_BUILTIN_VPCOMLEQ,
26581 IX86_BUILTIN_VPCOMGTQ,
26582 IX86_BUILTIN_VPCOMGEQ,
26583 IX86_BUILTIN_VPCOMFALSEQ,
26584 IX86_BUILTIN_VPCOMTRUEQ,
26586 /* LWP instructions. */
26587 IX86_BUILTIN_LLWPCB,
26588 IX86_BUILTIN_SLWPCB,
26589 IX86_BUILTIN_LWPVAL32,
26590 IX86_BUILTIN_LWPVAL64,
26591 IX86_BUILTIN_LWPINS32,
26592 IX86_BUILTIN_LWPINS64,
26594 IX86_BUILTIN_CLZS,
26596 /* RTM */
26597 IX86_BUILTIN_XBEGIN,
26598 IX86_BUILTIN_XEND,
26599 IX86_BUILTIN_XABORT,
26600 IX86_BUILTIN_XTEST,
26602 /* BMI instructions. */
26603 IX86_BUILTIN_BEXTR32,
26604 IX86_BUILTIN_BEXTR64,
26605 IX86_BUILTIN_CTZS,
26607 /* TBM instructions. */
26608 IX86_BUILTIN_BEXTRI32,
26609 IX86_BUILTIN_BEXTRI64,
26611 /* BMI2 instructions. */
26612 IX86_BUILTIN_BZHI32,
26613 IX86_BUILTIN_BZHI64,
26614 IX86_BUILTIN_PDEP32,
26615 IX86_BUILTIN_PDEP64,
26616 IX86_BUILTIN_PEXT32,
26617 IX86_BUILTIN_PEXT64,
26619 /* ADX instructions. */
26620 IX86_BUILTIN_ADDCARRYX32,
26621 IX86_BUILTIN_ADDCARRYX64,
26623 /* FSGSBASE instructions. */
26624 IX86_BUILTIN_RDFSBASE32,
26625 IX86_BUILTIN_RDFSBASE64,
26626 IX86_BUILTIN_RDGSBASE32,
26627 IX86_BUILTIN_RDGSBASE64,
26628 IX86_BUILTIN_WRFSBASE32,
26629 IX86_BUILTIN_WRFSBASE64,
26630 IX86_BUILTIN_WRGSBASE32,
26631 IX86_BUILTIN_WRGSBASE64,
26633 /* RDRND instructions. */
26634 IX86_BUILTIN_RDRAND16_STEP,
26635 IX86_BUILTIN_RDRAND32_STEP,
26636 IX86_BUILTIN_RDRAND64_STEP,
26638 /* RDSEED instructions. */
26639 IX86_BUILTIN_RDSEED16_STEP,
26640 IX86_BUILTIN_RDSEED32_STEP,
26641 IX86_BUILTIN_RDSEED64_STEP,
26643 /* F16C instructions. */
26644 IX86_BUILTIN_CVTPH2PS,
26645 IX86_BUILTIN_CVTPH2PS256,
26646 IX86_BUILTIN_CVTPS2PH,
26647 IX86_BUILTIN_CVTPS2PH256,
26649 /* CFString built-in for darwin */
26650 IX86_BUILTIN_CFSTRING,
26652 /* Builtins to get CPU type and supported features. */
26653 IX86_BUILTIN_CPU_INIT,
26654 IX86_BUILTIN_CPU_IS,
26655 IX86_BUILTIN_CPU_SUPPORTS,
26657 IX86_BUILTIN_MAX
26658 };
26660 /* Table for the ix86 builtin decls. */
26663 /* Table of all of the builtin functions that are possible with different ISA's
26664 but are waiting to be built until a function is declared to use that
26665 ISA. */
26672 };
26677 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26678 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26679 function decl in the ix86_builtins array. Returns the function decl or
26680 NULL_TREE, if the builtin was not added.
26682 If the front end has a special hook for builtin functions, delay adding
26683 builtin functions that aren't in the current ISA until the ISA is changed
26684 with function specific optimization. Doing so, can save about 300K for the
26685 default compiler. When the builtin is expanded, check at that time whether
26686 it is valid.
26688 If the front end doesn't have a special hook, record all builtins, even if
26689 it isn't an instruction set in the current ISA in case the user uses
26690 function specific options for a different ISA, so that we don't get scope
26691 errors if a builtin is added in the middle of a function scope. */
26697 {
26701 {
26710 {
26716 }
26717 else
26718 {
26724 }
26725 }
26728 }
26730 /* Like def_builtin, but also marks the function decl "const". */
26735 {
26739 else
26743 }
26745 /* Add any new builtin functions for a given ISA that may not have been
26746 declared. This saves a bit of space compared to adding all of the
26747 declarations to the tree, even if we didn't use them. */
26749 static void
26751 {
26755 {
26758 {
26761 /* Don't define the builtin again. */
26767 NULL_TREE);
26772 }
26773 }
26774 }
26776 /* Bits for builtin_description.flag. */
26778 /* Set when we don't support the comparison natively, and should
26779 swap_comparison in order to support it. */
26780 #define BUILTIN_DESC_SWAP_OPERANDS 1
26782 struct builtin_description
26783 {
26790 };
26793 {
26794 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26795 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26796 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26797 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26798 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26799 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26800 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26801 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26802 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26803 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26804 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26805 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26807 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26812 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26813 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26815 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26817 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26818 };
26821 {
26822 /* SSE4.2 */
26823 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26824 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26825 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26826 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26827 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26828 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26829 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26830 };
26833 {
26834 /* SSE4.2 */
26835 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26836 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26837 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26838 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26839 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26840 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26841 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26842 };
26844 /* Special builtins with variable number of arguments. */
26846 {
26847 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26848 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26849 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26851 /* MMX */
26852 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26854 /* 3DNow! */
26855 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26857 /* FXSR, XSAVE and XSAVEOPT */
26858 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26859 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26860 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26861 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26862 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26864 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26865 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26866 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26867 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26868 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26870 /* SSE */
26871 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26872 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26873 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26875 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26876 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26877 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26878 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26880 /* SSE or 3DNow!A */
26881 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26882 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
26884 /* SSE2 */
26885 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
26889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
26891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
26892 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
26893 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
26894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26896 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26899 /* SSE3 */
26900 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26902 /* SSE4.1 */
26903 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
26905 /* SSE4A */
26906 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26907 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26909 /* AVX */
26910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
26911 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
26913 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26914 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26915 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26916 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
26917 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
26919 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26920 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26921 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26922 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26923 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26924 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
26925 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26927 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
26928 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26929 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26931 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
26932 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
26933 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
26934 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
26935 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26936 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26937 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26938 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26940 /* AVX2 */
26941 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
26942 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
26943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
26944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
26945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
26946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26949 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26951 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26952 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26953 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26954 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26955 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26956 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26958 /* FSGSBASE */
26959 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26960 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26961 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26962 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26963 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26964 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26965 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26966 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26968 /* RTM */
26969 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26970 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
26971 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
26972 };
26974 /* Builtins with variable number of arguments. */
26976 {
26977 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26978 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26979 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26980 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26981 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26982 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26983 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26985 /* MMX */
26986 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26987 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26988 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26989 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26990 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26993 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26996 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26997 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26999 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27024 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27026 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27028 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27030 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27031 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27032 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27033 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27035 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27037 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27039 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27040 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27041 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27049 /* 3DNow! */
27050 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27051 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27052 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27053 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27055 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27056 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27057 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27058 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27059 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27060 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27061 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27062 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27063 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27064 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27065 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27066 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27067 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27068 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27069 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27071 /* 3DNow!A */
27072 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27073 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27074 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27075 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27076 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27077 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27079 /* SSE */
27080 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27082 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27083 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27084 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27087 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27088 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27089 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27090 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27091 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27093 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27095 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27096 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27097 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27098 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27099 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27102 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27104 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27105 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27106 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27107 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27108 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27109 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27110 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27111 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27113 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27115 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27116 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27117 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27118 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27119 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27125 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27127 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27128 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27130 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27132 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27134 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27135 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27137 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27139 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27140 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27141 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27142 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27143 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27145 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27146 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27147 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27149 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27151 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27152 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27153 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27155 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27156 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27158 /* SSE MMX or 3Dnow!A */
27159 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27160 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27161 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27163 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27164 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27165 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27166 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27168 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27169 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27171 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27173 /* SSE2 */
27174 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27176 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27178 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27180 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27192 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27193 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27197 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27199 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27200 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27201 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27202 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27206 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27208 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27211 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27230 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27234 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27236 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27237 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27239 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27242 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27243 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27245 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27247 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27248 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27249 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27250 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27251 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27252 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27253 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27254 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27256 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27265 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27266 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27268 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27270 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27271 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27274 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27283 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27284 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27285 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27288 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27289 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27290 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27291 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27292 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27293 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27294 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27295 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27301 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27305 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27310 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27315 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27317 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27318 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27319 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27320 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27323 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27324 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27325 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27327 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27328 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27330 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27331 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27332 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27333 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27341 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27343 /* SSE2 MMX */
27344 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27345 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27347 /* SSE3 */
27348 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27349 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27351 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27352 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27353 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27354 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27355 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27356 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27358 /* SSSE3 */
27359 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27360 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27361 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27362 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27363 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27364 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27366 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27367 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27368 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27369 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27370 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27371 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27372 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27373 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27374 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27375 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27376 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27377 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27378 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27379 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27380 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27381 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27382 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27383 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27384 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27385 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27386 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27387 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27388 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27389 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27391 /* SSSE3. */
27392 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27393 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27395 /* SSE4.1 */
27396 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27397 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27398 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27399 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27400 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27401 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27402 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27403 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27404 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27405 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27407 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27408 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27409 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27410 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27411 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27413 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27414 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27416 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27417 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27418 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27419 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27421 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27422 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27423 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27424 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27425 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27428 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27430 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27432 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27434 /* SSE4.1 */
27435 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27436 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27437 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27438 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27440 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27441 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27442 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27443 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27445 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27446 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27448 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27449 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27451 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27452 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27453 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27454 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27456 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27457 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27459 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27460 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27462 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27463 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27464 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27466 /* SSE4.2 */
27467 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27468 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27469 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27470 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27471 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27473 /* SSE4A */
27474 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27475 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27476 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27477 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27479 /* AES */
27480 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27481 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27483 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27484 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27485 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27486 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27488 /* PCLMUL */
27489 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27491 /* AVX */
27492 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27493 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27494 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27495 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27496 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27497 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27498 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27499 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27500 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27501 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27502 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27503 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27504 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27506 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27507 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27508 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27509 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27510 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27511 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27512 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27513 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27514 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27515 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27516 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27517 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27519 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27524 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27526 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27528 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27531 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27540 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27541 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27545 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27547 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27563 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27565 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27567 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27579 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27580 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27593 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27594 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27604 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27605 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27606 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27627 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27628 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27630 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27632 /* AVX2 */
27633 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27634 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27635 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27636 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27637 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27638 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27639 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27640 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27641 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27642 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27643 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27644 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27645 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27646 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27647 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27648 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27649 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27650 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27651 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27653 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27654 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27655 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27658 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27660 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27661 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27662 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27663 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27672 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27673 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27674 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27675 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27676 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27677 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27678 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27679 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27680 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27681 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27682 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27683 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27684 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27685 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27686 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27687 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27689 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27690 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27691 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27692 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27693 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27696 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27697 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27698 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27699 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27700 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27701 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27702 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27703 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27704 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27713 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27714 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27715 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27716 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27717 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27718 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27719 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27720 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27721 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27722 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27723 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27724 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27725 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27726 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27727 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27728 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27729 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27730 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27731 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27732 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27733 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27734 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27735 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27736 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27737 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27739 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27740 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27741 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27742 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27746 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27747 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27748 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27780 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27782 /* BMI */
27783 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27784 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27785 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27787 /* TBM */
27788 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27789 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27791 /* F16C */
27792 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27793 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27794 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27795 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27797 /* BMI2 */
27798 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27799 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27800 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27801 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27802 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27803 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27804 };
27806 /* FMA4 and XOP. */
27807 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27808 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27809 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27810 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27811 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27812 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27813 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27814 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27815 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27816 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27817 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27818 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27819 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27820 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27821 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27822 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27823 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27824 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27825 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27826 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27827 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27828 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27829 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27830 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27831 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27832 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27833 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27834 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27835 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27836 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27837 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27838 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27839 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27840 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27841 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27842 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27843 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27844 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27845 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27846 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27847 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27848 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27849 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27850 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27851 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27852 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27853 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27854 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27855 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27856 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27857 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27858 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27861 {
27902 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
27903 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
27904 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
27905 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
27906 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
27907 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
27908 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
27910 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27911 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27912 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
27913 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
27914 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
27915 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
27916 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
27918 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
27920 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27921 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27923 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27927 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27928 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27930 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27931 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27933 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
27935 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
27936 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
27937 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
27938 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
27939 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
27940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
27941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
27943 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
27944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
27945 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27946 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
27947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
27948 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
27950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
27951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
27952 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27953 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27968 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27970 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27971 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27976 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27979 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
27981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
27982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27984 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
27985 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
27986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
27987 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
27989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
27990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27992 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
27993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
27994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
27995 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
27997 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
27998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28000 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28002 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28003 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28008 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28009 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28011 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28016 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28024 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28042 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28044 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28047 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28049 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28050 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28055 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28057 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28058 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28060 };
28061 \f
28062 /* TM vector builtins. */
28064 /* Reuse the existing x86-specific `struct builtin_description' cause
28065 we're lazy. Add casts to make them fit. */
28067 {
28068 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28069 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28070 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28071 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28072 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28073 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28074 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28076 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28077 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28078 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28079 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28080 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28081 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28082 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28084 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28085 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28086 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28087 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28088 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28089 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28090 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28092 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28093 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28094 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28095 };
28097 /* TM callbacks. */
28099 /* Return the builtin decl needed to load a vector of TYPE. */
28101 static tree
28103 {
28105 {
28107 {
28114 }
28115 }
28117 }
28119 /* Return the builtin decl needed to store a vector of TYPE. */
28121 static tree
28123 {
28125 {
28127 {
28134 }
28135 }
28137 }
28138 \f
28139 /* Initialize the transactional memory vector load/store builtins. */
28141 static void
28143 {
28147 tree decl;
28154 /* If there are no builtins defined, we must be compiling in a
28155 language without trans-mem support. */
28159 /* Use whatever attributes a normal TM load has. */
28163 /* Use whatever attributes a normal TM store has. */
28167 /* Use whatever attributes a normal TM log has. */
28175 {
28179 {
28187 {
28190 }
28192 {
28195 }
28196 else
28197 {
28200 }
28202 /* The builtin without the prefix for
28203 calling it directly. */
28205 attrs);
28206 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28207 set the TYPE_ATTRIBUTES. */
28211 }
28212 }
28213 }
28215 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28216 in the current target ISA to allow the user to compile particular modules
28217 with different target specific options that differ from the command line
28218 options. */
28219 static void
28221 {
28226 /* Add all special builtins with variable number of operands. */
28230 {
28236 }
28238 /* Add all builtins with variable number of operands. */
28242 {
28248 }
28250 /* pcmpestr[im] insns. */
28254 {
28257 else
28260 }
28262 /* pcmpistr[im] insns. */
28266 {
28269 else
28272 }
28274 /* comi/ucomi insns. */
28276 {
28279 else
28282 }
28284 /* SSE */
28290 /* SSE or 3DNow!A */
28293 IX86_BUILTIN_MASKMOVQ);
28295 /* SSE2 */
28304 /* SSE3. */
28310 /* AES */
28324 /* PCLMUL */
28328 /* RDRND */
28335 IX86_BUILTIN_RDRAND64_STEP);
28337 /* AVX2 */
28339 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28340 IX86_BUILTIN_GATHERSIV2DF);
28343 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28344 IX86_BUILTIN_GATHERSIV4DF);
28347 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28348 IX86_BUILTIN_GATHERDIV2DF);
28351 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28352 IX86_BUILTIN_GATHERDIV4DF);
28355 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28356 IX86_BUILTIN_GATHERSIV4SF);
28359 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28360 IX86_BUILTIN_GATHERSIV8SF);
28363 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28364 IX86_BUILTIN_GATHERDIV4SF);
28367 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28368 IX86_BUILTIN_GATHERDIV8SF);
28371 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28372 IX86_BUILTIN_GATHERSIV2DI);
28375 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28376 IX86_BUILTIN_GATHERSIV4DI);
28379 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28380 IX86_BUILTIN_GATHERDIV2DI);
28383 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28384 IX86_BUILTIN_GATHERDIV4DI);
28387 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28388 IX86_BUILTIN_GATHERSIV4SI);
28391 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28392 IX86_BUILTIN_GATHERSIV8SI);
28395 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28396 IX86_BUILTIN_GATHERDIV4SI);
28399 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28400 IX86_BUILTIN_GATHERDIV8SI);
28403 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28404 IX86_BUILTIN_GATHERALTSIV4DF);
28407 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28408 IX86_BUILTIN_GATHERALTDIV8SF);
28411 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28412 IX86_BUILTIN_GATHERALTSIV4DI);
28415 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28416 IX86_BUILTIN_GATHERALTDIV8SI);
28418 /* RTM. */
28422 /* MMX access to the vec_init patterns. */
28427 V4HI_FTYPE_HI_HI_HI_HI,
28428 IX86_BUILTIN_VEC_INIT_V4HI);
28431 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28432 IX86_BUILTIN_VEC_INIT_V8QI);
28434 /* Access to the vec_extract patterns. */
28456 /* Access to the vec_set patterns. */
28477 /* RDSEED */
28486 /* ADCX */
28491 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28492 IX86_BUILTIN_ADDCARRYX64);
28494 /* Add FMA4 multi-arg argument instructions */
28496 {
28502 }
28503 }
28505 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28506 to return a pointer to VERSION_DECL if the outcome of the expression
28507 formed by PREDICATE_CHAIN is true. This function will be called during
28508 version dispatch to decide which function version to execute. It returns
28509 the basic block at the end, to which more conditions can be added. */
28511 static basic_block
28514 {
28515 gimple return_stmt;
28517 gimple convert_stmt;
28518 gimple call_cond_stmt;
28519 gimple if_else_stmt;
28525 gimple_seq gseq;
28542 {
28550 }
28553 {
28568 else
28569 {
28570 gimple assign_stmt;
28571 /* Use MIN_EXPR to check if any integer is zero?.
28572 and_expr_var = min_expr <cond_var, and_expr_var> */
28580 }
28581 }
28584 integer_zero_node,
28614 }
28616 /* This parses the attribute arguments to target in DECL and determines
28617 the right builtin to use to match the platform specification.
28618 It returns the priority value for this version decl. If PREDICATE_LIST
28619 is not NULL, it stores the list of cpu features that need to be checked
28620 before dispatching this function. */
28622 static unsigned int
28624 {
28625 tree attrs;
28627 tree target_node;
28634 /* Priority of i386 features, greater value is higher priority. This is
28635 used to decide the order in which function dispatch must happen. For
28636 instance, a version specialized for SSE4.2 should be checked for dispatch
28637 before a version for SSE3, as SSE4.2 implies SSE3. */
28638 enum feature_priority
28639 {
28641 P_MMX,
28642 P_SSE,
28643 P_SSE2,
28644 P_SSE3,
28645 P_SSSE3,
28646 P_PROC_SSSE3,
28647 P_SSE4_a,
28648 P_PROC_SSE4_a,
28649 P_SSE4_1,
28650 P_SSE4_2,
28651 P_PROC_SSE4_2,
28652 P_POPCNT,
28653 P_AVX,
28654 P_AVX2,
28655 P_FMA,
28656 P_PROC_FMA
28657 };
28661 /* These are the target attribute strings for which a dispatcher is
28662 available, from fold_builtin_cpu. */
28664 static struct _feature_list
28665 {
28668 }
28670 {
28681 };
28684 static unsigned int NUM_FEATURES
28700 /* Return priority zero for default function. */
28704 /* Handle arch= if specified. For priority, set it to be 1 more than
28705 the best instruction set the processor can handle. For instance, if
28706 there is a version for atom and a version for ssse3 (the highest ISA
28707 priority for atom), the atom version must be checked for dispatch
28708 before the ssse3 version. */
28710 {
28719 {
28721 {
28746 }
28747 }
28752 {
28756 }
28759 {
28761 /* For a C string literal the length includes the trailing NULL. */
28764 predicate_chain);
28765 }
28766 }
28768 /* Process feature name. */
28775 {
28776 /* Do not process "arch=" */
28778 {
28781 }
28783 {
28785 {
28787 {
28792 predicate_chain);
28793 }
28794 /* Find the maximum priority feature. */
28799 }
28800 }
28802 {
28806 }
28808 }
28812 {
28815 attrs_str);
28817 }
28819 {
28822 }
28825 }
28827 /* This compares the priority of target features in function DECL1
28828 and DECL2. It returns positive value if DECL1 is higher priority,
28829 negative value if DECL2 is higher priority and 0 if they are the
28830 same. */
28832 static int
28834 {
28839 }
28841 /* V1 and V2 point to function versions with different priorities
28842 based on the target ISA. This function compares their priorities. */
28844 static int
28846 {
28848 {
28849 tree version_decl;
28850 tree predicate_chain;
28857 }
28859 /* This function generates the dispatch function for
28860 multi-versioned functions. DISPATCH_DECL is the function which will
28861 contain the dispatch logic. FNDECLS are the function choices for
28862 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28863 in DISPATCH_DECL in which the dispatch code is generated. */
28865 static int
28869 {
28870 tree default_decl;
28871 gimple ifunc_cpu_init_stmt;
28872 gimple_seq gseq;
28874 tree ele;
28880 struct _function_version_info
28881 {
28882 tree version_decl;
28883 tree predicate_chain;
28891 /*fndecls_p is actually a vector. */
28894 /* At least one more version other than the default. */
28901 /* The first version in the vector is the default decl. */
28907 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
28908 constructors, so explicity call __builtin_cpu_init here. */
28919 {
28923 /* Get attribute string, parse it and find the right predicate decl.
28924 The predicate function could be a lengthy combination of many
28925 features, like arch-type and various isa-variants. */
28932 actual_versions++;
28936 }
28938 /* Sort the versions according to descending order of dispatch priority. The
28939 priority is based on the ISA. This is not a perfect solution. There
28940 could still be ambiguity. If more than one function version is suitable
28941 to execute, which one should be dispatched? In future, allow the user
28942 to specify a dispatch priority next to the version. */
28952 /* dispatch default version at the end. */
28958 }
28960 /* Comparator function to be used in qsort routine to sort attribute
28961 specification strings to "target". */
28963 static int
28965 {
28969 }
28971 /* ARGLIST is the argument to target attribute. This function tokenizes
28972 the comma separated arguments, sorts them and returns a string which
28973 is a unique identifier for the comma separated arguments. It also
28974 replaces non-identifier characters "=,-" with "_". */
28978 {
28979 tree arg;
28988 {
28993 argnum++;
28996 argnum++;
28997 }
29002 {
29008 }
29010 /* Replace "=,-" with "_". */
29023 {
29025 i++;
29027 }
29034 {
29039 }
29044 }
29046 /* This function changes the assembler name for functions that are
29047 versions. If DECL is a function version and has a "target"
29048 attribute, it appends the attribute string to its assembler name. */
29050 static tree
29052 {
29053 tree version_attr;
29061 "Function versions cannot be marked as gnu_inline,"
29070 /* target attribute string cannot be NULL. */
29074 version_string
29085 /* Allow assembler name to be modified if already set. */
29093 }
29095 /* This function returns true if FN1 and FN2 are versions of the same function,
29096 that is, the target strings of the function decls are different. This assumes
29097 that FN1 and FN2 have the same signature. */
29099 static bool
29101 {
29113 /* At least one function decl should have the target attribute specified. */
29117 /* Diagnose missing target attribute if one of the decls is already
29118 multi-versioned. */
29120 {
29122 {
29124 {
29129 }
29132 fn2);
29135 /* Prevent diagnosing of the same error multiple times. */
29140 }
29142 }
29147 /* The sorted target strings must be different for fn1 and fn2
29148 to be versions. */
29151 else
29158 }
29160 static tree
29162 {
29163 /* For function version, add the target suffix to the assembler name. */
29167 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29169 #endif
29172 }
29174 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29175 is true, append the full path name of the source file. */
29179 {
29187 /* Get a unique name that can be used globally without any chances
29188 of collision at link time. */
29198 /* Use '.' to concatenate names as it is demangler friendly. */
29201 suffix);
29202 else
29206 }
29208 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29210 /* Make a dispatcher declaration for the multi-versioned function DECL.
29211 Calls to DECL function will be replaced with calls to the dispatcher
29212 by the front-end. Return the decl created. */
29214 static tree
29216 {
29217 tree func_decl;
29237 /* Mark this func as external, the resolver will flip it again if
29238 it gets generated. */
29240 /* This will be of type IFUNCs have to be externally visible. */
29244 }
29246 #endif
29248 /* Returns true if decl is multi-versioned and DECL is the default function,
29249 that is it is not tagged with target specific optimization. */
29251 static bool
29253 {
29262 }
29264 /* Make a dispatcher declaration for the multi-versioned function DECL.
29265 Calls to DECL function will be replaced with calls to the dispatcher
29266 by the front-end. Returns the decl of the dispatcher function. */
29268 static tree
29270 {
29279 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29283 #endif
29298 /* Find the default version and make it the first node. */
29300 /* Go to the beginnig of the chain. */
29305 {
29310 }
29312 /* If there is no default node, just return NULL. */
29316 /* Make default info the first node. */
29318 {
29325 }
29329 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29330 /* Right now, the dispatching is done via ifunc. */
29336 dispatcher_version_info
29341 /* Set the dispatcher for all the versions. */
29344 {
29347 }
29348 #else
29350 "multiversioning needs ifunc which is not supported "
29352 #endif
29354 }
29356 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29357 it to CHAIN. */
29359 static tree
29361 {
29362 tree attr_name;
29363 tree attr_arg_name;
29364 tree attr_args;
29365 tree attr;
29372 }
29374 /* Make the resolver function decl to dispatch the versions of
29375 a multi-versioned function, DEFAULT_DECL. Create an
29376 empty basic block in the resolver and store the pointer in
29377 EMPTY_BB. Return the decl of the resolver function. */
29379 static tree
29383 {
29388 /* IFUNC's have to be globally visible. So, if the default_decl is
29389 not, then the name of the IFUNC should be made unique. */
29393 /* Append the filename to the resolver function if the versions are
29394 not externally visible. This is because the resolver function has
29395 to be externally visible for the loader to find it. So, appending
29396 the filename will prevent conflicts with a resolver function from
29397 another module which is based on the same version name. */
29400 /* The resolver function should return a (void *). */
29411 /* IFUNC resolvers have to be externally visible. */
29415 /* Resolver is not external, body is generated. */
29425 {
29426 /* In this case, each translation unit with a call to this
29427 versioned function will put out a resolver. Ensure it
29428 is comdat to keep just one copy. */
29431 }
29432 /* Build result decl and add to function_decl. */
29448 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29452 /* Create the alias for dispatch to resolver here. */
29453 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29457 }
29459 /* Generate the dispatching code body to dispatch multi-versioned function
29460 DECL. The target hook is called to process the "target" attributes and
29461 provide the code to dispatch the right function at run-time. NODE points
29462 to the dispatcher decl whose body will be created. */
29464 static tree
29466 {
29467 tree resolver_decl;
29468 basic_block empty_bb;
29470 tree default_ver_decl;
29486 /* The first version in the chain corresponds to the default version. */
29489 /* node is going to be an alias, so remove the finalized bit. */
29503 {
29505 /* Check for virtual functions here again, as by this time it should
29506 have been determined if this function needs a vtable index or
29507 not. This happens for methods in derived classes that override
29508 virtual methods in base classes but are not explicitly marked as
29509 virtual. */
29514 }
29521 }
29522 /* This builds the processor_model struct type defined in
29523 libgcc/config/i386/cpuinfo.c */
29525 static tree
29527 {
29534 /* The first 3 fields are unsigned int. */
29536 {
29542 }
29544 /* The last field is an array of unsigned integers of size one. */
29555 }
29557 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29559 static tree
29561 {
29562 tree new_decl;
29565 VAR_DECL,
29567 type);
29580 }
29582 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29583 into an integer defined in libgcc/config/i386/cpuinfo.c */
29585 static tree
29587 {
29593 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29594 enum processor_features
29595 {
29597 F_MMX,
29598 F_POPCNT,
29599 F_SSE,
29600 F_SSE2,
29601 F_SSE3,
29602 F_SSSE3,
29603 F_SSE4_1,
29604 F_SSE4_2,
29605 F_AVX,
29606 F_AVX2,
29607 F_MAX
29608 };
29610 /* These are the values for vendor types and cpu types and subtypes
29611 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29612 the corresponding start value. */
29613 enum processor_model
29614 {
29616 M_AMD,
29617 M_CPU_TYPE_START,
29618 M_INTEL_ATOM,
29619 M_INTEL_CORE2,
29620 M_INTEL_COREI7,
29621 M_AMDFAM10H,
29622 M_AMDFAM15H,
29623 M_CPU_SUBTYPE_START,
29624 M_INTEL_COREI7_NEHALEM,
29625 M_INTEL_COREI7_WESTMERE,
29626 M_INTEL_COREI7_SANDYBRIDGE,
29627 M_AMDFAM10H_BARCELONA,
29628 M_AMDFAM10H_SHANGHAI,
29629 M_AMDFAM10H_ISTANBUL,
29630 M_AMDFAM15H_BDVER1,
29631 M_AMDFAM15H_BDVER2,
29632 M_AMDFAM15H_BDVER3
29633 };
29635 static struct _arch_names_table
29636 {
29639 }
29641 {
29658 };
29660 static struct _isa_names_table
29661 {
29664 }
29666 {
29678 };
29689 {
29690 /* *args must be a expr that can contain other EXPRS leading to a
29691 STRING_CST. */
29693 {
29696 }
29698 }
29703 {
29704 tree ref;
29705 tree field;
29706 tree final;
29709 unsigned int NUM_ARCH_NAMES
29718 {
29722 }
29727 /* CPU types are stored in the next field. */
29730 {
29733 }
29735 /* CPU subtypes are stored in the next field. */
29737 {
29740 }
29742 /* Get the appropriate field in __cpu_model. */
29746 /* Check the value. */
29750 }
29752 {
29753 tree ref;
29754 tree array_elt;
29755 tree field;
29756 tree final;
29759 unsigned int NUM_ISA_NAMES
29768 {
29772 }
29775 /* Get the last field, which is __cpu_features. */
29779 /* Get the appropriate field: __cpu_model.__cpu_features */
29783 /* Access the 0th element of __cpu_features array. */
29788 /* Return __cpu_model.__cpu_features[0] & field_val */
29792 }
29794 }
29796 static tree
29799 {
29801 {
29806 {
29809 }
29810 }
29812 #ifdef SUBTARGET_FOLD_BUILTIN
29814 #endif
29817 }
29819 /* Make builtins to detect cpu type and features supported. NAME is
29820 the builtin name, CODE is the builtin code, and FTYPE is the function
29821 type of the builtin. */
29823 static void
29826 {
29827 tree decl;
29828 tree type;
29836 }
29838 /* Make builtins to get CPU type and features supported. The created
29839 builtins are :
29841 __builtin_cpu_init (), to detect cpu type and features,
29842 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29843 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29844 */
29846 static void
29848 {
29855 }
29857 /* Internal method for ix86_init_builtins. */
29859 static void
29861 {
29873 sysv_va_ref =
29876 fnvoid_va_end_ms =
29878 fnvoid_va_start_ms =
29880 fnvoid_va_end_sysv =
29882 fnvoid_va_start_sysv =
29884 NULL_TREE);
29885 fnvoid_va_copy_ms =
29887 NULL_TREE);
29888 fnvoid_va_copy_sysv =
29904 }
29906 static void
29908 {
29911 /* The __float80 type. */
29914 {
29915 /* The __float80 type. */
29920 }
29923 /* The __float128 type. */
29929 /* This macro is built by i386-builtin-types.awk. */
29930 DEFINE_BUILTIN_PRIMITIVE_TYPES;
29931 }
29933 static void
29935 {
29936 tree t;
29940 /* Builtins to get CPU type and features. */
29943 /* TFmode support builtins. */
29949 /* We will expand them to normal call if SSE isn't available since
29950 they are used by libgcc. */
29969 #ifdef SUBTARGET_INIT_BUILTINS
29970 SUBTARGET_INIT_BUILTINS;
29971 #endif
29972 }
29974 /* Return the ix86 builtin for CODE. */
29976 static tree
29978 {
29983 }
29985 /* Errors in the source file can cause expand_expr to return const0_rtx
29986 where we expect a vector. To avoid crashing, use one of the vector
29987 clear instructions. */
29988 static rtx
29990 {
29994 }
29996 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
29998 static rtx
30000 {
30001 rtx pat;
30021 {
30025 }
30039 }
30041 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30043 static rtx
30047 {
30048 rtx pat;
30056 rtx op;
30063 {
30143 }
30153 {
30160 {
30162 {
30165 {
30183 xop_rotl:
30185 {
30188 gcc_checking_assert
30190 }
30191 else
30192 {
30193 gcc_checking_assert
30204 }
30208 }
30209 }
30210 }
30211 else
30212 {
30213 non_constant:
30217 /* If we aren't optimizing, only allow one memory operand to be
30218 generated. */
30220 num_memory++;
30228 }
30232 }
30235 {
30246 else
30247 {
30253 }
30266 }
30273 }
30275 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30276 insns with vec_merge. */
30278 static rtx
30280 rtx target)
30281 {
30282 rtx pat;
30309 }
30311 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30313 static rtx
30316 {
30317 rtx pat;
30322 rtx op2;
30333 /* Swap operands if we have a comparison that isn't available in
30334 hardware. */
30336 {
30341 }
30361 }
30363 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30365 static rtx
30367 rtx target)
30368 {
30369 rtx pat;
30383 /* Swap operands if we have a comparison that isn't available in
30384 hardware. */
30386 {
30390 }
30411 const0_rtx)));
30414 }
30416 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30418 static rtx
30420 rtx target)
30421 {
30422 rtx pat;
30447 }
30449 static rtx
30452 {
30453 rtx pat;
30458 rtx op2;
30485 }
30487 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30489 static rtx
30491 rtx target)
30492 {
30493 rtx pat;
30526 const0_rtx)));
30529 }
30531 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30533 static rtx
30536 {
30537 rtx pat;
30575 {
30578 }
30581 {
30590 }
30592 {
30601 }
30602 else
30603 {
30610 }
30618 {
30623 emit_insn
30627 FLAGS_REG),
30628 const0_rtx)));
30630 }
30631 else
30633 }
30636 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30638 static rtx
30641 {
30642 rtx pat;
30670 {
30673 }
30676 {
30685 }
30687 {
30696 }
30697 else
30698 {
30705 }
30713 {
30718 emit_insn
30722 FLAGS_REG),
30723 const0_rtx)));
30725 }
30726 else
30728 }
30730 /* Subroutine of ix86_expand_builtin to take care of insns with
30731 variable number of operands. */
30733 static rtx
30736 {
30741 struct
30742 {
30743 rtx op;
30755 {
31034 }
31039 {
31042 }
31045 {
31052 }
31053 else
31054 {
31057 }
31060 {
31067 {
31068 /* SIMD shift insns take either an 8-bit immediate or
31069 register as count. But builtin functions take int as
31070 count. If count doesn't match, we put it in register. */
31072 {
31076 }
31077 }
31079 {
31082 {
31136 {
31139 {
31142 }
31148 }
31150 }
31151 }
31152 else
31153 {
31157 /* If we aren't optimizing, only allow one memory operand to
31158 be generated. */
31160 num_memory++;
31163 {
31166 }
31167 else
31168 {
31171 }
31172 }
31176 }
31179 {
31196 }
31203 }
31205 /* Subroutine of ix86_expand_builtin to take care of special insns
31206 with variable number of operands. */
31208 static rtx
31211 {
31212 tree arg;
31215 struct
31216 {
31217 rtx op;
31227 {
31275 /* Reserve memory operand for target. */
31306 /* Reserve memory operand for target. */
31320 }
31325 {
31330 {
31333 }
31334 else
31337 }
31338 else
31339 {
31346 }
31349 {
31358 {
31360 {
31366 else
31369 }
31370 }
31371 else
31372 {
31374 {
31375 /* This must be the memory operand. */
31380 }
31381 else
31382 {
31383 /* This must be register. */
31390 }
31391 }
31395 }
31398 {
31413 }
31419 }
31421 /* Return the integer constant in ARG. Constrain it to be in the range
31422 of the subparts of VEC_TYPE; issue an error if not. */
31424 static int
31426 {
31431 {
31434 }
31437 }
31439 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31440 ix86_expand_vector_init. We DO have language-level syntax for this, in
31441 the form of (type){ init-list }. Except that since we can't place emms
31442 instructions from inside the compiler, we can't allow the use of MMX
31443 registers unless the user explicitly asks for it. So we do *not* define
31444 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31445 we have builtins invoked by mmintrin.h that gives us license to emit
31446 these sorts of instructions. */
31448 static rtx
31450 {
31460 {
31463 }
31470 }
31472 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31473 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31474 had a language-level syntax for referencing vector elements. */
31476 static rtx
31478 {
31482 rtx op0;
31502 }
31504 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31505 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31506 a language-level syntax for referencing vector elements. */
31508 static rtx
31510 {
31534 /* OP0 is the source of these builtin functions and shouldn't be
31535 modified. Create a copy, use it and return it as target. */
31541 }
31543 /* Expand an expression EXP that calls a built-in function,
31544 with result going to TARGET if that's convenient
31545 (and in mode MODE if that's convenient).
31546 SUBTARGET may be used as the target for computing one of EXP's operands.
31547 IGNORE is nonzero if the value is to be ignored. */
31549 static rtx
31553 {
31563 /* For CPU builtins that can be folded, fold first and expand the fold. */
31565 {
31567 {
31568 /* Make it call __cpu_indicator_init in libgcc. */
31574 }
31577 {
31582 }
31583 }
31585 /* Determine whether the builtin function is available under the current ISA.
31586 Originally the builtin was not created if it wasn't applicable to the
31587 current ISA based on the command line switches. With function specific
31588 options, we need to check in the context of the function making the call
31589 whether it is supported. */
31592 {
31598 else
31599 {
31603 }
31605 }
31608 {
31612 ? CODE_FOR_mmx_maskmovq
31614 /* Note the arg order is different from the operand order. */
31715 {
31716 REAL_VALUE_TYPE inf;
31717 rtx tmp;
31729 }
31739 {
31745 insn = (TARGET_64BIT
31749 }
31751 {
31752 insn = (TARGET_64BIT
31756 }
31757 else
31758 {
31761 insn = (TARGET_64BIT
31769 {
31772 }
31774 }
31780 {
31785 }
31795 {
31810 }
31816 {
31819 }
31839 {
31842 }
31848 {
31852 {
31873 }
31878 }
31879 else
31880 {
31882 {
31894 }
31896 }
31926 ? CODE_FOR_tbm_bextri_si
31929 {
31932 }
31933 else
31934 {
31943 }
31959 rdrand_step:
31966 {
31969 }
31975 /* Emit SImode conditional move. */
31977 {
31980 }
31983 else
31990 const0_rtx);
32009 rdseed_step:
32016 {
32019 }
32025 const0_rtx);
32043 addcarryx:
32051 /* Generate CF from input operand. */
32056 /* Gen ADCX instruction to compute X+Y+CF. */
32071 /* Store the result. */
32074 {
32077 }
32080 /* Return current CF value. */
32149 gather_gen:
32160 /* Note the arg order is different from the operand order. */
32169 else
32174 {
32180 }
32183 {
32188 else
32198 }
32200 /* Force memory operand only with base register here. But we
32201 don't want to do it on memory operand for other builtin
32202 functions. */
32214 {
32217 }
32219 /* Optimize. If mask is known to have all high bits set,
32220 replace op0 with pc_rtx to signal that the instruction
32221 overwrites the whole destination and doesn't use its
32222 previous contents. */
32224 {
32226 {
32229 {
32233 negative++;
32236 negative++;
32237 }
32240 }
32242 {
32243 /* Recognize also when mask is like:
32244 __v2df src = _mm_setzero_pd ();
32245 __v2df mask = _mm_cmpeq_pd (src, src);
32246 or
32247 __v8sf src = _mm256_setzero_ps ();
32248 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32249 as that is a cheaper way to load all ones into
32250 a register than having to load a constant from
32251 memory. */
32254 {
32259 {
32266 /* FALLTHRU */
32276 }
32277 }
32278 }
32279 }
32288 {
32295 else
32297 }
32298 else
32309 {
32312 }
32318 }
32331 {
32335 /* Emit a normal call if SSE isn't available. */
32339 }
32364 }
32366 /* Returns a function decl for a vectorized version of the builtin function
32367 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32368 if it is not available. */
32370 static tree
32372 tree type_in)
32373 {
32389 {
32392 {
32397 }
32402 {
32407 }
32413 /* The round insn does not trap on denormals. */
32418 {
32423 }
32429 /* The round insn does not trap on denormals. */
32434 {
32439 }
32445 /* The round insn does not trap on denormals. */
32450 {
32455 }
32461 /* The round insn does not trap on denormals. */
32466 {
32471 }
32478 {
32483 }
32490 {
32495 }
32501 /* The round insn does not trap on denormals. */
32506 {
32511 }
32517 /* The round insn does not trap on denormals. */
32522 {
32527 }
32532 {
32537 }
32542 {
32547 }
32551 /* The round insn does not trap on denormals. */
32556 {
32561 }
32565 /* The round insn does not trap on denormals. */
32570 {
32575 }
32579 /* The round insn does not trap on denormals. */
32584 {
32589 }
32593 /* The round insn does not trap on denormals. */
32598 {
32603 }
32607 /* The round insn does not trap on denormals. */
32612 {
32617 }
32621 /* The round insn does not trap on denormals. */
32626 {
32631 }
32635 /* The round insn does not trap on denormals. */
32640 {
32645 }
32649 /* The round insn does not trap on denormals. */
32654 {
32659 }
32663 /* The round insn does not trap on denormals. */
32668 {
32673 }
32677 /* The round insn does not trap on denormals. */
32682 {
32687 }
32692 {
32697 }
32702 {
32707 }
32712 }
32714 /* Dispatch to a handler for a vectorization library. */
32717 type_in);
32720 }
32722 /* Handler for an SVML-style interface to
32723 a library with vectorized intrinsics. */
32725 static tree
32727 {
32735 /* The SVML is suitable for unsafe math only. */
32748 {
32795 }
32804 {
32807 }
32808 else
32811 /* Convert to uppercase. */
32816 args;
32818 arity++;
32822 else
32825 /* Build a function declaration for the vectorized function. */
32834 }
32836 /* Handler for an ACML-style interface to
32837 a library with vectorized intrinsics. */
32839 static tree
32841 {
32849 /* The ACML is 64bits only and suitable for unsafe math only as
32850 it does not correctly support parts of IEEE with the required
32851 precision such as denormals. */
32865 {
32895 }
32902 args;
32904 arity++;
32908 else
32911 /* Build a function declaration for the vectorized function. */
32920 }
32922 /* Returns a decl of a function that implements gather load with
32923 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
32924 Return NULL_TREE if it is not available. */
32926 static tree
32929 {
32945 /* v*gather* insn sign extends index to pointer mode. */
32957 {
32984 }
32987 }
32989 /* Returns a code for a target-specific builtin that implements
32990 reciprocal of the function, or NULL_TREE if not available. */
32992 static tree
32995 {
33002 /* Machine dependent builtins. */
33004 {
33005 /* Vectorized version of sqrt to rsqrt conversion. */
33014 }
33015 else
33016 /* Normal builtins. */
33018 {
33019 /* Sqrt to rsqrt conversion. */
33025 }
33026 }
33027 \f
33028 /* Helper for avx_vpermilps256_operand et al. This is also used by
33029 the expansion functions to turn the parallel back into a mask.
33030 The return value is 0 for no match and the imm8+1 for a match. */
33032 int
33034 {
33042 /* Validate that all of the elements are constants, and not totally
33043 out of range. Copy the data into an integral array to make the
33044 subsequent checks easier. */
33046 {
33056 }
33059 {
33061 /* In the 256-bit DFmode case, we can only move elements within
33062 a 128-bit lane. */
33064 {
33068 }
33070 {
33074 }
33078 /* In the 256-bit SFmode case, we have full freedom of movement
33079 within the low 128-bit lane, but the high 128-bit lane must
33080 mirror the exact same pattern. */
33085 /* FALLTHRU */
33089 /* In the 128-bit case, we've full freedom in the placement of
33090 the elements from the source operand. */
33097 }
33099 /* Make sure success has a non-zero value by adding one. */
33101 }
33103 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33104 the expansion functions to turn the parallel back into a mask.
33105 The return value is 0 for no match and the imm8+1 for a match. */
33107 int
33109 {
33117 /* Validate that all of the elements are constants, and not totally
33118 out of range. Copy the data into an integral array to make the
33119 subsequent checks easier. */
33121 {
33131 }
33133 /* Validate that the halves of the permute are halves. */
33141 /* Reconstruct the mask. */
33143 {
33149 }
33151 /* Make sure success has a non-zero value by adding one. */
33153 }
33154 \f
33155 /* Store OPERAND to the memory after reload is completed. This means
33156 that we can't easily use assign_stack_local. */
33157 rtx
33159 {
33160 rtx result;
33164 {
33167 stack_pointer_rtx,
33170 }
33172 {
33174 {
33178 /* FALLTHRU */
33184 stack_pointer_rtx)),
33185 operand));
33189 }
33191 }
33192 else
33193 {
33195 {
33197 {
33204 stack_pointer_rtx)),
33210 stack_pointer_rtx)),
33212 }
33215 /* Store HImodes as SImodes. */
33217 /* FALLTHRU */
33223 stack_pointer_rtx)),
33224 operand));
33228 }
33230 }
33232 }
33234 /* Free operand from the memory. */
33235 void
33237 {
33239 {
33244 else
33246 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33247 to pop or add instruction if registers are available. */
33251 }
33252 }
33254 /* Return a register priority for hard reg REGNO. */
33255 static int
33257 {
33258 /* ebp and r13 as the base always wants a displacement, r12 as the
33259 base always wants an index. So discourage their usage in an
33260 address. */
33265 /* New x86-64 int registers result in bigger code size. Discourage
33266 them. */
33269 /* New x86-64 SSE registers result in bigger code size. Discourage
33270 them. */
33273 /* Usage of AX register results in smaller code. Prefer it. */
33277 }
33279 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33281 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33282 QImode must go into class Q_REGS.
33283 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33284 movdf to do mem-to-mem moves through integer regs. */
33286 static reg_class_t
33288 {
33291 /* We're only allowed to return a subclass of CLASS. Many of the
33292 following checks fail for NO_REGS, so eliminate that early. */
33296 /* All classes can load zeros. */
33300 /* Force constants into memory if we are loading a (nonzero) constant into
33301 an MMX or SSE register. This is because there are no MMX/SSE instructions
33302 to load from a constant. */
33307 /* Prefer SSE regs only, if we can use them for math. */
33311 /* Floating-point constants need more complex checks. */
33313 {
33314 /* General regs can load everything. */
33318 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33319 zero above. We only want to wind up preferring 80387 registers if
33320 we plan on doing computation with them. */
33323 {
33324 /* Limit class to non-sse. */
33333 }
33336 }
33338 /* Generally when we see PLUS here, it's the function invariant
33339 (plus soft-fp const_int). Which can only be computed into general
33340 regs. */
33344 /* QImode constants are easy to load, but non-constant QImode data
33345 must go into Q_REGS. */
33347 {
33353 }
33356 }
33358 /* Discourage putting floating-point values in SSE registers unless
33359 SSE math is being used, and likewise for the 387 registers. */
33360 static reg_class_t
33362 {
33365 /* Restrict the output reload class to the register bank that we are doing
33366 math on. If we would like not to return a subset of CLASS, reject this
33367 alternative: if reload cannot do this, it will still use its choice. */
33373 {
33378 else
33380 }
33383 }
33385 static reg_class_t
33388 {
33389 /* Double-word spills from general registers to non-offsettable memory
33390 references (zero-extended addresses) require special handling. */
33396 {
33398 ? CODE_FOR_reload_noff_load
33400 /* Add the cost of moving address to a temporary. */
33404 }
33406 /* QImode spills from non-QI registers require
33407 intermediate register on 32bit targets. */
33416 {
33421 else
33427 /* Return Q_REGS if the operand is in memory. */
33430 }
33432 /* This condition handles corner case where an expression involving
33433 pointers gets vectorized. We're trying to use the address of a
33434 stack slot as a vector initializer.
33436 (set (reg:V2DI 74 [ vect_cst_.2 ])
33437 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33439 Eventually frame gets turned into sp+offset like this:
33441 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33442 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33443 (const_int 392 [0x188]))))
33445 That later gets turned into:
33447 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33448 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33449 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33451 We'll have the following reload recorded:
33453 Reload 0: reload_in (DI) =
33454 (plus:DI (reg/f:DI 7 sp)
33455 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33456 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33457 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33458 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33459 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33460 reload_reg_rtx: (reg:V2DI 22 xmm1)
33462 Which isn't going to work since SSE instructions can't handle scalar
33463 additions. Returning GENERAL_REGS forces the addition into integer
33464 register and reload can handle subsequent reloads without problems. */
33472 }
33474 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33476 static bool
33478 {
33480 {
33495 }
33498 }
33500 /* If we are copying between general and FP registers, we need a memory
33501 location. The same is true for SSE and MMX registers.
33503 To optimize register_move_cost performance, allow inline variant.
33505 The macro can't work reliably when one of the CLASSES is class containing
33506 registers from multiple units (SSE, MMX, integer). We avoid this by never
33507 combining those units in single alternative in the machine description.
33508 Ensure that this constraint holds to avoid unexpected surprises.
33510 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33511 enforce these sanity checks. */
33516 {
33523 {
33526 }
33531 /* ??? This is a lie. We do have moves between mmx/general, and for
33532 mmx/sse2. But by saying we need secondary memory we discourage the
33533 register allocator from using the mmx registers unless needed. */
33538 {
33539 /* SSE1 doesn't have any direct moves from other classes. */
33543 /* If the target says that inter-unit moves are more expensive
33544 than moving through memory, then don't generate them. */
33548 /* Between SSE and general, we have moves no larger than word size. */
33551 }
33554 }
33556 bool
33559 {
33561 }
33563 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33565 On the 80386, this is the size of MODE in words,
33566 except in the FP regs, where a single reg is always enough. */
33568 static unsigned char
33570 {
33572 {
33577 else
33579 }
33580 else
33581 {
33584 else
33586 }
33587 }
33589 /* Return true if the registers in CLASS cannot represent the change from
33590 modes FROM to TO. */
33592 bool
33595 {
33599 /* x87 registers can't do subreg at all, as all values are reformatted
33600 to extended precision. */
33605 {
33606 /* Vector registers do not support QI or HImode loads. If we don't
33607 disallow a change to these modes, reload will assume it's ok to
33608 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33609 the vec_dupv4hi pattern. */
33613 /* Vector registers do not support subreg with nonzero offsets, which
33614 are otherwise valid for integer registers. Since we can't see
33615 whether we have a nonzero offset from here, prohibit all
33616 nonparadoxical subregs changing size. */
33619 }
33622 }
33624 /* Return the cost of moving data of mode M between a
33625 register and memory. A value of 2 is the default; this cost is
33626 relative to those in `REGISTER_MOVE_COST'.
33628 This function is used extensively by register_move_cost that is used to
33629 build tables at startup. Make it inline in this case.
33630 When IN is 2, return maximum of in and out move cost.
33632 If moving between registers and memory is more expensive than
33633 between two registers, you should define this macro to express the
33634 relative cost.
33636 Model also increased moving costs of QImode registers in non
33637 Q_REGS classes.
33638 */
33642 {
33645 {
33648 {
33660 }
33664 }
33666 {
33669 {
33681 }
33685 }
33687 {
33690 {
33699 }
33703 }
33705 {
33708 {
33714 else
33719 }
33720 else
33721 {
33726 else
33728 }
33735 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33742 else
33746 }
33747 }
33749 static int
33752 {
33754 }
33757 /* Return the cost of moving data from a register in class CLASS1 to
33758 one in class CLASS2.
33760 It is not required that the cost always equal 2 when FROM is the same as TO;
33761 on some machines it is expensive to move between registers if they are not
33762 general registers. */
33764 static int
33766 reg_class_t class2_i)
33767 {
33771 /* In case we require secondary memory, compute cost of the store followed
33772 by load. In order to avoid bad register allocation choices, we need
33773 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33776 {
33782 /* In case of copying from general_purpose_register we may emit multiple
33783 stores followed by single load causing memory size mismatch stall.
33784 Count this as arbitrarily high cost of 20. */
33789 /* In the case of FP/MMX moves, the registers actually overlap, and we
33790 have to switch modes in order to treat them differently. */
33796 }
33798 /* Moves between SSE/MMX and integer unit are expensive. */
33802 /* ??? By keeping returned value relatively high, we limit the number
33803 of moves between integer and MMX/SSE registers for all targets.
33804 Additionally, high value prevents problem with x86_modes_tieable_p(),
33805 where integer modes in MMX/SSE registers are not tieable
33806 because of missing QImode and HImode moves to, from or between
33807 MMX/SSE registers. */
33817 }
33819 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33820 MODE. */
33822 bool
33824 {
33825 /* Flags and only flags can only hold CCmode values. */
33835 {
33836 /* We implement the move patterns for all vector modes into and
33837 out of SSE registers, even when no operation instructions
33838 are available. OImode move is available only when AVX is
33839 enabled. */
33846 }
33848 {
33849 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33850 so if the register is available at all, then we can move data of
33851 the given mode into or out of it. */
33854 }
33857 {
33858 /* Take care for QImode values - they can be in non-QI regs,
33859 but then they do cause partial register stalls. */
33865 }
33866 /* We handle both integer and floats in the general purpose registers. */
33873 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
33874 on to use that value in smaller contexts, this can easily force a
33875 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
33876 supporting DImode, allow it. */
33881 }
33883 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
33884 tieable integer mode. */
33886 static bool
33888 {
33890 {
33903 }
33904 }
33906 /* Return true if MODE1 is accessible in a register that can hold MODE2
33907 without copying. That is, all register classes that can hold MODE2
33908 can also hold MODE1. */
33910 bool
33912 {
33920 /* MODE2 being XFmode implies fp stack or general regs, which means we
33921 can tie any smaller floating point modes to it. Note that we do not
33922 tie this with TFmode. */
33926 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
33927 that we can tie it with SFmode. */
33931 /* If MODE2 is only appropriate for an SSE register, then tie with
33932 any other mode acceptable to SSE registers. */
33942 /* If MODE2 is appropriate for an MMX register, then tie
33943 with any other mode acceptable to MMX registers. */
33950 }
33952 /* Return the cost of moving between two registers of mode MODE. */
33954 static int
33956 {
33960 {
33991 }
33993 /* Return the cost of moving between two registers of mode MODE,
33994 assuming that the move will be in pieces of at most UNITS bytes. */
33996 }
33998 /* Compute a (partial) cost for rtx X. Return true if the complete
33999 cost has been computed, and false if subexpressions should be
34000 scanned. In either case, *TOTAL contains the cost result. */
34002 static bool
34005 {
34012 {
34016 {
34019 }
34031 && (!TARGET_64BIT
34036 else
34042 {
34045 }
34047 {
34057 }
34059 {
34062 {
34071 }
34072 }
34073 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34074 it'll probably end up. Add a penalty for size. */
34081 /* The zero extensions is often completely free on x86_64, so make
34082 it as cheap as possible. */
34088 else
34100 {
34103 {
34106 }
34109 {
34112 }
34113 }
34114 /* FALLTHRU */
34121 {
34122 /* ??? Should be SSE vector operation cost. */
34123 /* At least for published AMD latencies, this really is the same
34124 as the latency for a simple fpu operation like fabs. */
34125 /* V*QImode is emulated with 1-11 insns. */
34127 {
34130 {
34131 /* For XOP we use vpshab, which requires a broadcast of the
34132 value to the variable shift insn. For constants this
34133 means a V16Q const in mem; even when we can perform the
34134 shift with one insn set the cost to prefer paddb. */
34136 {
34141 }
34143 }
34147 }
34148 else
34150 }
34152 {
34154 {
34157 else
34159 }
34160 else
34161 {
34164 else
34166 }
34167 }
34168 else
34169 {
34172 else
34174 }
34178 {
34179 rtx sub;
34184 /* ??? SSE scalar/vector cost should be used here. */
34185 /* ??? Bald assumption that fma has the same cost as fmul. */
34189 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34200 }
34204 {
34205 /* ??? SSE scalar cost should be used here. */
34208 }
34210 {
34213 }
34215 {
34216 /* ??? SSE vector cost should be used here. */
34219 }
34221 {
34222 /* V*QImode is emulated with 7-13 insns. */
34224 {
34231 }
34232 /* V*DImode is emulated with 5-8 insns. */
34234 {
34237 else
34239 }
34240 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34241 insns, including two PMULUDQ. */
34244 else
34247 }
34248 else
34249 {
34254 {
34257 nbits++;
34258 }
34259 else
34260 /* This is arbitrary. */
34263 /* Compute costs correctly for widening multiplication. */
34267 {
34274 {
34278 else
34280 }
34284 }
34292 }
34299 /* ??? SSE cost should be used here. */
34304 /* ??? SSE vector cost should be used here. */
34306 else
34313 {
34318 {
34321 {
34329 }
34330 }
34333 {
34336 {
34342 }
34343 }
34345 {
34353 }
34354 }
34355 /* FALLTHRU */
34359 {
34360 /* ??? SSE cost should be used here. */
34363 }
34365 {
34368 }
34370 {
34371 /* ??? SSE vector cost should be used here. */
34374 }
34375 /* FALLTHRU */
34382 {
34389 }
34390 /* FALLTHRU */
34394 {
34395 /* ??? SSE cost should be used here. */
34398 }
34400 {
34403 }
34405 {
34406 /* ??? SSE vector cost should be used here. */
34409 }
34410 /* FALLTHRU */
34414 {
34415 /* ??? Should be SSE vector operation cost. */
34416 /* At least for published AMD latencies, this really is the same
34417 as the latency for a simple fpu operation like fabs. */
34419 }
34422 else
34431 {
34432 /* This kind of construct is implemented using test[bwl].
34433 Treat it as if we had an AND. */
34438 }
34448 /* ??? SSE cost should be used here. */
34453 /* ??? SSE vector cost should be used here. */
34459 /* ??? SSE cost should be used here. */
34464 /* ??? SSE vector cost should be used here. */
34477 /* ??? Assume all of these vector manipulation patterns are
34478 recognizable. In which case they all pretty much have the
34479 same cost. */
34485 }
34486 }
34488 #if TARGET_MACHO
34492 /* Given a symbol name and its associated stub, write out the
34493 definition of the stub. */
34495 void
34497 {
34502 /* For 64-bit we shouldn't get here. */
34505 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34522 else
34529 {
34531 }
34533 {
34534 /* PIC stub. */
34535 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34541 }
34542 else
34545 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34546 it needs no stub-binding-helper. */
34553 {
34556 }
34557 else
34562 /* N.B. Keep the correspondence of these
34563 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34564 old-pic/new-pic/non-pic stubs; altering this will break
34565 compatibility with existing dylibs. */
34567 {
34568 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34570 }
34571 else
34572 /* 16-byte -mdynamic-no-pic stub. */
34578 }
34581 /* Order the registers for register allocator. */
34583 void
34585 {
34589 /* First allocate the local general purpose registers. */
34594 /* Global general purpose registers. */
34599 /* x87 registers come first in case we are doing FP math
34600 using them. */
34605 /* SSE registers. */
34611 /* x87 registers. */
34619 /* Initialize the rest of array as we do not allocate some registers
34620 at all. */
34623 }
34625 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34626 in struct attribute_spec handler. */
34627 static tree
34629 tree args,
34632 {
34637 {
34639 name);
34642 }
34644 {
34646 name);
34649 }
34651 {
34652 tree cst;
34656 {
34659 name);
34661 }
34664 {
34667 name);
34669 }
34672 }
34675 }
34677 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34678 struct attribute_spec.handler. */
34679 static tree
34681 tree args ATTRIBUTE_UNUSED,
34683 {
34688 {
34690 name);
34693 }
34695 /* Can combine regparm with all attributes but fastcall. */
34697 {
34699 {
34701 }
34704 }
34706 {
34708 {
34710 }
34713 }
34716 }
34718 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34719 struct attribute_spec.handler. */
34720 static tree
34722 tree args ATTRIBUTE_UNUSED,
34724 {
34727 {
34730 }
34731 else
34735 {
34737 name);
34739 }
34745 {
34747 name);
34749 }
34752 }
34754 static tree
34756 tree args ATTRIBUTE_UNUSED,
34758 {
34760 {
34762 name);
34764 }
34766 }
34768 static bool
34770 {
34774 }
34776 /* Returns an expression indicating where the this parameter is
34777 located on entry to the FUNCTION. */
34779 static rtx
34781 {
34787 {
34792 else
34795 }
34800 {
34807 {
34812 }
34813 else
34814 {
34817 {
34823 }
34824 }
34826 }
34830 }
34832 /* Determine whether x86_output_mi_thunk can succeed. */
34834 static bool
34836 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34838 {
34839 /* 64-bit can handle anything. */
34843 /* For 32-bit, everything's fine if we have one free register. */
34847 /* Need a free register for vcall_offset. */
34851 /* Need a free register for GOT references. */
34855 /* Otherwise ok. */
34857 }
34859 /* Output the assembler code for a thunk function. THUNK_DECL is the
34860 declaration for the thunk function itself, FUNCTION is the decl for
34861 the target function. DELTA is an immediate constant offset to be
34862 added to THIS. If VCALL_OFFSET is nonzero, the word at
34863 *(*this + vcall_offset) should be added to THIS. */
34865 static void
34869 {
34876 else
34877 {
34883 else
34885 }
34889 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
34890 pull it in now and let DELTA benefit. */
34894 {
34895 /* Put the this parameter into %eax. */
34898 }
34899 else
34902 /* Adjust the this parameter by a fixed constant. */
34904 {
34909 {
34911 {
34915 }
34916 }
34919 }
34921 /* Adjust the this parameter by a value stored in the vtable. */
34923 {
34933 /* Adjust the this parameter. */
34937 {
34941 }
34948 vcall_mem));
34949 else
34951 }
34953 /* If necessary, drop THIS back to its stack slot. */
34959 {
34962 ;
34963 else
34964 {
34968 }
34969 }
34970 else
34971 {
34973 ;
34974 #if TARGET_MACHO
34976 {
34979 }
34981 else
34982 {
34989 }
34990 }
34992 /* Our sibling call patterns do not allow memories, because we have no
34993 predicate that can distinguish between frame and non-frame memory.
34994 For our purposes here, we can get away with (ab)using a jump pattern,
34995 because we're going to do no optimization. */
34998 else
34999 {
35005 {
35011 }
35017 }
35020 /* Emit just enough of rest_of_compilation to get the insns emitted.
35021 Note that use_thunk calls assemble_start_function et al. */
35027 }
35029 static void
35031 {
35033 #if TARGET_MACHO
35035 #endif
35042 }
35044 int
35046 {
35058 }
35060 /* Output assembler code to FILE to increment profiler label # LABELNO
35061 for profiling a function entry. */
35062 void
35064 {
35069 {
35070 #ifndef NO_PROFILE_COUNTERS
35072 #endif
35076 else
35078 }
35080 {
35081 #ifndef NO_PROFILE_COUNTERS
35084 #endif
35086 }
35087 else
35088 {
35089 #ifndef NO_PROFILE_COUNTERS
35092 #endif
35094 }
35095 }
35097 /* We don't have exact information about the insn sizes, but we may assume
35098 quite safely that we are informed about all 1 byte insns and memory
35099 address sizes. This is enough to eliminate unnecessary padding in
35100 99% of cases. */
35102 static int
35104 {
35110 /* Discard alignments we've emit and jump instructions. */
35117 /* Important case - calls are always 5 bytes.
35118 It is common to have many calls in the row. */
35127 /* For normal instructions we rely on get_attr_length being exact,
35128 with a few exceptions. */
35130 {
35134 {
35144 /* Otherwise trust get_attr_length. */
35146 }
35151 }
35154 else
35156 }
35158 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35160 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35161 window. */
35163 static void
35165 {
35170 /* Look for all minimal intervals of instructions containing 4 jumps.
35171 The intervals are bounded by START and INSN. NBYTES is the total
35172 size of instructions in the interval including INSN and not including
35173 START. When the NBYTES is smaller than 16 bytes, it is possible
35174 that the end of START and INSN ends up in the same 16byte page.
35176 The smallest offset in the page INSN can start is the case where START
35177 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35178 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35179 */
35181 {
35185 {
35191 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35192 already in the current 16 byte page, because otherwise
35193 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35194 bytes to reach 16 byte boundary. */
35202 {
35204 {
35211 else
35214 }
35215 }
35217 }
35228 njumps++;
35229 else
35233 {
35240 else
35243 }
35250 {
35257 }
35258 }
35259 }
35260 #endif
35262 /* AMD Athlon works faster
35263 when RET is not destination of conditional jump or directly preceded
35264 by other jump instruction. We avoid the penalty by inserting NOP just
35265 before the RET instructions in such cases. */
35266 static void
35268 {
35269 edge e;
35270 edge_iterator ei;
35273 {
35276 rtx prev;
35286 {
35287 edge e;
35288 edge_iterator ei;
35294 }
35296 {
35302 /* Empty functions get branch mispredict even when
35303 the jump destination is not visible to us. */
35306 }
35308 {
35311 }
35312 }
35313 }
35315 /* Count the minimum number of instructions in BB. Return 4 if the
35316 number of instructions >= 4. */
35318 static int
35320 {
35321 rtx insn;
35324 /* Count number of instructions in this block. Return 4 if the number
35325 of instructions >= 4. */
35327 {
35328 /* Only happen in exit blocks. */
35336 {
35337 insn_count++;
35340 }
35341 }
35344 }
35347 /* Count the minimum number of instructions in code path in BB.
35348 Return 4 if the number of instructions >= 4. */
35350 static int
35352 {
35353 edge e;
35354 edge_iterator ei;
35357 /* Only bother counting instructions along paths with no
35358 more than 2 basic blocks between entry and exit. Given
35359 that BB has an edge to exit, determine if a predecessor
35360 of BB has an edge from entry. If so, compute the number
35361 of instructions in the predecessor block. If there
35362 happen to be multiple such blocks, compute the minimum. */
35365 {
35366 edge prev_e;
35367 edge_iterator prev_ei;
35370 {
35373 }
35375 {
35377 {
35382 }
35383 }
35384 }
35390 }
35392 /* Pad short function to 4 instructions. */
35394 static void
35396 {
35397 edge e;
35398 edge_iterator ei;
35401 {
35404 {
35407 /* Pad short function. */
35409 {
35412 /* Find epilogue. */
35421 /* Two NOPs count as one instruction. */
35424 }
35425 }
35426 }
35427 }
35429 /* Implement machine specific optimizations. We implement padding of returns
35430 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35431 static void
35433 {
35434 /* We are freeing block_for_insn in the toplev to keep compatibility
35435 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35439 {
35444 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35447 #endif
35448 }
35449 }
35451 /* Return nonzero when QImode register that must be represented via REX prefix
35452 is used. */
35453 bool
35455 {
35463 }
35465 /* Return nonzero when P points to register encoded via REX prefix.
35466 Called via for_each_rtx. */
35467 static int
35469 {
35475 }
35477 /* Return true when INSN mentions register that must be encoded using REX
35478 prefix. */
35479 bool
35481 {
35484 }
35486 /* If profitable, negate (without causing overflow) integer constant
35487 of mode MODE at location LOC. Return true in this case. */
35488 bool
35490 {
35491 HOST_WIDE_INT val;
35497 {
35499 /* DImode x86_64 constants must fit in 32 bits. */
35512 }
35514 /* Avoid overflows. */
35520 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35521 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35524 {
35527 }
35530 }
35532 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35533 optabs would emit if we didn't have TFmode patterns. */
35535 void
35537 {
35571 }
35572 \f
35573 /* AVX2 does support 32-byte integer vector operations,
35574 thus the longest vector we are faced with is V32QImode. */
35575 #define MAX_VECT_LEN 32
35577 struct expand_vec_perm_d
35578 {
35585 };
35591 /* Get a vector mode of the same size as the original but with elements
35592 twice as wide. This is only guaranteed to apply to integral vectors. */
35596 {
35597 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35602 }
35604 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35605 with all elements equal to VAR. Return true if successful. */
35607 static bool
35610 {
35614 {
35619 /* FALLTHRU */
35629 {
35632 /* First attempt to recognize VAL as-is. */
35636 {
35637 rtx seq;
35638 /* If that fails, force VAL into a register. */
35649 }
35650 }
35657 {
35658 rtx x;
35665 }
35675 {
35679 permute:
35687 /* Extend to SImode using a paradoxical SUBREG. */
35691 /* Insert the SImode value as low element of a V4SImode vector. */
35699 }
35707 widen:
35708 /* Replicate the value once into the next wider mode and recurse. */
35709 {
35711 rtx x;
35727 }
35731 {
35740 }
35745 }
35746 }
35748 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35749 whose ONE_VAR element is VAR, and other elements are zero. Return true
35750 if successful. */
35752 static bool
35755 {
35757 rtx new_target;
35762 {
35764 /* For SSE4.1, we normally use vector set. But if the second
35765 element is zero and inter-unit moves are OK, we use movq
35766 instead. */
35767 use_vector_set = (TARGET_64BIT
35768 && TARGET_SSE4_1
35769 && !(TARGET_INTER_UNIT_MOVES
35791 /* Use ix86_expand_vector_set in 64bit mode only. */
35796 }
35799 {
35804 }
35807 {
35812 /* FALLTHRU */
35827 else
35834 {
35835 /* We need to shuffle the value to the correct position, so
35836 create a new pseudo to store the intermediate result. */
35838 /* With SSE2, we can use the integer shuffle insns. */
35840 {
35842 const1_rtx,
35849 }
35851 /* Otherwise convert the intermediate result to V4SFmode and
35852 use the SSE1 shuffle instructions. */
35854 {
35857 }
35858 else
35862 const1_rtx,
35871 }
35886 widen:
35890 /* Zero extend the variable element to SImode and recurse. */
35903 }
35904 }
35906 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35907 consisting of the values in VALS. It is known that all elements
35908 except ONE_VAR are constants. Return true if successful. */
35910 static bool
35913 {
35923 {
35928 /* For the two element vectors, it's just as easy to use
35929 the general case. */
35933 /* Use ix86_expand_vector_set in 64bit mode only. */
35955 widen:
35956 /* There's no way to set one QImode entry easily. Combine
35957 the variable value with its adjacent constant value, and
35958 promote to an HImode set. */
35961 {
35966 }
35967 else
35968 {
35971 }
35985 }
35990 }
35992 /* A subroutine of ix86_expand_vector_init_general. Use vector
35993 concatenate to handle the most general case: all values variable,
35994 and none identical. */
35996 static void
35999 {
36002 rtvec v;
36006 {
36009 {
36042 }
36055 {
36070 }
36075 {
36086 }
36089 half:
36090 /* FIXME: We process inputs backward to help RA. PR 36222. */
36094 {
36099 }
36103 {
36106 {
36110 }
36113 }
36114 else
36120 }
36121 }
36123 /* A subroutine of ix86_expand_vector_init_general. Use vector
36124 interleave to handle the most general case: all values variable,
36125 and none identical. */
36127 static void
36130 {
36139 {
36160 }
36163 {
36164 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36168 /* Insert the SImode value as low element of V4SImode vector. */
36172 op0),
36174 const1_rtx);
36177 /* Cast the V4SImode vector back to a vector in orignal mode. */
36181 /* Load even elements into the second positon. */
36185 const1_rtx));
36187 /* Cast vector to FIRST_IMODE vector. */
36190 }
36192 /* Interleave low FIRST_IMODE vectors. */
36194 {
36198 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36201 }
36203 /* Interleave low SECOND_IMODE vectors. */
36205 {
36208 {
36213 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36214 vector. */
36217 }
36220 /* FALLTHRU */
36227 /* Cast the SECOND_IMODE vector back to a vector on original
36228 mode. */
36235 }
36236 }
36238 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36239 all values variable, and none identical. */
36241 static void
36244 {
36250 {
36255 /* FALLTHRU */
36279 half:
36296 /* FALLTHRU */
36302 /* Don't use ix86_expand_vector_init_interleave if we can't
36303 move from GPR to SSE register directly. */
36319 }
36321 {
36333 {
36337 {
36343 else
36344 {
36349 }
36350 }
36353 }
36358 {
36364 }
36366 {
36372 }
36373 else
36375 }
36376 }
36378 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36379 instructions unless MMX_OK is true. */
36381 void
36383 {
36390 rtx x;
36393 {
36403 }
36405 /* Constants are best loaded from the constant pool. */
36407 {
36410 }
36412 /* If all values are identical, broadcast the value. */
36418 /* Values where only one field is non-constant are best loaded from
36419 the pool and overwritten via move later. */
36421 {
36425 one_var))
36430 }
36433 }
36435 void
36437 {
36442 rtx tmp;
36444 = {
36451 };
36453 = {
36460 };
36464 {
36468 {
36473 else
36477 }
36489 else
36495 {
36498 /* For the two element vectors, we implement a VEC_CONCAT with
36499 the extraction of the other element. */
36506 else
36511 }
36520 {
36526 /* tmp = target = A B C D */
36528 /* target = A A B B */
36530 /* target = X A B B */
36532 /* target = A X C D */
36539 /* tmp = target = A B C D */
36541 /* tmp = X B C D */
36543 /* target = A B X D */
36550 /* tmp = target = A B C D */
36552 /* tmp = X B C D */
36554 /* target = A B X D */
36562 }
36570 /* Element 0 handled by vec_merge below. */
36572 {
36575 }
36578 {
36579 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36580 store into element 0, then shuffle them back. */
36597 }
36598 else
36599 {
36600 /* For SSE1, we have to reuse the V4SF code. */
36603 }
36656 half:
36657 /* Compute offset. */
36663 /* Extract the half. */
36667 /* Put val in tmp at elt. */
36670 /* Put it back. */
36676 }
36679 {
36683 }
36684 else
36685 {
36694 }
36695 }
36697 void
36699 {
36703 rtx tmp;
36706 {
36711 /* FALLTHRU */
36724 {
36744 }
36756 {
36758 {
36778 }
36782 }
36783 else
36784 {
36785 /* For SSE1, we have to reuse the V4SF code. */
36789 }
36805 {
36809 else
36813 }
36818 {
36822 else
36826 }
36831 {
36835 else
36839 }
36844 {
36848 else
36852 }
36857 {
36861 else
36865 }
36870 {
36874 else
36878 }
36882 /* ??? Could extract the appropriate HImode element and shift. */
36885 }
36888 {
36892 /* Let the rtl optimizers know about the zero extension performed. */
36894 {
36897 }
36900 }
36901 else
36902 {
36909 }
36910 }
36912 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
36913 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
36914 The upper bits of DEST are undefined, though they shouldn't cause
36915 exceptions (some bits from src or all zeros are ok). */
36917 static void
36919 {
36920 rtx tem;
36922 {
36926 else
36944 else
36951 else
36962 const1_rtx);
36963 else
36970 }
36972 }
36974 /* Expand a vector reduction. FN is the binary pattern to reduce;
36975 DEST is the destination; IN is the input vector. */
36977 void
36979 {
36984 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
36988 {
36991 }
36996 {
37001 else
37005 }
37006 }
37007 \f
37008 /* Target hook for scalar_mode_supported_p. */
37009 static bool
37011 {
37016 else
37018 }
37020 /* Implements target hook vector_mode_supported_p. */
37021 static bool
37023 {
37035 }
37037 /* Target hook for c_mode_for_suffix. */
37038 static enum machine_mode
37040 {
37047 }
37049 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37051 We do this in the new i386 backend to maintain source compatibility
37052 with the old cc0-based compiler. */
37054 static tree
37056 tree inputs ATTRIBUTE_UNUSED,
37057 tree clobbers)
37058 {
37060 clobbers);
37062 clobbers);
37064 }
37066 /* Implements target vector targetm.asm.encode_section_info. */
37068 static void ATTRIBUTE_UNUSED
37070 {
37077 }
37079 /* Worker function for REVERSE_CONDITION. */
37081 enum rtx_code
37083 {
37087 }
37089 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37090 to OPERANDS[0]. */
37094 {
37096 {
37099 {
37103 }
37107 }
37109 {
37113 else
37114 {
37115 /* There is no non-popping store to memory for XFmode.
37116 So if we need one, follow the store with a load. */
37119 else
37121 }
37122 }
37123 else
37125 }
37127 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37128 FP status register is set. */
37130 void
37132 {
37134 rtx temp;
37139 {
37144 }
37145 else
37146 {
37151 }
37155 pc_rtx);
37160 }
37162 /* Output code to perform a log1p XFmode calculation. */
37165 {
37171 rtx test;
37177 XFmode));
37191 }
37193 /* Emit code for round calculation. */
37195 {
37202 rtx insn;
37207 {
37219 }
37222 {
37243 }
37251 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37253 /* scratch = fxam(op1) */
37256 UNSPEC_FXAM)));
37257 /* e1 = fabs(op1) */
37260 /* e2 = e1 + 0.5 */
37265 /* res = floor(e2) */
37267 {
37272 }
37273 else
37277 {
37280 {
37287 UNSPEC_TRUNC_NOOP)));
37288 }
37304 }
37306 /* flags = signbit(a) */
37309 /* if (flags) then res = -res */
37313 pc_rtx);
37324 }
37326 /* Output code to perform a Newton-Rhapson approximation of a single precision
37327 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37330 {
37338 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37342 /* x0 = rcp(b) estimate */
37345 UNSPEC_RCP)));
37346 /* e0 = x0 * b */
37350 /* e0 = x0 * e0 */
37354 /* e1 = x0 + x0 */
37358 /* x1 = e1 - e0 */
37362 /* res = a * x1 */
37365 }
37367 /* Output code to perform a Newton-Rhapson approximation of a
37368 single precision floating point [reciprocal] square root. */
37372 {
37374 REAL_VALUE_TYPE r;
37389 {
37392 }
37394 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37395 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37399 /* x0 = rsqrt(a) estimate */
37402 UNSPEC_RSQRT)));
37404 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37406 {
37418 }
37420 /* e0 = x0 * a */
37423 /* e1 = e0 * x0 */
37427 /* e2 = e1 - 3. */
37434 /* e3 = -.5 * x0 */
37437 else
37438 /* e3 = -.5 * e0 */
37441 /* ret = e2 * e3 */
37444 }
37446 #ifdef TARGET_SOLARIS
37447 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37449 static void
37451 tree decl)
37452 {
37453 /* With Binutils 2.15, the "@unwind" marker must be specified on
37454 every occurrence of the ".eh_frame" section, not just the first
37455 one. */
37458 {
37462 }
37464 #ifndef USE_GAS
37466 {
37469 }
37470 #endif
37473 }
37476 /* Return the mangling of TYPE if it is an extended fundamental type. */
37480 {
37488 {
37490 /* __float128 is "g". */
37493 /* "long double" or __float80 is "e". */
37497 }
37498 }
37500 /* For 32-bit code we can save PIC register setup by using
37501 __stack_chk_fail_local hidden function instead of calling
37502 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37503 register, so it is better to call __stack_chk_fail directly. */
37505 static tree ATTRIBUTE_UNUSED
37507 {
37508 return TARGET_64BIT
37511 }
37513 /* Select a format to encode pointers in exception handling data. CODE
37514 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37515 true if the symbol may be affected by dynamic relocations.
37517 ??? All x86 object file formats are capable of representing this.
37518 After all, the relocation needed is the same as for the call insn.
37519 Whether or not a particular assembler allows us to enter such, I
37520 guess we'll have to see. */
37521 int
37523 {
37525 {
37532 }
37537 }
37538 \f
37539 /* Expand copysign from SIGN to the positive value ABS_VALUE
37540 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37541 the sign-bit. */
37542 static void
37544 {
37548 {
37555 else
37560 {
37561 /* We need to generate a scalar mode mask in this case. */
37566 }
37567 }
37568 else
37574 }
37576 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37577 mask for masking out the sign-bit is stored in *SMASK, if that is
37578 non-null. */
37579 static rtx
37581 {
37590 else
37594 {
37595 /* We need to generate a scalar mode mask in this case. */
37600 }
37608 }
37610 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37611 swapping the operands if SWAP_OPERANDS is true. The expanded
37612 code is a forward jump to a newly created label in case the
37613 comparison is true. The generated label rtx is returned. */
37614 static rtx
37617 {
37621 {
37625 }
37638 }
37640 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37641 using comparison code CODE. Operands are swapped for the comparison if
37642 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37643 static rtx
37646 {
37652 {
37656 }
37663 }
37665 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37666 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37667 static rtx
37669 {
37670 REAL_VALUE_TYPE TWO52r;
37671 rtx TWO52;
37678 }
37680 /* Expand SSE sequence for computing lround from OP1 storing
37681 into OP0. */
37682 void
37684 {
37685 /* C code for the stuff we're doing below:
37686 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37687 return (long)tmp;
37688 */
37692 rtx adj;
37694 /* load nextafter (0.5, 0.0) */
37699 /* adj = copysign (0.5, op1) */
37703 /* adj = op1 + adj */
37706 /* op0 = (imode)adj */
37708 }
37710 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37711 into OPERAND0. */
37712 void
37714 {
37715 /* C code for the stuff we're doing below (for do_floor):
37716 xi = (long)op1;
37717 xi -= (double)xi > op1 ? 1 : 0;
37718 return xi;
37719 */
37724 /* reg = (long)op1 */
37728 /* freg = (double)reg */
37732 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37743 }
37745 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37746 result in OPERAND0. */
37747 void
37749 {
37750 /* C code for the stuff we're doing below:
37751 xa = fabs (operand1);
37752 if (!isless (xa, 2**52))
37753 return operand1;
37754 xa = xa + 2**52 - 2**52;
37755 return copysign (xa, operand1);
37756 */
37763 /* xa = abs (operand1) */
37766 /* if (!isless (xa, TWO52)) goto label; */
37779 }
37781 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37782 into OPERAND0. */
37783 void
37785 {
37786 /* C code for the stuff we expand below.
37787 double xa = fabs (x), x2;
37788 if (!isless (xa, TWO52))
37789 return x;
37790 xa = xa + TWO52 - TWO52;
37791 x2 = copysign (xa, x);
37792 Compensate. Floor:
37793 if (x2 > x)
37794 x2 -= 1;
37795 Compensate. Ceil:
37796 if (x2 < x)
37797 x2 -= -1;
37798 return x2;
37799 */
37805 /* Temporary for holding the result, initialized to the input
37806 operand to ease control flow. */
37810 /* xa = abs (operand1) */
37813 /* if (!isless (xa, TWO52)) goto label; */
37816 /* xa = xa + TWO52 - TWO52; */
37820 /* xa = copysign (xa, operand1) */
37823 /* generate 1.0 or -1.0 */
37828 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37832 /* We always need to subtract here to preserve signed zero. */
37841 }
37843 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37844 into OPERAND0. */
37845 void
37847 {
37848 /* C code for the stuff we expand below.
37849 double xa = fabs (x), x2;
37850 if (!isless (xa, TWO52))
37851 return x;
37852 x2 = (double)(long)x;
37853 Compensate. Floor:
37854 if (x2 > x)
37855 x2 -= 1;
37856 Compensate. Ceil:
37857 if (x2 < x)
37858 x2 += 1;
37859 if (HONOR_SIGNED_ZEROS (mode))
37860 return copysign (x2, x);
37861 return x2;
37862 */
37868 /* Temporary for holding the result, initialized to the input
37869 operand to ease control flow. */
37873 /* xa = abs (operand1) */
37876 /* if (!isless (xa, TWO52)) goto label; */
37879 /* xa = (double)(long)x */
37884 /* generate 1.0 */
37887 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37902 }
37904 /* Expand SSE sequence for computing round from OPERAND1 storing
37905 into OPERAND0. Sequence that works without relying on DImode truncation
37906 via cvttsd2siq that is only available on 64bit targets. */
37907 void
37909 {
37910 /* C code for the stuff we expand below.
37911 double xa = fabs (x), xa2, x2;
37912 if (!isless (xa, TWO52))
37913 return x;
37914 Using the absolute value and copying back sign makes
37915 -0.0 -> -0.0 correct.
37916 xa2 = xa + TWO52 - TWO52;
37917 Compensate.
37918 dxa = xa2 - xa;
37919 if (dxa <= -0.5)
37920 xa2 += 1;
37921 else if (dxa > 0.5)
37922 xa2 -= 1;
37923 x2 = copysign (xa2, x);
37924 return x2;
37925 */
37931 /* Temporary for holding the result, initialized to the input
37932 operand to ease control flow. */
37936 /* xa = abs (operand1) */
37939 /* if (!isless (xa, TWO52)) goto label; */
37942 /* xa2 = xa + TWO52 - TWO52; */
37946 /* dxa = xa2 - xa; */
37949 /* generate 0.5, 1.0 and -0.5 */
37955 /* Compensate. */
37957 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
37962 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
37968 /* res = copysign (xa2, operand1) */
37975 }
37977 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37978 into OPERAND0. */
37979 void
37981 {
37982 /* C code for SSE variant we expand below.
37983 double xa = fabs (x), x2;
37984 if (!isless (xa, TWO52))
37985 return x;
37986 x2 = (double)(long)x;
37987 if (HONOR_SIGNED_ZEROS (mode))
37988 return copysign (x2, x);
37989 return x2;
37990 */
37996 /* Temporary for holding the result, initialized to the input
37997 operand to ease control flow. */
38001 /* xa = abs (operand1) */
38004 /* if (!isless (xa, TWO52)) goto label; */
38007 /* x = (double)(long)x */
38019 }
38021 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38022 into OPERAND0. */
38023 void
38025 {
38029 /* C code for SSE variant we expand below.
38030 double xa = fabs (x), x2;
38031 if (!isless (xa, TWO52))
38032 return x;
38033 xa2 = xa + TWO52 - TWO52;
38034 Compensate:
38035 if (xa2 > xa)
38036 xa2 -= 1.0;
38037 x2 = copysign (xa2, x);
38038 return x2;
38039 */
38043 /* Temporary for holding the result, initialized to the input
38044 operand to ease control flow. */
38048 /* xa = abs (operand1) */
38051 /* if (!isless (xa, TWO52)) goto label; */
38054 /* res = xa + TWO52 - TWO52; */
38059 /* generate 1.0 */
38062 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38070 /* res = copysign (res, operand1) */
38077 }
38079 /* Expand SSE sequence for computing round from OPERAND1 storing
38080 into OPERAND0. */
38081 void
38083 {
38084 /* C code for the stuff we're doing below:
38085 double xa = fabs (x);
38086 if (!isless (xa, TWO52))
38087 return x;
38088 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38089 return copysign (xa, x);
38090 */
38096 /* Temporary for holding the result, initialized to the input
38097 operand to ease control flow. */
38105 /* load nextafter (0.5, 0.0) */
38110 /* xa = xa + 0.5 */
38114 /* xa = (double)(int64_t)xa */
38119 /* res = copysign (xa, operand1) */
38126 }
38128 /* Expand SSE sequence for computing round
38129 from OP1 storing into OP0 using sse4 round insn. */
38130 void
38132 {
38141 {
38152 }
38154 /* round (a) = trunc (a + copysign (0.5, a)) */
38156 /* load nextafter (0.5, 0.0) */
38162 /* e1 = copysign (0.5, op1) */
38166 /* e2 = op1 + e1 */
38169 /* res = trunc (e2) */
38174 }
38175 \f
38177 /* Table of valid machine attributes. */
38179 {
38180 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38181 affects_type_identity } */
38182 /* Stdcall attribute says callee is responsible for popping arguments
38183 if they are not variable. */
38186 /* Fastcall attribute says callee is responsible for popping arguments
38187 if they are not variable. */
38190 /* Thiscall attribute says callee is responsible for popping arguments
38191 if they are not variable. */
38194 /* Cdecl attribute says the callee is a normal C declaration */
38197 /* Regparm attribute specifies how many integer arguments are to be
38198 passed in registers. */
38201 /* Sseregparm attribute says we are using x86_64 calling conventions
38202 for FP arguments. */
38205 /* The transactional memory builtins are implicitly regparm or fastcall
38206 depending on the ABI. Override the generic do-nothing attribute that
38207 these builtins were declared with. */
38210 /* force_align_arg_pointer says this function realigns the stack at entry. */
38213 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38218 #endif
38223 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38224 SUBTARGET_ATTRIBUTE_TABLE,
38225 #endif
38226 /* ms_abi and sysv_abi calling convention function attributes. */
38233 /* End element. */
38235 };
38237 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38238 static int
38240 tree vectype,
38242 {
38246 {
38291 }
38292 }
38294 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38295 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38296 insn every time. */
38300 /* Initialize vselect_insn. */
38302 static void
38304 {
38306 rtx x;
38317 }
38319 /* Construct (set target (vec_select op0 (parallel perm))) and
38320 return true if that's a valid instruction in the active ISA. */
38322 static bool
38325 {
38351 }
38353 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38355 static bool
38359 {
38361 rtx x;
38376 }
38378 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38379 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38381 static bool
38383 {
38392 ;
38394 ;
38396 ;
38397 else
38400 /* This is a blend, not a permute. Elements must stay in their
38401 respective lanes. */
38403 {
38407 }
38412 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38413 decision should be extracted elsewhere, so that we only try that
38414 sequence once all budget==3 options have been tried. */
38421 {
38445 /* See if bytes move in pairs so we can use pblendw with
38446 an immediate argument, rather than pblendvb with a vector
38447 argument. */
38450 {
38451 use_pblendvb:
38455 finish_pblendvb:
38461 else
38464 }
38469 /* FALLTHRU */
38471 do_subreg:
38478 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38482 /* See if bytes move in quadruplets. If yes, vpblendd
38483 with immediate can be used. */
38488 {
38489 /* See if bytes move the same in both lanes. If yes,
38490 vpblendw with immediate can be used. */
38495 /* Use vpblendw. */
38500 }
38502 /* Use vpblendd. */
38509 /* See if words move in pairs. If yes, vpblendd can be used. */
38514 {
38515 /* See if words move the same in both lanes. If not,
38516 vpblendvb must be used. */
38519 {
38520 /* Use vpblendvb. */
38530 }
38532 /* Use vpblendw. */
38536 }
38538 /* Use vpblendd. */
38545 /* Use vpblendd. */
38553 }
38555 /* This matches five different patterns with the different modes. */
38561 }
38563 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38564 in terms of the variable form of vpermilps.
38566 Note that we will have already failed the immediate input vpermilps,
38567 which requires that the high and low part shuffle be identical; the
38568 variable form doesn't require that. */
38570 static bool
38572 {
38579 /* We can only permute within the 128-bit lane. */
38581 {
38585 }
38591 {
38594 /* Within each 128-bit lane, the elements of op0 are numbered
38595 from 0 and the elements of op1 are numbered from 4. */
38602 }
38609 }
38611 /* Return true if permutation D can be performed as VMODE permutation
38612 instead. */
38614 static bool
38616 {
38631 else
38637 }
38639 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38640 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38642 static bool
38644 {
38653 {
38655 {
38658 {
38662 /* Use vperm2i128 insn. The pattern uses
38663 V4DImode instead of V2TImode. */
38672 }
38674 }
38675 }
38676 else
38677 {
38679 {
38682 }
38684 {
38688 /* V4DImode should be already handled through
38689 expand_vselect by vpermq instruction. */
38696 {
38697 /* First see if vpermq can be used for
38698 V8SImode/V16HImode/V32QImode. */
38700 {
38708 }
38710 /* Next see if vpermd can be used. */
38713 }
38714 /* Or if vpermps can be used. */
38719 {
38720 /* vpshufb only works intra lanes, it is not
38721 possible to shuffle bytes in between the lanes. */
38725 }
38726 }
38727 else
38729 }
38737 else
38738 {
38744 else
38748 {
38752 }
38753 }
38762 {
38769 else
38771 }
38772 else
38773 {
38776 }
38779 }
38781 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38782 in a single instruction. */
38784 static bool
38786 {
38790 /* Check plain VEC_SELECT first, because AVX has instructions that could
38791 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38792 input where SEL+CONCAT may not. */
38794 {
38800 {
38806 }
38809 {
38813 }
38815 {
38816 /* Use vpbroadcast{b,w,d}. */
38819 {
38838 /* For other modes prefer other shuffles this function creates. */
38840 }
38842 {
38846 }
38847 }
38852 /* There are plenty of patterns in sse.md that are written for
38853 SEL+CONCAT and are not replicated for a single op. Perhaps
38854 that should be changed, to avoid the nastiness here. */
38856 /* Recognize interleave style patterns, which means incrementing
38857 every other permutation operand. */
38859 {
38862 }
38867 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
38869 {
38871 {
38876 }
38881 }
38882 }
38884 /* Finally, try the fully general two operand permute. */
38889 /* Recognize interleave style patterns with reversed operands. */
38891 {
38893 {
38897 else
38900 }
38905 }
38907 /* Try the SSE4.1 blend variable merge instructions. */
38911 /* Try one of the AVX vpermil variable permutations. */
38915 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
38916 vpshufb, vpermd, vpermps or vpermq variable permutation. */
38921 }
38923 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38924 in terms of a pair of pshuflw + pshufhw instructions. */
38926 static bool
38928 {
38936 /* The two permutations only operate in 64-bit lanes. */
38947 /* Emit the pshuflw. */
38954 /* Emit the pshufhw. */
38962 }
38964 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38965 the permutation using the SSSE3 palignr instruction. This succeeds
38966 when all of the elements in PERM fit within one vector and we merely
38967 need to shift them down so that a single vector permutation has a
38968 chance to succeed. */
38970 static bool
38972 {
38976 rtx shift;
38978 /* Even with AVX, palignr only operates on 128-bit vectors. */
38984 {
38990 }
38994 /* Given that we have SSSE3, we know we'll be able to implement the
38995 single operand permutation after the palignr with pshufb. */
39009 {
39014 }
39016 /* Test for the degenerate case where the alignment by itself
39017 produces the desired permutation. */
39025 }
39029 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39030 a two vector permutation into a single vector permutation by using
39031 an interleave operation to merge the vectors. */
39033 static bool
39035 {
39040 rtx seq;
39044 {
39047 }
39049 {
39052 /* For 32-byte modes allow even d->one_operand_p.
39053 The lack of cross-lane shuffling in some instructions
39054 might prevent a single insn shuffle. */
39057 /* If expand_vec_perm_interleave3 can expand this into
39058 a 3 insn sequence, give up and let it be expanded as
39059 3 insn sequence. While that is one insn longer,
39060 it doesn't need a memory operand and in the common
39061 case that both interleave low and high permutations
39062 with the same operands are adjacent needs 4 insns
39063 for both after CSE. */
39066 }
39067 else
39070 /* Examine from whence the elements come. */
39079 {
39082 /* Split the two input vectors into 4 halves. */
39088 /* If the elements from the low halves use interleave low, and similarly
39089 for interleave high. If the elements are from mis-matched halves, we
39090 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39092 {
39093 /* punpckl* */
39095 {
39100 }
39103 }
39105 {
39106 /* punpckh* */
39108 {
39113 }
39116 }
39118 {
39119 /* shufps */
39121 {
39126 }
39128 {
39129 /* shufpd */
39134 }
39135 }
39137 {
39138 /* shufps */
39140 {
39145 }
39147 {
39148 /* shufpd */
39153 }
39154 }
39155 else
39157 }
39158 else
39159 {
39164 /* Split the two input vectors into 8 quarters. */
39170 {
39173 }
39176 {
39180 }
39182 {
39185 }
39188 {
39190 {
39191 /* Attempt to increase the likelihood that dfinal
39192 shuffle will be intra-lane. */
39196 }
39198 /* vperm2f128 or vperm2i128. */
39200 {
39205 }
39210 {
39214 {
39217 }
39218 }
39219 }
39224 {
39225 /* vpunpckl* */
39227 {
39236 }
39237 }
39240 {
39241 /* vpunpckh* */
39243 {
39252 }
39253 }
39254 else
39256 }
39258 /* Use the remapping array set up above to move the elements from their
39259 swizzled locations into their final destinations. */
39262 {
39265 /* If same_halves is true, both halves of the remapped vector are the
39266 same. Avoid cross-lane accesses if possible. */
39268 {
39271 }
39272 else
39274 }
39280 /* Test if the final remap can be done with a single insn. For V4SFmode or
39281 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39294 {
39298 }
39305 }
39307 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39308 a single vector cross-lane permutation into vpermq followed
39309 by any of the single insn permutations. */
39311 static bool
39313 {
39327 {
39330 }
39333 {
39338 }
39351 {
39358 }
39365 {
39370 ;
39373 else
39375 }
39384 }
39386 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39387 a vector permutation using two instructions, vperm2f128 resp.
39388 vperm2i128 followed by any single in-lane permutation. */
39390 static bool
39392 {
39406 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39407 immediate. For perm < 16 the second permutation uses
39408 d->op0 as first operand, for perm >= 16 it uses d->op1
39409 as first operand. The second operand is the result of
39410 vperm2[fi]128. */
39412 {
39413 /* Ignore permutations which do not move anything cross-lane. */
39415 {
39416 /* The second shuffle for e.g. V4DFmode has
39417 0123 and ABCD operands.
39418 Ignore AB23, as 23 is already in the second lane
39419 of the first operand. */
39421 /* And 01CD, as 01 is in the first lane of the first
39422 operand. */
39424 /* And 4567, as then the vperm2[fi]128 doesn't change
39425 anything on the original 4567 second operand. */
39427 }
39428 else
39429 {
39430 /* The second shuffle for e.g. V4DFmode has
39431 4567 and ABCD operands.
39432 Ignore AB67, as 67 is already in the second lane
39433 of the first operand. */
39435 /* And 45CD, as 45 is in the first lane of the first
39436 operand. */
39438 /* And 0123, as then the vperm2[fi]128 doesn't change
39439 anything on the original 0123 first operand. */
39441 }
39444 {
39450 else
39452 }
39455 {
39459 }
39460 else
39464 {
39468 /* Found a usable second shuffle. dfirst will be
39469 vperm2f128 on d->op0 and d->op1. */
39480 /* And dsecond is some single insn shuffle, taking
39481 d->op0 and result of vperm2f128 (if perm < 16) or
39482 d->op1 and result of vperm2f128 (otherwise). */
39491 }
39493 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39496 }
39499 }
39501 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39502 a two vector permutation using 2 intra-lane interleave insns
39503 and cross-lane shuffle for 32-byte vectors. */
39505 static bool
39507 {
39514 ;
39516 ;
39517 else
39532 {
39536 else
39542 else
39548 else
39554 else
39560 else
39566 else
39571 }
39575 }
39577 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39578 a single vector permutation using a single intra-lane vector
39579 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39580 the non-swapped and swapped vectors together. */
39582 static bool
39584 {
39587 rtx seq;
39592 || TARGET_AVX2
39601 {
39608 }
39643 }
39645 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39646 permutation using two vperm2f128, followed by a vshufpd insn blending
39647 the two vectors together. */
39649 static bool
39651 {
39694 }
39696 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39697 permutation with two pshufb insns and an ior. We should have already
39698 failed all two instruction sequences. */
39700 static bool
39702 {
39713 /* Generate two permutation masks. If the required element is within
39714 the given vector it is shuffled into the proper lane. If the required
39715 element is in the other vector, force a zero into the lane by setting
39716 bit 7 in the permutation mask. */
39719 {
39726 {
39729 }
39730 }
39750 }
39752 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39753 with two vpshufb insns, vpermq and vpor. We should have already failed
39754 all two or three instruction sequences. */
39756 static bool
39758 {
39773 /* Generate two permutation masks. If the required element is within
39774 the same lane, it is shuffled in. If the required element from the
39775 other lane, force a zero by setting bit 7 in the permutation mask.
39776 In the other mask the mask has non-negative elements if element
39777 is requested from the other lane, but also moved to the other lane,
39778 so that the result of vpshufb can have the two V2TImode halves
39779 swapped. */
39782 {
39787 {
39790 }
39791 }
39800 /* Swap the 128-byte lanes of h into hp. */
39804 const1_rtx));
39817 }
39819 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39820 and extract-odd permutations of two V32QImode and V16QImode operand
39821 with two vpshufb insns, vpor and vpermq. We should have already
39822 failed all two or three instruction sequences. */
39824 static bool
39826 {
39845 /* Generate two permutation masks. In the first permutation mask
39846 the first quarter will contain indexes for the first half
39847 of the op0, the second quarter will contain bit 7 set, third quarter
39848 will contain indexes for the second half of the op0 and the
39849 last quarter bit 7 set. In the second permutation mask
39850 the first quarter will contain bit 7 set, the second quarter
39851 indexes for the first half of the op1, the third quarter bit 7 set
39852 and last quarter indexes for the second half of the op1.
39853 I.e. the first mask e.g. for V32QImode extract even will be:
39854 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39855 (all values masked with 0xf except for -128) and second mask
39856 for extract even will be
39857 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39860 {
39866 {
39869 }
39870 }
39889 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
39896 }
39898 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
39899 and extract-odd permutations. */
39901 static bool
39903 {
39907 {
39912 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39916 /* Now an unpck[lh]pd will produce the result required. */
39919 else
39925 {
39932 /* Shuffle within the 128-bit lanes to produce:
39933 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
39937 /* Shuffle the lanes around to produce:
39938 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
39942 /* Shuffle within the 128-bit lanes to produce:
39943 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
39946 /* Shuffle within the 128-bit lanes to produce:
39947 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
39950 /* Shuffle the lanes around to produce:
39951 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
39954 }
39961 /* These are always directly implementable by expand_vec_perm_1. */
39967 else
39968 {
39969 /* We need 2*log2(N)-1 operations to achieve odd/even
39970 with interleave. */
39979 else
39982 }
39988 else
39989 {
40001 else
40004 }
40013 {
40020 }
40025 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40029 /* Now an vpunpck[lh]qdq will produce the result required. */
40032 else
40039 {
40046 }
40051 /* Shuffle the lanes around into
40052 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40062 /* Swap the 2nd and 3rd position in each lane into
40063 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40069 /* Now an vpunpck[lh]qdq will produce
40070 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40075 else
40084 }
40087 }
40089 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40090 extract-even and extract-odd permutations. */
40092 static bool
40094 {
40106 }
40108 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40109 permutations. We assume that expand_vec_perm_1 has already failed. */
40111 static bool
40113 {
40121 {
40124 /* These are special-cased in sse.md so that we can optionally
40125 use the vbroadcast instruction. They expand to two insns
40126 if the input happens to be in a register. */
40133 /* These are always implementable using standard shuffle patterns. */
40138 /* These can be implemented via interleave. We save one insn by
40139 stopping once we have promoted to V4SImode and then use pshufd. */
40140 do
40141 {
40142 rtx dest;
40148 {
40152 }
40159 }
40172 /* For AVX2 broadcasts of the first element vpbroadcast* or
40173 vpermq should be used by expand_vec_perm_1. */
40179 }
40180 }
40182 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40183 broadcast permutations. */
40185 static bool
40187 {
40199 }
40201 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40202 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40203 all the shorter instruction sequences. */
40205 static bool
40207 {
40223 /* Generate 4 permutation masks. If the required element is within
40224 the same lane, it is shuffled in. If the required element from the
40225 other lane, force a zero by setting bit 7 in the permutation mask.
40226 In the other mask the mask has non-negative elements if element
40227 is requested from the other lane, but also moved to the other lane,
40228 so that the result of vpshufb can have the two V2TImode halves
40229 swapped. */
40232 {
40237 }
40243 {
40251 }
40254 {
40256 {
40259 }
40266 }
40268 /* Swap the 128-byte lanes of h[X]. */
40270 {
40276 const1_rtx));
40278 }
40281 {
40283 {
40286 }
40292 }
40295 {
40297 {
40301 }
40304 }
40310 }
40312 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40313 With all of the interface bits taken care of, perform the expansion
40314 in D and return true on success. */
40316 static bool
40318 {
40319 /* Try a single instruction expansion. */
40323 /* Try sequences of two instructions. */
40343 /* Try sequences of three instructions. */
40357 /* Try sequences of four instructions. */
40365 /* ??? Look for narrow permutations whose element orderings would
40366 allow the promotion to a wider mode. */
40368 /* ??? Look for sequences of interleave or a wider permute that place
40369 the data into the correct lanes for a half-vector shuffle like
40370 pshuf[lh]w or vpermilps. */
40372 /* ??? Look for sequences of interleave that produce the desired results.
40373 The combinatorics of punpck[lh] get pretty ugly... */
40378 /* Even longer sequences. */
40383 }
40385 /* If a permutation only uses one operand, make it clear. Returns true
40386 if the permutation references both operands. */
40388 static bool
40390 {
40398 {
40404 {
40407 }
40408 /* The elements of PERM do not suggest that only the first operand
40409 is used, but both operands are identical. Allow easier matching
40410 of the permutation by folding the permutation into the single
40411 input vector. */
40412 /* FALLTHRU */
40423 }
40426 }
40428 bool
40430 {
40435 rtx sel;
40452 {
40457 }
40464 /* If the selector says both arguments are needed, but the operands are the
40465 same, the above tried to expand with one_operand_p and flattened selector.
40466 If that didn't work, retry without one_operand_p; we succeeded with that
40467 during testing. */
40469 {
40473 }
40476 }
40478 /* Implement targetm.vectorize.vec_perm_const_ok. */
40480 static bool
40483 {
40492 /* Given sufficient ISA support we can just return true here
40493 for selected vector modes. */
40495 {
40496 /* All implementable with a single vpperm insn. */
40499 /* All implementable with 2 pshufb + 1 ior. */
40502 /* All implementable with shufpd or unpck[lh]pd. */
40505 }
40507 /* Extract the values from the vector CST into the permutation
40508 array in D. */
40511 {
40515 }
40517 /* For all elements from second vector, fold the elements to first. */
40522 /* Check whether the mask can be applied to the vector type. */
40525 /* Implementable with shufps or pshufd. */
40529 /* Otherwise we have to go through the motions and see if we can
40530 figure out how to generate the requested permutation. */
40541 }
40543 void
40545 {
40560 /* We'll either be able to implement the permutation directly... */
40564 /* ... or we use the special-case patterns. */
40566 }
40568 static void
40570 {
40585 {
40588 }
40590 /* Note that for AVX this isn't one instruction. */
40593 }
40596 /* Expand a vector operation CODE for a V*QImode in terms of the
40597 same operation on V*HImode. */
40599 void
40601 {
40613 {
40626 }
40630 {
40632 /* Unpack data such that we've got a source byte in each low byte of
40633 each word. We don't care what goes into the high byte of each word.
40634 Rather than trying to get zero in there, most convenient is to let
40635 it be a copy of the low byte. */
40640 /* FALLTHRU */
40652 /* FALLTHRU */
40662 }
40664 /* Perform the operation. */
40671 /* Merge the data back into the right place. */
40681 {
40682 /* For SSE2, we used an full interleave, so the desired
40683 results are in the even elements. */
40686 }
40687 else
40688 {
40689 /* For AVX, the interleave used above was not cross-lane. So the
40690 extraction is evens but with the second and third quarter swapped.
40691 Happily, that is even one insn shorter than even extraction. */
40694 }
40701 }
40703 void
40706 {
40709 rtx x;
40711 /* We only play even/odd games with vectors of SImode. */
40714 /* If we're looking for the odd results, shift those members down to
40715 the even slots. For some cpus this is faster than a PSHUFD. */
40717 {
40719 {
40723 }
40732 }
40735 {
40738 else
40740 }
40745 else
40746 {
40749 /* The easiest way to implement this without PMULDQ is to go through
40750 the motions as if we are performing a full 64-bit multiply. With
40751 the exception that we need to do less shuffling of the elements. */
40753 /* Compute the sign-extension, aka highparts, of the two operands. */
40759 /* Multiply LO(A) * HI(B), and vice-versa. */
40765 /* Multiply LO(A) * LO(B). */
40769 /* Combine and shift the highparts into place. */
40774 /* Combine high and low parts. */
40777 }
40779 }
40781 void
40784 {
40790 {
40795 {
40796 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40797 shuffle the elements once so that all elements are in the right
40798 place for immediate use: { A C B D }. */
40803 }
40804 else
40805 {
40806 /* Put the elements into place for the multiply. */
40810 }
40815 /* Shuffle the elements between the lanes. After this we
40816 have { A B E F | C D G H } for each operand. */
40826 /* Shuffle the elements within the lanes. After this we
40827 have { A A B B | C C D D } or { E E F F | G G H H }. */
40863 }
40864 }
40866 void
40868 {
40878 /* Move the results in element 2 down to element 1; we don't care
40879 what goes in elements 2 and 3. Then we can merge the parts
40880 back together with an interleave.
40882 Note that two other sequences were tried:
40883 (1) Use interleaves at the start instead of psrldq, which allows
40884 us to use a single shufps to merge things back at the end.
40885 (2) Use shufps here to combine the two vectors, then pshufd to
40886 put the elements in the correct order.
40887 In both cases the cost of the reformatting stall was too high
40888 and the overall sequence slower. */
40897 }
40899 void
40901 {
40906 {
40907 /* op1: A,B,C,D, op2: E,F,G,H */
40916 /* t1: B,A,D,C */
40923 /* t2: (B*E),(A*F),(D*G),(C*H) */
40926 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
40929 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
40932 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
40934 }
40935 else
40936 {
40941 {
40944 }
40946 {
40949 }
40950 else
40954 /* Multiply low parts. */
40958 /* Shift input vectors right 32 bits so we can multiply high parts. */
40963 /* Multiply high parts by low parts. */
40969 /* Combine and shift the highparts back. */
40973 /* Combine high and low parts. */
40975 }
40979 }
40981 /* Expand an insert into a vector register through pinsr insn.
40982 Return true if successful. */
40984 bool
40986 {
40994 {
40997 }
41003 {
41008 {
41015 {
41047 }
41056 }
41060 }
41061 }
41062 \f
41063 /* This function returns the calling abi specific va_list type node.
41064 It returns the FNDECL specific va_list type. */
41066 static tree
41068 {
41075 else
41077 }
41079 /* Returns the canonical va_list type specified by TYPE. If there
41080 is no valid TYPE provided, it return NULL_TREE. */
41082 static tree
41084 {
41087 /* Resolve references and pointers to va_list type. */
41096 {
41101 {
41102 /* If va_list is an array type, the argument may have decayed
41103 to a pointer type, e.g. by being passed to another function.
41104 In that case, unwrap both types so that we can compare the
41105 underlying records. */
41108 {
41111 }
41112 }
41119 {
41120 /* If va_list is an array type, the argument may have decayed
41121 to a pointer type, e.g. by being passed to another function.
41122 In that case, unwrap both types so that we can compare the
41123 underlying records. */
41126 {
41129 }
41130 }
41137 {
41138 /* If va_list is an array type, the argument may have decayed
41139 to a pointer type, e.g. by being passed to another function.
41140 In that case, unwrap both types so that we can compare the
41141 underlying records. */
41144 {
41147 }
41148 }
41152 }
41154 }
41156 /* Iterate through the target-specific builtin types for va_list.
41157 IDX denotes the iterator, *PTREE is set to the result type of
41158 the va_list builtin, and *PNAME to its internal type.
41159 Returns zero if there is no element for this index, otherwise
41160 IDX should be increased upon the next call.
41161 Note, do not iterate a base builtin's name like __builtin_va_list.
41162 Used from c_common_nodes_and_builtins. */
41164 static int
41166 {
41168 {
41170 {
41183 }
41184 }
41187 }
41189 #undef TARGET_SCHED_DISPATCH
41190 #define TARGET_SCHED_DISPATCH has_dispatch
41191 #undef TARGET_SCHED_DISPATCH_DO
41192 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41193 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41194 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41195 #undef TARGET_SCHED_REORDER
41196 #define TARGET_SCHED_REORDER ix86_sched_reorder
41197 #undef TARGET_SCHED_ADJUST_PRIORITY
41198 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41199 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41200 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook
41202 /* The size of the dispatch window is the total number of bytes of
41203 object code allowed in a window. */
41204 #define DISPATCH_WINDOW_SIZE 16
41206 /* Number of dispatch windows considered for scheduling. */
41207 #define MAX_DISPATCH_WINDOWS 3
41209 /* Maximum number of instructions in a window. */
41210 #define MAX_INSN 4
41212 /* Maximum number of immediate operands in a window. */
41213 #define MAX_IMM 4
41215 /* Maximum number of immediate bits allowed in a window. */
41216 #define MAX_IMM_SIZE 128
41218 /* Maximum number of 32 bit immediates allowed in a window. */
41219 #define MAX_IMM_32 4
41221 /* Maximum number of 64 bit immediates allowed in a window. */
41222 #define MAX_IMM_64 2
41224 /* Maximum total of loads or prefetches allowed in a window. */
41225 #define MAX_LOAD 2
41227 /* Maximum total of stores allowed in a window. */
41228 #define MAX_STORE 1
41230 #undef BIG
41231 #define BIG 100
41234 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41237 disp_load,
41238 disp_store,
41239 disp_load_store,
41240 disp_prefetch,
41241 disp_imm,
41242 disp_imm_32,
41243 disp_imm_64,
41244 disp_branch,
41245 disp_cmp,
41246 disp_jcc,
41247 disp_last
41248 };
41250 /* Number of allowable groups in a dispatch window. It is an array
41251 indexed by dispatch_group enum. 100 is used as a big number,
41252 because the number of these kind of operations does not have any
41253 effect in dispatch window, but we need them for other reasons in
41254 the table. */
41257 };
41263 };
41265 /* Instruction path. */
41271 last_path
41272 };
41274 /* sched_insn_info defines a window to the instructions scheduled in
41275 the basic block. It contains a pointer to the insn_info table and
41276 the instruction scheduled.
41278 Windows are allocated for each basic block and are linked
41279 together. */
41281 rtx insn;
41288 /* Linked list of dispatch windows. This is a two way list of
41289 dispatch windows of a basic block. It contains information about
41290 the number of uops in the window and the total number of
41291 instructions and of bytes in the object code for this dispatch
41292 window. */
41310 /* Immediate valuse used in an insn. */
41312 {
41321 /* Get dispatch group of insn. */
41323 static enum dispatch_group
41325 {
41341 }
41343 /* Return true if insn is a compare instruction. */
41345 static bool
41347 {
41355 }
41357 /* Return true if a dispatch violation encountered. */
41359 static bool
41361 {
41365 }
41367 /* Return true if insn is a branch instruction. */
41369 static bool
41371 {
41373 }
41375 /* Return true if insn is a prefetch instruction. */
41377 static bool
41379 {
41381 }
41383 /* This function initializes a dispatch window and the list container holding a
41384 pointer to the window. */
41386 static void
41388 {
41394 else
41412 {
41418 }
41420 }
41422 /* This function allocates and initializes a dispatch window and the
41423 list container holding a pointer to the window. */
41427 {
41432 }
41434 /* This routine initializes the dispatch scheduling information. It
41435 initiates building dispatch scheduler tables and constructs the
41436 first dispatch window. */
41438 static void
41440 {
41441 /* Allocate a dispatch list and a window. */
41446 }
41448 /* This function returns true if a branch is detected. End of a basic block
41449 does not have to be a branch, but here we assume only branches end a
41450 window. */
41452 static bool
41454 {
41456 }
41458 /* This function is called when the end of a window processing is reached. */
41460 static void
41462 {
41465 {
41470 }
41472 }
41474 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41475 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41476 for 48 bytes of instructions. Note that these windows are not dispatch
41477 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41481 {
41483 {
41488 }
41494 }
41496 /* Increment the number of immediate operands of an instruction. */
41498 static int
41500 {
41505 {
41512 else
41523 {
41526 }
41531 }
41534 }
41536 /* Compute number of immediate operands of an instruction. */
41538 static void
41540 {
41543 }
41545 /* Return total size of immediate operands of an instruction along with number
41546 of corresponding immediate-operands. It initializes its parameters to zero
41547 befor calling FIND_CONSTANT.
41548 INSN is the input instruction. IMM is the total of immediates.
41549 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41550 bit immediates. */
41552 static int
41554 {
41562 }
41564 /* This function indicates if an operand of an instruction is an
41565 immediate. */
41567 static bool
41569 {
41578 }
41580 /* Return single or double path for instructions. */
41582 static enum insn_path
41584 {
41594 }
41596 /* Return insn dispatch group. */
41598 static enum dispatch_group
41600 {
41618 }
41620 /* Count number of GROUP restricted instructions in a dispatch
41621 window WINDOW_LIST. */
41623 static int
41625 {
41636 {
41655 }
41668 }
41670 /* This function returns true if insn satisfies dispatch rules on the
41671 last window scheduled. */
41673 static bool
41675 {
41683 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41684 instructions should be given the lowest priority in the
41685 scheduling process in Haifa scheduler to make sure they will be
41686 scheduled in the same dispatch window as the reference to them. */
41690 /* Check nonrestricted. */
41694 /* Get last dispatch window. */
41699 {
41704 /* Window 1 is full. Go for next window. */
41706 }
41713 /* See if it fits in the first window. */
41715 {
41716 /* The first widow should have only single and double path
41717 uops. */
41723 }
41725 }
41727 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41728 dispatch window WINDOW_LIST. */
41730 static void
41732 {
41750 /* Initialize window with new instruction. */
41771 {
41774 }
41775 }
41777 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41778 If the total bytes of instructions or the number of instructions in
41779 the window exceed allowable, it allocates a new window. */
41781 static void
41783 {
41806 /* Get the last dispatch window. */
41814 else
41817 /* If current window is full, get a new window.
41818 Window number zero is full, if MAX_INSN uops are scheduled in it.
41819 Window number one is full, if window zero's bytes plus window
41820 one's bytes is 32, or if the bytes of the new instruction added
41821 to the total makes it greater than 48, or it has already MAX_INSN
41822 instructions in it. */
41831 {
41834 }
41837 {
41841 {
41844 }
41845 }
41847 {
41852 {
41855 }
41858 }
41859 else
41863 {
41864 /* End of basic block is reached do end-basic-block process. */
41867 }
41868 }
41870 /* Print the dispatch window, WINDOW_NUM, to FILE. */
41872 DEBUG_FUNCTION static void
41874 {
41880 else
41894 {
41897 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
41903 }
41904 }
41906 /* Print to stdout a dispatch window. */
41908 DEBUG_FUNCTION void
41910 {
41912 }
41914 /* Print INSN dispatch information to FILE. */
41916 DEBUG_FUNCTION static void
41918 {
41941 }
41943 /* Print to STDERR the status of the ready list with respect to
41944 dispatch windows. */
41946 DEBUG_FUNCTION void
41948 {
41956 }
41958 /* This routine is the driver of the dispatch scheduler. */
41960 static void
41962 {
41967 }
41969 /* Return TRUE if Dispatch Scheduling is supported. */
41971 static bool
41973 {
41977 {
41993 }
41996 }
41998 /* Implementation of reassociation_width target hook used by
41999 reassoc phase to identify parallelism level in reassociated
42000 tree. Statements tree_code is passed in OPC. Arguments type
42001 is passed in MODE.
42003 Currently parallel reassociation is enabled for Atom
42004 processors only and we set reassociation width to be 2
42005 because Atom may issue up to 2 instructions per cycle.
42007 Return value should be fixed if parallel reassociation is
42008 enabled for other processors. */
42010 static int
42013 {
42022 }
42024 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42025 place emms and femms instructions. */
42027 static enum machine_mode
42029 {
42034 {
42047 else
42057 /* FALLTHRU */
42061 }
42062 }
42064 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42065 vectors. */
42067 static unsigned int
42069 {
42071 }
42073 \f
42075 /* Return class of registers which could be used for pseudo of MODE
42076 and of class RCLASS for spilling instead of memory. Return NO_REGS
42077 if it is not possible or non-profitable. */
42078 static reg_class_t
42080 {
42086 }
42088 /* Implement targetm.vectorize.init_cost. */
42092 {
42096 }
42098 /* Implement targetm.vectorize.add_stmt_cost. */
42100 static unsigned
42104 {
42109 {
42113 /* Statements in an inner loop relative to the loop being
42114 vectorized are weighted more heavily. The value here is
42115 arbitrary and could potentially be improved with analysis. */
42121 }
42124 }
42126 /* Implement targetm.vectorize.finish_cost. */
42128 static void
42131 {
42136 }
42138 /* Implement targetm.vectorize.destroy_cost_data. */
42140 static void
42142 {
42144 }
42146 /* Validate target specific memory model bits in VAL. */
42148 static unsigned HOST_WIDE_INT
42150 {
42157 {
42161 }
42164 {
42168 }
42170 {
42174 }
42176 }
42178 /* Initialize the GCC target structure. */
42179 #undef TARGET_RETURN_IN_MEMORY
42180 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42182 #undef TARGET_LEGITIMIZE_ADDRESS
42183 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42185 #undef TARGET_ATTRIBUTE_TABLE
42186 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42187 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42188 # undef TARGET_MERGE_DECL_ATTRIBUTES
42189 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42190 #endif
42192 #undef TARGET_COMP_TYPE_ATTRIBUTES
42193 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42195 #undef TARGET_INIT_BUILTINS
42196 #define TARGET_INIT_BUILTINS ix86_init_builtins
42197 #undef TARGET_BUILTIN_DECL
42198 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42199 #undef TARGET_EXPAND_BUILTIN
42200 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42202 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42203 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42204 ix86_builtin_vectorized_function
42206 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42207 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42209 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42210 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42212 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42213 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42215 #undef TARGET_BUILTIN_RECIPROCAL
42216 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42218 #undef TARGET_ASM_FUNCTION_EPILOGUE
42219 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42221 #undef TARGET_ENCODE_SECTION_INFO
42222 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42223 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42224 #else
42225 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42226 #endif
42228 #undef TARGET_ASM_OPEN_PAREN
42230 #undef TARGET_ASM_CLOSE_PAREN
42233 #undef TARGET_ASM_BYTE_OP
42234 #define TARGET_ASM_BYTE_OP ASM_BYTE
42236 #undef TARGET_ASM_ALIGNED_HI_OP
42237 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42238 #undef TARGET_ASM_ALIGNED_SI_OP
42239 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42240 #ifdef ASM_QUAD
42241 #undef TARGET_ASM_ALIGNED_DI_OP
42242 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42243 #endif
42245 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42246 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42248 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42249 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42251 #undef TARGET_ASM_UNALIGNED_HI_OP
42252 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42253 #undef TARGET_ASM_UNALIGNED_SI_OP
42254 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42255 #undef TARGET_ASM_UNALIGNED_DI_OP
42256 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42258 #undef TARGET_PRINT_OPERAND
42259 #define TARGET_PRINT_OPERAND ix86_print_operand
42260 #undef TARGET_PRINT_OPERAND_ADDRESS
42261 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42262 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42263 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42264 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42265 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42267 #undef TARGET_SCHED_INIT_GLOBAL
42268 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42269 #undef TARGET_SCHED_ADJUST_COST
42270 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42271 #undef TARGET_SCHED_ISSUE_RATE
42272 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42273 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42274 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42275 ia32_multipass_dfa_lookahead
42277 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42278 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42280 #undef TARGET_MEMMODEL_CHECK
42281 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42283 #ifdef HAVE_AS_TLS
42284 #undef TARGET_HAVE_TLS
42285 #define TARGET_HAVE_TLS true
42286 #endif
42287 #undef TARGET_CANNOT_FORCE_CONST_MEM
42288 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42289 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42290 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42292 #undef TARGET_DELEGITIMIZE_ADDRESS
42293 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42295 #undef TARGET_MS_BITFIELD_LAYOUT_P
42296 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42298 #if TARGET_MACHO
42299 #undef TARGET_BINDS_LOCAL_P
42300 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42301 #endif
42302 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42303 #undef TARGET_BINDS_LOCAL_P
42304 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42305 #endif
42307 #undef TARGET_ASM_OUTPUT_MI_THUNK
42308 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42309 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42310 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42312 #undef TARGET_ASM_FILE_START
42313 #define TARGET_ASM_FILE_START x86_file_start
42315 #undef TARGET_OPTION_OVERRIDE
42316 #define TARGET_OPTION_OVERRIDE ix86_option_override
42318 #undef TARGET_REGISTER_MOVE_COST
42319 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42320 #undef TARGET_MEMORY_MOVE_COST
42321 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42322 #undef TARGET_RTX_COSTS
42323 #define TARGET_RTX_COSTS ix86_rtx_costs
42324 #undef TARGET_ADDRESS_COST
42325 #define TARGET_ADDRESS_COST ix86_address_cost
42327 #undef TARGET_FIXED_CONDITION_CODE_REGS
42328 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42329 #undef TARGET_CC_MODES_COMPATIBLE
42330 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42332 #undef TARGET_MACHINE_DEPENDENT_REORG
42333 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42335 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42336 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42338 #undef TARGET_BUILD_BUILTIN_VA_LIST
42339 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42341 #undef TARGET_FOLD_BUILTIN
42342 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42344 #undef TARGET_COMPARE_VERSION_PRIORITY
42345 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42347 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42348 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42349 ix86_generate_version_dispatcher_body
42351 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42352 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42353 ix86_get_function_versions_dispatcher
42355 #undef TARGET_ENUM_VA_LIST_P
42356 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42358 #undef TARGET_FN_ABI_VA_LIST
42359 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42361 #undef TARGET_CANONICAL_VA_LIST_TYPE
42362 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42364 #undef TARGET_EXPAND_BUILTIN_VA_START
42365 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42367 #undef TARGET_MD_ASM_CLOBBERS
42368 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42370 #undef TARGET_PROMOTE_PROTOTYPES
42371 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42372 #undef TARGET_STRUCT_VALUE_RTX
42373 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
42374 #undef TARGET_SETUP_INCOMING_VARARGS
42375 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42376 #undef TARGET_MUST_PASS_IN_STACK
42377 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42378 #undef TARGET_FUNCTION_ARG_ADVANCE
42379 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42380 #undef TARGET_FUNCTION_ARG
42381 #define TARGET_FUNCTION_ARG ix86_function_arg
42382 #undef TARGET_FUNCTION_ARG_BOUNDARY
42383 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42384 #undef TARGET_PASS_BY_REFERENCE
42385 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42386 #undef TARGET_INTERNAL_ARG_POINTER
42387 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42388 #undef TARGET_UPDATE_STACK_BOUNDARY
42389 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42390 #undef TARGET_GET_DRAP_RTX
42391 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42392 #undef TARGET_STRICT_ARGUMENT_NAMING
42393 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42394 #undef TARGET_STATIC_CHAIN
42395 #define TARGET_STATIC_CHAIN ix86_static_chain
42396 #undef TARGET_TRAMPOLINE_INIT
42397 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42398 #undef TARGET_RETURN_POPS_ARGS
42399 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42401 #undef TARGET_LEGITIMATE_COMBINED_INSN
42402 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42404 #undef TARGET_ASAN_SHADOW_OFFSET
42405 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42407 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42408 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42410 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42411 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42413 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42414 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42416 #undef TARGET_C_MODE_FOR_SUFFIX
42417 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42419 #ifdef HAVE_AS_TLS
42420 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42421 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42422 #endif
42424 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42425 #undef TARGET_INSERT_ATTRIBUTES
42426 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42427 #endif
42429 #undef TARGET_MANGLE_TYPE
42430 #define TARGET_MANGLE_TYPE ix86_mangle_type
42432 #if !TARGET_MACHO
42433 #undef TARGET_STACK_PROTECT_FAIL
42434 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42435 #endif
42437 #undef TARGET_FUNCTION_VALUE
42438 #define TARGET_FUNCTION_VALUE ix86_function_value
42440 #undef TARGET_FUNCTION_VALUE_REGNO_P
42441 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42443 #undef TARGET_PROMOTE_FUNCTION_MODE
42444 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42446 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42447 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42449 #undef TARGET_INSTANTIATE_DECLS
42450 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42452 #undef TARGET_SECONDARY_RELOAD
42453 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42455 #undef TARGET_CLASS_MAX_NREGS
42456 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42458 #undef TARGET_PREFERRED_RELOAD_CLASS
42459 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42460 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42461 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42462 #undef TARGET_CLASS_LIKELY_SPILLED_P
42463 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42465 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42466 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42467 ix86_builtin_vectorization_cost
42468 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42469 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42470 ix86_vectorize_vec_perm_const_ok
42471 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42472 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42473 ix86_preferred_simd_mode
42474 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42475 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42476 ix86_autovectorize_vector_sizes
42477 #undef TARGET_VECTORIZE_INIT_COST
42478 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42479 #undef TARGET_VECTORIZE_ADD_STMT_COST
42480 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42481 #undef TARGET_VECTORIZE_FINISH_COST
42482 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42483 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42484 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42486 #undef TARGET_SET_CURRENT_FUNCTION
42487 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42489 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42490 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42492 #undef TARGET_OPTION_SAVE
42493 #define TARGET_OPTION_SAVE ix86_function_specific_save
42495 #undef TARGET_OPTION_RESTORE
42496 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42498 #undef TARGET_OPTION_PRINT
42499 #define TARGET_OPTION_PRINT ix86_function_specific_print
42501 #undef TARGET_OPTION_FUNCTION_VERSIONS
42502 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42504 #undef TARGET_CAN_INLINE_P
42505 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42507 #undef TARGET_EXPAND_TO_RTL_HOOK
42508 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42510 #undef TARGET_LEGITIMATE_ADDRESS_P
42511 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42513 #undef TARGET_LRA_P
42514 #define TARGET_LRA_P hook_bool_void_true
42516 #undef TARGET_REGISTER_PRIORITY
42517 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42519 #undef TARGET_LEGITIMATE_CONSTANT_P
42520 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42522 #undef TARGET_FRAME_POINTER_REQUIRED
42523 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42525 #undef TARGET_CAN_ELIMINATE
42526 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42528 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42529 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42531 #undef TARGET_ASM_CODE_END
42532 #define TARGET_ASM_CODE_END ix86_code_end
42534 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42535 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42537 #if TARGET_MACHO
42538 #undef TARGET_INIT_LIBFUNCS
42539 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42540 #endif
42542 #undef TARGET_SPILL_CLASS
42543 #define TARGET_SPILL_CLASS ix86_spill_class
42546 \f