1 ;; Machine description for Tilera TILEPro chip for GCC.
2 ;; Copyright (C) 2011-2013 Free Software Foundation, Inc.
3 ;; Contributed by Walter Lee (walt@tilera.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
23 ;; The following represent intrinsic insns, organized by latency.
27 (UNSPEC_INSN_ADDLIS 1)
29 (UNSPEC_INSN_AVGB_U 3)
32 (UNSPEC_INSN_CRC32_32 6)
33 (UNSPEC_INSN_CRC32_8 7)
35 (UNSPEC_INSN_DTLBPR 9)
36 (UNSPEC_INSN_DWORD_ALIGN 10)
38 (UNSPEC_INSN_FLUSH 12)
43 (UNSPEC_INSN_INFOL 17)
46 (UNSPEC_INSN_MFSPR 20)
49 (UNSPEC_INSN_MOVELIS 23)
50 (UNSPEC_INSN_MTSPR 24)
54 (UNSPEC_INSN_PACKBS_U 28)
55 (UNSPEC_INSN_PACKHB 29)
56 (UNSPEC_INSN_PACKHS 30)
57 (UNSPEC_INSN_PACKLB 31)
58 (UNSPEC_INSN_PREFETCH_L1 32)
59 (UNSPEC_INSN_TBLIDXB0 33)
60 (UNSPEC_INSN_TBLIDXB1 34)
61 (UNSPEC_INSN_TBLIDXB2 35)
62 (UNSPEC_INSN_TBLIDXB3 36)
66 (UNSPEC_INSN_ADIFFB_U 100)
67 (UNSPEC_INSN_ADIFFH 101)
68 (UNSPEC_INSN_MULHHA_SS 102)
69 (UNSPEC_INSN_MULHHA_SU 103)
70 (UNSPEC_INSN_MULHHA_UU 104)
71 (UNSPEC_INSN_MULHHSA_UU 105)
72 (UNSPEC_INSN_MULHH_SS 106)
73 (UNSPEC_INSN_MULHH_SU 107)
74 (UNSPEC_INSN_MULHH_UU 108)
75 (UNSPEC_INSN_MULHLA_SS 109)
76 (UNSPEC_INSN_MULHLA_SU 110)
77 (UNSPEC_INSN_MULHLA_US 111)
78 (UNSPEC_INSN_MULHLA_UU 112)
79 (UNSPEC_INSN_MULHLSA_UU 113)
80 (UNSPEC_INSN_MULHL_SS 114)
81 (UNSPEC_INSN_MULHL_SU 115)
82 (UNSPEC_INSN_MULHL_US 116)
83 (UNSPEC_INSN_MULHL_UU 117)
84 (UNSPEC_INSN_MULLLA_SS 118)
85 (UNSPEC_INSN_MULLLA_SU 119)
86 (UNSPEC_INSN_MULLLA_UU 120)
87 (UNSPEC_INSN_MULLLSA_UU 121)
88 (UNSPEC_INSN_MULLL_SU 122)
89 (UNSPEC_INSN_MULLL_SS 123)
90 (UNSPEC_INSN_MULLL_UU 124)
91 (UNSPEC_INSN_SADAB_U 125)
92 (UNSPEC_INSN_SADAH 126)
93 (UNSPEC_INSN_SADAH_U 127)
94 (UNSPEC_INSN_SADB_U 128)
95 (UNSPEC_INSN_SADH 129)
96 (UNSPEC_INSN_SADH_U 130)
99 ;; The following are special insns.
103 (UNSPEC_BLOCKAGE 200)
105 ;; Latency specifying loads.
106 (UNSPEC_LATENCY_L2 201)
107 (UNSPEC_LATENCY_MISS 202)
110 (UNSPEC_LNK_AND_LABEL 203)
115 ;; A pseudo-op that prevents network operations from being ordered.
116 (UNSPEC_NETWORK_BARRIER 205)
118 ;; Operations that access network registers.
119 (UNSPEC_NETWORK_RECEIVE 206)
120 (UNSPEC_NETWORK_SEND 207)
122 ;; Stack protector operations
126 ;; A call to __tls_get_addr
127 (UNSPEC_TLS_GD_CALL 210)
129 ;; An opaque TLS "add" operation for TLS general dynamic model
131 (UNSPEC_TLS_GD_ADD 211)
133 ;; An opaque TLS "load" operation for TLS initial exec model access.
134 (UNSPEC_TLS_IE_LOAD 212)
137 ;; The following are operands.
139 (UNSPEC_PCREL_SYM 300)
140 (UNSPEC_GOT16_SYM 301)
141 (UNSPEC_GOT32_SYM 302)
147 ;; Mark the last instruction of various latencies, used to
148 ;; determine the rtx costs of unspec insns.
150 (TILEPRO_LAST_LATENCY_1_INSN 99)
151 (TILEPRO_LAST_LATENCY_2_INSN 199)
152 (TILEPRO_LAST_LATENCY_INSN 299)
155 ;; Constants for network registers.
157 (TILEPRO_NETREG_IDN0 0)
158 (TILEPRO_NETREG_IDN1 1)
159 (TILEPRO_NETREG_SN 2)
160 (TILEPRO_NETREG_UDN0 3)
161 (TILEPRO_NETREG_UDN1 4)
162 (TILEPRO_NETREG_UDN2 5)
163 (TILEPRO_NETREG_UDN3 6)
166 ;; Constants for special purpose registers.
168 (TILEPRO_NETORDER_REG 66)])
171 ;; Operand and operator predicates and constraints
173 (include "predicates.md")
174 (include "constraints.md")
175 (include "tilepro-generic.md")
177 ;; Define an insn type attribute. This defines what pipes things can
180 "X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_miss,X01,Y0,Y0_2cycle,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing"
181 (const_string "Y01"))
183 (define_attr "length" ""
184 (cond [(eq_attr "type" "X1_branch")
186 (and (le (minus (match_dup 0) (pc)) (const_int 524280))
187 (le (minus (pc) (match_dup 0)) (const_int 524288)))
195 (define_mode_iterator I48MODE [SI DI])
196 (define_mode_iterator I12MODE [QI HI])
198 (define_code_iterator binop_u5bit [ashift ashiftrt lshiftrt rotate])
199 (define_code_iterator binop_with_imm
200 [ashift lshiftrt ashiftrt rotate eq lt and ior xor])
201 (define_code_iterator unop [bswap clz ctz popcount])
203 (define_mode_attr load [(QI "lb") (HI "lh") (SI "lw")])
204 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw")])
206 ;; <optab> expands to the name of the optab for a particular code.
207 (define_code_attr optab [(ashift "ashl")
233 (popcount "popcount")])
235 ;; <insn> expands to the name of the insn that implements a particular
237 (define_code_attr insn [(ashift "shl")
265 ;; <u> expands to the suffix of the insn that implements a particular
267 (define_code_attr u [(ashift "")
291 ;; <comm> indicates whether a particular code is commutative, using
292 ;; the "%" commutative opterator constraint.
293 (define_code_attr comm [(ashift "")
317 (define_mode_iterator VEC [V4QI V2HI])
319 ;; Code iterator for all three shifts.
320 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
322 ;; Code iterator for all byte ops without immediate variants.
323 (define_code_iterator v1op [us_plus ne le leu minus us_minus])
325 ;; Code iterator for all 2-byte vector ops without immediate variants.
326 (define_code_iterator v2op [ss_plus ne le leu minus ss_minus])
328 ;; Code iterator for all byte vector ops with immediate variants.
329 (define_code_iterator v1op_immed [plus umax umin eq lt ltu])
331 ;; Code iterator for all 2-byte vector ops with immediate variants.
332 (define_code_iterator v2op_immed [plus smax smin eq lt ltu])
334 ;; Code for packing two 2-byte vectors.
335 (define_code_iterator v2pack [truncate us_truncate])
337 ;; <pack_optab> expands to the part of the optab name describing how
338 ;; two vectors are packed.
339 (define_code_attr pack_optab [(truncate "trunc")
341 (ss_truncate "ssat")])
343 ;; <pack_insn> expands to the insn that implements a particular vector
345 (define_code_attr pack_insn [(truncate "packl")
347 (ss_truncate "pack")])
349 ;; <pack_u> expands to the suffix of the insn that implements a
350 ;; particular vector packing code.
351 (define_code_attr pack_u [(truncate "")
357 ;; The basic data move insns.
360 (define_expand "movqi"
361 [(set (match_operand:QI 0 "nonimmediate_operand" "")
362 (match_operand:QI 1 "nonautoinc_operand" ""))]
365 if (tilepro_expand_mov (QImode, operands))
369 (define_insn "*movqi_insn"
370 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,U,m")
371 (match_operand:QI 1 "move_operand" "r,I,U,m,rO,rO"))]
372 "(register_operand (operands[0], QImode)
373 || reg_or_0_operand (operands[1], QImode))"
378 lbadd_u\t%0, %I1, %i1
380 sbadd\t%I0, %r1, %i0"
381 [(set_attr "type" "*,*,Y2_2cycle,X1_2cycle,Y2,X1")])
383 (define_expand "movhi"
384 [(set (match_operand:HI 0 "nonimmediate_operand" "")
385 (match_operand:HI 1 "nonautoinc_operand" ""))]
388 if (tilepro_expand_mov (HImode, operands))
392 (define_insn "*movhi_insn"
393 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,r,U,m")
394 (match_operand:HI 1 "move_operand" "r,I,J,U,m,rO,rO"))]
395 "(register_operand (operands[0], HImode)
396 || reg_or_0_operand (operands[1], HImode))"
402 lhadd_u\t%0, %I1, %i1
404 shadd\t%I0, %r1, %i0"
405 [(set_attr "type" "*,*,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
408 (define_expand "movsi"
409 [(set (match_operand:SI 0 "nonimmediate_operand" "")
410 (match_operand:SI 1 "nonautoinc_operand" ""))]
413 if (tilepro_expand_mov (SImode, operands))
417 (define_insn "*movsi_high_insn"
418 [(set (match_operand:SI 0 "register_operand" "=r")
419 (high:SI (match_operand:SI 1 "symbolic_operand" "in")))]
421 "auli\t%0, zero, ha16(%1)"
422 [(set_attr "type" "X01")])
424 (define_insn "*movsi_insn"
425 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,r,U,m")
426 (match_operand:SI 1 "move_operand" "r,I,J,K,N,P,U,m,rO,rO"))]
427 "(register_operand (operands[0], SImode)
428 || reg_or_0_operand (operands[1], SImode))"
439 swadd\t%I0, %r1, %i0"
440 [(set_attr "type" "*,*,X01,X01,X01,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
442 (define_insn "movstrictqi"
443 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
444 (match_operand:QI 1 "reg_or_0_operand" "rO"))]
446 "mm\t%r0, %r1, %r0, 0, 7"
447 [(set_attr "type" "X01")])
449 (define_insn "movstricthi"
450 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
451 (match_operand:HI 1 "reg_or_0_operand" "rO"))]
453 "mm\t%r0, %r1, %r0, 0, 15"
454 [(set_attr "type" "X01")])
456 (define_expand "movmisalign<mode>"
457 [(set (match_operand:VEC 0 "nonautoincmem_nonimmediate_operand" "")
458 (match_operand:VEC 1 "nonautoincmem_general_operand" ""))]
461 tilepro_expand_movmisalign (<MODE>mode, operands);
465 (define_expand "movsf"
466 [(set (match_operand:SF 0 "nonimmediate_operand" "")
467 (match_operand:SF 1 "general_operand" ""))]
470 /* Materialize immediates using clever SImode code, but don't
471 do this after reload starts, since gen_lowpart will choke
472 during reload if given an illegitimate address. */
473 if (immediate_operand (operands[1], SFmode)
474 && operands[1] != const0_rtx
475 && (register_operand (operands[0], SFmode)
476 || (!reload_in_progress && !reload_completed)))
478 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
479 gen_lowpart (SImode, operands[1])));
484 (define_insn "*movsf"
485 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,U,m")
486 (match_operand:SF 1 "general_operand" "rO,U,m,rO,rO"))]
493 swadd\t%I0, %r1, %i0"
494 [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
496 (define_expand "mov<mode>"
497 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
498 (match_operand:VEC 1 "general_operand" ""))]
501 /* Materialize immediates using clever SImode code, but don't
502 do this after reload starts, since gen_lowpart will choke
503 during reload if given an illegitimate address. */
504 if (immediate_operand (operands[1], <MODE>mode)
505 && operands[1] != const0_rtx
506 && (register_operand (operands[0], <MODE>mode)
507 || (!reload_in_progress && !reload_completed)))
509 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
510 gen_lowpart (SImode, operands[1])));
515 (define_insn "*mov<mode>"
516 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,U,m")
517 (match_operand:VEC 1 "general_operand" "rO,U,m,rO,rO"))]
524 swadd\t%I0, %r1, %i0"
525 [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
529 ;; Bit-field extracts
532 (define_expand "extv"
533 [(set (match_operand:SI 0 "register_operand" "")
535 (match_operand:QI 1 "nonautoincmem_operand" "")
536 (match_operand:SI 2 "immediate_operand" "")
537 (match_operand:SI 3 "immediate_operand" "")))]
540 HOST_WIDE_INT bit_offset, bit_width;
541 HOST_WIDE_INT first_byte_offset, last_byte_offset;
543 bit_width = INTVAL (operands[2]);
544 bit_offset = INTVAL (operands[3]);
546 /* Reject bitfields that can be done with a normal load */
547 if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
550 /* The value in memory cannot span more than 4 bytes. */
551 first_byte_offset = bit_offset / BITS_PER_UNIT;
552 last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
553 if (last_byte_offset - first_byte_offset > 3)
556 tilepro_expand_unaligned_load (operands[0], operands[1],
557 bit_width, bit_offset, 1);
562 (define_expand "extzv"
563 [(set (match_operand:SI 0 "register_operand" "")
565 (match_operand:QI 1 "nonautoincmem_operand" "")
566 (match_operand:SI 2 "immediate_operand" "")
567 (match_operand:SI 3 "immediate_operand" "")))]
570 HOST_WIDE_INT bit_offset, bit_width;
571 HOST_WIDE_INT first_byte_offset, last_byte_offset;
573 bit_width = INTVAL (operands[2]);
574 bit_offset = INTVAL (operands[3]);
576 /* Reject bitfields that can be done with a normal load */
577 if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
580 /* The value in memory cannot span more than 4 bytes. */
581 first_byte_offset = bit_offset / BITS_PER_UNIT;
582 last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
583 if (last_byte_offset - first_byte_offset > 3)
586 tilepro_expand_unaligned_load (operands[0], operands[1],
587 bit_width, bit_offset, 0);
597 (define_insn "*s123a_insn"
598 [(set (match_operand:SI 0 "register_operand" "=r")
599 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
600 (match_operand:SI 2 "cint_248_operand" "I"))
601 (match_operand:SI 3 "reg_or_0_operand" "rO")))]
603 "s%t2a\t%0, %r1, %r3")
605 (define_expand "addsi3"
606 [(set (match_operand:SI 0 "register_operand" "")
607 (plus:SI (match_operand:SI 1 "register_operand" "")
608 (match_operand:SI 2 "reg_or_cint_operand" "")))]
611 if (tilepro_expand_addsi (operands[0], operands[1], operands[2]))
615 (define_insn "*addsi_high_insn"
616 [(set (match_operand:SI 0 "register_operand" "=r")
618 (match_operand:SI 1 "reg_or_0_operand" "%rO")
619 (high:SI (match_operand:SI 2 "const_symbolic_operand" "T"))))]
622 [(set_attr "type" "X01")])
624 (define_insn "*addsi_lo_sum_insn"
625 [(set (match_operand:SI 0 "register_operand" "=r")
627 (match_operand:SI 1 "reg_or_0_operand" "%rO")
628 (match_operand:SI 2 "const_symbolic_operand" "T")))]
630 "addli\t%0, %r1, %L2"
631 [(set_attr "type" "X01")])
633 (define_insn "*addsi3_insn"
634 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
635 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO,rO,rO")
636 (match_operand:SI 2 "add_operand" "r,I,J,K")))]
643 [(set_attr "type" "*,*,X01,X01")])
645 (define_insn "subsi3"
646 [(set (match_operand:SI 0 "register_operand" "=r")
647 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
648 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
652 (define_insn "negsi2"
653 [(set (match_operand:SI 0 "register_operand" "=r")
654 (neg:SI (match_operand:SI 1 "reg_or_0_operand" "rO")))]
656 "sub\t%0, zero, %r1")
658 (define_insn "ssaddsi3"
659 [(set (match_operand:SI 0 "register_operand" "=r")
660 (ss_plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
661 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
664 [(set_attr "type" "X01")])
666 (define_insn "sssubsi3"
667 [(set (match_operand:SI 0 "register_operand" "=r")
668 (ss_minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
669 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
672 [(set_attr "type" "X01")])
678 ;; ashift, ashiftrt, lshiftrt, rotate.
679 (define_insn "<optab>si3"
680 [(set (match_operand:SI 0 "register_operand" "=r,r")
681 (binop_u5bit:SI (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
682 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO")))]
686 <insn>\t%0, %r1, %r2")
693 (define_expand "cstore<mode>4"
694 [(set (match_operand:SI 0 "register_operand" "")
695 (match_operator:SI 1 "ordered_comparison_operator"
696 [(match_operand:I48MODE 2 "reg_or_cint_operand" "")
697 (match_operand:I48MODE 3 "reg_or_cint_operand" "")]))]
699 { if (!tilepro_emit_setcc (operands, <MODE>mode)) FAIL; else DONE; })
701 (define_insn "insn_seq"
702 [(set (match_operand:SI 0 "register_operand" "=r,r")
703 (eq:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO")
704 (match_operand:SI 2 "reg_or_cint_operand" "I,rO")))]
710 (define_insn "insn_sne"
711 [(set (match_operand:SI 0 "register_operand" "=r")
712 (ne:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
713 (match_operand:SI 2 "reg_or_cint_operand" "rO")))]
717 (define_insn "insn_slt"
718 [(set (match_operand:SI 0 "register_operand" "=r,r")
719 (lt:SI (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
720 (match_operand:SI 2 "reg_or_cint_operand" "I,rO")))]
726 (define_insn "insn_slte"
727 [(set (match_operand:SI 0 "register_operand" "=r,r")
728 (le:SI (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
729 (match_operand:SI 2 "reg_or_cint_operand" "L,rO")))]
735 (define_insn "insn_slt_u"
736 [(set (match_operand:SI 0 "register_operand" "=r,r")
737 (ltu:SI (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
738 (match_operand:SI 2 "reg_or_cint_operand" "I,rO")))]
742 slt_u\t%0, %r1, %r2")
744 (define_insn "insn_slte_u"
745 [(set (match_operand:SI 0 "register_operand" "=r,r")
746 (leu:SI (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
747 (match_operand:SI 2 "reg_or_cint_operand" "Q,rO")))]
751 slte_u\t%0, %r1, %r2")
758 (define_insn "andsi3"
759 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
760 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO,rO")
761 (match_operand:SI 2 "and_operand" "I,M,rO")))]
765 mm\t%0, %r1, zero, %M2
767 [(set_attr "type" "*,X01,*")])
769 (define_insn "iorsi3"
770 [(set (match_operand:SI 0 "register_operand" "=r,r")
771 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO")
772 (match_operand:SI 2 "reg_or_s8bit_operand" "I,rO")))]
778 (define_insn "xorsi3"
779 [(set (match_operand:SI 0 "register_operand" "=r,r")
780 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO")
781 (match_operand:SI 2 "reg_or_s8bit_operand" "rO,I")))]
786 [(set_attr "type" "*,X01")])
788 ;; bswap, clz, ctz, popcount
789 (define_insn "<optab>si2"
790 [(set (match_operand:SI 0 "register_operand" "=r")
791 (unop:SI (match_operand:SI 1 "reg_or_0_operand" "rO")))]
794 [(set_attr "type" "Y0")])
796 (define_expand "ctzdi2"
797 [(set (match_operand:DI 0 "register_operand" "")
798 (ctz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
801 rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, result;
803 split_di (&operands[1], 1, &lo, &hi);
804 lo = force_reg (SImode, lo);
805 hi = force_reg (SImode, hi);
807 ctz_lo = gen_reg_rtx (SImode);
808 emit_insn (gen_ctzsi2 (ctz_lo, lo));
810 ctz_hi = gen_reg_rtx (SImode);
811 emit_insn (gen_ctzsi2 (ctz_hi, hi));
813 ctz_hi_plus_32 = gen_reg_rtx (SImode);
814 emit_insn (gen_addsi3 (ctz_hi_plus_32, ctz_hi, GEN_INT (32)));
816 result = gen_reg_rtx (SImode);
817 emit_insn (gen_insn_mvz (result, ctz_lo, lo, ctz_hi_plus_32));
819 emit_move_insn (operands[0], convert_to_mode (DImode, result, 1));
824 (define_expand "clzdi2"
825 [(set (match_operand:DI 0 "register_operand" "")
826 (clz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
829 rtx lo, hi, clz_lo, clz_hi, clz_lo_plus_32, result;
831 split_di (&operands[1], 1, &lo, &hi);
832 lo = force_reg (SImode, lo);
833 hi = force_reg (SImode, hi);
835 clz_lo = gen_reg_rtx (SImode);
836 emit_insn (gen_clzsi2 (clz_lo, lo));
838 clz_hi = gen_reg_rtx (SImode);
839 emit_insn (gen_clzsi2 (clz_hi, hi));
841 clz_lo_plus_32 = gen_reg_rtx (SImode);
842 emit_insn (gen_addsi3 (clz_lo_plus_32, clz_lo, GEN_INT (32)));
844 result = gen_reg_rtx (SImode);
845 emit_insn (gen_insn_mvz (result, clz_hi, hi, clz_lo_plus_32));
847 emit_move_insn (operands[0], convert_to_mode (DImode, result, 1));
852 (define_expand "ffsdi2"
853 [(set (match_operand:DI 0 "register_operand" "")
854 (ffs:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
857 rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, ctz, ctz_plus_1,ctz_cond;
860 split_di (&operands[1], 1, &lo, &hi);
861 lo = force_reg (SImode, lo);
862 hi = force_reg (SImode, hi);
864 ctz_lo = gen_reg_rtx (SImode);
865 emit_insn (gen_ctzsi2 (ctz_lo, lo));
867 ctz_hi = gen_reg_rtx (SImode);
868 emit_insn (gen_ctzsi2 (ctz_hi, hi));
870 ctz_hi_plus_32 = gen_reg_rtx (SImode);
871 emit_insn (gen_addsi3 (ctz_hi_plus_32, ctz_hi, GEN_INT (32)));
873 ctz = gen_reg_rtx (SImode);
874 emit_insn (gen_insn_mvz (ctz, ctz_lo, lo, ctz_hi_plus_32));
876 ctz_plus_1 = gen_reg_rtx (SImode);
877 emit_insn (gen_addsi3 (ctz_plus_1, ctz, GEN_INT (1)));
879 ctz_cond = gen_reg_rtx (SImode);
880 emit_insn (gen_iorsi3 (ctz_cond, lo, hi));
882 result = gen_reg_rtx (SImode);
883 emit_insn (gen_insn_mvz (result, ctz_plus_1, ctz_cond, const0_rtx));
885 emit_move_insn (operands[0], convert_to_mode (DImode, result, 1));
890 (define_expand "popcountdi2"
891 [(set (match_operand:DI 0 "register_operand" "")
892 (popcount:DI (match_operand:DI 1 "nonmemory_operand" "")))]
895 rtx lo, hi, popcount_lo, popcount_hi, result;
897 split_di (&operands[1], 1, &lo, &hi);
898 lo = force_reg (SImode, lo);
899 hi = force_reg (SImode, hi);
901 popcount_lo = gen_reg_rtx (SImode);
902 emit_insn (gen_popcountsi2 (popcount_lo, lo));
904 popcount_hi = gen_reg_rtx (SImode);
905 emit_insn (gen_popcountsi2 (popcount_hi, hi));
907 result = gen_reg_rtx (SImode);
908 emit_insn (gen_addsi3 (result, popcount_lo, popcount_hi));
910 emit_move_insn (operands[0], convert_to_mode (DImode, result, 1));
915 (define_expand "paritysi2"
916 [(set (match_operand:SI 0 "register_operand" "")
917 (parity:SI (match_operand:SI 1 "reg_or_0_operand" "")))]
920 operands[2] = gen_reg_rtx (SImode);
921 emit_insn (gen_popcountsi2 (operands[2], operands[1]));
922 emit_insn (gen_andsi3 (operands[0], operands[2], const1_rtx));
926 (define_expand "paritydi2"
927 [(set (match_operand:DI 0 "register_operand" "")
928 (parity:DI (match_operand:DI 1 "nonmemory_operand" "")))]
931 rtx lo, hi, xor_lohi, result;
933 split_di (&operands[1], 1, &lo, &hi);
934 lo = force_reg (SImode, lo);
935 hi = force_reg (SImode, hi);
937 xor_lohi = gen_reg_rtx (SImode);
938 emit_insn (gen_xorsi3 (xor_lohi, lo, hi));
940 result = gen_reg_rtx (SImode);
941 emit_insn (gen_paritysi2 (result, xor_lohi));
943 emit_move_insn (operands[0], convert_to_mode (DImode, result, 1));
948 (define_insn "one_cmplsi2"
949 [(set (match_operand:SI 0 "register_operand" "=r")
950 (not:SI (match_operand:SI 1 "reg_or_0_operand" "rO")))]
952 "nor\t%0, %r1, zero")
956 ;; Conditional moves.
959 (define_expand "movsicc"
960 [(set (match_operand:SI 0 "register_operand" "")
961 (if_then_else:SI (match_operand 1 "comparison_operator" "")
962 (match_operand:SI 2 "reg_or_0_operand" "")
963 (match_operand:SI 3 "reg_or_0_operand" "")))]
965 { operands[1] = tilepro_emit_conditional_move (operands[1]); })
967 (define_insn "movcc_insn"
968 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
970 (match_operator 4 "eqne_operator"
971 [(match_operand:SI 1 "reg_or_0_operand" "rO,rO,rO,rO")
973 (match_operand:SI 2 "reg_or_0_operand" "rO,O,rO,0")
974 (match_operand:SI 3 "reg_or_0_operand" "O,rO,0,rO")))]
981 [(set_attr "type" "*,*,Y0,Y0")])
983 (define_expand "insn_mz"
984 [(set (match_operand:SI 0 "register_operand" "")
986 (eq (match_operand:SI 1 "reg_or_0_operand" "")
988 (match_operand:SI 2 "reg_or_0_operand" "")
991 (define_expand "insn_mnz"
992 [(set (match_operand:SI 0 "register_operand" "")
994 (ne (match_operand:SI 1 "reg_or_0_operand" "")
996 (match_operand:SI 2 "reg_or_0_operand" "")
999 (define_expand "insn_mvz"
1000 [(set (match_operand:SI 0 "register_operand" "")
1002 (eq (match_operand:SI 2 "reg_or_0_operand" "")
1004 (match_operand:SI 3 "reg_or_0_operand" "")
1005 (match_operand:SI 1 "reg_or_0_operand" "")))])
1007 (define_expand "insn_mvnz"
1008 [(set (match_operand:SI 0 "register_operand" "")
1010 (ne (match_operand:SI 2 "reg_or_0_operand" "")
1012 (match_operand:SI 3 "reg_or_0_operand" "")
1013 (match_operand:SI 1 "reg_or_0_operand" "")))])
1020 (define_insn "zero_extendqisi2"
1021 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1022 (zero_extend:SI (match_operand:QI 1 "move_operand" "rO,U,m")))]
1025 mm\t%0, %r1, zero, 0, 7
1027 lbadd_u\t%0, %I1, %i1"
1028 [(set_attr "type" "X01,Y2_2cycle,X1_2cycle")])
1030 (define_insn "zero_extendhisi2"
1031 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1032 (zero_extend:SI (match_operand:HI 1 "move_operand" "rO,U,m")))]
1035 mm\t%0, %r1, zero, 0, 15
1037 lhadd_u\t%0, %I1, %i1"
1038 [(set_attr "type" "X01,Y2_2cycle,X1_2cycle")])
1040 (define_expand "extendhisi2"
1041 [(set (match_operand:SI 0 "register_operand" "")
1042 (sign_extend:SI (match_operand:HI 1 "move_operand" "")))]
1045 if (!memory_operand (operands[1], HImode))
1047 operands[1] = gen_lowpart (SImode, operands[1]);
1048 operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
1050 emit_move_insn (operands[2], gen_rtx_ASHIFT (SImode, operands[1],
1052 emit_move_insn (operands[0], gen_rtx_ASHIFTRT (SImode, operands[2],
1059 [(set (match_operand:SI 0 "register_operand" "=r,r")
1060 (sign_extend:SI (match_operand:HI 1 "memory_operand" "U,m")))]
1064 lhadd\t%0, %I1, %i1"
1065 [(set_attr "type" "Y2_2cycle,X1_2cycle")])
1067 (define_expand "extendqisi2"
1068 [(set (match_operand:SI 0 "register_operand" "")
1069 (sign_extend:SI (match_operand:QI 1 "move_operand" "")))]
1072 if (!memory_operand (operands[1], QImode))
1074 operands[1] = gen_lowpart (SImode, operands[1]);
1075 operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
1077 emit_move_insn (operands[2], gen_rtx_ASHIFT (SImode, operands[1],
1079 emit_move_insn (operands[0], gen_rtx_ASHIFTRT (SImode, operands[2],
1086 [(set (match_operand:SI 0 "register_operand" "=r,r")
1087 (sign_extend:SI (match_operand:QI 1 "memory_operand" "U,m")))]
1091 lbadd\t%0, %I1, %i1"
1092 [(set_attr "type" "Y2_2cycle,X1_2cycle")])
1097 (define_expand "insv"
1098 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
1099 (match_operand:SI 1 "u5bit_cint_operand" "")
1100 (match_operand:SI 2 "u5bit_cint_operand" ""))
1101 (match_operand:SI 3 "reg_or_cint_operand" ""))]
1104 tilepro_expand_insv (operands);
1108 (define_insn "*insv_tblidxb0"
1109 [(set (zero_extract:SI
1110 (match_operand:SI 0 "register_operand" "+r")
1113 (match_operand:SI 1 "register_operand" "rO"))]
1116 [(set_attr "type" "Y0")])
1118 (define_insn "*insv_tblidxb1"
1119 [(set (zero_extract:SI
1120 (match_operand:SI 0 "register_operand" "+r")
1126 (match_operand:SI 1 "register_operand" "rO")))]
1129 [(set_attr "type" "Y0")])
1131 (define_insn "*insv_tblidxb2"
1132 [(set (zero_extract:SI
1133 (match_operand:SI 0 "register_operand" "+r")
1139 (match_operand:SI 1 "register_operand" "rO")))]
1142 [(set_attr "type" "Y0")])
1144 (define_insn "*insv_tblidxb3"
1145 [(set (zero_extract:SI
1146 (match_operand:SI 0 "register_operand" "+r")
1152 (match_operand:SI 1 "register_operand" "rO")))]
1155 [(set_attr "type" "Y0")])
1157 (define_insn "*insv_mm1"
1158 [(set (zero_extract:SI
1159 (match_operand:SI 0 "register_operand" "+r")
1160 (match_operand:SI 1 "u5bit_cint_operand" "n")
1162 (match_operand:SI 2 "register_operand" "rO"))]
1164 "mm\t%0, %r2, %0, 0, %1-1"
1165 [(set_attr "type" "X01")])
1167 (define_insn "*insv_mm2"
1168 [(set (zero_extract:SI
1169 (match_operand:SI 0 "register_operand" "+r")
1170 (match_operand:SI 1 "u5bit_cint_operand" "n")
1171 (match_operand:SI 2 "u5bit_cint_operand" "n"))
1173 (match_operand:SI 3 "register_operand" "rO")
1177 "mm\t%0, %r3, %0, %2, %2+%1-1"
1178 [(set_attr "type" "X01")])
1185 (define_expand "mulsi3"
1186 [(set (match_operand:SI 0 "register_operand" "=r")
1187 (mult:SI (zero_extend:SI
1188 (subreg:HI (match_operand:SI 1 "nonmemory_operand" "") 0))
1190 (subreg:HI (match_operand:SI 2 "nonmemory_operand" "") 0))))
1192 (unspec:SI [(match_dup 0) (match_dup 1) (match_dup 2)]
1193 UNSPEC_INSN_MULHLSA_UU))
1195 (unspec:SI [(match_dup 0) (match_dup 2) (match_dup 1)]
1196 UNSPEC_INSN_MULHLSA_UU))]
1199 operands[1] = force_reg (SImode, operands[1]);
1200 operands[1] = make_safe_from (operands[1], operands[0]);
1202 if (tilepro_expand_mulsi (operands[0], operands[1], operands[2]))
1206 operands[2] = force_reg (SImode, operands[2]);
1207 operands[2] = make_safe_from (operands[2], operands[0]);
1211 (define_insn "mulhisi3"
1212 [(set (match_operand:SI 0 "register_operand" "=r")
1213 (mult:SI (sign_extend:SI
1214 (match_operand:HI 1 "reg_or_0_operand" "rO"))
1216 (match_operand:HI 2 "reg_or_0_operand" "rO"))))]
1218 "mulll_ss\t%0, %r1, %r2"
1219 [(set_attr "type" "Y0_2cycle")])
1221 (define_insn "umulhisi3"
1222 [(set (match_operand:SI 0 "register_operand" "=r")
1223 (mult:SI (zero_extend:SI
1224 (match_operand:HI 1 "reg_or_0_operand" "rO"))
1226 (match_operand:HI 2 "reg_or_0_operand" "rO"))))]
1228 "mulll_uu\t%0, %r1, %r2"
1229 [(set_attr "type" "Y0_2cycle")])
1231 (define_insn "usmulhisi3"
1232 [(set (match_operand:SI 0 "register_operand" "=r")
1233 (mult:SI (zero_extend:SI
1234 (match_operand:HI 1 "reg_or_0_operand" "rO"))
1236 (match_operand:HI 2 "reg_or_0_operand" "rO"))))]
1238 "mulll_su\t%0, %r2, %r1"
1239 [(set_attr "type" "X0_2cycle")])
1241 (define_insn "maddhisi4"
1242 [(set (match_operand:SI 0 "register_operand" "=r")
1244 (mult:SI (sign_extend:SI
1245 (match_operand:HI 1 "reg_or_0_operand" "rO"))
1247 (match_operand:HI 2 "reg_or_0_operand" "rO")))
1248 (match_operand:SI 3 "register_operand" "0")))]
1250 "mullla_ss\t%0, %r1, %r2"
1251 [(set_attr "type" "Y0_2cycle")])
1253 (define_insn "umaddhisi4"
1254 [(set (match_operand:SI 0 "register_operand" "=r")
1256 (mult:SI (zero_extend:SI
1257 (match_operand:HI 1 "reg_or_0_operand" "rO"))
1259 (match_operand:HI 2 "reg_or_0_operand" "rO")))
1260 (match_operand:SI 3 "register_operand" "0")))]
1262 "mullla_uu\t%0, %r1, %r2"
1263 [(set_attr "type" "Y0_2cycle")])
1266 (define_insn "mulqihi3"
1267 [(set (match_operand:HI 0 "register_operand" "=r")
1268 (mult:HI (sign_extend:HI
1269 (match_operand:QI 1 "reg_or_0_operand" "rO"))
1271 (match_operand:QI 2 "reg_or_0_operand" "rO"))))]
1273 "mulll_ss\t%0, %r1, %r2"
1274 [(set_attr "type" "Y0_2cycle")])
1276 (define_insn "umulqihi3"
1277 [(set (match_operand:HI 0 "register_operand" "=r")
1278 (mult:HI (zero_extend:HI
1279 (match_operand:QI 1 "reg_or_0_operand" "rO"))
1281 (match_operand:QI 2 "reg_or_0_operand" "rO"))))]
1283 "mulll_uu\t%0, %r1, %r2"
1284 [(set_attr "type" "Y0_2cycle")])
1286 (define_expand "smulsi3_highpart"
1287 [(set (match_operand:SI 0 "register_operand" "")
1290 (mult:DI (sign_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))
1291 (sign_extend:DI (match_operand:SI 2 "reg_or_0_operand" "")))
1295 tilepro_expand_smulsi3_highpart (operands[0], operands[1], operands[2]);
1299 (define_expand "umulsi3_highpart"
1300 [(set (match_operand:SI 0 "register_operand" "")
1303 (mult:DI (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))
1304 (zero_extend:DI (match_operand:SI 2 "reg_or_0_operand" "")))
1308 tilepro_expand_umulsi3_highpart (operands[0], operands[1], operands[2]);
1317 ;; Define the subtract-one-and-jump insns so loop.c knows what to
1319 (define_expand "doloop_end"
1320 [(use (match_operand 0 "" "")) ;; loop pseudo
1321 (use (match_operand 1 "" "")) ;; iterations; zero if unknown
1322 (use (match_operand 2 "" "")) ;; max iterations
1323 (use (match_operand 3 "" "")) ;; loop level
1324 (use (match_operand 4 "" "")) ;; label
1325 (use (match_operand 5 "" ""))] ;; flag: 1 if loop entered at top, else 0
1334 /* only do inner loop */
1335 if (INTVAL (operands[3]) > 1)
1337 /* only deal with loop counters in SImode */
1338 if (GET_MODE (operands[0]) != SImode)
1343 emit_move_insn (s0, gen_rtx_PLUS (SImode, s0, GEN_INT (-1)));
1344 bcomp = gen_rtx_NE(SImode, s0, const0_rtx);
1345 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
1346 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
1347 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1357 ;; Prologue/epilogue
1359 (define_expand "prologue"
1363 tilepro_expand_prologue ();
1367 (define_expand "epilogue"
1371 tilepro_expand_epilogue (false);
1375 (define_expand "sibcall_epilogue"
1379 tilepro_expand_epilogue (true);
1384 ;; Stack manipulations
1387 ;; An insn to allocate new stack space for dynamic use (e.g., alloca).
1388 (define_expand "allocate_stack"
1389 [(set (match_operand 0 "register_operand" "")
1390 (minus (reg 54) (match_operand 1 "nonmemory_operand" "")))
1392 (minus (reg 54) (match_dup 1)))]
1394 "tilepro_allocate_stack (operands[0], operands[1]); DONE;")
1399 (define_expand "call"
1400 [(parallel [(call (match_operand:SI 0 "call_operand" "")
1401 (match_operand 1 "" ""))
1403 (clobber (reg:SI 55))])]
1407 (define_insn "*call_insn"
1408 [(call (mem:SI (match_operand:SI 0 "call_address_operand" "rO,i"))
1409 (match_operand 1 "" ""))
1411 (clobber (reg:SI 55))]
1416 [(set_attr "type" "X1,X1")])
1418 (define_expand "call_value"
1419 [(parallel [(set (match_operand 0 "register_operand" "")
1420 (call (match_operand:SI 1 "call_operand" "")
1421 (match_operand 2 "" "")))
1423 (clobber (reg:SI 55))])]
1426 (define_insn "*call_value_insn"
1427 [(set (match_operand 0 "register_operand" "=r,r")
1428 (call (mem:SI (match_operand:SI 1 "call_address_operand" "rO,i"))
1429 (match_operand 2 "" "")))
1431 (clobber (reg:SI 55))]
1436 [(set_attr "type" "X1,X1")])
1438 (define_expand "sibcall"
1439 [(parallel [(call (match_operand:SI 0 "call_operand" "")
1440 (match_operand 1 "" ""))
1441 (use (reg:SI 54))])]
1445 (define_insn "*sibcall_insn"
1446 [(call (mem:SI (match_operand:SI 0 "call_address_operand" "rO,i"))
1447 (match_operand 1 "" ""))
1449 "SIBLING_CALL_P(insn)"
1453 [(set_attr "type" "X1,X1")])
1455 (define_expand "sibcall_value"
1456 [(parallel [(set (match_operand 0 "" "")
1457 (call (match_operand:SI 1 "call_operand" "")
1458 (match_operand:SI 2 "" "")))
1459 (use (reg:SI 54))])]
1463 (define_insn "*sibcall_value"
1464 [(set (match_operand 0 "" "")
1465 (call (mem:SI (match_operand:SI 1 "call_address_operand" "rO,i"))
1466 (match_operand:SI 2 "" "")))
1468 "SIBLING_CALL_P(insn)"
1472 [(set_attr "type" "X1,X1")])
1475 [(set (pc) (label_ref (match_operand 0 "" "")))]
1478 [(set_attr "type" "X1")])
1480 (define_insn "indirect_jump"
1481 [(set (pc) (match_operand:SI 0 "register_operand" "rO"))]
1484 [(set_attr "type" "X1")])
1486 (define_expand "return"
1489 (use (reg:SI 55))])]
1490 "tilepro_can_use_return_insn_p ()"
1493 (define_insn "_return"
1498 [(set_attr "type" "X1")])
1500 (define_expand "tablejump"
1501 [(set (pc) (match_operand:SI 0 "register_operand" ""))
1502 (use (label_ref (match_operand 1 "" "")))]
1505 tilepro_expand_tablejump (operands[0], operands[1]);
1509 (define_insn "tablejump_aux"
1510 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1511 (use (label_ref (match_operand 1 "" "")))]
1514 [(set_attr "type" "X1")])
1516 ;; Call subroutine returning any type.
1517 (define_expand "untyped_call"
1518 [(parallel [(call (match_operand 0 "" "")
1520 (match_operand 1 "" "")
1521 (match_operand 2 "" "")])]
1526 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
1528 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1530 rtx set = XVECEXP (operands[2], 0, i);
1531 emit_move_insn (SET_DEST (set), SET_SRC (set));
1534 /* The optimizer does not know that the call sets the function value
1535 registers we stored in the result block. We avoid problems by
1536 claiming that all hard registers are used and clobbered at this
1538 emit_insn (gen_blockage ());
1543 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers
1544 ;; and all of memory. This blocks insns from being moved across this
1546 (define_insn "blockage"
1547 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
1550 [(set_attr "type" "nothing")
1551 (set_attr "length" "0")])
1553 ;; Internal expanders to prevent memory ops from moving around frame
1554 ;; allocation/deallocation.
1556 ;; TODO: really this clobber should just clobber the frame memory. Is
1557 ;; this possibly by clobbering memory @ the sp reg (as alpha does?)
1558 ;; or by explicitly setting the alias set to the frame?
1559 (define_insn "sp_adjust"
1560 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1562 (match_operand:SI 1 "register_operand" "%r,r,r")
1563 (match_operand:SI 2 "add_operand" "r,I,J")))
1564 (clobber (mem:BLK (scratch)))]
1570 [(set_attr "type" "*,*,X01")])
1572 ;; Used for move sp, r52, to pop a stack frame. We need to make sure
1573 ;; that stack frame memory operations have been issued before we do
1574 ;; this. TODO: see above TODO.
1575 (define_insn "sp_restore"
1576 [(set (match_operand:SI 0 "register_operand" "=r")
1577 (match_operand:SI 1 "register_operand" "r"))
1578 (clobber (mem:BLK (scratch)))]
1586 [(set_attr "type" "Y01")])
1590 ;; Conditional branches
1593 (define_expand "cbranchsi4"
1595 (if_then_else (match_operator 0 "ordered_comparison_operator"
1596 [(match_operand:SI 1 "reg_or_cint_operand")
1597 (match_operand:SI 2 "reg_or_cint_operand")])
1598 (label_ref (match_operand 3 ""))
1601 { tilepro_emit_conditional_branch (operands, SImode); DONE; })
1604 (define_expand "cbranchdi4"
1606 (if_then_else (match_operator 0 "ordered_comparison_operator"
1607 [(match_operand:DI 1 "reg_or_cint_operand")
1608 (match_operand:DI 2 "reg_or_cint_operand")])
1609 (label_ref (match_operand 3 ""))
1612 { tilepro_emit_conditional_branch (operands, DImode); DONE; })
1615 (define_insn "*bcc_normal"
1618 (match_operator 1 "signed_comparison_operator"
1619 [(match_operand:SI 2 "reg_or_0_operand" "rO")
1621 (label_ref (match_operand 0 "" ""))
1624 { return tilepro_output_cbranch (insn, operands, false); }
1625 [(set_attr "type" "X1_branch")])
1627 (define_insn "*bcc_reverse"
1630 (match_operator 1 "signed_comparison_operator"
1631 [(match_operand:SI 2 "reg_or_0_operand" "rO")
1634 (label_ref (match_operand 0 "" ""))))]
1636 { return tilepro_output_cbranch (insn, operands, true); }
1637 [(set_attr "type" "X1_branch")])
1639 ;; FIXME: the straight forward versions which do not include the
1640 ;; subreg:QI does not match for some unknown reason.
1641 (define_insn "*bbs_normal"
1644 (ne (zero_extract:SI (subreg:QI
1645 (match_operand:SI 1 "reg_or_0_operand" "rO") 0)
1649 (label_ref (match_operand 0 "" ""))
1652 { return tilepro_output_cbranch_with_opcode (insn, operands, "bbs", "bbns",
1654 [(set_attr "type" "X1_branch")])
1656 (define_insn "*bbc_normal"
1659 (eq (zero_extract:SI (subreg:QI
1660 (match_operand:SI 1 "reg_or_0_operand" "rO") 0)
1664 (label_ref (match_operand 0 "" ""))
1667 { return tilepro_output_cbranch_with_opcode (insn, operands, "bbns", "bbs",
1669 [(set_attr "type" "X1_branch")])
1671 ;; Note that __insn_mf() expands to this.
1672 (define_expand "memory_barrier"
1674 (unspec_volatile:BLK [(match_dup 0)] UNSPEC_MF))]
1677 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
1678 MEM_VOLATILE_P (operands[0]) = 1;
1681 (define_insn "*memory_barrier"
1682 [(set (match_operand:BLK 0 "" "")
1683 (unspec_volatile:BLK [(match_dup 0)] UNSPEC_MF))]
1686 [(set_attr "type" "X1")])
1688 (define_insn "prefetch"
1689 [(prefetch (match_operand:SI 0 "address_operand" "rO")
1690 (match_operand:SI 1 "const_int_operand" "")
1691 (match_operand:SI 2 "const_int_operand" ""))]
1694 [(set_attr "type" "Y2")])
1698 ;; Network intrinsics
1701 ;; Note the "pseudo" text is handled specially by the
1702 ;; asm_output_opcode routine. If the output is an empty string, the
1703 ;; instruction would bypass the asm_output_opcode routine, bypassing
1704 ;; the bundle handling code.
1705 (define_insn "tilepro_network_barrier"
1706 [(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)]
1709 [(set_attr "type" "nothing")
1710 (set_attr "length" "0")])
1712 (define_insn "*netreg_receive"
1713 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,U,m")
1714 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i,i,i")
1715 (reg:SI TILEPRO_NETORDER_REG)]
1716 UNSPEC_NETWORK_RECEIVE))
1717 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1722 swadd\t%I0, %N1, %i0"
1723 [(set_attr "type" "*,Y2,X1")])
1725 (define_insn "*netreg_send"
1726 [(unspec_volatile:SI
1727 [(match_operand:SI 0 "netreg_operand" "i,i,i,i,i,i")
1728 (match_operand:SI 1 "reg_or_cint_operand" "rO,I,J,K,N,P")
1729 (reg:SI TILEPRO_NETORDER_REG)]
1730 UNSPEC_NETWORK_SEND)
1731 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1737 auli\t%N0, zero, %h1
1738 addib\t%N0, zero, %j1
1739 addih\t%N0, zero, %h1"
1740 [(set_attr "type" "*,*,X01,X01,X01,X01")])
1742 (define_insn "*netreg_copy"
1743 [(unspec_volatile:SI
1744 [(match_operand:SI 0 "netreg_operand" "i")
1745 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i")
1746 (reg:SI TILEPRO_NETORDER_REG)]
1747 UNSPEC_NETWORK_RECEIVE)
1748 (reg:SI TILEPRO_NETORDER_REG)]
1749 UNSPEC_NETWORK_SEND)
1750 (clobber (reg:SI TILEPRO_NETORDER_REG))
1751 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1755 (define_expand "tilepro_idn0_receive"
1757 [(set (match_operand:SI 0 "register_operand" "")
1758 (unspec_volatile:SI [(const_int TILEPRO_NETREG_IDN0)
1759 (reg:SI TILEPRO_NETORDER_REG)]
1760 UNSPEC_NETWORK_RECEIVE))
1761 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1764 (define_expand "tilepro_idn1_receive"
1766 [(set (match_operand:SI 0 "register_operand" "")
1767 (unspec_volatile:SI [(const_int TILEPRO_NETREG_IDN1)
1768 (reg:SI TILEPRO_NETORDER_REG)]
1769 UNSPEC_NETWORK_RECEIVE))
1770 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1773 (define_expand "tilepro_idn_send"
1775 [(unspec_volatile:SI [(const_int TILEPRO_NETREG_IDN0)
1776 (match_operand:SI 0 "reg_or_cint_operand" "")
1777 (reg:SI TILEPRO_NETORDER_REG)]
1778 UNSPEC_NETWORK_SEND)
1779 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1782 (define_expand "tilepro_sn_receive"
1784 [(set (match_operand:SI 0 "register_operand" "")
1785 (unspec_volatile:SI [(const_int TILEPRO_NETREG_SN)
1786 (reg:SI TILEPRO_NETORDER_REG)]
1787 UNSPEC_NETWORK_RECEIVE))
1788 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1791 (define_expand "tilepro_sn_send"
1793 [(unspec_volatile:SI [(const_int TILEPRO_NETREG_SN)
1794 (match_operand:SI 0 "reg_or_cint_operand" "")
1795 (reg:SI TILEPRO_NETORDER_REG)]
1796 UNSPEC_NETWORK_SEND)
1797 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1800 (define_expand "tilepro_udn0_receive"
1802 [(set (match_operand:SI 0 "register_operand" "")
1803 (unspec_volatile:SI [(const_int TILEPRO_NETREG_UDN0)
1804 (reg:SI TILEPRO_NETORDER_REG)]
1805 UNSPEC_NETWORK_RECEIVE))
1806 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1809 (define_expand "tilepro_udn1_receive"
1811 [(set (match_operand:SI 0 "register_operand" "")
1812 (unspec_volatile:SI [(const_int TILEPRO_NETREG_UDN1)
1813 (reg:SI TILEPRO_NETORDER_REG)]
1814 UNSPEC_NETWORK_RECEIVE))
1815 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1818 (define_expand "tilepro_udn2_receive"
1820 [(set (match_operand:SI 0 "register_operand" "")
1821 (unspec_volatile:SI [(const_int TILEPRO_NETREG_UDN2)
1822 (reg:SI TILEPRO_NETORDER_REG)]
1823 UNSPEC_NETWORK_RECEIVE))
1824 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1827 (define_expand "tilepro_udn3_receive"
1829 [(set (match_operand:SI 0 "register_operand" "")
1830 (unspec_volatile:SI [(const_int TILEPRO_NETREG_UDN3)
1831 (reg:SI TILEPRO_NETORDER_REG)]
1832 UNSPEC_NETWORK_RECEIVE))
1833 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1836 (define_expand "tilepro_udn_send"
1838 [(unspec_volatile:SI [(const_int TILEPRO_NETREG_UDN0)
1839 (match_operand:SI 0 "reg_or_cint_operand" "")
1840 (reg:SI TILEPRO_NETORDER_REG)]
1841 UNSPEC_NETWORK_SEND)
1842 (clobber (reg:SI TILEPRO_NETORDER_REG))])]
1845 (define_insn "*netreg_add_to_network"
1846 [(unspec_volatile:SI
1847 [(match_operand:SI 0 "netreg_operand" "i,i,i,i")
1848 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO,rO,rO")
1849 (match_operand:SI 2 "add_operand" "r,I,J,K"))
1850 (reg:SI TILEPRO_NETORDER_REG)]
1851 UNSPEC_NETWORK_SEND)
1852 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1858 auli\t%N0, %r1, %h2"
1859 [(set_attr "type" "*,*,X01,X01")])
1861 (define_insn "*netreg_add_from_network"
1862 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1864 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i,i,i,i")
1865 (reg:SI TILEPRO_NETORDER_REG)]
1866 UNSPEC_NETWORK_RECEIVE)
1867 (match_operand:SI 2 "add_operand" "rO,I,J,K")))
1868 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1875 [(set_attr "type" "*,*,X01,X01")])
1877 (define_insn "*netreg_add_from_to_network"
1878 [(unspec_volatile:SI
1879 [(match_operand:SI 0 "netreg_operand" "i,i,i,i")
1881 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i,i,i,i")
1882 (reg:SI TILEPRO_NETORDER_REG)]
1883 UNSPEC_NETWORK_RECEIVE)
1884 (match_operand:SI 2 "add_operand" "rO,I,J,K"))
1885 (reg:SI TILEPRO_NETORDER_REG)]
1886 UNSPEC_NETWORK_SEND)
1887 (clobber (reg:SI TILEPRO_NETORDER_REG))
1888 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1894 auli\t%N0, %N1, %h2"
1895 [(set_attr "type" "*,*,X01,X01")])
1897 (define_code_iterator netreg_binop
1900 (define_insn "*netreg_binop_to_network"
1901 [(unspec_volatile:SI
1902 [(match_operand:SI 0 "netreg_operand" "i")
1903 (netreg_binop:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1904 (match_operand:SI 2 "reg_or_0_operand" "rO"))
1905 (reg:SI TILEPRO_NETORDER_REG)]
1906 UNSPEC_NETWORK_SEND)
1907 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1909 "<insn>\t%N0, %r1, %r2")
1911 (define_insn "*netreg_binop_from_network0"
1912 [(set (match_operand:SI 0 "register_operand" "=r")
1914 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i")
1915 (reg:SI TILEPRO_NETORDER_REG)]
1916 UNSPEC_NETWORK_RECEIVE)
1917 (match_operand:SI 2 "reg_or_0_operand" "rO")))
1918 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1920 "<insn>\t%0, %N1, %r2")
1922 (define_insn "*netreg_binop_from_network1"
1923 [(set (match_operand:SI 0 "register_operand" "=r")
1925 (match_operand:SI 1 "reg_or_0_operand" "rO")
1926 (unspec_volatile:SI [(match_operand:SI 2 "netreg_operand" "i")
1927 (reg:SI TILEPRO_NETORDER_REG)]
1928 UNSPEC_NETWORK_RECEIVE)))
1929 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1931 "<insn>\t%0, %r1, %N2")
1933 (define_insn "*netreg_binop_from_to_network0"
1934 [(unspec_volatile:SI
1935 [(match_operand:SI 0 "netreg_operand" "i")
1937 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i")
1938 (reg:SI TILEPRO_NETORDER_REG)]
1939 UNSPEC_NETWORK_RECEIVE)
1940 (match_operand:SI 2 "reg_or_0_operand" "rO"))
1941 (reg:SI TILEPRO_NETORDER_REG)]
1942 UNSPEC_NETWORK_SEND)
1943 (clobber (reg:SI TILEPRO_NETORDER_REG))
1944 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1946 "<insn>\t%N0, %N1, %r2")
1948 (define_insn "*netreg_binop_from_to_network1"
1949 [(unspec_volatile:SI
1950 [(match_operand:SI 0 "netreg_operand" "i")
1952 (match_operand:SI 1 "reg_or_0_operand" "rO")
1953 (unspec_volatile:SI [(match_operand:SI 2 "netreg_operand" "i")
1954 (reg:SI TILEPRO_NETORDER_REG)]
1955 UNSPEC_NETWORK_RECEIVE))
1956 (reg:SI TILEPRO_NETORDER_REG)]
1957 UNSPEC_NETWORK_SEND)
1958 (clobber (reg:SI TILEPRO_NETORDER_REG))
1959 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1961 "<insn>\t%N0, %r1, %N2")
1963 (define_insn "*netreg_binop_to_network"
1964 [(unspec_volatile:SI
1965 [(match_operand:SI 0 "netreg_operand" "i,i")
1966 (binop_with_imm:SI (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1967 (match_operand:SI 2 "reg_or_cint_operand" "I,rO"))
1968 (reg:SI TILEPRO_NETORDER_REG)]
1969 UNSPEC_NETWORK_SEND)
1970 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1973 <insn>i<u>\t%N0, %r1, %2
1974 <insn><u>\t%N0, %r1, %r2")
1976 (define_insn "*netreg_binop_from_network"
1977 [(set (match_operand:SI 0 "register_operand" "=r,r")
1979 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i,i")
1980 (reg:SI TILEPRO_NETORDER_REG)]
1981 UNSPEC_NETWORK_RECEIVE)
1982 (match_operand:SI 2 "reg_or_cint_operand" "I,rO")))
1983 (clobber (reg:SI TILEPRO_NETORDER_REG))]
1986 <insn>i<u>\t%0, %N1, %2
1987 <insn><u>\t%0, %N1, %r2")
1989 (define_insn "*netreg_binop_from_to_network"
1990 [(unspec_volatile:SI
1991 [(match_operand:SI 0 "netreg_operand" "i,i")
1993 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i,i")
1994 (reg:SI TILEPRO_NETORDER_REG)]
1995 UNSPEC_NETWORK_RECEIVE)
1996 (match_operand:SI 2 "reg_or_cint_operand" "I,rO"))
1997 (reg:SI TILEPRO_NETORDER_REG)]
1998 UNSPEC_NETWORK_SEND)
1999 (clobber (reg:SI TILEPRO_NETORDER_REG))
2000 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2003 <insn>i<u>\t%N0, %N1, %2
2004 <insn><u>\t%N0, %N1, %r2")
2006 (define_insn "*netreg_unop_to_network"
2007 [(unspec_volatile:SI [(match_operand:SI 0 "netreg_operand" "i")
2008 (unop:SI (match_operand:SI 1 "reg_or_0_operand" "rO"))
2009 (reg:SI TILEPRO_NETORDER_REG)]
2010 UNSPEC_NETWORK_SEND)
2011 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2014 [(set_attr "type" "Y0")])
2016 (define_insn "*netreg_unop_from_network"
2017 [(set (match_operand:SI 0 "register_operand" "=r")
2019 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i")
2020 (reg:SI TILEPRO_NETORDER_REG)]
2021 UNSPEC_NETWORK_RECEIVE)))
2022 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2025 [(set_attr "type" "Y0")])
2027 (define_insn "*netreg_unop_from_to_network"
2028 [(unspec_volatile:SI
2029 [(match_operand:SI 0 "netreg_operand" "i")
2031 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i")
2032 (reg:SI TILEPRO_NETORDER_REG)]
2033 UNSPEC_NETWORK_RECEIVE))
2034 (reg:SI TILEPRO_NETORDER_REG)]
2035 UNSPEC_NETWORK_SEND)
2036 (clobber (reg:SI TILEPRO_NETORDER_REG))
2037 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2040 [(set_attr "type" "Y0")])
2042 (define_insn "*netreg_sadh_u_from_network0"
2043 [(set (match_operand:SI 0 "register_operand" "=r")
2045 [(unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i")
2046 (reg:SI TILEPRO_NETORDER_REG)]
2047 UNSPEC_NETWORK_RECEIVE)
2048 (match_operand:SI 2 "reg_or_0_operand" "rO")]
2049 UNSPEC_INSN_SADH_U))
2050 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2052 "sadh_u\t%0, %N1, %r2"
2053 [(set_attr "type" "X0_2cycle")])
2055 (define_insn "*netreg_sadh_u_from_network1"
2056 [(set (match_operand:SI 0 "register_operand" "=r")
2058 [(match_operand:SI 1 "reg_or_0_operand" "rO")
2059 (unspec_volatile:SI [(match_operand:SI 2 "netreg_operand" "i")
2060 (reg:SI TILEPRO_NETORDER_REG)]
2061 UNSPEC_NETWORK_RECEIVE)]
2062 UNSPEC_INSN_SADH_U))
2063 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2065 "sadh_u\t%0, %r1, %N2"
2066 [(set_attr "type" "X0_2cycle")])
2068 (define_insn "*netreg_sadah_u_from_network0"
2069 [(set (match_operand:SI 0 "register_operand" "=r")
2071 [(match_operand:SI 1 "reg_or_0_operand" "0")
2072 (unspec_volatile:SI [(match_operand:SI 2 "netreg_operand" "i")
2073 (reg:SI TILEPRO_NETORDER_REG)]
2074 UNSPEC_NETWORK_RECEIVE)
2075 (match_operand:SI 3 "reg_or_0_operand" "rO")]
2076 UNSPEC_INSN_SADAH_U))
2077 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2079 "sadah_u\t%0, %N2, %r3"
2080 [(set_attr "type" "X0_2cycle")])
2082 (define_insn "*netreg_sadah_u_from_network1"
2083 [(set (match_operand:SI 0 "register_operand" "=r")
2085 [(match_operand:SI 1 "reg_or_0_operand" "0")
2086 (match_operand:SI 2 "reg_or_0_operand" "rO")
2087 (unspec_volatile:SI [(match_operand:SI 3 "netreg_operand" "i")
2088 (reg:SI TILEPRO_NETORDER_REG)]
2089 UNSPEC_NETWORK_RECEIVE)]
2090 UNSPEC_INSN_SADAH_U))
2091 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2093 "sadah_u\t%0, %r2, %N3"
2094 [(set_attr "type" "X0_2cycle")])
2096 (define_code_iterator mm_combiner [ior xor plus])
2098 ;; This doesn't seem to match -- too complex for 'combine'?
2100 ;; (define_insn "*netreg_mm_to_network"
2101 ;; [(unspec_volatile:SI
2102 ;; [(match_operand:SI 0 "netreg_operand" "i")
2104 ;; (and:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
2105 ;; (match_operand:SI 3 "const_int_operand" "n"))
2106 ;; (and:SI (match_operand:SI 2 "reg_or_0_operand" "rO")
2107 ;; (match_operand:SI 4 "const_int_operand" "n")))]
2108 ;; UNSPEC_NETWORK_SEND)]
2109 ;; "tilepro_bitfield_operand_p (INTVAL (operands[3]), NULL, NULL)
2110 ;; && INTVAL (operands[3]) == ~INTVAL (operands[4])"
2111 ;; "mm\t%N0, %r1, %r2, %M3"
2112 ;; [(set_attr "type" "X01")])
2114 ;; FIXME: the straight forward versions which do not include the
2115 ;; subreg:QI does not match for some unknown reason.
2116 (define_insn "*netreg_bbs_normal"
2119 (ne (zero_extract:SI
2121 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i")
2122 (reg:SI TILEPRO_NETORDER_REG)]
2123 UNSPEC_NETWORK_RECEIVE) 0)
2127 (label_ref (match_operand 0 "" ""))
2129 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2131 { return tilepro_output_cbranch_with_opcode (insn, operands, "bbs", "bbns",
2133 [(set_attr "type" "X1_branch")])
2135 (define_insn "*netreg_bbc_normal"
2138 (eq (zero_extract:SI
2140 (unspec_volatile:SI [(match_operand:SI 1 "netreg_operand" "i")
2141 (reg:SI TILEPRO_NETORDER_REG)]
2142 UNSPEC_NETWORK_RECEIVE) 0)
2146 (label_ref (match_operand 0 "" ""))
2148 (clobber (reg:SI TILEPRO_NETORDER_REG))]
2150 { return tilepro_output_cbranch_with_opcode (insn, operands, "bbns", "bbns",
2152 [(set_attr "type" "X1_branch")])
2156 ;; "__insn" Intrinsics (some expand directly to normal patterns above).
2159 (define_insn "insn_addlis"
2160 [(set (match_operand:SI 0 "register_operand" "=r")
2161 (unspec_volatile:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
2162 (match_operand:SI 2 "s16bit_cint_operand" "i")]
2163 UNSPEC_INSN_ADDLIS))]
2165 "addlis\t%0, %r1, %2"
2166 [(set_attr "type" "X01")])
2168 (define_insn "insn_auli"
2169 [(set (match_operand:SI 0 "register_operand" "=r")
2170 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
2171 (match_operand:SI 2 "s16bit_cint_operand" "i")]
2175 [(set_attr "type" "X01")])
2177 (define_insn "insn_drain"
2178 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_DRAIN)]
2181 [(set_attr "type" "cannot_bundle")])
2183 (define_insn "insn_icoh"
2184 [(unspec_volatile:VOID [(match_operand:SI 0 "reg_or_0_operand" "rO")]
2188 [(set_attr "type" "X1")])
2191 (define_insn "insn_info"
2192 [(unspec_volatile:VOID [(match_operand:SI 0 "s8bit_cint_operand" "i")]
2197 (define_insn "insn_infol"
2198 [(unspec_volatile:VOID [(match_operand:SI 0 "s16bit_cint_operand" "i")]
2202 [(set_attr "type" "X01")])
2206 (define_expand "insn_<load>"
2207 [(set (match_operand:SI 0 "register_operand" "")
2209 (mem:I12MODE (match_operand:SI 1 "address_operand" ""))))]
2212 (define_expand "insn_<load>_u"
2213 [(set (match_operand:SI 0 "register_operand" "")
2215 (mem:I12MODE (match_operand:SI 1 "address_operand" ""))))]
2218 (define_insn "insn_<load>add"
2219 [(set (match_operand:SI 1 "register_operand" "=r")
2220 (plus:SI (match_operand:SI 3 "register_operand" "1")
2221 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2222 (set (match_operand:SI 0 "register_operand" "=r")
2223 (sign_extend:SI (mem:I12MODE (match_dup 3))))]
2225 "<load>add\t%0, %1, %2"
2226 [(set_attr "type" "X1_2cycle")])
2228 (define_insn "insn_<load>add_u"
2229 [(set (match_operand:SI 1 "register_operand" "=r")
2230 (plus:SI (match_operand:SI 3 "register_operand" "1")
2231 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2232 (set (match_operand:SI 0 "register_operand" "=r")
2233 (zero_extend:SI (mem:I12MODE (match_dup 3))))]
2235 "<load>add_u\t%0, %1, %2"
2236 [(set_attr "type" "X1_2cycle")])
2238 (define_expand "insn_lw"
2239 [(set (match_operand:SI 0 "register_operand" "")
2240 (mem:SI (match_operand:SI 1 "address_operand" "")))]
2243 (define_insn "insn_lwadd"
2244 [(set (match_operand:SI 1 "register_operand" "=r")
2245 (plus:SI (match_operand:SI 3 "register_operand" "1")
2246 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2247 (set (match_operand:SI 0 "register_operand" "=r")
2248 (mem:SI (match_dup 3)))]
2251 [(set_attr "type" "X1_2cycle")])
2253 (define_insn "insn_lwadd_na"
2254 [(set (match_operand:SI 1 "register_operand" "=r")
2255 (plus:SI (match_operand:SI 3 "register_operand" "1")
2256 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2257 (set (match_operand:SI 0 "register_operand" "=r")
2258 (mem:SI (and:SI (match_dup 3) (const_int -4))))]
2260 "lwadd_na\t%0, %1, %2"
2261 [(set_attr "type" "X1_2cycle")])
2263 (define_insn "insn_lw_na"
2264 [(set (match_operand:SI 0 "register_operand" "=r")
2265 (mem:SI (and:SI (match_operand:SI 1 "address_operand" "rO")
2269 [(set_attr "type" "X1_2cycle")])
2273 (define_insn "insn_<load>_L2"
2274 [(set (match_operand:SI 0 "register_operand" "=r")
2277 [(mem:I12MODE (match_operand:SI 1 "address_operand" "rO"))]
2278 UNSPEC_LATENCY_L2)))]
2281 [(set_attr "type" "Y2_L2")])
2283 (define_insn "insn_<load>_u_L2"
2284 [(set (match_operand:SI 0 "register_operand" "=r")
2287 [(mem:I12MODE (match_operand:SI 1 "address_operand" "rO"))]
2288 UNSPEC_LATENCY_L2)))]
2291 [(set_attr "type" "Y2_L2")])
2293 (define_insn "insn_<load>add_L2"
2294 [(set (match_operand:SI 1 "register_operand" "=r")
2295 (plus:SI (match_operand:SI 3 "register_operand" "1")
2296 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2297 (set (match_operand:SI 0 "register_operand" "=r")
2298 (sign_extend:SI (unspec:I12MODE [(mem:I12MODE (match_dup 3))]
2299 UNSPEC_LATENCY_L2)))]
2301 "<load>add\t%0, %1, %2"
2302 [(set_attr "type" "X1_L2")])
2304 (define_insn "insn_<load>add_u_L2"
2305 [(set (match_operand:SI 1 "register_operand" "=r")
2306 (plus:SI (match_operand:SI 3 "register_operand" "1")
2307 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2308 (set (match_operand:SI 0 "register_operand" "=r")
2309 (zero_extend:SI (unspec:I12MODE [(mem:I12MODE (match_dup 3))]
2310 UNSPEC_LATENCY_L2)))]
2312 "<load>add_u\t%0, %1, %2"
2313 [(set_attr "type" "X1_L2")])
2315 (define_insn "insn_lwadd_L2"
2316 [(set (match_operand:SI 1 "register_operand" "=r")
2317 (plus:SI (match_operand:SI 3 "register_operand" "1")
2318 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2319 (set (match_operand:SI 0 "register_operand" "=r")
2320 (unspec:SI [(mem:SI (match_dup 3))] UNSPEC_LATENCY_L2))]
2323 [(set_attr "type" "X1_L2")])
2325 (define_insn "insn_lwadd_na_L2"
2326 [(set (match_operand:SI 1 "register_operand" "=r")
2327 (plus:SI (match_operand:SI 3 "register_operand" "1")
2328 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2329 (set (match_operand:SI 0 "register_operand" "=r")
2330 (unspec:SI [(mem:SI (and:SI (match_dup 3) (const_int -4)))]
2331 UNSPEC_LATENCY_L2))]
2333 "lwadd_na\t%0, %1, %2"
2334 [(set_attr "type" "X1_L2")])
2336 (define_insn "insn_lw_na_L2"
2337 [(set (match_operand:SI 0 "register_operand" "=r")
2338 (unspec:SI [(mem:SI (and:SI (match_operand:SI 1 "address_operand" "rO")
2340 UNSPEC_LATENCY_L2))]
2343 [(set_attr "type" "X1_L2")])
2345 (define_insn "insn_lw_L2"
2346 [(set (match_operand:SI 0 "register_operand" "=r")
2347 (unspec:SI [(mem:SI (match_operand:SI 1 "address_operand" "rO"))]
2348 UNSPEC_LATENCY_L2))]
2351 [(set_attr "type" "Y2_L2")])
2355 (define_insn "insn_<load>_miss"
2356 [(set (match_operand:SI 0 "register_operand" "=r")
2359 [(mem:I12MODE (match_operand:SI 1 "address_operand" "rO"))]
2360 UNSPEC_LATENCY_MISS)))]
2363 [(set_attr "type" "Y2_miss")])
2365 (define_insn "insn_<load>_u_miss"
2366 [(set (match_operand:SI 0 "register_operand" "=r")
2369 [(mem:I12MODE (match_operand:SI 1 "address_operand" "rO"))]
2370 UNSPEC_LATENCY_MISS)))]
2373 [(set_attr "type" "Y2_miss")])
2375 (define_insn "insn_<load>add_miss"
2376 [(set (match_operand:SI 1 "register_operand" "=r")
2377 (plus:SI (match_operand:SI 3 "register_operand" "1")
2378 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2379 (set (match_operand:SI 0 "register_operand" "=r")
2380 (sign_extend:SI (unspec:I12MODE [(mem:I12MODE (match_dup 3))]
2381 UNSPEC_LATENCY_MISS)))]
2383 "<load>add\t%0, %1, %2"
2384 [(set_attr "type" "X1_miss")])
2386 (define_insn "insn_<load>add_u_miss"
2387 [(set (match_operand:SI 1 "register_operand" "=r")
2388 (plus:SI (match_operand:SI 3 "register_operand" "1")
2389 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2390 (set (match_operand:SI 0 "register_operand" "=r")
2391 (zero_extend:SI (unspec:I12MODE [(mem:I12MODE (match_dup 3))]
2392 UNSPEC_LATENCY_MISS)))]
2394 "<load>add_u\t%0, %1, %2"
2395 [(set_attr "type" "X1_miss")])
2397 (define_insn "insn_lwadd_miss"
2398 [(set (match_operand:SI 1 "register_operand" "=r")
2399 (plus:SI (match_operand:SI 3 "register_operand" "1")
2400 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2401 (set (match_operand:SI 0 "register_operand" "=r")
2402 (unspec:SI [(mem:SI (match_dup 3))] UNSPEC_LATENCY_MISS))]
2405 [(set_attr "type" "X1_miss")])
2407 (define_insn "insn_lwadd_na_miss"
2408 [(set (match_operand:SI 1 "register_operand" "=r")
2409 (plus:SI (match_operand:SI 3 "register_operand" "1")
2410 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2411 (set (match_operand:SI 0 "register_operand" "=r")
2412 (unspec:SI [(mem:SI (and:SI (match_dup 3) (const_int -4)))]
2413 UNSPEC_LATENCY_MISS))]
2415 "lwadd_na\t%0, %1, %2"
2416 [(set_attr "type" "X1_miss")])
2418 (define_insn "insn_lw_na_miss"
2419 [(set (match_operand:SI 0 "register_operand" "=r")
2420 (unspec:SI [(mem:SI (and:SI (match_operand:SI 1 "address_operand" "rO")
2422 UNSPEC_LATENCY_MISS))]
2425 [(set_attr "type" "X1_miss")])
2427 (define_insn "insn_lw_miss"
2428 [(set (match_operand:SI 0 "register_operand" "=r")
2429 (unspec:SI [(mem:SI (match_operand:SI 1 "address_operand" "rO"))]
2430 UNSPEC_LATENCY_MISS))]
2433 [(set_attr "type" "Y2_miss")])
2437 (define_insn "insn_mfspr"
2438 [(set (match_operand:SI 0 "register_operand" "=r")
2439 (unspec_volatile:SI [(match_operand:SI 1 "u15bit_cint_operand" "i")]
2441 (clobber (mem:BLK (const_int 0)))]
2444 [(set_attr "type" "X1")])
2447 [(set (match_operand:SI 0 "register_operand" "=r")
2449 (and:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
2450 (match_operand:SI 3 "const_int_operand" "n"))
2451 (and:SI (match_operand:SI 2 "reg_or_0_operand" "rO")
2452 (match_operand:SI 4 "const_int_operand" "n"))))]
2453 "tilepro_bitfield_operand_p (INTVAL (operands[3]), NULL, NULL)
2454 && INTVAL (operands[3]) == ~INTVAL (operands[4])"
2455 "mm\t%0, %r1, %r2, %M3"
2456 [(set_attr "type" "X01")])
2458 (define_expand "insn_mm"
2459 [(set (match_operand:SI 0 "register_operand" "")
2461 (and:SI (match_operand:SI 1 "reg_or_cint_operand" "")
2462 (match_operand:SI 3 "u5bit_cint_operand" ""))
2463 (and:SI (match_operand:SI 2 "reg_or_cint_operand" "")
2464 (match_operand:SI 4 "u5bit_cint_operand" ""))))]
2470 first = INTVAL (operands[3]) & 31;
2471 last = INTVAL (operands[4]) & 31;
2473 if (((last + 1) & 31) == first)
2475 /* Handle pathological case of a mask that includes only the
2476 first operand. The reordering code below can't handle this. */
2477 emit_move_insn (operands[0], operands[1]);
2481 /* Canonicalize order by putting constant second, if any. */
2482 if (CONST_INT_P (operands[1]))
2486 rtx tmp = operands[1];
2487 operands[1] = operands[2];
2490 /* Invert the bit range. */
2492 first = (last + 1) & 31;
2493 last = (tmp_first - 1) & 31;
2496 /* Convert the first/last bit range into a bit mask. */
2499 for (i = first; ; i = (i + 1) & 31)
2501 mask |= ((HOST_WIDE_INT)1) << i;
2506 mask = trunc_int_for_mode (mask, SImode);
2508 operands[1] = force_reg (SImode, operands[1]);
2509 operands[3] = GEN_INT (mask);
2510 operands[4] = GEN_INT (~mask);
2512 if (CONST_INT_P (operands[2]))
2514 HOST_WIDE_INT inserted_bits = INTVAL (operands[2]) & ~mask;
2516 if (inserted_bits == 0)
2518 /* All inserted bits are zero. Use a bitwise AND. */
2519 emit_insn (gen_andsi3 (operands[0], operands[1], operands[3]));
2522 else if (inserted_bits == ~mask)
2524 /* All inserted bits are ones. Use a bitwise IOR if we can. */
2525 if (satisfies_constraint_I (operands[4]))
2527 emit_insn (gen_iorsi3 (operands[0], operands[1], operands[4]));
2531 /* Canonicalize to inserting -1 when setting all masked bits
2532 to 1, to facilitate CSE. */
2536 /* Sign extend the inserted bits to make them easier to materialize
2537 in a register, but only if the inserted bits (~mask) do not already
2538 include the high bits. */
2539 if ((~mask & 0x80000000) == 0)
2541 int shift = sizeof (HOST_WIDE_INT) * 8 - first;
2542 inserted_bits = (inserted_bits << shift) >> shift;
2545 operands[2] = GEN_INT (inserted_bits);
2548 operands[2] = force_reg (SImode, operands[2]);
2551 (define_insn "insn_movelis"
2552 [(set (match_operand:SI 0 "register_operand" "=r")
2553 (unspec_volatile:SI [(match_operand:SI 1 "s16bit_cint_operand" "i")]
2554 UNSPEC_INSN_MOVELIS))]
2557 [(set_attr "type" "X01")])
2559 (define_insn "insn_mtspr"
2560 [(unspec_volatile:SI [(match_operand:SI 0 "u15bit_cint_operand" "i")
2561 (match_operand:SI 1 "reg_or_0_operand" "rO")]
2563 (clobber (mem:BLK (const_int 0)))]
2566 [(set_attr "type" "X1")])
2568 (define_expand "insn_prefetch"
2569 [(prefetch (match_operand:SI 0 "address_operand" "")
2573 (define_expand "insn_prefetch_L1"
2574 [(use (match_operand:SI 0 "address_operand" ""))]
2577 /* Generate a volatile byte load to a dummy register. */
2578 rtx mem = gen_rtx_MEM (QImode, operands[0]);
2579 MEM_VOLATILE_P (mem) = 1;
2581 emit_insn (gen_zero_extendqisi2 (gen_reg_rtx (SImode), mem));
2585 (define_expand "insn_s1a"
2586 [(set (match_operand:SI 0 "register_operand" "")
2587 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
2589 (match_operand:SI 2 "reg_or_0_operand" "")))]
2592 (define_expand "insn_s2a"
2593 [(set (match_operand:SI 0 "register_operand" "")
2594 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
2596 (match_operand:SI 2 "reg_or_0_operand" "")))]
2599 (define_expand "insn_s3a"
2600 [(set (match_operand:SI 0 "register_operand" "")
2601 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
2603 (match_operand:SI 2 "reg_or_0_operand" "")))]
2606 (define_expand "insn_<store>"
2607 [(set (mem:I12MODE (match_operand:SI 0 "address_operand" ""))
2608 (match_operand:SI 1 "reg_or_0_operand" ""))]
2611 operands[1] = simplify_gen_subreg (<MODE>mode, operands[1], SImode, 0);
2614 (define_expand "insn_sw"
2615 [(set (mem:SI (match_operand:SI 0 "address_operand" ""))
2616 (match_operand:SI 1 "reg_or_0_operand" ""))]
2619 (define_expand "insn_<store>add"
2621 [(set (match_operand:SI 0 "register_operand" "")
2622 (plus:SI (match_operand:SI 3 "register_operand" "")
2623 (match_operand:SI 2 "s8bit_cint_operand" "")))
2624 (set (mem:I12MODE (match_dup 3))
2625 (match_operand:SI 1 "reg_or_0_operand" ""))])]
2628 operands[1] = simplify_gen_subreg (<MODE>mode, operands[1], SImode, 0);
2631 (define_insn "*insn_<store>add"
2632 [(set (match_operand:SI 0 "register_operand" "=r")
2633 (plus:SI (match_operand:SI 3 "register_operand" "0")
2634 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2635 (set (mem:I12MODE (match_dup 3))
2636 (match_operand:I12MODE 1 "reg_or_0_operand" "rO"))]
2638 "<store>add\t%0, %r1, %2"
2639 [(set_attr "type" "X1")])
2641 (define_insn "insn_swadd"
2642 [(set (match_operand:SI 0 "register_operand" "=r")
2643 (plus:SI (match_operand:SI 3 "register_operand" "0")
2644 (match_operand:SI 2 "s8bit_cint_operand" "i")))
2645 (set (mem:SI (match_dup 3))
2646 (match_operand:SI 1 "reg_or_0_operand" "rO"))]
2648 "swadd\t%0, %r1, %2"
2649 [(set_attr "type" "X1")])
2651 (define_insn "insn_wh64"
2652 [(unspec_volatile:VOID [(match_operand:SI 0 "reg_or_0_operand" "rO")]
2654 (clobber (mem:BLK (const_int 0)))]
2657 [(set_attr "type" "X1")])
2659 (define_insn "insn_tns"
2660 [(set (match_operand:SI 0 "register_operand" "=r")
2661 (mem:SI (match_operand:SI 1 "reg_or_0_operand" "rO")))
2662 (set (mem:SI (match_dup 1)) (const_int 1))]
2665 [(set_attr "type" "X1")])
2679 (define_insn "<optab>v4qi3"
2680 [(set (match_operand:V4QI 0 "register_operand" "=r,r")
2682 (match_operand:V4QI 1 "reg_or_0_operand" "<comm>rO,rO")
2683 (match_operand:V4QI 2 "reg_or_v4s8bit_operand" "W,rO")))]
2686 <insn>ib<u>\t%0, %r1, %j2
2687 <insn>b<u>\t%0, %r1, %r2"
2688 [(set_attr "type" "X01,X01")])
2690 (define_expand "insn_<insn>b<u>"
2691 [(set (match_operand:SI 0 "register_operand" "")
2693 (match_operand:SI 1 "reg_or_0_operand" "")
2694 (match_operand:SI 2 "reg_or_0_operand" "")))]
2697 tilepro_expand_builtin_vector_binop (gen_<optab>v4qi3, V4QImode, operands[0],
2698 V4QImode, operands[1], operands[2], true);
2702 (define_expand "insn_<insn>ib<u>"
2703 [(set (match_operand:SI 0 "register_operand" "")
2705 (match_operand:SI 1 "reg_or_0_operand" "")
2706 (match_operand:SI 2 "s8bit_cint_operand" "")))]
2709 /* Tile out immediate and expand to general case. */
2710 rtx n = tilepro_simd_int (operands[2], QImode);
2711 tilepro_expand_builtin_vector_binop (gen_<optab>v4qi3, V4QImode, operands[0],
2712 V4QImode, operands[1], n, true);
2722 (define_insn "<optab>v4qi3"
2723 [(set (match_operand:V4QI 0 "register_operand" "=r,r")
2725 (match_operand:V4QI 1 "reg_or_0_operand" "rO,rO")
2726 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO")))]
2729 <insn>ib<u>\t%0, %r1, %2
2730 <insn>b<u>\t%0, %r1, %r2"
2731 [(set_attr "type" "X01,X01")])
2733 (define_expand "insn_<insn>b<u>"
2734 [(set (match_operand:SI 0 "register_operand" "")
2736 (match_operand:SI 1 "reg_or_0_operand" "")
2737 (match_operand:SI 2 "reg_or_u5bit_operand" "")))]
2740 tilepro_expand_builtin_vector_binop (gen_<optab>v4qi3, V4QImode, operands[0],
2741 V4QImode, operands[1], operands[2], false);
2757 (define_insn "<optab>v2hi3"
2758 [(set (match_operand:V2HI 0 "register_operand" "=r,r")
2760 (match_operand:V2HI 1 "reg_or_0_operand" "<comm>rO,rO")
2761 (match_operand:V2HI 2 "reg_or_v2s8bit_operand" "Y,rO")))]
2764 <insn>ih<u>\t%0, %r1, %j2
2765 <insn>h<u>\t%0, %r1, %r2"
2766 [(set_attr "type" "X01,X01")])
2768 (define_expand "insn_<insn>h<u>"
2769 [(set (match_operand:SI 0 "register_operand" "")
2771 (match_operand:SI 1 "reg_or_0_operand" "")
2772 (match_operand:SI 2 "reg_or_0_operand" "")))]
2775 tilepro_expand_builtin_vector_binop (gen_<optab>v2hi3, V2HImode, operands[0],
2776 V2HImode, operands[1], operands[2], true);
2780 (define_expand "insn_<insn>ih<u>"
2781 [(set (match_operand:SI 0 "register_operand" "")
2783 (match_operand:SI 1 "reg_or_0_operand" "")
2784 (match_operand:SI 2 "s8bit_cint_operand" "")))]
2787 /* Tile out immediate and expand to general case. */
2788 rtx n = tilepro_simd_int (operands[2], HImode);
2789 tilepro_expand_builtin_vector_binop (gen_<optab>v2hi3, V2HImode, operands[0],
2790 V2HImode, operands[1], n, true);
2800 (define_insn "<optab>v2hi3"
2801 [(set (match_operand:V2HI 0 "register_operand" "=r,r")
2803 (match_operand:V2HI 1 "reg_or_0_operand" "rO,rO")
2804 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO")))]
2807 <insn>ih<u>\t%0, %r1, %2
2808 <insn>h<u>\t%0, %r1, %r2"
2809 [(set_attr "type" "X01,X01")])
2811 (define_expand "insn_<insn>h<u>"
2812 [(set (match_operand:SI 0 "register_operand" "")
2814 (match_operand:SI 1 "reg_or_0_operand" "")
2815 (match_operand:SI 2 "reg_or_0_operand" "")))]
2818 tilepro_expand_builtin_vector_binop (gen_<optab>v2hi3, V2HImode, operands[0],
2819 V2HImode, operands[1], operands[2], false);
2829 (define_insn "<optab>v4qi3"
2830 [(set (match_operand:V4QI 0 "register_operand" "=r")
2832 (match_operand:V4QI 1 "reg_or_0_operand" "<comm>rO")
2833 (match_operand:V4QI 2 "reg_or_0_operand" "rO")))]
2835 "<insn>b<u>\t%0, %r1, %r2"
2836 [(set_attr "type" "X01")])
2838 (define_expand "insn_<insn>b<u>"
2839 [(set (match_operand:SI 0 "register_operand" "")
2841 (match_operand:SI 1 "reg_or_0_operand" "")
2842 (match_operand:SI 2 "reg_or_0_operand" "")))]
2845 tilepro_expand_builtin_vector_binop (gen_<optab>v4qi3, V4QImode, operands[0],
2846 V4QImode, operands[1], operands[2], true);
2856 (define_insn "<optab>v2hi3"
2857 [(set (match_operand:V2HI 0 "register_operand" "=r")
2859 (match_operand:V2HI 1 "reg_or_0_operand" "<comm>rO")
2860 (match_operand:V2HI 2 "reg_or_0_operand" "rO")))]
2862 "<insn>h<u>\t%0, %r1, %r2"
2863 [(set_attr "type" "X01")])
2865 (define_expand "insn_<insn>h<u>"
2866 [(set (match_operand:SI 0 "register_operand" "")
2868 (match_operand:SI 1 "reg_or_0_operand" "")
2869 (match_operand:SI 2 "reg_or_0_operand" "")))]
2872 tilepro_expand_builtin_vector_binop (gen_<optab>v2hi3, V2HImode, operands[0],
2873 V2HImode, operands[1], operands[2], true);
2879 ;; Byte ordering of these vectors is endian dependent. We concat
2880 ;; right-to-left for little endian. We concat and interleave in the
2881 ;; opposite way gcc's vector patterns work, so we need to reverse the
2882 ;; order of source operands.
2884 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
2885 ;; => {A3,A2,A1,A0,B3,B2,B1,B0}
2887 (define_insn "vec_interleave_highv4qi"
2888 [(set (match_operand:V4QI 0 "register_operand" "=r")
2890 (vec_concat:V8QI (match_operand:V4QI 1 "reg_or_0_operand" "rO")
2891 (match_operand:V4QI 2 "reg_or_0_operand" "rO"))
2892 (parallel [(const_int 2) (const_int 6)
2893 (const_int 3) (const_int 7)])))]
2895 "inthb\t%0, %r2, %r1"
2896 [(set_attr "type" "X01")])
2898 (define_expand "insn_inthb"
2899 [(match_operand:SI 0 "register_operand" "")
2900 (match_operand:SI 1 "reg_or_0_operand" "")
2901 (match_operand:SI 2 "reg_or_0_operand" "")]
2904 /* Our instruction interleaves opposite of the way vec_interleave
2905 works, so we need to reverse the source operands. */
2906 tilepro_expand_builtin_vector_binop (gen_vec_interleave_highv4qi, V4QImode,
2907 operands[0], V4QImode, operands[2],
2913 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
2914 ;; => {A3,A2,A1,A0,B3,B2,B1,B0}
2916 (define_insn "vec_interleave_lowv4qi"
2917 [(set (match_operand:V4QI 0 "register_operand" "=r")
2919 (vec_concat:V8QI (match_operand:V4QI 1 "reg_or_0_operand" "rO")
2920 (match_operand:V4QI 2 "reg_or_0_operand" "rO"))
2921 (parallel [(const_int 0) (const_int 4)
2922 (const_int 1) (const_int 5)])))]
2924 "intlb\t%0, %r2, %r1"
2925 [(set_attr "type" "X01")])
2927 (define_expand "insn_intlb"
2928 [(match_operand:SI 0 "register_operand" "")
2929 (match_operand:SI 1 "reg_or_0_operand" "")
2930 (match_operand:SI 2 "reg_or_0_operand" "")]
2933 /* Our instruction interleaves opposite of the way vec_interleave
2934 works, so we need to reverse the source operands. */
2935 tilepro_expand_builtin_vector_binop (gen_vec_interleave_lowv4qi, V4QImode,
2936 operands[0], V4QImode, operands[2],
2945 (define_insn "vec_interleave_highv2hi"
2946 [(set (match_operand:V2HI 0 "register_operand" "=r")
2948 (vec_concat:V4HI (match_operand:V2HI 1 "reg_or_0_operand" "rO")
2949 (match_operand:V2HI 2 "reg_or_0_operand" "rO"))
2950 (parallel [(const_int 1) (const_int 3)])))]
2952 "inthh\t%0, %r2, %r1"
2953 [(set_attr "type" "X01")])
2955 (define_expand "insn_inthh"
2956 [(match_operand:SI 0 "register_operand" "")
2957 (match_operand:SI 1 "reg_or_0_operand" "")
2958 (match_operand:SI 2 "reg_or_0_operand" "")]
2961 /* Our instruction interleaves opposite of the way vec_interleave
2962 works, so we need to reverse the source operands. */
2963 tilepro_expand_builtin_vector_binop (gen_vec_interleave_highv2hi, V2HImode,
2964 operands[0], V2HImode, operands[2],
2973 (define_insn "vec_interleave_lowv2hi"
2974 [(set (match_operand:V2HI 0 "register_operand" "=r")
2976 (vec_concat:V4HI (match_operand:V2HI 1 "reg_or_0_operand" "rO")
2977 (match_operand:V2HI 2 "reg_or_0_operand" "rO"))
2978 (parallel [(const_int 0) (const_int 2)])))]
2980 "intlh\t%0, %r2, %r1"
2981 [(set_attr "type" "X01")])
2983 (define_expand "insn_intlh"
2984 [(match_operand:SI 0 "register_operand" "")
2985 (match_operand:SI 1 "reg_or_0_operand" "")
2986 (match_operand:SI 2 "reg_or_0_operand" "")]
2989 /* Our instruction interleaves opposite of the way vec_interleave
2990 works, so we need to reverse the source operands. */
2991 tilepro_expand_builtin_vector_binop (gen_vec_interleave_lowv2hi, V2HImode,
2992 operands[0], V2HImode, operands[2],
3001 (define_insn "vec_pack_<pack_optab>_v2hi"
3002 [(set (match_operand:V4QI 0 "register_operand" "=r")
3004 (v2pack:V2QI (match_operand:V2HI 1 "reg_or_0_operand" "rO"))
3005 (v2pack:V2QI (match_operand:V2HI 2 "reg_or_0_operand" "rO"))))]
3007 "<pack_insn>b<pack_u>\t%0, %r2, %r1"
3008 [(set_attr "type" "X01")])
3010 (define_expand "insn_<pack_insn>b<pack_u>"
3011 [(set (match_operand:SI 0 "register_operand" "")
3013 (v2pack:V2QI (match_operand:SI 1 "reg_or_0_operand" ""))
3014 (v2pack:V2QI (match_operand:SI 2 "reg_or_0_operand" ""))))]
3017 /* Our instruction concats opposite of the way vec_pack works, so we
3018 need to reverse the source operands. */
3019 tilepro_expand_builtin_vector_binop (gen_vec_pack_<pack_optab>_v2hi,
3020 V4QImode, operands[0],
3021 V2HImode, operands[2], operands[1], true);
3028 (define_insn "vec_pack_hipart_v2hi"
3029 [(set (match_operand:V4QI 0 "register_operand" "=r")
3032 (ashiftrt:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "rO")
3035 (ashiftrt:V2HI (match_operand:V2HI 2 "reg_or_0_operand" "rO")
3038 "packhb\t%0, %r2, %r1"
3039 [(set_attr "type" "X01")])
3041 (define_expand "insn_packhb"
3042 [(set (match_operand:SI 0 "register_operand" "")
3045 (ashiftrt:V2HI (match_operand:SI 2 "reg_or_0_operand" "")
3048 (ashiftrt:V2HI (match_operand:SI 1 "reg_or_0_operand" "")
3052 /* Our instruction concats opposite of the way vec_pack works, so we
3053 need to reverse the source operands. */
3054 tilepro_expand_builtin_vector_binop (gen_vec_pack_hipart_v2hi,
3055 V4QImode, operands[0],
3056 V2HImode, operands[2], operands[1], true);
3063 (define_insn "vec_pack_ssat_si"
3064 [(set (match_operand:V2HI 0 "register_operand" "=r")
3066 (ss_truncate:HI (match_operand:SI 1 "reg_or_0_operand" "rO"))
3067 (ss_truncate:HI (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
3069 "packhs\t%0, %r2, %r1"
3070 [(set_attr "type" "X01")])
3072 (define_expand "insn_packhs"
3073 [(set (match_operand:SI 0 "register_operand" "")
3075 (ss_truncate:HI (match_operand:SI 2 "reg_or_0_operand" ""))
3076 (ss_truncate:HI (match_operand:SI 1 "reg_or_0_operand" ""))))]
3079 /* Our instruction concats opposite of the way vec_pack works, so we
3080 need to reverse the source operands. */
3081 tilepro_expand_builtin_vector_binop (gen_vec_pack_ssat_si,
3082 V2HImode, operands[0],
3083 SImode, operands[2], operands[1], true);
3087 ;; Rest of the intrinsics
3088 (define_insn "insn_adiffb_u"
3089 [(set (match_operand:SI 0 "register_operand" "=r")
3090 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3091 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3092 UNSPEC_INSN_ADIFFB_U))]
3094 "adiffb_u\t%0, %r1, %r2"
3095 [(set_attr "type" "X0_2cycle")])
3097 (define_insn "insn_adiffh"
3098 [(set (match_operand:SI 0 "register_operand" "=r")
3099 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3100 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3101 UNSPEC_INSN_ADIFFH))]
3103 "adiffh\t%0, %r1, %r2"
3104 [(set_attr "type" "X0_2cycle")])
3106 (define_insn "insn_avgb_u"
3107 [(set (match_operand:SI 0 "register_operand" "=r")
3108 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3109 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3110 UNSPEC_INSN_AVGB_U))]
3112 "avgb_u\t%0, %r1, %r2"
3113 [(set_attr "type" "X0")])
3115 (define_insn "insn_avgh"
3116 [(set (match_operand:SI 0 "register_operand" "=r")
3117 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3118 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3121 "avgh\t%0, %r1, %r2"
3122 [(set_attr "type" "X0")])
3124 (define_insn "insn_bitx"
3125 [(set (match_operand:SI 0 "register_operand" "=r")
3126 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")]
3130 [(set_attr "type" "Y0")])
3132 (define_insn "insn_crc32_32"
3133 [(set (match_operand:SI 0 "register_operand" "=r")
3134 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3135 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3136 UNSPEC_INSN_CRC32_32))]
3138 "crc32_32\t%0, %r1, %r2"
3139 [(set_attr "type" "X0")])
3141 (define_insn "insn_crc32_8"
3142 [(set (match_operand:SI 0 "register_operand" "=r")
3143 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3144 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3145 UNSPEC_INSN_CRC32_8))]
3147 "crc32_8\t%0, %r1, %r2"
3148 [(set_attr "type" "X0")])
3150 (define_insn "insn_dtlbpr"
3151 [(unspec_volatile:VOID [(match_operand:SI 0 "reg_or_0_operand" "rO")]
3152 UNSPEC_INSN_DTLBPR)]
3155 [(set_attr "type" "X1")])
3157 (define_insn "insn_dword_align"
3158 [(set (match_operand:SI 0 "register_operand" "=r")
3159 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3160 (match_operand:SI 2 "reg_or_0_operand" "rO")
3161 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3162 UNSPEC_INSN_DWORD_ALIGN))]
3164 "dword_align\t%0, %r2, %r3"
3165 [(set_attr "type" "X0")])
3167 (define_insn "insn_finv"
3168 [(unspec_volatile:VOID [(match_operand:SI 0 "reg_or_0_operand" "rO")]
3172 [(set_attr "type" "X1")])
3174 (define_insn "insn_flush"
3175 [(unspec_volatile:VOID [(match_operand:SI 0 "reg_or_0_operand" "rO")]
3179 [(set_attr "type" "X1")])
3181 (define_insn "insn_fnop"
3182 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_FNOP)]
3186 (define_insn "insn_ill"
3187 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_ILL)]
3190 [(set_attr "type" "cannot_bundle")])
3192 (define_insn "insn_inv"
3193 [(unspec_volatile:VOID [(match_operand:SI 0 "reg_or_0_operand" "rO")]
3197 [(set_attr "type" "X1")])
3199 (define_insn "insn_lnk"
3200 [(set (match_operand:SI 0 "register_operand" "=r")
3201 (unspec:SI [(const_int 0)] UNSPEC_INSN_LNK))]
3204 [(set_attr "type" "X1")])
3206 (define_insn "insn_mnzb"
3207 [(set (match_operand:SI 0 "register_operand" "=r")
3208 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3209 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3212 "mnzb\t%0, %r1, %r2"
3213 [(set_attr "type" "X01")])
3215 (define_insn "insn_mnzh"
3216 [(set (match_operand:SI 0 "register_operand" "=r")
3217 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3218 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3221 "mnzh\t%0, %r1, %r2"
3222 [(set_attr "type" "X01")])
3224 (define_insn "insn_mulhh_ss"
3225 [(set (match_operand:SI 0 "register_operand" "=r")
3226 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3227 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3228 UNSPEC_INSN_MULHH_SS))]
3230 "mulhh_ss\t%0, %r1, %r2"
3231 [(set_attr "type" "Y0_2cycle")])
3233 (define_insn "insn_mulhh_su"
3234 [(set (match_operand:SI 0 "register_operand" "=r")
3235 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3236 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3237 UNSPEC_INSN_MULHH_SU))]
3239 "mulhh_su\t%0, %r1, %r2"
3240 [(set_attr "type" "X0_2cycle")])
3242 (define_insn "insn_mulhh_uu"
3243 [(set (match_operand:SI 0 "register_operand" "=r")
3244 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3245 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3246 UNSPEC_INSN_MULHH_UU))]
3248 "mulhh_uu\t%0, %r1, %r2"
3249 [(set_attr "type" "Y0_2cycle")])
3251 (define_insn "insn_mulhha_ss"
3252 [(set (match_operand:SI 0 "register_operand" "=r")
3253 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3254 (match_operand:SI 2 "reg_or_0_operand" "rO")
3255 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3256 UNSPEC_INSN_MULHHA_SS))]
3258 "mulhha_ss\t%0, %r2, %r3"
3259 [(set_attr "type" "Y0_2cycle")])
3261 (define_insn "insn_mulhha_su"
3262 [(set (match_operand:SI 0 "register_operand" "=r")
3263 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3264 (match_operand:SI 2 "reg_or_0_operand" "rO")
3265 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3266 UNSPEC_INSN_MULHHA_SU))]
3268 "mulhha_su\t%0, %r2, %r3"
3269 [(set_attr "type" "X0_2cycle")])
3271 (define_insn "insn_mulhha_uu"
3272 [(set (match_operand:SI 0 "register_operand" "=r")
3273 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3274 (match_operand:SI 2 "reg_or_0_operand" "rO")
3275 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3276 UNSPEC_INSN_MULHHA_UU))]
3278 "mulhha_uu\t%0, %r2, %r3"
3279 [(set_attr "type" "Y0_2cycle")])
3281 (define_insn "insn_mulhhsa_uu"
3282 [(set (match_operand:SI 0 "register_operand" "=r")
3283 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3284 (match_operand:SI 2 "reg_or_0_operand" "rO")
3285 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3286 UNSPEC_INSN_MULHHSA_UU))]
3288 "mulhhsa_uu\t%0, %r2, %r3"
3289 [(set_attr "type" "X0_2cycle")])
3291 (define_insn "insn_mulhl_ss"
3292 [(set (match_operand:SI 0 "register_operand" "=r")
3293 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3294 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3295 UNSPEC_INSN_MULHL_SS))]
3297 "mulhl_ss\t%0, %r1, %r2"
3298 [(set_attr "type" "X0_2cycle")])
3300 (define_insn "insn_mulhl_su"
3301 [(set (match_operand:SI 0 "register_operand" "=r")
3302 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3303 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3304 UNSPEC_INSN_MULHL_SU))]
3306 "mulhl_su\t%0, %r1, %r2"
3307 [(set_attr "type" "X0_2cycle")])
3309 (define_insn "insn_mulhl_us"
3310 [(set (match_operand:SI 0 "register_operand" "=r")
3311 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3312 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3313 UNSPEC_INSN_MULHL_US))]
3315 "mulhl_us\t%0, %r1, %r2"
3316 [(set_attr "type" "X0_2cycle")])
3318 (define_insn "insn_mulhl_uu"
3319 [(set (match_operand:SI 0 "register_operand" "=r")
3320 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3321 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3322 UNSPEC_INSN_MULHL_UU))]
3324 "mulhl_uu\t%0, %r1, %r2"
3325 [(set_attr "type" "X0_2cycle")])
3327 (define_insn "insn_mulhla_ss"
3328 [(set (match_operand:SI 0 "register_operand" "=r")
3329 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3330 (match_operand:SI 2 "reg_or_0_operand" "rO")
3331 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3332 UNSPEC_INSN_MULHLA_SS))]
3334 "mulhla_ss\t%0, %r2, %r3"
3335 [(set_attr "type" "X0_2cycle")])
3337 (define_insn "insn_mulhla_su"
3338 [(set (match_operand:SI 0 "register_operand" "=r")
3339 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3340 (match_operand:SI 2 "reg_or_0_operand" "rO")
3341 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3342 UNSPEC_INSN_MULHLA_SU))]
3344 "mulhla_su\t%0, %r2, %r3"
3345 [(set_attr "type" "X0_2cycle")])
3347 (define_insn "insn_mulhla_us"
3348 [(set (match_operand:SI 0 "register_operand" "=r")
3349 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3350 (match_operand:SI 2 "reg_or_0_operand" "rO")
3351 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3352 UNSPEC_INSN_MULHLA_US))]
3354 "mulhla_us\t%0, %r2, %r3"
3355 [(set_attr "type" "X0_2cycle")])
3357 (define_insn "insn_mulhla_uu"
3358 [(set (match_operand:SI 0 "register_operand" "=r")
3359 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3360 (match_operand:SI 2 "reg_or_0_operand" "rO")
3361 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3362 UNSPEC_INSN_MULHLA_UU))]
3364 "mulhla_uu\t%0, %r2, %r3"
3365 [(set_attr "type" "X0_2cycle")])
3367 (define_insn "insn_mulhlsa_uu"
3368 [(set (match_operand:SI 0 "register_operand" "=r")
3369 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3370 (match_operand:SI 2 "reg_or_0_operand" "rO")
3371 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3372 UNSPEC_INSN_MULHLSA_UU))]
3374 "mulhlsa_uu\t%0, %r2, %r3"
3375 [(set_attr "type" "Y0_2cycle")])
3377 (define_insn "insn_mulll_ss"
3378 [(set (match_operand:SI 0 "register_operand" "=r")
3379 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3380 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3381 UNSPEC_INSN_MULLL_SS))]
3383 "mulll_ss\t%0, %r1, %r2"
3384 [(set_attr "type" "Y0_2cycle")])
3386 (define_insn "insn_mulll_su"
3387 [(set (match_operand:SI 0 "register_operand" "=r")
3388 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3389 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3390 UNSPEC_INSN_MULLL_SU))]
3392 "mulll_su\t%0, %r1, %r2"
3393 [(set_attr "type" "X0_2cycle")])
3395 (define_insn "insn_mulll_uu"
3396 [(set (match_operand:SI 0 "register_operand" "=r")
3397 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3398 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3399 UNSPEC_INSN_MULLL_UU))]
3401 "mulll_uu\t%0, %r1, %r2"
3402 [(set_attr "type" "Y0_2cycle")])
3404 (define_insn "insn_mullla_ss"
3405 [(set (match_operand:SI 0 "register_operand" "=r")
3406 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3407 (match_operand:SI 2 "reg_or_0_operand" "rO")
3408 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3409 UNSPEC_INSN_MULLLA_SS))]
3411 "mullla_ss\t%0, %r2, %r3"
3412 [(set_attr "type" "Y0_2cycle")])
3414 (define_insn "insn_mullla_su"
3415 [(set (match_operand:SI 0 "register_operand" "=r")
3416 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3417 (match_operand:SI 2 "reg_or_0_operand" "rO")
3418 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3419 UNSPEC_INSN_MULLLA_SU))]
3421 "mullla_su\t%0, %r2, %r3"
3422 [(set_attr "type" "X0_2cycle")])
3424 (define_insn "insn_mullla_uu"
3425 [(set (match_operand:SI 0 "register_operand" "=r")
3426 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3427 (match_operand:SI 2 "reg_or_0_operand" "rO")
3428 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3429 UNSPEC_INSN_MULLLA_UU))]
3431 "mullla_uu\t%0, %r2, %r3"
3432 [(set_attr "type" "Y0_2cycle")])
3434 (define_insn "insn_mulllsa_uu"
3435 [(set (match_operand:SI 0 "register_operand" "=r")
3436 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3437 (match_operand:SI 2 "reg_or_0_operand" "rO")
3438 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3439 UNSPEC_INSN_MULLLSA_UU))]
3441 "mulllsa_uu\t%0, %r2, %r3"
3442 [(set_attr "type" "X0_2cycle")])
3444 (define_insn "insn_mzb"
3445 [(set (match_operand:SI 0 "register_operand" "=r")
3446 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3447 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3451 [(set_attr "type" "X01")])
3453 (define_insn "insn_mzh"
3454 [(set (match_operand:SI 0 "register_operand" "=r")
3455 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3456 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3460 [(set_attr "type" "X01")])
3462 (define_insn "insn_nap"
3463 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_NAP)]
3466 [(set_attr "type" "cannot_bundle")])
3468 (define_insn "insn_nor"
3469 [(set (match_operand:SI 0 "register_operand" "=r")
3470 (and:SI (not:SI (match_operand:SI 1 "reg_or_0_operand" "rO"))
3471 (not:SI (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
3473 "nor\t%0, %r1, %r2")
3475 (define_insn "insn_sadab_u"
3476 [(set (match_operand:SI 0 "register_operand" "=r")
3477 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3478 (match_operand:SI 2 "reg_or_0_operand" "rO")
3479 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3480 UNSPEC_INSN_SADAB_U))]
3482 "sadab_u\t%0, %r2, %r3"
3483 [(set_attr "type" "X0_2cycle")])
3485 (define_insn "insn_sadah"
3486 [(set (match_operand:SI 0 "register_operand" "=r")
3487 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3488 (match_operand:SI 2 "reg_or_0_operand" "rO")
3489 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3490 UNSPEC_INSN_SADAH))]
3492 "sadah\t%0, %r2, %r3"
3493 [(set_attr "type" "X0_2cycle")])
3495 (define_insn "insn_sadah_u"
3496 [(set (match_operand:SI 0 "register_operand" "=r")
3497 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3498 (match_operand:SI 2 "reg_or_0_operand" "rO")
3499 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3500 UNSPEC_INSN_SADAH_U))]
3502 "sadah_u\t%0, %r2, %r3"
3503 [(set_attr "type" "X0_2cycle")])
3505 (define_insn "insn_sadb_u"
3506 [(set (match_operand:SI 0 "register_operand" "=r")
3507 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3508 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3509 UNSPEC_INSN_SADB_U))]
3511 "sadb_u\t%0, %r1, %r2"
3512 [(set_attr "type" "X0_2cycle")])
3514 (define_insn "insn_sadh"
3515 [(set (match_operand:SI 0 "register_operand" "=r")
3516 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3517 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3520 "sadh\t%0, %r1, %r2"
3521 [(set_attr "type" "X0_2cycle")])
3523 (define_insn "insn_sadh_u"
3524 [(set (match_operand:SI 0 "register_operand" "=r")
3525 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "rO")
3526 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3527 UNSPEC_INSN_SADH_U))]
3529 "sadh_u\t%0, %r1, %r2"
3530 [(set_attr "type" "X0_2cycle")])
3532 (define_insn "insn_tblidxb0"
3533 [(set (match_operand:SI 0 "register_operand" "=r")
3534 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3535 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3536 UNSPEC_INSN_TBLIDXB0))]
3539 [(set_attr "type" "Y0")])
3541 (define_insn "insn_tblidxb1"
3542 [(set (match_operand:SI 0 "register_operand" "=r")
3543 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3544 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3545 UNSPEC_INSN_TBLIDXB1))]
3548 [(set_attr "type" "Y0")])
3550 (define_insn "insn_tblidxb2"
3551 [(set (match_operand:SI 0 "register_operand" "=r")
3552 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3553 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3554 UNSPEC_INSN_TBLIDXB2))]
3557 [(set_attr "type" "Y0")])
3559 (define_insn "insn_tblidxb3"
3560 [(set (match_operand:SI 0 "register_operand" "=r")
3561 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3562 (match_operand:SI 2 "reg_or_0_operand" "rO")]
3563 UNSPEC_INSN_TBLIDXB3))]
3566 [(set_attr "type" "Y0")])
3570 ;; pic related instructions
3573 ;; NOTE: We compute the label in this unusual way because if we place
3574 ;; the label after the lnk, whether it is at the same address as the
3575 ;; lnk will vary depending on whether the optimization level chooses to
3576 ;; insert bundling braces.
3577 (define_insn "insn_lnk_and_label"
3578 [(set (match_operand:SI 0 "register_operand" "=r")
3579 (unspec_volatile:SI [(match_operand:SI 1 "symbolic_operand" "")]
3580 UNSPEC_LNK_AND_LABEL))]
3582 "%1 = . + 8\n\tlnk\t%0"
3583 [(set_attr "type" "X1")])
3585 (define_expand "addli_pcrel"
3586 [(set (match_operand:SI 0 "register_operand" "")
3588 (match_operand:SI 1 "register_operand" "")
3590 (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")
3591 (match_operand:SI 3 "symbolic_operand" "")]
3592 UNSPEC_PCREL_SYM))))]
3595 (define_expand "auli_pcrel"
3596 [(set (match_operand:SI 0 "register_operand" "")
3598 (match_operand:SI 1 "reg_or_0_operand" "")
3601 (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")
3602 (match_operand:SI 3 "symbolic_operand" "")]
3603 UNSPEC_PCREL_SYM)))))]
3606 (define_expand "add_got16"
3607 [(set (match_operand:SI 0 "register_operand" "")
3609 (match_operand:SI 1 "reg_or_0_operand" "")
3610 (const:SI (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")]
3611 UNSPEC_GOT16_SYM))))]
3614 (define_expand "addhi_got32"
3615 [(set (match_operand:SI 0 "register_operand" "")
3617 (match_operand:SI 1 "reg_or_0_operand" "")
3619 (const:SI (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")]
3620 UNSPEC_GOT32_SYM)))))]
3623 (define_expand "addlo_got32"
3624 [(set (match_operand:SI 0 "register_operand" "")
3626 (match_operand:SI 1 "reg_or_0_operand" "")
3627 (const:SI (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")]
3628 UNSPEC_GOT32_SYM))))]
3636 (define_expand "tls_gd_addhi"
3637 [(set (match_operand:SI 0 "register_operand" "")
3639 (match_operand:SI 1 "reg_or_0_operand" "")
3641 (const:SI (unspec:SI [(match_operand 2 "tls_symbolic_operand" "")]
3645 (define_expand "tls_gd_addlo"
3646 [(set (match_operand:SI 0 "register_operand" "")
3648 (match_operand:SI 1 "reg_or_0_operand" "")
3649 (const:SI (unspec:SI [(match_operand 2 "tls_symbolic_operand" "")]
3653 (define_expand "tls_gd_call"
3656 (unspec:SI [(match_operand:SI 0 "tls_symbolic_operand" "")
3658 UNSPEC_TLS_GD_CALL))
3659 (clobber (reg:SI 25))
3660 (clobber (reg:SI 26))
3661 (clobber (reg:SI 27))
3662 (clobber (reg:SI 28))
3663 (clobber (reg:SI 29))
3664 (clobber (reg:SI 55))])]
3667 cfun->machine->calls_tls_get_addr = true;
3670 (define_insn "*tls_gd_call"
3672 (unspec:SI [(match_operand:SI 0 "tls_symbolic_operand" "")
3674 UNSPEC_TLS_GD_CALL))
3675 (clobber (reg:SI 25))
3676 (clobber (reg:SI 26))
3677 (clobber (reg:SI 27))
3678 (clobber (reg:SI 28))
3679 (clobber (reg:SI 29))
3680 (clobber (reg:SI 55))]
3682 "jal\ttls_gd_call(%0)"
3683 [(set_attr "type" "X1")])
3685 (define_insn "tls_gd_add"
3686 [(set (match_operand:SI 0 "register_operand" "=r")
3687 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
3688 (match_operand:SI 2 "tls_symbolic_operand" "")]
3689 UNSPEC_TLS_GD_ADD))]
3691 "addi\t%0, %1, tls_gd_add(%2)")
3693 (define_insn "tls_ie_load"
3694 [(set (match_operand:SI 0 "register_operand" "=r")
3695 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
3696 (match_operand:SI 2 "tls_symbolic_operand" "")]
3697 UNSPEC_TLS_IE_LOAD))]
3699 "lw_tls\t%0, %1, tls_ie_load(%2)"
3700 [(set_attr "type" "X1_2cycle")])
3702 (define_expand "tls_ie_addhi"
3703 [(set (match_operand:SI 0 "register_operand" "")
3705 (match_operand:SI 1 "register_operand" "")
3707 (const:SI (unspec:SI [(match_operand 2 "tls_ie_symbolic_operand" "")]
3711 (define_expand "tls_ie_addlo"
3712 [(set (match_operand:SI 0 "register_operand" "")
3714 (match_operand:SI 1 "register_operand" "")
3715 (const:SI (unspec:SI [(match_operand 2 "tls_ie_symbolic_operand" "")]
3719 (define_expand "tls_le_addhi"
3720 [(set (match_operand:SI 0 "register_operand" "")
3722 (match_operand:SI 1 "register_operand" "")
3724 (const:SI (unspec:SI [(match_operand 2 "tls_le_symbolic_operand" "")]
3728 (define_expand "tls_le_addlo"
3729 [(set (match_operand:SI 0 "register_operand" "")
3731 (match_operand:SI 1 "register_operand" "")
3732 (const:SI (unspec:SI [(match_operand 2 "tls_le_symbolic_operand" "")]
3738 ;; Stack protector instructions.
3741 (define_expand "stack_protect_set"
3742 [(set (match_operand 0 "nonautoincmem_operand" "")
3743 (match_operand 1 "nonautoincmem_operand" ""))]
3746 #ifdef TARGET_THREAD_SSP_OFFSET
3747 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
3748 rtx ssp_addr = gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET));
3749 rtx ssp = gen_reg_rtx (Pmode);
3751 emit_insn (gen_rtx_SET (VOIDmode, ssp, ssp_addr));
3753 operands[1] = gen_rtx_MEM (Pmode, ssp);
3756 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
3761 (define_insn "stack_protect_setsi"
3762 [(set (match_operand:SI 0 "nonautoincmem_operand" "=U")
3763 (unspec:SI [(match_operand:SI 1 "nonautoincmem_operand" "U")]
3765 (set (match_scratch:SI 2 "=&r") (const_int 0))]
3767 "lw\t%2, %1; { sw\t%0, %2; move\t%2, zero }"
3768 [(set_attr "length" "16")
3769 (set_attr "type" "cannot_bundle_3cycle")])
3772 (define_expand "stack_protect_test"
3773 [(match_operand 0 "nonautoincmem_operand" "")
3774 (match_operand 1 "nonautoincmem_operand" "")
3775 (match_operand 2 "" "")]
3781 #ifdef TARGET_THREAD_SSP_OFFSET
3782 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
3783 rtx ssp_addr = gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET));
3784 rtx ssp = gen_reg_rtx (Pmode);
3786 emit_insn (gen_rtx_SET (VOIDmode, ssp, ssp_addr));
3788 operands[1] = gen_rtx_MEM (Pmode, ssp);
3791 compare_result = gen_reg_rtx (SImode);
3793 emit_insn (gen_stack_protect_testsi (compare_result, operands[0],
3796 bcomp = gen_rtx_NE (SImode, compare_result, const0_rtx);
3798 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[2]);
3800 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3801 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
3807 (define_insn "stack_protect_testsi"
3808 [(set (match_operand:SI 0 "register_operand" "=&r")
3809 (unspec:SI [(match_operand:SI 1 "nonautoincmem_operand" "U")
3810 (match_operand:SI 2 "nonautoincmem_operand" "U")]
3812 (set (match_scratch:SI 3 "=&r") (const_int 0))]
3814 "lw\t%0, %1; lw\t%3, %2; { seq\t%0, %0, %3; move\t%3, zero }"
3815 [(set_attr "length" "24")
3816 (set_attr "type" "cannot_bundle_4cycle")])