main/gcc/config/rl78/rl78.h

   1 /* GCC backend definitions for the Renesas RL78 processor.
   2    Copyright (C) 2011-2013 Free Software Foundation, Inc.
   3    Contributed by Red Hat.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20 \f
  21
  22 #define RL78_MUL_NONE   (rl78_mul_type == MUL_NONE)
  23 #define RL78_MUL_RL78   (rl78_mul_type == MUL_RL78)
  24 #define RL78_MUL_G13    (rl78_mul_type == MUL_G13)
  25
  26 #define TARGET_CPU_CPP_BUILTINS()               \
  27   do                                            \
  28     {                                           \
  29       builtin_define ("__RL78__");              \
  30       builtin_assert ("cpu=RL78");              \
  31       if (RL78_MUL_RL78)                        \
  32         builtin_define ("__RL78_MUL_RL78__");   \
  33       if (RL78_MUL_G13)                         \
  34         builtin_define ("__RL78_MUL_G13__");    \
  35     }                                           \
  36   while (0)
  37
  38 #undef  STARTFILE_SPEC
  39 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
  40
  41 #undef  ENDFILE_SPEC
  42 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  43
  44 #undef  LIB_SPEC
  45 #define LIB_SPEC "                                      \
  46 --start-group                                           \
  47 -lc                                                     \
  48 -lsim                                                   \
  49 %{fprofile-arcs|fprofile-generate|coverage:-lgcov}      \
  50 --end-group                                             \
  51 %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}}         \
  52 "
  53 \f
  54
  55 #define BITS_BIG_ENDIAN                 0
  56 #define BYTES_BIG_ENDIAN                0
  57 #define WORDS_BIG_ENDIAN                0
  58
  59 #ifdef IN_LIBGCC2
  60 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits).  */
  61 #define UNITS_PER_WORD                  4
  62 /* We have a problem with libgcc2.  It only defines two versions of
  63    each function, one for "int" and one for "long long".  Ie it assumes
  64    that "sizeof (int) == sizeof (long)".  For the RL78 this is not true
  65    and we need a third set of functions.  We explicitly define
  66    LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
  67    to get the SI and DI versions from the libgcc2.c sources, and we
  68    provide our own set of HI functions, which is why this
  69    definition is surrounded by #ifndef..#endif.  */
  70 #ifndef LIBGCC2_UNITS_PER_WORD
  71 #define LIBGCC2_UNITS_PER_WORD          4
  72 #endif
  73 #else
  74 /* Actual width of a word, in units (bytes).  */
  75 #define UNITS_PER_WORD                  1
  76 #endif
  77
  78 #define SHORT_TYPE_SIZE                 16
  79 #define INT_TYPE_SIZE                   16
  80 #define LONG_TYPE_SIZE                  32
  81 #define LONG_LONG_TYPE_SIZE             64
  82
  83 #define FLOAT_TYPE_SIZE                 32
  84 #define DOUBLE_TYPE_SIZE                32 /*64*/
  85 #define LONG_DOUBLE_TYPE_SIZE           64 /*DOUBLE_TYPE_SIZE*/
  86
  87 #define LIBGCC2_HAS_DF_MODE             1
  88 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE   64
  89
  90 #define DEFAULT_SIGNED_CHAR             0
  91
  92 #define STRICT_ALIGNMENT                1
  93 #define FUNCTION_BOUNDARY               8
  94 #define BIGGEST_ALIGNMENT               16
  95 #define STACK_BOUNDARY                  16
  96 #define PARM_BOUNDARY                   16
  97
  98 #define STACK_GROWS_DOWNWARD            1
  99 #define FRAME_GROWS_DOWNWARD            1
 100 #define FIRST_PARM_OFFSET(FNDECL)       0
 101
 102 #define MAX_REGS_PER_ADDRESS            1
 103
 104 #define Pmode                           HImode
 105 #define POINTER_SIZE                    16
 106 #undef  SIZE_TYPE
 107 #define SIZE_TYPE                       "unsigned int"
 108 #undef  PTRDIFF_TYPE
 109 #define PTRDIFF_TYPE                    "int"
 110 #undef  WCHAR_TYPE
 111 #define WCHAR_TYPE                      "long int"
 112 #undef  WCHAR_TYPE_SIZE
 113 #define WCHAR_TYPE_SIZE                 BITS_PER_WORD
 114 #define POINTERS_EXTEND_UNSIGNED        1
 115 #define FUNCTION_MODE                   HImode
 116 #define CASE_VECTOR_MODE                Pmode
 117 #define WORD_REGISTER_OPERATIONS        0
 118 #define HAS_LONG_COND_BRANCH            0
 119 #define HAS_LONG_UNCOND_BRANCH          0
 120
 121 #define MOVE_MAX                        2
 122 #define STARTING_FRAME_OFFSET           0
 123
 124 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)   1
 125
 126 #define ADDR_SPACE_FAR  1
 127
 128 #define HAVE_PRE_DECCREMENT             0
 129 #define HAVE_POST_INCREMENT             0
 130
 131 #define MOVE_RATIO(SPEED)               ((SPEED) ? 24 : 16)
 132 #define SLOW_BYTE_ACCESS                0
 133
 134 #define STORE_FLAG_VALUE                1
 135 #define LOAD_EXTEND_OP(MODE)            ZERO_EXTEND
 136 #define SHORT_IMMEDIATES_SIGN_EXTEND    0
 137 \f
 138
 139 /* The RL78 has four register banks.  Normal operation uses RB0 as
 140    real registers, RB1 and RB2 as "virtual" registers (because we know
 141    they'll be there, and not used as variables), and RB3 is reserved
 142    for interrupt handlers.  The virtual registers are accessed as
 143    SADDRs:
 144
 145    FFEE0-FFEE7 RB0
 146    FFEE8-FFEEF RB1
 147    FFEF0-FFEF7 RB2
 148    FFEF8-FFEFF RB3
 149 */
 150 #define REGISTER_NAMES                                          \
 151   {                                                             \
 152     "x", "a", "c", "b", "e", "d", "l", "h",                     \
 153     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",       \
 154     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",     \
 155     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",     \
 156       "sp", "ap", "psw", "es", "cs"                             \
 157   }
 158
 159 #define ADDITIONAL_REGISTER_NAMES       \
 160 {                                       \
 161 { "ax", 0 }, \
 162 { "bc", 2 }, \
 163 { "de", 4 }, \
 164 { "hl", 6 }, \
 165 { "rp0", 0 }, \
 166 { "rp1", 2 }, \
 167 { "rp2", 4 }, \
 168 { "rp3", 6 }, \
 169 { "r0", 0 }, \
 170 { "r1", 1 }, \
 171 { "r2", 2 }, \
 172 { "r3", 3 }, \
 173 { "r4", 4 }, \
 174 { "r5", 5 }, \
 175 { "r6", 6 }, \
 176 { "r7", 7 }, \
 177 }
 178
 179 enum reg_class
 180 {
 181   NO_REGS,                      /* No registers in set.  */
 182   XREG,
 183   AREG,
 184   AXREG,
 185   CREG,
 186   BREG,
 187   BCREG,
 188   EREG,
 189   DREG,
 190   DEREG,
 191   LREG,
 192   HREG,
 193   HLREG,
 194   IDX_REGS,
 195   QI_REGS,
 196   SPREG,
 197   R8W_REGS,
 198   R10W_REGS,
 199   INT_REGS,
 200   V_REGS,                       /* Virtual registers.  */
 201   GR_REGS,                      /* Integer registers.  */
 202   PSWREG,
 203   ALL_REGS,                     /* All registers.  */
 204   LIM_REG_CLASSES               /* Max value + 1.  */
 205 };
 206
 207 #define REG_CLASS_NAMES                                 \
 208 {                                                       \
 209   "NO_REGS",                                            \
 210   "XREG",                                               \
 211   "AREG",                                               \
 212   "AXREG",                                              \
 213   "CREG",                                               \
 214   "BREG",                                               \
 215   "BCREG",                                              \
 216   "EREG",                                               \
 217   "DREG",                                               \
 218   "DEREG",                                              \
 219   "LREG",                                               \
 220   "HREG",                                               \
 221   "HLREG",                                              \
 222   "IDX_REGS",                                           \
 223   "QI_REGS",                                            \
 224   "SPREG",                                              \
 225   "R8W_REGS",                                           \
 226   "R10W_REGS",                                          \
 227   "INT_REGS",                                           \
 228   "V_REGS",                                             \
 229   "GR_REGS",                                            \
 230   "PSWREG",                                             \
 231   "ALL_REGS"                                            \
 232 }
 233
 234 #define REG_CLASS_CONTENTS                              \
 235 {                                                       \
 236   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 237   { 0x00000001, 0x00000000 }, \
 238   { 0x00000002, 0x00000000 }, \
 239   { 0x00000003, 0x00000000 }, \
 240   { 0x00000004, 0x00000000 }, \
 241   { 0x00000008, 0x00000000 }, \
 242   { 0x0000000c, 0x00000000 }, \
 243   { 0x00000010, 0x00000000 }, \
 244   { 0x00000020, 0x00000000 }, \
 245   { 0x00000030, 0x00000000 }, \
 246   { 0x00000040, 0x00000000 }, \
 247   { 0x00000080, 0x00000000 }, \
 248   { 0x000000c0, 0x00000000 }, \
 249   { 0x0000000c, 0x00000000 },   /* B and C - index regs.  */    \
 250   { 0x000000ff, 0x00000000 },   /* all real registers.  */      \
 251   { 0x00000000, 0x00000001 },   /* SP */                        \
 252   { 0x00000300, 0x00000000 },   /* R8 - HImode */               \
 253   { 0x00000c00, 0x00000000 },   /* R10 - HImode */              \
 254   { 0xff000000, 0x00000000 },   /* INT - HImode */              \
 255   { 0x007fff00, 0x00000000 },   /* Virtual registers.  */       \
 256   { 0xff7fffff, 0x00000002 },   /* General registers.  */       \
 257   { 0x04000000, 0x00000004 },   /* PSW.  */     \
 258   { 0xff7fffff, 0x0000001f }    /* All registers.  */           \
 259 }
 260
 261 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
 262 #define N_REG_CLASSES                   (int) LIM_REG_CLASSES
 263 #define CLASS_MAX_NREGS(CLASS, MODE)    ((GET_MODE_SIZE (MODE) \
 264                                           + UNITS_PER_WORD - 1) \
 265                                          / UNITS_PER_WORD)
 266
 267 #define GENERAL_REGS                    GR_REGS
 268 #define BASE_REG_CLASS                  V_REGS
 269 #define INDEX_REG_CLASS                 V_REGS
 270
 271 #define FIRST_PSEUDO_REGISTER           37
 272
 273 #define REGNO_REG_CLASS(REGNO)          ((REGNO) < FIRST_PSEUDO_REGISTER \
 274                                          ? GR_REGS : NO_REGS)
 275
 276 #define FRAME_POINTER_REGNUM            22
 277 #define STACK_POINTER_REGNUM            32
 278 #define ARG_POINTER_REGNUM              33
 279 #define CC_REGNUM                       34
 280 #define FUNC_RETURN_REGNUM              8
 281 #define STATIC_CHAIN_REGNUM             14
 282
 283 /* Trampolines are implemented with a separate data stack.  The memory
 284    on stack only holds the function pointer for the chosen stub.
 285  */
 286
 287 #define TRAMPOLINE_SIZE                 4
 288 #define TRAMPOLINE_ALIGNMENT            16
 289
 290 #define ELIMINABLE_REGS                                 \
 291 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },        \
 292  { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM },        \
 293  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
 294
 295 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)    \
 296   (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
 297
 298
 299 #define FUNCTION_ARG_REGNO_P(N)         0
 300 #define FUNCTION_VALUE_REGNO_P(N)       ((N) == 8)
 301 #define DEFAULT_PCC_STRUCT_RETURN       0
 302
 303 #define FIXED_REGISTERS                                 \
 304 {                                                       \
 305   1,1,1,1, 1,1,1,1,                                     \
 306   0,0,0,0, 0,0,0,0,                                     \
 307   0,0,0,0, 0,0,1,1,                                     \
 308   1,1,1,1, 1,1,1,1,                                     \
 309   0, 1, 0, 1, 1                                         \
 310 }
 311
 312 #define CALL_USED_REGISTERS                             \
 313 {                                                       \
 314   1,1,1,1, 1,1,1,1,                                     \
 315   1,1,1,1, 1,1,1,1,                                     \
 316   0,0,0,0, 0,0,1,1,                                     \
 317   1,1,1,1, 1,1,1,1,                                     \
 318   0, 1, 1, 1, 1                                         \
 319 }
 320
 321 #define LIBCALL_VALUE(MODE)                             \
 322   gen_rtx_REG ((MODE),                                  \
 323                FUNC_RETURN_REGNUM)
 324
 325 /* Order of allocation of registers.  */
 326
 327 #define REG_ALLOC_ORDER                                 \
 328   { 8, 9, 10, 11, 12, 13, 14, 15,                       \
 329     16, 17, 18, 19, 20, 21, 22, 23,                     \
 330     0, 1, 6, 7, 2, 3, 4, 5,                             \
 331     24, 25, 26, 27, 28, 29, 30, 31,                     \
 332     32, 33, 34                                          \
 333 }
 334
 335 #define REGNO_IN_RANGE(REGNO, MIN, MAX)                 \
 336   (IN_RANGE ((REGNO), (MIN), (MAX))                     \
 337    || (reg_renumber != NULL                             \
 338        && reg_renumber[(REGNO)] >= (MIN)                \
 339        && reg_renumber[(REGNO)] <= (MAX)))
 340
 341 #ifdef REG_OK_STRICT
 342 #define REGNO_OK_FOR_BASE_P(regno)      REGNO_IN_RANGE (regno, 16, 23)
 343 #else
 344 #define REGNO_OK_FOR_BASE_P(regno)      1
 345 #endif
 346
 347 #define REGNO_OK_FOR_INDEX_P(regno)     REGNO_OK_FOR_BASE_P (regno)
 348
 349 #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
 350   rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
 351
 352 #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
 353   rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
 354
 355 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR)                               \
 356   ((COUNT) == 0                                                         \
 357    ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
 358    : NULL_RTX)
 359
 360 #define INCOMING_RETURN_ADDR_RTX        gen_rtx_MEM (Pmode, stack_pointer_rtx)
 361
 362 #define ACCUMULATE_OUTGOING_ARGS        1
 363
 364 typedef unsigned int CUMULATIVE_ARGS;
 365
 366 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 367   (CUM) = 0
 368
 369 \f
 370 /* FIXME */
 371 #define NO_PROFILE_COUNTERS     1
 372 #define PROFILE_BEFORE_PROLOGUE 1
 373
 374 #define FUNCTION_PROFILER(FILE, LABELNO)        \
 375     fprintf (FILE, "\tbsr\t__mcount\n");
 376 \f
 377
 378 #define HARD_REGNO_NREGS(REGNO, MODE)            \
 379   rl78_hard_regno_nregs (REGNO, MODE)
 380
 381 #define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
 382   rl78_hard_regno_mode_ok (REGNO, MODE)
 383
 384 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 385   (   (   GET_MODE_CLASS (MODE1) == MODE_FLOAT                  \
 386        || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)         \
 387    == (   GET_MODE_CLASS (MODE2) == MODE_FLOAT                  \
 388        || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 389 \f
 390
 391 #define TEXT_SECTION_ASM_OP ".text"
 392 #define DATA_SECTION_ASM_OP ".data"
 393 #define BSS_SECTION_ASM_OP ".bss"
 394 #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
 395 #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
 396
 397 #define ASM_COMMENT_START       " ;"
 398 #define ASM_APP_ON              ""
 399 #define ASM_APP_OFF             ""
 400 #define LOCAL_LABEL_PREFIX      ".L"
 401 #undef  USER_LABEL_PREFIX
 402 #define USER_LABEL_PREFIX       "_"
 403
 404 #define GLOBAL_ASM_OP           "\t.global\t"
 405
 406 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
 407   fprintf (FILE, "\t.long .L%d\n", VALUE)
 408
 409 /* This is how to output an element of a case-vector that is relative.
 410    Note: The local label referenced by the "3b" below is emitted by
 411    the tablejump insn.  */
 412
 413 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
 414   fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
 415
 416
 417 #define ASM_OUTPUT_ALIGN(STREAM, LOG)           \
 418   do                                            \
 419     {                                           \
 420       if ((LOG) == 0)                           \
 421         break;                                  \
 422       fprintf (STREAM, "\t.balign %d\n", 1 << (LOG));   \
 423     }                                           \
 424   while (0)
 425
 426 /* For PIC put jump tables into the text section so that the offsets that
 427    they contain are always computed between two same-section symbols.  */
 428 #define JUMP_TABLES_IN_TEXT_SECTION     (flag_pic)
 429 \f
 430 /* This is a version of REG_P that also returns TRUE for SUBREGs.  */
 431 #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
 432
 433 /* Like REG_P except that this macro is true for SET expressions.  */
 434 #define SET_P(rtl)    (GET_CODE (rtl) == SET)
 435 \f
 436 #undef  PREFERRED_DEBUGGING_TYPE
 437 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 438
 439 #undef  DWARF2_ADDR_SIZE
 440 #define DWARF2_ADDR_SIZE                        4
 441
 442 #define DWARF2_ASM_LINE_DEBUG_INFO              1
 443
 444 #define EXIT_IGNORE_STACK                       0
 445 #define INCOMING_FRAME_SP_OFFSET                4
 446 \f
 447
 448 #define BRANCH_COST(SPEED,PREDICT)       1
 449 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
 450
 451 #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
 452 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
 453
 454 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
 455
 456 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH.  */
 457 #define DWARF2_UNWIND_INFO 0
 458
 459 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()