gcc/config/i386/subst.md

   1 ;; GCC machine description for AVX512F instructions
   2 ;; Copyright (C) 2013-2020 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Some iterators for extending subst as much as possible
  21 ;; All vectors (Use it for destination)
  22 (define_mode_iterator SUBST_V
  23   [V64QI V32QI V16QI
  24    V32HI V16HI V8HI
  25    V16SI V8SI  V4SI
  26    V8DI  V4DI  V2DI
  27    V16SF V8SF  V4SF
  28    V8DF  V4DF  V2DF])
  29
  30 (define_mode_iterator SUBST_S
  31   [QI HI SI DI])
  32
  33 (define_mode_iterator SUBST_A
  34   [V64QI V32QI V16QI
  35    V32HI V16HI V8HI
  36    V16SI V8SI  V4SI
  37    V8DI  V4DI  V2DI
  38    V16SF V8SF  V4SF
  39    V8DF  V4DF  V2DF
  40    QI HI SI DI SF DF])
  41
  42 (define_subst_attr "mask_name" "mask" "" "_mask")
  43 (define_subst_attr "mask_applied" "mask" "false" "true")
  44 (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2")
  45 (define_subst_attr "mask_operand3" "mask" "" "%{%4%}%N3")
  46 (define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf
  47 (define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4")
  48 (define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6")
  49 (define_subst_attr "mask_operand7" "mask" "" "%{%8%}%N7")
  50 (define_subst_attr "mask_operand10" "mask" "" "%{%11%}%N10")
  51 (define_subst_attr "mask_operand11" "mask" "" "%{%12%}%N11")
  52 (define_subst_attr "mask_operand18" "mask" "" "%{%19%}%N18")
  53 (define_subst_attr "mask_operand19" "mask" "" "%{%20%}%N19")
  54 (define_subst_attr "mask_codefor" "mask" "*" "")
  55 (define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]")
  56 (define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
  57 (define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
  58 (define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW")
  59 (define_subst_attr "mask_avx512dq_condition" "mask" "1" "TARGET_AVX512DQ")
  60 (define_subst_attr "mask_prefix" "mask" "vex" "evex")
  61 (define_subst_attr "mask_prefix2" "mask" "maybe_vex" "evex")
  62 (define_subst_attr "mask_prefix3" "mask" "orig,vex" "evex,evex")
  63 (define_subst_attr "bcst_mask_prefix3" "mask" "orig,maybe_evex" "evex,evex")
  64 (define_subst_attr "mask_prefix4" "mask" "orig,orig,vex" "evex,evex,evex")
  65 (define_subst_attr "bcst_mask_prefix4" "mask" "orig,orig,maybe_evex" "evex,evex,evex")
  66 (define_subst_attr "mask_expand_op3" "mask" "3" "5")
  67
  68 (define_subst "mask"
  69   [(set (match_operand:SUBST_V 0)
  70         (match_operand:SUBST_V 1))]
  71   "TARGET_AVX512F"
  72   [(set (match_dup 0)
  73         (vec_merge:SUBST_V
  74           (match_dup 1)
  75           (match_operand:SUBST_V 2 "nonimm_or_0_operand" "0C")
  76           (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))])
  77
  78 (define_subst_attr "merge_mask_name" "merge_mask" "" "_merge_mask")
  79 (define_subst_attr "merge_mask_operand3" "merge_mask" "" "%{%3%}")
  80 (define_subst "merge_mask"
  81   [(set (match_operand:SUBST_V 0)
  82         (match_operand:SUBST_V 1))]
  83   "TARGET_AVX512F"
  84   [(set (match_dup 0)
  85         (vec_merge:SUBST_V
  86           (match_dup 1)
  87           (match_dup 0)
  88           (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))])
  89
  90 (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
  91 (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}")
  92 (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}")
  93
  94 (define_subst "mask_scalar_merge"
  95   [(set (match_operand:SUBST_S 0)
  96         (match_operand:SUBST_S 1))]
  97   "TARGET_AVX512F"
  98   [(set (match_dup 0)
  99         (and:SUBST_S
 100           (match_dup 1)
 101           (match_operand:SUBST_S 3 "register_operand" "Yk")))])
 102
 103 (define_subst_attr "sd_maskz_name" "sd" "" "_maskz_1")
 104 (define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4")
 105 (define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5")
 106 (define_subst_attr "sd_mask_codefor" "sd" "*" "")
 107 (define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
 108
 109 (define_subst "sd"
 110  [(set (match_operand:SUBST_V 0)
 111        (match_operand:SUBST_V 1))]
 112  ""
 113  [(set (match_dup 0)
 114        (vec_merge:SUBST_V
 115          (match_dup 1)
 116          (match_operand:SUBST_V 2 "const0_operand" "C")
 117          (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))
 118 ])
 119
 120 (define_subst_attr "round_name" "round" "" "_round")
 121 (define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
 122 (define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
 123 (define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6")
 124 (define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6")
 125 (define_subst_attr "round_op2" "round" "" "%R2")
 126 (define_subst_attr "round_op3" "round" "" "%R3")
 127 (define_subst_attr "round_op4" "round" "" "%R4")
 128 (define_subst_attr "round_op5" "round" "" "%R5")
 129 (define_subst_attr "round_op6" "round" "" "%R6")
 130 (define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>")
 131 (define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>")
 132 (define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>")
 133 (define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
 134 (define_subst_attr "round_constraint" "round" "vm" "v")
 135 (define_subst_attr "bcst_round_constraint" "round" "vmBr" "v")
 136 (define_subst_attr "round_constraint2" "round" "m" "v")
 137 (define_subst_attr "round_constraint3" "round" "rm" "r")
 138 (define_subst_attr "round_nimm_predicate" "round" "vector_operand" "register_operand")
 139 (define_subst_attr "bcst_round_nimm_predicate" "round" "bcst_vector_operand" "register_operand")
 140 (define_subst_attr "round_nimm_scalar_predicate" "round" "nonimmediate_operand" "register_operand")
 141 (define_subst_attr "round_prefix" "round" "vex" "evex")
 142 (define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode
 143                                                               || <MODE>mode == V8DFmode
 144                                                               || <MODE>mode == V8DImode
 145                                                               || <MODE>mode == V16SImode)")
 146 (define_subst_attr "round_modev8sf_condition" "round" "1" "(<MODE>mode == V8SFmode)")
 147 (define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)")
 148 (define_subst_attr "round_codefor" "round" "*" "")
 149 (define_subst_attr "round_opnum" "round" "5" "6")
 150
 151 (define_subst "round"
 152   [(set (match_operand:SUBST_A 0)
 153         (match_operand:SUBST_A 1))]
 154   "TARGET_AVX512F"
 155   [(set (match_dup 0)
 156         (unspec:SUBST_A [(match_dup 1)
 157           (match_operand:SI 2 "const_4_or_8_to_11_operand")]
 158           UNSPEC_EMBEDDED_ROUNDING))
 159 ])
 160
 161 (define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round")
 162 (define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4")
 163 (define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
 164 (define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
 165 (define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
 166 (define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
 167 (define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
 168 (define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3")
 169 (define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%r4")
 170 (define_subst_attr "round_saeonly_op5" "round_saeonly" "" "%r5")
 171 (define_subst_attr "round_saeonly_op6" "round_saeonly" "" "%r6")
 172 (define_subst_attr "round_saeonly_prefix" "round_saeonly" "vex" "evex")
 173 (define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "<round_saeonly_mask_operand2>")
 174 (define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "<round_saeonly_mask_operand3>")
 175 (define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
 176 (define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
 177 (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
 178 (define_subst_attr "round_saeonly_mask_arg3" "round_saeonly" "" ", operands[<mask_expand_op3>]")
 179 (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
 180 (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
 181 (define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand")
 182 (define_subst_attr "round_saeonly_nimm_scalar_predicate" "round_saeonly" "nonimmediate_operand" "register_operand")
 183 (define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode
 184                                                                               || <MODE>mode == V8DFmode
 185                                                                               || <MODE>mode == V8DImode
 186                                                                               || <MODE>mode == V16SImode)")
 187 (define_subst_attr "round_saeonly_modev8sf_condition" "round_saeonly" "1" "(<MODE>mode == V8SFmode)")
 188
 189 (define_subst "round_saeonly"
 190   [(set (match_operand:SUBST_A 0)
 191         (match_operand:SUBST_A 1))]
 192   "TARGET_AVX512F"
 193   [(set (match_dup 0)
 194         (unspec:SUBST_A [(match_dup 1)
 195           (match_operand:SI 2 "const48_operand")]
 196           UNSPEC_EMBEDDED_ROUNDING))
 197 ])
 198
 199 (define_subst "round_saeonly"
 200   [(set (match_operand:CCFP 0)
 201         (match_operand:CCFP 1))]
 202   "TARGET_AVX512F"
 203   [(set (match_dup 0)
 204         (unspec:CCFP [(match_dup 1)
 205           (match_operand:SI 2 "const48_operand")]
 206           UNSPEC_EMBEDDED_ROUNDING))
 207 ])
 208
 209 (define_subst_attr "round_expand_name" "round_expand" "" "_round")
 210 (define_subst_attr "round_expand_nimm_predicate" "round_expand" "nonimmediate_operand" "register_operand")
 211 (define_subst_attr "round_expand_operand" "round_expand" "" ", operands[5]")
 212
 213 (define_subst "round_expand"
 214  [(match_operand:SUBST_V 0)
 215   (match_operand:SUBST_V 1)
 216   (match_operand:SUBST_V 2)
 217   (match_operand:SUBST_V 3)
 218   (match_operand:SUBST_S 4)]
 219   "TARGET_AVX512F"
 220   [(match_dup 0)
 221    (match_dup 1)
 222    (match_dup 2)
 223    (match_dup 3)
 224    (match_dup 4)
 225    (unspec [(match_operand:SI 5 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)])
 226
 227 (define_subst_attr "round_saeonly_expand_name" "round_saeonly_expand" "" "_round")
 228 (define_subst_attr "round_saeonly_expand_nimm_predicate" "round_saeonly_expand" "nonimmediate_operand" "register_operand")
 229 (define_subst_attr "round_saeonly_expand_operand6" "round_saeonly_expand" "" ", operands[6]")
 230
 231 (define_subst "round_saeonly_expand"
 232  [(match_operand:SUBST_V 0)
 233   (match_operand:SUBST_V 1)
 234   (match_operand:SUBST_V 2)
 235   (match_operand:SUBST_A 3)
 236   (match_operand:SI 4)
 237   (match_operand:SUBST_S 5)]
 238   "TARGET_AVX512F"
 239   [(match_dup 0)
 240    (match_dup 1)
 241    (match_dup 2)
 242    (match_dup 3)
 243    (match_dup 4)
 244    (match_dup 5)
 245    (unspec [(match_operand:SI 6 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])
 246
 247 (define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
 248 (define_subst_attr "mask_expand4_args" "mask_expand4" "" ", operands[4], operands[5]")
 249
 250 (define_subst "mask_expand4"
 251   [(match_operand:SUBST_V 0)
 252    (match_operand:SUBST_V 1)
 253    (match_operand:SUBST_V 2)
 254    (match_operand:SI 3)]
 255    "TARGET_AVX512VL"
 256    [(match_dup 0)
 257     (match_dup 1)
 258     (match_dup 2)
 259     (match_dup 3)
 260     (match_operand:SUBST_V 4 "nonimm_or_0_operand")
 261     (match_operand:<avx512fmaskmode> 5 "register_operand")])
 262
 263 (define_subst_attr "mask_scalar_name" "mask_scalar" "" "_mask")
 264 (define_subst_attr "mask_scalar_operand3" "mask_scalar" "" "%{%4%}%N3")
 265 (define_subst_attr "mask_scalar_operand4" "mask_scalar" "" "%{%5%}%N4")
 266
 267 (define_subst "mask_scalar"
 268   [(set (match_operand:SUBST_V 0)
 269         (vec_merge:SUBST_V
 270           (match_operand:SUBST_V 1)
 271           (match_operand:SUBST_V 2)
 272           (const_int 1)))]
 273   "TARGET_AVX512F"
 274   [(set (match_dup 0)
 275         (vec_merge:SUBST_V
 276           (vec_merge:SUBST_V
 277             (match_dup 1)
 278             (match_operand:SUBST_V 3 "nonimm_or_0_operand" "0C")
 279             (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
 280           (match_dup 2)
 281           (const_int 1)))])
 282
 283 (define_subst_attr "round_scalar_name" "round_scalar" "" "_round")
 284 (define_subst_attr "round_scalar_mask_operand3" "mask_scalar" "%R3" "%R5")
 285 (define_subst_attr "round_scalar_mask_op3" "round_scalar" "" "<round_scalar_mask_operand3>")
 286 (define_subst_attr "round_scalar_constraint" "round_scalar" "vm" "v")
 287 (define_subst_attr "round_scalar_prefix" "round_scalar" "vex" "evex")
 288 (define_subst_attr "round_scalar_nimm_predicate" "round_scalar" "nonimmediate_operand" "register_operand")
 289
 290 (define_subst "round_scalar"
 291   [(set (match_operand:SUBST_V 0)
 292         (vec_merge:SUBST_V
 293           (match_operand:SUBST_V 1)
 294           (match_operand:SUBST_V 2)
 295           (const_int 1)))]
 296   "TARGET_AVX512F"
 297   [(set (match_dup 0)
 298         (unspec:SUBST_V [
 299              (vec_merge:SUBST_V
 300                 (match_dup 1)
 301                 (match_dup 2)
 302                 (const_int 1))
 303              (match_operand:SI 3 "const_4_or_8_to_11_operand")]
 304                 UNSPEC_EMBEDDED_ROUNDING))])
 305
 306 (define_subst_attr "round_saeonly_scalar_name" "round_saeonly_scalar" "" "_round")
 307 (define_subst_attr "round_saeonly_scalar_mask_operand3" "mask_scalar" "%r3" "%r5")
 308 (define_subst_attr "round_saeonly_scalar_mask_operand4" "mask_scalar" "%r4" "%r6")
 309 (define_subst_attr "round_saeonly_scalar_mask_op3" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand3>")
 310 (define_subst_attr "round_saeonly_scalar_mask_op4" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand4>")
 311 (define_subst_attr "round_saeonly_scalar_constraint" "round_saeonly_scalar" "vm" "v")
 312 (define_subst_attr "round_saeonly_scalar_prefix" "round_saeonly_scalar" "vex" "evex")
 313 (define_subst_attr "round_saeonly_scalar_nimm_predicate" "round_saeonly_scalar" "nonimmediate_operand" "register_operand")
 314
 315 (define_subst "round_saeonly_scalar"
 316   [(set (match_operand:SUBST_V 0)
 317         (vec_merge:SUBST_V
 318           (match_operand:SUBST_V 1)
 319           (match_operand:SUBST_V 2)
 320           (const_int 1)))]
 321   "TARGET_AVX512F"
 322   [(set (match_dup 0)
 323         (unspec:SUBST_V [
 324              (vec_merge:SUBST_V
 325                 (match_dup 1)
 326                 (match_dup 2)
 327                 (const_int 1))
 328              (match_operand:SI 3 "const48_operand")]
 329                 UNSPEC_EMBEDDED_ROUNDING))])
 330
 331 (define_subst_attr "maskz_half_name" "maskz_half" "" "_maskz_1")
 332 (define_subst_attr "maskz_half_operand4" "maskz_half" "" "%{%5%}%N4")
 333
 334 (define_subst "maskz_half"
 335   [(set (match_operand:SUBST_V 0)
 336         (match_operand:SUBST_V 1))]
 337   ""
 338   [(set (match_dup 0)
 339         (vec_merge:SUBST_V
 340           (match_dup 1)
 341           (match_operand:SUBST_V 2 "const0_operand" "C")
 342           (match_operand:<avx512fmaskhalfmode> 3 "register_operand" "Yk")))])