1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "diagnostic-core.h"
27 /* Include insn-config.h before expr.h so that HAVE_conditional_move
28 is properly defined. */
29 #include "insn-config.h"
32 #include "stor-layout.h"
33 #include "stringpool.h"
45 #include "basic-block.h"
48 struct target_optabs default_target_optabs
;
49 struct target_libfuncs default_target_libfuncs
;
50 struct target_optabs
*this_fn_optabs
= &default_target_optabs
;
52 struct target_optabs
*this_target_optabs
= &default_target_optabs
;
53 struct target_libfuncs
*this_target_libfuncs
= &default_target_libfuncs
;
56 #define libfunc_hash \
57 (this_target_libfuncs->x_libfunc_hash)
59 static void prepare_float_lib_cmp (rtx
, rtx
, enum rtx_code
, rtx
*,
61 static rtx
expand_unop_direct (enum machine_mode
, optab
, rtx
, rtx
, int);
62 static void emit_libcall_block_1 (rtx_insn
*, rtx
, rtx
, rtx
, bool);
64 /* Debug facility for use in GDB. */
65 void debug_optab_libfuncs (void);
67 /* Prefixes for the current version of decimal floating point (BID vs. DPD) */
68 #if ENABLE_DECIMAL_BID_FORMAT
69 #define DECIMAL_PREFIX "bid_"
71 #define DECIMAL_PREFIX "dpd_"
74 /* Used for libfunc_hash. */
77 hash_libfunc (const void *p
)
79 const struct libfunc_entry
*const e
= (const struct libfunc_entry
*) p
;
80 return ((e
->mode1
+ e
->mode2
* NUM_MACHINE_MODES
) ^ e
->op
);
83 /* Used for libfunc_hash. */
86 eq_libfunc (const void *p
, const void *q
)
88 const struct libfunc_entry
*const e1
= (const struct libfunc_entry
*) p
;
89 const struct libfunc_entry
*const e2
= (const struct libfunc_entry
*) q
;
90 return e1
->op
== e2
->op
&& e1
->mode1
== e2
->mode1
&& e1
->mode2
== e2
->mode2
;
93 /* Return libfunc corresponding operation defined by OPTAB converting
94 from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL
95 if no libfunc is available. */
97 convert_optab_libfunc (convert_optab optab
, enum machine_mode mode1
,
98 enum machine_mode mode2
)
100 struct libfunc_entry e
;
101 struct libfunc_entry
**slot
;
103 /* ??? This ought to be an assert, but not all of the places
104 that we expand optabs know about the optabs that got moved
106 if (!(optab
>= FIRST_CONV_OPTAB
&& optab
<= LAST_CONVLIB_OPTAB
))
112 slot
= (struct libfunc_entry
**)
113 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
116 const struct convert_optab_libcall_d
*d
117 = &convlib_def
[optab
- FIRST_CONV_OPTAB
];
119 if (d
->libcall_gen
== NULL
)
122 d
->libcall_gen (optab
, d
->libcall_basename
, mode1
, mode2
);
123 slot
= (struct libfunc_entry
**)
124 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
128 return (*slot
)->libfunc
;
131 /* Return libfunc corresponding operation defined by OPTAB in MODE.
132 Trigger lazy initialization if needed, return NULL if no libfunc is
135 optab_libfunc (optab optab
, enum machine_mode mode
)
137 struct libfunc_entry e
;
138 struct libfunc_entry
**slot
;
140 /* ??? This ought to be an assert, but not all of the places
141 that we expand optabs know about the optabs that got moved
143 if (!(optab
>= FIRST_NORM_OPTAB
&& optab
<= LAST_NORMLIB_OPTAB
))
149 slot
= (struct libfunc_entry
**)
150 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
153 const struct optab_libcall_d
*d
154 = &normlib_def
[optab
- FIRST_NORM_OPTAB
];
156 if (d
->libcall_gen
== NULL
)
159 d
->libcall_gen (optab
, d
->libcall_basename
, d
->libcall_suffix
, mode
);
160 slot
= (struct libfunc_entry
**)
161 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
165 return (*slot
)->libfunc
;
169 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
170 the result of operation CODE applied to OP0 (and OP1 if it is a binary
173 If the last insn does not set TARGET, don't do anything, but return 1.
175 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
176 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
177 try again, ensuring that TARGET is not one of the operands. */
180 add_equal_note (rtx insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
185 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
187 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
188 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
189 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
190 && GET_RTX_CLASS (code
) != RTX_COMPARE
191 && GET_RTX_CLASS (code
) != RTX_UNARY
)
194 if (GET_CODE (target
) == ZERO_EXTRACT
)
197 for (last_insn
= insns
;
198 NEXT_INSN (last_insn
) != NULL_RTX
;
199 last_insn
= NEXT_INSN (last_insn
))
202 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
203 a value changing in the insn, so the note would be invalid for CSE. */
204 if (reg_overlap_mentioned_p (target
, op0
)
205 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
208 && (rtx_equal_p (target
, op0
)
209 || (op1
&& rtx_equal_p (target
, op1
))))
211 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
212 over expanding it as temp = MEM op X, MEM = temp. If the target
213 supports MEM = MEM op X instructions, it is sometimes too hard
214 to reconstruct that form later, especially if X is also a memory,
215 and due to multiple occurrences of addresses the address might
216 be forced into register unnecessarily.
217 Note that not emitting the REG_EQUIV note might inhibit
218 CSE in some cases. */
219 set
= single_set (last_insn
);
221 && GET_CODE (SET_SRC (set
)) == code
222 && MEM_P (SET_DEST (set
))
223 && (rtx_equal_p (SET_DEST (set
), XEXP (SET_SRC (set
), 0))
224 || (op1
&& rtx_equal_p (SET_DEST (set
),
225 XEXP (SET_SRC (set
), 1)))))
231 set
= set_for_reg_notes (last_insn
);
235 if (! rtx_equal_p (SET_DEST (set
), target
)
236 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
237 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
238 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
241 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
251 if (GET_MODE (op0
) != VOIDmode
&& GET_MODE (target
) != GET_MODE (op0
))
253 note
= gen_rtx_fmt_e (code
, GET_MODE (op0
), copy_rtx (op0
));
254 if (GET_MODE_SIZE (GET_MODE (op0
))
255 > GET_MODE_SIZE (GET_MODE (target
)))
256 note
= simplify_gen_unary (TRUNCATE
, GET_MODE (target
),
257 note
, GET_MODE (op0
));
259 note
= simplify_gen_unary (ZERO_EXTEND
, GET_MODE (target
),
260 note
, GET_MODE (op0
));
265 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
269 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
271 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
276 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
277 for a widening operation would be. In most cases this would be OP0, but if
278 that's a constant it'll be VOIDmode, which isn't useful. */
280 static enum machine_mode
281 widened_mode (enum machine_mode to_mode
, rtx op0
, rtx op1
)
283 enum machine_mode m0
= GET_MODE (op0
);
284 enum machine_mode m1
= GET_MODE (op1
);
285 enum machine_mode result
;
287 if (m0
== VOIDmode
&& m1
== VOIDmode
)
289 else if (m0
== VOIDmode
|| GET_MODE_SIZE (m0
) < GET_MODE_SIZE (m1
))
294 if (GET_MODE_SIZE (result
) > GET_MODE_SIZE (to_mode
))
300 /* Like optab_handler, but for widening_operations that have a
301 TO_MODE and a FROM_MODE. */
304 widening_optab_handler (optab op
, enum machine_mode to_mode
,
305 enum machine_mode from_mode
)
307 unsigned scode
= (op
<< 16) | to_mode
;
308 if (to_mode
!= from_mode
&& from_mode
!= VOIDmode
)
310 /* ??? Why does find_widening_optab_handler_and_mode attempt to
311 widen things that can't be widened? E.g. add_optab... */
312 if (op
> LAST_CONV_OPTAB
)
313 return CODE_FOR_nothing
;
314 scode
|= from_mode
<< 8;
316 return raw_optab_handler (scode
);
319 /* Find a widening optab even if it doesn't widen as much as we want.
320 E.g. if from_mode is HImode, and to_mode is DImode, and there is no
321 direct HI->SI insn, then return SI->DI, if that exists.
322 If PERMIT_NON_WIDENING is non-zero then this can be used with
323 non-widening optabs also. */
326 find_widening_optab_handler_and_mode (optab op
, enum machine_mode to_mode
,
327 enum machine_mode from_mode
,
328 int permit_non_widening
,
329 enum machine_mode
*found_mode
)
331 for (; (permit_non_widening
|| from_mode
!= to_mode
)
332 && GET_MODE_SIZE (from_mode
) <= GET_MODE_SIZE (to_mode
)
333 && from_mode
!= VOIDmode
;
334 from_mode
= GET_MODE_WIDER_MODE (from_mode
))
336 enum insn_code handler
= widening_optab_handler (op
, to_mode
,
339 if (handler
!= CODE_FOR_nothing
)
342 *found_mode
= from_mode
;
347 return CODE_FOR_nothing
;
350 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
351 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
352 not actually do a sign-extend or zero-extend, but can leave the
353 higher-order bits of the result rtx undefined, for example, in the case
354 of logical operations, but not right shifts. */
357 widen_operand (rtx op
, enum machine_mode mode
, enum machine_mode oldmode
,
358 int unsignedp
, int no_extend
)
362 /* If we don't have to extend and this is a constant, return it. */
363 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
366 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
367 extend since it will be more efficient to do so unless the signedness of
368 a promoted object differs from our extension. */
370 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
371 && SUBREG_CHECK_PROMOTED_SIGN (op
, unsignedp
)))
372 return convert_modes (mode
, oldmode
, op
, unsignedp
);
374 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
376 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
377 return gen_lowpart (mode
, force_reg (GET_MODE (op
), op
));
379 /* Otherwise, get an object of MODE, clobber it, and set the low-order
382 result
= gen_reg_rtx (mode
);
383 emit_clobber (result
);
384 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
388 /* Return the optab used for computing the operation given by the tree code,
389 CODE and the tree EXP. This function is not always usable (for example, it
390 cannot give complete results for multiplication or division) but probably
391 ought to be relied on more widely throughout the expander. */
393 optab_for_tree_code (enum tree_code code
, const_tree type
,
394 enum optab_subtype subtype
)
406 return one_cmpl_optab
;
411 case MULT_HIGHPART_EXPR
:
412 return TYPE_UNSIGNED (type
) ? umul_highpart_optab
: smul_highpart_optab
;
418 return TYPE_UNSIGNED (type
) ? umod_optab
: smod_optab
;
426 if (TYPE_SATURATING (type
))
427 return TYPE_UNSIGNED (type
) ? usdiv_optab
: ssdiv_optab
;
428 return TYPE_UNSIGNED (type
) ? udiv_optab
: sdiv_optab
;
431 if (TREE_CODE (type
) == VECTOR_TYPE
)
433 if (subtype
== optab_vector
)
434 return TYPE_SATURATING (type
) ? unknown_optab
: vashl_optab
;
436 gcc_assert (subtype
== optab_scalar
);
438 if (TYPE_SATURATING (type
))
439 return TYPE_UNSIGNED (type
) ? usashl_optab
: ssashl_optab
;
443 if (TREE_CODE (type
) == VECTOR_TYPE
)
445 if (subtype
== optab_vector
)
446 return TYPE_UNSIGNED (type
) ? vlshr_optab
: vashr_optab
;
448 gcc_assert (subtype
== optab_scalar
);
450 return TYPE_UNSIGNED (type
) ? lshr_optab
: ashr_optab
;
453 if (TREE_CODE (type
) == VECTOR_TYPE
)
455 if (subtype
== optab_vector
)
458 gcc_assert (subtype
== optab_scalar
);
463 if (TREE_CODE (type
) == VECTOR_TYPE
)
465 if (subtype
== optab_vector
)
468 gcc_assert (subtype
== optab_scalar
);
473 return TYPE_UNSIGNED (type
) ? umax_optab
: smax_optab
;
476 return TYPE_UNSIGNED (type
) ? umin_optab
: smin_optab
;
478 case REALIGN_LOAD_EXPR
:
479 return vec_realign_load_optab
;
482 return TYPE_UNSIGNED (type
) ? usum_widen_optab
: ssum_widen_optab
;
485 return TYPE_UNSIGNED (type
) ? udot_prod_optab
: sdot_prod_optab
;
488 return TYPE_UNSIGNED (type
) ? usad_optab
: ssad_optab
;
490 case WIDEN_MULT_PLUS_EXPR
:
491 return (TYPE_UNSIGNED (type
)
492 ? (TYPE_SATURATING (type
)
493 ? usmadd_widen_optab
: umadd_widen_optab
)
494 : (TYPE_SATURATING (type
)
495 ? ssmadd_widen_optab
: smadd_widen_optab
));
497 case WIDEN_MULT_MINUS_EXPR
:
498 return (TYPE_UNSIGNED (type
)
499 ? (TYPE_SATURATING (type
)
500 ? usmsub_widen_optab
: umsub_widen_optab
)
501 : (TYPE_SATURATING (type
)
502 ? ssmsub_widen_optab
: smsub_widen_optab
));
508 return TYPE_UNSIGNED (type
) ? reduc_umax_optab
: reduc_smax_optab
;
511 return TYPE_UNSIGNED (type
) ? reduc_umin_optab
: reduc_smin_optab
;
513 case REDUC_PLUS_EXPR
:
514 return TYPE_UNSIGNED (type
) ? reduc_uplus_optab
: reduc_splus_optab
;
516 case VEC_LSHIFT_EXPR
:
517 return vec_shl_optab
;
519 case VEC_RSHIFT_EXPR
:
520 return vec_shr_optab
;
522 case VEC_WIDEN_MULT_HI_EXPR
:
523 return TYPE_UNSIGNED (type
) ?
524 vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
526 case VEC_WIDEN_MULT_LO_EXPR
:
527 return TYPE_UNSIGNED (type
) ?
528 vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
530 case VEC_WIDEN_MULT_EVEN_EXPR
:
531 return TYPE_UNSIGNED (type
) ?
532 vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
534 case VEC_WIDEN_MULT_ODD_EXPR
:
535 return TYPE_UNSIGNED (type
) ?
536 vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
538 case VEC_WIDEN_LSHIFT_HI_EXPR
:
539 return TYPE_UNSIGNED (type
) ?
540 vec_widen_ushiftl_hi_optab
: vec_widen_sshiftl_hi_optab
;
542 case VEC_WIDEN_LSHIFT_LO_EXPR
:
543 return TYPE_UNSIGNED (type
) ?
544 vec_widen_ushiftl_lo_optab
: vec_widen_sshiftl_lo_optab
;
546 case VEC_UNPACK_HI_EXPR
:
547 return TYPE_UNSIGNED (type
) ?
548 vec_unpacku_hi_optab
: vec_unpacks_hi_optab
;
550 case VEC_UNPACK_LO_EXPR
:
551 return TYPE_UNSIGNED (type
) ?
552 vec_unpacku_lo_optab
: vec_unpacks_lo_optab
;
554 case VEC_UNPACK_FLOAT_HI_EXPR
:
555 /* The signedness is determined from input operand. */
556 return TYPE_UNSIGNED (type
) ?
557 vec_unpacku_float_hi_optab
: vec_unpacks_float_hi_optab
;
559 case VEC_UNPACK_FLOAT_LO_EXPR
:
560 /* The signedness is determined from input operand. */
561 return TYPE_UNSIGNED (type
) ?
562 vec_unpacku_float_lo_optab
: vec_unpacks_float_lo_optab
;
564 case VEC_PACK_TRUNC_EXPR
:
565 return vec_pack_trunc_optab
;
567 case VEC_PACK_SAT_EXPR
:
568 return TYPE_UNSIGNED (type
) ? vec_pack_usat_optab
: vec_pack_ssat_optab
;
570 case VEC_PACK_FIX_TRUNC_EXPR
:
571 /* The signedness is determined from output operand. */
572 return TYPE_UNSIGNED (type
) ?
573 vec_pack_ufix_trunc_optab
: vec_pack_sfix_trunc_optab
;
579 trapv
= INTEGRAL_TYPE_P (type
) && TYPE_OVERFLOW_TRAPS (type
);
582 case POINTER_PLUS_EXPR
:
584 if (TYPE_SATURATING (type
))
585 return TYPE_UNSIGNED (type
) ? usadd_optab
: ssadd_optab
;
586 return trapv
? addv_optab
: add_optab
;
589 if (TYPE_SATURATING (type
))
590 return TYPE_UNSIGNED (type
) ? ussub_optab
: sssub_optab
;
591 return trapv
? subv_optab
: sub_optab
;
594 if (TYPE_SATURATING (type
))
595 return TYPE_UNSIGNED (type
) ? usmul_optab
: ssmul_optab
;
596 return trapv
? smulv_optab
: smul_optab
;
599 if (TYPE_SATURATING (type
))
600 return TYPE_UNSIGNED (type
) ? usneg_optab
: ssneg_optab
;
601 return trapv
? negv_optab
: neg_optab
;
604 return trapv
? absv_optab
: abs_optab
;
607 return unknown_optab
;
612 /* Expand vector widening operations.
614 There are two different classes of operations handled here:
615 1) Operations whose result is wider than all the arguments to the operation.
616 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
617 In this case OP0 and optionally OP1 would be initialized,
618 but WIDE_OP wouldn't (not relevant for this case).
619 2) Operations whose result is of the same size as the last argument to the
620 operation, but wider than all the other arguments to the operation.
621 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
622 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
624 E.g, when called to expand the following operations, this is how
625 the arguments will be initialized:
627 widening-sum 2 oprnd0 - oprnd1
628 widening-dot-product 3 oprnd0 oprnd1 oprnd2
629 widening-mult 2 oprnd0 oprnd1 -
630 type-promotion (vec-unpack) 1 oprnd0 - - */
633 expand_widen_pattern_expr (sepops ops
, rtx op0
, rtx op1
, rtx wide_op
,
634 rtx target
, int unsignedp
)
636 struct expand_operand eops
[4];
637 tree oprnd0
, oprnd1
, oprnd2
;
638 enum machine_mode wmode
= VOIDmode
, tmode0
, tmode1
= VOIDmode
;
639 optab widen_pattern_optab
;
640 enum insn_code icode
;
641 int nops
= TREE_CODE_LENGTH (ops
->code
);
645 tmode0
= TYPE_MODE (TREE_TYPE (oprnd0
));
646 widen_pattern_optab
=
647 optab_for_tree_code (ops
->code
, TREE_TYPE (oprnd0
), optab_default
);
648 if (ops
->code
== WIDEN_MULT_PLUS_EXPR
649 || ops
->code
== WIDEN_MULT_MINUS_EXPR
)
650 icode
= find_widening_optab_handler (widen_pattern_optab
,
651 TYPE_MODE (TREE_TYPE (ops
->op2
)),
654 icode
= optab_handler (widen_pattern_optab
, tmode0
);
655 gcc_assert (icode
!= CODE_FOR_nothing
);
660 tmode1
= TYPE_MODE (TREE_TYPE (oprnd1
));
663 /* The last operand is of a wider mode than the rest of the operands. */
668 gcc_assert (tmode1
== tmode0
);
671 wmode
= TYPE_MODE (TREE_TYPE (oprnd2
));
675 create_output_operand (&eops
[op
++], target
, TYPE_MODE (ops
->type
));
676 create_convert_operand_from (&eops
[op
++], op0
, tmode0
, unsignedp
);
678 create_convert_operand_from (&eops
[op
++], op1
, tmode1
, unsignedp
);
680 create_convert_operand_from (&eops
[op
++], wide_op
, wmode
, unsignedp
);
681 expand_insn (icode
, op
, eops
);
682 return eops
[0].value
;
685 /* Generate code to perform an operation specified by TERNARY_OPTAB
686 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
688 UNSIGNEDP is for the case where we have to widen the operands
689 to perform the operation. It says to use zero-extension.
691 If TARGET is nonzero, the value
692 is generated there, if it is convenient to do so.
693 In all cases an rtx is returned for the locus of the value;
694 this may or may not be TARGET. */
697 expand_ternary_op (enum machine_mode mode
, optab ternary_optab
, rtx op0
,
698 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
700 struct expand_operand ops
[4];
701 enum insn_code icode
= optab_handler (ternary_optab
, mode
);
703 gcc_assert (optab_handler (ternary_optab
, mode
) != CODE_FOR_nothing
);
705 create_output_operand (&ops
[0], target
, mode
);
706 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
707 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
708 create_convert_operand_from (&ops
[3], op2
, mode
, unsignedp
);
709 expand_insn (icode
, 4, ops
);
714 /* Like expand_binop, but return a constant rtx if the result can be
715 calculated at compile time. The arguments and return value are
716 otherwise the same as for expand_binop. */
719 simplify_expand_binop (enum machine_mode mode
, optab binoptab
,
720 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
721 enum optab_methods methods
)
723 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
725 rtx x
= simplify_binary_operation (optab_to_code (binoptab
),
731 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
734 /* Like simplify_expand_binop, but always put the result in TARGET.
735 Return true if the expansion succeeded. */
738 force_expand_binop (enum machine_mode mode
, optab binoptab
,
739 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
740 enum optab_methods methods
)
742 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
743 target
, unsignedp
, methods
);
747 emit_move_insn (target
, x
);
751 /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */
754 expand_vec_shift_expr (sepops ops
, rtx target
)
756 struct expand_operand eops
[3];
757 enum insn_code icode
;
758 rtx rtx_op1
, rtx_op2
;
759 enum machine_mode mode
= TYPE_MODE (ops
->type
);
760 tree vec_oprnd
= ops
->op0
;
761 tree shift_oprnd
= ops
->op1
;
766 case VEC_RSHIFT_EXPR
:
767 shift_optab
= vec_shr_optab
;
769 case VEC_LSHIFT_EXPR
:
770 shift_optab
= vec_shl_optab
;
776 icode
= optab_handler (shift_optab
, mode
);
777 gcc_assert (icode
!= CODE_FOR_nothing
);
779 rtx_op1
= expand_normal (vec_oprnd
);
780 rtx_op2
= expand_normal (shift_oprnd
);
782 create_output_operand (&eops
[0], target
, mode
);
783 create_input_operand (&eops
[1], rtx_op1
, GET_MODE (rtx_op1
));
784 create_convert_operand_from_type (&eops
[2], rtx_op2
, TREE_TYPE (shift_oprnd
));
785 expand_insn (icode
, 3, eops
);
787 return eops
[0].value
;
790 /* Create a new vector value in VMODE with all elements set to OP. The
791 mode of OP must be the element mode of VMODE. If OP is a constant,
792 then the return value will be a constant. */
795 expand_vector_broadcast (enum machine_mode vmode
, rtx op
)
797 enum insn_code icode
;
802 gcc_checking_assert (VECTOR_MODE_P (vmode
));
804 n
= GET_MODE_NUNITS (vmode
);
805 vec
= rtvec_alloc (n
);
806 for (i
= 0; i
< n
; ++i
)
807 RTVEC_ELT (vec
, i
) = op
;
810 return gen_rtx_CONST_VECTOR (vmode
, vec
);
812 /* ??? If the target doesn't have a vec_init, then we have no easy way
813 of performing this operation. Most of this sort of generic support
814 is hidden away in the vector lowering support in gimple. */
815 icode
= optab_handler (vec_init_optab
, vmode
);
816 if (icode
== CODE_FOR_nothing
)
819 ret
= gen_reg_rtx (vmode
);
820 emit_insn (GEN_FCN (icode
) (ret
, gen_rtx_PARALLEL (vmode
, vec
)));
825 /* This subroutine of expand_doubleword_shift handles the cases in which
826 the effective shift value is >= BITS_PER_WORD. The arguments and return
827 value are the same as for the parent routine, except that SUPERWORD_OP1
828 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
829 INTO_TARGET may be null if the caller has decided to calculate it. */
832 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
833 rtx outof_target
, rtx into_target
,
834 int unsignedp
, enum optab_methods methods
)
836 if (into_target
!= 0)
837 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
838 into_target
, unsignedp
, methods
))
841 if (outof_target
!= 0)
843 /* For a signed right shift, we must fill OUTOF_TARGET with copies
844 of the sign bit, otherwise we must fill it with zeros. */
845 if (binoptab
!= ashr_optab
)
846 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
848 if (!force_expand_binop (word_mode
, binoptab
,
849 outof_input
, GEN_INT (BITS_PER_WORD
- 1),
850 outof_target
, unsignedp
, methods
))
856 /* This subroutine of expand_doubleword_shift handles the cases in which
857 the effective shift value is < BITS_PER_WORD. The arguments and return
858 value are the same as for the parent routine. */
861 expand_subword_shift (enum machine_mode op1_mode
, optab binoptab
,
862 rtx outof_input
, rtx into_input
, rtx op1
,
863 rtx outof_target
, rtx into_target
,
864 int unsignedp
, enum optab_methods methods
,
865 unsigned HOST_WIDE_INT shift_mask
)
867 optab reverse_unsigned_shift
, unsigned_shift
;
870 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
871 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
873 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
874 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
875 the opposite direction to BINOPTAB. */
876 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
878 carries
= outof_input
;
879 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
,
880 op1_mode
), op1_mode
);
881 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
886 /* We must avoid shifting by BITS_PER_WORD bits since that is either
887 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
888 has unknown behavior. Do a single shift first, then shift by the
889 remainder. It's OK to use ~OP1 as the remainder if shift counts
890 are truncated to the mode size. */
891 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
892 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
893 if (shift_mask
== BITS_PER_WORD
- 1)
895 tmp
= immed_wide_int_const
896 (wi::minus_one (GET_MODE_PRECISION (op1_mode
)), op1_mode
);
897 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
902 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
- 1,
903 op1_mode
), op1_mode
);
904 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
908 if (tmp
== 0 || carries
== 0)
910 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
911 carries
, tmp
, 0, unsignedp
, methods
);
915 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
916 so the result can go directly into INTO_TARGET if convenient. */
917 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
918 into_target
, unsignedp
, methods
);
922 /* Now OR in the bits carried over from OUTOF_INPUT. */
923 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
924 into_target
, unsignedp
, methods
))
927 /* Use a standard word_mode shift for the out-of half. */
928 if (outof_target
!= 0)
929 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
930 outof_target
, unsignedp
, methods
))
937 #ifdef HAVE_conditional_move
938 /* Try implementing expand_doubleword_shift using conditional moves.
939 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
940 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
941 are the shift counts to use in the former and latter case. All other
942 arguments are the same as the parent routine. */
945 expand_doubleword_shift_condmove (enum machine_mode op1_mode
, optab binoptab
,
946 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
947 rtx outof_input
, rtx into_input
,
948 rtx subword_op1
, rtx superword_op1
,
949 rtx outof_target
, rtx into_target
,
950 int unsignedp
, enum optab_methods methods
,
951 unsigned HOST_WIDE_INT shift_mask
)
953 rtx outof_superword
, into_superword
;
955 /* Put the superword version of the output into OUTOF_SUPERWORD and
957 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
958 if (outof_target
!= 0 && subword_op1
== superword_op1
)
960 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
961 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
962 into_superword
= outof_target
;
963 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
964 outof_superword
, 0, unsignedp
, methods
))
969 into_superword
= gen_reg_rtx (word_mode
);
970 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
971 outof_superword
, into_superword
,
976 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
977 if (!expand_subword_shift (op1_mode
, binoptab
,
978 outof_input
, into_input
, subword_op1
,
979 outof_target
, into_target
,
980 unsignedp
, methods
, shift_mask
))
983 /* Select between them. Do the INTO half first because INTO_SUPERWORD
984 might be the current value of OUTOF_TARGET. */
985 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
986 into_target
, into_superword
, word_mode
, false))
989 if (outof_target
!= 0)
990 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
991 outof_target
, outof_superword
,
999 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
1000 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
1001 input operand; the shift moves bits in the direction OUTOF_INPUT->
1002 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
1003 of the target. OP1 is the shift count and OP1_MODE is its mode.
1004 If OP1 is constant, it will have been truncated as appropriate
1005 and is known to be nonzero.
1007 If SHIFT_MASK is zero, the result of word shifts is undefined when the
1008 shift count is outside the range [0, BITS_PER_WORD). This routine must
1009 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
1011 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
1012 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
1013 fill with zeros or sign bits as appropriate.
1015 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
1016 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
1017 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
1018 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
1021 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
1022 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
1023 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
1024 function wants to calculate it itself.
1026 Return true if the shift could be successfully synthesized. */
1029 expand_doubleword_shift (enum machine_mode op1_mode
, optab binoptab
,
1030 rtx outof_input
, rtx into_input
, rtx op1
,
1031 rtx outof_target
, rtx into_target
,
1032 int unsignedp
, enum optab_methods methods
,
1033 unsigned HOST_WIDE_INT shift_mask
)
1035 rtx superword_op1
, tmp
, cmp1
, cmp2
;
1036 rtx subword_label
, done_label
;
1037 enum rtx_code cmp_code
;
1039 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
1040 fill the result with sign or zero bits as appropriate. If so, the value
1041 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
1042 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
1043 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
1045 This isn't worthwhile for constant shifts since the optimizers will
1046 cope better with in-range shift counts. */
1047 if (shift_mask
>= BITS_PER_WORD
1048 && outof_target
!= 0
1049 && !CONSTANT_P (op1
))
1051 if (!expand_doubleword_shift (op1_mode
, binoptab
,
1052 outof_input
, into_input
, op1
,
1054 unsignedp
, methods
, shift_mask
))
1056 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
1057 outof_target
, unsignedp
, methods
))
1062 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
1063 is true when the effective shift value is less than BITS_PER_WORD.
1064 Set SUPERWORD_OP1 to the shift count that should be used to shift
1065 OUTOF_INPUT into INTO_TARGET when the condition is false. */
1066 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
, op1_mode
), op1_mode
);
1067 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
1069 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
1070 is a subword shift count. */
1071 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
1073 cmp2
= CONST0_RTX (op1_mode
);
1075 superword_op1
= op1
;
1079 /* Set CMP1 to OP1 - BITS_PER_WORD. */
1080 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
1082 cmp2
= CONST0_RTX (op1_mode
);
1084 superword_op1
= cmp1
;
1089 /* If we can compute the condition at compile time, pick the
1090 appropriate subroutine. */
1091 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
1092 if (tmp
!= 0 && CONST_INT_P (tmp
))
1094 if (tmp
== const0_rtx
)
1095 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1096 outof_target
, into_target
,
1097 unsignedp
, methods
);
1099 return expand_subword_shift (op1_mode
, binoptab
,
1100 outof_input
, into_input
, op1
,
1101 outof_target
, into_target
,
1102 unsignedp
, methods
, shift_mask
);
1105 #ifdef HAVE_conditional_move
1106 /* Try using conditional moves to generate straight-line code. */
1108 rtx_insn
*start
= get_last_insn ();
1109 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
1110 cmp_code
, cmp1
, cmp2
,
1111 outof_input
, into_input
,
1113 outof_target
, into_target
,
1114 unsignedp
, methods
, shift_mask
))
1116 delete_insns_since (start
);
1120 /* As a last resort, use branches to select the correct alternative. */
1121 subword_label
= gen_label_rtx ();
1122 done_label
= gen_label_rtx ();
1125 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
1126 0, 0, subword_label
, -1);
1129 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1130 outof_target
, into_target
,
1131 unsignedp
, methods
))
1134 emit_jump_insn (gen_jump (done_label
));
1136 emit_label (subword_label
);
1138 if (!expand_subword_shift (op1_mode
, binoptab
,
1139 outof_input
, into_input
, op1
,
1140 outof_target
, into_target
,
1141 unsignedp
, methods
, shift_mask
))
1144 emit_label (done_label
);
1148 /* Subroutine of expand_binop. Perform a double word multiplication of
1149 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
1150 as the target's word_mode. This function return NULL_RTX if anything
1151 goes wrong, in which case it may have already emitted instructions
1152 which need to be deleted.
1154 If we want to multiply two two-word values and have normal and widening
1155 multiplies of single-word values, we can do this with three smaller
1158 The multiplication proceeds as follows:
1159 _______________________
1160 [__op0_high_|__op0_low__]
1161 _______________________
1162 * [__op1_high_|__op1_low__]
1163 _______________________________________________
1164 _______________________
1165 (1) [__op0_low__*__op1_low__]
1166 _______________________
1167 (2a) [__op0_low__*__op1_high_]
1168 _______________________
1169 (2b) [__op0_high_*__op1_low__]
1170 _______________________
1171 (3) [__op0_high_*__op1_high_]
1174 This gives a 4-word result. Since we are only interested in the
1175 lower 2 words, partial result (3) and the upper words of (2a) and
1176 (2b) don't need to be calculated. Hence (2a) and (2b) can be
1177 calculated using non-widening multiplication.
1179 (1), however, needs to be calculated with an unsigned widening
1180 multiplication. If this operation is not directly supported we
1181 try using a signed widening multiplication and adjust the result.
1182 This adjustment works as follows:
1184 If both operands are positive then no adjustment is needed.
1186 If the operands have different signs, for example op0_low < 0 and
1187 op1_low >= 0, the instruction treats the most significant bit of
1188 op0_low as a sign bit instead of a bit with significance
1189 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
1190 with 2**BITS_PER_WORD - op0_low, and two's complements the
1191 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
1194 Similarly, if both operands are negative, we need to add
1195 (op0_low + op1_low) * 2**BITS_PER_WORD.
1197 We use a trick to adjust quickly. We logically shift op0_low right
1198 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
1199 op0_high (op1_high) before it is used to calculate 2b (2a). If no
1200 logical shift exists, we do an arithmetic right shift and subtract
1204 expand_doubleword_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
1205 bool umulp
, enum optab_methods methods
)
1207 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
1208 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
1209 rtx wordm1
= umulp
? NULL_RTX
: GEN_INT (BITS_PER_WORD
- 1);
1210 rtx product
, adjust
, product_high
, temp
;
1212 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
1213 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
1214 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
1215 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
1217 /* If we're using an unsigned multiply to directly compute the product
1218 of the low-order words of the operands and perform any required
1219 adjustments of the operands, we begin by trying two more multiplications
1220 and then computing the appropriate sum.
1222 We have checked above that the required addition is provided.
1223 Full-word addition will normally always succeed, especially if
1224 it is provided at all, so we don't worry about its failure. The
1225 multiplication may well fail, however, so we do handle that. */
1229 /* ??? This could be done with emit_store_flag where available. */
1230 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
1231 NULL_RTX
, 1, methods
);
1233 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
1234 NULL_RTX
, 0, OPTAB_DIRECT
);
1237 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
1238 NULL_RTX
, 0, methods
);
1241 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
1242 NULL_RTX
, 0, OPTAB_DIRECT
);
1249 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
1250 NULL_RTX
, 0, OPTAB_DIRECT
);
1254 /* OP0_HIGH should now be dead. */
1258 /* ??? This could be done with emit_store_flag where available. */
1259 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
1260 NULL_RTX
, 1, methods
);
1262 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
1263 NULL_RTX
, 0, OPTAB_DIRECT
);
1266 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
1267 NULL_RTX
, 0, methods
);
1270 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
1271 NULL_RTX
, 0, OPTAB_DIRECT
);
1278 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
1279 NULL_RTX
, 0, OPTAB_DIRECT
);
1283 /* OP1_HIGH should now be dead. */
1285 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
1286 NULL_RTX
, 0, OPTAB_DIRECT
);
1288 if (target
&& !REG_P (target
))
1292 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
1293 target
, 1, OPTAB_DIRECT
);
1295 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
1296 target
, 1, OPTAB_DIRECT
);
1301 product_high
= operand_subword (product
, high
, 1, mode
);
1302 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
1303 NULL_RTX
, 0, OPTAB_DIRECT
);
1304 emit_move_insn (product_high
, adjust
);
1308 /* Wrapper around expand_binop which takes an rtx code to specify
1309 the operation to perform, not an optab pointer. All other
1310 arguments are the same. */
1312 expand_simple_binop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
1313 rtx op1
, rtx target
, int unsignedp
,
1314 enum optab_methods methods
)
1316 optab binop
= code_to_optab (code
);
1319 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
1322 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1323 binop. Order them according to commutative_operand_precedence and, if
1324 possible, try to put TARGET or a pseudo first. */
1326 swap_commutative_operands_with_target (rtx target
, rtx op0
, rtx op1
)
1328 int op0_prec
= commutative_operand_precedence (op0
);
1329 int op1_prec
= commutative_operand_precedence (op1
);
1331 if (op0_prec
< op1_prec
)
1334 if (op0_prec
> op1_prec
)
1337 /* With equal precedence, both orders are ok, but it is better if the
1338 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1339 if (target
== 0 || REG_P (target
))
1340 return (REG_P (op1
) && !REG_P (op0
)) || target
== op1
;
1342 return rtx_equal_p (op1
, target
);
1345 /* Return true if BINOPTAB implements a shift operation. */
1348 shift_optab_p (optab binoptab
)
1350 switch (optab_to_code (binoptab
))
1366 /* Return true if BINOPTAB implements a commutative binary operation. */
1369 commutative_optab_p (optab binoptab
)
1371 return (GET_RTX_CLASS (optab_to_code (binoptab
)) == RTX_COMM_ARITH
1372 || binoptab
== smul_widen_optab
1373 || binoptab
== umul_widen_optab
1374 || binoptab
== smul_highpart_optab
1375 || binoptab
== umul_highpart_optab
);
1378 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1379 optimizing, and if the operand is a constant that costs more than
1380 1 instruction, force the constant into a register and return that
1381 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1384 avoid_expensive_constant (enum machine_mode mode
, optab binoptab
,
1385 int opn
, rtx x
, bool unsignedp
)
1387 bool speed
= optimize_insn_for_speed_p ();
1389 if (mode
!= VOIDmode
1392 && (rtx_cost (x
, optab_to_code (binoptab
), opn
, speed
)
1393 > set_src_cost (x
, speed
)))
1395 if (CONST_INT_P (x
))
1397 HOST_WIDE_INT intval
= trunc_int_for_mode (INTVAL (x
), mode
);
1398 if (intval
!= INTVAL (x
))
1399 x
= GEN_INT (intval
);
1402 x
= convert_modes (mode
, VOIDmode
, x
, unsignedp
);
1403 x
= force_reg (mode
, x
);
1408 /* Helper function for expand_binop: handle the case where there
1409 is an insn that directly implements the indicated operation.
1410 Returns null if this is not possible. */
1412 expand_binop_directly (enum machine_mode mode
, optab binoptab
,
1414 rtx target
, int unsignedp
, enum optab_methods methods
,
1417 enum machine_mode from_mode
= widened_mode (mode
, op0
, op1
);
1418 enum insn_code icode
= find_widening_optab_handler (binoptab
, mode
,
1420 enum machine_mode xmode0
= insn_data
[(int) icode
].operand
[1].mode
;
1421 enum machine_mode xmode1
= insn_data
[(int) icode
].operand
[2].mode
;
1422 enum machine_mode mode0
, mode1
, tmp_mode
;
1423 struct expand_operand ops
[3];
1426 rtx xop0
= op0
, xop1
= op1
;
1429 /* If it is a commutative operator and the modes would match
1430 if we would swap the operands, we can save the conversions. */
1431 commutative_p
= commutative_optab_p (binoptab
);
1433 && GET_MODE (xop0
) != xmode0
&& GET_MODE (xop1
) != xmode1
1434 && GET_MODE (xop0
) == xmode1
&& GET_MODE (xop1
) == xmode1
)
1441 /* If we are optimizing, force expensive constants into a register. */
1442 xop0
= avoid_expensive_constant (xmode0
, binoptab
, 0, xop0
, unsignedp
);
1443 if (!shift_optab_p (binoptab
))
1444 xop1
= avoid_expensive_constant (xmode1
, binoptab
, 1, xop1
, unsignedp
);
1446 /* In case the insn wants input operands in modes different from
1447 those of the actual operands, convert the operands. It would
1448 seem that we don't need to convert CONST_INTs, but we do, so
1449 that they're properly zero-extended, sign-extended or truncated
1452 mode0
= GET_MODE (xop0
) != VOIDmode
? GET_MODE (xop0
) : mode
;
1453 if (xmode0
!= VOIDmode
&& xmode0
!= mode0
)
1455 xop0
= convert_modes (xmode0
, mode0
, xop0
, unsignedp
);
1459 mode1
= GET_MODE (xop1
) != VOIDmode
? GET_MODE (xop1
) : mode
;
1460 if (xmode1
!= VOIDmode
&& xmode1
!= mode1
)
1462 xop1
= convert_modes (xmode1
, mode1
, xop1
, unsignedp
);
1466 /* If operation is commutative,
1467 try to make the first operand a register.
1468 Even better, try to make it the same as the target.
1469 Also try to make the last operand a constant. */
1471 && swap_commutative_operands_with_target (target
, xop0
, xop1
))
1478 /* Now, if insn's predicates don't allow our operands, put them into
1481 if (binoptab
== vec_pack_trunc_optab
1482 || binoptab
== vec_pack_usat_optab
1483 || binoptab
== vec_pack_ssat_optab
1484 || binoptab
== vec_pack_ufix_trunc_optab
1485 || binoptab
== vec_pack_sfix_trunc_optab
)
1487 /* The mode of the result is different then the mode of the
1489 tmp_mode
= insn_data
[(int) icode
].operand
[0].mode
;
1490 if (GET_MODE_NUNITS (tmp_mode
) != 2 * GET_MODE_NUNITS (mode
))
1492 delete_insns_since (last
);
1499 create_output_operand (&ops
[0], target
, tmp_mode
);
1500 create_input_operand (&ops
[1], xop0
, mode0
);
1501 create_input_operand (&ops
[2], xop1
, mode1
);
1502 pat
= maybe_gen_insn (icode
, 3, ops
);
1505 /* If PAT is composed of more than one insn, try to add an appropriate
1506 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1507 operand, call expand_binop again, this time without a target. */
1508 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
1509 && ! add_equal_note (pat
, ops
[0].value
, optab_to_code (binoptab
),
1510 ops
[1].value
, ops
[2].value
))
1512 delete_insns_since (last
);
1513 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1514 unsignedp
, methods
);
1518 return ops
[0].value
;
1520 delete_insns_since (last
);
1524 /* Generate code to perform an operation specified by BINOPTAB
1525 on operands OP0 and OP1, with result having machine-mode MODE.
1527 UNSIGNEDP is for the case where we have to widen the operands
1528 to perform the operation. It says to use zero-extension.
1530 If TARGET is nonzero, the value
1531 is generated there, if it is convenient to do so.
1532 In all cases an rtx is returned for the locus of the value;
1533 this may or may not be TARGET. */
1536 expand_binop (enum machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1537 rtx target
, int unsignedp
, enum optab_methods methods
)
1539 enum optab_methods next_methods
1540 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1541 ? OPTAB_WIDEN
: methods
);
1542 enum mode_class mclass
;
1543 enum machine_mode wider_mode
;
1546 rtx_insn
*entry_last
= get_last_insn ();
1549 mclass
= GET_MODE_CLASS (mode
);
1551 /* If subtracting an integer constant, convert this into an addition of
1552 the negated constant. */
1554 if (binoptab
== sub_optab
&& CONST_INT_P (op1
))
1556 op1
= negate_rtx (mode
, op1
);
1557 binoptab
= add_optab
;
1560 /* Record where to delete back to if we backtrack. */
1561 last
= get_last_insn ();
1563 /* If we can do it with a three-operand insn, do so. */
1565 if (methods
!= OPTAB_MUST_WIDEN
1566 && find_widening_optab_handler (binoptab
, mode
,
1567 widened_mode (mode
, op0
, op1
), 1)
1568 != CODE_FOR_nothing
)
1570 temp
= expand_binop_directly (mode
, binoptab
, op0
, op1
, target
,
1571 unsignedp
, methods
, last
);
1576 /* If we were trying to rotate, and that didn't work, try rotating
1577 the other direction before falling back to shifts and bitwise-or. */
1578 if (((binoptab
== rotl_optab
1579 && optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
1580 || (binoptab
== rotr_optab
1581 && optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
))
1582 && mclass
== MODE_INT
)
1584 optab otheroptab
= (binoptab
== rotl_optab
? rotr_optab
: rotl_optab
);
1586 unsigned int bits
= GET_MODE_PRECISION (mode
);
1588 if (CONST_INT_P (op1
))
1589 newop1
= GEN_INT (bits
- INTVAL (op1
));
1590 else if (targetm
.shift_truncation_mask (mode
) == bits
- 1)
1591 newop1
= negate_rtx (GET_MODE (op1
), op1
);
1593 newop1
= expand_binop (GET_MODE (op1
), sub_optab
,
1594 gen_int_mode (bits
, GET_MODE (op1
)), op1
,
1595 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1597 temp
= expand_binop_directly (mode
, otheroptab
, op0
, newop1
,
1598 target
, unsignedp
, methods
, last
);
1603 /* If this is a multiply, see if we can do a widening operation that
1604 takes operands of this mode and makes a wider mode. */
1606 if (binoptab
== smul_optab
1607 && GET_MODE_2XWIDER_MODE (mode
) != VOIDmode
1608 && (widening_optab_handler ((unsignedp
? umul_widen_optab
1609 : smul_widen_optab
),
1610 GET_MODE_2XWIDER_MODE (mode
), mode
)
1611 != CODE_FOR_nothing
))
1613 temp
= expand_binop (GET_MODE_2XWIDER_MODE (mode
),
1614 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1615 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1619 if (GET_MODE_CLASS (mode
) == MODE_INT
1620 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (temp
)))
1621 return gen_lowpart (mode
, temp
);
1623 return convert_to_mode (mode
, temp
, unsignedp
);
1627 /* If this is a vector shift by a scalar, see if we can do a vector
1628 shift by a vector. If so, broadcast the scalar into a vector. */
1629 if (mclass
== MODE_VECTOR_INT
)
1631 optab otheroptab
= unknown_optab
;
1633 if (binoptab
== ashl_optab
)
1634 otheroptab
= vashl_optab
;
1635 else if (binoptab
== ashr_optab
)
1636 otheroptab
= vashr_optab
;
1637 else if (binoptab
== lshr_optab
)
1638 otheroptab
= vlshr_optab
;
1639 else if (binoptab
== rotl_optab
)
1640 otheroptab
= vrotl_optab
;
1641 else if (binoptab
== rotr_optab
)
1642 otheroptab
= vrotr_optab
;
1644 if (otheroptab
&& optab_handler (otheroptab
, mode
) != CODE_FOR_nothing
)
1646 rtx vop1
= expand_vector_broadcast (mode
, op1
);
1649 temp
= expand_binop_directly (mode
, otheroptab
, op0
, vop1
,
1650 target
, unsignedp
, methods
, last
);
1657 /* Look for a wider mode of the same class for which we think we
1658 can open-code the operation. Check for a widening multiply at the
1659 wider mode as well. */
1661 if (CLASS_HAS_WIDER_MODES_P (mclass
)
1662 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1663 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
1664 wider_mode
!= VOIDmode
;
1665 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1667 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
1668 || (binoptab
== smul_optab
1669 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
1670 && (find_widening_optab_handler ((unsignedp
1672 : smul_widen_optab
),
1673 GET_MODE_WIDER_MODE (wider_mode
),
1675 != CODE_FOR_nothing
)))
1677 rtx xop0
= op0
, xop1
= op1
;
1680 /* For certain integer operations, we need not actually extend
1681 the narrow operands, as long as we will truncate
1682 the results to the same narrowness. */
1684 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1685 || binoptab
== xor_optab
1686 || binoptab
== add_optab
|| binoptab
== sub_optab
1687 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1688 && mclass
== MODE_INT
)
1691 xop0
= avoid_expensive_constant (mode
, binoptab
, 0,
1693 if (binoptab
!= ashl_optab
)
1694 xop1
= avoid_expensive_constant (mode
, binoptab
, 1,
1698 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1700 /* The second operand of a shift must always be extended. */
1701 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1702 no_extend
&& binoptab
!= ashl_optab
);
1704 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1705 unsignedp
, OPTAB_DIRECT
);
1708 if (mclass
!= MODE_INT
1709 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
1712 target
= gen_reg_rtx (mode
);
1713 convert_move (target
, temp
, 0);
1717 return gen_lowpart (mode
, temp
);
1720 delete_insns_since (last
);
1724 /* If operation is commutative,
1725 try to make the first operand a register.
1726 Even better, try to make it the same as the target.
1727 Also try to make the last operand a constant. */
1728 if (commutative_optab_p (binoptab
)
1729 && swap_commutative_operands_with_target (target
, op0
, op1
))
1736 /* These can be done a word at a time. */
1737 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1738 && mclass
== MODE_INT
1739 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1740 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1745 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1746 won't be accurate, so use a new target. */
1750 || !valid_multiword_target_p (target
))
1751 target
= gen_reg_rtx (mode
);
1755 /* Do the actual arithmetic. */
1756 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1758 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1759 rtx x
= expand_binop (word_mode
, binoptab
,
1760 operand_subword_force (op0
, i
, mode
),
1761 operand_subword_force (op1
, i
, mode
),
1762 target_piece
, unsignedp
, next_methods
);
1767 if (target_piece
!= x
)
1768 emit_move_insn (target_piece
, x
);
1771 insns
= get_insns ();
1774 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
1781 /* Synthesize double word shifts from single word shifts. */
1782 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1783 || binoptab
== ashr_optab
)
1784 && mclass
== MODE_INT
1785 && (CONST_INT_P (op1
) || optimize_insn_for_speed_p ())
1786 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1787 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
)
1788 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
1789 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1790 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1792 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1793 enum machine_mode op1_mode
;
1795 double_shift_mask
= targetm
.shift_truncation_mask (mode
);
1796 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1797 op1_mode
= GET_MODE (op1
) != VOIDmode
? GET_MODE (op1
) : word_mode
;
1799 /* Apply the truncation to constant shifts. */
1800 if (double_shift_mask
> 0 && CONST_INT_P (op1
))
1801 op1
= GEN_INT (INTVAL (op1
) & double_shift_mask
);
1803 if (op1
== CONST0_RTX (op1_mode
))
1806 /* Make sure that this is a combination that expand_doubleword_shift
1807 can handle. See the comments there for details. */
1808 if (double_shift_mask
== 0
1809 || (shift_mask
== BITS_PER_WORD
- 1
1810 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1813 rtx into_target
, outof_target
;
1814 rtx into_input
, outof_input
;
1815 int left_shift
, outof_word
;
1817 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1818 won't be accurate, so use a new target. */
1822 || !valid_multiword_target_p (target
))
1823 target
= gen_reg_rtx (mode
);
1827 /* OUTOF_* is the word we are shifting bits away from, and
1828 INTO_* is the word that we are shifting bits towards, thus
1829 they differ depending on the direction of the shift and
1830 WORDS_BIG_ENDIAN. */
1832 left_shift
= binoptab
== ashl_optab
;
1833 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1835 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1836 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1838 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1839 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1841 if (expand_doubleword_shift (op1_mode
, binoptab
,
1842 outof_input
, into_input
, op1
,
1843 outof_target
, into_target
,
1844 unsignedp
, next_methods
, shift_mask
))
1846 insns
= get_insns ();
1856 /* Synthesize double word rotates from single word shifts. */
1857 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1858 && mclass
== MODE_INT
1859 && CONST_INT_P (op1
)
1860 && GET_MODE_PRECISION (mode
) == 2 * BITS_PER_WORD
1861 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1862 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1865 rtx into_target
, outof_target
;
1866 rtx into_input
, outof_input
;
1868 int shift_count
, left_shift
, outof_word
;
1870 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1871 won't be accurate, so use a new target. Do this also if target is not
1872 a REG, first because having a register instead may open optimization
1873 opportunities, and second because if target and op0 happen to be MEMs
1874 designating the same location, we would risk clobbering it too early
1875 in the code sequence we generate below. */
1880 || !valid_multiword_target_p (target
))
1881 target
= gen_reg_rtx (mode
);
1885 shift_count
= INTVAL (op1
);
1887 /* OUTOF_* is the word we are shifting bits away from, and
1888 INTO_* is the word that we are shifting bits towards, thus
1889 they differ depending on the direction of the shift and
1890 WORDS_BIG_ENDIAN. */
1892 left_shift
= (binoptab
== rotl_optab
);
1893 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1895 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1896 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1898 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1899 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1901 if (shift_count
== BITS_PER_WORD
)
1903 /* This is just a word swap. */
1904 emit_move_insn (outof_target
, into_input
);
1905 emit_move_insn (into_target
, outof_input
);
1910 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1911 rtx first_shift_count
, second_shift_count
;
1912 optab reverse_unsigned_shift
, unsigned_shift
;
1914 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1915 ? lshr_optab
: ashl_optab
);
1917 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1918 ? ashl_optab
: lshr_optab
);
1920 if (shift_count
> BITS_PER_WORD
)
1922 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
1923 second_shift_count
= GEN_INT (2 * BITS_PER_WORD
- shift_count
);
1927 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
1928 second_shift_count
= GEN_INT (shift_count
);
1931 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1932 outof_input
, first_shift_count
,
1933 NULL_RTX
, unsignedp
, next_methods
);
1934 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1935 into_input
, second_shift_count
,
1936 NULL_RTX
, unsignedp
, next_methods
);
1938 if (into_temp1
!= 0 && into_temp2
!= 0)
1939 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1940 into_target
, unsignedp
, next_methods
);
1944 if (inter
!= 0 && inter
!= into_target
)
1945 emit_move_insn (into_target
, inter
);
1947 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1948 into_input
, first_shift_count
,
1949 NULL_RTX
, unsignedp
, next_methods
);
1950 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1951 outof_input
, second_shift_count
,
1952 NULL_RTX
, unsignedp
, next_methods
);
1954 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1955 inter
= expand_binop (word_mode
, ior_optab
,
1956 outof_temp1
, outof_temp2
,
1957 outof_target
, unsignedp
, next_methods
);
1959 if (inter
!= 0 && inter
!= outof_target
)
1960 emit_move_insn (outof_target
, inter
);
1963 insns
= get_insns ();
1973 /* These can be done a word at a time by propagating carries. */
1974 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1975 && mclass
== MODE_INT
1976 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
1977 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1980 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1981 const unsigned int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
1982 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1983 rtx xop0
, xop1
, xtarget
;
1985 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1986 value is one of those, use it. Otherwise, use 1 since it is the
1987 one easiest to get. */
1988 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1989 int normalizep
= STORE_FLAG_VALUE
;
1994 /* Prepare the operands. */
1995 xop0
= force_reg (mode
, op0
);
1996 xop1
= force_reg (mode
, op1
);
1998 xtarget
= gen_reg_rtx (mode
);
2000 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
2003 /* Indicate for flow that the entire target reg is being set. */
2005 emit_clobber (xtarget
);
2007 /* Do the actual arithmetic. */
2008 for (i
= 0; i
< nwords
; i
++)
2010 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
2011 rtx target_piece
= operand_subword (xtarget
, index
, 1, mode
);
2012 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
2013 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
2016 /* Main add/subtract of the input operands. */
2017 x
= expand_binop (word_mode
, binoptab
,
2018 op0_piece
, op1_piece
,
2019 target_piece
, unsignedp
, next_methods
);
2025 /* Store carry from main add/subtract. */
2026 carry_out
= gen_reg_rtx (word_mode
);
2027 carry_out
= emit_store_flag_force (carry_out
,
2028 (binoptab
== add_optab
2031 word_mode
, 1, normalizep
);
2038 /* Add/subtract previous carry to main result. */
2039 newx
= expand_binop (word_mode
,
2040 normalizep
== 1 ? binoptab
: otheroptab
,
2042 NULL_RTX
, 1, next_methods
);
2046 /* Get out carry from adding/subtracting carry in. */
2047 rtx carry_tmp
= gen_reg_rtx (word_mode
);
2048 carry_tmp
= emit_store_flag_force (carry_tmp
,
2049 (binoptab
== add_optab
2052 word_mode
, 1, normalizep
);
2054 /* Logical-ior the two poss. carry together. */
2055 carry_out
= expand_binop (word_mode
, ior_optab
,
2056 carry_out
, carry_tmp
,
2057 carry_out
, 0, next_methods
);
2061 emit_move_insn (target_piece
, newx
);
2065 if (x
!= target_piece
)
2066 emit_move_insn (target_piece
, x
);
2069 carry_in
= carry_out
;
2072 if (i
== GET_MODE_BITSIZE (mode
) / (unsigned) BITS_PER_WORD
)
2074 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
2075 || ! rtx_equal_p (target
, xtarget
))
2077 rtx temp
= emit_move_insn (target
, xtarget
);
2079 set_dst_reg_note (temp
, REG_EQUAL
,
2080 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2081 mode
, copy_rtx (xop0
),
2092 delete_insns_since (last
);
2095 /* Attempt to synthesize double word multiplies using a sequence of word
2096 mode multiplications. We first attempt to generate a sequence using a
2097 more efficient unsigned widening multiply, and if that fails we then
2098 try using a signed widening multiply. */
2100 if (binoptab
== smul_optab
2101 && mclass
== MODE_INT
2102 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
2103 && optab_handler (smul_optab
, word_mode
) != CODE_FOR_nothing
2104 && optab_handler (add_optab
, word_mode
) != CODE_FOR_nothing
)
2106 rtx product
= NULL_RTX
;
2107 if (widening_optab_handler (umul_widen_optab
, mode
, word_mode
)
2108 != CODE_FOR_nothing
)
2110 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2113 delete_insns_since (last
);
2116 if (product
== NULL_RTX
2117 && widening_optab_handler (smul_widen_optab
, mode
, word_mode
)
2118 != CODE_FOR_nothing
)
2120 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2123 delete_insns_since (last
);
2126 if (product
!= NULL_RTX
)
2128 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
)
2130 temp
= emit_move_insn (target
? target
: product
, product
);
2131 set_dst_reg_note (temp
,
2133 gen_rtx_fmt_ee (MULT
, mode
,
2136 target
? target
: product
);
2142 /* It can't be open-coded in this mode.
2143 Use a library call if one is available and caller says that's ok. */
2145 libfunc
= optab_libfunc (binoptab
, mode
);
2147 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
2151 enum machine_mode op1_mode
= mode
;
2156 if (shift_optab_p (binoptab
))
2158 op1_mode
= targetm
.libgcc_shift_count_mode ();
2159 /* Specify unsigned here,
2160 since negative shift counts are meaningless. */
2161 op1x
= convert_to_mode (op1_mode
, op1
, 1);
2164 if (GET_MODE (op0
) != VOIDmode
2165 && GET_MODE (op0
) != mode
)
2166 op0
= convert_to_mode (mode
, op0
, unsignedp
);
2168 /* Pass 1 for NO_QUEUE so we don't lose any increments
2169 if the libcall is cse'd or moved. */
2170 value
= emit_library_call_value (libfunc
,
2171 NULL_RTX
, LCT_CONST
, mode
, 2,
2172 op0
, mode
, op1x
, op1_mode
);
2174 insns
= get_insns ();
2177 target
= gen_reg_rtx (mode
);
2178 emit_libcall_block_1 (insns
, target
, value
,
2179 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2181 trapv_binoptab_p (binoptab
));
2186 delete_insns_since (last
);
2188 /* It can't be done in this mode. Can we do it in a wider mode? */
2190 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
2191 || methods
== OPTAB_MUST_WIDEN
))
2193 /* Caller says, don't even try. */
2194 delete_insns_since (entry_last
);
2198 /* Compute the value of METHODS to pass to recursive calls.
2199 Don't allow widening to be tried recursively. */
2201 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
2203 /* Look for a wider mode of the same class for which it appears we can do
2206 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2208 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2209 wider_mode
!= VOIDmode
;
2210 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2212 if (find_widening_optab_handler (binoptab
, wider_mode
, mode
, 1)
2214 || (methods
== OPTAB_LIB
2215 && optab_libfunc (binoptab
, wider_mode
)))
2217 rtx xop0
= op0
, xop1
= op1
;
2220 /* For certain integer operations, we need not actually extend
2221 the narrow operands, as long as we will truncate
2222 the results to the same narrowness. */
2224 if ((binoptab
== ior_optab
|| binoptab
== and_optab
2225 || binoptab
== xor_optab
2226 || binoptab
== add_optab
|| binoptab
== sub_optab
2227 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
2228 && mclass
== MODE_INT
)
2231 xop0
= widen_operand (xop0
, wider_mode
, mode
,
2232 unsignedp
, no_extend
);
2234 /* The second operand of a shift must always be extended. */
2235 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
2236 no_extend
&& binoptab
!= ashl_optab
);
2238 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
2239 unsignedp
, methods
);
2242 if (mclass
!= MODE_INT
2243 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
2246 target
= gen_reg_rtx (mode
);
2247 convert_move (target
, temp
, 0);
2251 return gen_lowpart (mode
, temp
);
2254 delete_insns_since (last
);
2259 delete_insns_since (entry_last
);
2263 /* Expand a binary operator which has both signed and unsigned forms.
2264 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2267 If we widen unsigned operands, we may use a signed wider operation instead
2268 of an unsigned wider operation, since the result would be the same. */
2271 sign_expand_binop (enum machine_mode mode
, optab uoptab
, optab soptab
,
2272 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
2273 enum optab_methods methods
)
2276 optab direct_optab
= unsignedp
? uoptab
: soptab
;
2279 /* Do it without widening, if possible. */
2280 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2281 unsignedp
, OPTAB_DIRECT
);
2282 if (temp
|| methods
== OPTAB_DIRECT
)
2285 /* Try widening to a signed int. Disable any direct use of any
2286 signed insn in the current mode. */
2287 save_enable
= swap_optab_enable (soptab
, mode
, false);
2289 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2290 unsignedp
, OPTAB_WIDEN
);
2292 /* For unsigned operands, try widening to an unsigned int. */
2293 if (!temp
&& unsignedp
)
2294 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2295 unsignedp
, OPTAB_WIDEN
);
2296 if (temp
|| methods
== OPTAB_WIDEN
)
2299 /* Use the right width libcall if that exists. */
2300 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2301 unsignedp
, OPTAB_LIB
);
2302 if (temp
|| methods
== OPTAB_LIB
)
2305 /* Must widen and use a libcall, use either signed or unsigned. */
2306 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2307 unsignedp
, methods
);
2308 if (!temp
&& unsignedp
)
2309 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2310 unsignedp
, methods
);
2313 /* Undo the fiddling above. */
2315 swap_optab_enable (soptab
, mode
, true);
2319 /* Generate code to perform an operation specified by UNOPPTAB
2320 on operand OP0, with two results to TARG0 and TARG1.
2321 We assume that the order of the operands for the instruction
2322 is TARG0, TARG1, OP0.
2324 Either TARG0 or TARG1 may be zero, but what that means is that
2325 the result is not actually wanted. We will generate it into
2326 a dummy pseudo-reg and discard it. They may not both be zero.
2328 Returns 1 if this operation can be performed; 0 if not. */
2331 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
2334 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2335 enum mode_class mclass
;
2336 enum machine_mode wider_mode
;
2337 rtx_insn
*entry_last
= get_last_insn ();
2340 mclass
= GET_MODE_CLASS (mode
);
2343 targ0
= gen_reg_rtx (mode
);
2345 targ1
= gen_reg_rtx (mode
);
2347 /* Record where to go back to if we fail. */
2348 last
= get_last_insn ();
2350 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2352 struct expand_operand ops
[3];
2353 enum insn_code icode
= optab_handler (unoptab
, mode
);
2355 create_fixed_operand (&ops
[0], targ0
);
2356 create_fixed_operand (&ops
[1], targ1
);
2357 create_convert_operand_from (&ops
[2], op0
, mode
, unsignedp
);
2358 if (maybe_expand_insn (icode
, 3, ops
))
2362 /* It can't be done in this mode. Can we do it in a wider mode? */
2364 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2366 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2367 wider_mode
!= VOIDmode
;
2368 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2370 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2372 rtx t0
= gen_reg_rtx (wider_mode
);
2373 rtx t1
= gen_reg_rtx (wider_mode
);
2374 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2376 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
2378 convert_move (targ0
, t0
, unsignedp
);
2379 convert_move (targ1
, t1
, unsignedp
);
2383 delete_insns_since (last
);
2388 delete_insns_since (entry_last
);
2392 /* Generate code to perform an operation specified by BINOPTAB
2393 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2394 We assume that the order of the operands for the instruction
2395 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2396 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2398 Either TARG0 or TARG1 may be zero, but what that means is that
2399 the result is not actually wanted. We will generate it into
2400 a dummy pseudo-reg and discard it. They may not both be zero.
2402 Returns 1 if this operation can be performed; 0 if not. */
2405 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
2408 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2409 enum mode_class mclass
;
2410 enum machine_mode wider_mode
;
2411 rtx_insn
*entry_last
= get_last_insn ();
2414 mclass
= GET_MODE_CLASS (mode
);
2417 targ0
= gen_reg_rtx (mode
);
2419 targ1
= gen_reg_rtx (mode
);
2421 /* Record where to go back to if we fail. */
2422 last
= get_last_insn ();
2424 if (optab_handler (binoptab
, mode
) != CODE_FOR_nothing
)
2426 struct expand_operand ops
[4];
2427 enum insn_code icode
= optab_handler (binoptab
, mode
);
2428 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2429 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2430 rtx xop0
= op0
, xop1
= op1
;
2432 /* If we are optimizing, force expensive constants into a register. */
2433 xop0
= avoid_expensive_constant (mode0
, binoptab
, 0, xop0
, unsignedp
);
2434 xop1
= avoid_expensive_constant (mode1
, binoptab
, 1, xop1
, unsignedp
);
2436 create_fixed_operand (&ops
[0], targ0
);
2437 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2438 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
2439 create_fixed_operand (&ops
[3], targ1
);
2440 if (maybe_expand_insn (icode
, 4, ops
))
2442 delete_insns_since (last
);
2445 /* It can't be done in this mode. Can we do it in a wider mode? */
2447 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2449 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2450 wider_mode
!= VOIDmode
;
2451 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2453 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
)
2455 rtx t0
= gen_reg_rtx (wider_mode
);
2456 rtx t1
= gen_reg_rtx (wider_mode
);
2457 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2458 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2460 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2463 convert_move (targ0
, t0
, unsignedp
);
2464 convert_move (targ1
, t1
, unsignedp
);
2468 delete_insns_since (last
);
2473 delete_insns_since (entry_last
);
2477 /* Expand the two-valued library call indicated by BINOPTAB, but
2478 preserve only one of the values. If TARG0 is non-NULL, the first
2479 value is placed into TARG0; otherwise the second value is placed
2480 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2481 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2482 This routine assumes that the value returned by the library call is
2483 as if the return value was of an integral mode twice as wide as the
2484 mode of OP0. Returns 1 if the call was successful. */
2487 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2488 rtx targ0
, rtx targ1
, enum rtx_code code
)
2490 enum machine_mode mode
;
2491 enum machine_mode libval_mode
;
2496 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2497 gcc_assert (!targ0
!= !targ1
);
2499 mode
= GET_MODE (op0
);
2500 libfunc
= optab_libfunc (binoptab
, mode
);
2504 /* The value returned by the library function will have twice as
2505 many bits as the nominal MODE. */
2506 libval_mode
= smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode
),
2509 libval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
2513 /* Get the part of VAL containing the value that we want. */
2514 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2515 targ0
? 0 : GET_MODE_SIZE (mode
));
2516 insns
= get_insns ();
2518 /* Move the into the desired location. */
2519 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2520 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2526 /* Wrapper around expand_unop which takes an rtx code to specify
2527 the operation to perform, not an optab pointer. All other
2528 arguments are the same. */
2530 expand_simple_unop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
2531 rtx target
, int unsignedp
)
2533 optab unop
= code_to_optab (code
);
2536 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2542 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2544 A similar operation can be used for clrsb. UNOPTAB says which operation
2545 we are trying to expand. */
2547 widen_leading (enum machine_mode mode
, rtx op0
, rtx target
, optab unoptab
)
2549 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2550 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2552 enum machine_mode wider_mode
;
2553 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2554 wider_mode
!= VOIDmode
;
2555 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2557 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2562 last
= get_last_insn ();
2565 target
= gen_reg_rtx (mode
);
2566 xop0
= widen_operand (op0
, wider_mode
, mode
,
2567 unoptab
!= clrsb_optab
, false);
2568 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2569 unoptab
!= clrsb_optab
);
2572 (wider_mode
, sub_optab
, temp
,
2573 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
2574 - GET_MODE_PRECISION (mode
),
2576 target
, true, OPTAB_DIRECT
);
2578 delete_insns_since (last
);
2587 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2588 quantities, choosing which based on whether the high word is nonzero. */
2590 expand_doubleword_clz (enum machine_mode mode
, rtx op0
, rtx target
)
2592 rtx xop0
= force_reg (mode
, op0
);
2593 rtx subhi
= gen_highpart (word_mode
, xop0
);
2594 rtx sublo
= gen_lowpart (word_mode
, xop0
);
2595 rtx_code_label
*hi0_label
= gen_label_rtx ();
2596 rtx_code_label
*after_label
= gen_label_rtx ();
2600 /* If we were not given a target, use a word_mode register, not a
2601 'mode' register. The result will fit, and nobody is expecting
2602 anything bigger (the return type of __builtin_clz* is int). */
2604 target
= gen_reg_rtx (word_mode
);
2606 /* In any case, write to a word_mode scratch in both branches of the
2607 conditional, so we can ensure there is a single move insn setting
2608 'target' to tag a REG_EQUAL note on. */
2609 result
= gen_reg_rtx (word_mode
);
2613 /* If the high word is not equal to zero,
2614 then clz of the full value is clz of the high word. */
2615 emit_cmp_and_jump_insns (subhi
, CONST0_RTX (word_mode
), EQ
, 0,
2616 word_mode
, true, hi0_label
);
2618 temp
= expand_unop_direct (word_mode
, clz_optab
, subhi
, result
, true);
2623 convert_move (result
, temp
, true);
2625 emit_jump_insn (gen_jump (after_label
));
2628 /* Else clz of the full value is clz of the low word plus the number
2629 of bits in the high word. */
2630 emit_label (hi0_label
);
2632 temp
= expand_unop_direct (word_mode
, clz_optab
, sublo
, 0, true);
2635 temp
= expand_binop (word_mode
, add_optab
, temp
,
2636 gen_int_mode (GET_MODE_BITSIZE (word_mode
), word_mode
),
2637 result
, true, OPTAB_DIRECT
);
2641 convert_move (result
, temp
, true);
2643 emit_label (after_label
);
2644 convert_move (target
, result
, true);
2649 add_equal_note (seq
, target
, CLZ
, xop0
, 0);
2661 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2663 widen_bswap (enum machine_mode mode
, rtx op0
, rtx target
)
2665 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2666 enum machine_mode wider_mode
;
2670 if (!CLASS_HAS_WIDER_MODES_P (mclass
))
2673 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2674 wider_mode
!= VOIDmode
;
2675 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2676 if (optab_handler (bswap_optab
, wider_mode
) != CODE_FOR_nothing
)
2681 last
= get_last_insn ();
2683 x
= widen_operand (op0
, wider_mode
, mode
, true, true);
2684 x
= expand_unop (wider_mode
, bswap_optab
, x
, NULL_RTX
, true);
2686 gcc_assert (GET_MODE_PRECISION (wider_mode
) == GET_MODE_BITSIZE (wider_mode
)
2687 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
));
2689 x
= expand_shift (RSHIFT_EXPR
, wider_mode
, x
,
2690 GET_MODE_BITSIZE (wider_mode
)
2691 - GET_MODE_BITSIZE (mode
),
2697 target
= gen_reg_rtx (mode
);
2698 emit_move_insn (target
, gen_lowpart (mode
, x
));
2701 delete_insns_since (last
);
2706 /* Try calculating bswap as two bswaps of two word-sized operands. */
2709 expand_doubleword_bswap (enum machine_mode mode
, rtx op
, rtx target
)
2713 t1
= expand_unop (word_mode
, bswap_optab
,
2714 operand_subword_force (op
, 0, mode
), NULL_RTX
, true);
2715 t0
= expand_unop (word_mode
, bswap_optab
,
2716 operand_subword_force (op
, 1, mode
), NULL_RTX
, true);
2718 if (target
== 0 || !valid_multiword_target_p (target
))
2719 target
= gen_reg_rtx (mode
);
2721 emit_clobber (target
);
2722 emit_move_insn (operand_subword (target
, 0, 1, mode
), t0
);
2723 emit_move_insn (operand_subword (target
, 1, 1, mode
), t1
);
2728 /* Try calculating (parity x) as (and (popcount x) 1), where
2729 popcount can also be done in a wider mode. */
2731 expand_parity (enum machine_mode mode
, rtx op0
, rtx target
)
2733 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2734 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2736 enum machine_mode wider_mode
;
2737 for (wider_mode
= mode
; wider_mode
!= VOIDmode
;
2738 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2740 if (optab_handler (popcount_optab
, wider_mode
) != CODE_FOR_nothing
)
2745 last
= get_last_insn ();
2748 target
= gen_reg_rtx (mode
);
2749 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2750 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2753 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2754 target
, true, OPTAB_DIRECT
);
2756 delete_insns_since (last
);
2765 /* Try calculating ctz(x) as K - clz(x & -x) ,
2766 where K is GET_MODE_PRECISION(mode) - 1.
2768 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2769 don't have to worry about what the hardware does in that case. (If
2770 the clz instruction produces the usual value at 0, which is K, the
2771 result of this code sequence will be -1; expand_ffs, below, relies
2772 on this. It might be nice to have it be K instead, for consistency
2773 with the (very few) processors that provide a ctz with a defined
2774 value, but that would take one more instruction, and it would be
2775 less convenient for expand_ffs anyway. */
2778 expand_ctz (enum machine_mode mode
, rtx op0
, rtx target
)
2783 if (optab_handler (clz_optab
, mode
) == CODE_FOR_nothing
)
2788 temp
= expand_unop_direct (mode
, neg_optab
, op0
, NULL_RTX
, true);
2790 temp
= expand_binop (mode
, and_optab
, op0
, temp
, NULL_RTX
,
2791 true, OPTAB_DIRECT
);
2793 temp
= expand_unop_direct (mode
, clz_optab
, temp
, NULL_RTX
, true);
2795 temp
= expand_binop (mode
, sub_optab
,
2796 gen_int_mode (GET_MODE_PRECISION (mode
) - 1, mode
),
2798 true, OPTAB_DIRECT
);
2808 add_equal_note (seq
, temp
, CTZ
, op0
, 0);
2814 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2815 else with the sequence used by expand_clz.
2817 The ffs builtin promises to return zero for a zero value and ctz/clz
2818 may have an undefined value in that case. If they do not give us a
2819 convenient value, we have to generate a test and branch. */
2821 expand_ffs (enum machine_mode mode
, rtx op0
, rtx target
)
2823 HOST_WIDE_INT val
= 0;
2824 bool defined_at_zero
= false;
2828 if (optab_handler (ctz_optab
, mode
) != CODE_FOR_nothing
)
2832 temp
= expand_unop_direct (mode
, ctz_optab
, op0
, 0, true);
2836 defined_at_zero
= (CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2);
2838 else if (optab_handler (clz_optab
, mode
) != CODE_FOR_nothing
)
2841 temp
= expand_ctz (mode
, op0
, 0);
2845 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2)
2847 defined_at_zero
= true;
2848 val
= (GET_MODE_PRECISION (mode
) - 1) - val
;
2854 if (defined_at_zero
&& val
== -1)
2855 /* No correction needed at zero. */;
2858 /* We don't try to do anything clever with the situation found
2859 on some processors (eg Alpha) where ctz(0:mode) ==
2860 bitsize(mode). If someone can think of a way to send N to -1
2861 and leave alone all values in the range 0..N-1 (where N is a
2862 power of two), cheaper than this test-and-branch, please add it.
2864 The test-and-branch is done after the operation itself, in case
2865 the operation sets condition codes that can be recycled for this.
2866 (This is true on i386, for instance.) */
2868 rtx_code_label
*nonzero_label
= gen_label_rtx ();
2869 emit_cmp_and_jump_insns (op0
, CONST0_RTX (mode
), NE
, 0,
2870 mode
, true, nonzero_label
);
2872 convert_move (temp
, GEN_INT (-1), false);
2873 emit_label (nonzero_label
);
2876 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
2877 to produce a value in the range 0..bitsize. */
2878 temp
= expand_binop (mode
, add_optab
, temp
, gen_int_mode (1, mode
),
2879 target
, false, OPTAB_DIRECT
);
2886 add_equal_note (seq
, temp
, FFS
, op0
, 0);
2895 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2896 conditions, VAL may already be a SUBREG against which we cannot generate
2897 a further SUBREG. In this case, we expect forcing the value into a
2898 register will work around the situation. */
2901 lowpart_subreg_maybe_copy (enum machine_mode omode
, rtx val
,
2902 enum machine_mode imode
)
2905 ret
= lowpart_subreg (omode
, val
, imode
);
2908 val
= force_reg (imode
, val
);
2909 ret
= lowpart_subreg (omode
, val
, imode
);
2910 gcc_assert (ret
!= NULL
);
2915 /* Expand a floating point absolute value or negation operation via a
2916 logical operation on the sign bit. */
2919 expand_absneg_bit (enum rtx_code code
, enum machine_mode mode
,
2920 rtx op0
, rtx target
)
2922 const struct real_format
*fmt
;
2923 int bitpos
, word
, nwords
, i
;
2924 enum machine_mode imode
;
2928 /* The format has to have a simple sign bit. */
2929 fmt
= REAL_MODE_FORMAT (mode
);
2933 bitpos
= fmt
->signbit_rw
;
2937 /* Don't create negative zeros if the format doesn't support them. */
2938 if (code
== NEG
&& !fmt
->has_signed_zero
)
2941 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2943 imode
= int_mode_for_mode (mode
);
2944 if (imode
== BLKmode
)
2953 if (FLOAT_WORDS_BIG_ENDIAN
)
2954 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2956 word
= bitpos
/ BITS_PER_WORD
;
2957 bitpos
= bitpos
% BITS_PER_WORD
;
2958 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2961 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
2967 || (nwords
> 1 && !valid_multiword_target_p (target
)))
2968 target
= gen_reg_rtx (mode
);
2974 for (i
= 0; i
< nwords
; ++i
)
2976 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2977 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2981 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2983 immed_wide_int_const (mask
, imode
),
2984 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2985 if (temp
!= targ_piece
)
2986 emit_move_insn (targ_piece
, temp
);
2989 emit_move_insn (targ_piece
, op0_piece
);
2992 insns
= get_insns ();
2999 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
3000 gen_lowpart (imode
, op0
),
3001 immed_wide_int_const (mask
, imode
),
3002 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3003 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3005 set_dst_reg_note (get_last_insn (), REG_EQUAL
,
3006 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)),
3013 /* As expand_unop, but will fail rather than attempt the operation in a
3014 different mode or with a libcall. */
3016 expand_unop_direct (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
3019 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
3021 struct expand_operand ops
[2];
3022 enum insn_code icode
= optab_handler (unoptab
, mode
);
3023 rtx_insn
*last
= get_last_insn ();
3026 create_output_operand (&ops
[0], target
, mode
);
3027 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
3028 pat
= maybe_gen_insn (icode
, 2, ops
);
3031 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
3032 && ! add_equal_note (pat
, ops
[0].value
, optab_to_code (unoptab
),
3033 ops
[1].value
, NULL_RTX
))
3035 delete_insns_since (last
);
3036 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
3041 return ops
[0].value
;
3047 /* Generate code to perform an operation specified by UNOPTAB
3048 on operand OP0, with result having machine-mode MODE.
3050 UNSIGNEDP is for the case where we have to widen the operands
3051 to perform the operation. It says to use zero-extension.
3053 If TARGET is nonzero, the value
3054 is generated there, if it is convenient to do so.
3055 In all cases an rtx is returned for the locus of the value;
3056 this may or may not be TARGET. */
3059 expand_unop (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
3062 enum mode_class mclass
= GET_MODE_CLASS (mode
);
3063 enum machine_mode wider_mode
;
3067 temp
= expand_unop_direct (mode
, unoptab
, op0
, target
, unsignedp
);
3071 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3073 /* Widening (or narrowing) clz needs special treatment. */
3074 if (unoptab
== clz_optab
)
3076 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3080 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3081 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3083 temp
= expand_doubleword_clz (mode
, op0
, target
);
3091 if (unoptab
== clrsb_optab
)
3093 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3099 /* Widening (or narrowing) bswap needs special treatment. */
3100 if (unoptab
== bswap_optab
)
3102 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3103 or ROTATERT. First try these directly; if this fails, then try the
3104 obvious pair of shifts with allowed widening, as this will probably
3105 be always more efficient than the other fallback methods. */
3111 if (optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
)
3113 temp
= expand_binop (mode
, rotl_optab
, op0
, GEN_INT (8), target
,
3114 unsignedp
, OPTAB_DIRECT
);
3119 if (optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
3121 temp
= expand_binop (mode
, rotr_optab
, op0
, GEN_INT (8), target
,
3122 unsignedp
, OPTAB_DIRECT
);
3127 last
= get_last_insn ();
3129 temp1
= expand_binop (mode
, ashl_optab
, op0
, GEN_INT (8), NULL_RTX
,
3130 unsignedp
, OPTAB_WIDEN
);
3131 temp2
= expand_binop (mode
, lshr_optab
, op0
, GEN_INT (8), NULL_RTX
,
3132 unsignedp
, OPTAB_WIDEN
);
3135 temp
= expand_binop (mode
, ior_optab
, temp1
, temp2
, target
,
3136 unsignedp
, OPTAB_WIDEN
);
3141 delete_insns_since (last
);
3144 temp
= widen_bswap (mode
, op0
, target
);
3148 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3149 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3151 temp
= expand_doubleword_bswap (mode
, op0
, target
);
3159 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3160 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3161 wider_mode
!= VOIDmode
;
3162 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3164 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
3167 rtx_insn
*last
= get_last_insn ();
3169 /* For certain operations, we need not actually extend
3170 the narrow operand, as long as we will truncate the
3171 results to the same narrowness. */
3173 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3174 (unoptab
== neg_optab
3175 || unoptab
== one_cmpl_optab
)
3176 && mclass
== MODE_INT
);
3178 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3183 if (mclass
!= MODE_INT
3184 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
3187 target
= gen_reg_rtx (mode
);
3188 convert_move (target
, temp
, 0);
3192 return gen_lowpart (mode
, temp
);
3195 delete_insns_since (last
);
3199 /* These can be done a word at a time. */
3200 if (unoptab
== one_cmpl_optab
3201 && mclass
== MODE_INT
3202 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
3203 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3208 if (target
== 0 || target
== op0
|| !valid_multiword_target_p (target
))
3209 target
= gen_reg_rtx (mode
);
3213 /* Do the actual arithmetic. */
3214 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
3216 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
3217 rtx x
= expand_unop (word_mode
, unoptab
,
3218 operand_subword_force (op0
, i
, mode
),
3219 target_piece
, unsignedp
);
3221 if (target_piece
!= x
)
3222 emit_move_insn (target_piece
, x
);
3225 insns
= get_insns ();
3232 if (optab_to_code (unoptab
) == NEG
)
3234 /* Try negating floating point values by flipping the sign bit. */
3235 if (SCALAR_FLOAT_MODE_P (mode
))
3237 temp
= expand_absneg_bit (NEG
, mode
, op0
, target
);
3242 /* If there is no negation pattern, and we have no negative zero,
3243 try subtracting from zero. */
3244 if (!HONOR_SIGNED_ZEROS (mode
))
3246 temp
= expand_binop (mode
, (unoptab
== negv_optab
3247 ? subv_optab
: sub_optab
),
3248 CONST0_RTX (mode
), op0
, target
,
3249 unsignedp
, OPTAB_DIRECT
);
3255 /* Try calculating parity (x) as popcount (x) % 2. */
3256 if (unoptab
== parity_optab
)
3258 temp
= expand_parity (mode
, op0
, target
);
3263 /* Try implementing ffs (x) in terms of clz (x). */
3264 if (unoptab
== ffs_optab
)
3266 temp
= expand_ffs (mode
, op0
, target
);
3271 /* Try implementing ctz (x) in terms of clz (x). */
3272 if (unoptab
== ctz_optab
)
3274 temp
= expand_ctz (mode
, op0
, target
);
3280 /* Now try a library call in this mode. */
3281 libfunc
= optab_libfunc (unoptab
, mode
);
3287 enum machine_mode outmode
= mode
;
3289 /* All of these functions return small values. Thus we choose to
3290 have them return something that isn't a double-word. */
3291 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
3292 || unoptab
== clrsb_optab
|| unoptab
== popcount_optab
3293 || unoptab
== parity_optab
)
3295 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
),
3296 optab_libfunc (unoptab
, mode
)));
3300 /* Pass 1 for NO_QUEUE so we don't lose any increments
3301 if the libcall is cse'd or moved. */
3302 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, outmode
,
3304 insns
= get_insns ();
3307 target
= gen_reg_rtx (outmode
);
3308 eq_value
= gen_rtx_fmt_e (optab_to_code (unoptab
), mode
, op0
);
3309 if (GET_MODE_SIZE (outmode
) < GET_MODE_SIZE (mode
))
3310 eq_value
= simplify_gen_unary (TRUNCATE
, outmode
, eq_value
, mode
);
3311 else if (GET_MODE_SIZE (outmode
) > GET_MODE_SIZE (mode
))
3312 eq_value
= simplify_gen_unary (ZERO_EXTEND
, outmode
, eq_value
, mode
);
3313 emit_libcall_block_1 (insns
, target
, value
, eq_value
,
3314 trapv_unoptab_p (unoptab
));
3319 /* It can't be done in this mode. Can we do it in a wider mode? */
3321 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3323 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3324 wider_mode
!= VOIDmode
;
3325 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3327 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
3328 || optab_libfunc (unoptab
, wider_mode
))
3331 rtx_insn
*last
= get_last_insn ();
3333 /* For certain operations, we need not actually extend
3334 the narrow operand, as long as we will truncate the
3335 results to the same narrowness. */
3336 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3337 (unoptab
== neg_optab
3338 || unoptab
== one_cmpl_optab
3339 || unoptab
== bswap_optab
)
3340 && mclass
== MODE_INT
);
3342 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3345 /* If we are generating clz using wider mode, adjust the
3346 result. Similarly for clrsb. */
3347 if ((unoptab
== clz_optab
|| unoptab
== clrsb_optab
)
3350 (wider_mode
, sub_optab
, temp
,
3351 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
3352 - GET_MODE_PRECISION (mode
),
3354 target
, true, OPTAB_DIRECT
);
3356 /* Likewise for bswap. */
3357 if (unoptab
== bswap_optab
&& temp
!= 0)
3359 gcc_assert (GET_MODE_PRECISION (wider_mode
)
3360 == GET_MODE_BITSIZE (wider_mode
)
3361 && GET_MODE_PRECISION (mode
)
3362 == GET_MODE_BITSIZE (mode
));
3364 temp
= expand_shift (RSHIFT_EXPR
, wider_mode
, temp
,
3365 GET_MODE_BITSIZE (wider_mode
)
3366 - GET_MODE_BITSIZE (mode
),
3372 if (mclass
!= MODE_INT
)
3375 target
= gen_reg_rtx (mode
);
3376 convert_move (target
, temp
, 0);
3380 return gen_lowpart (mode
, temp
);
3383 delete_insns_since (last
);
3388 /* One final attempt at implementing negation via subtraction,
3389 this time allowing widening of the operand. */
3390 if (optab_to_code (unoptab
) == NEG
&& !HONOR_SIGNED_ZEROS (mode
))
3393 temp
= expand_binop (mode
,
3394 unoptab
== negv_optab
? subv_optab
: sub_optab
,
3395 CONST0_RTX (mode
), op0
,
3396 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3404 /* Emit code to compute the absolute value of OP0, with result to
3405 TARGET if convenient. (TARGET may be 0.) The return value says
3406 where the result actually is to be found.
3408 MODE is the mode of the operand; the mode of the result is
3409 different but can be deduced from MODE.
3414 expand_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
,
3415 int result_unsignedp
)
3419 if (GET_MODE_CLASS (mode
) != MODE_INT
3421 result_unsignedp
= 1;
3423 /* First try to do it with a special abs instruction. */
3424 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
3429 /* For floating point modes, try clearing the sign bit. */
3430 if (SCALAR_FLOAT_MODE_P (mode
))
3432 temp
= expand_absneg_bit (ABS
, mode
, op0
, target
);
3437 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3438 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
3439 && !HONOR_SIGNED_ZEROS (mode
))
3441 rtx_insn
*last
= get_last_insn ();
3443 temp
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3446 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3452 delete_insns_since (last
);
3455 /* If this machine has expensive jumps, we can do integer absolute
3456 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3457 where W is the width of MODE. */
3459 if (GET_MODE_CLASS (mode
) == MODE_INT
3460 && BRANCH_COST (optimize_insn_for_speed_p (),
3463 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3464 GET_MODE_PRECISION (mode
) - 1,
3467 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3470 temp
= expand_binop (mode
, result_unsignedp
? sub_optab
: subv_optab
,
3471 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
3481 expand_abs (enum machine_mode mode
, rtx op0
, rtx target
,
3482 int result_unsignedp
, int safe
)
3485 rtx_code_label
*op1
;
3487 if (GET_MODE_CLASS (mode
) != MODE_INT
3489 result_unsignedp
= 1;
3491 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
3495 /* If that does not win, use conditional jump and negate. */
3497 /* It is safe to use the target if it is the same
3498 as the source if this is also a pseudo register */
3499 if (op0
== target
&& REG_P (op0
)
3500 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
3503 op1
= gen_label_rtx ();
3504 if (target
== 0 || ! safe
3505 || GET_MODE (target
) != mode
3506 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
3508 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
3509 target
= gen_reg_rtx (mode
);
3511 emit_move_insn (target
, op0
);
3514 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
3515 NULL_RTX
, NULL_RTX
, op1
, -1);
3517 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3520 emit_move_insn (target
, op0
);
3526 /* Emit code to compute the one's complement absolute value of OP0
3527 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3528 (TARGET may be NULL_RTX.) The return value says where the result
3529 actually is to be found.
3531 MODE is the mode of the operand; the mode of the result is
3532 different but can be deduced from MODE. */
3535 expand_one_cmpl_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
)
3539 /* Not applicable for floating point modes. */
3540 if (FLOAT_MODE_P (mode
))
3543 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3544 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
)
3546 rtx_insn
*last
= get_last_insn ();
3548 temp
= expand_unop (mode
, one_cmpl_optab
, op0
, NULL_RTX
, 0);
3550 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3556 delete_insns_since (last
);
3559 /* If this machine has expensive jumps, we can do one's complement
3560 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3562 if (GET_MODE_CLASS (mode
) == MODE_INT
3563 && BRANCH_COST (optimize_insn_for_speed_p (),
3566 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3567 GET_MODE_PRECISION (mode
) - 1,
3570 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3580 /* A subroutine of expand_copysign, perform the copysign operation using the
3581 abs and neg primitives advertised to exist on the target. The assumption
3582 is that we have a split register file, and leaving op0 in fp registers,
3583 and not playing with subregs so much, will help the register allocator. */
3586 expand_copysign_absneg (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3587 int bitpos
, bool op0_is_abs
)
3589 enum machine_mode imode
;
3590 enum insn_code icode
;
3592 rtx_code_label
*label
;
3597 /* Check if the back end provides an insn that handles signbit for the
3599 icode
= optab_handler (signbit_optab
, mode
);
3600 if (icode
!= CODE_FOR_nothing
)
3602 imode
= insn_data
[(int) icode
].operand
[0].mode
;
3603 sign
= gen_reg_rtx (imode
);
3604 emit_unop_insn (icode
, sign
, op1
, UNKNOWN
);
3608 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3610 imode
= int_mode_for_mode (mode
);
3611 if (imode
== BLKmode
)
3613 op1
= gen_lowpart (imode
, op1
);
3620 if (FLOAT_WORDS_BIG_ENDIAN
)
3621 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3623 word
= bitpos
/ BITS_PER_WORD
;
3624 bitpos
= bitpos
% BITS_PER_WORD
;
3625 op1
= operand_subword_force (op1
, word
, mode
);
3628 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3629 sign
= expand_binop (imode
, and_optab
, op1
,
3630 immed_wide_int_const (mask
, imode
),
3631 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3636 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
3643 if (target
== NULL_RTX
)
3644 target
= copy_to_reg (op0
);
3646 emit_move_insn (target
, op0
);
3649 label
= gen_label_rtx ();
3650 emit_cmp_and_jump_insns (sign
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
3652 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3653 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3655 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
3657 emit_move_insn (target
, op0
);
3665 /* A subroutine of expand_copysign, perform the entire copysign operation
3666 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3667 is true if op0 is known to have its sign bit clear. */
3670 expand_copysign_bit (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3671 int bitpos
, bool op0_is_abs
)
3673 enum machine_mode imode
;
3674 int word
, nwords
, i
;
3678 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3680 imode
= int_mode_for_mode (mode
);
3681 if (imode
== BLKmode
)
3690 if (FLOAT_WORDS_BIG_ENDIAN
)
3691 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3693 word
= bitpos
/ BITS_PER_WORD
;
3694 bitpos
= bitpos
% BITS_PER_WORD
;
3695 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3698 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3703 || (nwords
> 1 && !valid_multiword_target_p (target
)))
3704 target
= gen_reg_rtx (mode
);
3710 for (i
= 0; i
< nwords
; ++i
)
3712 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
3713 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
3719 = expand_binop (imode
, and_optab
, op0_piece
,
3720 immed_wide_int_const (~mask
, imode
),
3721 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3722 op1
= expand_binop (imode
, and_optab
,
3723 operand_subword_force (op1
, i
, mode
),
3724 immed_wide_int_const (mask
, imode
),
3725 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3727 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
3728 targ_piece
, 1, OPTAB_LIB_WIDEN
);
3729 if (temp
!= targ_piece
)
3730 emit_move_insn (targ_piece
, temp
);
3733 emit_move_insn (targ_piece
, op0_piece
);
3736 insns
= get_insns ();
3743 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
3744 immed_wide_int_const (mask
, imode
),
3745 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3747 op0
= gen_lowpart (imode
, op0
);
3749 op0
= expand_binop (imode
, and_optab
, op0
,
3750 immed_wide_int_const (~mask
, imode
),
3751 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3753 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
3754 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3755 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3761 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3762 scalar floating point mode. Return NULL if we do not know how to
3763 expand the operation inline. */
3766 expand_copysign (rtx op0
, rtx op1
, rtx target
)
3768 enum machine_mode mode
= GET_MODE (op0
);
3769 const struct real_format
*fmt
;
3773 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
3774 gcc_assert (GET_MODE (op1
) == mode
);
3776 /* First try to do it with a special instruction. */
3777 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
3778 target
, 0, OPTAB_DIRECT
);
3782 fmt
= REAL_MODE_FORMAT (mode
);
3783 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
3787 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3789 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
3790 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
3794 if (fmt
->signbit_ro
>= 0
3795 && (CONST_DOUBLE_AS_FLOAT_P (op0
)
3796 || (optab_handler (neg_optab
, mode
) != CODE_FOR_nothing
3797 && optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)))
3799 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
3800 fmt
->signbit_ro
, op0_is_abs
);
3805 if (fmt
->signbit_rw
< 0)
3807 return expand_copysign_bit (mode
, op0
, op1
, target
,
3808 fmt
->signbit_rw
, op0_is_abs
);
3811 /* Generate an instruction whose insn-code is INSN_CODE,
3812 with two operands: an output TARGET and an input OP0.
3813 TARGET *must* be nonzero, and the output is always stored there.
3814 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3815 the value that is stored into TARGET.
3817 Return false if expansion failed. */
3820 maybe_emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
,
3823 struct expand_operand ops
[2];
3826 create_output_operand (&ops
[0], target
, GET_MODE (target
));
3827 create_input_operand (&ops
[1], op0
, GET_MODE (op0
));
3828 pat
= maybe_gen_insn (icode
, 2, ops
);
3832 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
&& code
!= UNKNOWN
)
3833 add_equal_note (pat
, ops
[0].value
, code
, ops
[1].value
, NULL_RTX
);
3837 if (ops
[0].value
!= target
)
3838 emit_move_insn (target
, ops
[0].value
);
3841 /* Generate an instruction whose insn-code is INSN_CODE,
3842 with two operands: an output TARGET and an input OP0.
3843 TARGET *must* be nonzero, and the output is always stored there.
3844 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3845 the value that is stored into TARGET. */
3848 emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
, enum rtx_code code
)
3850 bool ok
= maybe_emit_unop_insn (icode
, target
, op0
, code
);
3854 struct no_conflict_data
3857 rtx_insn
*first
, *insn
;
3861 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
3862 the currently examined clobber / store has to stay in the list of
3863 insns that constitute the actual libcall block. */
3865 no_conflict_move_test (rtx dest
, const_rtx set
, void *p0
)
3867 struct no_conflict_data
*p
= (struct no_conflict_data
*) p0
;
3869 /* If this inns directly contributes to setting the target, it must stay. */
3870 if (reg_overlap_mentioned_p (p
->target
, dest
))
3871 p
->must_stay
= true;
3872 /* If we haven't committed to keeping any other insns in the list yet,
3873 there is nothing more to check. */
3874 else if (p
->insn
== p
->first
)
3876 /* If this insn sets / clobbers a register that feeds one of the insns
3877 already in the list, this insn has to stay too. */
3878 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3879 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3880 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3881 /* Likewise if this insn depends on a register set by a previous
3882 insn in the list, or if it sets a result (presumably a hard
3883 register) that is set or clobbered by a previous insn.
3884 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3885 SET_DEST perform the former check on the address, and the latter
3886 check on the MEM. */
3887 || (GET_CODE (set
) == SET
3888 && (modified_in_p (SET_SRC (set
), p
->first
)
3889 || modified_in_p (SET_DEST (set
), p
->first
)
3890 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3891 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3892 p
->must_stay
= true;
3896 /* Emit code to make a call to a constant function or a library call.
3898 INSNS is a list containing all insns emitted in the call.
3899 These insns leave the result in RESULT. Our block is to copy RESULT
3900 to TARGET, which is logically equivalent to EQUIV.
3902 We first emit any insns that set a pseudo on the assumption that these are
3903 loading constants into registers; doing so allows them to be safely cse'ed
3904 between blocks. Then we emit all the other insns in the block, followed by
3905 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3906 note with an operand of EQUIV. */
3909 emit_libcall_block_1 (rtx_insn
*insns
, rtx target
, rtx result
, rtx equiv
,
3910 bool equiv_may_trap
)
3912 rtx final_dest
= target
;
3913 rtx_insn
*next
, *last
, *insn
;
3915 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3916 into a MEM later. Protect the libcall block from this change. */
3917 if (! REG_P (target
) || REG_USERVAR_P (target
))
3918 target
= gen_reg_rtx (GET_MODE (target
));
3920 /* If we're using non-call exceptions, a libcall corresponding to an
3921 operation that may trap may also trap. */
3922 /* ??? See the comment in front of make_reg_eh_region_note. */
3923 if (cfun
->can_throw_non_call_exceptions
3924 && (equiv_may_trap
|| may_trap_p (equiv
)))
3926 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3929 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3932 int lp_nr
= INTVAL (XEXP (note
, 0));
3933 if (lp_nr
== 0 || lp_nr
== INT_MIN
)
3934 remove_note (insn
, note
);
3940 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3941 reg note to indicate that this call cannot throw or execute a nonlocal
3942 goto (unless there is already a REG_EH_REGION note, in which case
3944 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3946 make_reg_eh_region_note_nothrow_nononlocal (insn
);
3949 /* First emit all insns that set pseudos. Remove them from the list as
3950 we go. Avoid insns that set pseudos which were referenced in previous
3951 insns. These can be generated by move_by_pieces, for example,
3952 to update an address. Similarly, avoid insns that reference things
3953 set in previous insns. */
3955 for (insn
= insns
; insn
; insn
= next
)
3957 rtx set
= single_set (insn
);
3959 next
= NEXT_INSN (insn
);
3961 if (set
!= 0 && REG_P (SET_DEST (set
))
3962 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3964 struct no_conflict_data data
;
3966 data
.target
= const0_rtx
;
3970 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3971 if (! data
.must_stay
)
3973 if (PREV_INSN (insn
))
3974 SET_NEXT_INSN (PREV_INSN (insn
)) = next
;
3979 SET_PREV_INSN (next
) = PREV_INSN (insn
);
3985 /* Some ports use a loop to copy large arguments onto the stack.
3986 Don't move anything outside such a loop. */
3991 /* Write the remaining insns followed by the final copy. */
3992 for (insn
= insns
; insn
; insn
= next
)
3994 next
= NEXT_INSN (insn
);
3999 last
= emit_move_insn (target
, result
);
4000 set_dst_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
), target
);
4002 if (final_dest
!= target
)
4003 emit_move_insn (final_dest
, target
);
4007 emit_libcall_block (rtx insns
, rtx target
, rtx result
, rtx equiv
)
4009 emit_libcall_block_1 (safe_as_a
<rtx_insn
*> (insns
),
4010 target
, result
, equiv
, false);
4013 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
4014 PURPOSE describes how this comparison will be used. CODE is the rtx
4015 comparison code we will be using.
4017 ??? Actually, CODE is slightly weaker than that. A target is still
4018 required to implement all of the normal bcc operations, but not
4019 required to implement all (or any) of the unordered bcc operations. */
4022 can_compare_p (enum rtx_code code
, enum machine_mode mode
,
4023 enum can_compare_purpose purpose
)
4026 test
= gen_rtx_fmt_ee (code
, mode
, const0_rtx
, const0_rtx
);
4029 enum insn_code icode
;
4031 if (purpose
== ccp_jump
4032 && (icode
= optab_handler (cbranch_optab
, mode
)) != CODE_FOR_nothing
4033 && insn_operand_matches (icode
, 0, test
))
4035 if (purpose
== ccp_store_flag
4036 && (icode
= optab_handler (cstore_optab
, mode
)) != CODE_FOR_nothing
4037 && insn_operand_matches (icode
, 1, test
))
4039 if (purpose
== ccp_cmov
4040 && optab_handler (cmov_optab
, mode
) != CODE_FOR_nothing
)
4043 mode
= GET_MODE_WIDER_MODE (mode
);
4044 PUT_MODE (test
, mode
);
4046 while (mode
!= VOIDmode
);
4051 /* This function is called when we are going to emit a compare instruction that
4052 compares the values found in *PX and *PY, using the rtl operator COMPARISON.
4054 *PMODE is the mode of the inputs (in case they are const_int).
4055 *PUNSIGNEDP nonzero says that the operands are unsigned;
4056 this matters if they need to be widened (as given by METHODS).
4058 If they have mode BLKmode, then SIZE specifies the size of both operands.
4060 This function performs all the setup necessary so that the caller only has
4061 to emit a single comparison insn. This setup can involve doing a BLKmode
4062 comparison or emitting a library call to perform the comparison if no insn
4063 is available to handle it.
4064 The values which are passed in through pointers can be modified; the caller
4065 should perform the comparison on the modified values. Constant
4066 comparisons must have already been folded. */
4069 prepare_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4070 int unsignedp
, enum optab_methods methods
,
4071 rtx
*ptest
, enum machine_mode
*pmode
)
4073 enum machine_mode mode
= *pmode
;
4075 enum machine_mode cmp_mode
;
4076 enum mode_class mclass
;
4078 /* The other methods are not needed. */
4079 gcc_assert (methods
== OPTAB_DIRECT
|| methods
== OPTAB_WIDEN
4080 || methods
== OPTAB_LIB_WIDEN
);
4082 /* If we are optimizing, force expensive constants into a register. */
4083 if (CONSTANT_P (x
) && optimize
4084 && (rtx_cost (x
, COMPARE
, 0, optimize_insn_for_speed_p ())
4085 > COSTS_N_INSNS (1)))
4086 x
= force_reg (mode
, x
);
4088 if (CONSTANT_P (y
) && optimize
4089 && (rtx_cost (y
, COMPARE
, 1, optimize_insn_for_speed_p ())
4090 > COSTS_N_INSNS (1)))
4091 y
= force_reg (mode
, y
);
4094 /* Make sure if we have a canonical comparison. The RTL
4095 documentation states that canonical comparisons are required only
4096 for targets which have cc0. */
4097 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
4100 /* Don't let both operands fail to indicate the mode. */
4101 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
4102 x
= force_reg (mode
, x
);
4103 if (mode
== VOIDmode
)
4104 mode
= GET_MODE (x
) != VOIDmode
? GET_MODE (x
) : GET_MODE (y
);
4106 /* Handle all BLKmode compares. */
4108 if (mode
== BLKmode
)
4110 enum machine_mode result_mode
;
4111 enum insn_code cmp_code
;
4116 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
4120 /* Try to use a memory block compare insn - either cmpstr
4121 or cmpmem will do. */
4122 for (cmp_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
4123 cmp_mode
!= VOIDmode
;
4124 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
))
4126 cmp_code
= direct_optab_handler (cmpmem_optab
, cmp_mode
);
4127 if (cmp_code
== CODE_FOR_nothing
)
4128 cmp_code
= direct_optab_handler (cmpstr_optab
, cmp_mode
);
4129 if (cmp_code
== CODE_FOR_nothing
)
4130 cmp_code
= direct_optab_handler (cmpstrn_optab
, cmp_mode
);
4131 if (cmp_code
== CODE_FOR_nothing
)
4134 /* Must make sure the size fits the insn's mode. */
4135 if ((CONST_INT_P (size
)
4136 && INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
)))
4137 || (GET_MODE_BITSIZE (GET_MODE (size
))
4138 > GET_MODE_BITSIZE (cmp_mode
)))
4141 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
4142 result
= gen_reg_rtx (result_mode
);
4143 size
= convert_to_mode (cmp_mode
, size
, 1);
4144 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
4146 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, result
, const0_rtx
);
4147 *pmode
= result_mode
;
4151 if (methods
!= OPTAB_LIB
&& methods
!= OPTAB_LIB_WIDEN
)
4154 /* Otherwise call a library function, memcmp. */
4155 libfunc
= memcmp_libfunc
;
4156 length_type
= sizetype
;
4157 result_mode
= TYPE_MODE (integer_type_node
);
4158 cmp_mode
= TYPE_MODE (length_type
);
4159 size
= convert_to_mode (TYPE_MODE (length_type
), size
,
4160 TYPE_UNSIGNED (length_type
));
4162 result
= emit_library_call_value (libfunc
, 0, LCT_PURE
,
4170 methods
= OPTAB_LIB_WIDEN
;
4174 /* Don't allow operands to the compare to trap, as that can put the
4175 compare and branch in different basic blocks. */
4176 if (cfun
->can_throw_non_call_exceptions
)
4179 x
= force_reg (mode
, x
);
4181 y
= force_reg (mode
, y
);
4184 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4186 gcc_assert (can_compare_p (comparison
, CCmode
, ccp_jump
));
4187 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4191 mclass
= GET_MODE_CLASS (mode
);
4192 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4196 enum insn_code icode
;
4197 icode
= optab_handler (cbranch_optab
, cmp_mode
);
4198 if (icode
!= CODE_FOR_nothing
4199 && insn_operand_matches (icode
, 0, test
))
4201 rtx_insn
*last
= get_last_insn ();
4202 rtx op0
= prepare_operand (icode
, x
, 1, mode
, cmp_mode
, unsignedp
);
4203 rtx op1
= prepare_operand (icode
, y
, 2, mode
, cmp_mode
, unsignedp
);
4205 && insn_operand_matches (icode
, 1, op0
)
4206 && insn_operand_matches (icode
, 2, op1
))
4208 XEXP (test
, 0) = op0
;
4209 XEXP (test
, 1) = op1
;
4214 delete_insns_since (last
);
4217 if (methods
== OPTAB_DIRECT
|| !CLASS_HAS_WIDER_MODES_P (mclass
))
4219 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
);
4221 while (cmp_mode
!= VOIDmode
);
4223 if (methods
!= OPTAB_LIB_WIDEN
)
4226 if (!SCALAR_FLOAT_MODE_P (mode
))
4229 enum machine_mode ret_mode
;
4231 /* Handle a libcall just for the mode we are using. */
4232 libfunc
= optab_libfunc (cmp_optab
, mode
);
4233 gcc_assert (libfunc
);
4235 /* If we want unsigned, and this mode has a distinct unsigned
4236 comparison routine, use that. */
4239 rtx ulibfunc
= optab_libfunc (ucmp_optab
, mode
);
4244 ret_mode
= targetm
.libgcc_cmp_return_mode ();
4245 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4246 ret_mode
, 2, x
, mode
, y
, mode
);
4248 /* There are two kinds of comparison routines. Biased routines
4249 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4250 of gcc expect that the comparison operation is equivalent
4251 to the modified comparison. For signed comparisons compare the
4252 result against 1 in the biased case, and zero in the unbiased
4253 case. For unsigned comparisons always compare against 1 after
4254 biasing the unbiased result by adding 1. This gives us a way to
4256 The comparisons in the fixed-point helper library are always
4261 if (!TARGET_LIB_INT_CMP_BIASED
&& !ALL_FIXED_POINT_MODE_P (mode
))
4264 x
= plus_constant (ret_mode
, result
, 1);
4270 prepare_cmp_insn (x
, y
, comparison
, NULL_RTX
, unsignedp
, methods
,
4274 prepare_float_lib_cmp (x
, y
, comparison
, ptest
, pmode
);
4282 /* Before emitting an insn with code ICODE, make sure that X, which is going
4283 to be used for operand OPNUM of the insn, is converted from mode MODE to
4284 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4285 that it is accepted by the operand predicate. Return the new value. */
4288 prepare_operand (enum insn_code icode
, rtx x
, int opnum
, enum machine_mode mode
,
4289 enum machine_mode wider_mode
, int unsignedp
)
4291 if (mode
!= wider_mode
)
4292 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
4294 if (!insn_operand_matches (icode
, opnum
, x
))
4296 if (reload_completed
)
4298 x
= copy_to_mode_reg (insn_data
[(int) icode
].operand
[opnum
].mode
, x
);
4304 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4305 we can do the branch. */
4308 emit_cmp_and_jump_insn_1 (rtx test
, enum machine_mode mode
, rtx label
, int prob
)
4310 enum machine_mode optab_mode
;
4311 enum mode_class mclass
;
4312 enum insn_code icode
;
4315 mclass
= GET_MODE_CLASS (mode
);
4316 optab_mode
= (mclass
== MODE_CC
) ? CCmode
: mode
;
4317 icode
= optab_handler (cbranch_optab
, optab_mode
);
4319 gcc_assert (icode
!= CODE_FOR_nothing
);
4320 gcc_assert (insn_operand_matches (icode
, 0, test
));
4321 insn
= emit_jump_insn (GEN_FCN (icode
) (test
, XEXP (test
, 0),
4322 XEXP (test
, 1), label
));
4324 && profile_status_for_fn (cfun
) != PROFILE_ABSENT
4327 && any_condjump_p (insn
)
4328 && !find_reg_note (insn
, REG_BR_PROB
, 0))
4329 add_int_reg_note (insn
, REG_BR_PROB
, prob
);
4332 /* Generate code to compare X with Y so that the condition codes are
4333 set and to jump to LABEL if the condition is true. If X is a
4334 constant and Y is not a constant, then the comparison is swapped to
4335 ensure that the comparison RTL has the canonical form.
4337 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4338 need to be widened. UNSIGNEDP is also used to select the proper
4339 branch condition code.
4341 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4343 MODE is the mode of the inputs (in case they are const_int).
4345 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4346 It will be potentially converted into an unsigned variant based on
4347 UNSIGNEDP to select a proper jump instruction.
4349 PROB is the probability of jumping to LABEL. */
4352 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4353 enum machine_mode mode
, int unsignedp
, rtx label
,
4356 rtx op0
= x
, op1
= y
;
4359 /* Swap operands and condition to ensure canonical RTL. */
4360 if (swap_commutative_operands_p (x
, y
)
4361 && can_compare_p (swap_condition (comparison
), mode
, ccp_jump
))
4364 comparison
= swap_condition (comparison
);
4367 /* If OP0 is still a constant, then both X and Y must be constants
4368 or the opposite comparison is not supported. Force X into a register
4369 to create canonical RTL. */
4370 if (CONSTANT_P (op0
))
4371 op0
= force_reg (mode
, op0
);
4374 comparison
= unsigned_condition (comparison
);
4376 prepare_cmp_insn (op0
, op1
, comparison
, size
, unsignedp
, OPTAB_LIB_WIDEN
,
4378 emit_cmp_and_jump_insn_1 (test
, mode
, label
, prob
);
4382 /* Emit a library call comparison between floating point X and Y.
4383 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4386 prepare_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
,
4387 rtx
*ptest
, enum machine_mode
*pmode
)
4389 enum rtx_code swapped
= swap_condition (comparison
);
4390 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
4391 enum machine_mode orig_mode
= GET_MODE (x
);
4392 enum machine_mode mode
, cmp_mode
;
4393 rtx true_rtx
, false_rtx
;
4394 rtx value
, target
, equiv
;
4397 bool reversed_p
= false;
4398 cmp_mode
= targetm
.libgcc_cmp_return_mode ();
4400 for (mode
= orig_mode
;
4402 mode
= GET_MODE_WIDER_MODE (mode
))
4404 if (code_to_optab (comparison
)
4405 && (libfunc
= optab_libfunc (code_to_optab (comparison
), mode
)))
4408 if (code_to_optab (swapped
)
4409 && (libfunc
= optab_libfunc (code_to_optab (swapped
), mode
)))
4412 tmp
= x
; x
= y
; y
= tmp
;
4413 comparison
= swapped
;
4417 if (code_to_optab (reversed
)
4418 && (libfunc
= optab_libfunc (code_to_optab (reversed
), mode
)))
4420 comparison
= reversed
;
4426 gcc_assert (mode
!= VOIDmode
);
4428 if (mode
!= orig_mode
)
4430 x
= convert_to_mode (mode
, x
, 0);
4431 y
= convert_to_mode (mode
, y
, 0);
4434 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4435 the RTL. The allows the RTL optimizers to delete the libcall if the
4436 condition can be determined at compile-time. */
4437 if (comparison
== UNORDERED
4438 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4440 true_rtx
= const_true_rtx
;
4441 false_rtx
= const0_rtx
;
4448 true_rtx
= const0_rtx
;
4449 false_rtx
= const_true_rtx
;
4453 true_rtx
= const_true_rtx
;
4454 false_rtx
= const0_rtx
;
4458 true_rtx
= const1_rtx
;
4459 false_rtx
= const0_rtx
;
4463 true_rtx
= const0_rtx
;
4464 false_rtx
= constm1_rtx
;
4468 true_rtx
= constm1_rtx
;
4469 false_rtx
= const0_rtx
;
4473 true_rtx
= const0_rtx
;
4474 false_rtx
= const1_rtx
;
4482 if (comparison
== UNORDERED
)
4484 rtx temp
= simplify_gen_relational (NE
, cmp_mode
, mode
, x
, x
);
4485 equiv
= simplify_gen_relational (NE
, cmp_mode
, mode
, y
, y
);
4486 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4487 temp
, const_true_rtx
, equiv
);
4491 equiv
= simplify_gen_relational (comparison
, cmp_mode
, mode
, x
, y
);
4492 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4493 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4494 equiv
, true_rtx
, false_rtx
);
4498 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4499 cmp_mode
, 2, x
, mode
, y
, mode
);
4500 insns
= get_insns ();
4503 target
= gen_reg_rtx (cmp_mode
);
4504 emit_libcall_block (insns
, target
, value
, equiv
);
4506 if (comparison
== UNORDERED
4507 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
)
4509 *ptest
= gen_rtx_fmt_ee (reversed_p
? EQ
: NE
, VOIDmode
, target
, false_rtx
);
4511 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, target
, const0_rtx
);
4516 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4519 emit_indirect_jump (rtx loc
)
4521 struct expand_operand ops
[1];
4523 create_address_operand (&ops
[0], loc
);
4524 expand_jump_insn (CODE_FOR_indirect_jump
, 1, ops
);
4528 #ifdef HAVE_conditional_move
4530 /* Emit a conditional move instruction if the machine supports one for that
4531 condition and machine mode.
4533 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4534 the mode to use should they be constants. If it is VOIDmode, they cannot
4537 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4538 should be stored there. MODE is the mode to use should they be constants.
4539 If it is VOIDmode, they cannot both be constants.
4541 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4542 is not supported. */
4545 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4546 enum machine_mode cmode
, rtx op2
, rtx op3
,
4547 enum machine_mode mode
, int unsignedp
)
4549 rtx tem
, comparison
;
4551 enum insn_code icode
;
4552 enum rtx_code reversed
;
4554 /* If one operand is constant, make it the second one. Only do this
4555 if the other operand is not constant as well. */
4557 if (swap_commutative_operands_p (op0
, op1
))
4562 code
= swap_condition (code
);
4565 /* get_condition will prefer to generate LT and GT even if the old
4566 comparison was against zero, so undo that canonicalization here since
4567 comparisons against zero are cheaper. */
4568 if (code
== LT
&& op1
== const1_rtx
)
4569 code
= LE
, op1
= const0_rtx
;
4570 else if (code
== GT
&& op1
== constm1_rtx
)
4571 code
= GE
, op1
= const0_rtx
;
4573 if (cmode
== VOIDmode
)
4574 cmode
= GET_MODE (op0
);
4576 if (swap_commutative_operands_p (op2
, op3
)
4577 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4586 if (mode
== VOIDmode
)
4587 mode
= GET_MODE (op2
);
4589 icode
= direct_optab_handler (movcc_optab
, mode
);
4591 if (icode
== CODE_FOR_nothing
)
4595 target
= gen_reg_rtx (mode
);
4597 code
= unsignedp
? unsigned_condition (code
) : code
;
4598 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4600 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4601 return NULL and let the caller figure out how best to deal with this
4603 if (!COMPARISON_P (comparison
))
4606 saved_pending_stack_adjust save
;
4607 save_pending_stack_adjust (&save
);
4608 last
= get_last_insn ();
4609 do_pending_stack_adjust ();
4610 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4611 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4612 &comparison
, &cmode
);
4615 struct expand_operand ops
[4];
4617 create_output_operand (&ops
[0], target
, mode
);
4618 create_fixed_operand (&ops
[1], comparison
);
4619 create_input_operand (&ops
[2], op2
, mode
);
4620 create_input_operand (&ops
[3], op3
, mode
);
4621 if (maybe_expand_insn (icode
, 4, ops
))
4623 if (ops
[0].value
!= target
)
4624 convert_move (target
, ops
[0].value
, false);
4628 delete_insns_since (last
);
4629 restore_pending_stack_adjust (&save
);
4633 /* Return nonzero if a conditional move of mode MODE is supported.
4635 This function is for combine so it can tell whether an insn that looks
4636 like a conditional move is actually supported by the hardware. If we
4637 guess wrong we lose a bit on optimization, but that's it. */
4638 /* ??? sparc64 supports conditionally moving integers values based on fp
4639 comparisons, and vice versa. How do we handle them? */
4642 can_conditionally_move_p (enum machine_mode mode
)
4644 if (direct_optab_handler (movcc_optab
, mode
) != CODE_FOR_nothing
)
4650 #endif /* HAVE_conditional_move */
4652 /* Emit a conditional addition instruction if the machine supports one for that
4653 condition and machine mode.
4655 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4656 the mode to use should they be constants. If it is VOIDmode, they cannot
4659 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
4660 should be stored there. MODE is the mode to use should they be constants.
4661 If it is VOIDmode, they cannot both be constants.
4663 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4664 is not supported. */
4667 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4668 enum machine_mode cmode
, rtx op2
, rtx op3
,
4669 enum machine_mode mode
, int unsignedp
)
4671 rtx tem
, comparison
;
4673 enum insn_code icode
;
4675 /* If one operand is constant, make it the second one. Only do this
4676 if the other operand is not constant as well. */
4678 if (swap_commutative_operands_p (op0
, op1
))
4683 code
= swap_condition (code
);
4686 /* get_condition will prefer to generate LT and GT even if the old
4687 comparison was against zero, so undo that canonicalization here since
4688 comparisons against zero are cheaper. */
4689 if (code
== LT
&& op1
== const1_rtx
)
4690 code
= LE
, op1
= const0_rtx
;
4691 else if (code
== GT
&& op1
== constm1_rtx
)
4692 code
= GE
, op1
= const0_rtx
;
4694 if (cmode
== VOIDmode
)
4695 cmode
= GET_MODE (op0
);
4697 if (mode
== VOIDmode
)
4698 mode
= GET_MODE (op2
);
4700 icode
= optab_handler (addcc_optab
, mode
);
4702 if (icode
== CODE_FOR_nothing
)
4706 target
= gen_reg_rtx (mode
);
4708 code
= unsignedp
? unsigned_condition (code
) : code
;
4709 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4711 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4712 return NULL and let the caller figure out how best to deal with this
4714 if (!COMPARISON_P (comparison
))
4717 do_pending_stack_adjust ();
4718 last
= get_last_insn ();
4719 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4720 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4721 &comparison
, &cmode
);
4724 struct expand_operand ops
[4];
4726 create_output_operand (&ops
[0], target
, mode
);
4727 create_fixed_operand (&ops
[1], comparison
);
4728 create_input_operand (&ops
[2], op2
, mode
);
4729 create_input_operand (&ops
[3], op3
, mode
);
4730 if (maybe_expand_insn (icode
, 4, ops
))
4732 if (ops
[0].value
!= target
)
4733 convert_move (target
, ops
[0].value
, false);
4737 delete_insns_since (last
);
4741 /* These functions attempt to generate an insn body, rather than
4742 emitting the insn, but if the gen function already emits them, we
4743 make no attempt to turn them back into naked patterns. */
4745 /* Generate and return an insn body to add Y to X. */
4748 gen_add2_insn (rtx x
, rtx y
)
4750 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (x
));
4752 gcc_assert (insn_operand_matches (icode
, 0, x
));
4753 gcc_assert (insn_operand_matches (icode
, 1, x
));
4754 gcc_assert (insn_operand_matches (icode
, 2, y
));
4756 return GEN_FCN (icode
) (x
, x
, y
);
4759 /* Generate and return an insn body to add r1 and c,
4760 storing the result in r0. */
4763 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4765 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (r0
));
4767 if (icode
== CODE_FOR_nothing
4768 || !insn_operand_matches (icode
, 0, r0
)
4769 || !insn_operand_matches (icode
, 1, r1
)
4770 || !insn_operand_matches (icode
, 2, c
))
4773 return GEN_FCN (icode
) (r0
, r1
, c
);
4777 have_add2_insn (rtx x
, rtx y
)
4779 enum insn_code icode
;
4781 gcc_assert (GET_MODE (x
) != VOIDmode
);
4783 icode
= optab_handler (add_optab
, GET_MODE (x
));
4785 if (icode
== CODE_FOR_nothing
)
4788 if (!insn_operand_matches (icode
, 0, x
)
4789 || !insn_operand_matches (icode
, 1, x
)
4790 || !insn_operand_matches (icode
, 2, y
))
4796 /* Generate and return an insn body to add Y to X. */
4799 gen_addptr3_insn (rtx x
, rtx y
, rtx z
)
4801 enum insn_code icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4803 gcc_assert (insn_operand_matches (icode
, 0, x
));
4804 gcc_assert (insn_operand_matches (icode
, 1, y
));
4805 gcc_assert (insn_operand_matches (icode
, 2, z
));
4807 return GEN_FCN (icode
) (x
, y
, z
);
4810 /* Return true if the target implements an addptr pattern and X, Y,
4811 and Z are valid for the pattern predicates. */
4814 have_addptr3_insn (rtx x
, rtx y
, rtx z
)
4816 enum insn_code icode
;
4818 gcc_assert (GET_MODE (x
) != VOIDmode
);
4820 icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4822 if (icode
== CODE_FOR_nothing
)
4825 if (!insn_operand_matches (icode
, 0, x
)
4826 || !insn_operand_matches (icode
, 1, y
)
4827 || !insn_operand_matches (icode
, 2, z
))
4833 /* Generate and return an insn body to subtract Y from X. */
4836 gen_sub2_insn (rtx x
, rtx y
)
4838 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (x
));
4840 gcc_assert (insn_operand_matches (icode
, 0, x
));
4841 gcc_assert (insn_operand_matches (icode
, 1, x
));
4842 gcc_assert (insn_operand_matches (icode
, 2, y
));
4844 return GEN_FCN (icode
) (x
, x
, y
);
4847 /* Generate and return an insn body to subtract r1 and c,
4848 storing the result in r0. */
4851 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4853 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (r0
));
4855 if (icode
== CODE_FOR_nothing
4856 || !insn_operand_matches (icode
, 0, r0
)
4857 || !insn_operand_matches (icode
, 1, r1
)
4858 || !insn_operand_matches (icode
, 2, c
))
4861 return GEN_FCN (icode
) (r0
, r1
, c
);
4865 have_sub2_insn (rtx x
, rtx y
)
4867 enum insn_code icode
;
4869 gcc_assert (GET_MODE (x
) != VOIDmode
);
4871 icode
= optab_handler (sub_optab
, GET_MODE (x
));
4873 if (icode
== CODE_FOR_nothing
)
4876 if (!insn_operand_matches (icode
, 0, x
)
4877 || !insn_operand_matches (icode
, 1, x
)
4878 || !insn_operand_matches (icode
, 2, y
))
4884 /* Generate the body of an instruction to copy Y into X.
4885 It may be a list of insns, if one insn isn't enough. */
4888 gen_move_insn (rtx x
, rtx y
)
4893 emit_move_insn_1 (x
, y
);
4899 /* Return the insn code used to extend FROM_MODE to TO_MODE.
4900 UNSIGNEDP specifies zero-extension instead of sign-extension. If
4901 no such operation exists, CODE_FOR_nothing will be returned. */
4904 can_extend_p (enum machine_mode to_mode
, enum machine_mode from_mode
,
4908 #ifdef HAVE_ptr_extend
4910 return CODE_FOR_ptr_extend
;
4913 tab
= unsignedp
? zext_optab
: sext_optab
;
4914 return convert_optab_handler (tab
, to_mode
, from_mode
);
4917 /* Generate the body of an insn to extend Y (with mode MFROM)
4918 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4921 gen_extend_insn (rtx x
, rtx y
, enum machine_mode mto
,
4922 enum machine_mode mfrom
, int unsignedp
)
4924 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4925 return GEN_FCN (icode
) (x
, y
);
4928 /* can_fix_p and can_float_p say whether the target machine
4929 can directly convert a given fixed point type to
4930 a given floating point type, or vice versa.
4931 The returned value is the CODE_FOR_... value to use,
4932 or CODE_FOR_nothing if these modes cannot be directly converted.
4934 *TRUNCP_PTR is set to 1 if it is necessary to output
4935 an explicit FTRUNC insn before the fix insn; otherwise 0. */
4937 static enum insn_code
4938 can_fix_p (enum machine_mode fixmode
, enum machine_mode fltmode
,
4939 int unsignedp
, int *truncp_ptr
)
4942 enum insn_code icode
;
4944 tab
= unsignedp
? ufixtrunc_optab
: sfixtrunc_optab
;
4945 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4946 if (icode
!= CODE_FOR_nothing
)
4952 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
4953 for this to work. We need to rework the fix* and ftrunc* patterns
4954 and documentation. */
4955 tab
= unsignedp
? ufix_optab
: sfix_optab
;
4956 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4957 if (icode
!= CODE_FOR_nothing
4958 && optab_handler (ftrunc_optab
, fltmode
) != CODE_FOR_nothing
)
4965 return CODE_FOR_nothing
;
4969 can_float_p (enum machine_mode fltmode
, enum machine_mode fixmode
,
4974 tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4975 return convert_optab_handler (tab
, fltmode
, fixmode
);
4978 /* Function supportable_convert_operation
4980 Check whether an operation represented by the code CODE is a
4981 convert operation that is supported by the target platform in
4982 vector form (i.e., when operating on arguments of type VECTYPE_IN
4983 producing a result of type VECTYPE_OUT).
4985 Convert operations we currently support directly are FIX_TRUNC and FLOAT.
4986 This function checks if these operations are supported
4987 by the target platform either directly (via vector tree-codes), or via
4991 - CODE1 is code of vector operation to be used when
4992 vectorizing the operation, if available.
4993 - DECL is decl of target builtin functions to be used
4994 when vectorizing the operation, if available. In this case,
4995 CODE1 is CALL_EXPR. */
4998 supportable_convert_operation (enum tree_code code
,
4999 tree vectype_out
, tree vectype_in
,
5000 tree
*decl
, enum tree_code
*code1
)
5002 enum machine_mode m1
,m2
;
5005 m1
= TYPE_MODE (vectype_out
);
5006 m2
= TYPE_MODE (vectype_in
);
5008 /* First check if we can done conversion directly. */
5009 if ((code
== FIX_TRUNC_EXPR
5010 && can_fix_p (m1
,m2
,TYPE_UNSIGNED (vectype_out
), &truncp
)
5011 != CODE_FOR_nothing
)
5012 || (code
== FLOAT_EXPR
5013 && can_float_p (m1
,m2
,TYPE_UNSIGNED (vectype_in
))
5014 != CODE_FOR_nothing
))
5020 /* Now check for builtin. */
5021 if (targetm
.vectorize
.builtin_conversion
5022 && targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
))
5025 *decl
= targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
);
5032 /* Generate code to convert FROM to floating point
5033 and store in TO. FROM must be fixed point and not VOIDmode.
5034 UNSIGNEDP nonzero means regard FROM as unsigned.
5035 Normally this is done by correcting the final value
5036 if it is negative. */
5039 expand_float (rtx to
, rtx from
, int unsignedp
)
5041 enum insn_code icode
;
5043 enum machine_mode fmode
, imode
;
5044 bool can_do_signed
= false;
5046 /* Crash now, because we won't be able to decide which mode to use. */
5047 gcc_assert (GET_MODE (from
) != VOIDmode
);
5049 /* Look for an insn to do the conversion. Do it in the specified
5050 modes if possible; otherwise convert either input, output or both to
5051 wider mode. If the integer mode is wider than the mode of FROM,
5052 we can do the conversion signed even if the input is unsigned. */
5054 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5055 fmode
= GET_MODE_WIDER_MODE (fmode
))
5056 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
5057 imode
= GET_MODE_WIDER_MODE (imode
))
5059 int doing_unsigned
= unsignedp
;
5061 if (fmode
!= GET_MODE (to
)
5062 && significand_size (fmode
) < GET_MODE_PRECISION (GET_MODE (from
)))
5065 icode
= can_float_p (fmode
, imode
, unsignedp
);
5066 if (icode
== CODE_FOR_nothing
&& unsignedp
)
5068 enum insn_code scode
= can_float_p (fmode
, imode
, 0);
5069 if (scode
!= CODE_FOR_nothing
)
5070 can_do_signed
= true;
5071 if (imode
!= GET_MODE (from
))
5072 icode
= scode
, doing_unsigned
= 0;
5075 if (icode
!= CODE_FOR_nothing
)
5077 if (imode
!= GET_MODE (from
))
5078 from
= convert_to_mode (imode
, from
, unsignedp
);
5080 if (fmode
!= GET_MODE (to
))
5081 target
= gen_reg_rtx (fmode
);
5083 emit_unop_insn (icode
, target
, from
,
5084 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
5087 convert_move (to
, target
, 0);
5092 /* Unsigned integer, and no way to convert directly. Convert as signed,
5093 then unconditionally adjust the result. */
5094 if (unsignedp
&& can_do_signed
)
5096 rtx_code_label
*label
= gen_label_rtx ();
5098 REAL_VALUE_TYPE offset
;
5100 /* Look for a usable floating mode FMODE wider than the source and at
5101 least as wide as the target. Using FMODE will avoid rounding woes
5102 with unsigned values greater than the signed maximum value. */
5104 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5105 fmode
= GET_MODE_WIDER_MODE (fmode
))
5106 if (GET_MODE_PRECISION (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
5107 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
5110 if (fmode
== VOIDmode
)
5112 /* There is no such mode. Pretend the target is wide enough. */
5113 fmode
= GET_MODE (to
);
5115 /* Avoid double-rounding when TO is narrower than FROM. */
5116 if ((significand_size (fmode
) + 1)
5117 < GET_MODE_PRECISION (GET_MODE (from
)))
5120 rtx_code_label
*neglabel
= gen_label_rtx ();
5122 /* Don't use TARGET if it isn't a register, is a hard register,
5123 or is the wrong mode. */
5125 || REGNO (target
) < FIRST_PSEUDO_REGISTER
5126 || GET_MODE (target
) != fmode
)
5127 target
= gen_reg_rtx (fmode
);
5129 imode
= GET_MODE (from
);
5130 do_pending_stack_adjust ();
5132 /* Test whether the sign bit is set. */
5133 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
5136 /* The sign bit is not set. Convert as signed. */
5137 expand_float (target
, from
, 0);
5138 emit_jump_insn (gen_jump (label
));
5141 /* The sign bit is set.
5142 Convert to a usable (positive signed) value by shifting right
5143 one bit, while remembering if a nonzero bit was shifted
5144 out; i.e., compute (from & 1) | (from >> 1). */
5146 emit_label (neglabel
);
5147 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
5148 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
5149 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, 1, NULL_RTX
, 1);
5150 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
5152 expand_float (target
, temp
, 0);
5154 /* Multiply by 2 to undo the shift above. */
5155 temp
= expand_binop (fmode
, add_optab
, target
, target
,
5156 target
, 0, OPTAB_LIB_WIDEN
);
5158 emit_move_insn (target
, temp
);
5160 do_pending_stack_adjust ();
5166 /* If we are about to do some arithmetic to correct for an
5167 unsigned operand, do it in a pseudo-register. */
5169 if (GET_MODE (to
) != fmode
5170 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
5171 target
= gen_reg_rtx (fmode
);
5173 /* Convert as signed integer to floating. */
5174 expand_float (target
, from
, 0);
5176 /* If FROM is negative (and therefore TO is negative),
5177 correct its value by 2**bitwidth. */
5179 do_pending_stack_adjust ();
5180 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
),
5184 real_2expN (&offset
, GET_MODE_PRECISION (GET_MODE (from
)), fmode
);
5185 temp
= expand_binop (fmode
, add_optab
, target
,
5186 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
5187 target
, 0, OPTAB_LIB_WIDEN
);
5189 emit_move_insn (target
, temp
);
5191 do_pending_stack_adjust ();
5196 /* No hardware instruction available; call a library routine. */
5201 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
5203 if (GET_MODE_SIZE (GET_MODE (from
)) < GET_MODE_SIZE (SImode
))
5204 from
= convert_to_mode (SImode
, from
, unsignedp
);
5206 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5207 gcc_assert (libfunc
);
5211 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5212 GET_MODE (to
), 1, from
,
5214 insns
= get_insns ();
5217 emit_libcall_block (insns
, target
, value
,
5218 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FLOAT
: FLOAT
,
5219 GET_MODE (to
), from
));
5224 /* Copy result to requested destination
5225 if we have been computing in a temp location. */
5229 if (GET_MODE (target
) == GET_MODE (to
))
5230 emit_move_insn (to
, target
);
5232 convert_move (to
, target
, 0);
5236 /* Generate code to convert FROM to fixed point and store in TO. FROM
5237 must be floating point. */
5240 expand_fix (rtx to
, rtx from
, int unsignedp
)
5242 enum insn_code icode
;
5244 enum machine_mode fmode
, imode
;
5247 /* We first try to find a pair of modes, one real and one integer, at
5248 least as wide as FROM and TO, respectively, in which we can open-code
5249 this conversion. If the integer mode is wider than the mode of TO,
5250 we can do the conversion either signed or unsigned. */
5252 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5253 fmode
= GET_MODE_WIDER_MODE (fmode
))
5254 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5255 imode
= GET_MODE_WIDER_MODE (imode
))
5257 int doing_unsigned
= unsignedp
;
5259 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
5260 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
5261 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
5263 if (icode
!= CODE_FOR_nothing
)
5265 rtx_insn
*last
= get_last_insn ();
5266 if (fmode
!= GET_MODE (from
))
5267 from
= convert_to_mode (fmode
, from
, 0);
5271 rtx temp
= gen_reg_rtx (GET_MODE (from
));
5272 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
5276 if (imode
!= GET_MODE (to
))
5277 target
= gen_reg_rtx (imode
);
5279 if (maybe_emit_unop_insn (icode
, target
, from
,
5280 doing_unsigned
? UNSIGNED_FIX
: FIX
))
5283 convert_move (to
, target
, unsignedp
);
5286 delete_insns_since (last
);
5290 /* For an unsigned conversion, there is one more way to do it.
5291 If we have a signed conversion, we generate code that compares
5292 the real value to the largest representable positive number. If if
5293 is smaller, the conversion is done normally. Otherwise, subtract
5294 one plus the highest signed number, convert, and add it back.
5296 We only need to check all real modes, since we know we didn't find
5297 anything with a wider integer mode.
5299 This code used to extend FP value into mode wider than the destination.
5300 This is needed for decimal float modes which cannot accurately
5301 represent one plus the highest signed number of the same size, but
5302 not for binary modes. Consider, for instance conversion from SFmode
5305 The hot path through the code is dealing with inputs smaller than 2^63
5306 and doing just the conversion, so there is no bits to lose.
5308 In the other path we know the value is positive in the range 2^63..2^64-1
5309 inclusive. (as for other input overflow happens and result is undefined)
5310 So we know that the most important bit set in mantissa corresponds to
5311 2^63. The subtraction of 2^63 should not generate any rounding as it
5312 simply clears out that bit. The rest is trivial. */
5314 if (unsignedp
&& GET_MODE_PRECISION (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
5315 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5316 fmode
= GET_MODE_WIDER_MODE (fmode
))
5317 if (CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0, &must_trunc
)
5318 && (!DECIMAL_FLOAT_MODE_P (fmode
)
5319 || GET_MODE_BITSIZE (fmode
) > GET_MODE_PRECISION (GET_MODE (to
))))
5322 REAL_VALUE_TYPE offset
;
5324 rtx_code_label
*lab1
, *lab2
;
5327 bitsize
= GET_MODE_PRECISION (GET_MODE (to
));
5328 real_2expN (&offset
, bitsize
- 1, fmode
);
5329 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
5330 lab1
= gen_label_rtx ();
5331 lab2
= gen_label_rtx ();
5333 if (fmode
!= GET_MODE (from
))
5334 from
= convert_to_mode (fmode
, from
, 0);
5336 /* See if we need to do the subtraction. */
5337 do_pending_stack_adjust ();
5338 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
),
5341 /* If not, do the signed "fix" and branch around fixup code. */
5342 expand_fix (to
, from
, 0);
5343 emit_jump_insn (gen_jump (lab2
));
5346 /* Otherwise, subtract 2**(N-1), convert to signed number,
5347 then add 2**(N-1). Do the addition using XOR since this
5348 will often generate better code. */
5350 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
5351 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
5352 expand_fix (to
, target
, 0);
5353 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
5355 ((HOST_WIDE_INT
) 1 << (bitsize
- 1),
5357 to
, 1, OPTAB_LIB_WIDEN
);
5360 emit_move_insn (to
, target
);
5364 if (optab_handler (mov_optab
, GET_MODE (to
)) != CODE_FOR_nothing
)
5366 /* Make a place for a REG_NOTE and add it. */
5367 insn
= emit_move_insn (to
, to
);
5368 set_dst_reg_note (insn
, REG_EQUAL
,
5369 gen_rtx_fmt_e (UNSIGNED_FIX
, GET_MODE (to
),
5377 /* We can't do it with an insn, so use a library call. But first ensure
5378 that the mode of TO is at least as wide as SImode, since those are the
5379 only library calls we know about. */
5381 if (GET_MODE_SIZE (GET_MODE (to
)) < GET_MODE_SIZE (SImode
))
5383 target
= gen_reg_rtx (SImode
);
5385 expand_fix (target
, from
, unsignedp
);
5393 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
5394 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5395 gcc_assert (libfunc
);
5399 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5400 GET_MODE (to
), 1, from
,
5402 insns
= get_insns ();
5405 emit_libcall_block (insns
, target
, value
,
5406 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
5407 GET_MODE (to
), from
));
5412 if (GET_MODE (to
) == GET_MODE (target
))
5413 emit_move_insn (to
, target
);
5415 convert_move (to
, target
, 0);
5419 /* Generate code to convert FROM or TO a fixed-point.
5420 If UINTP is true, either TO or FROM is an unsigned integer.
5421 If SATP is true, we need to saturate the result. */
5424 expand_fixed_convert (rtx to
, rtx from
, int uintp
, int satp
)
5426 enum machine_mode to_mode
= GET_MODE (to
);
5427 enum machine_mode from_mode
= GET_MODE (from
);
5429 enum rtx_code this_code
;
5430 enum insn_code code
;
5435 if (to_mode
== from_mode
)
5437 emit_move_insn (to
, from
);
5443 tab
= satp
? satfractuns_optab
: fractuns_optab
;
5444 this_code
= satp
? UNSIGNED_SAT_FRACT
: UNSIGNED_FRACT_CONVERT
;
5448 tab
= satp
? satfract_optab
: fract_optab
;
5449 this_code
= satp
? SAT_FRACT
: FRACT_CONVERT
;
5451 code
= convert_optab_handler (tab
, to_mode
, from_mode
);
5452 if (code
!= CODE_FOR_nothing
)
5454 emit_unop_insn (code
, to
, from
, this_code
);
5458 libfunc
= convert_optab_libfunc (tab
, to_mode
, from_mode
);
5459 gcc_assert (libfunc
);
5462 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, to_mode
,
5463 1, from
, from_mode
);
5464 insns
= get_insns ();
5467 emit_libcall_block (insns
, to
, value
,
5468 gen_rtx_fmt_e (optab_to_code (tab
), to_mode
, from
));
5471 /* Generate code to convert FROM to fixed point and store in TO. FROM
5472 must be floating point, TO must be signed. Use the conversion optab
5473 TAB to do the conversion. */
5476 expand_sfix_optab (rtx to
, rtx from
, convert_optab tab
)
5478 enum insn_code icode
;
5480 enum machine_mode fmode
, imode
;
5482 /* We first try to find a pair of modes, one real and one integer, at
5483 least as wide as FROM and TO, respectively, in which we can open-code
5484 this conversion. If the integer mode is wider than the mode of TO,
5485 we can do the conversion either signed or unsigned. */
5487 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5488 fmode
= GET_MODE_WIDER_MODE (fmode
))
5489 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5490 imode
= GET_MODE_WIDER_MODE (imode
))
5492 icode
= convert_optab_handler (tab
, imode
, fmode
);
5493 if (icode
!= CODE_FOR_nothing
)
5495 rtx_insn
*last
= get_last_insn ();
5496 if (fmode
!= GET_MODE (from
))
5497 from
= convert_to_mode (fmode
, from
, 0);
5499 if (imode
!= GET_MODE (to
))
5500 target
= gen_reg_rtx (imode
);
5502 if (!maybe_emit_unop_insn (icode
, target
, from
, UNKNOWN
))
5504 delete_insns_since (last
);
5508 convert_move (to
, target
, 0);
5516 /* Report whether we have an instruction to perform the operation
5517 specified by CODE on operands of mode MODE. */
5519 have_insn_for (enum rtx_code code
, enum machine_mode mode
)
5521 return (code_to_optab (code
)
5522 && (optab_handler (code_to_optab (code
), mode
)
5523 != CODE_FOR_nothing
));
5526 /* Initialize the libfunc fields of an entire group of entries in some
5527 optab. Each entry is set equal to a string consisting of a leading
5528 pair of underscores followed by a generic operation name followed by
5529 a mode name (downshifted to lowercase) followed by a single character
5530 representing the number of operands for the given operation (which is
5531 usually one of the characters '2', '3', or '4').
5533 OPTABLE is the table in which libfunc fields are to be initialized.
5534 OPNAME is the generic (string) name of the operation.
5535 SUFFIX is the character which specifies the number of operands for
5536 the given generic operation.
5537 MODE is the mode to generate for.
5541 gen_libfunc (optab optable
, const char *opname
, int suffix
,
5542 enum machine_mode mode
)
5544 unsigned opname_len
= strlen (opname
);
5545 const char *mname
= GET_MODE_NAME (mode
);
5546 unsigned mname_len
= strlen (mname
);
5547 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5548 int len
= prefix_len
+ opname_len
+ mname_len
+ 1 + 1;
5549 char *libfunc_name
= XALLOCAVEC (char, len
);
5556 if (targetm
.libfunc_gnu_prefix
)
5563 for (q
= opname
; *q
; )
5565 for (q
= mname
; *q
; q
++)
5566 *p
++ = TOLOWER (*q
);
5570 set_optab_libfunc (optable
, mode
,
5571 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5574 /* Like gen_libfunc, but verify that integer operation is involved. */
5577 gen_int_libfunc (optab optable
, const char *opname
, char suffix
,
5578 enum machine_mode mode
)
5580 int maxsize
= 2 * BITS_PER_WORD
;
5581 int minsize
= BITS_PER_WORD
;
5583 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5585 if (maxsize
< LONG_LONG_TYPE_SIZE
)
5586 maxsize
= LONG_LONG_TYPE_SIZE
;
5587 if (minsize
> INT_TYPE_SIZE
5588 && (trapv_binoptab_p (optable
)
5589 || trapv_unoptab_p (optable
)))
5590 minsize
= INT_TYPE_SIZE
;
5591 if (GET_MODE_BITSIZE (mode
) < minsize
5592 || GET_MODE_BITSIZE (mode
) > maxsize
)
5594 gen_libfunc (optable
, opname
, suffix
, mode
);
5597 /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */
5600 gen_fp_libfunc (optab optable
, const char *opname
, char suffix
,
5601 enum machine_mode mode
)
5605 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5606 gen_libfunc (optable
, opname
, suffix
, mode
);
5607 if (DECIMAL_FLOAT_MODE_P (mode
))
5609 dec_opname
= XALLOCAVEC (char, sizeof (DECIMAL_PREFIX
) + strlen (opname
));
5610 /* For BID support, change the name to have either a bid_ or dpd_ prefix
5611 depending on the low level floating format used. */
5612 memcpy (dec_opname
, DECIMAL_PREFIX
, sizeof (DECIMAL_PREFIX
) - 1);
5613 strcpy (dec_opname
+ sizeof (DECIMAL_PREFIX
) - 1, opname
);
5614 gen_libfunc (optable
, dec_opname
, suffix
, mode
);
5618 /* Like gen_libfunc, but verify that fixed-point operation is involved. */
5621 gen_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5622 enum machine_mode mode
)
5624 if (!ALL_FIXED_POINT_MODE_P (mode
))
5626 gen_libfunc (optable
, opname
, suffix
, mode
);
5629 /* Like gen_libfunc, but verify that signed fixed-point operation is
5633 gen_signed_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5634 enum machine_mode mode
)
5636 if (!SIGNED_FIXED_POINT_MODE_P (mode
))
5638 gen_libfunc (optable
, opname
, suffix
, mode
);
5641 /* Like gen_libfunc, but verify that unsigned fixed-point operation is
5645 gen_unsigned_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5646 enum machine_mode mode
)
5648 if (!UNSIGNED_FIXED_POINT_MODE_P (mode
))
5650 gen_libfunc (optable
, opname
, suffix
, mode
);
5653 /* Like gen_libfunc, but verify that FP or INT operation is involved. */
5656 gen_int_fp_libfunc (optab optable
, const char *name
, char suffix
,
5657 enum machine_mode mode
)
5659 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5660 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5661 if (INTEGRAL_MODE_P (mode
))
5662 gen_int_libfunc (optable
, name
, suffix
, mode
);
5665 /* Like gen_libfunc, but verify that FP or INT operation is involved
5666 and add 'v' suffix for integer operation. */
5669 gen_intv_fp_libfunc (optab optable
, const char *name
, char suffix
,
5670 enum machine_mode mode
)
5672 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5673 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5674 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5676 int len
= strlen (name
);
5677 char *v_name
= XALLOCAVEC (char, len
+ 2);
5678 strcpy (v_name
, name
);
5680 v_name
[len
+ 1] = 0;
5681 gen_int_libfunc (optable
, v_name
, suffix
, mode
);
5685 /* Like gen_libfunc, but verify that FP or INT or FIXED operation is
5689 gen_int_fp_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5690 enum machine_mode mode
)
5692 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5693 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5694 if (INTEGRAL_MODE_P (mode
))
5695 gen_int_libfunc (optable
, name
, suffix
, mode
);
5696 if (ALL_FIXED_POINT_MODE_P (mode
))
5697 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5700 /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is
5704 gen_int_fp_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5705 enum machine_mode mode
)
5707 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5708 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5709 if (INTEGRAL_MODE_P (mode
))
5710 gen_int_libfunc (optable
, name
, suffix
, mode
);
5711 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5712 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5715 /* Like gen_libfunc, but verify that INT or FIXED operation is
5719 gen_int_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5720 enum machine_mode mode
)
5722 if (INTEGRAL_MODE_P (mode
))
5723 gen_int_libfunc (optable
, name
, suffix
, mode
);
5724 if (ALL_FIXED_POINT_MODE_P (mode
))
5725 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5728 /* Like gen_libfunc, but verify that INT or signed FIXED operation is
5732 gen_int_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5733 enum machine_mode mode
)
5735 if (INTEGRAL_MODE_P (mode
))
5736 gen_int_libfunc (optable
, name
, suffix
, mode
);
5737 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5738 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5741 /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is
5745 gen_int_unsigned_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5746 enum machine_mode mode
)
5748 if (INTEGRAL_MODE_P (mode
))
5749 gen_int_libfunc (optable
, name
, suffix
, mode
);
5750 if (UNSIGNED_FIXED_POINT_MODE_P (mode
))
5751 gen_unsigned_fixed_libfunc (optable
, name
, suffix
, mode
);
5754 /* Initialize the libfunc fields of an entire group of entries of an
5755 inter-mode-class conversion optab. The string formation rules are
5756 similar to the ones for init_libfuncs, above, but instead of having
5757 a mode name and an operand count these functions have two mode names
5758 and no operand count. */
5761 gen_interclass_conv_libfunc (convert_optab tab
,
5763 enum machine_mode tmode
,
5764 enum machine_mode fmode
)
5766 size_t opname_len
= strlen (opname
);
5767 size_t mname_len
= 0;
5769 const char *fname
, *tname
;
5771 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5772 char *libfunc_name
, *suffix
;
5773 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5776 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5777 depends on which underlying decimal floating point format is used. */
5778 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5780 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5782 nondec_name
= XALLOCAVEC (char, prefix_len
+ opname_len
+ mname_len
+ 1 + 1);
5783 nondec_name
[0] = '_';
5784 nondec_name
[1] = '_';
5785 if (targetm
.libfunc_gnu_prefix
)
5787 nondec_name
[2] = 'g';
5788 nondec_name
[3] = 'n';
5789 nondec_name
[4] = 'u';
5790 nondec_name
[5] = '_';
5793 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5794 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5796 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5799 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5800 memcpy (&dec_name
[2+dec_len
], opname
, opname_len
);
5801 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5803 fname
= GET_MODE_NAME (fmode
);
5804 tname
= GET_MODE_NAME (tmode
);
5806 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5808 libfunc_name
= dec_name
;
5809 suffix
= dec_suffix
;
5813 libfunc_name
= nondec_name
;
5814 suffix
= nondec_suffix
;
5818 for (q
= fname
; *q
; p
++, q
++)
5820 for (q
= tname
; *q
; p
++, q
++)
5825 set_conv_libfunc (tab
, tmode
, fmode
,
5826 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5829 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5830 int->fp conversion. */
5833 gen_int_to_fp_conv_libfunc (convert_optab tab
,
5835 enum machine_mode tmode
,
5836 enum machine_mode fmode
)
5838 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5840 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5842 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5845 /* ufloat_optab is special by using floatun for FP and floatuns decimal fp
5849 gen_ufloat_conv_libfunc (convert_optab tab
,
5850 const char *opname ATTRIBUTE_UNUSED
,
5851 enum machine_mode tmode
,
5852 enum machine_mode fmode
)
5854 if (DECIMAL_FLOAT_MODE_P (tmode
))
5855 gen_int_to_fp_conv_libfunc (tab
, "floatuns", tmode
, fmode
);
5857 gen_int_to_fp_conv_libfunc (tab
, "floatun", tmode
, fmode
);
5860 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5861 fp->int conversion. */
5864 gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab
,
5866 enum machine_mode tmode
,
5867 enum machine_mode fmode
)
5869 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5871 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
)
5873 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5876 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5877 fp->int conversion with no decimal floating point involved. */
5880 gen_fp_to_int_conv_libfunc (convert_optab tab
,
5882 enum machine_mode tmode
,
5883 enum machine_mode fmode
)
5885 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5887 if (GET_MODE_CLASS (tmode
) != MODE_INT
)
5889 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5892 /* Initialize the libfunc fields of an of an intra-mode-class conversion optab.
5893 The string formation rules are
5894 similar to the ones for init_libfunc, above. */
5897 gen_intraclass_conv_libfunc (convert_optab tab
, const char *opname
,
5898 enum machine_mode tmode
, enum machine_mode fmode
)
5900 size_t opname_len
= strlen (opname
);
5901 size_t mname_len
= 0;
5903 const char *fname
, *tname
;
5905 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5906 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5907 char *libfunc_name
, *suffix
;
5910 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5911 depends on which underlying decimal floating point format is used. */
5912 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5914 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5916 nondec_name
= XALLOCAVEC (char, 2 + opname_len
+ mname_len
+ 1 + 1);
5917 nondec_name
[0] = '_';
5918 nondec_name
[1] = '_';
5919 if (targetm
.libfunc_gnu_prefix
)
5921 nondec_name
[2] = 'g';
5922 nondec_name
[3] = 'n';
5923 nondec_name
[4] = 'u';
5924 nondec_name
[5] = '_';
5926 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5927 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5929 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5932 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5933 memcpy (&dec_name
[2 + dec_len
], opname
, opname_len
);
5934 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5936 fname
= GET_MODE_NAME (fmode
);
5937 tname
= GET_MODE_NAME (tmode
);
5939 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5941 libfunc_name
= dec_name
;
5942 suffix
= dec_suffix
;
5946 libfunc_name
= nondec_name
;
5947 suffix
= nondec_suffix
;
5951 for (q
= fname
; *q
; p
++, q
++)
5953 for (q
= tname
; *q
; p
++, q
++)
5959 set_conv_libfunc (tab
, tmode
, fmode
,
5960 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5963 /* Pick proper libcall for trunc_optab. We need to chose if we do
5964 truncation or extension and interclass or intraclass. */
5967 gen_trunc_conv_libfunc (convert_optab tab
,
5969 enum machine_mode tmode
,
5970 enum machine_mode fmode
)
5972 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5974 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5979 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5980 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5981 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5983 if (GET_MODE_PRECISION (fmode
) <= GET_MODE_PRECISION (tmode
))
5986 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5987 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5988 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5989 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5992 /* Pick proper libcall for extend_optab. We need to chose if we do
5993 truncation or extension and interclass or intraclass. */
5996 gen_extend_conv_libfunc (convert_optab tab
,
5997 const char *opname ATTRIBUTE_UNUSED
,
5998 enum machine_mode tmode
,
5999 enum machine_mode fmode
)
6001 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
6003 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
6008 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
6009 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
6010 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6012 if (GET_MODE_PRECISION (fmode
) > GET_MODE_PRECISION (tmode
))
6015 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
6016 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
6017 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
6018 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6021 /* Pick proper libcall for fract_optab. We need to chose if we do
6022 interclass or intraclass. */
6025 gen_fract_conv_libfunc (convert_optab tab
,
6027 enum machine_mode tmode
,
6028 enum machine_mode fmode
)
6032 if (!(ALL_FIXED_POINT_MODE_P (tmode
) || ALL_FIXED_POINT_MODE_P (fmode
)))
6035 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
6036 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6038 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6041 /* Pick proper libcall for fractuns_optab. */
6044 gen_fractuns_conv_libfunc (convert_optab tab
,
6046 enum machine_mode tmode
,
6047 enum machine_mode fmode
)
6051 /* One mode must be a fixed-point mode, and the other must be an integer
6053 if (!((ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
)
6054 || (ALL_FIXED_POINT_MODE_P (fmode
)
6055 && GET_MODE_CLASS (tmode
) == MODE_INT
)))
6058 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6061 /* Pick proper libcall for satfract_optab. We need to chose if we do
6062 interclass or intraclass. */
6065 gen_satfract_conv_libfunc (convert_optab tab
,
6067 enum machine_mode tmode
,
6068 enum machine_mode fmode
)
6072 /* TMODE must be a fixed-point mode. */
6073 if (!ALL_FIXED_POINT_MODE_P (tmode
))
6076 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
6077 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6079 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6082 /* Pick proper libcall for satfractuns_optab. */
6085 gen_satfractuns_conv_libfunc (convert_optab tab
,
6087 enum machine_mode tmode
,
6088 enum machine_mode fmode
)
6092 /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */
6093 if (!(ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
))
6096 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6099 /* A table of previously-created libfuncs, hashed by name. */
6100 static GTY ((param_is (union tree_node
))) htab_t libfunc_decls
;
6102 /* Hashtable callbacks for libfunc_decls. */
6105 libfunc_decl_hash (const void *entry
)
6107 return IDENTIFIER_HASH_VALUE (DECL_NAME ((const_tree
) entry
));
6111 libfunc_decl_eq (const void *entry1
, const void *entry2
)
6113 return DECL_NAME ((const_tree
) entry1
) == (const_tree
) entry2
;
6116 /* Build a decl for a libfunc named NAME. */
6119 build_libfunc_function (const char *name
)
6121 tree decl
= build_decl (UNKNOWN_LOCATION
, FUNCTION_DECL
,
6122 get_identifier (name
),
6123 build_function_type (integer_type_node
, NULL_TREE
));
6124 /* ??? We don't have any type information except for this is
6125 a function. Pretend this is "int foo()". */
6126 DECL_ARTIFICIAL (decl
) = 1;
6127 DECL_EXTERNAL (decl
) = 1;
6128 TREE_PUBLIC (decl
) = 1;
6129 gcc_assert (DECL_ASSEMBLER_NAME (decl
));
6131 /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
6132 are the flags assigned by targetm.encode_section_info. */
6133 SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl
), 0), NULL
);
6139 init_one_libfunc (const char *name
)
6145 if (libfunc_decls
== NULL
)
6146 libfunc_decls
= htab_create_ggc (37, libfunc_decl_hash
,
6147 libfunc_decl_eq
, NULL
);
6149 /* See if we have already created a libfunc decl for this function. */
6150 id
= get_identifier (name
);
6151 hash
= IDENTIFIER_HASH_VALUE (id
);
6152 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, INSERT
);
6153 decl
= (tree
) *slot
;
6156 /* Create a new decl, so that it can be passed to
6157 targetm.encode_section_info. */
6158 decl
= build_libfunc_function (name
);
6161 return XEXP (DECL_RTL (decl
), 0);
6164 /* Adjust the assembler name of libfunc NAME to ASMSPEC. */
6167 set_user_assembler_libfunc (const char *name
, const char *asmspec
)
6173 id
= get_identifier (name
);
6174 hash
= IDENTIFIER_HASH_VALUE (id
);
6175 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, NO_INSERT
);
6177 decl
= (tree
) *slot
;
6178 set_user_assembler_name (decl
, asmspec
);
6179 return XEXP (DECL_RTL (decl
), 0);
6182 /* Call this to reset the function entry for one optab (OPTABLE) in mode
6183 MODE to NAME, which should be either 0 or a string constant. */
6185 set_optab_libfunc (optab op
, enum machine_mode mode
, const char *name
)
6188 struct libfunc_entry e
;
6189 struct libfunc_entry
**slot
;
6196 val
= init_one_libfunc (name
);
6199 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6201 *slot
= ggc_alloc
<libfunc_entry
> ();
6203 (*slot
)->mode1
= mode
;
6204 (*slot
)->mode2
= VOIDmode
;
6205 (*slot
)->libfunc
= val
;
6208 /* Call this to reset the function entry for one conversion optab
6209 (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be
6210 either 0 or a string constant. */
6212 set_conv_libfunc (convert_optab optab
, enum machine_mode tmode
,
6213 enum machine_mode fmode
, const char *name
)
6216 struct libfunc_entry e
;
6217 struct libfunc_entry
**slot
;
6224 val
= init_one_libfunc (name
);
6227 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6229 *slot
= ggc_alloc
<libfunc_entry
> ();
6230 (*slot
)->op
= optab
;
6231 (*slot
)->mode1
= tmode
;
6232 (*slot
)->mode2
= fmode
;
6233 (*slot
)->libfunc
= val
;
6236 /* Call this to initialize the contents of the optabs
6237 appropriately for the current target machine. */
6243 htab_empty (libfunc_hash
);
6245 libfunc_hash
= htab_create_ggc (10, hash_libfunc
, eq_libfunc
, NULL
);
6247 /* Fill in the optabs with the insns we support. */
6248 init_all_optabs (this_fn_optabs
);
6250 /* The ffs function operates on `int'. Fall back on it if we do not
6251 have a libgcc2 function for that width. */
6252 if (INT_TYPE_SIZE
< BITS_PER_WORD
)
6253 set_optab_libfunc (ffs_optab
, mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0),
6256 /* Explicitly initialize the bswap libfuncs since we need them to be
6257 valid for things other than word_mode. */
6258 if (targetm
.libfunc_gnu_prefix
)
6260 set_optab_libfunc (bswap_optab
, SImode
, "__gnu_bswapsi2");
6261 set_optab_libfunc (bswap_optab
, DImode
, "__gnu_bswapdi2");
6265 set_optab_libfunc (bswap_optab
, SImode
, "__bswapsi2");
6266 set_optab_libfunc (bswap_optab
, DImode
, "__bswapdi2");
6269 /* Use cabs for double complex abs, since systems generally have cabs.
6270 Don't define any libcall for float complex, so that cabs will be used. */
6271 if (complex_double_type_node
)
6272 set_optab_libfunc (abs_optab
, TYPE_MODE (complex_double_type_node
),
6275 abort_libfunc
= init_one_libfunc ("abort");
6276 memcpy_libfunc
= init_one_libfunc ("memcpy");
6277 memmove_libfunc
= init_one_libfunc ("memmove");
6278 memcmp_libfunc
= init_one_libfunc ("memcmp");
6279 memset_libfunc
= init_one_libfunc ("memset");
6280 setbits_libfunc
= init_one_libfunc ("__setbits");
6282 #ifndef DONT_USE_BUILTIN_SETJMP
6283 setjmp_libfunc
= init_one_libfunc ("__builtin_setjmp");
6284 longjmp_libfunc
= init_one_libfunc ("__builtin_longjmp");
6286 setjmp_libfunc
= init_one_libfunc ("setjmp");
6287 longjmp_libfunc
= init_one_libfunc ("longjmp");
6289 unwind_sjlj_register_libfunc
= init_one_libfunc ("_Unwind_SjLj_Register");
6290 unwind_sjlj_unregister_libfunc
6291 = init_one_libfunc ("_Unwind_SjLj_Unregister");
6293 /* For function entry/exit instrumentation. */
6294 profile_function_entry_libfunc
6295 = init_one_libfunc ("__cyg_profile_func_enter");
6296 profile_function_exit_libfunc
6297 = init_one_libfunc ("__cyg_profile_func_exit");
6299 gcov_flush_libfunc
= init_one_libfunc ("__gcov_flush");
6301 /* Allow the target to add more libcalls or rename some, etc. */
6302 targetm
.init_libfuncs ();
6305 /* Use the current target and options to initialize
6306 TREE_OPTIMIZATION_OPTABS (OPTNODE). */
6309 init_tree_optimization_optabs (tree optnode
)
6311 /* Quick exit if we have already computed optabs for this target. */
6312 if (TREE_OPTIMIZATION_BASE_OPTABS (optnode
) == this_target_optabs
)
6315 /* Forget any previous information and set up for the current target. */
6316 TREE_OPTIMIZATION_BASE_OPTABS (optnode
) = this_target_optabs
;
6317 struct target_optabs
*tmp_optabs
= (struct target_optabs
*)
6318 TREE_OPTIMIZATION_OPTABS (optnode
);
6320 memset (tmp_optabs
, 0, sizeof (struct target_optabs
));
6322 tmp_optabs
= ggc_alloc
<target_optabs
> ();
6324 /* Generate a new set of optabs into tmp_optabs. */
6325 init_all_optabs (tmp_optabs
);
6327 /* If the optabs changed, record it. */
6328 if (memcmp (tmp_optabs
, this_target_optabs
, sizeof (struct target_optabs
)))
6329 TREE_OPTIMIZATION_OPTABS (optnode
) = tmp_optabs
;
6332 TREE_OPTIMIZATION_OPTABS (optnode
) = NULL
;
6333 ggc_free (tmp_optabs
);
6337 /* A helper function for init_sync_libfuncs. Using the basename BASE,
6338 install libfuncs into TAB for BASE_N for 1 <= N <= MAX. */
6341 init_sync_libfuncs_1 (optab tab
, const char *base
, int max
)
6343 enum machine_mode mode
;
6345 size_t len
= strlen (base
);
6348 gcc_assert (max
<= 8);
6349 gcc_assert (len
+ 3 < sizeof (buf
));
6351 memcpy (buf
, base
, len
);
6354 buf
[len
+ 2] = '\0';
6357 for (i
= 1; i
<= max
; i
*= 2)
6359 buf
[len
+ 1] = '0' + i
;
6360 set_optab_libfunc (tab
, mode
, buf
);
6361 mode
= GET_MODE_2XWIDER_MODE (mode
);
6366 init_sync_libfuncs (int max
)
6368 if (!flag_sync_libcalls
)
6371 init_sync_libfuncs_1 (sync_compare_and_swap_optab
,
6372 "__sync_val_compare_and_swap", max
);
6373 init_sync_libfuncs_1 (sync_lock_test_and_set_optab
,
6374 "__sync_lock_test_and_set", max
);
6376 init_sync_libfuncs_1 (sync_old_add_optab
, "__sync_fetch_and_add", max
);
6377 init_sync_libfuncs_1 (sync_old_sub_optab
, "__sync_fetch_and_sub", max
);
6378 init_sync_libfuncs_1 (sync_old_ior_optab
, "__sync_fetch_and_or", max
);
6379 init_sync_libfuncs_1 (sync_old_and_optab
, "__sync_fetch_and_and", max
);
6380 init_sync_libfuncs_1 (sync_old_xor_optab
, "__sync_fetch_and_xor", max
);
6381 init_sync_libfuncs_1 (sync_old_nand_optab
, "__sync_fetch_and_nand", max
);
6383 init_sync_libfuncs_1 (sync_new_add_optab
, "__sync_add_and_fetch", max
);
6384 init_sync_libfuncs_1 (sync_new_sub_optab
, "__sync_sub_and_fetch", max
);
6385 init_sync_libfuncs_1 (sync_new_ior_optab
, "__sync_or_and_fetch", max
);
6386 init_sync_libfuncs_1 (sync_new_and_optab
, "__sync_and_and_fetch", max
);
6387 init_sync_libfuncs_1 (sync_new_xor_optab
, "__sync_xor_and_fetch", max
);
6388 init_sync_libfuncs_1 (sync_new_nand_optab
, "__sync_nand_and_fetch", max
);
6391 /* Print information about the current contents of the optabs on
6395 debug_optab_libfuncs (void)
6399 /* Dump the arithmetic optabs. */
6400 for (i
= FIRST_NORM_OPTAB
; i
<= LAST_NORMLIB_OPTAB
; ++i
)
6401 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6403 rtx l
= optab_libfunc ((optab
) i
, (enum machine_mode
) j
);
6406 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6407 fprintf (stderr
, "%s\t%s:\t%s\n",
6408 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6414 /* Dump the conversion optabs. */
6415 for (i
= FIRST_CONV_OPTAB
; i
<= LAST_CONVLIB_OPTAB
; ++i
)
6416 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6417 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
6419 rtx l
= convert_optab_libfunc ((optab
) i
, (enum machine_mode
) j
,
6420 (enum machine_mode
) k
);
6423 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6424 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
6425 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6434 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
6435 CODE. Return 0 on failure. */
6438 gen_cond_trap (enum rtx_code code
, rtx op1
, rtx op2
, rtx tcode
)
6440 enum machine_mode mode
= GET_MODE (op1
);
6441 enum insn_code icode
;
6445 if (mode
== VOIDmode
)
6448 icode
= optab_handler (ctrap_optab
, mode
);
6449 if (icode
== CODE_FOR_nothing
)
6452 /* Some targets only accept a zero trap code. */
6453 if (!insn_operand_matches (icode
, 3, tcode
))
6456 do_pending_stack_adjust ();
6458 prepare_cmp_insn (op1
, op2
, code
, NULL_RTX
, false, OPTAB_DIRECT
,
6463 insn
= GEN_FCN (icode
) (trap_rtx
, XEXP (trap_rtx
, 0), XEXP (trap_rtx
, 1),
6466 /* If that failed, then give up. */
6474 insn
= get_insns ();
6479 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6480 or unsigned operation code. */
6482 static enum rtx_code
6483 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
6495 code
= unsignedp
? LTU
: LT
;
6498 code
= unsignedp
? LEU
: LE
;
6501 code
= unsignedp
? GTU
: GT
;
6504 code
= unsignedp
? GEU
: GE
;
6507 case UNORDERED_EXPR
:
6538 /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or
6539 unsigned operators. Do not generate compare instruction. */
6542 vector_compare_rtx (enum tree_code tcode
, tree t_op0
, tree t_op1
,
6543 bool unsignedp
, enum insn_code icode
)
6545 struct expand_operand ops
[2];
6546 rtx rtx_op0
, rtx_op1
;
6547 enum rtx_code rcode
= get_rtx_code (tcode
, unsignedp
);
6549 gcc_assert (TREE_CODE_CLASS (tcode
) == tcc_comparison
);
6551 /* Expand operands. */
6552 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)),
6554 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)),
6557 create_input_operand (&ops
[0], rtx_op0
, GET_MODE (rtx_op0
));
6558 create_input_operand (&ops
[1], rtx_op1
, GET_MODE (rtx_op1
));
6559 if (!maybe_legitimize_operands (icode
, 4, 2, ops
))
6561 return gen_rtx_fmt_ee (rcode
, VOIDmode
, ops
[0].value
, ops
[1].value
);
6564 /* Return true if VEC_PERM_EXPR can be expanded using SIMD extensions
6565 of the CPU. SEL may be NULL, which stands for an unknown constant. */
6568 can_vec_perm_p (enum machine_mode mode
, bool variable
,
6569 const unsigned char *sel
)
6571 enum machine_mode qimode
;
6573 /* If the target doesn't implement a vector mode for the vector type,
6574 then no operations are supported. */
6575 if (!VECTOR_MODE_P (mode
))
6580 if (direct_optab_handler (vec_perm_const_optab
, mode
) != CODE_FOR_nothing
6582 || targetm
.vectorize
.vec_perm_const_ok
== NULL
6583 || targetm
.vectorize
.vec_perm_const_ok (mode
, sel
)))
6587 if (direct_optab_handler (vec_perm_optab
, mode
) != CODE_FOR_nothing
)
6590 /* We allow fallback to a QI vector mode, and adjust the mask. */
6591 if (GET_MODE_INNER (mode
) == QImode
)
6593 qimode
= mode_for_vector (QImode
, GET_MODE_SIZE (mode
));
6594 if (!VECTOR_MODE_P (qimode
))
6597 /* ??? For completeness, we ought to check the QImode version of
6598 vec_perm_const_optab. But all users of this implicit lowering
6599 feature implement the variable vec_perm_optab. */
6600 if (direct_optab_handler (vec_perm_optab
, qimode
) == CODE_FOR_nothing
)
6603 /* In order to support the lowering of variable permutations,
6604 we need to support shifts and adds. */
6607 if (GET_MODE_UNIT_SIZE (mode
) > 2
6608 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
6609 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
)
6611 if (optab_handler (add_optab
, qimode
) == CODE_FOR_nothing
)
6618 /* A subroutine of expand_vec_perm for expanding one vec_perm insn. */
6621 expand_vec_perm_1 (enum insn_code icode
, rtx target
,
6622 rtx v0
, rtx v1
, rtx sel
)
6624 enum machine_mode tmode
= GET_MODE (target
);
6625 enum machine_mode smode
= GET_MODE (sel
);
6626 struct expand_operand ops
[4];
6628 create_output_operand (&ops
[0], target
, tmode
);
6629 create_input_operand (&ops
[3], sel
, smode
);
6631 /* Make an effort to preserve v0 == v1. The target expander is able to
6632 rely on this to determine if we're permuting a single input operand. */
6633 if (rtx_equal_p (v0
, v1
))
6635 if (!insn_operand_matches (icode
, 1, v0
))
6636 v0
= force_reg (tmode
, v0
);
6637 gcc_checking_assert (insn_operand_matches (icode
, 1, v0
));
6638 gcc_checking_assert (insn_operand_matches (icode
, 2, v0
));
6640 create_fixed_operand (&ops
[1], v0
);
6641 create_fixed_operand (&ops
[2], v0
);
6645 create_input_operand (&ops
[1], v0
, tmode
);
6646 create_input_operand (&ops
[2], v1
, tmode
);
6649 if (maybe_expand_insn (icode
, 4, ops
))
6650 return ops
[0].value
;
6654 /* Generate instructions for vec_perm optab given its mode
6655 and three operands. */
6658 expand_vec_perm (enum machine_mode mode
, rtx v0
, rtx v1
, rtx sel
, rtx target
)
6660 enum insn_code icode
;
6661 enum machine_mode qimode
;
6662 unsigned int i
, w
, e
, u
;
6663 rtx tmp
, sel_qi
= NULL
;
6666 if (!target
|| GET_MODE (target
) != mode
)
6667 target
= gen_reg_rtx (mode
);
6669 w
= GET_MODE_SIZE (mode
);
6670 e
= GET_MODE_NUNITS (mode
);
6671 u
= GET_MODE_UNIT_SIZE (mode
);
6673 /* Set QIMODE to a different vector mode with byte elements.
6674 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6676 if (GET_MODE_INNER (mode
) != QImode
)
6678 qimode
= mode_for_vector (QImode
, w
);
6679 if (!VECTOR_MODE_P (qimode
))
6683 /* If the input is a constant, expand it specially. */
6684 gcc_assert (GET_MODE_CLASS (GET_MODE (sel
)) == MODE_VECTOR_INT
);
6685 if (GET_CODE (sel
) == CONST_VECTOR
)
6687 icode
= direct_optab_handler (vec_perm_const_optab
, mode
);
6688 if (icode
!= CODE_FOR_nothing
)
6690 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6695 /* Fall back to a constant byte-based permutation. */
6696 if (qimode
!= VOIDmode
)
6698 vec
= rtvec_alloc (w
);
6699 for (i
= 0; i
< e
; ++i
)
6701 unsigned int j
, this_e
;
6703 this_e
= INTVAL (CONST_VECTOR_ELT (sel
, i
));
6704 this_e
&= 2 * e
- 1;
6707 for (j
= 0; j
< u
; ++j
)
6708 RTVEC_ELT (vec
, i
* u
+ j
) = GEN_INT (this_e
+ j
);
6710 sel_qi
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6712 icode
= direct_optab_handler (vec_perm_const_optab
, qimode
);
6713 if (icode
!= CODE_FOR_nothing
)
6715 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6716 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6717 gen_lowpart (qimode
, v1
), sel_qi
);
6719 return gen_lowpart (mode
, tmp
);
6724 /* Otherwise expand as a fully variable permuation. */
6725 icode
= direct_optab_handler (vec_perm_optab
, mode
);
6726 if (icode
!= CODE_FOR_nothing
)
6728 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6733 /* As a special case to aid several targets, lower the element-based
6734 permutation to a byte-based permutation and try again. */
6735 if (qimode
== VOIDmode
)
6737 icode
= direct_optab_handler (vec_perm_optab
, qimode
);
6738 if (icode
== CODE_FOR_nothing
)
6743 /* Multiply each element by its byte size. */
6744 enum machine_mode selmode
= GET_MODE (sel
);
6746 sel
= expand_simple_binop (selmode
, PLUS
, sel
, sel
,
6747 sel
, 0, OPTAB_DIRECT
);
6749 sel
= expand_simple_binop (selmode
, ASHIFT
, sel
,
6750 GEN_INT (exact_log2 (u
)),
6751 sel
, 0, OPTAB_DIRECT
);
6752 gcc_assert (sel
!= NULL
);
6754 /* Broadcast the low byte each element into each of its bytes. */
6755 vec
= rtvec_alloc (w
);
6756 for (i
= 0; i
< w
; ++i
)
6758 int this_e
= i
/ u
* u
;
6759 if (BYTES_BIG_ENDIAN
)
6761 RTVEC_ELT (vec
, i
) = GEN_INT (this_e
);
6763 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6764 sel
= gen_lowpart (qimode
, sel
);
6765 sel
= expand_vec_perm (qimode
, sel
, sel
, tmp
, NULL
);
6766 gcc_assert (sel
!= NULL
);
6768 /* Add the byte offset to each byte element. */
6769 /* Note that the definition of the indicies here is memory ordering,
6770 so there should be no difference between big and little endian. */
6771 vec
= rtvec_alloc (w
);
6772 for (i
= 0; i
< w
; ++i
)
6773 RTVEC_ELT (vec
, i
) = GEN_INT (i
% u
);
6774 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6775 sel_qi
= expand_simple_binop (qimode
, PLUS
, sel
, tmp
,
6776 sel
, 0, OPTAB_DIRECT
);
6777 gcc_assert (sel_qi
!= NULL
);
6780 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6781 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6782 gen_lowpart (qimode
, v1
), sel_qi
);
6784 tmp
= gen_lowpart (mode
, tmp
);
6788 /* Return insn code for a conditional operator with a comparison in
6789 mode CMODE, unsigned if UNS is true, resulting in a value of mode VMODE. */
6791 static inline enum insn_code
6792 get_vcond_icode (enum machine_mode vmode
, enum machine_mode cmode
, bool uns
)
6794 enum insn_code icode
= CODE_FOR_nothing
;
6796 icode
= convert_optab_handler (vcondu_optab
, vmode
, cmode
);
6798 icode
= convert_optab_handler (vcond_optab
, vmode
, cmode
);
6802 /* Return TRUE iff, appropriate vector insns are available
6803 for vector cond expr with vector type VALUE_TYPE and a comparison
6804 with operand vector types in CMP_OP_TYPE. */
6807 expand_vec_cond_expr_p (tree value_type
, tree cmp_op_type
)
6809 enum machine_mode value_mode
= TYPE_MODE (value_type
);
6810 enum machine_mode cmp_op_mode
= TYPE_MODE (cmp_op_type
);
6811 if (GET_MODE_SIZE (value_mode
) != GET_MODE_SIZE (cmp_op_mode
)
6812 || GET_MODE_NUNITS (value_mode
) != GET_MODE_NUNITS (cmp_op_mode
)
6813 || get_vcond_icode (TYPE_MODE (value_type
), TYPE_MODE (cmp_op_type
),
6814 TYPE_UNSIGNED (cmp_op_type
)) == CODE_FOR_nothing
)
6819 /* Generate insns for a VEC_COND_EXPR, given its TYPE and its
6823 expand_vec_cond_expr (tree vec_cond_type
, tree op0
, tree op1
, tree op2
,
6826 struct expand_operand ops
[6];
6827 enum insn_code icode
;
6828 rtx comparison
, rtx_op1
, rtx_op2
;
6829 enum machine_mode mode
= TYPE_MODE (vec_cond_type
);
6830 enum machine_mode cmp_op_mode
;
6833 enum tree_code tcode
;
6835 if (COMPARISON_CLASS_P (op0
))
6837 op0a
= TREE_OPERAND (op0
, 0);
6838 op0b
= TREE_OPERAND (op0
, 1);
6839 tcode
= TREE_CODE (op0
);
6844 gcc_assert (!TYPE_UNSIGNED (TREE_TYPE (op0
)));
6846 op0b
= build_zero_cst (TREE_TYPE (op0
));
6849 unsignedp
= TYPE_UNSIGNED (TREE_TYPE (op0a
));
6850 cmp_op_mode
= TYPE_MODE (TREE_TYPE (op0a
));
6853 gcc_assert (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (cmp_op_mode
)
6854 && GET_MODE_NUNITS (mode
) == GET_MODE_NUNITS (cmp_op_mode
));
6856 icode
= get_vcond_icode (mode
, cmp_op_mode
, unsignedp
);
6857 if (icode
== CODE_FOR_nothing
)
6860 comparison
= vector_compare_rtx (tcode
, op0a
, op0b
, unsignedp
, icode
);
6861 rtx_op1
= expand_normal (op1
);
6862 rtx_op2
= expand_normal (op2
);
6864 create_output_operand (&ops
[0], target
, mode
);
6865 create_input_operand (&ops
[1], rtx_op1
, mode
);
6866 create_input_operand (&ops
[2], rtx_op2
, mode
);
6867 create_fixed_operand (&ops
[3], comparison
);
6868 create_fixed_operand (&ops
[4], XEXP (comparison
, 0));
6869 create_fixed_operand (&ops
[5], XEXP (comparison
, 1));
6870 expand_insn (icode
, 6, ops
);
6871 return ops
[0].value
;
6874 /* Return non-zero if a highpart multiply is supported of can be synthisized.
6875 For the benefit of expand_mult_highpart, the return value is 1 for direct,
6876 2 for even/odd widening, and 3 for hi/lo widening. */
6879 can_mult_highpart_p (enum machine_mode mode
, bool uns_p
)
6885 op
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6886 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6889 /* If the mode is an integral vector, synth from widening operations. */
6890 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
6893 nunits
= GET_MODE_NUNITS (mode
);
6894 sel
= XALLOCAVEC (unsigned char, nunits
);
6896 op
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6897 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6899 op
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6900 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6902 for (i
= 0; i
< nunits
; ++i
)
6903 sel
[i
] = !BYTES_BIG_ENDIAN
+ (i
& ~1) + ((i
& 1) ? nunits
: 0);
6904 if (can_vec_perm_p (mode
, false, sel
))
6909 op
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6910 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6912 op
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6913 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6915 for (i
= 0; i
< nunits
; ++i
)
6916 sel
[i
] = 2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1);
6917 if (can_vec_perm_p (mode
, false, sel
))
6925 /* Expand a highpart multiply. */
6928 expand_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
6929 rtx target
, bool uns_p
)
6931 struct expand_operand eops
[3];
6932 enum insn_code icode
;
6933 int method
, i
, nunits
;
6934 enum machine_mode wmode
;
6939 method
= can_mult_highpart_p (mode
, uns_p
);
6945 tab1
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6946 return expand_binop (mode
, tab1
, op0
, op1
, target
, uns_p
,
6949 tab1
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6950 tab2
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6953 tab1
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6954 tab2
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6955 if (BYTES_BIG_ENDIAN
)
6966 icode
= optab_handler (tab1
, mode
);
6967 nunits
= GET_MODE_NUNITS (mode
);
6968 wmode
= insn_data
[icode
].operand
[0].mode
;
6969 gcc_checking_assert (2 * GET_MODE_NUNITS (wmode
) == nunits
);
6970 gcc_checking_assert (GET_MODE_SIZE (wmode
) == GET_MODE_SIZE (mode
));
6972 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6973 create_input_operand (&eops
[1], op0
, mode
);
6974 create_input_operand (&eops
[2], op1
, mode
);
6975 expand_insn (icode
, 3, eops
);
6976 m1
= gen_lowpart (mode
, eops
[0].value
);
6978 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6979 create_input_operand (&eops
[1], op0
, mode
);
6980 create_input_operand (&eops
[2], op1
, mode
);
6981 expand_insn (optab_handler (tab2
, mode
), 3, eops
);
6982 m2
= gen_lowpart (mode
, eops
[0].value
);
6984 v
= rtvec_alloc (nunits
);
6987 for (i
= 0; i
< nunits
; ++i
)
6988 RTVEC_ELT (v
, i
) = GEN_INT (!BYTES_BIG_ENDIAN
+ (i
& ~1)
6989 + ((i
& 1) ? nunits
: 0));
6993 for (i
= 0; i
< nunits
; ++i
)
6994 RTVEC_ELT (v
, i
) = GEN_INT (2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1));
6996 perm
= gen_rtx_CONST_VECTOR (mode
, v
);
6998 return expand_vec_perm (mode
, m1
, m2
, perm
, target
);
7001 /* Return true if target supports vector masked load/store for mode. */
7003 can_vec_mask_load_store_p (enum machine_mode mode
, bool is_load
)
7005 optab op
= is_load
? maskload_optab
: maskstore_optab
;
7006 enum machine_mode vmode
;
7007 unsigned int vector_sizes
;
7009 /* If mode is vector mode, check it directly. */
7010 if (VECTOR_MODE_P (mode
))
7011 return optab_handler (op
, mode
) != CODE_FOR_nothing
;
7013 /* Otherwise, return true if there is some vector mode with
7014 the mask load/store supported. */
7016 /* See if there is any chance the mask load or store might be
7017 vectorized. If not, punt. */
7018 vmode
= targetm
.vectorize
.preferred_simd_mode (mode
);
7019 if (!VECTOR_MODE_P (vmode
))
7022 if (optab_handler (op
, vmode
) != CODE_FOR_nothing
)
7025 vector_sizes
= targetm
.vectorize
.autovectorize_vector_sizes ();
7026 while (vector_sizes
!= 0)
7028 unsigned int cur
= 1 << floor_log2 (vector_sizes
);
7029 vector_sizes
&= ~cur
;
7030 if (cur
<= GET_MODE_SIZE (mode
))
7032 vmode
= mode_for_vector (mode
, cur
/ GET_MODE_SIZE (mode
));
7033 if (VECTOR_MODE_P (vmode
)
7034 && optab_handler (op
, vmode
) != CODE_FOR_nothing
)
7040 /* Return true if there is a compare_and_swap pattern. */
7043 can_compare_and_swap_p (enum machine_mode mode
, bool allow_libcall
)
7045 enum insn_code icode
;
7047 /* Check for __atomic_compare_and_swap. */
7048 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7049 if (icode
!= CODE_FOR_nothing
)
7052 /* Check for __sync_compare_and_swap. */
7053 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7054 if (icode
!= CODE_FOR_nothing
)
7056 if (allow_libcall
&& optab_libfunc (sync_compare_and_swap_optab
, mode
))
7059 /* No inline compare and swap. */
7063 /* Return true if an atomic exchange can be performed. */
7066 can_atomic_exchange_p (enum machine_mode mode
, bool allow_libcall
)
7068 enum insn_code icode
;
7070 /* Check for __atomic_exchange. */
7071 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7072 if (icode
!= CODE_FOR_nothing
)
7075 /* Don't check __sync_test_and_set, as on some platforms that
7076 has reduced functionality. Targets that really do support
7077 a proper exchange should simply be updated to the __atomics. */
7079 return can_compare_and_swap_p (mode
, allow_libcall
);
7083 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
7087 find_cc_set (rtx x
, const_rtx pat
, void *data
)
7089 if (REG_P (x
) && GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
7090 && GET_CODE (pat
) == SET
)
7092 rtx
*p_cc_reg
= (rtx
*) data
;
7093 gcc_assert (!*p_cc_reg
);
7098 /* This is a helper function for the other atomic operations. This function
7099 emits a loop that contains SEQ that iterates until a compare-and-swap
7100 operation at the end succeeds. MEM is the memory to be modified. SEQ is
7101 a set of instructions that takes a value from OLD_REG as an input and
7102 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
7103 set to the current contents of MEM. After SEQ, a compare-and-swap will
7104 attempt to update MEM with NEW_REG. The function returns true when the
7105 loop was generated successfully. */
7108 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
7110 enum machine_mode mode
= GET_MODE (mem
);
7111 rtx_code_label
*label
;
7112 rtx cmp_reg
, success
, oldval
;
7114 /* The loop we want to generate looks like
7120 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
7124 Note that we only do the plain load from memory once. Subsequent
7125 iterations use the value loaded by the compare-and-swap pattern. */
7127 label
= gen_label_rtx ();
7128 cmp_reg
= gen_reg_rtx (mode
);
7130 emit_move_insn (cmp_reg
, mem
);
7132 emit_move_insn (old_reg
, cmp_reg
);
7138 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
7139 new_reg
, false, MEMMODEL_SEQ_CST
,
7143 if (oldval
!= cmp_reg
)
7144 emit_move_insn (cmp_reg
, oldval
);
7146 /* Mark this jump predicted not taken. */
7147 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
7148 GET_MODE (success
), 1, label
, 0);
7153 /* This function tries to emit an atomic_exchange intruction. VAL is written
7154 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
7155 using TARGET if possible. */
7158 maybe_emit_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7160 enum machine_mode mode
= GET_MODE (mem
);
7161 enum insn_code icode
;
7163 /* If the target supports the exchange directly, great. */
7164 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7165 if (icode
!= CODE_FOR_nothing
)
7167 struct expand_operand ops
[4];
7169 create_output_operand (&ops
[0], target
, mode
);
7170 create_fixed_operand (&ops
[1], mem
);
7171 create_input_operand (&ops
[2], val
, mode
);
7172 create_integer_operand (&ops
[3], model
);
7173 if (maybe_expand_insn (icode
, 4, ops
))
7174 return ops
[0].value
;
7180 /* This function tries to implement an atomic exchange operation using
7181 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
7182 The previous contents of *MEM are returned, using TARGET if possible.
7183 Since this instructionn is an acquire barrier only, stronger memory
7184 models may require additional barriers to be emitted. */
7187 maybe_emit_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
,
7188 enum memmodel model
)
7190 enum machine_mode mode
= GET_MODE (mem
);
7191 enum insn_code icode
;
7192 rtx_insn
*last_insn
= get_last_insn ();
7194 icode
= optab_handler (sync_lock_test_and_set_optab
, mode
);
7196 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
7197 exists, and the memory model is stronger than acquire, add a release
7198 barrier before the instruction. */
7200 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
7201 || (model
& MEMMODEL_MASK
) == MEMMODEL_RELEASE
7202 || (model
& MEMMODEL_MASK
) == MEMMODEL_ACQ_REL
)
7203 expand_mem_thread_fence (model
);
7205 if (icode
!= CODE_FOR_nothing
)
7207 struct expand_operand ops
[3];
7208 create_output_operand (&ops
[0], target
, mode
);
7209 create_fixed_operand (&ops
[1], mem
);
7210 create_input_operand (&ops
[2], val
, mode
);
7211 if (maybe_expand_insn (icode
, 3, ops
))
7212 return ops
[0].value
;
7215 /* If an external test-and-set libcall is provided, use that instead of
7216 any external compare-and-swap that we might get from the compare-and-
7217 swap-loop expansion later. */
7218 if (!can_compare_and_swap_p (mode
, false))
7220 rtx libfunc
= optab_libfunc (sync_lock_test_and_set_optab
, mode
);
7221 if (libfunc
!= NULL
)
7225 addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7226 return emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7227 mode
, 2, addr
, ptr_mode
,
7232 /* If the test_and_set can't be emitted, eliminate any barrier that might
7233 have been emitted. */
7234 delete_insns_since (last_insn
);
7238 /* This function tries to implement an atomic exchange operation using a
7239 compare_and_swap loop. VAL is written to *MEM. The previous contents of
7240 *MEM are returned, using TARGET if possible. No memory model is required
7241 since a compare_and_swap loop is seq-cst. */
7244 maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
7246 enum machine_mode mode
= GET_MODE (mem
);
7248 if (can_compare_and_swap_p (mode
, true))
7250 if (!target
|| !register_operand (target
, mode
))
7251 target
= gen_reg_rtx (mode
);
7252 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
7259 /* This function tries to implement an atomic test-and-set operation
7260 using the atomic_test_and_set instruction pattern. A boolean value
7261 is returned from the operation, using TARGET if possible. */
7263 #ifndef HAVE_atomic_test_and_set
7264 #define HAVE_atomic_test_and_set 0
7265 #define CODE_FOR_atomic_test_and_set CODE_FOR_nothing
7269 maybe_emit_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7271 enum machine_mode pat_bool_mode
;
7272 struct expand_operand ops
[3];
7274 if (!HAVE_atomic_test_and_set
)
7277 /* While we always get QImode from __atomic_test_and_set, we get
7278 other memory modes from __sync_lock_test_and_set. Note that we
7279 use no endian adjustment here. This matches the 4.6 behavior
7280 in the Sparc backend. */
7282 (insn_data
[CODE_FOR_atomic_test_and_set
].operand
[1].mode
== QImode
);
7283 if (GET_MODE (mem
) != QImode
)
7284 mem
= adjust_address_nv (mem
, QImode
, 0);
7286 pat_bool_mode
= insn_data
[CODE_FOR_atomic_test_and_set
].operand
[0].mode
;
7287 create_output_operand (&ops
[0], target
, pat_bool_mode
);
7288 create_fixed_operand (&ops
[1], mem
);
7289 create_integer_operand (&ops
[2], model
);
7291 if (maybe_expand_insn (CODE_FOR_atomic_test_and_set
, 3, ops
))
7292 return ops
[0].value
;
7296 /* This function expands the legacy _sync_lock test_and_set operation which is
7297 generally an atomic exchange. Some limited targets only allow the
7298 constant 1 to be stored. This is an ACQUIRE operation.
7300 TARGET is an optional place to stick the return value.
7301 MEM is where VAL is stored. */
7304 expand_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
)
7308 /* Try an atomic_exchange first. */
7309 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7313 ret
= maybe_emit_sync_lock_test_and_set (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7317 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7321 /* If there are no other options, try atomic_test_and_set if the value
7322 being stored is 1. */
7323 if (val
== const1_rtx
)
7324 ret
= maybe_emit_atomic_test_and_set (target
, mem
, MEMMODEL_ACQUIRE
);
7329 /* This function expands the atomic test_and_set operation:
7330 atomically store a boolean TRUE into MEM and return the previous value.
7332 MEMMODEL is the memory model variant to use.
7333 TARGET is an optional place to stick the return value. */
7336 expand_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7338 enum machine_mode mode
= GET_MODE (mem
);
7339 rtx ret
, trueval
, subtarget
;
7341 ret
= maybe_emit_atomic_test_and_set (target
, mem
, model
);
7345 /* Be binary compatible with non-default settings of trueval, and different
7346 cpu revisions. E.g. one revision may have atomic-test-and-set, but
7347 another only has atomic-exchange. */
7348 if (targetm
.atomic_test_and_set_trueval
== 1)
7350 trueval
= const1_rtx
;
7351 subtarget
= target
? target
: gen_reg_rtx (mode
);
7355 trueval
= gen_int_mode (targetm
.atomic_test_and_set_trueval
, mode
);
7356 subtarget
= gen_reg_rtx (mode
);
7359 /* Try the atomic-exchange optab... */
7360 ret
= maybe_emit_atomic_exchange (subtarget
, mem
, trueval
, model
);
7362 /* ... then an atomic-compare-and-swap loop ... */
7364 ret
= maybe_emit_compare_and_swap_exchange_loop (subtarget
, mem
, trueval
);
7366 /* ... before trying the vaguely defined legacy lock_test_and_set. */
7368 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, trueval
, model
);
7370 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
7371 things with the value 1. Thus we try again without trueval. */
7372 if (!ret
&& targetm
.atomic_test_and_set_trueval
!= 1)
7373 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, const1_rtx
, model
);
7375 /* Failing all else, assume a single threaded environment and simply
7376 perform the operation. */
7379 /* If the result is ignored skip the move to target. */
7380 if (subtarget
!= const0_rtx
)
7381 emit_move_insn (subtarget
, mem
);
7383 emit_move_insn (mem
, trueval
);
7387 /* Recall that have to return a boolean value; rectify if trueval
7388 is not exactly one. */
7389 if (targetm
.atomic_test_and_set_trueval
!= 1)
7390 ret
= emit_store_flag_force (target
, NE
, ret
, const0_rtx
, mode
, 0, 1);
7395 /* This function expands the atomic exchange operation:
7396 atomically store VAL in MEM and return the previous value in MEM.
7398 MEMMODEL is the memory model variant to use.
7399 TARGET is an optional place to stick the return value. */
7402 expand_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7406 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7408 /* Next try a compare-and-swap loop for the exchange. */
7410 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7415 /* This function expands the atomic compare exchange operation:
7417 *PTARGET_BOOL is an optional place to store the boolean success/failure.
7418 *PTARGET_OVAL is an optional place to store the old value from memory.
7419 Both target parameters may be NULL to indicate that we do not care about
7420 that return value. Both target parameters are updated on success to
7421 the actual location of the corresponding result.
7423 MEMMODEL is the memory model variant to use.
7425 The return value of the function is true for success. */
7428 expand_atomic_compare_and_swap (rtx
*ptarget_bool
, rtx
*ptarget_oval
,
7429 rtx mem
, rtx expected
, rtx desired
,
7430 bool is_weak
, enum memmodel succ_model
,
7431 enum memmodel fail_model
)
7433 enum machine_mode mode
= GET_MODE (mem
);
7434 struct expand_operand ops
[8];
7435 enum insn_code icode
;
7436 rtx target_oval
, target_bool
= NULL_RTX
;
7439 /* Load expected into a register for the compare and swap. */
7440 if (MEM_P (expected
))
7441 expected
= copy_to_reg (expected
);
7443 /* Make sure we always have some place to put the return oldval.
7444 Further, make sure that place is distinct from the input expected,
7445 just in case we need that path down below. */
7446 if (ptarget_oval
== NULL
7447 || (target_oval
= *ptarget_oval
) == NULL
7448 || reg_overlap_mentioned_p (expected
, target_oval
))
7449 target_oval
= gen_reg_rtx (mode
);
7451 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7452 if (icode
!= CODE_FOR_nothing
)
7454 enum machine_mode bool_mode
= insn_data
[icode
].operand
[0].mode
;
7456 /* Make sure we always have a place for the bool operand. */
7457 if (ptarget_bool
== NULL
7458 || (target_bool
= *ptarget_bool
) == NULL
7459 || GET_MODE (target_bool
) != bool_mode
)
7460 target_bool
= gen_reg_rtx (bool_mode
);
7462 /* Emit the compare_and_swap. */
7463 create_output_operand (&ops
[0], target_bool
, bool_mode
);
7464 create_output_operand (&ops
[1], target_oval
, mode
);
7465 create_fixed_operand (&ops
[2], mem
);
7466 create_input_operand (&ops
[3], expected
, mode
);
7467 create_input_operand (&ops
[4], desired
, mode
);
7468 create_integer_operand (&ops
[5], is_weak
);
7469 create_integer_operand (&ops
[6], succ_model
);
7470 create_integer_operand (&ops
[7], fail_model
);
7471 if (maybe_expand_insn (icode
, 8, ops
))
7473 /* Return success/failure. */
7474 target_bool
= ops
[0].value
;
7475 target_oval
= ops
[1].value
;
7480 /* Otherwise fall back to the original __sync_val_compare_and_swap
7481 which is always seq-cst. */
7482 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7483 if (icode
!= CODE_FOR_nothing
)
7487 create_output_operand (&ops
[0], target_oval
, mode
);
7488 create_fixed_operand (&ops
[1], mem
);
7489 create_input_operand (&ops
[2], expected
, mode
);
7490 create_input_operand (&ops
[3], desired
, mode
);
7491 if (!maybe_expand_insn (icode
, 4, ops
))
7494 target_oval
= ops
[0].value
;
7496 /* If the caller isn't interested in the boolean return value,
7497 skip the computation of it. */
7498 if (ptarget_bool
== NULL
)
7501 /* Otherwise, work out if the compare-and-swap succeeded. */
7503 if (have_insn_for (COMPARE
, CCmode
))
7504 note_stores (PATTERN (get_last_insn ()), find_cc_set
, &cc_reg
);
7507 target_bool
= emit_store_flag_force (target_bool
, EQ
, cc_reg
,
7508 const0_rtx
, VOIDmode
, 0, 1);
7511 goto success_bool_from_val
;
7514 /* Also check for library support for __sync_val_compare_and_swap. */
7515 libfunc
= optab_libfunc (sync_compare_and_swap_optab
, mode
);
7516 if (libfunc
!= NULL
)
7518 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7519 target_oval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7520 mode
, 3, addr
, ptr_mode
,
7521 expected
, mode
, desired
, mode
);
7523 /* Compute the boolean return value only if requested. */
7525 goto success_bool_from_val
;
7533 success_bool_from_val
:
7534 target_bool
= emit_store_flag_force (target_bool
, EQ
, target_oval
,
7535 expected
, VOIDmode
, 1, 1);
7537 /* Make sure that the oval output winds up where the caller asked. */
7539 *ptarget_oval
= target_oval
;
7541 *ptarget_bool
= target_bool
;
7545 /* Generate asm volatile("" : : : "memory") as the memory barrier. */
7548 expand_asm_memory_barrier (void)
7552 asm_op
= gen_rtx_ASM_OPERANDS (VOIDmode
, empty_string
, empty_string
, 0,
7553 rtvec_alloc (0), rtvec_alloc (0),
7554 rtvec_alloc (0), UNKNOWN_LOCATION
);
7555 MEM_VOLATILE_P (asm_op
) = 1;
7557 clob
= gen_rtx_SCRATCH (VOIDmode
);
7558 clob
= gen_rtx_MEM (BLKmode
, clob
);
7559 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
7561 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, asm_op
, clob
)));
7564 /* This routine will either emit the mem_thread_fence pattern or issue a
7565 sync_synchronize to generate a fence for memory model MEMMODEL. */
7567 #ifndef HAVE_mem_thread_fence
7568 # define HAVE_mem_thread_fence 0
7569 # define gen_mem_thread_fence(x) (gcc_unreachable (), NULL_RTX)
7571 #ifndef HAVE_memory_barrier
7572 # define HAVE_memory_barrier 0
7573 # define gen_memory_barrier() (gcc_unreachable (), NULL_RTX)
7577 expand_mem_thread_fence (enum memmodel model
)
7579 if (HAVE_mem_thread_fence
)
7580 emit_insn (gen_mem_thread_fence (GEN_INT (model
)));
7581 else if ((model
& MEMMODEL_MASK
) != MEMMODEL_RELAXED
)
7583 if (HAVE_memory_barrier
)
7584 emit_insn (gen_memory_barrier ());
7585 else if (synchronize_libfunc
!= NULL_RTX
)
7586 emit_library_call (synchronize_libfunc
, LCT_NORMAL
, VOIDmode
, 0);
7588 expand_asm_memory_barrier ();
7592 /* This routine will either emit the mem_signal_fence pattern or issue a
7593 sync_synchronize to generate a fence for memory model MEMMODEL. */
7595 #ifndef HAVE_mem_signal_fence
7596 # define HAVE_mem_signal_fence 0
7597 # define gen_mem_signal_fence(x) (gcc_unreachable (), NULL_RTX)
7601 expand_mem_signal_fence (enum memmodel model
)
7603 if (HAVE_mem_signal_fence
)
7604 emit_insn (gen_mem_signal_fence (GEN_INT (model
)));
7605 else if ((model
& MEMMODEL_MASK
) != MEMMODEL_RELAXED
)
7607 /* By default targets are coherent between a thread and the signal
7608 handler running on the same thread. Thus this really becomes a
7609 compiler barrier, in that stores must not be sunk past
7610 (or raised above) a given point. */
7611 expand_asm_memory_barrier ();
7615 /* This function expands the atomic load operation:
7616 return the atomically loaded value in MEM.
7618 MEMMODEL is the memory model variant to use.
7619 TARGET is an option place to stick the return value. */
7622 expand_atomic_load (rtx target
, rtx mem
, enum memmodel model
)
7624 enum machine_mode mode
= GET_MODE (mem
);
7625 enum insn_code icode
;
7627 /* If the target supports the load directly, great. */
7628 icode
= direct_optab_handler (atomic_load_optab
, mode
);
7629 if (icode
!= CODE_FOR_nothing
)
7631 struct expand_operand ops
[3];
7633 create_output_operand (&ops
[0], target
, mode
);
7634 create_fixed_operand (&ops
[1], mem
);
7635 create_integer_operand (&ops
[2], model
);
7636 if (maybe_expand_insn (icode
, 3, ops
))
7637 return ops
[0].value
;
7640 /* If the size of the object is greater than word size on this target,
7641 then we assume that a load will not be atomic. */
7642 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7644 /* Issue val = compare_and_swap (mem, 0, 0).
7645 This may cause the occasional harmless store of 0 when the value is
7646 already 0, but it seems to be OK according to the standards guys. */
7647 if (expand_atomic_compare_and_swap (NULL
, &target
, mem
, const0_rtx
,
7648 const0_rtx
, false, model
, model
))
7651 /* Otherwise there is no atomic load, leave the library call. */
7655 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7656 if (!target
|| target
== const0_rtx
)
7657 target
= gen_reg_rtx (mode
);
7659 /* For SEQ_CST, emit a barrier before the load. */
7660 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
)
7661 expand_mem_thread_fence (model
);
7663 emit_move_insn (target
, mem
);
7665 /* Emit the appropriate barrier after the load. */
7666 expand_mem_thread_fence (model
);
7671 /* This function expands the atomic store operation:
7672 Atomically store VAL in MEM.
7673 MEMMODEL is the memory model variant to use.
7674 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7675 function returns const0_rtx if a pattern was emitted. */
7678 expand_atomic_store (rtx mem
, rtx val
, enum memmodel model
, bool use_release
)
7680 enum machine_mode mode
= GET_MODE (mem
);
7681 enum insn_code icode
;
7682 struct expand_operand ops
[3];
7684 /* If the target supports the store directly, great. */
7685 icode
= direct_optab_handler (atomic_store_optab
, mode
);
7686 if (icode
!= CODE_FOR_nothing
)
7688 create_fixed_operand (&ops
[0], mem
);
7689 create_input_operand (&ops
[1], val
, mode
);
7690 create_integer_operand (&ops
[2], model
);
7691 if (maybe_expand_insn (icode
, 3, ops
))
7695 /* If using __sync_lock_release is a viable alternative, try it. */
7698 icode
= direct_optab_handler (sync_lock_release_optab
, mode
);
7699 if (icode
!= CODE_FOR_nothing
)
7701 create_fixed_operand (&ops
[0], mem
);
7702 create_input_operand (&ops
[1], const0_rtx
, mode
);
7703 if (maybe_expand_insn (icode
, 2, ops
))
7705 /* lock_release is only a release barrier. */
7706 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
)
7707 expand_mem_thread_fence (model
);
7713 /* If the size of the object is greater than word size on this target,
7714 a default store will not be atomic, Try a mem_exchange and throw away
7715 the result. If that doesn't work, don't do anything. */
7716 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7718 rtx target
= maybe_emit_atomic_exchange (NULL_RTX
, mem
, val
, model
);
7720 target
= maybe_emit_compare_and_swap_exchange_loop (NULL_RTX
, mem
, val
);
7727 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7728 expand_mem_thread_fence (model
);
7730 emit_move_insn (mem
, val
);
7732 /* For SEQ_CST, also emit a barrier after the store. */
7733 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
)
7734 expand_mem_thread_fence (model
);
7740 /* Structure containing the pointers and values required to process the
7741 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7743 struct atomic_op_functions
7745 direct_optab mem_fetch_before
;
7746 direct_optab mem_fetch_after
;
7747 direct_optab mem_no_result
;
7750 direct_optab no_result
;
7751 enum rtx_code reverse_code
;
7755 /* Fill in structure pointed to by OP with the various optab entries for an
7756 operation of type CODE. */
7759 get_atomic_op_for_code (struct atomic_op_functions
*op
, enum rtx_code code
)
7761 gcc_assert (op
!= NULL
);
7763 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7764 in the source code during compilation, and the optab entries are not
7765 computable until runtime. Fill in the values at runtime. */
7769 op
->mem_fetch_before
= atomic_fetch_add_optab
;
7770 op
->mem_fetch_after
= atomic_add_fetch_optab
;
7771 op
->mem_no_result
= atomic_add_optab
;
7772 op
->fetch_before
= sync_old_add_optab
;
7773 op
->fetch_after
= sync_new_add_optab
;
7774 op
->no_result
= sync_add_optab
;
7775 op
->reverse_code
= MINUS
;
7778 op
->mem_fetch_before
= atomic_fetch_sub_optab
;
7779 op
->mem_fetch_after
= atomic_sub_fetch_optab
;
7780 op
->mem_no_result
= atomic_sub_optab
;
7781 op
->fetch_before
= sync_old_sub_optab
;
7782 op
->fetch_after
= sync_new_sub_optab
;
7783 op
->no_result
= sync_sub_optab
;
7784 op
->reverse_code
= PLUS
;
7787 op
->mem_fetch_before
= atomic_fetch_xor_optab
;
7788 op
->mem_fetch_after
= atomic_xor_fetch_optab
;
7789 op
->mem_no_result
= atomic_xor_optab
;
7790 op
->fetch_before
= sync_old_xor_optab
;
7791 op
->fetch_after
= sync_new_xor_optab
;
7792 op
->no_result
= sync_xor_optab
;
7793 op
->reverse_code
= XOR
;
7796 op
->mem_fetch_before
= atomic_fetch_and_optab
;
7797 op
->mem_fetch_after
= atomic_and_fetch_optab
;
7798 op
->mem_no_result
= atomic_and_optab
;
7799 op
->fetch_before
= sync_old_and_optab
;
7800 op
->fetch_after
= sync_new_and_optab
;
7801 op
->no_result
= sync_and_optab
;
7802 op
->reverse_code
= UNKNOWN
;
7805 op
->mem_fetch_before
= atomic_fetch_or_optab
;
7806 op
->mem_fetch_after
= atomic_or_fetch_optab
;
7807 op
->mem_no_result
= atomic_or_optab
;
7808 op
->fetch_before
= sync_old_ior_optab
;
7809 op
->fetch_after
= sync_new_ior_optab
;
7810 op
->no_result
= sync_ior_optab
;
7811 op
->reverse_code
= UNKNOWN
;
7814 op
->mem_fetch_before
= atomic_fetch_nand_optab
;
7815 op
->mem_fetch_after
= atomic_nand_fetch_optab
;
7816 op
->mem_no_result
= atomic_nand_optab
;
7817 op
->fetch_before
= sync_old_nand_optab
;
7818 op
->fetch_after
= sync_new_nand_optab
;
7819 op
->no_result
= sync_nand_optab
;
7820 op
->reverse_code
= UNKNOWN
;
7827 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7828 using memory order MODEL. If AFTER is true the operation needs to return
7829 the value of *MEM after the operation, otherwise the previous value.
7830 TARGET is an optional place to place the result. The result is unused if
7832 Return the result if there is a better sequence, otherwise NULL_RTX. */
7835 maybe_optimize_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7836 enum memmodel model
, bool after
)
7838 /* If the value is prefetched, or not used, it may be possible to replace
7839 the sequence with a native exchange operation. */
7840 if (!after
|| target
== const0_rtx
)
7842 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7843 if (code
== AND
&& val
== const0_rtx
)
7845 if (target
== const0_rtx
)
7846 target
= gen_reg_rtx (GET_MODE (mem
));
7847 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7850 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7851 if (code
== IOR
&& val
== constm1_rtx
)
7853 if (target
== const0_rtx
)
7854 target
= gen_reg_rtx (GET_MODE (mem
));
7855 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7862 /* Try to emit an instruction for a specific operation varaition.
7863 OPTAB contains the OP functions.
7864 TARGET is an optional place to return the result. const0_rtx means unused.
7865 MEM is the memory location to operate on.
7866 VAL is the value to use in the operation.
7867 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7868 MODEL is the memory model, if used.
7869 AFTER is true if the returned result is the value after the operation. */
7872 maybe_emit_op (const struct atomic_op_functions
*optab
, rtx target
, rtx mem
,
7873 rtx val
, bool use_memmodel
, enum memmodel model
, bool after
)
7875 enum machine_mode mode
= GET_MODE (mem
);
7876 struct expand_operand ops
[4];
7877 enum insn_code icode
;
7881 /* Check to see if there is a result returned. */
7882 if (target
== const0_rtx
)
7886 icode
= direct_optab_handler (optab
->mem_no_result
, mode
);
7887 create_integer_operand (&ops
[2], model
);
7892 icode
= direct_optab_handler (optab
->no_result
, mode
);
7896 /* Otherwise, we need to generate a result. */
7901 icode
= direct_optab_handler (after
? optab
->mem_fetch_after
7902 : optab
->mem_fetch_before
, mode
);
7903 create_integer_operand (&ops
[3], model
);
7908 icode
= optab_handler (after
? optab
->fetch_after
7909 : optab
->fetch_before
, mode
);
7912 create_output_operand (&ops
[op_counter
++], target
, mode
);
7914 if (icode
== CODE_FOR_nothing
)
7917 create_fixed_operand (&ops
[op_counter
++], mem
);
7918 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7919 create_convert_operand_to (&ops
[op_counter
++], val
, mode
, true);
7921 if (maybe_expand_insn (icode
, num_ops
, ops
))
7922 return (target
== const0_rtx
? const0_rtx
: ops
[0].value
);
7928 /* This function expands an atomic fetch_OP or OP_fetch operation:
7929 TARGET is an option place to stick the return value. const0_rtx indicates
7930 the result is unused.
7931 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7932 CODE is the operation being performed (OP)
7933 MEMMODEL is the memory model variant to use.
7934 AFTER is true to return the result of the operation (OP_fetch).
7935 AFTER is false to return the value before the operation (fetch_OP).
7937 This function will *only* generate instructions if there is a direct
7938 optab. No compare and swap loops or libcalls will be generated. */
7941 expand_atomic_fetch_op_no_fallback (rtx target
, rtx mem
, rtx val
,
7942 enum rtx_code code
, enum memmodel model
,
7945 enum machine_mode mode
= GET_MODE (mem
);
7946 struct atomic_op_functions optab
;
7948 bool unused_result
= (target
== const0_rtx
);
7950 get_atomic_op_for_code (&optab
, code
);
7952 /* Check to see if there are any better instructions. */
7953 result
= maybe_optimize_fetch_op (target
, mem
, val
, code
, model
, after
);
7957 /* Check for the case where the result isn't used and try those patterns. */
7960 /* Try the memory model variant first. */
7961 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, true);
7965 /* Next try the old style withuot a memory model. */
7966 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, true);
7970 /* There is no no-result pattern, so try patterns with a result. */
7974 /* Try the __atomic version. */
7975 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, after
);
7979 /* Try the older __sync version. */
7980 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, after
);
7984 /* If the fetch value can be calculated from the other variation of fetch,
7985 try that operation. */
7986 if (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
)
7988 /* Try the __atomic version, then the older __sync version. */
7989 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, !after
);
7991 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, !after
);
7995 /* If the result isn't used, no need to do compensation code. */
7999 /* Issue compensation code. Fetch_after == fetch_before OP val.
8000 Fetch_before == after REVERSE_OP val. */
8002 code
= optab
.reverse_code
;
8005 result
= expand_simple_binop (mode
, AND
, result
, val
, NULL_RTX
,
8006 true, OPTAB_LIB_WIDEN
);
8007 result
= expand_simple_unop (mode
, NOT
, result
, target
, true);
8010 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
8011 true, OPTAB_LIB_WIDEN
);
8016 /* No direct opcode can be generated. */
8022 /* This function expands an atomic fetch_OP or OP_fetch operation:
8023 TARGET is an option place to stick the return value. const0_rtx indicates
8024 the result is unused.
8025 atomically fetch MEM, perform the operation with VAL and return it to MEM.
8026 CODE is the operation being performed (OP)
8027 MEMMODEL is the memory model variant to use.
8028 AFTER is true to return the result of the operation (OP_fetch).
8029 AFTER is false to return the value before the operation (fetch_OP). */
8031 expand_atomic_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
8032 enum memmodel model
, bool after
)
8034 enum machine_mode mode
= GET_MODE (mem
);
8036 bool unused_result
= (target
== const0_rtx
);
8038 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, val
, code
, model
,
8044 /* Add/sub can be implemented by doing the reverse operation with -(val). */
8045 if (code
== PLUS
|| code
== MINUS
)
8048 enum rtx_code reverse
= (code
== PLUS
? MINUS
: PLUS
);
8051 tmp
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, true);
8052 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, tmp
, reverse
,
8056 /* PLUS worked so emit the insns and return. */
8063 /* PLUS did not work, so throw away the negation code and continue. */
8067 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
8068 if (!can_compare_and_swap_p (mode
, false))
8072 enum rtx_code orig_code
= code
;
8073 struct atomic_op_functions optab
;
8075 get_atomic_op_for_code (&optab
, code
);
8076 libfunc
= optab_libfunc (after
? optab
.fetch_after
8077 : optab
.fetch_before
, mode
);
8079 && (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
))
8083 code
= optab
.reverse_code
;
8084 libfunc
= optab_libfunc (after
? optab
.fetch_before
8085 : optab
.fetch_after
, mode
);
8087 if (libfunc
!= NULL
)
8089 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
8090 result
= emit_library_call_value (libfunc
, NULL
, LCT_NORMAL
, mode
,
8091 2, addr
, ptr_mode
, val
, mode
);
8093 if (!unused_result
&& fixup
)
8094 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
8095 true, OPTAB_LIB_WIDEN
);
8099 /* We need the original code for any further attempts. */
8103 /* If nothing else has succeeded, default to a compare and swap loop. */
8104 if (can_compare_and_swap_p (mode
, true))
8107 rtx t0
= gen_reg_rtx (mode
), t1
;
8111 /* If the result is used, get a register for it. */
8114 if (!target
|| !register_operand (target
, mode
))
8115 target
= gen_reg_rtx (mode
);
8116 /* If fetch_before, copy the value now. */
8118 emit_move_insn (target
, t0
);
8121 target
= const0_rtx
;
8126 t1
= expand_simple_binop (mode
, AND
, t1
, val
, NULL_RTX
,
8127 true, OPTAB_LIB_WIDEN
);
8128 t1
= expand_simple_unop (mode
, code
, t1
, NULL_RTX
, true);
8131 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
, true,
8134 /* For after, copy the value now. */
8135 if (!unused_result
&& after
)
8136 emit_move_insn (target
, t1
);
8137 insn
= get_insns ();
8140 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
8147 /* Return true if OPERAND is suitable for operand number OPNO of
8148 instruction ICODE. */
8151 insn_operand_matches (enum insn_code icode
, unsigned int opno
, rtx operand
)
8153 return (!insn_data
[(int) icode
].operand
[opno
].predicate
8154 || (insn_data
[(int) icode
].operand
[opno
].predicate
8155 (operand
, insn_data
[(int) icode
].operand
[opno
].mode
)));
8158 /* TARGET is a target of a multiword operation that we are going to
8159 implement as a series of word-mode operations. Return true if
8160 TARGET is suitable for this purpose. */
8163 valid_multiword_target_p (rtx target
)
8165 enum machine_mode mode
;
8168 mode
= GET_MODE (target
);
8169 for (i
= 0; i
< GET_MODE_SIZE (mode
); i
+= UNITS_PER_WORD
)
8170 if (!validate_subreg (word_mode
, mode
, target
, i
))
8175 /* Like maybe_legitimize_operand, but do not change the code of the
8176 current rtx value. */
8179 maybe_legitimize_operand_same_code (enum insn_code icode
, unsigned int opno
,
8180 struct expand_operand
*op
)
8182 /* See if the operand matches in its current form. */
8183 if (insn_operand_matches (icode
, opno
, op
->value
))
8186 /* If the operand is a memory whose address has no side effects,
8187 try forcing the address into a non-virtual pseudo register.
8188 The check for side effects is important because copy_to_mode_reg
8189 cannot handle things like auto-modified addresses. */
8190 if (insn_data
[(int) icode
].operand
[opno
].allows_mem
&& MEM_P (op
->value
))
8195 addr
= XEXP (mem
, 0);
8196 if (!(REG_P (addr
) && REGNO (addr
) > LAST_VIRTUAL_REGISTER
)
8197 && !side_effects_p (addr
))
8200 enum machine_mode mode
;
8202 last
= get_last_insn ();
8203 mode
= get_address_mode (mem
);
8204 mem
= replace_equiv_address (mem
, copy_to_mode_reg (mode
, addr
));
8205 if (insn_operand_matches (icode
, opno
, mem
))
8210 delete_insns_since (last
);
8217 /* Try to make OP match operand OPNO of instruction ICODE. Return true
8218 on success, storing the new operand value back in OP. */
8221 maybe_legitimize_operand (enum insn_code icode
, unsigned int opno
,
8222 struct expand_operand
*op
)
8224 enum machine_mode mode
, imode
;
8225 bool old_volatile_ok
, result
;
8231 old_volatile_ok
= volatile_ok
;
8233 result
= maybe_legitimize_operand_same_code (icode
, opno
, op
);
8234 volatile_ok
= old_volatile_ok
;
8238 gcc_assert (mode
!= VOIDmode
);
8240 && op
->value
!= const0_rtx
8241 && GET_MODE (op
->value
) == mode
8242 && maybe_legitimize_operand_same_code (icode
, opno
, op
))
8245 op
->value
= gen_reg_rtx (mode
);
8250 gcc_assert (mode
!= VOIDmode
);
8251 gcc_assert (GET_MODE (op
->value
) == VOIDmode
8252 || GET_MODE (op
->value
) == mode
);
8253 if (maybe_legitimize_operand_same_code (icode
, opno
, op
))
8256 op
->value
= copy_to_mode_reg (mode
, op
->value
);
8259 case EXPAND_CONVERT_TO
:
8260 gcc_assert (mode
!= VOIDmode
);
8261 op
->value
= convert_to_mode (mode
, op
->value
, op
->unsigned_p
);
8264 case EXPAND_CONVERT_FROM
:
8265 if (GET_MODE (op
->value
) != VOIDmode
)
8266 mode
= GET_MODE (op
->value
);
8268 /* The caller must tell us what mode this value has. */
8269 gcc_assert (mode
!= VOIDmode
);
8271 imode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8272 if (imode
!= VOIDmode
&& imode
!= mode
)
8274 op
->value
= convert_modes (imode
, mode
, op
->value
, op
->unsigned_p
);
8279 case EXPAND_ADDRESS
:
8280 gcc_assert (mode
!= VOIDmode
);
8281 op
->value
= convert_memory_address (mode
, op
->value
);
8284 case EXPAND_INTEGER
:
8285 mode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8286 if (mode
!= VOIDmode
&& const_int_operand (op
->value
, mode
))
8290 return insn_operand_matches (icode
, opno
, op
->value
);
8293 /* Make OP describe an input operand that should have the same value
8294 as VALUE, after any mode conversion that the target might request.
8295 TYPE is the type of VALUE. */
8298 create_convert_operand_from_type (struct expand_operand
*op
,
8299 rtx value
, tree type
)
8301 create_convert_operand_from (op
, value
, TYPE_MODE (type
),
8302 TYPE_UNSIGNED (type
));
8305 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
8306 of instruction ICODE. Return true on success, leaving the new operand
8307 values in the OPS themselves. Emit no code on failure. */
8310 maybe_legitimize_operands (enum insn_code icode
, unsigned int opno
,
8311 unsigned int nops
, struct expand_operand
*ops
)
8316 last
= get_last_insn ();
8317 for (i
= 0; i
< nops
; i
++)
8318 if (!maybe_legitimize_operand (icode
, opno
+ i
, &ops
[i
]))
8320 delete_insns_since (last
);
8326 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
8327 as its operands. Return the instruction pattern on success,
8328 and emit any necessary set-up code. Return null and emit no
8332 maybe_gen_insn (enum insn_code icode
, unsigned int nops
,
8333 struct expand_operand
*ops
)
8335 gcc_assert (nops
== (unsigned int) insn_data
[(int) icode
].n_generator_args
);
8336 if (!maybe_legitimize_operands (icode
, 0, nops
, ops
))
8342 return GEN_FCN (icode
) (ops
[0].value
);
8344 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
);
8346 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
);
8348 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8351 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8352 ops
[3].value
, ops
[4].value
);
8354 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8355 ops
[3].value
, ops
[4].value
, ops
[5].value
);
8357 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8358 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8361 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8362 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8363 ops
[6].value
, ops
[7].value
);
8365 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8366 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8367 ops
[6].value
, ops
[7].value
, ops
[8].value
);
8372 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
8373 as its operands. Return true on success and emit no code on failure. */
8376 maybe_expand_insn (enum insn_code icode
, unsigned int nops
,
8377 struct expand_operand
*ops
)
8379 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8388 /* Like maybe_expand_insn, but for jumps. */
8391 maybe_expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8392 struct expand_operand
*ops
)
8394 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8397 emit_jump_insn (pat
);
8403 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8407 expand_insn (enum insn_code icode
, unsigned int nops
,
8408 struct expand_operand
*ops
)
8410 if (!maybe_expand_insn (icode
, nops
, ops
))
8414 /* Like expand_insn, but for jumps. */
8417 expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8418 struct expand_operand
*ops
)
8420 if (!maybe_expand_jump_insn (icode
, nops
, ops
))
8424 /* Reduce conditional compilation elsewhere. */
8427 #define CODE_FOR_insv CODE_FOR_nothing
8431 #define CODE_FOR_extv CODE_FOR_nothing
8434 #define HAVE_extzv 0
8435 #define CODE_FOR_extzv CODE_FOR_nothing
8438 /* Enumerates the possible types of structure operand to an
8440 enum extraction_type
{ ET_unaligned_mem
, ET_reg
};
8442 /* Check whether insv, extv or extzv pattern ICODE can be used for an
8443 insertion or extraction of type TYPE on a structure of mode MODE.
8444 Return true if so and fill in *INSN accordingly. STRUCT_OP is the
8445 operand number of the structure (the first sign_extract or zero_extract
8446 operand) and FIELD_OP is the operand number of the field (the other
8447 side of the set from the sign_extract or zero_extract). */
8450 get_traditional_extraction_insn (extraction_insn
*insn
,
8451 enum extraction_type type
,
8452 enum machine_mode mode
,
8453 enum insn_code icode
,
8454 int struct_op
, int field_op
)
8456 const struct insn_data_d
*data
= &insn_data
[icode
];
8458 enum machine_mode struct_mode
= data
->operand
[struct_op
].mode
;
8459 if (struct_mode
== VOIDmode
)
8460 struct_mode
= word_mode
;
8461 if (mode
!= struct_mode
)
8464 enum machine_mode field_mode
= data
->operand
[field_op
].mode
;
8465 if (field_mode
== VOIDmode
)
8466 field_mode
= word_mode
;
8468 enum machine_mode pos_mode
= data
->operand
[struct_op
+ 2].mode
;
8469 if (pos_mode
== VOIDmode
)
8470 pos_mode
= word_mode
;
8472 insn
->icode
= icode
;
8473 insn
->field_mode
= field_mode
;
8474 insn
->struct_mode
= (type
== ET_unaligned_mem
? byte_mode
: struct_mode
);
8475 insn
->pos_mode
= pos_mode
;
8479 /* Return true if an optab exists to perform an insertion or extraction
8480 of type TYPE in mode MODE. Describe the instruction in *INSN if so.
8482 REG_OPTAB is the optab to use for register structures and
8483 MISALIGN_OPTAB is the optab to use for misaligned memory structures.
8484 POS_OP is the operand number of the bit position. */
8487 get_optab_extraction_insn (struct extraction_insn
*insn
,
8488 enum extraction_type type
,
8489 enum machine_mode mode
, direct_optab reg_optab
,
8490 direct_optab misalign_optab
, int pos_op
)
8492 direct_optab optab
= (type
== ET_unaligned_mem
? misalign_optab
: reg_optab
);
8493 enum insn_code icode
= direct_optab_handler (optab
, mode
);
8494 if (icode
== CODE_FOR_nothing
)
8497 const struct insn_data_d
*data
= &insn_data
[icode
];
8499 insn
->icode
= icode
;
8500 insn
->field_mode
= mode
;
8501 insn
->struct_mode
= (type
== ET_unaligned_mem
? BLKmode
: mode
);
8502 insn
->pos_mode
= data
->operand
[pos_op
].mode
;
8503 if (insn
->pos_mode
== VOIDmode
)
8504 insn
->pos_mode
= word_mode
;
8508 /* Return true if an instruction exists to perform an insertion or
8509 extraction (PATTERN says which) of type TYPE in mode MODE.
8510 Describe the instruction in *INSN if so. */
8513 get_extraction_insn (extraction_insn
*insn
,
8514 enum extraction_pattern pattern
,
8515 enum extraction_type type
,
8516 enum machine_mode mode
)
8522 && get_traditional_extraction_insn (insn
, type
, mode
,
8523 CODE_FOR_insv
, 0, 3))
8525 return get_optab_extraction_insn (insn
, type
, mode
, insv_optab
,
8526 insvmisalign_optab
, 2);
8530 && get_traditional_extraction_insn (insn
, type
, mode
,
8531 CODE_FOR_extv
, 1, 0))
8533 return get_optab_extraction_insn (insn
, type
, mode
, extv_optab
,
8534 extvmisalign_optab
, 3);
8538 && get_traditional_extraction_insn (insn
, type
, mode
,
8539 CODE_FOR_extzv
, 1, 0))
8541 return get_optab_extraction_insn (insn
, type
, mode
, extzv_optab
,
8542 extzvmisalign_optab
, 3);
8549 /* Return true if an instruction exists to access a field of mode
8550 FIELDMODE in a structure that has STRUCT_BITS significant bits.
8551 Describe the "best" such instruction in *INSN if so. PATTERN and
8552 TYPE describe the type of insertion or extraction we want to perform.
8554 For an insertion, the number of significant structure bits includes
8555 all bits of the target. For an extraction, it need only include the
8556 most significant bit of the field. Larger widths are acceptable
8560 get_best_extraction_insn (extraction_insn
*insn
,
8561 enum extraction_pattern pattern
,
8562 enum extraction_type type
,
8563 unsigned HOST_WIDE_INT struct_bits
,
8564 enum machine_mode field_mode
)
8566 enum machine_mode mode
= smallest_mode_for_size (struct_bits
, MODE_INT
);
8567 while (mode
!= VOIDmode
)
8569 if (get_extraction_insn (insn
, pattern
, type
, mode
))
8571 while (mode
!= VOIDmode
8572 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (field_mode
)
8573 && !TRULY_NOOP_TRUNCATION_MODES_P (insn
->field_mode
,
8576 get_extraction_insn (insn
, pattern
, type
, mode
);
8577 mode
= GET_MODE_WIDER_MODE (mode
);
8581 mode
= GET_MODE_WIDER_MODE (mode
);
8586 /* Return true if an instruction exists to access a field of mode
8587 FIELDMODE in a register structure that has STRUCT_BITS significant bits.
8588 Describe the "best" such instruction in *INSN if so. PATTERN describes
8589 the type of insertion or extraction we want to perform.
8591 For an insertion, the number of significant structure bits includes
8592 all bits of the target. For an extraction, it need only include the
8593 most significant bit of the field. Larger widths are acceptable
8597 get_best_reg_extraction_insn (extraction_insn
*insn
,
8598 enum extraction_pattern pattern
,
8599 unsigned HOST_WIDE_INT struct_bits
,
8600 enum machine_mode field_mode
)
8602 return get_best_extraction_insn (insn
, pattern
, ET_reg
, struct_bits
,
8606 /* Return true if an instruction exists to access a field of BITSIZE
8607 bits starting BITNUM bits into a memory structure. Describe the
8608 "best" such instruction in *INSN if so. PATTERN describes the type
8609 of insertion or extraction we want to perform and FIELDMODE is the
8610 natural mode of the extracted field.
8612 The instructions considered here only access bytes that overlap
8613 the bitfield; they do not touch any surrounding bytes. */
8616 get_best_mem_extraction_insn (extraction_insn
*insn
,
8617 enum extraction_pattern pattern
,
8618 HOST_WIDE_INT bitsize
, HOST_WIDE_INT bitnum
,
8619 enum machine_mode field_mode
)
8621 unsigned HOST_WIDE_INT struct_bits
= (bitnum
% BITS_PER_UNIT
8623 + BITS_PER_UNIT
- 1);
8624 struct_bits
-= struct_bits
% BITS_PER_UNIT
;
8625 return get_best_extraction_insn (insn
, pattern
, ET_unaligned_mem
,
8626 struct_bits
, field_mode
);
8629 #include "gt-optabs.h"