PR rtl-optimization/57439
[official-gcc.git] / gcc / postreload.c
blob558ab8b867ea21715c6834f44d9c028c7e40f785
1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "tm.h"
25 #include "machmode.h"
26 #include "hard-reg-set.h"
27 #include "rtl.h"
28 #include "tm_p.h"
29 #include "obstack.h"
30 #include "insn-config.h"
31 #include "flags.h"
32 #include "function.h"
33 #include "expr.h"
34 #include "optabs.h"
35 #include "regs.h"
36 #include "basic-block.h"
37 #include "reload.h"
38 #include "recog.h"
39 #include "cselib.h"
40 #include "diagnostic-core.h"
41 #include "except.h"
42 #include "tree.h"
43 #include "target.h"
44 #include "tree-pass.h"
45 #include "df.h"
46 #include "dbgcnt.h"
48 static int reload_cse_noop_set_p (rtx);
49 static bool reload_cse_simplify (rtx, rtx);
50 static void reload_cse_regs_1 (void);
51 static int reload_cse_simplify_set (rtx, rtx);
52 static int reload_cse_simplify_operands (rtx, rtx);
54 static void reload_combine (void);
55 static void reload_combine_note_use (rtx *, rtx, int, rtx);
56 static void reload_combine_note_store (rtx, const_rtx, void *);
58 static bool reload_cse_move2add (rtx);
59 static void move2add_note_store (rtx, const_rtx, void *);
61 /* Call cse / combine like post-reload optimization phases.
62 FIRST is the first instruction. */
64 static void
65 reload_cse_regs (rtx first ATTRIBUTE_UNUSED)
67 bool moves_converted;
68 reload_cse_regs_1 ();
69 reload_combine ();
70 moves_converted = reload_cse_move2add (first);
71 if (flag_expensive_optimizations)
73 if (moves_converted)
74 reload_combine ();
75 reload_cse_regs_1 ();
79 /* See whether a single set SET is a noop. */
80 static int
81 reload_cse_noop_set_p (rtx set)
83 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
84 return 0;
86 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
89 /* Try to simplify INSN. Return true if the CFG may have changed. */
90 static bool
91 reload_cse_simplify (rtx insn, rtx testreg)
93 rtx body = PATTERN (insn);
94 basic_block insn_bb = BLOCK_FOR_INSN (insn);
95 unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
97 if (GET_CODE (body) == SET)
99 int count = 0;
101 /* Simplify even if we may think it is a no-op.
102 We may think a memory load of a value smaller than WORD_SIZE
103 is redundant because we haven't taken into account possible
104 implicit extension. reload_cse_simplify_set() will bring
105 this out, so it's safer to simplify before we delete. */
106 count += reload_cse_simplify_set (body, insn);
108 if (!count && reload_cse_noop_set_p (body))
110 rtx value = SET_DEST (body);
111 if (REG_P (value)
112 && ! REG_FUNCTION_VALUE_P (value))
113 value = 0;
114 if (check_for_inc_dec (insn))
115 delete_insn_and_edges (insn);
116 /* We're done with this insn. */
117 goto done;
120 if (count > 0)
121 apply_change_group ();
122 else
123 reload_cse_simplify_operands (insn, testreg);
125 else if (GET_CODE (body) == PARALLEL)
127 int i;
128 int count = 0;
129 rtx value = NULL_RTX;
131 /* Registers mentioned in the clobber list for an asm cannot be reused
132 within the body of the asm. Invalidate those registers now so that
133 we don't try to substitute values for them. */
134 if (asm_noperands (body) >= 0)
136 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
138 rtx part = XVECEXP (body, 0, i);
139 if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0)))
140 cselib_invalidate_rtx (XEXP (part, 0));
144 /* If every action in a PARALLEL is a noop, we can delete
145 the entire PARALLEL. */
146 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
148 rtx part = XVECEXP (body, 0, i);
149 if (GET_CODE (part) == SET)
151 if (! reload_cse_noop_set_p (part))
152 break;
153 if (REG_P (SET_DEST (part))
154 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
156 if (value)
157 break;
158 value = SET_DEST (part);
161 else if (GET_CODE (part) != CLOBBER)
162 break;
165 if (i < 0)
167 if (check_for_inc_dec (insn))
168 delete_insn_and_edges (insn);
169 /* We're done with this insn. */
170 goto done;
173 /* It's not a no-op, but we can try to simplify it. */
174 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
175 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
176 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
178 if (count > 0)
179 apply_change_group ();
180 else
181 reload_cse_simplify_operands (insn, testreg);
184 done:
185 return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs);
188 /* Do a very simple CSE pass over the hard registers.
190 This function detects no-op moves where we happened to assign two
191 different pseudo-registers to the same hard register, and then
192 copied one to the other. Reload will generate a useless
193 instruction copying a register to itself.
195 This function also detects cases where we load a value from memory
196 into two different registers, and (if memory is more expensive than
197 registers) changes it to simply copy the first register into the
198 second register.
200 Another optimization is performed that scans the operands of each
201 instruction to see whether the value is already available in a
202 hard register. It then replaces the operand with the hard register
203 if possible, much like an optional reload would. */
205 static void
206 reload_cse_regs_1 (void)
208 bool cfg_changed = false;
209 basic_block bb;
210 rtx insn;
211 rtx testreg = gen_rtx_REG (VOIDmode, -1);
213 cselib_init (CSELIB_RECORD_MEMORY);
214 init_alias_analysis ();
216 FOR_EACH_BB (bb)
217 FOR_BB_INSNS (bb, insn)
219 if (INSN_P (insn))
220 cfg_changed |= reload_cse_simplify (insn, testreg);
222 cselib_process_insn (insn);
225 /* Clean up. */
226 end_alias_analysis ();
227 cselib_finish ();
228 if (cfg_changed)
229 cleanup_cfg (0);
232 /* Try to simplify a single SET instruction. SET is the set pattern.
233 INSN is the instruction it came from.
234 This function only handles one case: if we set a register to a value
235 which is not a register, we try to find that value in some other register
236 and change the set into a register copy. */
238 static int
239 reload_cse_simplify_set (rtx set, rtx insn)
241 int did_change = 0;
242 int dreg;
243 rtx src;
244 reg_class_t dclass;
245 int old_cost;
246 cselib_val *val;
247 struct elt_loc_list *l;
248 #ifdef LOAD_EXTEND_OP
249 enum rtx_code extend_op = UNKNOWN;
250 #endif
251 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
253 dreg = true_regnum (SET_DEST (set));
254 if (dreg < 0)
255 return 0;
257 src = SET_SRC (set);
258 if (side_effects_p (src) || true_regnum (src) >= 0)
259 return 0;
261 dclass = REGNO_REG_CLASS (dreg);
263 #ifdef LOAD_EXTEND_OP
264 /* When replacing a memory with a register, we need to honor assumptions
265 that combine made wrt the contents of sign bits. We'll do this by
266 generating an extend instruction instead of a reg->reg copy. Thus
267 the destination must be a register that we can widen. */
268 if (MEM_P (src)
269 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
270 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN
271 && !REG_P (SET_DEST (set)))
272 return 0;
273 #endif
275 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode);
276 if (! val)
277 return 0;
279 /* If memory loads are cheaper than register copies, don't change them. */
280 if (MEM_P (src))
281 old_cost = memory_move_cost (GET_MODE (src), dclass, true);
282 else if (REG_P (src))
283 old_cost = register_move_cost (GET_MODE (src),
284 REGNO_REG_CLASS (REGNO (src)), dclass);
285 else
286 old_cost = set_src_cost (src, speed);
288 for (l = val->locs; l; l = l->next)
290 rtx this_rtx = l->loc;
291 int this_cost;
293 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
295 #ifdef LOAD_EXTEND_OP
296 if (extend_op != UNKNOWN)
298 HOST_WIDE_INT this_val;
300 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
301 constants, such as SYMBOL_REF, cannot be extended. */
302 if (!CONST_INT_P (this_rtx))
303 continue;
305 this_val = INTVAL (this_rtx);
306 switch (extend_op)
308 case ZERO_EXTEND:
309 this_val &= GET_MODE_MASK (GET_MODE (src));
310 break;
311 case SIGN_EXTEND:
312 /* ??? In theory we're already extended. */
313 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
314 break;
315 default:
316 gcc_unreachable ();
318 this_rtx = GEN_INT (this_val);
320 #endif
321 this_cost = set_src_cost (this_rtx, speed);
323 else if (REG_P (this_rtx))
325 #ifdef LOAD_EXTEND_OP
326 if (extend_op != UNKNOWN)
328 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
329 this_cost = set_src_cost (this_rtx, speed);
331 else
332 #endif
333 this_cost = register_move_cost (GET_MODE (this_rtx),
334 REGNO_REG_CLASS (REGNO (this_rtx)),
335 dclass);
337 else
338 continue;
340 /* If equal costs, prefer registers over anything else. That
341 tends to lead to smaller instructions on some machines. */
342 if (this_cost < old_cost
343 || (this_cost == old_cost
344 && REG_P (this_rtx)
345 && !REG_P (SET_SRC (set))))
347 #ifdef LOAD_EXTEND_OP
348 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
349 && extend_op != UNKNOWN
350 #ifdef CANNOT_CHANGE_MODE_CLASS
351 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
352 word_mode,
353 REGNO_REG_CLASS (REGNO (SET_DEST (set))))
354 #endif
357 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
358 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
359 validate_change (insn, &SET_DEST (set), wide_dest, 1);
361 #endif
363 validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
364 old_cost = this_cost, did_change = 1;
368 return did_change;
371 /* Try to replace operands in INSN with equivalent values that are already
372 in registers. This can be viewed as optional reloading.
374 For each non-register operand in the insn, see if any hard regs are
375 known to be equivalent to that operand. Record the alternatives which
376 can accept these hard registers. Among all alternatives, select the
377 ones which are better or equal to the one currently matching, where
378 "better" is in terms of '?' and '!' constraints. Among the remaining
379 alternatives, select the one which replaces most operands with
380 hard registers. */
382 static int
383 reload_cse_simplify_operands (rtx insn, rtx testreg)
385 int i, j;
387 /* For each operand, all registers that are equivalent to it. */
388 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
390 const char *constraints[MAX_RECOG_OPERANDS];
392 /* Vector recording how bad an alternative is. */
393 int *alternative_reject;
394 /* Vector recording how many registers can be introduced by choosing
395 this alternative. */
396 int *alternative_nregs;
397 /* Array of vectors recording, for each operand and each alternative,
398 which hard register to substitute, or -1 if the operand should be
399 left as it is. */
400 int *op_alt_regno[MAX_RECOG_OPERANDS];
401 /* Array of alternatives, sorted in order of decreasing desirability. */
402 int *alternative_order;
404 extract_insn (insn);
406 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
407 return 0;
409 /* Figure out which alternative currently matches. */
410 if (! constrain_operands (1))
411 fatal_insn_not_found (insn);
413 alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
414 alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
415 alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
416 memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
417 memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
419 /* For each operand, find out which regs are equivalent. */
420 for (i = 0; i < recog_data.n_operands; i++)
422 cselib_val *v;
423 struct elt_loc_list *l;
424 rtx op;
426 CLEAR_HARD_REG_SET (equiv_regs[i]);
428 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
429 right, so avoid the problem here. Likewise if we have a constant
430 and the insn pattern doesn't tell us the mode we need. */
431 if (LABEL_P (recog_data.operand[i])
432 || (CONSTANT_P (recog_data.operand[i])
433 && recog_data.operand_mode[i] == VOIDmode))
434 continue;
436 op = recog_data.operand[i];
437 #ifdef LOAD_EXTEND_OP
438 if (MEM_P (op)
439 && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD
440 && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN)
442 rtx set = single_set (insn);
444 /* We might have multiple sets, some of which do implicit
445 extension. Punt on this for now. */
446 if (! set)
447 continue;
448 /* If the destination is also a MEM or a STRICT_LOW_PART, no
449 extension applies.
450 Also, if there is an explicit extension, we don't have to
451 worry about an implicit one. */
452 else if (MEM_P (SET_DEST (set))
453 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
454 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND
455 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
456 ; /* Continue ordinary processing. */
457 #ifdef CANNOT_CHANGE_MODE_CLASS
458 /* If the register cannot change mode to word_mode, it follows that
459 it cannot have been used in word_mode. */
460 else if (REG_P (SET_DEST (set))
461 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
462 word_mode,
463 REGNO_REG_CLASS (REGNO (SET_DEST (set)))))
464 ; /* Continue ordinary processing. */
465 #endif
466 /* If this is a straight load, make the extension explicit. */
467 else if (REG_P (SET_DEST (set))
468 && recog_data.n_operands == 2
469 && SET_SRC (set) == op
470 && SET_DEST (set) == recog_data.operand[1-i])
472 validate_change (insn, recog_data.operand_loc[i],
473 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)),
474 word_mode, op),
476 validate_change (insn, recog_data.operand_loc[1-i],
477 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
479 if (! apply_change_group ())
480 return 0;
481 return reload_cse_simplify_operands (insn, testreg);
483 else
484 /* ??? There might be arithmetic operations with memory that are
485 safe to optimize, but is it worth the trouble? */
486 continue;
488 #endif /* LOAD_EXTEND_OP */
489 if (side_effects_p (op))
490 continue;
491 v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode);
492 if (! v)
493 continue;
495 for (l = v->locs; l; l = l->next)
496 if (REG_P (l->loc))
497 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
500 for (i = 0; i < recog_data.n_operands; i++)
502 enum machine_mode mode;
503 int regno;
504 const char *p;
506 op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
507 for (j = 0; j < recog_data.n_alternatives; j++)
508 op_alt_regno[i][j] = -1;
510 p = constraints[i] = recog_data.constraints[i];
511 mode = recog_data.operand_mode[i];
513 /* Add the reject values for each alternative given by the constraints
514 for this operand. */
515 j = 0;
516 while (*p != '\0')
518 char c = *p++;
519 if (c == ',')
520 j++;
521 else if (c == '?')
522 alternative_reject[j] += 3;
523 else if (c == '!')
524 alternative_reject[j] += 300;
527 /* We won't change operands which are already registers. We
528 also don't want to modify output operands. */
529 regno = true_regnum (recog_data.operand[i]);
530 if (regno >= 0
531 || constraints[i][0] == '='
532 || constraints[i][0] == '+')
533 continue;
535 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
537 enum reg_class rclass = NO_REGS;
539 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
540 continue;
542 SET_REGNO_RAW (testreg, regno);
543 PUT_MODE (testreg, mode);
545 /* We found a register equal to this operand. Now look for all
546 alternatives that can accept this register and have not been
547 assigned a register they can use yet. */
548 j = 0;
549 p = constraints[i];
550 for (;;)
552 char c = *p;
554 switch (c)
556 case '=': case '+': case '?':
557 case '#': case '&': case '!':
558 case '*': case '%':
559 case '0': case '1': case '2': case '3': case '4':
560 case '5': case '6': case '7': case '8': case '9':
561 case '<': case '>': case 'V': case 'o':
562 case 'E': case 'F': case 'G': case 'H':
563 case 's': case 'i': case 'n':
564 case 'I': case 'J': case 'K': case 'L':
565 case 'M': case 'N': case 'O': case 'P':
566 case 'p': case 'X': case TARGET_MEM_CONSTRAINT:
567 /* These don't say anything we care about. */
568 break;
570 case 'g': case 'r':
571 rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS];
572 break;
574 default:
575 rclass
576 = (reg_class_subunion
577 [(int) rclass]
578 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
579 break;
581 case ',': case '\0':
582 /* See if REGNO fits this alternative, and set it up as the
583 replacement register if we don't have one for this
584 alternative yet and the operand being replaced is not
585 a cheap CONST_INT. */
586 if (op_alt_regno[i][j] == -1
587 && recog_data.alternative_enabled_p[j]
588 && reg_fits_class_p (testreg, rclass, 0, mode)
589 && (!CONST_INT_P (recog_data.operand[i])
590 || (set_src_cost (recog_data.operand[i],
591 optimize_bb_for_speed_p
592 (BLOCK_FOR_INSN (insn)))
593 > set_src_cost (testreg,
594 optimize_bb_for_speed_p
595 (BLOCK_FOR_INSN (insn))))))
597 alternative_nregs[j]++;
598 op_alt_regno[i][j] = regno;
600 j++;
601 rclass = NO_REGS;
602 break;
604 p += CONSTRAINT_LEN (c, p);
606 if (c == '\0')
607 break;
612 /* Record all alternatives which are better or equal to the currently
613 matching one in the alternative_order array. */
614 for (i = j = 0; i < recog_data.n_alternatives; i++)
615 if (alternative_reject[i] <= alternative_reject[which_alternative])
616 alternative_order[j++] = i;
617 recog_data.n_alternatives = j;
619 /* Sort it. Given a small number of alternatives, a dumb algorithm
620 won't hurt too much. */
621 for (i = 0; i < recog_data.n_alternatives - 1; i++)
623 int best = i;
624 int best_reject = alternative_reject[alternative_order[i]];
625 int best_nregs = alternative_nregs[alternative_order[i]];
626 int tmp;
628 for (j = i + 1; j < recog_data.n_alternatives; j++)
630 int this_reject = alternative_reject[alternative_order[j]];
631 int this_nregs = alternative_nregs[alternative_order[j]];
633 if (this_reject < best_reject
634 || (this_reject == best_reject && this_nregs > best_nregs))
636 best = j;
637 best_reject = this_reject;
638 best_nregs = this_nregs;
642 tmp = alternative_order[best];
643 alternative_order[best] = alternative_order[i];
644 alternative_order[i] = tmp;
647 /* Substitute the operands as determined by op_alt_regno for the best
648 alternative. */
649 j = alternative_order[0];
651 for (i = 0; i < recog_data.n_operands; i++)
653 enum machine_mode mode = recog_data.operand_mode[i];
654 if (op_alt_regno[i][j] == -1)
655 continue;
657 validate_change (insn, recog_data.operand_loc[i],
658 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
661 for (i = recog_data.n_dups - 1; i >= 0; i--)
663 int op = recog_data.dup_num[i];
664 enum machine_mode mode = recog_data.operand_mode[op];
666 if (op_alt_regno[op][j] == -1)
667 continue;
669 validate_change (insn, recog_data.dup_loc[i],
670 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
673 return apply_change_group ();
676 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
677 addressing now.
678 This code might also be useful when reload gave up on reg+reg addressing
679 because of clashes between the return register and INDEX_REG_CLASS. */
681 /* The maximum number of uses of a register we can keep track of to
682 replace them with reg+reg addressing. */
683 #define RELOAD_COMBINE_MAX_USES 16
685 /* Describes a recorded use of a register. */
686 struct reg_use
688 /* The insn where a register has been used. */
689 rtx insn;
690 /* Points to the memory reference enclosing the use, if any, NULL_RTX
691 otherwise. */
692 rtx containing_mem;
693 /* Location of the register within INSN. */
694 rtx *usep;
695 /* The reverse uid of the insn. */
696 int ruid;
699 /* If the register is used in some unknown fashion, USE_INDEX is negative.
700 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
701 indicates where it is first set or clobbered.
702 Otherwise, USE_INDEX is the index of the last encountered use of the
703 register (which is first among these we have seen since we scan backwards).
704 USE_RUID indicates the first encountered, i.e. last, of these uses.
705 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
706 with a constant offset; OFFSET contains this constant in that case.
707 STORE_RUID is always meaningful if we only want to use a value in a
708 register in a different place: it denotes the next insn in the insn
709 stream (i.e. the last encountered) that sets or clobbers the register.
710 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
711 static struct
713 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
714 rtx offset;
715 int use_index;
716 int store_ruid;
717 int real_store_ruid;
718 int use_ruid;
719 bool all_offsets_match;
720 } reg_state[FIRST_PSEUDO_REGISTER];
722 /* Reverse linear uid. This is increased in reload_combine while scanning
723 the instructions from last to first. It is used to set last_label_ruid
724 and the store_ruid / use_ruid fields in reg_state. */
725 static int reload_combine_ruid;
727 /* The RUID of the last label we encountered in reload_combine. */
728 static int last_label_ruid;
730 /* The RUID of the last jump we encountered in reload_combine. */
731 static int last_jump_ruid;
733 /* The register numbers of the first and last index register. A value of
734 -1 in LAST_INDEX_REG indicates that we've previously computed these
735 values and found no suitable index registers. */
736 static int first_index_reg = -1;
737 static int last_index_reg;
739 #define LABEL_LIVE(LABEL) \
740 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
742 /* Subroutine of reload_combine_split_ruids, called to fix up a single
743 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
745 static inline void
746 reload_combine_split_one_ruid (int *pruid, int split_ruid)
748 if (*pruid > split_ruid)
749 (*pruid)++;
752 /* Called when we insert a new insn in a position we've already passed in
753 the scan. Examine all our state, increasing all ruids that are higher
754 than SPLIT_RUID by one in order to make room for a new insn. */
756 static void
757 reload_combine_split_ruids (int split_ruid)
759 unsigned i;
761 reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
762 reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
763 reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
767 int j, idx = reg_state[i].use_index;
768 reload_combine_split_one_ruid (&reg_state[i].use_ruid, split_ruid);
769 reload_combine_split_one_ruid (&reg_state[i].store_ruid, split_ruid);
770 reload_combine_split_one_ruid (&reg_state[i].real_store_ruid,
771 split_ruid);
772 if (idx < 0)
773 continue;
774 for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
776 reload_combine_split_one_ruid (&reg_state[i].reg_use[j].ruid,
777 split_ruid);
782 /* Called when we are about to rescan a previously encountered insn with
783 reload_combine_note_use after modifying some part of it. This clears all
784 information about uses in that particular insn. */
786 static void
787 reload_combine_purge_insn_uses (rtx insn)
789 unsigned i;
791 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
793 int j, k, idx = reg_state[i].use_index;
794 if (idx < 0)
795 continue;
796 j = k = RELOAD_COMBINE_MAX_USES;
797 while (j-- > idx)
799 if (reg_state[i].reg_use[j].insn != insn)
801 k--;
802 if (k != j)
803 reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
806 reg_state[i].use_index = k;
810 /* Called when we need to forget about all uses of REGNO after an insn
811 which is identified by RUID. */
813 static void
814 reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
816 int j, k, idx = reg_state[regno].use_index;
817 if (idx < 0)
818 return;
819 j = k = RELOAD_COMBINE_MAX_USES;
820 while (j-- > idx)
822 if (reg_state[regno].reg_use[j].ruid >= ruid)
824 k--;
825 if (k != j)
826 reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
829 reg_state[regno].use_index = k;
832 /* Find the use of REGNO with the ruid that is highest among those
833 lower than RUID_LIMIT, and return it if it is the only use of this
834 reg in the insn. Return NULL otherwise. */
836 static struct reg_use *
837 reload_combine_closest_single_use (unsigned regno, int ruid_limit)
839 int i, best_ruid = 0;
840 int use_idx = reg_state[regno].use_index;
841 struct reg_use *retval;
843 if (use_idx < 0)
844 return NULL;
845 retval = NULL;
846 for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
848 struct reg_use *use = reg_state[regno].reg_use + i;
849 int this_ruid = use->ruid;
850 if (this_ruid >= ruid_limit)
851 continue;
852 if (this_ruid > best_ruid)
854 best_ruid = this_ruid;
855 retval = use;
857 else if (this_ruid == best_ruid)
858 retval = NULL;
860 if (last_label_ruid >= best_ruid)
861 return NULL;
862 return retval;
865 /* After we've moved an add insn, fix up any debug insns that occur
866 between the old location of the add and the new location. REG is
867 the destination register of the add insn; REPLACEMENT is the
868 SET_SRC of the add. FROM and TO specify the range in which we
869 should make this change on debug insns. */
871 static void
872 fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to)
874 rtx insn;
875 for (insn = from; insn != to; insn = NEXT_INSN (insn))
877 rtx t;
879 if (!DEBUG_INSN_P (insn))
880 continue;
882 t = INSN_VAR_LOCATION_LOC (insn);
883 t = simplify_replace_rtx (t, reg, replacement);
884 validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
888 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
889 with SRC in the insn described by USE, taking costs into account. Return
890 true if we made the replacement. */
892 static bool
893 try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
895 rtx use_insn = use->insn;
896 rtx mem = use->containing_mem;
897 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
899 if (mem != NULL_RTX)
901 addr_space_t as = MEM_ADDR_SPACE (mem);
902 rtx oldaddr = XEXP (mem, 0);
903 rtx newaddr = NULL_RTX;
904 int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
905 int new_cost;
907 newaddr = simplify_replace_rtx (oldaddr, reg, src);
908 if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
910 XEXP (mem, 0) = newaddr;
911 new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
912 XEXP (mem, 0) = oldaddr;
913 if (new_cost <= old_cost
914 && validate_change (use_insn,
915 &XEXP (mem, 0), newaddr, 0))
916 return true;
919 else
921 rtx new_set = single_set (use_insn);
922 if (new_set
923 && REG_P (SET_DEST (new_set))
924 && GET_CODE (SET_SRC (new_set)) == PLUS
925 && REG_P (XEXP (SET_SRC (new_set), 0))
926 && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
928 rtx new_src;
929 int old_cost = set_src_cost (SET_SRC (new_set), speed);
931 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
932 new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
934 if (set_src_cost (new_src, speed) <= old_cost
935 && validate_change (use_insn, &SET_SRC (new_set),
936 new_src, 0))
937 return true;
940 return false;
943 /* Called by reload_combine when scanning INSN. This function tries to detect
944 patterns where a constant is added to a register, and the result is used
945 in an address.
946 Return true if no further processing is needed on INSN; false if it wasn't
947 recognized and should be handled normally. */
949 static bool
950 reload_combine_recognize_const_pattern (rtx insn)
952 int from_ruid = reload_combine_ruid;
953 rtx set, pat, reg, src, addreg;
954 unsigned int regno;
955 struct reg_use *use;
956 bool must_move_add;
957 rtx add_moved_after_insn = NULL_RTX;
958 int add_moved_after_ruid = 0;
959 int clobbered_regno = -1;
961 set = single_set (insn);
962 if (set == NULL_RTX)
963 return false;
965 reg = SET_DEST (set);
966 src = SET_SRC (set);
967 if (!REG_P (reg)
968 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1
969 || GET_MODE (reg) != Pmode
970 || reg == stack_pointer_rtx)
971 return false;
973 regno = REGNO (reg);
975 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
976 uses of REG1 inside an address, or inside another add insn. If
977 possible and profitable, merge the addition into subsequent
978 uses. */
979 if (GET_CODE (src) != PLUS
980 || !REG_P (XEXP (src, 0))
981 || !CONSTANT_P (XEXP (src, 1)))
982 return false;
984 addreg = XEXP (src, 0);
985 must_move_add = rtx_equal_p (reg, addreg);
987 pat = PATTERN (insn);
988 if (must_move_add && set != pat)
990 /* We have to be careful when moving the add; apart from the
991 single_set there may also be clobbers. Recognize one special
992 case, that of one clobber alongside the set (likely a clobber
993 of the CC register). */
994 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
995 if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
996 || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
997 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
998 return false;
999 clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
1004 use = reload_combine_closest_single_use (regno, from_ruid);
1006 if (use)
1007 /* Start the search for the next use from here. */
1008 from_ruid = use->ruid;
1010 if (use && GET_MODE (*use->usep) == Pmode)
1012 bool delete_add = false;
1013 rtx use_insn = use->insn;
1014 int use_ruid = use->ruid;
1016 /* Avoid moving the add insn past a jump. */
1017 if (must_move_add && use_ruid <= last_jump_ruid)
1018 break;
1020 /* If the add clobbers another hard reg in parallel, don't move
1021 it past a real set of this hard reg. */
1022 if (must_move_add && clobbered_regno >= 0
1023 && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
1024 break;
1026 #ifdef HAVE_cc0
1027 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
1028 if (must_move_add && sets_cc0_p (PATTERN (use_insn)))
1029 break;
1030 #endif
1032 gcc_assert (reg_state[regno].store_ruid <= use_ruid);
1033 /* Avoid moving a use of ADDREG past a point where it is stored. */
1034 if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
1035 break;
1037 /* We also must not move the addition past an insn that sets
1038 the same register, unless we can combine two add insns. */
1039 if (must_move_add && reg_state[regno].store_ruid == use_ruid)
1041 if (use->containing_mem == NULL_RTX)
1042 delete_add = true;
1043 else
1044 break;
1047 if (try_replace_in_use (use, reg, src))
1049 reload_combine_purge_insn_uses (use_insn);
1050 reload_combine_note_use (&PATTERN (use_insn), use_insn,
1051 use_ruid, NULL_RTX);
1053 if (delete_add)
1055 fixup_debug_insns (reg, src, insn, use_insn);
1056 delete_insn (insn);
1057 return true;
1059 if (must_move_add)
1061 add_moved_after_insn = use_insn;
1062 add_moved_after_ruid = use_ruid;
1064 continue;
1067 /* If we get here, we couldn't handle this use. */
1068 if (must_move_add)
1069 break;
1071 while (use);
1073 if (!must_move_add || add_moved_after_insn == NULL_RTX)
1074 /* Process the add normally. */
1075 return false;
1077 fixup_debug_insns (reg, src, insn, add_moved_after_insn);
1079 reorder_insns (insn, insn, add_moved_after_insn);
1080 reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
1081 reload_combine_split_ruids (add_moved_after_ruid - 1);
1082 reload_combine_note_use (&PATTERN (insn), insn,
1083 add_moved_after_ruid, NULL_RTX);
1084 reg_state[regno].store_ruid = add_moved_after_ruid;
1086 return true;
1089 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1090 can handle and improve. Return true if no further processing is needed on
1091 INSN; false if it wasn't recognized and should be handled normally. */
1093 static bool
1094 reload_combine_recognize_pattern (rtx insn)
1096 rtx set, reg, src;
1097 unsigned int regno;
1099 set = single_set (insn);
1100 if (set == NULL_RTX)
1101 return false;
1103 reg = SET_DEST (set);
1104 src = SET_SRC (set);
1105 if (!REG_P (reg)
1106 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1)
1107 return false;
1109 regno = REGNO (reg);
1111 /* Look for (set (REGX) (CONST_INT))
1112 (set (REGX) (PLUS (REGX) (REGY)))
1114 ... (MEM (REGX)) ...
1115 and convert it to
1116 (set (REGZ) (CONST_INT))
1118 ... (MEM (PLUS (REGZ) (REGY)))... .
1120 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1121 and that we know all uses of REGX before it dies.
1122 Also, explicitly check that REGX != REGY; our life information
1123 does not yet show whether REGY changes in this insn. */
1125 if (GET_CODE (src) == PLUS
1126 && reg_state[regno].all_offsets_match
1127 && last_index_reg != -1
1128 && REG_P (XEXP (src, 1))
1129 && rtx_equal_p (XEXP (src, 0), reg)
1130 && !rtx_equal_p (XEXP (src, 1), reg)
1131 && reg_state[regno].use_index >= 0
1132 && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES
1133 && last_label_ruid < reg_state[regno].use_ruid)
1135 rtx base = XEXP (src, 1);
1136 rtx prev = prev_nonnote_nondebug_insn (insn);
1137 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
1138 rtx index_reg = NULL_RTX;
1139 rtx reg_sum = NULL_RTX;
1140 int i;
1142 /* Now we need to set INDEX_REG to an index register (denoted as
1143 REGZ in the illustration above) and REG_SUM to the expression
1144 register+register that we want to use to substitute uses of REG
1145 (typically in MEMs) with. First check REG and BASE for being
1146 index registers; we can use them even if they are not dead. */
1147 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
1148 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
1149 REGNO (base)))
1151 index_reg = reg;
1152 reg_sum = src;
1154 else
1156 /* Otherwise, look for a free index register. Since we have
1157 checked above that neither REG nor BASE are index registers,
1158 if we find anything at all, it will be different from these
1159 two registers. */
1160 for (i = first_index_reg; i <= last_index_reg; i++)
1162 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
1163 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
1164 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
1165 && (call_used_regs[i] || df_regs_ever_live_p (i))
1166 && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
1167 && !fixed_regs[i] && !global_regs[i]
1168 && hard_regno_nregs[i][GET_MODE (reg)] == 1
1169 && targetm.hard_regno_scratch_ok (i))
1171 index_reg = gen_rtx_REG (GET_MODE (reg), i);
1172 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
1173 break;
1178 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1179 (REGY), i.e. BASE, is not clobbered before the last use we'll
1180 create. */
1181 if (reg_sum
1182 && prev_set
1183 && CONST_INT_P (SET_SRC (prev_set))
1184 && rtx_equal_p (SET_DEST (prev_set), reg)
1185 && (reg_state[REGNO (base)].store_ruid
1186 <= reg_state[regno].use_ruid))
1188 /* Change destination register and, if necessary, the constant
1189 value in PREV, the constant loading instruction. */
1190 validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
1191 if (reg_state[regno].offset != const0_rtx)
1192 validate_change (prev,
1193 &SET_SRC (prev_set),
1194 GEN_INT (INTVAL (SET_SRC (prev_set))
1195 + INTVAL (reg_state[regno].offset)),
1198 /* Now for every use of REG that we have recorded, replace REG
1199 with REG_SUM. */
1200 for (i = reg_state[regno].use_index;
1201 i < RELOAD_COMBINE_MAX_USES; i++)
1202 validate_unshare_change (reg_state[regno].reg_use[i].insn,
1203 reg_state[regno].reg_use[i].usep,
1204 /* Each change must have its own
1205 replacement. */
1206 reg_sum, 1);
1208 if (apply_change_group ())
1210 struct reg_use *lowest_ruid = NULL;
1212 /* For every new use of REG_SUM, we have to record the use
1213 of BASE therein, i.e. operand 1. */
1214 for (i = reg_state[regno].use_index;
1215 i < RELOAD_COMBINE_MAX_USES; i++)
1217 struct reg_use *use = reg_state[regno].reg_use + i;
1218 reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
1219 use->ruid, use->containing_mem);
1220 if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
1221 lowest_ruid = use;
1224 fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
1226 /* Delete the reg-reg addition. */
1227 delete_insn (insn);
1229 if (reg_state[regno].offset != const0_rtx)
1230 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1231 are now invalid. */
1232 remove_reg_equal_equiv_notes (prev);
1234 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
1235 return true;
1239 return false;
1242 static void
1243 reload_combine (void)
1245 rtx insn, prev;
1246 basic_block bb;
1247 unsigned int r;
1248 int min_labelno, n_labels;
1249 HARD_REG_SET ever_live_at_start, *label_live;
1251 /* To avoid wasting too much time later searching for an index register,
1252 determine the minimum and maximum index register numbers. */
1253 if (INDEX_REG_CLASS == NO_REGS)
1254 last_index_reg = -1;
1255 else if (first_index_reg == -1 && last_index_reg == 0)
1257 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1258 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
1260 if (first_index_reg == -1)
1261 first_index_reg = r;
1263 last_index_reg = r;
1266 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1267 to -1 so we'll know to quit early the next time we get here. */
1268 if (first_index_reg == -1)
1270 last_index_reg = -1;
1271 return;
1275 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1276 information is a bit fuzzy immediately after reload, but it's
1277 still good enough to determine which registers are live at a jump
1278 destination. */
1279 min_labelno = get_first_label_num ();
1280 n_labels = max_label_num () - min_labelno;
1281 label_live = XNEWVEC (HARD_REG_SET, n_labels);
1282 CLEAR_HARD_REG_SET (ever_live_at_start);
1284 FOR_EACH_BB_REVERSE (bb)
1286 insn = BB_HEAD (bb);
1287 if (LABEL_P (insn))
1289 HARD_REG_SET live;
1290 bitmap live_in = df_get_live_in (bb);
1292 REG_SET_TO_HARD_REG_SET (live, live_in);
1293 compute_use_by_pseudos (&live, live_in);
1294 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
1295 IOR_HARD_REG_SET (ever_live_at_start, live);
1299 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1300 last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
1301 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1303 reg_state[r].store_ruid = 0;
1304 reg_state[r].real_store_ruid = 0;
1305 if (fixed_regs[r])
1306 reg_state[r].use_index = -1;
1307 else
1308 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1311 for (insn = get_last_insn (); insn; insn = prev)
1313 bool control_flow_insn;
1314 rtx note;
1316 prev = PREV_INSN (insn);
1318 /* We cannot do our optimization across labels. Invalidating all the use
1319 information we have would be costly, so we just note where the label
1320 is and then later disable any optimization that would cross it. */
1321 if (LABEL_P (insn))
1322 last_label_ruid = reload_combine_ruid;
1323 else if (BARRIER_P (insn))
1325 /* Crossing a barrier resets all the use information. */
1326 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1327 if (! fixed_regs[r])
1328 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1330 else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn)))
1331 /* Optimizations across insns being marked as volatile must be
1332 prevented. All the usage information is invalidated
1333 here. */
1334 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1335 if (! fixed_regs[r]
1336 && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES)
1337 reg_state[r].use_index = -1;
1339 if (! NONDEBUG_INSN_P (insn))
1340 continue;
1342 reload_combine_ruid++;
1344 control_flow_insn = control_flow_insn_p (insn);
1345 if (control_flow_insn)
1346 last_jump_ruid = reload_combine_ruid;
1348 if (reload_combine_recognize_const_pattern (insn)
1349 || reload_combine_recognize_pattern (insn))
1350 continue;
1352 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
1354 if (CALL_P (insn))
1356 rtx link;
1358 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1359 if (call_used_regs[r])
1361 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1362 reg_state[r].store_ruid = reload_combine_ruid;
1365 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
1366 link = XEXP (link, 1))
1368 rtx setuse = XEXP (link, 0);
1369 rtx usage_rtx = XEXP (setuse, 0);
1370 if ((GET_CODE (setuse) == USE || GET_CODE (setuse) == CLOBBER)
1371 && REG_P (usage_rtx))
1373 unsigned int i;
1374 unsigned int start_reg = REGNO (usage_rtx);
1375 unsigned int num_regs
1376 = hard_regno_nregs[start_reg][GET_MODE (usage_rtx)];
1377 unsigned int end_reg = start_reg + num_regs - 1;
1378 for (i = start_reg; i <= end_reg; i++)
1379 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
1381 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1382 reg_state[i].store_ruid = reload_combine_ruid;
1384 else
1385 reg_state[i].use_index = -1;
1390 if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn)))
1392 /* Non-spill registers might be used at the call destination in
1393 some unknown fashion, so we have to mark the unknown use. */
1394 HARD_REG_SET *live;
1396 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
1397 && JUMP_LABEL (insn))
1399 if (ANY_RETURN_P (JUMP_LABEL (insn)))
1400 live = NULL;
1401 else
1402 live = &LABEL_LIVE (JUMP_LABEL (insn));
1404 else
1405 live = &ever_live_at_start;
1407 if (live)
1408 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1409 if (TEST_HARD_REG_BIT (*live, r))
1410 reg_state[r].use_index = -1;
1413 reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid,
1414 NULL_RTX);
1416 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1418 if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0)))
1420 int regno = REGNO (XEXP (note, 0));
1421 reg_state[regno].store_ruid = reload_combine_ruid;
1422 reg_state[regno].real_store_ruid = reload_combine_ruid;
1423 reg_state[regno].use_index = -1;
1428 free (label_live);
1431 /* Check if DST is a register or a subreg of a register; if it is,
1432 update store_ruid, real_store_ruid and use_index in the reg_state
1433 structure accordingly. Called via note_stores from reload_combine. */
1435 static void
1436 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
1438 int regno = 0;
1439 int i;
1440 enum machine_mode mode = GET_MODE (dst);
1442 if (GET_CODE (dst) == SUBREG)
1444 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
1445 GET_MODE (SUBREG_REG (dst)),
1446 SUBREG_BYTE (dst),
1447 GET_MODE (dst));
1448 dst = SUBREG_REG (dst);
1451 /* Some targets do argument pushes without adding REG_INC notes. */
1453 if (MEM_P (dst))
1455 dst = XEXP (dst, 0);
1456 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
1457 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC
1458 || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY)
1460 regno = REGNO (XEXP (dst, 0));
1461 mode = GET_MODE (XEXP (dst, 0));
1462 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1464 /* We could probably do better, but for now mark the register
1465 as used in an unknown fashion and set/clobbered at this
1466 insn. */
1467 reg_state[i].use_index = -1;
1468 reg_state[i].store_ruid = reload_combine_ruid;
1469 reg_state[i].real_store_ruid = reload_combine_ruid;
1472 else
1473 return;
1476 if (!REG_P (dst))
1477 return;
1478 regno += REGNO (dst);
1480 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1481 careful with registers / register parts that are not full words.
1482 Similarly for ZERO_EXTRACT. */
1483 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
1484 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1486 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1488 reg_state[i].use_index = -1;
1489 reg_state[i].store_ruid = reload_combine_ruid;
1490 reg_state[i].real_store_ruid = reload_combine_ruid;
1493 else
1495 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1497 reg_state[i].store_ruid = reload_combine_ruid;
1498 if (GET_CODE (set) == SET)
1499 reg_state[i].real_store_ruid = reload_combine_ruid;
1500 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1505 /* XP points to a piece of rtl that has to be checked for any uses of
1506 registers.
1507 *XP is the pattern of INSN, or a part of it.
1508 Called from reload_combine, and recursively by itself. */
1509 static void
1510 reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem)
1512 rtx x = *xp;
1513 enum rtx_code code = x->code;
1514 const char *fmt;
1515 int i, j;
1516 rtx offset = const0_rtx; /* For the REG case below. */
1518 switch (code)
1520 case SET:
1521 if (REG_P (SET_DEST (x)))
1523 reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
1524 return;
1526 break;
1528 case USE:
1529 /* If this is the USE of a return value, we can't change it. */
1530 if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
1532 /* Mark the return register as used in an unknown fashion. */
1533 rtx reg = XEXP (x, 0);
1534 int regno = REGNO (reg);
1535 int nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1537 while (--nregs >= 0)
1538 reg_state[regno + nregs].use_index = -1;
1539 return;
1541 break;
1543 case CLOBBER:
1544 if (REG_P (SET_DEST (x)))
1546 /* No spurious CLOBBERs of pseudo registers may remain. */
1547 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER);
1548 return;
1550 break;
1552 case PLUS:
1553 /* We are interested in (plus (reg) (const_int)) . */
1554 if (!REG_P (XEXP (x, 0))
1555 || !CONST_INT_P (XEXP (x, 1)))
1556 break;
1557 offset = XEXP (x, 1);
1558 x = XEXP (x, 0);
1559 /* Fall through. */
1560 case REG:
1562 int regno = REGNO (x);
1563 int use_index;
1564 int nregs;
1566 /* No spurious USEs of pseudo registers may remain. */
1567 gcc_assert (regno < FIRST_PSEUDO_REGISTER);
1569 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1571 /* We can't substitute into multi-hard-reg uses. */
1572 if (nregs > 1)
1574 while (--nregs >= 0)
1575 reg_state[regno + nregs].use_index = -1;
1576 return;
1579 /* We may be called to update uses in previously seen insns.
1580 Don't add uses beyond the last store we saw. */
1581 if (ruid < reg_state[regno].store_ruid)
1582 return;
1584 /* If this register is already used in some unknown fashion, we
1585 can't do anything.
1586 If we decrement the index from zero to -1, we can't store more
1587 uses, so this register becomes used in an unknown fashion. */
1588 use_index = --reg_state[regno].use_index;
1589 if (use_index < 0)
1590 return;
1592 if (use_index == RELOAD_COMBINE_MAX_USES - 1)
1594 /* This is the first use of this register we have seen since we
1595 marked it as dead. */
1596 reg_state[regno].offset = offset;
1597 reg_state[regno].all_offsets_match = true;
1598 reg_state[regno].use_ruid = ruid;
1600 else
1602 if (reg_state[regno].use_ruid > ruid)
1603 reg_state[regno].use_ruid = ruid;
1605 if (! rtx_equal_p (offset, reg_state[regno].offset))
1606 reg_state[regno].all_offsets_match = false;
1609 reg_state[regno].reg_use[use_index].insn = insn;
1610 reg_state[regno].reg_use[use_index].ruid = ruid;
1611 reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
1612 reg_state[regno].reg_use[use_index].usep = xp;
1613 return;
1616 case MEM:
1617 containing_mem = x;
1618 break;
1620 default:
1621 break;
1624 /* Recursively process the components of X. */
1625 fmt = GET_RTX_FORMAT (code);
1626 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1628 if (fmt[i] == 'e')
1629 reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
1630 else if (fmt[i] == 'E')
1632 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1633 reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
1634 containing_mem);
1639 /* See if we can reduce the cost of a constant by replacing a move
1640 with an add. We track situations in which a register is set to a
1641 constant or to a register plus a constant. */
1642 /* We cannot do our optimization across labels. Invalidating all the
1643 information about register contents we have would be costly, so we
1644 use move2add_last_label_luid to note where the label is and then
1645 later disable any optimization that would cross it.
1646 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1647 are only valid if reg_set_luid[n] is greater than
1648 move2add_last_label_luid.
1649 For a set that established a new (potential) base register with
1650 non-constant value, we use move2add_luid from the place where the
1651 setting insn is encountered; registers based off that base then
1652 get the same reg_set_luid. Constants all get
1653 move2add_last_label_luid + 1 as their reg_set_luid. */
1654 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
1656 /* If reg_base_reg[n] is negative, register n has been set to
1657 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1658 If reg_base_reg[n] is non-negative, register n has been set to the
1659 sum of reg_offset[n] and the value of register reg_base_reg[n]
1660 before reg_set_luid[n], calculated in mode reg_mode[n] .
1661 For multi-hard-register registers, all but the first one are
1662 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1663 marks it as invalid. */
1664 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
1665 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
1666 static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER];
1667 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
1669 /* move2add_luid is linearly increased while scanning the instructions
1670 from first to last. It is used to set reg_set_luid in
1671 reload_cse_move2add and move2add_note_store. */
1672 static int move2add_luid;
1674 /* move2add_last_label_luid is set whenever a label is found. Labels
1675 invalidate all previously collected reg_offset data. */
1676 static int move2add_last_label_luid;
1678 /* ??? We don't know how zero / sign extension is handled, hence we
1679 can't go from a narrower to a wider mode. */
1680 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1681 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1682 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1683 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1685 /* Record that REG is being set to a value with the mode of REG. */
1687 static void
1688 move2add_record_mode (rtx reg)
1690 int regno, nregs;
1691 enum machine_mode mode = GET_MODE (reg);
1693 if (GET_CODE (reg) == SUBREG)
1695 regno = subreg_regno (reg);
1696 nregs = subreg_nregs (reg);
1698 else if (REG_P (reg))
1700 regno = REGNO (reg);
1701 nregs = hard_regno_nregs[regno][mode];
1703 else
1704 gcc_unreachable ();
1705 for (int i = nregs - 1; i > 0; i--)
1706 reg_mode[regno + i] = BLKmode;
1707 reg_mode[regno] = mode;
1710 /* Record that REG is being set to the sum of SYM and OFF. */
1712 static void
1713 move2add_record_sym_value (rtx reg, rtx sym, rtx off)
1715 int regno = REGNO (reg);
1717 move2add_record_mode (reg);
1718 reg_set_luid[regno] = move2add_luid;
1719 reg_base_reg[regno] = -1;
1720 reg_symbol_ref[regno] = sym;
1721 reg_offset[regno] = INTVAL (off);
1724 /* Check if REGNO contains a valid value in MODE. */
1726 static bool
1727 move2add_valid_value_p (int regno, enum machine_mode mode)
1729 if (reg_set_luid[regno] <= move2add_last_label_luid
1730 || !MODES_OK_FOR_MOVE2ADD (mode, reg_mode[regno]))
1731 return false;
1733 for (int i = hard_regno_nregs[regno][mode] - 1; i > 0; i--)
1734 if (reg_mode[regno + i] != BLKmode)
1735 return false;
1736 return true;
1739 /* This function is called with INSN that sets REG to (SYM + OFF),
1740 while REG is known to already have value (SYM + offset).
1741 This function tries to change INSN into an add instruction
1742 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1743 It also updates the information about REG's known value.
1744 Return true if we made a change. */
1746 static bool
1747 move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
1749 rtx pat = PATTERN (insn);
1750 rtx src = SET_SRC (pat);
1751 int regno = REGNO (reg);
1752 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
1753 GET_MODE (reg));
1754 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1755 bool changed = false;
1757 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1758 use (set (reg) (reg)) instead.
1759 We don't delete this insn, nor do we convert it into a
1760 note, to avoid losing register notes or the return
1761 value flag. jump2 already knows how to get rid of
1762 no-op moves. */
1763 if (new_src == const0_rtx)
1765 /* If the constants are different, this is a
1766 truncation, that, if turned into (set (reg)
1767 (reg)), would be discarded. Maybe we should
1768 try a truncMN pattern? */
1769 if (INTVAL (off) == reg_offset [regno])
1770 changed = validate_change (insn, &SET_SRC (pat), reg, 0);
1772 else
1774 struct full_rtx_costs oldcst, newcst;
1775 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
1777 get_full_set_rtx_cost (pat, &oldcst);
1778 SET_SRC (pat) = tem;
1779 get_full_set_rtx_cost (pat, &newcst);
1780 SET_SRC (pat) = src;
1782 if (costs_lt_p (&newcst, &oldcst, speed)
1783 && have_add2_insn (reg, new_src))
1784 changed = validate_change (insn, &SET_SRC (pat), tem, 0);
1785 else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
1787 enum machine_mode narrow_mode;
1788 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
1789 narrow_mode != VOIDmode
1790 && narrow_mode != GET_MODE (reg);
1791 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
1793 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
1794 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode))
1795 == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode))))
1797 rtx narrow_reg = gen_lowpart_common (narrow_mode, reg);
1798 rtx narrow_src = gen_int_mode (INTVAL (off),
1799 narrow_mode);
1800 rtx new_set
1801 = gen_rtx_SET (VOIDmode,
1802 gen_rtx_STRICT_LOW_PART (VOIDmode,
1803 narrow_reg),
1804 narrow_src);
1805 changed = validate_change (insn, &PATTERN (insn),
1806 new_set, 0);
1807 if (changed)
1808 break;
1813 move2add_record_sym_value (reg, sym, off);
1814 return changed;
1818 /* This function is called with INSN that sets REG to (SYM + OFF),
1819 but REG doesn't have known value (SYM + offset). This function
1820 tries to find another register which is known to already have
1821 value (SYM + offset) and change INSN into an add instruction
1822 (set (REG) (plus (the found register) (OFF - offset))) if such
1823 a register is found. It also updates the information about
1824 REG's known value.
1825 Return true iff we made a change. */
1827 static bool
1828 move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
1830 rtx pat = PATTERN (insn);
1831 rtx src = SET_SRC (pat);
1832 int regno = REGNO (reg);
1833 int min_regno = 0;
1834 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1835 int i;
1836 bool changed = false;
1837 struct full_rtx_costs oldcst, newcst, mincst;
1838 rtx plus_expr;
1840 init_costs_to_max (&mincst);
1841 get_full_set_rtx_cost (pat, &oldcst);
1843 plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx);
1844 SET_SRC (pat) = plus_expr;
1846 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1847 if (move2add_valid_value_p (i, GET_MODE (reg))
1848 && reg_base_reg[i] < 0
1849 && reg_symbol_ref[i] != NULL_RTX
1850 && rtx_equal_p (sym, reg_symbol_ref[i]))
1852 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i],
1853 GET_MODE (reg));
1854 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1855 use (set (reg) (reg)) instead.
1856 We don't delete this insn, nor do we convert it into a
1857 note, to avoid losing register notes or the return
1858 value flag. jump2 already knows how to get rid of
1859 no-op moves. */
1860 if (new_src == const0_rtx)
1862 init_costs_to_zero (&mincst);
1863 min_regno = i;
1864 break;
1866 else
1868 XEXP (plus_expr, 1) = new_src;
1869 get_full_set_rtx_cost (pat, &newcst);
1871 if (costs_lt_p (&newcst, &mincst, speed))
1873 mincst = newcst;
1874 min_regno = i;
1878 SET_SRC (pat) = src;
1880 if (costs_lt_p (&mincst, &oldcst, speed))
1882 rtx tem;
1884 tem = gen_rtx_REG (GET_MODE (reg), min_regno);
1885 if (i != min_regno)
1887 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno],
1888 GET_MODE (reg));
1889 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
1891 if (validate_change (insn, &SET_SRC (pat), tem, 0))
1892 changed = true;
1894 reg_set_luid[regno] = move2add_luid;
1895 move2add_record_sym_value (reg, sym, off);
1896 return changed;
1899 /* Convert move insns with constant inputs to additions if they are cheaper.
1900 Return true if any changes were made. */
1901 static bool
1902 reload_cse_move2add (rtx first)
1904 int i;
1905 rtx insn;
1906 bool changed = false;
1908 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1910 reg_set_luid[i] = 0;
1911 reg_offset[i] = 0;
1912 reg_base_reg[i] = 0;
1913 reg_symbol_ref[i] = NULL_RTX;
1914 reg_mode[i] = VOIDmode;
1917 move2add_last_label_luid = 0;
1918 move2add_luid = 2;
1919 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
1921 rtx pat, note;
1923 if (LABEL_P (insn))
1925 move2add_last_label_luid = move2add_luid;
1926 /* We're going to increment move2add_luid twice after a
1927 label, so that we can use move2add_last_label_luid + 1 as
1928 the luid for constants. */
1929 move2add_luid++;
1930 continue;
1932 if (! INSN_P (insn))
1933 continue;
1934 pat = PATTERN (insn);
1935 /* For simplicity, we only perform this optimization on
1936 straightforward SETs. */
1937 if (GET_CODE (pat) == SET
1938 && REG_P (SET_DEST (pat)))
1940 rtx reg = SET_DEST (pat);
1941 int regno = REGNO (reg);
1942 rtx src = SET_SRC (pat);
1944 /* Check if we have valid information on the contents of this
1945 register in the mode of REG. */
1946 if (move2add_valid_value_p (regno, GET_MODE (reg))
1947 && dbg_cnt (cse2_move2add))
1949 /* Try to transform (set (REGX) (CONST_INT A))
1951 (set (REGX) (CONST_INT B))
1953 (set (REGX) (CONST_INT A))
1955 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1957 (set (REGX) (CONST_INT A))
1959 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1962 if (CONST_INT_P (src)
1963 && reg_base_reg[regno] < 0
1964 && reg_symbol_ref[regno] == NULL_RTX)
1966 changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn);
1967 continue;
1970 /* Try to transform (set (REGX) (REGY))
1971 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1973 (set (REGX) (REGY))
1974 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1976 (set (REGX) (REGY))
1977 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1979 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1980 else if (REG_P (src)
1981 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
1982 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
1983 && move2add_valid_value_p (REGNO (src), GET_MODE (reg)))
1985 rtx next = next_nonnote_nondebug_insn (insn);
1986 rtx set = NULL_RTX;
1987 if (next)
1988 set = single_set (next);
1989 if (set
1990 && SET_DEST (set) == reg
1991 && GET_CODE (SET_SRC (set)) == PLUS
1992 && XEXP (SET_SRC (set), 0) == reg
1993 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
1995 rtx src3 = XEXP (SET_SRC (set), 1);
1996 HOST_WIDE_INT added_offset = INTVAL (src3);
1997 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
1998 HOST_WIDE_INT regno_offset = reg_offset[regno];
1999 rtx new_src =
2000 gen_int_mode (added_offset
2001 + base_offset
2002 - regno_offset,
2003 GET_MODE (reg));
2004 bool success = false;
2005 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
2007 if (new_src == const0_rtx)
2008 /* See above why we create (set (reg) (reg)) here. */
2009 success
2010 = validate_change (next, &SET_SRC (set), reg, 0);
2011 else
2013 rtx old_src = SET_SRC (set);
2014 struct full_rtx_costs oldcst, newcst;
2015 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
2017 get_full_set_rtx_cost (set, &oldcst);
2018 SET_SRC (set) = tem;
2019 get_full_set_src_cost (tem, &newcst);
2020 SET_SRC (set) = old_src;
2021 costs_add_n_insns (&oldcst, 1);
2023 if (costs_lt_p (&newcst, &oldcst, speed)
2024 && have_add2_insn (reg, new_src))
2026 rtx newpat = gen_rtx_SET (VOIDmode, reg, tem);
2027 success
2028 = validate_change (next, &PATTERN (next),
2029 newpat, 0);
2032 if (success)
2033 delete_insn (insn);
2034 changed |= success;
2035 insn = next;
2036 move2add_record_mode (reg);
2037 reg_offset[regno]
2038 = trunc_int_for_mode (added_offset + base_offset,
2039 GET_MODE (reg));
2040 continue;
2045 /* Try to transform
2046 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2048 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2050 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2052 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2053 if ((GET_CODE (src) == SYMBOL_REF
2054 || (GET_CODE (src) == CONST
2055 && GET_CODE (XEXP (src, 0)) == PLUS
2056 && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
2057 && CONST_INT_P (XEXP (XEXP (src, 0), 1))))
2058 && dbg_cnt (cse2_move2add))
2060 rtx sym, off;
2062 if (GET_CODE (src) == SYMBOL_REF)
2064 sym = src;
2065 off = const0_rtx;
2067 else
2069 sym = XEXP (XEXP (src, 0), 0);
2070 off = XEXP (XEXP (src, 0), 1);
2073 /* If the reg already contains the value which is sum of
2074 sym and some constant value, we can use an add2 insn. */
2075 if (move2add_valid_value_p (regno, GET_MODE (reg))
2076 && reg_base_reg[regno] < 0
2077 && reg_symbol_ref[regno] != NULL_RTX
2078 && rtx_equal_p (sym, reg_symbol_ref[regno]))
2079 changed |= move2add_use_add2_insn (reg, sym, off, insn);
2081 /* Otherwise, we have to find a register whose value is sum
2082 of sym and some constant value. */
2083 else
2084 changed |= move2add_use_add3_insn (reg, sym, off, insn);
2086 continue;
2090 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2092 if (REG_NOTE_KIND (note) == REG_INC
2093 && REG_P (XEXP (note, 0)))
2095 /* Reset the information about this register. */
2096 int regno = REGNO (XEXP (note, 0));
2097 if (regno < FIRST_PSEUDO_REGISTER)
2099 move2add_record_mode (XEXP (note, 0));
2100 reg_mode[regno] = VOIDmode;
2104 note_stores (PATTERN (insn), move2add_note_store, insn);
2106 /* If INSN is a conditional branch, we try to extract an
2107 implicit set out of it. */
2108 if (any_condjump_p (insn))
2110 rtx cnd = fis_get_condition (insn);
2112 if (cnd != NULL_RTX
2113 && GET_CODE (cnd) == NE
2114 && REG_P (XEXP (cnd, 0))
2115 && !reg_set_p (XEXP (cnd, 0), insn)
2116 /* The following two checks, which are also in
2117 move2add_note_store, are intended to reduce the
2118 number of calls to gen_rtx_SET to avoid memory
2119 allocation if possible. */
2120 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
2121 && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1
2122 && CONST_INT_P (XEXP (cnd, 1)))
2124 rtx implicit_set =
2125 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
2126 move2add_note_store (SET_DEST (implicit_set), implicit_set, insn);
2130 /* If this is a CALL_INSN, all call used registers are stored with
2131 unknown values. */
2132 if (CALL_P (insn))
2134 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
2136 if (call_used_regs[i])
2137 /* Reset the information about this register. */
2138 reg_mode[i] = VOIDmode;
2142 return changed;
2145 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2146 contains SET.
2147 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2148 Called from reload_cse_move2add via note_stores. */
2150 static void
2151 move2add_note_store (rtx dst, const_rtx set, void *data)
2153 rtx insn = (rtx) data;
2154 unsigned int regno = 0;
2155 enum machine_mode mode = GET_MODE (dst);
2157 /* Some targets do argument pushes without adding REG_INC notes. */
2159 if (MEM_P (dst))
2161 dst = XEXP (dst, 0);
2162 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
2163 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
2164 reg_mode[REGNO (XEXP (dst, 0))] = VOIDmode;
2165 return;
2168 if (GET_CODE (dst) == SUBREG)
2169 regno = subreg_regno (dst);
2170 else if (REG_P (dst))
2171 regno = REGNO (dst);
2172 else
2173 return;
2175 if (SCALAR_INT_MODE_P (mode)
2176 && GET_CODE (set) == SET)
2178 rtx note, sym = NULL_RTX;
2179 rtx off;
2181 note = find_reg_equal_equiv_note (insn);
2182 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
2184 sym = XEXP (note, 0);
2185 off = const0_rtx;
2187 else if (note && GET_CODE (XEXP (note, 0)) == CONST
2188 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
2189 && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
2190 && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
2192 sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
2193 off = XEXP (XEXP (XEXP (note, 0), 0), 1);
2196 if (sym != NULL_RTX)
2198 move2add_record_sym_value (dst, sym, off);
2199 return;
2203 if (SCALAR_INT_MODE_P (mode)
2204 && GET_CODE (set) == SET
2205 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
2206 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
2208 rtx src = SET_SRC (set);
2209 rtx base_reg;
2210 HOST_WIDE_INT offset;
2211 int base_regno;
2213 switch (GET_CODE (src))
2215 case PLUS:
2216 if (REG_P (XEXP (src, 0)))
2218 base_reg = XEXP (src, 0);
2220 if (CONST_INT_P (XEXP (src, 1)))
2221 offset = INTVAL (XEXP (src, 1));
2222 else if (REG_P (XEXP (src, 1))
2223 && move2add_valid_value_p (REGNO (XEXP (src, 1)), mode))
2225 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0
2226 && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX)
2227 offset = reg_offset[REGNO (XEXP (src, 1))];
2228 /* Maybe the first register is known to be a
2229 constant. */
2230 else if (move2add_valid_value_p (REGNO (base_reg), mode)
2231 && reg_base_reg[REGNO (base_reg)] < 0
2232 && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX)
2234 offset = reg_offset[REGNO (base_reg)];
2235 base_reg = XEXP (src, 1);
2237 else
2238 goto invalidate;
2240 else
2241 goto invalidate;
2243 break;
2246 goto invalidate;
2248 case REG:
2249 base_reg = src;
2250 offset = 0;
2251 break;
2253 case CONST_INT:
2254 /* Start tracking the register as a constant. */
2255 reg_base_reg[regno] = -1;
2256 reg_symbol_ref[regno] = NULL_RTX;
2257 reg_offset[regno] = INTVAL (SET_SRC (set));
2258 /* We assign the same luid to all registers set to constants. */
2259 reg_set_luid[regno] = move2add_last_label_luid + 1;
2260 move2add_record_mode (dst);
2261 return;
2263 default:
2264 goto invalidate;
2267 base_regno = REGNO (base_reg);
2268 /* If information about the base register is not valid, set it
2269 up as a new base register, pretending its value is known
2270 starting from the current insn. */
2271 if (!move2add_valid_value_p (base_regno, mode))
2273 reg_base_reg[base_regno] = base_regno;
2274 reg_symbol_ref[base_regno] = NULL_RTX;
2275 reg_offset[base_regno] = 0;
2276 reg_set_luid[base_regno] = move2add_luid;
2277 gcc_assert (GET_MODE (base_reg) == mode);
2278 move2add_record_mode (base_reg);
2281 /* Copy base information from our base register. */
2282 reg_set_luid[regno] = reg_set_luid[base_regno];
2283 reg_base_reg[regno] = reg_base_reg[base_regno];
2284 reg_symbol_ref[regno] = reg_symbol_ref[base_regno];
2286 /* Compute the sum of the offsets or constants. */
2287 reg_offset[regno]
2288 = trunc_int_for_mode (offset + reg_offset[base_regno], mode);
2290 move2add_record_mode (dst);
2292 else
2294 invalidate:
2295 /* Invalidate the contents of the register. */
2296 move2add_record_mode (dst);
2297 reg_mode[regno] = VOIDmode;
2301 static bool
2302 gate_handle_postreload (void)
2304 return (optimize > 0 && reload_completed);
2308 static unsigned int
2309 rest_of_handle_postreload (void)
2311 if (!dbg_cnt (postreload_cse))
2312 return 0;
2314 /* Do a very simple CSE pass over just the hard registers. */
2315 reload_cse_regs (get_insns ());
2316 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2317 Remove any EH edges associated with them. */
2318 if (cfun->can_throw_non_call_exceptions
2319 && purge_all_dead_edges ())
2320 cleanup_cfg (0);
2322 return 0;
2325 struct rtl_opt_pass pass_postreload_cse =
2328 RTL_PASS,
2329 "postreload", /* name */
2330 OPTGROUP_NONE, /* optinfo_flags */
2331 gate_handle_postreload, /* gate */
2332 rest_of_handle_postreload, /* execute */
2333 NULL, /* sub */
2334 NULL, /* next */
2335 0, /* static_pass_number */
2336 TV_RELOAD_CSE_REGS, /* tv_id */
2337 0, /* properties_required */
2338 0, /* properties_provided */
2339 0, /* properties_destroyed */
2340 0, /* todo_flags_start */
2341 TODO_df_finish | TODO_verify_rtl_sharing |
2342 0 /* todo_flags_finish */