1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 ;; Boston, MA 02110-1301, USA.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_EH_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
53 (UNSPEC_ADDRESS_FIRST 100)
57 ;; For MIPS Paired-Singled Floating Point Instructions.
59 (UNSPEC_MOVE_TF_PS 200)
62 ;; MIPS64/MIPS32R2 alnv.ps
65 ;; MIPS-3D instructions
69 (UNSPEC_CVT_PW_PS 205)
70 (UNSPEC_CVT_PS_PW 206)
78 (UNSPEC_SINGLE_CC 213)
81 ;; MIPS DSP ASE Revision 0.98 3/24/2005
89 (UNSPEC_RADDU_W_QB 307)
91 (UNSPEC_PRECRQ_QB_PH 309)
92 (UNSPEC_PRECRQ_PH_W 310)
93 (UNSPEC_PRECRQ_RS_PH_W 311)
94 (UNSPEC_PRECRQU_S_QB_PH 312)
95 (UNSPEC_PRECEQ_W_PHL 313)
96 (UNSPEC_PRECEQ_W_PHR 314)
97 (UNSPEC_PRECEQU_PH_QBL 315)
98 (UNSPEC_PRECEQU_PH_QBR 316)
99 (UNSPEC_PRECEQU_PH_QBLA 317)
100 (UNSPEC_PRECEQU_PH_QBRA 318)
101 (UNSPEC_PRECEU_PH_QBL 319)
102 (UNSPEC_PRECEU_PH_QBR 320)
103 (UNSPEC_PRECEU_PH_QBLA 321)
104 (UNSPEC_PRECEU_PH_QBRA 322)
110 (UNSPEC_MULEU_S_PH_QBL 328)
111 (UNSPEC_MULEU_S_PH_QBR 329)
112 (UNSPEC_MULQ_RS_PH 330)
113 (UNSPEC_MULEQ_S_W_PHL 331)
114 (UNSPEC_MULEQ_S_W_PHR 332)
115 (UNSPEC_DPAU_H_QBL 333)
116 (UNSPEC_DPAU_H_QBR 334)
117 (UNSPEC_DPSU_H_QBL 335)
118 (UNSPEC_DPSU_H_QBR 336)
119 (UNSPEC_DPAQ_S_W_PH 337)
120 (UNSPEC_DPSQ_S_W_PH 338)
121 (UNSPEC_MULSAQ_S_W_PH 339)
122 (UNSPEC_DPAQ_SA_L_W 340)
123 (UNSPEC_DPSQ_SA_L_W 341)
124 (UNSPEC_MAQ_S_W_PHL 342)
125 (UNSPEC_MAQ_S_W_PHR 343)
126 (UNSPEC_MAQ_SA_W_PHL 344)
127 (UNSPEC_MAQ_SA_W_PHR 345)
135 (UNSPEC_CMPGU_EQ_QB 353)
136 (UNSPEC_CMPGU_LT_QB 354)
137 (UNSPEC_CMPGU_LE_QB 355)
139 (UNSPEC_PACKRL_PH 357)
141 (UNSPEC_EXTR_R_W 359)
142 (UNSPEC_EXTR_RS_W 360)
143 (UNSPEC_EXTR_S_H 361)
151 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
152 (UNSPEC_ABSQ_S_QB 400)
154 (UNSPEC_ADDU_S_PH 402)
155 (UNSPEC_ADDUH_QB 403)
156 (UNSPEC_ADDUH_R_QB 404)
159 (UNSPEC_CMPGDU_EQ_QB 407)
160 (UNSPEC_CMPGDU_LT_QB 408)
161 (UNSPEC_CMPGDU_LE_QB 409)
162 (UNSPEC_DPA_W_PH 410)
163 (UNSPEC_DPS_W_PH 411)
169 (UNSPEC_MUL_S_PH 417)
170 (UNSPEC_MULQ_RS_W 418)
171 (UNSPEC_MULQ_S_PH 419)
172 (UNSPEC_MULQ_S_W 420)
173 (UNSPEC_MULSA_W_PH 421)
176 (UNSPEC_PRECR_QB_PH 424)
177 (UNSPEC_PRECR_SRA_PH_W 425)
178 (UNSPEC_PRECR_SRA_R_PH_W 426)
181 (UNSPEC_SHRA_R_QB 429)
184 (UNSPEC_SUBU_S_PH 432)
185 (UNSPEC_SUBUH_QB 433)
186 (UNSPEC_SUBUH_R_QB 434)
187 (UNSPEC_ADDQH_PH 435)
188 (UNSPEC_ADDQH_R_PH 436)
190 (UNSPEC_ADDQH_R_W 438)
191 (UNSPEC_SUBQH_PH 439)
192 (UNSPEC_SUBQH_R_PH 440)
194 (UNSPEC_SUBQH_R_W 442)
195 (UNSPEC_DPAX_W_PH 443)
196 (UNSPEC_DPSX_W_PH 444)
197 (UNSPEC_DPAQX_S_W_PH 445)
198 (UNSPEC_DPAQX_SA_W_PH 446)
199 (UNSPEC_DPSQX_S_W_PH 447)
200 (UNSPEC_DPSQX_SA_W_PH 448)
204 (include "predicates.md")
205 (include "constraints.md")
207 ;; ....................
211 ;; ....................
213 (define_attr "got" "unset,xgot_high,load"
214 (const_string "unset"))
216 ;; For jal instructions, this attribute is DIRECT when the target address
217 ;; is symbolic and INDIRECT when it is a register.
218 (define_attr "jal" "unset,direct,indirect"
219 (const_string "unset"))
221 ;; This attribute is YES if the instruction is a jal macro (not a
222 ;; real jal instruction).
224 ;; jal is always a macro for o32 and o64 abicalls because it includes an
225 ;; instruction to restore $gp. Direct jals are also macros for -mshared
226 ;; abicalls because they first load the target address into $25.
227 (define_attr "jal_macro" "no,yes"
228 (cond [(eq_attr "jal" "direct")
229 (symbol_ref "TARGET_ABICALLS
230 && (TARGET_OLDABI || !TARGET_ABSOLUTE_ABICALLS)")
231 (eq_attr "jal" "indirect")
232 (symbol_ref "TARGET_ABICALLS && TARGET_OLDABI")]
233 (const_string "no")))
235 ;; Classification of each insn.
236 ;; branch conditional branch
237 ;; jump unconditional jump
238 ;; call unconditional call
239 ;; load load instruction(s)
240 ;; fpload floating point load
241 ;; fpidxload floating point indexed load
242 ;; store store instruction(s)
243 ;; fpstore floating point store
244 ;; fpidxstore floating point indexed store
245 ;; prefetch memory prefetch (register + offset)
246 ;; prefetchx memory indexed prefetch (register + register)
247 ;; condmove conditional moves
248 ;; mfc transfer from coprocessor
249 ;; mtc transfer to coprocessor
250 ;; mthilo transfer to hi/lo registers
251 ;; mfhilo transfer from hi/lo registers
252 ;; const load constant
253 ;; arith integer arithmetic and logical instructions
254 ;; shift integer shift instructions
255 ;; slt set less than instructions
256 ;; clz the clz and clo instructions
257 ;; trap trap if instructions
258 ;; imul integer multiply 2 operands
259 ;; imul3 integer multiply 3 operands
260 ;; imadd integer multiply-add
261 ;; idiv integer divide
262 ;; fmove floating point register move
263 ;; fadd floating point add/subtract
264 ;; fmul floating point multiply
265 ;; fmadd floating point multiply-add
266 ;; fdiv floating point divide
267 ;; frdiv floating point reciprocal divide
268 ;; frdiv1 floating point reciprocal divide step 1
269 ;; frdiv2 floating point reciprocal divide step 2
270 ;; fabs floating point absolute value
271 ;; fneg floating point negation
272 ;; fcmp floating point compare
273 ;; fcvt floating point convert
274 ;; fsqrt floating point square root
275 ;; frsqrt floating point reciprocal square root
276 ;; frsqrt1 floating point reciprocal square root step1
277 ;; frsqrt2 floating point reciprocal square root step2
278 ;; multi multiword sequence (or user asm statements)
281 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
282 (cond [(eq_attr "jal" "!unset") (const_string "call")
283 (eq_attr "got" "load") (const_string "load")]
284 (const_string "unknown")))
286 ;; Main data type used by the insn
287 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
288 (const_string "unknown"))
290 ;; Mode for conversion types (fcvt)
291 ;; I2S integer to float single (SI/DI to SF)
292 ;; I2D integer to float double (SI/DI to DF)
293 ;; S2I float to integer (SF to SI/DI)
294 ;; D2I float to integer (DF to SI/DI)
295 ;; D2S double to float single
296 ;; S2D float single to double
298 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
299 (const_string "unknown"))
301 ;; Is this an extended instruction in mips16 mode?
302 (define_attr "extended_mips16" "no,yes"
305 ;; Length of instruction in bytes.
306 (define_attr "length" ""
307 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
308 ;; If a branch is outside this range, we have a choice of two
309 ;; sequences. For PIC, an out-of-range branch like:
314 ;; becomes the equivalent of:
323 ;; where the load address can be up to three instructions long
326 ;; The non-PIC case is similar except that we use a direct
327 ;; jump instead of an la/jr pair. Since the target of this
328 ;; jump is an absolute 28-bit bit address (the other bits
329 ;; coming from the address of the delay slot) this form cannot
330 ;; cross a 256MB boundary. We could provide the option of
331 ;; using la/jr in this case too, but we do not do so at
334 ;; Note that this value does not account for the delay slot
335 ;; instruction, whose length is added separately. If the RTL
336 ;; pattern has no explicit delay slot, mips_adjust_insn_length
337 ;; will add the length of the implicit nop. The values for
338 ;; forward and backward branches will be different as well.
339 (eq_attr "type" "branch")
340 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
341 (le (minus (pc) (match_dup 1)) (const_int 131068)))
343 (ne (symbol_ref "flag_pic") (const_int 0))
347 (eq_attr "got" "load")
349 (eq_attr "got" "xgot_high")
352 (eq_attr "type" "const")
353 (symbol_ref "mips_const_insns (operands[1]) * 4")
354 (eq_attr "type" "load,fpload")
355 (symbol_ref "mips_fetch_insns (operands[1]) * 4")
356 (eq_attr "type" "store,fpstore")
357 (symbol_ref "mips_fetch_insns (operands[0]) * 4")
359 ;; In the worst case, a call macro will take 8 instructions:
361 ;; lui $25,%call_hi(FOO)
363 ;; lw $25,%call_lo(FOO)($25)
369 (eq_attr "jal_macro" "yes")
372 (and (eq_attr "extended_mips16" "yes")
373 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
376 ;; Various VR4120 errata require a nop to be inserted after a macc
377 ;; instruction. The assembler does this for us, so account for
378 ;; the worst-case length here.
379 (and (eq_attr "type" "imadd")
380 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
383 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
384 ;; the result of the second one is missed. The assembler should work
385 ;; around this by inserting a nop after the first dmult.
386 (and (eq_attr "type" "imul,imul3")
387 (and (eq_attr "mode" "DI")
388 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
391 (eq_attr "type" "idiv")
392 (symbol_ref "mips_idiv_insns () * 4")
395 ;; Attribute describing the processor. This attribute must match exactly
396 ;; with the processor_type enumeration in mips.h.
398 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
399 (const (symbol_ref "mips_tune")))
401 ;; The type of hardware hazard associated with this instruction.
402 ;; DELAY means that the next instruction cannot read the result
403 ;; of this one. HILO means that the next two instructions cannot
404 ;; write to HI or LO.
405 (define_attr "hazard" "none,delay,hilo"
406 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
407 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
408 (const_string "delay")
410 (and (eq_attr "type" "mfc,mtc")
411 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
412 (const_string "delay")
414 (and (eq_attr "type" "fcmp")
415 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
416 (const_string "delay")
418 ;; The r4000 multiplication patterns include an mflo instruction.
419 (and (eq_attr "type" "imul")
420 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
421 (const_string "hilo")
423 (and (eq_attr "type" "mfhilo")
424 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
425 (const_string "hilo")]
426 (const_string "none")))
428 ;; Is it a single instruction?
429 (define_attr "single_insn" "no,yes"
430 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
432 ;; Can the instruction be put into a delay slot?
433 (define_attr "can_delay" "no,yes"
434 (if_then_else (and (eq_attr "type" "!branch,call,jump")
435 (and (eq_attr "hazard" "none")
436 (eq_attr "single_insn" "yes")))
438 (const_string "no")))
440 ;; Attribute defining whether or not we can use the branch-likely instructions
441 (define_attr "branch_likely" "no,yes"
443 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
445 (const_string "no"))))
447 ;; True if an instruction might assign to hi or lo when reloaded.
448 ;; This is used by the TUNE_MACC_CHAINS code.
449 (define_attr "may_clobber_hilo" "no,yes"
450 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
452 (const_string "no")))
454 ;; Describe a user's asm statement.
455 (define_asm_attributes
456 [(set_attr "type" "multi")
457 (set_attr "can_delay" "no")])
459 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
460 ;; from the same template.
461 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
463 ;; This mode macro allows :P to be used for patterns that operate on
464 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
465 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
467 ;; This mode macro allows :MOVECC to be used anywhere that a
468 ;; conditional-move-type condition is needed.
469 (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
471 ;; This mode macro allows the QI and HI extension patterns to be defined from
472 ;; the same template.
473 (define_mode_macro SHORT [QI HI])
475 ;; This mode macro allows :ANYF to be used wherever a scalar or vector
476 ;; floating-point mode is allowed.
477 (define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
478 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
479 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
481 ;; Like ANYF, but only applies to scalar modes.
482 (define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
483 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
485 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
486 ;; 32-bit version and "dsubu" in the 64-bit version.
487 (define_mode_attr d [(SI "") (DI "d")])
489 ;; This attribute gives the length suffix for a sign- or zero-extension
491 (define_mode_attr size [(QI "b") (HI "h")])
493 ;; This attributes gives the mode mask of a SHORT.
494 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
496 ;; Mode attributes for GPR loads and stores.
497 (define_mode_attr load [(SI "lw") (DI "ld")])
498 (define_mode_attr store [(SI "sw") (DI "sd")])
500 ;; Similarly for MIPS IV indexed FPR loads and stores.
501 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
502 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
504 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
505 ;; are different. Some forms of unextended addiu have an 8-bit immediate
506 ;; field but the equivalent daddiu has only a 5-bit field.
507 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
509 ;; This attribute gives the best constraint to use for registers of
511 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
513 ;; This attribute gives the format suffix for floating-point operations.
514 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
516 ;; This attribute gives the upper-case mode name for one unit of a
517 ;; floating-point mode.
518 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
520 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
522 ;; In certain cases, div.s and div.ps may have a rounding error
523 ;; and/or wrong inexact flag.
525 ;; Therefore, we only allow div.s if not working around SB-1 rev2
526 ;; errata or if a slight loss of precision is OK.
527 (define_mode_attr divide_condition
528 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
529 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
531 ; This attribute gives the condition for which sqrt instructions exist.
532 (define_mode_attr sqrt_condition
533 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
535 ; This attribute gives the condition for which recip and rsqrt instructions
537 (define_mode_attr recip_condition
538 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
540 ;; This code macro allows all branch instructions to be generated from
541 ;; a single define_expand template.
542 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
543 eq ne gt ge lt le gtu geu ltu leu])
545 ;; This code macro allows signed and unsigned widening multiplications
546 ;; to use the same template.
547 (define_code_macro any_extend [sign_extend zero_extend])
549 ;; This code macro allows the three shift instructions to be generated
550 ;; from the same template.
551 (define_code_macro any_shift [ashift ashiftrt lshiftrt])
553 ;; This code macro allows all native floating-point comparisons to be
554 ;; generated from the same template.
555 (define_code_macro fcond [unordered uneq unlt unle eq lt le])
557 ;; This code macro is used for comparisons that can be implemented
558 ;; by swapping the operands.
559 (define_code_macro swapped_fcond [ge gt unge ungt])
561 ;; <u> expands to an empty string when doing a signed operation and
562 ;; "u" when doing an unsigned operation.
563 (define_code_attr u [(sign_extend "") (zero_extend "u")])
565 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
566 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
568 ;; <optab> expands to the name of the optab for a particular code.
569 (define_code_attr optab [(ashift "ashl")
573 ;; <insn> expands to the name of the insn that implements a particular code.
574 (define_code_attr insn [(ashift "sll")
578 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
579 (define_code_attr fcond [(unordered "un")
587 ;; Similar, but for swapped conditions.
588 (define_code_attr swapped_fcond [(ge "le")
593 ;; .........................
595 ;; Branch, call and jump delay slots
597 ;; .........................
599 (define_delay (and (eq_attr "type" "branch")
600 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
601 [(eq_attr "can_delay" "yes")
603 (and (eq_attr "branch_likely" "yes")
604 (eq_attr "can_delay" "yes"))])
606 (define_delay (eq_attr "type" "jump")
607 [(eq_attr "can_delay" "yes")
611 (define_delay (and (eq_attr "type" "call")
612 (eq_attr "jal_macro" "no"))
613 [(eq_attr "can_delay" "yes")
617 ;; Pipeline descriptions.
619 ;; generic.md provides a fallback for processors without a specific
620 ;; pipeline description. It is derived from the old define_function_unit
621 ;; version and uses the "alu" and "imuldiv" units declared below.
623 ;; Some of the processor-specific files are also derived from old
624 ;; define_function_unit descriptions and simply override the parts of
625 ;; generic.md that don't apply. The other processor-specific files
626 ;; are self-contained.
627 (define_automaton "alu,imuldiv")
629 (define_cpu_unit "alu" "alu")
630 (define_cpu_unit "imuldiv" "imuldiv")
649 (include "generic.md")
652 ;; ....................
656 ;; ....................
660 [(trap_if (const_int 1) (const_int 0))]
663 if (ISA_HAS_COND_TRAP)
665 else if (TARGET_MIPS16)
670 [(set_attr "type" "trap")])
672 (define_expand "conditional_trap"
673 [(trap_if (match_operator 0 "comparison_operator"
674 [(match_dup 2) (match_dup 3)])
675 (match_operand 1 "const_int_operand"))]
678 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
679 && operands[1] == const0_rtx)
681 mips_gen_conditional_trap (operands);
688 (define_insn "*conditional_trap<mode>"
689 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
690 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
691 (match_operand:GPR 2 "arith_operand" "dI")])
695 [(set_attr "type" "trap")])
698 ;; ....................
702 ;; ....................
705 (define_insn "add<mode>3"
706 [(set (match_operand:ANYF 0 "register_operand" "=f")
707 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
708 (match_operand:ANYF 2 "register_operand" "f")))]
710 "add.<fmt>\t%0,%1,%2"
711 [(set_attr "type" "fadd")
712 (set_attr "mode" "<UNITMODE>")])
714 (define_expand "add<mode>3"
715 [(set (match_operand:GPR 0 "register_operand")
716 (plus:GPR (match_operand:GPR 1 "register_operand")
717 (match_operand:GPR 2 "arith_operand")))]
720 (define_insn "*add<mode>3"
721 [(set (match_operand:GPR 0 "register_operand" "=d,d")
722 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
723 (match_operand:GPR 2 "arith_operand" "d,Q")))]
728 [(set_attr "type" "arith")
729 (set_attr "mode" "<MODE>")])
731 ;; We need to recognize MIPS16 stack pointer additions explicitly, since
732 ;; we don't have a constraint for $sp. These insns will be generated by
733 ;; the save_restore_insns functions.
735 (define_insn "*add<mode>3_sp1"
737 (plus:GPR (reg:GPR 29)
738 (match_operand:GPR 0 "const_arith_operand" "")))]
741 [(set_attr "type" "arith")
742 (set_attr "mode" "<MODE>")
743 (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")
747 (define_insn "*add<mode>3_sp2"
748 [(set (match_operand:GPR 0 "register_operand" "=d")
749 (plus:GPR (reg:GPR 29)
750 (match_operand:GPR 1 "const_arith_operand" "")))]
753 [(set_attr "type" "arith")
754 (set_attr "mode" "<MODE>")
755 (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4")
759 (define_insn "*add<mode>3_mips16"
760 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
761 (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")
762 (match_operand:GPR 2 "arith_operand" "Q,O,d")))]
768 [(set_attr "type" "arith")
769 (set_attr "mode" "<MODE>")
770 (set_attr_alternative "length"
771 [(if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
774 (if_then_else (match_operand 2 "m16_simm4_1")
780 ;; On the mips16, we can sometimes split an add of a constant which is
781 ;; a 4 byte instruction into two adds which are both 2 byte
782 ;; instructions. There are two cases: one where we are adding a
783 ;; constant plus a register to another register, and one where we are
784 ;; simply adding a constant to a register.
787 [(set (match_operand:SI 0 "register_operand")
788 (plus:SI (match_dup 0)
789 (match_operand:SI 1 "const_int_operand")))]
790 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
791 && REG_P (operands[0])
792 && M16_REG_P (REGNO (operands[0]))
793 && GET_CODE (operands[1]) == CONST_INT
794 && ((INTVAL (operands[1]) > 0x7f
795 && INTVAL (operands[1]) <= 0x7f + 0x7f)
796 || (INTVAL (operands[1]) < - 0x80
797 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
798 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
799 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
801 HOST_WIDE_INT val = INTVAL (operands[1]);
805 operands[1] = GEN_INT (0x7f);
806 operands[2] = GEN_INT (val - 0x7f);
810 operands[1] = GEN_INT (- 0x80);
811 operands[2] = GEN_INT (val + 0x80);
816 [(set (match_operand:SI 0 "register_operand")
817 (plus:SI (match_operand:SI 1 "register_operand")
818 (match_operand:SI 2 "const_int_operand")))]
819 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
820 && REG_P (operands[0])
821 && M16_REG_P (REGNO (operands[0]))
822 && REG_P (operands[1])
823 && M16_REG_P (REGNO (operands[1]))
824 && REGNO (operands[0]) != REGNO (operands[1])
825 && GET_CODE (operands[2]) == CONST_INT
826 && ((INTVAL (operands[2]) > 0x7
827 && INTVAL (operands[2]) <= 0x7 + 0x7f)
828 || (INTVAL (operands[2]) < - 0x8
829 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
830 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
831 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
833 HOST_WIDE_INT val = INTVAL (operands[2]);
837 operands[2] = GEN_INT (0x7);
838 operands[3] = GEN_INT (val - 0x7);
842 operands[2] = GEN_INT (- 0x8);
843 operands[3] = GEN_INT (val + 0x8);
848 [(set (match_operand:DI 0 "register_operand")
849 (plus:DI (match_dup 0)
850 (match_operand:DI 1 "const_int_operand")))]
851 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
852 && REG_P (operands[0])
853 && M16_REG_P (REGNO (operands[0]))
854 && GET_CODE (operands[1]) == CONST_INT
855 && ((INTVAL (operands[1]) > 0xf
856 && INTVAL (operands[1]) <= 0xf + 0xf)
857 || (INTVAL (operands[1]) < - 0x10
858 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
859 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
860 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
862 HOST_WIDE_INT val = INTVAL (operands[1]);
866 operands[1] = GEN_INT (0xf);
867 operands[2] = GEN_INT (val - 0xf);
871 operands[1] = GEN_INT (- 0x10);
872 operands[2] = GEN_INT (val + 0x10);
877 [(set (match_operand:DI 0 "register_operand")
878 (plus:DI (match_operand:DI 1 "register_operand")
879 (match_operand:DI 2 "const_int_operand")))]
880 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
881 && REG_P (operands[0])
882 && M16_REG_P (REGNO (operands[0]))
883 && REG_P (operands[1])
884 && M16_REG_P (REGNO (operands[1]))
885 && REGNO (operands[0]) != REGNO (operands[1])
886 && GET_CODE (operands[2]) == CONST_INT
887 && ((INTVAL (operands[2]) > 0x7
888 && INTVAL (operands[2]) <= 0x7 + 0xf)
889 || (INTVAL (operands[2]) < - 0x8
890 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
891 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
892 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
894 HOST_WIDE_INT val = INTVAL (operands[2]);
898 operands[2] = GEN_INT (0x7);
899 operands[3] = GEN_INT (val - 0x7);
903 operands[2] = GEN_INT (- 0x8);
904 operands[3] = GEN_INT (val + 0x8);
908 (define_insn "*addsi3_extended"
909 [(set (match_operand:DI 0 "register_operand" "=d,d")
911 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
912 (match_operand:SI 2 "arith_operand" "d,Q"))))]
913 "TARGET_64BIT && !TARGET_MIPS16"
917 [(set_attr "type" "arith")
918 (set_attr "mode" "SI")])
920 ;; Split this insn so that the addiu splitters can have a crack at it.
921 ;; Use a conservative length estimate until the split.
922 (define_insn_and_split "*addsi3_extended_mips16"
923 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
925 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
926 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
927 "TARGET_64BIT && TARGET_MIPS16"
929 "&& reload_completed"
930 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
931 { operands[3] = gen_lowpart (SImode, operands[0]); }
932 [(set_attr "type" "arith")
933 (set_attr "mode" "SI")
934 (set_attr "extended_mips16" "yes")])
937 ;; ....................
941 ;; ....................
944 (define_insn "sub<mode>3"
945 [(set (match_operand:ANYF 0 "register_operand" "=f")
946 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
947 (match_operand:ANYF 2 "register_operand" "f")))]
949 "sub.<fmt>\t%0,%1,%2"
950 [(set_attr "type" "fadd")
951 (set_attr "mode" "<UNITMODE>")])
953 (define_insn "sub<mode>3"
954 [(set (match_operand:GPR 0 "register_operand" "=d")
955 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
956 (match_operand:GPR 2 "register_operand" "d")))]
959 [(set_attr "type" "arith")
960 (set_attr "mode" "<MODE>")])
962 (define_insn "*subsi3_extended"
963 [(set (match_operand:DI 0 "register_operand" "=d")
965 (minus:SI (match_operand:SI 1 "register_operand" "d")
966 (match_operand:SI 2 "register_operand" "d"))))]
969 [(set_attr "type" "arith")
970 (set_attr "mode" "DI")])
973 ;; ....................
977 ;; ....................
980 (define_expand "mul<mode>3"
981 [(set (match_operand:SCALARF 0 "register_operand")
982 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
983 (match_operand:SCALARF 2 "register_operand")))]
987 (define_insn "*mul<mode>3"
988 [(set (match_operand:SCALARF 0 "register_operand" "=f")
989 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
990 (match_operand:SCALARF 2 "register_operand" "f")))]
991 "!TARGET_4300_MUL_FIX"
992 "mul.<fmt>\t%0,%1,%2"
993 [(set_attr "type" "fmul")
994 (set_attr "mode" "<MODE>")])
996 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
997 ;; operands may corrupt immediately following multiplies. This is a
998 ;; simple fix to insert NOPs.
1000 (define_insn "*mul<mode>3_r4300"
1001 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1002 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1003 (match_operand:SCALARF 2 "register_operand" "f")))]
1004 "TARGET_4300_MUL_FIX"
1005 "mul.<fmt>\t%0,%1,%2\;nop"
1006 [(set_attr "type" "fmul")
1007 (set_attr "mode" "<MODE>")
1008 (set_attr "length" "8")])
1010 (define_insn "mulv2sf3"
1011 [(set (match_operand:V2SF 0 "register_operand" "=f")
1012 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1013 (match_operand:V2SF 2 "register_operand" "f")))]
1014 "TARGET_PAIRED_SINGLE_FLOAT"
1016 [(set_attr "type" "fmul")
1017 (set_attr "mode" "SF")])
1019 ;; The original R4000 has a cpu bug. If a double-word or a variable
1020 ;; shift executes while an integer multiplication is in progress, the
1021 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1022 ;; with the mult on the R4000.
1024 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1025 ;; (also valid for MIPS R4000MC processors):
1027 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1028 ;; this errata description.
1029 ;; The following code sequence causes the R4000 to incorrectly
1030 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1031 ;; instruction. If the dsra32 instruction is executed during an
1032 ;; integer multiply, the dsra32 will only shift by the amount in
1033 ;; specified in the instruction rather than the amount plus 32
1035 ;; instruction 1: mult rs,rt integer multiply
1036 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1037 ;; right arithmetic + 32
1038 ;; Workaround: A dsra32 instruction placed after an integer
1039 ;; multiply should not be one of the 11 instructions after the
1040 ;; multiply instruction."
1044 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1045 ;; the following description.
1046 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1047 ;; 64-bit versions) may produce incorrect results under the
1048 ;; following conditions:
1049 ;; 1) An integer multiply is currently executing
1050 ;; 2) These types of shift instructions are executed immediately
1051 ;; following an integer divide instruction.
1053 ;; 1) Make sure no integer multiply is running wihen these
1054 ;; instruction are executed. If this cannot be predicted at
1055 ;; compile time, then insert a "mfhi" to R0 instruction
1056 ;; immediately after the integer multiply instruction. This
1057 ;; will cause the integer multiply to complete before the shift
1059 ;; 2) Separate integer divide and these two classes of shift
1060 ;; instructions by another instruction or a noop."
1062 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1065 (define_expand "mulsi3"
1066 [(set (match_operand:SI 0 "register_operand")
1067 (mult:SI (match_operand:SI 1 "register_operand")
1068 (match_operand:SI 2 "register_operand")))]
1072 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1073 else if (TARGET_FIX_R4000)
1074 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1076 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1080 (define_expand "muldi3"
1081 [(set (match_operand:DI 0 "register_operand")
1082 (mult:DI (match_operand:DI 1 "register_operand")
1083 (match_operand:DI 2 "register_operand")))]
1086 if (TARGET_FIX_R4000)
1087 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1089 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1093 (define_insn "mulsi3_mult3"
1094 [(set (match_operand:SI 0 "register_operand" "=d,l")
1095 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1096 (match_operand:SI 2 "register_operand" "d,d")))
1097 (clobber (match_scratch:SI 3 "=h,h"))
1098 (clobber (match_scratch:SI 4 "=l,X"))]
1101 if (which_alternative == 1)
1102 return "mult\t%1,%2";
1103 if (TARGET_MIPS3900)
1104 return "mult\t%0,%1,%2";
1105 return "mul\t%0,%1,%2";
1107 [(set_attr "type" "imul3,imul")
1108 (set_attr "mode" "SI")])
1110 ;; If a register gets allocated to LO, and we spill to memory, the reload
1111 ;; will include a move from LO to a GPR. Merge it into the multiplication
1112 ;; if it can set the GPR directly.
1115 ;; Operand 1: GPR (1st multiplication operand)
1116 ;; Operand 2: GPR (2nd multiplication operand)
1118 ;; Operand 4: GPR (destination)
1121 [(set (match_operand:SI 0 "register_operand")
1122 (mult:SI (match_operand:SI 1 "register_operand")
1123 (match_operand:SI 2 "register_operand")))
1124 (clobber (match_operand:SI 3 "register_operand"))
1125 (clobber (scratch:SI))])
1126 (set (match_operand:SI 4 "register_operand")
1127 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1128 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1131 (mult:SI (match_dup 1)
1133 (clobber (match_dup 3))
1134 (clobber (match_dup 0))])])
1136 (define_insn "mul<mode>3_internal"
1137 [(set (match_operand:GPR 0 "register_operand" "=l")
1138 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1139 (match_operand:GPR 2 "register_operand" "d")))
1140 (clobber (match_scratch:GPR 3 "=h"))]
1143 [(set_attr "type" "imul")
1144 (set_attr "mode" "<MODE>")])
1146 (define_insn "mul<mode>3_r4000"
1147 [(set (match_operand:GPR 0 "register_operand" "=d")
1148 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1149 (match_operand:GPR 2 "register_operand" "d")))
1150 (clobber (match_scratch:GPR 3 "=h"))
1151 (clobber (match_scratch:GPR 4 "=l"))]
1153 "<d>mult\t%1,%2\;mflo\t%0"
1154 [(set_attr "type" "imul")
1155 (set_attr "mode" "<MODE>")
1156 (set_attr "length" "8")])
1158 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1159 ;; of "mult; mflo". They have the same latency, but the first form gives
1160 ;; us an extra cycle to compute the operands.
1163 ;; Operand 1: GPR (1st multiplication operand)
1164 ;; Operand 2: GPR (2nd multiplication operand)
1166 ;; Operand 4: GPR (destination)
1169 [(set (match_operand:SI 0 "register_operand")
1170 (mult:SI (match_operand:SI 1 "register_operand")
1171 (match_operand:SI 2 "register_operand")))
1172 (clobber (match_operand:SI 3 "register_operand"))])
1173 (set (match_operand:SI 4 "register_operand")
1174 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1175 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1180 (plus:SI (mult:SI (match_dup 1)
1184 (plus:SI (mult:SI (match_dup 1)
1187 (clobber (match_dup 3))])])
1189 ;; Multiply-accumulate patterns
1191 ;; For processors that can copy the output to a general register:
1193 ;; The all-d alternative is needed because the combiner will find this
1194 ;; pattern and then register alloc/reload will move registers around to
1195 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1197 ;; The last alternative should be made slightly less desirable, but adding
1198 ;; "?" to the constraint is too strong, and causes values to be loaded into
1199 ;; LO even when that's more costly. For now, using "*d" mostly does the
1201 (define_insn "*mul_acc_si"
1202 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1203 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1204 (match_operand:SI 2 "register_operand" "d,d,d"))
1205 (match_operand:SI 3 "register_operand" "0,l,*d")))
1206 (clobber (match_scratch:SI 4 "=h,h,h"))
1207 (clobber (match_scratch:SI 5 "=X,3,l"))
1208 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1210 || ISA_HAS_MADD_MSUB)
1213 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1214 if (which_alternative == 2)
1216 if (ISA_HAS_MADD_MSUB && which_alternative != 0)
1218 return madd[which_alternative];
1220 [(set_attr "type" "imadd,imadd,multi")
1221 (set_attr "mode" "SI")
1222 (set_attr "length" "4,4,8")])
1224 ;; Split the above insn if we failed to get LO allocated.
1226 [(set (match_operand:SI 0 "register_operand")
1227 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1228 (match_operand:SI 2 "register_operand"))
1229 (match_operand:SI 3 "register_operand")))
1230 (clobber (match_scratch:SI 4))
1231 (clobber (match_scratch:SI 5))
1232 (clobber (match_scratch:SI 6))]
1233 "reload_completed && !TARGET_DEBUG_D_MODE
1234 && GP_REG_P (true_regnum (operands[0]))
1235 && GP_REG_P (true_regnum (operands[3]))"
1236 [(parallel [(set (match_dup 6)
1237 (mult:SI (match_dup 1) (match_dup 2)))
1238 (clobber (match_dup 4))
1239 (clobber (match_dup 5))])
1240 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1243 ;; Splitter to copy result of MADD to a general register
1245 [(set (match_operand:SI 0 "register_operand")
1246 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1247 (match_operand:SI 2 "register_operand"))
1248 (match_operand:SI 3 "register_operand")))
1249 (clobber (match_scratch:SI 4))
1250 (clobber (match_scratch:SI 5))
1251 (clobber (match_scratch:SI 6))]
1252 "reload_completed && !TARGET_DEBUG_D_MODE
1253 && GP_REG_P (true_regnum (operands[0]))
1254 && true_regnum (operands[3]) == LO_REGNUM"
1255 [(parallel [(set (match_dup 3)
1256 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1258 (clobber (match_dup 4))
1259 (clobber (match_dup 5))
1260 (clobber (match_dup 6))])
1261 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1264 (define_insn "*macc"
1265 [(set (match_operand:SI 0 "register_operand" "=l,d")
1266 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1267 (match_operand:SI 2 "register_operand" "d,d"))
1268 (match_operand:SI 3 "register_operand" "0,l")))
1269 (clobber (match_scratch:SI 4 "=h,h"))
1270 (clobber (match_scratch:SI 5 "=X,3"))]
1273 if (which_alternative == 1)
1274 return "macc\t%0,%1,%2";
1275 else if (TARGET_MIPS5500)
1276 return "madd\t%1,%2";
1278 /* The VR4130 assumes that there is a two-cycle latency between a macc
1279 that "writes" to $0 and an instruction that reads from it. We avoid
1280 this by assigning to $1 instead. */
1281 return "%[macc\t%@,%1,%2%]";
1283 [(set_attr "type" "imadd")
1284 (set_attr "mode" "SI")])
1286 (define_insn "*msac"
1287 [(set (match_operand:SI 0 "register_operand" "=l,d")
1288 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1289 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1290 (match_operand:SI 3 "register_operand" "d,d"))))
1291 (clobber (match_scratch:SI 4 "=h,h"))
1292 (clobber (match_scratch:SI 5 "=X,1"))]
1295 if (which_alternative == 1)
1296 return "msac\t%0,%2,%3";
1297 else if (TARGET_MIPS5500)
1298 return "msub\t%2,%3";
1300 return "msac\t$0,%2,%3";
1302 [(set_attr "type" "imadd")
1303 (set_attr "mode" "SI")])
1305 ;; An msac-like instruction implemented using negation and a macc.
1306 (define_insn_and_split "*msac_using_macc"
1307 [(set (match_operand:SI 0 "register_operand" "=l,d")
1308 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1309 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1310 (match_operand:SI 3 "register_operand" "d,d"))))
1311 (clobber (match_scratch:SI 4 "=h,h"))
1312 (clobber (match_scratch:SI 5 "=X,1"))
1313 (clobber (match_scratch:SI 6 "=d,d"))]
1314 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1316 "&& reload_completed"
1318 (neg:SI (match_dup 3)))
1321 (plus:SI (mult:SI (match_dup 2)
1324 (clobber (match_dup 4))
1325 (clobber (match_dup 5))])]
1327 [(set_attr "type" "imadd")
1328 (set_attr "length" "8")])
1330 ;; Patterns generated by the define_peephole2 below.
1332 (define_insn "*macc2"
1333 [(set (match_operand:SI 0 "register_operand" "=l")
1334 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1335 (match_operand:SI 2 "register_operand" "d"))
1337 (set (match_operand:SI 3 "register_operand" "=d")
1338 (plus:SI (mult:SI (match_dup 1)
1341 (clobber (match_scratch:SI 4 "=h"))]
1342 "ISA_HAS_MACC && reload_completed"
1344 [(set_attr "type" "imadd")
1345 (set_attr "mode" "SI")])
1347 (define_insn "*msac2"
1348 [(set (match_operand:SI 0 "register_operand" "=l")
1349 (minus:SI (match_dup 0)
1350 (mult:SI (match_operand:SI 1 "register_operand" "d")
1351 (match_operand:SI 2 "register_operand" "d"))))
1352 (set (match_operand:SI 3 "register_operand" "=d")
1353 (minus:SI (match_dup 0)
1354 (mult:SI (match_dup 1)
1356 (clobber (match_scratch:SI 4 "=h"))]
1357 "ISA_HAS_MSAC && reload_completed"
1359 [(set_attr "type" "imadd")
1360 (set_attr "mode" "SI")])
1362 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1366 ;; Operand 1: macc/msac
1368 ;; Operand 3: GPR (destination)
1371 [(set (match_operand:SI 0 "register_operand")
1372 (match_operand:SI 1 "macc_msac_operand"))
1373 (clobber (match_operand:SI 2 "register_operand"))
1374 (clobber (scratch:SI))])
1375 (set (match_operand:SI 3 "register_operand")
1376 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1378 [(parallel [(set (match_dup 0)
1382 (clobber (match_dup 2))])]
1385 ;; When we have a three-address multiplication instruction, it should
1386 ;; be faster to do a separate multiply and add, rather than moving
1387 ;; something into LO in order to use a macc instruction.
1389 ;; This peephole needs a scratch register to cater for the case when one
1390 ;; of the multiplication operands is the same as the destination.
1392 ;; Operand 0: GPR (scratch)
1394 ;; Operand 2: GPR (addend)
1395 ;; Operand 3: GPR (destination)
1396 ;; Operand 4: macc/msac
1398 ;; Operand 6: new multiplication
1399 ;; Operand 7: new addition/subtraction
1401 [(match_scratch:SI 0 "d")
1402 (set (match_operand:SI 1 "register_operand")
1403 (match_operand:SI 2 "register_operand"))
1406 [(set (match_operand:SI 3 "register_operand")
1407 (match_operand:SI 4 "macc_msac_operand"))
1408 (clobber (match_operand:SI 5 "register_operand"))
1409 (clobber (match_dup 1))])]
1411 && true_regnum (operands[1]) == LO_REGNUM
1412 && peep2_reg_dead_p (2, operands[1])
1413 && GP_REG_P (true_regnum (operands[3]))"
1414 [(parallel [(set (match_dup 0)
1416 (clobber (match_dup 5))
1417 (clobber (match_dup 1))])
1421 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1422 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1423 operands[2], operands[0]);
1426 ;; Same as above, except LO is the initial target of the macc.
1428 ;; Operand 0: GPR (scratch)
1430 ;; Operand 2: GPR (addend)
1431 ;; Operand 3: macc/msac
1433 ;; Operand 5: GPR (destination)
1434 ;; Operand 6: new multiplication
1435 ;; Operand 7: new addition/subtraction
1437 [(match_scratch:SI 0 "d")
1438 (set (match_operand:SI 1 "register_operand")
1439 (match_operand:SI 2 "register_operand"))
1443 (match_operand:SI 3 "macc_msac_operand"))
1444 (clobber (match_operand:SI 4 "register_operand"))
1445 (clobber (scratch:SI))])
1447 (set (match_operand:SI 5 "register_operand")
1448 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1449 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1450 [(parallel [(set (match_dup 0)
1452 (clobber (match_dup 4))
1453 (clobber (match_dup 1))])
1457 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1458 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1459 operands[2], operands[0]);
1462 (define_insn "*mul_sub_si"
1463 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1464 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1465 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1466 (match_operand:SI 3 "register_operand" "d,d,d"))))
1467 (clobber (match_scratch:SI 4 "=h,h,h"))
1468 (clobber (match_scratch:SI 5 "=X,1,l"))
1469 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1475 [(set_attr "type" "imadd,multi,multi")
1476 (set_attr "mode" "SI")
1477 (set_attr "length" "4,8,8")])
1479 ;; Split the above insn if we failed to get LO allocated.
1481 [(set (match_operand:SI 0 "register_operand")
1482 (minus:SI (match_operand:SI 1 "register_operand")
1483 (mult:SI (match_operand:SI 2 "register_operand")
1484 (match_operand:SI 3 "register_operand"))))
1485 (clobber (match_scratch:SI 4))
1486 (clobber (match_scratch:SI 5))
1487 (clobber (match_scratch:SI 6))]
1488 "reload_completed && !TARGET_DEBUG_D_MODE
1489 && GP_REG_P (true_regnum (operands[0]))
1490 && GP_REG_P (true_regnum (operands[1]))"
1491 [(parallel [(set (match_dup 6)
1492 (mult:SI (match_dup 2) (match_dup 3)))
1493 (clobber (match_dup 4))
1494 (clobber (match_dup 5))])
1495 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1498 ;; Splitter to copy result of MSUB to a general register
1500 [(set (match_operand:SI 0 "register_operand")
1501 (minus:SI (match_operand:SI 1 "register_operand")
1502 (mult:SI (match_operand:SI 2 "register_operand")
1503 (match_operand:SI 3 "register_operand"))))
1504 (clobber (match_scratch:SI 4))
1505 (clobber (match_scratch:SI 5))
1506 (clobber (match_scratch:SI 6))]
1507 "reload_completed && !TARGET_DEBUG_D_MODE
1508 && GP_REG_P (true_regnum (operands[0]))
1509 && true_regnum (operands[1]) == LO_REGNUM"
1510 [(parallel [(set (match_dup 1)
1511 (minus:SI (match_dup 1)
1512 (mult:SI (match_dup 2) (match_dup 3))))
1513 (clobber (match_dup 4))
1514 (clobber (match_dup 5))
1515 (clobber (match_dup 6))])
1516 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1519 (define_insn "*muls"
1520 [(set (match_operand:SI 0 "register_operand" "=l,d")
1521 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1522 (match_operand:SI 2 "register_operand" "d,d"))))
1523 (clobber (match_scratch:SI 3 "=h,h"))
1524 (clobber (match_scratch:SI 4 "=X,l"))]
1529 [(set_attr "type" "imul,imul3")
1530 (set_attr "mode" "SI")])
1532 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1534 (define_expand "<u>mulsidi3"
1536 [(set (match_operand:DI 0 "register_operand")
1537 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1538 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1539 (clobber (scratch:DI))
1540 (clobber (scratch:DI))
1541 (clobber (scratch:DI))])]
1542 "!TARGET_64BIT || !TARGET_FIX_R4000"
1546 if (!TARGET_FIX_R4000)
1547 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1550 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1556 (define_insn "<u>mulsidi3_32bit_internal"
1557 [(set (match_operand:DI 0 "register_operand" "=x")
1558 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1559 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1560 "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
1562 [(set_attr "type" "imul")
1563 (set_attr "mode" "SI")])
1565 (define_insn "<u>mulsidi3_32bit_r4000"
1566 [(set (match_operand:DI 0 "register_operand" "=d")
1567 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1568 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1569 (clobber (match_scratch:DI 3 "=x"))]
1570 "!TARGET_64BIT && TARGET_FIX_R4000"
1571 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1572 [(set_attr "type" "imul")
1573 (set_attr "mode" "SI")
1574 (set_attr "length" "12")])
1576 (define_insn_and_split "*<u>mulsidi3_64bit"
1577 [(set (match_operand:DI 0 "register_operand" "=d")
1578 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1579 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1580 (clobber (match_scratch:DI 3 "=l"))
1581 (clobber (match_scratch:DI 4 "=h"))
1582 (clobber (match_scratch:DI 5 "=d"))]
1583 "TARGET_64BIT && !TARGET_FIX_R4000"
1585 "&& reload_completed"
1589 (mult:SI (match_dup 1)
1593 (mult:DI (any_extend:DI (match_dup 1))
1594 (any_extend:DI (match_dup 2)))
1597 ;; OP5 <- LO, OP0 <- HI
1598 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1599 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1603 (ashift:DI (match_dup 5)
1606 (lshiftrt:DI (match_dup 5)
1609 ;; Shift OP0 into place.
1611 (ashift:DI (match_dup 0)
1614 ;; OR the two halves together
1616 (ior:DI (match_dup 0)
1619 [(set_attr "type" "imul")
1620 (set_attr "mode" "SI")
1621 (set_attr "length" "24")])
1623 (define_insn "*<u>mulsidi3_64bit_parts"
1624 [(set (match_operand:DI 0 "register_operand" "=l")
1626 (mult:SI (match_operand:SI 2 "register_operand" "d")
1627 (match_operand:SI 3 "register_operand" "d"))))
1628 (set (match_operand:DI 1 "register_operand" "=h")
1630 (mult:DI (any_extend:DI (match_dup 2))
1631 (any_extend:DI (match_dup 3)))
1633 "TARGET_64BIT && !TARGET_FIX_R4000"
1635 [(set_attr "type" "imul")
1636 (set_attr "mode" "SI")])
1638 ;; Widening multiply with negation.
1639 (define_insn "*muls<u>_di"
1640 [(set (match_operand:DI 0 "register_operand" "=x")
1643 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1644 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1645 "!TARGET_64BIT && ISA_HAS_MULS"
1647 [(set_attr "type" "imul")
1648 (set_attr "mode" "SI")])
1650 (define_insn "*msac<u>_di"
1651 [(set (match_operand:DI 0 "register_operand" "=x")
1653 (match_operand:DI 3 "register_operand" "0")
1655 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1656 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1657 "!TARGET_64BIT && ISA_HAS_MSAC"
1659 if (TARGET_MIPS5500)
1660 return "msub<u>\t%1,%2";
1662 return "msac<u>\t$0,%1,%2";
1664 [(set_attr "type" "imadd")
1665 (set_attr "mode" "SI")])
1667 ;; _highpart patterns
1669 (define_expand "<su>mulsi3_highpart"
1670 [(set (match_operand:SI 0 "register_operand")
1673 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1674 (any_extend:DI (match_operand:SI 2 "register_operand")))
1676 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1679 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1683 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1688 (define_insn "<su>mulsi3_highpart_internal"
1689 [(set (match_operand:SI 0 "register_operand" "=h")
1692 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1693 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1695 (clobber (match_scratch:SI 3 "=l"))]
1696 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1698 [(set_attr "type" "imul")
1699 (set_attr "mode" "SI")])
1701 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1702 [(set (match_operand:SI 0 "register_operand" "=h,d")
1706 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1707 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1709 (clobber (match_scratch:SI 3 "=l,l"))
1710 (clobber (match_scratch:SI 4 "=X,h"))]
1715 [(set_attr "type" "imul,imul3")
1716 (set_attr "mode" "SI")])
1718 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1719 [(set (match_operand:SI 0 "register_operand" "=h,d")
1724 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1725 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1727 (clobber (match_scratch:SI 3 "=l,l"))
1728 (clobber (match_scratch:SI 4 "=X,h"))]
1732 mulshi<u>\t%0,%1,%2"
1733 [(set_attr "type" "imul,imul3")
1734 (set_attr "mode" "SI")])
1736 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1737 ;; errata MD(0), which says that dmultu does not always produce the
1739 (define_insn "<su>muldi3_highpart"
1740 [(set (match_operand:DI 0 "register_operand" "=h")
1744 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1745 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1747 (clobber (match_scratch:DI 3 "=l"))]
1748 "TARGET_64BIT && !TARGET_FIX_R4000
1749 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1751 [(set_attr "type" "imul")
1752 (set_attr "mode" "DI")])
1754 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1755 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1757 (define_insn "madsi"
1758 [(set (match_operand:SI 0 "register_operand" "+l")
1759 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1760 (match_operand:SI 2 "register_operand" "d"))
1762 (clobber (match_scratch:SI 3 "=h"))]
1765 [(set_attr "type" "imadd")
1766 (set_attr "mode" "SI")])
1768 (define_insn "*<su>mul_acc_di"
1769 [(set (match_operand:DI 0 "register_operand" "=x")
1771 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1772 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1773 (match_operand:DI 3 "register_operand" "0")))]
1774 "(TARGET_MAD || ISA_HAS_MACC)
1778 return "mad<u>\t%1,%2";
1779 else if (TARGET_MIPS5500)
1780 return "madd<u>\t%1,%2";
1782 /* See comment in *macc. */
1783 return "%[macc<u>\t%@,%1,%2%]";
1785 [(set_attr "type" "imadd")
1786 (set_attr "mode" "SI")])
1788 ;; Floating point multiply accumulate instructions.
1790 (define_insn "*madd<mode>"
1791 [(set (match_operand:ANYF 0 "register_operand" "=f")
1792 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1793 (match_operand:ANYF 2 "register_operand" "f"))
1794 (match_operand:ANYF 3 "register_operand" "f")))]
1795 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1796 "madd.<fmt>\t%0,%3,%1,%2"
1797 [(set_attr "type" "fmadd")
1798 (set_attr "mode" "<UNITMODE>")])
1800 (define_insn "*msub<mode>"
1801 [(set (match_operand:ANYF 0 "register_operand" "=f")
1802 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1803 (match_operand:ANYF 2 "register_operand" "f"))
1804 (match_operand:ANYF 3 "register_operand" "f")))]
1805 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1806 "msub.<fmt>\t%0,%3,%1,%2"
1807 [(set_attr "type" "fmadd")
1808 (set_attr "mode" "<UNITMODE>")])
1810 (define_insn "*nmadd<mode>"
1811 [(set (match_operand:ANYF 0 "register_operand" "=f")
1812 (neg:ANYF (plus:ANYF
1813 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1814 (match_operand:ANYF 2 "register_operand" "f"))
1815 (match_operand:ANYF 3 "register_operand" "f"))))]
1816 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1817 && HONOR_SIGNED_ZEROS (<MODE>mode)
1818 && !HONOR_NANS (<MODE>mode)"
1819 "nmadd.<fmt>\t%0,%3,%1,%2"
1820 [(set_attr "type" "fmadd")
1821 (set_attr "mode" "<UNITMODE>")])
1823 (define_insn "*nmadd<mode>_fastmath"
1824 [(set (match_operand:ANYF 0 "register_operand" "=f")
1826 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1827 (match_operand:ANYF 2 "register_operand" "f"))
1828 (match_operand:ANYF 3 "register_operand" "f")))]
1829 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1830 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1831 && !HONOR_NANS (<MODE>mode)"
1832 "nmadd.<fmt>\t%0,%3,%1,%2"
1833 [(set_attr "type" "fmadd")
1834 (set_attr "mode" "<UNITMODE>")])
1836 (define_insn "*nmsub<mode>"
1837 [(set (match_operand:ANYF 0 "register_operand" "=f")
1838 (neg:ANYF (minus:ANYF
1839 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1840 (match_operand:ANYF 3 "register_operand" "f"))
1841 (match_operand:ANYF 1 "register_operand" "f"))))]
1842 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1843 && HONOR_SIGNED_ZEROS (<MODE>mode)
1844 && !HONOR_NANS (<MODE>mode)"
1845 "nmsub.<fmt>\t%0,%1,%2,%3"
1846 [(set_attr "type" "fmadd")
1847 (set_attr "mode" "<UNITMODE>")])
1849 (define_insn "*nmsub<mode>_fastmath"
1850 [(set (match_operand:ANYF 0 "register_operand" "=f")
1852 (match_operand:ANYF 1 "register_operand" "f")
1853 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1854 (match_operand:ANYF 3 "register_operand" "f"))))]
1855 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1856 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1857 && !HONOR_NANS (<MODE>mode)"
1858 "nmsub.<fmt>\t%0,%1,%2,%3"
1859 [(set_attr "type" "fmadd")
1860 (set_attr "mode" "<UNITMODE>")])
1863 ;; ....................
1865 ;; DIVISION and REMAINDER
1867 ;; ....................
1870 (define_expand "div<mode>3"
1871 [(set (match_operand:ANYF 0 "register_operand")
1872 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1873 (match_operand:ANYF 2 "register_operand")))]
1874 "<divide_condition>"
1876 if (const_1_operand (operands[1], <MODE>mode))
1877 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1878 operands[1] = force_reg (<MODE>mode, operands[1]);
1881 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1883 ;; If an mfc1 or dmfc1 happens to access the floating point register
1884 ;; file at the same time a long latency operation (div, sqrt, recip,
1885 ;; sqrt) iterates an intermediate result back through the floating
1886 ;; point register file bypass, then instead returning the correct
1887 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1888 ;; result of the long latency operation.
1890 ;; The workaround is to insert an unconditional 'mov' from/to the
1891 ;; long latency op destination register.
1893 (define_insn "*div<mode>3"
1894 [(set (match_operand:ANYF 0 "register_operand" "=f")
1895 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1896 (match_operand:ANYF 2 "register_operand" "f")))]
1897 "<divide_condition>"
1900 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1902 return "div.<fmt>\t%0,%1,%2";
1904 [(set_attr "type" "fdiv")
1905 (set_attr "mode" "<UNITMODE>")
1906 (set (attr "length")
1907 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1911 (define_insn "*recip<mode>3"
1912 [(set (match_operand:ANYF 0 "register_operand" "=f")
1913 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1914 (match_operand:ANYF 2 "register_operand" "f")))]
1915 "<recip_condition> && flag_unsafe_math_optimizations"
1918 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1920 return "recip.<fmt>\t%0,%2";
1922 [(set_attr "type" "frdiv")
1923 (set_attr "mode" "<UNITMODE>")
1924 (set (attr "length")
1925 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1929 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1930 ;; with negative operands. We use special libgcc functions instead.
1931 (define_insn "divmod<mode>4"
1932 [(set (match_operand:GPR 0 "register_operand" "=l")
1933 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1934 (match_operand:GPR 2 "register_operand" "d")))
1935 (set (match_operand:GPR 3 "register_operand" "=h")
1936 (mod:GPR (match_dup 1)
1938 "!TARGET_FIX_VR4120"
1939 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1940 [(set_attr "type" "idiv")
1941 (set_attr "mode" "<MODE>")])
1943 (define_insn "udivmod<mode>4"
1944 [(set (match_operand:GPR 0 "register_operand" "=l")
1945 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1946 (match_operand:GPR 2 "register_operand" "d")))
1947 (set (match_operand:GPR 3 "register_operand" "=h")
1948 (umod:GPR (match_dup 1)
1951 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1952 [(set_attr "type" "idiv")
1953 (set_attr "mode" "<MODE>")])
1956 ;; ....................
1960 ;; ....................
1962 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1963 ;; "*div[sd]f3" comment for details).
1965 (define_insn "sqrt<mode>2"
1966 [(set (match_operand:ANYF 0 "register_operand" "=f")
1967 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1971 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1973 return "sqrt.<fmt>\t%0,%1";
1975 [(set_attr "type" "fsqrt")
1976 (set_attr "mode" "<UNITMODE>")
1977 (set (attr "length")
1978 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1982 (define_insn "*rsqrt<mode>a"
1983 [(set (match_operand:ANYF 0 "register_operand" "=f")
1984 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1985 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
1986 "<recip_condition> && flag_unsafe_math_optimizations"
1989 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1991 return "rsqrt.<fmt>\t%0,%2";
1993 [(set_attr "type" "frsqrt")
1994 (set_attr "mode" "<UNITMODE>")
1995 (set (attr "length")
1996 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2000 (define_insn "*rsqrt<mode>b"
2001 [(set (match_operand:ANYF 0 "register_operand" "=f")
2002 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2003 (match_operand:ANYF 2 "register_operand" "f"))))]
2004 "<recip_condition> && flag_unsafe_math_optimizations"
2007 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2009 return "rsqrt.<fmt>\t%0,%2";
2011 [(set_attr "type" "frsqrt")
2012 (set_attr "mode" "<UNITMODE>")
2013 (set (attr "length")
2014 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2019 ;; ....................
2023 ;; ....................
2025 ;; Do not use the integer abs macro instruction, since that signals an
2026 ;; exception on -2147483648 (sigh).
2028 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2029 ;; invalid; it does not clear their sign bits. We therefore can't use
2030 ;; abs.fmt if the signs of NaNs matter.
2032 (define_insn "abs<mode>2"
2033 [(set (match_operand:ANYF 0 "register_operand" "=f")
2034 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2035 "!HONOR_NANS (<MODE>mode)"
2037 [(set_attr "type" "fabs")
2038 (set_attr "mode" "<UNITMODE>")])
2041 ;; ...................
2043 ;; Count leading zeroes.
2045 ;; ...................
2048 (define_insn "clz<mode>2"
2049 [(set (match_operand:GPR 0 "register_operand" "=d")
2050 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2053 [(set_attr "type" "clz")
2054 (set_attr "mode" "<MODE>")])
2057 ;; ....................
2059 ;; NEGATION and ONE'S COMPLEMENT
2061 ;; ....................
2063 (define_insn "negsi2"
2064 [(set (match_operand:SI 0 "register_operand" "=d")
2065 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2069 return "neg\t%0,%1";
2071 return "subu\t%0,%.,%1";
2073 [(set_attr "type" "arith")
2074 (set_attr "mode" "SI")])
2076 (define_insn "negdi2"
2077 [(set (match_operand:DI 0 "register_operand" "=d")
2078 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2079 "TARGET_64BIT && !TARGET_MIPS16"
2081 [(set_attr "type" "arith")
2082 (set_attr "mode" "DI")])
2084 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2085 ;; invalid; it does not flip their sign bit. We therefore can't use
2086 ;; neg.fmt if the signs of NaNs matter.
2088 (define_insn "neg<mode>2"
2089 [(set (match_operand:ANYF 0 "register_operand" "=f")
2090 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2091 "!HONOR_NANS (<MODE>mode)"
2093 [(set_attr "type" "fneg")
2094 (set_attr "mode" "<UNITMODE>")])
2096 (define_insn "one_cmpl<mode>2"
2097 [(set (match_operand:GPR 0 "register_operand" "=d")
2098 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2102 return "not\t%0,%1";
2104 return "nor\t%0,%.,%1";
2106 [(set_attr "type" "arith")
2107 (set_attr "mode" "<MODE>")])
2110 ;; ....................
2114 ;; ....................
2117 ;; Many of these instructions use trivial define_expands, because we
2118 ;; want to use a different set of constraints when TARGET_MIPS16.
2120 (define_expand "and<mode>3"
2121 [(set (match_operand:GPR 0 "register_operand")
2122 (and:GPR (match_operand:GPR 1 "register_operand")
2123 (match_operand:GPR 2 "uns_arith_operand")))]
2127 operands[2] = force_reg (<MODE>mode, operands[2]);
2130 (define_insn "*and<mode>3"
2131 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2132 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2133 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2138 [(set_attr "type" "arith")
2139 (set_attr "mode" "<MODE>")])
2141 (define_insn "*and<mode>3_mips16"
2142 [(set (match_operand:GPR 0 "register_operand" "=d")
2143 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2144 (match_operand:GPR 2 "register_operand" "d")))]
2147 [(set_attr "type" "arith")
2148 (set_attr "mode" "<MODE>")])
2150 (define_expand "ior<mode>3"
2151 [(set (match_operand:GPR 0 "register_operand")
2152 (ior:GPR (match_operand:GPR 1 "register_operand")
2153 (match_operand:GPR 2 "uns_arith_operand")))]
2157 operands[2] = force_reg (<MODE>mode, operands[2]);
2160 (define_insn "*ior<mode>3"
2161 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2162 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2163 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2168 [(set_attr "type" "arith")
2169 (set_attr "mode" "<MODE>")])
2171 (define_insn "*ior<mode>3_mips16"
2172 [(set (match_operand:GPR 0 "register_operand" "=d")
2173 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2174 (match_operand:GPR 2 "register_operand" "d")))]
2177 [(set_attr "type" "arith")
2178 (set_attr "mode" "<MODE>")])
2180 (define_expand "xor<mode>3"
2181 [(set (match_operand:GPR 0 "register_operand")
2182 (xor:GPR (match_operand:GPR 1 "register_operand")
2183 (match_operand:GPR 2 "uns_arith_operand")))]
2188 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2189 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2190 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2195 [(set_attr "type" "arith")
2196 (set_attr "mode" "<MODE>")])
2199 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2200 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2201 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2207 [(set_attr "type" "arith")
2208 (set_attr "mode" "<MODE>")
2209 (set_attr_alternative "length"
2211 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2216 (define_insn "*nor<mode>3"
2217 [(set (match_operand:GPR 0 "register_operand" "=d")
2218 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2219 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2222 [(set_attr "type" "arith")
2223 (set_attr "mode" "<MODE>")])
2226 ;; ....................
2230 ;; ....................
2234 (define_insn "truncdfsf2"
2235 [(set (match_operand:SF 0 "register_operand" "=f")
2236 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2237 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2239 [(set_attr "type" "fcvt")
2240 (set_attr "cnv_mode" "D2S")
2241 (set_attr "mode" "SF")])
2243 ;; Integer truncation patterns. Truncating SImode values to smaller
2244 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2245 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2246 ;; need to make sure that the lower 32 bits are properly sign-extended
2247 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2248 ;; smaller than SImode is equivalent to two separate truncations:
2251 ;; DI ---> HI == DI ---> SI ---> HI
2252 ;; DI ---> QI == DI ---> SI ---> QI
2254 ;; Step A needs a real instruction but step B does not.
2256 (define_insn "truncdisi2"
2257 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2258 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2263 [(set_attr "type" "shift,store")
2264 (set_attr "mode" "SI")
2265 (set_attr "extended_mips16" "yes,*")])
2267 (define_insn "truncdihi2"
2268 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2269 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2274 [(set_attr "type" "shift,store")
2275 (set_attr "mode" "SI")
2276 (set_attr "extended_mips16" "yes,*")])
2278 (define_insn "truncdiqi2"
2279 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2280 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2285 [(set_attr "type" "shift,store")
2286 (set_attr "mode" "SI")
2287 (set_attr "extended_mips16" "yes,*")])
2289 ;; Combiner patterns to optimize shift/truncate combinations.
2292 [(set (match_operand:SI 0 "register_operand" "=d")
2294 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2295 (match_operand:DI 2 "const_arith_operand" ""))))]
2296 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2298 [(set_attr "type" "shift")
2299 (set_attr "mode" "SI")])
2302 [(set (match_operand:SI 0 "register_operand" "=d")
2303 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2305 "TARGET_64BIT && !TARGET_MIPS16"
2307 [(set_attr "type" "shift")
2308 (set_attr "mode" "SI")])
2311 ;; Combiner patterns for truncate/sign_extend combinations. They use
2312 ;; the shift/truncate patterns above.
2314 (define_insn_and_split ""
2315 [(set (match_operand:SI 0 "register_operand" "=d")
2317 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2318 "TARGET_64BIT && !TARGET_MIPS16"
2320 "&& reload_completed"
2322 (ashift:DI (match_dup 1)
2325 (truncate:SI (ashiftrt:DI (match_dup 2)
2327 { operands[2] = gen_lowpart (DImode, operands[0]); })
2329 (define_insn_and_split ""
2330 [(set (match_operand:SI 0 "register_operand" "=d")
2332 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2333 "TARGET_64BIT && !TARGET_MIPS16"
2335 "&& reload_completed"
2337 (ashift:DI (match_dup 1)
2340 (truncate:SI (ashiftrt:DI (match_dup 2)
2342 { operands[2] = gen_lowpart (DImode, operands[0]); })
2345 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2348 [(set (match_operand:SI 0 "register_operand" "=d")
2349 (zero_extend:SI (truncate:HI
2350 (match_operand:DI 1 "register_operand" "d"))))]
2351 "TARGET_64BIT && !TARGET_MIPS16"
2352 "andi\t%0,%1,0xffff"
2353 [(set_attr "type" "arith")
2354 (set_attr "mode" "SI")])
2357 [(set (match_operand:SI 0 "register_operand" "=d")
2358 (zero_extend:SI (truncate:QI
2359 (match_operand:DI 1 "register_operand" "d"))))]
2360 "TARGET_64BIT && !TARGET_MIPS16"
2362 [(set_attr "type" "arith")
2363 (set_attr "mode" "SI")])
2366 [(set (match_operand:HI 0 "register_operand" "=d")
2367 (zero_extend:HI (truncate:QI
2368 (match_operand:DI 1 "register_operand" "d"))))]
2369 "TARGET_64BIT && !TARGET_MIPS16"
2371 [(set_attr "type" "arith")
2372 (set_attr "mode" "HI")])
2375 ;; ....................
2379 ;; ....................
2383 (define_insn_and_split "zero_extendsidi2"
2384 [(set (match_operand:DI 0 "register_operand" "=d,d")
2385 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2390 "&& reload_completed && REG_P (operands[1])"
2392 (ashift:DI (match_dup 1) (const_int 32)))
2394 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2395 { operands[1] = gen_lowpart (DImode, operands[1]); }
2396 [(set_attr "type" "multi,load")
2397 (set_attr "mode" "DI")
2398 (set_attr "length" "8,*")])
2400 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2401 ;; because of TRULY_NOOP_TRUNCATION.
2403 (define_insn_and_split "*clear_upper32"
2404 [(set (match_operand:DI 0 "register_operand" "=d,d")
2405 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2406 (const_int 4294967295)))]
2409 if (which_alternative == 0)
2412 operands[1] = gen_lowpart (SImode, operands[1]);
2413 return "lwu\t%0,%1";
2415 "&& reload_completed && REG_P (operands[1])"
2417 (ashift:DI (match_dup 1) (const_int 32)))
2419 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2421 [(set_attr "type" "multi,load")
2422 (set_attr "mode" "DI")
2423 (set_attr "length" "8,*")])
2425 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2426 [(set (match_operand:GPR 0 "register_operand")
2427 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2430 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2431 && !memory_operand (operands[1], <SHORT:MODE>mode))
2433 emit_insn (gen_and<GPR:mode>3 (operands[0],
2434 gen_lowpart (<GPR:MODE>mode, operands[1]),
2435 force_reg (<GPR:MODE>mode,
2436 GEN_INT (<SHORT:mask>))));
2441 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2442 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2444 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2447 andi\t%0,%1,<SHORT:mask>
2448 l<SHORT:size>u\t%0,%1"
2449 [(set_attr "type" "arith,load")
2450 (set_attr "mode" "<GPR:MODE>")])
2452 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2453 [(set (match_operand:GPR 0 "register_operand" "=d")
2454 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2456 "ze<SHORT:size>\t%0"
2457 [(set_attr "type" "arith")
2458 (set_attr "mode" "<GPR:MODE>")])
2460 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2461 [(set (match_operand:GPR 0 "register_operand" "=d")
2462 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2464 "l<SHORT:size>u\t%0,%1"
2465 [(set_attr "type" "load")
2466 (set_attr "mode" "<GPR:MODE>")])
2468 (define_expand "zero_extendqihi2"
2469 [(set (match_operand:HI 0 "register_operand")
2470 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2473 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2475 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2481 (define_insn "*zero_extendqihi2"
2482 [(set (match_operand:HI 0 "register_operand" "=d,d")
2483 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2488 [(set_attr "type" "arith,load")
2489 (set_attr "mode" "HI")])
2491 (define_insn "*zero_extendqihi2_mips16"
2492 [(set (match_operand:HI 0 "register_operand" "=d")
2493 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2496 [(set_attr "type" "load")
2497 (set_attr "mode" "HI")])
2500 ;; ....................
2504 ;; ....................
2507 ;; Those for integer source operand are ordered widest source type first.
2509 ;; When TARGET_64BIT, all SImode integer registers should already be in
2510 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2511 ;; therefore get rid of register->register instructions if we constrain
2512 ;; the source to be in the same register as the destination.
2514 ;; The register alternative has type "arith" so that the pre-reload
2515 ;; scheduler will treat it as a move. This reflects what happens if
2516 ;; the register alternative needs a reload.
2517 (define_insn_and_split "extendsidi2"
2518 [(set (match_operand:DI 0 "register_operand" "=d,d")
2519 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2524 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2527 emit_note (NOTE_INSN_DELETED);
2530 [(set_attr "type" "arith,load")
2531 (set_attr "mode" "DI")])
2533 (define_expand "extend<SHORT:mode><GPR:mode>2"
2534 [(set (match_operand:GPR 0 "register_operand")
2535 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2538 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2539 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2540 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2544 l<SHORT:size>\t%0,%1"
2545 [(set_attr "type" "arith,load")
2546 (set_attr "mode" "<GPR:MODE>")])
2548 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2549 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2551 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2552 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2555 l<SHORT:size>\t%0,%1"
2556 "&& reload_completed && REG_P (operands[1])"
2557 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2558 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2560 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2561 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2562 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2564 [(set_attr "type" "arith,load")
2565 (set_attr "mode" "<GPR:MODE>")
2566 (set_attr "length" "8,*")])
2568 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2569 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2571 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2574 se<SHORT:size>\t%0,%1
2575 l<SHORT:size>\t%0,%1"
2576 [(set_attr "type" "arith,load")
2577 (set_attr "mode" "<GPR:MODE>")])
2579 ;; This pattern generates the same code as extendqisi2; split it into
2580 ;; that form after reload.
2581 (define_insn_and_split "extendqihi2"
2582 [(set (match_operand:HI 0 "register_operand" "=d,d")
2583 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2587 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
2588 { operands[0] = gen_lowpart (SImode, operands[0]); }
2589 [(set_attr "type" "arith,load")
2590 (set_attr "mode" "SI")
2591 (set_attr "length" "8,*")])
2593 (define_insn "extendsfdf2"
2594 [(set (match_operand:DF 0 "register_operand" "=f")
2595 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2596 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2598 [(set_attr "type" "fcvt")
2599 (set_attr "cnv_mode" "S2D")
2600 (set_attr "mode" "DF")])
2603 ;; ....................
2607 ;; ....................
2609 (define_expand "fix_truncdfsi2"
2610 [(set (match_operand:SI 0 "register_operand")
2611 (fix:SI (match_operand:DF 1 "register_operand")))]
2612 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2614 if (!ISA_HAS_TRUNC_W)
2616 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2621 (define_insn "fix_truncdfsi2_insn"
2622 [(set (match_operand:SI 0 "register_operand" "=f")
2623 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2624 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2626 [(set_attr "type" "fcvt")
2627 (set_attr "mode" "DF")
2628 (set_attr "cnv_mode" "D2I")
2629 (set_attr "length" "4")])
2631 (define_insn "fix_truncdfsi2_macro"
2632 [(set (match_operand:SI 0 "register_operand" "=f")
2633 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2634 (clobber (match_scratch:DF 2 "=d"))]
2635 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2638 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2640 return "trunc.w.d %0,%1,%2";
2642 [(set_attr "type" "fcvt")
2643 (set_attr "mode" "DF")
2644 (set_attr "cnv_mode" "D2I")
2645 (set_attr "length" "36")])
2647 (define_expand "fix_truncsfsi2"
2648 [(set (match_operand:SI 0 "register_operand")
2649 (fix:SI (match_operand:SF 1 "register_operand")))]
2652 if (!ISA_HAS_TRUNC_W)
2654 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2659 (define_insn "fix_truncsfsi2_insn"
2660 [(set (match_operand:SI 0 "register_operand" "=f")
2661 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2662 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2664 [(set_attr "type" "fcvt")
2665 (set_attr "mode" "SF")
2666 (set_attr "cnv_mode" "S2I")
2667 (set_attr "length" "4")])
2669 (define_insn "fix_truncsfsi2_macro"
2670 [(set (match_operand:SI 0 "register_operand" "=f")
2671 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2672 (clobber (match_scratch:SF 2 "=d"))]
2673 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2676 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2678 return "trunc.w.s %0,%1,%2";
2680 [(set_attr "type" "fcvt")
2681 (set_attr "mode" "SF")
2682 (set_attr "cnv_mode" "S2I")
2683 (set_attr "length" "36")])
2686 (define_insn "fix_truncdfdi2"
2687 [(set (match_operand:DI 0 "register_operand" "=f")
2688 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2689 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2691 [(set_attr "type" "fcvt")
2692 (set_attr "mode" "DF")
2693 (set_attr "cnv_mode" "D2I")
2694 (set_attr "length" "4")])
2697 (define_insn "fix_truncsfdi2"
2698 [(set (match_operand:DI 0 "register_operand" "=f")
2699 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2700 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2702 [(set_attr "type" "fcvt")
2703 (set_attr "mode" "SF")
2704 (set_attr "cnv_mode" "S2I")
2705 (set_attr "length" "4")])
2708 (define_insn "floatsidf2"
2709 [(set (match_operand:DF 0 "register_operand" "=f")
2710 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2711 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2713 [(set_attr "type" "fcvt")
2714 (set_attr "mode" "DF")
2715 (set_attr "cnv_mode" "I2D")
2716 (set_attr "length" "4")])
2719 (define_insn "floatdidf2"
2720 [(set (match_operand:DF 0 "register_operand" "=f")
2721 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2722 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2724 [(set_attr "type" "fcvt")
2725 (set_attr "mode" "DF")
2726 (set_attr "cnv_mode" "I2D")
2727 (set_attr "length" "4")])
2730 (define_insn "floatsisf2"
2731 [(set (match_operand:SF 0 "register_operand" "=f")
2732 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2735 [(set_attr "type" "fcvt")
2736 (set_attr "mode" "SF")
2737 (set_attr "cnv_mode" "I2S")
2738 (set_attr "length" "4")])
2741 (define_insn "floatdisf2"
2742 [(set (match_operand:SF 0 "register_operand" "=f")
2743 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2744 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2746 [(set_attr "type" "fcvt")
2747 (set_attr "mode" "SF")
2748 (set_attr "cnv_mode" "I2S")
2749 (set_attr "length" "4")])
2752 (define_expand "fixuns_truncdfsi2"
2753 [(set (match_operand:SI 0 "register_operand")
2754 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2755 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2757 rtx reg1 = gen_reg_rtx (DFmode);
2758 rtx reg2 = gen_reg_rtx (DFmode);
2759 rtx reg3 = gen_reg_rtx (SImode);
2760 rtx label1 = gen_label_rtx ();
2761 rtx label2 = gen_label_rtx ();
2762 REAL_VALUE_TYPE offset;
2764 real_2expN (&offset, 31);
2766 if (reg1) /* Turn off complaints about unreached code. */
2768 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2769 do_pending_stack_adjust ();
2771 emit_insn (gen_cmpdf (operands[1], reg1));
2772 emit_jump_insn (gen_bge (label1));
2774 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2775 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2776 gen_rtx_LABEL_REF (VOIDmode, label2)));
2779 emit_label (label1);
2780 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2781 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2782 (BITMASK_HIGH, SImode)));
2784 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2785 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2787 emit_label (label2);
2789 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2790 fields, and can't be used for REG_NOTES anyway). */
2791 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2797 (define_expand "fixuns_truncdfdi2"
2798 [(set (match_operand:DI 0 "register_operand")
2799 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2800 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2802 rtx reg1 = gen_reg_rtx (DFmode);
2803 rtx reg2 = gen_reg_rtx (DFmode);
2804 rtx reg3 = gen_reg_rtx (DImode);
2805 rtx label1 = gen_label_rtx ();
2806 rtx label2 = gen_label_rtx ();
2807 REAL_VALUE_TYPE offset;
2809 real_2expN (&offset, 63);
2811 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2812 do_pending_stack_adjust ();
2814 emit_insn (gen_cmpdf (operands[1], reg1));
2815 emit_jump_insn (gen_bge (label1));
2817 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2818 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2819 gen_rtx_LABEL_REF (VOIDmode, label2)));
2822 emit_label (label1);
2823 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2824 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2825 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2827 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2828 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2830 emit_label (label2);
2832 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2833 fields, and can't be used for REG_NOTES anyway). */
2834 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2839 (define_expand "fixuns_truncsfsi2"
2840 [(set (match_operand:SI 0 "register_operand")
2841 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2844 rtx reg1 = gen_reg_rtx (SFmode);
2845 rtx reg2 = gen_reg_rtx (SFmode);
2846 rtx reg3 = gen_reg_rtx (SImode);
2847 rtx label1 = gen_label_rtx ();
2848 rtx label2 = gen_label_rtx ();
2849 REAL_VALUE_TYPE offset;
2851 real_2expN (&offset, 31);
2853 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2854 do_pending_stack_adjust ();
2856 emit_insn (gen_cmpsf (operands[1], reg1));
2857 emit_jump_insn (gen_bge (label1));
2859 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2860 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2861 gen_rtx_LABEL_REF (VOIDmode, label2)));
2864 emit_label (label1);
2865 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2866 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2867 (BITMASK_HIGH, SImode)));
2869 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2870 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2872 emit_label (label2);
2874 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2875 fields, and can't be used for REG_NOTES anyway). */
2876 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2881 (define_expand "fixuns_truncsfdi2"
2882 [(set (match_operand:DI 0 "register_operand")
2883 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2884 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2886 rtx reg1 = gen_reg_rtx (SFmode);
2887 rtx reg2 = gen_reg_rtx (SFmode);
2888 rtx reg3 = gen_reg_rtx (DImode);
2889 rtx label1 = gen_label_rtx ();
2890 rtx label2 = gen_label_rtx ();
2891 REAL_VALUE_TYPE offset;
2893 real_2expN (&offset, 63);
2895 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2896 do_pending_stack_adjust ();
2898 emit_insn (gen_cmpsf (operands[1], reg1));
2899 emit_jump_insn (gen_bge (label1));
2901 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2902 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2903 gen_rtx_LABEL_REF (VOIDmode, label2)));
2906 emit_label (label1);
2907 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2908 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2909 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2911 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2912 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2914 emit_label (label2);
2916 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2917 fields, and can't be used for REG_NOTES anyway). */
2918 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2923 ;; ....................
2927 ;; ....................
2929 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2931 (define_expand "extv"
2932 [(set (match_operand 0 "register_operand")
2933 (sign_extract (match_operand:QI 1 "memory_operand")
2934 (match_operand 2 "immediate_operand")
2935 (match_operand 3 "immediate_operand")))]
2938 if (mips_expand_unaligned_load (operands[0], operands[1],
2939 INTVAL (operands[2]),
2940 INTVAL (operands[3])))
2946 (define_expand "extzv"
2947 [(set (match_operand 0 "register_operand")
2948 (zero_extract (match_operand 1 "nonimmediate_operand")
2949 (match_operand 2 "immediate_operand")
2950 (match_operand 3 "immediate_operand")))]
2953 if (mips_expand_unaligned_load (operands[0], operands[1],
2954 INTVAL (operands[2]),
2955 INTVAL (operands[3])))
2957 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
2959 if (GET_MODE (operands[0]) == DImode)
2960 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
2963 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
2971 (define_insn "extzv<mode>"
2972 [(set (match_operand:GPR 0 "register_operand" "=d")
2973 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
2974 (match_operand:SI 2 "immediate_operand" "I")
2975 (match_operand:SI 3 "immediate_operand" "I")))]
2976 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
2977 "<d>ext\t%0,%1,%3,%2"
2978 [(set_attr "type" "arith")
2979 (set_attr "mode" "<MODE>")])
2982 (define_expand "insv"
2983 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
2984 (match_operand 1 "immediate_operand")
2985 (match_operand 2 "immediate_operand"))
2986 (match_operand 3 "reg_or_0_operand"))]
2989 if (mips_expand_unaligned_store (operands[0], operands[3],
2990 INTVAL (operands[1]),
2991 INTVAL (operands[2])))
2993 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
2995 if (GET_MODE (operands[0]) == DImode)
2996 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
2999 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3007 (define_insn "insv<mode>"
3008 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3009 (match_operand:SI 1 "immediate_operand" "I")
3010 (match_operand:SI 2 "immediate_operand" "I"))
3011 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3012 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
3013 "<d>ins\t%0,%z3,%2,%1"
3014 [(set_attr "type" "arith")
3015 (set_attr "mode" "<MODE>")])
3017 ;; Unaligned word moves generated by the bit field patterns.
3019 ;; As far as the rtl is concerned, both the left-part and right-part
3020 ;; instructions can access the whole field. However, the real operand
3021 ;; refers to just the first or the last byte (depending on endianness).
3022 ;; We therefore use two memory operands to each instruction, one to
3023 ;; describe the rtl effect and one to use in the assembly output.
3025 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3026 ;; This allows us to use the standard length calculations for the "load"
3027 ;; and "store" type attributes.
3029 (define_insn "mov_<load>l"
3030 [(set (match_operand:GPR 0 "register_operand" "=d")
3031 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3032 (match_operand:QI 2 "memory_operand" "m")]
3034 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3036 [(set_attr "type" "load")
3037 (set_attr "mode" "<MODE>")])
3039 (define_insn "mov_<load>r"
3040 [(set (match_operand:GPR 0 "register_operand" "=d")
3041 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3042 (match_operand:QI 2 "memory_operand" "m")
3043 (match_operand:GPR 3 "register_operand" "0")]
3044 UNSPEC_LOAD_RIGHT))]
3045 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3047 [(set_attr "type" "load")
3048 (set_attr "mode" "<MODE>")])
3050 (define_insn "mov_<store>l"
3051 [(set (match_operand:BLK 0 "memory_operand" "=m")
3052 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3053 (match_operand:QI 2 "memory_operand" "m")]
3054 UNSPEC_STORE_LEFT))]
3055 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3057 [(set_attr "type" "store")
3058 (set_attr "mode" "<MODE>")])
3060 (define_insn "mov_<store>r"
3061 [(set (match_operand:BLK 0 "memory_operand" "+m")
3062 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3063 (match_operand:QI 2 "memory_operand" "m")
3065 UNSPEC_STORE_RIGHT))]
3066 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3068 [(set_attr "type" "store")
3069 (set_attr "mode" "<MODE>")])
3071 ;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL.
3072 ;; The required value is:
3074 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3076 ;; which translates to:
3078 ;; lui op0,%highest(op1)
3079 ;; daddiu op0,op0,%higher(op1)
3081 ;; daddiu op0,op0,%hi(op1)
3084 ;; The split is deferred until after flow2 to allow the peephole2 below
3086 (define_insn_and_split "*lea_high64"
3087 [(set (match_operand:DI 0 "register_operand" "=d")
3088 (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
3089 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3091 "&& flow2_completed"
3092 [(set (match_dup 0) (high:DI (match_dup 2)))
3093 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3094 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3095 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3096 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3098 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3099 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3101 [(set_attr "length" "20")])
3103 ;; Use a scratch register to reduce the latency of the above pattern
3104 ;; on superscalar machines. The optimized sequence is:
3106 ;; lui op1,%highest(op2)
3108 ;; daddiu op1,op1,%higher(op2)
3110 ;; daddu op1,op1,op0
3112 [(set (match_operand:DI 1 "register_operand")
3113 (high:DI (match_operand:DI 2 "general_symbolic_operand")))
3114 (match_scratch:DI 0 "d")]
3115 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3116 [(set (match_dup 1) (high:DI (match_dup 3)))
3117 (set (match_dup 0) (high:DI (match_dup 4)))
3118 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3119 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3120 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3122 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3123 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3126 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3127 ;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
3128 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3129 ;; used once. We can then use the sequence:
3131 ;; lui op0,%highest(op1)
3133 ;; daddiu op0,op0,%higher(op1)
3134 ;; daddiu op2,op2,%lo(op1)
3136 ;; daddu op0,op0,op2
3138 ;; which takes 4 cycles on most superscalar targets.
3139 (define_insn_and_split "*lea64"
3140 [(set (match_operand:DI 0 "register_operand" "=d")
3141 (match_operand:DI 1 "general_symbolic_operand" ""))
3142 (clobber (match_scratch:DI 2 "=&d"))]
3143 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3145 "&& reload_completed"
3146 [(set (match_dup 0) (high:DI (match_dup 3)))
3147 (set (match_dup 2) (high:DI (match_dup 4)))
3148 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3149 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3150 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3151 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3153 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3154 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3156 [(set_attr "length" "24")])
3158 ;; Insns to fetch a global symbol from a big GOT.
3160 (define_insn_and_split "*xgot_hi<mode>"
3161 [(set (match_operand:P 0 "register_operand" "=d")
3162 (high:P (match_operand:P 1 "global_got_operand" "")))]
3163 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3165 "&& reload_completed"
3166 [(set (match_dup 0) (high:P (match_dup 2)))
3167 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3169 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
3170 operands[3] = pic_offset_table_rtx;
3172 [(set_attr "got" "xgot_high")
3173 (set_attr "mode" "<MODE>")])
3175 (define_insn_and_split "*xgot_lo<mode>"
3176 [(set (match_operand:P 0 "register_operand" "=d")
3177 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3178 (match_operand:P 2 "global_got_operand" "")))]
3179 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3181 "&& reload_completed"
3183 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3184 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_GLOBAL); }
3185 [(set_attr "got" "load")
3186 (set_attr "mode" "<MODE>")])
3188 ;; Insns to fetch a global symbol from a normal GOT.
3190 (define_insn_and_split "*got_disp<mode>"
3191 [(set (match_operand:P 0 "register_operand" "=d")
3192 (match_operand:P 1 "global_got_operand" ""))]
3193 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3195 "&& reload_completed"
3197 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3199 operands[2] = pic_offset_table_rtx;
3200 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
3202 [(set_attr "got" "load")
3203 (set_attr "mode" "<MODE>")])
3205 ;; Insns for loading the high part of a local symbol.
3207 (define_insn_and_split "*got_page<mode>"
3208 [(set (match_operand:P 0 "register_operand" "=d")
3209 (high:P (match_operand:P 1 "local_got_operand" "")))]
3210 "TARGET_EXPLICIT_RELOCS"
3212 "&& reload_completed"
3214 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3216 operands[2] = pic_offset_table_rtx;
3217 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3219 [(set_attr "got" "load")
3220 (set_attr "mode" "<MODE>")])
3222 ;; Lower-level instructions for loading an address from the GOT.
3223 ;; We could use MEMs, but an unspec gives more optimization
3226 (define_insn "load_got<mode>"
3227 [(set (match_operand:P 0 "register_operand" "=d")
3228 (unspec:P [(match_operand:P 1 "register_operand" "d")
3229 (match_operand:P 2 "immediate_operand" "")]
3232 "<load>\t%0,%R2(%1)"
3233 [(set_attr "type" "load")
3234 (set_attr "mode" "<MODE>")
3235 (set_attr "length" "4")])
3237 ;; Instructions for adding the low 16 bits of an address to a register.
3238 ;; Operand 2 is the address: print_operand works out which relocation
3239 ;; should be applied.
3241 (define_insn "*low<mode>"
3242 [(set (match_operand:P 0 "register_operand" "=d")
3243 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3244 (match_operand:P 2 "immediate_operand" "")))]
3246 "<d>addiu\t%0,%1,%R2"
3247 [(set_attr "type" "arith")
3248 (set_attr "mode" "<MODE>")])
3250 (define_insn "*low<mode>_mips16"
3251 [(set (match_operand:P 0 "register_operand" "=d")
3252 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3253 (match_operand:P 2 "immediate_operand" "")))]
3256 [(set_attr "type" "arith")
3257 (set_attr "mode" "<MODE>")
3258 (set_attr "length" "8")])
3260 ;; Allow combine to split complex const_int load sequences, using operand 2
3261 ;; to store the intermediate results. See move_operand for details.
3263 [(set (match_operand:GPR 0 "register_operand")
3264 (match_operand:GPR 1 "splittable_const_int_operand"))
3265 (clobber (match_operand:GPR 2 "register_operand"))]
3269 mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
3273 ;; Likewise, for symbolic operands.
3275 [(set (match_operand:P 0 "register_operand")
3276 (match_operand:P 1 "splittable_symbolic_operand"))
3277 (clobber (match_operand:P 2 "register_operand"))]
3279 [(set (match_dup 0) (match_dup 1))]
3280 { operands[1] = mips_split_symbol (operands[2], operands[1]); })
3282 ;; 64-bit integer moves
3284 ;; Unlike most other insns, the move insns can't be split with
3285 ;; different predicates, because register spilling and other parts of
3286 ;; the compiler, have memoized the insn number already.
3288 (define_expand "movdi"
3289 [(set (match_operand:DI 0 "")
3290 (match_operand:DI 1 ""))]
3293 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3297 ;; For mips16, we need a special case to handle storing $31 into
3298 ;; memory, since we don't have a constraint to match $31. This
3299 ;; instruction can be generated by save_restore_insns.
3301 (define_insn "*mov<mode>_ra"
3302 [(set (match_operand:GPR 0 "stack_operand" "=m")
3306 [(set_attr "type" "store")
3307 (set_attr "mode" "<MODE>")])
3309 (define_insn "*movdi_32bit"
3310 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3311 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3312 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3313 && (register_operand (operands[0], DImode)
3314 || reg_or_0_operand (operands[1], DImode))"
3315 { return mips_output_move (operands[0], operands[1]); }
3316 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3317 (set_attr "mode" "DI")
3318 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3320 (define_insn "*movdi_gp32_fp64"
3321 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
3322 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
3323 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3324 && (register_operand (operands[0], DImode)
3325 || reg_or_0_operand (operands[1], DImode))"
3326 { return mips_output_move (operands[0], operands[1]); }
3327 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
3328 (set_attr "mode" "DI")
3329 (set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
3331 (define_insn "*movdi_32bit_mips16"
3332 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3333 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3334 "!TARGET_64BIT && TARGET_MIPS16
3335 && (register_operand (operands[0], DImode)
3336 || register_operand (operands[1], DImode))"
3337 { return mips_output_move (operands[0], operands[1]); }
3338 [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo")
3339 (set_attr "mode" "DI")
3340 (set_attr "length" "8,8,8,8,12,*,*,8")])
3342 (define_insn "*movdi_64bit"
3343 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3344 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3345 "TARGET_64BIT && !TARGET_MIPS16
3346 && (register_operand (operands[0], DImode)
3347 || reg_or_0_operand (operands[1], DImode))"
3348 { return mips_output_move (operands[0], operands[1]); }
3349 [(set_attr "type" "arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3350 (set_attr "mode" "DI")
3351 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3353 (define_insn "*movdi_64bit_mips16"
3354 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3355 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3356 "TARGET_64BIT && TARGET_MIPS16
3357 && (register_operand (operands[0], DImode)
3358 || register_operand (operands[1], DImode))"
3359 { return mips_output_move (operands[0], operands[1]); }
3360 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3361 (set_attr "mode" "DI")
3362 (set_attr_alternative "length"
3366 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3369 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3374 (const_string "*")])])
3377 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3378 ;; when the original load is a 4 byte instruction but the add and the
3379 ;; load are 2 2 byte instructions.
3382 [(set (match_operand:DI 0 "register_operand")
3383 (mem:DI (plus:DI (match_dup 0)
3384 (match_operand:DI 1 "const_int_operand"))))]
3385 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3386 && !TARGET_DEBUG_D_MODE
3387 && REG_P (operands[0])
3388 && M16_REG_P (REGNO (operands[0]))
3389 && GET_CODE (operands[1]) == CONST_INT
3390 && ((INTVAL (operands[1]) < 0
3391 && INTVAL (operands[1]) >= -0x10)
3392 || (INTVAL (operands[1]) >= 32 * 8
3393 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3394 || (INTVAL (operands[1]) >= 0
3395 && INTVAL (operands[1]) < 32 * 8
3396 && (INTVAL (operands[1]) & 7) != 0))"
3397 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3398 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3400 HOST_WIDE_INT val = INTVAL (operands[1]);
3403 operands[2] = const0_rtx;
3404 else if (val >= 32 * 8)
3408 operands[1] = GEN_INT (0x8 + off);
3409 operands[2] = GEN_INT (val - off - 0x8);
3415 operands[1] = GEN_INT (off);
3416 operands[2] = GEN_INT (val - off);
3420 ;; 32-bit Integer moves
3422 ;; Unlike most other insns, the move insns can't be split with
3423 ;; different predicates, because register spilling and other parts of
3424 ;; the compiler, have memoized the insn number already.
3426 (define_expand "movsi"
3427 [(set (match_operand:SI 0 "")
3428 (match_operand:SI 1 ""))]
3431 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3435 ;; The difference between these two is whether or not ints are allowed
3436 ;; in FP registers (off by default, use -mdebugh to enable).
3438 (define_insn "*movsi_internal"
3439 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3440 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3442 && (register_operand (operands[0], SImode)
3443 || reg_or_0_operand (operands[1], SImode))"
3444 { return mips_output_move (operands[0], operands[1]); }
3445 [(set_attr "type" "arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3446 (set_attr "mode" "SI")
3447 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
3449 (define_insn "*movsi_mips16"
3450 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3451 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3453 && (register_operand (operands[0], SImode)
3454 || register_operand (operands[1], SImode))"
3455 { return mips_output_move (operands[0], operands[1]); }
3456 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3457 (set_attr "mode" "SI")
3458 (set_attr_alternative "length"
3462 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3465 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3470 (const_string "*")])])
3472 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3473 ;; when the original load is a 4 byte instruction but the add and the
3474 ;; load are 2 2 byte instructions.
3477 [(set (match_operand:SI 0 "register_operand")
3478 (mem:SI (plus:SI (match_dup 0)
3479 (match_operand:SI 1 "const_int_operand"))))]
3480 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3481 && REG_P (operands[0])
3482 && M16_REG_P (REGNO (operands[0]))
3483 && GET_CODE (operands[1]) == CONST_INT
3484 && ((INTVAL (operands[1]) < 0
3485 && INTVAL (operands[1]) >= -0x80)
3486 || (INTVAL (operands[1]) >= 32 * 4
3487 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3488 || (INTVAL (operands[1]) >= 0
3489 && INTVAL (operands[1]) < 32 * 4
3490 && (INTVAL (operands[1]) & 3) != 0))"
3491 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3492 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3494 HOST_WIDE_INT val = INTVAL (operands[1]);
3497 operands[2] = const0_rtx;
3498 else if (val >= 32 * 4)
3502 operands[1] = GEN_INT (0x7c + off);
3503 operands[2] = GEN_INT (val - off - 0x7c);
3509 operands[1] = GEN_INT (off);
3510 operands[2] = GEN_INT (val - off);
3514 ;; On the mips16, we can split a load of certain constants into a load
3515 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3519 [(set (match_operand:SI 0 "register_operand")
3520 (match_operand:SI 1 "const_int_operand"))]
3521 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3522 && REG_P (operands[0])
3523 && M16_REG_P (REGNO (operands[0]))
3524 && GET_CODE (operands[1]) == CONST_INT
3525 && INTVAL (operands[1]) >= 0x100
3526 && INTVAL (operands[1]) <= 0xff + 0x7f"
3527 [(set (match_dup 0) (match_dup 1))
3528 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3530 int val = INTVAL (operands[1]);
3532 operands[1] = GEN_INT (0xff);
3533 operands[2] = GEN_INT (val - 0xff);
3536 ;; This insn handles moving CCmode values. It's really just a
3537 ;; slightly simplified copy of movsi_internal2, with additional cases
3538 ;; to move a condition register to a general register and to move
3539 ;; between the general registers and the floating point registers.
3541 (define_insn "movcc"
3542 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3543 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3544 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3545 { return mips_output_move (operands[0], operands[1]); }
3546 [(set_attr "type" "multi,arith,load,store,mfc,mtc,fmove,fpload,fpstore")
3547 (set_attr "mode" "SI")
3548 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3550 ;; Reload condition code registers. reload_incc and reload_outcc
3551 ;; both handle moves from arbitrary operands into condition code
3552 ;; registers. reload_incc handles the more common case in which
3553 ;; a source operand is constrained to be in a condition-code
3554 ;; register, but has not been allocated to one.
3556 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3557 ;; constraints do not include 'z'. reload_outcc handles the case
3558 ;; when such an operand is allocated to a condition-code register.
3560 ;; Note that reloads from a condition code register to some
3561 ;; other location can be done using ordinary moves. Moving
3562 ;; into a GPR takes a single movcc, moving elsewhere takes
3563 ;; two. We can leave these cases to the generic reload code.
3564 (define_expand "reload_incc"
3565 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3566 (match_operand:CC 1 "general_operand" ""))
3567 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3568 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3570 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3574 (define_expand "reload_outcc"
3575 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3576 (match_operand:CC 1 "register_operand" ""))
3577 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3578 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3580 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3584 ;; MIPS4 supports loading and storing a floating point register from
3585 ;; the sum of two general registers. We use two versions for each of
3586 ;; these four instructions: one where the two general registers are
3587 ;; SImode, and one where they are DImode. This is because general
3588 ;; registers will be in SImode when they hold 32-bit values, but,
3589 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3590 ;; instructions will still work correctly.
3592 ;; ??? Perhaps it would be better to support these instructions by
3593 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3594 ;; these instructions can only be used to load and store floating
3595 ;; point registers, that would probably cause trouble in reload.
3597 (define_insn "*<ANYF:loadx>_<P:mode>"
3598 [(set (match_operand:ANYF 0 "register_operand" "=f")
3599 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3600 (match_operand:P 2 "register_operand" "d"))))]
3602 "<ANYF:loadx>\t%0,%1(%2)"
3603 [(set_attr "type" "fpidxload")
3604 (set_attr "mode" "<ANYF:UNITMODE>")])
3606 (define_insn "*<ANYF:storex>_<P:mode>"
3607 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3608 (match_operand:P 2 "register_operand" "d")))
3609 (match_operand:ANYF 0 "register_operand" "f"))]
3611 "<ANYF:storex>\t%0,%1(%2)"
3612 [(set_attr "type" "fpidxstore")
3613 (set_attr "mode" "<ANYF:UNITMODE>")])
3615 ;; 16-bit Integer moves
3617 ;; Unlike most other insns, the move insns can't be split with
3618 ;; different predicates, because register spilling and other parts of
3619 ;; the compiler, have memoized the insn number already.
3620 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3622 (define_expand "movhi"
3623 [(set (match_operand:HI 0 "")
3624 (match_operand:HI 1 ""))]
3627 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3631 (define_insn "*movhi_internal"
3632 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3633 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3635 && (register_operand (operands[0], HImode)
3636 || reg_or_0_operand (operands[1], HImode))"
3646 [(set_attr "type" "arith,arith,load,store,mfc,mtc,fmove,mthilo")
3647 (set_attr "mode" "HI")
3648 (set_attr "length" "4,4,*,*,4,4,4,4")])
3650 (define_insn "*movhi_mips16"
3651 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3652 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3654 && (register_operand (operands[0], HImode)
3655 || register_operand (operands[1], HImode))"
3664 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3665 (set_attr "mode" "HI")
3666 (set_attr_alternative "length"
3670 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3673 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3677 (const_string "*")])])
3680 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3681 ;; when the original load is a 4 byte instruction but the add and the
3682 ;; load are 2 2 byte instructions.
3685 [(set (match_operand:HI 0 "register_operand")
3686 (mem:HI (plus:SI (match_dup 0)
3687 (match_operand:SI 1 "const_int_operand"))))]
3688 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3689 && REG_P (operands[0])
3690 && M16_REG_P (REGNO (operands[0]))
3691 && GET_CODE (operands[1]) == CONST_INT
3692 && ((INTVAL (operands[1]) < 0
3693 && INTVAL (operands[1]) >= -0x80)
3694 || (INTVAL (operands[1]) >= 32 * 2
3695 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3696 || (INTVAL (operands[1]) >= 0
3697 && INTVAL (operands[1]) < 32 * 2
3698 && (INTVAL (operands[1]) & 1) != 0))"
3699 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3700 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3702 HOST_WIDE_INT val = INTVAL (operands[1]);
3705 operands[2] = const0_rtx;
3706 else if (val >= 32 * 2)
3710 operands[1] = GEN_INT (0x7e + off);
3711 operands[2] = GEN_INT (val - off - 0x7e);
3717 operands[1] = GEN_INT (off);
3718 operands[2] = GEN_INT (val - off);
3722 ;; 8-bit Integer moves
3724 ;; Unlike most other insns, the move insns can't be split with
3725 ;; different predicates, because register spilling and other parts of
3726 ;; the compiler, have memoized the insn number already.
3727 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3729 (define_expand "movqi"
3730 [(set (match_operand:QI 0 "")
3731 (match_operand:QI 1 ""))]
3734 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3738 (define_insn "*movqi_internal"
3739 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3740 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3742 && (register_operand (operands[0], QImode)
3743 || reg_or_0_operand (operands[1], QImode))"
3753 [(set_attr "type" "arith,arith,load,store,mfc,mtc,fmove,mthilo")
3754 (set_attr "mode" "QI")
3755 (set_attr "length" "4,4,*,*,4,4,4,4")])
3757 (define_insn "*movqi_mips16"
3758 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3759 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3761 && (register_operand (operands[0], QImode)
3762 || register_operand (operands[1], QImode))"
3771 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3772 (set_attr "mode" "QI")
3773 (set_attr "length" "4,4,4,4,8,*,*")])
3775 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3776 ;; when the original load is a 4 byte instruction but the add and the
3777 ;; load are 2 2 byte instructions.
3780 [(set (match_operand:QI 0 "register_operand")
3781 (mem:QI (plus:SI (match_dup 0)
3782 (match_operand:SI 1 "const_int_operand"))))]
3783 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3784 && REG_P (operands[0])
3785 && M16_REG_P (REGNO (operands[0]))
3786 && GET_CODE (operands[1]) == CONST_INT
3787 && ((INTVAL (operands[1]) < 0
3788 && INTVAL (operands[1]) >= -0x80)
3789 || (INTVAL (operands[1]) >= 32
3790 && INTVAL (operands[1]) <= 31 + 0x7f))"
3791 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3792 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3794 HOST_WIDE_INT val = INTVAL (operands[1]);
3797 operands[2] = const0_rtx;
3800 operands[1] = GEN_INT (0x7f);
3801 operands[2] = GEN_INT (val - 0x7f);
3805 ;; 32-bit floating point moves
3807 (define_expand "movsf"
3808 [(set (match_operand:SF 0 "")
3809 (match_operand:SF 1 ""))]
3812 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3816 (define_insn "*movsf_hardfloat"
3817 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3818 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3820 && (register_operand (operands[0], SFmode)
3821 || reg_or_0_operand (operands[1], SFmode))"
3822 { return mips_output_move (operands[0], operands[1]); }
3823 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3824 (set_attr "mode" "SF")
3825 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3827 (define_insn "*movsf_softfloat"
3828 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3829 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3830 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3831 && (register_operand (operands[0], SFmode)
3832 || reg_or_0_operand (operands[1], SFmode))"
3833 { return mips_output_move (operands[0], operands[1]); }
3834 [(set_attr "type" "arith,load,store")
3835 (set_attr "mode" "SF")
3836 (set_attr "length" "4,*,*")])
3838 (define_insn "*movsf_mips16"
3839 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3840 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3842 && (register_operand (operands[0], SFmode)
3843 || register_operand (operands[1], SFmode))"
3844 { return mips_output_move (operands[0], operands[1]); }
3845 [(set_attr "type" "arith,arith,arith,load,store")
3846 (set_attr "mode" "SF")
3847 (set_attr "length" "4,4,4,*,*")])
3850 ;; 64-bit floating point moves
3852 (define_expand "movdf"
3853 [(set (match_operand:DF 0 "")
3854 (match_operand:DF 1 ""))]
3857 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3861 (define_insn "*movdf_hardfloat_64bit"
3862 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3863 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3864 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3865 && (register_operand (operands[0], DFmode)
3866 || reg_or_0_operand (operands[1], DFmode))"
3867 { return mips_output_move (operands[0], operands[1]); }
3868 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3869 (set_attr "mode" "DF")
3870 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3872 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
3873 (define_insn "*movdf_hardfloat_32bit"
3874 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3875 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3876 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3877 && (register_operand (operands[0], DFmode)
3878 || reg_or_0_operand (operands[1], DFmode))"
3879 { return mips_output_move (operands[0], operands[1]); }
3880 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3881 (set_attr "mode" "DF")
3882 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3884 (define_insn "*movdf_softfloat"
3885 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3886 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3887 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3888 && (register_operand (operands[0], DFmode)
3889 || reg_or_0_operand (operands[1], DFmode))"
3890 { return mips_output_move (operands[0], operands[1]); }
3891 [(set_attr "type" "arith,load,store,mfc,mtc,fmove")
3892 (set_attr "mode" "DF")
3893 (set_attr "length" "8,*,*,4,4,4")])
3895 (define_insn "*movdf_mips16"
3896 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3897 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3899 && (register_operand (operands[0], DFmode)
3900 || register_operand (operands[1], DFmode))"
3901 { return mips_output_move (operands[0], operands[1]); }
3902 [(set_attr "type" "arith,arith,arith,load,store")
3903 (set_attr "mode" "DF")
3904 (set_attr "length" "8,8,8,*,*")])
3907 [(set (match_operand:DI 0 "nonimmediate_operand")
3908 (match_operand:DI 1 "move_operand"))]
3909 "reload_completed && !TARGET_64BIT
3910 && mips_split_64bit_move_p (operands[0], operands[1])"
3913 mips_split_64bit_move (operands[0], operands[1]);
3918 [(set (match_operand:DF 0 "nonimmediate_operand")
3919 (match_operand:DF 1 "move_operand"))]
3920 "reload_completed && !TARGET_64BIT
3921 && mips_split_64bit_move_p (operands[0], operands[1])"
3924 mips_split_64bit_move (operands[0], operands[1]);
3928 ;; When generating mips16 code, split moves of negative constants into
3929 ;; a positive "li" followed by a negation.
3931 [(set (match_operand 0 "register_operand")
3932 (match_operand 1 "const_int_operand"))]
3933 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
3937 (neg:SI (match_dup 2)))]
3939 operands[2] = gen_lowpart (SImode, operands[0]);
3940 operands[3] = GEN_INT (-INTVAL (operands[1]));
3943 ;; 64-bit paired-single floating point moves
3945 (define_expand "movv2sf"
3946 [(set (match_operand:V2SF 0)
3947 (match_operand:V2SF 1))]
3948 "TARGET_PAIRED_SINGLE_FLOAT"
3950 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
3954 (define_insn "movv2sf_hardfloat_64bit"
3955 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3956 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
3957 "TARGET_PAIRED_SINGLE_FLOAT
3959 && (register_operand (operands[0], V2SFmode)
3960 || reg_or_0_operand (operands[1], V2SFmode))"
3961 { return mips_output_move (operands[0], operands[1]); }
3962 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3963 (set_attr "mode" "SF")
3964 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3966 ;; The HI and LO registers are not truly independent. If we move an mthi
3967 ;; instruction before an mflo instruction, it will make the result of the
3968 ;; mflo unpredictable. The same goes for mtlo and mfhi.
3970 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
3971 ;; Operand 1 is the register we want, operand 2 is the other one.
3973 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
3974 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
3975 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
3977 (define_expand "mfhilo_<mode>"
3978 [(set (match_operand:GPR 0 "register_operand")
3979 (unspec:GPR [(match_operand:GPR 1 "register_operand")
3980 (match_operand:GPR 2 "register_operand")]
3983 (define_insn "*mfhilo_<mode>"
3984 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3985 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3986 (match_operand:GPR 2 "register_operand" "l,h")]
3990 [(set_attr "type" "mfhilo")
3991 (set_attr "mode" "<MODE>")])
3993 (define_insn "*mfhilo_<mode>_macc"
3994 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3995 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3996 (match_operand:GPR 2 "register_operand" "l,h")]
4000 if (REGNO (operands[1]) == HI_REGNUM)
4001 return "<d>macchi\t%0,%.,%.";
4003 return "<d>macc\t%0,%.,%.";
4005 [(set_attr "type" "mfhilo")
4006 (set_attr "mode" "<MODE>")])
4008 ;; Patterns for loading or storing part of a paired floating point
4009 ;; register. We need them because odd-numbered floating-point registers
4010 ;; are not fully independent: see mips_split_64bit_move.
4012 ;; Load the low word of operand 0 with operand 1.
4013 (define_insn "load_df_low"
4014 [(set (match_operand:DF 0 "register_operand" "=f,f")
4015 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
4016 UNSPEC_LOAD_DF_LOW))]
4017 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4019 operands[0] = mips_subword (operands[0], 0);
4020 return mips_output_move (operands[0], operands[1]);
4022 [(set_attr "type" "mtc,fpload")
4023 (set_attr "mode" "SF")])
4025 ;; Load the high word of operand 0 from operand 1, preserving the value
4027 (define_insn "load_df_high"
4028 [(set (match_operand:DF 0 "register_operand" "=f,f")
4029 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
4030 (match_operand:DF 2 "register_operand" "0,0")]
4031 UNSPEC_LOAD_DF_HIGH))]
4032 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4034 operands[0] = mips_subword (operands[0], 1);
4035 return mips_output_move (operands[0], operands[1]);
4037 [(set_attr "type" "mtc,fpload")
4038 (set_attr "mode" "SF")])
4040 ;; Store the high word of operand 1 in operand 0. The corresponding
4041 ;; low-word move is done in the normal way.
4042 (define_insn "store_df_high"
4043 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
4044 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
4045 UNSPEC_STORE_DF_HIGH))]
4046 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4048 operands[1] = mips_subword (operands[1], 1);
4049 return mips_output_move (operands[0], operands[1]);
4051 [(set_attr "type" "mfc,fpstore")
4052 (set_attr "mode" "SF")])
4054 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4055 ;; value in the low word.
4056 (define_insn "mthc1"
4057 [(set (match_operand:DF 0 "register_operand" "=f")
4058 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
4059 (match_operand:DF 2 "register_operand" "0")]
4061 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4063 [(set_attr "type" "mtc")
4064 (set_attr "mode" "SF")])
4066 ;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
4067 ;; low-word move is done in the normal way.
4068 (define_insn "mfhc1"
4069 [(set (match_operand:SI 0 "register_operand" "=d")
4070 (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
4072 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4074 [(set_attr "type" "mfc")
4075 (set_attr "mode" "SF")])
4077 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4078 (define_expand "load_const_gp"
4079 [(set (match_operand 0 "register_operand" "=d")
4080 (const (unspec [(const_int 0)] UNSPEC_GP)))])
4082 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4083 ;; of _gp from the start of this function. Operand 1 is the incoming
4084 ;; function address.
4085 (define_insn_and_split "loadgp"
4086 [(unspec_volatile [(match_operand 0 "" "")
4087 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
4088 "mips_current_loadgp_style () == LOADGP_NEWABI"
4091 [(set (match_dup 2) (match_dup 3))
4092 (set (match_dup 2) (match_dup 4))
4093 (set (match_dup 2) (match_dup 5))]
4095 operands[2] = pic_offset_table_rtx;
4096 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
4097 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
4098 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
4100 [(set_attr "length" "12")])
4102 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4103 (define_insn_and_split "loadgp_noshared"
4104 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
4105 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4110 emit_move_insn (pic_offset_table_rtx, operands[0]);
4113 [(set_attr "length" "8")])
4115 ;; The use of gp is hidden when not using explicit relocations.
4116 ;; This blockage instruction prevents the gp load from being
4117 ;; scheduled after an implicit use of gp. It also prevents
4118 ;; the load from being deleted as dead.
4119 (define_insn "loadgp_blockage"
4120 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4123 [(set_attr "type" "unknown")
4124 (set_attr "mode" "none")
4125 (set_attr "length" "0")])
4127 ;; Emit a .cprestore directive, which normally expands to a single store
4128 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4129 ;; code so that jals inside inline asms will work correctly.
4130 (define_insn "cprestore"
4131 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
4135 if (set_nomacro && which_alternative == 1)
4136 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4138 return ".cprestore\t%0";
4140 [(set_attr "type" "store")
4141 (set_attr "length" "4,12")])
4143 ;; Block moves, see mips.c for more details.
4144 ;; Argument 0 is the destination
4145 ;; Argument 1 is the source
4146 ;; Argument 2 is the length
4147 ;; Argument 3 is the alignment
4149 (define_expand "movmemsi"
4150 [(parallel [(set (match_operand:BLK 0 "general_operand")
4151 (match_operand:BLK 1 "general_operand"))
4152 (use (match_operand:SI 2 ""))
4153 (use (match_operand:SI 3 "const_int_operand"))])]
4154 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4156 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4163 ;; ....................
4167 ;; ....................
4169 (define_expand "<optab><mode>3"
4170 [(set (match_operand:GPR 0 "register_operand")
4171 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4172 (match_operand:SI 2 "arith_operand")))]
4175 /* On the mips16, a shift of more than 8 is a four byte instruction,
4176 so, for a shift between 8 and 16, it is just as fast to do two
4177 shifts of 8 or less. If there is a lot of shifting going on, we
4178 may win in CSE. Otherwise combine will put the shifts back
4179 together again. This can be called by function_arg, so we must
4180 be careful not to allocate a new register if we've reached the
4184 && GET_CODE (operands[2]) == CONST_INT
4185 && INTVAL (operands[2]) > 8
4186 && INTVAL (operands[2]) <= 16
4187 && !reload_in_progress
4188 && !reload_completed)
4190 rtx temp = gen_reg_rtx (<MODE>mode);
4192 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4193 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4194 GEN_INT (INTVAL (operands[2]) - 8)));
4199 (define_insn "*<optab><mode>3"
4200 [(set (match_operand:GPR 0 "register_operand" "=d")
4201 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4202 (match_operand:SI 2 "arith_operand" "dI")))]
4205 if (GET_CODE (operands[2]) == CONST_INT)
4206 operands[2] = GEN_INT (INTVAL (operands[2])
4207 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4209 return "<d><insn>\t%0,%1,%2";
4211 [(set_attr "type" "shift")
4212 (set_attr "mode" "<MODE>")])
4214 (define_insn "*<optab>si3_extend"
4215 [(set (match_operand:DI 0 "register_operand" "=d")
4217 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4218 (match_operand:SI 2 "arith_operand" "dI"))))]
4219 "TARGET_64BIT && !TARGET_MIPS16"
4221 if (GET_CODE (operands[2]) == CONST_INT)
4222 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4224 return "<insn>\t%0,%1,%2";
4226 [(set_attr "type" "shift")
4227 (set_attr "mode" "SI")])
4229 (define_insn "*<optab>si3_mips16"
4230 [(set (match_operand:SI 0 "register_operand" "=d,d")
4231 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4232 (match_operand:SI 2 "arith_operand" "d,I")))]
4235 if (which_alternative == 0)
4236 return "<insn>\t%0,%2";
4238 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4239 return "<insn>\t%0,%1,%2";
4241 [(set_attr "type" "shift")
4242 (set_attr "mode" "SI")
4243 (set_attr_alternative "length"
4245 (if_then_else (match_operand 2 "m16_uimm3_b")
4249 ;; We need separate DImode MIPS16 patterns because of the irregularity
4251 (define_insn "*ashldi3_mips16"
4252 [(set (match_operand:DI 0 "register_operand" "=d,d")
4253 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4254 (match_operand:SI 2 "arith_operand" "d,I")))]
4255 "TARGET_64BIT && TARGET_MIPS16"
4257 if (which_alternative == 0)
4258 return "dsll\t%0,%2";
4260 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4261 return "dsll\t%0,%1,%2";
4263 [(set_attr "type" "shift")
4264 (set_attr "mode" "DI")
4265 (set_attr_alternative "length"
4267 (if_then_else (match_operand 2 "m16_uimm3_b")
4271 (define_insn "*ashrdi3_mips16"
4272 [(set (match_operand:DI 0 "register_operand" "=d,d")
4273 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4274 (match_operand:SI 2 "arith_operand" "d,I")))]
4275 "TARGET_64BIT && TARGET_MIPS16"
4277 if (GET_CODE (operands[2]) == CONST_INT)
4278 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4280 return "dsra\t%0,%2";
4282 [(set_attr "type" "shift")
4283 (set_attr "mode" "DI")
4284 (set_attr_alternative "length"
4286 (if_then_else (match_operand 2 "m16_uimm3_b")
4290 (define_insn "*lshrdi3_mips16"
4291 [(set (match_operand:DI 0 "register_operand" "=d,d")
4292 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4293 (match_operand:SI 2 "arith_operand" "d,I")))]
4294 "TARGET_64BIT && TARGET_MIPS16"
4296 if (GET_CODE (operands[2]) == CONST_INT)
4297 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4299 return "dsrl\t%0,%2";
4301 [(set_attr "type" "shift")
4302 (set_attr "mode" "DI")
4303 (set_attr_alternative "length"
4305 (if_then_else (match_operand 2 "m16_uimm3_b")
4309 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4312 [(set (match_operand:GPR 0 "register_operand")
4313 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4314 (match_operand:GPR 2 "const_int_operand")))]
4315 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4316 && GET_CODE (operands[2]) == CONST_INT
4317 && INTVAL (operands[2]) > 8
4318 && INTVAL (operands[2]) <= 16"
4319 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4320 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4321 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4323 ;; If we load a byte on the mips16 as a bitfield, the resulting
4324 ;; sequence of instructions is too complicated for combine, because it
4325 ;; involves four instructions: a load, a shift, a constant load into a
4326 ;; register, and an and (the key problem here is that the mips16 does
4327 ;; not have and immediate). We recognize a shift of a load in order
4328 ;; to make it simple enough for combine to understand.
4330 ;; The length here is the worst case: the length of the split version
4331 ;; will be more accurate.
4332 (define_insn_and_split ""
4333 [(set (match_operand:SI 0 "register_operand" "=d")
4334 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4335 (match_operand:SI 2 "immediate_operand" "I")))]
4339 [(set (match_dup 0) (match_dup 1))
4340 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4342 [(set_attr "type" "load")
4343 (set_attr "mode" "SI")
4344 (set_attr "length" "16")])
4346 (define_insn "rotr<mode>3"
4347 [(set (match_operand:GPR 0 "register_operand" "=d")
4348 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4349 (match_operand:SI 2 "arith_operand" "dI")))]
4352 if (GET_CODE (operands[2]) == CONST_INT)
4353 gcc_assert (INTVAL (operands[2]) >= 0
4354 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4356 return "<d>ror\t%0,%1,%2";
4358 [(set_attr "type" "shift")
4359 (set_attr "mode" "<MODE>")])
4362 ;; ....................
4366 ;; ....................
4368 ;; Flow here is rather complex:
4370 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4371 ;; into cmp_operands[] but generates no RTL.
4373 ;; 2) The appropriate branch define_expand is called, which then
4374 ;; creates the appropriate RTL for the comparison and branch.
4375 ;; Different CC modes are used, based on what type of branch is
4376 ;; done, so that we can constrain things appropriately. There
4377 ;; are assumptions in the rest of GCC that break if we fold the
4378 ;; operands into the branches for integer operations, and use cc0
4379 ;; for floating point, so we use the fp status register instead.
4380 ;; If needed, an appropriate temporary is created to hold the
4381 ;; of the integer compare.
4383 (define_expand "cmp<mode>"
4385 (compare:CC (match_operand:GPR 0 "register_operand")
4386 (match_operand:GPR 1 "nonmemory_operand")))]
4389 cmp_operands[0] = operands[0];
4390 cmp_operands[1] = operands[1];
4394 (define_expand "cmp<mode>"
4396 (compare:CC (match_operand:SCALARF 0 "register_operand")
4397 (match_operand:SCALARF 1 "register_operand")))]
4400 cmp_operands[0] = operands[0];
4401 cmp_operands[1] = operands[1];
4406 ;; ....................
4408 ;; CONDITIONAL BRANCHES
4410 ;; ....................
4412 ;; Conditional branches on floating-point equality tests.
4414 (define_insn "*branch_fp"
4417 (match_operator 0 "equality_operator"
4418 [(match_operand:CC 2 "register_operand" "z")
4420 (label_ref (match_operand 1 "" ""))
4424 return mips_output_conditional_branch (insn, operands,
4425 MIPS_BRANCH ("b%F0", "%Z2%1"),
4426 MIPS_BRANCH ("b%W0", "%Z2%1"));
4428 [(set_attr "type" "branch")
4429 (set_attr "mode" "none")])
4431 (define_insn "*branch_fp_inverted"
4434 (match_operator 0 "equality_operator"
4435 [(match_operand:CC 2 "register_operand" "z")
4438 (label_ref (match_operand 1 "" ""))))]
4441 return mips_output_conditional_branch (insn, operands,
4442 MIPS_BRANCH ("b%W0", "%Z2%1"),
4443 MIPS_BRANCH ("b%F0", "%Z2%1"));
4445 [(set_attr "type" "branch")
4446 (set_attr "mode" "none")])
4448 ;; Conditional branches on ordered comparisons with zero.
4450 (define_insn "*branch_order<mode>"
4453 (match_operator 0 "order_operator"
4454 [(match_operand:GPR 2 "register_operand" "d")
4456 (label_ref (match_operand 1 "" ""))
4459 { return mips_output_order_conditional_branch (insn, operands, false); }
4460 [(set_attr "type" "branch")
4461 (set_attr "mode" "none")])
4463 (define_insn "*branch_order<mode>_inverted"
4466 (match_operator 0 "order_operator"
4467 [(match_operand:GPR 2 "register_operand" "d")
4470 (label_ref (match_operand 1 "" ""))))]
4472 { return mips_output_order_conditional_branch (insn, operands, true); }
4473 [(set_attr "type" "branch")
4474 (set_attr "mode" "none")])
4476 ;; Conditional branch on equality comparison.
4478 (define_insn "*branch_equality<mode>"
4481 (match_operator 0 "equality_operator"
4482 [(match_operand:GPR 2 "register_operand" "d")
4483 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4484 (label_ref (match_operand 1 "" ""))
4488 return mips_output_conditional_branch (insn, operands,
4489 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4490 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4492 [(set_attr "type" "branch")
4493 (set_attr "mode" "none")])
4495 (define_insn "*branch_equality<mode>_inverted"
4498 (match_operator 0 "equality_operator"
4499 [(match_operand:GPR 2 "register_operand" "d")
4500 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4502 (label_ref (match_operand 1 "" ""))))]
4505 return mips_output_conditional_branch (insn, operands,
4506 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4507 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4509 [(set_attr "type" "branch")
4510 (set_attr "mode" "none")])
4514 (define_insn "*branch_equality<mode>_mips16"
4517 (match_operator 0 "equality_operator"
4518 [(match_operand:GPR 1 "register_operand" "d,t")
4520 (match_operand 2 "pc_or_label_operand" "")
4521 (match_operand 3 "pc_or_label_operand" "")))]
4524 if (operands[2] != pc_rtx)
4526 if (which_alternative == 0)
4527 return "b%C0z\t%1,%2";
4529 return "bt%C0z\t%2";
4533 if (which_alternative == 0)
4534 return "b%N0z\t%1,%3";
4536 return "bt%N0z\t%3";
4539 [(set_attr "type" "branch")
4540 (set_attr "mode" "none")
4541 (set_attr "length" "8")])
4543 (define_expand "b<code>"
4545 (if_then_else (any_cond:CC (cc0)
4547 (label_ref (match_operand 0 ""))
4551 gen_conditional_branch (operands, <CODE>);
4555 ;; Used to implement built-in functions.
4556 (define_expand "condjump"
4558 (if_then_else (match_operand 0)
4559 (label_ref (match_operand 1))
4563 ;; ....................
4565 ;; SETTING A REGISTER FROM A COMPARISON
4567 ;; ....................
4569 (define_expand "seq"
4570 [(set (match_operand:SI 0 "register_operand")
4571 (eq:SI (match_dup 1)
4574 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4576 (define_insn "*seq_<mode>"
4577 [(set (match_operand:GPR 0 "register_operand" "=d")
4578 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4582 [(set_attr "type" "slt")
4583 (set_attr "mode" "<MODE>")])
4585 (define_insn "*seq_<mode>_mips16"
4586 [(set (match_operand:GPR 0 "register_operand" "=t")
4587 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4591 [(set_attr "type" "slt")
4592 (set_attr "mode" "<MODE>")])
4594 ;; "sne" uses sltu instructions in which the first operand is $0.
4595 ;; This isn't possible in mips16 code.
4597 (define_expand "sne"
4598 [(set (match_operand:SI 0 "register_operand")
4599 (ne:SI (match_dup 1)
4602 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
4604 (define_insn "*sne_<mode>"
4605 [(set (match_operand:GPR 0 "register_operand" "=d")
4606 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
4610 [(set_attr "type" "slt")
4611 (set_attr "mode" "<MODE>")])
4613 (define_expand "sgt"
4614 [(set (match_operand:SI 0 "register_operand")
4615 (gt:SI (match_dup 1)
4618 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
4620 (define_insn "*sgt_<mode>"
4621 [(set (match_operand:GPR 0 "register_operand" "=d")
4622 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4623 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4626 [(set_attr "type" "slt")
4627 (set_attr "mode" "<MODE>")])
4629 (define_insn "*sgt_<mode>_mips16"
4630 [(set (match_operand:GPR 0 "register_operand" "=t")
4631 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4632 (match_operand:GPR 2 "register_operand" "d")))]
4635 [(set_attr "type" "slt")
4636 (set_attr "mode" "<MODE>")])
4638 (define_expand "sge"
4639 [(set (match_operand:SI 0 "register_operand")
4640 (ge:SI (match_dup 1)
4643 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
4645 (define_insn "*sge_<mode>"
4646 [(set (match_operand:GPR 0 "register_operand" "=d")
4647 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
4651 [(set_attr "type" "slt")
4652 (set_attr "mode" "<MODE>")])
4654 (define_expand "slt"
4655 [(set (match_operand:SI 0 "register_operand")
4656 (lt:SI (match_dup 1)
4659 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
4661 (define_insn "*slt_<mode>"
4662 [(set (match_operand:GPR 0 "register_operand" "=d")
4663 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
4664 (match_operand:GPR 2 "arith_operand" "dI")))]
4667 [(set_attr "type" "slt")
4668 (set_attr "mode" "<MODE>")])
4670 (define_insn "*slt_<mode>_mips16"
4671 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4672 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
4673 (match_operand:GPR 2 "arith_operand" "d,I")))]
4676 [(set_attr "type" "slt")
4677 (set_attr "mode" "<MODE>")
4678 (set_attr_alternative "length"
4680 (if_then_else (match_operand 2 "m16_uimm8_1")
4684 (define_expand "sle"
4685 [(set (match_operand:SI 0 "register_operand")
4686 (le:SI (match_dup 1)
4689 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
4691 (define_insn "*sle_<mode>"
4692 [(set (match_operand:GPR 0 "register_operand" "=d")
4693 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4694 (match_operand:GPR 2 "sle_operand" "")))]
4697 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4698 return "slt\t%0,%1,%2";
4700 [(set_attr "type" "slt")
4701 (set_attr "mode" "<MODE>")])
4703 (define_insn "*sle_<mode>_mips16"
4704 [(set (match_operand:GPR 0 "register_operand" "=t")
4705 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4706 (match_operand:GPR 2 "sle_operand" "")))]
4709 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4710 return "slt\t%1,%2";
4712 [(set_attr "type" "slt")
4713 (set_attr "mode" "<MODE>")
4714 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4718 (define_expand "sgtu"
4719 [(set (match_operand:SI 0 "register_operand")
4720 (gtu:SI (match_dup 1)
4723 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
4725 (define_insn "*sgtu_<mode>"
4726 [(set (match_operand:GPR 0 "register_operand" "=d")
4727 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4728 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4731 [(set_attr "type" "slt")
4732 (set_attr "mode" "<MODE>")])
4734 (define_insn "*sgtu_<mode>_mips16"
4735 [(set (match_operand:GPR 0 "register_operand" "=t")
4736 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4737 (match_operand:GPR 2 "register_operand" "d")))]
4740 [(set_attr "type" "slt")
4741 (set_attr "mode" "<MODE>")])
4743 (define_expand "sgeu"
4744 [(set (match_operand:SI 0 "register_operand")
4745 (geu:SI (match_dup 1)
4748 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
4750 (define_insn "*sge_<mode>"
4751 [(set (match_operand:GPR 0 "register_operand" "=d")
4752 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
4756 [(set_attr "type" "slt")
4757 (set_attr "mode" "<MODE>")])
4759 (define_expand "sltu"
4760 [(set (match_operand:SI 0 "register_operand")
4761 (ltu:SI (match_dup 1)
4764 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
4766 (define_insn "*sltu_<mode>"
4767 [(set (match_operand:GPR 0 "register_operand" "=d")
4768 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
4769 (match_operand:GPR 2 "arith_operand" "dI")))]
4772 [(set_attr "type" "slt")
4773 (set_attr "mode" "<MODE>")])
4775 (define_insn "*sltu_<mode>_mips16"
4776 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4777 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
4778 (match_operand:GPR 2 "arith_operand" "d,I")))]
4781 [(set_attr "type" "slt")
4782 (set_attr "mode" "<MODE>")
4783 (set_attr_alternative "length"
4785 (if_then_else (match_operand 2 "m16_uimm8_1")
4789 (define_expand "sleu"
4790 [(set (match_operand:SI 0 "register_operand")
4791 (leu:SI (match_dup 1)
4794 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
4796 (define_insn "*sleu_<mode>"
4797 [(set (match_operand:GPR 0 "register_operand" "=d")
4798 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4799 (match_operand:GPR 2 "sleu_operand" "")))]
4802 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4803 return "sltu\t%0,%1,%2";
4805 [(set_attr "type" "slt")
4806 (set_attr "mode" "<MODE>")])
4808 (define_insn "*sleu_<mode>_mips16"
4809 [(set (match_operand:GPR 0 "register_operand" "=t")
4810 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4811 (match_operand:GPR 2 "sleu_operand" "")))]
4814 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4815 return "sltu\t%1,%2";
4817 [(set_attr "type" "slt")
4818 (set_attr "mode" "<MODE>")
4819 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4824 ;; ....................
4826 ;; FLOATING POINT COMPARISONS
4828 ;; ....................
4830 (define_insn "s<code>_<mode>"
4831 [(set (match_operand:CC 0 "register_operand" "=z")
4832 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4833 (match_operand:SCALARF 2 "register_operand" "f")))]
4835 "c.<fcond>.<fmt>\t%Z0%1,%2"
4836 [(set_attr "type" "fcmp")
4837 (set_attr "mode" "FPSW")])
4839 (define_insn "s<code>_<mode>"
4840 [(set (match_operand:CC 0 "register_operand" "=z")
4841 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4842 (match_operand:SCALARF 2 "register_operand" "f")))]
4844 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
4845 [(set_attr "type" "fcmp")
4846 (set_attr "mode" "FPSW")])
4849 ;; ....................
4851 ;; UNCONDITIONAL BRANCHES
4853 ;; ....................
4855 ;; Unconditional branches.
4859 (label_ref (match_operand 0 "" "")))]
4864 if (get_attr_length (insn) <= 8)
4865 return "%*b\t%l0%/";
4868 output_asm_insn (mips_output_load_label (), operands);
4869 return "%*jr\t%@%/%]";
4873 return "%*j\t%l0%/";
4875 [(set_attr "type" "jump")
4876 (set_attr "mode" "none")
4877 (set (attr "length")
4878 ;; We can't use `j' when emitting PIC. Emit a branch if it's
4879 ;; in range, otherwise load the address of the branch target into
4880 ;; $at and then jump to it.
4882 (ior (eq (symbol_ref "flag_pic") (const_int 0))
4883 (lt (abs (minus (match_dup 0)
4884 (plus (pc) (const_int 4))))
4885 (const_int 131072)))
4886 (const_int 4) (const_int 16)))])
4888 ;; We need a different insn for the mips16, because a mips16 branch
4889 ;; does not have a delay slot.
4893 (label_ref (match_operand 0 "" "")))]
4896 [(set_attr "type" "branch")
4897 (set_attr "mode" "none")
4898 (set_attr "length" "8")])
4900 (define_expand "indirect_jump"
4901 [(set (pc) (match_operand 0 "register_operand"))]
4904 operands[0] = force_reg (Pmode, operands[0]);
4905 if (Pmode == SImode)
4906 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
4908 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
4912 (define_insn "indirect_jump<mode>"
4913 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
4916 [(set_attr "type" "jump")
4917 (set_attr "mode" "none")])
4919 (define_expand "tablejump"
4921 (match_operand 0 "register_operand"))
4922 (use (label_ref (match_operand 1 "")))]
4926 operands[0] = expand_binop (Pmode, add_optab,
4927 convert_to_mode (Pmode, operands[0], false),
4928 gen_rtx_LABEL_REF (Pmode, operands[1]),
4930 else if (TARGET_GPWORD)
4931 operands[0] = expand_binop (Pmode, add_optab, operands[0],
4932 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
4934 if (Pmode == SImode)
4935 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
4937 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
4941 (define_insn "tablejump<mode>"
4943 (match_operand:P 0 "register_operand" "d"))
4944 (use (label_ref (match_operand 1 "" "")))]
4947 [(set_attr "type" "jump")
4948 (set_attr "mode" "none")])
4950 ;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well.
4951 ;; While it is possible to either pull it off the stack (in the
4952 ;; o32 case) or recalculate it given t9 and our target label,
4953 ;; it takes 3 or 4 insns to do so.
4955 (define_expand "builtin_setjmp_setup"
4956 [(use (match_operand 0 "register_operand"))]
4961 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
4962 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
4966 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
4967 ;; that older code did recalculate the gp from $25. Continue to jump through
4968 ;; $25 for compatibility (we lose nothing by doing so).
4970 (define_expand "builtin_longjmp"
4971 [(use (match_operand 0 "register_operand"))]
4974 /* The elements of the buffer are, in order: */
4975 int W = GET_MODE_SIZE (Pmode);
4976 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
4977 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
4978 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
4979 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
4980 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
4981 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
4982 The target is bound to be using $28 as the global pointer
4983 but the current function might not be. */
4984 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
4986 /* This bit is similar to expand_builtin_longjmp except that it
4987 restores $gp as well. */
4988 emit_move_insn (hard_frame_pointer_rtx, fp);
4989 emit_move_insn (pv, lab);
4990 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
4991 emit_move_insn (gp, gpv);
4992 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
4993 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4994 emit_insn (gen_rtx_USE (VOIDmode, gp));
4995 emit_indirect_jump (pv);
5000 ;; ....................
5002 ;; Function prologue/epilogue
5004 ;; ....................
5007 (define_expand "prologue"
5011 mips_expand_prologue ();
5015 ;; Block any insns from being moved before this point, since the
5016 ;; profiling call to mcount can use various registers that aren't
5017 ;; saved or used to pass arguments.
5019 (define_insn "blockage"
5020 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5023 [(set_attr "type" "unknown")
5024 (set_attr "mode" "none")
5025 (set_attr "length" "0")])
5027 (define_expand "epilogue"
5031 mips_expand_epilogue (false);
5035 (define_expand "sibcall_epilogue"
5039 mips_expand_epilogue (true);
5043 ;; Trivial return. Make it look like a normal return insn as that
5044 ;; allows jump optimizations to work better.
5046 (define_insn "return"
5048 "mips_can_use_return_insn ()"
5050 [(set_attr "type" "jump")
5051 (set_attr "mode" "none")])
5055 (define_insn "return_internal"
5057 (use (match_operand 0 "pmode_register_operand" ""))]
5060 [(set_attr "type" "jump")
5061 (set_attr "mode" "none")])
5063 ;; This is used in compiling the unwind routines.
5064 (define_expand "eh_return"
5065 [(use (match_operand 0 "general_operand"))]
5068 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
5070 if (GET_MODE (operands[0]) != gpr_mode)
5071 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
5073 emit_insn (gen_eh_set_lr_di (operands[0]));
5075 emit_insn (gen_eh_set_lr_si (operands[0]));
5080 ;; Clobber the return address on the stack. We can't expand this
5081 ;; until we know where it will be put in the stack frame.
5083 (define_insn "eh_set_lr_si"
5084 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5085 (clobber (match_scratch:SI 1 "=&d"))]
5089 (define_insn "eh_set_lr_di"
5090 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5091 (clobber (match_scratch:DI 1 "=&d"))]
5096 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5097 (clobber (match_scratch 1))]
5098 "reload_completed && !TARGET_DEBUG_D_MODE"
5101 mips_set_return_address (operands[0], operands[1]);
5105 (define_insn_and_split "exception_receiver"
5107 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
5108 "TARGET_ABICALLS && TARGET_OLDABI"
5110 "&& reload_completed"
5116 [(set_attr "type" "load")
5117 (set_attr "length" "12")])
5120 ;; ....................
5124 ;; ....................
5126 ;; Instructions to load a call address from the GOT. The address might
5127 ;; point to a function or to a lazy binding stub. In the latter case,
5128 ;; the stub will use the dynamic linker to resolve the function, which
5129 ;; in turn will change the GOT entry to point to the function's real
5132 ;; This means that every call, even pure and constant ones, can
5133 ;; potentially modify the GOT entry. And once a stub has been called,
5134 ;; we must not call it again.
5136 ;; We represent this restriction using an imaginary fixed register that
5137 ;; acts like a GOT version number. By making the register call-clobbered,
5138 ;; we tell the target-independent code that the address could be changed
5139 ;; by any call insn.
5140 (define_insn "load_call<mode>"
5141 [(set (match_operand:P 0 "register_operand" "=c")
5142 (unspec:P [(match_operand:P 1 "register_operand" "r")
5143 (match_operand:P 2 "immediate_operand" "")
5144 (reg:P FAKE_CALL_REGNO)]
5147 "<load>\t%0,%R2(%1)"
5148 [(set_attr "type" "load")
5149 (set_attr "mode" "<MODE>")
5150 (set_attr "length" "4")])
5152 ;; Sibling calls. All these patterns use jump instructions.
5154 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5155 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5156 ;; is defined in terms of call_insn_operand, the same is true of the
5159 ;; When we use an indirect jump, we need a register that will be
5160 ;; preserved by the epilogue. Since TARGET_ABICALLS forces us to
5161 ;; use $25 for this purpose -- and $25 is never clobbered by the
5162 ;; epilogue -- we might as well use it for !TARGET_ABICALLS as well.
5164 (define_expand "sibcall"
5165 [(parallel [(call (match_operand 0 "")
5166 (match_operand 1 ""))
5167 (use (match_operand 2 "")) ;; next_arg_reg
5168 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5171 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5175 (define_insn "sibcall_internal"
5176 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5177 (match_operand 1 "" ""))]
5178 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5179 { return MIPS_CALL ("j", operands, 0); }
5180 [(set_attr "type" "call")])
5182 (define_expand "sibcall_value"
5183 [(parallel [(set (match_operand 0 "")
5184 (call (match_operand 1 "")
5185 (match_operand 2 "")))
5186 (use (match_operand 3 ""))])] ;; next_arg_reg
5189 mips_expand_call (operands[0], XEXP (operands[1], 0),
5190 operands[2], operands[3], true);
5194 (define_insn "sibcall_value_internal"
5195 [(set (match_operand 0 "register_operand" "=df,df")
5196 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5197 (match_operand 2 "" "")))]
5198 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5199 { return MIPS_CALL ("j", operands, 1); }
5200 [(set_attr "type" "call")])
5202 (define_insn "sibcall_value_multiple_internal"
5203 [(set (match_operand 0 "register_operand" "=df,df")
5204 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5205 (match_operand 2 "" "")))
5206 (set (match_operand 3 "register_operand" "=df,df")
5207 (call (mem:SI (match_dup 1))
5209 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5210 { return MIPS_CALL ("j", operands, 1); }
5211 [(set_attr "type" "call")])
5213 (define_expand "call"
5214 [(parallel [(call (match_operand 0 "")
5215 (match_operand 1 ""))
5216 (use (match_operand 2 "")) ;; next_arg_reg
5217 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5220 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5224 ;; This instruction directly corresponds to an assembly-language "jal".
5225 ;; There are four cases:
5228 ;; Both symbolic and register destinations are OK. The pattern
5229 ;; always expands to a single mips instruction.
5231 ;; - -mabicalls/-mno-explicit-relocs:
5232 ;; Again, both symbolic and register destinations are OK.
5233 ;; The call is treated as a multi-instruction black box.
5235 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5236 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5239 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5240 ;; Only "jal $25" is allowed. The call is actually two instructions:
5241 ;; "jalr $25" followed by an insn to reload $gp.
5243 ;; In the last case, we can generate the individual instructions with
5244 ;; a define_split. There are several things to be wary of:
5246 ;; - We can't expose the load of $gp before reload. If we did,
5247 ;; it might get removed as dead, but reload can introduce new
5248 ;; uses of $gp by rematerializing constants.
5250 ;; - We shouldn't restore $gp after calls that never return.
5251 ;; It isn't valid to insert instructions between a noreturn
5252 ;; call and the following barrier.
5254 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5255 ;; instruction preserves $gp and so have no effect on its liveness.
5256 ;; But once we generate the separate insns, it becomes obvious that
5257 ;; $gp is not live on entry to the call.
5259 ;; ??? The operands[2] = insn check is a hack to make the original insn
5260 ;; available to the splitter.
5261 (define_insn_and_split "call_internal"
5262 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5263 (match_operand 1 "" ""))
5264 (clobber (reg:SI 31))]
5266 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5267 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5270 emit_call_insn (gen_call_split (operands[0], operands[1]));
5271 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5275 [(set_attr "jal" "indirect,direct")
5276 (set_attr "extended_mips16" "no,yes")])
5278 (define_insn "call_split"
5279 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5280 (match_operand 1 "" ""))
5281 (clobber (reg:SI 31))
5282 (clobber (reg:SI 28))]
5283 "TARGET_SPLIT_CALLS"
5284 { return MIPS_CALL ("jal", operands, 0); }
5285 [(set_attr "type" "call")])
5287 (define_expand "call_value"
5288 [(parallel [(set (match_operand 0 "")
5289 (call (match_operand 1 "")
5290 (match_operand 2 "")))
5291 (use (match_operand 3 ""))])] ;; next_arg_reg
5294 mips_expand_call (operands[0], XEXP (operands[1], 0),
5295 operands[2], operands[3], false);
5299 ;; See comment for call_internal.
5300 (define_insn_and_split "call_value_internal"
5301 [(set (match_operand 0 "register_operand" "=df,df")
5302 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5303 (match_operand 2 "" "")))
5304 (clobber (reg:SI 31))]
5306 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5307 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5310 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5312 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5316 [(set_attr "jal" "indirect,direct")
5317 (set_attr "extended_mips16" "no,yes")])
5319 (define_insn "call_value_split"
5320 [(set (match_operand 0 "register_operand" "=df")
5321 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5322 (match_operand 2 "" "")))
5323 (clobber (reg:SI 31))
5324 (clobber (reg:SI 28))]
5325 "TARGET_SPLIT_CALLS"
5326 { return MIPS_CALL ("jal", operands, 1); }
5327 [(set_attr "type" "call")])
5329 ;; See comment for call_internal.
5330 (define_insn_and_split "call_value_multiple_internal"
5331 [(set (match_operand 0 "register_operand" "=df,df")
5332 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5333 (match_operand 2 "" "")))
5334 (set (match_operand 3 "register_operand" "=df,df")
5335 (call (mem:SI (match_dup 1))
5337 (clobber (reg:SI 31))]
5339 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5340 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5343 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5344 operands[2], operands[3]));
5345 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5349 [(set_attr "jal" "indirect,direct")
5350 (set_attr "extended_mips16" "no,yes")])
5352 (define_insn "call_value_multiple_split"
5353 [(set (match_operand 0 "register_operand" "=df")
5354 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5355 (match_operand 2 "" "")))
5356 (set (match_operand 3 "register_operand" "=df")
5357 (call (mem:SI (match_dup 1))
5359 (clobber (reg:SI 31))
5360 (clobber (reg:SI 28))]
5361 "TARGET_SPLIT_CALLS"
5362 { return MIPS_CALL ("jal", operands, 1); }
5363 [(set_attr "type" "call")])
5365 ;; Call subroutine returning any type.
5367 (define_expand "untyped_call"
5368 [(parallel [(call (match_operand 0 "")
5370 (match_operand 1 "")
5371 (match_operand 2 "")])]
5376 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5378 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5380 rtx set = XVECEXP (operands[2], 0, i);
5381 emit_move_insn (SET_DEST (set), SET_SRC (set));
5384 emit_insn (gen_blockage ());
5389 ;; ....................
5393 ;; ....................
5397 (define_insn "prefetch"
5398 [(prefetch (match_operand:QI 0 "address_operand" "p")
5399 (match_operand 1 "const_int_operand" "n")
5400 (match_operand 2 "const_int_operand" "n"))]
5401 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5403 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5404 return "pref\t%1,%a0";
5406 [(set_attr "type" "prefetch")])
5408 (define_insn "*prefetch_indexed_<mode>"
5409 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5410 (match_operand:P 1 "register_operand" "d"))
5411 (match_operand 2 "const_int_operand" "n")
5412 (match_operand 3 "const_int_operand" "n"))]
5413 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5415 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5416 return "prefx\t%2,%1(%0)";
5418 [(set_attr "type" "prefetchx")])
5424 [(set_attr "type" "nop")
5425 (set_attr "mode" "none")])
5427 ;; Like nop, but commented out when outside a .set noreorder block.
5428 (define_insn "hazard_nop"
5437 [(set_attr "type" "nop")])
5439 ;; MIPS4 Conditional move instructions.
5441 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5442 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5444 (match_operator:MOVECC 4 "equality_operator"
5445 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5447 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5448 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5453 [(set_attr "type" "condmove")
5454 (set_attr "mode" "<GPR:MODE>")])
5456 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5457 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5458 (if_then_else:SCALARF
5459 (match_operator:MOVECC 4 "equality_operator"
5460 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5462 (match_operand:SCALARF 2 "register_operand" "f,0")
5463 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5466 mov%T4.<fmt>\t%0,%2,%1
5467 mov%t4.<fmt>\t%0,%3,%1"
5468 [(set_attr "type" "condmove")
5469 (set_attr "mode" "<SCALARF:MODE>")])
5471 ;; These are the main define_expand's used to make conditional moves.
5473 (define_expand "mov<mode>cc"
5474 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5475 (set (match_operand:GPR 0 "register_operand")
5476 (if_then_else:GPR (match_dup 5)
5477 (match_operand:GPR 2 "reg_or_0_operand")
5478 (match_operand:GPR 3 "reg_or_0_operand")))]
5481 gen_conditional_move (operands);
5485 (define_expand "mov<mode>cc"
5486 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5487 (set (match_operand:SCALARF 0 "register_operand")
5488 (if_then_else:SCALARF (match_dup 5)
5489 (match_operand:SCALARF 2 "register_operand")
5490 (match_operand:SCALARF 3 "register_operand")))]
5493 gen_conditional_move (operands);
5498 ;; ....................
5500 ;; mips16 inline constant tables
5502 ;; ....................
5505 (define_insn "consttable_int"
5506 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5507 (match_operand 1 "const_int_operand" "")]
5508 UNSPEC_CONSTTABLE_INT)]
5511 assemble_integer (operands[0], INTVAL (operands[1]),
5512 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5515 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5517 (define_insn "consttable_float"
5518 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5519 UNSPEC_CONSTTABLE_FLOAT)]
5524 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5525 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5526 assemble_real (d, GET_MODE (operands[0]),
5527 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5530 [(set (attr "length")
5531 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5533 (define_insn "align"
5534 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5537 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5540 [(match_operand 0 "small_data_pattern")]
5543 { operands[0] = mips_rewrite_small_data (operands[0]); })
5545 ; Thread-Local Storage
5547 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
5548 ; MIPS architecture defines this register, and no current
5549 ; implementation provides it; instead, any OS which supports TLS is
5550 ; expected to trap and emulate this instruction. rdhwr is part of the
5551 ; MIPS 32r2 specification, but we use it on any architecture because
5552 ; we expect it to be emulated. Use .set to force the assembler to
5555 (define_insn "tls_get_tp_<mode>"
5556 [(set (match_operand:P 0 "register_operand" "=v")
5557 (unspec:P [(const_int 0)]
5558 UNSPEC_TLS_GET_TP))]
5559 "HAVE_AS_TLS && !TARGET_MIPS16"
5560 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
5561 [(set_attr "type" "unknown")
5562 ; Since rdhwr always generates a trap for now, putting it in a delay
5563 ; slot would make the kernel's emulation of it much slower.
5564 (set_attr "can_delay" "no")
5565 (set_attr "mode" "<MODE>")])
5567 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
5569 (include "mips-ps-3d.md")
5571 ; The MIPS DSP Instructions.
5573 (include "mips-dsp.md")
5575 ; The MIPS DSP REV 2 Instructions.
5577 (include "mips-dspr2.md")