1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type
{
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF
,
140 MIPS_V2SF_FTYPE_V2SF_V2SF
,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT
,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF
,
143 MIPS_V2SF_FTYPE_SF_SF
,
144 MIPS_INT_FTYPE_V2SF_V2SF
,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF
,
146 MIPS_INT_FTYPE_SF_SF
,
147 MIPS_INT_FTYPE_DF_DF
,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI
,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI
,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI
,
160 MIPS_SI_FTYPE_PTR_SI
,
164 MIPS_SI_FTYPE_V2HI_V2HI
,
166 MIPS_SI_FTYPE_V4QI_V4QI
,
169 MIPS_V2HI_FTYPE_SI_SI
,
170 MIPS_V2HI_FTYPE_V2HI
,
171 MIPS_V2HI_FTYPE_V2HI_SI
,
172 MIPS_V2HI_FTYPE_V2HI_V2HI
,
173 MIPS_V2HI_FTYPE_V4QI
,
174 MIPS_V2HI_FTYPE_V4QI_V2HI
,
176 MIPS_V4QI_FTYPE_V2HI_V2HI
,
177 MIPS_V4QI_FTYPE_V4QI_SI
,
178 MIPS_V4QI_FTYPE_V4QI_V4QI
,
179 MIPS_VOID_FTYPE_SI_SI
,
180 MIPS_VOID_FTYPE_V2HI_V2HI
,
181 MIPS_VOID_FTYPE_V4QI_V4QI
,
183 /* For MIPS DSP REV 2 ASE. */
184 MIPS_V4QI_FTYPE_V4QI
,
185 MIPS_SI_FTYPE_SI_SI_SI
,
186 MIPS_DI_FTYPE_DI_USI_USI
,
188 MIPS_DI_FTYPE_USI_USI
,
189 MIPS_V2HI_FTYPE_SI_SI_SI
,
195 /* Specifies how a builtin function should be converted into rtl. */
196 enum mips_builtin_type
198 /* The builtin corresponds directly to an .md pattern. The return
199 value is mapped to operand 0 and the arguments are mapped to
200 operands 1 and above. */
203 /* The builtin corresponds directly to an .md pattern. There is no return
204 value and the arguments are mapped to operands 0 and above. */
205 MIPS_BUILTIN_DIRECT_NO_TARGET
,
207 /* The builtin corresponds to a comparison instruction followed by
208 a mips_cond_move_tf_ps pattern. The first two arguments are the
209 values to compare and the second two arguments are the vector
210 operands for the movt.ps or movf.ps instruction (in assembly order). */
214 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
215 of this instruction is the result of the comparison, which has mode
216 CCV2 or CCV4. The function arguments are mapped to operands 1 and
217 above. The function's return value is an SImode boolean that is
218 true under the following conditions:
220 MIPS_BUILTIN_CMP_ANY: one of the registers is true
221 MIPS_BUILTIN_CMP_ALL: all of the registers are true
222 MIPS_BUILTIN_CMP_LOWER: the first register is true
223 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
224 MIPS_BUILTIN_CMP_ANY
,
225 MIPS_BUILTIN_CMP_ALL
,
226 MIPS_BUILTIN_CMP_UPPER
,
227 MIPS_BUILTIN_CMP_LOWER
,
229 /* As above, but the instruction only sets a single $fcc register. */
230 MIPS_BUILTIN_CMP_SINGLE
,
232 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
233 MIPS_BUILTIN_BPOSGE32
236 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
237 #define MIPS_FP_CONDITIONS(MACRO) \
255 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
256 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
257 enum mips_fp_condition
{
258 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
261 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
262 #define STRINGIFY(X) #X
263 static const char *const mips_fp_conditions
[] = {
264 MIPS_FP_CONDITIONS (STRINGIFY
)
267 /* A function to save or store a register. The first argument is the
268 register and the second is the stack slot. */
269 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
271 struct mips16_constant
;
272 struct mips_arg_info
;
273 struct mips_address_info
;
274 struct mips_integer_op
;
277 static enum mips_symbol_type
mips_classify_symbol (rtx
);
278 static bool mips_valid_base_register_p (rtx
, enum machine_mode
, int);
279 static bool mips_symbolic_address_p (enum mips_symbol_type
, enum machine_mode
);
280 static bool mips_classify_address (struct mips_address_info
*, rtx
,
281 enum machine_mode
, int);
282 static bool mips_cannot_force_const_mem (rtx
);
283 static bool mips_use_blocks_for_constant_p (enum machine_mode
, rtx
);
284 static int mips_symbol_insns (enum mips_symbol_type
);
285 static bool mips16_unextended_reference_p (enum machine_mode mode
, rtx
, rtx
);
286 static rtx
mips_force_temporary (rtx
, rtx
);
287 static rtx
mips_unspec_offset_high (rtx
, rtx
, rtx
, enum mips_symbol_type
);
288 static rtx
mips_add_offset (rtx
, rtx
, HOST_WIDE_INT
);
289 static unsigned int mips_build_shift (struct mips_integer_op
*, HOST_WIDE_INT
);
290 static unsigned int mips_build_lower (struct mips_integer_op
*,
291 unsigned HOST_WIDE_INT
);
292 static unsigned int mips_build_integer (struct mips_integer_op
*,
293 unsigned HOST_WIDE_INT
);
294 static void mips_legitimize_const_move (enum machine_mode
, rtx
, rtx
);
295 static int m16_check_op (rtx
, int, int, int);
296 static bool mips_rtx_costs (rtx
, int, int, int *);
297 static int mips_address_cost (rtx
);
298 static void mips_emit_compare (enum rtx_code
*, rtx
*, rtx
*, bool);
299 static void mips_load_call_address (rtx
, rtx
, int);
300 static bool mips_function_ok_for_sibcall (tree
, tree
);
301 static void mips_block_move_straight (rtx
, rtx
, HOST_WIDE_INT
);
302 static void mips_adjust_block_mem (rtx
, HOST_WIDE_INT
, rtx
*, rtx
*);
303 static void mips_block_move_loop (rtx
, rtx
, HOST_WIDE_INT
);
304 static void mips_arg_info (const CUMULATIVE_ARGS
*, enum machine_mode
,
305 tree
, int, struct mips_arg_info
*);
306 static bool mips_get_unaligned_mem (rtx
*, unsigned int, int, rtx
*, rtx
*);
307 static void mips_set_architecture (const struct mips_cpu_info
*);
308 static void mips_set_tune (const struct mips_cpu_info
*);
309 static bool mips_handle_option (size_t, const char *, int);
310 static struct machine_function
*mips_init_machine_status (void);
311 static void print_operand_reloc (FILE *, rtx
, const char **);
312 static void mips_file_start (void);
313 static bool mips_rewrite_small_data_p (rtx
);
314 static int mips_small_data_pattern_1 (rtx
*, void *);
315 static int mips_rewrite_small_data_1 (rtx
*, void *);
316 static bool mips_function_has_gp_insn (void);
317 static unsigned int mips_global_pointer (void);
318 static bool mips_save_reg_p (unsigned int);
319 static void mips_save_restore_reg (enum machine_mode
, int, HOST_WIDE_INT
,
320 mips_save_restore_fn
);
321 static void mips_for_each_saved_reg (HOST_WIDE_INT
, mips_save_restore_fn
);
322 static void mips_output_cplocal (void);
323 static void mips_emit_loadgp (void);
324 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT
);
325 static void mips_set_frame_expr (rtx
);
326 static rtx
mips_frame_set (rtx
, rtx
);
327 static void mips_save_reg (rtx
, rtx
);
328 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT
);
329 static void mips_restore_reg (rtx
, rtx
);
330 static void mips_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
331 HOST_WIDE_INT
, tree
);
332 static int symbolic_expression_p (rtx
);
333 static section
*mips_select_rtx_section (enum machine_mode
, rtx
,
334 unsigned HOST_WIDE_INT
);
335 static section
*mips_function_rodata_section (tree
);
336 static bool mips_in_small_data_p (tree
);
337 static bool mips_use_anchors_for_symbol_p (rtx
);
338 static int mips_fpr_return_fields (tree
, tree
*);
339 static bool mips_return_in_msb (tree
);
340 static rtx
mips_return_fpr_pair (enum machine_mode mode
,
341 enum machine_mode mode1
, HOST_WIDE_INT
,
342 enum machine_mode mode2
, HOST_WIDE_INT
);
343 static rtx
mips16_gp_pseudo_reg (void);
344 static void mips16_fp_args (FILE *, int, int);
345 static void build_mips16_function_stub (FILE *);
346 static rtx
dump_constants_1 (enum machine_mode
, rtx
, rtx
);
347 static void dump_constants (struct mips16_constant
*, rtx
);
348 static int mips16_insn_length (rtx
);
349 static int mips16_rewrite_pool_refs (rtx
*, void *);
350 static void mips16_lay_out_constants (void);
351 static void mips_sim_reset (struct mips_sim
*);
352 static void mips_sim_init (struct mips_sim
*, state_t
);
353 static void mips_sim_next_cycle (struct mips_sim
*);
354 static void mips_sim_wait_reg (struct mips_sim
*, rtx
, rtx
);
355 static int mips_sim_wait_regs_2 (rtx
*, void *);
356 static void mips_sim_wait_regs_1 (rtx
*, void *);
357 static void mips_sim_wait_regs (struct mips_sim
*, rtx
);
358 static void mips_sim_wait_units (struct mips_sim
*, rtx
);
359 static void mips_sim_wait_insn (struct mips_sim
*, rtx
);
360 static void mips_sim_record_set (rtx
, rtx
, void *);
361 static void mips_sim_issue_insn (struct mips_sim
*, rtx
);
362 static void mips_sim_issue_nop (struct mips_sim
*);
363 static void mips_sim_finish_insn (struct mips_sim
*, rtx
);
364 static void vr4130_avoid_branch_rt_conflict (rtx
);
365 static void vr4130_align_insns (void);
366 static void mips_avoid_hazard (rtx
, rtx
, int *, rtx
*, rtx
);
367 static void mips_avoid_hazards (void);
368 static void mips_reorg (void);
369 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
370 static bool mips_matching_cpu_name_p (const char *, const char *);
371 static const struct mips_cpu_info
*mips_parse_cpu (const char *);
372 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
373 static bool mips_return_in_memory (tree
, tree
);
374 static bool mips_strict_argument_naming (CUMULATIVE_ARGS
*);
375 static void mips_macc_chains_record (rtx
);
376 static void mips_macc_chains_reorder (rtx
*, int);
377 static void vr4130_true_reg_dependence_p_1 (rtx
, rtx
, void *);
378 static bool vr4130_true_reg_dependence_p (rtx
);
379 static bool vr4130_swap_insns_p (rtx
, rtx
);
380 static void vr4130_reorder (rtx
*, int);
381 static void mips_promote_ready (rtx
*, int, int);
382 static int mips_sched_reorder (FILE *, int, rtx
*, int *, int);
383 static int mips_variable_issue (FILE *, int, rtx
, int);
384 static int mips_adjust_cost (rtx
, rtx
, rtx
, int);
385 static int mips_issue_rate (void);
386 static int mips_multipass_dfa_lookahead (void);
387 static void mips_init_libfuncs (void);
388 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
390 static tree
mips_build_builtin_va_list (void);
391 static tree
mips_gimplify_va_arg_expr (tree
, tree
, tree
*, tree
*);
392 static bool mips_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode mode
,
394 static bool mips_callee_copies (CUMULATIVE_ARGS
*, enum machine_mode mode
,
396 static int mips_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode mode
,
398 static bool mips_valid_pointer_mode (enum machine_mode
);
399 static bool mips_vector_mode_supported_p (enum machine_mode
);
400 static rtx
mips_prepare_builtin_arg (enum insn_code
, unsigned int, tree
, unsigned int);
401 static rtx
mips_prepare_builtin_target (enum insn_code
, unsigned int, rtx
);
402 static rtx
mips_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
403 static void mips_init_builtins (void);
404 static rtx
mips_expand_builtin_direct (enum insn_code
, rtx
, tree
, bool);
405 static rtx
mips_expand_builtin_movtf (enum mips_builtin_type
,
406 enum insn_code
, enum mips_fp_condition
,
408 static rtx
mips_expand_builtin_compare (enum mips_builtin_type
,
409 enum insn_code
, enum mips_fp_condition
,
411 static rtx
mips_expand_builtin_bposge (enum mips_builtin_type
, rtx
);
412 static void mips_encode_section_info (tree
, rtx
, int);
413 static void mips_extra_live_on_entry (bitmap
);
414 static int mips_mode_rep_extended (enum machine_mode
, enum machine_mode
);
416 /* Structure to be filled in by compute_frame_size with register
417 save masks, and offsets for the current function. */
419 struct mips_frame_info
GTY(())
421 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
422 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
423 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
424 HOST_WIDE_INT cprestore_size
; /* # bytes that the .cprestore slot takes up */
425 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
426 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
427 unsigned int mask
; /* mask of saved gp registers */
428 unsigned int fmask
; /* mask of saved fp registers */
429 HOST_WIDE_INT gp_save_offset
; /* offset from vfp to store gp registers */
430 HOST_WIDE_INT fp_save_offset
; /* offset from vfp to store fp registers */
431 HOST_WIDE_INT gp_sp_offset
; /* offset from new sp to store gp registers */
432 HOST_WIDE_INT fp_sp_offset
; /* offset from new sp to store fp registers */
433 bool initialized
; /* true if frame size already calculated */
434 int num_gp
; /* number of gp registers saved */
435 int num_fp
; /* number of fp registers saved */
438 struct machine_function
GTY(()) {
439 /* Pseudo-reg holding the value of $28 in a mips16 function which
440 refers to GP relative global variables. */
441 rtx mips16_gp_pseudo_rtx
;
443 /* The number of extra stack bytes taken up by register varargs.
444 This area is allocated by the callee at the very top of the frame. */
447 /* Current frame information, calculated by compute_frame_size. */
448 struct mips_frame_info frame
;
450 /* The register to use as the global pointer within this function. */
451 unsigned int global_pointer
;
453 /* True if mips_adjust_insn_length should ignore an instruction's
455 bool ignore_hazard_length_p
;
457 /* True if the whole function is suitable for .set noreorder and
459 bool all_noreorder_p
;
461 /* True if the function is known to have an instruction that needs $gp. */
465 /* Information about a single argument. */
468 /* True if the argument is passed in a floating-point register, or
469 would have been if we hadn't run out of registers. */
472 /* The number of words passed in registers, rounded up. */
473 unsigned int reg_words
;
475 /* For EABI, the offset of the first register from GP_ARG_FIRST or
476 FP_ARG_FIRST. For other ABIs, the offset of the first register from
477 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
478 comment for details).
480 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
482 unsigned int reg_offset
;
484 /* The number of words that must be passed on the stack, rounded up. */
485 unsigned int stack_words
;
487 /* The offset from the start of the stack overflow area of the argument's
488 first stack word. Only meaningful when STACK_WORDS is nonzero. */
489 unsigned int stack_offset
;
493 /* Information about an address described by mips_address_type.
499 REG is the base register and OFFSET is the constant offset.
502 REG is the register that contains the high part of the address,
503 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
504 is the type of OFFSET's symbol.
507 SYMBOL_TYPE is the type of symbol being referenced. */
509 struct mips_address_info
511 enum mips_address_type type
;
514 enum mips_symbol_type symbol_type
;
518 /* One stage in a constant building sequence. These sequences have
522 A = A CODE[1] VALUE[1]
523 A = A CODE[2] VALUE[2]
526 where A is an accumulator, each CODE[i] is a binary rtl operation
527 and each VALUE[i] is a constant integer. */
528 struct mips_integer_op
{
530 unsigned HOST_WIDE_INT value
;
534 /* The largest number of operations needed to load an integer constant.
535 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
536 When the lowest bit is clear, we can try, but reject a sequence with
537 an extra SLL at the end. */
538 #define MIPS_MAX_INTEGER_OPS 7
541 /* Global variables for machine-dependent things. */
543 /* Threshold for data being put into the small data/bss area, instead
544 of the normal data area. */
545 int mips_section_threshold
= -1;
547 /* Count the number of .file directives, so that .loc is up to date. */
548 int num_source_filenames
= 0;
550 /* Count the number of sdb related labels are generated (to find block
551 start and end boundaries). */
552 int sdb_label_count
= 0;
554 /* Next label # for each statement for Silicon Graphics IRIS systems. */
557 /* Name of the file containing the current function. */
558 const char *current_function_file
= "";
560 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
566 /* The next branch instruction is a branch likely, not branch normal. */
567 int mips_branch_likely
;
569 /* The operands passed to the last cmpMM expander. */
572 /* The target cpu for code generation. */
573 enum processor_type mips_arch
;
574 const struct mips_cpu_info
*mips_arch_info
;
576 /* The target cpu for optimization and scheduling. */
577 enum processor_type mips_tune
;
578 const struct mips_cpu_info
*mips_tune_info
;
580 /* Which instruction set architecture to use. */
583 /* Which ABI to use. */
584 int mips_abi
= MIPS_ABI_DEFAULT
;
586 /* Cost information to use. */
587 const struct mips_rtx_cost_data
*mips_cost
;
589 /* Whether we are generating mips16 hard float code. In mips16 mode
590 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
591 -msoft-float was not specified by the user, which means that we
592 should arrange to call mips32 hard floating point code. */
593 int mips16_hard_float
;
595 /* The architecture selected by -mipsN. */
596 static const struct mips_cpu_info
*mips_isa_info
;
598 /* If TRUE, we split addresses into their high and low parts in the RTL. */
599 int mips_split_addresses
;
601 /* Mode used for saving/restoring general purpose registers. */
602 static enum machine_mode gpr_mode
;
604 /* Array giving truth value on whether or not a given hard register
605 can support a given mode. */
606 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
608 /* List of all MIPS punctuation characters used by print_operand. */
609 char mips_print_operand_punct
[256];
611 /* Map GCC register number to debugger register number. */
612 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
614 /* A copy of the original flag_delayed_branch: see override_options. */
615 static int mips_flag_delayed_branch
;
617 static GTY (()) int mips_output_filename_first_time
= 1;
619 /* mips_split_p[X] is true if symbols of type X can be split by
620 mips_split_symbol(). */
621 bool mips_split_p
[NUM_SYMBOL_TYPES
];
623 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
624 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
625 if they are matched by a special .md file pattern. */
626 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
628 /* Likewise for HIGHs. */
629 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
631 /* Map hard register number to register class */
632 const enum reg_class mips_regno_to_class
[] =
634 LEA_REGS
, LEA_REGS
, M16_NA_REGS
, V1_REG
,
635 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
636 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
637 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
638 M16_NA_REGS
, M16_NA_REGS
, LEA_REGS
, LEA_REGS
,
639 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
640 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
641 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
642 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
643 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
644 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
645 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
646 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
647 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
648 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
649 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
650 HI_REG
, LO_REG
, NO_REGS
, ST_REGS
,
651 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
652 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
653 NO_REGS
, ALL_REGS
, ALL_REGS
, NO_REGS
,
654 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
655 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
656 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
657 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
658 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
659 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
660 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
661 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
662 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
663 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
664 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
665 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
666 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
667 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
668 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
669 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
670 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
671 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
672 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
673 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
674 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
675 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
676 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
677 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
678 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
679 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
680 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
683 /* Table of machine dependent attributes. */
684 const struct attribute_spec mips_attribute_table
[] =
686 { "long_call", 0, 0, false, true, true, NULL
},
687 { NULL
, 0, 0, false, false, false, NULL
}
690 /* A table describing all the processors gcc knows about. Names are
691 matched in the order listed. The first mention of an ISA level is
692 taken as the canonical name for that ISA.
694 To ease comparison, please keep this table in the same order as
695 gas's mips_cpu_info_table[]. */
696 const struct mips_cpu_info mips_cpu_info_table
[] = {
697 /* Entries for generic ISAs */
698 { "mips1", PROCESSOR_R3000
, 1 },
699 { "mips2", PROCESSOR_R6000
, 2 },
700 { "mips3", PROCESSOR_R4000
, 3 },
701 { "mips4", PROCESSOR_R8000
, 4 },
702 { "mips32", PROCESSOR_4KC
, 32 },
703 { "mips32r2", PROCESSOR_M4K
, 33 },
704 { "mips64", PROCESSOR_5KC
, 64 },
707 { "r3000", PROCESSOR_R3000
, 1 },
708 { "r2000", PROCESSOR_R3000
, 1 }, /* = r3000 */
709 { "r3900", PROCESSOR_R3900
, 1 },
712 { "r6000", PROCESSOR_R6000
, 2 },
715 { "r4000", PROCESSOR_R4000
, 3 },
716 { "vr4100", PROCESSOR_R4100
, 3 },
717 { "vr4111", PROCESSOR_R4111
, 3 },
718 { "vr4120", PROCESSOR_R4120
, 3 },
719 { "vr4130", PROCESSOR_R4130
, 3 },
720 { "vr4300", PROCESSOR_R4300
, 3 },
721 { "r4400", PROCESSOR_R4000
, 3 }, /* = r4000 */
722 { "r4600", PROCESSOR_R4600
, 3 },
723 { "orion", PROCESSOR_R4600
, 3 }, /* = r4600 */
724 { "r4650", PROCESSOR_R4650
, 3 },
727 { "r8000", PROCESSOR_R8000
, 4 },
728 { "vr5000", PROCESSOR_R5000
, 4 },
729 { "vr5400", PROCESSOR_R5400
, 4 },
730 { "vr5500", PROCESSOR_R5500
, 4 },
731 { "rm7000", PROCESSOR_R7000
, 4 },
732 { "rm9000", PROCESSOR_R9000
, 4 },
735 { "4kc", PROCESSOR_4KC
, 32 },
736 { "4km", PROCESSOR_4KC
, 32 }, /* = 4kc */
737 { "4kp", PROCESSOR_4KP
, 32 },
739 /* MIPS32 Release 2 */
740 { "m4k", PROCESSOR_M4K
, 33 },
741 { "4kec", PROCESSOR_4KC
, 33 },
742 { "4kem", PROCESSOR_4KC
, 33 },
743 { "4kep", PROCESSOR_4KP
, 33 },
744 { "24kc", PROCESSOR_24KC
, 33 }, /* 24K no FPU */
745 { "24kf", PROCESSOR_24KF
, 33 }, /* 24K 1:2 FPU */
746 { "24kx", PROCESSOR_24KX
, 33 }, /* 24K 1:1 FPU */
747 { "24kec", PROCESSOR_24KC
, 33 }, /* 24K with DSP */
748 { "24kef", PROCESSOR_24KF
, 33 },
749 { "24kex", PROCESSOR_24KX
, 33 },
750 { "34kc", PROCESSOR_24KC
, 33 }, /* 34K with MT/DSP */
751 { "34kf", PROCESSOR_24KF
, 33 },
752 { "34kx", PROCESSOR_24KX
, 33 },
755 { "5kc", PROCESSOR_5KC
, 64 },
756 { "5kf", PROCESSOR_5KF
, 64 },
757 { "20kc", PROCESSOR_20KC
, 64 },
758 { "sb1", PROCESSOR_SB1
, 64 },
759 { "sb1a", PROCESSOR_SB1A
, 64 },
760 { "sr71000", PROCESSOR_SR71000
, 64 },
766 /* Default costs. If these are used for a processor we should look
767 up the actual costs. */
768 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
769 COSTS_N_INSNS (7), /* fp_mult_sf */ \
770 COSTS_N_INSNS (8), /* fp_mult_df */ \
771 COSTS_N_INSNS (23), /* fp_div_sf */ \
772 COSTS_N_INSNS (36), /* fp_div_df */ \
773 COSTS_N_INSNS (10), /* int_mult_si */ \
774 COSTS_N_INSNS (10), /* int_mult_di */ \
775 COSTS_N_INSNS (69), /* int_div_si */ \
776 COSTS_N_INSNS (69), /* int_div_di */ \
777 2, /* branch_cost */ \
778 4 /* memory_latency */
780 /* Need to replace these with the costs of calling the appropriate
782 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
783 COSTS_N_INSNS (256), /* fp_mult_sf */ \
784 COSTS_N_INSNS (256), /* fp_mult_df */ \
785 COSTS_N_INSNS (256), /* fp_div_sf */ \
786 COSTS_N_INSNS (256) /* fp_div_df */
788 static struct mips_rtx_cost_data
const mips_rtx_cost_optimize_size
=
790 COSTS_N_INSNS (1), /* fp_add */
791 COSTS_N_INSNS (1), /* fp_mult_sf */
792 COSTS_N_INSNS (1), /* fp_mult_df */
793 COSTS_N_INSNS (1), /* fp_div_sf */
794 COSTS_N_INSNS (1), /* fp_div_df */
795 COSTS_N_INSNS (1), /* int_mult_si */
796 COSTS_N_INSNS (1), /* int_mult_di */
797 COSTS_N_INSNS (1), /* int_div_si */
798 COSTS_N_INSNS (1), /* int_div_di */
800 4 /* memory_latency */
803 static struct mips_rtx_cost_data
const mips_rtx_cost_data
[PROCESSOR_MAX
] =
806 COSTS_N_INSNS (2), /* fp_add */
807 COSTS_N_INSNS (4), /* fp_mult_sf */
808 COSTS_N_INSNS (5), /* fp_mult_df */
809 COSTS_N_INSNS (12), /* fp_div_sf */
810 COSTS_N_INSNS (19), /* fp_div_df */
811 COSTS_N_INSNS (12), /* int_mult_si */
812 COSTS_N_INSNS (12), /* int_mult_di */
813 COSTS_N_INSNS (35), /* int_div_si */
814 COSTS_N_INSNS (35), /* int_div_di */
816 4 /* memory_latency */
821 COSTS_N_INSNS (6), /* int_mult_si */
822 COSTS_N_INSNS (6), /* int_mult_di */
823 COSTS_N_INSNS (36), /* int_div_si */
824 COSTS_N_INSNS (36), /* int_div_di */
826 4 /* memory_latency */
830 COSTS_N_INSNS (36), /* int_mult_si */
831 COSTS_N_INSNS (36), /* int_mult_di */
832 COSTS_N_INSNS (37), /* int_div_si */
833 COSTS_N_INSNS (37), /* int_div_di */
835 4 /* memory_latency */
839 COSTS_N_INSNS (4), /* int_mult_si */
840 COSTS_N_INSNS (11), /* int_mult_di */
841 COSTS_N_INSNS (36), /* int_div_si */
842 COSTS_N_INSNS (68), /* int_div_di */
844 4 /* memory_latency */
847 COSTS_N_INSNS (4), /* fp_add */
848 COSTS_N_INSNS (4), /* fp_mult_sf */
849 COSTS_N_INSNS (5), /* fp_mult_df */
850 COSTS_N_INSNS (17), /* fp_div_sf */
851 COSTS_N_INSNS (32), /* fp_div_df */
852 COSTS_N_INSNS (4), /* int_mult_si */
853 COSTS_N_INSNS (11), /* int_mult_di */
854 COSTS_N_INSNS (36), /* int_div_si */
855 COSTS_N_INSNS (68), /* int_div_di */
857 4 /* memory_latency */
864 COSTS_N_INSNS (5), /* int_mult_si */
865 COSTS_N_INSNS (5), /* int_mult_di */
866 COSTS_N_INSNS (41), /* int_div_si */
867 COSTS_N_INSNS (41), /* int_div_di */
869 4 /* memory_latency */
872 COSTS_N_INSNS (8), /* fp_add */
873 COSTS_N_INSNS (8), /* fp_mult_sf */
874 COSTS_N_INSNS (10), /* fp_mult_df */
875 COSTS_N_INSNS (34), /* fp_div_sf */
876 COSTS_N_INSNS (64), /* fp_div_df */
877 COSTS_N_INSNS (5), /* int_mult_si */
878 COSTS_N_INSNS (5), /* int_mult_di */
879 COSTS_N_INSNS (41), /* int_div_si */
880 COSTS_N_INSNS (41), /* int_div_di */
882 4 /* memory_latency */
885 COSTS_N_INSNS (4), /* fp_add */
886 COSTS_N_INSNS (4), /* fp_mult_sf */
887 COSTS_N_INSNS (5), /* fp_mult_df */
888 COSTS_N_INSNS (17), /* fp_div_sf */
889 COSTS_N_INSNS (32), /* fp_div_df */
890 COSTS_N_INSNS (5), /* int_mult_si */
891 COSTS_N_INSNS (5), /* int_mult_di */
892 COSTS_N_INSNS (41), /* int_div_si */
893 COSTS_N_INSNS (41), /* int_div_di */
895 4 /* memory_latency */
901 COSTS_N_INSNS (2), /* fp_add */
902 COSTS_N_INSNS (4), /* fp_mult_sf */
903 COSTS_N_INSNS (5), /* fp_mult_df */
904 COSTS_N_INSNS (12), /* fp_div_sf */
905 COSTS_N_INSNS (19), /* fp_div_df */
906 COSTS_N_INSNS (2), /* int_mult_si */
907 COSTS_N_INSNS (2), /* int_mult_di */
908 COSTS_N_INSNS (35), /* int_div_si */
909 COSTS_N_INSNS (35), /* int_div_di */
911 4 /* memory_latency */
914 COSTS_N_INSNS (3), /* fp_add */
915 COSTS_N_INSNS (5), /* fp_mult_sf */
916 COSTS_N_INSNS (6), /* fp_mult_df */
917 COSTS_N_INSNS (15), /* fp_div_sf */
918 COSTS_N_INSNS (16), /* fp_div_df */
919 COSTS_N_INSNS (17), /* int_mult_si */
920 COSTS_N_INSNS (17), /* int_mult_di */
921 COSTS_N_INSNS (38), /* int_div_si */
922 COSTS_N_INSNS (38), /* int_div_di */
924 6 /* memory_latency */
927 COSTS_N_INSNS (6), /* fp_add */
928 COSTS_N_INSNS (7), /* fp_mult_sf */
929 COSTS_N_INSNS (8), /* fp_mult_df */
930 COSTS_N_INSNS (23), /* fp_div_sf */
931 COSTS_N_INSNS (36), /* fp_div_df */
932 COSTS_N_INSNS (10), /* int_mult_si */
933 COSTS_N_INSNS (10), /* int_mult_di */
934 COSTS_N_INSNS (69), /* int_div_si */
935 COSTS_N_INSNS (69), /* int_div_di */
937 6 /* memory_latency */
949 /* The only costs that appear to be updated here are
950 integer multiplication. */
952 COSTS_N_INSNS (4), /* int_mult_si */
953 COSTS_N_INSNS (6), /* int_mult_di */
954 COSTS_N_INSNS (69), /* int_div_si */
955 COSTS_N_INSNS (69), /* int_div_di */
957 4 /* memory_latency */
969 COSTS_N_INSNS (6), /* fp_add */
970 COSTS_N_INSNS (4), /* fp_mult_sf */
971 COSTS_N_INSNS (5), /* fp_mult_df */
972 COSTS_N_INSNS (23), /* fp_div_sf */
973 COSTS_N_INSNS (36), /* fp_div_df */
974 COSTS_N_INSNS (5), /* int_mult_si */
975 COSTS_N_INSNS (5), /* int_mult_di */
976 COSTS_N_INSNS (36), /* int_div_si */
977 COSTS_N_INSNS (36), /* int_div_di */
979 4 /* memory_latency */
982 COSTS_N_INSNS (6), /* fp_add */
983 COSTS_N_INSNS (5), /* fp_mult_sf */
984 COSTS_N_INSNS (6), /* fp_mult_df */
985 COSTS_N_INSNS (30), /* fp_div_sf */
986 COSTS_N_INSNS (59), /* fp_div_df */
987 COSTS_N_INSNS (3), /* int_mult_si */
988 COSTS_N_INSNS (4), /* int_mult_di */
989 COSTS_N_INSNS (42), /* int_div_si */
990 COSTS_N_INSNS (74), /* int_div_di */
992 4 /* memory_latency */
995 COSTS_N_INSNS (6), /* fp_add */
996 COSTS_N_INSNS (5), /* fp_mult_sf */
997 COSTS_N_INSNS (6), /* fp_mult_df */
998 COSTS_N_INSNS (30), /* fp_div_sf */
999 COSTS_N_INSNS (59), /* fp_div_df */
1000 COSTS_N_INSNS (5), /* int_mult_si */
1001 COSTS_N_INSNS (9), /* int_mult_di */
1002 COSTS_N_INSNS (42), /* int_div_si */
1003 COSTS_N_INSNS (74), /* int_div_di */
1004 1, /* branch_cost */
1005 4 /* memory_latency */
1008 /* The only costs that are changed here are
1009 integer multiplication. */
1010 COSTS_N_INSNS (6), /* fp_add */
1011 COSTS_N_INSNS (7), /* fp_mult_sf */
1012 COSTS_N_INSNS (8), /* fp_mult_df */
1013 COSTS_N_INSNS (23), /* fp_div_sf */
1014 COSTS_N_INSNS (36), /* fp_div_df */
1015 COSTS_N_INSNS (5), /* int_mult_si */
1016 COSTS_N_INSNS (9), /* int_mult_di */
1017 COSTS_N_INSNS (69), /* int_div_si */
1018 COSTS_N_INSNS (69), /* int_div_di */
1019 1, /* branch_cost */
1020 4 /* memory_latency */
1026 /* The only costs that are changed here are
1027 integer multiplication. */
1028 COSTS_N_INSNS (6), /* fp_add */
1029 COSTS_N_INSNS (7), /* fp_mult_sf */
1030 COSTS_N_INSNS (8), /* fp_mult_df */
1031 COSTS_N_INSNS (23), /* fp_div_sf */
1032 COSTS_N_INSNS (36), /* fp_div_df */
1033 COSTS_N_INSNS (3), /* int_mult_si */
1034 COSTS_N_INSNS (8), /* int_mult_di */
1035 COSTS_N_INSNS (69), /* int_div_si */
1036 COSTS_N_INSNS (69), /* int_div_di */
1037 1, /* branch_cost */
1038 4 /* memory_latency */
1041 /* These costs are the same as the SB-1A below. */
1042 COSTS_N_INSNS (4), /* fp_add */
1043 COSTS_N_INSNS (4), /* fp_mult_sf */
1044 COSTS_N_INSNS (4), /* fp_mult_df */
1045 COSTS_N_INSNS (24), /* fp_div_sf */
1046 COSTS_N_INSNS (32), /* fp_div_df */
1047 COSTS_N_INSNS (3), /* int_mult_si */
1048 COSTS_N_INSNS (4), /* int_mult_di */
1049 COSTS_N_INSNS (36), /* int_div_si */
1050 COSTS_N_INSNS (68), /* int_div_di */
1051 1, /* branch_cost */
1052 4 /* memory_latency */
1055 /* These costs are the same as the SB-1 above. */
1056 COSTS_N_INSNS (4), /* fp_add */
1057 COSTS_N_INSNS (4), /* fp_mult_sf */
1058 COSTS_N_INSNS (4), /* fp_mult_df */
1059 COSTS_N_INSNS (24), /* fp_div_sf */
1060 COSTS_N_INSNS (32), /* fp_div_df */
1061 COSTS_N_INSNS (3), /* int_mult_si */
1062 COSTS_N_INSNS (4), /* int_mult_di */
1063 COSTS_N_INSNS (36), /* int_div_si */
1064 COSTS_N_INSNS (68), /* int_div_di */
1065 1, /* branch_cost */
1066 4 /* memory_latency */
1074 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1075 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1076 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1079 /* Initialize the GCC target structure. */
1080 #undef TARGET_ASM_ALIGNED_HI_OP
1081 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1082 #undef TARGET_ASM_ALIGNED_SI_OP
1083 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1084 #undef TARGET_ASM_ALIGNED_DI_OP
1085 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1087 #undef TARGET_ASM_FUNCTION_PROLOGUE
1088 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1089 #undef TARGET_ASM_FUNCTION_EPILOGUE
1090 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1091 #undef TARGET_ASM_SELECT_RTX_SECTION
1092 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1093 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1094 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1096 #undef TARGET_SCHED_REORDER
1097 #define TARGET_SCHED_REORDER mips_sched_reorder
1098 #undef TARGET_SCHED_VARIABLE_ISSUE
1099 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1100 #undef TARGET_SCHED_ADJUST_COST
1101 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1102 #undef TARGET_SCHED_ISSUE_RATE
1103 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1104 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1105 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1106 mips_multipass_dfa_lookahead
1108 #undef TARGET_DEFAULT_TARGET_FLAGS
1109 #define TARGET_DEFAULT_TARGET_FLAGS \
1111 | TARGET_CPU_DEFAULT \
1112 | TARGET_ENDIAN_DEFAULT \
1113 | TARGET_FP_EXCEPTIONS_DEFAULT \
1114 | MASK_CHECK_ZERO_DIV \
1116 #undef TARGET_HANDLE_OPTION
1117 #define TARGET_HANDLE_OPTION mips_handle_option
1119 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1120 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1122 #undef TARGET_VALID_POINTER_MODE
1123 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1124 #undef TARGET_RTX_COSTS
1125 #define TARGET_RTX_COSTS mips_rtx_costs
1126 #undef TARGET_ADDRESS_COST
1127 #define TARGET_ADDRESS_COST mips_address_cost
1129 #undef TARGET_IN_SMALL_DATA_P
1130 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1132 #undef TARGET_MACHINE_DEPENDENT_REORG
1133 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1135 #undef TARGET_ASM_FILE_START
1136 #define TARGET_ASM_FILE_START mips_file_start
1137 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1138 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1140 #undef TARGET_INIT_LIBFUNCS
1141 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1143 #undef TARGET_BUILD_BUILTIN_VA_LIST
1144 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1145 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1146 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1148 #undef TARGET_PROMOTE_FUNCTION_ARGS
1149 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1150 #undef TARGET_PROMOTE_FUNCTION_RETURN
1151 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1152 #undef TARGET_PROMOTE_PROTOTYPES
1153 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1155 #undef TARGET_RETURN_IN_MEMORY
1156 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1157 #undef TARGET_RETURN_IN_MSB
1158 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1160 #undef TARGET_ASM_OUTPUT_MI_THUNK
1161 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1162 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1163 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1165 #undef TARGET_SETUP_INCOMING_VARARGS
1166 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1167 #undef TARGET_STRICT_ARGUMENT_NAMING
1168 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1169 #undef TARGET_MUST_PASS_IN_STACK
1170 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1171 #undef TARGET_PASS_BY_REFERENCE
1172 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1173 #undef TARGET_CALLEE_COPIES
1174 #define TARGET_CALLEE_COPIES mips_callee_copies
1175 #undef TARGET_ARG_PARTIAL_BYTES
1176 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1178 #undef TARGET_MODE_REP_EXTENDED
1179 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1181 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1182 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1184 #undef TARGET_INIT_BUILTINS
1185 #define TARGET_INIT_BUILTINS mips_init_builtins
1186 #undef TARGET_EXPAND_BUILTIN
1187 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1189 #undef TARGET_HAVE_TLS
1190 #define TARGET_HAVE_TLS HAVE_AS_TLS
1192 #undef TARGET_CANNOT_FORCE_CONST_MEM
1193 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1195 #undef TARGET_ENCODE_SECTION_INFO
1196 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1198 #undef TARGET_ATTRIBUTE_TABLE
1199 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1201 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1202 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1204 #undef TARGET_MIN_ANCHOR_OFFSET
1205 #define TARGET_MIN_ANCHOR_OFFSET -32768
1206 #undef TARGET_MAX_ANCHOR_OFFSET
1207 #define TARGET_MAX_ANCHOR_OFFSET 32767
1208 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1209 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1210 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1211 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1213 struct gcc_target targetm
= TARGET_INITIALIZER
;
1215 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1217 static enum mips_symbol_type
1218 mips_classify_symbol (rtx x
)
1222 if (GET_CODE (x
) == LABEL_REF
)
1225 return SYMBOL_CONSTANT_POOL
;
1226 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1227 return SYMBOL_GOT_LOCAL
;
1228 return SYMBOL_GENERAL
;
1231 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1233 if (SYMBOL_REF_TLS_MODEL (x
))
1236 if (CONSTANT_POOL_ADDRESS_P (x
))
1239 return SYMBOL_CONSTANT_POOL
;
1241 if (GET_MODE_SIZE (get_pool_mode (x
)) <= mips_section_threshold
)
1242 return SYMBOL_SMALL_DATA
;
1245 /* Do not use small-data accesses for weak symbols; they may end up
1247 if (SYMBOL_REF_SMALL_P (x
)
1248 && !SYMBOL_REF_WEAK (x
))
1249 return SYMBOL_SMALL_DATA
;
1251 if (TARGET_ABICALLS
)
1253 decl
= SYMBOL_REF_DECL (x
);
1256 if (!SYMBOL_REF_LOCAL_P (x
))
1257 return SYMBOL_GOT_GLOBAL
;
1261 /* Don't use GOT accesses for locally-binding symbols if
1262 TARGET_ABSOLUTE_ABICALLS. Otherwise, there are three
1265 - o32 PIC (either with or without explicit relocs)
1266 - n32/n64 PIC without explicit relocs
1267 - n32/n64 PIC with explicit relocs
1269 In the first case, both local and global accesses will use an
1270 R_MIPS_GOT16 relocation. We must correctly predict which of
1271 the two semantics (local or global) the assembler and linker
1272 will apply. The choice doesn't depend on the symbol's
1273 visibility, so we deliberately ignore decl_visibility and
1276 In the second case, the assembler will not use R_MIPS_GOT16
1277 relocations, but it chooses between local and global accesses
1278 in the same way as for o32 PIC.
1280 In the third case we have more freedom since both forms of
1281 access will work for any kind of symbol. However, there seems
1282 little point in doing things differently.
1284 Note that weakref symbols are not TREE_PUBLIC, but their
1285 targets are global or weak symbols. Relocations in the
1286 object file will be against the target symbol, so it's
1287 that symbol's binding that matters here. */
1289 && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
))
1290 && !(TARGET_ABSOLUTE_ABICALLS
&& targetm
.binds_local_p (decl
)))
1291 return SYMBOL_GOT_GLOBAL
;
1294 if (!TARGET_ABSOLUTE_ABICALLS
)
1295 return SYMBOL_GOT_LOCAL
;
1298 return SYMBOL_GENERAL
;
1301 /* Return true if X is a symbolic constant that can be calculated in
1302 the same way as a bare symbol. If it is, store the type of the
1303 symbol in *SYMBOL_TYPE. */
1306 mips_symbolic_constant_p (rtx x
, enum mips_symbol_type
*symbol_type
)
1310 split_const (x
, &x
, &offset
);
1311 if (UNSPEC_ADDRESS_P (x
))
1312 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1313 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1315 *symbol_type
= mips_classify_symbol (x
);
1316 if (*symbol_type
== SYMBOL_TLS
)
1322 if (offset
== const0_rtx
)
1325 /* Check whether a nonzero offset is valid for the underlying
1327 switch (*symbol_type
)
1329 case SYMBOL_GENERAL
:
1330 case SYMBOL_64_HIGH
:
1333 /* If the target has 64-bit pointers and the object file only
1334 supports 32-bit symbols, the values of those symbols will be
1335 sign-extended. In this case we can't allow an arbitrary offset
1336 in case the 32-bit value X + OFFSET has a different sign from X. */
1337 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1338 return offset_within_block_p (x
, INTVAL (offset
));
1340 /* In other cases the relocations can handle any offset. */
1343 case SYMBOL_CONSTANT_POOL
:
1344 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1345 In this case, we no longer have access to the underlying constant,
1346 but the original symbol-based access was known to be valid. */
1347 if (GET_CODE (x
) == LABEL_REF
)
1352 case SYMBOL_SMALL_DATA
:
1353 /* Make sure that the offset refers to something within the
1354 same object block. This should guarantee that the final
1355 PC- or GP-relative offset is within the 16-bit limit. */
1356 return offset_within_block_p (x
, INTVAL (offset
));
1358 case SYMBOL_GOT_LOCAL
:
1359 case SYMBOL_GOTOFF_PAGE
:
1360 /* The linker should provide enough local GOT entries for a
1361 16-bit offset. Larger offsets may lead to GOT overflow. */
1362 return SMALL_INT (offset
);
1364 case SYMBOL_GOT_GLOBAL
:
1365 case SYMBOL_GOTOFF_GLOBAL
:
1366 case SYMBOL_GOTOFF_CALL
:
1367 case SYMBOL_GOTOFF_LOADGP
:
1372 case SYMBOL_GOTTPREL
:
1380 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1383 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
, int strict
)
1385 if (!HARD_REGISTER_NUM_P (regno
))
1389 regno
= reg_renumber
[regno
];
1392 /* These fake registers will be eliminated to either the stack or
1393 hard frame pointer, both of which are usually valid base registers.
1394 Reload deals with the cases where the eliminated form isn't valid. */
1395 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
1398 /* In mips16 mode, the stack pointer can only address word and doubleword
1399 values, nothing smaller. There are two problems here:
1401 (a) Instantiating virtual registers can introduce new uses of the
1402 stack pointer. If these virtual registers are valid addresses,
1403 the stack pointer should be too.
1405 (b) Most uses of the stack pointer are not made explicit until
1406 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1407 We don't know until that stage whether we'll be eliminating to the
1408 stack pointer (which needs the restriction) or the hard frame
1409 pointer (which doesn't).
1411 All in all, it seems more consistent to only enforce this restriction
1412 during and after reload. */
1413 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
1414 return !strict
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
1416 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
1420 /* Return true if X is a valid base register for the given mode.
1421 Allow only hard registers if STRICT. */
1424 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, int strict
)
1426 if (!strict
&& GET_CODE (x
) == SUBREG
)
1430 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict
));
1434 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1435 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1438 mips_symbolic_address_p (enum mips_symbol_type symbol_type
,
1439 enum machine_mode mode
)
1441 switch (symbol_type
)
1443 case SYMBOL_GENERAL
:
1444 return !TARGET_MIPS16
;
1446 case SYMBOL_SMALL_DATA
:
1449 case SYMBOL_CONSTANT_POOL
:
1450 /* PC-relative addressing is only available for lw and ld. */
1451 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
1453 case SYMBOL_GOT_LOCAL
:
1456 case SYMBOL_GOT_GLOBAL
:
1457 /* The address will have to be loaded from the GOT first. */
1460 case SYMBOL_GOTOFF_PAGE
:
1461 case SYMBOL_GOTOFF_GLOBAL
:
1462 case SYMBOL_GOTOFF_CALL
:
1463 case SYMBOL_GOTOFF_LOADGP
:
1468 case SYMBOL_GOTTPREL
:
1470 case SYMBOL_64_HIGH
:
1479 /* Return true if X is a valid address for machine mode MODE. If it is,
1480 fill in INFO appropriately. STRICT is true if we should only accept
1481 hard base registers. */
1484 mips_classify_address (struct mips_address_info
*info
, rtx x
,
1485 enum machine_mode mode
, int strict
)
1487 switch (GET_CODE (x
))
1491 info
->type
= ADDRESS_REG
;
1493 info
->offset
= const0_rtx
;
1494 return mips_valid_base_register_p (info
->reg
, mode
, strict
);
1497 info
->type
= ADDRESS_REG
;
1498 info
->reg
= XEXP (x
, 0);
1499 info
->offset
= XEXP (x
, 1);
1500 return (mips_valid_base_register_p (info
->reg
, mode
, strict
)
1501 && const_arith_operand (info
->offset
, VOIDmode
));
1504 info
->type
= ADDRESS_LO_SUM
;
1505 info
->reg
= XEXP (x
, 0);
1506 info
->offset
= XEXP (x
, 1);
1507 return (mips_valid_base_register_p (info
->reg
, mode
, strict
)
1508 && mips_symbolic_constant_p (info
->offset
, &info
->symbol_type
)
1509 && mips_symbolic_address_p (info
->symbol_type
, mode
)
1510 && mips_lo_relocs
[info
->symbol_type
] != 0);
1513 /* Small-integer addresses don't occur very often, but they
1514 are legitimate if $0 is a valid base register. */
1515 info
->type
= ADDRESS_CONST_INT
;
1516 return !TARGET_MIPS16
&& SMALL_INT (x
);
1521 info
->type
= ADDRESS_SYMBOLIC
;
1522 return (mips_symbolic_constant_p (x
, &info
->symbol_type
)
1523 && mips_symbolic_address_p (info
->symbol_type
, mode
)
1524 && !mips_split_p
[info
->symbol_type
]);
1531 /* Return true if X is a thread-local symbol. */
1534 mips_tls_operand_p (rtx x
)
1536 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1539 /* Return true if X can not be forced into a constant pool. */
1542 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1544 return mips_tls_operand_p (*x
);
1547 /* Return true if X can not be forced into a constant pool. */
1550 mips_cannot_force_const_mem (rtx x
)
1556 /* As an optimization, reject constants that mips_legitimize_move
1559 Suppose we have a multi-instruction sequence that loads constant C
1560 into register R. If R does not get allocated a hard register, and
1561 R is used in an operand that allows both registers and memory
1562 references, reload will consider forcing C into memory and using
1563 one of the instruction's memory alternatives. Returning false
1564 here will force it to use an input reload instead. */
1565 if (GET_CODE (x
) == CONST_INT
)
1568 split_const (x
, &base
, &offset
);
1569 if (symbolic_operand (base
, VOIDmode
) && SMALL_INT (offset
))
1573 if (TARGET_HAVE_TLS
&& for_each_rtx (&x
, &mips_tls_symbol_ref_1
, 0))
1579 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1580 constant pools, but normal-mode code doesn't need to. */
1583 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1584 rtx x ATTRIBUTE_UNUSED
)
1586 return !TARGET_MIPS16
;
1589 /* Return the number of instructions needed to load a symbol of the
1590 given type into a register. If valid in an address, the same number
1591 of instructions are needed for loads and stores. Treat extended
1592 mips16 instructions as two instructions. */
1595 mips_symbol_insns (enum mips_symbol_type type
)
1599 case SYMBOL_GENERAL
:
1600 /* In mips16 code, general symbols must be fetched from the
1605 /* When using 64-bit symbols, we need 5 preparatory instructions,
1608 lui $at,%highest(symbol)
1609 daddiu $at,$at,%higher(symbol)
1611 daddiu $at,$at,%hi(symbol)
1614 The final address is then $at + %lo(symbol). With 32-bit
1615 symbols we just need a preparatory lui. */
1616 return (ABI_HAS_64BIT_SYMBOLS
? 6 : 2);
1618 case SYMBOL_SMALL_DATA
:
1621 case SYMBOL_CONSTANT_POOL
:
1622 /* This case is for mips16 only. Assume we'll need an
1623 extended instruction. */
1626 case SYMBOL_GOT_LOCAL
:
1627 case SYMBOL_GOT_GLOBAL
:
1628 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1629 the local/global classification is accurate. See override_options
1632 The worst cases are:
1634 (1) For local symbols when generating o32 or o64 code. The assembler
1640 ...and the final address will be $at + %lo(symbol).
1642 (2) For global symbols when -mxgot. The assembler will use:
1644 lui $at,%got_hi(symbol)
1647 ...and the final address will be $at + %got_lo(symbol). */
1650 case SYMBOL_GOTOFF_PAGE
:
1651 case SYMBOL_GOTOFF_GLOBAL
:
1652 case SYMBOL_GOTOFF_CALL
:
1653 case SYMBOL_GOTOFF_LOADGP
:
1654 case SYMBOL_64_HIGH
:
1660 case SYMBOL_GOTTPREL
:
1662 /* Check whether the offset is a 16- or 32-bit value. */
1663 return mips_split_p
[type
] ? 2 : 1;
1666 /* We don't treat a bare TLS symbol as a constant. */
1672 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1675 mips_stack_address_p (rtx x
, enum machine_mode mode
)
1677 struct mips_address_info addr
;
1679 return (mips_classify_address (&addr
, x
, mode
, false)
1680 && addr
.type
== ADDRESS_REG
1681 && addr
.reg
== stack_pointer_rtx
);
1684 /* Return true if a value at OFFSET bytes from BASE can be accessed
1685 using an unextended mips16 instruction. MODE is the mode of the
1688 Usually the offset in an unextended instruction is a 5-bit field.
1689 The offset is unsigned and shifted left once for HIs, twice
1690 for SIs, and so on. An exception is SImode accesses off the
1691 stack pointer, which have an 8-bit immediate field. */
1694 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
, rtx offset
)
1697 && GET_CODE (offset
) == CONST_INT
1698 && INTVAL (offset
) >= 0
1699 && (INTVAL (offset
) & (GET_MODE_SIZE (mode
) - 1)) == 0)
1701 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
1702 return INTVAL (offset
) < 256 * GET_MODE_SIZE (mode
);
1703 return INTVAL (offset
) < 32 * GET_MODE_SIZE (mode
);
1709 /* Return the number of instructions needed to load or store a value
1710 of mode MODE at X. Return 0 if X isn't valid for MODE.
1712 For mips16 code, count extended instructions as two instructions. */
1715 mips_address_insns (rtx x
, enum machine_mode mode
)
1717 struct mips_address_info addr
;
1720 if (mode
== BLKmode
)
1721 /* BLKmode is used for single unaligned loads and stores. */
1724 /* Each word of a multi-word value will be accessed individually. */
1725 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1727 if (mips_classify_address (&addr
, x
, mode
, false))
1732 && !mips16_unextended_reference_p (mode
, addr
.reg
, addr
.offset
))
1736 case ADDRESS_LO_SUM
:
1737 return (TARGET_MIPS16
? factor
* 2 : factor
);
1739 case ADDRESS_CONST_INT
:
1742 case ADDRESS_SYMBOLIC
:
1743 return factor
* mips_symbol_insns (addr
.symbol_type
);
1749 /* Likewise for constant X. */
1752 mips_const_insns (rtx x
)
1754 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
1755 enum mips_symbol_type symbol_type
;
1758 switch (GET_CODE (x
))
1762 || !mips_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
1763 || !mips_split_p
[symbol_type
])
1770 /* Unsigned 8-bit constants can be loaded using an unextended
1771 LI instruction. Unsigned 16-bit constants can be loaded
1772 using an extended LI. Negative constants must be loaded
1773 using LI and then negated. */
1774 return (INTVAL (x
) >= 0 && INTVAL (x
) < 256 ? 1
1775 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
1776 : INTVAL (x
) > -256 && INTVAL (x
) < 0 ? 2
1777 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
1780 return mips_build_integer (codes
, INTVAL (x
));
1784 return (!TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0);
1790 /* See if we can refer to X directly. */
1791 if (mips_symbolic_constant_p (x
, &symbol_type
))
1792 return mips_symbol_insns (symbol_type
);
1794 /* Otherwise try splitting the constant into a base and offset.
1795 16-bit offsets can be added using an extra addiu. Larger offsets
1796 must be calculated separately and then added to the base. */
1797 split_const (x
, &x
, &offset
);
1800 int n
= mips_const_insns (x
);
1803 if (SMALL_INT (offset
))
1806 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
1813 return mips_symbol_insns (mips_classify_symbol (x
));
1821 /* Return the number of instructions needed for memory reference X.
1822 Count extended mips16 instructions as two instructions. */
1825 mips_fetch_insns (rtx x
)
1827 gcc_assert (MEM_P (x
));
1828 return mips_address_insns (XEXP (x
, 0), GET_MODE (x
));
1832 /* Return the number of instructions needed for an integer division. */
1835 mips_idiv_insns (void)
1840 if (TARGET_CHECK_ZERO_DIV
)
1842 if (GENERATE_DIVIDE_TRAPS
)
1848 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
1853 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1854 returns a nonzero value if X is a legitimate address for a memory
1855 operand of the indicated MODE. STRICT is nonzero if this function
1856 is called during reload. */
1859 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1861 struct mips_address_info addr
;
1863 return mips_classify_address (&addr
, x
, mode
, strict
);
1867 /* Copy VALUE to a register and return that register. If new psuedos
1868 are allowed, copy it into a new register, otherwise use DEST. */
1871 mips_force_temporary (rtx dest
, rtx value
)
1873 if (!no_new_pseudos
)
1874 return force_reg (Pmode
, value
);
1877 emit_move_insn (copy_rtx (dest
), value
);
1883 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1884 and is used to load the high part into a register. */
1887 mips_split_symbol (rtx temp
, rtx addr
)
1892 high
= mips_force_temporary (temp
, gen_rtx_HIGH (Pmode
, copy_rtx (addr
)));
1893 else if (no_new_pseudos
)
1895 emit_insn (gen_load_const_gp (copy_rtx (temp
)));
1899 high
= mips16_gp_pseudo_reg ();
1900 return gen_rtx_LO_SUM (Pmode
, high
, addr
);
1904 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1905 type SYMBOL_TYPE. */
1908 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
1912 split_const (address
, &base
, &offset
);
1913 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
1914 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
1915 if (offset
!= const0_rtx
)
1916 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
1917 return gen_rtx_CONST (Pmode
, base
);
1921 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1922 high part to BASE and return the result. Just return BASE otherwise.
1923 TEMP is available as a temporary register if needed.
1925 The returned expression can be used as the first operand to a LO_SUM. */
1928 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
1929 enum mips_symbol_type symbol_type
)
1931 if (mips_split_p
[symbol_type
])
1933 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
1934 addr
= mips_force_temporary (temp
, addr
);
1935 return mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
1941 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1942 mips_force_temporary; it is only needed when OFFSET is not a
1946 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1948 if (!SMALL_OPERAND (offset
))
1953 /* Load the full offset into a register so that we can use
1954 an unextended instruction for the address itself. */
1955 high
= GEN_INT (offset
);
1960 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1961 high
= GEN_INT (CONST_HIGH_PART (offset
));
1962 offset
= CONST_LOW_PART (offset
);
1964 high
= mips_force_temporary (temp
, high
);
1965 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
1967 return plus_constant (reg
, offset
);
1970 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1971 referencing, and TYPE is the symbol type to use (either global
1972 dynamic or local dynamic). V0 is an RTX for the return value
1973 location. The entire insn sequence is returned. */
1975 static GTY(()) rtx mips_tls_symbol
;
1978 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
1980 rtx insn
, loc
, tga
, a0
;
1982 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
1984 if (!mips_tls_symbol
)
1985 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
1987 loc
= mips_unspec_address (sym
, type
);
1991 emit_insn (gen_rtx_SET (Pmode
, a0
,
1992 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
1993 tga
= gen_rtx_MEM (Pmode
, mips_tls_symbol
);
1994 insn
= emit_call_insn (gen_call_value (v0
, tga
, const0_rtx
, const0_rtx
));
1995 CONST_OR_PURE_CALL_P (insn
) = 1;
1996 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), v0
);
1997 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
1998 insn
= get_insns ();
2005 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2006 return value will be a valid address and move_operand (either a REG
2010 mips_legitimize_tls_address (rtx loc
)
2012 rtx dest
, insn
, v0
, v1
, tmp1
, tmp2
, eqv
;
2013 enum tls_model model
;
2015 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2016 v1
= gen_rtx_REG (Pmode
, GP_RETURN
+ 1);
2018 model
= SYMBOL_REF_TLS_MODEL (loc
);
2019 /* Only TARGET_ABICALLS code can have more than one module; other
2020 code must be be static and should not use a GOT. All TLS models
2021 reduce to local exec in this situation. */
2022 if (!TARGET_ABICALLS
)
2023 model
= TLS_MODEL_LOCAL_EXEC
;
2027 case TLS_MODEL_GLOBAL_DYNAMIC
:
2028 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2029 dest
= gen_reg_rtx (Pmode
);
2030 emit_libcall_block (insn
, dest
, v0
, loc
);
2033 case TLS_MODEL_LOCAL_DYNAMIC
:
2034 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2035 tmp1
= gen_reg_rtx (Pmode
);
2037 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2038 share the LDM result with other LD model accesses. */
2039 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2041 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2043 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2044 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
,
2045 mips_unspec_address (loc
, SYMBOL_DTPREL
));
2048 case TLS_MODEL_INITIAL_EXEC
:
2049 tmp1
= gen_reg_rtx (Pmode
);
2050 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2051 if (Pmode
== DImode
)
2053 emit_insn (gen_tls_get_tp_di (v1
));
2054 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2058 emit_insn (gen_tls_get_tp_si (v1
));
2059 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2061 dest
= gen_reg_rtx (Pmode
);
2062 emit_insn (gen_add3_insn (dest
, tmp1
, v1
));
2065 case TLS_MODEL_LOCAL_EXEC
:
2066 if (Pmode
== DImode
)
2067 emit_insn (gen_tls_get_tp_di (v1
));
2069 emit_insn (gen_tls_get_tp_si (v1
));
2071 tmp1
= mips_unspec_offset_high (NULL
, v1
, loc
, SYMBOL_TPREL
);
2072 dest
= gen_rtx_LO_SUM (Pmode
, tmp1
,
2073 mips_unspec_address (loc
, SYMBOL_TPREL
));
2083 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2084 be legitimized in a way that the generic machinery might not expect,
2085 put the new address in *XLOC and return true. MODE is the mode of
2086 the memory being accessed. */
2089 mips_legitimize_address (rtx
*xloc
, enum machine_mode mode
)
2091 enum mips_symbol_type symbol_type
;
2093 if (mips_tls_operand_p (*xloc
))
2095 *xloc
= mips_legitimize_tls_address (*xloc
);
2099 /* See if the address can split into a high part and a LO_SUM. */
2100 if (mips_symbolic_constant_p (*xloc
, &symbol_type
)
2101 && mips_symbolic_address_p (symbol_type
, mode
)
2102 && mips_split_p
[symbol_type
])
2104 *xloc
= mips_split_symbol (0, *xloc
);
2108 if (GET_CODE (*xloc
) == PLUS
&& GET_CODE (XEXP (*xloc
, 1)) == CONST_INT
)
2110 /* Handle REG + CONSTANT using mips_add_offset. */
2113 reg
= XEXP (*xloc
, 0);
2114 if (!mips_valid_base_register_p (reg
, mode
, 0))
2115 reg
= copy_to_mode_reg (Pmode
, reg
);
2116 *xloc
= mips_add_offset (0, reg
, INTVAL (XEXP (*xloc
, 1)));
2124 /* Subroutine of mips_build_integer (with the same interface).
2125 Assume that the final action in the sequence should be a left shift. */
2128 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
2130 unsigned int i
, shift
;
2132 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2133 since signed numbers are easier to load than unsigned ones. */
2135 while ((value
& 1) == 0)
2136 value
/= 2, shift
++;
2138 i
= mips_build_integer (codes
, value
);
2139 codes
[i
].code
= ASHIFT
;
2140 codes
[i
].value
= shift
;
2145 /* As for mips_build_shift, but assume that the final action will be
2146 an IOR or PLUS operation. */
2149 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
2151 unsigned HOST_WIDE_INT high
;
2154 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
2155 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
2157 /* The constant is too complex to load with a simple lui/ori pair
2158 so our goal is to clear as many trailing zeros as possible.
2159 In this case, we know bit 16 is set and that the low 16 bits
2160 form a negative number. If we subtract that number from VALUE,
2161 we will clear at least the lowest 17 bits, maybe more. */
2162 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
2163 codes
[i
].code
= PLUS
;
2164 codes
[i
].value
= CONST_LOW_PART (value
);
2168 i
= mips_build_integer (codes
, high
);
2169 codes
[i
].code
= IOR
;
2170 codes
[i
].value
= value
& 0xffff;
2176 /* Fill CODES with a sequence of rtl operations to load VALUE.
2177 Return the number of operations needed. */
2180 mips_build_integer (struct mips_integer_op
*codes
,
2181 unsigned HOST_WIDE_INT value
)
2183 if (SMALL_OPERAND (value
)
2184 || SMALL_OPERAND_UNSIGNED (value
)
2185 || LUI_OPERAND (value
))
2187 /* The value can be loaded with a single instruction. */
2188 codes
[0].code
= UNKNOWN
;
2189 codes
[0].value
= value
;
2192 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
2194 /* Either the constant is a simple LUI/ORI combination or its
2195 lowest bit is set. We don't want to shift in this case. */
2196 return mips_build_lower (codes
, value
);
2198 else if ((value
& 0xffff) == 0)
2200 /* The constant will need at least three actions. The lowest
2201 16 bits are clear, so the final action will be a shift. */
2202 return mips_build_shift (codes
, value
);
2206 /* The final action could be a shift, add or inclusive OR.
2207 Rather than use a complex condition to select the best
2208 approach, try both mips_build_shift and mips_build_lower
2209 and pick the one that gives the shortest sequence.
2210 Note that this case is only used once per constant. */
2211 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
2212 unsigned int cost
, alt_cost
;
2214 cost
= mips_build_shift (codes
, value
);
2215 alt_cost
= mips_build_lower (alt_codes
, value
);
2216 if (alt_cost
< cost
)
2218 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
2226 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2229 mips_move_integer (rtx dest
, rtx temp
, unsigned HOST_WIDE_INT value
)
2231 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2232 enum machine_mode mode
;
2233 unsigned int i
, cost
;
2236 mode
= GET_MODE (dest
);
2237 cost
= mips_build_integer (codes
, value
);
2239 /* Apply each binary operation to X. Invariant: X is a legitimate
2240 source operand for a SET pattern. */
2241 x
= GEN_INT (codes
[0].value
);
2242 for (i
= 1; i
< cost
; i
++)
2246 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
2250 x
= force_reg (mode
, x
);
2251 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
2254 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
2258 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2259 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2263 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
2267 /* Split moves of big integers into smaller pieces. */
2268 if (splittable_const_int_operand (src
, mode
))
2270 mips_move_integer (dest
, dest
, INTVAL (src
));
2274 /* Split moves of symbolic constants into high/low pairs. */
2275 if (splittable_symbolic_operand (src
, mode
))
2277 emit_insn (gen_rtx_SET (VOIDmode
, dest
, mips_split_symbol (dest
, src
)));
2281 if (mips_tls_operand_p (src
))
2283 emit_move_insn (dest
, mips_legitimize_tls_address (src
));
2287 /* If we have (const (plus symbol offset)), load the symbol first
2288 and then add in the offset. This is usually better than forcing
2289 the constant into memory, at least in non-mips16 code. */
2290 split_const (src
, &base
, &offset
);
2292 && offset
!= const0_rtx
2293 && (!no_new_pseudos
|| SMALL_INT (offset
)))
2295 base
= mips_force_temporary (dest
, base
);
2296 emit_move_insn (dest
, mips_add_offset (0, base
, INTVAL (offset
)));
2300 src
= force_const_mem (mode
, src
);
2302 /* When using explicit relocs, constant pool references are sometimes
2303 not legitimate addresses. */
2304 if (!memory_operand (src
, VOIDmode
))
2305 src
= replace_equiv_address (src
, mips_split_symbol (dest
, XEXP (src
, 0)));
2306 emit_move_insn (dest
, src
);
2310 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2311 sequence that is valid. */
2314 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
2316 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
2318 emit_move_insn (dest
, force_reg (mode
, src
));
2322 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2323 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
2324 && REG_P (src
) && MD_REG_P (REGNO (src
))
2325 && REG_P (dest
) && GP_REG_P (REGNO (dest
)))
2327 int other_regno
= REGNO (src
) == HI_REGNUM
? LO_REGNUM
: HI_REGNUM
;
2328 if (GET_MODE_SIZE (mode
) <= 4)
2329 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode
, REGNO (dest
)),
2330 gen_rtx_REG (SImode
, REGNO (src
)),
2331 gen_rtx_REG (SImode
, other_regno
)));
2333 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode
, REGNO (dest
)),
2334 gen_rtx_REG (DImode
, REGNO (src
)),
2335 gen_rtx_REG (DImode
, other_regno
)));
2339 /* We need to deal with constants that would be legitimate
2340 immediate_operands but not legitimate move_operands. */
2341 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
2343 mips_legitimize_const_move (mode
, dest
, src
);
2344 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
2350 /* We need a lot of little routines to check constant values on the
2351 mips16. These are used to figure out how long the instruction will
2352 be. It would be much better to do this using constraints, but
2353 there aren't nearly enough letters available. */
2356 m16_check_op (rtx op
, int low
, int high
, int mask
)
2358 return (GET_CODE (op
) == CONST_INT
2359 && INTVAL (op
) >= low
2360 && INTVAL (op
) <= high
2361 && (INTVAL (op
) & mask
) == 0);
2365 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2367 return m16_check_op (op
, 0x1, 0x8, 0);
2371 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2373 return m16_check_op (op
, - 0x8, 0x7, 0);
2377 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2379 return m16_check_op (op
, - 0x7, 0x8, 0);
2383 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2385 return m16_check_op (op
, - 0x10, 0xf, 0);
2389 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2391 return m16_check_op (op
, - 0xf, 0x10, 0);
2395 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2397 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
2401 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2403 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
2407 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2409 return m16_check_op (op
, - 0x80, 0x7f, 0);
2413 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2415 return m16_check_op (op
, - 0x7f, 0x80, 0);
2419 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2421 return m16_check_op (op
, 0x0, 0xff, 0);
2425 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2427 return m16_check_op (op
, - 0xff, 0x0, 0);
2431 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2433 return m16_check_op (op
, - 0x1, 0xfe, 0);
2437 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2439 return m16_check_op (op
, 0x0, 0xff << 2, 3);
2443 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2445 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
2449 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2451 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
2455 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2457 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
2461 mips_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2463 enum machine_mode mode
= GET_MODE (x
);
2464 bool float_mode_p
= FLOAT_MODE_P (mode
);
2471 /* A number between 1 and 8 inclusive is efficient for a shift.
2472 Otherwise, we will need an extended instruction. */
2473 if ((outer_code
) == ASHIFT
|| (outer_code
) == ASHIFTRT
2474 || (outer_code
) == LSHIFTRT
)
2476 if (INTVAL (x
) >= 1 && INTVAL (x
) <= 8)
2479 *total
= COSTS_N_INSNS (1);
2483 /* We can use cmpi for an xor with an unsigned 16-bit value. */
2484 if ((outer_code
) == XOR
2485 && INTVAL (x
) >= 0 && INTVAL (x
) < 0x10000)
2491 /* We may be able to use slt or sltu for a comparison with a
2492 signed 16-bit value. (The boundary conditions aren't quite
2493 right, but this is just a heuristic anyhow.) */
2494 if (((outer_code
) == LT
|| (outer_code
) == LE
2495 || (outer_code
) == GE
|| (outer_code
) == GT
2496 || (outer_code
) == LTU
|| (outer_code
) == LEU
2497 || (outer_code
) == GEU
|| (outer_code
) == GTU
)
2498 && INTVAL (x
) >= -0x8000 && INTVAL (x
) < 0x8000)
2504 /* Equality comparisons with 0 are cheap. */
2505 if (((outer_code
) == EQ
|| (outer_code
) == NE
)
2512 /* Constants in the range 0...255 can be loaded with an unextended
2513 instruction. They are therefore as cheap as a register move.
2515 Given the choice between "li R1,0...255" and "move R1,R2"
2516 (where R2 is a known constant), it is usually better to use "li",
2517 since we do not want to unnecessarily extend the lifetime
2519 if (outer_code
== SET
2521 && INTVAL (x
) < 256)
2529 /* These can be used anywhere. */
2534 /* Otherwise fall through to the handling below because
2535 we'll need to construct the constant. */
2541 if (LEGITIMATE_CONSTANT_P (x
))
2543 *total
= COSTS_N_INSNS (1);
2548 /* The value will need to be fetched from the constant pool. */
2549 *total
= CONSTANT_POOL_COST
;
2555 /* If the address is legitimate, return the number of
2556 instructions it needs, otherwise use the default handling. */
2557 int n
= mips_address_insns (XEXP (x
, 0), GET_MODE (x
));
2560 *total
= COSTS_N_INSNS (n
+ 1);
2567 *total
= COSTS_N_INSNS (6);
2571 *total
= COSTS_N_INSNS ((mode
== DImode
&& !TARGET_64BIT
) ? 2 : 1);
2577 if (mode
== DImode
&& !TARGET_64BIT
)
2579 *total
= COSTS_N_INSNS (2);
2587 if (mode
== DImode
&& !TARGET_64BIT
)
2589 *total
= COSTS_N_INSNS ((GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2597 *total
= COSTS_N_INSNS (1);
2599 *total
= COSTS_N_INSNS (4);
2603 *total
= COSTS_N_INSNS (1);
2610 *total
= mips_cost
->fp_add
;
2614 else if (mode
== DImode
&& !TARGET_64BIT
)
2616 *total
= COSTS_N_INSNS (4);
2622 if (mode
== DImode
&& !TARGET_64BIT
)
2624 *total
= COSTS_N_INSNS (4);
2631 *total
= mips_cost
->fp_mult_sf
;
2633 else if (mode
== DFmode
)
2634 *total
= mips_cost
->fp_mult_df
;
2636 else if (mode
== SImode
)
2637 *total
= mips_cost
->int_mult_si
;
2640 *total
= mips_cost
->int_mult_di
;
2649 *total
= mips_cost
->fp_div_sf
;
2651 *total
= mips_cost
->fp_div_df
;
2660 *total
= mips_cost
->int_div_di
;
2662 *total
= mips_cost
->int_div_si
;
2667 /* A sign extend from SImode to DImode in 64-bit mode is often
2668 zero instructions, because the result can often be used
2669 directly by another instruction; we'll call it one. */
2670 if (TARGET_64BIT
&& mode
== DImode
2671 && GET_MODE (XEXP (x
, 0)) == SImode
)
2672 *total
= COSTS_N_INSNS (1);
2674 *total
= COSTS_N_INSNS (2);
2678 if (TARGET_64BIT
&& mode
== DImode
2679 && GET_MODE (XEXP (x
, 0)) == SImode
)
2680 *total
= COSTS_N_INSNS (2);
2682 *total
= COSTS_N_INSNS (1);
2686 case UNSIGNED_FLOAT
:
2689 case FLOAT_TRUNCATE
:
2691 *total
= mips_cost
->fp_add
;
2699 /* Provide the costs of an addressing mode that contains ADDR.
2700 If ADDR is not a valid address, its cost is irrelevant. */
2703 mips_address_cost (rtx addr
)
2705 return mips_address_insns (addr
, SImode
);
2708 /* Return one word of double-word value OP, taking into account the fixed
2709 endianness of certain registers. HIGH_P is true to select the high part,
2710 false to select the low part. */
2713 mips_subword (rtx op
, int high_p
)
2716 enum machine_mode mode
;
2718 mode
= GET_MODE (op
);
2719 if (mode
== VOIDmode
)
2722 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
2723 byte
= UNITS_PER_WORD
;
2729 if (FP_REG_P (REGNO (op
)))
2730 return gen_rtx_REG (word_mode
, high_p
? REGNO (op
) + 1 : REGNO (op
));
2731 if (ACC_HI_REG_P (REGNO (op
)))
2732 return gen_rtx_REG (word_mode
, high_p
? REGNO (op
) : REGNO (op
) + 1);
2736 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
2738 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
2742 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2745 mips_split_64bit_move_p (rtx dest
, rtx src
)
2750 /* FP->FP moves can be done in a single instruction. */
2751 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
2754 /* Check for floating-point loads and stores. They can be done using
2755 ldc1 and sdc1 on MIPS II and above. */
2758 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
2760 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
2767 /* Split a 64-bit move from SRC to DEST assuming that
2768 mips_split_64bit_move_p holds.
2770 Moves into and out of FPRs cause some difficulty here. Such moves
2771 will always be DFmode, since paired FPRs are not allowed to store
2772 DImode values. The most natural representation would be two separate
2773 32-bit moves, such as:
2775 (set (reg:SI $f0) (mem:SI ...))
2776 (set (reg:SI $f1) (mem:SI ...))
2778 However, the second insn is invalid because odd-numbered FPRs are
2779 not allowed to store independent values. Use the patterns load_df_low,
2780 load_df_high and store_df_high instead. */
2783 mips_split_64bit_move (rtx dest
, rtx src
)
2785 if (FP_REG_RTX_P (dest
))
2787 /* Loading an FPR from memory or from GPRs. */
2790 dest
= gen_lowpart (DFmode
, dest
);
2791 emit_insn (gen_load_df_low (dest
, mips_subword (src
, 0)));
2792 emit_insn (gen_mthc1 (dest
, mips_subword (src
, 1),
2797 emit_insn (gen_load_df_low (copy_rtx (dest
),
2798 mips_subword (src
, 0)));
2799 emit_insn (gen_load_df_high (dest
, mips_subword (src
, 1),
2803 else if (FP_REG_RTX_P (src
))
2805 /* Storing an FPR into memory or GPRs. */
2808 src
= gen_lowpart (DFmode
, src
);
2809 emit_move_insn (mips_subword (dest
, 0), mips_subword (src
, 0));
2810 emit_insn (gen_mfhc1 (mips_subword (dest
, 1), src
));
2814 emit_move_insn (mips_subword (dest
, 0), mips_subword (src
, 0));
2815 emit_insn (gen_store_df_high (mips_subword (dest
, 1), src
));
2820 /* The operation can be split into two normal moves. Decide in
2821 which order to do them. */
2824 low_dest
= mips_subword (dest
, 0);
2825 if (REG_P (low_dest
)
2826 && reg_overlap_mentioned_p (low_dest
, src
))
2828 emit_move_insn (mips_subword (dest
, 1), mips_subword (src
, 1));
2829 emit_move_insn (low_dest
, mips_subword (src
, 0));
2833 emit_move_insn (low_dest
, mips_subword (src
, 0));
2834 emit_move_insn (mips_subword (dest
, 1), mips_subword (src
, 1));
2839 /* Return the appropriate instructions to move SRC into DEST. Assume
2840 that SRC is operand 1 and DEST is operand 0. */
2843 mips_output_move (rtx dest
, rtx src
)
2845 enum rtx_code dest_code
, src_code
;
2848 dest_code
= GET_CODE (dest
);
2849 src_code
= GET_CODE (src
);
2850 dbl_p
= (GET_MODE_SIZE (GET_MODE (dest
)) == 8);
2852 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
2855 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
2856 || (!TARGET_MIPS16
&& src
== CONST0_RTX (GET_MODE (dest
))))
2858 if (dest_code
== REG
)
2860 if (GP_REG_P (REGNO (dest
)))
2861 return "move\t%0,%z1";
2863 if (MD_REG_P (REGNO (dest
)))
2866 if (DSP_ACC_REG_P (REGNO (dest
)))
2868 static char retval
[] = "mt__\t%z1,%q0";
2869 retval
[2] = reg_names
[REGNO (dest
)][4];
2870 retval
[3] = reg_names
[REGNO (dest
)][5];
2874 if (FP_REG_P (REGNO (dest
)))
2875 return (dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2877 if (ALL_COP_REG_P (REGNO (dest
)))
2879 static char retval
[] = "dmtc_\t%z1,%0";
2881 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
2882 return (dbl_p
? retval
: retval
+ 1);
2885 if (dest_code
== MEM
)
2886 return (dbl_p
? "sd\t%z1,%0" : "sw\t%z1,%0");
2888 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
2890 if (src_code
== REG
)
2892 if (DSP_ACC_REG_P (REGNO (src
)))
2894 static char retval
[] = "mf__\t%0,%q1";
2895 retval
[2] = reg_names
[REGNO (src
)][4];
2896 retval
[3] = reg_names
[REGNO (src
)][5];
2900 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
2901 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2903 if (FP_REG_P (REGNO (src
)))
2904 return (dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2906 if (ALL_COP_REG_P (REGNO (src
)))
2908 static char retval
[] = "dmfc_\t%0,%1";
2910 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
2911 return (dbl_p
? retval
: retval
+ 1);
2915 if (src_code
== MEM
)
2916 return (dbl_p
? "ld\t%0,%1" : "lw\t%0,%1");
2918 if (src_code
== CONST_INT
)
2920 /* Don't use the X format, because that will give out of
2921 range numbers for 64-bit hosts and 32-bit targets. */
2923 return "li\t%0,%1\t\t\t# %X1";
2925 if (INTVAL (src
) >= 0 && INTVAL (src
) <= 0xffff)
2928 if (INTVAL (src
) < 0 && INTVAL (src
) >= -0xffff)
2932 if (src_code
== HIGH
)
2933 return "lui\t%0,%h1";
2935 if (CONST_GP_P (src
))
2936 return "move\t%0,%1";
2938 if (symbolic_operand (src
, VOIDmode
))
2939 return (dbl_p
? "dla\t%0,%1" : "la\t%0,%1");
2941 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
2943 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2945 if (GET_MODE (dest
) == V2SFmode
)
2946 return "mov.ps\t%0,%1";
2948 return (dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2951 if (dest_code
== MEM
)
2952 return (dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0");
2954 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
2956 if (src_code
== MEM
)
2957 return (dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2959 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
2961 static char retval
[] = "l_c_\t%0,%1";
2963 retval
[1] = (dbl_p
? 'd' : 'w');
2964 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
2967 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
2969 static char retval
[] = "s_c_\t%1,%0";
2971 retval
[1] = (dbl_p
? 'd' : 'w');
2972 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
2978 /* Restore $gp from its save slot. Valid only when using o32 or
2982 mips_restore_gp (void)
2986 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
);
2988 address
= mips_add_offset (pic_offset_table_rtx
,
2989 frame_pointer_needed
2990 ? hard_frame_pointer_rtx
2991 : stack_pointer_rtx
,
2992 current_function_outgoing_args_size
);
2993 slot
= gen_rtx_MEM (Pmode
, address
);
2995 emit_move_insn (pic_offset_table_rtx
, slot
);
2996 if (!TARGET_EXPLICIT_RELOCS
)
2997 emit_insn (gen_blockage ());
3000 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3003 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
3005 emit_insn (gen_rtx_SET (VOIDmode
, target
,
3006 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
3009 /* Return true if CMP1 is a suitable second operand for relational
3010 operator CODE. See also the *sCC patterns in mips.md. */
3013 mips_relational_operand_ok_p (enum rtx_code code
, rtx cmp1
)
3019 return reg_or_0_operand (cmp1
, VOIDmode
);
3023 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
3027 return arith_operand (cmp1
, VOIDmode
);
3030 return sle_operand (cmp1
, VOIDmode
);
3033 return sleu_operand (cmp1
, VOIDmode
);
3040 /* Canonicalize LE or LEU comparisons into LT comparisons when
3041 possible to avoid extra instructions or inverting the
3045 mips_canonicalize_comparison (enum rtx_code
*code
, rtx
*cmp1
,
3046 enum machine_mode mode
)
3048 HOST_WIDE_INT original
, plus_one
;
3050 if (GET_CODE (*cmp1
) != CONST_INT
)
3053 original
= INTVAL (*cmp1
);
3054 plus_one
= trunc_int_for_mode ((unsigned HOST_WIDE_INT
) original
+ 1, mode
);
3059 if (original
< plus_one
)
3062 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3071 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3084 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3085 result in TARGET. CMP0 and TARGET are register_operands that have
3086 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3087 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3090 mips_emit_int_relational (enum rtx_code code
, bool *invert_ptr
,
3091 rtx target
, rtx cmp0
, rtx cmp1
)
3093 /* First see if there is a MIPS instruction that can do this operation
3094 with CMP1 in its current form. If not, try to canonicalize the
3095 comparison to LT. If that fails, try doing the same for the
3096 inverse operation. If that also fails, force CMP1 into a register
3098 if (mips_relational_operand_ok_p (code
, cmp1
))
3099 mips_emit_binary (code
, target
, cmp0
, cmp1
);
3100 else if (mips_canonicalize_comparison (&code
, &cmp1
, GET_MODE (target
)))
3101 mips_emit_binary (code
, target
, cmp0
, cmp1
);
3104 enum rtx_code inv_code
= reverse_condition (code
);
3105 if (!mips_relational_operand_ok_p (inv_code
, cmp1
))
3107 cmp1
= force_reg (GET_MODE (cmp0
), cmp1
);
3108 mips_emit_int_relational (code
, invert_ptr
, target
, cmp0
, cmp1
);
3110 else if (invert_ptr
== 0)
3112 rtx inv_target
= gen_reg_rtx (GET_MODE (target
));
3113 mips_emit_binary (inv_code
, inv_target
, cmp0
, cmp1
);
3114 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
3118 *invert_ptr
= !*invert_ptr
;
3119 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
3124 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3125 The register will have the same mode as CMP0. */
3128 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
3130 if (cmp1
== const0_rtx
)
3133 if (uns_arith_operand (cmp1
, VOIDmode
))
3134 return expand_binop (GET_MODE (cmp0
), xor_optab
,
3135 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3137 return expand_binop (GET_MODE (cmp0
), sub_optab
,
3138 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3141 /* Convert *CODE into a code that can be used in a floating-point
3142 scc instruction (c.<cond>.<fmt>). Return true if the values of
3143 the condition code registers will be inverted, with 0 indicating
3144 that the condition holds. */
3147 mips_reverse_fp_cond_p (enum rtx_code
*code
)
3154 *code
= reverse_condition_maybe_unordered (*code
);
3162 /* Convert a comparison into something that can be used in a branch or
3163 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3164 being compared and *CODE is the code used to compare them.
3166 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3167 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3168 otherwise any standard branch condition can be used. The standard branch
3171 - EQ/NE between two registers.
3172 - any comparison between a register and zero. */
3175 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
3177 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) == MODE_INT
)
3179 if (!need_eq_ne_p
&& cmp_operands
[1] == const0_rtx
)
3181 *op0
= cmp_operands
[0];
3182 *op1
= cmp_operands
[1];
3184 else if (*code
== EQ
|| *code
== NE
)
3188 *op0
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3193 *op0
= cmp_operands
[0];
3194 *op1
= force_reg (GET_MODE (*op0
), cmp_operands
[1]);
3199 /* The comparison needs a separate scc instruction. Store the
3200 result of the scc in *OP0 and compare it against zero. */
3201 bool invert
= false;
3202 *op0
= gen_reg_rtx (GET_MODE (cmp_operands
[0]));
3204 mips_emit_int_relational (*code
, &invert
, *op0
,
3205 cmp_operands
[0], cmp_operands
[1]);
3206 *code
= (invert
? EQ
: NE
);
3211 enum rtx_code cmp_code
;
3213 /* Floating-point tests use a separate c.cond.fmt comparison to
3214 set a condition code register. The branch or conditional move
3215 will then compare that register against zero.
3217 Set CMP_CODE to the code of the comparison instruction and
3218 *CODE to the code that the branch or move should use. */
3220 *code
= mips_reverse_fp_cond_p (&cmp_code
) ? EQ
: NE
;
3222 ? gen_reg_rtx (CCmode
)
3223 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
3225 mips_emit_binary (cmp_code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
3229 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3230 Store the result in TARGET and return true if successful.
3232 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3235 mips_emit_scc (enum rtx_code code
, rtx target
)
3237 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) != MODE_INT
)
3240 target
= gen_lowpart (GET_MODE (cmp_operands
[0]), target
);
3241 if (code
== EQ
|| code
== NE
)
3243 rtx zie
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3244 mips_emit_binary (code
, target
, zie
, const0_rtx
);
3247 mips_emit_int_relational (code
, 0, target
,
3248 cmp_operands
[0], cmp_operands
[1]);
3252 /* Emit the common code for doing conditional branches.
3253 operand[0] is the label to jump to.
3254 The comparison operands are saved away by cmp{si,di,sf,df}. */
3257 gen_conditional_branch (rtx
*operands
, enum rtx_code code
)
3259 rtx op0
, op1
, condition
;
3261 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
3262 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3263 emit_jump_insn (gen_condjump (condition
, operands
[0]));
3268 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3269 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3272 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
3273 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
3278 reversed_p
= mips_reverse_fp_cond_p (&cond
);
3279 cmp_result
= gen_reg_rtx (CCV2mode
);
3280 emit_insn (gen_scc_ps (cmp_result
,
3281 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
3283 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
3286 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
3290 /* Emit the common code for conditional moves. OPERANDS is the array
3291 of operands passed to the conditional move define_expand. */
3294 gen_conditional_move (rtx
*operands
)
3299 code
= GET_CODE (operands
[1]);
3300 mips_emit_compare (&code
, &op0
, &op1
, true);
3301 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
3302 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
3303 gen_rtx_fmt_ee (code
,
3306 operands
[2], operands
[3])));
3309 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3310 the conditional_trap expander. */
3313 mips_gen_conditional_trap (rtx
*operands
)
3316 enum rtx_code cmp_code
= GET_CODE (operands
[0]);
3317 enum machine_mode mode
= GET_MODE (cmp_operands
[0]);
3319 /* MIPS conditional trap machine instructions don't have GT or LE
3320 flavors, so we must invert the comparison and convert to LT and
3321 GE, respectively. */
3324 case GT
: cmp_code
= LT
; break;
3325 case LE
: cmp_code
= GE
; break;
3326 case GTU
: cmp_code
= LTU
; break;
3327 case LEU
: cmp_code
= GEU
; break;
3330 if (cmp_code
== GET_CODE (operands
[0]))
3332 op0
= cmp_operands
[0];
3333 op1
= cmp_operands
[1];
3337 op0
= cmp_operands
[1];
3338 op1
= cmp_operands
[0];
3340 op0
= force_reg (mode
, op0
);
3341 if (!arith_operand (op1
, mode
))
3342 op1
= force_reg (mode
, op1
);
3344 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
3345 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
),
3349 /* Load function address ADDR into register DEST. SIBCALL_P is true
3350 if the address is needed for a sibling call. */
3353 mips_load_call_address (rtx dest
, rtx addr
, int sibcall_p
)
3355 /* If we're generating PIC, and this call is to a global function,
3356 try to allow its address to be resolved lazily. This isn't
3357 possible for NewABI sibcalls since the value of $gp on entry
3358 to the stub would be our caller's gp, not ours. */
3359 if (TARGET_EXPLICIT_RELOCS
3360 && !(sibcall_p
&& TARGET_NEWABI
)
3361 && global_got_operand (addr
, VOIDmode
))
3363 rtx high
, lo_sum_symbol
;
3365 high
= mips_unspec_offset_high (dest
, pic_offset_table_rtx
,
3366 addr
, SYMBOL_GOTOFF_CALL
);
3367 lo_sum_symbol
= mips_unspec_address (addr
, SYMBOL_GOTOFF_CALL
);
3368 if (Pmode
== SImode
)
3369 emit_insn (gen_load_callsi (dest
, high
, lo_sum_symbol
));
3371 emit_insn (gen_load_calldi (dest
, high
, lo_sum_symbol
));
3374 emit_move_insn (dest
, addr
);
3378 /* Expand a call or call_value instruction. RESULT is where the
3379 result will go (null for calls), ADDR is the address of the
3380 function, ARGS_SIZE is the size of the arguments and AUX is
3381 the value passed to us by mips_function_arg. SIBCALL_P is true
3382 if we are expanding a sibling call, false if we're expanding
3386 mips_expand_call (rtx result
, rtx addr
, rtx args_size
, rtx aux
, int sibcall_p
)
3388 rtx orig_addr
, pattern
, insn
;
3391 if (!call_insn_operand (addr
, VOIDmode
))
3393 addr
= gen_reg_rtx (Pmode
);
3394 mips_load_call_address (addr
, orig_addr
, sibcall_p
);
3398 && mips16_hard_float
3399 && build_mips16_call_stub (result
, addr
, args_size
,
3400 aux
== 0 ? 0 : (int) GET_MODE (aux
)))
3404 pattern
= (sibcall_p
3405 ? gen_sibcall_internal (addr
, args_size
)
3406 : gen_call_internal (addr
, args_size
));
3407 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
3411 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
3412 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
3415 ? gen_sibcall_value_multiple_internal (reg1
, addr
, args_size
, reg2
)
3416 : gen_call_value_multiple_internal (reg1
, addr
, args_size
, reg2
));
3419 pattern
= (sibcall_p
3420 ? gen_sibcall_value_internal (result
, addr
, args_size
)
3421 : gen_call_value_internal (result
, addr
, args_size
));
3423 insn
= emit_call_insn (pattern
);
3425 /* Lazy-binding stubs require $gp to be valid on entry. */
3426 if (global_got_operand (orig_addr
, VOIDmode
))
3427 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3431 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3434 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
3435 tree exp ATTRIBUTE_UNUSED
)
3437 return TARGET_SIBCALLS
;
3440 /* Emit code to move general operand SRC into condition-code
3441 register DEST. SCRATCH is a scratch TFmode float register.
3448 where FP1 and FP2 are single-precision float registers
3449 taken from SCRATCH. */
3452 mips_emit_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
3456 /* Change the source to SFmode. */
3458 src
= adjust_address (src
, SFmode
, 0);
3459 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
3460 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
3462 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
3463 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + FP_INC
);
3465 emit_move_insn (copy_rtx (fp1
), src
);
3466 emit_move_insn (copy_rtx (fp2
), CONST0_RTX (SFmode
));
3467 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
3470 /* Emit code to change the current function's return address to
3471 ADDRESS. SCRATCH is available as a scratch register, if needed.
3472 ADDRESS and SCRATCH are both word-mode GPRs. */
3475 mips_set_return_address (rtx address
, rtx scratch
)
3479 compute_frame_size (get_frame_size ());
3480 gcc_assert ((cfun
->machine
->frame
.mask
>> 31) & 1);
3481 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
3482 cfun
->machine
->frame
.gp_sp_offset
);
3484 emit_move_insn (gen_rtx_MEM (GET_MODE (address
), slot_address
), address
);
3487 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3488 Assume that the areas do not overlap. */
3491 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
3493 HOST_WIDE_INT offset
, delta
;
3494 unsigned HOST_WIDE_INT bits
;
3496 enum machine_mode mode
;
3499 /* Work out how many bits to move at a time. If both operands have
3500 half-word alignment, it is usually better to move in half words.
3501 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3502 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3503 Otherwise move word-sized chunks. */
3504 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
3505 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
3506 bits
= BITS_PER_WORD
/ 2;
3508 bits
= BITS_PER_WORD
;
3510 mode
= mode_for_size (bits
, MODE_INT
, 0);
3511 delta
= bits
/ BITS_PER_UNIT
;
3513 /* Allocate a buffer for the temporary registers. */
3514 regs
= alloca (sizeof (rtx
) * length
/ delta
);
3516 /* Load as many BITS-sized chunks as possible. Use a normal load if
3517 the source has enough alignment, otherwise use left/right pairs. */
3518 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3520 regs
[i
] = gen_reg_rtx (mode
);
3521 if (MEM_ALIGN (src
) >= bits
)
3522 emit_move_insn (regs
[i
], adjust_address (src
, mode
, offset
));
3525 rtx part
= adjust_address (src
, BLKmode
, offset
);
3526 if (!mips_expand_unaligned_load (regs
[i
], part
, bits
, 0))
3531 /* Copy the chunks to the destination. */
3532 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
3533 if (MEM_ALIGN (dest
) >= bits
)
3534 emit_move_insn (adjust_address (dest
, mode
, offset
), regs
[i
]);
3537 rtx part
= adjust_address (dest
, BLKmode
, offset
);
3538 if (!mips_expand_unaligned_store (part
, regs
[i
], bits
, 0))
3542 /* Mop up any left-over bytes. */
3543 if (offset
< length
)
3545 src
= adjust_address (src
, BLKmode
, offset
);
3546 dest
= adjust_address (dest
, BLKmode
, offset
);
3547 move_by_pieces (dest
, src
, length
- offset
,
3548 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
3552 #define MAX_MOVE_REGS 4
3553 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3556 /* Helper function for doing a loop-based block operation on memory
3557 reference MEM. Each iteration of the loop will operate on LENGTH
3560 Create a new base register for use within the loop and point it to
3561 the start of MEM. Create a new memory reference that uses this
3562 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3565 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
3566 rtx
*loop_reg
, rtx
*loop_mem
)
3568 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
3570 /* Although the new mem does not refer to a known location,
3571 it does keep up to LENGTH bytes of alignment. */
3572 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
3573 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
3577 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3578 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3579 memory regions do not overlap. */
3582 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
)
3584 rtx label
, src_reg
, dest_reg
, final_src
;
3585 HOST_WIDE_INT leftover
;
3587 leftover
= length
% MAX_MOVE_BYTES
;
3590 /* Create registers and memory references for use within the loop. */
3591 mips_adjust_block_mem (src
, MAX_MOVE_BYTES
, &src_reg
, &src
);
3592 mips_adjust_block_mem (dest
, MAX_MOVE_BYTES
, &dest_reg
, &dest
);
3594 /* Calculate the value that SRC_REG should have after the last iteration
3596 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
3599 /* Emit the start of the loop. */
3600 label
= gen_label_rtx ();
3603 /* Emit the loop body. */
3604 mips_block_move_straight (dest
, src
, MAX_MOVE_BYTES
);
3606 /* Move on to the next block. */
3607 emit_move_insn (src_reg
, plus_constant (src_reg
, MAX_MOVE_BYTES
));
3608 emit_move_insn (dest_reg
, plus_constant (dest_reg
, MAX_MOVE_BYTES
));
3610 /* Emit the loop condition. */
3611 if (Pmode
== DImode
)
3612 emit_insn (gen_cmpdi (src_reg
, final_src
));
3614 emit_insn (gen_cmpsi (src_reg
, final_src
));
3615 emit_jump_insn (gen_bne (label
));
3617 /* Mop up any left-over bytes. */
3619 mips_block_move_straight (dest
, src
, leftover
);
3622 /* Expand a movmemsi instruction. */
3625 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
3627 if (GET_CODE (length
) == CONST_INT
)
3629 if (INTVAL (length
) <= 2 * MAX_MOVE_BYTES
)
3631 mips_block_move_straight (dest
, src
, INTVAL (length
));
3636 mips_block_move_loop (dest
, src
, INTVAL (length
));
3643 /* Argument support functions. */
3645 /* Initialize CUMULATIVE_ARGS for a function. */
3648 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
3649 rtx libname ATTRIBUTE_UNUSED
)
3651 static CUMULATIVE_ARGS zero_cum
;
3652 tree param
, next_param
;
3655 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
3657 /* Determine if this function has variable arguments. This is
3658 indicated by the last argument being 'void_type_mode' if there
3659 are no variable arguments. The standard MIPS calling sequence
3660 passes all arguments in the general purpose registers in this case. */
3662 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
3663 param
!= 0; param
= next_param
)
3665 next_param
= TREE_CHAIN (param
);
3666 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
3667 cum
->gp_reg_found
= 1;
3672 /* Fill INFO with information about a single argument. CUM is the
3673 cumulative state for earlier arguments. MODE is the mode of this
3674 argument and TYPE is its type (if known). NAMED is true if this
3675 is a named (fixed) argument rather than a variable one. */
3678 mips_arg_info (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3679 tree type
, int named
, struct mips_arg_info
*info
)
3681 bool doubleword_aligned_p
;
3682 unsigned int num_bytes
, num_words
, max_regs
;
3684 /* Work out the size of the argument. */
3685 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
3686 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3688 /* Decide whether it should go in a floating-point register, assuming
3689 one is free. Later code checks for availability.
3691 The checks against UNITS_PER_FPVALUE handle the soft-float and
3692 single-float cases. */
3696 /* The EABI conventions have traditionally been defined in terms
3697 of TYPE_MODE, regardless of the actual type. */
3698 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3699 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3700 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
3705 /* Only leading floating-point scalars are passed in
3706 floating-point registers. We also handle vector floats the same
3707 say, which is OK because they are not covered by the standard ABI. */
3708 info
->fpr_p
= (!cum
->gp_reg_found
3709 && cum
->arg_number
< 2
3710 && (type
== 0 || SCALAR_FLOAT_TYPE_P (type
)
3711 || VECTOR_FLOAT_TYPE_P (type
))
3712 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3713 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3714 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
3719 /* Scalar and complex floating-point types are passed in
3720 floating-point registers. */
3721 info
->fpr_p
= (named
3722 && (type
== 0 || FLOAT_TYPE_P (type
))
3723 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3724 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
3725 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3726 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
3728 /* ??? According to the ABI documentation, the real and imaginary
3729 parts of complex floats should be passed in individual registers.
3730 The real and imaginary parts of stack arguments are supposed
3731 to be contiguous and there should be an extra word of padding
3734 This has two problems. First, it makes it impossible to use a
3735 single "void *" va_list type, since register and stack arguments
3736 are passed differently. (At the time of writing, MIPSpro cannot
3737 handle complex float varargs correctly.) Second, it's unclear
3738 what should happen when there is only one register free.
3740 For now, we assume that named complex floats should go into FPRs
3741 if there are two FPRs free, otherwise they should be passed in the
3742 same way as a struct containing two floats. */
3744 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
3745 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
3747 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
3748 info
->fpr_p
= false;
3758 /* See whether the argument has doubleword alignment. */
3759 doubleword_aligned_p
= FUNCTION_ARG_BOUNDARY (mode
, type
) > BITS_PER_WORD
;
3761 /* Set REG_OFFSET to the register count we're interested in.
3762 The EABI allocates the floating-point registers separately,
3763 but the other ABIs allocate them like integer registers. */
3764 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
3768 /* Advance to an even register if the argument is doubleword-aligned. */
3769 if (doubleword_aligned_p
)
3770 info
->reg_offset
+= info
->reg_offset
& 1;
3772 /* Work out the offset of a stack argument. */
3773 info
->stack_offset
= cum
->stack_words
;
3774 if (doubleword_aligned_p
)
3775 info
->stack_offset
+= info
->stack_offset
& 1;
3777 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
3779 /* Partition the argument between registers and stack. */
3780 info
->reg_words
= MIN (num_words
, max_regs
);
3781 info
->stack_words
= num_words
- info
->reg_words
;
3785 /* Implement FUNCTION_ARG_ADVANCE. */
3788 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3789 tree type
, int named
)
3791 struct mips_arg_info info
;
3793 mips_arg_info (cum
, mode
, type
, named
, &info
);
3796 cum
->gp_reg_found
= true;
3798 /* See the comment above the cumulative args structure in mips.h
3799 for an explanation of what this code does. It assumes the O32
3800 ABI, which passes at most 2 arguments in float registers. */
3801 if (cum
->arg_number
< 2 && info
.fpr_p
)
3802 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << ((cum
->arg_number
- 1) * 2);
3804 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
3805 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
3806 else if (info
.reg_words
> 0)
3807 cum
->num_fprs
+= FP_INC
;
3809 if (info
.stack_words
> 0)
3810 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
3815 /* Implement FUNCTION_ARG. */
3818 function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3819 tree type
, int named
)
3821 struct mips_arg_info info
;
3823 /* We will be called with a mode of VOIDmode after the last argument
3824 has been seen. Whatever we return will be passed to the call
3825 insn. If we need a mips16 fp_code, return a REG with the code
3826 stored as the mode. */
3827 if (mode
== VOIDmode
)
3829 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
3830 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
3836 mips_arg_info (cum
, mode
, type
, named
, &info
);
3838 /* Return straight away if the whole argument is passed on the stack. */
3839 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
3843 && TREE_CODE (type
) == RECORD_TYPE
3845 && TYPE_SIZE_UNIT (type
)
3846 && host_integerp (TYPE_SIZE_UNIT (type
), 1)
3849 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
3850 structure contains a double in its entirety, then that 64-bit
3851 chunk is passed in a floating point register. */
3854 /* First check to see if there is any such field. */
3855 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3856 if (TREE_CODE (field
) == FIELD_DECL
3857 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3858 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3859 && host_integerp (bit_position (field
), 0)
3860 && int_bit_position (field
) % BITS_PER_WORD
== 0)
3865 /* Now handle the special case by returning a PARALLEL
3866 indicating where each 64-bit chunk goes. INFO.REG_WORDS
3867 chunks are passed in registers. */
3869 HOST_WIDE_INT bitpos
;
3872 /* assign_parms checks the mode of ENTRY_PARM, so we must
3873 use the actual mode here. */
3874 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
3877 field
= TYPE_FIELDS (type
);
3878 for (i
= 0; i
< info
.reg_words
; i
++)
3882 for (; field
; field
= TREE_CHAIN (field
))
3883 if (TREE_CODE (field
) == FIELD_DECL
3884 && int_bit_position (field
) >= bitpos
)
3888 && int_bit_position (field
) == bitpos
3889 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3890 && !TARGET_SOFT_FLOAT
3891 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3892 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
3894 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
3897 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
3898 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3900 bitpos
+= BITS_PER_WORD
;
3906 /* Handle the n32/n64 conventions for passing complex floating-point
3907 arguments in FPR pairs. The real part goes in the lower register
3908 and the imaginary part goes in the upper register. */
3911 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3914 enum machine_mode inner
;
3917 inner
= GET_MODE_INNER (mode
);
3918 reg
= FP_ARG_FIRST
+ info
.reg_offset
;
3919 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
3921 /* Real part in registers, imaginary part on stack. */
3922 gcc_assert (info
.stack_words
== info
.reg_words
);
3923 return gen_rtx_REG (inner
, reg
);
3927 gcc_assert (info
.stack_words
== 0);
3928 real
= gen_rtx_EXPR_LIST (VOIDmode
,
3929 gen_rtx_REG (inner
, reg
),
3931 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
3933 reg
+ info
.reg_words
/ 2),
3934 GEN_INT (GET_MODE_SIZE (inner
)));
3935 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
3940 return gen_rtx_REG (mode
, GP_ARG_FIRST
+ info
.reg_offset
);
3941 else if (info
.reg_offset
== 1)
3942 /* This code handles the special o32 case in which the second word
3943 of the argument structure is passed in floating-point registers. */
3944 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ FP_INC
);
3946 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ info
.reg_offset
);
3950 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3953 mips_arg_partial_bytes (CUMULATIVE_ARGS
*cum
,
3954 enum machine_mode mode
, tree type
, bool named
)
3956 struct mips_arg_info info
;
3958 mips_arg_info (cum
, mode
, type
, named
, &info
);
3959 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
3963 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3964 PARM_BOUNDARY bits of alignment, but will be given anything up
3965 to STACK_BOUNDARY bits if the type requires it. */
3968 function_arg_boundary (enum machine_mode mode
, tree type
)
3970 unsigned int alignment
;
3972 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
3973 if (alignment
< PARM_BOUNDARY
)
3974 alignment
= PARM_BOUNDARY
;
3975 if (alignment
> STACK_BOUNDARY
)
3976 alignment
= STACK_BOUNDARY
;
3980 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3981 upward rather than downward. In other words, return true if the
3982 first byte of the stack slot has useful data, false if the last
3986 mips_pad_arg_upward (enum machine_mode mode
, tree type
)
3988 /* On little-endian targets, the first byte of every stack argument
3989 is passed in the first byte of the stack slot. */
3990 if (!BYTES_BIG_ENDIAN
)
3993 /* Otherwise, integral types are padded downward: the last byte of a
3994 stack argument is passed in the last byte of the stack slot. */
3996 ? INTEGRAL_TYPE_P (type
) || POINTER_TYPE_P (type
)
3997 : GET_MODE_CLASS (mode
) == MODE_INT
)
4000 /* Big-endian o64 pads floating-point arguments downward. */
4001 if (mips_abi
== ABI_O64
)
4002 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4005 /* Other types are padded upward for o32, o64, n32 and n64. */
4006 if (mips_abi
!= ABI_EABI
)
4009 /* Arguments smaller than a stack slot are padded downward. */
4010 if (mode
!= BLKmode
)
4011 return (GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
);
4013 return (int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
));
4017 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4018 if the least significant byte of the register has useful data. Return
4019 the opposite if the most significant byte does. */
4022 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
4024 /* No shifting is required for floating-point arguments. */
4025 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4026 return !BYTES_BIG_ENDIAN
;
4028 /* Otherwise, apply the same padding to register arguments as we do
4029 to stack arguments. */
4030 return mips_pad_arg_upward (mode
, type
);
4034 mips_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4035 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
4038 CUMULATIVE_ARGS local_cum
;
4039 int gp_saved
, fp_saved
;
4041 /* The caller has advanced CUM up to, but not beyond, the last named
4042 argument. Advance a local copy of CUM past the last "real" named
4043 argument, to find out how many registers are left over. */
4046 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, 1);
4048 /* Found out how many registers we need to save. */
4049 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
4050 fp_saved
= (EABI_FLOAT_VARARGS_P
4051 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
4060 ptr
= plus_constant (virtual_incoming_args_rtx
,
4061 REG_PARM_STACK_SPACE (cfun
->decl
)
4062 - gp_saved
* UNITS_PER_WORD
);
4063 mem
= gen_rtx_MEM (BLKmode
, ptr
);
4064 set_mem_alias_set (mem
, get_varargs_alias_set ());
4066 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
4071 /* We can't use move_block_from_reg, because it will use
4073 enum machine_mode mode
;
4076 /* Set OFF to the offset from virtual_incoming_args_rtx of
4077 the first float register. The FP save area lies below
4078 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4079 off
= -gp_saved
* UNITS_PER_WORD
;
4080 off
&= ~(UNITS_PER_FPVALUE
- 1);
4081 off
-= fp_saved
* UNITS_PER_FPREG
;
4083 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
4085 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
; i
+= FP_INC
)
4089 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
4090 mem
= gen_rtx_MEM (mode
, ptr
);
4091 set_mem_alias_set (mem
, get_varargs_alias_set ());
4092 emit_move_insn (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
4093 off
+= UNITS_PER_HWFPVALUE
;
4097 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
4098 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
4099 + fp_saved
* UNITS_PER_FPREG
);
4102 /* Create the va_list data type.
4103 We keep 3 pointers, and two offsets.
4104 Two pointers are to the overflow area, which starts at the CFA.
4105 One of these is constant, for addressing into the GPR save area below it.
4106 The other is advanced up the stack through the overflow region.
4107 The third pointer is to the GPR save area. Since the FPR save area
4108 is just below it, we can address FPR slots off this pointer.
4109 We also keep two one-byte offsets, which are to be subtracted from the
4110 constant pointers to yield addresses in the GPR and FPR save areas.
4111 These are downcounted as float or non-float arguments are used,
4112 and when they get to zero, the argument must be obtained from the
4114 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4115 pointer is enough. It's started at the GPR save area, and is
4117 Note that the GPR save area is not constant size, due to optimization
4118 in the prologue. Hence, we can't use a design with two pointers
4119 and two offsets, although we could have designed this with two pointers
4120 and three offsets. */
4123 mips_build_builtin_va_list (void)
4125 if (EABI_FLOAT_VARARGS_P
)
4127 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
4130 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
4132 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
4134 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
4136 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
4138 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
4139 unsigned_char_type_node
);
4140 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
4141 unsigned_char_type_node
);
4142 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4143 warn on every user file. */
4144 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
4145 array
= build_array_type (unsigned_char_type_node
,
4146 build_index_type (index
));
4147 f_res
= build_decl (FIELD_DECL
, get_identifier ("__reserved"), array
);
4149 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
4150 DECL_FIELD_CONTEXT (f_gtop
) = record
;
4151 DECL_FIELD_CONTEXT (f_ftop
) = record
;
4152 DECL_FIELD_CONTEXT (f_goff
) = record
;
4153 DECL_FIELD_CONTEXT (f_foff
) = record
;
4154 DECL_FIELD_CONTEXT (f_res
) = record
;
4156 TYPE_FIELDS (record
) = f_ovfl
;
4157 TREE_CHAIN (f_ovfl
) = f_gtop
;
4158 TREE_CHAIN (f_gtop
) = f_ftop
;
4159 TREE_CHAIN (f_ftop
) = f_goff
;
4160 TREE_CHAIN (f_goff
) = f_foff
;
4161 TREE_CHAIN (f_foff
) = f_res
;
4163 layout_type (record
);
4166 else if (TARGET_IRIX
&& TARGET_IRIX6
)
4167 /* On IRIX 6, this type is 'char *'. */
4168 return build_pointer_type (char_type_node
);
4170 /* Otherwise, we use 'void *'. */
4171 return ptr_type_node
;
4174 /* Implement va_start. */
4177 mips_va_start (tree valist
, rtx nextarg
)
4179 if (EABI_FLOAT_VARARGS_P
)
4181 const CUMULATIVE_ARGS
*cum
;
4182 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4183 tree ovfl
, gtop
, ftop
, goff
, foff
;
4185 int gpr_save_area_size
;
4186 int fpr_save_area_size
;
4189 cum
= ¤t_function_args_info
;
4191 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
4193 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
4195 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4196 f_gtop
= TREE_CHAIN (f_ovfl
);
4197 f_ftop
= TREE_CHAIN (f_gtop
);
4198 f_goff
= TREE_CHAIN (f_ftop
);
4199 f_foff
= TREE_CHAIN (f_goff
);
4201 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4203 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
4205 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
4207 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
4209 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
4212 /* Emit code to initialize OVFL, which points to the next varargs
4213 stack argument. CUM->STACK_WORDS gives the number of stack
4214 words used by named arguments. */
4215 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
4216 if (cum
->stack_words
> 0)
4217 t
= build2 (PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
4218 build_int_cst (NULL_TREE
,
4219 cum
->stack_words
* UNITS_PER_WORD
));
4220 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovfl
), ovfl
, t
);
4221 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4223 /* Emit code to initialize GTOP, the top of the GPR save area. */
4224 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
4225 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (gtop
), gtop
, t
);
4226 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4228 /* Emit code to initialize FTOP, the top of the FPR save area.
4229 This address is gpr_save_area_bytes below GTOP, rounded
4230 down to the next fp-aligned boundary. */
4231 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
4232 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
4233 fpr_offset
&= ~(UNITS_PER_FPVALUE
- 1);
4235 t
= build2 (PLUS_EXPR
, TREE_TYPE (ftop
), t
,
4236 build_int_cst (NULL_TREE
, -fpr_offset
));
4237 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ftop
), ftop
, t
);
4238 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4240 /* Emit code to initialize GOFF, the offset from GTOP of the
4241 next GPR argument. */
4242 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (goff
), goff
,
4243 build_int_cst (NULL_TREE
, gpr_save_area_size
));
4244 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4246 /* Likewise emit code to initialize FOFF, the offset from FTOP
4247 of the next FPR argument. */
4248 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (foff
), foff
,
4249 build_int_cst (NULL_TREE
, fpr_save_area_size
));
4250 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4254 nextarg
= plus_constant (nextarg
, -cfun
->machine
->varargs_size
);
4255 std_expand_builtin_va_start (valist
, nextarg
);
4259 /* Implement va_arg. */
4262 mips_gimplify_va_arg_expr (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
4264 HOST_WIDE_INT size
, rsize
;
4268 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4271 type
= build_pointer_type (type
);
4273 size
= int_size_in_bytes (type
);
4274 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4276 if (mips_abi
!= ABI_EABI
|| !EABI_FLOAT_VARARGS_P
)
4277 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
4280 /* Not a simple merged stack. */
4282 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4283 tree ovfl
, top
, off
, align
;
4284 HOST_WIDE_INT osize
;
4287 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4288 f_gtop
= TREE_CHAIN (f_ovfl
);
4289 f_ftop
= TREE_CHAIN (f_gtop
);
4290 f_goff
= TREE_CHAIN (f_ftop
);
4291 f_foff
= TREE_CHAIN (f_goff
);
4293 /* We maintain separate pointers and offsets for floating-point
4294 and integer arguments, but we need similar code in both cases.
4297 TOP be the top of the register save area;
4298 OFF be the offset from TOP of the next register;
4299 ADDR_RTX be the address of the argument;
4300 RSIZE be the number of bytes used to store the argument
4301 when it's in the register save area;
4302 OSIZE be the number of bytes used to store it when it's
4303 in the stack overflow area; and
4304 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4306 The code we want is:
4308 1: off &= -rsize; // round down
4311 4: addr_rtx = top - off;
4316 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4317 10: addr_rtx = ovfl + PADDING;
4321 [1] and [9] can sometimes be optimized away. */
4323 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4326 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
4327 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
4329 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
4331 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
4334 /* When floating-point registers are saved to the stack,
4335 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4336 of the float's precision. */
4337 rsize
= UNITS_PER_HWFPVALUE
;
4339 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4340 (= PARM_BOUNDARY bits). This can be different from RSIZE
4343 (1) On 32-bit targets when TYPE is a structure such as:
4345 struct s { float f; };
4347 Such structures are passed in paired FPRs, so RSIZE
4348 will be 8 bytes. However, the structure only takes
4349 up 4 bytes of memory, so OSIZE will only be 4.
4351 (2) In combinations such as -mgp64 -msingle-float
4352 -fshort-double. Doubles passed in registers
4353 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4354 but those passed on the stack take up
4355 UNITS_PER_WORD bytes. */
4356 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
4360 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
4362 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
4364 if (rsize
> UNITS_PER_WORD
)
4366 /* [1] Emit code for: off &= -rsize. */
4367 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
4368 build_int_cst (NULL_TREE
, -rsize
));
4369 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (off
), off
, t
);
4370 gimplify_and_add (t
, pre_p
);
4375 /* [2] Emit code to branch if off == 0. */
4376 t
= build2 (NE_EXPR
, boolean_type_node
, off
,
4377 build_int_cst (TREE_TYPE (off
), 0));
4378 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
4380 /* [5] Emit code for: off -= rsize. We do this as a form of
4381 post-increment not available to C. Also widen for the
4382 coming pointer arithmetic. */
4383 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
4384 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
4385 t
= fold_convert (sizetype
, t
);
4386 t
= fold_convert (TREE_TYPE (top
), t
);
4388 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4389 the argument has RSIZE - SIZE bytes of leading padding. */
4390 t
= build2 (MINUS_EXPR
, TREE_TYPE (top
), top
, t
);
4391 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
4393 u
= fold_convert (TREE_TYPE (t
), build_int_cst (NULL_TREE
,
4395 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
4397 COND_EXPR_THEN (addr
) = t
;
4399 if (osize
> UNITS_PER_WORD
)
4401 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4402 u
= fold_convert (TREE_TYPE (ovfl
),
4403 build_int_cst (NULL_TREE
, osize
- 1));
4404 t
= build2 (PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
4405 u
= fold_convert (TREE_TYPE (ovfl
),
4406 build_int_cst (NULL_TREE
, -osize
));
4407 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (ovfl
), t
, u
);
4408 align
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovfl
), ovfl
, t
);
4413 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4414 post-increment ovfl by osize. On big-endian machines,
4415 the argument has OSIZE - SIZE bytes of leading padding. */
4416 u
= fold_convert (TREE_TYPE (ovfl
),
4417 build_int_cst (NULL_TREE
, osize
));
4418 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
4419 if (BYTES_BIG_ENDIAN
&& osize
> size
)
4421 u
= fold_convert (TREE_TYPE (t
),
4422 build_int_cst (NULL_TREE
, osize
- size
));
4423 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
4426 /* String [9] and [10,11] together. */
4428 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
4429 COND_EXPR_ELSE (addr
) = t
;
4431 addr
= fold_convert (build_pointer_type (type
), addr
);
4432 addr
= build_va_arg_indirect_ref (addr
);
4436 addr
= build_va_arg_indirect_ref (addr
);
4441 /* Return true if it is possible to use left/right accesses for a
4442 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4443 returning true, update *OP, *LEFT and *RIGHT as follows:
4445 *OP is a BLKmode reference to the whole field.
4447 *LEFT is a QImode reference to the first byte if big endian or
4448 the last byte if little endian. This address can be used in the
4449 left-side instructions (lwl, swl, ldl, sdl).
4451 *RIGHT is a QImode reference to the opposite end of the field and
4452 can be used in the patterning right-side instruction. */
4455 mips_get_unaligned_mem (rtx
*op
, unsigned int width
, int bitpos
,
4456 rtx
*left
, rtx
*right
)
4460 /* Check that the operand really is a MEM. Not all the extv and
4461 extzv predicates are checked. */
4465 /* Check that the size is valid. */
4466 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
4469 /* We can only access byte-aligned values. Since we are always passed
4470 a reference to the first byte of the field, it is not necessary to
4471 do anything with BITPOS after this check. */
4472 if (bitpos
% BITS_PER_UNIT
!= 0)
4475 /* Reject aligned bitfields: we want to use a normal load or store
4476 instead of a left/right pair. */
4477 if (MEM_ALIGN (*op
) >= width
)
4480 /* Adjust *OP to refer to the whole field. This also has the effect
4481 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4482 *op
= adjust_address (*op
, BLKmode
, 0);
4483 set_mem_size (*op
, GEN_INT (width
/ BITS_PER_UNIT
));
4485 /* Get references to both ends of the field. We deliberately don't
4486 use the original QImode *OP for FIRST since the new BLKmode one
4487 might have a simpler address. */
4488 first
= adjust_address (*op
, QImode
, 0);
4489 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
4491 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4492 be the upper word and RIGHT the lower word. */
4493 if (TARGET_BIG_ENDIAN
)
4494 *left
= first
, *right
= last
;
4496 *left
= last
, *right
= first
;
4502 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4503 Return true on success. We only handle cases where zero_extract is
4504 equivalent to sign_extract. */
4507 mips_expand_unaligned_load (rtx dest
, rtx src
, unsigned int width
, int bitpos
)
4509 rtx left
, right
, temp
;
4511 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4512 paradoxical word_mode subreg. This is the only case in which
4513 we allow the destination to be larger than the source. */
4514 if (GET_CODE (dest
) == SUBREG
4515 && GET_MODE (dest
) == DImode
4516 && SUBREG_BYTE (dest
) == 0
4517 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
4518 dest
= SUBREG_REG (dest
);
4520 /* After the above adjustment, the destination must be the same
4521 width as the source. */
4522 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
4525 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
4528 temp
= gen_reg_rtx (GET_MODE (dest
));
4529 if (GET_MODE (dest
) == DImode
)
4531 emit_insn (gen_mov_ldl (temp
, src
, left
));
4532 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
4536 emit_insn (gen_mov_lwl (temp
, src
, left
));
4537 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
4543 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4547 mips_expand_unaligned_store (rtx dest
, rtx src
, unsigned int width
, int bitpos
)
4550 enum machine_mode mode
;
4552 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
4555 mode
= mode_for_size (width
, MODE_INT
, 0);
4556 src
= gen_lowpart (mode
, src
);
4560 emit_insn (gen_mov_sdl (dest
, src
, left
));
4561 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
4565 emit_insn (gen_mov_swl (dest
, src
, left
));
4566 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
4571 /* Return true if X is a MEM with the same size as MODE. */
4574 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
4581 size
= MEM_SIZE (x
);
4582 return size
&& INTVAL (size
) == GET_MODE_SIZE (mode
);
4585 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4586 source of an "ext" instruction or the destination of an "ins"
4587 instruction. OP must be a register operand and the following
4588 conditions must hold:
4590 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4591 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4592 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4594 Also reject lengths equal to a word as they are better handled
4595 by the move patterns. */
4598 mips_use_ins_ext_p (rtx op
, rtx size
, rtx position
)
4600 HOST_WIDE_INT len
, pos
;
4602 if (!ISA_HAS_EXT_INS
4603 || !register_operand (op
, VOIDmode
)
4604 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
4607 len
= INTVAL (size
);
4608 pos
= INTVAL (position
);
4610 if (len
<= 0 || len
>= GET_MODE_BITSIZE (GET_MODE (op
))
4611 || pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (op
)))
4617 /* Set up globals to generate code for the ISA or processor
4618 described by INFO. */
4621 mips_set_architecture (const struct mips_cpu_info
*info
)
4625 mips_arch_info
= info
;
4626 mips_arch
= info
->cpu
;
4627 mips_isa
= info
->isa
;
4632 /* Likewise for tuning. */
4635 mips_set_tune (const struct mips_cpu_info
*info
)
4639 mips_tune_info
= info
;
4640 mips_tune
= info
->cpu
;
4644 /* Implement TARGET_HANDLE_OPTION. */
4647 mips_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
4652 if (strcmp (arg
, "32") == 0)
4654 else if (strcmp (arg
, "o64") == 0)
4656 else if (strcmp (arg
, "n32") == 0)
4658 else if (strcmp (arg
, "64") == 0)
4660 else if (strcmp (arg
, "eabi") == 0)
4661 mips_abi
= ABI_EABI
;
4668 return mips_parse_cpu (arg
) != 0;
4671 mips_isa_info
= mips_parse_cpu (ACONCAT (("mips", arg
, NULL
)));
4672 return mips_isa_info
!= 0;
4674 case OPT_mno_flush_func
:
4675 mips_cache_flush_func
= NULL
;
4683 /* Set up the threshold for data to go into the small data area, instead
4684 of the normal data area, and detect any conflicts in the switches. */
4687 override_options (void)
4689 int i
, start
, regno
;
4690 enum machine_mode mode
;
4692 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
4694 /* The following code determines the architecture and register size.
4695 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4696 The GAS and GCC code should be kept in sync as much as possible. */
4698 if (mips_arch_string
!= 0)
4699 mips_set_architecture (mips_parse_cpu (mips_arch_string
));
4701 if (mips_isa_info
!= 0)
4703 if (mips_arch_info
== 0)
4704 mips_set_architecture (mips_isa_info
);
4705 else if (mips_arch_info
->isa
!= mips_isa_info
->isa
)
4706 error ("-%s conflicts with the other architecture options, "
4707 "which specify a %s processor",
4708 mips_isa_info
->name
,
4709 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
4712 if (mips_arch_info
== 0)
4714 #ifdef MIPS_CPU_STRING_DEFAULT
4715 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT
));
4717 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
4721 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
4722 error ("-march=%s is not compatible with the selected ABI",
4723 mips_arch_info
->name
);
4725 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4726 if (mips_tune_string
!= 0)
4727 mips_set_tune (mips_parse_cpu (mips_tune_string
));
4729 if (mips_tune_info
== 0)
4730 mips_set_tune (mips_arch_info
);
4732 /* Set cost structure for the processor. */
4734 mips_cost
= &mips_rtx_cost_optimize_size
;
4736 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
4738 if ((target_flags_explicit
& MASK_64BIT
) != 0)
4740 /* The user specified the size of the integer registers. Make sure
4741 it agrees with the ABI and ISA. */
4742 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
4743 error ("-mgp64 used with a 32-bit processor");
4744 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
4745 error ("-mgp32 used with a 64-bit ABI");
4746 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
4747 error ("-mgp64 used with a 32-bit ABI");
4751 /* Infer the integer register size from the ABI and processor.
4752 Restrict ourselves to 32-bit registers if that's all the
4753 processor has, or if the ABI cannot handle 64-bit registers. */
4754 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
4755 target_flags
&= ~MASK_64BIT
;
4757 target_flags
|= MASK_64BIT
;
4760 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
4762 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4763 only one right answer here. */
4764 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
4765 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4766 else if (!TARGET_64BIT
&& TARGET_FLOAT64
4767 && !(ISA_HAS_MXHC1
&& mips_abi
== ABI_32
))
4768 error ("-mgp32 and -mfp64 can only be combined if the target"
4769 " supports the mfhc1 and mthc1 instructions");
4770 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
4771 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4775 /* -msingle-float selects 32-bit float registers. Otherwise the
4776 float registers should be the same size as the integer ones. */
4777 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
4778 target_flags
|= MASK_FLOAT64
;
4780 target_flags
&= ~MASK_FLOAT64
;
4783 /* End of code shared with GAS. */
4785 if ((target_flags_explicit
& MASK_LONG64
) == 0)
4787 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
4788 target_flags
|= MASK_LONG64
;
4790 target_flags
&= ~MASK_LONG64
;
4793 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4794 && (target_flags_explicit
& MASK_SOFT_FLOAT
) == 0)
4796 /* For some configurations, it is useful to have -march control
4797 the default setting of MASK_SOFT_FLOAT. */
4798 switch ((int) mips_arch
)
4800 case PROCESSOR_R4100
:
4801 case PROCESSOR_R4111
:
4802 case PROCESSOR_R4120
:
4803 case PROCESSOR_R4130
:
4804 target_flags
|= MASK_SOFT_FLOAT
;
4808 target_flags
&= ~MASK_SOFT_FLOAT
;
4814 flag_pcc_struct_return
= 0;
4816 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
4818 /* If neither -mbranch-likely nor -mno-branch-likely was given
4819 on the command line, set MASK_BRANCHLIKELY based on the target
4822 By default, we enable use of Branch Likely instructions on
4823 all architectures which support them with the following
4824 exceptions: when creating MIPS32 or MIPS64 code, and when
4825 tuning for architectures where their use tends to hurt
4828 The MIPS32 and MIPS64 architecture specifications say "Software
4829 is strongly encouraged to avoid use of Branch Likely
4830 instructions, as they will be removed from a future revision
4831 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4832 issue those instructions unless instructed to do so by
4834 if (ISA_HAS_BRANCHLIKELY
4835 && !(ISA_MIPS32
|| ISA_MIPS32R2
|| ISA_MIPS64
)
4836 && !(TUNE_MIPS5500
|| TUNE_SB1
))
4837 target_flags
|= MASK_BRANCHLIKELY
;
4839 target_flags
&= ~MASK_BRANCHLIKELY
;
4841 if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
4842 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4844 /* The effect of -mabicalls isn't defined for the EABI. */
4845 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
4847 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4848 target_flags
&= ~MASK_ABICALLS
;
4851 if (TARGET_ABICALLS
)
4853 /* We need to set flag_pic for executables as well as DSOs
4854 because we may reference symbols that are not defined in
4855 the final executable. (MIPS does not use things like
4856 copy relocs, for example.)
4858 Also, there is a body of code that uses __PIC__ to distinguish
4859 between -mabicalls and -mno-abicalls code. */
4861 if (mips_section_threshold
> 0)
4862 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
4865 /* mips_split_addresses is a half-way house between explicit
4866 relocations and the traditional assembler macros. It can
4867 split absolute 32-bit symbolic constants into a high/lo_sum
4868 pair but uses macros for other sorts of access.
4870 Like explicit relocation support for REL targets, it relies
4871 on GNU extensions in the assembler and the linker.
4873 Although this code should work for -O0, it has traditionally
4874 been treated as an optimization. */
4875 if (!TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
4876 && optimize
&& !flag_pic
4877 && !ABI_HAS_64BIT_SYMBOLS
)
4878 mips_split_addresses
= 1;
4880 mips_split_addresses
= 0;
4882 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4883 faster code, but at the expense of more nops. Enable it at -O3 and
4885 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
4886 target_flags
|= MASK_VR4130_ALIGN
;
4888 /* When compiling for the mips16, we cannot use floating point. We
4889 record the original hard float value in mips16_hard_float. */
4892 if (TARGET_SOFT_FLOAT
)
4893 mips16_hard_float
= 0;
4895 mips16_hard_float
= 1;
4896 target_flags
|= MASK_SOFT_FLOAT
;
4898 /* Don't run the scheduler before reload, since it tends to
4899 increase register pressure. */
4900 flag_schedule_insns
= 0;
4902 /* Don't do hot/cold partitioning. The constant layout code expects
4903 the whole function to be in a single section. */
4904 flag_reorder_blocks_and_partition
= 0;
4906 /* Silently disable -mexplicit-relocs since it doesn't apply
4907 to mips16 code. Even so, it would overly pedantic to warn
4908 about "-mips16 -mexplicit-relocs", especially given that
4909 we use a %gprel() operator. */
4910 target_flags
&= ~MASK_EXPLICIT_RELOCS
;
4913 /* When using explicit relocs, we call dbr_schedule from within
4915 if (TARGET_EXPLICIT_RELOCS
)
4917 mips_flag_delayed_branch
= flag_delayed_branch
;
4918 flag_delayed_branch
= 0;
4921 #ifdef MIPS_TFMODE_FORMAT
4922 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
4925 /* Make sure that the user didn't turn off paired single support when
4926 MIPS-3D support is requested. */
4927 if (TARGET_MIPS3D
&& (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
4928 && !TARGET_PAIRED_SINGLE_FLOAT
)
4929 error ("-mips3d requires -mpaired-single");
4931 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4933 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
4935 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4936 and TARGET_HARD_FLOAT are both true. */
4937 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT
))
4938 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4940 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4942 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_MIPS64
)
4943 error ("-mips3d/-mpaired-single must be used with -mips64");
4945 /* If TARGET_DSPR2, enable MASK_DSP. */
4947 target_flags
|= MASK_DSP
;
4949 if (TARGET_MIPS16
&& TARGET_DSP
)
4950 error ("-mips16 and -mdsp cannot be used together");
4952 mips_print_operand_punct
['?'] = 1;
4953 mips_print_operand_punct
['#'] = 1;
4954 mips_print_operand_punct
['/'] = 1;
4955 mips_print_operand_punct
['&'] = 1;
4956 mips_print_operand_punct
['!'] = 1;
4957 mips_print_operand_punct
['*'] = 1;
4958 mips_print_operand_punct
['@'] = 1;
4959 mips_print_operand_punct
['.'] = 1;
4960 mips_print_operand_punct
['('] = 1;
4961 mips_print_operand_punct
[')'] = 1;
4962 mips_print_operand_punct
['['] = 1;
4963 mips_print_operand_punct
[']'] = 1;
4964 mips_print_operand_punct
['<'] = 1;
4965 mips_print_operand_punct
['>'] = 1;
4966 mips_print_operand_punct
['{'] = 1;
4967 mips_print_operand_punct
['}'] = 1;
4968 mips_print_operand_punct
['^'] = 1;
4969 mips_print_operand_punct
['$'] = 1;
4970 mips_print_operand_punct
['+'] = 1;
4971 mips_print_operand_punct
['~'] = 1;
4973 /* Set up array to map GCC register number to debug register number.
4974 Ignore the special purpose register numbers. */
4976 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4977 mips_dbx_regno
[i
] = -1;
4979 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
4980 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
4981 mips_dbx_regno
[i
] = i
+ start
;
4983 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
4984 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
4985 mips_dbx_regno
[i
] = i
+ start
;
4987 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
4988 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
4990 /* Set up array giving whether a given register can hold a given mode. */
4992 for (mode
= VOIDmode
;
4993 mode
!= MAX_MACHINE_MODE
;
4994 mode
= (enum machine_mode
) ((int)mode
+ 1))
4996 register int size
= GET_MODE_SIZE (mode
);
4997 register enum mode_class
class = GET_MODE_CLASS (mode
);
4999 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
5003 if (mode
== CCV2mode
)
5006 && (regno
- ST_REG_FIRST
) % 2 == 0);
5008 else if (mode
== CCV4mode
)
5011 && (regno
- ST_REG_FIRST
) % 4 == 0);
5013 else if (mode
== CCmode
)
5016 temp
= (regno
== FPSW_REGNUM
);
5018 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
5019 || FP_REG_P (regno
));
5022 else if (GP_REG_P (regno
))
5023 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
5025 else if (FP_REG_P (regno
))
5026 temp
= ((regno
% FP_INC
) == 0)
5027 && (((class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
5028 || class == MODE_VECTOR_FLOAT
)
5029 && size
<= UNITS_PER_FPVALUE
)
5030 /* Allow integer modes that fit into a single
5031 register. We need to put integers into FPRs
5032 when using instructions like cvt and trunc.
5033 We can't allow sizes smaller than a word,
5034 the FPU has no appropriate load/store
5035 instructions for those. */
5036 || (class == MODE_INT
5037 && size
>= MIN_UNITS_PER_WORD
5038 && size
<= UNITS_PER_FPREG
)
5039 /* Allow TFmode for CCmode reloads. */
5040 || (ISA_HAS_8CC
&& mode
== TFmode
));
5042 else if (ACC_REG_P (regno
))
5043 temp
= (INTEGRAL_MODE_P (mode
)
5044 && (size
<= UNITS_PER_WORD
5045 || (ACC_HI_REG_P (regno
)
5046 && size
== 2 * UNITS_PER_WORD
)));
5048 else if (ALL_COP_REG_P (regno
))
5049 temp
= (class == MODE_INT
&& size
<= UNITS_PER_WORD
);
5053 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
5057 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5058 initialized yet, so we can't use that here. */
5059 gpr_mode
= TARGET_64BIT
? DImode
: SImode
;
5061 /* Provide default values for align_* for 64-bit targets. */
5062 if (TARGET_64BIT
&& !TARGET_MIPS16
)
5064 if (align_loops
== 0)
5066 if (align_jumps
== 0)
5068 if (align_functions
== 0)
5069 align_functions
= 8;
5072 /* Function to allocate machine-dependent function status. */
5073 init_machine_status
= &mips_init_machine_status
;
5075 if (ABI_HAS_64BIT_SYMBOLS
)
5077 if (TARGET_EXPLICIT_RELOCS
)
5079 mips_split_p
[SYMBOL_64_HIGH
] = true;
5080 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
5081 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
5083 mips_split_p
[SYMBOL_64_MID
] = true;
5084 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
5085 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
5087 mips_split_p
[SYMBOL_64_LOW
] = true;
5088 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
5089 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
5091 mips_split_p
[SYMBOL_GENERAL
] = true;
5092 mips_lo_relocs
[SYMBOL_GENERAL
] = "%lo(";
5097 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses
)
5099 mips_split_p
[SYMBOL_GENERAL
] = true;
5100 mips_hi_relocs
[SYMBOL_GENERAL
] = "%hi(";
5101 mips_lo_relocs
[SYMBOL_GENERAL
] = "%lo(";
5107 /* The high part is provided by a pseudo copy of $gp. */
5108 mips_split_p
[SYMBOL_SMALL_DATA
] = true;
5109 mips_lo_relocs
[SYMBOL_SMALL_DATA
] = "%gprel(";
5112 if (TARGET_EXPLICIT_RELOCS
)
5114 /* Small data constants are kept whole until after reload,
5115 then lowered by mips_rewrite_small_data. */
5116 mips_lo_relocs
[SYMBOL_SMALL_DATA
] = "%gp_rel(";
5118 mips_split_p
[SYMBOL_GOT_LOCAL
] = true;
5121 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
5122 mips_lo_relocs
[SYMBOL_GOT_LOCAL
] = "%got_ofst(";
5126 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
5127 mips_lo_relocs
[SYMBOL_GOT_LOCAL
] = "%lo(";
5132 /* The HIGH and LO_SUM are matched by special .md patterns. */
5133 mips_split_p
[SYMBOL_GOT_GLOBAL
] = true;
5135 mips_split_p
[SYMBOL_GOTOFF_GLOBAL
] = true;
5136 mips_hi_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got_hi(";
5137 mips_lo_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got_lo(";
5139 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
5140 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
5141 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
5146 mips_lo_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got_disp(";
5148 mips_lo_relocs
[SYMBOL_GOTOFF_GLOBAL
] = "%got(";
5149 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
5155 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
5156 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
5157 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
5160 /* Thread-local relocation operators. */
5161 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
5162 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
5163 mips_split_p
[SYMBOL_DTPREL
] = 1;
5164 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
5165 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
5166 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
5167 mips_split_p
[SYMBOL_TPREL
] = 1;
5168 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
5169 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
5171 /* We don't have a thread pointer access instruction on MIPS16, or
5172 appropriate TLS relocations. */
5174 targetm
.have_tls
= false;
5176 /* Default to working around R4000 errata only if the processor
5177 was selected explicitly. */
5178 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
5179 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4000"))
5180 target_flags
|= MASK_FIX_R4000
;
5182 /* Default to working around R4400 errata only if the processor
5183 was selected explicitly. */
5184 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
5185 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4400"))
5186 target_flags
|= MASK_FIX_R4400
;
5189 /* Implement CONDITIONAL_REGISTER_USAGE. */
5192 mips_conditional_register_usage (void)
5198 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
5199 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5201 if (!TARGET_HARD_FLOAT
)
5205 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
5206 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5207 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
5208 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5210 else if (! ISA_HAS_8CC
)
5214 /* We only have a single condition code register. We
5215 implement this by hiding all the condition code registers,
5216 and generating RTL that refers directly to ST_REG_FIRST. */
5217 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
5218 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5220 /* In mips16 mode, we permit the $t temporary registers to be used
5221 for reload. We prohibit the unused $s registers, since they
5222 are caller saved, and saving them via a mips16 register would
5223 probably waste more time than just reloading the value. */
5226 fixed_regs
[18] = call_used_regs
[18] = 1;
5227 fixed_regs
[19] = call_used_regs
[19] = 1;
5228 fixed_regs
[20] = call_used_regs
[20] = 1;
5229 fixed_regs
[21] = call_used_regs
[21] = 1;
5230 fixed_regs
[22] = call_used_regs
[22] = 1;
5231 fixed_regs
[23] = call_used_regs
[23] = 1;
5232 fixed_regs
[26] = call_used_regs
[26] = 1;
5233 fixed_regs
[27] = call_used_regs
[27] = 1;
5234 fixed_regs
[30] = call_used_regs
[30] = 1;
5236 /* fp20-23 are now caller saved. */
5237 if (mips_abi
== ABI_64
)
5240 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
5241 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
5243 /* Odd registers from fp21 to fp31 are now caller saved. */
5244 if (mips_abi
== ABI_N32
)
5247 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
5248 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
5252 /* Allocate a chunk of memory for per-function machine-dependent data. */
5253 static struct machine_function
*
5254 mips_init_machine_status (void)
5256 return ((struct machine_function
*)
5257 ggc_alloc_cleared (sizeof (struct machine_function
)));
5260 /* On the mips16, we want to allocate $24 (T_REG) before other
5261 registers for instructions for which it is possible. This helps
5262 avoid shuffling registers around in order to set up for an xor,
5263 encouraging the compiler to use a cmp instead. */
5266 mips_order_regs_for_local_alloc (void)
5270 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5271 reg_alloc_order
[i
] = i
;
5275 /* It really doesn't matter where we put register 0, since it is
5276 a fixed register anyhow. */
5277 reg_alloc_order
[0] = 24;
5278 reg_alloc_order
[24] = 0;
5283 /* The MIPS debug format wants all automatic variables and arguments
5284 to be in terms of the virtual frame pointer (stack pointer before
5285 any adjustment in the function), while the MIPS 3.0 linker wants
5286 the frame pointer to be the stack pointer after the initial
5287 adjustment. So, we do the adjustment here. The arg pointer (which
5288 is eliminated) points to the virtual frame pointer, while the frame
5289 pointer (which may be eliminated) points to the stack pointer after
5290 the initial adjustments. */
5293 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
5295 rtx offset2
= const0_rtx
;
5296 rtx reg
= eliminate_constant_term (addr
, &offset2
);
5299 offset
= INTVAL (offset2
);
5301 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
5302 || reg
== hard_frame_pointer_rtx
)
5304 HOST_WIDE_INT frame_size
= (!cfun
->machine
->frame
.initialized
)
5305 ? compute_frame_size (get_frame_size ())
5306 : cfun
->machine
->frame
.total_size
;
5308 /* MIPS16 frame is smaller */
5309 if (frame_pointer_needed
&& TARGET_MIPS16
)
5310 frame_size
-= cfun
->machine
->frame
.args_size
;
5312 offset
= offset
- frame_size
;
5315 /* sdbout_parms does not want this to crash for unrecognized cases. */
5317 else if (reg
!= arg_pointer_rtx
)
5318 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5325 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5327 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5328 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5329 'h' OP is HIGH, prints %hi(X),
5330 'd' output integer constant in decimal,
5331 'z' if the operand is 0, use $0 instead of normal operand.
5332 'D' print second part of double-word register or memory operand.
5333 'L' print low-order register of double-word register operand.
5334 'M' print high-order register of double-word register operand.
5335 'C' print part of opcode for a branch condition.
5336 'F' print part of opcode for a floating-point branch condition.
5337 'N' print part of opcode for a branch condition, inverted.
5338 'W' print part of opcode for a floating-point branch condition, inverted.
5339 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5340 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5341 't' like 'T', but with the EQ/NE cases reversed
5342 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5343 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5344 'R' print the reloc associated with LO_SUM
5345 'q' print DSP accumulator registers
5347 The punctuation characters are:
5349 '(' Turn on .set noreorder
5350 ')' Turn on .set reorder
5351 '[' Turn on .set noat
5353 '<' Turn on .set nomacro
5354 '>' Turn on .set macro
5355 '{' Turn on .set volatile (not GAS)
5356 '}' Turn on .set novolatile (not GAS)
5357 '&' Turn on .set noreorder if filling delay slots
5358 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5359 '!' Turn on .set nomacro if filling delay slots
5360 '#' Print nop if in a .set noreorder section.
5361 '/' Like '#', but does nothing within a delayed branch sequence
5362 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5363 '@' Print the name of the assembler temporary register (at or $1).
5364 '.' Print the name of the register with a hard-wired zero (zero or $0).
5365 '^' Print the name of the pic call-through register (t9 or $25).
5366 '$' Print the name of the stack pointer register (sp or $29).
5367 '+' Print the name of the gp register (usually gp or $28).
5368 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5371 print_operand (FILE *file
, rtx op
, int letter
)
5373 register enum rtx_code code
;
5375 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
5380 if (mips_branch_likely
)
5385 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
5389 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
5393 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
5397 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
5401 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
5405 if (final_sequence
!= 0 && set_noreorder
++ == 0)
5406 fputs (".set\tnoreorder\n\t", file
);
5410 if (final_sequence
!= 0)
5412 if (set_noreorder
++ == 0)
5413 fputs (".set\tnoreorder\n\t", file
);
5415 if (set_nomacro
++ == 0)
5416 fputs (".set\tnomacro\n\t", file
);
5421 if (final_sequence
!= 0 && set_nomacro
++ == 0)
5422 fputs ("\n\t.set\tnomacro", file
);
5426 if (set_noreorder
!= 0)
5427 fputs ("\n\tnop", file
);
5431 /* Print an extra newline so that the delayed insn is separated
5432 from the following ones. This looks neater and is consistent
5433 with non-nop delayed sequences. */
5434 if (set_noreorder
!= 0 && final_sequence
== 0)
5435 fputs ("\n\tnop\n", file
);
5439 if (set_noreorder
++ == 0)
5440 fputs (".set\tnoreorder\n\t", file
);
5444 if (set_noreorder
== 0)
5445 error ("internal error: %%) found without a %%( in assembler pattern");
5447 else if (--set_noreorder
== 0)
5448 fputs ("\n\t.set\treorder", file
);
5453 if (set_noat
++ == 0)
5454 fputs (".set\tnoat\n\t", file
);
5459 error ("internal error: %%] found without a %%[ in assembler pattern");
5460 else if (--set_noat
== 0)
5461 fputs ("\n\t.set\tat", file
);
5466 if (set_nomacro
++ == 0)
5467 fputs (".set\tnomacro\n\t", file
);
5471 if (set_nomacro
== 0)
5472 error ("internal error: %%> found without a %%< in assembler pattern");
5473 else if (--set_nomacro
== 0)
5474 fputs ("\n\t.set\tmacro", file
);
5479 if (set_volatile
++ == 0)
5480 fputs ("#.set\tvolatile\n\t", file
);
5484 if (set_volatile
== 0)
5485 error ("internal error: %%} found without a %%{ in assembler pattern");
5486 else if (--set_volatile
== 0)
5487 fputs ("\n\t#.set\tnovolatile", file
);
5493 if (align_labels_log
> 0)
5494 ASM_OUTPUT_ALIGN (file
, align_labels_log
);
5499 error ("PRINT_OPERAND: unknown punctuation '%c'", letter
);
5508 error ("PRINT_OPERAND null pointer");
5512 code
= GET_CODE (op
);
5517 case EQ
: fputs ("eq", file
); break;
5518 case NE
: fputs ("ne", file
); break;
5519 case GT
: fputs ("gt", file
); break;
5520 case GE
: fputs ("ge", file
); break;
5521 case LT
: fputs ("lt", file
); break;
5522 case LE
: fputs ("le", file
); break;
5523 case GTU
: fputs ("gtu", file
); break;
5524 case GEU
: fputs ("geu", file
); break;
5525 case LTU
: fputs ("ltu", file
); break;
5526 case LEU
: fputs ("leu", file
); break;
5528 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op
);
5531 else if (letter
== 'N')
5534 case EQ
: fputs ("ne", file
); break;
5535 case NE
: fputs ("eq", file
); break;
5536 case GT
: fputs ("le", file
); break;
5537 case GE
: fputs ("lt", file
); break;
5538 case LT
: fputs ("ge", file
); break;
5539 case LE
: fputs ("gt", file
); break;
5540 case GTU
: fputs ("leu", file
); break;
5541 case GEU
: fputs ("ltu", file
); break;
5542 case LTU
: fputs ("geu", file
); break;
5543 case LEU
: fputs ("gtu", file
); break;
5545 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op
);
5548 else if (letter
== 'F')
5551 case EQ
: fputs ("c1f", file
); break;
5552 case NE
: fputs ("c1t", file
); break;
5554 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op
);
5557 else if (letter
== 'W')
5560 case EQ
: fputs ("c1t", file
); break;
5561 case NE
: fputs ("c1f", file
); break;
5563 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op
);
5566 else if (letter
== 'h')
5568 if (GET_CODE (op
) == HIGH
)
5571 print_operand_reloc (file
, op
, mips_hi_relocs
);
5574 else if (letter
== 'R')
5575 print_operand_reloc (file
, op
, mips_lo_relocs
);
5577 else if (letter
== 'Y')
5579 if (GET_CODE (op
) == CONST_INT
5580 && ((unsigned HOST_WIDE_INT
) INTVAL (op
)
5581 < ARRAY_SIZE (mips_fp_conditions
)))
5582 fputs (mips_fp_conditions
[INTVAL (op
)], file
);
5584 output_operand_lossage ("invalid %%Y value");
5587 else if (letter
== 'Z')
5591 print_operand (file
, op
, 0);
5596 else if (letter
== 'q')
5601 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op
);
5603 regnum
= REGNO (op
);
5604 if (MD_REG_P (regnum
))
5605 fprintf (file
, "$ac0");
5606 else if (DSP_ACC_REG_P (regnum
))
5607 fprintf (file
, "$ac%c", reg_names
[regnum
][3]);
5609 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op
);
5612 else if (code
== REG
|| code
== SUBREG
)
5614 register int regnum
;
5617 regnum
= REGNO (op
);
5619 regnum
= true_regnum (op
);
5621 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
5622 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
5626 fprintf (file
, "%s", reg_names
[regnum
]);
5629 else if (code
== MEM
)
5632 output_address (plus_constant (XEXP (op
, 0), 4));
5634 output_address (XEXP (op
, 0));
5637 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
5638 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, 0xffff & INTVAL(op
));
5640 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
5641 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
5643 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
5644 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
5646 else if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
5647 fputs (reg_names
[GP_REG_FIRST
], file
);
5649 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
5650 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5652 else if (letter
== 'T' || letter
== 't')
5654 int truth
= (code
== NE
) == (letter
== 'T');
5655 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
5658 else if (CONST_GP_P (op
))
5659 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
5662 output_addr_const (file
, op
);
5666 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5667 RELOCS is the array of relocations to use. */
5670 print_operand_reloc (FILE *file
, rtx op
, const char **relocs
)
5672 enum mips_symbol_type symbol_type
;
5676 if (!mips_symbolic_constant_p (op
, &symbol_type
) || relocs
[symbol_type
] == 0)
5677 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op
);
5679 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5680 split_const (op
, &base
, &offset
);
5681 if (UNSPEC_ADDRESS_P (base
))
5682 op
= plus_constant (UNSPEC_ADDRESS (base
), INTVAL (offset
));
5684 fputs (relocs
[symbol_type
], file
);
5685 output_addr_const (file
, op
);
5686 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
5691 /* Output address operand X to FILE. */
5694 print_operand_address (FILE *file
, rtx x
)
5696 struct mips_address_info addr
;
5698 if (mips_classify_address (&addr
, x
, word_mode
, true))
5702 print_operand (file
, addr
.offset
, 0);
5703 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
5706 case ADDRESS_LO_SUM
:
5707 print_operand (file
, addr
.offset
, 'R');
5708 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
5711 case ADDRESS_CONST_INT
:
5712 output_addr_const (file
, x
);
5713 fprintf (file
, "(%s)", reg_names
[0]);
5716 case ADDRESS_SYMBOLIC
:
5717 output_addr_const (file
, x
);
5723 /* When using assembler macros, keep track of all of small-data externs
5724 so that mips_file_end can emit the appropriate declarations for them.
5726 In most cases it would be safe (though pointless) to emit .externs
5727 for other symbols too. One exception is when an object is within
5728 the -G limit but declared by the user to be in a section other
5729 than .sbss or .sdata. */
5732 mips_output_external (FILE *file
, tree decl
, const char *name
)
5734 default_elf_asm_output_external (file
, decl
, name
);
5736 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
5737 set in order to avoid putting out names that are never really
5739 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
5741 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
5743 fputs ("\t.extern\t", file
);
5744 assemble_name (file
, name
);
5745 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
5746 int_size_in_bytes (TREE_TYPE (decl
)));
5748 else if (TARGET_IRIX
5749 && mips_abi
== ABI_32
5750 && TREE_CODE (decl
) == FUNCTION_DECL
)
5752 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5753 `.global name .text' directive for every used but
5754 undefined function. If we don't, the linker may perform
5755 an optimization (skipping over the insns that set $gp)
5756 when it is unsafe. */
5757 fputs ("\t.globl ", file
);
5758 assemble_name (file
, name
);
5759 fputs (" .text\n", file
);
5764 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5765 put out a MIPS ECOFF file and a stab. */
5768 mips_output_filename (FILE *stream
, const char *name
)
5771 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5773 if (write_symbols
== DWARF2_DEBUG
)
5775 else if (mips_output_filename_first_time
)
5777 mips_output_filename_first_time
= 0;
5778 num_source_filenames
+= 1;
5779 current_function_file
= name
;
5780 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
5781 output_quoted_string (stream
, name
);
5782 putc ('\n', stream
);
5785 /* If we are emitting stabs, let dbxout.c handle this (except for
5786 the mips_output_filename_first_time case). */
5787 else if (write_symbols
== DBX_DEBUG
)
5790 else if (name
!= current_function_file
5791 && strcmp (name
, current_function_file
) != 0)
5793 num_source_filenames
+= 1;
5794 current_function_file
= name
;
5795 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
5796 output_quoted_string (stream
, name
);
5797 putc ('\n', stream
);
5801 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5802 that should be written before the opening quote, such as "\t.ascii\t"
5803 for real string data or "\t# " for a comment. */
5806 mips_output_ascii (FILE *stream
, const char *string_param
, size_t len
,
5811 register const unsigned char *string
=
5812 (const unsigned char *)string_param
;
5814 fprintf (stream
, "%s\"", prefix
);
5815 for (i
= 0; i
< len
; i
++)
5817 register int c
= string
[i
];
5821 if (c
== '\\' || c
== '\"')
5823 putc ('\\', stream
);
5831 fprintf (stream
, "\\%03o", c
);
5835 if (cur_pos
> 72 && i
+1 < len
)
5838 fprintf (stream
, "\"\n%s\"", prefix
);
5841 fprintf (stream
, "\"\n");
5844 /* Implement TARGET_ASM_FILE_START. */
5847 mips_file_start (void)
5849 default_file_start ();
5853 /* Generate a special section to describe the ABI switches used to
5854 produce the resultant binary. This used to be done by the assembler
5855 setting bits in the ELF header's flags field, but we have run out of
5856 bits. GDB needs this information in order to be able to correctly
5857 debug these binaries. See the function mips_gdbarch_init() in
5858 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5859 causes unnecessary IRIX 6 ld warnings. */
5860 const char * abi_string
= NULL
;
5864 case ABI_32
: abi_string
= "abi32"; break;
5865 case ABI_N32
: abi_string
= "abiN32"; break;
5866 case ABI_64
: abi_string
= "abi64"; break;
5867 case ABI_O64
: abi_string
= "abiO64"; break;
5868 case ABI_EABI
: abi_string
= TARGET_64BIT
? "eabi64" : "eabi32"; break;
5872 /* Note - we use fprintf directly rather than calling switch_to_section
5873 because in this way we can avoid creating an allocated section. We
5874 do not want this section to take up any space in the running
5876 fprintf (asm_out_file
, "\t.section .mdebug.%s\n", abi_string
);
5878 /* There is no ELF header flag to distinguish long32 forms of the
5879 EABI from long64 forms. Emit a special section to help tools
5880 such as GDB. Do the same for o64, which is sometimes used with
5882 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
5883 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n",
5884 TARGET_LONG64
? 64 : 32);
5886 /* Restore the default section. */
5887 fprintf (asm_out_file
, "\t.previous\n");
5890 /* Generate the pseudo ops that System V.4 wants. */
5891 if (TARGET_ABICALLS
)
5892 fprintf (asm_out_file
, "\t.abicalls\n");
5895 fprintf (asm_out_file
, "\t.set\tmips16\n");
5897 if (flag_verbose_asm
)
5898 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5900 mips_section_threshold
, mips_arch_info
->name
, mips_isa
);
5903 #ifdef BSS_SECTION_ASM_OP
5904 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5905 in the use of sbss. */
5908 mips_output_aligned_bss (FILE *stream
, tree decl
, const char *name
,
5909 unsigned HOST_WIDE_INT size
, int align
)
5911 extern tree last_assemble_variable_decl
;
5913 if (mips_in_small_data_p (decl
))
5914 switch_to_section (get_named_section (NULL
, ".sbss", 0));
5916 switch_to_section (bss_section
);
5917 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
5918 last_assemble_variable_decl
= decl
;
5919 ASM_DECLARE_OBJECT_NAME (stream
, name
, decl
);
5920 ASM_OUTPUT_SKIP (stream
, size
!= 0 ? size
: 1);
5924 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5925 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5928 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
5929 unsigned HOST_WIDE_INT size
,
5932 /* If the target wants uninitialized const declarations in
5933 .rdata then don't put them in .comm. */
5934 if (TARGET_EMBEDDED_DATA
&& TARGET_UNINIT_CONST_IN_RODATA
5935 && TREE_CODE (decl
) == VAR_DECL
&& TREE_READONLY (decl
)
5936 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
5938 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
5939 targetm
.asm_out
.globalize_label (stream
, name
);
5941 switch_to_section (readonly_data_section
);
5942 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
5943 mips_declare_object (stream
, name
, "",
5944 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
5948 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
5952 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5953 NAME is the name of the object and ALIGN is the required alignment
5954 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5955 alignment argument. */
5958 mips_declare_common_object (FILE *stream
, const char *name
,
5959 const char *init_string
,
5960 unsigned HOST_WIDE_INT size
,
5961 unsigned int align
, bool takes_alignment_p
)
5963 if (!takes_alignment_p
)
5965 size
+= (align
/ BITS_PER_UNIT
) - 1;
5966 size
-= size
% (align
/ BITS_PER_UNIT
);
5967 mips_declare_object (stream
, name
, init_string
,
5968 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
5971 mips_declare_object (stream
, name
, init_string
,
5972 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
5973 size
, align
/ BITS_PER_UNIT
);
5976 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5977 macros, mark the symbol as written so that mips_file_end won't emit an
5978 .extern for it. STREAM is the output file, NAME is the name of the
5979 symbol, INIT_STRING is the string that should be written before the
5980 symbol and FINAL_STRING is the string that should be written after it.
5981 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5984 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
5985 const char *final_string
, ...)
5989 fputs (init_string
, stream
);
5990 assemble_name (stream
, name
);
5991 va_start (ap
, final_string
);
5992 vfprintf (stream
, final_string
, ap
);
5995 if (!TARGET_EXPLICIT_RELOCS
)
5997 tree name_tree
= get_identifier (name
);
5998 TREE_ASM_WRITTEN (name_tree
) = 1;
6002 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6003 extern int size_directive_output
;
6005 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6006 definitions except that it uses mips_declare_object() to emit the label. */
6009 mips_declare_object_name (FILE *stream
, const char *name
,
6010 tree decl ATTRIBUTE_UNUSED
)
6012 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6013 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
6016 size_directive_output
= 0;
6017 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
6021 size_directive_output
= 1;
6022 size
= int_size_in_bytes (TREE_TYPE (decl
));
6023 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
6026 mips_declare_object (stream
, name
, "", ":\n");
6029 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6032 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
6036 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
6037 if (!flag_inhibit_size_directive
6038 && DECL_SIZE (decl
) != 0
6039 && !at_end
&& top_level
6040 && DECL_INITIAL (decl
) == error_mark_node
6041 && !size_directive_output
)
6045 size_directive_output
= 1;
6046 size
= int_size_in_bytes (TREE_TYPE (decl
));
6047 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
6052 /* Return true if X is a small data address that can be rewritten
6056 mips_rewrite_small_data_p (rtx x
)
6058 enum mips_symbol_type symbol_type
;
6060 return (TARGET_EXPLICIT_RELOCS
6061 && mips_symbolic_constant_p (x
, &symbol_type
)
6062 && symbol_type
== SYMBOL_SMALL_DATA
);
6066 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6069 mips_small_data_pattern_1 (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
6071 if (GET_CODE (*loc
) == LO_SUM
)
6074 return mips_rewrite_small_data_p (*loc
);
6077 /* Return true if OP refers to small data symbols directly, not through
6081 mips_small_data_pattern_p (rtx op
)
6083 return for_each_rtx (&op
, mips_small_data_pattern_1
, 0);
6086 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6089 mips_rewrite_small_data_1 (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
6091 if (mips_rewrite_small_data_p (*loc
))
6092 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
6094 if (GET_CODE (*loc
) == LO_SUM
)
6100 /* If possible, rewrite OP so that it refers to small data using
6101 explicit relocations. */
6104 mips_rewrite_small_data (rtx op
)
6106 op
= copy_insn (op
);
6107 for_each_rtx (&op
, mips_rewrite_small_data_1
, 0);
6111 /* Return true if the current function has an insn that implicitly
6115 mips_function_has_gp_insn (void)
6117 /* Don't bother rechecking if we found one last time. */
6118 if (!cfun
->machine
->has_gp_insn_p
)
6122 push_topmost_sequence ();
6123 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6125 && GET_CODE (PATTERN (insn
)) != USE
6126 && GET_CODE (PATTERN (insn
)) != CLOBBER
6127 && (get_attr_got (insn
) != GOT_UNSET
6128 || small_data_pattern (PATTERN (insn
), VOIDmode
)))
6130 pop_topmost_sequence ();
6132 cfun
->machine
->has_gp_insn_p
= (insn
!= 0);
6134 return cfun
->machine
->has_gp_insn_p
;
6138 /* Return the register that should be used as the global pointer
6139 within this function. Return 0 if the function doesn't need
6140 a global pointer. */
6143 mips_global_pointer (void)
6147 /* $gp is always available in non-abicalls code. */
6148 if (!TARGET_ABICALLS
)
6149 return GLOBAL_POINTER_REGNUM
;
6151 /* We must always provide $gp when it is used implicitly. */
6152 if (!TARGET_EXPLICIT_RELOCS
)
6153 return GLOBAL_POINTER_REGNUM
;
6155 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6157 if (current_function_profile
)
6158 return GLOBAL_POINTER_REGNUM
;
6160 /* If the function has a nonlocal goto, $gp must hold the correct
6161 global pointer for the target function. */
6162 if (current_function_has_nonlocal_goto
)
6163 return GLOBAL_POINTER_REGNUM
;
6165 /* If the gp is never referenced, there's no need to initialize it.
6166 Note that reload can sometimes introduce constant pool references
6167 into a function that otherwise didn't need them. For example,
6168 suppose we have an instruction like:
6170 (set (reg:DF R1) (float:DF (reg:SI R2)))
6172 If R2 turns out to be constant such as 1, the instruction may have a
6173 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6174 using this constant if R2 doesn't get allocated to a register.
6176 In cases like these, reload will have added the constant to the pool
6177 but no instruction will yet refer to it. */
6178 if (!regs_ever_live
[GLOBAL_POINTER_REGNUM
]
6179 && !current_function_uses_const_pool
6180 && !mips_function_has_gp_insn ())
6183 /* We need a global pointer, but perhaps we can use a call-clobbered
6184 register instead of $gp. */
6185 if (TARGET_NEWABI
&& current_function_is_leaf
)
6186 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
6187 if (!regs_ever_live
[regno
]
6188 && call_used_regs
[regno
]
6189 && !fixed_regs
[regno
]
6190 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
6193 return GLOBAL_POINTER_REGNUM
;
6197 /* Return true if the current function must save REGNO. */
6200 mips_save_reg_p (unsigned int regno
)
6202 /* We only need to save $gp for NewABI PIC. */
6203 if (regno
== GLOBAL_POINTER_REGNUM
)
6204 return (TARGET_ABICALLS
&& TARGET_NEWABI
6205 && cfun
->machine
->global_pointer
== regno
);
6207 /* Check call-saved registers. */
6208 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6211 /* We need to save the old frame pointer before setting up a new one. */
6212 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
6215 /* We need to save the incoming return address if it is ever clobbered
6216 within the function. */
6217 if (regno
== GP_REG_FIRST
+ 31 && regs_ever_live
[regno
])
6224 return_type
= DECL_RESULT (current_function_decl
);
6226 /* $18 is a special case in mips16 code. It may be used to call
6227 a function which returns a floating point value, but it is
6228 marked in call_used_regs. */
6229 if (regno
== GP_REG_FIRST
+ 18 && regs_ever_live
[regno
])
6232 /* $31 is also a special case. It will be used to copy a return
6233 value into the floating point registers if the return value is
6235 if (regno
== GP_REG_FIRST
+ 31
6236 && mips16_hard_float
6237 && !aggregate_value_p (return_type
, current_function_decl
)
6238 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
6239 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
6247 /* Return the bytes needed to compute the frame pointer from the current
6248 stack pointer. SIZE is the size (in bytes) of the local variables.
6250 MIPS stack frames look like:
6252 Before call After call
6253 +-----------------------+ +-----------------------+
6256 | caller's temps. | | caller's temps. |
6258 +-----------------------+ +-----------------------+
6260 | arguments on stack. | | arguments on stack. |
6262 +-----------------------+ +-----------------------+
6263 | 4 words to save | | 4 words to save |
6264 | arguments passed | | arguments passed |
6265 | in registers, even | | in registers, even |
6266 SP->| if not passed. | VFP->| if not passed. |
6267 +-----------------------+ +-----------------------+
6269 | fp register save |
6271 +-----------------------+
6273 | gp register save |
6275 +-----------------------+
6279 +-----------------------+
6281 | alloca allocations |
6283 +-----------------------+
6285 | GP save for V.4 abi |
6287 +-----------------------+
6289 | arguments on stack |
6291 +-----------------------+
6293 | arguments passed |
6294 | in registers, even |
6295 low SP->| if not passed. |
6296 memory +-----------------------+
6301 compute_frame_size (HOST_WIDE_INT size
)
6304 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
6305 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
6306 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
6307 HOST_WIDE_INT cprestore_size
; /* # bytes that the cprestore slot takes up */
6308 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
6309 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
6310 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
6311 unsigned int mask
; /* mask of saved gp registers */
6312 unsigned int fmask
; /* mask of saved fp registers */
6314 cfun
->machine
->global_pointer
= mips_global_pointer ();
6320 var_size
= MIPS_STACK_ALIGN (size
);
6321 args_size
= current_function_outgoing_args_size
;
6322 cprestore_size
= MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET
) - args_size
;
6324 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6325 functions. If the function has local variables, we're committed
6326 to allocating it anyway. Otherwise reclaim it here. */
6327 if (var_size
== 0 && current_function_is_leaf
)
6328 cprestore_size
= args_size
= 0;
6330 /* The MIPS 3.0 linker does not like functions that dynamically
6331 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6332 looks like we are trying to create a second frame pointer to the
6333 function, so allocate some stack space to make it happy. */
6335 if (args_size
== 0 && current_function_calls_alloca
)
6336 args_size
= 4 * UNITS_PER_WORD
;
6338 total_size
= var_size
+ args_size
+ cprestore_size
;
6340 /* Calculate space needed for gp registers. */
6341 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
6342 if (mips_save_reg_p (regno
))
6344 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6345 mask
|= 1 << (regno
- GP_REG_FIRST
);
6348 /* We need to restore these for the handler. */
6349 if (current_function_calls_eh_return
)
6354 regno
= EH_RETURN_DATA_REGNO (i
);
6355 if (regno
== INVALID_REGNUM
)
6357 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6358 mask
|= 1 << (regno
- GP_REG_FIRST
);
6362 /* This loop must iterate over the same space as its companion in
6363 save_restore_insns. */
6364 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
6365 regno
>= FP_REG_FIRST
;
6368 if (mips_save_reg_p (regno
))
6370 fp_reg_size
+= FP_INC
* UNITS_PER_FPREG
;
6371 fmask
|= ((1 << FP_INC
) - 1) << (regno
- FP_REG_FIRST
);
6375 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6376 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
6378 /* Add in the space required for saving incoming register arguments. */
6379 total_size
+= current_function_pretend_args_size
;
6380 total_size
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
6382 /* Save other computed information. */
6383 cfun
->machine
->frame
.total_size
= total_size
;
6384 cfun
->machine
->frame
.var_size
= var_size
;
6385 cfun
->machine
->frame
.args_size
= args_size
;
6386 cfun
->machine
->frame
.cprestore_size
= cprestore_size
;
6387 cfun
->machine
->frame
.gp_reg_size
= gp_reg_size
;
6388 cfun
->machine
->frame
.fp_reg_size
= fp_reg_size
;
6389 cfun
->machine
->frame
.mask
= mask
;
6390 cfun
->machine
->frame
.fmask
= fmask
;
6391 cfun
->machine
->frame
.initialized
= reload_completed
;
6392 cfun
->machine
->frame
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
6393 cfun
->machine
->frame
.num_fp
= fp_reg_size
/ (FP_INC
* UNITS_PER_FPREG
);
6397 HOST_WIDE_INT offset
;
6399 offset
= (args_size
+ cprestore_size
+ var_size
6400 + gp_reg_size
- GET_MODE_SIZE (gpr_mode
));
6401 cfun
->machine
->frame
.gp_sp_offset
= offset
;
6402 cfun
->machine
->frame
.gp_save_offset
= offset
- total_size
;
6406 cfun
->machine
->frame
.gp_sp_offset
= 0;
6407 cfun
->machine
->frame
.gp_save_offset
= 0;
6412 HOST_WIDE_INT offset
;
6414 offset
= (args_size
+ cprestore_size
+ var_size
6415 + gp_reg_rounded
+ fp_reg_size
6416 - FP_INC
* UNITS_PER_FPREG
);
6417 cfun
->machine
->frame
.fp_sp_offset
= offset
;
6418 cfun
->machine
->frame
.fp_save_offset
= offset
- total_size
;
6422 cfun
->machine
->frame
.fp_sp_offset
= 0;
6423 cfun
->machine
->frame
.fp_save_offset
= 0;
6426 /* Ok, we're done. */
6430 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6431 pointer or argument pointer. TO is either the stack pointer or
6432 hard frame pointer. */
6435 mips_initial_elimination_offset (int from
, int to
)
6437 HOST_WIDE_INT offset
;
6439 compute_frame_size (get_frame_size ());
6441 /* Set OFFSET to the offset from the stack pointer. */
6444 case FRAME_POINTER_REGNUM
:
6448 case ARG_POINTER_REGNUM
:
6449 offset
= (cfun
->machine
->frame
.total_size
6450 - current_function_pretend_args_size
);
6457 if (TARGET_MIPS16
&& to
== HARD_FRAME_POINTER_REGNUM
)
6458 offset
-= cfun
->machine
->frame
.args_size
;
6463 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6464 back to a previous frame. */
6466 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
6471 return get_hard_reg_initial_val (Pmode
, GP_REG_FIRST
+ 31);
6474 /* Use FN to save or restore register REGNO. MODE is the register's
6475 mode and OFFSET is the offset of its save slot from the current
6479 mips_save_restore_reg (enum machine_mode mode
, int regno
,
6480 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
6484 mem
= gen_frame_mem (mode
, plus_constant (stack_pointer_rtx
, offset
));
6486 fn (gen_rtx_REG (mode
, regno
), mem
);
6490 /* Call FN for each register that is saved by the current function.
6491 SP_OFFSET is the offset of the current stack pointer from the start
6495 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
6497 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6499 enum machine_mode fpr_mode
;
6500 HOST_WIDE_INT offset
;
6503 /* Save registers starting from high to low. The debuggers prefer at least
6504 the return register be stored at func+4, and also it allows us not to
6505 need a nop in the epilogue if at least one register is reloaded in
6506 addition to return address. */
6507 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
6508 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
6509 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
6511 mips_save_restore_reg (gpr_mode
, regno
, offset
, fn
);
6512 offset
-= GET_MODE_SIZE (gpr_mode
);
6515 /* This loop must iterate over the same space as its companion in
6516 compute_frame_size. */
6517 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
6518 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
6519 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
6520 regno
>= FP_REG_FIRST
;
6522 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
6524 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
6525 offset
-= GET_MODE_SIZE (fpr_mode
);
6530 /* If we're generating n32 or n64 abicalls, and the current function
6531 does not use $28 as its global pointer, emit a cplocal directive.
6532 Use pic_offset_table_rtx as the argument to the directive. */
6535 mips_output_cplocal (void)
6537 if (!TARGET_EXPLICIT_RELOCS
6538 && cfun
->machine
->global_pointer
> 0
6539 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
6540 output_asm_insn (".cplocal %+", 0);
6543 /* Return the style of GP load sequence that is being used for the
6544 current function. */
6546 enum mips_loadgp_style
6547 mips_current_loadgp_style (void)
6549 if (!TARGET_ABICALLS
|| cfun
->machine
->global_pointer
== 0)
6552 if (TARGET_ABSOLUTE_ABICALLS
)
6553 return LOADGP_ABSOLUTE
;
6555 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
6558 /* The __gnu_local_gp symbol. */
6560 static GTY(()) rtx mips_gnu_local_gp
;
6562 /* If we're generating n32 or n64 abicalls, emit instructions
6563 to set up the global pointer. */
6566 mips_emit_loadgp (void)
6568 rtx addr
, offset
, incoming_address
;
6570 switch (mips_current_loadgp_style ())
6572 case LOADGP_ABSOLUTE
:
6573 if (mips_gnu_local_gp
== NULL
)
6575 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
6576 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
6578 emit_insn (gen_loadgp_noshared (mips_gnu_local_gp
));
6582 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
6583 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
6584 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
6585 emit_insn (gen_loadgp (offset
, incoming_address
));
6586 if (!TARGET_EXPLICIT_RELOCS
)
6587 emit_insn (gen_loadgp_blockage ());
6595 /* Set up the stack and frame (if desired) for the function. */
6598 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
6601 HOST_WIDE_INT tsize
= cfun
->machine
->frame
.total_size
;
6603 #ifdef SDB_DEBUGGING_INFO
6604 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
6605 SDB_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
6608 /* In mips16 mode, we may need to generate a 32 bit to handle
6609 floating point arguments. The linker will arrange for any 32-bit
6610 functions to call this stub, which will then jump to the 16-bit
6612 if (TARGET_MIPS16
&& !TARGET_SOFT_FLOAT
6613 && current_function_args_info
.fp_code
!= 0)
6614 build_mips16_function_stub (file
);
6616 if (!FUNCTION_NAME_ALREADY_DECLARED
)
6618 /* Get the function name the same way that toplev.c does before calling
6619 assemble_start_function. This is needed so that the name used here
6620 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6621 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
6623 if (!flag_inhibit_size_directive
)
6625 fputs ("\t.ent\t", file
);
6626 assemble_name (file
, fnname
);
6630 assemble_name (file
, fnname
);
6631 fputs (":\n", file
);
6634 /* Stop mips_file_end from treating this function as external. */
6635 if (TARGET_IRIX
&& mips_abi
== ABI_32
)
6636 TREE_ASM_WRITTEN (DECL_NAME (cfun
->decl
)) = 1;
6638 if (!flag_inhibit_size_directive
)
6640 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6642 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
6643 "# vars= " HOST_WIDE_INT_PRINT_DEC
", regs= %d/%d"
6644 ", args= " HOST_WIDE_INT_PRINT_DEC
6645 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
6646 (reg_names
[(frame_pointer_needed
)
6647 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
6648 ((frame_pointer_needed
&& TARGET_MIPS16
)
6649 ? tsize
- cfun
->machine
->frame
.args_size
6651 reg_names
[GP_REG_FIRST
+ 31],
6652 cfun
->machine
->frame
.var_size
,
6653 cfun
->machine
->frame
.num_gp
,
6654 cfun
->machine
->frame
.num_fp
,
6655 cfun
->machine
->frame
.args_size
,
6656 cfun
->machine
->frame
.cprestore_size
);
6658 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6659 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
6660 cfun
->machine
->frame
.mask
,
6661 cfun
->machine
->frame
.gp_save_offset
);
6662 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
6663 cfun
->machine
->frame
.fmask
,
6664 cfun
->machine
->frame
.fp_save_offset
);
6667 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6668 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6671 if (mips_current_loadgp_style () == LOADGP_OLDABI
)
6673 /* Handle the initialization of $gp for SVR4 PIC. */
6674 if (!cfun
->machine
->all_noreorder_p
)
6675 output_asm_insn ("%(.cpload\t%^%)", 0);
6677 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6679 else if (cfun
->machine
->all_noreorder_p
)
6680 output_asm_insn ("%(%<", 0);
6682 /* Tell the assembler which register we're using as the global
6683 pointer. This is needed for thunks, since they can use either
6684 explicit relocs or assembler macros. */
6685 mips_output_cplocal ();
6688 /* Make the last instruction frame related and note that it performs
6689 the operation described by FRAME_PATTERN. */
6692 mips_set_frame_expr (rtx frame_pattern
)
6696 insn
= get_last_insn ();
6697 RTX_FRAME_RELATED_P (insn
) = 1;
6698 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6704 /* Return a frame-related rtx that stores REG at MEM.
6705 REG must be a single register. */
6708 mips_frame_set (rtx mem
, rtx reg
)
6712 /* If we're saving the return address register and the dwarf return
6713 address column differs from the hard register number, adjust the
6714 note reg to refer to the former. */
6715 if (REGNO (reg
) == GP_REG_FIRST
+ 31
6716 && DWARF_FRAME_RETURN_COLUMN
!= GP_REG_FIRST
+ 31)
6717 reg
= gen_rtx_REG (GET_MODE (reg
), DWARF_FRAME_RETURN_COLUMN
);
6719 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
6720 RTX_FRAME_RELATED_P (set
) = 1;
6726 /* Save register REG to MEM. Make the instruction frame-related. */
6729 mips_save_reg (rtx reg
, rtx mem
)
6731 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
6735 if (mips_split_64bit_move_p (mem
, reg
))
6736 mips_split_64bit_move (mem
, reg
);
6738 emit_move_insn (mem
, reg
);
6740 x1
= mips_frame_set (mips_subword (mem
, 0), mips_subword (reg
, 0));
6741 x2
= mips_frame_set (mips_subword (mem
, 1), mips_subword (reg
, 1));
6742 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
6747 && REGNO (reg
) != GP_REG_FIRST
+ 31
6748 && !M16_REG_P (REGNO (reg
)))
6750 /* Save a non-mips16 register by moving it through a temporary.
6751 We don't need to do this for $31 since there's a special
6752 instruction for it. */
6753 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg
)), reg
);
6754 emit_move_insn (mem
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
6757 emit_move_insn (mem
, reg
);
6759 mips_set_frame_expr (mips_frame_set (mem
, reg
));
6764 /* Expand the prologue into a bunch of separate insns. */
6767 mips_expand_prologue (void)
6771 if (cfun
->machine
->global_pointer
> 0)
6772 REGNO (pic_offset_table_rtx
) = cfun
->machine
->global_pointer
;
6774 size
= compute_frame_size (get_frame_size ());
6776 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6777 bytes beforehand; this is enough to cover the register save area
6778 without going out of range. */
6779 if ((cfun
->machine
->frame
.mask
| cfun
->machine
->frame
.fmask
) != 0)
6781 HOST_WIDE_INT step1
;
6783 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
6784 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
6786 GEN_INT (-step1
)))) = 1;
6788 mips_for_each_saved_reg (size
, mips_save_reg
);
6791 /* Allocate the rest of the frame. */
6794 if (SMALL_OPERAND (-size
))
6795 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
6797 GEN_INT (-size
)))) = 1;
6800 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
6803 /* There are no instructions to add or subtract registers
6804 from the stack pointer, so use the frame pointer as a
6805 temporary. We should always be using a frame pointer
6806 in this case anyway. */
6807 gcc_assert (frame_pointer_needed
);
6808 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
6809 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
6810 hard_frame_pointer_rtx
,
6811 MIPS_PROLOGUE_TEMP (Pmode
)));
6812 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
6815 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
6817 MIPS_PROLOGUE_TEMP (Pmode
)));
6819 /* Describe the combined effect of the previous instructions. */
6821 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
6822 plus_constant (stack_pointer_rtx
, -size
)));
6826 /* Set up the frame pointer, if we're using one. In mips16 code,
6827 we point the frame pointer ahead of the outgoing argument area.
6828 This should allow more variables & incoming arguments to be
6829 accessed with unextended instructions. */
6830 if (frame_pointer_needed
)
6832 if (TARGET_MIPS16
&& cfun
->machine
->frame
.args_size
!= 0)
6834 rtx offset
= GEN_INT (cfun
->machine
->frame
.args_size
);
6835 if (SMALL_OPERAND (cfun
->machine
->frame
.args_size
))
6837 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
6842 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode
), offset
);
6843 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
6844 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
6845 hard_frame_pointer_rtx
,
6846 MIPS_PROLOGUE_TEMP (Pmode
)));
6848 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
6849 plus_constant (stack_pointer_rtx
,
6850 cfun
->machine
->frame
.args_size
)));
6854 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx
,
6855 stack_pointer_rtx
)) = 1;
6858 mips_emit_loadgp ();
6860 /* If generating o32/o64 abicalls, save $gp on the stack. */
6861 if (TARGET_ABICALLS
&& !TARGET_NEWABI
&& !current_function_is_leaf
)
6862 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size
)));
6864 /* If we are profiling, make sure no instructions are scheduled before
6865 the call to mcount. */
6867 if (current_function_profile
)
6868 emit_insn (gen_blockage ());
6871 /* Do any necessary cleanup after a function to restore stack, frame,
6874 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6877 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
6878 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
6880 /* Reinstate the normal $gp. */
6881 REGNO (pic_offset_table_rtx
) = GLOBAL_POINTER_REGNUM
;
6882 mips_output_cplocal ();
6884 if (cfun
->machine
->all_noreorder_p
)
6886 /* Avoid using %>%) since it adds excess whitespace. */
6887 output_asm_insn (".set\tmacro", 0);
6888 output_asm_insn (".set\treorder", 0);
6889 set_noreorder
= set_nomacro
= 0;
6892 if (!FUNCTION_NAME_ALREADY_DECLARED
&& !flag_inhibit_size_directive
)
6896 /* Get the function name the same way that toplev.c does before calling
6897 assemble_start_function. This is needed so that the name used here
6898 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6899 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
6900 fputs ("\t.end\t", file
);
6901 assemble_name (file
, fnname
);
6906 /* Emit instructions to restore register REG from slot MEM. */
6909 mips_restore_reg (rtx reg
, rtx mem
)
6911 /* There's no mips16 instruction to load $31 directly. Load into
6912 $7 instead and adjust the return insn appropriately. */
6913 if (TARGET_MIPS16
&& REGNO (reg
) == GP_REG_FIRST
+ 31)
6914 reg
= gen_rtx_REG (GET_MODE (reg
), 7);
6916 if (TARGET_MIPS16
&& !M16_REG_P (REGNO (reg
)))
6918 /* Can't restore directly; move through a temporary. */
6919 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg
)), mem
);
6920 emit_move_insn (reg
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
6923 emit_move_insn (reg
, mem
);
6927 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6928 if this epilogue precedes a sibling call, false if it is for a normal
6929 "epilogue" pattern. */
6932 mips_expand_epilogue (int sibcall_p
)
6934 HOST_WIDE_INT step1
, step2
;
6937 if (!sibcall_p
&& mips_can_use_return_insn ())
6939 emit_jump_insn (gen_return ());
6943 /* Split the frame into two. STEP1 is the amount of stack we should
6944 deallocate before restoring the registers. STEP2 is the amount we
6945 should deallocate afterwards.
6947 Start off by assuming that no registers need to be restored. */
6948 step1
= cfun
->machine
->frame
.total_size
;
6951 /* Work out which register holds the frame address. Account for the
6952 frame pointer offset used by mips16 code. */
6953 if (!frame_pointer_needed
)
6954 base
= stack_pointer_rtx
;
6957 base
= hard_frame_pointer_rtx
;
6959 step1
-= cfun
->machine
->frame
.args_size
;
6962 /* If we need to restore registers, deallocate as much stack as
6963 possible in the second step without going out of range. */
6964 if ((cfun
->machine
->frame
.mask
| cfun
->machine
->frame
.fmask
) != 0)
6966 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
6970 /* Set TARGET to BASE + STEP1. */
6976 /* Get an rtx for STEP1 that we can add to BASE. */
6977 adjust
= GEN_INT (step1
);
6978 if (!SMALL_OPERAND (step1
))
6980 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
6981 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
6984 /* Normal mode code can copy the result straight into $sp. */
6986 target
= stack_pointer_rtx
;
6988 emit_insn (gen_add3_insn (target
, base
, adjust
));
6991 /* Copy TARGET into the stack pointer. */
6992 if (target
!= stack_pointer_rtx
)
6993 emit_move_insn (stack_pointer_rtx
, target
);
6995 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6996 implicitly used by all SYMBOL_REFs. We must emit a blockage
6997 insn before restoring it. */
6998 if (TARGET_ABICALLS
&& TARGET_NEWABI
&& !TARGET_EXPLICIT_RELOCS
)
6999 emit_insn (gen_blockage ());
7001 /* Restore the registers. */
7002 mips_for_each_saved_reg (cfun
->machine
->frame
.total_size
- step2
,
7005 /* Deallocate the final bit of the frame. */
7007 emit_insn (gen_add3_insn (stack_pointer_rtx
,
7011 /* Add in the __builtin_eh_return stack adjustment. We need to
7012 use a temporary in mips16 code. */
7013 if (current_function_calls_eh_return
)
7017 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
7018 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
7019 MIPS_EPILOGUE_TEMP (Pmode
),
7020 EH_RETURN_STACKADJ_RTX
));
7021 emit_move_insn (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
7024 emit_insn (gen_add3_insn (stack_pointer_rtx
,
7026 EH_RETURN_STACKADJ_RTX
));
7031 /* The mips16 loads the return address into $7, not $31. */
7032 if (TARGET_MIPS16
&& (cfun
->machine
->frame
.mask
& RA_MASK
) != 0)
7033 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
,
7034 GP_REG_FIRST
+ 7)));
7036 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
,
7037 GP_REG_FIRST
+ 31)));
7041 /* Return nonzero if this function is known to have a null epilogue.
7042 This allows the optimizer to omit jumps to jumps if no stack
7046 mips_can_use_return_insn (void)
7050 if (! reload_completed
)
7053 if (regs_ever_live
[31] || current_function_profile
)
7056 return_type
= DECL_RESULT (current_function_decl
);
7058 /* In mips16 mode, a function which returns a floating point value
7059 needs to arrange to copy the return value into the floating point
7062 && mips16_hard_float
7063 && ! aggregate_value_p (return_type
, current_function_decl
)
7064 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
7065 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
7068 if (cfun
->machine
->frame
.initialized
)
7069 return cfun
->machine
->frame
.total_size
== 0;
7071 return compute_frame_size (get_frame_size ()) == 0;
7074 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7075 in order to avoid duplicating too much logic from elsewhere. */
7078 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
7079 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
7082 rtx
this, temp1
, temp2
, insn
, fnaddr
;
7084 /* Pretend to be a post-reload pass while generating rtl. */
7086 reload_completed
= 1;
7087 reset_block_changes ();
7089 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7090 for TARGET_NEWABI since the latter is a call-saved register. */
7091 if (TARGET_ABICALLS
)
7092 cfun
->machine
->global_pointer
7093 = REGNO (pic_offset_table_rtx
)
7094 = TARGET_NEWABI
? 15 : GLOBAL_POINTER_REGNUM
;
7096 /* Set up the global pointer for n32 or n64 abicalls. */
7097 mips_emit_loadgp ();
7099 /* We need two temporary registers in some cases. */
7100 temp1
= gen_rtx_REG (Pmode
, 2);
7101 temp2
= gen_rtx_REG (Pmode
, 3);
7103 /* Find out which register contains the "this" pointer. */
7104 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
7105 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
7107 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
7109 /* Add DELTA to THIS. */
7112 rtx offset
= GEN_INT (delta
);
7113 if (!SMALL_OPERAND (delta
))
7115 emit_move_insn (temp1
, offset
);
7118 emit_insn (gen_add3_insn (this, this, offset
));
7121 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7122 if (vcall_offset
!= 0)
7126 /* Set TEMP1 to *THIS. */
7127 emit_move_insn (temp1
, gen_rtx_MEM (Pmode
, this));
7129 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7130 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
7132 /* Load the offset and add it to THIS. */
7133 emit_move_insn (temp1
, gen_rtx_MEM (Pmode
, addr
));
7134 emit_insn (gen_add3_insn (this, this, temp1
));
7137 /* Jump to the target function. Use a sibcall if direct jumps are
7138 allowed, otherwise load the address into a register first. */
7139 fnaddr
= XEXP (DECL_RTL (function
), 0);
7140 if (TARGET_MIPS16
|| TARGET_ABICALLS
|| TARGET_LONG_CALLS
)
7142 /* This is messy. gas treats "la $25,foo" as part of a call
7143 sequence and may allow a global "foo" to be lazily bound.
7144 The general move patterns therefore reject this combination.
7146 In this context, lazy binding would actually be OK for o32 and o64,
7147 but it's still wrong for n32 and n64; see mips_load_call_address.
7148 We must therefore load the address via a temporary register if
7149 mips_dangerous_for_la25_p.
7151 If we jump to the temporary register rather than $25, the assembler
7152 can use the move insn to fill the jump's delay slot. */
7153 if (TARGET_ABICALLS
&& !mips_dangerous_for_la25_p (fnaddr
))
7154 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
7155 mips_load_call_address (temp1
, fnaddr
, true);
7157 if (TARGET_ABICALLS
&& REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
7158 emit_move_insn (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
7159 emit_jump_insn (gen_indirect_jump (temp1
));
7163 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
7164 SIBLING_CALL_P (insn
) = 1;
7167 /* Run just enough of rest_of_compilation. This sequence was
7168 "borrowed" from alpha.c. */
7169 insn
= get_insns ();
7170 insn_locators_initialize ();
7171 split_all_insns_noflow ();
7173 mips16_lay_out_constants ();
7174 shorten_branches (insn
);
7175 final_start_function (insn
, file
, 1);
7176 final (insn
, file
, 1);
7177 final_end_function ();
7179 /* Clean up the vars set above. Note that final_end_function resets
7180 the global pointer for us. */
7181 reload_completed
= 0;
7185 /* Returns nonzero if X contains a SYMBOL_REF. */
7188 symbolic_expression_p (rtx x
)
7190 if (GET_CODE (x
) == SYMBOL_REF
)
7193 if (GET_CODE (x
) == CONST
)
7194 return symbolic_expression_p (XEXP (x
, 0));
7197 return symbolic_expression_p (XEXP (x
, 0));
7199 if (ARITHMETIC_P (x
))
7200 return (symbolic_expression_p (XEXP (x
, 0))
7201 || symbolic_expression_p (XEXP (x
, 1)));
7206 /* Choose the section to use for the constant rtx expression X that has
7210 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
7211 unsigned HOST_WIDE_INT align
)
7215 /* In mips16 mode, the constant table always goes in the same section
7216 as the function, so that constants can be loaded using PC relative
7218 return function_section (current_function_decl
);
7220 else if (TARGET_EMBEDDED_DATA
)
7222 /* For embedded applications, always put constants in read-only data,
7223 in order to reduce RAM usage. */
7224 return mergeable_constant_section (mode
, align
, 0);
7228 /* For hosted applications, always put constants in small data if
7229 possible, as this gives the best performance. */
7230 /* ??? Consider using mergeable small data sections. */
7232 if (GET_MODE_SIZE (mode
) <= (unsigned) mips_section_threshold
7233 && mips_section_threshold
> 0)
7234 return get_named_section (NULL
, ".sdata", 0);
7235 else if (flag_pic
&& symbolic_expression_p (x
))
7236 return get_named_section (NULL
, ".data.rel.ro", 3);
7238 return mergeable_constant_section (mode
, align
, 0);
7242 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7244 The complication here is that, with the combination TARGET_ABICALLS
7245 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7246 therefore not be included in the read-only part of a DSO. Handle such
7247 cases by selecting a normal data section instead of a read-only one.
7248 The logic apes that in default_function_rodata_section. */
7251 mips_function_rodata_section (tree decl
)
7253 if (!TARGET_ABICALLS
|| TARGET_GPWORD
)
7254 return default_function_rodata_section (decl
);
7256 if (decl
&& DECL_SECTION_NAME (decl
))
7258 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7259 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
7261 char *rname
= ASTRDUP (name
);
7263 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
7265 else if (flag_function_sections
&& flag_data_sections
7266 && strncmp (name
, ".text.", 6) == 0)
7268 char *rname
= ASTRDUP (name
);
7269 memcpy (rname
+ 1, "data", 4);
7270 return get_section (rname
, SECTION_WRITE
, decl
);
7273 return data_section
;
7276 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
7277 locally-defined objects go in a small data section. It also controls
7278 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
7279 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
7282 mips_in_small_data_p (tree decl
)
7286 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
7289 /* We don't yet generate small-data references for -mabicalls. See related
7290 -G handling in override_options. */
7291 if (TARGET_ABICALLS
)
7294 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
7298 /* Reject anything that isn't in a known small-data section. */
7299 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7300 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
7303 /* If a symbol is defined externally, the assembler will use the
7304 usual -G rules when deciding how to implement macros. */
7305 if (TARGET_EXPLICIT_RELOCS
|| !DECL_EXTERNAL (decl
))
7308 else if (TARGET_EMBEDDED_DATA
)
7310 /* Don't put constants into the small data section: we want them
7311 to be in ROM rather than RAM. */
7312 if (TREE_CODE (decl
) != VAR_DECL
)
7315 if (TREE_READONLY (decl
)
7316 && !TREE_SIDE_EFFECTS (decl
)
7317 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
7321 size
= int_size_in_bytes (TREE_TYPE (decl
));
7322 return (size
> 0 && size
<= mips_section_threshold
);
7325 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7326 anchors for small data: the GP register acts as an anchor in that
7327 case. We also don't want to use them for PC-relative accesses,
7328 where the PC acts as an anchor. */
7331 mips_use_anchors_for_symbol_p (rtx symbol
)
7333 switch (mips_classify_symbol (symbol
))
7335 case SYMBOL_CONSTANT_POOL
:
7336 case SYMBOL_SMALL_DATA
:
7344 /* See whether VALTYPE is a record whose fields should be returned in
7345 floating-point registers. If so, return the number of fields and
7346 list them in FIELDS (which should have two elements). Return 0
7349 For n32 & n64, a structure with one or two fields is returned in
7350 floating-point registers as long as every field has a floating-point
7354 mips_fpr_return_fields (tree valtype
, tree
*fields
)
7362 if (TREE_CODE (valtype
) != RECORD_TYPE
)
7366 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= TREE_CHAIN (field
))
7368 if (TREE_CODE (field
) != FIELD_DECL
)
7371 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
)
7377 fields
[i
++] = field
;
7383 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7384 a value in the most significant part of $2/$3 if:
7386 - the target is big-endian;
7388 - the value has a structure or union type (we generalize this to
7389 cover aggregates from other languages too); and
7391 - the structure is not returned in floating-point registers. */
7394 mips_return_in_msb (tree valtype
)
7398 return (TARGET_NEWABI
7399 && TARGET_BIG_ENDIAN
7400 && AGGREGATE_TYPE_P (valtype
)
7401 && mips_fpr_return_fields (valtype
, fields
) == 0);
7405 /* Return a composite value in a pair of floating-point registers.
7406 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7407 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7410 For n32 & n64, $f0 always holds the first value and $f2 the second.
7411 Otherwise the values are packed together as closely as possible. */
7414 mips_return_fpr_pair (enum machine_mode mode
,
7415 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
7416 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
7420 inc
= (TARGET_NEWABI
? 2 : FP_INC
);
7421 return gen_rtx_PARALLEL
7424 gen_rtx_EXPR_LIST (VOIDmode
,
7425 gen_rtx_REG (mode1
, FP_RETURN
),
7427 gen_rtx_EXPR_LIST (VOIDmode
,
7428 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
7429 GEN_INT (offset2
))));
7434 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7435 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7436 VALTYPE is null and MODE is the mode of the return value. */
7439 mips_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
7440 enum machine_mode mode
)
7447 mode
= TYPE_MODE (valtype
);
7448 unsignedp
= TYPE_UNSIGNED (valtype
);
7450 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7451 true, we must promote the mode just as PROMOTE_MODE does. */
7452 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
7454 /* Handle structures whose fields are returned in $f0/$f2. */
7455 switch (mips_fpr_return_fields (valtype
, fields
))
7458 return gen_rtx_REG (mode
, FP_RETURN
);
7461 return mips_return_fpr_pair (mode
,
7462 TYPE_MODE (TREE_TYPE (fields
[0])),
7463 int_byte_position (fields
[0]),
7464 TYPE_MODE (TREE_TYPE (fields
[1])),
7465 int_byte_position (fields
[1]));
7468 /* If a value is passed in the most significant part of a register, see
7469 whether we have to round the mode up to a whole number of words. */
7470 if (mips_return_in_msb (valtype
))
7472 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
7473 if (size
% UNITS_PER_WORD
!= 0)
7475 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
7476 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7480 /* For EABI, the class of return register depends entirely on MODE.
7481 For example, "struct { some_type x; }" and "union { some_type x; }"
7482 are returned in the same way as a bare "some_type" would be.
7483 Other ABIs only use FPRs for scalar, complex or vector types. */
7484 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
7485 return gen_rtx_REG (mode
, GP_RETURN
);
7488 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
7489 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
7490 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
)
7491 return gen_rtx_REG (mode
, FP_RETURN
);
7493 /* Handle long doubles for n32 & n64. */
7495 return mips_return_fpr_pair (mode
,
7497 DImode
, GET_MODE_SIZE (mode
) / 2);
7499 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7500 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
* 2)
7501 return mips_return_fpr_pair (mode
,
7502 GET_MODE_INNER (mode
), 0,
7503 GET_MODE_INNER (mode
),
7504 GET_MODE_SIZE (mode
) / 2);
7506 return gen_rtx_REG (mode
, GP_RETURN
);
7509 /* Return nonzero when an argument must be passed by reference. */
7512 mips_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
7513 enum machine_mode mode
, tree type
,
7514 bool named ATTRIBUTE_UNUSED
)
7516 if (mips_abi
== ABI_EABI
)
7520 /* ??? How should SCmode be handled? */
7521 if (mode
== DImode
|| mode
== DFmode
)
7524 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
7525 return size
== -1 || size
> UNITS_PER_WORD
;
7529 /* If we have a variable-sized parameter, we have no choice. */
7530 return targetm
.calls
.must_pass_in_stack (mode
, type
);
7535 mips_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
7536 enum machine_mode mode ATTRIBUTE_UNUSED
,
7537 tree type ATTRIBUTE_UNUSED
, bool named
)
7539 return mips_abi
== ABI_EABI
&& named
;
7542 /* Return true if registers of class CLASS cannot change from mode FROM
7546 mips_cannot_change_mode_class (enum machine_mode from
,
7547 enum machine_mode to
, enum reg_class
class)
7549 if (MIN (GET_MODE_SIZE (from
), GET_MODE_SIZE (to
)) <= UNITS_PER_WORD
7550 && MAX (GET_MODE_SIZE (from
), GET_MODE_SIZE (to
)) > UNITS_PER_WORD
)
7552 if (TARGET_BIG_ENDIAN
)
7554 /* When a multi-word value is stored in paired floating-point
7555 registers, the first register always holds the low word.
7556 We therefore can't allow FPRs to change between single-word
7557 and multi-word modes. */
7558 if (FP_INC
> 1 && reg_classes_intersect_p (FP_REGS
, class))
7563 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7564 in LO and HI, the high word always comes first. We therefore
7565 can't allow values stored in HI to change between single-word
7566 and multi-word modes.
7567 This rule applies to both the original HI/LO pair and the new
7568 DSP accumulators. */
7569 if (reg_classes_intersect_p (ACC_REGS
, class))
7574 /* gcc assumes that each word of a multiword register can be accessed
7575 individually using SUBREGs. This is not true for floating-point
7576 registers if they are bigger than a word. */
7577 if (UNITS_PER_FPREG
> UNITS_PER_WORD
7578 && GET_MODE_SIZE (from
) > UNITS_PER_WORD
7579 && GET_MODE_SIZE (to
) < UNITS_PER_FPREG
7580 && reg_classes_intersect_p (FP_REGS
, class))
7583 /* Loading a 32-bit value into a 64-bit floating-point register
7584 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7585 We can't allow 64-bit float registers to change from SImode to
7590 && GET_MODE_SIZE (to
) >= UNITS_PER_WORD
7591 && reg_classes_intersect_p (FP_REGS
, class))
7597 /* Return true if X should not be moved directly into register $25.
7598 We need this because many versions of GAS will treat "la $25,foo" as
7599 part of a call sequence and so allow a global "foo" to be lazily bound. */
7602 mips_dangerous_for_la25_p (rtx x
)
7606 if (TARGET_EXPLICIT_RELOCS
)
7609 split_const (x
, &x
, &offset
);
7610 return global_got_operand (x
, VOIDmode
);
7613 /* Implement PREFERRED_RELOAD_CLASS. */
7616 mips_preferred_reload_class (rtx x
, enum reg_class
class)
7618 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, class))
7621 if (TARGET_HARD_FLOAT
7622 && FLOAT_MODE_P (GET_MODE (x
))
7623 && reg_class_subset_p (FP_REGS
, class))
7626 if (reg_class_subset_p (GR_REGS
, class))
7629 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, class))
7635 /* This function returns the register class required for a secondary
7636 register when copying between one of the registers in CLASS, and X,
7637 using MODE. If IN_P is nonzero, the copy is going from X to the
7638 register, otherwise the register is the source. A return value of
7639 NO_REGS means that no secondary register is required. */
7642 mips_secondary_reload_class (enum reg_class
class,
7643 enum machine_mode mode
, rtx x
, int in_p
)
7645 enum reg_class gr_regs
= TARGET_MIPS16
? M16_REGS
: GR_REGS
;
7649 if (REG_P (x
)|| GET_CODE (x
) == SUBREG
)
7650 regno
= true_regnum (x
);
7652 gp_reg_p
= TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
7654 if (mips_dangerous_for_la25_p (x
))
7657 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], 25))
7661 /* Copying from HI or LO to anywhere other than a general register
7662 requires a general register.
7663 This rule applies to both the original HI/LO pair and the new
7664 DSP accumulators. */
7665 if (reg_class_subset_p (class, ACC_REGS
))
7667 if (TARGET_MIPS16
&& in_p
)
7669 /* We can't really copy to HI or LO at all in mips16 mode. */
7672 return gp_reg_p
? NO_REGS
: gr_regs
;
7674 if (ACC_REG_P (regno
))
7676 if (TARGET_MIPS16
&& ! in_p
)
7678 /* We can't really copy to HI or LO at all in mips16 mode. */
7681 return class == gr_regs
? NO_REGS
: gr_regs
;
7684 /* We can only copy a value to a condition code register from a
7685 floating point register, and even then we require a scratch
7686 floating point register. We can only copy a value out of a
7687 condition code register into a general register. */
7688 if (class == ST_REGS
)
7692 return gp_reg_p
? NO_REGS
: gr_regs
;
7694 if (ST_REG_P (regno
))
7698 return class == gr_regs
? NO_REGS
: gr_regs
;
7701 if (class == FP_REGS
)
7705 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7708 else if (CONSTANT_P (x
) && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7710 /* We can use the l.s and l.d macros to load floating-point
7711 constants. ??? For l.s, we could probably get better
7712 code by returning GR_REGS here. */
7715 else if (gp_reg_p
|| x
== CONST0_RTX (mode
))
7717 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7720 else if (FP_REG_P (regno
))
7722 /* In this case we can use mov.s or mov.d. */
7727 /* Otherwise, we need to reload through an integer register. */
7732 /* In mips16 mode, going between memory and anything but M16_REGS
7733 requires an M16_REG. */
7736 if (class != M16_REGS
&& class != M16_NA_REGS
)
7744 if (class == M16_REGS
|| class == M16_NA_REGS
)
7753 /* Implement CLASS_MAX_NREGS.
7755 - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
7757 - ST_REGS are always hold CCmode values, and CCmode values are
7758 considered to be 4 bytes wide.
7760 All other register classes are covered by UNITS_PER_WORD. Note that
7761 this is true even for unions of integer and float registers when the
7762 latter are smaller than the former. The only supported combination
7763 in which case this occurs is -mgp64 -msingle-float, which has 64-bit
7764 words but 32-bit float registers. A word-based calculation is correct
7765 in that case since -msingle-float disallows multi-FPR values. */
7768 mips_class_max_nregs (enum reg_class
class ATTRIBUTE_UNUSED
,
7769 enum machine_mode mode
)
7771 if (class == ST_REGS
)
7772 return (GET_MODE_SIZE (mode
) + 3) / 4;
7773 else if (class == FP_REGS
)
7774 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
7776 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7780 mips_valid_pointer_mode (enum machine_mode mode
)
7782 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
7785 /* Target hook for vector_mode_supported_p. */
7788 mips_vector_mode_supported_p (enum machine_mode mode
)
7793 return TARGET_PAIRED_SINGLE_FLOAT
;
7804 /* If we can access small data directly (using gp-relative relocation
7805 operators) return the small data pointer, otherwise return null.
7807 For each mips16 function which refers to GP relative symbols, we
7808 use a pseudo register, initialized at the start of the function, to
7809 hold the $gp value. */
7812 mips16_gp_pseudo_reg (void)
7814 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
7818 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
7820 /* We want to initialize this to a value which gcc will believe
7822 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
7824 push_topmost_sequence ();
7825 /* We need to emit the initialization after the FUNCTION_BEG
7826 note, so that it will be integrated. */
7827 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
7829 && NOTE_LINE_NUMBER (scan
) == NOTE_INSN_FUNCTION_BEG
)
7831 if (scan
== NULL_RTX
)
7832 scan
= get_insns ();
7833 insn
= emit_insn_after (insn
, scan
);
7834 pop_topmost_sequence ();
7837 return cfun
->machine
->mips16_gp_pseudo_rtx
;
7840 /* Write out code to move floating point arguments in or out of
7841 general registers. Output the instructions to FILE. FP_CODE is
7842 the code describing which arguments are present (see the comment at
7843 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7844 we are copying from the floating point registers. */
7847 mips16_fp_args (FILE *file
, int fp_code
, int from_fp_p
)
7853 /* This code only works for the original 32-bit ABI and the O64 ABI. */
7854 gcc_assert (TARGET_OLDABI
);
7860 gparg
= GP_ARG_FIRST
;
7861 fparg
= FP_ARG_FIRST
;
7862 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7866 if ((fparg
& 1) != 0)
7868 fprintf (file
, "\t%s\t%s,%s\n", s
,
7869 reg_names
[gparg
], reg_names
[fparg
]);
7871 else if ((f
& 3) == 2)
7874 fprintf (file
, "\td%s\t%s,%s\n", s
,
7875 reg_names
[gparg
], reg_names
[fparg
]);
7878 if ((fparg
& 1) != 0)
7880 if (TARGET_BIG_ENDIAN
)
7881 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
7882 reg_names
[gparg
], reg_names
[fparg
+ 1], s
,
7883 reg_names
[gparg
+ 1], reg_names
[fparg
]);
7885 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
7886 reg_names
[gparg
], reg_names
[fparg
], s
,
7887 reg_names
[gparg
+ 1], reg_names
[fparg
+ 1]);
7900 /* Build a mips16 function stub. This is used for functions which
7901 take arguments in the floating point registers. It is 32-bit code
7902 that moves the floating point args into the general registers, and
7903 then jumps to the 16-bit code. */
7906 build_mips16_function_stub (FILE *file
)
7909 char *secname
, *stubname
;
7910 tree stubid
, stubdecl
;
7914 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7915 secname
= (char *) alloca (strlen (fnname
) + 20);
7916 sprintf (secname
, ".mips16.fn.%s", fnname
);
7917 stubname
= (char *) alloca (strlen (fnname
) + 20);
7918 sprintf (stubname
, "__fn_stub_%s", fnname
);
7919 stubid
= get_identifier (stubname
);
7920 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
7921 build_function_type (void_type_node
, NULL_TREE
));
7922 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
7924 fprintf (file
, "\t# Stub function for %s (", current_function_name ());
7926 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
7928 fprintf (file
, "%s%s",
7929 need_comma
? ", " : "",
7930 (f
& 3) == 1 ? "float" : "double");
7933 fprintf (file
, ")\n");
7935 fprintf (file
, "\t.set\tnomips16\n");
7936 switch_to_section (function_section (stubdecl
));
7937 ASM_OUTPUT_ALIGN (file
, floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
7939 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7940 within a .ent, and we cannot emit another .ent. */
7941 if (!FUNCTION_NAME_ALREADY_DECLARED
)
7943 fputs ("\t.ent\t", file
);
7944 assemble_name (file
, stubname
);
7948 assemble_name (file
, stubname
);
7949 fputs (":\n", file
);
7951 /* We don't want the assembler to insert any nops here. */
7952 fprintf (file
, "\t.set\tnoreorder\n");
7954 mips16_fp_args (file
, current_function_args_info
.fp_code
, 1);
7956 fprintf (asm_out_file
, "\t.set\tnoat\n");
7957 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
7958 assemble_name (file
, fnname
);
7959 fprintf (file
, "\n");
7960 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
7961 fprintf (asm_out_file
, "\t.set\tat\n");
7963 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7964 with one of the mfc1 instructions, because the result is not
7965 available for one instruction, so if the very first instruction
7966 in the function refers to the register, it will see the wrong
7968 fprintf (file
, "\tnop\n");
7970 fprintf (file
, "\t.set\treorder\n");
7972 if (!FUNCTION_NAME_ALREADY_DECLARED
)
7974 fputs ("\t.end\t", file
);
7975 assemble_name (file
, stubname
);
7979 fprintf (file
, "\t.set\tmips16\n");
7981 switch_to_section (function_section (current_function_decl
));
7984 /* We keep a list of functions for which we have already built stubs
7985 in build_mips16_call_stub. */
7989 struct mips16_stub
*next
;
7994 static struct mips16_stub
*mips16_stubs
;
7996 /* Build a call stub for a mips16 call. A stub is needed if we are
7997 passing any floating point values which should go into the floating
7998 point registers. If we are, and the call turns out to be to a
7999 32-bit function, the stub will be used to move the values into the
8000 floating point registers before calling the 32-bit function. The
8001 linker will magically adjust the function call to either the 16-bit
8002 function or the 32-bit stub, depending upon where the function call
8003 is actually defined.
8005 Similarly, we need a stub if the return value might come back in a
8006 floating point register.
8008 RETVAL is the location of the return value, or null if this is
8009 a call rather than a call_value. FN is the address of the
8010 function and ARG_SIZE is the size of the arguments. FP_CODE
8011 is the code built by function_arg. This function returns a nonzero
8012 value if it builds the call instruction itself. */
8015 build_mips16_call_stub (rtx retval
, rtx fn
, rtx arg_size
, int fp_code
)
8019 char *secname
, *stubname
;
8020 struct mips16_stub
*l
;
8021 tree stubid
, stubdecl
;
8025 /* We don't need to do anything if we aren't in mips16 mode, or if
8026 we were invoked with the -msoft-float option. */
8027 if (! TARGET_MIPS16
|| ! mips16_hard_float
)
8030 /* Figure out whether the value might come back in a floating point
8032 fpret
= (retval
!= 0
8033 && GET_MODE_CLASS (GET_MODE (retval
)) == MODE_FLOAT
8034 && GET_MODE_SIZE (GET_MODE (retval
)) <= UNITS_PER_FPVALUE
);
8036 /* We don't need to do anything if there were no floating point
8037 arguments and the value will not be returned in a floating point
8039 if (fp_code
== 0 && ! fpret
)
8042 /* We don't need to do anything if this is a call to a special
8043 mips16 support function. */
8044 if (GET_CODE (fn
) == SYMBOL_REF
8045 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
8048 /* This code will only work for o32 and o64 abis. The other ABI's
8049 require more sophisticated support. */
8050 gcc_assert (TARGET_OLDABI
);
8052 /* We can only handle SFmode and DFmode floating point return
8055 gcc_assert (GET_MODE (retval
) == SFmode
|| GET_MODE (retval
) == DFmode
);
8057 /* If we're calling via a function pointer, then we must always call
8058 via a stub. There are magic stubs provided in libgcc.a for each
8059 of the required cases. Each of them expects the function address
8060 to arrive in register $2. */
8062 if (GET_CODE (fn
) != SYMBOL_REF
)
8068 /* ??? If this code is modified to support other ABI's, we need
8069 to handle PARALLEL return values here. */
8071 sprintf (buf
, "__mips16_call_stub_%s%d",
8073 ? (GET_MODE (retval
) == SFmode
? "sf_" : "df_")
8076 id
= get_identifier (buf
);
8077 stub_fn
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (id
));
8079 emit_move_insn (gen_rtx_REG (Pmode
, 2), fn
);
8081 if (retval
== NULL_RTX
)
8082 insn
= gen_call_internal (stub_fn
, arg_size
);
8084 insn
= gen_call_value_internal (retval
, stub_fn
, arg_size
);
8085 insn
= emit_call_insn (insn
);
8087 /* Put the register usage information on the CALL. */
8088 CALL_INSN_FUNCTION_USAGE (insn
) =
8089 gen_rtx_EXPR_LIST (VOIDmode
,
8090 gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 2)),
8091 CALL_INSN_FUNCTION_USAGE (insn
));
8093 /* If we are handling a floating point return value, we need to
8094 save $18 in the function prologue. Putting a note on the
8095 call will mean that regs_ever_live[$18] will be true if the
8096 call is not eliminated, and we can check that in the prologue
8099 CALL_INSN_FUNCTION_USAGE (insn
) =
8100 gen_rtx_EXPR_LIST (VOIDmode
,
8101 gen_rtx_USE (VOIDmode
,
8102 gen_rtx_REG (word_mode
, 18)),
8103 CALL_INSN_FUNCTION_USAGE (insn
));
8105 /* Return 1 to tell the caller that we've generated the call
8110 /* We know the function we are going to call. If we have already
8111 built a stub, we don't need to do anything further. */
8113 fnname
= XSTR (fn
, 0);
8114 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
8115 if (strcmp (l
->name
, fnname
) == 0)
8120 /* Build a special purpose stub. When the linker sees a
8121 function call in mips16 code, it will check where the target
8122 is defined. If the target is a 32-bit call, the linker will
8123 search for the section defined here. It can tell which
8124 symbol this section is associated with by looking at the
8125 relocation information (the name is unreliable, since this
8126 might be a static function). If such a section is found, the
8127 linker will redirect the call to the start of the magic
8130 If the function does not return a floating point value, the
8131 special stub section is named
8134 If the function does return a floating point value, the stub
8136 .mips16.call.fp.FNNAME
8139 secname
= (char *) alloca (strlen (fnname
) + 40);
8140 sprintf (secname
, ".mips16.call.%s%s",
8143 stubname
= (char *) alloca (strlen (fnname
) + 20);
8144 sprintf (stubname
, "__call_stub_%s%s",
8147 stubid
= get_identifier (stubname
);
8148 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8149 build_function_type (void_type_node
, NULL_TREE
));
8150 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8152 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
8154 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
8158 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8160 fprintf (asm_out_file
, "%s%s",
8161 need_comma
? ", " : "",
8162 (f
& 3) == 1 ? "float" : "double");
8165 fprintf (asm_out_file
, ")\n");
8167 fprintf (asm_out_file
, "\t.set\tnomips16\n");
8168 assemble_start_function (stubdecl
, stubname
);
8170 if (!FUNCTION_NAME_ALREADY_DECLARED
)
8172 fputs ("\t.ent\t", asm_out_file
);
8173 assemble_name (asm_out_file
, stubname
);
8174 fputs ("\n", asm_out_file
);
8176 assemble_name (asm_out_file
, stubname
);
8177 fputs (":\n", asm_out_file
);
8180 /* We build the stub code by hand. That's the only way we can
8181 do it, since we can't generate 32-bit code during a 16-bit
8184 /* We don't want the assembler to insert any nops here. */
8185 fprintf (asm_out_file
, "\t.set\tnoreorder\n");
8187 mips16_fp_args (asm_out_file
, fp_code
, 0);
8191 fprintf (asm_out_file
, "\t.set\tnoat\n");
8192 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
8194 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
8195 fprintf (asm_out_file
, "\t.set\tat\n");
8196 /* Unfortunately, we can't fill the jump delay slot. We
8197 can't fill with one of the mtc1 instructions, because the
8198 result is not available for one instruction, so if the
8199 very first instruction in the function refers to the
8200 register, it will see the wrong value. */
8201 fprintf (asm_out_file
, "\tnop\n");
8205 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
8206 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
8207 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
8208 /* As above, we can't fill the delay slot. */
8209 fprintf (asm_out_file
, "\tnop\n");
8210 if (GET_MODE (retval
) == SFmode
)
8211 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8212 reg_names
[GP_REG_FIRST
+ 2], reg_names
[FP_REG_FIRST
+ 0]);
8215 if (TARGET_BIG_ENDIAN
)
8217 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8218 reg_names
[GP_REG_FIRST
+ 2],
8219 reg_names
[FP_REG_FIRST
+ 1]);
8220 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8221 reg_names
[GP_REG_FIRST
+ 3],
8222 reg_names
[FP_REG_FIRST
+ 0]);
8226 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8227 reg_names
[GP_REG_FIRST
+ 2],
8228 reg_names
[FP_REG_FIRST
+ 0]);
8229 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8230 reg_names
[GP_REG_FIRST
+ 3],
8231 reg_names
[FP_REG_FIRST
+ 1]);
8234 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
8235 /* As above, we can't fill the delay slot. */
8236 fprintf (asm_out_file
, "\tnop\n");
8239 fprintf (asm_out_file
, "\t.set\treorder\n");
8241 #ifdef ASM_DECLARE_FUNCTION_SIZE
8242 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
8245 if (!FUNCTION_NAME_ALREADY_DECLARED
)
8247 fputs ("\t.end\t", asm_out_file
);
8248 assemble_name (asm_out_file
, stubname
);
8249 fputs ("\n", asm_out_file
);
8252 fprintf (asm_out_file
, "\t.set\tmips16\n");
8254 /* Record this stub. */
8255 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
8256 l
->name
= xstrdup (fnname
);
8258 l
->next
= mips16_stubs
;
8262 /* If we expect a floating point return value, but we've built a
8263 stub which does not expect one, then we're in trouble. We can't
8264 use the existing stub, because it won't handle the floating point
8265 value. We can't build a new stub, because the linker won't know
8266 which stub to use for the various calls in this object file.
8267 Fortunately, this case is illegal, since it means that a function
8268 was declared in two different ways in a single compilation. */
8269 if (fpret
&& ! l
->fpret
)
8270 error ("cannot handle inconsistent calls to %qs", fnname
);
8272 /* If we are calling a stub which handles a floating point return
8273 value, we need to arrange to save $18 in the prologue. We do
8274 this by marking the function call as using the register. The
8275 prologue will later see that it is used, and emit code to save
8282 if (retval
== NULL_RTX
)
8283 insn
= gen_call_internal (fn
, arg_size
);
8285 insn
= gen_call_value_internal (retval
, fn
, arg_size
);
8286 insn
= emit_call_insn (insn
);
8288 CALL_INSN_FUNCTION_USAGE (insn
) =
8289 gen_rtx_EXPR_LIST (VOIDmode
,
8290 gen_rtx_USE (VOIDmode
, gen_rtx_REG (word_mode
, 18)),
8291 CALL_INSN_FUNCTION_USAGE (insn
));
8293 /* Return 1 to tell the caller that we've generated the call
8298 /* Return 0 to let the caller generate the call insn. */
8302 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8303 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8305 struct mips16_constant
{
8306 struct mips16_constant
*next
;
8309 enum machine_mode mode
;
8312 /* Information about an incomplete mips16 constant pool. FIRST is the
8313 first constant, HIGHEST_ADDRESS is the highest address that the first
8314 byte of the pool can have, and INSN_ADDRESS is the current instruction
8317 struct mips16_constant_pool
{
8318 struct mips16_constant
*first
;
8319 int highest_address
;
8323 /* Add constant VALUE to POOL and return its label. MODE is the
8324 value's mode (used for CONST_INTs, etc.). */
8327 add_constant (struct mips16_constant_pool
*pool
,
8328 rtx value
, enum machine_mode mode
)
8330 struct mips16_constant
**p
, *c
;
8331 bool first_of_size_p
;
8333 /* See whether the constant is already in the pool. If so, return the
8334 existing label, otherwise leave P pointing to the place where the
8335 constant should be added.
8337 Keep the pool sorted in increasing order of mode size so that we can
8338 reduce the number of alignments needed. */
8339 first_of_size_p
= true;
8340 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
8342 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
8344 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
8346 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
8347 first_of_size_p
= false;
8350 /* In the worst case, the constant needed by the earliest instruction
8351 will end up at the end of the pool. The entire pool must then be
8352 accessible from that instruction.
8354 When adding the first constant, set the pool's highest address to
8355 the address of the first out-of-range byte. Adjust this address
8356 downwards each time a new constant is added. */
8357 if (pool
->first
== 0)
8358 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8359 is the address of the instruction with the lowest two bits clear.
8360 The base PC value for ld has the lowest three bits clear. Assume
8361 the worst case here. */
8362 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
8363 pool
->highest_address
-= GET_MODE_SIZE (mode
);
8364 if (first_of_size_p
)
8365 /* Take into account the worst possible padding due to alignment. */
8366 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
8368 /* Create a new entry. */
8369 c
= (struct mips16_constant
*) xmalloc (sizeof *c
);
8372 c
->label
= gen_label_rtx ();
8379 /* Output constant VALUE after instruction INSN and return the last
8380 instruction emitted. MODE is the mode of the constant. */
8383 dump_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
8385 switch (GET_MODE_CLASS (mode
))
8389 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
8390 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
8394 return emit_insn_after (gen_consttable_float (value
), insn
);
8396 case MODE_VECTOR_FLOAT
:
8397 case MODE_VECTOR_INT
:
8400 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
8401 insn
= dump_constants_1 (GET_MODE_INNER (mode
),
8402 CONST_VECTOR_ELT (value
, i
), insn
);
8412 /* Dump out the constants in CONSTANTS after INSN. */
8415 dump_constants (struct mips16_constant
*constants
, rtx insn
)
8417 struct mips16_constant
*c
, *next
;
8421 for (c
= constants
; c
!= NULL
; c
= next
)
8423 /* If necessary, increase the alignment of PC. */
8424 if (align
< GET_MODE_SIZE (c
->mode
))
8426 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
8427 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
8429 align
= GET_MODE_SIZE (c
->mode
);
8431 insn
= emit_label_after (c
->label
, insn
);
8432 insn
= dump_constants_1 (c
->mode
, c
->value
, insn
);
8438 emit_barrier_after (insn
);
8441 /* Return the length of instruction INSN. */
8444 mips16_insn_length (rtx insn
)
8448 rtx body
= PATTERN (insn
);
8449 if (GET_CODE (body
) == ADDR_VEC
)
8450 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
8451 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
8452 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
8454 return get_attr_length (insn
);
8457 /* Rewrite *X so that constant pool references refer to the constant's
8458 label instead. DATA points to the constant pool structure. */
8461 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
8463 struct mips16_constant_pool
*pool
= data
;
8464 if (GET_CODE (*x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (*x
))
8465 *x
= gen_rtx_LABEL_REF (Pmode
, add_constant (pool
,
8466 get_pool_constant (*x
),
8467 get_pool_mode (*x
)));
8471 /* Build MIPS16 constant pools. */
8474 mips16_lay_out_constants (void)
8476 struct mips16_constant_pool pool
;
8480 memset (&pool
, 0, sizeof (pool
));
8481 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8483 /* Rewrite constant pool references in INSN. */
8485 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &pool
);
8487 pool
.insn_address
+= mips16_insn_length (insn
);
8489 if (pool
.first
!= NULL
)
8491 /* If there are no natural barriers between the first user of
8492 the pool and the highest acceptable address, we'll need to
8493 create a new instruction to jump around the constant pool.
8494 In the worst case, this instruction will be 4 bytes long.
8496 If it's too late to do this transformation after INSN,
8497 do it immediately before INSN. */
8498 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
8502 label
= gen_label_rtx ();
8504 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
8505 JUMP_LABEL (jump
) = label
;
8506 LABEL_NUSES (label
) = 1;
8507 barrier
= emit_barrier_after (jump
);
8509 emit_label_after (label
, barrier
);
8510 pool
.insn_address
+= 4;
8513 /* See whether the constant pool is now out of range of the first
8514 user. If so, output the constants after the previous barrier.
8515 Note that any instructions between BARRIER and INSN (inclusive)
8516 will use negative offsets to refer to the pool. */
8517 if (pool
.insn_address
> pool
.highest_address
)
8519 dump_constants (pool
.first
, barrier
);
8523 else if (BARRIER_P (insn
))
8527 dump_constants (pool
.first
, get_last_insn ());
8530 /* A temporary variable used by for_each_rtx callbacks, etc. */
8531 static rtx mips_sim_insn
;
8533 /* A structure representing the state of the processor pipeline.
8534 Used by the mips_sim_* family of functions. */
8536 /* The maximum number of instructions that can be issued in a cycle.
8537 (Caches mips_issue_rate.) */
8538 unsigned int issue_rate
;
8540 /* The current simulation time. */
8543 /* How many more instructions can be issued in the current cycle. */
8544 unsigned int insns_left
;
8546 /* LAST_SET[X].INSN is the last instruction to set register X.
8547 LAST_SET[X].TIME is the time at which that instruction was issued.
8548 INSN is null if no instruction has yet set register X. */
8552 } last_set
[FIRST_PSEUDO_REGISTER
];
8554 /* The pipeline's current DFA state. */
8558 /* Reset STATE to the initial simulation state. */
8561 mips_sim_reset (struct mips_sim
*state
)
8564 state
->insns_left
= state
->issue_rate
;
8565 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
8566 state_reset (state
->dfa_state
);
8569 /* Initialize STATE before its first use. DFA_STATE points to an
8570 allocated but uninitialized DFA state. */
8573 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
8575 state
->issue_rate
= mips_issue_rate ();
8576 state
->dfa_state
= dfa_state
;
8577 mips_sim_reset (state
);
8580 /* Advance STATE by one clock cycle. */
8583 mips_sim_next_cycle (struct mips_sim
*state
)
8586 state
->insns_left
= state
->issue_rate
;
8587 state_transition (state
->dfa_state
, 0);
8590 /* Advance simulation state STATE until instruction INSN can read
8594 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
8598 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)); i
++)
8599 if (state
->last_set
[REGNO (reg
) + i
].insn
!= 0)
8603 t
= state
->last_set
[REGNO (reg
) + i
].time
;
8604 t
+= insn_latency (state
->last_set
[REGNO (reg
) + i
].insn
, insn
);
8605 while (state
->time
< t
)
8606 mips_sim_next_cycle (state
);
8610 /* A for_each_rtx callback. If *X is a register, advance simulation state
8611 DATA until mips_sim_insn can read the register's value. */
8614 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
8617 mips_sim_wait_reg (data
, mips_sim_insn
, *x
);
8621 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8624 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
8626 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
8629 /* Advance simulation state STATE until all of INSN's register
8630 dependencies are satisfied. */
8633 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
8635 mips_sim_insn
= insn
;
8636 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
8639 /* Advance simulation state STATE until the units required by
8640 instruction INSN are available. */
8643 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
8647 tmp_state
= alloca (state_size ());
8648 while (state
->insns_left
== 0
8649 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
8650 state_transition (tmp_state
, insn
) >= 0))
8651 mips_sim_next_cycle (state
);
8654 /* Advance simulation state STATE until INSN is ready to issue. */
8657 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
8659 mips_sim_wait_regs (state
, insn
);
8660 mips_sim_wait_units (state
, insn
);
8663 /* mips_sim_insn has just set X. Update the LAST_SET array
8664 in simulation state DATA. */
8667 mips_sim_record_set (rtx x
, rtx pat ATTRIBUTE_UNUSED
, void *data
)
8669 struct mips_sim
*state
;
8674 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (x
), GET_MODE (x
)); i
++)
8676 state
->last_set
[REGNO (x
) + i
].insn
= mips_sim_insn
;
8677 state
->last_set
[REGNO (x
) + i
].time
= state
->time
;
8681 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8682 can issue immediately (i.e., that mips_sim_wait_insn has already
8686 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
8688 state_transition (state
->dfa_state
, insn
);
8689 state
->insns_left
--;
8691 mips_sim_insn
= insn
;
8692 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
8695 /* Simulate issuing a NOP in state STATE. */
8698 mips_sim_issue_nop (struct mips_sim
*state
)
8700 if (state
->insns_left
== 0)
8701 mips_sim_next_cycle (state
);
8702 state
->insns_left
--;
8705 /* Update simulation state STATE so that it's ready to accept the instruction
8706 after INSN. INSN should be part of the main rtl chain, not a member of a
8710 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
8712 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8714 mips_sim_issue_nop (state
);
8716 switch (GET_CODE (SEQ_BEGIN (insn
)))
8720 /* We can't predict the processor state after a call or label. */
8721 mips_sim_reset (state
);
8725 /* The delay slots of branch likely instructions are only executed
8726 when the branch is taken. Therefore, if the caller has simulated
8727 the delay slot instruction, STATE does not really reflect the state
8728 of the pipeline for the instruction after the delay slot. Also,
8729 branch likely instructions tend to incur a penalty when not taken,
8730 so there will probably be an extra delay between the branch and
8731 the instruction after the delay slot. */
8732 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
8733 mips_sim_reset (state
);
8741 /* The VR4130 pipeline issues aligned pairs of instructions together,
8742 but it stalls the second instruction if it depends on the first.
8743 In order to cut down the amount of logic required, this dependence
8744 check is not based on a full instruction decode. Instead, any non-SPECIAL
8745 instruction is assumed to modify the register specified by bits 20-16
8746 (which is usually the "rt" field).
8748 In beq, beql, bne and bnel instructions, the rt field is actually an
8749 input, so we can end up with a false dependence between the branch
8750 and its delay slot. If this situation occurs in instruction INSN,
8751 try to avoid it by swapping rs and rt. */
8754 vr4130_avoid_branch_rt_conflict (rtx insn
)
8758 first
= SEQ_BEGIN (insn
);
8759 second
= SEQ_END (insn
);
8761 && NONJUMP_INSN_P (second
)
8762 && GET_CODE (PATTERN (first
)) == SET
8763 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
8764 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
8766 /* Check for the right kind of condition. */
8767 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
8768 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8769 && REG_P (XEXP (cond
, 0))
8770 && REG_P (XEXP (cond
, 1))
8771 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
8772 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
8774 /* SECOND mentions the rt register but not the rs register. */
8775 rtx tmp
= XEXP (cond
, 0);
8776 XEXP (cond
, 0) = XEXP (cond
, 1);
8777 XEXP (cond
, 1) = tmp
;
8782 /* Implement -mvr4130-align. Go through each basic block and simulate the
8783 processor pipeline. If we find that a pair of instructions could execute
8784 in parallel, and the first of those instruction is not 8-byte aligned,
8785 insert a nop to make it aligned. */
8788 vr4130_align_insns (void)
8790 struct mips_sim state
;
8791 rtx insn
, subinsn
, last
, last2
, next
;
8796 /* LAST is the last instruction before INSN to have a nonzero length.
8797 LAST2 is the last such instruction before LAST. */
8801 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8804 mips_sim_init (&state
, alloca (state_size ()));
8805 for (insn
= get_insns (); insn
!= 0; insn
= next
)
8807 unsigned int length
;
8809 next
= NEXT_INSN (insn
);
8811 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8812 This isn't really related to the alignment pass, but we do it on
8813 the fly to avoid a separate instruction walk. */
8814 vr4130_avoid_branch_rt_conflict (insn
);
8816 if (USEFUL_INSN_P (insn
))
8817 FOR_EACH_SUBINSN (subinsn
, insn
)
8819 mips_sim_wait_insn (&state
, subinsn
);
8821 /* If we want this instruction to issue in parallel with the
8822 previous one, make sure that the previous instruction is
8823 aligned. There are several reasons why this isn't worthwhile
8824 when the second instruction is a call:
8826 - Calls are less likely to be performance critical,
8827 - There's a good chance that the delay slot can execute
8828 in parallel with the call.
8829 - The return address would then be unaligned.
8831 In general, if we're going to insert a nop between instructions
8832 X and Y, it's better to insert it immediately after X. That
8833 way, if the nop makes Y aligned, it will also align any labels
8835 if (state
.insns_left
!= state
.issue_rate
8836 && !CALL_P (subinsn
))
8838 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
8840 /* SUBINSN is the first instruction in INSN and INSN is
8841 aligned. We want to align the previous instruction
8842 instead, so insert a nop between LAST2 and LAST.
8844 Note that LAST could be either a single instruction
8845 or a branch with a delay slot. In the latter case,
8846 LAST, like INSN, is already aligned, but the delay
8847 slot must have some extra delay that stops it from
8848 issuing at the same time as the branch. We therefore
8849 insert a nop before the branch in order to align its
8851 emit_insn_after (gen_nop (), last2
);
8854 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
8856 /* SUBINSN is the delay slot of INSN, but INSN is
8857 currently unaligned. Insert a nop between
8858 LAST and INSN to align it. */
8859 emit_insn_after (gen_nop (), last
);
8863 mips_sim_issue_insn (&state
, subinsn
);
8865 mips_sim_finish_insn (&state
, insn
);
8867 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8868 length
= get_attr_length (insn
);
8871 /* If the instruction is an asm statement or multi-instruction
8872 mips.md patern, the length is only an estimate. Insert an
8873 8 byte alignment after it so that the following instructions
8874 can be handled correctly. */
8875 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
8876 && (recog_memoized (insn
) < 0 || length
>= 8))
8878 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
8879 next
= NEXT_INSN (next
);
8880 mips_sim_next_cycle (&state
);
8883 else if (length
& 4)
8884 aligned_p
= !aligned_p
;
8889 /* See whether INSN is an aligned label. */
8890 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
8896 /* Subroutine of mips_reorg. If there is a hazard between INSN
8897 and a previous instruction, avoid it by inserting nops after
8900 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8901 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8902 before using the value of that register. *HILO_DELAY counts the
8903 number of instructions since the last hilo hazard (that is,
8904 the number of instructions since the last mflo or mfhi).
8906 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8907 for the next instruction.
8909 LO_REG is an rtx for the LO register, used in dependence checking. */
8912 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
8913 rtx
*delayed_reg
, rtx lo_reg
)
8921 pattern
= PATTERN (insn
);
8923 /* Do not put the whole function in .set noreorder if it contains
8924 an asm statement. We don't know whether there will be hazards
8925 between the asm statement and the gcc-generated code. */
8926 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
8927 cfun
->machine
->all_noreorder_p
= false;
8929 /* Ignore zero-length instructions (barriers and the like). */
8930 ninsns
= get_attr_length (insn
) / 4;
8934 /* Work out how many nops are needed. Note that we only care about
8935 registers that are explicitly mentioned in the instruction's pattern.
8936 It doesn't matter that calls use the argument registers or that they
8937 clobber hi and lo. */
8938 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
8939 nops
= 2 - *hilo_delay
;
8940 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
8945 /* Insert the nops between this instruction and the previous one.
8946 Each new nop takes us further from the last hilo hazard. */
8947 *hilo_delay
+= nops
;
8949 emit_insn_after (gen_hazard_nop (), after
);
8951 /* Set up the state for the next instruction. */
8952 *hilo_delay
+= ninsns
;
8954 if (INSN_CODE (insn
) >= 0)
8955 switch (get_attr_hazard (insn
))
8965 set
= single_set (insn
);
8966 gcc_assert (set
!= 0);
8967 *delayed_reg
= SET_DEST (set
);
8973 /* Go through the instruction stream and insert nops where necessary.
8974 See if the whole function can then be put into .set noreorder &
8978 mips_avoid_hazards (void)
8980 rtx insn
, last_insn
, lo_reg
, delayed_reg
;
8983 /* Force all instructions to be split into their final form. */
8984 split_all_insns_noflow ();
8986 /* Recalculate instruction lengths without taking nops into account. */
8987 cfun
->machine
->ignore_hazard_length_p
= true;
8988 shorten_branches (get_insns ());
8990 cfun
->machine
->all_noreorder_p
= true;
8992 /* Profiled functions can't be all noreorder because the profiler
8993 support uses assembler macros. */
8994 if (current_function_profile
)
8995 cfun
->machine
->all_noreorder_p
= false;
8997 /* Code compiled with -mfix-vr4120 can't be all noreorder because
8998 we rely on the assembler to work around some errata. */
8999 if (TARGET_FIX_VR4120
)
9000 cfun
->machine
->all_noreorder_p
= false;
9002 /* The same is true for -mfix-vr4130 if we might generate mflo or
9003 mfhi instructions. Note that we avoid using mflo and mfhi if
9004 the VR4130 macc and dmacc instructions are available instead;
9005 see the *mfhilo_{si,di}_macc patterns. */
9006 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
9007 cfun
->machine
->all_noreorder_p
= false;
9012 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
9014 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
9017 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
9018 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
9019 mips_avoid_hazard (last_insn
, XVECEXP (PATTERN (insn
), 0, i
),
9020 &hilo_delay
, &delayed_reg
, lo_reg
);
9022 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
9023 &delayed_reg
, lo_reg
);
9030 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9036 mips16_lay_out_constants ();
9037 else if (TARGET_EXPLICIT_RELOCS
)
9039 if (mips_flag_delayed_branch
)
9040 dbr_schedule (get_insns ());
9041 mips_avoid_hazards ();
9042 if (TUNE_MIPS4130
&& TARGET_VR4130_ALIGN
)
9043 vr4130_align_insns ();
9047 /* This function does three things:
9049 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9050 - Register the mips16 hardware floating point stubs.
9051 - Register the gofast functions if selected using --enable-gofast. */
9053 #include "config/gofast.h"
9056 mips_init_libfuncs (void)
9058 if (TARGET_FIX_VR4120
)
9060 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
9061 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
9064 if (TARGET_MIPS16
&& mips16_hard_float
)
9066 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
9067 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
9068 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
9069 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
9071 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
9072 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
9073 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
9074 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
9075 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
9076 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
9078 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
9079 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
9081 if (TARGET_DOUBLE_FLOAT
)
9083 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
9084 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
9085 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
9086 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
9088 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
9089 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
9090 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
9091 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
9092 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
9093 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
9095 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__mips16_extendsfdf2");
9096 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__mips16_truncdfsf2");
9098 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__mips16_fix_truncdfsi");
9099 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__mips16_floatsidf");
9103 gofast_maybe_init_libfuncs ();
9106 /* Return a number assessing the cost of moving a register in class
9107 FROM to class TO. The classes are expressed using the enumeration
9108 values such as `GENERAL_REGS'. A value of 2 is the default; other
9109 values are interpreted relative to that.
9111 It is not required that the cost always equal 2 when FROM is the
9112 same as TO; on some machines it is expensive to move between
9113 registers if they are not general registers.
9115 If reload sees an insn consisting of a single `set' between two
9116 hard registers, and if `REGISTER_MOVE_COST' applied to their
9117 classes returns a value of 2, reload does not check to ensure that
9118 the constraints of the insn are met. Setting a cost of other than
9119 2 will allow reload to verify that the constraints are met. You
9120 should do this if the `movM' pattern's constraints do not allow
9123 ??? We make the cost of moving from HI/LO into general
9124 registers the same as for one of moving general registers to
9125 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9126 pseudo to HI/LO. This might hurt optimizations though, it
9127 isn't clear if it is wise. And it might not work in all cases. We
9128 could solve the DImode LO reg problem by using a multiply, just
9129 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9130 problem by using divide instructions. divu puts the remainder in
9131 the HI reg, so doing a divide by -1 will move the value in the HI
9132 reg for all values except -1. We could handle that case by using a
9133 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9134 a compare/branch to test the input value to see which instruction
9135 we need to use. This gets pretty messy, but it is feasible. */
9138 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
9139 enum reg_class to
, enum reg_class from
)
9141 if (from
== M16_REGS
&& GR_REG_CLASS_P (to
))
9143 else if (from
== M16_NA_REGS
&& GR_REG_CLASS_P (to
))
9145 else if (GR_REG_CLASS_P (from
))
9149 else if (to
== M16_NA_REGS
)
9151 else if (GR_REG_CLASS_P (to
))
9158 else if (to
== FP_REGS
)
9160 else if (reg_class_subset_p (to
, ACC_REGS
))
9167 else if (COP_REG_CLASS_P (to
))
9172 else if (from
== FP_REGS
)
9174 if (GR_REG_CLASS_P (to
))
9176 else if (to
== FP_REGS
)
9178 else if (to
== ST_REGS
)
9181 else if (reg_class_subset_p (from
, ACC_REGS
))
9183 if (GR_REG_CLASS_P (to
))
9191 else if (from
== ST_REGS
&& GR_REG_CLASS_P (to
))
9193 else if (COP_REG_CLASS_P (from
))
9199 ??? What cases are these? Shouldn't we return 2 here? */
9204 /* Return the length of INSN. LENGTH is the initial length computed by
9205 attributes in the machine-description file. */
9208 mips_adjust_insn_length (rtx insn
, int length
)
9210 /* A unconditional jump has an unfilled delay slot if it is not part
9211 of a sequence. A conditional jump normally has a delay slot, but
9212 does not on MIPS16. */
9213 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
9216 /* See how many nops might be needed to avoid hardware hazards. */
9217 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
9218 switch (get_attr_hazard (insn
))
9232 /* All MIPS16 instructions are a measly two bytes. */
9240 /* Return an asm sequence to start a noat block and load the address
9241 of a label into $1. */
9244 mips_output_load_label (void)
9246 if (TARGET_EXPLICIT_RELOCS
)
9250 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9253 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9256 if (ISA_HAS_LOAD_DELAY
)
9257 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9258 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9262 if (Pmode
== DImode
)
9263 return "%[dla\t%@,%0";
9265 return "%[la\t%@,%0";
9269 /* Return the assembly code for INSN, which has the operands given by
9270 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9271 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9272 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9273 version of BRANCH_IF_TRUE. */
9276 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
9277 const char *branch_if_true
,
9278 const char *branch_if_false
)
9280 unsigned int length
;
9281 rtx taken
, not_taken
;
9283 length
= get_attr_length (insn
);
9286 /* Just a simple conditional branch. */
9287 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
9288 return branch_if_true
;
9291 /* Generate a reversed branch around a direct jump. This fallback does
9292 not use branch-likely instructions. */
9293 mips_branch_likely
= false;
9294 not_taken
= gen_label_rtx ();
9295 taken
= operands
[1];
9297 /* Generate the reversed branch to NOT_TAKEN. */
9298 operands
[1] = not_taken
;
9299 output_asm_insn (branch_if_false
, operands
);
9301 /* If INSN has a delay slot, we must provide delay slots for both the
9302 branch to NOT_TAKEN and the conditional jump. We must also ensure
9303 that INSN's delay slot is executed in the appropriate cases. */
9306 /* This first delay slot will always be executed, so use INSN's
9307 delay slot if is not annulled. */
9308 if (!INSN_ANNULLED_BRANCH_P (insn
))
9310 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
9311 asm_out_file
, optimize
, 1, NULL
);
9312 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
9315 output_asm_insn ("nop", 0);
9316 fprintf (asm_out_file
, "\n");
9319 /* Output the unconditional branch to TAKEN. */
9321 output_asm_insn ("j\t%0%/", &taken
);
9324 output_asm_insn (mips_output_load_label (), &taken
);
9325 output_asm_insn ("jr\t%@%]%/", 0);
9328 /* Now deal with its delay slot; see above. */
9331 /* This delay slot will only be executed if the branch is taken.
9332 Use INSN's delay slot if is annulled. */
9333 if (INSN_ANNULLED_BRANCH_P (insn
))
9335 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
9336 asm_out_file
, optimize
, 1, NULL
);
9337 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
9340 output_asm_insn ("nop", 0);
9341 fprintf (asm_out_file
, "\n");
9344 /* Output NOT_TAKEN. */
9345 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
9346 CODE_LABEL_NUMBER (not_taken
));
9350 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9351 if some ordered condition is true. The condition is given by
9352 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9353 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9354 its second is always zero. */
9357 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
9359 const char *branch
[2];
9361 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9362 Make BRANCH[0] branch on the inverse condition. */
9363 switch (GET_CODE (operands
[0]))
9365 /* These cases are equivalent to comparisons against zero. */
9367 inverted_p
= !inverted_p
;
9370 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%1");
9371 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%1");
9374 /* These cases are always true or always false. */
9376 inverted_p
= !inverted_p
;
9379 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%1");
9380 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%1");
9384 branch
[!inverted_p
] = MIPS_BRANCH ("b%C0z", "%2,%1");
9385 branch
[inverted_p
] = MIPS_BRANCH ("b%N0z", "%2,%1");
9388 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
9391 /* Used to output div or ddiv instruction DIVISION, which has the operands
9392 given by OPERANDS. Add in a divide-by-zero check if needed.
9394 When working around R4000 and R4400 errata, we need to make sure that
9395 the division is not immediately followed by a shift[1][2]. We also
9396 need to stop the division from being put into a branch delay slot[3].
9397 The easiest way to avoid both problems is to add a nop after the
9398 division. When a divide-by-zero check is needed, this nop can be
9399 used to fill the branch delay slot.
9401 [1] If a double-word or a variable shift executes immediately
9402 after starting an integer division, the shift may give an
9403 incorrect result. See quotations of errata #16 and #28 from
9404 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9405 in mips.md for details.
9407 [2] A similar bug to [1] exists for all revisions of the
9408 R4000 and the R4400 when run in an MC configuration.
9409 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9411 "19. In this following sequence:
9413 ddiv (or ddivu or div or divu)
9414 dsll32 (or dsrl32, dsra32)
9416 if an MPT stall occurs, while the divide is slipping the cpu
9417 pipeline, then the following double shift would end up with an
9420 Workaround: The compiler needs to avoid generating any
9421 sequence with divide followed by extended double shift."
9423 This erratum is also present in "MIPS R4400MC Errata, Processor
9424 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9425 & 3.0" as errata #10 and #4, respectively.
9427 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9428 (also valid for MIPS R4000MC processors):
9430 "52. R4000SC: This bug does not apply for the R4000PC.
9432 There are two flavors of this bug:
9434 1) If the instruction just after divide takes an RF exception
9435 (tlb-refill, tlb-invalid) and gets an instruction cache
9436 miss (both primary and secondary) and the line which is
9437 currently in secondary cache at this index had the first
9438 data word, where the bits 5..2 are set, then R4000 would
9439 get a wrong result for the div.
9444 ------------------- # end-of page. -tlb-refill
9449 ------------------- # end-of page. -tlb-invalid
9452 2) If the divide is in the taken branch delay slot, where the
9453 target takes RF exception and gets an I-cache miss for the
9454 exception vector or where I-cache miss occurs for the
9455 target address, under the above mentioned scenarios, the
9456 div would get wrong results.
9459 j r2 # to next page mapped or unmapped
9460 div r8,r9 # this bug would be there as long
9461 # as there is an ICache miss and
9462 nop # the "data pattern" is present
9465 beq r0, r0, NextPage # to Next page
9469 This bug is present for div, divu, ddiv, and ddivu
9472 Workaround: For item 1), OS could make sure that the next page
9473 after the divide instruction is also mapped. For item 2), the
9474 compiler could make sure that the divide instruction is not in
9475 the branch delay slot."
9477 These processors have PRId values of 0x00004220 and 0x00004300 for
9478 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9481 mips_output_division (const char *division
, rtx
*operands
)
9486 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
9488 output_asm_insn (s
, operands
);
9491 if (TARGET_CHECK_ZERO_DIV
)
9495 output_asm_insn (s
, operands
);
9496 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
9498 else if (GENERATE_DIVIDE_TRAPS
)
9500 output_asm_insn (s
, operands
);
9505 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
9506 output_asm_insn (s
, operands
);
9507 s
= "break\t7%)\n1:";
9513 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9514 with a final "000" replaced by "k". Ignore case.
9516 Note: this function is shared between GCC and GAS. */
9519 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
9521 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
9522 given
++, canonical
++;
9524 return ((*given
== 0 && *canonical
== 0)
9525 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
9529 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9530 CPU name. We've traditionally allowed a lot of variation here.
9532 Note: this function is shared between GCC and GAS. */
9535 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
9537 /* First see if the name matches exactly, or with a final "000"
9539 if (mips_strict_matching_cpu_name_p (canonical
, given
))
9542 /* If not, try comparing based on numerical designation alone.
9543 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9544 if (TOLOWER (*given
) == 'r')
9546 if (!ISDIGIT (*given
))
9549 /* Skip over some well-known prefixes in the canonical name,
9550 hoping to find a number there too. */
9551 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
9553 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
9555 else if (TOLOWER (canonical
[0]) == 'r')
9558 return mips_strict_matching_cpu_name_p (canonical
, given
);
9562 /* Return the mips_cpu_info entry for the processor or ISA given
9563 by CPU_STRING. Return null if the string isn't recognized.
9565 A similar function exists in GAS. */
9567 static const struct mips_cpu_info
*
9568 mips_parse_cpu (const char *cpu_string
)
9570 const struct mips_cpu_info
*p
;
9573 /* In the past, we allowed upper-case CPU names, but it doesn't
9574 work well with the multilib machinery. */
9575 for (s
= cpu_string
; *s
!= 0; s
++)
9578 warning (0, "the cpu name must be lower case");
9582 /* 'from-abi' selects the most compatible architecture for the given
9583 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9584 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9585 version. Look first at the -mgp options, if given, otherwise base
9586 the choice on MASK_64BIT in TARGET_DEFAULT. */
9587 if (strcasecmp (cpu_string
, "from-abi") == 0)
9588 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
9589 : ABI_NEEDS_64BIT_REGS
? 3
9590 : (TARGET_64BIT
? 3 : 1));
9592 /* 'default' has traditionally been a no-op. Probably not very useful. */
9593 if (strcasecmp (cpu_string
, "default") == 0)
9596 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
9597 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
9604 /* Return the processor associated with the given ISA level, or null
9605 if the ISA isn't valid. */
9607 static const struct mips_cpu_info
*
9608 mips_cpu_info_from_isa (int isa
)
9610 const struct mips_cpu_info
*p
;
9612 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
9619 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9620 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9621 they only hold condition code modes, and CCmode is always considered to
9622 be 4 bytes wide. All other registers are word sized. */
9625 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
9627 if (ST_REG_P (regno
))
9628 return ((GET_MODE_SIZE (mode
) + 3) / 4);
9629 else if (! FP_REG_P (regno
))
9630 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
9632 return ((GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
);
9635 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9636 all BLKmode objects are returned in memory. Under the new (N32 and
9637 64-bit MIPS ABIs) small structures are returned in a register.
9638 Objects with varying size must still be returned in memory, of
9642 mips_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
9645 return (TYPE_MODE (type
) == BLKmode
);
9647 return ((int_size_in_bytes (type
) > (2 * UNITS_PER_WORD
))
9648 || (int_size_in_bytes (type
) == -1));
9652 mips_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
9654 return !TARGET_OLDABI
;
9657 /* Return true if INSN is a multiply-add or multiply-subtract
9658 instruction and PREV assigns to the accumulator operand. */
9661 mips_linked_madd_p (rtx prev
, rtx insn
)
9665 x
= single_set (insn
);
9671 if (GET_CODE (x
) == PLUS
9672 && GET_CODE (XEXP (x
, 0)) == MULT
9673 && reg_set_p (XEXP (x
, 1), prev
))
9676 if (GET_CODE (x
) == MINUS
9677 && GET_CODE (XEXP (x
, 1)) == MULT
9678 && reg_set_p (XEXP (x
, 0), prev
))
9684 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9685 that may clobber hi or lo. */
9687 static rtx mips_macc_chains_last_hilo
;
9689 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9690 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9693 mips_macc_chains_record (rtx insn
)
9695 if (get_attr_may_clobber_hilo (insn
))
9696 mips_macc_chains_last_hilo
= insn
;
9699 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9700 has NREADY elements, looking for a multiply-add or multiply-subtract
9701 instruction that is cumulative with mips_macc_chains_last_hilo.
9702 If there is one, promote it ahead of anything else that might
9703 clobber hi or lo. */
9706 mips_macc_chains_reorder (rtx
*ready
, int nready
)
9710 if (mips_macc_chains_last_hilo
!= 0)
9711 for (i
= nready
- 1; i
>= 0; i
--)
9712 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
9714 for (j
= nready
- 1; j
> i
; j
--)
9715 if (recog_memoized (ready
[j
]) >= 0
9716 && get_attr_may_clobber_hilo (ready
[j
]))
9718 mips_promote_ready (ready
, i
, j
);
9725 /* The last instruction to be scheduled. */
9727 static rtx vr4130_last_insn
;
9729 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9730 points to an rtx that is initially an instruction. Nullify the rtx
9731 if the instruction uses the value of register X. */
9734 vr4130_true_reg_dependence_p_1 (rtx x
, rtx pat ATTRIBUTE_UNUSED
, void *data
)
9736 rtx
*insn_ptr
= data
;
9739 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
9743 /* Return true if there is true register dependence between vr4130_last_insn
9747 vr4130_true_reg_dependence_p (rtx insn
)
9749 note_stores (PATTERN (vr4130_last_insn
),
9750 vr4130_true_reg_dependence_p_1
, &insn
);
9754 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9755 the ready queue and that INSN2 is the instruction after it, return
9756 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9757 in which INSN1 and INSN2 can probably issue in parallel, but for
9758 which (INSN2, INSN1) should be less sensitive to instruction
9759 alignment than (INSN1, INSN2). See 4130.md for more details. */
9762 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
9766 /* Check for the following case:
9768 1) there is some other instruction X with an anti dependence on INSN1;
9769 2) X has a higher priority than INSN2; and
9770 3) X is an arithmetic instruction (and thus has no unit restrictions).
9772 If INSN1 is the last instruction blocking X, it would better to
9773 choose (INSN1, X) over (INSN2, INSN1). */
9774 FOR_EACH_DEP_LINK (dep
, INSN_FORW_DEPS (insn1
))
9775 if (DEP_LINK_KIND (dep
) == REG_DEP_ANTI
9776 && INSN_PRIORITY (DEP_LINK_CON (dep
)) > INSN_PRIORITY (insn2
)
9777 && recog_memoized (DEP_LINK_CON (dep
)) >= 0
9778 && get_attr_vr4130_class (DEP_LINK_CON (dep
)) == VR4130_CLASS_ALU
)
9781 if (vr4130_last_insn
!= 0
9782 && recog_memoized (insn1
) >= 0
9783 && recog_memoized (insn2
) >= 0)
9785 /* See whether INSN1 and INSN2 use different execution units,
9786 or if they are both ALU-type instructions. If so, they can
9787 probably execute in parallel. */
9788 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
9789 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
9790 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
9792 /* If only one of the instructions has a dependence on
9793 vr4130_last_insn, prefer to schedule the other one first. */
9794 bool dep1
= vr4130_true_reg_dependence_p (insn1
);
9795 bool dep2
= vr4130_true_reg_dependence_p (insn2
);
9799 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9800 is not an ALU-type instruction and if INSN1 uses the same
9801 execution unit. (Note that if this condition holds, we already
9802 know that INSN2 uses a different execution unit.) */
9803 if (class1
!= VR4130_CLASS_ALU
9804 && recog_memoized (vr4130_last_insn
) >= 0
9805 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
9812 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9813 queue with at least two instructions. Swap the first two if
9814 vr4130_swap_insns_p says that it could be worthwhile. */
9817 vr4130_reorder (rtx
*ready
, int nready
)
9819 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
9820 mips_promote_ready (ready
, nready
- 2, nready
- 1);
9823 /* Remove the instruction at index LOWER from ready queue READY and
9824 reinsert it in front of the instruction at index HIGHER. LOWER must
9828 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
9833 new_head
= ready
[lower
];
9834 for (i
= lower
; i
< higher
; i
++)
9835 ready
[i
] = ready
[i
+ 1];
9836 ready
[i
] = new_head
;
9839 /* Implement TARGET_SCHED_REORDER. */
9842 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9843 rtx
*ready
, int *nreadyp
, int cycle
)
9845 if (!reload_completed
&& TUNE_MACC_CHAINS
)
9848 mips_macc_chains_last_hilo
= 0;
9850 mips_macc_chains_reorder (ready
, *nreadyp
);
9852 if (reload_completed
&& TUNE_MIPS4130
&& !TARGET_VR4130_ALIGN
)
9855 vr4130_last_insn
= 0;
9857 vr4130_reorder (ready
, *nreadyp
);
9859 return mips_issue_rate ();
9862 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9865 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
9868 switch (GET_CODE (PATTERN (insn
)))
9872 /* Don't count USEs and CLOBBERs against the issue rate. */
9877 if (!reload_completed
&& TUNE_MACC_CHAINS
)
9878 mips_macc_chains_record (insn
);
9879 vr4130_last_insn
= insn
;
9885 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9886 dependencies have no cost. */
9889 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
9890 rtx dep ATTRIBUTE_UNUSED
, int cost
)
9892 if (REG_NOTE_KIND (link
) != 0)
9897 /* Return the number of instructions that can be issued per cycle. */
9900 mips_issue_rate (void)
9904 case PROCESSOR_R4130
:
9905 case PROCESSOR_R5400
:
9906 case PROCESSOR_R5500
:
9907 case PROCESSOR_R7000
:
9908 case PROCESSOR_R9000
:
9912 case PROCESSOR_SB1A
:
9913 /* This is actually 4, but we get better performance if we claim 3.
9914 This is partly because of unwanted speculative code motion with the
9915 larger number, and partly because in most common cases we can't
9916 reach the theoretical max of 4. */
9924 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9925 be as wide as the scheduling freedom in the DFA. */
9928 mips_multipass_dfa_lookahead (void)
9930 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9937 /* Implements a store data bypass check. We need this because the cprestore
9938 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
9939 default routine to abort. We just return false for that case. */
9940 /* ??? Should try to give a better result here than assuming false. */
9943 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
9945 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
9948 return ! store_data_bypass_p (out_insn
, in_insn
);
9951 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9952 return the first operand of the associated "pref" or "prefx" insn. */
9955 mips_prefetch_cookie (rtx write
, rtx locality
)
9957 /* store_streamed / load_streamed. */
9958 if (INTVAL (locality
) <= 0)
9959 return GEN_INT (INTVAL (write
) + 4);
9962 if (INTVAL (locality
) <= 2)
9965 /* store_retained / load_retained. */
9966 return GEN_INT (INTVAL (write
) + 6);
9969 /* MIPS builtin function support. */
9971 struct builtin_description
9973 /* The code of the main .md file instruction. See mips_builtin_type
9974 for more information. */
9975 enum insn_code icode
;
9977 /* The floating-point comparison code to use with ICODE, if any. */
9978 enum mips_fp_condition cond
;
9980 /* The name of the builtin function. */
9983 /* Specifies how the function should be expanded. */
9984 enum mips_builtin_type builtin_type
;
9986 /* The function's prototype. */
9987 enum mips_function_type function_type
;
9989 /* The target flags required for this function. */
9993 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9994 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9995 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9996 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9997 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9999 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10001 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10002 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10003 "__builtin_mips_" #INSN "_" #COND "_s", \
10004 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10005 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10006 "__builtin_mips_" #INSN "_" #COND "_d", \
10007 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10009 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10010 The lower and upper forms require TARGET_FLAGS while the any and all
10011 forms require MASK_MIPS3D. */
10012 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10013 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10014 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10015 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10016 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10017 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10018 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10019 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10020 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10021 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10022 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10023 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10024 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10026 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10027 require MASK_MIPS3D. */
10028 #define CMP_4S_BUILTINS(INSN, COND) \
10029 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10030 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10031 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10033 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10034 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10035 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10038 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10039 instruction requires TARGET_FLAGS. */
10040 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10041 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10042 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10043 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10045 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10046 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10047 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10050 /* Define all the builtins related to c.cond.fmt condition COND. */
10051 #define CMP_BUILTINS(COND) \
10052 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10053 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10054 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10055 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10056 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10057 CMP_4S_BUILTINS (c, COND), \
10058 CMP_4S_BUILTINS (cabs, COND)
10060 static const struct builtin_description mips_bdesc
[] =
10062 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10063 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10064 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10065 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10066 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, MASK_PAIRED_SINGLE_FLOAT
),
10067 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10068 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10069 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10071 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
,
10072 MASK_PAIRED_SINGLE_FLOAT
),
10073 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10074 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10075 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10076 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10078 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
10079 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
10080 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10081 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
10082 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
10083 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10085 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
10086 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
10087 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10088 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
10089 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
10090 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10092 MIPS_FP_CONDITIONS (CMP_BUILTINS
)
10095 /* Builtin functions for the SB-1 processor. */
10097 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10099 static const struct builtin_description sb1_bdesc
[] =
10101 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
)
10104 /* Builtin functions for DSP ASE. */
10106 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10107 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10108 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10109 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10110 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10112 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10113 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10114 builtin_description fields. */
10115 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10116 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10117 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10119 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10120 branch instruction. TARGET_FLAGS is a builtin_description field. */
10121 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10122 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10123 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10125 static const struct builtin_description dsp_bdesc
[] =
10127 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10128 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10129 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10130 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10131 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10132 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10133 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10134 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10135 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10136 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10137 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10138 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10139 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10140 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, MASK_DSP
),
10141 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, MASK_DSP
),
10142 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10143 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10144 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10145 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10146 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10147 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10148 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10149 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10150 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10151 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10152 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10153 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10154 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10155 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10156 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10157 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10158 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10159 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10160 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10161 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10162 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10163 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10164 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10165 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10166 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10167 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10168 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10169 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10170 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10171 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10172 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, MASK_DSP
),
10173 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, MASK_DSP
),
10174 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10175 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10176 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10177 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10178 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10179 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10180 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10181 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10182 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10183 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10184 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10185 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10186 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, MASK_DSP
),
10187 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10188 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_PTR_SI
, MASK_DSP
),
10189 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_PTR_SI
, MASK_DSP
),
10190 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_PTR_SI
, MASK_DSP
),
10191 BPOSGE_BUILTIN (32, MASK_DSP
),
10193 /* The following are for the MIPS DSP ASE REV 2. */
10194 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, MASK_DSPR2
),
10195 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10196 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10197 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10198 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10199 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10200 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10201 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10202 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10203 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10204 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10205 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10206 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10207 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10208 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10209 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10210 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10211 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10212 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10213 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSPR2
),
10214 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSPR2
),
10215 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSPR2
),
10216 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10217 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10218 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10219 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10220 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10221 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10222 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10223 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10224 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10225 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10226 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10227 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
)
10230 static const struct builtin_description dsp_32only_bdesc
[] =
10232 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10233 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10234 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10235 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10236 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10237 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10238 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10239 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10240 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10241 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10242 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10243 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10244 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10245 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10246 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10247 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10248 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10249 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10250 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10251 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10252 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10254 /* The following are for the MIPS DSP ASE REV 2. */
10255 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10256 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10257 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSPR2
),
10258 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, MASK_DSPR2
),
10259 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSPR2
),
10260 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, MASK_DSPR2
),
10261 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10262 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, MASK_DSPR2
),
10263 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, MASK_DSPR2
),
10264 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10265 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10266 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10267 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10268 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10269 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
)
10272 /* This helps provide a mapping from builtin function codes to bdesc
10277 /* The builtin function table that this entry describes. */
10278 const struct builtin_description
*bdesc
;
10280 /* The number of entries in the builtin function table. */
10283 /* The target processor that supports these builtin functions.
10284 PROCESSOR_MAX means we enable them for all processors. */
10285 enum processor_type proc
;
10287 /* If the target has these flags, this builtin function table
10288 will not be supported. */
10289 int unsupported_target_flags
;
10292 static const struct bdesc_map bdesc_arrays
[] =
10294 { mips_bdesc
, ARRAY_SIZE (mips_bdesc
), PROCESSOR_MAX
, 0 },
10295 { sb1_bdesc
, ARRAY_SIZE (sb1_bdesc
), PROCESSOR_SB1
, 0 },
10296 { dsp_bdesc
, ARRAY_SIZE (dsp_bdesc
), PROCESSOR_MAX
, 0 },
10297 { dsp_32only_bdesc
, ARRAY_SIZE (dsp_32only_bdesc
), PROCESSOR_MAX
,
10301 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
10302 suitable for input operand OP of instruction ICODE. Return the value. */
10305 mips_prepare_builtin_arg (enum insn_code icode
,
10306 unsigned int op
, tree exp
, unsigned int argnum
)
10309 enum machine_mode mode
;
10311 value
= expand_normal (CALL_EXPR_ARG (exp
, argnum
));
10312 mode
= insn_data
[icode
].operand
[op
].mode
;
10313 if (!insn_data
[icode
].operand
[op
].predicate (value
, mode
))
10315 value
= copy_to_mode_reg (mode
, value
);
10316 /* Check the predicate again. */
10317 if (!insn_data
[icode
].operand
[op
].predicate (value
, mode
))
10319 error ("invalid argument to builtin function");
10327 /* Return an rtx suitable for output operand OP of instruction ICODE.
10328 If TARGET is non-null, try to use it where possible. */
10331 mips_prepare_builtin_target (enum insn_code icode
, unsigned int op
, rtx target
)
10333 enum machine_mode mode
;
10335 mode
= insn_data
[icode
].operand
[op
].mode
;
10336 if (target
== 0 || !insn_data
[icode
].operand
[op
].predicate (target
, mode
))
10337 target
= gen_reg_rtx (mode
);
10342 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10345 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10346 enum machine_mode mode ATTRIBUTE_UNUSED
,
10347 int ignore ATTRIBUTE_UNUSED
)
10349 enum insn_code icode
;
10350 enum mips_builtin_type type
;
10352 unsigned int fcode
;
10353 const struct builtin_description
*bdesc
;
10354 const struct bdesc_map
*m
;
10356 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10357 fcode
= DECL_FUNCTION_CODE (fndecl
);
10360 for (m
= bdesc_arrays
; m
< &bdesc_arrays
[ARRAY_SIZE (bdesc_arrays
)]; m
++)
10362 if (fcode
< m
->size
)
10365 icode
= bdesc
[fcode
].icode
;
10366 type
= bdesc
[fcode
].builtin_type
;
10376 case MIPS_BUILTIN_DIRECT
:
10377 return mips_expand_builtin_direct (icode
, target
, exp
, true);
10379 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
10380 return mips_expand_builtin_direct (icode
, target
, exp
, false);
10382 case MIPS_BUILTIN_MOVT
:
10383 case MIPS_BUILTIN_MOVF
:
10384 return mips_expand_builtin_movtf (type
, icode
, bdesc
[fcode
].cond
,
10387 case MIPS_BUILTIN_CMP_ANY
:
10388 case MIPS_BUILTIN_CMP_ALL
:
10389 case MIPS_BUILTIN_CMP_UPPER
:
10390 case MIPS_BUILTIN_CMP_LOWER
:
10391 case MIPS_BUILTIN_CMP_SINGLE
:
10392 return mips_expand_builtin_compare (type
, icode
, bdesc
[fcode
].cond
,
10395 case MIPS_BUILTIN_BPOSGE32
:
10396 return mips_expand_builtin_bposge (type
, target
);
10403 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10406 mips_init_builtins (void)
10408 const struct builtin_description
*d
;
10409 const struct bdesc_map
*m
;
10410 tree types
[(int) MIPS_MAX_FTYPE_MAX
];
10411 tree V2SF_type_node
;
10412 tree V2HI_type_node
;
10413 tree V4QI_type_node
;
10414 unsigned int offset
;
10416 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10417 if (!TARGET_PAIRED_SINGLE_FLOAT
&& !TARGET_DSP
)
10420 if (TARGET_PAIRED_SINGLE_FLOAT
)
10422 V2SF_type_node
= build_vector_type_for_mode (float_type_node
, V2SFmode
);
10424 types
[MIPS_V2SF_FTYPE_V2SF
]
10425 = build_function_type_list (V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10427 types
[MIPS_V2SF_FTYPE_V2SF_V2SF
]
10428 = build_function_type_list (V2SF_type_node
,
10429 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10431 types
[MIPS_V2SF_FTYPE_V2SF_V2SF_INT
]
10432 = build_function_type_list (V2SF_type_node
,
10433 V2SF_type_node
, V2SF_type_node
,
10434 integer_type_node
, NULL_TREE
);
10436 types
[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF
]
10437 = build_function_type_list (V2SF_type_node
,
10438 V2SF_type_node
, V2SF_type_node
,
10439 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10441 types
[MIPS_V2SF_FTYPE_SF_SF
]
10442 = build_function_type_list (V2SF_type_node
,
10443 float_type_node
, float_type_node
, NULL_TREE
);
10445 types
[MIPS_INT_FTYPE_V2SF_V2SF
]
10446 = build_function_type_list (integer_type_node
,
10447 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10449 types
[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF
]
10450 = build_function_type_list (integer_type_node
,
10451 V2SF_type_node
, V2SF_type_node
,
10452 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
10454 types
[MIPS_INT_FTYPE_SF_SF
]
10455 = build_function_type_list (integer_type_node
,
10456 float_type_node
, float_type_node
, NULL_TREE
);
10458 types
[MIPS_INT_FTYPE_DF_DF
]
10459 = build_function_type_list (integer_type_node
,
10460 double_type_node
, double_type_node
, NULL_TREE
);
10462 types
[MIPS_SF_FTYPE_V2SF
]
10463 = build_function_type_list (float_type_node
, V2SF_type_node
, NULL_TREE
);
10465 types
[MIPS_SF_FTYPE_SF
]
10466 = build_function_type_list (float_type_node
,
10467 float_type_node
, NULL_TREE
);
10469 types
[MIPS_SF_FTYPE_SF_SF
]
10470 = build_function_type_list (float_type_node
,
10471 float_type_node
, float_type_node
, NULL_TREE
);
10473 types
[MIPS_DF_FTYPE_DF
]
10474 = build_function_type_list (double_type_node
,
10475 double_type_node
, NULL_TREE
);
10477 types
[MIPS_DF_FTYPE_DF_DF
]
10478 = build_function_type_list (double_type_node
,
10479 double_type_node
, double_type_node
, NULL_TREE
);
10484 V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
10485 V4QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V4QImode
);
10487 types
[MIPS_V2HI_FTYPE_V2HI_V2HI
]
10488 = build_function_type_list (V2HI_type_node
,
10489 V2HI_type_node
, V2HI_type_node
,
10492 types
[MIPS_SI_FTYPE_SI_SI
]
10493 = build_function_type_list (intSI_type_node
,
10494 intSI_type_node
, intSI_type_node
,
10497 types
[MIPS_V4QI_FTYPE_V4QI_V4QI
]
10498 = build_function_type_list (V4QI_type_node
,
10499 V4QI_type_node
, V4QI_type_node
,
10502 types
[MIPS_SI_FTYPE_V4QI
]
10503 = build_function_type_list (intSI_type_node
,
10507 types
[MIPS_V2HI_FTYPE_V2HI
]
10508 = build_function_type_list (V2HI_type_node
,
10512 types
[MIPS_SI_FTYPE_SI
]
10513 = build_function_type_list (intSI_type_node
,
10517 types
[MIPS_V4QI_FTYPE_V2HI_V2HI
]
10518 = build_function_type_list (V4QI_type_node
,
10519 V2HI_type_node
, V2HI_type_node
,
10522 types
[MIPS_V2HI_FTYPE_SI_SI
]
10523 = build_function_type_list (V2HI_type_node
,
10524 intSI_type_node
, intSI_type_node
,
10527 types
[MIPS_SI_FTYPE_V2HI
]
10528 = build_function_type_list (intSI_type_node
,
10532 types
[MIPS_V2HI_FTYPE_V4QI
]
10533 = build_function_type_list (V2HI_type_node
,
10537 types
[MIPS_V4QI_FTYPE_V4QI_SI
]
10538 = build_function_type_list (V4QI_type_node
,
10539 V4QI_type_node
, intSI_type_node
,
10542 types
[MIPS_V2HI_FTYPE_V2HI_SI
]
10543 = build_function_type_list (V2HI_type_node
,
10544 V2HI_type_node
, intSI_type_node
,
10547 types
[MIPS_V2HI_FTYPE_V4QI_V2HI
]
10548 = build_function_type_list (V2HI_type_node
,
10549 V4QI_type_node
, V2HI_type_node
,
10552 types
[MIPS_SI_FTYPE_V2HI_V2HI
]
10553 = build_function_type_list (intSI_type_node
,
10554 V2HI_type_node
, V2HI_type_node
,
10557 types
[MIPS_DI_FTYPE_DI_V4QI_V4QI
]
10558 = build_function_type_list (intDI_type_node
,
10559 intDI_type_node
, V4QI_type_node
, V4QI_type_node
,
10562 types
[MIPS_DI_FTYPE_DI_V2HI_V2HI
]
10563 = build_function_type_list (intDI_type_node
,
10564 intDI_type_node
, V2HI_type_node
, V2HI_type_node
,
10567 types
[MIPS_DI_FTYPE_DI_SI_SI
]
10568 = build_function_type_list (intDI_type_node
,
10569 intDI_type_node
, intSI_type_node
, intSI_type_node
,
10572 types
[MIPS_V4QI_FTYPE_SI
]
10573 = build_function_type_list (V4QI_type_node
,
10577 types
[MIPS_V2HI_FTYPE_SI
]
10578 = build_function_type_list (V2HI_type_node
,
10582 types
[MIPS_VOID_FTYPE_V4QI_V4QI
]
10583 = build_function_type_list (void_type_node
,
10584 V4QI_type_node
, V4QI_type_node
,
10587 types
[MIPS_SI_FTYPE_V4QI_V4QI
]
10588 = build_function_type_list (intSI_type_node
,
10589 V4QI_type_node
, V4QI_type_node
,
10592 types
[MIPS_VOID_FTYPE_V2HI_V2HI
]
10593 = build_function_type_list (void_type_node
,
10594 V2HI_type_node
, V2HI_type_node
,
10597 types
[MIPS_SI_FTYPE_DI_SI
]
10598 = build_function_type_list (intSI_type_node
,
10599 intDI_type_node
, intSI_type_node
,
10602 types
[MIPS_DI_FTYPE_DI_SI
]
10603 = build_function_type_list (intDI_type_node
,
10604 intDI_type_node
, intSI_type_node
,
10607 types
[MIPS_VOID_FTYPE_SI_SI
]
10608 = build_function_type_list (void_type_node
,
10609 intSI_type_node
, intSI_type_node
,
10612 types
[MIPS_SI_FTYPE_PTR_SI
]
10613 = build_function_type_list (intSI_type_node
,
10614 ptr_type_node
, intSI_type_node
,
10617 types
[MIPS_SI_FTYPE_VOID
]
10618 = build_function_type (intSI_type_node
, void_list_node
);
10622 types
[MIPS_V4QI_FTYPE_V4QI
]
10623 = build_function_type_list (V4QI_type_node
,
10627 types
[MIPS_SI_FTYPE_SI_SI_SI
]
10628 = build_function_type_list (intSI_type_node
,
10629 intSI_type_node
, intSI_type_node
,
10630 intSI_type_node
, NULL_TREE
);
10632 types
[MIPS_DI_FTYPE_DI_USI_USI
]
10633 = build_function_type_list (intDI_type_node
,
10635 unsigned_intSI_type_node
,
10636 unsigned_intSI_type_node
, NULL_TREE
);
10638 types
[MIPS_DI_FTYPE_SI_SI
]
10639 = build_function_type_list (intDI_type_node
,
10640 intSI_type_node
, intSI_type_node
,
10643 types
[MIPS_DI_FTYPE_USI_USI
]
10644 = build_function_type_list (intDI_type_node
,
10645 unsigned_intSI_type_node
,
10646 unsigned_intSI_type_node
, NULL_TREE
);
10648 types
[MIPS_V2HI_FTYPE_SI_SI_SI
]
10649 = build_function_type_list (V2HI_type_node
,
10650 intSI_type_node
, intSI_type_node
,
10651 intSI_type_node
, NULL_TREE
);
10656 /* Iterate through all of the bdesc arrays, initializing all of the
10657 builtin functions. */
10660 for (m
= bdesc_arrays
; m
< &bdesc_arrays
[ARRAY_SIZE (bdesc_arrays
)]; m
++)
10662 if ((m
->proc
== PROCESSOR_MAX
|| (m
->proc
== mips_arch
))
10663 && (m
->unsupported_target_flags
& target_flags
) == 0)
10664 for (d
= m
->bdesc
; d
< &m
->bdesc
[m
->size
]; d
++)
10665 if ((d
->target_flags
& target_flags
) == d
->target_flags
)
10666 add_builtin_function (d
->name
, types
[d
->function_type
],
10667 d
- m
->bdesc
+ offset
,
10668 BUILT_IN_MD
, NULL
, NULL
);
10673 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10674 .md pattern and CALL is the function expr with arguments. TARGET,
10675 if nonnull, suggests a good place to put the result.
10676 HAS_TARGET indicates the function must return something. */
10679 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
10682 rtx ops
[MAX_RECOG_OPERANDS
];
10688 /* We save target to ops[0]. */
10689 ops
[0] = mips_prepare_builtin_target (icode
, 0, target
);
10693 /* We need to test if the arglist is not zero. Some instructions have extra
10694 clobber registers. */
10695 for (; i
< insn_data
[icode
].n_operands
&& i
<= call_expr_nargs (exp
); i
++, j
++)
10696 ops
[i
] = mips_prepare_builtin_arg (icode
, i
, exp
, j
);
10701 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1]));
10705 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2]));
10709 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2], ops
[3]));
10713 gcc_unreachable ();
10718 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10719 function (TYPE says which). EXP is the tree for the function
10720 function, ICODE is the instruction that should be used to compare
10721 the first two arguments, and COND is the condition it should test.
10722 TARGET, if nonnull, suggests a good place to put the result. */
10725 mips_expand_builtin_movtf (enum mips_builtin_type type
,
10726 enum insn_code icode
, enum mips_fp_condition cond
,
10727 rtx target
, tree exp
)
10729 rtx cmp_result
, op0
, op1
;
10731 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10732 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 0);
10733 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 1);
10734 emit_insn (GEN_FCN (icode
) (cmp_result
, op0
, op1
, GEN_INT (cond
)));
10736 icode
= CODE_FOR_mips_cond_move_tf_ps
;
10737 target
= mips_prepare_builtin_target (icode
, 0, target
);
10738 if (type
== MIPS_BUILTIN_MOVT
)
10740 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 2);
10741 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 3);
10745 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 2);
10746 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 3);
10748 emit_insn (gen_mips_cond_move_tf_ps (target
, op0
, op1
, cmp_result
));
10752 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10753 into TARGET otherwise. Return TARGET. */
10756 mips_builtin_branch_and_move (rtx condition
, rtx target
,
10757 rtx value_if_true
, rtx value_if_false
)
10759 rtx true_label
, done_label
;
10761 true_label
= gen_label_rtx ();
10762 done_label
= gen_label_rtx ();
10764 /* First assume that CONDITION is false. */
10765 emit_move_insn (target
, value_if_false
);
10767 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10768 emit_jump_insn (gen_condjump (condition
, true_label
));
10769 emit_jump_insn (gen_jump (done_label
));
10772 /* Fix TARGET if CONDITION is true. */
10773 emit_label (true_label
);
10774 emit_move_insn (target
, value_if_true
);
10776 emit_label (done_label
);
10780 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10781 of the comparison instruction and COND is the condition it should test.
10782 EXP is the function call and arguments and TARGET, if nonnull,
10783 suggests a good place to put the boolean result. */
10786 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
10787 enum insn_code icode
, enum mips_fp_condition cond
,
10788 rtx target
, tree exp
)
10790 rtx offset
, condition
, cmp_result
, ops
[MAX_RECOG_OPERANDS
];
10794 if (target
== 0 || GET_MODE (target
) != SImode
)
10795 target
= gen_reg_rtx (SImode
);
10797 /* Prepare the operands to the comparison. */
10798 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10799 for (i
= 1; i
< insn_data
[icode
].n_operands
- 1; i
++, j
++)
10800 ops
[i
] = mips_prepare_builtin_arg (icode
, i
, exp
, j
);
10802 switch (insn_data
[icode
].n_operands
)
10805 emit_insn (GEN_FCN (icode
) (cmp_result
, ops
[1], ops
[2], GEN_INT (cond
)));
10809 emit_insn (GEN_FCN (icode
) (cmp_result
, ops
[1], ops
[2],
10810 ops
[3], ops
[4], GEN_INT (cond
)));
10814 gcc_unreachable ();
10817 /* If the comparison sets more than one register, we define the result
10818 to be 0 if all registers are false and -1 if all registers are true.
10819 The value of the complete result is indeterminate otherwise. */
10820 switch (builtin_type
)
10822 case MIPS_BUILTIN_CMP_ALL
:
10823 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
10824 return mips_builtin_branch_and_move (condition
, target
,
10825 const0_rtx
, const1_rtx
);
10827 case MIPS_BUILTIN_CMP_UPPER
:
10828 case MIPS_BUILTIN_CMP_LOWER
:
10829 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
10830 condition
= gen_single_cc (cmp_result
, offset
);
10831 return mips_builtin_branch_and_move (condition
, target
,
10832 const1_rtx
, const0_rtx
);
10835 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
10836 return mips_builtin_branch_and_move (condition
, target
,
10837 const1_rtx
, const0_rtx
);
10841 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10842 suggests a good place to put the boolean result. */
10845 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
10847 rtx condition
, cmp_result
;
10850 if (target
== 0 || GET_MODE (target
) != SImode
)
10851 target
= gen_reg_rtx (SImode
);
10853 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
10855 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
10860 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
10861 return mips_builtin_branch_and_move (condition
, target
,
10862 const1_rtx
, const0_rtx
);
10865 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10866 FIRST is true if this is the first time handling this decl. */
10869 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
10871 default_encode_section_info (decl
, rtl
, first
);
10873 if (TREE_CODE (decl
) == FUNCTION_DECL
10874 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
10876 rtx symbol
= XEXP (rtl
, 0);
10877 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
10881 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. PIC_FUNCTION_ADDR_REGNUM is live
10882 on entry to a function when generating -mshared abicalls code. */
10885 mips_extra_live_on_entry (bitmap regs
)
10887 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
10888 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10891 /* SImode values are represented as sign-extended to DImode. */
10894 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
10896 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
10897 return SIGN_EXTEND
;
10902 #include "gt-mips.h"