| blob | 3b1c9ef6000d2d6f86d24de04a001f57e017e381 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
71 /* This file should be included last. */
74 /* Defined for convenience. */
75 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
77 /* Classifies an address.
79 ADDRESS_REG_IMM
80 A simple base register plus immediate offset.
82 ADDRESS_REG_WB
83 A base register indexed by immediate offset with writeback.
85 ADDRESS_REG_REG
86 A base register indexed by (optionally scaled) register.
88 ADDRESS_REG_UXTW
89 A base register indexed by (optionally scaled) zero-extended register.
91 ADDRESS_REG_SXTW
92 A base register indexed by (optionally scaled) sign-extended register.
94 ADDRESS_LO_SUM
95 A LO_SUM rtx with a base register and "LO12" symbol relocation.
97 ADDRESS_SYMBOLIC:
98 A constant symbolic address, in pc-relative literal pool. */
101 ADDRESS_REG_IMM,
102 ADDRESS_REG_WB,
103 ADDRESS_REG_REG,
104 ADDRESS_REG_UXTW,
105 ADDRESS_REG_SXTW,
106 ADDRESS_LO_SUM,
107 ADDRESS_SYMBOLIC
108 };
112 rtx base;
113 rtx offset;
116 };
118 struct simd_immediate_info
119 {
120 rtx value;
125 };
127 /* The current code model. */
130 #ifdef HAVE_AS_TLS
131 #undef TARGET_HAVE_TLS
132 #define TARGET_HAVE_TLS 1
133 #endif
137 const_tree,
148 const_tree type,
151 static machine_mode
154 /* Major revision number of the ARM Architecture implemented by the target. */
157 /* The processor for which instructions should be scheduled. */
160 /* Mask to specify which instruction scheduling options should be used. */
163 /* Global flag for PC relative loads. */
166 /* Support for command line parsing of boolean flags in the tuning
167 structures. */
168 struct aarch64_flag_desc
169 {
172 };
174 #define AARCH64_FUSION_PAIR(name, internal_name) \
175 { name, AARCH64_FUSE_##internal_name },
177 {
182 };
184 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
185 { name, AARCH64_EXTRA_TUNE_##internal_name },
187 {
192 };
194 /* Tuning parameters. */
197 {
198 {
203 },
210 };
213 {
214 {
219 },
226 };
229 {
230 {
235 },
242 };
245 {
246 {
251 },
258 };
261 {
263 /* Avoid the use of slow int<->fp moves for spilling by setting
264 their cost higher than memmov_cost. */
268 };
271 {
273 /* Avoid the use of slow int<->fp moves for spilling by setting
274 their cost higher than memmov_cost. */
278 };
281 {
283 /* Avoid the use of slow int<->fp moves for spilling by setting
284 their cost higher than memmov_cost. */
288 };
291 {
293 /* Avoid the use of slow int<->fp moves for spilling by setting
294 their cost higher than memmov_cost (actual, 4 and 9). */
298 };
301 {
306 };
309 {
311 /* Avoid the use of slow int<->fp moves for spilling by setting
312 their cost higher than memmov_cost. */
316 };
319 {
321 /* Avoid the use of int<->fp moves for spilling. */
325 };
328 {
330 /* Avoid the use of int<->fp moves for spilling. */
334 };
336 /* Generic costs for vector insn classes. */
338 {
354 };
356 /* ThunderX costs for vector insn classes. */
358 {
374 };
376 /* Generic costs for vector insn classes. */
378 {
394 };
397 {
413 };
415 /* Generic costs for vector insn classes. */
417 {
433 };
435 /* Costs for vector insn classes for Vulcan. */
437 {
453 };
455 /* Generic costs for branch instructions. */
457 {
460 };
462 /* Generic approximation modes. */
464 {
467 AARCH64_APPROX_NONE /* recip_sqrt */
468 };
470 /* Approximation modes for Exynos M1. */
472 {
475 AARCH64_APPROX_ALL /* recip_sqrt */
476 };
478 /* Approximation modes for X-Gene 1. */
480 {
483 AARCH64_APPROX_ALL /* recip_sqrt */
484 };
486 /* Generic prefetch settings (which disable prefetch). */
488 {
494 };
497 {
503 };
506 {
512 };
515 {
521 };
524 {
530 };
533 {
539 };
542 {
563 &generic_prefetch_tune
564 };
567 {
589 &generic_prefetch_tune
590 };
593 {
615 &generic_prefetch_tune
616 };
619 {
641 &generic_prefetch_tune
642 };
645 {
667 &generic_prefetch_tune
668 };
671 {
693 &generic_prefetch_tune
694 };
699 {
720 &exynosm1_prefetch_tune
721 };
724 {
745 &thunderxt88_prefetch_tune
746 };
749 {
769 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
771 &thunderx_prefetch_tune
772 };
775 {
796 &generic_prefetch_tune
797 };
800 {
822 &qdf24xx_prefetch_tune
823 };
826 {
848 &thunderx2t99_prefetch_tune
849 };
851 /* Support for fine-grained override of the tuning structures. */
852 struct aarch64_tuning_override_function
853 {
856 };
861 static const struct aarch64_tuning_override_function
862 aarch64_tuning_override_functions[] =
863 {
867 };
869 /* A processor implementing AArch64. */
870 struct processor
871 {
879 };
881 /* Architectures implementing AArch64. */
883 {
884 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
885 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
888 };
890 /* Processor cores implementing AArch64. */
892 {
893 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
894 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
895 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
896 FLAGS, &COSTS##_tunings},
901 };
904 /* Target specification. These are populated by the -march, -mtune, -mcpu
905 handling code or by target attributes. */
910 /* The current tuning set. */
913 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
915 /* An ISA extension in the co-processor and main instruction set space. */
916 struct aarch64_option_extension
917 {
921 };
924 {
928 }
929 aarch64_cc;
931 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
933 /* The condition codes of the processor, and the inverse function. */
935 {
938 };
940 /* Generate code to enable conditional branches in functions over 1 MiB. */
944 {
961 }
963 void
965 {
969 else
971 }
973 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
974 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
975 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
976 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
977 cost (in this case the best class is the lowest cost one). Using ALL_REGS
978 irrespectively of its cost results in bad allocations with many redundant
979 int<->FP moves which are expensive on various cores.
980 To avoid this we don't allow ALL_REGS as the allocno class, but force a
981 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
982 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
983 Otherwise set the allocno class depending on the mode.
984 The result of this is that it is no longer inefficient to have a higher
985 memory move cost than the register move cost.
986 */
988 static reg_class_t
990 reg_class_t best_class)
991 {
992 machine_mode mode;
1002 }
1004 static unsigned int
1006 {
1010 }
1012 static int
1014 machine_mode mode)
1015 {
1023 }
1025 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1026 unsigned
1028 {
1036 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1037 equivalent DWARF register. */
1039 }
1041 /* Return TRUE if MODE is any of the large INT modes. */
1042 static bool
1044 {
1046 }
1048 /* Return TRUE if MODE is any of the vector modes. */
1049 static bool
1051 {
1054 }
1056 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1057 static bool
1060 {
1068 }
1070 /* Implement HARD_REGNO_NREGS. */
1072 int
1074 {
1076 {
1082 }
1084 }
1086 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1088 static bool
1090 {
1095 /* The purpose of comparing with ptr_mode is to support the
1096 global register variable associated with the stack pointer
1097 register via the syntax of asm ("wsp") in ILP32. */
1107 {
1110 else
1112 }
1115 }
1117 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1118 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1119 clobbers the top 64 bits when restoring the bottom 64 bits. */
1121 static bool
1123 {
1125 }
1127 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1128 machine_mode
1130 machine_mode mode)
1131 {
1132 /* Handle modes that fit within single registers. */
1134 {
1137 else
1139 }
1140 /* Fall back to generic for multi-reg and very large modes. */
1141 else
1143 }
1145 /* Return true if calls to DECL should be treated as
1146 long-calls (ie called via a register). */
1147 static bool
1149 {
1151 }
1153 /* Return true if calls to symbol-ref SYM should be treated as
1154 long-calls (ie called via a register). */
1155 bool
1157 {
1159 }
1161 /* Return true if calls to symbol-ref SYM should not go through
1162 plt stubs. */
1164 bool
1166 {
1170 && decl
1171 && (!flag_plt
1177 }
1179 /* Return true if the offsets to a zero/sign-extract operation
1180 represent an expression that matches an extend operation. The
1181 operands represent the paramters from
1183 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1184 bool
1186 rtx extract_imm)
1187 {
1204 }
1206 /* Emit an insn that's a simple single-set. Both the operands must be
1207 known to be valid. */
1210 {
1212 }
1214 /* X and Y are two things to compare using CODE. Emit the compare insn and
1215 return the rtx for register 0 in the proper mode. */
1216 rtx
1218 {
1224 }
1226 /* Build the SYMBOL_REF for __tls_get_addr. */
1230 rtx
1232 {
1236 }
1238 /* Return the TLS model to use for ADDR. */
1240 static enum tls_model
1242 {
1247 {
1251 }
1256 }
1258 /* We'll allow lo_sum's in addresses in our legitimate addresses
1259 so that combine would take care of combining addresses where
1260 necessary, but for generation purposes, we'll generate the address
1261 as :
1262 RTL Absolute
1263 tmp = hi (symbol_ref); adrp x1, foo
1264 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1265 nop
1267 PIC TLS
1268 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1269 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1270 bl __tls_get_addr
1271 nop
1273 Load TLS symbol, depending on TLS mechanism and TLS access model.
1275 Global Dynamic - Traditional TLS:
1276 adrp tmp, :tlsgd:imm
1277 add dest, tmp, #:tlsgd_lo12:imm
1278 bl __tls_get_addr
1280 Global Dynamic - TLS Descriptors:
1281 adrp dest, :tlsdesc:imm
1282 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1283 add dest, dest, #:tlsdesc_lo12:imm
1284 blr tmp
1285 mrs tp, tpidr_el0
1286 add dest, dest, tp
1288 Initial Exec:
1289 mrs tp, tpidr_el0
1290 adrp tmp, :gottprel:imm
1291 ldr dest, [tmp, #:gottprel_lo12:imm]
1292 add dest, dest, tp
1294 Local Exec:
1295 mrs tp, tpidr_el0
1296 add t0, tp, #:tprel_hi12:imm, lsl #12
1297 add t0, t0, #:tprel_lo12_nc:imm
1298 */
1300 static void
1303 {
1305 {
1307 {
1308 /* In ILP32, the mode of dest can be either SImode or DImode. */
1320 }
1327 {
1330 rtx insn;
1331 rtx mem;
1333 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1334 here before rtl expand. Tree IVOPT will generate rtl pattern to
1335 decide rtx costs, in which case pic_offset_table_rtx is not
1336 initialized. For that case no need to generate the first adrp
1337 instruction as the final cost for global variable access is
1338 one instruction. */
1340 {
1341 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1342 using the page base as GOT base, the first page may be wasted,
1343 in the worst scenario, there is only 28K space for GOT).
1345 The generate instruction sequence for accessing global variable
1346 is:
1348 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1350 Only one instruction needed. But we must initialize
1351 pic_offset_table_rtx properly. We generate initialize insn for
1352 every global access, and allow CSE to remove all redundant.
1354 The final instruction sequences will look like the following
1355 for multiply global variables access.
1357 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1359 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1360 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1361 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1362 ... */
1371 }
1374 {
1377 else
1381 }
1382 else
1383 {
1388 }
1390 /* The operand is expected to be MEM. Whenever the related insn
1391 pattern changed, above code which calculate mem should be
1392 updated. */
1398 }
1401 {
1402 /* In ILP32, the mode of dest can be either SImode or DImode,
1403 while the got entry is always of SImode size. The mode of
1404 dest depends on how dest is used: if dest is assigned to a
1405 pointer (e.g. in the memory), it has SImode; it may have
1406 DImode if dest is dereferenced to access the memeory.
1407 This is why we have to handle three different ldr_got_small
1408 patterns here (two patterns for ILP32). */
1410 rtx insn;
1411 rtx mem;
1420 {
1423 else
1427 }
1428 else
1429 {
1434 }
1441 }
1444 {
1452 else
1460 }
1463 {
1466 rtx tp;
1470 /* In ILP32, the got entry is always of SImode size. Unlike
1471 small GOT, the dest is fixed at reg 0. */
1474 else
1484 }
1487 {
1488 /* In ILP32, the mode of dest can be either SImode or DImode,
1489 while the got entry is always of SImode size. The mode of
1490 dest depends on how dest is used: if dest is assigned to a
1491 pointer (e.g. in the memory), it has SImode; it may have
1492 DImode if dest is dereferenced to access the memeory.
1493 This is why we have to handle three different tlsie_small
1494 patterns here (two patterns for ILP32). */
1500 {
1503 else
1504 {
1507 }
1508 }
1509 else
1510 {
1513 }
1518 }
1524 {
1532 {
1555 }
1559 }
1566 {
1571 {
1574 else
1575 {
1578 }
1579 }
1580 else
1581 {
1584 }
1588 }
1592 }
1593 }
1595 /* Emit a move from SRC to DEST. Assume that the move expanders can
1596 handle all moves if !can_create_pseudo_p (). The distinction is
1597 important because, unlike emit_move_insn, the move expanders know
1598 how to force Pmode objects into the constant pool even when the
1599 constant pool address is not itself legitimate. */
1600 static rtx
1602 {
1606 }
1608 /* Split a 128-bit move operation into two 64-bit move operations,
1609 taking care to handle partial overlap of register to register
1610 copies. Special cases are needed when moving between GP regs and
1611 FP regs. SRC can be a register, constant or memory; DST a register
1612 or memory. If either operand is memory it must not have any side
1613 effects. */
1614 void
1616 {
1627 {
1631 /* Handle FP <-> GP regs. */
1633 {
1638 {
1641 }
1642 else
1643 {
1646 }
1648 }
1650 {
1655 {
1658 }
1659 else
1660 {
1663 }
1665 }
1666 }
1673 /* At most one pairing may overlap. */
1675 {
1678 }
1679 else
1680 {
1683 }
1684 }
1686 bool
1688 {
1691 }
1693 /* Split a complex SIMD combine. */
1695 void
1697 {
1709 {
1733 }
1737 }
1739 /* Split a complex SIMD move. */
1741 void
1743 {
1750 {
1756 {
1780 }
1784 }
1785 }
1787 bool
1790 {
1794 }
1797 static rtx
1799 {
1802 else
1803 {
1806 }
1807 }
1810 static rtx
1812 HOST_WIDE_INT offset)
1813 {
1815 {
1816 rtx high;
1817 /* Load the full offset into a register. This
1818 might be improvable in the future. */
1824 }
1826 }
1828 static int
1830 scalar_int_mode mode)
1831 {
1840 {
1844 }
1846 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1847 (with XXXX non-zero). In that case check to see if the move can be done in
1848 a smaller mode. */
1853 {
1857 /* Check if we have to emit a second instruction by checking to see
1858 if any of the upper 32 bits of the original DI mode value is set. */
1869 }
1872 {
1874 {
1879 else
1882 }
1884 }
1886 /* Remaining cases are all for DImode. */
1895 {
1896 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1897 For a 64-bit bitmask try whether changing 16 bits to all ones or
1898 zeroes creates a valid bitmask. To check any repeated bitmask,
1899 try using 16 bits from the other 32-bit half of val. */
1902 {
1913 }
1915 {
1917 {
1921 }
1923 }
1924 }
1926 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1927 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1928 otherwise skip zero bits. */
1940 {
1946 num_insns ++;
1947 }
1950 }
1953 void
1955 {
1960 /* Check on what type of symbol it is. */
1961 scalar_int_mode int_mode;
1966 {
1970 /* If we have (const (plus symbol offset)), separate out the offset
1971 before we start classifying the symbol. */
1976 {
1980 {
1987 }
1992 /* If we aren't generating PC relative literals, then
1993 we need to expand the literal pool access carefully.
1994 This is something that needs to be done in a number
1995 of places, so could well live as a separate function. */
1997 {
2004 }
2021 {
2028 }
2029 /* FALLTHRU */
2042 }
2043 }
2046 {
2049 else
2050 {
2054 }
2057 }
2061 }
2063 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
2064 temporary value if necessary. FRAME_RELATED_P should be true if
2065 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
2066 to the generated instructions. If SCRATCHREG is known to hold
2067 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2068 immediate again.
2070 Since this function may be used to adjust the stack pointer, we must
2071 ensure that it cannot cause transient stack deallocation (for example
2072 by first incrementing SP and then decrementing when adjusting by a
2073 large immediate). */
2075 static void
2079 {
2087 /* Single instruction adjustment. */
2089 {
2093 }
2095 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2096 Only do this if mdelta is not a 16-bit move as adjusting using a move
2097 is better. */
2099 {
2108 }
2110 /* Emit a move immediate if required and an addition/subtraction. */
2117 {
2121 }
2122 }
2126 HOST_WIDE_INT delta)
2127 {
2129 }
2133 {
2136 }
2140 {
2143 }
2145 static bool
2147 tree exp ATTRIBUTE_UNUSED)
2148 {
2149 /* Currently, always true. */
2151 }
2153 /* Implement TARGET_PASS_BY_REFERENCE. */
2155 static bool
2157 machine_mode mode,
2158 const_tree type,
2160 {
2161 HOST_WIDE_INT size;
2162 machine_mode dummymode;
2165 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2169 /* Aggregates are passed by reference based on their size. */
2171 {
2173 }
2175 /* Variable sized arguments are always returned by reference. */
2179 /* Can this be a candidate to be passed in fp/simd register(s)? */
2182 NULL))
2185 /* Arguments which are variable sized or larger than 2 registers are
2186 passed by reference unless they are a homogenous floating point
2187 aggregate. */
2189 }
2191 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2192 static bool
2194 {
2195 machine_mode dummy_mode;
2198 /* Never happens in little-endian mode. */
2202 /* Only composite types smaller than or equal to 16 bytes can
2203 be potentially returned in registers. */
2209 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2210 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2211 is always passed/returned in the least significant bits of fp/simd
2212 register(s). */
2218 }
2220 /* Implement TARGET_FUNCTION_VALUE.
2221 Define how to find the value returned by a function. */
2223 static rtx
2226 {
2227 machine_mode mode;
2230 machine_mode ag_mode;
2237 {
2241 {
2244 }
2245 }
2249 {
2251 {
2254 }
2255 else
2256 {
2258 rtx par;
2262 {
2267 }
2269 }
2270 }
2271 else
2273 }
2275 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2276 Return true if REGNO is the number of a hard register in which the values
2277 of called function may come back. */
2279 static bool
2281 {
2282 /* Maximum of 16 bytes can be returned in the general registers. Examples
2283 of 16-byte return values are: 128-bit integers and 16-byte small
2284 structures (excluding homogeneous floating-point aggregates). */
2288 /* Up to four fp/simd registers can return a function value, e.g. a
2289 homogeneous floating-point aggregate having four members. */
2294 }
2296 /* Implement TARGET_RETURN_IN_MEMORY.
2298 If the type T of the result of a function is such that
2299 void func (T arg)
2300 would require that arg be passed as a value in a register (or set of
2301 registers) according to the parameter passing rules, then the result
2302 is returned in the same registers as would be used for such an
2303 argument. */
2305 static bool
2307 {
2308 HOST_WIDE_INT size;
2309 machine_mode ag_mode;
2315 /* Simple scalar types always returned in registers. */
2319 type,
2322 NULL))
2325 /* Types larger than 2 registers returned in memory. */
2328 }
2330 static bool
2333 {
2336 type,
2338 nregs,
2339 NULL);
2340 }
2342 /* Given MODE and TYPE of a function argument, return the alignment in
2343 bits. The idea is to suppress any stronger alignment requested by
2344 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2345 This is a helper function for local use only. */
2347 static unsigned int
2349 {
2370 }
2372 /* Layout a function argument according to the AAPCS64 rules. The rule
2373 numbers refer to the rule numbers in the AAPCS64. */
2375 static void
2377 const_tree type,
2379 {
2383 HOST_WIDE_INT size;
2385 /* We need to do this once per argument. */
2391 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2392 size
2394 UNITS_PER_WORD);
2398 mode,
2399 type,
2402 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2403 The following code thus handles passing by SIMD/FP registers first. */
2407 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2408 and homogenous short-vector aggregates (HVA). */
2410 {
2415 {
2418 {
2421 }
2422 else
2423 {
2424 rtx par;
2428 {
2431 tmp = gen_rtx_EXPR_LIST
2435 }
2437 }
2439 }
2440 else
2441 {
2442 /* C.3 NSRN is set to 8. */
2445 }
2446 }
2451 /* C6 - C9. though the sign and zero extension semantics are
2452 handled elsewhere. This is the case where the argument fits
2453 entirely general registers. */
2455 {
2459 /* C.8 if the argument has an alignment of 16 then the NGRN is
2460 rounded up to the next even number. */
2463 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2464 comparison is there because for > 16 * BITS_PER_UNIT
2465 alignment nregs should be > 2 and therefore it should be
2466 passed by reference rather than value. */
2468 {
2471 }
2473 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2474 A reg is still generated for it, but the caller should be smart
2475 enough not to use it. */
2478 else
2479 {
2480 rtx par;
2485 {
2490 }
2492 }
2496 }
2498 /* C.11 */
2501 /* The argument is passed on stack; record the needed number of words for
2502 this argument and align the total size if necessary. */
2503 on_stack:
2510 }
2512 /* Implement TARGET_FUNCTION_ARG. */
2514 static rtx
2517 {
2526 }
2528 void
2530 const_tree fntype ATTRIBUTE_UNUSED,
2531 rtx libname ATTRIBUTE_UNUSED,
2532 const_tree fndecl ATTRIBUTE_UNUSED,
2534 {
2548 {
2555 }
2557 }
2559 static void
2561 machine_mode mode,
2562 const_tree type,
2564 {
2567 {
2577 }
2578 }
2580 bool
2582 {
2585 }
2587 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2588 PARM_BOUNDARY bits of alignment, but will be given anything up
2589 to STACK_BOUNDARY bits if the type requires it. This makes sure
2590 that both before and after the layout of each argument, the Next
2591 Stacked Argument Address (NSAA) will have a minimum alignment of
2592 8 bytes. */
2594 static unsigned int
2596 {
2599 }
2601 /* Implement TARGET_FUNCTION_ARG_PADDING.
2603 Small aggregate types are placed in the lowest memory address.
2605 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2607 static pad_direction
2609 {
2610 /* On little-endian targets, the least significant byte of every stack
2611 argument is passed at the lowest byte address of the stack slot. */
2615 /* Otherwise, integral, floating-point and pointer types are padded downward:
2616 the least significant byte of a stack argument is passed at the highest
2617 byte address of the stack slot. */
2624 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2626 }
2628 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2630 It specifies padding for the last (may also be the only)
2631 element of a block move between registers and memory. If
2632 assuming the block is in the memory, padding upward means that
2633 the last element is padded after its highest significant byte,
2634 while in downward padding, the last element is padded at the
2635 its least significant byte side.
2637 Small aggregates and small complex types are always padded
2638 upwards.
2640 We don't need to worry about homogeneous floating-point or
2641 short-vector aggregates; their move is not affected by the
2642 padding direction determined here. Regardless of endianness,
2643 each element of such an aggregate is put in the least
2644 significant bits of a fp/simd register.
2646 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2647 register has useful data, and return the opposite if the most
2648 significant byte does. */
2650 bool
2653 {
2655 /* Small composite types are always padded upward. */
2657 {
2662 }
2664 /* Otherwise, use the default padding. */
2666 }
2668 static scalar_int_mode
2670 {
2672 }
2674 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2676 /* We use the 12-bit shifted immediate arithmetic instructions so values
2677 must be multiple of (1 << 12), i.e. 4096. */
2678 #define ARITH_FACTOR 4096
2680 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2681 #error Cannot use simple address calculation for stack probing
2682 #endif
2684 /* The pair of scratch registers used for stack probing. */
2685 #define PROBE_STACK_FIRST_REG 9
2686 #define PROBE_STACK_SECOND_REG 10
2688 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2689 inclusive. These are offsets from the current stack pointer. */
2691 static void
2693 {
2696 /* See the same assertion on PROBE_INTERVAL above. */
2699 /* See if we have a constant small number of probes to generate. If so,
2700 that's the easy case. */
2702 {
2709 }
2711 /* The run-time loop is made up of 8 insns in the generic case while the
2712 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2714 {
2719 stack_pointer_rtx,
2723 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2724 it exceeds SIZE. If only two probes are needed, this will not
2725 generate any code. Then probe at FIRST + SIZE. */
2727 {
2731 }
2735 {
2740 }
2741 else
2743 }
2745 /* Otherwise, do the same as above, but in a loop. Note that we must be
2746 extra careful with variables wrapping around because we might be at
2747 the very top (or the very bottom) of the address space and we have
2748 to be able to handle this case properly; in particular, we use an
2749 equality test for the loop condition. */
2750 else
2751 {
2754 /* Step 1: round SIZE to the previous multiple of the interval. */
2759 /* Step 2: compute initial and final value of the loop counter. */
2761 /* TEST_ADDR = SP + FIRST. */
2765 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2768 {
2772 }
2773 else
2774 {
2777 }
2779 /* Step 3: the loop
2781 do
2782 {
2783 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2784 probe at TEST_ADDR
2785 }
2786 while (TEST_ADDR != LAST_ADDR)
2788 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2789 until it is equal to ROUNDED_SIZE. */
2794 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2795 that SIZE is equal to ROUNDED_SIZE. */
2798 {
2802 {
2807 }
2808 else
2810 }
2811 }
2813 /* Make sure nothing is scheduled before we are done. */
2815 }
2817 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2818 absolute addresses. */
2822 {
2829 /* Loop. */
2832 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2837 /* Probe at TEST_ADDR. */
2840 /* Test if TEST_ADDR == LAST_ADDR. */
2844 /* Branch. */
2850 }
2852 static bool
2854 {
2855 /* In aarch64_override_options_after_change
2856 flag_omit_leaf_frame_pointer turns off the frame pointer by
2857 default. Turn it back on now if we've not got a leaf
2858 function. */
2863 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2868 }
2870 /* Mark the registers that need to be saved by the callee and calculate
2871 the size of the callee-saved registers area and frame record (both FP
2872 and LR may be omitted). */
2873 static void
2875 {
2882 #define SLOT_NOT_REQUIRED (-2)
2883 #define SLOT_REQUIRED (-1)
2888 /* First mark all the registers that really need to be saved... */
2895 /* ... that includes the eh data registers (if needed)... */
2901 /* ... and any callee saved register that dataflow says is live. */
2911 {
2914 }
2917 {
2918 /* FP and LR are placed in the linkage record. */
2924 }
2926 /* Now assign stack slots for them. */
2929 {
2936 }
2944 {
2945 /* If there is an alignment gap between integer and fp callee-saves,
2946 allocate the last fp register to it if possible. */
2948 {
2951 }
2960 }
2966 HOST_WIDE_INT varargs_and_saved_regs_size
2993 {
2994 /* Simple, small frame with no outgoing arguments:
2995 stp reg1, reg2, [sp, -frame_size]!
2996 stp reg3, reg4, [sp, 16] */
2998 }
3003 {
3004 /* Frame with small outgoing arguments:
3005 sub sp, sp, frame_size
3006 stp reg1, reg2, [sp, outgoing_args_size]
3007 stp reg3, reg4, [sp, outgoing_args_size + 16] */
3011 }
3013 {
3014 /* Frame with large outgoing arguments but a small local area:
3015 stp reg1, reg2, [sp, -hard_fp_offset]!
3016 stp reg3, reg4, [sp, 16]
3017 sub sp, sp, outgoing_args_size */
3021 }
3024 {
3025 /* Frame with large local area and outgoing arguments (this pushes the
3026 callee-saves first, followed by the locals and outgoing area):
3027 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
3028 stp reg3, reg4, [sp, 16]
3029 sub sp, sp, frame_size - varargs_and_saved_regs_size */
3035 }
3036 else
3037 {
3038 /* Frame with large local area and outgoing arguments using frame pointer:
3039 sub sp, sp, hard_fp_offset
3040 stp x29, x30, [sp, 0]
3041 add x29, sp, 0
3042 stp reg3, reg4, [sp, 16]
3043 sub sp, sp, outgoing_args_size */
3047 }
3050 }
3052 /* Return true if the register REGNO is saved on entry to
3053 the current function. */
3055 static bool
3057 {
3059 }
3061 /* Return the next register up from REGNO up to LIMIT for the callee
3062 to save. */
3064 static unsigned
3066 {
3068 regno ++;
3070 }
3072 /* Push the register number REGNO of mode MODE to the stack with write-back
3073 adjusting the stack by ADJUSTMENT. */
3075 static void
3077 HOST_WIDE_INT adjustment)
3078 {
3089 }
3091 /* Generate and return an instruction to store the pair of registers
3092 REG and REG2 of mode MODE to location BASE with write-back adjusting
3093 the stack location BASE by ADJUSTMENT. */
3095 static rtx
3097 HOST_WIDE_INT adjustment)
3098 {
3100 {
3111 }
3112 }
3114 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3115 stack pointer by ADJUSTMENT. */
3117 static void
3119 {
3134 }
3136 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3137 adjusting it by ADJUSTMENT afterwards. */
3139 static rtx
3141 HOST_WIDE_INT adjustment)
3142 {
3144 {
3153 }
3154 }
3156 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3157 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3158 into CFI_OPS. */
3160 static void
3163 {
3170 {
3174 }
3175 else
3176 {
3181 }
3182 }
3184 /* Generate and return a store pair instruction of mode MODE to store
3185 register REG1 to MEM1 and register REG2 to MEM2. */
3187 static rtx
3189 rtx reg2)
3190 {
3192 {
3201 }
3202 }
3204 /* Generate and regurn a load pair isntruction of mode MODE to load register
3205 REG1 from MEM1 and register REG2 from MEM2. */
3207 static rtx
3209 rtx mem2)
3210 {
3212 {
3221 }
3222 }
3224 /* Return TRUE if return address signing should be enabled for the current
3225 function, otherwise return FALSE. */
3227 bool
3229 {
3230 /* This function should only be called after frame laid out. */
3233 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3234 if it's LR is pushed onto stack. */
3238 }
3240 /* Emit code to save the callee-saved registers from register number START
3241 to LIMIT to the stack at the location starting at offset START_OFFSET,
3242 skipping any write-back candidates if SKIP_WB is true. */
3244 static void
3247 {
3255 {
3257 HOST_WIDE_INT offset;
3270 offset));
3279 {
3281 rtx mem2;
3285 offset));
3287 reg2));
3289 /* The first part of a frame-related parallel insn is
3290 always assumed to be relevant to the frame
3291 calculations; subsequent parts, are only
3292 frame-related if explicitly marked. */
3295 }
3296 else
3300 }
3301 }
3303 /* Emit code to restore the callee registers of mode MODE from register
3304 number START up to and including LIMIT. Restore from the stack offset
3305 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3306 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3308 static void
3312 {
3316 HOST_WIDE_INT offset;
3321 {
3342 {
3344 rtx mem2;
3352 }
3353 else
3356 }
3357 }
3361 HOST_WIDE_INT offset)
3362 {
3364 }
3368 {
3372 }
3374 bool
3376 {
3380 }
3382 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3384 static sbitmap
3386 {
3392 /* The registers we need saved to the frame. */
3395 {
3400 /* Check that we can access the stack slot of the register with one
3401 direct load with no adjustments needed. */
3404 }
3406 /* Don't mess with the hard frame pointer. */
3412 /* If aarch64_layout_frame has chosen registers to store/restore with
3413 writeback don't interfere with them to avoid having to output explicit
3414 stack adjustment instructions. */
3424 }
3426 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3428 static sbitmap
3430 {
3438 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3447 }
3449 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3450 Nothing to do for aarch64. */
3452 static void
3454 {
3455 }
3457 /* Return the next set bit in BMP from START onwards. Return the total number
3458 of bits in BMP if no set bit is found at or after START. */
3460 static unsigned int
3462 {
3473 }
3475 /* Do the work for aarch64_emit_prologue_components and
3476 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3477 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3478 for these components or the epilogue sequence. That is, it determines
3479 whether we should emit stores or loads and what kind of CFA notes to attach
3480 to the insns. Otherwise the logic for the two sequences is very
3481 similar. */
3483 static void
3485 {
3487 ? HARD_FRAME_POINTER_REGNUM
3495 {
3496 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3497 so DFmode for the vector registers is enough. */
3509 /* No more registers to handle after REGNO.
3510 Emit a single save/restore and exit. */
3512 {
3517 else
3520 }
3523 /* The next register is not of the same class or its offset is not
3524 mergeable with the current one into a pair. */
3529 {
3534 else
3539 }
3541 /* REGNO2 can be saved/restored in a pair with REGNO. */
3553 else
3558 {
3561 }
3562 else
3563 {
3566 }
3569 }
3570 }
3572 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3574 static void
3576 {
3578 }
3580 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3582 static void
3584 {
3586 }
3588 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3590 static void
3592 {
3596 }
3598 /* AArch64 stack frames generated by this compiler look like:
3600 +-------------------------------+
3601 | |
3602 | incoming stack arguments |
3603 | |
3604 +-------------------------------+
3605 | | <-- incoming stack pointer (aligned)
3606 | callee-allocated save area |
3607 | for register varargs |
3608 | |
3609 +-------------------------------+
3610 | local variables | <-- frame_pointer_rtx
3611 | |
3612 +-------------------------------+
3613 | padding0 | \
3614 +-------------------------------+ |
3615 | callee-saved registers | | frame.saved_regs_size
3616 +-------------------------------+ |
3617 | LR' | |
3618 +-------------------------------+ |
3619 | FP' | / <- hard_frame_pointer_rtx (aligned)
3620 +-------------------------------+
3621 | dynamic allocation |
3622 +-------------------------------+
3623 | padding |
3624 +-------------------------------+
3625 | outgoing stack arguments | <-- arg_pointer
3626 | |
3627 +-------------------------------+
3628 | | <-- stack_pointer_rtx (aligned)
3630 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3631 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3632 unchanged. */
3634 /* Generate the prologue instructions for entry into a function.
3635 Establish the stack frame by decreasing the stack pointer with a
3636 properly calculated size and, if necessary, create a frame record
3637 filled with the values of LR and previous frame pointer. The
3638 current FP is also set up if it is in use. */
3640 void
3642 {
3654 /* Sign return address for functions. */
3656 {
3660 }
3666 {
3668 {
3672 }
3675 }
3683 {
3688 stack_pointer_rtx,
3692 }
3699 }
3701 /* Return TRUE if we can use a simple_return insn.
3703 This function checks whether the callee saved stack is empty, which
3704 means no restore actions are need. The pro_and_epilogue will use
3705 this to check whether shrink-wrapping opt is feasible. */
3707 bool
3709 {
3719 }
3721 /* Generate the epilogue instructions for returning from a function.
3722 This is almost exactly the reverse of the prolog sequence, except
3723 that we need to insert barriers to avoid scheduling loads that read
3724 from a deallocated stack, and we optimize the unwind records by
3725 emitting them all together if possible. */
3726 void
3728 {
3740 /* We need to add memory barrier to prevent read from deallocated stack. */
3744 /* Emit a barrier to prevent loads from a deallocated stack. */
3747 {
3750 }
3752 /* Restore the stack pointer from the frame pointer if it may not
3753 be the same as the stack pointer. */
3755 {
3757 hard_frame_pointer_rtx,
3759 /* If writeback is used when restoring callee-saves, the CFA
3760 is restored on the instruction doing the writeback. */
3762 }
3763 else
3778 {
3779 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3785 }
3790 {
3791 /* Emit delayed restores and reset the CFA to be SP. */
3796 }
3798 /* We prefer to emit the combined return/authenticate instruction RETAA,
3799 however there are three cases in which we must instead emit an explicit
3800 authentication instruction.
3802 1) Sibcalls don't return in a normal way, so if we're about to call one
3803 we must authenticate.
3805 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3806 generating code for !TARGET_ARMV8_3 we can't use it and must
3807 explicitly authenticate.
3809 3) On an eh_return path we make extra stack adjustments to update the
3810 canonical frame address to be the exception handler's CFA. We want
3811 to authenticate using the CFA of the function which calls eh_return.
3812 */
3815 {
3819 }
3821 /* Stack adjustment for exception handler. */
3823 {
3824 /* We need to unwind the stack by the offset computed by
3825 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3826 to be SP; letting the CFA move during this adjustment
3827 is just as correct as retaining the CFA from the body
3828 of the function. Therefore, do nothing special. */
3830 }
3835 }
3837 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3838 normally or return to a previous frame after unwinding.
3840 An EH return uses a single shared return sequence. The epilogue is
3841 exactly like a normal epilogue except that it has an extra input
3842 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3843 that must be applied after the frame has been destroyed. An extra label
3844 is inserted before the epilogue which initializes this register to zero,
3845 and this is the entry point for a normal return.
3847 An actual EH return updates the return address, initializes the stack
3848 adjustment and jumps directly into the epilogue (bypassing the zeroing
3849 of the adjustment). Since the return address is typically saved on the
3850 stack when a function makes a call, the saved LR must be updated outside
3851 the epilogue.
3853 This poses problems as the store is generated well before the epilogue,
3854 so the offset of LR is not known yet. Also optimizations will remove the
3855 store as it appears dead, even after the epilogue is generated (as the
3856 base or offset for loading LR is different in many cases).
3858 To avoid these problems this implementation forces the frame pointer
3859 in eh_return functions so that the location of LR is fixed and known early.
3860 It also marks the store volatile, so no optimization is permitted to
3861 remove the store. */
3862 rtx
3864 {
3868 /* Mark the store volatile, so no optimization is permitted to remove it. */
3871 }
3873 /* Output code to add DELTA to the first argument, and then jump
3874 to FUNCTION. Used for C++ multiple inheritance. */
3875 static void
3877 HOST_WIDE_INT delta,
3878 HOST_WIDE_INT vcall_offset,
3879 tree function)
3880 {
3881 /* The this pointer is always in x0. Note that this differs from
3882 Arm where the this pointer maybe bumped to r1 if r0 is required
3883 to return a pointer to an aggregate. On AArch64 a result value
3884 pointer will be in x8. */
3894 else
3895 {
3904 {
3908 else
3910 }
3914 else
3921 else
3922 {
3924 Pmode);
3926 }
3930 else
3936 }
3938 /* Generate a tail call to the target function. */
3940 {
3943 }
3955 /* Stop pretending to be a post-reload pass. */
3957 }
3959 static bool
3961 {
3966 {
3970 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3971 TLS offsets, not real symbol references. */
3974 }
3976 }
3979 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3980 a left shift of 0 or 12 bits. */
3981 bool
3983 {
3986 );
3987 }
3990 /* Return true if val is an immediate that can be loaded into a
3991 register by a MOVZ instruction. */
3992 static bool
3994 {
3996 {
4000 }
4001 else
4002 {
4003 /* Ignore sign extension. */
4005 }
4008 }
4010 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4013 {
4019 };
4022 /* Return true if val is a valid bitmask immediate. */
4024 bool
4026 {
4030 /* Check for a single sequence of one bits and return quickly if so.
4031 The special cases of all ones and all zeroes returns false. */
4038 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4042 /* Invert if the immediate doesn't start with a zero bit - this means we
4043 only need to search for sequences of one bits. */
4047 /* Find the first set bit and set tmp to val with the first sequence of one
4048 bits removed. Return success if there is a single sequence of ones. */
4055 /* Find the next set bit and compute the difference in bit position. */
4060 /* Check the bit position difference is a power of 2, and that the first
4061 sequence of one bits fits within 'bits' bits. */
4065 /* Check the sequence of one bits is repeated 64/bits times. */
4067 }
4069 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4070 Assumed precondition: VAL_IN Is not zero. */
4072 unsigned HOST_WIDE_INT
4074 {
4081 }
4083 /* Create constant where bits outside of lowest bit set to highest bit set
4084 are set to 1. */
4086 unsigned HOST_WIDE_INT
4088 {
4090 }
4092 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4094 bool
4096 {
4097 scalar_int_mode int_mode;
4110 }
4112 /* Return true if val is an immediate that can be loaded into a
4113 register in a single instruction. */
4114 bool
4116 {
4117 scalar_int_mode int_mode;
4124 }
4126 static bool
4128 {
4136 {
4140 else
4141 /* Avoid generating a 64-bit relocation in ILP32; leave
4142 to aarch64_expand_mov_immediate to handle it properly. */
4144 }
4147 }
4149 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4150 The expansion for a table switch is quite expensive due to the number
4151 of instructions, the table lookup and hard to predict indirect jump.
4152 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4153 set, otherwise use tables for > 16 cases as a tradeoff between size and
4154 performance. When optimizing for size, use the default setting. */
4156 static unsigned int
4158 {
4159 /* Use the specified limit for the number of cases before using jump
4160 tables at higher optimization levels. */
4164 else
4166 }
4168 /* Return true if register REGNO is a valid index register.
4169 STRICT_P is true if REG_OK_STRICT is in effect. */
4171 bool
4173 {
4175 {
4183 }
4185 }
4187 /* Return true if register REGNO is a valid base register for mode MODE.
4188 STRICT_P is true if REG_OK_STRICT is in effect. */
4190 bool
4192 {
4194 {
4202 }
4204 /* The fake registers will be eliminated to either the stack or
4205 hard frame pointer, both of which are usually valid base registers.
4206 Reload deals with the cases where the eliminated form isn't valid. */
4211 }
4213 /* Return true if X is a valid base register for mode MODE.
4214 STRICT_P is true if REG_OK_STRICT is in effect. */
4216 static bool
4218 {
4225 }
4227 /* Return true if address offset is a valid index. If it is, fill in INFO
4228 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4230 static bool
4233 {
4235 rtx index;
4238 /* (reg:P) */
4241 {
4245 }
4246 /* (sign_extend:DI (reg:SI)) */
4251 {
4256 }
4257 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4264 {
4269 }
4270 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4277 {
4282 }
4283 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4290 {
4298 }
4299 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4300 (const_int 0xffffffff<<shift)) */
4307 {
4313 }
4314 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4321 {
4329 }
4330 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4331 (const_int 0xffffffff<<shift)) */
4338 {
4344 }
4345 /* (mult:P (reg:P) (const_int scale)) */
4350 {
4354 }
4355 /* (ashift:P (reg:P) (const_int shift)) */
4360 {
4364 }
4365 else
4378 {
4383 }
4386 }
4388 /* Return true if MODE is one of the modes for which we
4389 support LDP/STP operations. */
4391 static bool
4393 {
4398 }
4400 /* Return true if REGNO is a virtual pointer register, or an eliminable
4401 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4402 include stack_pointer or hard_frame_pointer. */
4403 static bool
4405 {
4410 }
4412 /* Return true if X is a valid address for machine mode MODE. If it is,
4413 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4414 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4416 static bool
4420 {
4424 /* On BE, we use load/store pair for all large int mode load/stores.
4425 TI/TFmode may also use a load/store pair. */
4429 || (BYTES_BIG_ENDIAN
4433 !load_store_pair_p
4437 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4438 REG addressing. */
4444 {
4460 {
4466 }
4471 {
4478 /* TImode and TFmode values are allowed in both pairs of X
4479 registers and individual Q registers. The available
4480 address modes are:
4481 X,X: 7-bit signed scaled offset
4482 Q: 9-bit signed offset
4483 We conservatively require an offset representable in either mode.
4484 When performing the check for pairs of X registers i.e. LDP/STP
4485 pass down DImode since that is the natural size of the LDP/STP
4486 instruction memory accesses. */
4492 /* A 7bit offset check because OImode will emit a ldp/stp
4493 instruction (only big endian will get here).
4494 For ldp/stp instructions, the offset is scaled for the size of a
4495 single element of the pair. */
4499 /* Three 9/12 bit offsets checks because CImode will emit three
4500 ldr/str instructions (only big endian will get here). */
4507 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4508 instructions (only big endian will get here). */
4517 else
4520 }
4523 {
4524 /* Look for base + (scaled/extended) index register. */
4527 {
4530 }
4533 {
4536 }
4537 }
4558 {
4559 HOST_WIDE_INT offset;
4563 /* TImode and TFmode values are allowed in both pairs of X
4564 registers and individual Q registers. The available
4565 address modes are:
4566 X,X: 7-bit signed scaled offset
4567 Q: 9-bit signed offset
4568 We conservatively require an offset representable in either mode.
4569 */
4577 else
4579 }
4585 /* load literal: pc-relative constant pool entry. Only supported
4586 for SI mode or larger. */
4590 {
4598 }
4607 {
4612 {
4613 /* The symbol and offset must be aligned to the access size. */
4620 {
4624 }
4630 else
4639 }
4640 }
4645 }
4646 }
4648 /* Return true if the address X is valid for a PRFM instruction.
4649 STRICT_P is true if we should do strict checking with
4650 aarch64_classify_address. */
4652 bool
4654 {
4657 /* PRFM accepts the same addresses as DImode... */
4662 /* ... except writeback forms. */
4664 }
4666 bool
4668 {
4669 rtx offset;
4673 }
4675 /* Classify the base of symbolic expression X. */
4677 enum aarch64_symbol_type
4679 {
4680 rtx offset;
4684 }
4687 /* Return TRUE if X is a legitimate address for accessing memory in
4688 mode MODE. */
4689 static bool
4691 {
4695 }
4697 /* Return TRUE if X is a legitimate address for accessing memory in
4698 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4699 pair operation. */
4700 bool
4703 {
4707 }
4709 /* Split an out-of-range address displacement into a base and offset.
4710 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4711 to increase opportunities for sharing the base address of different sizes.
4712 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4713 static bool
4715 {
4726 }
4728 /* Return the binary representation of floating point constant VALUE in INTVAL.
4729 If the value cannot be converted, return false without setting INTVAL.
4730 The conversion is done in the given MODE. */
4731 bool
4733 {
4735 /* We make a general exception for 0. */
4737 {
4740 }
4746 /* Only support up to DF mode. */
4758 {
4762 }
4763 else
4768 }
4770 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4771 single MOV(+MOVK) followed by an FMOV. */
4772 bool
4774 {
4779 /* Determine whether it's cheaper to write float constants as
4780 mov/movk pairs over ldr/adrp pairs. */
4786 {
4788 ? SImode
4793 }
4796 }
4798 /* Return TRUE if rtx X is immediate constant 0.0 */
4799 bool
4801 {
4808 }
4810 /* Return TRUE if rtx X is immediate constant that fits in a single
4811 MOVI immediate operation. */
4812 bool
4814 {
4818 machine_mode vmode;
4819 scalar_int_mode imode;
4824 {
4828 /* We make a general exception for 0. */
4833 }
4837 else
4840 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4841 a 128 bit vector mode. */
4848 }
4851 /* Return the fixed registers used for condition codes. */
4853 static bool
4855 {
4859 }
4861 /* This function is used by the call expanders of the machine description.
4862 RESULT is the register in which the result is returned. It's NULL for
4863 "call" and "sibcall".
4864 MEM is the location of the function call.
4865 SIBCALL indicates whether this function call is normal call or sibling call.
4866 It will generate different pattern accordingly. */
4868 void
4870 {
4872 rtvec vec;
4873 machine_mode mode;
4880 /* Decide if we should generate indirect calls by loading the
4881 address of the callee into a register before performing
4882 the branch-and-link. */
4896 else
4903 }
4905 /* Emit call insn with PAT and do aarch64-specific handling. */
4907 void
4909 {
4915 }
4917 machine_mode
4919 {
4920 /* All floating point compares return CCFP if it is an equality
4921 comparison, and CCFPE otherwise. */
4923 {
4925 {
4946 }
4947 }
4949 /* Equality comparisons of short modes against zero can be performed
4950 using the TST instruction with the appropriate bitmask. */
4956 /* Similarly, comparisons of zero_extends from shorter modes can
4957 be performed using an ANDS with an immediate mask. */
4973 /* A compare with a shifted operand. Because of canonicalization,
4974 the comparison will have to be swapped when we emit the assembly
4975 code. */
4983 /* Similarly for a negated operand, but we can only do this for
4984 equalities. */
4991 /* A test for unsigned overflow. */
4998 /* For everything else, return CCmode. */
5000 }
5002 static int
5005 int
5007 {
5014 }
5016 static int
5018 {
5020 {
5024 {
5038 }
5043 {
5055 }
5060 {
5072 }
5077 {
5083 }
5088 {
5092 }
5097 {
5101 }
5106 }
5109 }
5111 bool
5113 HOST_WIDE_INT minval,
5114 HOST_WIDE_INT maxval)
5115 {
5116 HOST_WIDE_INT firstval;
5133 }
5135 bool
5137 {
5139 }
5142 /* N Z C V. */
5143 #define AARCH64_CC_V 1
5144 #define AARCH64_CC_C (1 << 1)
5145 #define AARCH64_CC_Z (1 << 2)
5146 #define AARCH64_CC_N (1 << 3)
5148 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5150 {
5167 };
5169 /* Print operand X to file F in a target specific manner according to CODE.
5170 The acceptable formatting commands given by CODE are:
5171 'c': An integer or symbol address without a preceding #
5172 sign.
5173 'e': Print the sign/zero-extend size as a character 8->b,
5174 16->h, 32->w.
5175 'p': Prints N such that 2^N == X (X must be power of 2 and
5176 const int).
5177 'P': Print the number of non-zero bits in X (a const_int).
5178 'H': Print the higher numbered register of a pair (TImode)
5179 of regs.
5180 'm': Print a condition (eq, ne, etc).
5181 'M': Same as 'm', but invert condition.
5182 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5183 'S/T/U/V': Print a FP/SIMD register name for a register list.
5184 The register printed is the FP/SIMD register name
5185 of X + 0/1/2/3 for S/T/U/V.
5186 'R': Print a scalar FP/SIMD register name + 1.
5187 'X': Print bottom 16 bits of integer constant in hex.
5188 'w/x': Print a general register name or the zero register
5189 (32-bit or 64-bit).
5190 '0': Print a normal operand, if it's a general register,
5191 then we assume DImode.
5192 'k': Print NZCV for conditional compare instructions.
5193 'A': Output address constant representing the first
5194 argument of X, specifying a relocation offset
5195 if appropriate.
5196 'L': Output constant address specified by X
5197 with a relocation offset if appropriate.
5198 'G': Prints address of X, specifying a PC relative
5199 relocation mode if appropriate. */
5201 static void
5203 {
5205 {
5208 {
5220 {
5223 }
5224 /* Fall through. */
5228 }
5232 {
5237 {
5240 }
5243 {
5256 }
5257 }
5261 {
5265 {
5268 }
5271 }
5276 {
5279 }
5286 {
5289 }
5296 {
5298 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5300 {
5304 }
5307 {
5310 }
5317 }
5326 {
5327 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5329 }
5338 {
5339 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5341 }
5347 {
5348 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5350 }
5356 {
5359 }
5367 {
5370 }
5373 {
5376 }
5379 {
5382 }
5384 /* Fall through */
5388 {
5391 }
5394 {
5401 /* Check all memory references are Pmode - even with ILP32. */
5417 {
5420 HOST_WIDE_INT_MIN,
5421 HOST_WIDE_INT_MAX));
5423 }
5425 {
5427 }
5428 else
5433 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5434 be getting CONST_DOUBLEs holding integers. */
5437 {
5440 }
5442 {
5443 #define buf_size 20
5451 #undef buf_size
5452 }
5458 }
5466 {
5493 }
5499 {
5534 }
5540 {
5546 }
5551 {
5552 HOST_WIDE_INT cond_code;
5555 {
5558 }
5563 }
5569 }
5570 }
5572 static void
5574 {
5579 {
5583 else
5592 else
5601 else
5610 else
5617 {
5644 }
5655 }
5658 }
5660 bool
5662 {
5669 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5670 referencing instruction, but they are constant offsets, not
5671 symbols. */
5677 {
5679 {
5685 }
5688 }
5691 }
5693 /* Implement REGNO_REG_CLASS. */
5695 enum reg_class
5697 {
5712 }
5714 static rtx
5716 {
5717 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5718 where mask is selected by alignment and size of the offset.
5719 We try to pick as large a range for the offset as possible to
5720 maximize the chance of a CSE. However, for aligned addresses
5721 we limit the range to 4k so that structures with different sized
5722 elements are likely to use the same base. We need to be careful
5723 not to split a CONST for some forms of address expression, otherwise
5724 it will generate sub-optimal code. */
5727 {
5733 {
5737 /* Force any scaling into a temp for CSE. */
5741 /* Let the pointer register be in op0. */
5745 /* If the pointer is virtual or frame related, then we know that
5746 virtual register instantiation or register elimination is going
5747 to apply a second constant. We want the two constants folded
5748 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5750 {
5754 }
5756 /* Otherwise, in order to encourage CSE (and thence loop strength
5757 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5761 }
5763 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5764 HOST_WIDE_INT base_offset;
5767 /* For offsets aren't a multiple of the access size, the limit is
5768 -256...255. */
5770 {
5773 /* BLKmode typically uses LDP of X-registers. */
5776 }
5777 /* Small negative offsets are supported. */
5782 /* Use 12-bit offset by access size. */
5783 else
5787 {
5791 }
5792 }
5795 }
5797 /* Return the reload icode required for a constant pool in mode. */
5798 static enum insn_code
5800 {
5802 {
5838 }
5841 }
5842 static reg_class_t
5844 reg_class_t rclass,
5845 machine_mode mode,
5847 {
5849 /* If we have to disable direct literal pool loads and stores because the
5850 function is too big, then we need a scratch register. */
5855 {
5858 }
5860 /* Without the TARGET_SIMD instructions we cannot move a Q register
5861 to a Q register directly. We need a scratch. */
5865 {
5871 }
5873 /* A TFmode or TImode memory access should be handled via an FP_REGS
5874 because AArch64 has richer addressing modes for LDR/STR instructions
5875 than LDP/STP instructions. */
5884 }
5886 static bool
5888 {
5889 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5890 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5893 {
5905 }
5906 else
5907 {
5908 /* If we decided that we didn't need a leaf frame pointer but then used
5909 LR in the function, then we'll want a frame pointer after all, so
5910 prevent this elimination to ensure a frame pointer is used. */
5912 && flag_omit_leaf_frame_pointer
5915 }
5918 }
5920 HOST_WIDE_INT
5922 {
5926 {
5933 }
5936 {
5940 }
5943 }
5945 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5946 previous frame. */
5948 rtx
5950 {
5954 }
5957 static void
5959 {
5961 {
5964 }
5965 else
5966 {
5969 }
5974 }
5976 static void
5978 {
5982 /* Don't need to copy the trailing D-words, we fill those in below. */
5994 /* XXX We should really define a "clear_cache" pattern and use
5995 gen_clear_cache(). */
6000 ptr_mode);
6001 }
6003 static unsigned char
6005 {
6007 {
6014 return
6026 }
6028 }
6030 static reg_class_t
6032 {
6037 {
6043 }
6045 /* Register eliminiation can result in a request for
6046 SP+constant->FP_REGS. We cannot support such operations which
6047 use SP as source and an FP_REG as destination, so reject out
6048 right now. */
6050 {
6053 /* Look through a possible SUBREG introduced by ILP32. */
6059 POINTER_REGS));
6061 }
6064 }
6066 void
6068 {
6070 }
6072 static void
6074 {
6077 else
6078 {
6080 /* While priority is known to be in range [0, 65535], so 18 bytes
6081 would be enough, the compiler might not know that. To avoid
6082 -Wformat-truncation false positive, use a larger size. */
6089 }
6090 }
6092 static void
6094 {
6097 else
6098 {
6100 /* While priority is known to be in range [0, 65535], so 18 bytes
6101 would be enough, the compiler might not know that. To avoid
6102 -Wformat-truncation false positive, use a larger size. */
6109 }
6110 }
6114 {
6120 {
6121 {
6124 },
6125 {
6128 },
6129 {
6132 },
6133 /* We assume that DImode is only generated when not optimizing and
6134 that we don't really need 64-bit address offsets. That would
6135 imply an object file with 8GB of code in a single function! */
6136 {
6139 }
6140 };
6149 /* Need to implement table size reduction, by chaning the code below. */
6159 }
6162 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6163 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6164 operator. */
6166 int
6168 {
6170 {
6173 {
6177 }
6178 }
6180 }
6182 /* Constant pools are per function only when PC relative
6183 literal loads are true or we are in the large memory
6184 model. */
6188 {
6191 }
6193 static bool
6195 {
6196 /* Fixme:: In an ideal world this would work similar
6197 to the logic in aarch64_select_rtx_section but this
6198 breaks bootstrap in gcc go. For now we workaround
6199 this by returning false here. */
6201 }
6203 /* Select appropriate section for constants depending
6204 on where we place literal pools. */
6208 rtx x,
6210 {
6215 }
6217 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6218 void
6220 HOST_WIDE_INT offset)
6221 {
6222 /* When using per-function literal pools, we must ensure that any code
6223 section is aligned to the minimal instruction length, lest we get
6224 errors from the assembler re "unaligned instructions". */
6227 }
6229 /* Costs. */
6231 /* Helper function for rtx cost calculation. Strip a shift expression
6232 from X. Returns the inner operand if successful, or the original
6233 expression on failure. */
6234 static rtx
6236 {
6239 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6240 we can convert both to ROR during final output. */
6255 }
6257 /* Helper function for rtx cost calculation. Strip an extend
6258 expression from X. Returns the inner operand if successful, or the
6259 original expression on failure. We deal with a number of possible
6260 canonicalization variations here. If STRIP_SHIFT is true, then
6261 we can strip off a shift also. */
6262 static rtx
6264 {
6265 scalar_int_mode mode;
6271 /* Zero and sign extraction of a widened value. */
6279 /* It can also be represented (for zero-extend) as an AND with an
6280 immediate. */
6289 /* Now handle extended register, as this may also have an optional
6290 left shift by 1..4. */
6305 }
6307 /* Return true iff CODE is a shift supported in combination
6308 with arithmetic instructions. */
6310 static bool
6312 {
6314 }
6317 /* Return true iff X is a cheap shift without a sign extend. */
6319 static bool
6321 {
6347 }
6349 /* Helper function for rtx cost calculation. Calculate the cost of
6350 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6351 Return the calculated cost of the expression, recursing manually in to
6352 operands where needed. */
6354 static int
6356 {
6372 /* Integer multiply/fma. */
6374 {
6375 /* The multiply will be canonicalized as a shift, cost it as such. */
6379 {
6383 {
6385 {
6386 /* If the shift is considered cheap,
6387 then don't add any cost. */
6389 ;
6391 /* ARITH + shift-by-register. */
6394 /* ARITH + extended register. We don't have a cost field
6395 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6397 else
6398 /* ARITH + shift-by-immediate. */
6400 }
6401 else
6402 /* LSL (immediate). */
6405 }
6406 /* Strip extends as we will have costed them in the case above. */
6413 }
6415 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6416 compound and let the below cases handle it. After all, MNEG is a
6417 special-case alias of MSUB. */
6419 {
6422 }
6424 /* Integer multiplies or FMAs have zero/sign extending variants. */
6429 {
6434 {
6436 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6438 else
6439 /* MUL/SMULL/UMULL. */
6441 }
6444 }
6446 /* This is either an integer multiply or a MADD. In both cases
6447 we want to recurse and cost the operands. */
6452 {
6454 /* MADD/MSUB. */
6456 else
6457 /* MUL. */
6459 }
6462 }
6463 else
6464 {
6466 {
6467 /* Floating-point FMA/FMUL can also support negations of the
6468 operands, unless the rounding mode is upward or downward in
6469 which case FNMUL is different than FMUL with operand negation. */
6473 {
6478 }
6481 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6483 else
6484 /* FMUL/FNMUL. */
6486 }
6491 }
6492 }
6494 static int
6496 machine_mode mode,
6497 addr_space_t as ATTRIBUTE_UNUSED,
6499 {
6507 {
6509 {
6510 /* This is a CONST or SYMBOL ref which will be split
6511 in a different way depending on the code model in use.
6512 Cost it through the generic infrastructure. */
6514 /* Divide through by the cost of one instruction to
6515 bring it to the same units as the address costs. */
6517 /* The cost is then the cost of preparing the address,
6518 followed by an immediate (possibly 0) offset. */
6520 }
6521 else
6522 {
6523 /* This is most likely a jump table from a case
6524 statement. */
6526 }
6527 }
6530 {
6542 else
6561 }
6565 {
6566 /* For the sake of calculating the cost of the shifted register
6567 component, we can treat same sized modes in the same way. */
6569 {
6582 /* We can't tell, or this is a 128-bit vector. */
6586 }
6587 }
6590 }
6592 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6593 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6594 to be taken. */
6596 int
6598 {
6599 /* When optimizing for speed, use the cost of unpredictable branches. */
6605 else
6607 }
6609 /* Return true if the RTX X in mode MODE is a zero or sign extract
6610 usable in an ADD or SUB (extended register) instruction. */
6611 static bool
6613 {
6614 /* Catch add with a sign extract.
6615 This is add_<optab><mode>_multp2. */
6618 {
6629 op1))
6630 {
6632 }
6633 }
6634 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6635 No shift. */
6641 }
6643 static bool
6645 {
6647 {
6659 }
6660 }
6662 /* Return true iff X is an rtx that will match an extr instruction
6663 i.e. as described in the *extr<mode>5_insn family of patterns.
6664 OP0 and OP1 will be set to the operands of the shifts involved
6665 on success and will be NULL_RTX otherwise. */
6667 static bool
6669 {
6671 scalar_int_mode mode;
6686 {
6687 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6699 {
6703 }
6704 }
6707 }
6709 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6710 storing it in *COST. Result is true if the total cost of the operation
6711 has now been calculated. */
6712 static bool
6714 {
6715 rtx inner;
6716 rtx comparator;
6720 {
6724 }
6725 else
6726 {
6730 }
6733 {
6734 /* Conditional branch. */
6737 else
6738 {
6740 {
6742 {
6743 /* TBZ/TBNZ/CBZ/CBNZ. */
6745 /* TBZ/TBNZ. */
6748 else
6749 /* CBZ/CBNZ. */
6753 }
6754 }
6756 {
6757 /* TBZ/TBNZ. */
6760 }
6761 }
6762 }
6764 {
6765 /* CCMP. */
6767 {
6768 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6772 {
6779 else
6781 }
6783 }
6785 /* It's a conditional operation based on the status flags,
6786 so it must be some flavor of CSEL. */
6788 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6794 {
6795 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6798 }
6803 }
6805 /* We don't know what this is, cost all operands. */
6807 }
6809 /* Check whether X is a bitfield operation of the form shift + extend that
6810 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6811 operand to which the bitfield operation is applied. Otherwise return
6812 NULL_RTX. */
6814 static rtx
6816 {
6830 {
6848 }
6851 }
6853 /* Return true if the mask and a shift amount from an RTX of the form
6854 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6855 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6857 bool
6859 rtx shft_amnt)
6860 {
6865 }
6867 /* Calculate the cost of calculating X, storing it in *COST. Result
6868 is true if the total cost of the operation has now been calculated. */
6869 static bool
6872 {
6877 scalar_int_mode int_mode;
6879 /* By default, assume that everything has equivalent cost to the
6880 cheapest instruction. Any additional costs are applied as a delta
6881 above this default. */
6885 {
6887 /* The cost depends entirely on the operands to SET. */
6893 {
6896 {
6910 }
6919 /* Fall through. */
6921 /* The cost is one per vector-register copied. */
6923 {
6927 }
6928 /* const0_rtx is in general free, but we will use an
6929 instruction to set a register to 0. */
6931 {
6932 /* The cost is 1 per register copied. */
6936 }
6937 else
6938 /* Cost is just the cost of the RHS of the set. */
6944 /* Bit-field insertion. Strip any redundant widening of
6945 the RHS to meet the width of the target. */
6956 {
6957 /* MOV immediate is assumed to always be cheap. */
6959 }
6960 else
6961 {
6962 /* BFM. */
6966 }
6971 /* We can't make sense of this, assume default cost. */
6974 }
6978 /* If an instruction can incorporate a constant within the
6979 instruction, the instruction's expression avoids calling
6980 rtx_cost() on the constant. If rtx_cost() is called on a
6981 constant, then it is usually because the constant must be
6982 moved into a register by one or more instructions.
6984 The exception is constant 0, which can be expressed
6985 as XZR/WZR and is therefore free. The exception to this is
6986 if we have (set (reg) (const0_rtx)) in which case we must cost
6987 the move. However, we can catch that when we cost the SET, so
6988 we don't need to consider that here. */
6991 else
6992 {
6993 /* To an approximation, building any other constant is
6994 proportionally expensive to the number of instructions
6995 required to build that constant. This is true whether we
6996 are compiling for SPEED or otherwise. */
7001 }
7006 /* First determine number of instructions to do the move
7007 as an integer constant. */
7011 {
7017 ? SImode
7023 }
7026 {
7027 /* mov[df,sf]_aarch64. */
7029 /* FMOV (scalar immediate). */
7032 {
7033 /* This will be a load from memory. */
7036 else
7038 }
7039 else
7040 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7041 or MOV v0.s[0], wzr - neither of which are modeled by the
7042 cost tables. Just use the default cost. */
7043 {
7044 }
7045 }
7051 {
7052 /* For loads we want the base cost of a load, plus an
7053 approximation for the additional cost of the addressing
7054 mode. */
7068 }
7076 {
7078 {
7079 /* FNEG. */
7081 }
7083 }
7086 {
7089 {
7090 /* CSETM. */
7093 }
7095 /* Cost this as SUB wzr, X. */
7099 }
7102 {
7103 /* Support (neg(fma...)) as a single instruction only if
7104 sign of zeros is unimportant. This matches the decision
7105 making in aarch64.md. */
7107 {
7108 /* FNMADD. */
7111 }
7113 {
7114 /* FNMUL. */
7117 }
7119 /* FNEG. */
7122 }
7129 {
7132 else
7134 }
7144 {
7148 }
7151 {
7152 /* TODO: A write to the CC flags possibly costs extra, this
7153 needs encoding in the cost tables. */
7156 /* ANDS. */
7158 {
7161 }
7164 {
7165 /* ADDS (and CMN alias). */
7168 }
7171 {
7172 /* SUBS. */
7175 }
7180 {
7181 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7182 Handle it here directly rather than going to cost_logic
7183 since we know the immediate generated for the TST is valid
7184 so we can avoid creating an intermediate rtx for it only
7185 for costing purposes. */
7192 }
7195 {
7196 /* CMN. */
7203 }
7205 /* CMP.
7207 Compare can freely swap the order of operands, and
7208 canonicalization puts the more complex operation first.
7209 But the integer MINUS logic expects the shift/extend
7210 operation in op1. */
7213 {
7216 }
7218 }
7221 {
7222 /* FCMP. */
7227 {
7229 /* FCMP supports constant 0.0 for no extra cost. */
7231 }
7233 }
7236 {
7237 /* Vector compare. */
7242 {
7243 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7244 cost. */
7246 }
7248 }
7252 {
7256 cost_minus:
7259 /* Detect valid immediates. */
7265 {
7267 /* SUB(S) (immediate). */
7270 }
7272 /* Look for SUB (extended register). */
7275 {
7283 }
7287 /* Cost this as an FMA-alike operation. */
7291 {
7294 speed);
7296 }
7301 {
7303 {
7304 /* Vector SUB. */
7306 }
7308 {
7309 /* SUB(S). */
7311 }
7313 {
7314 /* FSUB. */
7316 }
7317 }
7319 }
7322 {
7323 rtx new_op0;
7328 cost_plus:
7331 {
7332 /* CSINC. */
7336 }
7341 {
7345 /* ADD (immediate). */
7348 }
7352 /* Look for ADD (extended register). */
7355 {
7363 }
7365 /* Strip any extend, leave shifts behind as we will
7366 cost them through mult_cost. */
7371 {
7373 speed);
7375 }
7380 {
7382 {
7383 /* Vector ADD. */
7385 }
7387 {
7388 /* ADD. */
7390 }
7392 {
7393 /* FADD. */
7395 }
7396 }
7398 }
7404 {
7407 else
7409 }
7414 {
7418 {
7421 else
7423 }
7425 }
7428 {
7435 }
7436 /* Fall through. */
7439 cost_logic:
7444 {
7448 }
7456 {
7457 /* This is a UBFM/SBFM. */
7462 }
7465 {
7467 {
7468 /* We have a mask + shift version of a UBFIZ
7469 i.e. the *andim_ashift<mode>_bfiz pattern. */
7473 {
7480 }
7482 {
7483 /* We possibly get the immediate for free, this is not
7484 modelled. */
7491 }
7492 }
7493 else
7494 {
7497 /* Handle ORN, EON, or BIC. */
7503 /* If we had a shift on op0 then this is a logical-shift-
7504 by-register/immediate operation. Otherwise, this is just
7505 a logical operation. */
7507 {
7509 {
7510 /* Shift by immediate. */
7513 else
7515 }
7516 else
7518 }
7520 /* In both cases we want to cost both operands. */
7527 }
7528 }
7536 {
7537 /* Vector NOT. */
7540 }
7542 /* MVN-shifted-reg. */
7544 {
7551 }
7552 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7553 Handle the second form here taking care that 'a' in the above can
7554 be a shift. */
7556 {
7565 {
7568 else
7570 }
7573 }
7574 /* MVN. */
7583 /* If a value is written in SI mode, then zero extended to DI
7584 mode, the operation will in general be free as a write to
7585 a 'w' register implicitly zeroes the upper bits of an 'x'
7586 register. However, if this is
7588 (set (reg) (zero_extend (reg)))
7590 we must cost the explicit register move. */
7594 {
7597 /* If OP_COST is non-zero, then the cost of the zero extend
7598 is effectively the cost of the inner operation. Otherwise
7599 we have a MOV instruction and we take the cost from the MOV
7600 itself. This is true independently of whether we are
7601 optimizing for space or time. */
7606 }
7608 {
7609 /* All loads can zero extend to any size for free. */
7612 }
7616 {
7621 }
7624 {
7626 {
7627 /* UMOV. */
7629 }
7630 else
7631 {
7632 /* We generate an AND instead of UXTB/UXTH. */
7634 }
7635 }
7640 {
7641 /* LDRSH. */
7643 {
7650 }
7652 }
7656 {
7661 }
7664 {
7667 else
7669 }
7677 {
7679 {
7681 {
7682 /* Vector shift (immediate). */
7684 }
7685 else
7686 {
7687 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7688 aliases. */
7690 }
7691 }
7693 /* We can incorporate zero/sign extend for free. */
7700 }
7701 else
7702 {
7704 {
7706 /* Vector shift (register). */
7708 }
7709 else
7710 {
7712 /* LSLV. */
7718 {
7720 /* We already demanded XEXP (op1, 0) to be REG_P, so
7721 don't recurse into it. */
7723 }
7724 }
7726 }
7736 {
7737 /* ASR (immediate) and friends. */
7739 {
7742 else
7744 }
7748 }
7749 else
7750 {
7752 {
7754 /* Vector shift (register). */
7756 }
7757 else
7758 {
7760 /* ASR (register) and friends. */
7766 {
7768 /* We already demanded XEXP (op1, 0) to be REG_P, so
7769 don't recurse into it. */
7771 }
7772 }
7774 }
7780 {
7781 /* LDR. */
7784 }
7787 {
7788 /* ADRP, followed by ADD. */
7792 }
7795 {
7796 /* ADR. */
7799 }
7802 {
7803 /* One extra load instruction, after accessing the GOT. */
7807 }
7812 /* ADRP/ADD (immediate). */
7819 /* UBFX/SBFX. */
7821 {
7824 else
7826 }
7828 /* We can trust that the immediates used will be correct (there
7829 are no by-register forms), so we need only cost op0. */
7835 /* aarch64_rtx_mult_cost always handles recursion to its
7836 operands. */
7840 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7841 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7842 an unconditional negate. This case should only ever be reached through
7843 the set_smod_pow2_cheap check in expmed.c. */
7847 {
7848 /* We expand to 4 instructions. Reset the baseline. */
7856 }
7858 /* Fall-through. */
7861 {
7862 /* Slighly prefer UMOD over SMOD. */
7869 }
7876 {
7880 /* There is no integer SQRT, so only DIV and UDIV can get
7881 here. */
7883 /* Slighly prefer UDIV over SDIV. */
7885 else
7887 }
7913 {
7916 else
7918 }
7920 /* FMSUB, FNMADD, and FNMSUB are free. */
7927 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7928 and the by-element operand as operand 0. */
7932 /* Catch vector-by-element operations. The by-element operand can
7933 either be (vec_duplicate (vec_select (x))) or just
7934 (vec_select (x)), depending on whether we are multiplying by
7935 a vector or a scalar.
7937 Canonicalization is not very good in these cases, FMA4 will put the
7938 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7949 /* If the remaining parameters are not registers,
7950 get the cost to put them into registers. */
7964 {
7966 {
7967 /*Vector truncate. */
7969 }
7970 else
7972 }
7977 {
7979 {
7980 /*Vector conversion. */
7982 }
7983 else
7985 }
7991 /* Strip the rounding part. They will all be implemented
7992 by the fcvt* family of instructions anyway. */
7994 {
8003 }
8006 {
8009 else
8011 }
8013 /* We can combine fmul by a power of 2 followed by a fcvt into a single
8014 fixed-point fcvt. */
8019 {
8023 }
8030 {
8031 /* ABS (vector). */
8034 }
8036 {
8039 /* FABD, which is analogous to FADD. */
8041 {
8048 }
8049 /* Simple FABS is analogous to FNEG. */
8052 }
8053 else
8054 {
8055 /* Integer ABS will either be split to
8056 two arithmetic instructions, or will be an ABS
8057 (scalar), which we don't model. */
8061 }
8067 {
8070 else
8071 {
8072 /* FMAXNM/FMINNM/FMAX/FMIN.
8073 TODO: This may not be accurate for all implementations, but
8074 we do not model this in the cost tables. */
8076 }
8077 }
8081 /* The floating point round to integer frint* instructions. */
8083 {
8088 }
8091 {
8096 }
8101 /* Decompose <su>muldi3_highpart. */
8103 mode == DImode
8104 /* (lshiftrt:TI */
8107 /* (mult:TI */
8109 /* (ANY_EXTEND:TI (reg:DI))
8110 (ANY_EXTEND:TI (reg:DI))) */
8117 /* (const_int 64) */
8120 {
8121 /* UMULH/SMULH. */
8129 }
8131 /* Fall through. */
8134 }
8142 }
8144 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8145 calculated for X. This cost is stored in *COST. Returns true
8146 if the total cost of X was calculated. */
8147 static bool
8150 {
8155 {
8160 }
8163 }
8165 static int
8168 {
8174 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8181 /* Moving between GPR and stack cost is the same as GP2GP. */
8186 /* To/From the stack register, we move via the gprs. */
8192 {
8193 /* 128-bit operations on general registers require 2 instructions. */
8201 /* When AdvSIMD instructions are disabled it is not possible to move
8202 a 128-bit value directly between Q registers. This is handled in
8203 secondary reload. A general register is used as a scratch to move
8204 the upper DI value and the lower DI value is moved directly,
8205 hence the cost is the sum of three moves. */
8210 }
8220 }
8222 static int
8224 reg_class_t rclass ATTRIBUTE_UNUSED,
8226 {
8228 }
8230 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8231 to optimize 1.0/sqrt. */
8233 static bool
8235 {
8237 && flag_unsafe_math_optimizations
8241 }
8243 /* Function to decide when to use the approximate reciprocal square root
8244 builtin. */
8246 static tree
8248 {
8254 }
8258 /* Select reciprocal square root initial estimate insn depending on machine
8259 mode. */
8261 static rsqrte_type
8263 {
8265 {
8272 }
8273 }
8277 /* Select reciprocal square root series step insn depending on machine mode. */
8279 static rsqrts_type
8281 {
8283 {
8290 }
8291 }
8293 /* Emit instruction sequence to compute either the approximate square root
8294 or its approximate reciprocal, depending on the flag RECP, and return
8295 whether the sequence was emitted or not. */
8297 bool
8299 {
8303 {
8306 }
8309 {
8316 || flag_trapping_math
8317 || !flag_unsafe_math_optimizations
8320 }
8321 else
8322 /* Caller assumes we cannot fail. */
8328 /* When calculating the approximate square root, compare the
8329 argument with 0.0 and create a mask. */
8335 /* Estimate the approximate reciprocal square root. */
8339 /* Iterate over the series twice for SF and thrice for DF. */
8342 /* Optionally iterate over the series once less for faster performance
8343 while sacrificing the accuracy. */
8346 iterations--;
8348 /* Iterate over the series to calculate the approximate reciprocal square
8349 root. */
8352 {
8360 }
8363 {
8364 /* Qualify the approximate reciprocal square root when the argument is
8365 0.0 by squashing the intermediary result to 0.0. */
8371 /* Calculate the approximate square root. */
8373 }
8375 /* Finalize the approximation. */
8379 }
8383 /* Select reciprocal initial estimate insn depending on machine mode. */
8385 static recpe_type
8387 {
8389 {
8396 }
8397 }
8401 /* Select reciprocal series step insn depending on machine mode. */
8403 static recps_type
8405 {
8407 {
8414 }
8415 }
8417 /* Emit the instruction sequence to compute the approximation for the division
8418 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8420 bool
8422 {
8433 || flag_trapping_math
8434 || !flag_unsafe_math_optimizations
8439 /* Estimate the approximate reciprocal. */
8443 /* Iterate over the series twice for SF and thrice for DF. */
8446 /* Optionally iterate over the series once less for faster performance,
8447 while sacrificing the accuracy. */
8449 iterations--;
8451 /* Iterate over the series to calculate the approximate reciprocal. */
8454 {
8459 }
8462 {
8463 /* As the approximate reciprocal of DEN is already calculated, only
8464 calculate the approximate division when NUM is not 1.0. */
8467 }
8469 /* Finalize the approximation. */
8472 }
8474 /* Return the number of instructions that can be issued per cycle. */
8475 static int
8477 {
8479 }
8481 static int
8483 {
8487 }
8490 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8491 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8492 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8494 static int
8497 {
8499 }
8502 /* Vectorizer cost model target hooks. */
8504 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8505 static int
8507 tree vectype,
8509 {
8518 {
8567 }
8568 }
8570 /* Implement targetm.vectorize.add_stmt_cost. */
8571 static unsigned
8575 {
8580 {
8585 /* Statements in an inner loop relative to the loop being
8586 vectorized are weighted more heavily. The value here is
8587 arbitrary and could potentially be improved with analysis. */
8593 }
8596 }
8600 /* Parse the TO_PARSE string and put the architecture struct that it
8601 selects into RES and the architectural features into ISA_FLAGS.
8602 Return an aarch64_parse_opt_result describing the parse result.
8603 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8605 static enum aarch64_parse_opt_result
8608 {
8620 else
8627 /* Loop through the list of supported ARCHes to find a match. */
8629 {
8631 {
8635 {
8636 /* TO_PARSE string contains at least one extension. */
8637 enum aarch64_parse_opt_result ext_res
8642 }
8643 /* Extension parsing was successful. Confirm the result
8644 arch and ISA flags. */
8648 }
8649 }
8651 /* ARCH name not found in list. */
8653 }
8655 /* Parse the TO_PARSE string and put the result tuning in RES and the
8656 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8657 describing the parse result. If there is an error parsing, RES and
8658 ISA_FLAGS are left unchanged. */
8660 static enum aarch64_parse_opt_result
8663 {
8675 else
8682 /* Loop through the list of supported CPUs to find a match. */
8684 {
8686 {
8691 {
8692 /* TO_PARSE string contains at least one extension. */
8693 enum aarch64_parse_opt_result ext_res
8698 }
8699 /* Extension parsing was successfull. Confirm the result
8700 cpu and ISA flags. */
8704 }
8705 }
8707 /* CPU name not found in list. */
8709 }
8711 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8712 Return an aarch64_parse_opt_result describing the parse result.
8713 If the parsing fails the RES does not change. */
8715 static enum aarch64_parse_opt_result
8717 {
8723 /* Loop through the list of supported CPUs to find a match. */
8725 {
8727 {
8730 }
8731 }
8733 /* CPU name not found in list. */
8735 }
8737 /* Parse TOKEN, which has length LENGTH to see if it is an option
8738 described in FLAG. If it is, return the index bit for that fusion type.
8739 If not, error (printing OPTION_NAME) and return zero. */
8741 static unsigned int
8746 {
8748 {
8752 }
8756 }
8758 /* Parse OPTION which is a comma-separated list of flags to enable.
8759 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8760 default state we inherit from the CPU tuning structures. OPTION_NAME
8761 gives the top-level option we are parsing in the -moverride string,
8762 for use in error messages. */
8764 static unsigned int
8769 {
8776 {
8779 token_length,
8780 flags,
8781 option_name);
8782 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8783 in the token stream, reset the supported operations. So:
8785 adrp+add.cmp+branch.none.adrp+add
8787 would have the result of turning on only adrp+add fusion. */
8793 }
8795 /* We ended with a comma, print something. */
8797 {
8800 }
8802 /* We still have one more token to parse. */
8805 token_length,
8806 flags,
8807 option_name);
8813 }
8815 /* Support for overriding instruction fusion. */
8817 static void
8820 {
8822 aarch64_fusible_pairs,
8825 }
8827 /* Support for overriding other tuning flags. */
8829 static void
8832 {
8833 tune->extra_tuning_flags
8835 aarch64_tuning_flags,
8838 }
8840 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8841 we understand. If it is, extract the option string and handoff to
8842 the appropriate function. */
8844 void
8848 {
8854 {
8857 }
8859 /* Get the length of the option name. */
8861 /* Skip the '=' to get to the option string. */
8862 option_part++;
8865 {
8867 {
8870 }
8871 }
8875 }
8877 /* A checking mechanism for the implementation of the tls size. */
8879 static void
8881 {
8886 {
8888 /* Both the default and maximum TLS size allowed under tiny is 1M which
8889 needs two instructions to address, so we clamp the size to 24. */
8894 /* The maximum TLS size allowed under small is 4G. */
8899 /* The maximum TLS size allowed under large is 16E.
8900 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8906 }
8909 }
8911 /* Parse STRING looking for options in the format:
8912 string :: option:string
8913 option :: name=substring
8914 name :: {a-z}
8915 substring :: defined by option. */
8917 static void
8920 {
8931 {
8933 /* Make this substring look like a string. */
8937 }
8939 /* One last option to parse. */
8942 }
8945 static void
8947 {
8948 /* The logic here is that if we are disabling all frame pointer generation
8949 then we do not need to disable leaf frame pointer generation as a
8950 separate operation. But if we are *only* disabling leaf frame pointer
8951 generation then we set flag_omit_frame_pointer to true, but in
8952 aarch64_frame_pointer_required we return false only for leaf functions.
8954 PR 70044: We have to be careful about being called multiple times for the
8955 same function. Once we have decided to set flag_omit_frame_pointer just
8956 so that we can omit leaf frame pointers, we must then not interpret a
8957 second call as meaning that all frame pointer generation should be
8958 omitted. We do this by setting flag_omit_frame_pointer to a special,
8959 non-zero value. */
8968 /* If not optimizing for size, set the default
8969 alignment to what the target wants. */
8971 {
8978 }
8980 /* We default to no pc-relative literal loads. */
8984 /* If -mpc-relative-literal-loads is set on the command line, this
8985 implies that the user asked for PC relative literal loads. */
8989 /* This is PR70113. When building the Linux kernel with
8990 CONFIG_ARM64_ERRATUM_843419, support for relocations
8991 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8992 removed from the kernel to avoid loading objects with possibly
8993 offending sequences. Without -mpc-relative-literal-loads we would
8994 generate such relocations, preventing the kernel build from
8995 succeeding. */
9000 /* In the tiny memory model it makes no sense to disallow PC relative
9001 literal pool loads. */
9006 /* When enabling the lower precision Newton series for the square root, also
9007 enable it for the reciprocal square root, since the latter is an
9008 intermediary step for the former. */
9011 }
9013 /* 'Unpack' up the internal tuning structs and update the options
9014 in OPTS. The caller must have set up selected_tune and selected_arch
9015 as all the other target-specific codegen decisions are
9016 derived from them. */
9018 void
9020 {
9023 /* Make a copy of the tuning parameters attached to the core, which
9024 we may later overwrite. */
9032 /* This target defaults to strict volatile bitfields. */
9041 {
9053 }
9055 /* We don't mind passing in global_options_set here as we don't use
9056 the *options_set structs anyway. */
9058 queue_depth,
9062 /* Set up parameters to be used in prefetching algorithm. Do not
9063 override the defaults unless we are tuning for a core we have
9064 researched values for. */
9086 /* Enable sw prefetching at specified optimization level for
9087 CPUS that have prefetch. Lower optimization level threshold by 1
9088 when profiling is enabled. */
9096 }
9098 /* Print a hint with a suggestion for a core or architecture name that
9099 most closely resembles what the user passed in STR. ARCH is true if
9100 the user is asking for an architecture name. ARCH is false if the user
9101 is asking for a core name. */
9103 static void
9105 {
9116 }
9118 /* Print a hint with a suggestion for a core name that most closely resembles
9119 what the user passed in STR. */
9123 {
9125 }
9127 /* Print a hint with a suggestion for an architecture name that most closely
9128 resembles what the user passed in STR. */
9132 {
9134 }
9136 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9137 specified in STR and throw errors if appropriate. Put the results if
9138 they are valid in RES and ISA_FLAGS. Return whether the option is
9139 valid. */
9141 static bool
9144 {
9145 enum aarch64_parse_opt_result parse_res
9152 {
9165 }
9168 }
9170 /* Validate a command-line -march option. Parse the arch and extensions
9171 (if any) specified in STR and throw errors if appropriate. Put the
9172 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9173 option is valid. */
9175 static bool
9178 {
9179 enum aarch64_parse_opt_result parse_res
9186 {
9199 }
9202 }
9204 /* Validate a command-line -mtune option. Parse the cpu
9205 specified in STR and throw errors if appropriate. Put the
9206 result, if it is valid, in RES. Return whether the option is
9207 valid. */
9209 static bool
9211 {
9212 enum aarch64_parse_opt_result parse_res
9219 {
9229 }
9231 }
9233 /* Return the CPU corresponding to the enum CPU.
9234 If it doesn't specify a cpu, return the default. */
9238 {
9242 /* The & 0x3f is to extract the bottom 6 bits that encode the
9243 default cpu as selected by the --with-cpu GCC configure option
9244 in config.gcc.
9245 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9246 flags mechanism should be reworked to make it more sane. */
9248 }
9250 /* Return the architecture corresponding to the enum ARCH.
9251 If it doesn't specify a valid architecture, return the default. */
9255 {
9262 }
9264 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9265 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9266 tuning structs. In particular it must set selected_tune and
9267 aarch64_isa_flags that define the available ISA features and tuning
9268 decisions. It must also set selected_arch as this will be used to
9269 output the .arch asm tags for each function. */
9271 static void
9273 {
9286 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9287 If either of -march or -mtune is given, they override their
9288 respective component of -mcpu. */
9300 /* If the user did not specify a processor, choose the default
9301 one for them. This will be the CPU set during configuration using
9302 --with-cpu, otherwise it is "generic". */
9304 {
9306 {
9310 }
9311 else
9312 {
9313 /* Get default configure-time CPU. */
9316 }
9320 }
9321 /* If both -mcpu and -march are specified check that they are architecturally
9322 compatible, warn if they're not and prefer the -march ISA flags. */
9324 {
9326 {
9330 }
9335 }
9336 else
9337 {
9338 /* -mcpu but no -march. */
9345 }
9347 /* Set the arch as well as we will need it when outputing
9348 the .arch directive in assembly. */
9350 {
9353 }
9358 #ifndef HAVE_AS_MABI_OPTION
9359 /* The compiler may have been configured with 2.23.* binutils, which does
9360 not have support for ILP32. */
9363 #endif
9368 /* Make sure we properly set up the explicit options. */
9379 /* Save these options as the default ones in case we push and pop them later
9380 while processing functions with potential target attributes. */
9381 target_option_default_node = target_option_current_node
9383 }
9385 /* Implement targetm.override_options_after_change. */
9387 static void
9389 {
9391 }
9395 {
9399 }
9401 void
9403 {
9405 }
9407 /* A checking mechanism for the implementation of the various code models. */
9408 static void
9410 {
9412 {
9414 {
9419 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9421 ? AARCH64_CMODEL_SMALL_PIC
9423 #else
9425 #endif
9433 }
9434 }
9435 else
9437 }
9439 /* Implement TARGET_OPTION_SAVE. */
9441 static void
9443 {
9445 }
9447 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9448 using the information saved in PTR. */
9450 static void
9452 {
9460 }
9462 /* Implement TARGET_OPTION_PRINT. */
9464 static void
9466 {
9477 }
9481 void
9483 {
9485 }
9487 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9488 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9489 make sure optab availability predicates are recomputed when necessary. */
9491 void
9493 {
9498 else
9500 }
9502 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9503 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9504 of the function, if such exists. This function may be called multiple
9505 times on a single function so use aarch64_previous_fndecl to avoid
9506 setting up identical state. */
9508 static void
9510 {
9514 tree old_tree = (aarch64_previous_fndecl
9520 /* If current function has no attributes but the previous one did,
9521 use the default node. */
9525 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9526 the default have been handled by aarch64_save_restore_target_globals from
9527 aarch64_pragma_target_parse. */
9533 /* First set the target options. */
9537 }
9539 /* Enum describing the various ways we can handle attributes.
9540 In many cases we can reuse the generic option handling machinery. */
9542 enum aarch64_attr_opt_type
9543 {
9547 aarch64_attr_custom /* Attribute requires a custom handling function. */
9548 };
9550 /* All the information needed to handle a target attribute.
9551 NAME is the name of the attribute.
9552 ATTR_TYPE specifies the type of behavior of the attribute as described
9553 in the definition of enum aarch64_attr_opt_type.
9554 ALLOW_NEG is true if the attribute supports a "no-" form.
9555 HANDLER is the function that takes the attribute string and whether
9556 it is a pragma or attribute and handles the option. It is needed only
9557 when the ATTR_TYPE is aarch64_attr_custom.
9558 OPT_NUM is the enum specifying the option that the attribute modifies.
9559 This is needed for attributes that mirror the behavior of a command-line
9560 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9561 aarch64_attr_enum. */
9563 struct aarch64_attribute_info
9564 {
9570 };
9572 /* Handle the ARCH_STR argument to the arch= target attribute.
9573 PRAGMA_OR_ATTR is used in potential error messages. */
9575 static bool
9577 {
9579 enum aarch64_parse_opt_result parse_res
9583 {
9588 }
9591 {
9605 }
9608 }
9610 /* Handle the argument CPU_STR to the cpu= target attribute.
9611 PRAGMA_OR_ATTR is used in potential error messages. */
9613 static bool
9615 {
9617 enum aarch64_parse_opt_result parse_res
9621 {
9629 }
9632 {
9646 }
9649 }
9651 /* Handle the argument STR to the tune= target attribute.
9652 PRAGMA_OR_ATTR is used in potential error messages. */
9654 static bool
9656 {
9658 enum aarch64_parse_opt_result parse_res
9662 {
9667 }
9670 {
9677 }
9680 }
9682 /* Parse an architecture extensions target attribute string specified in STR.
9683 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9684 if successful. Update aarch64_isa_flags to reflect the ISA features
9685 modified.
9686 PRAGMA_OR_ATTR is used in potential error messages. */
9688 static bool
9690 {
9694 /* We allow "+nothing" in the beginning to clear out all architectural
9695 features if the user wants to handpick specific features. */
9697 {
9700 }
9705 {
9708 }
9711 {
9724 }
9727 }
9729 /* The target attributes that we support. On top of these we also support just
9730 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9731 handled explicitly in aarch64_process_one_target_attr. */
9734 {
9736 OPT_mgeneral_regs_only },
9738 OPT_mfix_cortex_a53_835769 },
9740 OPT_mfix_cortex_a53_843419 },
9744 OPT_momit_leaf_frame_pointer },
9747 OPT_march_ },
9750 OPT_mtune_ },
9752 OPT_msign_return_address_ },
9754 };
9756 /* Parse ARG_STR which contains the definition of one target attribute.
9757 Show appropriate errors if any or return true if the attribute is valid.
9758 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9759 we're processing a target attribute or pragma. */
9761 static bool
9763 {
9769 {
9772 }
9777 /* Skip leading whitespace. */
9779 str_to_check++;
9781 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9782 It is easier to detect and handle it explicitly here rather than going
9783 through the machinery for the rest of the target attributes in this
9784 function. */
9789 {
9792 }
9795 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9796 and point ARG to "foo". */
9798 {
9800 arg++;
9801 }
9805 {
9806 /* If the names don't match up, or the user has given an argument
9807 to an attribute that doesn't accept one, or didn't give an argument
9808 to an attribute that expects one, fail to match. */
9817 {
9821 }
9823 /* If the name matches but the attribute does not allow "no-" versions
9824 then we can't match. */
9826 {
9830 }
9833 {
9834 /* Has a custom handler registered.
9835 For example, cpu=, arch=, tune=. */
9842 /* Either set or unset a boolean option. */
9844 {
9852 }
9853 /* Set or unset a bit in the target_flags. aarch64_handle_option
9854 should know what mask to apply given the option number. */
9856 {
9858 /* We only need to specify the option number.
9859 aarch64_handle_option will know which mask to apply. */
9865 }
9866 /* Use the option setting machinery to set an option to an enum. */
9868 {
9875 {
9878 global_dc);
9879 }
9880 else
9881 {
9884 }
9886 }
9889 }
9890 }
9892 /* If we reached here we either have found an attribute and validated
9893 it or didn't match any. If we matched an attribute but its arguments
9894 were malformed we will have returned false already. */
9896 }
9898 /* Count how many times the character C appears in
9899 NULL-terminated string STR. */
9901 static unsigned int
9903 {
9906 {
9908 res++;
9910 str++;
9911 }
9914 }
9916 /* Parse the tree in ARGS that contains the target attribute information
9917 and update the global target options space. PRAGMA_OR_ATTR is a string
9918 to be used in error messages, specifying whether this is processing
9919 a target attribute or a target pragma. */
9921 bool
9923 {
9925 {
9926 do
9927 {
9930 {
9933 }
9938 }
9941 {
9944 }
9951 {
9954 }
9956 /* Used to catch empty spaces between commas i.e.
9957 attribute ((target ("attr1,,attr2"))). */
9960 /* Handle multiple target attributes separated by ','. */
9965 {
9966 num_attrs++;
9968 {
9971 }
9974 }
9977 {
9981 }
9984 }
9986 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9987 process attribute ((target ("..."))). */
9989 static bool
9991 {
9994 tree old_optimize;
9998 /* If what we're processing is the current pragma string then the
9999 target option node is already stored in target_option_current_node
10000 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
10001 having to re-parse the string. This is especially useful to keep
10002 arm_neon.h compile times down since that header contains a lot
10003 of intrinsics enclosed in pragmas. */
10005 {
10008 }
10014 /* If the function changed the optimization levels as well as setting
10015 target options, start with the optimizations specified. */
10020 /* Save the current target options to restore at the end. */
10023 /* If fndecl already has some target attributes applied to it, unpack
10024 them so that we add this attribute on top of them, rather than
10025 overwriting them. */
10027 {
10033 }
10034 else
10041 /* Set up any additional state. */
10043 {
10045 /* Initialize SIMD builtins if we haven't already.
10046 Set current_target_pragma to NULL for the duration so that
10047 the builtin initialization code doesn't try to tag the functions
10048 being built with the attributes specified by any current pragma, thus
10049 going into an infinite recursion. */
10051 {
10056 }
10058 }
10059 else
10065 {
10070 }
10078 }
10080 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10081 tri-bool options (yes, no, don't care) and the default value is
10082 DEF, determine whether to reject inlining. */
10084 static bool
10087 {
10088 /* If the callee doesn't care, always allow inlining. */
10092 /* If the caller doesn't care, always allow inlining. */
10096 /* Otherwise, allow inlining if either the callee and caller values
10097 agree, or if the callee is using the default value. */
10099 }
10101 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10102 to inline CALLEE into CALLER based on target-specific info.
10103 Make sure that the caller and callee have compatible architectural
10104 features. Then go through the other possible target attributes
10105 and see if they can block inlining. Try not to reject always_inline
10106 callees unless they are incompatible architecturally. */
10108 static bool
10110 {
10114 /* If callee has no option attributes, then it is ok to inline. */
10125 /* Callee's ISA flags should be a subset of the caller's. */
10130 /* Allow non-strict aligned functions inlining into strict
10131 aligned ones. */
10141 /* If the architectural features match up and the callee is always_inline
10142 then the other attributes don't matter. */
10154 /* Honour explicit requests to workaround errata. */
10167 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10168 caller and calle and they don't match up, reject inlining. */
10175 /* If the callee has specific tuning overrides, respect them. */
10180 /* If the user specified tuning override strings for the
10181 caller and callee and they don't match up, reject inlining.
10182 We just do a string compare here, we don't analyze the meaning
10183 of the string, as it would be too costly for little gain. */
10191 }
10193 /* Return true if SYMBOL_REF X binds locally. */
10195 static bool
10197 {
10201 }
10203 /* Return true if SYMBOL_REF X is thread local */
10204 static bool
10206 {
10214 }
10216 /* Classify a TLS symbol into one of the TLS kinds. */
10217 enum aarch64_symbol_type
10219 {
10223 {
10230 {
10236 }
10247 else
10256 }
10257 }
10259 /* Return the method that should be used to access SYMBOL_REF or
10260 LABEL_REF X. */
10262 enum aarch64_symbol_type
10264 {
10266 {
10268 {
10283 }
10284 }
10287 {
10292 {
10294 /* When we retrieve symbol + offset address, we have to make sure
10295 the offset does not cause overflow of the final address. But
10296 we have no way of knowing the address of symbol at compile time
10297 so we can't accurately say if the distance between the PC and
10298 symbol + offset is outside the addressible range of +/-1M in the
10299 TINY code model. So we rely on images not being greater than
10300 1M and cap the offset at 1M and anything beyond 1M will have to
10301 be loaded using an alternative mechanism. Furthermore if the
10302 symbol is a weak reference to something that isn't known to
10303 resolve to a symbol in this module, then force to memory. */
10311 /* Same reasoning as the tiny code model, but the offset cap here is
10312 4G. */
10333 /* This is alright even in PIC code as the constant
10334 pool reference is always PC relative and within
10335 the same translation unit. */
10338 else
10343 }
10344 }
10346 /* By default push everything into the constant pool. */
10348 }
10350 bool
10352 {
10354 }
10356 bool
10358 {
10366 }
10368 /* Return true if X holds either a quarter-precision or
10369 floating-point +0.0 constant. */
10370 static bool
10372 {
10376 /* This call determines which constants can be used in mov<mode>
10377 as integer moves instead of constant loads. */
10382 }
10384 static bool
10386 {
10387 /* Do not allow vector struct mode constants. We could support
10388 0 and -1 easily, but they need support in aarch64-simd.md. */
10392 /* For these cases we never want to use a literal load.
10393 As such we have to prevent the compiler from forcing these
10394 to memory. */
10407 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10408 so spilling them is better than rematerialization. */
10413 }
10415 rtx
10417 {
10423 /* Can return in any reg. */
10426 }
10428 /* On AAPCS systems, this is the "struct __va_list". */
10431 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10432 Return the type to use as __builtin_va_list.
10434 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10436 struct __va_list
10437 {
10438 void *__stack;
10439 void *__gr_top;
10440 void *__vr_top;
10441 int __gr_offs;
10442 int __vr_offs;
10443 }; */
10445 static tree
10447 {
10448 tree va_list_name;
10451 /* Create the type. */
10453 /* Give it the required name. */
10455 TYPE_DECL,
10457 va_list_type);
10462 /* Create the fields. */
10465 ptr_type_node);
10468 ptr_type_node);
10471 ptr_type_node);
10474 integer_type_node);
10477 integer_type_node);
10479 /* Tell tree-stdarg pass about our internal offset fields.
10480 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10481 purpose to identify whether the code is updating va_list internal
10482 offset fields through irregular way. */
10504 /* Compute its layout. */
10508 }
10510 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10511 static void
10513 {
10517 tree t;
10531 {
10534 }
10543 NULL_TREE);
10545 NULL_TREE);
10547 NULL_TREE);
10549 NULL_TREE);
10551 NULL_TREE);
10553 /* Emit code to initialize STACK, which points to the next varargs stack
10554 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10555 by named arguments. STACK is 8-byte aligned. */
10562 /* Emit code to initialize GRTOP, the top of the GR save area.
10563 virtual_incoming_args_rtx should have been 16 byte aligned. */
10568 /* Emit code to initialize VRTOP, the top of the VR save area.
10569 This address is gr_save_area_bytes below GRTOP, rounded
10570 down to the next 16-byte boundary. */
10580 /* Emit code to initialize GROFF, the offset from GRTOP of the
10581 next GPR argument. */
10586 /* Likewise emit code to initialize VROFF, the offset from FTOP
10587 of the next VR argument. */
10591 }
10593 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10595 static tree
10598 {
10599 tree addr;
10605 machine_mode mode;
10632 type,
10636 {
10637 /* TYPE passed in fp/simd registers. */
10649 {
10652 }
10655 {
10657 }
10658 }
10659 else
10660 {
10661 /* TYPE passed in general registers. */
10674 {
10676 }
10677 }
10679 /* Get a local temporary for the field value. */
10682 /* Emit code to branch if off >= 0. */
10688 {
10689 /* Emit: offs = (offs + 15) & -16. */
10695 }
10696 else
10699 /* Update ap.__[g|v]r_offs */
10704 /* String up. */
10708 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10713 /* String up: make sure the assignment happens before the use. */
10717 /* Prepare the trees handling the argument that is passed on the stack;
10718 the top level node will store in ON_STACK. */
10721 {
10722 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10730 }
10731 else
10733 /* Advance ap.__stack */
10741 /* String up roundup and advance. */
10744 /* String up with arg */
10746 /* Big-endianness related address adjustment. */
10749 {
10753 }
10758 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10768 {
10769 /* type ha; // treat as "struct {ftype field[n];}"
10770 ... [computing offs]
10771 for (i = 0; i <nregs; ++i, offs += 16)
10772 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10773 return ha; */
10777 /* Declare a local variable. */
10781 /* Establish the base type. */
10783 {
10802 {
10806 }
10810 }
10812 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10820 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10822 {
10832 }
10836 }
10846 }
10848 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10850 static void
10854 {
10856 CUMULATIVE_ARGS local_cum;
10860 /* The caller has advanced CUM up to, but not beyond, the last named
10861 argument. Advance a local copy of CUM past the last "real" named
10862 argument, to find out how many registers are left over. */
10866 /* Found out how many registers we need to save.
10867 Honor tree-stdvar analysis results. */
10876 {
10879 }
10882 {
10884 {
10887 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10895 }
10897 {
10898 /* We can't use move_block_from_reg, because it will use
10899 the wrong mode, storing D regs only. */
10903 /* Set OFF to the offset from virtual_incoming_args_rtx of
10904 the first vector register. The VR save area lies below
10905 the GR one, and is aligned to 16 bytes. */
10912 {
10920 }
10921 }
10922 }
10924 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10925 any complication of having crtl->args.pretend_args_size changed. */
10930 }
10932 static void
10934 {
10937 {
10939 {
10942 }
10943 }
10944 }
10946 /* Walk down the type tree of TYPE counting consecutive base elements.
10947 If *MODEP is VOIDmode, then set it to the first valid floating point
10948 type. If a non-floating point type is found, or if a floating point
10949 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10950 otherwise return the count in the sub-tree. */
10951 static int
10953 {
10954 machine_mode mode;
10955 HOST_WIDE_INT size;
10958 {
10988 /* Use V2SImode and V4SImode as representatives of all 64-bit
10989 and 128-bit vector types. */
10992 {
11001 }
11006 /* Vector modes are considered to be opaque: two vectors are
11007 equivalent for the purposes of being homogeneous aggregates
11008 if they are the same size. */
11015 {
11019 /* Can't handle incomplete types nor sizes that are not
11020 fixed. */
11027 || !index
11038 /* There must be no padding. */
11043 }
11046 {
11049 tree field;
11051 /* Can't handle incomplete types nor sizes that are not
11052 fixed. */
11058 {
11066 }
11068 /* There must be no padding. */
11073 }
11077 {
11078 /* These aren't very interesting except in a degenerate case. */
11081 tree field;
11083 /* Can't handle incomplete types nor sizes that are not
11084 fixed. */
11090 {
11098 }
11100 /* There must be no padding. */
11105 }
11109 }
11112 }
11114 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11115 type as described in AAPCS64 \S 4.1.2.
11117 See the comment above aarch64_composite_type_p for the notes on MODE. */
11119 static bool
11121 machine_mode mode)
11122 {
11132 }
11134 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11135 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11136 array types. The C99 floating-point complex types are also considered
11137 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11138 types, which are GCC extensions and out of the scope of AAPCS64, are
11139 treated as composite types here as well.
11141 Note that MODE itself is not sufficient in determining whether a type
11142 is such a composite type or not. This is because
11143 stor-layout.c:compute_record_mode may have already changed the MODE
11144 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11145 structure with only one field may have its MODE set to the mode of the
11146 field. Also an integer mode whose size matches the size of the
11147 RECORD_TYPE type may be used to substitute the original mode
11148 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11149 solely relied on. */
11151 static bool
11153 machine_mode mode)
11154 {
11167 }
11169 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11170 shall be passed or returned in simd/fp register(s) (providing these
11171 parameter passing registers are available).
11173 Upon successful return, *COUNT returns the number of needed registers,
11174 *BASE_MODE returns the mode of the individual register and when IS_HAF
11175 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11176 floating-point aggregate or a homogeneous short-vector aggregate. */
11178 static bool
11180 const_tree type,
11184 {
11192 {
11195 }
11197 {
11201 }
11203 {
11207 {
11210 }
11211 else
11213 }
11214 else
11219 }
11221 /* Implement TARGET_STRUCT_VALUE_RTX. */
11223 static rtx
11226 {
11228 }
11230 /* Implements target hook vector_mode_supported_p. */
11231 static bool
11233 {
11245 }
11247 /* Return appropriate SIMD container
11248 for MODE within a vector of WIDTH bits. */
11249 static machine_mode
11251 {
11254 {
11257 {
11274 }
11275 else
11277 {
11290 }
11291 }
11293 }
11295 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11296 static machine_mode
11298 {
11300 }
11302 /* Return the bitmask of possible vector sizes for the vectorizer
11303 to iterate over. */
11304 static unsigned int
11306 {
11308 }
11310 /* Implement TARGET_MANGLE_TYPE. */
11314 {
11315 /* The AArch64 ABI documents say that "__va_list" has to be
11316 managled as if it is in the "std" namespace. */
11320 /* Half-precision float. */
11324 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11325 builtin types. */
11329 /* Use the default mangling. */
11331 }
11333 /* Find the first rtx_insn before insn that will generate an assembly
11334 instruction. */
11338 {
11342 do
11343 {
11345 }
11349 }
11351 static bool
11353 {
11355 /* A number of these may be AArch32 only. */
11360 };
11363 {
11366 }
11369 }
11371 /* Check if there is a register dependency between a load and the insn
11372 for which we hold recog_data. */
11374 static bool
11376 {
11377 rtx load_reg;
11387 {
11393 }
11395 }
11398 /* When working around the Cortex-A53 erratum 835769,
11399 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11400 instruction and has a preceding memory instruction such that a NOP
11401 should be inserted between them. */
11403 bool
11405 {
11408 rtx body;
11421 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11422 Restore recog state to INSN to avoid state corruption. */
11430 /* If the previous insn is a memory op and there is no dependency between
11431 it and the DImode madd, emit a NOP between them. If body is NULL then we
11432 have a complex memory operation, probably a load/store pair.
11433 Be conservative for now and emit a NOP. */
11440 }
11443 /* Implement FINAL_PRESCAN_INSN. */
11445 void
11447 {
11450 }
11453 /* Return the equivalent letter for size. */
11454 static char
11456 {
11458 {
11464 }
11465 }
11467 /* Return true iff x is a uniform vector of floating-point
11468 constants, and the constant can be represented in
11469 quarter-precision form. Note, as aarch64_float_const_representable
11470 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11471 static bool
11473 {
11474 rtx elt;
11478 }
11480 /* Return true for valid and false for invalid. */
11481 bool
11484 {
11485 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11486 matches = 1; \
11487 for (i = 0; i < idx; i += (STRIDE)) \
11488 if (!(TEST)) \
11489 matches = 0; \
11490 if (matches) \
11491 { \
11492 immtype = (CLASS); \
11493 elsize = (ELSIZE); \
11494 eshift = (SHIFT); \
11495 emvn = (NEG); \
11496 break; \
11497 }
11507 {
11513 {
11515 scalar_float_mode elt_mode
11522 }
11525 }
11527 /* Splat vector constant out into a byte vector. */
11529 {
11530 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11531 it must be laid out in the vector register in reverse order. */
11539 {
11542 }
11544 }
11546 /* Sanity check. */
11549 do
11550 {
11599 }
11606 {
11616 /* Un-invert bytes of recognized vector, if necessary. */
11622 {
11623 /* FIXME: Broken on 32-bit H_W_I hosts. */
11632 }
11633 else
11634 {
11638 /* Construct 'abcdefgh' because the assembler cannot handle
11639 generic constants. */
11644 }
11645 }
11648 #undef CHECK
11649 }
11651 /* Check of immediate shift constants are within range. */
11652 bool
11654 {
11658 else
11660 }
11662 /* Return true if X is a uniform vector where all elements
11663 are either the floating-point constant 0.0 or the
11664 integer constant 0. */
11665 bool
11667 {
11669 }
11672 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11673 operation of width WIDTH at bit position POS. */
11675 rtx
11677 {
11681 unsigned HOST_WIDE_INT mask
11684 }
11686 bool
11688 {
11701 }
11703 /* Return a const_int vector of VAL. */
11704 rtx
11706 {
11717 }
11719 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11721 bool
11723 {
11724 machine_mode vmode;
11729 }
11731 /* Construct and return a PARALLEL RTX vector with elements numbering the
11732 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11733 the vector - from the perspective of the architecture. This does not
11734 line up with GCC's perspective on lane numbers, so we end up with
11735 different masks depending on our target endian-ness. The diagram
11736 below may help. We must draw the distinction when building masks
11737 which select one half of the vector. An instruction selecting
11738 architectural low-lanes for a big-endian target, must be described using
11739 a mask selecting GCC high-lanes.
11741 Big-Endian Little-Endian
11743 GCC 0 1 2 3 3 2 1 0
11744 | x | x | x | x | | x | x | x | x |
11745 Architecture 3 2 1 0 3 2 1 0
11747 Low Mask: { 2, 3 } { 0, 1 }
11748 High Mask: { 0, 1 } { 2, 3 }
11749 */
11751 rtx
11753 {
11759 rtx t1;
11764 else
11772 }
11774 /* Check OP for validity as a PARALLEL RTX vector with elements
11775 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11776 from the perspective of the architecture. See the diagram above
11777 aarch64_simd_vect_par_cnst_half for more details. */
11779 bool
11782 {
11795 {
11802 }
11804 }
11806 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11807 HIGH (exclusive). */
11808 void
11810 const_tree exp)
11811 {
11812 HOST_WIDE_INT lane;
11817 {
11820 else
11822 }
11823 }
11825 /* Return TRUE if OP is a valid vector addressing mode. */
11826 bool
11828 {
11831 }
11833 /* Emit a register copy from operand to operand, taking care not to
11834 early-clobber source registers in the process.
11836 COUNT is the number of components into which the copy needs to be
11837 decomposed. */
11838 void
11841 {
11851 else
11855 }
11857 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11858 one of VSTRUCT modes: OI, CI, or XI. */
11859 int
11861 {
11863 }
11865 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11866 alignment of a vector to 128 bits. */
11867 static HOST_WIDE_INT
11869 {
11872 }
11874 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11875 static bool
11877 {
11881 /* We guarantee alignment for vectors up to 128-bits. */
11886 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11888 }
11890 /* Return true if the vector misalignment factor is supported by the
11891 target. */
11892 static bool
11896 {
11898 {
11899 /* Return if movmisalign pattern is not supported for this mode. */
11904 {
11905 /* Misalignment factor is unknown at compile time but we know
11906 it's word aligned. */
11908 {
11913 }
11915 }
11916 }
11918 is_packed);
11919 }
11921 /* If VALS is a vector constant that can be loaded into a register
11922 using DUP, generate instructions to do so and return an RTX to
11923 assign to the register. Otherwise return NULL_RTX. */
11924 static rtx
11926 {
11929 rtx x;
11934 /* We can load this constant by using DUP and a constant in a
11935 single ARM register. This will be cheaper than a vector
11936 load. */
11939 }
11942 /* Generate code to load VALS, which is a PARALLEL containing only
11943 constants (for vec_init) or CONST_VECTOR, efficiently into a
11944 register. Returns an RTX to copy into the register, or NULL_RTX
11945 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11946 static rtx
11948 {
11950 rtx const_dup;
11959 {
11960 /* A CONST_VECTOR must contain only CONST_INTs and
11961 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11962 Only store valid constants in a CONST_VECTOR. */
11964 {
11967 n_const++;
11968 }
11971 }
11972 else
11977 /* Load using MOVI/MVNI. */
11980 /* Loaded using DUP. */
11983 /* Load from constant pool. We can not take advantage of single-cycle
11984 LD1 because we need a PC-relative addressing mode. */
11986 else
11987 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11988 We can not construct an initializer. */
11990 }
11992 /* Expand a vector initialisation sequence, such that TARGET is
11993 initialised to contain VALS. */
11995 void
11997 {
12000 /* The number of vector elements. */
12002 /* The number of vector elements which are not constant. */
12005 /* The first element of vals. */
12009 /* Count the number of variable elements to initialise. */
12011 {
12015 else
12019 }
12021 /* No variable elements, hand off to aarch64_simd_make_constant which knows
12022 how best to handle this. */
12024 {
12027 {
12030 }
12031 }
12033 /* Splat a single non-constant element if we can. */
12035 {
12039 }
12044 /* If there are only variable elements, try to optimize
12045 the insertion using dup for the most common element
12046 followed by insertions. */
12048 /* The algorithm will fill matches[*][0] with the earliest matching element,
12049 and matches[X][1] with the count of duplicate elements (if X is the
12050 earliest element which has duplicates). */
12053 {
12056 {
12058 {
12060 {
12064 }
12065 }
12066 }
12071 {
12074 }
12076 /* Create a duplicate of the most common element. */
12080 /* Insert the rest. */
12082 {
12088 }
12090 }
12092 /* Initialise a vector which is part-variable. We want to first try
12093 to build those lanes which are constant in the most efficient way we
12094 can. */
12096 {
12099 /* Load constant part of vector. We really don't care what goes into the
12100 parts we will overwrite, but we're more likely to be able to load the
12101 constant efficiently if it has fewer, larger, repeating parts
12102 (see aarch64_simd_valid_immediate). */
12104 {
12110 {
12111 /* Look in the copied vector, as more elements are const. */
12114 {
12117 }
12118 }
12120 }
12122 }
12124 /* Insert the variable lanes directly. */
12126 {
12132 }
12133 }
12135 static unsigned HOST_WIDE_INT
12137 {
12138 return
12139 (!SHIFT_COUNT_TRUNCATED
12142 }
12144 /* Select a format to encode pointers in exception handling data. */
12145 int
12147 {
12150 {
12156 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12157 for everything. */
12161 /* No assumptions here. 8-byte relocs required. */
12164 }
12166 }
12168 /* The last .arch and .tune assembly strings that we printed. */
12172 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12173 by the function fndecl. */
12175 void
12177 tree fndecl)
12178 {
12184 else
12195 /* Only update the assembler .arch string if it is distinct from the last
12196 such string we printed. */
12199 {
12202 }
12204 /* Print the cpu name we're tuning for in the comments, might be
12205 useful to readers of the generated asm. Do it only when it changes
12206 from function to function and verbose assembly is requested. */
12211 {
12215 }
12217 /* Don't forget the type directive for ELF. */
12220 }
12222 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12224 static void
12226 {
12243 }
12245 /* Emit load exclusive. */
12247 static void
12250 {
12254 {
12261 }
12264 }
12266 /* Emit store exclusive. */
12268 static void
12271 {
12275 {
12282 }
12285 }
12287 /* Mark the previous jump instruction as unlikely. */
12289 static void
12291 {
12294 }
12296 /* Expand a compare and swap pattern. */
12298 void
12300 {
12305 gen_cas_fn gen;
12307 {
12308 gen_aarch64_compare_and_swapqi,
12309 gen_aarch64_compare_and_swaphi,
12310 gen_aarch64_compare_and_swapsi,
12311 gen_aarch64_compare_and_swapdi
12312 };
12314 {
12315 gen_aarch64_compare_and_swapqi_lse,
12316 gen_aarch64_compare_and_swaphi_lse,
12317 gen_aarch64_compare_and_swapsi_lse,
12318 gen_aarch64_compare_and_swapdi_lse
12319 };
12332 /* Normally the succ memory model must be stronger than fail, but in the
12333 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12334 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12341 {
12344 /* For short modes, we're going to perform the comparison in SImode,
12345 so do the zero-extension now. */
12349 /* Fall through. */
12353 /* Force the value into a register if needed. */
12360 }
12363 {
12370 }
12373 else
12384 }
12386 /* Test whether the target supports using a atomic load-operate instruction.
12387 CODE is the operation and AFTER is TRUE if the data in memory after the
12388 operation should be returned and FALSE if the data before the operation
12389 should be returned. Returns FALSE if the operation isn't supported by the
12390 architecture. */
12392 bool
12394 {
12399 {
12409 }
12410 }
12412 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12413 sequence implementing an atomic operation. */
12415 static void
12417 {
12424 {
12426 }
12427 }
12429 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12430 for the data in memory. EXPECTED is the value expected to be in memory.
12431 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12432 is the memory ordering to use. */
12434 void
12437 rtx model)
12438 {
12440 machine_mode mode;
12445 {
12452 }
12454 /* Move the expected value into the CAS destination register. */
12457 /* Emit the CAS. */
12460 /* Compare the expected value with the value loaded by the CAS, to establish
12461 whether the swap was made. */
12463 }
12465 /* Split a compare and swap pattern. */
12467 void
12469 {
12471 machine_mode mode;
12476 rtx model_rtx;
12488 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12489 loop:
12490 .label1:
12491 LD[A]XR rval, [mem]
12492 CBNZ rval, .label2
12493 ST[L]XR scratch, newval, [mem]
12494 CBNZ scratch, .label1
12495 .label2:
12496 CMP rval, 0. */
12501 {
12504 }
12507 /* The initial load can be relaxed for a __sync operation since a final
12508 barrier will be emitted to stop code hoisting. */
12512 else
12516 {
12521 }
12522 else
12523 {
12529 }
12534 {
12539 }
12540 else
12541 {
12545 }
12548 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12549 to set the condition flags. If this is not used it will be removed by
12550 later passes. */
12552 {
12556 }
12557 /* Emit any final barrier needed for a __sync operation. */
12560 }
12562 /* Emit a BIC instruction. */
12564 static void
12566 {
12571 {
12576 }
12579 }
12581 /* Emit an atomic swap. */
12583 static void
12586 {
12590 {
12597 }
12600 }
12602 /* Operations supported by aarch64_emit_atomic_load_op. */
12604 enum aarch64_atomic_load_op_code
12605 {
12609 AARCH64_LDOP_BIC /* A & ~B */
12610 };
12612 /* Emit an atomic load-operate. */
12614 static void
12618 {
12621 {
12622 gen_aarch64_atomic_loadaddqi,
12623 gen_aarch64_atomic_loadaddhi,
12624 gen_aarch64_atomic_loadaddsi,
12625 gen_aarch64_atomic_loadadddi
12626 };
12628 {
12629 gen_aarch64_atomic_loadeorqi,
12630 gen_aarch64_atomic_loadeorhi,
12631 gen_aarch64_atomic_loadeorsi,
12632 gen_aarch64_atomic_loadeordi
12633 };
12635 {
12636 gen_aarch64_atomic_loadsetqi,
12637 gen_aarch64_atomic_loadsethi,
12638 gen_aarch64_atomic_loadsetsi,
12639 gen_aarch64_atomic_loadsetdi
12640 };
12642 {
12643 gen_aarch64_atomic_loadclrqi,
12644 gen_aarch64_atomic_loadclrhi,
12645 gen_aarch64_atomic_loadclrsi,
12646 gen_aarch64_atomic_loadclrdi
12647 };
12648 aarch64_atomic_load_op_fn gen;
12652 {
12659 }
12662 {
12669 }
12672 }
12674 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12675 location to store the data read from memory. OUT_RESULT is the location to
12676 store the result of the operation. MEM is the memory location to read and
12677 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12678 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12679 be NULL. */
12681 void
12684 {
12688 aarch64_atomic_load_op_code ldop_code;
12689 rtx src;
12690 rtx x;
12698 /* Make sure the value is in a register, putting it into a destination
12699 register if it needs to be manipulated. */
12702 {
12705 }
12706 else
12710 /* Preprocess the data for the operation as necessary. If the operation is
12711 a SET then emit a swap instruction and finish. */
12713 {
12719 /* Negate the value and treat it as a PLUS. */
12720 {
12721 rtx neg_src;
12723 /* Resize the value if necessary. */
12732 }
12733 /* Fall-through. */
12747 {
12748 rtx not_src;
12750 /* Resize the value if necessary. */
12759 }
12764 /* The operation can't be done with atomic instructions. */
12766 }
12770 /* If necessary, calculate the data in memory after the update by redoing the
12771 operation from values in registers. */
12776 {
12780 }
12785 {
12801 }
12806 }
12808 /* Split an atomic operation. */
12810 void
12813 {
12819 rtx x;
12821 /* Split the atomic operation into a sequence. */
12829 else
12833 /* The initial load can be relaxed for a __sync operation since a final
12834 barrier will be emitted to stop code hoisting. */
12838 else
12842 {
12856 {
12859 }
12860 /* Fall through. */
12866 }
12876 /* Emit any final barrier needed for a __sync operation. */
12879 }
12881 static void
12883 {
12884 /* Half-precision float operations. The compiler handles all operations
12885 with NULL libfuncs by converting to SFmode. */
12887 /* Conversions. */
12891 /* Arithmetic. */
12898 /* Comparisons. */
12906 }
12908 /* Target hook for c_mode_for_suffix. */
12909 static machine_mode
12911 {
12916 }
12918 /* We can only represent floating point constants which will fit in
12919 "quarter-precision" values. These values are characterised by
12920 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12921 by:
12923 (-1)^s * (n/16) * 2^r
12925 Where:
12926 's' is the sign bit.
12927 'n' is an integer in the range 16 <= n <= 31.
12928 'r' is an integer in the range -3 <= r <= 4. */
12930 /* Return true iff X can be represented by a quarter-precision
12931 floating point immediate operand X. Note, we cannot represent 0.0. */
12932 bool
12934 {
12935 /* This represents our current view of how many bits
12936 make up the mantissa. */
12946 /* We don't support HFmode constants yet. */
12952 /* We cannot represent infinities, NaNs or +/-zero. We won't
12953 know if we have +zero until we analyse the mantissa, but we
12954 can reject the other invalid values. */
12959 /* Extract exponent. */
12963 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12964 highest (sign) bit, with a fixed binary point at bit point_pos.
12965 m1 holds the low part of the mantissa, m2 the high part.
12966 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12967 bits for the mantissa, this can fail (low bits will be lost). */
12971 /* If the low part of the mantissa has bits set we cannot represent
12972 the value. */
12975 /* We have rejected the lower HOST_WIDE_INT, so update our
12976 understanding of how many bits lie in the mantissa and
12977 look only at the high HOST_WIDE_INT. */
12981 /* We can only represent values with a mantissa of the form 1.xxxx. */
12986 /* Having filtered unrepresentable values, we may now remove all
12987 but the highest 5 bits. */
12990 /* We cannot represent the value 0.0, so reject it. This is handled
12991 elsewhere. */
12995 /* Then, as bit 4 is always set, we can mask it off, leaving
12996 the mantissa in the range [0, 15]. */
13000 /* GCC internally does not use IEEE754-like encoding (where normalized
13001 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
13002 Our mantissa values are shifted 4 places to the left relative to
13003 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
13004 by 5 places to correct for GCC's representation. */
13008 }
13012 machine_mode mode,
13014 {
13024 /* This will return true to show const_vector is legal for use as either
13025 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
13026 also update INFO to show how the immediate should be generated. */
13035 {
13037 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
13038 move immediate path. */
13041 else
13042 {
13051 else
13055 }
13056 }
13069 else
13073 }
13077 {
13079 /* If a floating point number was passed and we desire to use it in an
13080 integer mode do the conversion to integer. */
13082 {
13087 }
13089 machine_mode vmode;
13090 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13091 a 128 bit vector mode. */
13097 }
13099 /* Split operands into moves from op[1] + op[2] into op[0]. */
13101 void
13103 {
13114 {
13115 /* No-op move. Can't split to nothing; emit something. */
13118 }
13120 /* Preserve register attributes for variable tracking. */
13125 /* Special case of reversed high/low parts. */
13128 {
13132 }
13134 {
13135 /* Try to avoid unnecessary moves if part of the result
13136 is in the right place already. */
13141 }
13142 else
13143 {
13148 }
13149 }
13151 /* vec_perm support. */
13153 #define MAX_VECT_LEN 16
13155 struct expand_vec_perm_d
13156 {
13159 machine_mode vmode;
13163 };
13165 /* Generate a variable permutation. */
13167 static void
13169 {
13180 {
13182 {
13183 /* Expand the argument to a V16QI mode by duplicating it. */
13187 }
13188 else
13189 {
13191 }
13192 }
13193 else
13194 {
13195 rtx pair;
13198 {
13202 }
13203 else
13204 {
13208 }
13209 }
13210 }
13212 void
13214 {
13218 rtx mask;
13220 /* The TBL instruction does not use a modulo index, so we must take care
13221 of that ourselves. */
13226 /* For big-endian, we also need to reverse the index within the vector
13227 (but not which vector). */
13229 {
13230 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13235 }
13237 }
13239 /* Recognize patterns suitable for the TRN instructions. */
13240 static bool
13242 {
13251 /* Note that these are little-endian tests.
13252 We correct for big-endian later. */
13257 else
13262 {
13267 }
13269 /* Success! */
13276 {
13279 }
13283 {
13285 {
13300 }
13301 }
13302 else
13303 {
13305 {
13320 }
13321 }
13325 }
13327 /* Recognize patterns suitable for the UZP instructions. */
13328 static bool
13330 {
13339 /* Note that these are little-endian tests.
13340 We correct for big-endian later. */
13345 else
13350 {
13354 }
13356 /* Success! */
13363 {
13366 }
13370 {
13372 {
13387 }
13388 }
13389 else
13390 {
13392 {
13407 }
13408 }
13412 }
13414 /* Recognize patterns suitable for the ZIP instructions. */
13415 static bool
13417 {
13426 /* Note that these are little-endian tests.
13427 We correct for big-endian later. */
13430 /* Do Nothing. */
13431 ;
13434 else
13439 {
13446 }
13448 /* Success! */
13455 {
13458 }
13462 {
13464 {
13479 }
13480 }
13481 else
13482 {
13484 {
13499 }
13500 }
13504 }
13506 /* Recognize patterns for the EXT insn. */
13508 static bool
13510 {
13513 rtx offset;
13517 /* Check if the extracted indices are increasing by one. */
13519 {
13522 {
13523 /* We'll pass the same vector in twice, so allow indices to wrap. */
13525 }
13528 }
13531 {
13546 }
13548 /* Success! */
13552 /* The case where (location == 0) is a no-op for both big- and little-endian,
13553 and is removed by the mid-end at optimization levels -O1 and higher. */
13556 {
13557 /* After setup, we want the high elements of the first vector (stored
13558 at the LSB end of the register), and the low elements of the second
13559 vector (stored at the MSB end of the register). So swap. */
13561 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13563 }
13568 }
13570 /* Recognize patterns for the REV insns. */
13572 static bool
13574 {
13583 {
13586 {
13591 }
13595 {
13602 }
13606 {
13619 }
13623 }
13627 {
13628 /* This is guaranteed to be true as the value of diff
13629 is 7, 3, 1 and we should have enough elements in the
13630 queue to generate this. Getting a vector mask with a
13631 value of diff other than these values implies that
13632 something is wrong by the time we get here. */
13636 }
13638 /* Success! */
13644 }
13646 static bool
13648 {
13651 rtx in0;
13654 rtx lane;
13658 {
13661 }
13663 /* The generic preparation in aarch64_expand_vec_perm_const_1
13664 swaps the operand order and the permute indices if it finds
13665 d->perm[0] to be in the second operand. Thus, we can always
13666 use d->op0 and need not do any extra arithmetic to get the
13667 correct lane number. */
13672 {
13687 }
13691 }
13693 static bool
13695 {
13703 /* Generic code will try constant permutation twice. Once with the
13704 original mode and again with the elements lowered to QImode.
13705 So wait and don't do the selector expansion ourselves. */
13710 {
13713 /* If big-endian and two vectors we end up with a weird mixed-endian
13714 mode on NEON. Reverse the index within each word but not the word
13715 itself. */
13718 }
13724 }
13726 static bool
13728 {
13729 /* The pattern matching functions above are written to look for a small
13730 number to begin the sequence (0, 1, N/2). If we begin with an index
13731 from the second operand, we can swap the operands. */
13733 {
13741 }
13744 {
13758 }
13760 }
13762 /* Expand a vec_perm_const pattern. */
13764 bool
13766 {
13780 {
13785 }
13788 {
13797 /* The elements of PERM do not suggest that only the first operand
13798 is used, but both operands are identical. Allow easier matching
13799 of the permutation by folding the permutation into the single
13800 input vector. */
13801 /* Fall Through. */
13813 }
13816 }
13818 static bool
13821 {
13831 /* Calculate whether all elements are in one vector. */
13833 {
13837 }
13839 /* If all elements are from the second vector, reindex as if from the
13840 first vector. */
13845 /* Check whether the mask can be applied to a single vector. */
13858 }
13860 rtx
13862 {
13863 /* We have to reverse each vector because we dont have
13864 a permuted load that can reverse-load according to ABI rules. */
13865 rtx mask;
13879 }
13881 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
13882 true. However due to issues with register allocation it is preferable
13883 to avoid tieing integer scalar and FP scalar modes. Executing integer
13884 operations in general registers is better than treating them as scalar
13885 vector operations. This reduces latency and avoids redundant int<->FP
13886 moves. So tie modes if they are either the same class, or vector modes
13887 with other vector modes, vector structs or any scalar mode. */
13889 static bool
13891 {
13895 /* We specifically want to allow elements of "structure" modes to
13896 be tieable to the structure. This more general condition allows
13897 other rarer situations too. */
13901 /* Also allow any scalar modes with vectors. */
13907 }
13909 /* Return a new RTX holding the result of moving POINTER forward by
13910 AMOUNT bytes. */
13912 static rtx
13914 {
13919 }
13921 /* Return a new RTX holding the result of moving POINTER forward by the
13922 size of the mode it points to. */
13924 static rtx
13926 {
13930 }
13932 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13933 MODE bytes. */
13935 static void
13937 machine_mode mode)
13938 {
13941 /* "Cast" the pointers to the correct mode. */
13944 /* Emit the memcpy. */
13947 /* Move the pointers forward. */
13950 }
13952 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13953 we succeed, otherwise return false. */
13955 bool
13957 {
13961 rtx base;
13964 /* When optimizing for size, give a better estimate of the length of a
13965 memcpy call, but use the default otherwise. */
13968 /* We can't do anything smart if the amount to copy is not constant. */
13974 /* Try to keep the number of instructions low. For cases below 16 bytes we
13975 need to make at most two moves. For cases above 16 bytes it will be one
13976 move for each 16 byte chunk, then at most two additional moves. */
13986 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13987 1-byte chunk. */
13989 {
13991 {
13994 }
14000 }
14002 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
14003 4-byte chunk, partially overlapping with the previously copied chunk. */
14005 {
14009 {
14015 }
14017 }
14019 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
14020 them, then (if applicable) an 8-byte chunk. */
14022 {
14024 {
14027 }
14028 else
14029 {
14032 }
14033 }
14035 /* Finish the final bytes of the copy. We can always do this in one
14036 instruction. We either copy the exact amount we need, or partially
14037 overlap with the previous chunk we copied and copy 8-bytes. */
14046 else
14047 {
14049 {
14053 }
14054 else
14055 {
14061 }
14062 }
14065 }
14067 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
14068 SImode stores. Handle the case when the constant has identical
14069 bottom and top halves. This is beneficial when the two stores can be
14070 merged into an STP and we avoid synthesising potentially expensive
14071 immediates twice. Return true if such a split is possible. */
14073 bool
14075 {
14084 unsigned int orig_cost
14086 unsigned int lo_cost
14089 /* We want to transform:
14090 MOV x1, 49370
14091 MOVK x1, 0x140, lsl 16
14092 MOVK x1, 0xc0da, lsl 32
14093 MOVK x1, 0x140, lsl 48
14094 STR x1, [x0]
14095 into:
14096 MOV w1, 49370
14097 MOVK w1, 0x140, lsl 16
14098 STP w1, w1, [x0]
14099 So we want to perform this only when we save two instructions
14100 or more. When optimizing for size, however, accept any code size
14101 savings we can. */
14116 /* Don't emit an explicit store pair as this may not be always profitable.
14117 Let the sched-fusion logic decide whether to merge them. */
14122 }
14124 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
14126 static unsigned HOST_WIDE_INT
14128 {
14130 }
14132 static bool
14137 {
14138 /* STORE_BY_PIECES can be used when copying a constant string, but
14139 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
14140 For now we always fail this and let the move_by_pieces code copy
14141 the string from read-only memory. */
14146 }
14148 static rtx
14151 {
14155 insn_code icode;
14166 {
14194 }
14199 {
14202 }
14211 {
14214 }
14220 }
14222 static rtx
14225 {
14229 insn_code icode;
14241 {
14269 }
14274 {
14277 }
14285 {
14290 }
14301 {
14304 }
14310 }
14312 #undef TARGET_GEN_CCMP_FIRST
14313 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14315 #undef TARGET_GEN_CCMP_NEXT
14316 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14318 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14319 instruction fusion of some sort. */
14321 static bool
14323 {
14325 }
14328 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14329 should be kept together during scheduling. */
14331 static bool
14333 {
14334 rtx set_dest;
14337 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14344 {
14345 /* We are trying to match:
14346 prev (mov) == (set (reg r0) (const_int imm16))
14347 curr (movk) == (set (zero_extract (reg r0)
14348 (const_int 16)
14349 (const_int 16))
14350 (const_int imm16_1)) */
14362 {
14364 }
14365 }
14368 {
14370 /* We're trying to match:
14371 prev (adrp) == (set (reg r1)
14372 (high (symbol_ref ("SYM"))))
14373 curr (add) == (set (reg r0)
14374 (lo_sum (reg r1)
14375 (symbol_ref ("SYM"))))
14376 Note that r0 need not necessarily be the same as r1, especially
14377 during pre-regalloc scheduling. */
14381 {
14389 }
14390 }
14393 {
14395 /* We're trying to match:
14396 prev (movk) == (set (zero_extract (reg r0)
14397 (const_int 16)
14398 (const_int 32))
14399 (const_int imm16_1))
14400 curr (movk) == (set (zero_extract (reg r0)
14401 (const_int 16)
14402 (const_int 48))
14403 (const_int imm16_2)) */
14419 }
14421 {
14422 /* We're trying to match:
14423 prev (adrp) == (set (reg r0)
14424 (high (symbol_ref ("SYM"))))
14425 curr (ldr) == (set (reg r1)
14426 (mem (lo_sum (reg r0)
14427 (symbol_ref ("SYM")))))
14428 or
14429 curr (ldr) == (set (reg r1)
14430 (zero_extend (mem
14431 (lo_sum (reg r0)
14432 (symbol_ref ("SYM")))))) */
14435 {
14448 }
14449 }
14457 {
14461 rtx cc_reg_1;
14466 && prev
14468 {
14469 /* FIXME: this misses some which is considered simple arthematic
14470 instructions for ThunderX. Simple shifts are missed here. */
14476 }
14477 }
14480 && curr_set
14483 {
14484 /* We're trying to match:
14485 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14486 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14487 (const_int 0))
14488 (label_ref ("SYM"))
14489 (pc)) */
14496 {
14497 /* Fuse ALU operations followed by conditional branch instruction. */
14499 {
14520 }
14521 }
14522 }
14525 }
14527 /* Return true iff the instruction fusion described by OP is enabled. */
14529 bool
14531 {
14533 }
14535 /* If MEM is in the form of [base+offset], extract the two parts
14536 of address and set to BASE and OFFSET, otherwise return false
14537 after clearing BASE and OFFSET. */
14539 bool
14541 {
14542 rtx addr;
14549 {
14553 }
14557 {
14561 }
14567 }
14569 /* Types for scheduling fusion. */
14570 enum sched_fusion_type
14571 {
14573 SCHED_FUSION_LD_SIGN_EXTEND,
14574 SCHED_FUSION_LD_ZERO_EXTEND,
14575 SCHED_FUSION_LD,
14576 SCHED_FUSION_ST,
14577 SCHED_FUSION_NUM
14578 };
14580 /* If INSN is a load or store of address in the form of [base+offset],
14581 extract the two parts and set to BASE and OFFSET. Return scheduling
14582 fusion type this INSN is. */
14584 static enum sched_fusion_type
14586 {
14604 {
14609 }
14611 {
14616 }
14621 {
14624 }
14625 else
14632 }
14634 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14636 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14637 and PRI are only calculated for these instructions. For other instruction,
14638 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14639 type instruction fusion can be added by returning different priorities.
14641 It's important that irrelevant instructions get the largest FUSION_PRI. */
14643 static void
14646 {
14656 {
14660 }
14662 /* Set FUSION_PRI according to fusion type and base register. */
14665 /* Calculate PRI. */
14668 /* INSN with smaller offset goes first. */
14672 else
14677 }
14679 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14680 Adjust priority of sha1h instructions so they are scheduled before
14681 other SHA1 instructions. */
14683 static int
14685 {
14689 {
14694 }
14697 }
14699 /* Given OPERANDS of consecutive load/store, check if we can merge
14700 them into ldp/stp. LOAD is true if they are load instructions.
14701 MODE is the mode of memory operands. */
14703 bool
14705 machine_mode mode)
14706 {
14712 {
14720 }
14721 else
14722 {
14727 }
14729 /* The mems cannot be volatile. */
14733 /* If we have SImode and slow unaligned ldp,
14734 check the alignment to be at least 8 byte. */
14738 && !optimize_size
14742 /* Check if the addresses are in the form of [base+offset]. */
14750 /* Check if the bases are same. */
14757 /* Check if the offsets are consecutive. */
14761 /* Check if the addresses are clobbered by load. */
14763 {
14767 /* In increasing order, the last load can clobber the address. */
14770 }
14774 else
14779 else
14782 /* Check if the registers are of same class. */
14787 }
14789 /* Given OPERANDS of consecutive load/store, check if we can merge
14790 them into ldp/stp by adjusting the offset. LOAD is true if they
14791 are load instructions. MODE is the mode of memory operands.
14793 Given below consecutive stores:
14795 str w1, [xb, 0x100]
14796 str w1, [xb, 0x104]
14797 str w1, [xb, 0x108]
14798 str w1, [xb, 0x10c]
14800 Though the offsets are out of the range supported by stp, we can
14801 still pair them after adjusting the offset, like:
14803 add scratch, xb, 0x100
14804 stp w1, w1, [scratch]
14805 stp w1, w1, [scratch, 0x8]
14807 The peephole patterns detecting this opportunity should guarantee
14808 the scratch register is avaliable. */
14810 bool
14812 scalar_mode mode)
14813 {
14820 {
14833 }
14834 else
14835 {
14844 }
14845 /* Skip if memory operand is by itslef valid for ldp/stp. */
14849 /* The mems cannot be volatile. */
14854 /* Check if the addresses are in the form of [base+offset]. */
14868 /* Check if the bases are same. */
14879 /* Check if the offsets are consecutive. */
14888 /* Check if the addresses are clobbered by load. */
14890 {
14896 /* In increasing order, the last load can clobber the address. */
14899 }
14901 /* If we have SImode and slow unaligned ldp,
14902 check the alignment to be at least 8 byte. */
14906 && !optimize_size
14912 else
14917 else
14922 else
14927 else
14930 /* Check if the registers are of same class. */
14935 }
14937 /* Given OPERANDS of consecutive load/store, this function pairs them
14938 into ldp/stp after adjusting the offset. It depends on the fact
14939 that addresses of load/store instructions are in increasing order.
14940 MODE is the mode of memory operands. CODE is the rtl operator
14941 which should be applied to all memory operands, it's SIGN_EXTEND,
14942 ZERO_EXTEND or UNKNOWN. */
14944 bool
14947 {
14953 {
14958 }
14959 else
14960 {
14966 }
14971 /* Adjust offset thus it can fit in ldp/stp instruction. */
14979 /* Further adjust to make sure all offsets are OK. */
14981 {
14984 }
14986 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14991 {
14994 }
14996 /* Create new memory references. */
15000 /* Check if the adjusted address is OK for ldp/stp. */
15019 {
15024 }
15026 {
15031 }
15034 {
15039 }
15040 else
15041 {
15046 }
15048 /* Emit adjusting instruction. */
15050 /* Emit ldp/stp instructions. */
15058 }
15060 /* Return 1 if pseudo register should be created and used to hold
15061 GOT address for PIC code. */
15063 bool
15065 {
15067 }
15069 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
15071 static int
15073 {
15075 {
15082 }
15085 }
15088 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
15089 return the log2 of that value. Otherwise return -1. */
15091 int
15093 {
15108 }
15110 /* If X is a vector of equal CONST_DOUBLE values and that value is
15111 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
15113 int
15115 {
15131 }
15133 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
15134 to float.
15136 __fp16 always promotes through this hook.
15137 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
15138 through the generic excess precision logic rather than here. */
15140 static tree
15142 {
15148 }
15150 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
15152 static bool
15154 optimization_type opt_type)
15155 {
15157 {
15163 }
15164 }
15166 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
15167 if MODE is HFmode, and punt to the generic implementation otherwise. */
15169 static bool
15171 {
15175 }
15177 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15178 if MODE is HFmode, and punt to the generic implementation otherwise. */
15180 static bool
15182 {
15186 }
15188 /* Set the value of FLT_EVAL_METHOD.
15189 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15191 0: evaluate all operations and constants, whose semantic type has at
15192 most the range and precision of type float, to the range and
15193 precision of float; evaluate all other operations and constants to
15194 the range and precision of the semantic type;
15196 N, where _FloatN is a supported interchange floating type
15197 evaluate all operations and constants, whose semantic type has at
15198 most the range and precision of _FloatN type, to the range and
15199 precision of the _FloatN type; evaluate all other operations and
15200 constants to the range and precision of the semantic type;
15202 If we have the ARMv8.2-A extensions then we support _Float16 in native
15203 precision, so we should set this to 16. Otherwise, we support the type,
15204 but want to evaluate expressions in float precision, so set this to
15205 0. */
15207 static enum flt_eval_method
15209 {
15211 {
15214 /* We can calculate either in 16-bit range and precision or
15215 32-bit range and precision. Make that decision based on whether
15216 we have native support for the ARMv8.2-A 16-bit floating-point
15217 instructions or not. */
15219 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15225 }
15227 }
15229 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15230 scheduled for speculative execution. Reject the long-running division
15231 and square-root instructions. */
15233 static bool
15235 {
15237 {
15255 }
15256 }
15258 /* Target-specific selftests. */
15260 #if CHECKING_P
15264 /* Selftest for the RTL loader.
15265 Verify that the RTL loader copes with a dump from
15266 print_rtx_function. This is essentially just a test that class
15267 function_reader can handle a real dump, but it also verifies
15268 that lookup_reg_by_dump_name correctly handles hard regs.
15269 The presence of hard reg names in the dump means that the test is
15270 target-specific, hence it is in this file. */
15272 static void
15274 {
15286 /* Verify crtl->return_rtx. */
15290 }
15292 /* Run all target-specific selftests. */
15294 static void
15296 {
15298 }
15304 #undef TARGET_ADDRESS_COST
15305 #define TARGET_ADDRESS_COST aarch64_address_cost
15307 /* This hook will determines whether unnamed bitfields affect the alignment
15308 of the containing structure. The hook returns true if the structure
15309 should inherit the alignment requirements of an unnamed bitfield's
15310 type. */
15311 #undef TARGET_ALIGN_ANON_BITFIELD
15312 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15314 #undef TARGET_ASM_ALIGNED_DI_OP
15317 #undef TARGET_ASM_ALIGNED_HI_OP
15320 #undef TARGET_ASM_ALIGNED_SI_OP
15323 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15324 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15325 hook_bool_const_tree_hwi_hwi_const_tree_true
15327 #undef TARGET_ASM_FILE_START
15328 #define TARGET_ASM_FILE_START aarch64_start_file
15330 #undef TARGET_ASM_OUTPUT_MI_THUNK
15331 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15333 #undef TARGET_ASM_SELECT_RTX_SECTION
15334 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15336 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15337 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15339 #undef TARGET_BUILD_BUILTIN_VA_LIST
15340 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15342 #undef TARGET_CALLEE_COPIES
15343 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15345 #undef TARGET_CAN_ELIMINATE
15346 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15348 #undef TARGET_CAN_INLINE_P
15349 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15351 #undef TARGET_CANNOT_FORCE_CONST_MEM
15352 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15354 #undef TARGET_CASE_VALUES_THRESHOLD
15355 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15357 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15358 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15360 /* Only the least significant bit is used for initialization guard
15361 variables. */
15362 #undef TARGET_CXX_GUARD_MASK_BIT
15363 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15365 #undef TARGET_C_MODE_FOR_SUFFIX
15366 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15368 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15369 #undef TARGET_DEFAULT_TARGET_FLAGS
15370 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15371 #endif
15373 #undef TARGET_CLASS_MAX_NREGS
15374 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15376 #undef TARGET_BUILTIN_DECL
15377 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15379 #undef TARGET_BUILTIN_RECIPROCAL
15380 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15382 #undef TARGET_C_EXCESS_PRECISION
15383 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15385 #undef TARGET_EXPAND_BUILTIN
15386 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15388 #undef TARGET_EXPAND_BUILTIN_VA_START
15389 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15391 #undef TARGET_FOLD_BUILTIN
15392 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15394 #undef TARGET_FUNCTION_ARG
15395 #define TARGET_FUNCTION_ARG aarch64_function_arg
15397 #undef TARGET_FUNCTION_ARG_ADVANCE
15398 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15400 #undef TARGET_FUNCTION_ARG_BOUNDARY
15401 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15403 #undef TARGET_FUNCTION_ARG_PADDING
15404 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
15406 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15407 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15409 #undef TARGET_FUNCTION_VALUE
15410 #define TARGET_FUNCTION_VALUE aarch64_function_value
15412 #undef TARGET_FUNCTION_VALUE_REGNO_P
15413 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15415 #undef TARGET_FRAME_POINTER_REQUIRED
15416 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
15418 #undef TARGET_GIMPLE_FOLD_BUILTIN
15419 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15421 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15422 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15424 #undef TARGET_INIT_BUILTINS
15425 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15427 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15428 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15429 aarch64_ira_change_pseudo_allocno_class
15431 #undef TARGET_LEGITIMATE_ADDRESS_P
15432 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15434 #undef TARGET_LEGITIMATE_CONSTANT_P
15435 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15437 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15438 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15439 aarch64_legitimize_address_displacement
15441 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15442 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15444 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15445 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15446 aarch64_libgcc_floating_mode_supported_p
15448 #undef TARGET_MANGLE_TYPE
15449 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15451 #undef TARGET_MEMORY_MOVE_COST
15452 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15454 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15455 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15457 #undef TARGET_MUST_PASS_IN_STACK
15458 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15460 /* This target hook should return true if accesses to volatile bitfields
15461 should use the narrowest mode possible. It should return false if these
15462 accesses should use the bitfield container type. */
15463 #undef TARGET_NARROW_VOLATILE_BITFIELD
15464 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15466 #undef TARGET_OPTION_OVERRIDE
15467 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15469 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15470 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15471 aarch64_override_options_after_change
15473 #undef TARGET_OPTION_SAVE
15474 #define TARGET_OPTION_SAVE aarch64_option_save
15476 #undef TARGET_OPTION_RESTORE
15477 #define TARGET_OPTION_RESTORE aarch64_option_restore
15479 #undef TARGET_OPTION_PRINT
15480 #define TARGET_OPTION_PRINT aarch64_option_print
15482 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15483 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15485 #undef TARGET_SET_CURRENT_FUNCTION
15486 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15488 #undef TARGET_PASS_BY_REFERENCE
15489 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15491 #undef TARGET_PREFERRED_RELOAD_CLASS
15492 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15494 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15495 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15497 #undef TARGET_PROMOTED_TYPE
15498 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15500 #undef TARGET_SECONDARY_RELOAD
15501 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15503 #undef TARGET_SHIFT_TRUNCATION_MASK
15504 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15506 #undef TARGET_SETUP_INCOMING_VARARGS
15507 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15509 #undef TARGET_STRUCT_VALUE_RTX
15510 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15512 #undef TARGET_REGISTER_MOVE_COST
15513 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15515 #undef TARGET_RETURN_IN_MEMORY
15516 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15518 #undef TARGET_RETURN_IN_MSB
15519 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15521 #undef TARGET_RTX_COSTS
15522 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15524 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15525 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15527 #undef TARGET_SCHED_ISSUE_RATE
15528 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15530 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15531 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15532 aarch64_sched_first_cycle_multipass_dfa_lookahead
15534 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15535 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15536 aarch64_first_cycle_multipass_dfa_lookahead_guard
15538 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15539 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15540 aarch64_get_separate_components
15542 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15543 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15544 aarch64_components_for_bb
15546 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15547 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15548 aarch64_disqualify_components
15550 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15551 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15552 aarch64_emit_prologue_components
15554 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15555 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15556 aarch64_emit_epilogue_components
15558 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15559 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15560 aarch64_set_handled_components
15562 #undef TARGET_TRAMPOLINE_INIT
15563 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15565 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15566 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15568 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15569 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15571 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15572 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15573 aarch64_builtin_support_vector_misalignment
15575 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15576 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15578 #undef TARGET_VECTORIZE_ADD_STMT_COST
15579 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15581 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15582 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15583 aarch64_builtin_vectorization_cost
15585 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15586 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15588 #undef TARGET_VECTORIZE_BUILTINS
15589 #define TARGET_VECTORIZE_BUILTINS
15591 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15592 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15593 aarch64_builtin_vectorized_function
15595 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15596 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15597 aarch64_autovectorize_vector_sizes
15599 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15600 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15601 aarch64_atomic_assign_expand_fenv
15603 /* Section anchor support. */
15605 #undef TARGET_MIN_ANCHOR_OFFSET
15606 #define TARGET_MIN_ANCHOR_OFFSET -256
15608 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15609 byte offset; we can do much more for larger data types, but have no way
15610 to determine the size of the access. We assume accesses are aligned. */
15611 #undef TARGET_MAX_ANCHOR_OFFSET
15612 #define TARGET_MAX_ANCHOR_OFFSET 4095
15614 #undef TARGET_VECTOR_ALIGNMENT
15615 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15617 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15618 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15619 aarch64_simd_vector_alignment_reachable
15621 /* vec_perm support. */
15623 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15624 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15625 aarch64_vectorize_vec_perm_const_ok
15627 #undef TARGET_INIT_LIBFUNCS
15628 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15630 #undef TARGET_FIXED_CONDITION_CODE_REGS
15631 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15633 #undef TARGET_FLAGS_REGNUM
15634 #define TARGET_FLAGS_REGNUM CC_REGNUM
15636 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15637 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15639 #undef TARGET_ASAN_SHADOW_OFFSET
15640 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15642 #undef TARGET_LEGITIMIZE_ADDRESS
15643 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15645 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15646 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15647 aarch64_use_by_pieces_infrastructure_p
15649 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15650 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15652 #undef TARGET_CAN_USE_DOLOOP_P
15653 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15655 #undef TARGET_SCHED_ADJUST_PRIORITY
15656 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15658 #undef TARGET_SCHED_MACRO_FUSION_P
15659 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15661 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15662 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15664 #undef TARGET_SCHED_FUSION_PRIORITY
15665 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15667 #undef TARGET_UNSPEC_MAY_TRAP_P
15668 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15670 #undef TARGET_USE_PSEUDO_PIC_REG
15671 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15673 #undef TARGET_PRINT_OPERAND
15674 #define TARGET_PRINT_OPERAND aarch64_print_operand
15676 #undef TARGET_PRINT_OPERAND_ADDRESS
15677 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15679 #undef TARGET_OPTAB_SUPPORTED_P
15680 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15682 #undef TARGET_OMIT_STRUCT_RETURN_REG
15683 #define TARGET_OMIT_STRUCT_RETURN_REG true
15685 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15686 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15687 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15689 #undef TARGET_HARD_REGNO_MODE_OK
15690 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
15692 #undef TARGET_MODES_TIEABLE_P
15693 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
15695 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
15696 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
15697 aarch64_hard_regno_call_part_clobbered
15699 #if CHECKING_P
15700 #undef TARGET_RUN_TARGET_SELFTESTS
15701 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests