1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2016 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
125 #include "addresses.h"
128 #include "rtl-error.h"
132 #include "print-rtl.h"
134 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
135 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 static int bb_reload_num
;
139 /* The current insn being processed and corresponding its single set
140 (NULL otherwise), its data (basic block, the insn data, the insn
141 static data, and the mode of each operand). */
142 static rtx_insn
*curr_insn
;
143 static rtx curr_insn_set
;
144 static basic_block curr_bb
;
145 static lra_insn_recog_data_t curr_id
;
146 static struct lra_static_insn_data
*curr_static_id
;
147 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
148 /* Mode of the register substituted by its equivalence with VOIDmode
149 (e.g. constant) and whose subreg is given operand of the current
150 insn. VOIDmode in all other cases. */
151 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
155 /* Start numbers for new registers and insns at the current constraints
157 static int new_regno_start
;
158 static int new_insn_uid_start
;
160 /* If LOC is nonnull, strip any outer subreg from it. */
162 strip_subreg (rtx
*loc
)
164 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
167 /* Return hard regno of REGNO or if it is was not assigned to a hard
168 register, use a hard register from its allocno class. */
170 get_try_hard_regno (int regno
)
173 enum reg_class rclass
;
175 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
176 hard_regno
= lra_get_regno_hard_regno (regno
);
179 rclass
= lra_get_allocno_class (regno
);
180 if (rclass
== NO_REGS
)
182 return ira_class_hard_regs
[rclass
][0];
185 /* Return final hard regno (plus offset) which will be after
186 elimination. We do this for matching constraints because the final
187 hard regno could have a different class. */
189 get_final_hard_regno (int hard_regno
, int offset
)
193 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
194 return hard_regno
+ offset
;
197 /* Return hard regno of X after removing subreg and making
198 elimination. If X is not a register or subreg of register, return
199 -1. For pseudo use its assignment. */
201 get_hard_regno (rtx x
)
204 int offset
, hard_regno
;
207 if (GET_CODE (x
) == SUBREG
)
208 reg
= SUBREG_REG (x
);
211 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
212 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
216 if (GET_CODE (x
) == SUBREG
)
217 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
218 SUBREG_BYTE (x
), GET_MODE (x
));
219 return get_final_hard_regno (hard_regno
, offset
);
222 /* If REGNO is a hard register or has been allocated a hard register,
223 return the class of that register. If REGNO is a reload pseudo
224 created by the current constraints pass, return its allocno class.
225 Return NO_REGS otherwise. */
226 static enum reg_class
227 get_reg_class (int regno
)
231 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
232 hard_regno
= lra_get_regno_hard_regno (regno
);
235 hard_regno
= get_final_hard_regno (hard_regno
, 0);
236 return REGNO_REG_CLASS (hard_regno
);
238 if (regno
>= new_regno_start
)
239 return lra_get_allocno_class (regno
);
243 /* Return true if REG satisfies (or will satisfy) reg class constraint
244 CL. Use elimination first if REG is a hard register. If REG is a
245 reload pseudo created by this constraints pass, assume that it will
246 be allocated a hard register from its allocno class, but allow that
247 class to be narrowed to CL if it is currently a superset of CL.
249 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
250 REGNO (reg), or NO_REGS if no change in its class was needed. */
252 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
254 enum reg_class rclass
, common_class
;
255 machine_mode reg_mode
;
256 int class_size
, hard_regno
, nregs
, i
, j
;
257 int regno
= REGNO (reg
);
259 if (new_class
!= NULL
)
260 *new_class
= NO_REGS
;
261 if (regno
< FIRST_PSEUDO_REGISTER
)
264 rtx
*final_loc
= &final_reg
;
266 lra_eliminate_reg_if_possible (final_loc
);
267 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
269 reg_mode
= GET_MODE (reg
);
270 rclass
= get_reg_class (regno
);
271 if (regno
< new_regno_start
272 /* Do not allow the constraints for reload instructions to
273 influence the classes of new pseudos. These reloads are
274 typically moves that have many alternatives, and restricting
275 reload pseudos for one alternative may lead to situations
276 where other reload pseudos are no longer allocatable. */
277 || (INSN_UID (curr_insn
) >= new_insn_uid_start
278 && curr_insn_set
!= NULL
279 && ((OBJECT_P (SET_SRC (curr_insn_set
))
280 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
281 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
282 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
283 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
284 /* When we don't know what class will be used finally for reload
285 pseudos, we use ALL_REGS. */
286 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
287 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
288 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
289 lra_no_alloc_regs
)));
292 common_class
= ira_reg_class_subset
[rclass
][cl
];
293 if (new_class
!= NULL
)
294 *new_class
= common_class
;
295 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
298 /* Check that there are enough allocatable regs. */
299 class_size
= ira_class_hard_regs_num
[common_class
];
300 for (i
= 0; i
< class_size
; i
++)
302 hard_regno
= ira_class_hard_regs
[common_class
][i
];
303 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
306 for (j
= 0; j
< nregs
; j
++)
307 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
308 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
318 /* Return true if REGNO satisfies a memory constraint. */
322 return get_reg_class (regno
) == NO_REGS
;
325 /* Return 1 if ADDR is a valid memory address for mode MODE in address
326 space AS, and check that each pseudo has the proper kind of hard
329 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
330 rtx addr
, addr_space_t as
)
332 #ifdef GO_IF_LEGITIMATE_ADDRESS
333 lra_assert (ADDR_SPACE_GENERIC_P (as
));
334 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
340 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
345 /* Temporarily eliminates registers in an address (for the lifetime of
347 class address_eliminator
{
349 address_eliminator (struct address_info
*ad
);
350 ~address_eliminator ();
353 struct address_info
*m_ad
;
361 address_eliminator::address_eliminator (struct address_info
*ad
)
363 m_base_loc (strip_subreg (ad
->base_term
)),
364 m_base_reg (NULL_RTX
),
365 m_index_loc (strip_subreg (ad
->index_term
)),
366 m_index_reg (NULL_RTX
)
368 if (m_base_loc
!= NULL
)
370 m_base_reg
= *m_base_loc
;
371 lra_eliminate_reg_if_possible (m_base_loc
);
372 if (m_ad
->base_term2
!= NULL
)
373 *m_ad
->base_term2
= *m_ad
->base_term
;
375 if (m_index_loc
!= NULL
)
377 m_index_reg
= *m_index_loc
;
378 lra_eliminate_reg_if_possible (m_index_loc
);
382 address_eliminator::~address_eliminator ()
384 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
386 *m_base_loc
= m_base_reg
;
387 if (m_ad
->base_term2
!= NULL
)
388 *m_ad
->base_term2
= *m_ad
->base_term
;
390 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
391 *m_index_loc
= m_index_reg
;
394 /* Return true if the eliminated form of AD is a legitimate target address. */
396 valid_address_p (struct address_info
*ad
)
398 address_eliminator
eliminator (ad
);
399 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
402 /* Return true if the eliminated form of memory reference OP satisfies
403 extra (special) memory constraint CONSTRAINT. */
405 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
407 struct address_info ad
;
409 decompose_mem_address (&ad
, op
);
410 address_eliminator
eliminator (&ad
);
411 return constraint_satisfied_p (op
, constraint
);
414 /* Return true if the eliminated form of address AD satisfies extra
415 address constraint CONSTRAINT. */
417 satisfies_address_constraint_p (struct address_info
*ad
,
418 enum constraint_num constraint
)
420 address_eliminator
eliminator (ad
);
421 return constraint_satisfied_p (*ad
->outer
, constraint
);
424 /* Return true if the eliminated form of address OP satisfies extra
425 address constraint CONSTRAINT. */
427 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
429 struct address_info ad
;
431 decompose_lea_address (&ad
, &op
);
432 return satisfies_address_constraint_p (&ad
, constraint
);
435 /* Initiate equivalences for LRA. As we keep original equivalences
436 before any elimination, we need to make copies otherwise any change
437 in insns might change the equivalences. */
439 lra_init_equiv (void)
441 ira_expand_reg_equiv ();
442 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
446 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
447 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
448 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
449 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
453 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
455 /* Update equivalence for REGNO. We need to this as the equivalence
456 might contain other pseudos which are changed by their
459 update_equiv (int regno
)
463 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
464 ira_reg_equiv
[regno
].memory
465 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
467 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
468 ira_reg_equiv
[regno
].invariant
469 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
473 /* If we have decided to substitute X with another value, return that
474 value, otherwise return X. */
481 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
482 || ! ira_reg_equiv
[regno
].defined_p
483 || ! ira_reg_equiv
[regno
].profitable_p
484 || lra_get_regno_hard_regno (regno
) >= 0)
486 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
488 if (targetm
.cannot_substitute_mem_equiv_p (res
))
492 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
494 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
499 /* If we have decided to substitute X with the equivalent value,
500 return that value after elimination for INSN, otherwise return
503 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
505 rtx res
= get_equiv (x
);
507 if (x
== res
|| CONSTANT_P (res
))
509 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
510 false, false, 0, true);
513 /* Set up curr_operand_mode. */
515 init_curr_operand_mode (void)
517 int nop
= curr_static_id
->n_operands
;
518 for (int i
= 0; i
< nop
; i
++)
520 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
521 if (mode
== VOIDmode
)
523 /* The .md mode for address operands is the mode of the
524 addressed value rather than the mode of the address itself. */
525 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
528 mode
= curr_static_id
->operand
[i
].mode
;
530 curr_operand_mode
[i
] = mode
;
536 /* The page contains code to reuse input reloads. */
538 /* Structure describes input reload of the current insns. */
541 /* Reloaded value. */
543 /* Reload pseudo used. */
547 /* The number of elements in the following array. */
548 static int curr_insn_input_reloads_num
;
549 /* Array containing info about input reloads. It is used to find the
550 same input reload and reuse the reload pseudo in this case. */
551 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
553 /* Initiate data concerning reuse of input reloads for the current
556 init_curr_insn_input_reloads (void)
558 curr_insn_input_reloads_num
= 0;
561 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
562 created input reload pseudo (only if TYPE is not OP_OUT). Don't
563 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
564 wrapped up in SUBREG. The result pseudo is returned through
565 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
566 reused the already created input reload pseudo. Use TITLE to
567 describe new registers for debug purposes. */
569 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
570 enum reg_class rclass
, bool in_subreg_p
,
571 const char *title
, rtx
*result_reg
)
574 enum reg_class new_class
;
579 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
582 /* Prevent reuse value of expression with side effects,
583 e.g. volatile memory. */
584 if (! side_effects_p (original
))
585 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
586 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
587 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
589 rtx reg
= curr_insn_input_reloads
[i
].reg
;
591 /* If input is equal to original and both are VOIDmode,
592 GET_MODE (reg) might be still different from mode.
593 Ensure we don't return *result_reg with wrong mode. */
594 if (GET_MODE (reg
) != mode
)
598 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
600 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
601 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
605 if (lra_dump_file
!= NULL
)
607 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
608 dump_value_slim (lra_dump_file
, original
, 1);
610 if (new_class
!= lra_get_allocno_class (regno
))
611 lra_change_class (regno
, new_class
, ", change to", false);
612 if (lra_dump_file
!= NULL
)
613 fprintf (lra_dump_file
, "\n");
616 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
617 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
618 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
619 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
625 /* The page contains code to extract memory address parts. */
627 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
629 ok_for_index_p_nonstrict (rtx reg
)
631 unsigned regno
= REGNO (reg
);
633 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
636 /* A version of regno_ok_for_base_p for use here, when all pseudos
637 should count as OK. Arguments as for regno_ok_for_base_p. */
639 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
640 enum rtx_code outer_code
, enum rtx_code index_code
)
642 unsigned regno
= REGNO (reg
);
644 if (regno
>= FIRST_PSEUDO_REGISTER
)
646 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
651 /* The page contains major code to choose the current insn alternative
652 and generate reloads for it. */
654 /* Return the offset from REGNO of the least significant register
657 This function is used to tell whether two registers satisfy
658 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
660 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
661 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
663 lra_constraint_offset (int regno
, machine_mode mode
)
665 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
666 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
667 && SCALAR_INT_MODE_P (mode
))
668 return hard_regno_nregs
[regno
][mode
] - 1;
672 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
673 if they are the same hard reg, and has special hacks for
674 auto-increment and auto-decrement. This is specifically intended for
675 process_alt_operands to use in determining whether two operands
676 match. X is the operand whose number is the lower of the two.
678 It is supposed that X is the output operand and Y is the input
679 operand. Y_HARD_REGNO is the final hard regno of register Y or
680 register in subreg Y as we know it now. Otherwise, it is a
683 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
686 RTX_CODE code
= GET_CODE (x
);
691 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
692 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
696 i
= get_hard_regno (x
);
700 if ((j
= y_hard_regno
) < 0)
703 i
+= lra_constraint_offset (i
, GET_MODE (x
));
704 j
+= lra_constraint_offset (j
, GET_MODE (y
));
709 /* If two operands must match, because they are really a single
710 operand of an assembler insn, then two post-increments are invalid
711 because the assembler insn would increment only once. On the
712 other hand, a post-increment matches ordinary indexing if the
713 post-increment is the output operand. */
714 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
715 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
717 /* Two pre-increments are invalid because the assembler insn would
718 increment only once. On the other hand, a pre-increment matches
719 ordinary indexing if the pre-increment is the input operand. */
720 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
721 || GET_CODE (y
) == PRE_MODIFY
)
722 return operands_match_p (x
, XEXP (y
, 0), -1);
726 if (code
== REG
&& REG_P (y
))
727 return REGNO (x
) == REGNO (y
);
729 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
730 && x
== SUBREG_REG (y
))
732 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
733 && SUBREG_REG (x
) == y
)
736 /* Now we have disposed of all the cases in which different rtx
738 if (code
!= GET_CODE (y
))
741 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
742 if (GET_MODE (x
) != GET_MODE (y
))
751 return LABEL_REF_LABEL (x
) == LABEL_REF_LABEL (y
);
753 return XSTR (x
, 0) == XSTR (y
, 0);
759 /* Compare the elements. If any pair of corresponding elements fail
760 to match, return false for the whole things. */
762 fmt
= GET_RTX_FORMAT (code
);
763 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
769 if (XWINT (x
, i
) != XWINT (y
, i
))
774 if (XINT (x
, i
) != XINT (y
, i
))
779 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
788 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
790 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
792 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
798 /* It is believed that rtx's at this level will never
799 contain anything but integers and other rtx's, except for
800 within LABEL_REFs and SYMBOL_REFs. */
808 /* True if X is a constant that can be forced into the constant pool.
809 MODE is the mode of the operand, or VOIDmode if not known. */
810 #define CONST_POOL_OK_P(MODE, X) \
811 ((MODE) != VOIDmode \
813 && GET_CODE (X) != HIGH \
814 && !targetm.cannot_force_const_mem (MODE, X))
816 /* True if C is a non-empty register class that has too few registers
817 to be safely used as a reload target class. */
818 #define SMALL_REGISTER_CLASS_P(C) \
819 (ira_class_hard_regs_num [(C)] == 1 \
820 || (ira_class_hard_regs_num [(C)] >= 1 \
821 && targetm.class_likely_spilled_p (C)))
823 /* If REG is a reload pseudo, try to make its class satisfying CL. */
825 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
827 enum reg_class rclass
;
829 /* Do not make more accurate class from reloads generated. They are
830 mostly moves with a lot of constraints. Making more accurate
831 class may results in very narrow class and impossibility of find
832 registers for several reloads of one insn. */
833 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
835 if (GET_CODE (reg
) == SUBREG
)
836 reg
= SUBREG_REG (reg
);
837 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
839 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
840 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
843 /* Searches X for any reference to a reg with the same value as REGNO,
844 returning the rtx of the reference found if any. Otherwise,
847 regno_val_use_in (unsigned int regno
, rtx x
)
853 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
856 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
857 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
861 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
864 else if (fmt
[i
] == 'E')
865 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
866 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
873 /* Generate reloads for matching OUT and INS (array of input operand
874 numbers with end marker -1) with reg class GOAL_CLASS. Add input
875 and output reloads correspondingly to the lists *BEFORE and *AFTER.
876 OUT might be negative. In this case we generate input reloads for
877 matched input operands INS. EARLY_CLOBBER_P is a flag that the
878 output operand is early clobbered for chosen alternative. */
880 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
881 rtx_insn
**before
, rtx_insn
**after
, bool early_clobber_p
)
884 rtx new_in_reg
, new_out_reg
, reg
;
885 machine_mode inmode
, outmode
;
886 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
887 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
889 inmode
= curr_operand_mode
[ins
[0]];
890 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
891 push_to_sequence (*before
);
892 if (inmode
!= outmode
)
894 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
897 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
899 if (SCALAR_INT_MODE_P (inmode
))
900 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
902 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
903 LRA_SUBREG_P (new_out_reg
) = 1;
904 /* If the input reg is dying here, we can use the same hard
905 register for REG and IN_RTX. We do it only for original
906 pseudos as reload pseudos can die although original
907 pseudos still live where reload pseudos dies. */
908 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
909 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
910 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
915 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
917 if (SCALAR_INT_MODE_P (outmode
))
918 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
920 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
921 /* NEW_IN_REG is non-paradoxical subreg. We don't want
922 NEW_OUT_REG living above. We add clobber clause for
923 this. This is just a temporary clobber. We can remove
924 it at the end of LRA work. */
925 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
926 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
927 LRA_SUBREG_P (new_in_reg
) = 1;
928 if (GET_CODE (in_rtx
) == SUBREG
)
930 rtx subreg_reg
= SUBREG_REG (in_rtx
);
932 /* If SUBREG_REG is dying here and sub-registers IN_RTX
933 and NEW_IN_REG are similar, we can use the same hard
934 register for REG and SUBREG_REG. */
935 if (REG_P (subreg_reg
)
936 && (int) REGNO (subreg_reg
) < lra_new_regno_start
937 && GET_MODE (subreg_reg
) == outmode
938 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
939 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
940 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
946 /* Pseudos have values -- see comments for lra_reg_info.
947 Different pseudos with the same value do not conflict even if
948 they live in the same place. When we create a pseudo we
949 assign value of original pseudo (if any) from which we
950 created the new pseudo. If we create the pseudo from the
951 input pseudo, the new pseudo will have no conflict with the
952 input pseudo which is wrong when the input pseudo lives after
953 the insn and as the new pseudo value is changed by the insn
954 output. Therefore we create the new pseudo from the output
955 except the case when we have single matched dying input
958 We cannot reuse the current output register because we might
959 have a situation like "a <- a op b", where the constraints
960 force the second input operand ("b") to match the output
961 operand ("a"). "b" must then be copied into a new register
962 so that it doesn't clobber the current value of "a".
964 We can not use the same value if the output pseudo is
965 early clobbered or the input pseudo is mentioned in the
966 output, e.g. as an address part in memory, because
967 output reload will actually extend the pseudo liveness.
968 We don't care about eliminable hard regs here as we are
969 interesting only in pseudos. */
971 new_in_reg
= new_out_reg
972 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
973 && (int) REGNO (in_rtx
) < lra_new_regno_start
974 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
976 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
977 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
978 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
981 /* In operand can be got from transformations before processing insn
982 constraints. One example of such transformations is subreg
983 reloading (see function simplify_operand_subreg). The new
984 pseudos created by the transformations might have inaccurate
985 class (ALL_REGS) and we should make their classes more
987 narrow_reload_pseudo_class (in_rtx
, goal_class
);
988 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
989 *before
= get_insns ();
991 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
994 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
995 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
996 *curr_id
->operand_loc
[in
] = new_in_reg
;
998 lra_update_dups (curr_id
, ins
);
1001 /* See a comment for the input operand above. */
1002 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1003 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1006 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1008 *after
= get_insns ();
1011 *curr_id
->operand_loc
[out
] = new_out_reg
;
1012 lra_update_dup (curr_id
, out
);
1015 /* Return register class which is union of all reg classes in insn
1016 constraint alternative string starting with P. */
1017 static enum reg_class
1018 reg_class_from_constraints (const char *p
)
1021 enum reg_class op_class
= NO_REGS
;
1024 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1031 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1035 enum constraint_num cn
= lookup_constraint (p
);
1036 enum reg_class cl
= reg_class_for_constraint (cn
);
1039 if (insn_extra_address_constraint (cn
))
1041 = (reg_class_subunion
1042 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1043 ADDRESS
, SCRATCH
)]);
1047 op_class
= reg_class_subunion
[op_class
][cl
];
1050 while ((p
+= len
), c
);
1054 /* If OP is a register, return the class of the register as per
1055 get_reg_class, otherwise return NO_REGS. */
1056 static inline enum reg_class
1057 get_op_class (rtx op
)
1059 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1062 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1063 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1064 SUBREG for VAL to make them equal. */
1066 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1068 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1070 /* Usually size of mem_pseudo is greater than val size but in
1071 rare cases it can be less as it can be defined by target
1072 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1075 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1076 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1078 LRA_SUBREG_P (val
) = 1;
1082 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1083 LRA_SUBREG_P (mem_pseudo
) = 1;
1086 return to_p
? gen_move_insn (mem_pseudo
, val
)
1087 : gen_move_insn (val
, mem_pseudo
);
1090 /* Process a special case insn (register move), return true if we
1091 don't need to process it anymore. INSN should be a single set
1092 insn. Set up that RTL was changed through CHANGE_P and macro
1093 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1096 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1099 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1101 enum reg_class dclass
, sclass
, secondary_class
;
1102 secondary_reload_info sri
;
1104 lra_assert (curr_insn_set
!= NULL_RTX
);
1105 dreg
= dest
= SET_DEST (curr_insn_set
);
1106 sreg
= src
= SET_SRC (curr_insn_set
);
1107 if (GET_CODE (dest
) == SUBREG
)
1108 dreg
= SUBREG_REG (dest
);
1109 if (GET_CODE (src
) == SUBREG
)
1110 sreg
= SUBREG_REG (src
);
1111 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1113 sclass
= dclass
= NO_REGS
;
1115 dclass
= get_reg_class (REGNO (dreg
));
1116 if (dclass
== ALL_REGS
)
1117 /* ALL_REGS is used for new pseudos created by transformations
1118 like reload of SUBREG_REG (see function
1119 simplify_operand_subreg). We don't know their class yet. We
1120 should figure out the class from processing the insn
1121 constraints not in this fast path function. Even if ALL_REGS
1122 were a right class for the pseudo, secondary_... hooks usually
1123 are not define for ALL_REGS. */
1126 sclass
= get_reg_class (REGNO (sreg
));
1127 if (sclass
== ALL_REGS
)
1128 /* See comments above. */
1130 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1132 #ifdef SECONDARY_MEMORY_NEEDED
1133 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1134 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1135 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1136 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1144 if (! REG_P (dreg
) || ! REG_P (sreg
))
1146 sri
.prev_sri
= NULL
;
1147 sri
.icode
= CODE_FOR_nothing
;
1149 secondary_class
= NO_REGS
;
1150 /* Set up hard register for a reload pseudo for hook
1151 secondary_reload because some targets just ignore unassigned
1152 pseudos in the hook. */
1153 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1155 dregno
= REGNO (dreg
);
1156 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1160 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1162 sregno
= REGNO (sreg
);
1163 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1167 if (sclass
!= NO_REGS
)
1169 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1170 (reg_class_t
) sclass
,
1171 GET_MODE (src
), &sri
);
1172 if (sclass
== NO_REGS
1173 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1174 && dclass
!= NO_REGS
))
1176 enum reg_class old_sclass
= secondary_class
;
1177 secondary_reload_info old_sri
= sri
;
1179 sri
.prev_sri
= NULL
;
1180 sri
.icode
= CODE_FOR_nothing
;
1183 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1184 (reg_class_t
) dclass
,
1185 GET_MODE (src
), &sri
);
1186 /* Check the target hook consistency. */
1188 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1189 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1190 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1193 reg_renumber
[sregno
] = -1;
1195 reg_renumber
[dregno
] = -1;
1196 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1200 if (secondary_class
!= NO_REGS
)
1201 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1205 if (sri
.icode
== CODE_FOR_nothing
)
1206 lra_emit_move (new_reg
, src
);
1209 enum reg_class scratch_class
;
1211 scratch_class
= (reg_class_from_constraints
1212 (insn_data
[sri
.icode
].operand
[2].constraint
));
1213 scratch_reg
= (lra_create_new_reg_with_unique_value
1214 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1215 scratch_class
, "scratch"));
1216 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1219 before
= get_insns ();
1221 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1222 if (new_reg
!= NULL_RTX
)
1223 SET_SRC (curr_insn_set
) = new_reg
;
1226 if (lra_dump_file
!= NULL
)
1228 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1229 dump_insn_slim (lra_dump_file
, curr_insn
);
1231 lra_set_insn_deleted (curr_insn
);
1237 /* The following data describe the result of process_alt_operands.
1238 The data are used in curr_insn_transform to generate reloads. */
1240 /* The chosen reg classes which should be used for the corresponding
1242 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1243 /* True if the operand should be the same as another operand and that
1244 other operand does not need a reload. */
1245 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1246 /* True if the operand does not need a reload. */
1247 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1248 /* True if the operand can be offsetable memory. */
1249 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1250 /* The number of an operand to which given operand can be matched to. */
1251 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1252 /* The number of elements in the following array. */
1253 static int goal_alt_dont_inherit_ops_num
;
1254 /* Numbers of operands whose reload pseudos should not be inherited. */
1255 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1256 /* True if the insn commutative operands should be swapped. */
1257 static bool goal_alt_swapped
;
1258 /* The chosen insn alternative. */
1259 static int goal_alt_number
;
1261 /* The following five variables are used to choose the best insn
1262 alternative. They reflect final characteristics of the best
1265 /* Number of necessary reloads and overall cost reflecting the
1266 previous value and other unpleasantness of the best alternative. */
1267 static int best_losers
, best_overall
;
1268 /* Overall number hard registers used for reloads. For example, on
1269 some targets we need 2 general registers to reload DFmode and only
1270 one floating point register. */
1271 static int best_reload_nregs
;
1272 /* Overall number reflecting distances of previous reloading the same
1273 value. The distances are counted from the current BB start. It is
1274 used to improve inheritance chances. */
1275 static int best_reload_sum
;
1277 /* True if the current insn should have no correspondingly input or
1279 static bool no_input_reloads_p
, no_output_reloads_p
;
1281 /* True if we swapped the commutative operands in the current
1283 static int curr_swapped
;
1285 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1286 register of class CL. Add any input reloads to list BEFORE. AFTER
1287 is nonnull if *LOC is an automodified value; handle that case by
1288 adding the required output reloads to list AFTER. Return true if
1289 the RTL was changed.
1291 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1292 register. Return false if the address register is correct. */
1294 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1298 enum reg_class rclass
, new_class
;
1302 bool subreg_p
, before_p
= false;
1304 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1306 loc
= &SUBREG_REG (*loc
);
1308 mode
= GET_MODE (reg
);
1313 /* Always reload memory in an address even if the target supports
1315 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1320 regno
= REGNO (reg
);
1321 rclass
= get_reg_class (regno
);
1323 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1325 if (lra_dump_file
!= NULL
)
1327 fprintf (lra_dump_file
,
1328 "Changing pseudo %d in address of insn %u on equiv ",
1329 REGNO (reg
), INSN_UID (curr_insn
));
1330 dump_value_slim (lra_dump_file
, *loc
, 1);
1331 fprintf (lra_dump_file
, "\n");
1333 *loc
= copy_rtx (*loc
);
1335 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1340 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1341 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1344 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1348 lra_change_class (regno
, new_class
, " Change to", true);
1356 push_to_sequence (*before
);
1357 lra_emit_move (new_reg
, reg
);
1358 *before
= get_insns ();
1365 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1367 *after
= get_insns ();
1373 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1374 the insn to be inserted before curr insn. AFTER returns the
1375 the insn to be inserted after curr insn. ORIGREG and NEWREG
1376 are the original reg and new reg for reload. */
1378 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1383 push_to_sequence (*before
);
1384 lra_emit_move (newreg
, origreg
);
1385 *before
= get_insns ();
1391 lra_emit_move (origreg
, newreg
);
1393 *after
= get_insns ();
1398 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1400 /* Make reloads for subreg in operand NOP with internal subreg mode
1401 REG_MODE, add new reloads for further processing. Return true if
1402 any change was done. */
1404 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1407 rtx_insn
*before
, *after
;
1408 machine_mode mode
, innermode
;
1410 rtx operand
= *curr_id
->operand_loc
[nop
];
1411 enum reg_class regclass
;
1414 before
= after
= NULL
;
1416 if (GET_CODE (operand
) != SUBREG
)
1419 mode
= GET_MODE (operand
);
1420 reg
= SUBREG_REG (operand
);
1421 innermode
= GET_MODE (reg
);
1422 type
= curr_static_id
->operand
[nop
].type
;
1423 /* If we change address for paradoxical subreg of memory, the
1424 address might violate the necessary alignment or the access might
1425 be slow. So take this into consideration. We should not worry
1426 about access beyond allocated memory for paradoxical memory
1427 subregs as we don't substitute such equiv memory (see processing
1428 equivalences in function lra_constraints) and because for spilled
1429 pseudos we allocate stack memory enough for the biggest
1430 corresponding paradoxical subreg. */
1432 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1433 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1435 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1437 alter_subreg (curr_id
->operand_loc
[nop
], false);
1438 subst
= *curr_id
->operand_loc
[nop
];
1439 lra_assert (MEM_P (subst
));
1440 if (! valid_address_p (innermode
, XEXP (reg
, 0),
1441 MEM_ADDR_SPACE (reg
))
1442 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1443 MEM_ADDR_SPACE (subst
)))
1445 else if ((get_constraint_type (lookup_constraint
1446 (curr_static_id
->operand
[nop
].constraint
))
1447 != CT_SPECIAL_MEMORY
)
1448 /* We still can reload address and if the address is
1449 valid, we can remove subreg without reloading its
1451 && valid_address_p (GET_MODE (subst
),
1453 [ira_class_hard_regs
1454 [base_reg_class (GET_MODE (subst
),
1455 MEM_ADDR_SPACE (subst
),
1456 ADDRESS
, SCRATCH
)][0]],
1457 MEM_ADDR_SPACE (subst
)))
1460 /* If the address was valid and became invalid, prefer to reload
1461 the memory. Typical case is when the index scale should
1462 correspond the memory. */
1463 *curr_id
->operand_loc
[nop
] = old
;
1465 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1467 alter_subreg (curr_id
->operand_loc
[nop
], false);
1470 else if (CONSTANT_P (reg
))
1472 /* Try to simplify subreg of constant. It is usually result of
1473 equivalence substitution. */
1474 if (innermode
== VOIDmode
1475 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1476 innermode
= curr_static_id
->operand
[nop
].mode
;
1477 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1478 SUBREG_BYTE (operand
))) != NULL_RTX
)
1480 *curr_id
->operand_loc
[nop
] = new_reg
;
1484 /* Put constant into memory when we have mixed modes. It generates
1485 a better code in most cases as it does not need a secondary
1486 reload memory. It also prevents LRA looping when LRA is using
1487 secondary reload memory again and again. */
1488 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1489 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1491 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1492 alter_subreg (curr_id
->operand_loc
[nop
], false);
1495 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1496 if there may be a problem accessing OPERAND in the outer
1499 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1500 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1501 /* Don't reload paradoxical subregs because we could be looping
1502 having repeatedly final regno out of hard regs range. */
1503 && (hard_regno_nregs
[hard_regno
][innermode
]
1504 >= hard_regno_nregs
[hard_regno
][mode
])
1505 && simplify_subreg_regno (hard_regno
, innermode
,
1506 SUBREG_BYTE (operand
), mode
) < 0
1507 /* Don't reload subreg for matching reload. It is actually
1508 valid subreg in LRA. */
1509 && ! LRA_SUBREG_P (operand
))
1510 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1512 enum reg_class rclass
;
1515 /* There is a big probability that we will get the same class
1516 for the new pseudo and we will get the same insn which
1517 means infinite looping. So spill the new pseudo. */
1520 /* The class will be defined later in curr_insn_transform. */
1522 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1524 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1525 rclass
, TRUE
, "subreg reg", &new_reg
))
1527 bool insert_before
, insert_after
;
1528 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1530 insert_before
= (type
!= OP_OUT
1531 || GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (mode
));
1532 insert_after
= (type
!= OP_IN
);
1533 insert_move_for_subreg (insert_before
? &before
: NULL
,
1534 insert_after
? &after
: NULL
,
1537 SUBREG_REG (operand
) = new_reg
;
1538 lra_process_new_insns (curr_insn
, before
, after
,
1539 "Inserting subreg reload");
1542 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1543 IRA allocates hardreg to the inner pseudo reg according to its mode
1544 instead of the outermode, so the size of the hardreg may not be enough
1545 to contain the outermode operand, in that case we may need to insert
1546 reload for the reg. For the following two types of paradoxical subreg,
1547 we need to insert reload:
1548 1. If the op_type is OP_IN, and the hardreg could not be paired with
1549 other hardreg to contain the outermode operand
1550 (checked by in_hard_reg_set_p), we need to insert the reload.
1551 2. If the op_type is OP_OUT or OP_INOUT.
1553 Here is a paradoxical subreg example showing how the reload is generated:
1555 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1556 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1558 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1559 here, if reg107 is assigned to hardreg R15, because R15 is the last
1560 hardreg, compiler cannot find another hardreg to pair with R15 to
1561 contain TImode data. So we insert a TImode reload reg180 for it.
1562 After reload is inserted:
1564 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1565 (reg:DI 107 [ __comp ])) -1
1566 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1567 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1569 Two reload hard registers will be allocated to reg180 to save TImode data
1571 else if (REG_P (reg
)
1572 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1573 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1574 && (hard_regno_nregs
[hard_regno
][innermode
]
1575 < hard_regno_nregs
[hard_regno
][mode
])
1576 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1578 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1581 /* The class will be defined later in curr_insn_transform. */
1582 enum reg_class rclass
1583 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1585 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1586 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1589 bool insert_before
, insert_after
;
1591 PUT_MODE (new_reg
, mode
);
1592 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1593 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1595 insert_before
= (type
!= OP_OUT
);
1596 insert_after
= (type
!= OP_IN
);
1597 insert_move_for_subreg (insert_before
? &before
: NULL
,
1598 insert_after
? &after
: NULL
,
1601 SUBREG_REG (operand
) = new_reg
;
1602 lra_process_new_insns (curr_insn
, before
, after
,
1603 "Inserting paradoxical subreg reload");
1609 /* Return TRUE if X refers for a hard register from SET. */
1611 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1613 int i
, j
, x_hard_regno
;
1620 code
= GET_CODE (x
);
1621 mode
= GET_MODE (x
);
1625 code
= GET_CODE (x
);
1626 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1627 mode
= GET_MODE (x
);
1632 x_hard_regno
= get_hard_regno (x
);
1633 return (x_hard_regno
>= 0
1634 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1638 struct address_info ad
;
1640 decompose_mem_address (&ad
, x
);
1641 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1643 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1646 fmt
= GET_RTX_FORMAT (code
);
1647 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1651 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1654 else if (fmt
[i
] == 'E')
1656 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1657 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1664 /* Return true if OP is a spilled pseudo. */
1666 spilled_pseudo_p (rtx op
)
1669 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1672 /* Return true if X is a general constant. */
1674 general_constant_p (rtx x
)
1676 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1680 reg_in_class_p (rtx reg
, enum reg_class cl
)
1683 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1684 return in_class_p (reg
, cl
, NULL
);
1687 /* Return true if SET of RCLASS contains no hard regs which can be
1690 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1692 enum machine_mode mode
)
1696 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1697 COPY_HARD_REG_SET (temp
, set
);
1698 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1699 return (hard_reg_set_subset_p
1700 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1703 /* Major function to choose the current insn alternative and what
1704 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1705 negative we should consider only this alternative. Return false if
1706 we can not choose the alternative or find how to reload the
1709 process_alt_operands (int only_alternative
)
1712 int nop
, overall
, nalt
;
1713 int n_alternatives
= curr_static_id
->n_alternatives
;
1714 int n_operands
= curr_static_id
->n_operands
;
1715 /* LOSERS counts the operands that don't fit this alternative and
1716 would require loading. */
1718 /* REJECT is a count of how undesirable this alternative says it is
1719 if any reloading is required. If the alternative matches exactly
1720 then REJECT is ignored, but otherwise it gets this much counted
1721 against it in addition to the reloading needed. */
1724 /* The number of elements in the following array. */
1725 int early_clobbered_regs_num
;
1726 /* Numbers of operands which are early clobber registers. */
1727 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1728 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1729 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1730 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1731 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1732 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1733 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1734 /* The number of elements in the following array. */
1735 int curr_alt_dont_inherit_ops_num
;
1736 /* Numbers of operands whose reload pseudos should not be inherited. */
1737 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1739 /* The register when the operand is a subreg of register, otherwise the
1741 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1742 /* The register if the operand is a register or subreg of register,
1744 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1745 int hard_regno
[MAX_RECOG_OPERANDS
];
1746 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1747 int reload_nregs
, reload_sum
;
1751 /* Calculate some data common for all alternatives to speed up the
1753 for (nop
= 0; nop
< n_operands
; nop
++)
1757 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1758 /* The real hard regno of the operand after the allocation. */
1759 hard_regno
[nop
] = get_hard_regno (op
);
1761 operand_reg
[nop
] = reg
= op
;
1762 biggest_mode
[nop
] = GET_MODE (op
);
1763 if (GET_CODE (op
) == SUBREG
)
1765 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1766 if (GET_MODE_SIZE (biggest_mode
[nop
])
1767 < GET_MODE_SIZE (GET_MODE (reg
)))
1768 biggest_mode
[nop
] = GET_MODE (reg
);
1771 operand_reg
[nop
] = NULL_RTX
;
1772 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1773 || ((int) REGNO (reg
)
1774 == lra_get_elimination_hard_regno (REGNO (reg
))))
1775 no_subreg_reg_operand
[nop
] = reg
;
1777 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1778 /* Just use natural mode for elimination result. It should
1779 be enough for extra constraints hooks. */
1780 = regno_reg_rtx
[hard_regno
[nop
]];
1783 /* The constraints are made of several alternatives. Each operand's
1784 constraint looks like foo,bar,... with commas separating the
1785 alternatives. The first alternatives for all operands go
1786 together, the second alternatives go together, etc.
1788 First loop over alternatives. */
1789 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1790 if (only_alternative
>= 0)
1791 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1793 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1795 /* Loop over operands for one constraint alternative. */
1796 if (!TEST_BIT (preferred
, nalt
))
1799 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1800 for (nop
= 0; nop
< n_operands
; nop
++)
1802 int inc
= (curr_static_id
1803 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1804 if (lra_dump_file
!= NULL
&& inc
!= 0)
1805 fprintf (lra_dump_file
,
1806 " Staticly defined alt reject+=%d\n", inc
);
1809 early_clobbered_regs_num
= 0;
1811 for (nop
= 0; nop
< n_operands
; nop
++)
1815 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1816 bool win
, did_match
, offmemok
, early_clobber_p
;
1817 /* false => this operand can be reloaded somehow for this
1820 /* true => this operand can be reloaded if the alternative
1823 /* True if a constant forced into memory would be OK for
1826 enum reg_class this_alternative
, this_costly_alternative
;
1827 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1828 bool this_alternative_match_win
, this_alternative_win
;
1829 bool this_alternative_offmemok
;
1832 enum constraint_num cn
;
1834 opalt_num
= nalt
* n_operands
+ nop
;
1835 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1837 /* Fast track for no constraints at all. */
1838 curr_alt
[nop
] = NO_REGS
;
1839 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1840 curr_alt_win
[nop
] = true;
1841 curr_alt_match_win
[nop
] = false;
1842 curr_alt_offmemok
[nop
] = false;
1843 curr_alt_matches
[nop
] = -1;
1847 op
= no_subreg_reg_operand
[nop
];
1848 mode
= curr_operand_mode
[nop
];
1850 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1853 early_clobber_p
= false;
1854 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1856 this_costly_alternative
= this_alternative
= NO_REGS
;
1857 /* We update set of possible hard regs besides its class
1858 because reg class might be inaccurate. For example,
1859 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1860 is translated in HI_REGS because classes are merged by
1861 pairs and there is no accurate intermediate class. */
1862 CLEAR_HARD_REG_SET (this_alternative_set
);
1863 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1864 this_alternative_win
= false;
1865 this_alternative_match_win
= false;
1866 this_alternative_offmemok
= false;
1867 this_alternative_matches
= -1;
1869 /* An empty constraint should be excluded by the fast
1871 lra_assert (*p
!= 0 && *p
!= ',');
1874 /* Scan this alternative's specs for this operand; set WIN
1875 if the operand fits any letter in this alternative.
1876 Otherwise, clear BADOP if this operand could fit some
1877 letter after reloads, or set WINREG if this operand could
1878 fit after reloads provided the constraint allows some
1883 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1893 early_clobber_p
= true;
1897 op_reject
+= LRA_MAX_REJECT
;
1900 op_reject
+= LRA_LOSER_COST_FACTOR
;
1904 /* Ignore rest of this alternative. */
1908 case '0': case '1': case '2': case '3': case '4':
1909 case '5': case '6': case '7': case '8': case '9':
1914 m
= strtoul (p
, &end
, 10);
1917 lra_assert (nop
> m
);
1919 this_alternative_matches
= m
;
1920 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1921 /* We are supposed to match a previous operand.
1922 If we do, we win if that one did. If we do
1923 not, count both of the operands as losers.
1924 (This is too conservative, since most of the
1925 time only a single reload insn will be needed
1926 to make the two operands win. As a result,
1927 this alternative may be rejected when it is
1928 actually desirable.) */
1930 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1931 *curr_id
->operand_loc
[m
], m_hregno
))
1933 /* We should reject matching of an early
1934 clobber operand if the matching operand is
1935 not dying in the insn. */
1936 if (! curr_static_id
->operand
[m
].early_clobber
1937 || operand_reg
[nop
] == NULL_RTX
1938 || (find_regno_note (curr_insn
, REG_DEAD
,
1940 || REGNO (op
) == REGNO (operand_reg
[m
])))
1945 /* If we are matching a non-offsettable
1946 address where an offsettable address was
1947 expected, then we must reject this
1948 combination, because we can't reload
1950 if (curr_alt_offmemok
[m
]
1951 && MEM_P (*curr_id
->operand_loc
[m
])
1952 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1957 /* Operands don't match. Both operands must
1958 allow a reload register, otherwise we
1959 cannot make them match. */
1960 if (curr_alt
[m
] == NO_REGS
)
1962 /* Retroactively mark the operand we had to
1963 match as a loser, if it wasn't already and
1964 it wasn't matched to a register constraint
1965 (e.g it might be matched by memory). */
1967 && (operand_reg
[m
] == NULL_RTX
1968 || hard_regno
[m
] < 0))
1972 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1973 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1976 /* Prefer matching earlyclobber alternative as
1977 it results in less hard regs required for
1978 the insn than a non-matching earlyclobber
1980 if (curr_static_id
->operand
[m
].early_clobber
)
1982 if (lra_dump_file
!= NULL
)
1985 " %d Matching earlyclobber alt:"
1990 /* Otherwise we prefer no matching
1991 alternatives because it gives more freedom
1993 else if (operand_reg
[nop
] == NULL_RTX
1994 || (find_regno_note (curr_insn
, REG_DEAD
,
1995 REGNO (operand_reg
[nop
]))
1998 if (lra_dump_file
!= NULL
)
2001 " %d Matching alt: reject+=2\n",
2006 /* If we have to reload this operand and some
2007 previous operand also had to match the same
2008 thing as this operand, we don't know how to do
2010 if (!match_p
|| !curr_alt_win
[m
])
2012 for (i
= 0; i
< nop
; i
++)
2013 if (curr_alt_matches
[i
] == m
)
2021 /* This can be fixed with reloads if the operand
2022 we are supposed to match can be fixed with
2025 this_alternative
= curr_alt
[m
];
2026 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2027 winreg
= this_alternative
!= NO_REGS
;
2033 || general_constant_p (op
)
2034 || spilled_pseudo_p (op
))
2040 cn
= lookup_constraint (p
);
2041 switch (get_constraint_type (cn
))
2044 cl
= reg_class_for_constraint (cn
);
2050 if (CONST_INT_P (op
)
2051 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2057 && satisfies_memory_constraint_p (op
, cn
))
2059 else if (spilled_pseudo_p (op
))
2062 /* If we didn't already win, we can reload constants
2063 via force_const_mem or put the pseudo value into
2064 memory, or make other memory by reloading the
2065 address like for 'o'. */
2066 if (CONST_POOL_OK_P (mode
, op
)
2067 || MEM_P (op
) || REG_P (op
))
2074 /* If we didn't already win, we can reload the address
2075 into a base register. */
2076 if (satisfies_address_constraint_p (op
, cn
))
2078 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2084 if (constraint_satisfied_p (op
, cn
))
2088 case CT_SPECIAL_MEMORY
:
2090 && satisfies_memory_constraint_p (op
, cn
))
2092 else if (spilled_pseudo_p (op
))
2099 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2100 IOR_HARD_REG_SET (this_alternative_set
,
2101 reg_class_contents
[cl
]);
2104 this_costly_alternative
2105 = reg_class_subunion
[this_costly_alternative
][cl
];
2106 IOR_HARD_REG_SET (this_costly_alternative_set
,
2107 reg_class_contents
[cl
]);
2109 if (mode
== BLKmode
)
2114 if (hard_regno
[nop
] >= 0
2115 && in_hard_reg_set_p (this_alternative_set
,
2116 mode
, hard_regno
[nop
]))
2118 else if (hard_regno
[nop
] < 0
2119 && in_class_p (op
, this_alternative
, NULL
))
2124 if (c
!= ' ' && c
!= '\t')
2125 costly_p
= c
== '*';
2127 while ((p
+= len
), c
);
2129 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2130 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2131 /* Record which operands fit this alternative. */
2134 this_alternative_win
= true;
2135 if (operand_reg
[nop
] != NULL_RTX
)
2137 if (hard_regno
[nop
] >= 0)
2139 if (in_hard_reg_set_p (this_costly_alternative_set
,
2140 mode
, hard_regno
[nop
]))
2142 if (lra_dump_file
!= NULL
)
2143 fprintf (lra_dump_file
,
2144 " %d Costly set: reject++\n",
2151 /* Prefer won reg to spilled pseudo under other
2152 equal conditions for possibe inheritance. */
2155 if (lra_dump_file
!= NULL
)
2158 " %d Non pseudo reload: reject++\n",
2162 if (in_class_p (operand_reg
[nop
],
2163 this_costly_alternative
, NULL
))
2165 if (lra_dump_file
!= NULL
)
2168 " %d Non pseudo costly reload:"
2174 /* We simulate the behavior of old reload here.
2175 Although scratches need hard registers and it
2176 might result in spilling other pseudos, no reload
2177 insns are generated for the scratches. So it
2178 might cost something but probably less than old
2179 reload pass believes. */
2182 if (lra_dump_file
!= NULL
)
2183 fprintf (lra_dump_file
,
2184 " %d Scratch win: reject+=2\n",
2191 this_alternative_match_win
= true;
2194 int const_to_mem
= 0;
2197 reject
+= op_reject
;
2198 /* Never do output reload of stack pointer. It makes
2199 impossible to do elimination when SP is changed in
2201 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2202 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2205 /* If this alternative asks for a specific reg class, see if there
2206 is at least one allocatable register in that class. */
2208 = (this_alternative
== NO_REGS
2209 || (hard_reg_set_subset_p
2210 (reg_class_contents
[this_alternative
],
2211 lra_no_alloc_regs
)));
2213 /* For asms, verify that the class for this alternative is possible
2214 for the mode that is specified. */
2215 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2218 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2219 if (HARD_REGNO_MODE_OK (i
, mode
)
2220 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2223 if (i
== FIRST_PSEUDO_REGISTER
)
2227 /* If this operand accepts a register, and if the
2228 register class has at least one allocatable register,
2229 then this operand can be reloaded. */
2230 if (winreg
&& !no_regs_p
)
2235 if (lra_dump_file
!= NULL
)
2236 fprintf (lra_dump_file
,
2237 " alt=%d: Bad operand -- refuse\n",
2242 /* If not assigned pseudo has a class which a subset of
2243 required reg class, it is a less costly alternative
2244 as the pseudo still can get a hard reg of necessary
2246 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2247 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2248 && ira_class_subset_p
[this_alternative
][cl
])
2250 if (lra_dump_file
!= NULL
)
2253 " %d Super set class reg: reject-=3\n", nop
);
2257 this_alternative_offmemok
= offmemok
;
2258 if (this_costly_alternative
!= NO_REGS
)
2260 if (lra_dump_file
!= NULL
)
2261 fprintf (lra_dump_file
,
2262 " %d Costly loser: reject++\n", nop
);
2265 /* If the operand is dying, has a matching constraint,
2266 and satisfies constraints of the matched operand
2267 which failed to satisfy the own constraints, most probably
2268 the reload for this operand will be gone. */
2269 if (this_alternative_matches
>= 0
2270 && !curr_alt_win
[this_alternative_matches
]
2272 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2273 && (hard_regno
[nop
] >= 0
2274 ? in_hard_reg_set_p (this_alternative_set
,
2275 mode
, hard_regno
[nop
])
2276 : in_class_p (op
, this_alternative
, NULL
)))
2278 if (lra_dump_file
!= NULL
)
2281 " %d Dying matched operand reload: reject++\n",
2287 /* Strict_low_part requires to reload the register
2288 not the sub-register. In this case we should
2289 check that a final reload hard reg can hold the
2291 if (curr_static_id
->operand
[nop
].strict_low
2293 && hard_regno
[nop
] < 0
2294 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2295 && ira_class_hard_regs_num
[this_alternative
] > 0
2296 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2297 [this_alternative
][0],
2299 (*curr_id
->operand_loc
[nop
])))
2301 if (lra_dump_file
!= NULL
)
2304 " alt=%d: Strict low subreg reload -- refuse\n",
2310 if (operand_reg
[nop
] != NULL_RTX
2311 /* Output operands and matched input operands are
2312 not inherited. The following conditions do not
2313 exactly describe the previous statement but they
2314 are pretty close. */
2315 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2316 && (this_alternative_matches
< 0
2317 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2319 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2323 /* The value of reload_sum has sense only if we
2324 process insns in their order. It happens only on
2325 the first constraints sub-pass when we do most of
2327 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2328 reload_sum
+= last_reload
- bb_reload_num
;
2330 /* If this is a constant that is reloaded into the
2331 desired class by copying it to memory first, count
2332 that as another reload. This is consistent with
2333 other code and is required to avoid choosing another
2334 alternative when the constant is moved into memory.
2335 Note that the test here is precisely the same as in
2336 the code below that calls force_const_mem. */
2337 if (CONST_POOL_OK_P (mode
, op
)
2338 && ((targetm
.preferred_reload_class
2339 (op
, this_alternative
) == NO_REGS
)
2340 || no_input_reloads_p
))
2347 /* Alternative loses if it requires a type of reload not
2348 permitted for this insn. We can always reload
2349 objects with a REG_UNUSED note. */
2350 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2351 && no_output_reloads_p
2352 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2353 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2354 && no_input_reloads_p
&& ! const_to_mem
)
2355 || (this_alternative_matches
>= 0
2356 && (no_input_reloads_p
2357 || (no_output_reloads_p
2358 && (curr_static_id
->operand
2359 [this_alternative_matches
].type
!= OP_IN
)
2360 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2361 no_subreg_reg_operand
2362 [this_alternative_matches
])))))
2364 if (lra_dump_file
!= NULL
)
2367 " alt=%d: No input/otput reload -- refuse\n",
2372 /* Alternative loses if it required class pseudo can not
2373 hold value of required mode. Such insns can be
2374 described by insn definitions with mode iterators. */
2375 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2376 && ! hard_reg_set_empty_p (this_alternative_set
)
2377 /* It is common practice for constraints to use a
2378 class which does not have actually enough regs to
2379 hold the value (e.g. x86 AREG for mode requiring
2380 more one general reg). Therefore we have 2
2381 conditions to check that the reload pseudo can
2382 not hold the mode value. */
2383 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2384 [this_alternative
][0],
2385 GET_MODE (*curr_id
->operand_loc
[nop
]))
2386 /* The above condition is not enough as the first
2387 reg in ira_class_hard_regs can be not aligned for
2388 multi-words mode values. */
2389 && (prohibited_class_reg_set_mode_p
2390 (this_alternative
, this_alternative_set
,
2391 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2393 if (lra_dump_file
!= NULL
)
2394 fprintf (lra_dump_file
,
2395 " alt=%d: reload pseudo for op %d "
2396 " can not hold the mode value -- refuse\n",
2401 /* Check strong discouragement of reload of non-constant
2402 into class THIS_ALTERNATIVE. */
2403 if (! CONSTANT_P (op
) && ! no_regs_p
2404 && (targetm
.preferred_reload_class
2405 (op
, this_alternative
) == NO_REGS
2406 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2407 && (targetm
.preferred_output_reload_class
2408 (op
, this_alternative
) == NO_REGS
))))
2410 if (lra_dump_file
!= NULL
)
2411 fprintf (lra_dump_file
,
2412 " %d Non-prefered reload: reject+=%d\n",
2413 nop
, LRA_MAX_REJECT
);
2414 reject
+= LRA_MAX_REJECT
;
2417 if (! (MEM_P (op
) && offmemok
)
2418 && ! (const_to_mem
&& constmemok
))
2420 /* We prefer to reload pseudos over reloading other
2421 things, since such reloads may be able to be
2422 eliminated later. So bump REJECT in other cases.
2423 Don't do this in the case where we are forcing a
2424 constant into memory and it will then win since
2425 we don't want to have a different alternative
2427 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2429 if (lra_dump_file
!= NULL
)
2432 " %d Non-pseudo reload: reject+=2\n",
2439 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2441 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2443 if (lra_dump_file
!= NULL
)
2446 " %d Small class reload: reject+=%d\n",
2447 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2448 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2452 /* We are trying to spill pseudo into memory. It is
2453 usually more costly than moving to a hard register
2454 although it might takes the same number of
2456 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2458 if (lra_dump_file
!= NULL
)
2461 " %d Spill pseudo into memory: reject+=3\n",
2464 if (VECTOR_MODE_P (mode
))
2466 /* Spilling vectors into memory is usually more
2467 costly as they contain big values. */
2468 if (lra_dump_file
!= NULL
)
2471 " %d Spill vector pseudo: reject+=2\n",
2477 #ifdef SECONDARY_MEMORY_NEEDED
2478 /* If reload requires moving value through secondary
2479 memory, it will need one more insn at least. */
2480 if (this_alternative
!= NO_REGS
2481 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2482 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2483 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2485 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2486 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2490 /* Input reloads can be inherited more often than output
2491 reloads can be removed, so penalize output
2493 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2495 if (lra_dump_file
!= NULL
)
2498 " %d Non input pseudo reload: reject++\n",
2504 if (early_clobber_p
&& ! scratch_p
)
2506 if (lra_dump_file
!= NULL
)
2507 fprintf (lra_dump_file
,
2508 " %d Early clobber: reject++\n", nop
);
2511 /* ??? We check early clobbers after processing all operands
2512 (see loop below) and there we update the costs more.
2513 Should we update the cost (may be approximately) here
2514 because of early clobber register reloads or it is a rare
2515 or non-important thing to be worth to do it. */
2516 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2517 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2519 if (lra_dump_file
!= NULL
)
2520 fprintf (lra_dump_file
,
2521 " alt=%d,overall=%d,losers=%d -- refuse\n",
2522 nalt
, overall
, losers
);
2526 curr_alt
[nop
] = this_alternative
;
2527 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2528 curr_alt_win
[nop
] = this_alternative_win
;
2529 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2530 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2531 curr_alt_matches
[nop
] = this_alternative_matches
;
2533 if (this_alternative_matches
>= 0
2534 && !did_match
&& !this_alternative_win
)
2535 curr_alt_win
[this_alternative_matches
] = false;
2537 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2538 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2540 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2541 /* Prevent processing non-move insns. */
2542 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2543 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2544 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2545 && REG_P (no_subreg_reg_operand
[0])
2546 && REG_P (no_subreg_reg_operand
[1])
2547 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2548 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2549 || (! curr_alt_win
[0] && curr_alt_win
[1]
2550 && REG_P (no_subreg_reg_operand
[1])
2551 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2552 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2553 && REG_P (no_subreg_reg_operand
[0])
2554 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2555 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2556 no_subreg_reg_operand
[1])
2557 || (targetm
.preferred_reload_class
2558 (no_subreg_reg_operand
[1],
2559 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2560 /* If it is a result of recent elimination in move
2561 insn we can transform it into an add still by
2562 using this alternative. */
2563 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2565 /* We have a move insn and a new reload insn will be similar
2566 to the current insn. We should avoid such situation as it
2567 results in LRA cycling. */
2568 overall
+= LRA_MAX_REJECT
;
2571 curr_alt_dont_inherit_ops_num
= 0;
2572 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2574 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2575 HARD_REG_SET temp_set
;
2577 i
= early_clobbered_nops
[nop
];
2578 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2579 || hard_regno
[i
] < 0)
2581 lra_assert (operand_reg
[i
] != NULL_RTX
);
2582 clobbered_hard_regno
= hard_regno
[i
];
2583 CLEAR_HARD_REG_SET (temp_set
);
2584 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2585 first_conflict_j
= last_conflict_j
= -1;
2586 for (j
= 0; j
< n_operands
; j
++)
2588 /* We don't want process insides of match_operator and
2589 match_parallel because otherwise we would process
2590 their operands once again generating a wrong
2592 || curr_static_id
->operand
[j
].is_operator
)
2594 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2595 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2597 /* If we don't reload j-th operand, check conflicts. */
2598 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2599 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2601 if (first_conflict_j
< 0)
2602 first_conflict_j
= j
;
2603 last_conflict_j
= j
;
2605 if (last_conflict_j
< 0)
2607 /* If earlyclobber operand conflicts with another
2608 non-matching operand which is actually the same register
2609 as the earlyclobber operand, it is better to reload the
2610 another operand as an operand matching the earlyclobber
2611 operand can be also the same. */
2612 if (first_conflict_j
== last_conflict_j
2613 && operand_reg
[last_conflict_j
] != NULL_RTX
2614 && ! curr_alt_match_win
[last_conflict_j
]
2615 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2617 curr_alt_win
[last_conflict_j
] = false;
2618 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2621 /* Early clobber was already reflected in REJECT. */
2622 lra_assert (reject
> 0);
2623 if (lra_dump_file
!= NULL
)
2626 " %d Conflict early clobber reload: reject--\n",
2629 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2633 /* We need to reload early clobbered register and the
2634 matched registers. */
2635 for (j
= 0; j
< n_operands
; j
++)
2636 if (curr_alt_matches
[j
] == i
)
2638 curr_alt_match_win
[j
] = false;
2640 overall
+= LRA_LOSER_COST_FACTOR
;
2642 if (! curr_alt_match_win
[i
])
2643 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2646 /* Remember pseudos used for match reloads are never
2648 lra_assert (curr_alt_matches
[i
] >= 0);
2649 curr_alt_win
[curr_alt_matches
[i
]] = false;
2651 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2653 /* Early clobber was already reflected in REJECT. */
2654 lra_assert (reject
> 0);
2655 if (lra_dump_file
!= NULL
)
2658 " %d Matched conflict early clobber reloads:"
2662 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2665 if (lra_dump_file
!= NULL
)
2666 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2667 nalt
, overall
, losers
, reload_nregs
);
2669 /* If this alternative can be made to work by reloading, and it
2670 needs less reloading than the others checked so far, record
2671 it as the chosen goal for reloading. */
2672 if ((best_losers
!= 0 && losers
== 0)
2673 || (((best_losers
== 0 && losers
== 0)
2674 || (best_losers
!= 0 && losers
!= 0))
2675 && (best_overall
> overall
2676 || (best_overall
== overall
2677 /* If the cost of the reloads is the same,
2678 prefer alternative which requires minimal
2679 number of reload regs. */
2680 && (reload_nregs
< best_reload_nregs
2681 || (reload_nregs
== best_reload_nregs
2682 && (best_reload_sum
< reload_sum
2683 || (best_reload_sum
== reload_sum
2684 && nalt
< goal_alt_number
))))))))
2686 for (nop
= 0; nop
< n_operands
; nop
++)
2688 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2689 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2690 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2691 goal_alt
[nop
] = curr_alt
[nop
];
2692 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2694 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2695 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2696 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2697 goal_alt_swapped
= curr_swapped
;
2698 best_overall
= overall
;
2699 best_losers
= losers
;
2700 best_reload_nregs
= reload_nregs
;
2701 best_reload_sum
= reload_sum
;
2702 goal_alt_number
= nalt
;
2705 /* Everything is satisfied. Do not process alternatives
2714 /* Make reload base reg from address AD. */
2716 base_to_reg (struct address_info
*ad
)
2720 rtx new_inner
= NULL_RTX
;
2721 rtx new_reg
= NULL_RTX
;
2723 rtx_insn
*last_insn
= get_last_insn();
2725 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2726 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2727 get_index_code (ad
));
2728 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2730 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2731 ad
->disp_term
== NULL
2732 ? gen_int_mode (0, ad
->mode
)
2734 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2736 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base_term
));
2737 code
= recog_memoized (insn
);
2740 delete_insns_since (last_insn
);
2747 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2749 base_plus_disp_to_reg (struct address_info
*ad
)
2754 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2755 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2756 get_index_code (ad
));
2757 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2759 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2763 /* Make reload of index part of address AD. Return the new
2766 index_part_to_reg (struct address_info
*ad
)
2770 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2771 INDEX_REG_CLASS
, "index term");
2772 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2773 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2777 /* Return true if we can add a displacement to address AD, even if that
2778 makes the address invalid. The fix-up code requires any new address
2779 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2781 can_add_disp_p (struct address_info
*ad
)
2783 return (!ad
->autoinc_p
2784 && ad
->segment
== NULL
2785 && ad
->base
== ad
->base_term
2786 && ad
->disp
== ad
->disp_term
);
2789 /* Make equiv substitution in address AD. Return true if a substitution
2792 equiv_address_substitution (struct address_info
*ad
)
2794 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2795 HOST_WIDE_INT disp
, scale
;
2798 base_term
= strip_subreg (ad
->base_term
);
2799 if (base_term
== NULL
)
2800 base_reg
= new_base_reg
= NULL_RTX
;
2803 base_reg
= *base_term
;
2804 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2806 index_term
= strip_subreg (ad
->index_term
);
2807 if (index_term
== NULL
)
2808 index_reg
= new_index_reg
= NULL_RTX
;
2811 index_reg
= *index_term
;
2812 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2814 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2818 if (lra_dump_file
!= NULL
)
2820 fprintf (lra_dump_file
, "Changing address in insn %d ",
2821 INSN_UID (curr_insn
));
2822 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2824 if (base_reg
!= new_base_reg
)
2826 if (REG_P (new_base_reg
))
2828 *base_term
= new_base_reg
;
2831 else if (GET_CODE (new_base_reg
) == PLUS
2832 && REG_P (XEXP (new_base_reg
, 0))
2833 && CONST_INT_P (XEXP (new_base_reg
, 1))
2834 && can_add_disp_p (ad
))
2836 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2837 *base_term
= XEXP (new_base_reg
, 0);
2840 if (ad
->base_term2
!= NULL
)
2841 *ad
->base_term2
= *ad
->base_term
;
2843 if (index_reg
!= new_index_reg
)
2845 if (REG_P (new_index_reg
))
2847 *index_term
= new_index_reg
;
2850 else if (GET_CODE (new_index_reg
) == PLUS
2851 && REG_P (XEXP (new_index_reg
, 0))
2852 && CONST_INT_P (XEXP (new_index_reg
, 1))
2853 && can_add_disp_p (ad
)
2854 && (scale
= get_index_scale (ad
)))
2856 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2857 *index_term
= XEXP (new_index_reg
, 0);
2863 if (ad
->disp
!= NULL
)
2864 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2867 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2868 update_address (ad
);
2872 if (lra_dump_file
!= NULL
)
2875 fprintf (lra_dump_file
, " -- no change\n");
2878 fprintf (lra_dump_file
, " on equiv ");
2879 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2880 fprintf (lra_dump_file
, "\n");
2886 /* Major function to make reloads for an address in operand NOP or
2887 check its correctness (If CHECK_ONLY_P is true). The supported
2890 1) an address that existed before LRA started, at which point it
2891 must have been valid. These addresses are subject to elimination
2892 and may have become invalid due to the elimination offset being out
2895 2) an address created by forcing a constant to memory
2896 (force_const_to_mem). The initial form of these addresses might
2897 not be valid, and it is this function's job to make them valid.
2899 3) a frame address formed from a register and a (possibly zero)
2900 constant offset. As above, these addresses might not be valid and
2901 this function must make them so.
2903 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2904 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2905 address. Return true for any RTL change.
2907 The function is a helper function which does not produce all
2908 transformations (when CHECK_ONLY_P is false) which can be
2909 necessary. It does just basic steps. To do all necessary
2910 transformations use function process_address. */
2912 process_address_1 (int nop
, bool check_only_p
,
2913 rtx_insn
**before
, rtx_insn
**after
)
2915 struct address_info ad
;
2917 HOST_WIDE_INT scale
;
2918 rtx op
= *curr_id
->operand_loc
[nop
];
2919 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2920 enum constraint_num cn
= lookup_constraint (constraint
);
2921 bool change_p
= false;
2924 && GET_MODE (op
) == BLKmode
2925 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
2928 if (insn_extra_address_constraint (cn
))
2929 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2930 else if (MEM_P (op
))
2931 decompose_mem_address (&ad
, op
);
2932 else if (GET_CODE (op
) == SUBREG
2933 && MEM_P (SUBREG_REG (op
)))
2934 decompose_mem_address (&ad
, SUBREG_REG (op
));
2937 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
2938 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
2939 when INDEX_REG_CLASS is a single register class. */
2940 if (ad
.base_term
!= NULL
2941 && ad
.index_term
!= NULL
2942 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
2943 && REG_P (*ad
.base_term
)
2944 && REG_P (*ad
.index_term
)
2945 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
2946 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
2948 std::swap (ad
.base
, ad
.index
);
2949 std::swap (ad
.base_term
, ad
.index_term
);
2952 change_p
= equiv_address_substitution (&ad
);
2953 if (ad
.base_term
!= NULL
2954 && (process_addr_reg
2955 (ad
.base_term
, check_only_p
, before
,
2957 && !(REG_P (*ad
.base_term
)
2958 && find_regno_note (curr_insn
, REG_DEAD
,
2959 REGNO (*ad
.base_term
)) != NULL_RTX
)
2961 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2962 get_index_code (&ad
)))))
2965 if (ad
.base_term2
!= NULL
)
2966 *ad
.base_term2
= *ad
.base_term
;
2968 if (ad
.index_term
!= NULL
2969 && process_addr_reg (ad
.index_term
, check_only_p
,
2970 before
, NULL
, INDEX_REG_CLASS
))
2973 /* Target hooks sometimes don't treat extra-constraint addresses as
2974 legitimate address_operands, so handle them specially. */
2975 if (insn_extra_address_constraint (cn
)
2976 && satisfies_address_constraint_p (&ad
, cn
))
2982 /* There are three cases where the shape of *AD.INNER may now be invalid:
2984 1) the original address was valid, but either elimination or
2985 equiv_address_substitution was applied and that made
2986 the address invalid.
2988 2) the address is an invalid symbolic address created by
2991 3) the address is a frame address with an invalid offset.
2993 4) the address is a frame address with an invalid base.
2995 All these cases involve a non-autoinc address, so there is no
2996 point revalidating other types. */
2997 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3000 /* Any index existed before LRA started, so we can assume that the
3001 presence and shape of the index is valid. */
3002 push_to_sequence (*before
);
3003 lra_assert (ad
.disp
== ad
.disp_term
);
3004 if (ad
.base
== NULL
)
3006 if (ad
.index
== NULL
)
3009 rtx_insn
*last
= get_last_insn ();
3011 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3013 rtx addr
= *ad
.inner
;
3015 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3018 /* addr => lo_sum (new_base, addr), case (2) above. */
3019 insn
= emit_insn (gen_rtx_SET
3021 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3022 code
= recog_memoized (insn
);
3025 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3026 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3028 /* Try to put lo_sum into register. */
3029 insn
= emit_insn (gen_rtx_SET
3031 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3032 code
= recog_memoized (insn
);
3035 *ad
.inner
= new_reg
;
3036 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3046 delete_insns_since (last
);
3051 /* addr => new_base, case (2) above. */
3052 lra_emit_move (new_reg
, addr
);
3054 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3056 insn
= NEXT_INSN (insn
))
3057 if (recog_memoized (insn
) < 0)
3059 if (insn
!= NULL_RTX
)
3061 /* Do nothing if we cannot generate right insns.
3062 This is analogous to reload pass behavior. */
3063 delete_insns_since (last
);
3067 *ad
.inner
= new_reg
;
3072 /* index * scale + disp => new base + index * scale,
3074 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3075 GET_CODE (*ad
.index
));
3077 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3078 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3079 lra_emit_move (new_reg
, *ad
.disp
);
3080 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3081 new_reg
, *ad
.index
);
3084 else if (ad
.index
== NULL
)
3089 rtx_insn
*insns
, *last_insn
;
3090 /* Try to reload base into register only if the base is invalid
3091 for the address but with valid offset, case (4) above. */
3093 new_reg
= base_to_reg (&ad
);
3095 /* base + disp => new base, cases (1) and (3) above. */
3096 /* Another option would be to reload the displacement into an
3097 index register. However, postreload has code to optimize
3098 address reloads that have the same base and different
3099 displacements, so reloading into an index register would
3100 not necessarily be a win. */
3101 if (new_reg
== NULL_RTX
)
3102 new_reg
= base_plus_disp_to_reg (&ad
);
3103 insns
= get_insns ();
3104 last_insn
= get_last_insn ();
3105 /* If we generated at least two insns, try last insn source as
3106 an address. If we succeed, we generate one less insn. */
3107 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3108 && GET_CODE (SET_SRC (set
)) == PLUS
3109 && REG_P (XEXP (SET_SRC (set
), 0))
3110 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3112 *ad
.inner
= SET_SRC (set
);
3113 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3115 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3116 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3117 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3118 get_index_code (&ad
));
3119 regno
= REGNO (*ad
.base_term
);
3120 if (regno
>= FIRST_PSEUDO_REGISTER
3121 && cl
!= lra_get_allocno_class (regno
))
3122 lra_change_class (regno
, cl
, " Change to", true);
3123 new_reg
= SET_SRC (set
);
3124 delete_insns_since (PREV_INSN (last_insn
));
3127 /* Try if target can split displacement into legitimite new disp
3128 and offset. If it's the case, we replace the last insn with
3129 insns for base + offset => new_reg and set new_reg + new disp
3131 last_insn
= get_last_insn ();
3132 if ((set
= single_set (last_insn
)) != NULL_RTX
3133 && GET_CODE (SET_SRC (set
)) == PLUS
3134 && REG_P (XEXP (SET_SRC (set
), 0))
3135 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3136 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3138 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3139 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3142 rtx_insn
*new_insns
;
3144 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3145 new_insns
= get_insns ();
3147 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3148 delete_insns_since (PREV_INSN (last_insn
));
3149 add_insn (new_insns
);
3150 insns
= get_insns ();
3155 *ad
.inner
= new_reg
;
3157 else if (ad
.disp_term
!= NULL
)
3159 /* base + scale * index + disp => new base + scale * index,
3161 new_reg
= base_plus_disp_to_reg (&ad
);
3162 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3163 new_reg
, *ad
.index
);
3165 else if ((scale
= get_index_scale (&ad
)) == 1)
3167 /* The last transformation to one reg will be made in
3168 curr_insn_transform function. */
3172 else if (scale
!= 0)
3174 /* base + scale * index => base + new_reg,
3176 Index part of address may become invalid. For example, we
3177 changed pseudo on the equivalent memory and a subreg of the
3178 pseudo onto the memory of different mode for which the scale is
3180 new_reg
= index_part_to_reg (&ad
);
3181 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3182 *ad
.base_term
, new_reg
);
3186 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3188 rtx addr
= *ad
.inner
;
3190 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3191 /* addr => new_base. */
3192 lra_emit_move (new_reg
, addr
);
3193 *ad
.inner
= new_reg
;
3195 *before
= get_insns ();
3200 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3201 Use process_address_1 as a helper function. Return true for any
3204 If CHECK_ONLY_P is true, just check address correctness. Return
3205 false if the address correct. */
3207 process_address (int nop
, bool check_only_p
,
3208 rtx_insn
**before
, rtx_insn
**after
)
3212 while (process_address_1 (nop
, check_only_p
, before
, after
))
3221 /* Emit insns to reload VALUE into a new register. VALUE is an
3222 auto-increment or auto-decrement RTX whose operand is a register or
3223 memory location; so reloading involves incrementing that location.
3224 IN is either identical to VALUE, or some cheaper place to reload
3225 value being incremented/decremented from.
3227 INC_AMOUNT is the number to increment or decrement by (always
3228 positive and ignored for POST_MODIFY/PRE_MODIFY).
3230 Return pseudo containing the result. */
3232 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3234 /* REG or MEM to be copied and incremented. */
3235 rtx incloc
= XEXP (value
, 0);
3236 /* Nonzero if increment after copying. */
3237 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3238 || GET_CODE (value
) == POST_MODIFY
);
3243 rtx real_in
= in
== value
? incloc
: in
;
3247 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3249 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3250 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3251 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3252 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3253 inc
= XEXP (XEXP (value
, 1), 1);
3257 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3258 inc_amount
= -inc_amount
;
3260 inc
= GEN_INT (inc_amount
);
3263 if (! post
&& REG_P (incloc
))
3266 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3269 if (real_in
!= result
)
3271 /* First copy the location to the result register. */
3272 lra_assert (REG_P (result
));
3273 emit_insn (gen_move_insn (result
, real_in
));
3276 /* We suppose that there are insns to add/sub with the constant
3277 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3278 old reload worked with this assumption. If the assumption
3279 becomes wrong, we should use approach in function
3280 base_plus_disp_to_reg. */
3283 /* See if we can directly increment INCLOC. */
3284 last
= get_last_insn ();
3285 add_insn
= emit_insn (plus_p
3286 ? gen_add2_insn (incloc
, inc
)
3287 : gen_sub2_insn (incloc
, inc
));
3289 code
= recog_memoized (add_insn
);
3292 if (! post
&& result
!= incloc
)
3293 emit_insn (gen_move_insn (result
, incloc
));
3296 delete_insns_since (last
);
3299 /* If couldn't do the increment directly, must increment in RESULT.
3300 The way we do this depends on whether this is pre- or
3301 post-increment. For pre-increment, copy INCLOC to the reload
3302 register, increment it there, then save back. */
3305 if (real_in
!= result
)
3306 emit_insn (gen_move_insn (result
, real_in
));
3308 emit_insn (gen_add2_insn (result
, inc
));
3310 emit_insn (gen_sub2_insn (result
, inc
));
3311 if (result
!= incloc
)
3312 emit_insn (gen_move_insn (incloc
, result
));
3318 Because this might be a jump insn or a compare, and because
3319 RESULT may not be available after the insn in an input
3320 reload, we must do the incrementing before the insn being
3323 We have already copied IN to RESULT. Increment the copy in
3324 RESULT, save that back, then decrement RESULT so it has
3325 the original value. */
3327 emit_insn (gen_add2_insn (result
, inc
));
3329 emit_insn (gen_sub2_insn (result
, inc
));
3330 emit_insn (gen_move_insn (incloc
, result
));
3331 /* Restore non-modified value for the result. We prefer this
3332 way because it does not require an additional hard
3336 if (CONST_INT_P (inc
))
3337 emit_insn (gen_add2_insn (result
,
3338 gen_int_mode (-INTVAL (inc
),
3339 GET_MODE (result
))));
3341 emit_insn (gen_sub2_insn (result
, inc
));
3344 emit_insn (gen_add2_insn (result
, inc
));
3349 /* Return true if the current move insn does not need processing as we
3350 already know that it satisfies its constraints. */
3352 simple_move_p (void)
3355 enum reg_class dclass
, sclass
;
3357 lra_assert (curr_insn_set
!= NULL_RTX
);
3358 dest
= SET_DEST (curr_insn_set
);
3359 src
= SET_SRC (curr_insn_set
);
3360 return ((dclass
= get_op_class (dest
)) != NO_REGS
3361 && (sclass
= get_op_class (src
)) != NO_REGS
3362 /* The backend guarantees that register moves of cost 2
3363 never need reloads. */
3364 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3367 /* Swap operands NOP and NOP + 1. */
3369 swap_operands (int nop
)
3371 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3372 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3373 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3374 /* Swap the duplicates too. */
3375 lra_update_dup (curr_id
, nop
);
3376 lra_update_dup (curr_id
, nop
+ 1);
3379 /* Main entry point of the constraint code: search the body of the
3380 current insn to choose the best alternative. It is mimicking insn
3381 alternative cost calculation model of former reload pass. That is
3382 because machine descriptions were written to use this model. This
3383 model can be changed in future. Make commutative operand exchange
3386 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3387 constraints. Return true if any change happened during function
3390 If CHECK_ONLY_P is true then don't do any transformation. Just
3391 check that the insn satisfies all constraints. If the insn does
3392 not satisfy any constraint, return true. */
3394 curr_insn_transform (bool check_only_p
)
3400 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3401 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3402 rtx_insn
*before
, *after
;
3404 /* Flag that the insn has been changed through a transformation. */
3407 #ifdef SECONDARY_MEMORY_NEEDED
3410 int max_regno_before
;
3411 int reused_alternative_num
;
3413 curr_insn_set
= single_set (curr_insn
);
3414 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3417 no_input_reloads_p
= no_output_reloads_p
= false;
3418 goal_alt_number
= -1;
3419 change_p
= sec_mem_p
= false;
3420 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3421 reloads; neither are insns that SET cc0. Insns that use CC0 are
3422 not allowed to have any input reloads. */
3423 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3424 no_output_reloads_p
= true;
3426 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3427 no_input_reloads_p
= true;
3428 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3429 no_output_reloads_p
= true;
3431 n_operands
= curr_static_id
->n_operands
;
3432 n_alternatives
= curr_static_id
->n_alternatives
;
3434 /* Just return "no reloads" if insn has no operands with
3436 if (n_operands
== 0 || n_alternatives
== 0)
3439 max_regno_before
= max_reg_num ();
3441 for (i
= 0; i
< n_operands
; i
++)
3443 goal_alt_matched
[i
][0] = -1;
3444 goal_alt_matches
[i
] = -1;
3447 commutative
= curr_static_id
->commutative
;
3449 /* Now see what we need for pseudos that didn't get hard regs or got
3450 the wrong kind of hard reg. For this, we must consider all the
3451 operands together against the register constraints. */
3453 best_losers
= best_overall
= INT_MAX
;
3454 best_reload_sum
= 0;
3456 curr_swapped
= false;
3457 goal_alt_swapped
= false;
3460 /* Make equivalence substitution and memory subreg elimination
3461 before address processing because an address legitimacy can
3462 depend on memory mode. */
3463 for (i
= 0; i
< n_operands
; i
++)
3466 bool op_change_p
= false;
3468 if (curr_static_id
->operand
[i
].is_operator
)
3471 old
= op
= *curr_id
->operand_loc
[i
];
3472 if (GET_CODE (old
) == SUBREG
)
3473 old
= SUBREG_REG (old
);
3474 subst
= get_equiv_with_elimination (old
, curr_insn
);
3475 original_subreg_reg_mode
[i
] = VOIDmode
;
3478 subst
= copy_rtx (subst
);
3479 lra_assert (REG_P (old
));
3480 if (GET_CODE (op
) != SUBREG
)
3481 *curr_id
->operand_loc
[i
] = subst
;
3484 SUBREG_REG (op
) = subst
;
3485 if (GET_MODE (subst
) == VOIDmode
)
3486 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3488 if (lra_dump_file
!= NULL
)
3490 fprintf (lra_dump_file
,
3491 "Changing pseudo %d in operand %i of insn %u on equiv ",
3492 REGNO (old
), i
, INSN_UID (curr_insn
));
3493 dump_value_slim (lra_dump_file
, subst
, 1);
3494 fprintf (lra_dump_file
, "\n");
3496 op_change_p
= change_p
= true;
3498 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3501 lra_update_dup (curr_id
, i
);
3505 /* Reload address registers and displacements. We do it before
3506 finding an alternative because of memory constraints. */
3507 before
= after
= NULL
;
3508 for (i
= 0; i
< n_operands
; i
++)
3509 if (! curr_static_id
->operand
[i
].is_operator
3510 && process_address (i
, check_only_p
, &before
, &after
))
3515 lra_update_dup (curr_id
, i
);
3519 /* If we've changed the instruction then any alternative that
3520 we chose previously may no longer be valid. */
3521 lra_set_used_insn_alternative (curr_insn
, -1);
3523 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3524 && check_and_process_move (&change_p
, &sec_mem_p
))
3529 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3530 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3531 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3532 reused_alternative_num
, INSN_UID (curr_insn
));
3534 if (process_alt_operands (reused_alternative_num
))
3538 return ! alt_p
|| best_losers
!= 0;
3540 /* If insn is commutative (it's safe to exchange a certain pair of
3541 operands) then we need to try each alternative twice, the second
3542 time matching those two operands as if we had exchanged them. To
3543 do this, really exchange them in operands.
3545 If we have just tried the alternatives the second time, return
3546 operands to normal and drop through. */
3548 if (reused_alternative_num
< 0 && commutative
>= 0)
3550 curr_swapped
= !curr_swapped
;
3553 swap_operands (commutative
);
3557 swap_operands (commutative
);
3560 if (! alt_p
&& ! sec_mem_p
)
3562 /* No alternative works with reloads?? */
3563 if (INSN_CODE (curr_insn
) >= 0)
3564 fatal_insn ("unable to generate reloads for:", curr_insn
);
3565 error_for_asm (curr_insn
,
3566 "inconsistent operand constraints in an %<asm%>");
3567 /* Avoid further trouble with this insn. */
3568 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3569 lra_invalidate_insn_data (curr_insn
);
3573 /* If the best alternative is with operands 1 and 2 swapped, swap
3574 them. Update the operand numbers of any reloads already
3577 if (goal_alt_swapped
)
3579 if (lra_dump_file
!= NULL
)
3580 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3581 INSN_UID (curr_insn
));
3583 /* Swap the duplicates too. */
3584 swap_operands (commutative
);
3588 #ifdef SECONDARY_MEMORY_NEEDED
3589 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3590 too conservatively. So we use the secondary memory only if there
3591 is no any alternative without reloads. */
3592 use_sec_mem_p
= false;
3594 use_sec_mem_p
= true;
3597 for (i
= 0; i
< n_operands
; i
++)
3598 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3600 use_sec_mem_p
= i
< n_operands
;
3605 int in
= -1, out
= -1;
3606 rtx new_reg
, src
, dest
, rld
;
3607 machine_mode sec_mode
, rld_mode
;
3609 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3610 dest
= SET_DEST (curr_insn_set
);
3611 src
= SET_SRC (curr_insn_set
);
3612 for (i
= 0; i
< n_operands
; i
++)
3613 if (*curr_id
->operand_loc
[i
] == dest
)
3615 else if (*curr_id
->operand_loc
[i
] == src
)
3617 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3618 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3619 out
= curr_static_id
->dup_num
[i
];
3620 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3621 in
= curr_static_id
->dup_num
[i
];
3622 lra_assert (out
>= 0 && in
>= 0
3623 && curr_static_id
->operand
[out
].type
== OP_OUT
3624 && curr_static_id
->operand
[in
].type
== OP_IN
);
3625 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3627 rld_mode
= GET_MODE (rld
);
3628 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3629 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3631 sec_mode
= rld_mode
;
3633 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3634 NO_REGS
, "secondary");
3635 /* If the mode is changed, it should be wider. */
3636 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3637 if (sec_mode
!= rld_mode
)
3639 /* If the target says specifically to use another mode for
3640 secondary memory moves we can not reuse the original
3642 after
= emit_spill_move (false, new_reg
, dest
);
3643 lra_process_new_insns (curr_insn
, NULL
, after
,
3644 "Inserting the sec. move");
3645 /* We may have non null BEFORE here (e.g. after address
3647 push_to_sequence (before
);
3648 before
= emit_spill_move (true, new_reg
, src
);
3650 before
= get_insns ();
3652 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3653 lra_set_insn_deleted (curr_insn
);
3655 else if (dest
== rld
)
3657 *curr_id
->operand_loc
[out
] = new_reg
;
3658 lra_update_dup (curr_id
, out
);
3659 after
= emit_spill_move (false, new_reg
, dest
);
3660 lra_process_new_insns (curr_insn
, NULL
, after
,
3661 "Inserting the sec. move");
3665 *curr_id
->operand_loc
[in
] = new_reg
;
3666 lra_update_dup (curr_id
, in
);
3667 /* See comments above. */
3668 push_to_sequence (before
);
3669 before
= emit_spill_move (true, new_reg
, src
);
3671 before
= get_insns ();
3673 lra_process_new_insns (curr_insn
, before
, NULL
,
3674 "Inserting the sec. move");
3676 lra_update_insn_regno_info (curr_insn
);
3681 lra_assert (goal_alt_number
>= 0);
3682 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3684 if (lra_dump_file
!= NULL
)
3688 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3689 goal_alt_number
, INSN_UID (curr_insn
));
3690 for (i
= 0; i
< n_operands
; i
++)
3692 p
= (curr_static_id
->operand_alternative
3693 [goal_alt_number
* n_operands
+ i
].constraint
);
3696 fprintf (lra_dump_file
, " (%d) ", i
);
3697 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3698 fputc (*p
, lra_dump_file
);
3700 if (INSN_CODE (curr_insn
) >= 0
3701 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3702 fprintf (lra_dump_file
, " {%s}", p
);
3703 if (curr_id
->sp_offset
!= 0)
3704 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3705 curr_id
->sp_offset
);
3706 fprintf (lra_dump_file
, "\n");
3709 /* Right now, for any pair of operands I and J that are required to
3710 match, with J < I, goal_alt_matches[I] is J. Add I to
3711 goal_alt_matched[J]. */
3713 for (i
= 0; i
< n_operands
; i
++)
3714 if ((j
= goal_alt_matches
[i
]) >= 0)
3716 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3718 /* We allow matching one output operand and several input
3721 || (curr_static_id
->operand
[j
].type
== OP_OUT
3722 && curr_static_id
->operand
[i
].type
== OP_IN
3723 && (curr_static_id
->operand
3724 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3725 goal_alt_matched
[j
][k
] = i
;
3726 goal_alt_matched
[j
][k
+ 1] = -1;
3729 for (i
= 0; i
< n_operands
; i
++)
3730 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3732 /* Any constants that aren't allowed and can't be reloaded into
3733 registers are here changed into memory references. */
3734 for (i
= 0; i
< n_operands
; i
++)
3735 if (goal_alt_win
[i
])
3738 enum reg_class new_class
;
3739 rtx reg
= *curr_id
->operand_loc
[i
];
3741 if (GET_CODE (reg
) == SUBREG
)
3742 reg
= SUBREG_REG (reg
);
3744 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3746 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3748 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3751 lra_change_class (regno
, new_class
, " Change to", true);
3757 const char *constraint
;
3759 rtx op
= *curr_id
->operand_loc
[i
];
3760 rtx subreg
= NULL_RTX
;
3761 machine_mode mode
= curr_operand_mode
[i
];
3763 if (GET_CODE (op
) == SUBREG
)
3766 op
= SUBREG_REG (op
);
3767 mode
= GET_MODE (op
);
3770 if (CONST_POOL_OK_P (mode
, op
)
3771 && ((targetm
.preferred_reload_class
3772 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3773 || no_input_reloads_p
))
3775 rtx tem
= force_const_mem (mode
, op
);
3778 if (subreg
!= NULL_RTX
)
3779 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3781 *curr_id
->operand_loc
[i
] = tem
;
3782 lra_update_dup (curr_id
, i
);
3783 process_address (i
, false, &before
, &after
);
3785 /* If the alternative accepts constant pool refs directly
3786 there will be no reload needed at all. */
3787 if (subreg
!= NULL_RTX
)
3789 /* Skip alternatives before the one requested. */
3790 constraint
= (curr_static_id
->operand_alternative
3791 [goal_alt_number
* n_operands
+ i
].constraint
);
3793 (c
= *constraint
) && c
!= ',' && c
!= '#';
3794 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3796 enum constraint_num cn
= lookup_constraint (constraint
);
3797 if ((insn_extra_memory_constraint (cn
)
3798 || insn_extra_special_memory_constraint (cn
))
3799 && satisfies_memory_constraint_p (tem
, cn
))
3802 if (c
== '\0' || c
== ',' || c
== '#')
3805 goal_alt_win
[i
] = true;
3809 for (i
= 0; i
< n_operands
; i
++)
3812 bool optional_p
= false;
3814 rtx op
= *curr_id
->operand_loc
[i
];
3816 if (goal_alt_win
[i
])
3818 if (goal_alt
[i
] == NO_REGS
3820 /* When we assign NO_REGS it means that we will not
3821 assign a hard register to the scratch pseudo by
3822 assigment pass and the scratch pseudo will be
3823 spilled. Spilled scratch pseudos are transformed
3824 back to scratches at the LRA end. */
3825 && lra_former_scratch_operand_p (curr_insn
, i
)
3826 && lra_former_scratch_p (REGNO (op
)))
3828 int regno
= REGNO (op
);
3829 lra_change_class (regno
, NO_REGS
, " Change to", true);
3830 if (lra_get_regno_hard_regno (regno
) >= 0)
3831 /* We don't have to mark all insn affected by the
3832 spilled pseudo as there is only one such insn, the
3834 reg_renumber
[regno
] = -1;
3835 lra_assert (bitmap_single_bit_set_p
3836 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
3838 /* We can do an optional reload. If the pseudo got a hard
3839 reg, we might improve the code through inheritance. If
3840 it does not get a hard register we coalesce memory/memory
3841 moves later. Ignore move insns to avoid cycling. */
3843 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3844 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3845 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3846 && regno
< new_regno_start
3847 && ! lra_former_scratch_p (regno
)
3848 && reg_renumber
[regno
] < 0
3849 /* Check that the optional reload pseudo will be able to
3850 hold given mode value. */
3851 && ! (prohibited_class_reg_set_mode_p
3852 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
3853 PSEUDO_REGNO_MODE (regno
)))
3854 && (curr_insn_set
== NULL_RTX
3855 || !((REG_P (SET_SRC (curr_insn_set
))
3856 || MEM_P (SET_SRC (curr_insn_set
))
3857 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3858 && (REG_P (SET_DEST (curr_insn_set
))
3859 || MEM_P (SET_DEST (curr_insn_set
))
3860 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3866 /* Operands that match previous ones have already been handled. */
3867 if (goal_alt_matches
[i
] >= 0)
3870 /* We should not have an operand with a non-offsettable address
3871 appearing where an offsettable address will do. It also may
3872 be a case when the address should be special in other words
3873 not a general one (e.g. it needs no index reg). */
3874 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3876 enum reg_class rclass
;
3877 rtx
*loc
= &XEXP (op
, 0);
3878 enum rtx_code code
= GET_CODE (*loc
);
3880 push_to_sequence (before
);
3881 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3883 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3884 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3885 /* This value does not matter for MODIFY. */
3886 GET_MODE_SIZE (GET_MODE (op
)));
3887 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3888 "offsetable address", &new_reg
))
3889 lra_emit_move (new_reg
, *loc
);
3890 before
= get_insns ();
3893 lra_update_dup (curr_id
, i
);
3895 else if (goal_alt_matched
[i
][0] == -1)
3899 int hard_regno
, byte
;
3900 enum op_type type
= curr_static_id
->operand
[i
].type
;
3902 loc
= curr_id
->operand_loc
[i
];
3903 mode
= curr_operand_mode
[i
];
3904 if (GET_CODE (*loc
) == SUBREG
)
3906 reg
= SUBREG_REG (*loc
);
3907 byte
= SUBREG_BYTE (*loc
);
3909 /* Strict_low_part requires reload the register not
3910 the sub-register. */
3911 && (curr_static_id
->operand
[i
].strict_low
3912 || (GET_MODE_SIZE (mode
)
3913 <= GET_MODE_SIZE (GET_MODE (reg
))
3915 = get_try_hard_regno (REGNO (reg
))) >= 0
3916 && (simplify_subreg_regno
3918 GET_MODE (reg
), byte
, mode
) < 0)
3919 && (goal_alt
[i
] == NO_REGS
3920 || (simplify_subreg_regno
3921 (ira_class_hard_regs
[goal_alt
[i
]][0],
3922 GET_MODE (reg
), byte
, mode
) >= 0)))))
3926 loc
= &SUBREG_REG (*loc
);
3927 mode
= GET_MODE (*loc
);
3931 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3932 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3935 push_to_sequence (before
);
3936 lra_emit_move (new_reg
, old
);
3937 before
= get_insns ();
3942 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3945 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3947 after
= get_insns ();
3951 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3952 if (goal_alt_dont_inherit_ops
[j
] == i
)
3954 lra_set_regno_unique_value (REGNO (new_reg
));
3957 lra_update_dup (curr_id
, i
);
3959 else if (curr_static_id
->operand
[i
].type
== OP_IN
3960 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3963 /* generate reloads for input and matched outputs. */
3964 match_inputs
[0] = i
;
3965 match_inputs
[1] = -1;
3966 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3967 goal_alt
[i
], &before
, &after
,
3968 curr_static_id
->operand_alternative
3969 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
3972 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3973 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3975 /* Generate reloads for output and matched inputs. */
3976 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
,
3977 curr_static_id
->operand_alternative
3978 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
3979 else if (curr_static_id
->operand
[i
].type
== OP_IN
3980 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3983 /* Generate reloads for matched inputs. */
3984 match_inputs
[0] = i
;
3985 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3986 match_inputs
[j
+ 1] = k
;
3987 match_inputs
[j
+ 1] = -1;
3988 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
, false);
3991 /* We must generate code in any case when function
3992 process_alt_operands decides that it is possible. */
3996 lra_assert (REG_P (op
));
3998 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3999 if (GET_CODE (op
) == SUBREG
)
4000 op
= SUBREG_REG (op
);
4001 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4002 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4003 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
4004 if (lra_dump_file
!= NULL
)
4005 fprintf (lra_dump_file
,
4006 " Making reload reg %d for reg %d optional\n",
4010 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4011 || max_regno_before
!= max_reg_num ())
4015 lra_update_operator_dups (curr_id
);
4016 /* Something changes -- process the insn. */
4017 lra_update_insn_regno_info (curr_insn
);
4019 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4023 /* Return true if INSN satisfies all constraints. In other words, no
4024 reload insns are needed. */
4026 lra_constrain_insn (rtx_insn
*insn
)
4028 int saved_new_regno_start
= new_regno_start
;
4029 int saved_new_insn_uid_start
= new_insn_uid_start
;
4033 curr_id
= lra_get_insn_recog_data (curr_insn
);
4034 curr_static_id
= curr_id
->insn_static_data
;
4035 new_insn_uid_start
= get_max_uid ();
4036 new_regno_start
= max_reg_num ();
4037 change_p
= curr_insn_transform (true);
4038 new_regno_start
= saved_new_regno_start
;
4039 new_insn_uid_start
= saved_new_insn_uid_start
;
4043 /* Return true if X is in LIST. */
4045 in_list_p (rtx x
, rtx list
)
4047 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4048 if (XEXP (list
, 0) == x
)
4053 /* Return true if X contains an allocatable hard register (if
4054 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4056 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4062 code
= GET_CODE (x
);
4065 int regno
= REGNO (x
);
4066 HARD_REG_SET alloc_regs
;
4070 if (regno
>= FIRST_PSEUDO_REGISTER
)
4071 regno
= lra_get_regno_hard_regno (regno
);
4074 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4075 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4079 if (regno
< FIRST_PSEUDO_REGISTER
)
4083 return lra_get_regno_hard_regno (regno
) < 0;
4086 fmt
= GET_RTX_FORMAT (code
);
4087 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4091 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4094 else if (fmt
[i
] == 'E')
4096 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4097 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4104 /* Process all regs in location *LOC and change them on equivalent
4105 substitution. Return true if any change was done. */
4107 loc_equivalence_change_p (rtx
*loc
)
4109 rtx subst
, reg
, x
= *loc
;
4110 bool result
= false;
4111 enum rtx_code code
= GET_CODE (x
);
4117 reg
= SUBREG_REG (x
);
4118 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4119 && GET_MODE (subst
) == VOIDmode
)
4121 /* We cannot reload debug location. Simplify subreg here
4122 while we know the inner mode. */
4123 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4124 GET_MODE (reg
), SUBREG_BYTE (x
));
4128 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4134 /* Scan all the operand sub-expressions. */
4135 fmt
= GET_RTX_FORMAT (code
);
4136 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4139 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4140 else if (fmt
[i
] == 'E')
4141 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4143 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4148 /* Similar to loc_equivalence_change_p, but for use as
4149 simplify_replace_fn_rtx callback. DATA is insn for which the
4150 elimination is done. If it null we don't do the elimination. */
4152 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4157 rtx subst
= (data
== NULL
4158 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4165 /* Maximum number of generated reload insns per an insn. It is for
4166 preventing this pass cycling in a bug case. */
4167 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4169 /* The current iteration number of this LRA pass. */
4170 int lra_constraint_iter
;
4172 /* True if we substituted equiv which needs checking register
4173 allocation correctness because the equivalent value contains
4174 allocatable hard registers or when we restore multi-register
4176 bool lra_risky_transformations_p
;
4178 /* Return true if REGNO is referenced in more than one block. */
4180 multi_block_pseudo_p (int regno
)
4182 basic_block bb
= NULL
;
4186 if (regno
< FIRST_PSEUDO_REGISTER
)
4189 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4191 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4192 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4197 /* Return true if LIST contains a deleted insn. */
4199 contains_deleted_insn_p (rtx_insn_list
*list
)
4201 for (; list
!= NULL_RTX
; list
= list
->next ())
4202 if (NOTE_P (list
->insn ())
4203 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4208 /* Return true if X contains a pseudo dying in INSN. */
4210 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4217 return (insn
!= NULL_RTX
4218 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4219 code
= GET_CODE (x
);
4220 fmt
= GET_RTX_FORMAT (code
);
4221 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4225 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4228 else if (fmt
[i
] == 'E')
4230 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4231 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4238 /* Return true if INSN contains a dying pseudo in INSN right hand
4241 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4243 rtx set
= single_set (insn
);
4245 gcc_assert (set
!= NULL
);
4246 return dead_pseudo_p (SET_SRC (set
), insn
);
4249 /* Return true if any init insn of REGNO contains a dying pseudo in
4250 insn right hand side. */
4252 init_insn_rhs_dead_pseudo_p (int regno
)
4254 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4258 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4259 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4264 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4265 reverse only if we have one init insn with given REGNO as a
4268 reverse_equiv_p (int regno
)
4270 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4275 if (! INSN_P (insns
->insn ())
4276 || insns
->next () != NULL
)
4278 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4280 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4283 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4284 call this function only for non-reverse equivalence. */
4286 contains_reloaded_insn_p (int regno
)
4289 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4291 for (; list
!= NULL
; list
= list
->next ())
4292 if ((set
= single_set (list
->insn ())) == NULL_RTX
4293 || ! REG_P (SET_DEST (set
))
4294 || (int) REGNO (SET_DEST (set
)) != regno
)
4299 /* Entry function of LRA constraint pass. Return true if the
4300 constraint pass did change the code. */
4302 lra_constraints (bool first_p
)
4305 int i
, hard_regno
, new_insns_num
;
4306 unsigned int min_len
, new_min_len
, uid
;
4307 rtx set
, x
, reg
, dest_reg
;
4308 basic_block last_bb
;
4309 bitmap_head equiv_insn_bitmap
;
4312 lra_constraint_iter
++;
4313 if (lra_dump_file
!= NULL
)
4314 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4315 lra_constraint_iter
);
4317 if (pic_offset_table_rtx
4318 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4319 lra_risky_transformations_p
= true;
4321 lra_risky_transformations_p
= false;
4322 new_insn_uid_start
= get_max_uid ();
4323 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4324 /* Mark used hard regs for target stack size calulations. */
4325 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4326 if (lra_reg_info
[i
].nrefs
!= 0
4327 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4331 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4332 for (j
= 0; j
< nregs
; j
++)
4333 df_set_regs_ever_live (hard_regno
+ j
, true);
4335 /* Do elimination before the equivalence processing as we can spill
4336 some pseudos during elimination. */
4337 lra_eliminate (false, first_p
);
4338 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4339 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4340 if (lra_reg_info
[i
].nrefs
!= 0)
4342 ira_reg_equiv
[i
].profitable_p
= true;
4343 reg
= regno_reg_rtx
[i
];
4344 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4346 bool pseudo_p
= contains_reg_p (x
, false, false);
4348 /* After RTL transformation, we can not guarantee that
4349 pseudo in the substitution was not reloaded which might
4350 make equivalence invalid. For example, in reverse
4357 the memory address register was reloaded before the 2nd
4359 if ((! first_p
&& pseudo_p
)
4360 /* We don't use DF for compilation speed sake. So it
4361 is problematic to update live info when we use an
4362 equivalence containing pseudos in more than one
4364 || (pseudo_p
&& multi_block_pseudo_p (i
))
4365 /* If an init insn was deleted for some reason, cancel
4366 the equiv. We could update the equiv insns after
4367 transformations including an equiv insn deletion
4368 but it is not worthy as such cases are extremely
4370 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4371 /* If it is not a reverse equivalence, we check that a
4372 pseudo in rhs of the init insn is not dying in the
4373 insn. Otherwise, the live info at the beginning of
4374 the corresponding BB might be wrong after we
4375 removed the insn. When the equiv can be a
4376 constant, the right hand side of the init insn can
4378 || (! reverse_equiv_p (i
)
4379 && (init_insn_rhs_dead_pseudo_p (i
)
4380 /* If we reloaded the pseudo in an equivalence
4381 init insn, we can not remove the equiv init
4382 insns and the init insns might write into
4383 const memory in this case. */
4384 || contains_reloaded_insn_p (i
)))
4385 /* Prevent access beyond equivalent memory for
4386 paradoxical subregs. */
4388 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4389 > GET_MODE_SIZE (GET_MODE (x
))))
4390 || (pic_offset_table_rtx
4391 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4392 && (targetm
.preferred_reload_class
4393 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4394 || contains_symbol_ref_p (x
))))
4395 ira_reg_equiv
[i
].defined_p
= false;
4396 if (contains_reg_p (x
, false, true))
4397 ira_reg_equiv
[i
].profitable_p
= false;
4398 if (get_equiv (reg
) != reg
)
4399 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4402 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4404 /* We should add all insns containing pseudos which should be
4405 substituted by their equivalences. */
4406 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4407 lra_push_insn_by_uid (uid
);
4408 min_len
= lra_insn_stack_length ();
4412 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4414 curr_insn
= lra_pop_insn ();
4416 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4417 if (curr_bb
!= last_bb
)
4420 bb_reload_num
= lra_curr_reload_num
;
4422 if (min_len
> new_min_len
)
4424 min_len
= new_min_len
;
4427 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4429 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4430 MAX_RELOAD_INSNS_NUMBER
);
4432 if (DEBUG_INSN_P (curr_insn
))
4434 /* We need to check equivalence in debug insn and change
4435 pseudo to the equivalent value if necessary. */
4436 curr_id
= lra_get_insn_recog_data (curr_insn
);
4437 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4439 rtx old
= *curr_id
->operand_loc
[0];
4440 *curr_id
->operand_loc
[0]
4441 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4442 loc_equivalence_callback
, curr_insn
);
4443 if (old
!= *curr_id
->operand_loc
[0])
4445 lra_update_insn_regno_info (curr_insn
);
4450 else if (INSN_P (curr_insn
))
4452 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4454 dest_reg
= SET_DEST (set
);
4455 /* The equivalence pseudo could be set up as SUBREG in a
4456 case when it is a call restore insn in a mode
4457 different from the pseudo mode. */
4458 if (GET_CODE (dest_reg
) == SUBREG
)
4459 dest_reg
= SUBREG_REG (dest_reg
);
4460 if ((REG_P (dest_reg
)
4461 && (x
= get_equiv (dest_reg
)) != dest_reg
4462 /* Remove insns which set up a pseudo whose value
4463 can not be changed. Such insns might be not in
4464 init_insns because we don't update equiv data
4465 during insn transformations.
4467 As an example, let suppose that a pseudo got
4468 hard register and on the 1st pass was not
4469 changed to equivalent constant. We generate an
4470 additional insn setting up the pseudo because of
4471 secondary memory movement. Then the pseudo is
4472 spilled and we use the equiv constant. In this
4473 case we should remove the additional insn and
4474 this insn is not init_insns list. */
4475 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4476 /* Check that this is actually an insn setting
4477 up the equivalence. */
4478 || in_list_p (curr_insn
,
4480 [REGNO (dest_reg
)].init_insns
)))
4481 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4482 && in_list_p (curr_insn
,
4484 [REGNO (SET_SRC (set
))].init_insns
)))
4486 /* This is equiv init insn of pseudo which did not get a
4487 hard register -- remove the insn. */
4488 if (lra_dump_file
!= NULL
)
4490 fprintf (lra_dump_file
,
4491 " Removing equiv init insn %i (freq=%d)\n",
4492 INSN_UID (curr_insn
),
4493 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4494 dump_insn_slim (lra_dump_file
, curr_insn
);
4496 if (contains_reg_p (x
, true, false))
4497 lra_risky_transformations_p
= true;
4498 lra_set_insn_deleted (curr_insn
);
4502 curr_id
= lra_get_insn_recog_data (curr_insn
);
4503 curr_static_id
= curr_id
->insn_static_data
;
4504 init_curr_insn_input_reloads ();
4505 init_curr_operand_mode ();
4506 if (curr_insn_transform (false))
4508 /* Check non-transformed insns too for equiv change as USE
4509 or CLOBBER don't need reloads but can contain pseudos
4510 being changed on their equivalences. */
4511 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4512 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4514 lra_update_insn_regno_info (curr_insn
);
4519 bitmap_clear (&equiv_insn_bitmap
);
4520 /* If we used a new hard regno, changed_p should be true because the
4521 hard reg is assigned to a new pseudo. */
4522 if (flag_checking
&& !changed_p
)
4524 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4525 if (lra_reg_info
[i
].nrefs
!= 0
4526 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4528 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4530 for (j
= 0; j
< nregs
; j
++)
4531 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4537 /* Initiate the LRA constraint pass. It is done once per
4540 lra_constraints_init (void)
4544 /* Finalize the LRA constraint pass. It is done once per
4547 lra_constraints_finish (void)
4553 /* This page contains code to do inheritance/split
4556 /* Number of reloads passed so far in current EBB. */
4557 static int reloads_num
;
4559 /* Number of calls passed so far in current EBB. */
4560 static int calls_num
;
4562 /* Current reload pseudo check for validity of elements in
4564 static int curr_usage_insns_check
;
4566 /* Info about last usage of registers in EBB to do inheritance/split
4567 transformation. Inheritance transformation is done from a spilled
4568 pseudo and split transformations from a hard register or a pseudo
4569 assigned to a hard register. */
4572 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4573 value INSNS is valid. The insns is chain of optional debug insns
4574 and a finishing non-debug insn using the corresponding reg. The
4575 value is also used to mark the registers which are set up in the
4576 current insn. The negated insn uid is used for this. */
4578 /* Value of global reloads_num at the last insn in INSNS. */
4580 /* Value of global reloads_nums at the last insn in INSNS. */
4582 /* It can be true only for splitting. And it means that the restore
4583 insn should be put after insn given by the following member. */
4585 /* Next insns in the current EBB which use the original reg and the
4586 original reg value is not changed between the current insn and
4587 the next insns. In order words, e.g. for inheritance, if we need
4588 to use the original reg value again in the next insns we can try
4589 to use the value in a hard register from a reload insn of the
4594 /* Map: regno -> corresponding pseudo usage insns. */
4595 static struct usage_insns
*usage_insns
;
4598 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4600 usage_insns
[regno
].check
= curr_usage_insns_check
;
4601 usage_insns
[regno
].insns
= insn
;
4602 usage_insns
[regno
].reloads_num
= reloads_num
;
4603 usage_insns
[regno
].calls_num
= calls_num
;
4604 usage_insns
[regno
].after_p
= after_p
;
4607 /* The function is used to form list REGNO usages which consists of
4608 optional debug insns finished by a non-debug insn using REGNO.
4609 RELOADS_NUM is current number of reload insns processed so far. */
4611 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
4613 rtx next_usage_insns
;
4615 if (usage_insns
[regno
].check
== curr_usage_insns_check
4616 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4617 && DEBUG_INSN_P (insn
))
4619 /* Check that we did not add the debug insn yet. */
4620 if (next_usage_insns
!= insn
4621 && (GET_CODE (next_usage_insns
) != INSN_LIST
4622 || XEXP (next_usage_insns
, 0) != insn
))
4623 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4626 else if (NONDEBUG_INSN_P (insn
))
4627 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4629 usage_insns
[regno
].check
= 0;
4632 /* Return first non-debug insn in list USAGE_INSNS. */
4634 skip_usage_debug_insns (rtx usage_insns
)
4638 /* Skip debug insns. */
4639 for (insn
= usage_insns
;
4640 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4641 insn
= XEXP (insn
, 1))
4643 return safe_as_a
<rtx_insn
*> (insn
);
4646 /* Return true if we need secondary memory moves for insn in
4647 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4650 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4651 rtx usage_insns ATTRIBUTE_UNUSED
)
4653 #ifndef SECONDARY_MEMORY_NEEDED
4660 if (inher_cl
== ALL_REGS
4661 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4663 lra_assert (INSN_P (insn
));
4664 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4666 dest
= SET_DEST (set
);
4669 lra_assert (inher_cl
!= NO_REGS
);
4670 cl
= get_reg_class (REGNO (dest
));
4671 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4672 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4676 /* Registers involved in inheritance/split in the current EBB
4677 (inheritance/split pseudos and original registers). */
4678 static bitmap_head check_only_regs
;
4680 /* Do inheritance transformations for insn INSN, which defines (if
4681 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4682 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4683 form as the "insns" field of usage_insns. Return true if we
4684 succeed in such transformation.
4686 The transformations look like:
4689 ... p <- i (new insn)
4691 <- ... p ... <- ... i ...
4693 ... i <- p (new insn)
4694 <- ... p ... <- ... i ...
4696 <- ... p ... <- ... i ...
4697 where p is a spilled original pseudo and i is a new inheritance pseudo.
4700 The inheritance pseudo has the smallest class of two classes CL and
4701 class of ORIGINAL REGNO. */
4703 inherit_reload_reg (bool def_p
, int original_regno
,
4704 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4706 if (optimize_function_for_size_p (cfun
))
4709 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4710 rtx original_reg
= regno_reg_rtx
[original_regno
];
4711 rtx new_reg
, usage_insn
;
4712 rtx_insn
*new_insns
;
4714 lra_assert (! usage_insns
[original_regno
].after_p
);
4715 if (lra_dump_file
!= NULL
)
4716 fprintf (lra_dump_file
,
4717 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4718 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4720 if (lra_dump_file
!= NULL
)
4722 fprintf (lra_dump_file
,
4723 " Rejecting inheritance for %d "
4724 "because of disjoint classes %s and %s\n",
4725 original_regno
, reg_class_names
[cl
],
4726 reg_class_names
[rclass
]);
4727 fprintf (lra_dump_file
,
4728 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4732 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4733 /* We don't use a subset of two classes because it can be
4734 NO_REGS. This transformation is still profitable in most
4735 cases even if the classes are not intersected as register
4736 move is probably cheaper than a memory load. */
4737 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4739 if (lra_dump_file
!= NULL
)
4740 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4741 reg_class_names
[cl
], reg_class_names
[rclass
]);
4745 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4747 /* Reject inheritance resulting in secondary memory moves.
4748 Otherwise, there is a danger in LRA cycling. Also such
4749 transformation will be unprofitable. */
4750 if (lra_dump_file
!= NULL
)
4752 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
4753 rtx set
= single_set (insn
);
4755 lra_assert (set
!= NULL_RTX
);
4757 rtx dest
= SET_DEST (set
);
4759 lra_assert (REG_P (dest
));
4760 fprintf (lra_dump_file
,
4761 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4762 "as secondary mem is needed\n",
4763 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4764 original_regno
, reg_class_names
[rclass
]);
4765 fprintf (lra_dump_file
,
4766 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4770 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4771 rclass
, "inheritance");
4774 lra_emit_move (original_reg
, new_reg
);
4776 lra_emit_move (new_reg
, original_reg
);
4777 new_insns
= get_insns ();
4779 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4781 if (lra_dump_file
!= NULL
)
4783 fprintf (lra_dump_file
,
4784 " Rejecting inheritance %d->%d "
4785 "as it results in 2 or more insns:\n",
4786 original_regno
, REGNO (new_reg
));
4787 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
4788 fprintf (lra_dump_file
,
4789 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4793 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
4794 lra_update_insn_regno_info (insn
);
4796 /* We now have a new usage insn for original regno. */
4797 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4798 if (lra_dump_file
!= NULL
)
4799 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4800 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4801 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4802 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4803 bitmap_set_bit (&check_only_regs
, original_regno
);
4804 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4806 lra_process_new_insns (insn
, NULL
, new_insns
,
4807 "Add original<-inheritance");
4809 lra_process_new_insns (insn
, new_insns
, NULL
,
4810 "Add inheritance<-original");
4811 while (next_usage_insns
!= NULL_RTX
)
4813 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4815 usage_insn
= next_usage_insns
;
4816 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4817 next_usage_insns
= NULL
;
4821 usage_insn
= XEXP (next_usage_insns
, 0);
4822 lra_assert (DEBUG_INSN_P (usage_insn
));
4823 next_usage_insns
= XEXP (next_usage_insns
, 1);
4825 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
4826 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4827 if (lra_dump_file
!= NULL
)
4829 fprintf (lra_dump_file
,
4830 " Inheritance reuse change %d->%d (bb%d):\n",
4831 original_regno
, REGNO (new_reg
),
4832 BLOCK_FOR_INSN (usage_insn
)->index
);
4833 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
4836 if (lra_dump_file
!= NULL
)
4837 fprintf (lra_dump_file
,
4838 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4842 /* Return true if we need a caller save/restore for pseudo REGNO which
4843 was assigned to a hard register. */
4845 need_for_call_save_p (int regno
)
4847 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4848 return (usage_insns
[regno
].calls_num
< calls_num
4849 && (overlaps_hard_reg_set_p
4851 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4852 ? lra_reg_info
[regno
].actual_call_used_reg_set
4853 : call_used_reg_set
,
4854 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4855 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4856 PSEUDO_REGNO_MODE (regno
))));
4859 /* Global registers occurring in the current EBB. */
4860 static bitmap_head ebb_global_regs
;
4862 /* Return true if we need a split for hard register REGNO or pseudo
4863 REGNO which was assigned to a hard register.
4864 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4865 used for reloads since the EBB end. It is an approximation of the
4866 used hard registers in the split range. The exact value would
4867 require expensive calculations. If we were aggressive with
4868 splitting because of the approximation, the split pseudo will save
4869 the same hard register assignment and will be removed in the undo
4870 pass. We still need the approximation because too aggressive
4871 splitting would result in too inaccurate cost calculation in the
4872 assignment pass because of too many generated moves which will be
4873 probably removed in the undo pass. */
4875 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4877 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4879 lra_assert (hard_regno
>= 0);
4880 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4881 /* Don't split eliminable hard registers, otherwise we can
4882 split hard registers like hard frame pointer, which
4883 lives on BB start/end according to DF-infrastructure,
4884 when there is a pseudo assigned to the register and
4885 living in the same BB. */
4886 && (regno
>= FIRST_PSEUDO_REGISTER
4887 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4888 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4889 /* Don't split call clobbered hard regs living through
4890 calls, otherwise we might have a check problem in the
4891 assign sub-pass as in the most cases (exception is a
4892 situation when lra_risky_transformations_p value is
4893 true) the assign pass assumes that all pseudos living
4894 through calls are assigned to call saved hard regs. */
4895 && (regno
>= FIRST_PSEUDO_REGISTER
4896 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4897 || usage_insns
[regno
].calls_num
== calls_num
)
4898 /* We need at least 2 reloads to make pseudo splitting
4899 profitable. We should provide hard regno splitting in
4900 any case to solve 1st insn scheduling problem when
4901 moving hard register definition up might result in
4902 impossibility to find hard register for reload pseudo of
4903 small register class. */
4904 && (usage_insns
[regno
].reloads_num
4905 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4906 && (regno
< FIRST_PSEUDO_REGISTER
4907 /* For short living pseudos, spilling + inheritance can
4908 be considered a substitution for splitting.
4909 Therefore we do not splitting for local pseudos. It
4910 decreases also aggressiveness of splitting. The
4911 minimal number of references is chosen taking into
4912 account that for 2 references splitting has no sense
4913 as we can just spill the pseudo. */
4914 || (regno
>= FIRST_PSEUDO_REGISTER
4915 && lra_reg_info
[regno
].nrefs
> 3
4916 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4917 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4920 /* Return class for the split pseudo created from original pseudo with
4921 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4922 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4923 results in no secondary memory movements. */
4924 static enum reg_class
4925 choose_split_class (enum reg_class allocno_class
,
4926 int hard_regno ATTRIBUTE_UNUSED
,
4927 machine_mode mode ATTRIBUTE_UNUSED
)
4929 #ifndef SECONDARY_MEMORY_NEEDED
4930 return allocno_class
;
4933 enum reg_class cl
, best_cl
= NO_REGS
;
4934 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4935 = REGNO_REG_CLASS (hard_regno
);
4937 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4938 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4939 return allocno_class
;
4941 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4943 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4944 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4945 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4946 && (best_cl
== NO_REGS
4947 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4953 /* Do split transformations for insn INSN, which defines or uses
4954 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4955 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4956 "insns" field of usage_insns.
4958 The transformations look like:
4961 ... s <- p (new insn -- save)
4963 ... p <- s (new insn -- restore)
4964 <- ... p ... <- ... p ...
4966 <- ... p ... <- ... p ...
4967 ... s <- p (new insn -- save)
4969 ... p <- s (new insn -- restore)
4970 <- ... p ... <- ... p ...
4972 where p is an original pseudo got a hard register or a hard
4973 register and s is a new split pseudo. The save is put before INSN
4974 if BEFORE_P is true. Return true if we succeed in such
4977 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
4978 rtx next_usage_insns
)
4980 enum reg_class rclass
;
4982 int hard_regno
, nregs
;
4983 rtx new_reg
, usage_insn
;
4984 rtx_insn
*restore
, *save
;
4989 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4991 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4992 hard_regno
= original_regno
;
4993 call_save_p
= false;
4995 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
4996 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
4997 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
4998 as part of a multi-word register. In that case, or if the biggest
4999 mode was larger than a register, just use the reg_rtx. Otherwise,
5000 limit the size to that of the biggest access in the function. */
5001 if (mode
== VOIDmode
5002 || GET_MODE_SIZE (mode
) > GET_MODE_SIZE (reg_rtx_mode
))
5004 original_reg
= regno_reg_rtx
[hard_regno
];
5005 mode
= reg_rtx_mode
;
5008 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5012 mode
= PSEUDO_REGNO_MODE (original_regno
);
5013 hard_regno
= reg_renumber
[original_regno
];
5014 nregs
= hard_regno_nregs
[hard_regno
][mode
];
5015 rclass
= lra_get_allocno_class (original_regno
);
5016 original_reg
= regno_reg_rtx
[original_regno
];
5017 call_save_p
= need_for_call_save_p (original_regno
);
5019 lra_assert (hard_regno
>= 0);
5020 if (lra_dump_file
!= NULL
)
5021 fprintf (lra_dump_file
,
5022 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5026 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5027 hard_regno_nregs
[hard_regno
][mode
],
5029 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5033 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5034 if (rclass
== NO_REGS
)
5036 if (lra_dump_file
!= NULL
)
5038 fprintf (lra_dump_file
,
5039 " Rejecting split of %d(%s): "
5040 "no good reg class for %d(%s)\n",
5042 reg_class_names
[lra_get_allocno_class (original_regno
)],
5044 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5047 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5051 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5052 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5054 save
= emit_spill_move (true, new_reg
, original_reg
);
5055 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5057 if (lra_dump_file
!= NULL
)
5061 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5062 original_regno
, REGNO (new_reg
));
5063 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5064 fprintf (lra_dump_file
,
5065 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5069 restore
= emit_spill_move (false, new_reg
, original_reg
);
5070 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5072 if (lra_dump_file
!= NULL
)
5074 fprintf (lra_dump_file
,
5075 " Rejecting split %d->%d "
5076 "resulting in > 2 restore insns:\n",
5077 original_regno
, REGNO (new_reg
));
5078 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5079 fprintf (lra_dump_file
,
5080 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5084 after_p
= usage_insns
[original_regno
].after_p
;
5085 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
5086 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5087 bitmap_set_bit (&check_only_regs
, original_regno
);
5088 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
5091 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5093 usage_insn
= next_usage_insns
;
5096 usage_insn
= XEXP (next_usage_insns
, 0);
5097 lra_assert (DEBUG_INSN_P (usage_insn
));
5098 next_usage_insns
= XEXP (next_usage_insns
, 1);
5099 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5100 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5101 if (lra_dump_file
!= NULL
)
5103 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5104 original_regno
, REGNO (new_reg
));
5105 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5108 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5109 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5110 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5111 after_p
? NULL
: restore
,
5112 after_p
? restore
: NULL
,
5114 ? "Add reg<-save" : "Add reg<-split");
5115 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5116 before_p
? NULL
: save
,
5118 ? "Add save<-reg" : "Add split<-reg");
5120 /* If we are trying to split multi-register. We should check
5121 conflicts on the next assignment sub-pass. IRA can allocate on
5122 sub-register levels, LRA do this on pseudos level right now and
5123 this discrepancy may create allocation conflicts after
5125 lra_risky_transformations_p
= true;
5126 if (lra_dump_file
!= NULL
)
5127 fprintf (lra_dump_file
,
5128 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5132 /* Recognize that we need a split transformation for insn INSN, which
5133 defines or uses REGNO in its insn biggest MODE (we use it only if
5134 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5135 hard registers which might be used for reloads since the EBB end.
5136 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5137 uid before starting INSN processing. Return true if we succeed in
5138 such transformation. */
5140 split_if_necessary (int regno
, machine_mode mode
,
5141 HARD_REG_SET potential_reload_hard_regs
,
5142 bool before_p
, rtx_insn
*insn
, int max_uid
)
5146 rtx next_usage_insns
;
5148 if (regno
< FIRST_PSEUDO_REGISTER
)
5149 nregs
= hard_regno_nregs
[regno
][mode
];
5150 for (i
= 0; i
< nregs
; i
++)
5151 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5152 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5153 /* To avoid processing the register twice or more. */
5154 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5155 && INSN_UID (next_usage_insns
) < max_uid
)
5156 || (GET_CODE (next_usage_insns
) == INSN_LIST
5157 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5158 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5159 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5164 /* Check only registers living at the current program point in the
5166 static bitmap_head live_regs
;
5168 /* Update live info in EBB given by its HEAD and TAIL insns after
5169 inheritance/split transformation. The function removes dead moves
5172 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5177 rtx_insn
*prev_insn
;
5180 basic_block last_bb
, prev_bb
, curr_bb
;
5182 struct lra_insn_reg
*reg
;
5186 last_bb
= BLOCK_FOR_INSN (tail
);
5188 for (curr_insn
= tail
;
5189 curr_insn
!= PREV_INSN (head
);
5190 curr_insn
= prev_insn
)
5192 prev_insn
= PREV_INSN (curr_insn
);
5193 /* We need to process empty blocks too. They contain
5194 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5195 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5197 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5198 if (curr_bb
!= prev_bb
)
5200 if (prev_bb
!= NULL
)
5202 /* Update df_get_live_in (prev_bb): */
5203 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5204 if (bitmap_bit_p (&live_regs
, j
))
5205 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5207 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5209 if (curr_bb
!= last_bb
)
5211 /* Update df_get_live_out (curr_bb): */
5212 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5214 live_p
= bitmap_bit_p (&live_regs
, j
);
5216 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5217 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5223 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5225 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5229 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5231 if (! NONDEBUG_INSN_P (curr_insn
))
5233 curr_id
= lra_get_insn_recog_data (curr_insn
);
5234 curr_static_id
= curr_id
->insn_static_data
;
5236 if ((set
= single_set (curr_insn
)) != NULL_RTX
5237 && REG_P (SET_DEST (set
))
5238 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5239 && SET_DEST (set
) != pic_offset_table_rtx
5240 && bitmap_bit_p (&check_only_regs
, regno
)
5241 && ! bitmap_bit_p (&live_regs
, regno
))
5243 /* See which defined values die here. */
5244 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5245 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5246 bitmap_clear_bit (&live_regs
, reg
->regno
);
5247 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5248 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5249 bitmap_clear_bit (&live_regs
, reg
->regno
);
5250 if (curr_id
->arg_hard_regs
!= NULL
)
5251 /* Make clobbered argument hard registers die. */
5252 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5253 if (regno
>= FIRST_PSEUDO_REGISTER
)
5254 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5255 /* Mark each used value as live. */
5256 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5257 if (reg
->type
!= OP_OUT
5258 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5259 bitmap_set_bit (&live_regs
, reg
->regno
);
5260 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5261 if (reg
->type
!= OP_OUT
5262 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5263 bitmap_set_bit (&live_regs
, reg
->regno
);
5264 if (curr_id
->arg_hard_regs
!= NULL
)
5265 /* Make used argument hard registers live. */
5266 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5267 if (regno
< FIRST_PSEUDO_REGISTER
5268 && bitmap_bit_p (&check_only_regs
, regno
))
5269 bitmap_set_bit (&live_regs
, regno
);
5270 /* It is quite important to remove dead move insns because it
5271 means removing dead store. We don't need to process them for
5275 if (lra_dump_file
!= NULL
)
5277 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5278 dump_insn_slim (lra_dump_file
, curr_insn
);
5280 lra_set_insn_deleted (curr_insn
);
5285 /* The structure describes info to do an inheritance for the current
5286 insn. We need to collect such info first before doing the
5287 transformations because the transformations change the insn
5288 internal representation. */
5291 /* Original regno. */
5293 /* Subsequent insns which can inherit original reg value. */
5297 /* Array containing all info for doing inheritance from the current
5299 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5301 /* Number elements in the previous array. */
5302 static int to_inherit_num
;
5304 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5305 structure to_inherit. */
5307 add_to_inherit (int regno
, rtx insns
)
5311 for (i
= 0; i
< to_inherit_num
; i
++)
5312 if (to_inherit
[i
].regno
== regno
)
5314 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5315 to_inherit
[to_inherit_num
].regno
= regno
;
5316 to_inherit
[to_inherit_num
++].insns
= insns
;
5319 /* Return the last non-debug insn in basic block BB, or the block begin
5322 get_last_insertion_point (basic_block bb
)
5326 FOR_BB_INSNS_REVERSE (bb
, insn
)
5327 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5332 /* Set up RES by registers living on edges FROM except the edge (FROM,
5333 TO) or by registers set up in a jump insn in BB FROM. */
5335 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5338 struct lra_insn_reg
*reg
;
5342 lra_assert (to
!= NULL
);
5344 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5346 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5347 last
= get_last_insertion_point (from
);
5348 if (! JUMP_P (last
))
5350 curr_id
= lra_get_insn_recog_data (last
);
5351 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5352 if (reg
->type
!= OP_IN
)
5353 bitmap_set_bit (res
, reg
->regno
);
5356 /* Used as a temporary results of some bitmap calculations. */
5357 static bitmap_head temp_bitmap
;
5359 /* We split for reloads of small class of hard regs. The following
5360 defines how many hard regs the class should have to be qualified as
5361 small. The code is mostly oriented to x86/x86-64 architecture
5362 where some insns need to use only specific register or pair of
5363 registers and these register can live in RTL explicitly, e.g. for
5364 parameter passing. */
5365 static const int max_small_class_regs_num
= 2;
5367 /* Do inheritance/split transformations in EBB starting with HEAD and
5368 finishing on TAIL. We process EBB insns in the reverse order.
5369 Return true if we did any inheritance/split transformation in the
5372 We should avoid excessive splitting which results in worse code
5373 because of inaccurate cost calculations for spilling new split
5374 pseudos in such case. To achieve this we do splitting only if
5375 register pressure is high in given basic block and there are reload
5376 pseudos requiring hard registers. We could do more register
5377 pressure calculations at any given program point to avoid necessary
5378 splitting even more but it is to expensive and the current approach
5379 works well enough. */
5381 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5383 int i
, src_regno
, dst_regno
, nregs
;
5384 bool change_p
, succ_p
, update_reloads_num_p
;
5385 rtx_insn
*prev_insn
, *last_insn
;
5386 rtx next_usage_insns
, set
;
5388 struct lra_insn_reg
*reg
;
5389 basic_block last_processed_bb
, curr_bb
= NULL
;
5390 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5394 bool head_p
, after_p
;
5397 curr_usage_insns_check
++;
5398 reloads_num
= calls_num
= 0;
5399 bitmap_clear (&check_only_regs
);
5400 last_processed_bb
= NULL
;
5401 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5402 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5403 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5404 /* We don't process new insns generated in the loop. */
5405 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5407 prev_insn
= PREV_INSN (curr_insn
);
5408 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5409 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5410 if (last_processed_bb
!= curr_bb
)
5412 /* We are at the end of BB. Add qualified living
5413 pseudos for potential splitting. */
5414 to_process
= df_get_live_out (curr_bb
);
5415 if (last_processed_bb
!= NULL
)
5417 /* We are somewhere in the middle of EBB. */
5418 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5420 to_process
= &temp_bitmap
;
5422 last_processed_bb
= curr_bb
;
5423 last_insn
= get_last_insertion_point (curr_bb
);
5424 after_p
= (! JUMP_P (last_insn
)
5425 && (! CALL_P (last_insn
)
5426 || (find_reg_note (last_insn
,
5427 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5428 && ! SIBLING_CALL_P (last_insn
))));
5429 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5430 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5432 if ((int) j
>= lra_constraint_new_regno_start
)
5434 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5436 if (j
< FIRST_PSEUDO_REGISTER
)
5437 SET_HARD_REG_BIT (live_hard_regs
, j
);
5439 add_to_hard_reg_set (&live_hard_regs
,
5440 PSEUDO_REGNO_MODE (j
),
5442 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5446 src_regno
= dst_regno
= -1;
5447 if (NONDEBUG_INSN_P (curr_insn
)
5448 && (set
= single_set (curr_insn
)) != NULL_RTX
5449 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5451 src_regno
= REGNO (SET_SRC (set
));
5452 dst_regno
= REGNO (SET_DEST (set
));
5454 update_reloads_num_p
= true;
5455 if (src_regno
< lra_constraint_new_regno_start
5456 && src_regno
>= FIRST_PSEUDO_REGISTER
5457 && reg_renumber
[src_regno
] < 0
5458 && dst_regno
>= lra_constraint_new_regno_start
5459 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5461 /* 'reload_pseudo <- original_pseudo'. */
5462 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5464 update_reloads_num_p
= false;
5466 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5467 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5468 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5469 curr_insn
, next_usage_insns
);
5473 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5474 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5475 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5476 reg_class_contents
[cl
]);
5478 else if (src_regno
>= lra_constraint_new_regno_start
5479 && dst_regno
< lra_constraint_new_regno_start
5480 && dst_regno
>= FIRST_PSEUDO_REGISTER
5481 && reg_renumber
[dst_regno
] < 0
5482 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5483 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5484 && (next_usage_insns
5485 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5487 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5489 update_reloads_num_p
= false;
5490 /* 'original_pseudo <- reload_pseudo'. */
5491 if (! JUMP_P (curr_insn
)
5492 && inherit_reload_reg (true, dst_regno
, cl
,
5493 curr_insn
, next_usage_insns
))
5496 usage_insns
[dst_regno
].check
= 0;
5497 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5498 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5499 reg_class_contents
[cl
]);
5501 else if (INSN_P (curr_insn
))
5504 int max_uid
= get_max_uid ();
5506 curr_id
= lra_get_insn_recog_data (curr_insn
);
5507 curr_static_id
= curr_id
->insn_static_data
;
5509 /* Process insn definitions. */
5510 for (iter
= 0; iter
< 2; iter
++)
5511 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5514 if (reg
->type
!= OP_IN
5515 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5517 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5518 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5519 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5520 && (next_usage_insns
5521 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5523 struct lra_insn_reg
*r
;
5525 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5526 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5528 /* Don't do inheritance if the pseudo is also
5529 used in the insn. */
5531 /* We can not do inheritance right now
5532 because the current insn reg info (chain
5533 regs) can change after that. */
5534 add_to_inherit (dst_regno
, next_usage_insns
);
5536 /* We can not process one reg twice here because of
5537 usage_insns invalidation. */
5538 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5539 || reg_renumber
[dst_regno
] >= 0)
5540 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5544 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5545 potential_reload_hard_regs
,
5546 false, curr_insn
, max_uid
))
5548 CLEAR_HARD_REG_SET (s
);
5549 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5550 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5552 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5553 reg_renumber
[dst_regno
]);
5554 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5556 /* We should invalidate potential inheritance or
5557 splitting for the current insn usages to the next
5558 usage insns (see code below) as the output pseudo
5560 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5561 && reg_renumber
[dst_regno
] < 0)
5562 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5563 && (dst_regno
< FIRST_PSEUDO_REGISTER
5564 || reg_renumber
[dst_regno
] >= 0)))
5566 /* Invalidate and mark definitions. */
5567 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5568 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5571 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5572 for (i
= 0; i
< nregs
; i
++)
5573 usage_insns
[dst_regno
+ i
].check
5574 = -(int) INSN_UID (curr_insn
);
5578 /* Process clobbered call regs. */
5579 if (curr_id
->arg_hard_regs
!= NULL
)
5580 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5581 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5582 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
5583 = -(int) INSN_UID (curr_insn
);
5584 if (! JUMP_P (curr_insn
))
5585 for (i
= 0; i
< to_inherit_num
; i
++)
5586 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5587 ALL_REGS
, curr_insn
,
5588 to_inherit
[i
].insns
))
5590 if (CALL_P (curr_insn
))
5592 rtx cheap
, pat
, dest
;
5594 int regno
, hard_regno
;
5597 if ((cheap
= find_reg_note (curr_insn
,
5598 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5599 && ((cheap
= XEXP (cheap
, 0)), true)
5600 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5601 && (hard_regno
= reg_renumber
[regno
]) >= 0
5602 /* If there are pending saves/restores, the
5603 optimization is not worth. */
5604 && usage_insns
[regno
].calls_num
== calls_num
- 1
5605 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5607 /* Restore the pseudo from the call result as
5608 REG_RETURNED note says that the pseudo value is
5609 in the call result and the pseudo is an argument
5611 pat
= PATTERN (curr_insn
);
5612 if (GET_CODE (pat
) == PARALLEL
)
5613 pat
= XVECEXP (pat
, 0, 0);
5614 dest
= SET_DEST (pat
);
5615 /* For multiple return values dest is PARALLEL.
5616 Currently we handle only single return value case. */
5620 emit_move_insn (cheap
, copy_rtx (dest
));
5621 restore
= get_insns ();
5623 lra_process_new_insns (curr_insn
, NULL
, restore
,
5624 "Inserting call parameter restore");
5625 /* We don't need to save/restore of the pseudo from
5627 usage_insns
[regno
].calls_num
= calls_num
;
5628 bitmap_set_bit (&check_only_regs
, regno
);
5633 /* Process insn usages. */
5634 for (iter
= 0; iter
< 2; iter
++)
5635 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5638 if ((reg
->type
!= OP_OUT
5639 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5640 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5642 if (src_regno
>= FIRST_PSEUDO_REGISTER
5643 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5645 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5646 && (next_usage_insns
5647 = usage_insns
[src_regno
].insns
) != NULL_RTX
5648 && NONDEBUG_INSN_P (curr_insn
))
5649 add_to_inherit (src_regno
, next_usage_insns
);
5650 else if (usage_insns
[src_regno
].check
5651 != -(int) INSN_UID (curr_insn
))
5652 /* Add usages but only if the reg is not set up
5653 in the same insn. */
5654 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5656 else if (src_regno
< FIRST_PSEUDO_REGISTER
5657 || reg_renumber
[src_regno
] >= 0)
5660 rtx_insn
*use_insn
= curr_insn
;
5662 before_p
= (JUMP_P (curr_insn
)
5663 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5664 if (NONDEBUG_INSN_P (curr_insn
)
5665 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5666 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5667 potential_reload_hard_regs
,
5668 before_p
, curr_insn
, max_uid
))
5671 lra_risky_transformations_p
= true;
5674 usage_insns
[src_regno
].check
= 0;
5676 use_insn
= PREV_INSN (curr_insn
);
5678 if (NONDEBUG_INSN_P (curr_insn
))
5680 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5681 add_to_hard_reg_set (&live_hard_regs
,
5682 reg
->biggest_mode
, src_regno
);
5684 add_to_hard_reg_set (&live_hard_regs
,
5685 PSEUDO_REGNO_MODE (src_regno
),
5686 reg_renumber
[src_regno
]);
5688 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5691 /* Process used call regs. */
5692 if (curr_id
->arg_hard_regs
!= NULL
)
5693 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5694 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5696 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5697 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5699 for (i
= 0; i
< to_inherit_num
; i
++)
5701 src_regno
= to_inherit
[i
].regno
;
5702 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5703 curr_insn
, to_inherit
[i
].insns
))
5706 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5709 if (update_reloads_num_p
5710 && NONDEBUG_INSN_P (curr_insn
)
5711 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5714 if ((REG_P (SET_DEST (set
))
5715 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5716 && reg_renumber
[regno
] < 0
5717 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5718 || (REG_P (SET_SRC (set
))
5719 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5720 && reg_renumber
[regno
] < 0
5721 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5723 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5725 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5726 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5727 reg_class_contents
[cl
]);
5730 /* We reached the start of the current basic block. */
5731 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5732 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5734 /* We reached the beginning of the current block -- do
5735 rest of spliting in the current BB. */
5736 to_process
= df_get_live_in (curr_bb
);
5737 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5739 /* We are somewhere in the middle of EBB. */
5740 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5741 curr_bb
, &temp_bitmap
);
5742 to_process
= &temp_bitmap
;
5745 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5747 if ((int) j
>= lra_constraint_new_regno_start
)
5749 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5750 && usage_insns
[j
].check
== curr_usage_insns_check
5751 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5753 if (need_for_split_p (potential_reload_hard_regs
, j
))
5755 if (lra_dump_file
!= NULL
&& head_p
)
5757 fprintf (lra_dump_file
,
5758 " ----------------------------------\n");
5761 if (split_reg (false, j
, bb_note (curr_bb
),
5765 usage_insns
[j
].check
= 0;
5773 /* This value affects EBB forming. If probability of edge from EBB to
5774 a BB is not greater than the following value, we don't add the BB
5776 #define EBB_PROBABILITY_CUTOFF \
5777 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
5779 /* Current number of inheritance/split iteration. */
5780 int lra_inheritance_iter
;
5782 /* Entry function for inheritance/split pass. */
5784 lra_inheritance (void)
5787 basic_block bb
, start_bb
;
5790 lra_inheritance_iter
++;
5791 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5793 timevar_push (TV_LRA_INHERITANCE
);
5794 if (lra_dump_file
!= NULL
)
5795 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5796 lra_inheritance_iter
);
5797 curr_usage_insns_check
= 0;
5798 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5799 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5800 usage_insns
[i
].check
= 0;
5801 bitmap_initialize (&check_only_regs
, ®_obstack
);
5802 bitmap_initialize (&live_regs
, ®_obstack
);
5803 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5804 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5805 FOR_EACH_BB_FN (bb
, cfun
)
5808 if (lra_dump_file
!= NULL
)
5809 fprintf (lra_dump_file
, "EBB");
5810 /* Form a EBB starting with BB. */
5811 bitmap_clear (&ebb_global_regs
);
5812 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5815 if (lra_dump_file
!= NULL
)
5816 fprintf (lra_dump_file
, " %d", bb
->index
);
5817 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5818 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5820 e
= find_fallthru_edge (bb
->succs
);
5823 if (e
->probability
< EBB_PROBABILITY_CUTOFF
)
5827 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5828 if (lra_dump_file
!= NULL
)
5829 fprintf (lra_dump_file
, "\n");
5830 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5831 /* Remember that the EBB head and tail can change in
5833 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5835 bitmap_clear (&ebb_global_regs
);
5836 bitmap_clear (&temp_bitmap
);
5837 bitmap_clear (&live_regs
);
5838 bitmap_clear (&check_only_regs
);
5841 timevar_pop (TV_LRA_INHERITANCE
);
5846 /* This page contains code to undo failed inheritance/split
5849 /* Current number of iteration undoing inheritance/split. */
5850 int lra_undo_inheritance_iter
;
5852 /* Fix BB live info LIVE after removing pseudos created on pass doing
5853 inheritance/split which are REMOVED_PSEUDOS. */
5855 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5860 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5861 if (bitmap_clear_bit (live
, regno
))
5862 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5865 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5870 if (GET_CODE (reg
) == SUBREG
)
5871 reg
= SUBREG_REG (reg
);
5877 /* Delete a move INSN with destination reg DREGNO and a previous
5878 clobber insn with the same regno. The inheritance/split code can
5879 generate moves with preceding clobber and when we delete such moves
5880 we should delete the clobber insn too to keep the correct life
5883 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
5885 rtx_insn
*prev_insn
= PREV_INSN (insn
);
5887 lra_set_insn_deleted (insn
);
5888 lra_assert (dregno
>= 0);
5889 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
5890 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
5891 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
5892 lra_set_insn_deleted (prev_insn
);
5895 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5896 return true if we did any change. The undo transformations for
5897 inheritance looks like
5901 p <- i, i <- p, and i <- i3
5902 where p is original pseudo from which inheritance pseudo i was
5903 created, i and i3 are removed inheritance pseudos, i2 is another
5904 not removed inheritance pseudo. All split pseudos or other
5905 occurrences of removed inheritance pseudos are changed on the
5906 corresponding original pseudos.
5908 The function also schedules insns changed and created during
5909 inheritance/split pass for processing by the subsequent constraint
5912 remove_inheritance_pseudos (bitmap remove_pseudos
)
5915 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5917 rtx_insn
*prev_insn
;
5918 bool change_p
, done_p
;
5920 change_p
= ! bitmap_empty_p (remove_pseudos
);
5921 /* We can not finish the function right away if CHANGE_P is true
5922 because we need to marks insns affected by previous
5923 inheritance/split pass for processing by the subsequent
5925 FOR_EACH_BB_FN (bb
, cfun
)
5927 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5928 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5929 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5931 if (! INSN_P (curr_insn
))
5934 sregno
= dregno
= -1;
5935 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5936 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5938 dregno
= get_regno (SET_DEST (set
));
5939 sregno
= get_regno (SET_SRC (set
));
5942 if (sregno
>= 0 && dregno
>= 0)
5944 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5945 && (lra_reg_info
[sregno
].restore_regno
== dregno
5946 || (bitmap_bit_p (remove_pseudos
, dregno
)
5947 && (lra_reg_info
[sregno
].restore_regno
5948 == lra_reg_info
[dregno
].restore_regno
))))
5949 || (bitmap_bit_p (remove_pseudos
, dregno
)
5950 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5951 /* One of the following cases:
5952 original <- removed inheritance pseudo
5953 removed inherit pseudo <- another removed inherit pseudo
5954 removed inherit pseudo <- original pseudo
5956 removed_split_pseudo <- original_reg
5957 original_reg <- removed_split_pseudo */
5959 if (lra_dump_file
!= NULL
)
5961 fprintf (lra_dump_file
, " Removing %s:\n",
5962 bitmap_bit_p (&lra_split_regs
, sregno
)
5963 || bitmap_bit_p (&lra_split_regs
, dregno
)
5964 ? "split" : "inheritance");
5965 dump_insn_slim (lra_dump_file
, curr_insn
);
5967 delete_move_and_clobber (curr_insn
, dregno
);
5970 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5971 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5973 /* Search the following pattern:
5974 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5975 original_pseudo <- inherit_or_split_pseudo1
5976 where the 2nd insn is the current insn and
5977 inherit_or_split_pseudo2 is not removed. If it is found,
5978 change the current insn onto:
5979 original_pseudo <- inherit_or_split_pseudo2. */
5980 for (prev_insn
= PREV_INSN (curr_insn
);
5981 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5982 prev_insn
= PREV_INSN (prev_insn
))
5984 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5985 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5986 /* There should be no subregs in insn we are
5987 searching because only the original reg might
5988 be in subreg when we changed the mode of
5989 load/store for splitting. */
5990 && REG_P (SET_DEST (prev_set
))
5991 && REG_P (SET_SRC (prev_set
))
5992 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5993 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5994 >= FIRST_PSEUDO_REGISTER
)
5995 /* As we consider chain of inheritance or
5996 splitting described in above comment we should
5997 check that sregno and prev_sregno were
5998 inheritance/split pseudos created from the
5999 same original regno. */
6000 && (lra_reg_info
[sregno
].restore_regno
6001 == lra_reg_info
[prev_sregno
].restore_regno
)
6002 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6004 lra_assert (GET_MODE (SET_SRC (prev_set
))
6005 == GET_MODE (regno_reg_rtx
[sregno
]));
6006 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
6007 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
6009 SET_SRC (set
) = SET_SRC (prev_set
);
6010 /* As we are finishing with processing the insn
6011 here, check the destination too as it might
6012 inheritance pseudo for another pseudo. */
6013 if (bitmap_bit_p (remove_pseudos
, dregno
)
6014 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6016 = lra_reg_info
[dregno
].restore_regno
) >= 0)
6018 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6019 SUBREG_REG (SET_DEST (set
))
6020 = regno_reg_rtx
[restore_regno
];
6022 SET_DEST (set
) = regno_reg_rtx
[restore_regno
];
6024 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6025 lra_set_used_insn_alternative_by_uid
6026 (INSN_UID (curr_insn
), -1);
6028 if (lra_dump_file
!= NULL
)
6030 fprintf (lra_dump_file
, " Change reload insn:\n");
6031 dump_insn_slim (lra_dump_file
, curr_insn
);
6038 struct lra_insn_reg
*reg
;
6039 bool restored_regs_p
= false;
6040 bool kept_regs_p
= false;
6042 curr_id
= lra_get_insn_recog_data (curr_insn
);
6043 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6046 restore_regno
= lra_reg_info
[regno
].restore_regno
;
6047 if (restore_regno
>= 0)
6049 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6051 lra_substitute_pseudo_within_insn
6052 (curr_insn
, regno
, regno_reg_rtx
[restore_regno
],
6054 restored_regs_p
= true;
6060 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6062 /* The instruction has changed since the previous
6063 constraints pass. */
6064 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6065 lra_set_used_insn_alternative_by_uid
6066 (INSN_UID (curr_insn
), -1);
6068 else if (restored_regs_p
)
6069 /* The instruction has been restored to the form that
6070 it had during the previous constraints pass. */
6071 lra_update_insn_regno_info (curr_insn
);
6072 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6074 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6075 dump_insn_slim (lra_dump_file
, curr_insn
);
6083 /* If optional reload pseudos failed to get a hard register or was not
6084 inherited, it is better to remove optional reloads. We do this
6085 transformation after undoing inheritance to figure out necessity to
6086 remove optional reloads easier. Return true if we do any
6089 undo_optional_reloads (void)
6091 bool change_p
, keep_p
;
6092 unsigned int regno
, uid
;
6093 bitmap_iterator bi
, bi2
;
6096 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
6098 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
6099 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6100 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6103 /* Keep optional reloads from previous subpasses. */
6104 if (lra_reg_info
[regno
].restore_regno
< 0
6105 /* If the original pseudo changed its allocation, just
6106 removing the optional pseudo is dangerous as the original
6107 pseudo will have longer live range. */
6108 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
6110 else if (reg_renumber
[regno
] >= 0)
6111 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6113 insn
= lra_insn_recog_data
[uid
]->insn
;
6114 if ((set
= single_set (insn
)) == NULL_RTX
)
6116 src
= SET_SRC (set
);
6117 dest
= SET_DEST (set
);
6118 if (! REG_P (src
) || ! REG_P (dest
))
6120 if (REGNO (dest
) == regno
6121 /* Ignore insn for optional reloads itself. */
6122 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
6123 /* Check only inheritance on last inheritance pass. */
6124 && (int) REGNO (src
) >= new_regno_start
6125 /* Check that the optional reload was inherited. */
6126 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6134 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
6135 if (lra_dump_file
!= NULL
)
6136 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6139 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
6140 bitmap_initialize (&insn_bitmap
, ®_obstack
);
6141 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
6143 if (lra_dump_file
!= NULL
)
6144 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6145 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6146 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
6148 insn
= lra_insn_recog_data
[uid
]->insn
;
6149 if ((set
= single_set (insn
)) != NULL_RTX
)
6151 src
= SET_SRC (set
);
6152 dest
= SET_DEST (set
);
6153 if (REG_P (src
) && REG_P (dest
)
6154 && ((REGNO (src
) == regno
6155 && (lra_reg_info
[regno
].restore_regno
6156 == (int) REGNO (dest
)))
6157 || (REGNO (dest
) == regno
6158 && (lra_reg_info
[regno
].restore_regno
6159 == (int) REGNO (src
)))))
6161 if (lra_dump_file
!= NULL
)
6163 fprintf (lra_dump_file
, " Deleting move %u\n",
6165 dump_insn_slim (lra_dump_file
, insn
);
6167 delete_move_and_clobber (insn
, REGNO (dest
));
6170 /* We should not worry about generation memory-memory
6171 moves here as if the corresponding inheritance did
6172 not work (inheritance pseudo did not get a hard reg),
6173 we remove the inheritance pseudo and the optional
6176 lra_substitute_pseudo_within_insn
6177 (insn
, regno
, regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
],
6179 lra_update_insn_regno_info (insn
);
6180 if (lra_dump_file
!= NULL
)
6182 fprintf (lra_dump_file
,
6183 " Restoring original insn:\n");
6184 dump_insn_slim (lra_dump_file
, insn
);
6188 /* Clear restore_regnos. */
6189 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6190 lra_reg_info
[regno
].restore_regno
= -1;
6191 bitmap_clear (&insn_bitmap
);
6192 bitmap_clear (&removed_optional_reload_pseudos
);
6196 /* Entry function for undoing inheritance/split transformation. Return true
6197 if we did any RTL change in this pass. */
6199 lra_undo_inheritance (void)
6202 int restore_regno
, hard_regno
;
6203 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6204 bitmap_head remove_pseudos
;
6208 lra_undo_inheritance_iter
++;
6209 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6211 if (lra_dump_file
!= NULL
)
6212 fprintf (lra_dump_file
,
6213 "\n********** Undoing inheritance #%d: **********\n\n",
6214 lra_undo_inheritance_iter
);
6215 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6216 n_inherit
= n_all_inherit
= 0;
6217 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6218 if (lra_reg_info
[regno
].restore_regno
>= 0)
6221 if (reg_renumber
[regno
] < 0
6222 /* If the original pseudo changed its allocation, just
6223 removing inheritance is dangerous as for changing
6224 allocation we used shorter live-ranges. */
6225 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
6226 bitmap_set_bit (&remove_pseudos
, regno
);
6230 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6231 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6232 n_inherit
, n_all_inherit
,
6233 (double) n_inherit
/ n_all_inherit
* 100);
6234 n_split
= n_all_split
= 0;
6235 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6236 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
6239 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6240 ? reg_renumber
[restore_regno
] : restore_regno
);
6241 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6242 bitmap_set_bit (&remove_pseudos
, regno
);
6246 if (lra_dump_file
!= NULL
)
6247 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6248 regno
, restore_regno
);
6251 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6252 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6253 n_split
, n_all_split
,
6254 (double) n_split
/ n_all_split
* 100);
6255 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6256 bitmap_clear (&remove_pseudos
);
6257 /* Clear restore_regnos. */
6258 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6259 lra_reg_info
[regno
].restore_regno
= -1;
6260 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6261 lra_reg_info
[regno
].restore_regno
= -1;
6262 change_p
= undo_optional_reloads () || change_p
;