gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 ;; Return true if OP a (const_int 0) operand.
  34 (define_predicate "const0_operand"
  35   (and (match_code "const_int")
  36        (match_test "op == CONST0_RTX (mode)")))
  37
  38 (define_special_predicate "subreg_lowpart_operator"
  39   (and (match_code "subreg")
  40        (match_test "subreg_lowpart_p (op)")))
  41
  42 (define_predicate "aarch64_ccmp_immediate"
  43   (and (match_code "const_int")
  44        (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
  45
  46 (define_predicate "aarch64_ccmp_operand"
  47   (ior (match_operand 0 "register_operand")
  48        (match_operand 0 "aarch64_ccmp_immediate")))
  49
  50 (define_predicate "aarch64_simd_register"
  51   (and (match_code "reg")
  52        (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
  53             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
  54
  55 (define_predicate "aarch64_reg_or_zero"
  56   (and (match_code "reg,subreg,const_int")
  57        (ior (match_operand 0 "register_operand")
  58             (match_test "op == const0_rtx"))))
  59
  60 (define_predicate "aarch64_reg_or_fp_zero"
  61   (ior (match_operand 0 "register_operand")
  62         (and (match_code "const_double")
  63              (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  64
  65 (define_predicate "aarch64_reg_zero_or_fp_zero"
  66   (ior (match_operand 0 "aarch64_reg_or_fp_zero")
  67        (match_operand 0 "aarch64_reg_or_zero")))
  68
  69 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  70   (and (match_code "reg,subreg,const_int")
  71        (ior (match_operand 0 "register_operand")
  72             (ior (match_test "op == const0_rtx")
  73                  (ior (match_test "op == constm1_rtx")
  74                       (match_test "op == const1_rtx"))))))
  75
  76 (define_predicate "aarch64_reg_or_orr_imm"
  77    (ior (match_operand 0 "register_operand")
  78         (and (match_code "const_vector")
  79              (match_test "aarch64_simd_valid_immediate (op, NULL,
  80                                                         AARCH64_CHECK_ORR)"))))
  81
  82 (define_predicate "aarch64_reg_or_bic_imm"
  83    (ior (match_operand 0 "register_operand")
  84         (and (match_code "const_vector")
  85              (match_test "aarch64_simd_valid_immediate (op, NULL,
  86                                                         AARCH64_CHECK_BIC)"))))
  87
  88 (define_predicate "aarch64_fp_compare_operand"
  89   (ior (match_operand 0 "register_operand")
  90        (and (match_code "const_double")
  91             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  92
  93 (define_predicate "aarch64_fp_pow2"
  94   (and (match_code "const_double")
  95         (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
  96
  97 (define_predicate "aarch64_fp_vec_pow2"
  98   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
  99
 100 (define_predicate "aarch64_sve_cnt_immediate"
 101   (and (match_code "const_poly_int")
 102        (match_test "aarch64_sve_cnt_immediate_p (op)")))
 103
 104 (define_predicate "aarch64_sub_immediate"
 105   (and (match_code "const_int")
 106        (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
 107
 108 (define_predicate "aarch64_plus_immediate"
 109   (and (match_code "const_int")
 110        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
 111             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
 112
 113 (define_predicate "aarch64_plus_operand"
 114   (ior (match_operand 0 "register_operand")
 115        (match_operand 0 "aarch64_plus_immediate")))
 116
 117 (define_predicate "aarch64_pluslong_immediate"
 118   (and (match_code "const_int")
 119        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
 120
 121 (define_predicate "aarch64_pluslong_strict_immedate"
 122   (and (match_operand 0 "aarch64_pluslong_immediate")
 123        (not (match_operand 0 "aarch64_plus_immediate"))))
 124
 125 (define_predicate "aarch64_sve_addvl_addpl_immediate"
 126   (and (match_code "const_poly_int")
 127        (match_test "aarch64_sve_addvl_addpl_immediate_p (op)")))
 128
 129 (define_predicate "aarch64_split_add_offset_immediate"
 130   (and (match_code "const_poly_int")
 131        (match_test "aarch64_add_offset_temporaries (op) == 1")))
 132
 133 (define_predicate "aarch64_pluslong_operand"
 134   (ior (match_operand 0 "register_operand")
 135        (match_operand 0 "aarch64_pluslong_immediate")
 136        (match_operand 0 "aarch64_sve_addvl_addpl_immediate")))
 137
 138 (define_predicate "aarch64_pluslong_or_poly_operand"
 139   (ior (match_operand 0 "aarch64_pluslong_operand")
 140        (match_operand 0 "aarch64_split_add_offset_immediate")))
 141
 142 (define_predicate "aarch64_logical_immediate"
 143   (and (match_code "const_int")
 144        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
 145
 146 (define_predicate "aarch64_logical_operand"
 147   (ior (match_operand 0 "register_operand")
 148        (match_operand 0 "aarch64_logical_immediate")))
 149
 150 (define_predicate "aarch64_mov_imm_operand"
 151   (and (match_code "const_int")
 152        (match_test "aarch64_move_imm (INTVAL (op), mode)")))
 153
 154 (define_predicate "aarch64_logical_and_immediate"
 155   (and (match_code "const_int")
 156        (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
 157
 158 (define_predicate "aarch64_shift_imm_si"
 159   (and (match_code "const_int")
 160        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
 161
 162 (define_predicate "aarch64_shift_imm_di"
 163   (and (match_code "const_int")
 164        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
 165
 166 (define_predicate "aarch64_shift_imm64_di"
 167   (and (match_code "const_int")
 168        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
 169
 170 (define_predicate "aarch64_reg_or_shift_imm_si"
 171   (ior (match_operand 0 "register_operand")
 172        (match_operand 0 "aarch64_shift_imm_si")))
 173
 174 (define_predicate "aarch64_reg_or_shift_imm_di"
 175   (ior (match_operand 0 "register_operand")
 176        (match_operand 0 "aarch64_shift_imm_di")))
 177
 178 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 179 ;; range 0..4.
 180 (define_predicate "aarch64_imm3"
 181   (and (match_code "const_int")
 182        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 183
 184 ;; The imm2 field is a 2-bit field that only accepts immediates in the
 185 ;; range 0..3.
 186 (define_predicate "aarch64_imm2"
 187   (and (match_code "const_int")
 188        (match_test "UINTVAL (op) <= 3")))
 189
 190 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 191 ;; range 0..7.
 192 (define_predicate "aarch64_lane_imm3"
 193   (and (match_code "const_int")
 194        (match_test "UINTVAL (op) <= 7")))
 195
 196 ;; An immediate that fits into 24 bits.
 197 (define_predicate "aarch64_imm24"
 198   (and (match_code "const_int")
 199        (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
 200
 201 (define_predicate "aarch64_pwr_imm3"
 202   (and (match_code "const_int")
 203        (match_test "INTVAL (op) != 0
 204                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 205
 206 (define_predicate "aarch64_pwr_2_si"
 207   (and (match_code "const_int")
 208        (match_test "INTVAL (op) != 0
 209                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 210
 211 (define_predicate "aarch64_pwr_2_di"
 212   (and (match_code "const_int")
 213        (match_test "INTVAL (op) != 0
 214                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 215
 216 (define_predicate "aarch64_mem_pair_offset"
 217   (and (match_code "const_int")
 218        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 219
 220 (define_predicate "aarch64_mem_pair_operand"
 221   (and (match_code "mem")
 222        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false,
 223                                                   ADDR_QUERY_LDP_STP)")))
 224
 225 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
 226 ;; as a 128-bit vec_concat.
 227 (define_predicate "aarch64_mem_pair_lanes_operand"
 228   (and (match_code "mem")
 229        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 230                                                   false,
 231                                                   ADDR_QUERY_LDP_STP_N)")))
 232
 233 (define_predicate "aarch64_prefetch_operand"
 234   (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
 235
 236 (define_predicate "aarch64_valid_symref"
 237   (match_code "const, symbol_ref, label_ref")
 238 {
 239   return (aarch64_classify_symbolic_expression (op)
 240           != SYMBOL_FORCE_TO_MEM);
 241 })
 242
 243 (define_predicate "aarch64_tls_ie_symref"
 244   (match_code "const, symbol_ref, label_ref")
 245 {
 246   switch (GET_CODE (op))
 247     {
 248     case CONST:
 249       op = XEXP (op, 0);
 250       if (GET_CODE (op) != PLUS
 251           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 252           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 253         return false;
 254       op = XEXP (op, 0);
 255       /* FALLTHRU */
 256
 257     case SYMBOL_REF:
 258       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 259
 260     default:
 261       gcc_unreachable ();
 262     }
 263 })
 264
 265 (define_predicate "aarch64_tls_le_symref"
 266   (match_code "const, symbol_ref, label_ref")
 267 {
 268   switch (GET_CODE (op))
 269     {
 270     case CONST:
 271       op = XEXP (op, 0);
 272       if (GET_CODE (op) != PLUS
 273           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 274           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 275         return false;
 276       op = XEXP (op, 0);
 277       /* FALLTHRU */
 278
 279     case SYMBOL_REF:
 280       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 281
 282     default:
 283       gcc_unreachable ();
 284     }
 285 })
 286
 287 (define_predicate "aarch64_mov_operand"
 288   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high,
 289                     const_poly_int,const_vector")
 290        (ior (match_operand 0 "register_operand")
 291             (ior (match_operand 0 "memory_operand")
 292                  (match_test "aarch64_mov_operand_p (op, mode)")))))
 293
 294 (define_predicate "aarch64_nonmemory_operand"
 295   (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high,
 296                     const_poly_int,const_vector")
 297        (ior (match_operand 0 "register_operand")
 298             (match_test "aarch64_mov_operand_p (op, mode)"))))
 299
 300 (define_predicate "aarch64_movti_operand"
 301   (ior (match_operand 0 "register_operand")
 302        (match_operand 0 "memory_operand")
 303        (and (match_operand 0 "const_scalar_int_operand")
 304             (match_test "aarch64_mov128_immediate (op)"))))
 305
 306 (define_predicate "aarch64_reg_or_imm"
 307   (ior (match_operand 0 "register_operand")
 308        (match_operand 0 "const_scalar_int_operand")))
 309
 310 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 311 (define_special_predicate "aarch64_comparison_operator"
 312   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 313                ordered,unlt,unle,unge,ungt"))
 314
 315 ;; Same as aarch64_comparison_operator but don't ignore the mode.
 316 ;; RTL SET operations require their operands source and destination have
 317 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 318 (define_predicate "aarch64_comparison_operator_mode"
 319   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 320                ordered,unlt,unle,unge,ungt"))
 321
 322 (define_special_predicate "aarch64_comparison_operation"
 323   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 324                ordered,unlt,unle,unge,ungt")
 325 {
 326   if (XEXP (op, 1) != const0_rtx)
 327     return false;
 328   rtx op0 = XEXP (op, 0);
 329   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 330     return false;
 331   return aarch64_get_condition_code (op) >= 0;
 332 })
 333
 334 (define_special_predicate "aarch64_equality_operator"
 335   (match_code "eq,ne"))
 336
 337 (define_special_predicate "aarch64_carry_operation"
 338   (match_code "ne,geu")
 339 {
 340   if (XEXP (op, 1) != const0_rtx)
 341     return false;
 342   machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
 343   rtx op0 = XEXP (op, 0);
 344   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 345 })
 346
 347 (define_special_predicate "aarch64_borrow_operation"
 348   (match_code "eq,ltu")
 349 {
 350   if (XEXP (op, 1) != const0_rtx)
 351     return false;
 352   machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
 353   rtx op0 = XEXP (op, 0);
 354   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 355 })
 356
 357 ;; True if the operand is memory reference suitable for a load/store exclusive.
 358 (define_predicate "aarch64_sync_memory_operand"
 359   (and (match_operand 0 "memory_operand")
 360        (match_code "reg" "0")))
 361
 362 ;; Predicates for parallel expanders based on mode.
 363 (define_special_predicate "vect_par_cnst_hi_half"
 364   (match_code "parallel")
 365 {
 366   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 367 })
 368
 369 (define_special_predicate "vect_par_cnst_lo_half"
 370   (match_code "parallel")
 371 {
 372   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 373 })
 374
 375 (define_special_predicate "aarch64_simd_lshift_imm"
 376   (match_code "const,const_vector")
 377 {
 378   return aarch64_simd_shift_imm_p (op, mode, true);
 379 })
 380
 381 (define_special_predicate "aarch64_simd_rshift_imm"
 382   (match_code "const,const_vector")
 383 {
 384   return aarch64_simd_shift_imm_p (op, mode, false);
 385 })
 386
 387 (define_predicate "aarch64_simd_imm_zero"
 388   (and (match_code "const,const_vector")
 389        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 390
 391 (define_predicate "aarch64_simd_or_scalar_imm_zero"
 392   (and (match_code "const_int,const_double,const,const_vector")
 393        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 394
 395 (define_predicate "aarch64_simd_imm_minus_one"
 396   (and (match_code "const,const_vector")
 397        (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
 398
 399 (define_predicate "aarch64_simd_reg_or_zero"
 400   (and (match_code "reg,subreg,const_int,const_double,const,const_vector")
 401        (ior (match_operand 0 "register_operand")
 402             (match_test "op == const0_rtx")
 403             (match_operand 0 "aarch64_simd_or_scalar_imm_zero"))))
 404
 405 (define_predicate "aarch64_simd_struct_operand"
 406   (and (match_code "mem")
 407        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 408
 409 ;; Like general_operand but allow only valid SIMD addressing modes.
 410 (define_predicate "aarch64_simd_general_operand"
 411   (and (match_operand 0 "general_operand")
 412        (match_test "!MEM_P (op)
 413                     || GET_CODE (XEXP (op, 0)) == POST_INC
 414                     || GET_CODE (XEXP (op, 0)) == REG")))
 415
 416 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 417 (define_predicate "aarch64_simd_nonimmediate_operand"
 418   (and (match_operand 0 "nonimmediate_operand")
 419        (match_test "!MEM_P (op)
 420                     || GET_CODE (XEXP (op, 0)) == POST_INC
 421                     || GET_CODE (XEXP (op, 0)) == REG")))
 422
 423 ;; Predicates used by the various SIMD shift operations.  These
 424 ;; fall in to 3 categories.
 425 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 426 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 427 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 428 (define_predicate "aarch64_simd_shift_imm_qi"
 429   (and (match_code "const_int")
 430        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 431
 432 (define_predicate "aarch64_simd_shift_imm_hi"
 433   (and (match_code "const_int")
 434        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 435
 436 (define_predicate "aarch64_simd_shift_imm_si"
 437   (and (match_code "const_int")
 438        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 439
 440 (define_predicate "aarch64_simd_shift_imm_di"
 441   (and (match_code "const_int")
 442        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 443
 444 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 445   (and (match_code "const_int")
 446        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 447
 448 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 449   (and (match_code "const_int")
 450        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 451
 452 (define_predicate "aarch64_simd_shift_imm_offset_si"
 453   (and (match_code "const_int")
 454        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 455
 456 (define_predicate "aarch64_simd_shift_imm_offset_di"
 457   (and (match_code "const_int")
 458        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 459
 460 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 461   (and (match_code "const_int")
 462        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 463
 464 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 465   (and (match_code "const_int")
 466        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 467
 468 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 469   (and (match_code "const_int")
 470        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 471
 472 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 473   (and (match_code "const_int")
 474        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
 475
 476 (define_predicate "aarch64_constant_pool_symref"
 477    (and (match_code "symbol_ref")
 478         (match_test "CONSTANT_POOL_ADDRESS_P (op)")))
 479
 480 (define_predicate "aarch64_constant_vector_operand"
 481   (match_code "const,const_vector"))
 482
 483 (define_predicate "aarch64_sve_ld1r_operand"
 484   (and (match_operand 0 "memory_operand")
 485        (match_test "aarch64_sve_ld1r_operand_p (op)")))
 486
 487 ;; Like memory_operand, but restricted to addresses that are valid for
 488 ;; SVE LDR and STR instructions.
 489 (define_predicate "aarch64_sve_ldr_operand"
 490   (and (match_code "mem")
 491        (match_test "aarch64_sve_ldr_operand_p (op)")))
 492
 493 (define_predicate "aarch64_sve_nonimmediate_operand"
 494   (ior (match_operand 0 "register_operand")
 495        (match_operand 0 "aarch64_sve_ldr_operand")))
 496
 497 (define_predicate "aarch64_sve_general_operand"
 498   (and (match_code "reg,subreg,mem,const,const_vector")
 499        (ior (match_operand 0 "register_operand")
 500             (match_operand 0 "aarch64_sve_ldr_operand")
 501             (match_test "aarch64_mov_operand_p (op, mode)"))))
 502
 503 (define_predicate "aarch64_sve_struct_memory_operand"
 504   (and (match_code "mem")
 505        (match_test "aarch64_sve_struct_memory_operand_p (op)")))
 506
 507 (define_predicate "aarch64_sve_struct_nonimmediate_operand"
 508   (ior (match_operand 0 "register_operand")
 509        (match_operand 0 "aarch64_sve_struct_memory_operand")))
 510
 511 ;; Doesn't include immediates, since those are handled by the move
 512 ;; patterns instead.
 513 (define_predicate "aarch64_sve_dup_operand"
 514   (ior (match_operand 0 "register_operand")
 515        (match_operand 0 "aarch64_sve_ld1r_operand")))
 516
 517 (define_predicate "aarch64_sve_arith_immediate"
 518   (and (match_code "const,const_vector")
 519        (match_test "aarch64_sve_arith_immediate_p (op, false)")))
 520
 521 (define_predicate "aarch64_sve_sub_arith_immediate"
 522   (and (match_code "const,const_vector")
 523        (match_test "aarch64_sve_arith_immediate_p (op, true)")))
 524
 525 (define_predicate "aarch64_sve_inc_dec_immediate"
 526   (and (match_code "const,const_vector")
 527        (match_test "aarch64_sve_inc_dec_immediate_p (op)")))
 528
 529 (define_predicate "aarch64_sve_logical_immediate"
 530   (and (match_code "const,const_vector")
 531        (match_test "aarch64_sve_bitmask_immediate_p (op)")))
 532
 533 (define_predicate "aarch64_sve_mul_immediate"
 534   (and (match_code "const,const_vector")
 535        (match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)")))
 536
 537 (define_predicate "aarch64_sve_dup_immediate"
 538   (and (match_code "const,const_vector")
 539        (match_test "aarch64_sve_dup_immediate_p (op)")))
 540
 541 (define_predicate "aarch64_sve_cmp_vsc_immediate"
 542   (and (match_code "const,const_vector")
 543        (match_test "aarch64_sve_cmp_immediate_p (op, true)")))
 544
 545 (define_predicate "aarch64_sve_cmp_vsd_immediate"
 546   (and (match_code "const,const_vector")
 547        (match_test "aarch64_sve_cmp_immediate_p (op, false)")))
 548
 549 (define_predicate "aarch64_sve_index_immediate"
 550   (and (match_code "const_int")
 551        (match_test "aarch64_sve_index_immediate_p (op)")))
 552
 553 (define_predicate "aarch64_sve_float_arith_immediate"
 554   (and (match_code "const,const_vector")
 555        (match_test "aarch64_sve_float_arith_immediate_p (op, false)")))
 556
 557 (define_predicate "aarch64_sve_float_arith_with_sub_immediate"
 558   (and (match_code "const,const_vector")
 559        (match_test "aarch64_sve_float_arith_immediate_p (op, true)")))
 560
 561 (define_predicate "aarch64_sve_float_mul_immediate"
 562   (and (match_code "const,const_vector")
 563        (match_test "aarch64_sve_float_mul_immediate_p (op)")))
 564
 565 (define_predicate "aarch64_sve_arith_operand"
 566   (ior (match_operand 0 "register_operand")
 567        (match_operand 0 "aarch64_sve_arith_immediate")))
 568
 569 (define_predicate "aarch64_sve_add_operand"
 570   (ior (match_operand 0 "aarch64_sve_arith_operand")
 571        (match_operand 0 "aarch64_sve_sub_arith_immediate")
 572        (match_operand 0 "aarch64_sve_inc_dec_immediate")))
 573
 574 (define_predicate "aarch64_sve_logical_operand"
 575   (ior (match_operand 0 "register_operand")
 576        (match_operand 0 "aarch64_sve_logical_immediate")))
 577
 578 (define_predicate "aarch64_sve_lshift_operand"
 579   (ior (match_operand 0 "register_operand")
 580        (match_operand 0 "aarch64_simd_lshift_imm")))
 581
 582 (define_predicate "aarch64_sve_rshift_operand"
 583   (ior (match_operand 0 "register_operand")
 584        (match_operand 0 "aarch64_simd_rshift_imm")))
 585
 586 (define_predicate "aarch64_sve_mul_operand"
 587   (ior (match_operand 0 "register_operand")
 588        (match_operand 0 "aarch64_sve_mul_immediate")))
 589
 590 (define_predicate "aarch64_sve_cmp_vsc_operand"
 591   (ior (match_operand 0 "register_operand")
 592        (match_operand 0 "aarch64_sve_cmp_vsc_immediate")))
 593
 594 (define_predicate "aarch64_sve_cmp_vsd_operand"
 595   (ior (match_operand 0 "register_operand")
 596        (match_operand 0 "aarch64_sve_cmp_vsd_immediate")))
 597
 598 (define_predicate "aarch64_sve_index_operand"
 599   (ior (match_operand 0 "register_operand")
 600        (match_operand 0 "aarch64_sve_index_immediate")))
 601
 602 (define_predicate "aarch64_sve_float_arith_operand"
 603   (ior (match_operand 0 "register_operand")
 604        (match_operand 0 "aarch64_sve_float_arith_immediate")))
 605
 606 (define_predicate "aarch64_sve_float_arith_with_sub_operand"
 607   (ior (match_operand 0 "aarch64_sve_float_arith_operand")
 608        (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate")))
 609
 610 (define_predicate "aarch64_sve_float_mul_operand"
 611   (ior (match_operand 0 "register_operand")
 612        (match_operand 0 "aarch64_sve_float_mul_immediate")))
 613
 614 (define_predicate "aarch64_sve_vec_perm_operand"
 615   (ior (match_operand 0 "register_operand")
 616        (match_operand 0 "aarch64_constant_vector_operand")))
 617
 618 (define_predicate "aarch64_gather_scale_operand_w"
 619   (and (match_code "const_int")
 620        (match_test "INTVAL (op) == 1 || INTVAL (op) == 4")))
 621
 622 (define_predicate "aarch64_gather_scale_operand_d"
 623   (and (match_code "const_int")
 624        (match_test "INTVAL (op) == 1 || INTVAL (op) == 8")))
 625
 626 ;; A special predicate that doesn't match a particular mode.
 627 (define_special_predicate "aarch64_any_register_operand"
 628   (match_code "reg"))
 629
 630 (define_predicate "aarch64_sve_any_binary_operator"
 631   (match_code "plus,minus,mult,div,udiv,smax,umax,smin,umin,and,ior,xor"))