gcc/config/aarch64/aarch64.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_H
  23 #define GCC_AARCH64_H
  24
  25 /* Target CPU builtins.  */
  26 #define TARGET_CPU_CPP_BUILTINS()       \
  27   aarch64_cpu_cpp_builtins (pfile)
  28
  29 \f
  30
  31 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
  32
  33 /* Target machine storage layout.  */
  34
  35 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  36   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  37       && GET_MODE_SIZE (MODE) < 4)              \
  38     {                                           \
  39       if (MODE == QImode || MODE == HImode)     \
  40         {                                       \
  41           MODE = SImode;                        \
  42         }                                       \
  43     }
  44
  45 /* Bits are always numbered from the LSBit.  */
  46 #define BITS_BIG_ENDIAN 0
  47
  48 /* Big/little-endian flavour.  */
  49 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
  50 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
  51
  52 /* AdvSIMD is supported in the default configuration, unless disabled by
  53    -mgeneral-regs-only or by the +nosimd extension.  */
  54 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
  55 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
  56
  57 #define UNITS_PER_WORD          8
  58
  59 #define UNITS_PER_VREG          16
  60
  61 #define PARM_BOUNDARY           64
  62
  63 #define STACK_BOUNDARY          128
  64
  65 #define FUNCTION_BOUNDARY       32
  66
  67 #define EMPTY_FIELD_BOUNDARY    32
  68
  69 #define BIGGEST_ALIGNMENT       128
  70
  71 #define SHORT_TYPE_SIZE         16
  72
  73 #define INT_TYPE_SIZE           32
  74
  75 #define LONG_TYPE_SIZE          (TARGET_ILP32 ? 32 : 64)
  76
  77 #define POINTER_SIZE            (TARGET_ILP32 ? 32 : 64)
  78
  79 #define LONG_LONG_TYPE_SIZE     64
  80
  81 #define FLOAT_TYPE_SIZE         32
  82
  83 #define DOUBLE_TYPE_SIZE        64
  84
  85 #define LONG_DOUBLE_TYPE_SIZE   128
  86
  87 /* The architecture reserves all bits of the address for hardware use,
  88    so the vbit must go into the delta field of pointers to member
  89    functions.  This is the same config as that in the AArch32
  90    port.  */
  91 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
  92
  93 /* Align definitions of arrays, unions and structures so that
  94    initializations and copies can be made more efficient.  This is not
  95    ABI-changing, so it only affects places where we can see the
  96    definition.  Increasing the alignment tends to introduce padding,
  97    so don't do this when optimizing for size/conserving stack space.  */
  98 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN)                      \
  99   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 100     && (TREE_CODE (EXP) == ARRAY_TYPE                                   \
 101         || TREE_CODE (EXP) == UNION_TYPE                                \
 102         || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 103
 104 /* Align global data.  */
 105 #define DATA_ALIGNMENT(EXP, ALIGN)                      \
 106   AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN)
 107
 108 /* Similarly, make sure that objects on the stack are sensibly aligned.  */
 109 #define LOCAL_ALIGNMENT(EXP, ALIGN)                             \
 110   AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN)
 111
 112 #define STRUCTURE_SIZE_BOUNDARY         8
 113
 114 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY).  */
 115 #define MALLOC_ABI_ALIGNMENT  128
 116
 117 /* Defined by the ABI */
 118 #define WCHAR_TYPE "unsigned int"
 119 #define WCHAR_TYPE_SIZE                 32
 120
 121 /* Using long long breaks -ansi and -std=c90, so these will need to be
 122    made conditional for an LLP64 ABI.  */
 123
 124 #define SIZE_TYPE       "long unsigned int"
 125
 126 #define PTRDIFF_TYPE    "long int"
 127
 128 #define PCC_BITFIELD_TYPE_MATTERS       1
 129
 130 /* Major revision number of the ARM Architecture implemented by the target.  */
 131 extern unsigned aarch64_architecture_version;
 132
 133 /* Instruction tuning/selection flags.  */
 134
 135 /* Bit values used to identify processor capabilities.  */
 136 #define AARCH64_FL_SIMD       (1 << 0)  /* Has SIMD instructions.  */
 137 #define AARCH64_FL_FP         (1 << 1)  /* Has FP.  */
 138 #define AARCH64_FL_CRYPTO     (1 << 2)  /* Has crypto.  */
 139 #define AARCH64_FL_CRC        (1 << 3)  /* Has CRC.  */
 140 /* ARMv8.1-A architecture extensions.  */
 141 #define AARCH64_FL_LSE        (1 << 4)  /* Has Large System Extensions.  */
 142 #define AARCH64_FL_RDMA       (1 << 5)  /* Has Round Double Multiply Add.  */
 143 #define AARCH64_FL_V8_1       (1 << 6)  /* Has ARMv8.1-A extensions.  */
 144 /* ARMv8.2-A architecture extensions.  */
 145 #define AARCH64_FL_V8_2       (1 << 8)  /* Has ARMv8.2-A features.  */
 146 #define AARCH64_FL_F16        (1 << 9)  /* Has ARMv8.2-A FP16 extensions.  */
 147 #define AARCH64_FL_SVE        (1 << 10) /* Has Scalable Vector Extensions.  */
 148 /* ARMv8.3-A architecture extensions.  */
 149 #define AARCH64_FL_V8_3       (1 << 11)  /* Has ARMv8.3-A features.  */
 150 #define AARCH64_FL_RCPC       (1 << 12)  /* Has support for RCpc model.  */
 151 #define AARCH64_FL_DOTPROD    (1 << 13)  /* Has ARMv8.2-A Dot Product ins.  */
 152 /* New flags to split crypto into aes and sha2.  */
 153 #define AARCH64_FL_AES        (1 << 14)  /* Has Crypto AES.  */
 154 #define AARCH64_FL_SHA2       (1 << 15)  /* Has Crypto SHA2.  */
 155 /* ARMv8.4-A architecture extensions.  */
 156 #define AARCH64_FL_V8_4       (1 << 16)  /* Has ARMv8.4-A features.  */
 157 #define AARCH64_FL_SM4        (1 << 17)  /* Has ARMv8.4-A SM3 and SM4.  */
 158 #define AARCH64_FL_SHA3       (1 << 18)  /* Has ARMv8.4-a SHA3 and SHA512.  */
 159 #define AARCH64_FL_F16FML     (1 << 19)  /* Has ARMv8.4-a FP16 extensions.  */
 160
 161 /* Statistical Profiling extensions.  */
 162 #define AARCH64_FL_PROFILE    (1 << 20)
 163
 164 /* Has FP and SIMD.  */
 165 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
 166
 167 /* Has FP without SIMD.  */
 168 #define AARCH64_FL_FPQ16      (AARCH64_FL_FP & ~AARCH64_FL_SIMD)
 169
 170 /* Architecture flags that effect instruction selection.  */
 171 #define AARCH64_FL_FOR_ARCH8       (AARCH64_FL_FPSIMD)
 172 #define AARCH64_FL_FOR_ARCH8_1                         \
 173   (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \
 174    | AARCH64_FL_RDMA | AARCH64_FL_V8_1)
 175 #define AARCH64_FL_FOR_ARCH8_2                  \
 176   (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
 177 #define AARCH64_FL_FOR_ARCH8_3                  \
 178   (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3)
 179 #define AARCH64_FL_FOR_ARCH8_4                  \
 180   (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \
 181    | AARCH64_FL_DOTPROD)
 182
 183 /* Macros to test ISA flags.  */
 184
 185 #define AARCH64_ISA_CRC            (aarch64_isa_flags & AARCH64_FL_CRC)
 186 #define AARCH64_ISA_CRYPTO         (aarch64_isa_flags & AARCH64_FL_CRYPTO)
 187 #define AARCH64_ISA_FP             (aarch64_isa_flags & AARCH64_FL_FP)
 188 #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
 189 #define AARCH64_ISA_LSE            (aarch64_isa_flags & AARCH64_FL_LSE)
 190 #define AARCH64_ISA_RDMA           (aarch64_isa_flags & AARCH64_FL_RDMA)
 191 #define AARCH64_ISA_V8_2           (aarch64_isa_flags & AARCH64_FL_V8_2)
 192 #define AARCH64_ISA_F16            (aarch64_isa_flags & AARCH64_FL_F16)
 193 #define AARCH64_ISA_SVE            (aarch64_isa_flags & AARCH64_FL_SVE)
 194 #define AARCH64_ISA_V8_3           (aarch64_isa_flags & AARCH64_FL_V8_3)
 195 #define AARCH64_ISA_DOTPROD        (aarch64_isa_flags & AARCH64_FL_DOTPROD)
 196 #define AARCH64_ISA_AES            (aarch64_isa_flags & AARCH64_FL_AES)
 197 #define AARCH64_ISA_SHA2           (aarch64_isa_flags & AARCH64_FL_SHA2)
 198 #define AARCH64_ISA_V8_4           (aarch64_isa_flags & AARCH64_FL_V8_4)
 199 #define AARCH64_ISA_SM4            (aarch64_isa_flags & AARCH64_FL_SM4)
 200 #define AARCH64_ISA_SHA3           (aarch64_isa_flags & AARCH64_FL_SHA3)
 201 #define AARCH64_ISA_F16FML         (aarch64_isa_flags & AARCH64_FL_F16FML)
 202
 203 /* Crypto is an optional extension to AdvSIMD.  */
 204 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
 205
 206 /* SHA2 is an optional extension to AdvSIMD.  */
 207 #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO)
 208
 209 /* SHA3 is an optional extension to AdvSIMD.  */
 210 #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3)
 211
 212 /* AES is an optional extension to AdvSIMD.  */
 213 #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO)
 214
 215 /* SM is an optional extension to AdvSIMD.  */
 216 #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4)
 217
 218 /* FP16FML is an optional extension to AdvSIMD.  */
 219 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST)
 220
 221 /* CRC instructions that can be enabled through +crc arch extension.  */
 222 #define TARGET_CRC32 (AARCH64_ISA_CRC)
 223
 224 /* Atomic instructions that can be enabled through the +lse extension.  */
 225 #define TARGET_LSE (AARCH64_ISA_LSE)
 226
 227 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension.  */
 228 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
 229 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
 230
 231 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod.  */
 232 #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD)
 233
 234 /* SVE instructions, enabled through +sve.  */
 235 #define TARGET_SVE (AARCH64_ISA_SVE)
 236
 237 /* ARMv8.3-A features.  */
 238 #define TARGET_ARMV8_3  (AARCH64_ISA_V8_3)
 239
 240 /* Make sure this is always defined so we don't have to check for ifdefs
 241    but rather use normal ifs.  */
 242 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
 243 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0
 244 #else
 245 #undef TARGET_FIX_ERR_A53_835769_DEFAULT
 246 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1
 247 #endif
 248
 249 /* Apply the workaround for Cortex-A53 erratum 835769.  */
 250 #define TARGET_FIX_ERR_A53_835769       \
 251   ((aarch64_fix_a53_err835769 == 2)     \
 252   ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
 253
 254 /* Make sure this is always defined so we don't have to check for ifdefs
 255    but rather use normal ifs.  */
 256 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
 257 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0
 258 #else
 259 #undef TARGET_FIX_ERR_A53_843419_DEFAULT
 260 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1
 261 #endif
 262
 263 /* Apply the workaround for Cortex-A53 erratum 843419.  */
 264 #define TARGET_FIX_ERR_A53_843419       \
 265   ((aarch64_fix_a53_err843419 == 2)     \
 266   ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
 267
 268 /* ARMv8.1-A Adv.SIMD support.  */
 269 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
 270
 271 /* Standard register usage.  */
 272
 273 /* 31 64-bit general purpose registers R0-R30:
 274    R30          LR (link register)
 275    R29          FP (frame pointer)
 276    R19-R28      Callee-saved registers
 277    R18          The platform register; use as temporary register.
 278    R17          IP1 The second intra-procedure-call temporary register
 279                 (can be used by call veneers and PLT code); otherwise use
 280                 as a temporary register
 281    R16          IP0 The first intra-procedure-call temporary register (can
 282                 be used by call veneers and PLT code); otherwise use as a
 283                 temporary register
 284    R9-R15       Temporary registers
 285    R8           Structure value parameter / temporary register
 286    R0-R7        Parameter/result registers
 287
 288    SP           stack pointer, encoded as X/R31 where permitted.
 289    ZR           zero register, encoded as X/R31 elsewhere
 290
 291    32 x 128-bit floating-point/vector registers
 292    V16-V31      Caller-saved (temporary) registers
 293    V8-V15       Callee-saved registers
 294    V0-V7        Parameter/result registers
 295
 296    The vector register V0 holds scalar B0, H0, S0 and D0 in its least
 297    significant bits.  Unlike AArch32 S1 is not packed into D0, etc.
 298
 299    P0-P7        Predicate low registers: valid in all predicate contexts
 300    P8-P15       Predicate high registers: used as scratch space
 301
 302    VG           Pseudo "vector granules" register
 303
 304    VG is the number of 64-bit elements in an SVE vector.  We define
 305    it as a hard register so that we can easily map it to the DWARF VG
 306    register.  GCC internally uses the poly_int variable aarch64_sve_vg
 307    instead.  */
 308
 309 #define FIXED_REGISTERS                                 \
 310   {                                                     \
 311     0, 0, 0, 0,   0, 0, 0, 0,   /* R0 - R7 */           \
 312     0, 0, 0, 0,   0, 0, 0, 0,   /* R8 - R15 */          \
 313     0, 0, 0, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 314     0, 0, 0, 0,   0, 1, 0, 1,   /* R24 - R30, SP */     \
 315     0, 0, 0, 0,   0, 0, 0, 0,   /* V0 - V7 */           \
 316     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 317     0, 0, 0, 0,   0, 0, 0, 0,   /* V16 - V23 */         \
 318     0, 0, 0, 0,   0, 0, 0, 0,   /* V24 - V31 */         \
 319     1, 1, 1, 1,                 /* SFP, AP, CC, VG */   \
 320     0, 0, 0, 0,   0, 0, 0, 0,   /* P0 - P7 */           \
 321     0, 0, 0, 0,   0, 0, 0, 0,   /* P8 - P15 */          \
 322   }
 323
 324 /* X30 is marked as caller-saved which is in line with regular function call
 325    behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does
 326    that for regular function calls and avoids it for sibcalls.  X30 is
 327    considered live for sibcalls; EPILOGUE_USES helps achieve that by returning
 328    true but not until function epilogues have been generated.  This ensures
 329    that X30 is available for use in leaf functions if needed.  */
 330
 331 #define CALL_USED_REGISTERS                             \
 332   {                                                     \
 333     1, 1, 1, 1,   1, 1, 1, 1,   /* R0 - R7 */           \
 334     1, 1, 1, 1,   1, 1, 1, 1,   /* R8 - R15 */          \
 335     1, 1, 1, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 336     0, 0, 0, 0,   0, 1, 1, 1,   /* R24 - R30, SP */     \
 337     1, 1, 1, 1,   1, 1, 1, 1,   /* V0 - V7 */           \
 338     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 339     1, 1, 1, 1,   1, 1, 1, 1,   /* V16 - V23 */         \
 340     1, 1, 1, 1,   1, 1, 1, 1,   /* V24 - V31 */         \
 341     1, 1, 1, 1,                 /* SFP, AP, CC, VG */   \
 342     1, 1, 1, 1,   1, 1, 1, 1,   /* P0 - P7 */           \
 343     1, 1, 1, 1,   1, 1, 1, 1,   /* P8 - P15 */          \
 344   }
 345
 346 #define REGISTER_NAMES                                          \
 347   {                                                             \
 348     "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",      \
 349     "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",     \
 350     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",     \
 351     "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp",      \
 352     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",      \
 353     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",     \
 354     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",     \
 355     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",     \
 356     "sfp", "ap",  "cc",  "vg",                                  \
 357     "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",      \
 358     "p8",  "p9",  "p10", "p11", "p12", "p13", "p14", "p15",     \
 359   }
 360
 361 /* Generate the register aliases for core register N */
 362 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
 363                      {"w" # N, R0_REGNUM + (N)}
 364
 365 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
 366                      {"d" # N, V0_REGNUM + (N)}, \
 367                      {"s" # N, V0_REGNUM + (N)}, \
 368                      {"h" # N, V0_REGNUM + (N)}, \
 369                      {"b" # N, V0_REGNUM + (N)}, \
 370                      {"z" # N, V0_REGNUM + (N)}
 371
 372 /* Provide aliases for all of the ISA defined register name forms.
 373    These aliases are convenient for use in the clobber lists of inline
 374    asm statements.  */
 375
 376 #define ADDITIONAL_REGISTER_NAMES \
 377   { R_ALIASES(0),  R_ALIASES(1),  R_ALIASES(2),  R_ALIASES(3),  \
 378     R_ALIASES(4),  R_ALIASES(5),  R_ALIASES(6),  R_ALIASES(7),  \
 379     R_ALIASES(8),  R_ALIASES(9),  R_ALIASES(10), R_ALIASES(11), \
 380     R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
 381     R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
 382     R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
 383     R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
 384     R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
 385     V_ALIASES(0),  V_ALIASES(1),  V_ALIASES(2),  V_ALIASES(3),  \
 386     V_ALIASES(4),  V_ALIASES(5),  V_ALIASES(6),  V_ALIASES(7),  \
 387     V_ALIASES(8),  V_ALIASES(9),  V_ALIASES(10), V_ALIASES(11), \
 388     V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
 389     V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
 390     V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
 391     V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
 392     V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31)  \
 393   }
 394
 395 /* Say that the return address register is used by the epilogue, but only after
 396    epilogue generation is complete.  Note that in the case of sibcalls, the
 397    values "used by the epilogue" are considered live at the start of the called
 398    function.  */
 399
 400 #define EPILOGUE_USES(REGNO) \
 401   (epilogue_completed && (REGNO) == LR_REGNUM)
 402
 403 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 404    the stack pointer does not matter.  This is only true if the function
 405    uses alloca.  */
 406 #define EXIT_IGNORE_STACK       (cfun->calls_alloca)
 407
 408 #define STATIC_CHAIN_REGNUM             R18_REGNUM
 409 #define HARD_FRAME_POINTER_REGNUM       R29_REGNUM
 410 #define FRAME_POINTER_REGNUM            SFP_REGNUM
 411 #define STACK_POINTER_REGNUM            SP_REGNUM
 412 #define ARG_POINTER_REGNUM              AP_REGNUM
 413 #define FIRST_PSEUDO_REGISTER           (P15_REGNUM + 1)
 414
 415 /* The number of (integer) argument register available.  */
 416 #define NUM_ARG_REGS                    8
 417 #define NUM_FP_ARG_REGS                 8
 418
 419 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
 420    four members.  */
 421 #define HA_MAX_NUM_FLDS         4
 422
 423 /* External dwarf register number scheme.  These number are used to
 424    identify registers in dwarf debug information, the values are
 425    defined by the AArch64 ABI.  The numbering scheme is independent of
 426    GCC's internal register numbering scheme.  */
 427
 428 #define AARCH64_DWARF_R0        0
 429
 430 /* The number of R registers, note 31! not 32.  */
 431 #define AARCH64_DWARF_NUMBER_R 31
 432
 433 #define AARCH64_DWARF_SP       31
 434 #define AARCH64_DWARF_VG       46
 435 #define AARCH64_DWARF_P0       48
 436 #define AARCH64_DWARF_V0       64
 437
 438 /* The number of V registers.  */
 439 #define AARCH64_DWARF_NUMBER_V 32
 440
 441 /* For signal frames we need to use an alternative return column.  This
 442    value must not correspond to a hard register and must be out of the
 443    range of DWARF_FRAME_REGNUM().  */
 444 #define DWARF_ALT_FRAME_RETURN_COLUMN   \
 445   (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
 446
 447 /* We add 1 extra frame register for use as the
 448    DWARF_ALT_FRAME_RETURN_COLUMN.  */
 449 #define DWARF_FRAME_REGISTERS           (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
 450
 451
 452 #define DBX_REGISTER_NUMBER(REGNO)      aarch64_dbx_register_number (REGNO)
 453 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
 454    can use DWARF_ALT_FRAME_RETURN_COLUMN defined below.  This is just the same
 455    as the default definition in dwarf2out.c.  */
 456 #undef DWARF_FRAME_REGNUM
 457 #define DWARF_FRAME_REGNUM(REGNO)       DBX_REGISTER_NUMBER (REGNO)
 458
 459 #define DWARF_FRAME_RETURN_COLUMN       DWARF_FRAME_REGNUM (LR_REGNUM)
 460
 461 #define DWARF2_UNWIND_INFO 1
 462
 463 /* Use R0 through R3 to pass exception handling information.  */
 464 #define EH_RETURN_DATA_REGNO(N) \
 465   ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
 466
 467 /* Select a format to encode pointers in exception handling data.  */
 468 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
 469   aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
 470
 471 /* Output the assembly strings we want to add to a function definition.  */
 472 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)      \
 473   aarch64_declare_function_name (STR, NAME, DECL)
 474
 475 /* For EH returns X4 contains the stack adjustment.  */
 476 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, R4_REGNUM)
 477 #define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
 478
 479 /* Don't use __builtin_setjmp until we've defined it.  */
 480 #undef DONT_USE_BUILTIN_SETJMP
 481 #define DONT_USE_BUILTIN_SETJMP 1
 482
 483 /* Register in which the structure value is to be returned.  */
 484 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
 485
 486 /* Non-zero if REGNO is part of the Core register set.
 487
 488    The rather unusual way of expressing this check is to avoid
 489    warnings when building the compiler when R0_REGNUM is 0 and REGNO
 490    is unsigned.  */
 491 #define GP_REGNUM_P(REGNO)                                              \
 492   (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
 493
 494 #define FP_REGNUM_P(REGNO)                      \
 495   (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
 496
 497 #define FP_LO_REGNUM_P(REGNO)            \
 498   (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
 499
 500 #define PR_REGNUM_P(REGNO)\
 501   (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM))
 502
 503 #define PR_LO_REGNUM_P(REGNO)\
 504   (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM))
 505
 506 \f
 507 /* Register and constant classes.  */
 508
 509 enum reg_class
 510 {
 511   NO_REGS,
 512   TAILCALL_ADDR_REGS,
 513   GENERAL_REGS,
 514   STACK_REG,
 515   POINTER_REGS,
 516   FP_LO_REGS,
 517   FP_REGS,
 518   POINTER_AND_FP_REGS,
 519   PR_LO_REGS,
 520   PR_HI_REGS,
 521   PR_REGS,
 522   ALL_REGS,
 523   LIM_REG_CLASSES               /* Last */
 524 };
 525
 526 #define N_REG_CLASSES   ((int) LIM_REG_CLASSES)
 527
 528 #define REG_CLASS_NAMES                         \
 529 {                                               \
 530   "NO_REGS",                                    \
 531   "TAILCALL_ADDR_REGS",                         \
 532   "GENERAL_REGS",                               \
 533   "STACK_REG",                                  \
 534   "POINTER_REGS",                               \
 535   "FP_LO_REGS",                                 \
 536   "FP_REGS",                                    \
 537   "POINTER_AND_FP_REGS",                        \
 538   "PR_LO_REGS",                                 \
 539   "PR_HI_REGS",                                 \
 540   "PR_REGS",                                    \
 541   "ALL_REGS"                                    \
 542 }
 543
 544 #define REG_CLASS_CONTENTS                                              \
 545 {                                                                       \
 546   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 547   { 0x0004ffff, 0x00000000, 0x00000000 },       /* TAILCALL_ADDR_REGS */\
 548   { 0x7fffffff, 0x00000000, 0x00000003 },       /* GENERAL_REGS */      \
 549   { 0x80000000, 0x00000000, 0x00000000 },       /* STACK_REG */         \
 550   { 0xffffffff, 0x00000000, 0x00000003 },       /* POINTER_REGS */      \
 551   { 0x00000000, 0x0000ffff, 0x00000000 },       /* FP_LO_REGS  */       \
 552   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS  */          \
 553   { 0xffffffff, 0xffffffff, 0x00000003 },       /* POINTER_AND_FP_REGS */\
 554   { 0x00000000, 0x00000000, 0x00000ff0 },       /* PR_LO_REGS */        \
 555   { 0x00000000, 0x00000000, 0x000ff000 },       /* PR_HI_REGS */        \
 556   { 0x00000000, 0x00000000, 0x000ffff0 },       /* PR_REGS */           \
 557   { 0xffffffff, 0xffffffff, 0x000fffff }        /* ALL_REGS */          \
 558 }
 559
 560 #define REGNO_REG_CLASS(REGNO)  aarch64_regno_regclass (REGNO)
 561
 562 #define INDEX_REG_CLASS GENERAL_REGS
 563 #define BASE_REG_CLASS  POINTER_REGS
 564
 565 /* Register pairs used to eliminate unneeded registers that point into
 566    the stack frame.  */
 567 #define ELIMINABLE_REGS                                                 \
 568 {                                                                       \
 569   { ARG_POINTER_REGNUM,         STACK_POINTER_REGNUM            },      \
 570   { ARG_POINTER_REGNUM,         HARD_FRAME_POINTER_REGNUM       },      \
 571   { FRAME_POINTER_REGNUM,       STACK_POINTER_REGNUM            },      \
 572   { FRAME_POINTER_REGNUM,       HARD_FRAME_POINTER_REGNUM       },      \
 573 }
 574
 575 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 576   (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
 577
 578 /* CPU/ARCH option handling.  */
 579 #include "config/aarch64/aarch64-opts.h"
 580
 581 enum target_cpus
 582 {
 583 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
 584   TARGET_CPU_##INTERNAL_IDENT,
 585 #include "aarch64-cores.def"
 586   TARGET_CPU_generic
 587 };
 588
 589 /* If there is no CPU defined at configure, use generic as default.  */
 590 #ifndef TARGET_CPU_DEFAULT
 591 #define TARGET_CPU_DEFAULT \
 592   (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6))
 593 #endif
 594
 595 /* If inserting NOP before a mult-accumulate insn remember to adjust the
 596    length so that conditional branching code is updated appropriately.  */
 597 #define ADJUST_INSN_LENGTH(insn, length)        \
 598   do                                            \
 599     {                                           \
 600        if (aarch64_madd_needs_nop (insn))       \
 601          length += 4;                           \
 602     } while (0)
 603
 604 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)      \
 605     aarch64_final_prescan_insn (INSN);                  \
 606
 607 /* The processor for which instructions should be scheduled.  */
 608 extern enum aarch64_processor aarch64_tune;
 609
 610 /* RTL generation support.  */
 611 #define INIT_EXPANDERS aarch64_init_expanders ()
 612 \f
 613
 614 /* Stack layout; function entry, exit and calling.  */
 615 #define STACK_GROWS_DOWNWARD    1
 616
 617 #define FRAME_GROWS_DOWNWARD    1
 618
 619 #define ACCUMULATE_OUTGOING_ARGS        1
 620
 621 #define FIRST_PARM_OFFSET(FNDECL) 0
 622
 623 /* Fix for VFP */
 624 #define LIBCALL_VALUE(MODE)  \
 625   gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
 626
 627 #define DEFAULT_PCC_STRUCT_RETURN 0
 628
 629 #ifdef HAVE_POLY_INT_H
 630 struct GTY (()) aarch64_frame
 631 {
 632   HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
 633
 634   /* The number of extra stack bytes taken up by register varargs.
 635      This area is allocated by the callee at the very top of the
 636      frame.  This value is rounded up to a multiple of
 637      STACK_BOUNDARY.  */
 638   HOST_WIDE_INT saved_varargs_size;
 639
 640   /* The size of the saved callee-save int/FP registers.  */
 641
 642   HOST_WIDE_INT saved_regs_size;
 643
 644   /* Offset from the base of the frame (incomming SP) to the
 645      top of the locals area.  This value is always a multiple of
 646      STACK_BOUNDARY.  */
 647   poly_int64 locals_offset;
 648
 649   /* Offset from the base of the frame (incomming SP) to the
 650      hard_frame_pointer.  This value is always a multiple of
 651      STACK_BOUNDARY.  */
 652   poly_int64 hard_fp_offset;
 653
 654   /* The size of the frame.  This value is the offset from base of the
 655      frame (incomming SP) to the stack_pointer.  This value is always
 656      a multiple of STACK_BOUNDARY.  */
 657   poly_int64 frame_size;
 658
 659   /* The size of the initial stack adjustment before saving callee-saves.  */
 660   poly_int64 initial_adjust;
 661
 662   /* The writeback value when pushing callee-save registers.
 663      It is zero when no push is used.  */
 664   HOST_WIDE_INT callee_adjust;
 665
 666   /* The offset from SP to the callee-save registers after initial_adjust.
 667      It may be non-zero if no push is used (ie. callee_adjust == 0).  */
 668   poly_int64 callee_offset;
 669
 670   /* The size of the stack adjustment after saving callee-saves.  */
 671   poly_int64 final_adjust;
 672
 673   /* Store FP,LR and setup a frame pointer.  */
 674   bool emit_frame_chain;
 675
 676   unsigned wb_candidate1;
 677   unsigned wb_candidate2;
 678
 679   bool laid_out;
 680 };
 681
 682 typedef struct GTY (()) machine_function
 683 {
 684   struct aarch64_frame frame;
 685   /* One entry for each hard register.  */
 686   bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
 687 } machine_function;
 688 #endif
 689
 690 /* Which ABI to use.  */
 691 enum aarch64_abi_type
 692 {
 693   AARCH64_ABI_LP64 = 0,
 694   AARCH64_ABI_ILP32 = 1
 695 };
 696
 697 #ifndef AARCH64_ABI_DEFAULT
 698 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
 699 #endif
 700
 701 #define TARGET_ILP32    (aarch64_abi & AARCH64_ABI_ILP32)
 702
 703 enum arm_pcs
 704 {
 705   ARM_PCS_AAPCS64,              /* Base standard AAPCS for 64 bit.  */
 706   ARM_PCS_UNKNOWN
 707 };
 708
 709
 710
 711
 712 /* We can't use machine_mode inside a generator file because it
 713    hasn't been created yet; we shouldn't be using any code that
 714    needs the real definition though, so this ought to be safe.  */
 715 #ifdef GENERATOR_FILE
 716 #define MACHMODE int
 717 #else
 718 #include "insn-modes.h"
 719 #define MACHMODE machine_mode
 720 #endif
 721
 722 #ifndef USED_FOR_TARGET
 723 /* AAPCS related state tracking.  */
 724 typedef struct
 725 {
 726   enum arm_pcs pcs_variant;
 727   int aapcs_arg_processed;      /* No need to lay out this argument again.  */
 728   int aapcs_ncrn;               /* Next Core register number.  */
 729   int aapcs_nextncrn;           /* Next next core register number.  */
 730   int aapcs_nvrn;               /* Next Vector register number.  */
 731   int aapcs_nextnvrn;           /* Next Next Vector register number.  */
 732   rtx aapcs_reg;                /* Register assigned to this argument.  This
 733                                    is NULL_RTX if this parameter goes on
 734                                    the stack.  */
 735   MACHMODE aapcs_vfp_rmode;
 736   int aapcs_stack_words;        /* If the argument is passed on the stack, this
 737                                    is the number of words needed, after rounding
 738                                    up.  Only meaningful when
 739                                    aapcs_reg == NULL_RTX.  */
 740   int aapcs_stack_size;         /* The total size (in words, per 8 byte) of the
 741                                    stack arg area so far.  */
 742 } CUMULATIVE_ARGS;
 743 #endif
 744
 745 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
 746   (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
 747
 748 #define PAD_VARARGS_DOWN        0
 749
 750 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 751   aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
 752
 753 #define FUNCTION_ARG_REGNO_P(REGNO) \
 754   aarch64_function_arg_regno_p(REGNO)
 755 \f
 756
 757 /* ISA Features.  */
 758
 759 /* Addressing modes, etc.  */
 760 #define HAVE_POST_INCREMENT     1
 761 #define HAVE_PRE_INCREMENT      1
 762 #define HAVE_POST_DECREMENT     1
 763 #define HAVE_PRE_DECREMENT      1
 764 #define HAVE_POST_MODIFY_DISP   1
 765 #define HAVE_PRE_MODIFY_DISP    1
 766
 767 #define MAX_REGS_PER_ADDRESS    2
 768
 769 #define CONSTANT_ADDRESS_P(X)           aarch64_constant_address_p(X)
 770
 771 #define REGNO_OK_FOR_BASE_P(REGNO)      \
 772   aarch64_regno_ok_for_base_p (REGNO, true)
 773
 774 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 775   aarch64_regno_ok_for_index_p (REGNO, true)
 776
 777 #define LEGITIMATE_PIC_OPERAND_P(X) \
 778   aarch64_legitimate_pic_operand_p (X)
 779
 780 #define CASE_VECTOR_MODE Pmode
 781
 782 #define DEFAULT_SIGNED_CHAR 0
 783
 784 /* An integer expression for the size in bits of the largest integer machine
 785    mode that should actually be used.  We allow pairs of registers.  */
 786 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
 787
 788 /* Maximum bytes moved by a single instruction (load/store pair).  */
 789 #define MOVE_MAX (UNITS_PER_WORD * 2)
 790
 791 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends.  */
 792 #define AARCH64_CALL_RATIO 8
 793
 794 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
 795    move_by_pieces will continually copy the largest safe chunks.  So a
 796    7-byte copy is a 4-byte + 2-byte + byte copy.  This proves inefficient
 797    for both size and speed of copy, so we will instead use the "movmem"
 798    standard name to implement the copy.  This logic does not apply when
 799    targeting -mstrict-align, so keep a sensible default in that case.  */
 800 #define MOVE_RATIO(speed) \
 801   (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
 802
 803 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 804    of the length of a memset call, but use the default otherwise.  */
 805 #define CLEAR_RATIO(speed) \
 806   ((speed) ? 15 : AARCH64_CALL_RATIO)
 807
 808 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when
 809    optimizing for size adjust the ratio to account for the overhead of loading
 810    the constant.  */
 811 #define SET_RATIO(speed) \
 812   ((speed) ? 15 : AARCH64_CALL_RATIO - 2)
 813
 814 /* Disable auto-increment in move_by_pieces et al.  Use of auto-increment is
 815    rarely a good idea in straight-line code since it adds an extra address
 816    dependency between each instruction.  Better to use incrementing offsets.  */
 817 #define USE_LOAD_POST_INCREMENT(MODE)   0
 818 #define USE_LOAD_POST_DECREMENT(MODE)   0
 819 #define USE_LOAD_PRE_INCREMENT(MODE)    0
 820 #define USE_LOAD_PRE_DECREMENT(MODE)    0
 821 #define USE_STORE_POST_INCREMENT(MODE)  0
 822 #define USE_STORE_POST_DECREMENT(MODE)  0
 823 #define USE_STORE_PRE_INCREMENT(MODE)   0
 824 #define USE_STORE_PRE_DECREMENT(MODE)   0
 825
 826 /* WORD_REGISTER_OPERATIONS does not hold for AArch64.
 827    The assigned word_mode is DImode but operations narrower than SImode
 828    behave as 32-bit operations if using the W-form of the registers rather
 829    than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
 830    expects.  */
 831 #define WORD_REGISTER_OPERATIONS 0
 832
 833 /* Define if loading from memory in MODE, an integral mode narrower than
 834    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
 835    macro should be the code that says which one of the two operations is
 836    implicitly done, or UNKNOWN if none.  */
 837 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 838
 839 /* Define this macro to be non-zero if instructions will fail to work
 840    if given data not on the nominal alignment.  */
 841 #define STRICT_ALIGNMENT                TARGET_STRICT_ALIGN
 842
 843 /* Define this macro to be non-zero if accessing less than a word of
 844    memory is no faster than accessing a word of memory, i.e., if such
 845    accesses require more than one instruction or if there is no
 846    difference in cost.
 847    Although there's no difference in instruction count or cycles,
 848    in AArch64 we don't want to expand to a sub-word to a 64-bit access
 849    if we don't have to, for power-saving reasons.  */
 850 #define SLOW_BYTE_ACCESS                0
 851
 852 #define NO_FUNCTION_CSE 1
 853
 854 /* Specify the machine mode that the hardware addresses have.
 855    After generation of rtl, the compiler makes no further distinction
 856    between pointers and any other objects of this machine mode.  */
 857 #define Pmode           DImode
 858
 859 /* A C expression whose value is zero if pointers that need to be extended
 860    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
 861    greater then zero if they are zero-extended and less then zero if the
 862    ptr_extend instruction should be used.  */
 863 #define POINTERS_EXTEND_UNSIGNED 1
 864
 865 /* Mode of a function address in a call instruction (for indexing purposes).  */
 866 #define FUNCTION_MODE   Pmode
 867
 868 #define SELECT_CC_MODE(OP, X, Y)        aarch64_select_cc_mode (OP, X, Y)
 869
 870 #define REVERSIBLE_CC_MODE(MODE) 1
 871
 872 #define REVERSE_CONDITION(CODE, MODE)           \
 873   (((MODE) == CCFPmode || (MODE) == CCFPEmode)  \
 874    ? reverse_condition_maybe_unordered (CODE)   \
 875    : reverse_condition (CODE))
 876
 877 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 878   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 879 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 880   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 881
 882 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 883
 884 #define RETURN_ADDR_RTX aarch64_return_addr
 885
 886 /* 3 insns + padding + 2 pointer-sized entries.  */
 887 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32)
 888
 889 /* Trampolines contain dwords, so must be dword aligned.  */
 890 #define TRAMPOLINE_ALIGNMENT 64
 891
 892 /* Put trampolines in the text section so that mapping symbols work
 893    correctly.  */
 894 #define TRAMPOLINE_SECTION text_section
 895
 896 /* To start with.  */
 897 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
 898   (aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
 899 \f
 900
 901 /* Assembly output.  */
 902
 903 /* For now we'll make all jump tables pc-relative.  */
 904 #define CASE_VECTOR_PC_RELATIVE 1
 905
 906 #define CASE_VECTOR_SHORTEN_MODE(min, max, body)        \
 907   ((min < -0x1fff0 || max > 0x1fff0) ? SImode           \
 908    : (min < -0x1f0 || max > 0x1f0) ? HImode             \
 909    : QImode)
 910
 911 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL.  */
 912 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
 913
 914 #define MCOUNT_NAME "_mcount"
 915
 916 #define NO_PROFILE_COUNTERS 1
 917
 918 /* Emit rtl for profiling.  Output assembler code to FILE
 919    to call "_mcount" for profiling a function entry.  */
 920 #define PROFILE_HOOK(LABEL)                                             \
 921   {                                                                     \
 922     rtx fun, lr;                                                        \
 923     lr = get_hard_reg_initial_val (Pmode, LR_REGNUM);                   \
 924     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 925     emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode);           \
 926   }
 927
 928 /* All the work done in PROFILE_HOOK, but still required.  */
 929 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 930
 931 /* For some reason, the Linux headers think they know how to define
 932    these macros.  They don't!!!  */
 933 #undef ASM_APP_ON
 934 #undef ASM_APP_OFF
 935 #define ASM_APP_ON      "\t" ASM_COMMENT_START " Start of user assembly\n"
 936 #define ASM_APP_OFF     "\t" ASM_COMMENT_START " End of user assembly\n"
 937
 938 #define CONSTANT_POOL_BEFORE_FUNCTION 0
 939
 940 /* This definition should be relocated to aarch64-elf-raw.h.  This macro
 941    should be undefined in aarch64-linux.h and a clear_cache pattern
 942    implmented to emit either the call to __aarch64_sync_cache_range()
 943    directly or preferably the appropriate sycall or cache clear
 944    instructions inline.  */
 945 #define CLEAR_INSN_CACHE(beg, end)                              \
 946   extern void  __aarch64_sync_cache_range (void *, void *);     \
 947   __aarch64_sync_cache_range (beg, end)
 948
 949 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
 950
 951 /* Choose appropriate mode for caller saves, so we do the minimum
 952    required size of load/store.  */
 953 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 954   aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
 955
 956 #undef SWITCHABLE_TARGET
 957 #define SWITCHABLE_TARGET 1
 958
 959 /* Check TLS Descriptors mechanism is selected.  */
 960 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
 961
 962 extern enum aarch64_code_model aarch64_cmodel;
 963
 964 /* When using the tiny addressing model conditional and unconditional branches
 965    can span the whole of the available address space (1MB).  */
 966 #define HAS_LONG_COND_BRANCH                            \
 967   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 968    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 969
 970 #define HAS_LONG_UNCOND_BRANCH                          \
 971   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 972    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 973
 974 #define TARGET_SUPPORTS_WIDE_INT 1
 975
 976 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register.  */
 977 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
 978   ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
 979    || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
 980    || (MODE) == DFmode)
 981
 982 /* Modes valid for AdvSIMD Q registers.  */
 983 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
 984   ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
 985    || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \
 986    || (MODE) == V2DFmode)
 987
 988 #define ENDIAN_LANE_N(NUNITS, N) \
 989   (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N)
 990
 991 /* Support for a configure-time default CPU, etc.  We currently support
 992    --with-arch and --with-cpu.  Both are ignored if either is specified
 993    explicitly on the command line at run time.  */
 994 #define OPTION_DEFAULT_SPECS                            \
 995   {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" },  \
 996   {"cpu",  "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" },
 997
 998 #define MCPU_TO_MARCH_SPEC \
 999    " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
1000
1001 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
1002 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
1003   { "rewrite_mcpu", aarch64_rewrite_mcpu },
1004
1005 #if defined(__aarch64__)
1006 extern const char *host_detect_local_cpu (int argc, const char **argv);
1007 #define HAVE_LOCAL_CPU_DETECT
1008 # define EXTRA_SPEC_FUNCTIONS                                           \
1009   { "local_cpu_detect", host_detect_local_cpu },                        \
1010   MCPU_TO_MARCH_SPEC_FUNCTIONS
1011
1012 # define MCPU_MTUNE_NATIVE_SPECS                                        \
1013    " %{march=native:%<march=native %:local_cpu_detect(arch)}"           \
1014    " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}"              \
1015    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
1016 #else
1017 # define MCPU_MTUNE_NATIVE_SPECS ""
1018 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS
1019 #endif
1020
1021 #define ASM_CPU_SPEC \
1022    MCPU_TO_MARCH_SPEC
1023
1024 #define EXTRA_SPECS                                             \
1025   { "asm_cpu_spec",             ASM_CPU_SPEC }
1026
1027 #define ASM_OUTPUT_POOL_EPILOGUE  aarch64_asm_output_pool_epilogue
1028
1029 /* This type is the user-visible __fp16, and a pointer to that type.  We
1030    need it in many places in the backend.  Defined in aarch64-builtins.c.  */
1031 extern tree aarch64_fp16_type_node;
1032 extern tree aarch64_fp16_ptr_type_node;
1033
1034 /* The generic unwind code in libgcc does not initialize the frame pointer.
1035    So in order to unwind a function using a frame pointer, the very first
1036    function that is unwound must save the frame pointer.  That way the frame
1037    pointer is restored and its value is now valid - otherwise _Unwind_GetGR
1038    crashes.  Libgcc can now be safely built with -fomit-frame-pointer.  */
1039 #define LIBGCC2_UNWIND_ATTRIBUTE \
1040   __attribute__((optimize ("no-omit-frame-pointer")))
1041
1042 #ifndef USED_FOR_TARGET
1043 extern poly_uint16 aarch64_sve_vg;
1044
1045 /* The number of bits and bytes in an SVE vector.  */
1046 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64))
1047 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8))
1048
1049 /* The number of bytes in an SVE predicate.  */
1050 #define BYTES_PER_SVE_PRED aarch64_sve_vg
1051
1052 /* The SVE mode for a vector of bytes.  */
1053 #define SVE_BYTE_MODE VNx16QImode
1054
1055 /* The maximum number of bytes in a fixed-size vector.  This is 256 bytes
1056    (for -msve-vector-bits=2048) multiplied by the maximum number of
1057    vectors in a structure mode (4).
1058
1059    This limit must not be used for variable-size vectors, since
1060    VL-agnostic code must work with arbitary vector lengths.  */
1061 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4)
1062 #endif
1063
1064 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE)
1065
1066 #endif /* GCC_AARCH64_H */