1 /* Copyright (C
) 2011-2018 Free Software Foundation
, Inc.
2 Contributed by ARM Ltd.
4 This file is part of GCC.
6 GCC is free software
; you can redistribute it and
/or modify it
7 under the terms of the GNU General Public License as published by
8 the Free Software Foundation
; either version
3, or (at your option
)
11 GCC is distributed in the hope that it will be useful
, but
12 WITHOUT ANY WARRANTY
; without even the implied warranty of
13 MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC
; see the file COPYING3. If not see
18 <http
://www.gnu.org
/licenses
/>.
*/
20 /* This is a list of cores that implement AArch64.
22 Before using #include to read this file
, define a macro
:
24 AARCH64_CORE(CORE_NAME
, CORE_IDENT
, SCHEDULER_IDENT
, ARCH_IDENT
, FLAGS
, COSTS
, IMP
, PART
, VARIANT
)
26 The CORE_NAME is the name of the core
, represented as a string constant.
27 The CORE_IDENT is the name of the core
, represented as an identifier.
28 The SCHEDULER_IDENT is the name of the core for which scheduling decisions
29 will be made
, represented as an identifier.
30 ARCH_IDENT is the architecture implemented by the chip as specified in
32 FLAGS are the bitwise
-or of the traits that apply to that core.
33 This need not include flags implied by the architecture.
34 COSTS is the name of the rtx_costs routine to use.
35 IMP is the implementer ID of the CPU vendor. On a GNU
/Linux system it
36 can be found in
/proc
/cpuinfo. A partial list of implementer IDs is
37 given in the ARM Architecture Reference Manual ARMv8
, for
38 ARMv8
-A architecture profile.
39 PART is the part number of the CPU. On a GNU
/Linux system it can be
40 found in
/proc
/cpuinfo. For big.LITTLE systems this should use the
41 macro AARCH64_BIG_LITTLE where the big part number comes as the first
42 argument to the macro and little is the second.
43 VARIANT is the variant of the CPU. In a GNU
/Linux system it can found
44 in
/proc
/cpuinfo. If this is
-1, this means it can match any variant.
*/
46 /* ARMv8
-A Architecture Processors.
*/
48 /* ARM ('A') cores.
*/
49 AARCH64_CORE("cortex-a35", cortexa35
, cortexa53
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC
, cortexa35
, 0x41, 0xd04, -1)
50 AARCH64_CORE("cortex-a53", cortexa53
, cortexa53
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC
, cortexa53
, 0x41, 0xd03, -1)
51 AARCH64_CORE("cortex-a57", cortexa57
, cortexa57
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC
, cortexa57
, 0x41, 0xd07, -1)
52 AARCH64_CORE("cortex-a72", cortexa72
, cortexa57
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC
, cortexa72
, 0x41, 0xd08, -1)
53 AARCH64_CORE("cortex-a73", cortexa73
, cortexa57
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC
, cortexa73
, 0x41, 0xd09, -1)
55 /* Cavium ('C') cores.
*/
56 AARCH64_CORE("thunderx", thunderx
, thunderx
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO
, thunderx
, 0x43, 0x0a0, -1)
57 /* Do not swap around
"thunderxt88p1" and
"thunderxt88",
58 this order is required to handle variant correctly.
*/
59 AARCH64_CORE("thunderxt88p1", thunderxt88p1
, thunderx
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO
, thunderxt88
, 0x43, 0x0a1, 0)
60 AARCH64_CORE("thunderxt88", thunderxt88
, thunderx
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO
, thunderxt88
, 0x43, 0x0a1, -1)
61 AARCH64_CORE("thunderxt81", thunderxt81
, thunderx
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO
, thunderx
, 0x43, 0x0a2, -1)
62 AARCH64_CORE("thunderxt83", thunderxt83
, thunderx
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO
, thunderx
, 0x43, 0x0a3, -1)
64 /* APM ('P') cores.
*/
65 AARCH64_CORE("xgene1", xgene1
, xgene1
, 8A
, AARCH64_FL_FOR_ARCH8
, xgene1
, 0x50, 0x000, -1)
67 /* Qualcomm ('Q') cores.
*/
68 AARCH64_CORE("falkor", falkor
, falkor
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA
, qdf24xx
, 0x51, 0xC00, -1)
69 AARCH64_CORE("qdf24xx", qdf24xx
, falkor
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA
, qdf24xx
, 0x51, 0xC00, -1)
71 /* Samsung ('S') cores.
*/
72 AARCH64_CORE("exynos-m1", exynosm1
, exynosm1
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO
, exynosm1
, 0x53, 0x001, -1)
74 /* HXT ('h') cores.
*/
75 AARCH64_CORE("phecda", phecda
, falkor
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO
, qdf24xx
, 0x68, 0x000, -1)
77 /* ARMv8.1
-A Architecture Processors.
*/
79 /* Broadcom ('B') cores.
*/
80 AARCH64_CORE("thunderx2t99p1", thunderx2t99p1
, thunderx2t99
, 8_1A
, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO
, thunderx2t99
, 0x42, 0x516, -1)
81 AARCH64_CORE("vulcan", vulcan
, thunderx2t99
, 8_1A
, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO
, thunderx2t99
, 0x42, 0x516, -1)
83 /* Cavium ('C') cores.
*/
84 AARCH64_CORE("thunderx2t99", thunderx2t99
, thunderx2t99
, 8_1A
, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO
, thunderx2t99
, 0x43, 0x0af, -1)
86 /* ARMv8.2
-A Architecture Processors.
*/
88 /* ARM ('A') cores.
*/
89 AARCH64_CORE("cortex-a55", cortexa55
, cortexa53
, 8_2A
, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD
, cortexa53
, 0x41, 0xd05, -1)
90 AARCH64_CORE("cortex-a75", cortexa75
, cortexa57
, 8_2A
, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD
, cortexa73
, 0x41, 0xd0a, -1)
91 AARCH64_CORE("cortex-a76", cortexa76
, cortexa57
, 8_2A
, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD
, cortexa72
, 0x41, 0xd0b, -1)
93 /* ARMv8.4
-A Architecture Processors.
*/
95 /* Qualcomm ('Q') cores.
*/
96 AARCH64_CORE("saphira", saphira
, falkor
, 8_4A
, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC
, saphira
, 0x51, 0xC01, -1)
98 /* ARMv8
-A big.LITTLE implementations.
*/
100 AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53
, cortexa53
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC
, cortexa57
, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1)
101 AARCH64_CORE("cortex-a72.cortex-a53", cortexa72cortexa53
, cortexa53
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC
, cortexa72
, 0x41, AARCH64_BIG_LITTLE (0xd08, 0xd03), -1)
102 AARCH64_CORE("cortex-a73.cortex-a35", cortexa73cortexa35
, cortexa53
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC
, cortexa73
, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd04), -1)
103 AARCH64_CORE("cortex-a73.cortex-a53", cortexa73cortexa53
, cortexa53
, 8A
, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC
, cortexa73
, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd03), -1)
105 /* ARM DynamIQ big.LITTLE configurations.
*/
107 AARCH64_CORE("cortex-a75.cortex-a55", cortexa75cortexa55
, cortexa53
, 8_2A
, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD
, cortexa73
, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1)
108 AARCH64_CORE("cortex-a76.cortex-a55", cortexa76cortexa55
, cortexa53
, 8_2A
, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD
, cortexa72
, 0x41, AARCH64_BIG_LITTLE (0xd0b, 0xd05), -1)