gcc/config/sh/sh.c

   1 /* Output routines for GCC for Hitachi Super-H.
   2    Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
   3
   4 This file is part of GNU CC.
   5
   6 GNU CC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2, or (at your option)
   9 any later version.
  10
  11 GNU CC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GNU CC; see the file COPYING.  If not, write to
  18 the Free Software Foundation, 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.  */
  20
  21 /* Contributed by Steve Chamberlain (sac@cygnus.com).
  22    Improved by Jim Wilson (wilson@cygnus.com).  */
  23
  24 #include "config.h"
  25
  26 #include <stdio.h>
  27
  28 #include "rtl.h"
  29 #include "tree.h"
  30 #include "flags.h"
  31 #include "insn-flags.h"
  32 #include "expr.h"
  33 #include "regs.h"
  34 #include "hard-reg-set.h"
  35 #include "output.h"
  36 #include "insn-attr.h"
  37
  38 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
  39 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
  40
  41 /* ??? The pragma interrupt support will not work for SH3.  */
  42 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
  43    output code for the next function appropriate for an interrupt handler.  */
  44 int pragma_interrupt;
  45
  46 /* This is set by the trap_exit attribute for functions.   It specifies
  47    a trap number to be used in a trapa instruction at function exit
  48    (instead of an rte instruction).  */
  49 int trap_exit;
  50
  51 /* This is used by the sp_switch attribute for functions.  It specifies
  52    a variable holding the address of the stack the interrupt function
  53    should switch to/from at entry/exit.  */
  54 rtx sp_switch;
  55
  56 /* This is set by #pragma trapa, and is similar to the above, except that
  57    the compiler doesn't emit code to preserve all registers.  */
  58 static int pragma_trapa;
  59
  60 /* This is set by #pragma nosave_low_regs.  This is useful on the SH3,
  61    which has a separate set of low regs for User and Supervisor modes.
  62    This should only be used for the lowest level of interrupts.  Higher levels
  63    of interrupts must save the registers in case they themselves are
  64    interrupted.  */
  65 int pragma_nosave_low_regs;
  66
  67 /* This is used for communication between SETUP_INCOMING_VARARGS and
  68    sh_expand_prologue.  */
  69 int current_function_anonymous_args;
  70
  71 /* Global variables from toplev.c and final.c that are used within, but
  72    not declared in any header file.  */
  73 extern char *version_string;
  74 extern int *insn_addresses;
  75
  76 /* Global variables for machine-dependent things. */
  77
  78 /* Which cpu are we scheduling for.  */
  79 enum processor_type sh_cpu;
  80
  81 /* Saved operands from the last compare to use when we generate an scc
  82    or bcc insn.  */
  83
  84 rtx sh_compare_op0;
  85 rtx sh_compare_op1;
  86
  87 /* Provides the class number of the smallest class containing
  88    reg number.  */
  89
  90 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
  91 {
  92   R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
  93   GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
  94   GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
  95   GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
  96   GENERAL_REGS, PR_REGS, T_REGS, NO_REGS,
  97   MAC_REGS, MAC_REGS, FPUL_REGS, GENERAL_REGS,
  98   FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
  99   FP_REGS, FP_REGS, FP_REGS, FP_REGS,
 100   FP_REGS, FP_REGS, FP_REGS, FP_REGS,
 101   FP_REGS, FP_REGS, FP_REGS, FP_REGS,
 102 };
 103
 104 /* Provide reg_class from a letter such as appears in the machine
 105    description.  */
 106
 107 enum reg_class reg_class_from_letter[] =
 108 {
 109   /* a */ NO_REGS, /* b */ NO_REGS, /* c */ NO_REGS, /* d */ NO_REGS,
 110   /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
 111   /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
 112   /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
 113   /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
 114   /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
 115   /* y */ FPUL_REGS, /* z */ R0_REGS
 116 };
 117 \f
 118 /* Print the operand address in x to the stream.  */
 119
 120 void
 121 print_operand_address (stream, x)
 122      FILE *stream;
 123      rtx x;
 124 {
 125   switch (GET_CODE (x))
 126     {
 127     case REG:
 128       fprintf (stream, "@%s", reg_names[REGNO (x)]);
 129       break;
 130
 131     case PLUS:
 132       {
 133         rtx base = XEXP (x, 0);
 134         rtx index = XEXP (x, 1);
 135
 136         switch (GET_CODE (index))
 137           {
 138           case CONST_INT:
 139             fprintf (stream, "@(%d,%s)", INTVAL (index),
 140                      reg_names[REGNO (base)]);
 141             break;
 142
 143           case REG:
 144             fprintf (stream, "@(r0,%s)",
 145                      reg_names[MAX (REGNO (base), REGNO (index))]);
 146             break;
 147
 148           default:
 149             debug_rtx (x);
 150             abort ();
 151           }
 152       }
 153       break;
 154
 155     case PRE_DEC:
 156       fprintf (stream, "@-%s", reg_names[REGNO (XEXP (x, 0))]);
 157       break;
 158
 159     case POST_INC:
 160       fprintf (stream, "@%s+", reg_names[REGNO (XEXP (x, 0))]);
 161       break;
 162
 163     default:
 164       output_addr_const (stream, x);
 165       break;
 166     }
 167 }
 168
 169 /* Print operand x (an rtx) in assembler syntax to file stream
 170    according to modifier code.
 171
 172    '.'  print a .s if insn needs delay slot
 173    '@'  print trap, rte or rts depending upon pragma interruptness
 174    '#'  output a nop if there is nothing to put in the delay slot
 175    'O'  print a constant without the #
 176    'R'  print the LSW of a dp value - changes if in little endian
 177    'S'  print the MSW of a dp value - changes if in little endian
 178    'T'  print the next word of a dp value - same as 'R' in big endian mode.  */
 179
 180 void
 181 print_operand (stream, x, code)
 182      FILE *stream;
 183      rtx x;
 184      int code;
 185 {
 186   switch (code)
 187     {
 188     case '.':
 189       if (final_sequence
 190           && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
 191         fprintf (stream, ".s");
 192       break;
 193     case '@':
 194       if (trap_exit)
 195         fprintf (stream, "trapa #%d", trap_exit);
 196       else if (pragma_interrupt)
 197         fprintf (stream, "rte");
 198       else
 199         fprintf (stream, "rts");
 200       break;
 201     case '#':
 202       /* Output a nop if there's nothing in the delay slot.  */
 203       if (dbr_sequence_length () == 0)
 204         fprintf (stream, "\n\tnop");
 205       break;
 206     case 'O':
 207       output_addr_const (stream, x);
 208       break;
 209     case 'R':
 210       fputs (reg_names[REGNO (x) + LSW], (stream));
 211       break;
 212     case 'S':
 213       fputs (reg_names[REGNO (x) + MSW], (stream));
 214       break;
 215     case 'T':
 216       /* Next word of a double.  */
 217       switch (GET_CODE (x))
 218         {
 219         case REG:
 220           fputs (reg_names[REGNO (x) + 1], (stream));
 221           break;
 222         case MEM:
 223           print_operand_address (stream,
 224                                  XEXP (adj_offsettable_operand (x, 4), 0));
 225           break;
 226         }
 227       break;
 228     default:
 229       switch (GET_CODE (x))
 230         {
 231         case REG:
 232           fputs (reg_names[REGNO (x)], (stream));
 233           break;
 234         case MEM:
 235           output_address (XEXP (x, 0));
 236           break;
 237         default:
 238           fputc ('#', stream);
 239           output_addr_const (stream, x);
 240           break;
 241         }
 242       break;
 243     }
 244 }
 245 \f
 246 /* Emit code to perform a block move.  Choose the best method.
 247
 248    OPERANDS[0] is the destination.
 249    OPERANDS[1] is the source.
 250    OPERANDS[2] is the size.
 251    OPERANDS[3] is the alignment safe to use.  */
 252
 253 int
 254 expand_block_move (operands)
 255      rtx *operands;
 256 {
 257   int align = INTVAL (operands[3]);
 258   int constp = (GET_CODE (operands[2]) == CONST_INT);
 259   int bytes = (constp ? INTVAL (operands[2]) : 0);
 260
 261   /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
 262      alignment, or if it isn't a multiple of 4 bytes, then fail.  */
 263   if (! constp || align < 4 || (bytes % 4 != 0))
 264     return 0;
 265
 266   if (bytes < 64)
 267     {
 268       char entry[30];
 269       tree entry_name;
 270       rtx func_addr_rtx;
 271       rtx r4 = gen_rtx (REG, SImode, 4);
 272       rtx r5 = gen_rtx (REG, SImode, 5);
 273
 274       sprintf (entry, "__movstrSI%d", bytes);
 275       entry_name = get_identifier (entry);
 276
 277       func_addr_rtx
 278         = copy_to_mode_reg (Pmode,
 279                             gen_rtx (SYMBOL_REF, Pmode,
 280                                      IDENTIFIER_POINTER (entry_name)));
 281       emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
 282       emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
 283       emit_insn (gen_block_move_real (func_addr_rtx));
 284       return 1;
 285     }
 286
 287   /* This is the same number of bytes as a memcpy call, but to a different
 288      less common function name, so this will occasionally use more space.  */
 289   if (! TARGET_SMALLCODE)
 290     {
 291       tree entry_name;
 292       rtx func_addr_rtx;
 293       int final_switch, while_loop;
 294       rtx r4 = gen_rtx (REG, SImode, 4);
 295       rtx r5 = gen_rtx (REG, SImode, 5);
 296       rtx r6 = gen_rtx (REG, SImode, 6);
 297
 298       entry_name = get_identifier ("__movstr");
 299       func_addr_rtx
 300         = copy_to_mode_reg (Pmode,
 301                             gen_rtx (SYMBOL_REF, Pmode,
 302                                      IDENTIFIER_POINTER (entry_name)));
 303       emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
 304       emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
 305
 306       /* r6 controls the size of the move.  16 is decremented from it
 307          for each 64 bytes moved.  Then the negative bit left over is used
 308          as an index into a list of move instructions.  e.g., a 72 byte move
 309          would be set up with size(r6) = 14, for one iteration through the
 310          big while loop, and a switch of -2 for the last part.  */
 311
 312       final_switch = 16 - ((bytes / 4) % 16);
 313       while_loop = ((bytes / 4) / 16 - 1) * 16;
 314       emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
 315       emit_insn (gen_block_lump_real (func_addr_rtx));
 316       return 1;
 317     }
 318
 319   return 0;
 320 }
 321
 322 /* Prepare operands for a move define_expand; specifically, one of the
 323    operands must be in a register.  */
 324
 325 int
 326 prepare_move_operands (operands, mode)
 327      rtx operands[];
 328      enum machine_mode mode;
 329 {
 330   if (! reload_in_progress && ! reload_completed)
 331     {
 332       /* Copy the source to a register if both operands aren't registers.  */
 333       if (! register_operand (operands[0], mode)
 334           && ! register_operand (operands[1], mode))
 335         operands[1] = copy_to_mode_reg (mode, operands[1]);
 336
 337       /* This case can happen while generating code to move the result
 338          of a library call to the target.  Reject `st r0,@(rX,rY)' because
 339          reload will fail to find a spill register for rX, since r0 is already
 340          being used for the source.  */
 341       else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
 342                && GET_CODE (operands[0]) == MEM
 343                && GET_CODE (XEXP (operands[0], 0)) == PLUS
 344                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
 345         operands[1] = copy_to_mode_reg (mode, operands[1]);
 346     }
 347
 348   return 0;
 349 }
 350
 351 /* Prepare the operands for an scc instruction; make sure that the
 352    compare has been done.  */
 353 rtx
 354 prepare_scc_operands (code)
 355      enum rtx_code code;
 356 {
 357   rtx t_reg = gen_rtx (REG, SImode, T_REG);
 358   enum rtx_code oldcode = code;
 359   enum machine_mode mode;
 360
 361   /* First need a compare insn.  */
 362   switch (code)
 363     {
 364     case NE:
 365       /* It isn't possible to handle this case.  */
 366       abort ();
 367     case LT:
 368       code = GT;
 369       break;
 370     case LE:
 371       code = GE;
 372       break;
 373     case LTU:
 374       code = GTU;
 375       break;
 376     case LEU:
 377       code = GEU;
 378       break;
 379     }
 380   if (code != oldcode)
 381     {
 382       rtx tmp = sh_compare_op0;
 383       sh_compare_op0 = sh_compare_op1;
 384       sh_compare_op1 = tmp;
 385     }
 386
 387   mode = GET_MODE (sh_compare_op0);
 388   if (mode == VOIDmode)
 389     mode = GET_MODE (sh_compare_op1);
 390
 391   sh_compare_op0 = force_reg (mode, sh_compare_op0);
 392   if (code != EQ && code != NE
 393       && (sh_compare_op1 != const0_rtx
 394           || code == GTU  || code == GEU || code == LTU || code == LEU))
 395     sh_compare_op1 = force_reg (mode, sh_compare_op1);
 396
 397   /* ??? This should be `mode' not `SImode' in the compare, but that would
 398      require fixing the branch patterns too.  */
 399   emit_insn (gen_rtx (SET, VOIDmode, t_reg,
 400                       gen_rtx (code, SImode, sh_compare_op0,
 401                                sh_compare_op1)));
 402
 403   return t_reg;
 404 }
 405
 406 /* Called from the md file, set up the operands of a compare instruction.  */
 407
 408 void
 409 from_compare (operands, code)
 410      rtx *operands;
 411      int code;
 412 {
 413   if (code != EQ && code != NE)
 414     {
 415       enum machine_mode mode = GET_MODE (sh_compare_op0);
 416       if (mode == VOIDmode)
 417         mode = GET_MODE (sh_compare_op1);
 418
 419       /* Force args into regs, since we can't use constants here.  */
 420       sh_compare_op0 = force_reg (mode, sh_compare_op0);
 421       if (sh_compare_op1 != const0_rtx
 422           || code == GTU  || code == GEU || code == LTU || code == LEU)
 423         sh_compare_op1 = force_reg (mode, sh_compare_op1);
 424     }
 425   operands[1] = sh_compare_op0;
 426   operands[2] = sh_compare_op1;
 427 }
 428 \f
 429 /* Functions to output assembly code.  */
 430
 431 /* Return a sequence of instructions to perform DI or DF move.
 432
 433    Since the SH cannot move a DI or DF in one instruction, we have
 434    to take care when we see overlapping source and dest registers.  */
 435
 436 char *
 437 output_movedouble (insn, operands, mode)
 438      rtx insn;
 439      rtx operands[];
 440      enum machine_mode mode;
 441 {
 442   rtx dst = operands[0];
 443   rtx src = operands[1];
 444
 445   if (GET_CODE (dst) == MEM
 446       && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
 447     return "mov.l       %T1,%0\n\tmov.l %1,%0";
 448
 449   if (register_operand (dst, mode)
 450       && register_operand (src, mode))
 451     {
 452       if (REGNO (src) == MACH_REG)
 453         return "sts     mach,%S0\n\tsts macl,%R0";
 454
 455       /* When mov.d r1,r2 do r2->r3 then r1->r2;
 456          when mov.d r1,r0 do r1->r0 then r2->r1.  */
 457
 458       if (REGNO (src) + 1 == REGNO (dst))
 459         return "mov     %T1,%T0\n\tmov  %1,%0";
 460       else
 461         return "mov     %1,%0\n\tmov    %T1,%T0";
 462     }
 463   else if (GET_CODE (src) == CONST_INT)
 464     {
 465       if (INTVAL (src) < 0)
 466         output_asm_insn ("mov   #-1,%S0", operands);
 467       else
 468         output_asm_insn ("mov   #0,%S0", operands);
 469
 470       return "mov       %1,%R0";
 471     }
 472   else if (GET_CODE (src) == MEM)
 473     {
 474       int ptrreg = -1;
 475       int dreg = REGNO (dst);
 476       rtx inside = XEXP (src, 0);
 477
 478       if (GET_CODE (inside) == REG)
 479         ptrreg = REGNO (inside);
 480       else if (GET_CODE (inside) == SUBREG)
 481         ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside);
 482       else if (GET_CODE (inside) == PLUS)
 483         {
 484           ptrreg = REGNO (XEXP (inside, 0));
 485           /* ??? A r0+REG address shouldn't be possible here, because it isn't
 486              an offsettable address.  Unfortunately, offsettable addresses use
 487              QImode to check the offset, and a QImode offsettable address
 488              requires r0 for the other operand, which is not currently
 489              supported, so we can't use the 'o' constraint.
 490              Thus we must check for and handle r0+REG addresses here.
 491              We punt for now, since this is likely very rare.  */
 492           if (GET_CODE (XEXP (inside, 1)) == REG)
 493             abort ();
 494         }
 495       else if (GET_CODE (inside) == LABEL_REF)
 496         return "mov.l   %1,%0\n\tmov.l  %1+4,%T0";
 497       else if (GET_CODE (inside) == POST_INC)
 498         return "mov.l   %1,%0\n\tmov.l  %1,%T0";
 499       else
 500         abort ();
 501
 502       /* Work out the safe way to copy.  Copy into the second half first.  */
 503       if (dreg == ptrreg)
 504         return "mov.l   %T1,%T0\n\tmov.l        %1,%0";
 505     }
 506
 507   return "mov.l %1,%0\n\tmov.l  %T1,%T0";
 508 }
 509
 510 /* Print an instruction which would have gone into a delay slot after
 511    another instruction, but couldn't because the other instruction expanded
 512    into a sequence where putting the slot insn at the end wouldn't work.  */
 513
 514 static void
 515 print_slot (insn)
 516      rtx insn;
 517 {
 518   final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
 519
 520   INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
 521 }
 522
 523 /* We can't tell if we need a register as a scratch for the jump
 524    until after branch shortening, and then it's too late to allocate a
 525    register the 'proper' way.  These instruction sequences are rare
 526    anyway, so to avoid always using a reg up from our limited set, we'll
 527    grab one when we need one on output.  */
 528
 529 /* ??? Should fix compiler so that using a clobber scratch in jump
 530    instructions works, and then this will be unnecessary.  */
 531
 532 char *
 533 output_far_jump (insn, op)
 534      rtx insn;
 535      rtx op;
 536 {
 537   rtx thislab = gen_label_rtx ();
 538
 539   /* Output the delay slot insn first if any.  */
 540   if (dbr_sequence_length ())
 541     print_slot (final_sequence);
 542
 543   output_asm_insn ("mov.l       r13,@-r15", 0);
 544   output_asm_insn ("mov.l       %O0,r13", &thislab);
 545   output_asm_insn ("jmp @r13", 0);
 546   output_asm_insn ("mov.l       @r15+,r13", 0);
 547   output_asm_insn (".align      2", 0);
 548   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (thislab));
 549   output_asm_insn (".long       %O0", &op);
 550   return "";
 551 }
 552
 553 /* Local label counter, used for constants in the pool and inside
 554    pattern branches.  */
 555
 556 static int lf = 100;
 557
 558 /* Output code for ordinary branches.  */
 559
 560 char *
 561 output_branch (logic, insn, operands)
 562      int logic;
 563      rtx insn;
 564      rtx *operands;
 565 {
 566   int label = lf++;
 567   int length = get_attr_length (insn);
 568   int adjusted_length;
 569
 570   /* Undo the effects of ADJUST_INSN_LENGTH, so that we get the real
 571      length.  If NEXT_INSN (PREV_INSN (insn)) != insn, then the insn
 572      is inside a sequence, and ADJUST_INSN_LENGTH was not called on
 573      it.  */
 574   if (PREV_INSN (insn) == NULL
 575       || NEXT_INSN (PREV_INSN (insn)) == insn)
 576     {
 577       adjusted_length = length;
 578       ADJUST_INSN_LENGTH (insn, adjusted_length);
 579       length -= (adjusted_length - length);
 580     }
 581
 582   switch (length)
 583     {
 584     case 2:
 585       /* A branch with an unfilled delay slot.  */
 586     case 4:
 587       /* Simple branch in range -252..+258 bytes */
 588       return logic ? "bt%.      %l0" : "bf%.    %l0";
 589
 590     case 6:
 591       /* A branch with an unfilled delay slot.  */
 592     case 8:
 593       /* Branch in range -4092..+4098 bytes.  */
 594       {
 595         /* The call to print_slot will clobber the operands.  */
 596         rtx op0 = operands[0];
 597
 598         /* If the instruction in the delay slot is annulled (true), then
 599            there is no delay slot where we can put it now.  The only safe
 600            place for it is after the label.  */
 601
 602         if (final_sequence)
 603           {
 604             fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
 605                      INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
 606                      ? "" : ".s", label);
 607             if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
 608               print_slot (final_sequence);
 609           }
 610         else
 611           fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
 612
 613         output_asm_insn ("bra   %l0", &op0);
 614         fprintf (asm_out_file, "\tnop\n");
 615         fprintf (asm_out_file, "LF%d:\n", label);
 616
 617         if (final_sequence
 618             && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
 619           print_slot (final_sequence);
 620       }
 621       return "";
 622
 623     case 16:
 624       /* A branch with an unfilled delay slot.  */
 625     case 18:
 626       /* Branches a long way away.  */
 627       {
 628         /* The call to print_slot will clobber the operands.  */
 629         rtx op0 = operands[0];
 630
 631         /* If the instruction in the delay slot is annulled (true), then
 632            there is no delay slot where we can put it now.  The only safe
 633            place for it is after the label.  */
 634
 635         if (final_sequence)
 636           {
 637             fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
 638                      INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
 639                      ? "" : ".s", label);
 640             if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
 641               print_slot (final_sequence);
 642           }
 643         else
 644           fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
 645
 646         output_far_jump (insn, op0);
 647         fprintf (asm_out_file, "LF%d:\n", label);
 648
 649         if (final_sequence
 650             && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
 651           print_slot (final_sequence);
 652       }
 653       return "";
 654     }
 655
 656   abort ();
 657 }
 658 \f
 659 /* Output to FILE the start of the assembler file.  */
 660
 661 void
 662 output_file_start (file)
 663      FILE *file;
 664 {
 665   register int pos;
 666
 667   output_file_directive (file, main_input_filename);
 668
 669   /* Switch to the data section so that the coffsem symbol and the
 670      gcc2_compiled. symbol aren't in the text section.  */
 671   data_section ();
 672
 673   if (TARGET_LITTLE_ENDIAN)
 674     fprintf (file, "\t.little\n");
 675 }
 676 \f
 677 /* Actual number of instructions used to make a shift by N.  */
 678 static char ashiftrt_insns[] =
 679   { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
 680
 681 /* Left shift and logical right shift are the same.  */
 682 static char shift_insns[]    =
 683   { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
 684
 685 /* Individual shift amounts needed to get the above length sequences.
 686    One bit right shifts clobber the T bit, so when possible, put one bit
 687    shifts in the middle of the sequence, so the ends are eligible for
 688    branch delay slots.  */
 689 static short shift_amounts[32][5] = {
 690   {0}, {1}, {2}, {2, 1},
 691   {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
 692   {8}, {8, 1}, {8, 2}, {8, 1, 2},
 693   {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
 694   {16}, {16, 1}, {16, 2}, {16, 1, 2},
 695   {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
 696   {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
 697   {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
 698
 699 /* Likewise, but for shift amounts < 16, up to three highmost bits
 700    might be clobbered.  This is typically used when combined with some
 701    kind of sign or zero extension.  */
 702
 703 static char ext_shift_insns[]    =
 704   { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
 705
 706 static short ext_shift_amounts[32][4] = {
 707   {0}, {1}, {2}, {2, 1},
 708   {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
 709   {8}, {8, 1}, {8, 2}, {8, 1, 2},
 710   {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
 711   {16}, {16, 1}, {16, 2}, {16, 1, 2},
 712   {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
 713   {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
 714   {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
 715
 716 /* Assuming we have a value that has been sign-extended by at least one bit,
 717    can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
 718    to shift it by N without data loss, and quicker than by other means?  */
 719 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
 720
 721 /* This is used in length attributes in sh.md to help compute the length
 722    of arbitrary constant shift instructions.  */
 723
 724 int
 725 shift_insns_rtx (insn)
 726      rtx insn;
 727 {
 728   rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
 729   int shift_count = INTVAL (XEXP (set_src, 1));
 730   enum rtx_code shift_code = GET_CODE (set_src);
 731
 732   switch (shift_code)
 733     {
 734     case ASHIFTRT:
 735       return ashiftrt_insns[shift_count];
 736     case LSHIFTRT:
 737     case ASHIFT:
 738       return shift_insns[shift_count];
 739     default:
 740       abort();
 741     }
 742 }
 743
 744 /* Return the cost of a shift.  */
 745
 746 int
 747 shiftcosts (x)
 748      rtx x;
 749 {
 750   int value = INTVAL (XEXP (x, 1));
 751
 752   /* If shift by a non constant, then this will be expensive.  */
 753   if (GET_CODE (XEXP (x, 1)) != CONST_INT)
 754     {
 755       if (TARGET_SH3)
 756         return 2;
 757       /* If not an sh3 then we don't even have an instruction for it.  */
 758       return 20;
 759     }
 760
 761   /* Otherwise, return the true cost in instructions.  */
 762   if (GET_CODE (x) == ASHIFTRT)
 763     {
 764       int cost = ashiftrt_insns[value];
 765       /* If SH3, then we put the constant in a reg and use shad.  */
 766       if (TARGET_SH3 && cost > 3)
 767         cost = 3;
 768       return cost;
 769     }
 770   else
 771     return shift_insns[value];
 772 }
 773
 774 /* Return the cost of an AND operation.  */
 775
 776 int
 777 andcosts (x)
 778      rtx x;
 779 {
 780   int i;
 781
 782   /* Anding with a register is a single cycle and instruction.  */
 783   if (GET_CODE (XEXP (x, 1)) != CONST_INT)
 784     return 1;
 785
 786   i = INTVAL (XEXP (x, 1));
 787   /* These constants are single cycle extu.[bw] instructions.  */
 788   if (i == 0xff || i == 0xffff)
 789     return 1;
 790   /* Constants that can be used in an and immediate instruction is a single
 791      cycle, but this requires r0, so make it a little more expensive.  */
 792   if (CONST_OK_FOR_L (i))
 793     return 2;
 794   /* Constants that can be loaded with a mov immediate and an and.
 795      This case is probably unnecessary.  */
 796   if (CONST_OK_FOR_I (i))
 797     return 2;
 798   /* Any other constants requires a 2 cycle pc-relative load plus an and.
 799      This case is probably unnecessary.  */
 800   return 3;
 801 }
 802
 803 /* Return the cost of a multiply.  */
 804 int
 805 multcosts (x)
 806      rtx x;
 807 {
 808   if (TARGET_SH2)
 809     {
 810       /* We have a mul insn, so we can never take more than the mul and the
 811          read of the mac reg, but count more because of the latency and extra
 812          reg usage.  */
 813       if (TARGET_SMALLCODE)
 814         return 2;
 815       return 3;
 816     }
 817
 818   /* If we're aiming at small code, then just count the number of
 819      insns in a multiply call sequence.  */
 820   if (TARGET_SMALLCODE)
 821     return 5;
 822
 823   /* Otherwise count all the insns in the routine we'd be calling too.  */
 824   return 20;
 825 }
 826
 827 /* Code to expand a shift.  */
 828
 829 void
 830 gen_ashift (type, n, reg)
 831      int type;
 832      int n;
 833      rtx reg;
 834 {
 835   /* Negative values here come from the shift_amounts array.  */
 836   if (n < 0)
 837     {
 838       if (type == ASHIFT)
 839         type = LSHIFTRT;
 840       else
 841         type = ASHIFT;
 842       n = -n;
 843     }
 844
 845   switch (type)
 846     {
 847     case ASHIFTRT:
 848       emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
 849       break;
 850     case LSHIFTRT:
 851       if (n == 1)
 852         emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
 853       else
 854         emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
 855       break;
 856     case ASHIFT:
 857       emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
 858       break;
 859     }
 860 }
 861
 862 /* Same for HImode */
 863
 864 void
 865 gen_ashift_hi (type, n, reg)
 866      int type;
 867      int n;
 868      rtx reg;
 869 {
 870   /* Negative values here come from the shift_amounts array.  */
 871   if (n < 0)
 872     {
 873       if (type == ASHIFT)
 874         type = LSHIFTRT;
 875       else
 876         type = ASHIFT;
 877       n = -n;
 878     }
 879
 880   switch (type)
 881     {
 882     case ASHIFTRT:
 883       emit_insn (gen_ashrhi3_k (reg, reg, GEN_INT (n)));
 884       break;
 885     case LSHIFTRT:
 886       if (n == 1)
 887         emit_insn (gen_lshrhi3_m (reg, reg, GEN_INT (n)));
 888       else
 889         emit_insn (gen_lshrhi3_k (reg, reg, GEN_INT (n)));
 890       break;
 891     case ASHIFT:
 892       emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
 893       break;
 894     }
 895 }
 896
 897 /* Output RTL to split a constant shift into its component SH constant
 898    shift instructions.  */
 899
 900 int
 901 gen_shifty_op (code, operands)
 902      int code;
 903      rtx *operands;
 904 {
 905   int value = INTVAL (operands[2]);
 906   int max, i;
 907
 908   /* Truncate the shift count in case it is out of bounds.  */
 909   value = value & 0x1f;
 910
 911   if (value == 31)
 912     {
 913       if (code == LSHIFTRT)
 914         {
 915           emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
 916           emit_insn (gen_movt (operands[0]));
 917           return;
 918         }
 919       else if (code == ASHIFT)
 920         {
 921           /* There is a two instruction sequence for 31 bit left shifts,
 922              but it requires r0.  */
 923           if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
 924             {
 925               emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
 926               emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
 927               return;
 928             }
 929         }
 930     }
 931   else if (value == 0)
 932     {
 933       /* This can happen when not optimizing.  We must output something here
 934          to prevent the compiler from aborting in final.c after the try_split
 935          call.  */
 936       emit_insn (gen_nop ());
 937       return;
 938     }
 939
 940   max = shift_insns[value];
 941   for (i = 0; i < max; i++)
 942     gen_ashift (code, shift_amounts[value][i], operands[0]);
 943 }
 944
 945 /* Same as above, but optimized for values where the topmost bits don't
 946    matter.  */
 947
 948 int
 949 gen_shifty_hi_op (code, operands)
 950      int code;
 951      rtx *operands;
 952 {
 953   int value = INTVAL (operands[2]);
 954   int max, i;
 955   void (*gen_fun)();
 956
 957   /* This operation is used by and_shl for SImode values with a few
 958      high bits known to be cleared.  */
 959   value &= 31;
 960   if (value == 0)
 961     {
 962       emit_insn (gen_nop ());
 963       return;
 964     }
 965
 966   gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
 967   if (code == ASHIFT)
 968     {
 969       max = ext_shift_insns[value];
 970       for (i = 0; i < max; i++)
 971         gen_fun (code, ext_shift_amounts[value][i], operands[0]);
 972     }
 973   else
 974     /* When shifting right, emit the shifts in reverse order, so that
 975        solitary negative values come first.  */
 976     for (i = ext_shift_insns[value] - 1; i >= 0; i--)
 977       gen_fun (code, ext_shift_amounts[value][i], operands[0]);
 978 }
 979
 980 /* Output RTL for an arithmetic right shift.  */
 981
 982 /* ??? Rewrite to use super-optimizer sequences.  */
 983
 984 int
 985 expand_ashiftrt (operands)
 986      rtx *operands;
 987 {
 988   rtx wrk;
 989   char func[18];
 990   tree func_name;
 991   int value;
 992
 993   if (TARGET_SH3)
 994     {
 995       if (GET_CODE (operands[2]) != CONST_INT)
 996         {
 997           rtx count = copy_to_mode_reg (SImode, operands[2]);
 998           emit_insn (gen_negsi2 (count, count));
 999           emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1000           return 1;
1001         }
1002       else if (ashiftrt_insns[INTVAL (operands[2])] > 3)
1003         {
1004           rtx count = force_reg (SImode, GEN_INT (- INTVAL (operands[2])));
1005           emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1006           return 1;
1007         }
1008     }
1009   if (GET_CODE (operands[2]) != CONST_INT)
1010     return 0;
1011
1012   value = INTVAL (operands[2]);
1013
1014   if (value == 31)
1015     {
1016       emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1017       return 1;
1018     }
1019   else if (value >= 16 && value <= 19)
1020     {
1021       wrk = gen_reg_rtx (SImode);
1022       emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1023       value -= 16;
1024       while (value--)
1025         gen_ashift (ASHIFTRT, 1, wrk);
1026       emit_move_insn (operands[0], wrk);
1027       return 1;
1028     }
1029   /* Expand a short sequence inline, longer call a magic routine.  */
1030   else if (value <= 5)
1031     {
1032       wrk = gen_reg_rtx (SImode);
1033       emit_move_insn (wrk, operands[1]);
1034       while (value--)
1035         gen_ashift (ASHIFTRT, 1, wrk);
1036       emit_move_insn (operands[0], wrk);
1037       return 1;
1038     }
1039
1040   wrk = gen_reg_rtx (Pmode);
1041
1042   /* Load the value into an arg reg and call a helper.  */
1043   emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
1044   sprintf (func, "__ashiftrt_r4_%d", value);
1045   func_name = get_identifier (func);
1046   emit_move_insn (wrk, gen_rtx (SYMBOL_REF, Pmode,
1047                                 IDENTIFIER_POINTER (func_name)));
1048   emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1049   emit_move_insn (operands[0], gen_rtx (REG, SImode, 4));
1050   return 1;
1051 }
1052
1053 /* Try to find a good way to implement the combiner pattern
1054   [(set (match_operand:SI 0 "register_operand" "r")
1055         (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1056                            (match_operand:SI 2 "const_int_operand" "n"))
1057                 (match_operand:SI 3 "const_int_operand" "n"))) .
1058   LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1059   return 0 for simple right / left or left/right shift combination.
1060   return 1 for a combination of shifts with zero_extend.
1061   return 2 for a combination of shifts with an AND that needs r0.
1062   return 3 for a combination of shifts with an AND that needs an extra
1063     scratch register, when the three highmost bits of the AND mask are clear.
1064   return 4 for a combination of shifts with an AND that needs an extra
1065     scratch register, when any of the three highmost bits of the AND mask
1066     is set.
1067   If ATTRP is set, store an initial right shift width in ATTRP[0],
1068   and the instruction length in ATTRP[1] .  These values are not valid
1069   when returning 0.
1070   When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1071   shift_amounts for the last shift value that is to be used before the
1072   sign extend.  */
1073 int
1074 shl_and_kind (left_rtx, mask_rtx, attrp)
1075      rtx left_rtx, mask_rtx;
1076      int *attrp;
1077 {
1078   unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1079   int left = INTVAL (left_rtx), right;
1080   int best = 0;
1081   int cost, best_cost = 10000;
1082   int best_right = 0, best_len = 0;
1083   int i;
1084   int can_ext;
1085
1086   if (left < 0 || left > 31)
1087     return 0;
1088   if (GET_CODE (mask_rtx) == CONST_INT)
1089     mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1090   else
1091     mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1092   /* Can this be expressed as a right shift / left shift pair ? */
1093   lsb = ((mask ^ (mask - 1)) >> 1) + 1;
1094   right = exact_log2 (lsb);
1095   mask2 = ~(mask + lsb - 1);
1096   lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
1097   /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1098   if (! mask2)
1099     best_cost = shift_insns[right] + shift_insns[right + left];
1100   /* mask has no trailing zeroes <==> ! right */
1101   else if (! right && mask2 == ~(lsb2 - 1))
1102     {
1103       int late_right = exact_log2 (lsb2);
1104       best_cost = shift_insns[left + late_right] + shift_insns[late_right];
1105     }
1106   /* Try to use zero extend */
1107   if (mask2 == ~(lsb2 - 1))
1108     {
1109       int width, first;
1110
1111       for (width = 8; width <= 16; width += 8)
1112         {
1113           /* Can we zero-extend right away? */
1114           if (lsb2 == (HOST_WIDE_INT)1 << width)
1115             {
1116               cost
1117                 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
1118               if (cost < best_cost)
1119                 {
1120                   best = 1;
1121                   best_cost = cost;
1122                   best_right = right;
1123                   best_len = cost;
1124                   if (attrp)
1125                     attrp[2] = -1;
1126                 }
1127               continue;
1128             }
1129           /* ??? Could try to put zero extend into initial right shift,
1130              or even shift a bit left before the right shift. */
1131           /* Determine value of first part of left shift, to get to the
1132              zero extend cut-off point.  */
1133           first = width - exact_log2 (lsb2) + right;
1134           if (first >= 0 && right + left - first >= 0)
1135             {
1136               cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
1137                 + ext_shift_insns[right + left - first];
1138               if (cost < best_cost)
1139                 {
1140                   best = 1;
1141                   best_cost = cost;
1142                   best_right = right;
1143                   best_len = cost;
1144                   if (attrp)
1145                     attrp[2] = first;
1146                   }
1147             }
1148         }
1149     }
1150   /* Try to use r0 AND pattern */
1151   for (i = 0; i <= 2; i++)
1152     {
1153       if (i > right)
1154         break;
1155       if (! CONST_OK_FOR_L (mask >> i))
1156         continue;
1157       cost = (i != 0) + 2 + ext_shift_insns[left + i];
1158       if (cost < best_cost)
1159         {
1160           best = 2;
1161           best_cost = cost;
1162           best_right = i;
1163           best_len = cost - 1;
1164         }
1165     }
1166   /* Try to use a scratch register to hold the AND operand.  */
1167   can_ext = ((mask << left) & 0xe0000000) == 0;
1168   for (i = 0; i <= 2; i++)
1169     {
1170       if (i > right)
1171         break;
1172       cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
1173         + (can_ext ? ext_shift_insns : shift_insns)[left + i];
1174       if (cost < best_cost)
1175         {
1176           best = 4 - can_ext;
1177           best_cost = cost;
1178           best_right = i;
1179           best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
1180         }
1181     }
1182
1183   if (attrp)
1184     {
1185       attrp[0] = best_right;
1186       attrp[1] = best_len;
1187     }
1188   return best;
1189 }
1190
1191 /* This is used in length attributes of the unnamed instructions
1192    corresponding to shl_and_kind return values of 1 and 2.  */
1193 int
1194 shl_and_length (insn)
1195      rtx insn;
1196 {
1197   rtx set_src, left_rtx, mask_rtx;
1198   int attributes[3];
1199
1200   set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1201   left_rtx = XEXP (XEXP (set_src, 0), 1);
1202   mask_rtx = XEXP (set_src, 1);
1203   shl_and_kind (left_rtx, mask_rtx, attributes);
1204   return attributes[1];
1205 }
1206
1207 /* This is used in length attribute of the and_shl_scratch instruction.  */
1208
1209 int
1210 shl_and_scr_length (insn)
1211      rtx insn;
1212 {
1213   rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1214   int len = shift_insns[INTVAL (XEXP (set_src, 1))];
1215   rtx op = XEXP (set_src, 0);
1216   len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
1217   op = XEXP (XEXP (op, 0), 0);
1218   return len + shift_insns[INTVAL (XEXP (op, 1))];
1219 }
1220
1221 /* Generating rtl? */
1222 extern int rtx_equal_function_value_matters;
1223
1224 /* Generate rtl for instructions for which shl_and_kind advised a particular
1225    method of generating them, i.e. returned zero.  */
1226
1227 int
1228 gen_shl_and (dest, left_rtx, mask_rtx, source)
1229      rtx dest, left_rtx, mask_rtx, source;
1230 {
1231   int attributes[3];
1232   unsigned HOST_WIDE_INT mask;
1233   int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
1234   int right, total_shift;
1235   int (*shift_gen_fun) PROTO((int, rtx*)) = gen_shifty_hi_op;
1236
1237   right = attributes[0];
1238   total_shift = INTVAL (left_rtx) + right;
1239   mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
1240   switch (kind)
1241     {
1242     default:
1243       return -1;
1244     case 1:
1245       {
1246         int first = attributes[2];
1247         rtx operands[3];
1248
1249         if (first < 0)
1250           {
1251             emit_insn ((mask << right) == 0xff
1252                        ? gen_zero_extendqisi2(dest,
1253                                               gen_lowpart (QImode, source))
1254                        : gen_zero_extendhisi2(dest,
1255                                               gen_lowpart (HImode, source)));
1256             source = dest;
1257           }
1258         if (source != dest)
1259           emit_insn (gen_movsi (dest, source));
1260         operands[0] = dest;
1261         if (right)
1262           {
1263             operands[2] = GEN_INT (right);
1264             gen_shifty_hi_op (LSHIFTRT, operands);
1265           }
1266         if (first > 0)
1267           {
1268             operands[2] = GEN_INT (first);
1269             gen_shifty_hi_op (ASHIFT, operands);
1270             total_shift -= first;
1271             mask <<= first;
1272           }
1273         if (first >= 0)
1274           emit_insn (mask == 0xff
1275                      ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
1276                      : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
1277         if (total_shift > 0)
1278           {
1279             operands[2] = GEN_INT (total_shift);
1280             gen_shifty_hi_op (ASHIFT, operands);
1281           }
1282         break;
1283       }
1284     case 4:
1285       shift_gen_fun = gen_shifty_op;
1286     case 2:
1287     case 3:
1288       /* If the topmost bit that matters is set, set the topmost bits
1289          that don't matter.  This way, we might be able to get a shorter
1290          signed constant.  */
1291       if (mask & ((HOST_WIDE_INT)1 << 31 - total_shift))
1292         mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
1293       /* Don't expand fine-grained when combining, because that will
1294          make the pattern fail.  */
1295       if (rtx_equal_function_value_matters
1296           || reload_in_progress || reload_completed)
1297         {
1298           rtx operands[3];
1299
1300           if (right)
1301             {
1302               emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
1303               source = dest;
1304             }
1305           emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
1306           if (total_shift)
1307             {
1308               operands[0] = dest;
1309               operands[1] = dest;
1310               operands[2] = GEN_INT (total_shift);
1311               shift_gen_fun (ASHIFT, operands);
1312             }
1313           break;
1314         }
1315       else
1316         {
1317           int neg = 0;
1318           if (kind != 4 && total_shift < 16)
1319             {
1320               neg = -ext_shift_amounts[total_shift][1];
1321               if (neg > 0)
1322                 neg -= ext_shift_amounts[total_shift][2];
1323               else
1324                 neg = 0;
1325             }
1326           emit_insn (gen_and_shl_scratch (dest, source,
1327                                           GEN_INT (right),
1328                                           GEN_INT (mask),
1329                                           GEN_INT (total_shift + neg),
1330                                           GEN_INT (neg)));
1331           emit_insn (gen_movsi (dest, dest));
1332           break;
1333         }
1334     }
1335   return 0;
1336 }
1337
1338 /* Try to find a good way to implement the combiner pattern
1339   [(set (match_operand:SI 0 "register_operand" "=r")
1340         (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1341                                     (match_operand:SI 2 "const_int_operand" "n")
1342                          (match_operand:SI 3 "const_int_operand" "n")
1343                          (const_int 0)))
1344    (clobber (reg:SI 18))]
1345   LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1346   return 0 for simple left / right shift combination.
1347   return 1 for left shift / 8 bit sign extend / left shift.
1348   return 2 for left shift / 16 bit sign extend / left shift.
1349   return 3 for left shift / 8 bit sign extend / shift / sign extend.
1350   return 4 for left shift / 16 bit sign extend / shift / sign extend.
1351   return 5 for left shift / 16 bit sign extend / right shift
1352   return 6 for < 8 bit sign extend / left shift.
1353   return 7 for < 8 bit sign extend / left shift / single right shift.
1354   If COSTP is nonzero, assign the calculated cost to *COSTP.  */
1355
1356 int
1357 shl_sext_kind (left_rtx, size_rtx, costp)
1358      rtx left_rtx, size_rtx;
1359      int *costp;
1360 {
1361   int left, size, insize, ext;
1362   int cost, best_cost;
1363   int kind;
1364
1365   left = INTVAL (left_rtx);
1366   size = INTVAL (size_rtx);
1367   insize = size - left;
1368   if (insize <= 0)
1369     abort ();
1370   /* Default to left / right shift.  */
1371   kind = 0;
1372   best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
1373   if (size <= 16)
1374     {
1375       /* 16 bit shift / sign extend / 16 bit shift */
1376       cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
1377       /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1378          below, by alternative 3 or something even better.  */
1379       if (cost < best_cost)
1380         {
1381           kind = 5;
1382           best_cost = cost;
1383         }
1384     }
1385   /* Try a plain sign extend between two shifts.  */
1386   for (ext = 16; ext >= insize; ext -= 8)
1387     {
1388       if (ext <= size)
1389         {
1390           cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
1391           if (cost < best_cost)
1392             {
1393               kind = ext / 8U;
1394               best_cost = cost;
1395             }
1396         }
1397       /* Check if we can do a sloppy shift with a final signed shift
1398          restoring the sign.  */
1399       if (EXT_SHIFT_SIGNED (size - ext))
1400         cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
1401       /* If not, maybe it's still cheaper to do the second shift sloppy,
1402          and do a final sign extend?  */
1403       else if (size <= 16)
1404         cost = ext_shift_insns[ext - insize] + 1
1405           + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
1406       else
1407         continue;
1408       if (cost < best_cost)
1409         {
1410           kind = ext / 8U + 2;
1411           best_cost = cost;
1412         }
1413     }
1414   /* Check if we can sign extend in r0 */
1415   if (insize < 8)
1416     {
1417       cost = 3 + shift_insns[left];
1418       if (cost < best_cost)
1419         {
1420           kind = 6;
1421           best_cost = cost;
1422         }
1423       /* Try the same with a final signed shift.  */
1424       if (left < 31)
1425         {
1426           cost = 3 + ext_shift_insns[left + 1] + 1;
1427           if (cost < best_cost)
1428             {
1429               kind = 7;
1430               best_cost = cost;
1431             }
1432         }
1433     }
1434   if (TARGET_SH3)
1435     {
1436       /* Try to use a dynamic shift.  */
1437       cost = shift_insns[32 - insize] + 3;
1438       if (cost < best_cost)
1439         {
1440           kind = 0;
1441           best_cost = cost;
1442         }
1443     }
1444   if (costp)
1445     *costp = cost;
1446   return kind;
1447 }
1448
1449 /* Function to be used in the length attribute of the instructions
1450    implementing this pattern.  */
1451
1452 int
1453 shl_sext_length (insn)
1454      rtx insn;
1455 {
1456   rtx set_src, left_rtx, size_rtx;
1457   int cost;
1458
1459   set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1460   left_rtx = XEXP (XEXP (set_src, 0), 1);
1461   size_rtx = XEXP (set_src, 1);
1462   shl_sext_kind (left_rtx, size_rtx, &cost);
1463   return cost;
1464 }
1465
1466 /* Generate rtl for this pattern */
1467
1468 int
1469 gen_shl_sext (dest, left_rtx, size_rtx, source)
1470      rtx dest, left_rtx, size_rtx, source;
1471 {
1472   int kind;
1473   int left, size, insize, cost;
1474   rtx operands[3];
1475
1476   kind = shl_sext_kind (left_rtx, size_rtx, &cost);
1477   left = INTVAL (left_rtx);
1478   size = INTVAL (size_rtx);
1479   insize = size - left;
1480   switch (kind)
1481     {
1482     case 1:
1483     case 2:
1484     case 3:
1485     case 4:
1486       {
1487         int ext = kind & 1 ? 8 : 16;
1488         int shift2 = size - ext;
1489
1490         /* Don't expand fine-grained when combining, because that will
1491            make the pattern fail.  */
1492         if (! rtx_equal_function_value_matters
1493             && ! reload_in_progress && ! reload_completed)
1494           {
1495             emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
1496             emit_insn (gen_movsi (dest, source));
1497             break;
1498           }
1499         if (dest != source)
1500           emit_insn (gen_movsi (dest, source));
1501         operands[0] = dest;
1502         if (ext - insize)
1503           {
1504             operands[2] = GEN_INT (ext - insize);
1505             gen_shifty_hi_op (ASHIFT, operands);
1506           }
1507         emit_insn (kind & 1
1508                    ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
1509                    : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
1510         if (kind <= 2)
1511           {
1512             if (shift2)
1513               {
1514                 operands[2] = GEN_INT (shift2);
1515                 gen_shifty_op (ASHIFT, operands);
1516               }
1517           }
1518         else
1519           {
1520             if (shift2 > 0)
1521               {
1522                 if (EXT_SHIFT_SIGNED (shift2))
1523                   {
1524                     operands[2] = GEN_INT (shift2 + 1);
1525                     gen_shifty_op (ASHIFT, operands);
1526                     operands[2] = GEN_INT (1);
1527                     gen_shifty_op (ASHIFTRT, operands);
1528                     break;
1529                   }
1530                 operands[2] = GEN_INT (shift2);
1531                 gen_shifty_hi_op (ASHIFT, operands);
1532               }
1533             else if (shift2)
1534               {
1535                 operands[2] = GEN_INT (-shift2);
1536                 gen_shifty_hi_op (LSHIFTRT, operands);
1537               }
1538             emit_insn (size <= 8
1539                        ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
1540                        : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
1541           }
1542         break;
1543       }
1544     case 5:
1545       {
1546         int i = 16 - size;
1547         emit_insn (gen_shl_sext_ext (dest, source, GEN_INT (16 - insize),
1548                                      GEN_INT (16)));
1549         /* Don't use gen_ashrsi3 because it generates new pseudos.  */
1550         while (--i >= 0)
1551           gen_ashift (ASHIFTRT, 1, dest);
1552         break;
1553       }
1554     case 6:
1555     case 7:
1556       /* Don't expand fine-grained when combining, because that will
1557          make the pattern fail.  */
1558       if (! rtx_equal_function_value_matters
1559           && ! reload_in_progress && ! reload_completed)
1560         {
1561           emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
1562           emit_insn (gen_movsi (dest, source));
1563           break;
1564         }
1565       emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
1566       emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
1567       emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
1568       operands[0] = dest;
1569       operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
1570       gen_shifty_op (ASHIFT, operands);
1571       if (kind == 7)
1572         emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
1573       break;
1574     default:
1575       return -1;
1576     }
1577   return 0;
1578 }
1579 \f
1580 /* The SH cannot load a large constant into a register, constants have to
1581    come from a pc relative load.  The reference of a pc relative load
1582    instruction must be less than 1k infront of the instruction.  This
1583    means that we often have to dump a constant inside a function, and
1584    generate code to branch around it.
1585
1586    It is important to minimize this, since the branches will slow things
1587    down and make things bigger.
1588
1589    Worst case code looks like:
1590
1591    mov.l L1,rn
1592    bra   L2
1593    nop
1594    align
1595    L1:   .long value
1596    L2:
1597    ..
1598
1599    mov.l L3,rn
1600    bra   L4
1601    nop
1602    align
1603    L3:   .long value
1604    L4:
1605    ..
1606
1607    We fix this by performing a scan before scheduling, which notices which
1608    instructions need to have their operands fetched from the constant table
1609    and builds the table.
1610
1611    The algorithm is:
1612
1613    scan, find an instruction which needs a pcrel move.  Look forward, find the
1614    last barrier which is within MAX_COUNT bytes of the requirement.
1615    If there isn't one, make one.  Process all the instructions between
1616    the find and the barrier.
1617
1618    In the above example, we can tell that L3 is within 1k of L1, so
1619    the first move can be shrunk from the 3 insn+constant sequence into
1620    just 1 insn, and the constant moved to L3 to make:
1621
1622    mov.l        L1,rn
1623    ..
1624    mov.l        L3,rn
1625    bra          L4
1626    nop
1627    align
1628    L3:.long value
1629    L4:.long value
1630
1631    Then the second move becomes the target for the shortening process.  */
1632
1633 typedef struct
1634 {
1635   rtx value;                    /* Value in table.  */
1636   rtx label;                    /* Label of value.  */
1637   enum machine_mode mode;       /* Mode of value.  */
1638 } pool_node;
1639
1640 /* The maximum number of constants that can fit into one pool, since
1641    the pc relative range is 0...1020 bytes and constants are at least 4
1642    bytes long.  */
1643
1644 #define MAX_POOL_SIZE (1020/4)
1645 static pool_node pool_vector[MAX_POOL_SIZE];
1646 static int pool_size;
1647
1648 /* ??? If we need a constant in HImode which is the truncated value of a
1649    constant we need in SImode, we could combine the two entries thus saving
1650    two bytes.  Is this common enough to be worth the effort of implementing
1651    it?  */
1652
1653 /* ??? This stuff should be done at the same time that we shorten branches.
1654    As it is now, we must assume that all branches are the maximum size, and
1655    this causes us to almost always output constant pools sooner than
1656    necessary.  */
1657
1658 /* Add a constant to the pool and return its label.  */
1659
1660 static rtx
1661 add_constant (x, mode)
1662      rtx x;
1663      enum machine_mode mode;
1664 {
1665   int i;
1666   rtx lab;
1667
1668   /* First see if we've already got it.  */
1669   for (i = 0; i < pool_size; i++)
1670     {
1671       if (x->code == pool_vector[i].value->code
1672           && mode == pool_vector[i].mode)
1673         {
1674           if (x->code == CODE_LABEL)
1675             {
1676               if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
1677                 continue;
1678             }
1679           if (rtx_equal_p (x, pool_vector[i].value))
1680             return pool_vector[i].label;
1681         }
1682     }
1683
1684   /* Need a new one.  */
1685   pool_vector[pool_size].value = x;
1686   lab = gen_label_rtx ();
1687   pool_vector[pool_size].mode = mode;
1688   pool_vector[pool_size].label = lab;
1689   pool_size++;
1690   return lab;
1691 }
1692
1693 /* Output the literal table.  */
1694
1695 static void
1696 dump_table (scan)
1697      rtx scan;
1698 {
1699   int i;
1700   int need_align = 1;
1701
1702   /* Do two passes, first time dump out the HI sized constants.  */
1703
1704   for (i = 0; i < pool_size; i++)
1705     {
1706       pool_node *p = &pool_vector[i];
1707
1708       if (p->mode == HImode)
1709         {
1710           if (need_align)
1711             {
1712               scan = emit_insn_after (gen_align_2 (), scan);
1713               need_align = 0;
1714             }
1715           scan = emit_label_after (p->label, scan);
1716           scan = emit_insn_after (gen_consttable_2 (p->value), scan);
1717         }
1718     }
1719
1720   need_align = 1;
1721
1722   for (i = 0; i < pool_size; i++)
1723     {
1724       pool_node *p = &pool_vector[i];
1725
1726       switch (p->mode)
1727         {
1728         case HImode:
1729           break;
1730         case SImode:
1731         case SFmode:
1732           if (need_align)
1733             {
1734               need_align = 0;
1735               scan = emit_label_after (gen_label_rtx (), scan);
1736               scan = emit_insn_after (gen_align_4 (), scan);
1737             }
1738           scan = emit_label_after (p->label, scan);
1739           scan = emit_insn_after (gen_consttable_4 (p->value), scan);
1740           break;
1741         case DFmode:
1742         case DImode:
1743           if (need_align)
1744             {
1745               need_align = 0;
1746               scan = emit_label_after (gen_label_rtx (), scan);
1747               scan = emit_insn_after (gen_align_4 (), scan);
1748             }
1749           scan = emit_label_after (p->label, scan);
1750           scan = emit_insn_after (gen_consttable_8 (p->value), scan);
1751           break;
1752         default:
1753           abort ();
1754           break;
1755         }
1756     }
1757
1758   scan = emit_insn_after (gen_consttable_end (), scan);
1759   scan = emit_barrier_after (scan);
1760   pool_size = 0;
1761 }
1762
1763 /* Return non-zero if constant would be an ok source for a
1764    mov.w instead of a mov.l.  */
1765
1766 static int
1767 hi_const (src)
1768      rtx src;
1769 {
1770   return (GET_CODE (src) == CONST_INT
1771           && INTVAL (src) >= -32768
1772           && INTVAL (src) <= 32767);
1773 }
1774
1775 /* Non-zero if the insn is a move instruction which needs to be fixed.  */
1776
1777 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
1778    CONST_DOUBLE input value is CONST_OK_FOR_I.  For a SFmode move, we don't
1779    need to fix it if the input value is CONST_OK_FOR_I.  */
1780
1781 static int
1782 broken_move (insn)
1783      rtx insn;
1784 {
1785   if (GET_CODE (insn) == INSN)
1786     {
1787       rtx pat = PATTERN (insn);
1788       if (GET_CODE (pat) == PARALLEL)
1789         pat = XVECEXP (pat, 0, 0);
1790       if (GET_CODE (pat) == SET
1791           /* We can load any 8 bit value if we don't care what the high
1792              order bits end up as.  */
1793           && GET_MODE (SET_DEST (pat)) != QImode
1794           && CONSTANT_P (SET_SRC (pat))
1795           && ! (GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
1796                 && (fp_zero_operand (SET_SRC (pat))
1797                     || fp_one_operand (SET_SRC (pat)))
1798                 && GET_CODE (SET_DEST (pat)) == REG
1799                 && REGNO (SET_DEST (pat)) >= FIRST_FP_REG
1800                 && REGNO (SET_DEST (pat)) <= LAST_FP_REG)
1801           && (GET_CODE (SET_SRC (pat)) != CONST_INT
1802               || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
1803         return 1;
1804     }
1805
1806   return 0;
1807 }
1808
1809 /* Find the last barrier from insn FROM which is close enough to hold the
1810    constant pool.  If we can't find one, then create one near the end of
1811    the range.  */
1812
1813 /* ??? It would be good to put constant pool tables between a case jump and
1814    the jump table.  This fails for two reasons.  First, there is no
1815    barrier after the case jump.  This is a bug in the casesi pattern.
1816    Second, inserting the table here may break the mova instruction that
1817    loads the jump table address, by moving the jump table too far away.
1818    We fix that problem by never outputting the constant pool between a mova
1819    and its label.  */
1820
1821 static rtx
1822 find_barrier (from)
1823      rtx from;
1824 {
1825   int count_si = 0;
1826   int count_hi = 0;
1827   int found_hi = 0;
1828   int found_si = 0;
1829   rtx found_barrier = 0;
1830   rtx found_mova = 0;
1831   int si_limit;
1832   int hi_limit;
1833
1834   /* For HImode: range is 510, add 4 because pc counts from address of
1835      second instruction after this one, subtract 2 for the jump instruction
1836      that we may need to emit before the table, subtract 2 for the instruction
1837      that fills the jump delay slot (in very rare cases, reorg will take an
1838      instruction from after the constant pool or will leave the delay slot
1839      empty).  This gives 510.
1840      For SImode: range is 1020, add 4 because pc counts from address of
1841      second instruction after this one, subtract 2 in case pc is 2 byte
1842      aligned, subtract 2 for the jump instruction that we may need to emit
1843      before the table, subtract 2 for the instruction that fills the jump
1844      delay slot.  This gives 1018.  */
1845
1846   /* If not optimizing, then it is possible that the jump instruction we add
1847      won't be shortened, and thus will have a length of 14 instead of 2.
1848      We must adjust the limits downwards to account for this, giving a limit
1849      of 1008 for SImode and 500 for HImode.  */
1850
1851   if (optimize)
1852     {
1853       si_limit = 1018;
1854       hi_limit = 510;
1855     }
1856   else
1857     {
1858       si_limit = 1008;
1859       hi_limit = 500;
1860     }
1861
1862   /* If not optimizing for space, then the constant pool will be
1863      aligned to a 4 to 16 byte boundary.  We must make room for that
1864      alignment that by reducing the limits.
1865      ??? It would be better to not align the constant pool, but
1866      ASM_OUTPUT_ALIGN_CODE does not make any provision for basing the
1867      alignment on the instruction.  */
1868
1869   if (! TARGET_SMALLCODE)
1870     {
1871       if (TARGET_SH3 || TARGET_SH3E)
1872         {
1873           si_limit -= 14;
1874           hi_limit -= 14;
1875         }
1876       else
1877         {
1878           si_limit -= 2;
1879           hi_limit -= 2;
1880         }
1881     }
1882
1883   while (from && count_si < si_limit && count_hi < hi_limit)
1884     {
1885       int inc = get_attr_length (from);
1886
1887       if (GET_CODE (from) == BARRIER)
1888         found_barrier = from;
1889
1890       if (broken_move (from))
1891         {
1892           rtx pat = PATTERN (from);
1893           rtx src = SET_SRC (pat);
1894           rtx dst = SET_DEST (pat);
1895           enum machine_mode mode = GET_MODE (dst);
1896
1897           /* We must explicitly check the mode, because sometimes the
1898              front end will generate code to load unsigned constants into
1899              HImode targets without properly sign extending them.  */
1900           if (mode == HImode || (mode == SImode && hi_const (src)))
1901             {
1902               found_hi = 1;
1903               /* We put the short constants before the long constants, so
1904                  we must count the length of short constants in the range
1905                  for the long constants.  */
1906               /* ??? This isn't optimal, but is easy to do.  */
1907               if (found_si)
1908                 count_si += 2;
1909             }
1910           else
1911             found_si = 1;
1912         }
1913
1914       if (GET_CODE (from) == INSN
1915           && GET_CODE (PATTERN (from)) == SET
1916           && GET_CODE (SET_SRC (PATTERN (from))) == UNSPEC
1917           && XINT (SET_SRC (PATTERN (from)), 1) == 1)
1918         found_mova = from;
1919       else if (GET_CODE (from) == JUMP_INSN
1920                && (GET_CODE (PATTERN (from)) == ADDR_VEC
1921                    || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
1922         found_mova = 0;
1923
1924       if (found_si)
1925         count_si += inc;
1926       if (found_hi)
1927         count_hi += inc;
1928       from = NEXT_INSN (from);
1929     }
1930
1931   /* Insert the constant pool table before the mova instruction, to prevent
1932      the mova label reference from going out of range.  */
1933   if (found_mova)
1934     from = found_mova;
1935
1936   if (! found_barrier)
1937     {
1938       /* We didn't find a barrier in time to dump our stuff,
1939          so we'll make one.  */
1940       rtx label = gen_label_rtx ();
1941
1942       /* If we exceeded the range, then we must back up over the last
1943          instruction we looked at.  Otherwise, we just need to undo the
1944          NEXT_INSN at the end of the loop.  */
1945       if (count_hi > hi_limit || count_si > si_limit)
1946         from = PREV_INSN (PREV_INSN (from));
1947       else
1948         from = PREV_INSN (from);
1949
1950       /* Walk back to be just before any jump or label.
1951          Putting it before a label reduces the number of times the branch
1952          around the constant pool table will be hit.  Putting it before
1953          a jump makes it more likely that the bra delay slot will be
1954          filled.  */
1955       while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
1956              || GET_CODE (from) == CODE_LABEL)
1957         from = PREV_INSN (from);
1958
1959       from = emit_jump_insn_after (gen_jump (label), from);
1960       JUMP_LABEL (from) = label;
1961       LABEL_NUSES (label) = 1;
1962       found_barrier = emit_barrier_after (from);
1963       emit_label_after (label, found_barrier);
1964     }
1965
1966   return found_barrier;
1967 }
1968
1969 /* If the instruction INSN is implemented by a special function, and we can
1970    positively find the register that is used to call the sfunc, and this
1971    register is not used anywhere else in this instruction - except as the
1972    destination of a set, return this register; else, return 0.  */
1973 static rtx
1974 sfunc_uses_reg (insn)
1975      rtx insn;
1976 {
1977   int i;
1978   rtx pattern, part, reg_part, reg;
1979
1980   if (GET_CODE (insn) != INSN)
1981     return 0;
1982   pattern = PATTERN (insn);
1983   if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
1984     return 0;
1985
1986   for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
1987     {
1988       part = XVECEXP (pattern, 0, i);
1989       if (GET_CODE (part) == USE)
1990         reg_part = part;
1991     }
1992   if (! reg_part)
1993     return 0;
1994   reg = XEXP (reg_part, 0);
1995   for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
1996     {
1997       part = XVECEXP (pattern, 0, i);
1998       if (part == reg_part)
1999         continue;
2000       if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
2001                                   && GET_CODE (SET_DEST (part)) == REG)
2002                                  ? SET_SRC (part) : part)))
2003         return 0;
2004     }
2005   return reg;
2006 }
2007
2008 /* See if the only way in which INSN uses REG is by calling it, or by
2009    setting it while calling it.  Set *SET to a SET rtx if the register
2010    is set by INSN.  */
2011
2012 static int
2013 noncall_uses_reg (reg, insn, set)
2014      rtx reg;
2015      rtx insn;
2016      rtx *set;
2017 {
2018   rtx pattern, reg2;
2019
2020   *set = NULL_RTX;
2021
2022   reg2 = sfunc_uses_reg (insn);
2023   if (reg2 && REGNO (reg2) == REGNO (reg))
2024     {
2025       pattern = single_set (insn);
2026       if (pattern
2027           && GET_CODE (SET_DEST (pattern)) == REG
2028           && REGNO (reg) == REGNO (SET_DEST (pattern)))
2029         *set = pattern;
2030       return 0;
2031     }
2032   if (GET_CODE (insn) != CALL_INSN)
2033     {
2034       /* We don't use rtx_equal_p because we don't care if the mode is
2035          different.  */
2036       pattern = single_set (insn);
2037       if (pattern
2038           && GET_CODE (SET_DEST (pattern)) == REG
2039           && REGNO (reg) == REGNO (SET_DEST (pattern)))
2040         {
2041           rtx par, part;
2042           int i;
2043
2044           *set = pattern;
2045           par = PATTERN (insn);
2046           if (GET_CODE (par) == PARALLEL)
2047             for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
2048               {
2049                 part = XVECEXP (par, 0, i);
2050                 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
2051                   return 1;
2052               }
2053           return reg_mentioned_p (reg, SET_SRC (pattern));
2054         }
2055
2056       return 1;
2057     }
2058
2059   pattern = PATTERN (insn);
2060
2061   if (GET_CODE (pattern) == PARALLEL)
2062     {
2063       int i;
2064
2065       for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2066         if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
2067           return 1;
2068       pattern = XVECEXP (pattern, 0, 0);
2069     }
2070
2071   if (GET_CODE (pattern) == SET)
2072     {
2073       if (reg_mentioned_p (reg, SET_DEST (pattern)))
2074         {
2075           /* We don't use rtx_equal_p, because we don't care if the
2076              mode is different.  */
2077           if (GET_CODE (SET_DEST (pattern)) != REG
2078               || REGNO (reg) != REGNO (SET_DEST (pattern)))
2079             return 1;
2080
2081           *set = pattern;
2082         }
2083
2084       pattern = SET_SRC (pattern);
2085     }
2086
2087   if (GET_CODE (pattern) != CALL
2088       || GET_CODE (XEXP (pattern, 0)) != MEM
2089       || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
2090     return 1;
2091
2092   return 0;
2093 }
2094
2095 /* Exported to toplev.c.
2096
2097    Do a final pass over the function, just before delayed branch
2098    scheduling.  */
2099
2100 void
2101 machine_dependent_reorg (first)
2102      rtx first;
2103 {
2104   rtx insn;
2105
2106   /* If relaxing, generate pseudo-ops to associate function calls with
2107      the symbols they call.  It does no harm to not generate these
2108      pseudo-ops.  However, when we can generate them, it enables to
2109      linker to potentially relax the jsr to a bsr, and eliminate the
2110      register load and, possibly, the constant pool entry.  */
2111
2112   if (TARGET_RELAX)
2113     {
2114       /* Remove all REG_LABEL notes.  We want to use them for our own
2115          purposes.  This works because none of the remaining passes
2116          need to look at them.
2117
2118          ??? But it may break in the future.  We should use a machine
2119          dependent REG_NOTE, or some other approach entirely.  */
2120       for (insn = first; insn; insn = NEXT_INSN (insn))
2121         {
2122           if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2123             {
2124               rtx note;
2125
2126               while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
2127                 remove_note (insn, note);
2128             }
2129         }
2130
2131       for (insn = first; insn; insn = NEXT_INSN (insn))
2132         {
2133           rtx pattern, reg, link, set, scan, dies, label;
2134           int rescan = 0, foundinsn = 0;
2135
2136           if (GET_CODE (insn) == CALL_INSN)
2137             {
2138               pattern = PATTERN (insn);
2139
2140               if (GET_CODE (pattern) == PARALLEL)
2141                 pattern = XVECEXP (pattern, 0, 0);
2142               if (GET_CODE (pattern) == SET)
2143                 pattern = SET_SRC (pattern);
2144
2145               if (GET_CODE (pattern) != CALL
2146                   || GET_CODE (XEXP (pattern, 0)) != MEM)
2147                 continue;
2148
2149               reg = XEXP (XEXP (pattern, 0), 0);
2150             }
2151           else
2152             {
2153               reg = sfunc_uses_reg (insn);
2154               if (! reg)
2155                 continue;
2156             }
2157
2158           if (GET_CODE (reg) != REG)
2159             continue;
2160
2161           /* This is a function call via REG.  If the only uses of REG
2162              between the time that it is set and the time that it dies
2163              are in function calls, then we can associate all the
2164              function calls with the setting of REG.  */
2165
2166           for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
2167             {
2168               if (REG_NOTE_KIND (link) != 0)
2169                 continue;
2170               set = single_set (XEXP (link, 0));
2171               if (set && rtx_equal_p (reg, SET_DEST (set)))
2172                 {
2173                   link = XEXP (link, 0);
2174                   break;
2175                 }
2176             }
2177
2178           if (! link)
2179             {
2180               /* ??? Sometimes global register allocation will have
2181                  deleted the insn pointed to by LOG_LINKS.  Try
2182                  scanning backward to find where the register is set.  */
2183               for (scan = PREV_INSN (insn);
2184                    scan && GET_CODE (scan) != CODE_LABEL;
2185                    scan = PREV_INSN (scan))
2186                 {
2187                   if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
2188                     continue;
2189
2190                   if (! reg_mentioned_p (reg, scan))
2191                     continue;
2192
2193                   if (noncall_uses_reg (reg, scan, &set))
2194                     break;
2195
2196                   if (set)
2197                     {
2198                       link = scan;
2199                       break;
2200                     }
2201                 }
2202             }
2203
2204           if (! link)
2205             continue;
2206
2207           /* The register is set at LINK.  */
2208
2209           /* We can only optimize the function call if the register is
2210              being set to a symbol.  In theory, we could sometimes
2211              optimize calls to a constant location, but the assembler
2212              and linker do not support that at present.  */
2213           if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
2214               && GET_CODE (SET_SRC (set)) != LABEL_REF)
2215             continue;
2216
2217           /* Scan forward from LINK to the place where REG dies, and
2218              make sure that the only insns which use REG are
2219              themselves function calls.  */
2220
2221           /* ??? This doesn't work for call targets that were allocated
2222              by reload, since there may not be a REG_DEAD note for the
2223              register.  */
2224
2225           dies = NULL_RTX;
2226           for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
2227             {
2228               rtx scanset;
2229
2230               /* Don't try to trace forward past a CODE_LABEL if we haven't
2231                  seen INSN yet.  Ordinarily, we will only find the setting insn
2232                  in LOG_LINKS if it is in the same basic block.  However,
2233                  cross-jumping can insert code labels in between the load and
2234                  the call, and can result in situations where a single call
2235                  insn may have two targets depending on where we came from.  */
2236
2237               if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
2238                 break;
2239
2240               if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
2241                 continue;
2242
2243               /* Don't try to trace forward past a JUMP.  To optimize
2244                  safely, we would have to check that all the
2245                  instructions at the jump destination did not use REG.  */
2246
2247               if (GET_CODE (scan) == JUMP_INSN)
2248                 break;
2249
2250               if (! reg_mentioned_p (reg, scan))
2251                 continue;
2252
2253               if (noncall_uses_reg (reg, scan, &scanset))
2254                 break;
2255
2256               if (scan == insn)
2257                 foundinsn = 1;
2258
2259               if (scan != insn
2260                   && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
2261                 {
2262                   /* There is a function call to this register other
2263                      than the one we are checking.  If we optimize
2264                      this call, we need to rescan again below.  */
2265                   rescan = 1;
2266                 }
2267
2268               /* ??? We shouldn't have to worry about SCANSET here.
2269                  We should just be able to check for a REG_DEAD note
2270                  on a function call.  However, the REG_DEAD notes are
2271                  apparently not dependable around libcalls; c-torture
2272                  execute/920501-2 is a test case.  If SCANSET is set,
2273                  then this insn sets the register, so it must have
2274                  died earlier.  Unfortunately, this will only handle
2275                  the cases in which the register is, in fact, set in a
2276                  later insn.  */
2277
2278               /* ??? We shouldn't have to use FOUNDINSN here.
2279                  However, the LOG_LINKS fields are apparently not
2280                  entirely reliable around libcalls;
2281                  newlib/libm/math/e_pow.c is a test case.  Sometimes
2282                  an insn will appear in LOG_LINKS even though it is
2283                  not the most recent insn which sets the register. */
2284
2285               if (foundinsn
2286                   && (scanset
2287                       || find_reg_note (scan, REG_DEAD, reg)))
2288                 {
2289                   dies = scan;
2290                   break;
2291                 }
2292             }
2293
2294           if (! dies)
2295             {
2296               /* Either there was a branch, or some insn used REG
2297                  other than as a function call address.  */
2298               continue;
2299             }
2300
2301           /* Create a code label, and put it in a REG_LABEL note on
2302              the insn which sets the register, and on each call insn
2303              which uses the register.  In final_prescan_insn we look
2304              for the REG_LABEL notes, and output the appropriate label
2305              or pseudo-op.  */
2306
2307           label = gen_label_rtx ();
2308           REG_NOTES (link) = gen_rtx (EXPR_LIST, REG_LABEL, label,
2309                                       REG_NOTES (link));
2310           REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, label,
2311                                       REG_NOTES (insn));
2312           if (rescan)
2313             {
2314               scan = link;
2315               do
2316                 {
2317                   rtx reg2;
2318
2319                   scan = NEXT_INSN (scan);
2320                   if (scan != insn
2321                       && ((GET_CODE (scan) == CALL_INSN
2322                            && reg_mentioned_p (reg, scan))
2323                           || ((reg2 = sfunc_uses_reg (scan))
2324                               && REGNO (reg2) == REGNO (reg))))
2325                     REG_NOTES (scan) = gen_rtx (EXPR_LIST, REG_LABEL,
2326                                                 label, REG_NOTES (scan));
2327                 }
2328               while (scan != dies);
2329             }
2330         }
2331     }
2332
2333   /* Scan the function looking for move instructions which have to be
2334      changed to pc-relative loads and insert the literal tables.  */
2335
2336   for (insn = first; insn; insn = NEXT_INSN (insn))
2337     {
2338       if (broken_move (insn))
2339         {
2340           rtx scan;
2341           /* Scan ahead looking for a barrier to stick the constant table
2342              behind.  */
2343           rtx barrier = find_barrier (insn);
2344
2345           /* Now find all the moves between the points and modify them.  */
2346           for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
2347             {
2348               if (broken_move (scan))
2349                 {
2350                   rtx *patp = &PATTERN (scan), pat = *patp;
2351                   rtx src, dst;
2352                   rtx lab;
2353                   rtx newinsn;
2354                   rtx newsrc;
2355                   enum machine_mode mode;
2356
2357                   if (GET_CODE (pat) == PARALLEL)
2358                     patp = &XVECEXP (pat, 0, 0), pat = *patp;
2359                   src = SET_SRC (pat);
2360                   dst = SET_DEST (pat);
2361                   mode = GET_MODE (dst);
2362
2363                   if (mode == SImode && hi_const (src))
2364                     {
2365                       int offset = 0;
2366
2367                       mode = HImode;
2368                       while (GET_CODE (dst) == SUBREG)
2369                         {
2370                           offset += SUBREG_WORD (dst);
2371                           dst = SUBREG_REG (dst);
2372                         }
2373                       dst = gen_rtx (REG, HImode, REGNO (dst) + offset);
2374                     }
2375
2376                   lab = add_constant (src, mode);
2377                   newsrc = gen_rtx (MEM, mode,
2378                                     gen_rtx (LABEL_REF, VOIDmode, lab));
2379                   RTX_UNCHANGING_P (newsrc) = 1;
2380                   *patp = gen_rtx (SET, VOIDmode, dst, newsrc);
2381                   INSN_CODE (scan) = -1;
2382                 }
2383             }
2384           dump_table (barrier);
2385         }
2386     }
2387 }
2388
2389 /* Dump out instruction addresses, which is useful for debugging the
2390    constant pool table stuff.
2391
2392    If relaxing, output the label and pseudo-ops used to link together
2393    calls and the instruction which set the registers.  */
2394
2395 /* ??? This is unnecessary, and probably should be deleted.  This makes
2396    the insn_addresses declaration above unnecessary.  */
2397
2398 /* ??? The addresses printed by this routine for insns are nonsense for
2399    insns which are inside of a sequence where none of the inner insns have
2400    variable length.  This is because the second pass of shorten_branches
2401    does not bother to update them.  */
2402
2403 void
2404 final_prescan_insn (insn, opvec, noperands)
2405      rtx insn;
2406      rtx *opvec;
2407      int noperands;
2408 {
2409   if (TARGET_DUMPISIZE)
2410     fprintf (asm_out_file, "\n! at %04x\n", insn_addresses[INSN_UID (insn)]);
2411
2412   if (TARGET_RELAX)
2413     {
2414       rtx note;
2415
2416       note = find_reg_note (insn, REG_LABEL, NULL_RTX);
2417       if (note)
2418         {
2419           rtx pattern;
2420
2421           pattern = PATTERN (insn);
2422           if (GET_CODE (pattern) == PARALLEL)
2423             pattern = XVECEXP (pattern, 0, 0);
2424           if (GET_CODE (pattern) == CALL
2425               || (GET_CODE (pattern) == SET
2426                   && (GET_CODE (SET_SRC (pattern)) == CALL
2427                       || get_attr_type (insn) == TYPE_SFUNC)))
2428             fprintf (asm_out_file, "\t.uses L%d\n",
2429                      CODE_LABEL_NUMBER (XEXP (note, 0)));
2430           else if (GET_CODE (pattern) == SET)
2431             ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
2432                                        CODE_LABEL_NUMBER (XEXP (note, 0)));
2433           else
2434             abort ();
2435         }
2436     }
2437 }
2438
2439 /* Dump out any constants accumulated in the final pass.  These will
2440    will only be labels.  */
2441
2442 char *
2443 output_jump_label_table ()
2444 {
2445   int i;
2446
2447   if (pool_size)
2448     {
2449       fprintf (asm_out_file, "\t.align 2\n");
2450       for (i = 0; i < pool_size; i++)
2451         {
2452           pool_node *p = &pool_vector[i];
2453
2454           ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
2455                                      CODE_LABEL_NUMBER (p->label));
2456           output_asm_insn (".long       %O0", &p->value);
2457         }
2458       pool_size = 0;
2459     }
2460
2461   return "";
2462 }
2463 \f
2464 /* A full frame looks like:
2465
2466    arg-5
2467    arg-4
2468    [ if current_function_anonymous_args
2469    arg-3
2470    arg-2
2471    arg-1
2472    arg-0 ]
2473    saved-fp
2474    saved-r10
2475    saved-r11
2476    saved-r12
2477    saved-pr
2478    local-n
2479    ..
2480    local-1
2481    local-0        <- fp points here.  */
2482
2483 /* Number of bytes pushed for anonymous args, used to pass information
2484    between expand_prologue and expand_epilogue.  */
2485
2486 static int extra_push;
2487
2488 /* Adjust the stack by SIZE bytes.  REG holds the rtl of the register
2489   to be adjusted, and TEMP, if nonnegative, holds the register number
2490   of a general register that we may clobber.  */
2491
2492 static void
2493 output_stack_adjust (size, reg, temp)
2494      int size;
2495      rtx reg;
2496      int temp;
2497 {
2498   if (size)
2499     {
2500       if (CONST_OK_FOR_I (size))
2501         emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
2502       /* Try to do it with two partial adjustments; however, we must make
2503          sure that the stack is properly aligned at all times, in case
2504          an interrupt occurs between the two partial adjustments. */
2505       else if (CONST_OK_FOR_I (size / 2 & -4)
2506                && CONST_OK_FOR_I (size - (size / 2 & -4)))
2507         {
2508           emit_insn (gen_addsi3 (reg, reg, GEN_INT (size / 2 & -4)));
2509           emit_insn (gen_addsi3 (reg, reg, GEN_INT (size - (size / 2 & -4))));
2510         }
2511       else
2512         {
2513           rtx const_reg;
2514
2515           /* If TEMP is invalid, we could temporarily save a general
2516              register to MACL.  However, there is currently no need
2517              to handle this case, so just abort when we see it.  */
2518           if (temp < 0)
2519             abort ();
2520           const_reg = gen_rtx (REG, SImode, temp);
2521
2522           /* If SIZE is negative, subtract the positive value.
2523              This sometimes allows a constant pool entry to be shared
2524              between prologue and epilogue code.  */
2525           if (size < 0)
2526             {
2527               emit_insn (gen_movsi (const_reg, GEN_INT (-size)));
2528               emit_insn (gen_subsi3 (reg, reg, const_reg));
2529             }
2530           else
2531             {
2532               emit_insn (gen_movsi (const_reg, GEN_INT (size)));
2533               emit_insn (gen_addsi3 (reg, reg, const_reg));
2534             }
2535         }
2536     }
2537 }
2538
2539 /* Output RTL to push register RN onto the stack.  */
2540
2541 static void
2542 push (rn)
2543      int rn;
2544 {
2545   rtx x;
2546   if ((rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
2547       || rn == FPUL_REG)
2548     x = emit_insn (gen_push_e (gen_rtx (REG, SFmode, rn)));
2549   else
2550     x = emit_insn (gen_push (gen_rtx (REG, SImode, rn)));
2551
2552   REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
2553                            gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
2554 }
2555
2556 /* Output RTL to pop register RN from the stack.  */
2557
2558 static void
2559 pop (rn)
2560      int rn;
2561 {
2562   rtx x;
2563   if ((rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
2564       || rn == FPUL_REG)
2565     x = emit_insn (gen_pop_e (gen_rtx (REG, SFmode, rn)));
2566   else
2567     x = emit_insn (gen_pop (gen_rtx (REG, SImode, rn)));
2568
2569   REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
2570                            gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
2571 }
2572
2573 /* Generate code to push the regs specified in the mask, and return
2574    the number of bytes the insns take.  */
2575
2576 static void
2577 push_regs (mask, mask2)
2578      int mask, mask2;
2579 {
2580   int i;
2581
2582   for (i = 0; i < 32; i++)
2583     if (mask & (1 << i))
2584       push (i);
2585   for (i = 32; i < FIRST_PSEUDO_REGISTER; i++)
2586     if (mask2 & (1 << (i - 32)))
2587       push (i);
2588 }
2589
2590 /* Work out the registers which need to be saved, both as a mask and a
2591    count.
2592
2593    If doing a pragma interrupt function, then push all regs used by the
2594    function, and if we call another function (we can tell by looking at PR),
2595    make sure that all the regs it clobbers are safe too.  */
2596
2597 static int
2598 calc_live_regs (count_ptr, live_regs_mask2)
2599      int *count_ptr;
2600      int *live_regs_mask2;
2601 {
2602   int reg;
2603   int live_regs_mask = 0;
2604   int count = 0;
2605
2606   *live_regs_mask2 = 0;
2607   for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
2608     {
2609       if (pragma_interrupt && ! pragma_trapa)
2610         {
2611           /* Need to save all the regs ever live.  */
2612           if ((regs_ever_live[reg]
2613                || (call_used_regs[reg]
2614                    && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
2615                    && regs_ever_live[PR_REG]))
2616               && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
2617               && reg != RETURN_ADDRESS_POINTER_REGNUM
2618               && reg != T_REG && reg != GBR_REG)
2619             {
2620               if (reg >= 32)
2621                 *live_regs_mask2 |= 1 << (reg - 32);
2622               else
2623                 live_regs_mask |= 1 << reg;
2624               count++;
2625             }
2626         }
2627       else
2628         {
2629           /* Only push those regs which are used and need to be saved.  */
2630           if (regs_ever_live[reg] && ! call_used_regs[reg])
2631             {
2632               if (reg >= 32)
2633                 *live_regs_mask2 |= 1 << (reg - 32);
2634               else
2635                 live_regs_mask |= (1 << reg);
2636               count++;
2637             }
2638         }
2639     }
2640
2641   *count_ptr = count;
2642   return live_regs_mask;
2643 }
2644
2645 /* Code to generate prologue and epilogue sequences */
2646
2647 void
2648 sh_expand_prologue ()
2649 {
2650   int live_regs_mask;
2651   int d, i;
2652   int live_regs_mask2;
2653   live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
2654
2655   /* We have pretend args if we had an object sent partially in registers
2656      and partially on the stack, e.g. a large structure.  */
2657   output_stack_adjust (-current_function_pretend_args_size,
2658                        stack_pointer_rtx, 3);
2659
2660   extra_push = 0;
2661
2662   /* This is set by SETUP_VARARGS to indicate that this is a varargs
2663      routine.  Clear it here so that the next function isn't affected. */
2664   if (current_function_anonymous_args)
2665     {
2666       current_function_anonymous_args = 0;
2667
2668       /* This is not used by the SH3E calling convention  */
2669       if (!TARGET_SH3E)
2670         {
2671           /* Push arg regs as if they'd been provided by caller in stack.  */
2672           for (i = 0; i < NPARM_REGS(SImode); i++)
2673             {
2674               int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
2675               if (i > (NPARM_REGS(SImode)
2676                        - current_function_args_info.arg_count[(int) SH_ARG_INT]
2677                        - current_function_varargs))
2678                 break;
2679               push (rn);
2680               extra_push += 4;
2681             }
2682         }
2683     }
2684
2685   /* If we're supposed to switch stacks at function entry, do so now.  */
2686   if (sp_switch)
2687     emit_insn (gen_sp_switch_1 ());
2688
2689   push_regs (live_regs_mask, live_regs_mask2);
2690
2691   output_stack_adjust (-get_frame_size (), stack_pointer_rtx, 3);
2692
2693   if (frame_pointer_needed)
2694     emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2695 }
2696
2697 void
2698 sh_expand_epilogue ()
2699 {
2700   int live_regs_mask;
2701   int d, i;
2702
2703   int live_regs_mask2;
2704   live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
2705
2706   if (frame_pointer_needed)
2707     {
2708       /* We deliberately make the add dependent on the frame_pointer,
2709          to ensure that instruction scheduling won't move the stack pointer
2710          adjust before instructions reading from the frame.  This can fail
2711          if there is an interrupt which then writes to the stack.  */
2712       output_stack_adjust (get_frame_size (), frame_pointer_rtx, 7);
2713       emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
2714     }
2715   else
2716     output_stack_adjust (get_frame_size (), stack_pointer_rtx, 7);
2717
2718   /* Pop all the registers.  */
2719
2720   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2721     {
2722       int j = (FIRST_PSEUDO_REGISTER - 1) - i;
2723       if (j < 32 && (live_regs_mask & (1 << j)))
2724         pop (j);
2725       else if (j >= 32 && (live_regs_mask2 & (1 << (j - 32))))
2726         pop (j);
2727     }
2728
2729   output_stack_adjust (extra_push + current_function_pretend_args_size,
2730                        stack_pointer_rtx, 7);
2731
2732   /* Switch back to the normal stack if necessary.  */
2733   if (sp_switch)
2734     emit_insn (gen_sp_switch_2 ());
2735 }
2736
2737 /* Clear variables at function end.  */
2738
2739 void
2740 function_epilogue (stream, size)
2741      FILE *stream;
2742      int size;
2743 {
2744   trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
2745   sp_switch = NULL_RTX;
2746 }
2747
2748 rtx
2749 sh_builtin_saveregs (arglist)
2750      tree arglist;
2751 {
2752   tree fntype = TREE_TYPE (current_function_decl);
2753   /* First unnamed integer register.  */
2754   int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
2755   /* Number of integer registers we need to save.  */
2756   int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
2757   /* First unnamed SFmode float reg */
2758   int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
2759   /* Number of SFmode float regs to save.  */
2760   int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
2761   int ptrsize = GET_MODE_SIZE (Pmode);
2762   rtx valist, regbuf, fpregs;
2763   int bufsize, regno;
2764
2765   /* Allocate block of memory for the regs. */
2766   /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
2767      Or can assign_stack_local accept a 0 SIZE argument?  */
2768   bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
2769
2770   regbuf = assign_stack_local (BLKmode, bufsize, 0);
2771   MEM_IN_STRUCT_P (regbuf) = 1;
2772
2773   /* Save int args.
2774      This is optimized to only save the regs that are necessary.  Explicitly
2775      named args need not be saved.  */
2776   if (n_intregs > 0)
2777     move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
2778                          gen_rtx (MEM, BLKmode,
2779                                 plus_constant (XEXP (regbuf, 0),
2780                                         n_floatregs * UNITS_PER_WORD)),
2781                          n_intregs, n_intregs * UNITS_PER_WORD);
2782
2783   /* Save float args.
2784      This is optimized to only save the regs that are necessary.  Explicitly
2785      named args need not be saved.
2786      We explicitly build a pointer to the buffer because it halves the insn
2787      count when not optimizing (otherwise the pointer is built for each reg
2788      saved).  */
2789
2790   fpregs = gen_reg_rtx (Pmode);
2791   emit_move_insn (fpregs, XEXP (regbuf, 0));
2792   for (regno = first_floatreg; regno < NPARM_REGS (SFmode); regno ++)
2793     emit_move_insn (gen_rtx (MEM, SFmode,
2794                              plus_constant (fpregs,
2795                                             GET_MODE_SIZE (SFmode)
2796                                             * (regno - first_floatreg))),
2797                     gen_rtx (REG, SFmode,
2798                              BASE_ARG_REG (SFmode) + regno));
2799
2800   /* Return the address of the regbuf.  */
2801   return XEXP (regbuf, 0);
2802 }
2803
2804 /* Define the offset between two registers, one to be eliminated, and
2805    the other its replacement, at the start of a routine.  */
2806
2807 int
2808 initial_elimination_offset (from, to)
2809      int from;
2810      int to;
2811 {
2812   int regs_saved;
2813   int total_saved_regs_space;
2814   int total_auto_space = get_frame_size ();
2815
2816   int live_regs_mask, live_regs_mask2;
2817   live_regs_mask = calc_live_regs (&regs_saved, &live_regs_mask2);
2818
2819   total_saved_regs_space = (regs_saved) * 4;
2820
2821   if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
2822     return total_saved_regs_space + total_auto_space;
2823
2824   if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2825     return total_saved_regs_space + total_auto_space;
2826
2827   /* Initial gap between fp and sp is 0.  */
2828   if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2829     return 0;
2830
2831   if (from == RETURN_ADDRESS_POINTER_REGNUM
2832       && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
2833     {
2834       int i, n = 0;
2835       for (i = PR_REG+1; i < 32; i++)
2836         if (live_regs_mask & (1 << i))
2837           n += 4;
2838       for (i = 32; i < FIRST_PSEUDO_REGISTER; i++)
2839         if (live_regs_mask2 & (1 << (i - 32)))
2840           n += 4;
2841       return n + total_auto_space;
2842     }
2843
2844   abort ();
2845 }
2846 \f
2847 /* Handle machine specific pragmas to be semi-compatible with Hitachi
2848    compiler.  */
2849
2850 int
2851 handle_pragma (file, t)
2852      FILE *file;
2853      tree t;
2854 {
2855   int retval = 0;
2856   register char *pname;
2857
2858   if (TREE_CODE (t) != IDENTIFIER_NODE)
2859     return 0;
2860
2861   pname = IDENTIFIER_POINTER (t);
2862   if (strcmp (pname, "interrupt") == 0)
2863     pragma_interrupt = retval = 1;
2864   else if (strcmp (pname, "trapa") == 0)
2865     pragma_interrupt = pragma_trapa = retval = 1;
2866   else if (strcmp (pname, "nosave_low_regs") == 0)
2867     pragma_nosave_low_regs = retval = 1;
2868
2869   return retval;
2870 }
2871 /* Return nonzero if ATTR is a valid attribute for DECL.
2872    ATTRIBUTES are any existing attributes and ARGS are the arguments
2873    supplied with ATTR.
2874
2875    Supported attributes:
2876
2877    interrupt_handler -- specifies this function is an interrupt handler.
2878
2879    sp_switch -- specifies an alternate stack for an interrupt handler
2880    to run on.
2881
2882    trap_exit -- use a trapa to exit an interrupt function intead of
2883    an rte instruction.  */
2884
2885 int
2886 sh_valid_machine_decl_attribute (decl, attributes, attr, args)
2887      tree decl;
2888      tree attributes;
2889      tree attr;
2890      tree args;
2891 {
2892   int retval = 0;
2893
2894   if (TREE_CODE (decl) != FUNCTION_DECL)
2895     return 0;
2896
2897   if (is_attribute_p ("interrupt_handler", attr))
2898     {
2899       pragma_interrupt = 1;
2900       return 1;
2901     }
2902
2903   if (is_attribute_p ("sp_switch", attr))
2904     {
2905       /* The sp_switch attribute only has meaning for interrupt functions.  */
2906       if (!pragma_interrupt)
2907         return 0;
2908
2909       /* sp_switch must have an argument.  */
2910       if (!args || TREE_CODE (args) != TREE_LIST)
2911         return 0;
2912
2913       /* The argument must be a constant string.  */
2914       if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
2915         return 0;
2916
2917       sp_switch = gen_rtx (SYMBOL_REF, VOIDmode,
2918                            TREE_STRING_POINTER (TREE_VALUE (args)));
2919       return 1;
2920     }
2921
2922   if (is_attribute_p ("trap_exit", attr))
2923     {
2924       /* The trap_exit attribute only has meaning for interrupt functions.  */
2925       if (!pragma_interrupt)
2926         return 0;
2927
2928       /* trap_exit must have an argument.  */
2929       if (!args || TREE_CODE (args) != TREE_LIST)
2930         return 0;
2931
2932       /* The argument must be a constant integer.  */
2933       if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
2934         return 0;
2935
2936       trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
2937       return 1;
2938     }
2939 }
2940
2941 \f
2942 /* Predicates used by the templates.  */
2943
2944 /* Returns 1 if OP is MACL, MACH or PR.  The input must be a REG rtx.
2945    Used only in general_movsrc_operand.  */
2946
2947 int
2948 system_reg_operand (op, mode)
2949      rtx op;
2950      enum machine_mode mode;
2951 {
2952   switch (REGNO (op))
2953     {
2954     case PR_REG:
2955     case MACL_REG:
2956     case MACH_REG:
2957       return 1;
2958     }
2959   return 0;
2960 }
2961
2962 /* Returns 1 if OP can be source of a simple move operation.
2963    Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
2964    invalid as are subregs of system registers.  */
2965
2966 int
2967 general_movsrc_operand (op, mode)
2968      rtx op;
2969      enum machine_mode mode;
2970 {
2971   if (GET_CODE (op) == MEM)
2972     {
2973       rtx inside = XEXP (op, 0);
2974       if (GET_CODE (inside) == CONST)
2975         inside = XEXP (inside, 0);
2976
2977       if (GET_CODE (inside) == LABEL_REF)
2978         return 1;
2979
2980       if (GET_CODE (inside) == PLUS
2981           && GET_CODE (XEXP (inside, 0)) == LABEL_REF
2982           && GET_CODE (XEXP (inside, 1)) == CONST_INT)
2983         return 1;
2984
2985       /* Only post inc allowed.  */
2986       if (GET_CODE (inside) == PRE_DEC)
2987         return 0;
2988     }
2989
2990   if ((mode == QImode || mode == HImode)
2991       && (GET_CODE (op) == SUBREG
2992           && GET_CODE (XEXP (op, 0)) == REG
2993           && system_reg_operand (XEXP (op, 0), mode)))
2994     return 0;
2995
2996   return general_operand (op, mode);
2997 }
2998
2999 /* Returns 1 if OP can be a destination of a move.
3000    Same as general_operand, but no preinc allowed.  */
3001
3002 int
3003 general_movdst_operand (op, mode)
3004      rtx op;
3005      enum machine_mode mode;
3006 {
3007   /* Only pre dec allowed.  */
3008   if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
3009     return 0;
3010
3011   return general_operand (op, mode);
3012 }
3013
3014 /* Returns 1 if OP is a normal arithmetic register.  */
3015
3016 int
3017 arith_reg_operand (op, mode)
3018      rtx op;
3019      enum machine_mode mode;
3020 {
3021   if (register_operand (op, mode))
3022     {
3023       int regno;
3024
3025       if (GET_CODE (op) == REG)
3026         regno = REGNO (op);
3027       else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
3028         regno = REGNO (SUBREG_REG (op));
3029       else
3030         return 1;
3031
3032       return (regno != T_REG && regno != PR_REG && regno != FPUL_REG
3033               && regno != MACH_REG && regno != MACL_REG);
3034     }
3035   return 0;
3036 }
3037
3038 /* Returns 1 if OP is a valid source operand for an arithmetic insn.  */
3039
3040 int
3041 arith_operand (op, mode)
3042      rtx op;
3043      enum machine_mode mode;
3044 {
3045   if (arith_reg_operand (op, mode))
3046     return 1;
3047
3048   if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
3049     return 1;
3050
3051   return 0;
3052 }
3053
3054 /* Returns 1 if OP is a valid source operand for a compare insn.  */
3055
3056 int
3057 arith_reg_or_0_operand (op, mode)
3058      rtx op;
3059      enum machine_mode mode;
3060 {
3061   if (arith_reg_operand (op, mode))
3062     return 1;
3063
3064   if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
3065     return 1;
3066
3067   return 0;
3068 }
3069
3070 /* Returns 1 if OP is a valid source operand for a logical operation.  */
3071
3072 int
3073 logical_operand (op, mode)
3074      rtx op;
3075      enum machine_mode mode;
3076 {
3077   if (arith_reg_operand (op, mode))
3078     return 1;
3079
3080   if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
3081     return 1;
3082
3083   return 0;
3084 }
3085
3086 /* Nonzero if OP is a floating point value with value 0.0.  */
3087
3088 int
3089 fp_zero_operand (op)
3090      rtx op;
3091 {
3092   REAL_VALUE_TYPE r;
3093
3094   if (GET_MODE (op) != SFmode)
3095     return 0;
3096
3097   REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3098   return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
3099 }
3100
3101 /* Nonzero if OP is a floating point value with value 1.0.  */
3102
3103 int
3104 fp_one_operand (op)
3105      rtx op;
3106 {
3107   REAL_VALUE_TYPE r;
3108
3109   if (GET_MODE (op) != SFmode)
3110     return 0;
3111
3112   REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3113   return REAL_VALUES_EQUAL (r, dconst1);
3114 }
3115 \f
3116 /* Return non-zero if REG is not used after INSN.
3117    We assume REG is a reload reg, and therefore does
3118    not live past labels.  It may live past calls or jumps though.  */
3119 int
3120 reg_unused_after (reg, insn)
3121      rtx reg;
3122      rtx insn;
3123 {
3124   enum rtx_code code;
3125   rtx set;
3126
3127   /* If the reg is set by this instruction, then it is safe for our
3128      case.  Disregard the case where this is a store to memory, since
3129      we are checking a register used in the store address.  */
3130   set = single_set (insn);
3131   if (set && GET_CODE (SET_DEST (set)) != MEM
3132       && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3133     return 1;
3134
3135   while (insn = NEXT_INSN (insn))
3136     {
3137       code = GET_CODE (insn);
3138
3139 #if 0
3140       /* If this is a label that existed before reload, then the register
3141          if dead here.  However, if this is a label added by reorg, then
3142          the register may still be live here.  We can't tell the difference,
3143          so we just ignore labels completely.  */
3144       if (code == CODE_LABEL)
3145         return 1;
3146       /* else */
3147 #endif
3148
3149       if (code == JUMP_INSN)
3150         return 0;
3151
3152       /* If this is a sequence, we must handle them all at once.
3153          We could have for instance a call that sets the target register,
3154          and a insn in a delay slot that uses the register.  In this case,
3155          we must return 0.  */
3156       else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3157         {
3158           int i;
3159           int retval = 0;
3160
3161           for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
3162             {
3163               rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
3164               rtx set = single_set (this_insn);
3165
3166               if (GET_CODE (this_insn) == CALL_INSN)
3167                 code = CALL_INSN;
3168               else if (GET_CODE (this_insn) == JUMP_INSN)
3169                 {
3170                   if (INSN_ANNULLED_BRANCH_P (this_insn))
3171                     return 0;
3172                   code = JUMP_INSN;
3173                 }
3174
3175               if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
3176                 return 0;
3177               if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3178                 {
3179                   if (GET_CODE (SET_DEST (set)) != MEM)
3180                     retval = 1;
3181                   else
3182                     return 0;
3183                 }
3184               if (set == 0
3185                   && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
3186                 return 0;
3187             }
3188           if (retval == 1)
3189             return 1;
3190           else if (code == JUMP_INSN)
3191             return 0;
3192         }
3193       else if (GET_RTX_CLASS (code) == 'i')
3194         {
3195           rtx set = single_set (insn);
3196
3197           if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
3198             return 0;
3199           if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3200             return GET_CODE (SET_DEST (set)) != MEM;
3201           if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3202             return 0;
3203         }
3204
3205       if (code == CALL_INSN && call_used_regs[REGNO (reg)])
3206         return 1;
3207     }
3208   return 1;
3209 }