1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx
, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
81 static arm_cc
get_arm_condition_code (rtx
);
82 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
83 static rtx
is_jump_table (rtx
);
84 static const char *output_multi_immediate (rtx
*, const char *, const char *,
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_size_rtx_costs (rtx
, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
133 static int arm_address_cost (rtx
);
134 static bool arm_memory_load_p (rtx
);
135 static bool arm_cirrus_insn_p (rtx
);
136 static void cirrus_reorg (rtx
);
137 static void arm_init_builtins (void);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
141 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
142 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
143 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
144 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 static rtx
emit_set_insn (rtx
, rtx
);
146 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
149 #ifdef OBJECT_FORMAT_ELF
150 static void arm_elf_asm_constructor (rtx
, int);
153 static void arm_encode_section_info (tree
, rtx
, int);
156 static void arm_file_end (void);
157 static void arm_file_start (void);
160 static void aof_globalize_label (FILE *, const char *);
161 static void aof_dump_imports (FILE *);
162 static void aof_dump_pic_table (FILE *);
163 static void aof_file_start (void);
164 static void aof_file_end (void);
165 static void aof_asm_init_sections (void);
167 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
169 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
170 enum machine_mode
, tree
, bool);
171 static bool arm_promote_prototypes (tree
);
172 static bool arm_default_short_enums (void);
173 static bool arm_align_anon_bitfield (void);
174 static bool arm_return_in_msb (tree
);
175 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
176 #ifdef TARGET_UNWIND_INFO
177 static void arm_unwind_emit (FILE *, rtx
);
178 static bool arm_output_ttype (rtx
);
181 static tree
arm_cxx_guard_type (void);
182 static bool arm_cxx_guard_mask_bit (void);
183 static tree
arm_get_cookie_size (tree
);
184 static bool arm_cookie_has_size (void);
185 static bool arm_cxx_cdtor_returns_this (void);
186 static bool arm_cxx_key_method_may_be_inline (void);
187 static void arm_cxx_determine_class_data_visibility (tree
);
188 static bool arm_cxx_class_data_always_comdat (void);
189 static bool arm_cxx_use_aeabi_atexit (void);
190 static void arm_init_libfuncs (void);
191 static bool arm_handle_option (size_t, const char *, int);
192 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
193 static bool arm_cannot_copy_insn_p (rtx
);
194 static bool arm_tls_symbol_p (rtx x
);
197 /* Initialize the GCC target structure. */
198 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
199 #undef TARGET_MERGE_DECL_ATTRIBUTES
200 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
203 #undef TARGET_ATTRIBUTE_TABLE
204 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
206 #undef TARGET_ASM_FILE_START
207 #define TARGET_ASM_FILE_START arm_file_start
209 #undef TARGET_ASM_FILE_END
210 #define TARGET_ASM_FILE_END arm_file_end
213 #undef TARGET_ASM_BYTE_OP
214 #define TARGET_ASM_BYTE_OP "\tDCB\t"
215 #undef TARGET_ASM_ALIGNED_HI_OP
216 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
217 #undef TARGET_ASM_ALIGNED_SI_OP
218 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
219 #undef TARGET_ASM_GLOBALIZE_LABEL
220 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
221 #undef TARGET_ASM_FILE_START
222 #define TARGET_ASM_FILE_START aof_file_start
223 #undef TARGET_ASM_FILE_END
224 #define TARGET_ASM_FILE_END aof_file_end
226 #undef TARGET_ASM_ALIGNED_SI_OP
227 #define TARGET_ASM_ALIGNED_SI_OP NULL
228 #undef TARGET_ASM_INTEGER
229 #define TARGET_ASM_INTEGER arm_assemble_integer
232 #undef TARGET_ASM_FUNCTION_PROLOGUE
233 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
235 #undef TARGET_ASM_FUNCTION_EPILOGUE
236 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
238 #undef TARGET_DEFAULT_TARGET_FLAGS
239 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
240 #undef TARGET_HANDLE_OPTION
241 #define TARGET_HANDLE_OPTION arm_handle_option
243 #undef TARGET_COMP_TYPE_ATTRIBUTES
244 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
246 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
247 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
249 #undef TARGET_SCHED_ADJUST_COST
250 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
252 #undef TARGET_ENCODE_SECTION_INFO
254 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
256 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
259 #undef TARGET_STRIP_NAME_ENCODING
260 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
262 #undef TARGET_ASM_INTERNAL_LABEL
263 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
265 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
266 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
268 #undef TARGET_ASM_OUTPUT_MI_THUNK
269 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
270 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
271 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
273 /* This will be overridden in arm_override_options. */
274 #undef TARGET_RTX_COSTS
275 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
276 #undef TARGET_ADDRESS_COST
277 #define TARGET_ADDRESS_COST arm_address_cost
279 #undef TARGET_SHIFT_TRUNCATION_MASK
280 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
281 #undef TARGET_VECTOR_MODE_SUPPORTED_P
282 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
284 #undef TARGET_MACHINE_DEPENDENT_REORG
285 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
287 #undef TARGET_INIT_BUILTINS
288 #define TARGET_INIT_BUILTINS arm_init_builtins
289 #undef TARGET_EXPAND_BUILTIN
290 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
292 #undef TARGET_INIT_LIBFUNCS
293 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
295 #undef TARGET_PROMOTE_FUNCTION_ARGS
296 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
297 #undef TARGET_PROMOTE_FUNCTION_RETURN
298 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
299 #undef TARGET_PROMOTE_PROTOTYPES
300 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
301 #undef TARGET_PASS_BY_REFERENCE
302 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
303 #undef TARGET_ARG_PARTIAL_BYTES
304 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
306 #undef TARGET_SETUP_INCOMING_VARARGS
307 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
309 #undef TARGET_DEFAULT_SHORT_ENUMS
310 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
312 #undef TARGET_ALIGN_ANON_BITFIELD
313 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
315 #undef TARGET_NARROW_VOLATILE_BITFIELD
316 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
318 #undef TARGET_CXX_GUARD_TYPE
319 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
321 #undef TARGET_CXX_GUARD_MASK_BIT
322 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
324 #undef TARGET_CXX_GET_COOKIE_SIZE
325 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
327 #undef TARGET_CXX_COOKIE_HAS_SIZE
328 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
330 #undef TARGET_CXX_CDTOR_RETURNS_THIS
331 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
333 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
334 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
336 #undef TARGET_CXX_USE_AEABI_ATEXIT
337 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
339 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
340 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
341 arm_cxx_determine_class_data_visibility
343 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
344 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
346 #undef TARGET_RETURN_IN_MSB
347 #define TARGET_RETURN_IN_MSB arm_return_in_msb
349 #undef TARGET_MUST_PASS_IN_STACK
350 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
352 #ifdef TARGET_UNWIND_INFO
353 #undef TARGET_UNWIND_EMIT
354 #define TARGET_UNWIND_EMIT arm_unwind_emit
356 /* EABI unwinding tables use a different format for the typeinfo tables. */
357 #undef TARGET_ASM_TTYPE
358 #define TARGET_ASM_TTYPE arm_output_ttype
360 #undef TARGET_ARM_EABI_UNWINDER
361 #define TARGET_ARM_EABI_UNWINDER true
362 #endif /* TARGET_UNWIND_INFO */
364 #undef TARGET_CANNOT_COPY_INSN_P
365 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
368 #undef TARGET_HAVE_TLS
369 #define TARGET_HAVE_TLS true
372 #undef TARGET_CANNOT_FORCE_CONST_MEM
373 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
375 struct gcc_target targetm
= TARGET_INITIALIZER
;
377 /* Obstack for minipool constant handling. */
378 static struct obstack minipool_obstack
;
379 static char * minipool_startobj
;
381 /* The maximum number of insns skipped which
382 will be conditionalised if possible. */
383 static int max_insns_skipped
= 5;
385 extern FILE * asm_out_file
;
387 /* True if we are currently building a constant table. */
388 int making_const_table
;
390 /* Define the information needed to generate branch insns. This is
391 stored from the compare operation. */
392 rtx arm_compare_op0
, arm_compare_op1
;
394 /* The processor for which instructions should be scheduled. */
395 enum processor_type arm_tune
= arm_none
;
397 /* The default processor used if not overriden by commandline. */
398 static enum processor_type arm_default_cpu
= arm_none
;
400 /* Which floating point model to use. */
401 enum arm_fp_model arm_fp_model
;
403 /* Which floating point hardware is available. */
404 enum fputype arm_fpu_arch
;
406 /* Which floating point hardware to schedule for. */
407 enum fputype arm_fpu_tune
;
409 /* Whether to use floating point hardware. */
410 enum float_abi_type arm_float_abi
;
412 /* Which ABI to use. */
413 enum arm_abi_type arm_abi
;
415 /* Which thread pointer model to use. */
416 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
418 /* Used to parse -mstructure_size_boundary command line option. */
419 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
421 /* Used for Thumb call_via trampolines. */
422 rtx thumb_call_via_label
[14];
423 static int thumb_call_reg_needed
;
425 /* Bit values used to identify processor capabilities. */
426 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
427 #define FL_ARCH3M (1 << 1) /* Extended multiply */
428 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
429 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
430 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
431 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
432 #define FL_THUMB (1 << 6) /* Thumb aware */
433 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
434 #define FL_STRONG (1 << 8) /* StrongARM */
435 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
436 #define FL_XSCALE (1 << 10) /* XScale */
437 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
438 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
439 media instructions. */
440 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
441 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
442 Note: ARM6 & 7 derivatives only. */
443 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
445 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
447 #define FL_FOR_ARCH2 0
448 #define FL_FOR_ARCH3 FL_MODE32
449 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
450 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
451 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
452 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
453 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
454 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
455 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
456 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
457 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
458 #define FL_FOR_ARCH6J FL_FOR_ARCH6
459 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
460 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
461 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
463 /* The bits in this mask specify which
464 instructions we are allowed to generate. */
465 static unsigned long insn_flags
= 0;
467 /* The bits in this mask specify which instruction scheduling options should
469 static unsigned long tune_flags
= 0;
471 /* The following are used in the arm.md file as equivalents to bits
472 in the above two flag variables. */
474 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
477 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
480 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
483 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
486 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
489 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
492 /* Nonzero if this chip supports the ARM 6K extensions. */
495 /* Nonzero if this chip can benefit from load scheduling. */
496 int arm_ld_sched
= 0;
498 /* Nonzero if this chip is a StrongARM. */
499 int arm_tune_strongarm
= 0;
501 /* Nonzero if this chip is a Cirrus variant. */
502 int arm_arch_cirrus
= 0;
504 /* Nonzero if this chip supports Intel Wireless MMX technology. */
505 int arm_arch_iwmmxt
= 0;
507 /* Nonzero if this chip is an XScale. */
508 int arm_arch_xscale
= 0;
510 /* Nonzero if tuning for XScale */
511 int arm_tune_xscale
= 0;
513 /* Nonzero if we want to tune for stores that access the write-buffer.
514 This typically means an ARM6 or ARM7 with MMU or MPU. */
515 int arm_tune_wbuf
= 0;
517 /* Nonzero if generating Thumb instructions. */
520 /* Nonzero if we should define __THUMB_INTERWORK__ in the
522 XXX This is a bit of a hack, it's intended to help work around
523 problems in GLD which doesn't understand that armv5t code is
524 interworking clean. */
525 int arm_cpp_interwork
= 0;
527 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
528 must report the mode of the memory reference from PRINT_OPERAND to
529 PRINT_OPERAND_ADDRESS. */
530 enum machine_mode output_memory_reference_mode
;
532 /* The register number to be used for the PIC offset register. */
533 unsigned arm_pic_register
= INVALID_REGNUM
;
535 /* Set to 1 when a return insn is output, this means that the epilogue
537 int return_used_this_function
;
539 /* Set to 1 after arm_reorg has started. Reset to start at the start of
540 the next function. */
541 static int after_arm_reorg
= 0;
543 /* The maximum number of insns to be used when loading a constant. */
544 static int arm_constant_limit
= 3;
546 /* For an explanation of these variables, see final_prescan_insn below. */
548 enum arm_cond_code arm_current_cc
;
550 int arm_target_label
;
552 /* The condition codes of the ARM, and the inverse function. */
553 static const char * const arm_condition_codes
[] =
555 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
556 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
559 #define streq(string1, string2) (strcmp (string1, string2) == 0)
561 /* Initialization code. */
565 const char *const name
;
566 enum processor_type core
;
568 const unsigned long flags
;
569 bool (* rtx_costs
) (rtx
, int, int, int *);
572 /* Not all of these give usefully different compilation alternatives,
573 but there is no simple way of generalizing them. */
574 static const struct processors all_cores
[] =
577 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
578 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
579 #include "arm-cores.def"
581 {NULL
, arm_none
, NULL
, 0, NULL
}
584 static const struct processors all_architectures
[] =
586 /* ARM Architectures */
587 /* We don't specify rtx_costs here as it will be figured out
590 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
591 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
592 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
593 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
594 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
595 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
596 implementations that support it, so we will leave it out for now. */
597 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
598 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
599 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
600 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
601 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
602 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
603 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
604 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
605 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
606 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
607 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
608 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
609 {NULL
, arm_none
, NULL
, 0 , NULL
}
612 struct arm_cpu_select
616 const struct processors
* processors
;
619 /* This is a magic structure. The 'string' field is magically filled in
620 with a pointer to the value specified by the user on the command line
621 assuming that the user has specified such a value. */
623 static struct arm_cpu_select arm_select
[] =
625 /* string name processors */
626 { NULL
, "-mcpu=", all_cores
},
627 { NULL
, "-march=", all_architectures
},
628 { NULL
, "-mtune=", all_cores
}
631 /* Defines representing the indexes into the above table. */
632 #define ARM_OPT_SET_CPU 0
633 #define ARM_OPT_SET_ARCH 1
634 #define ARM_OPT_SET_TUNE 2
636 /* The name of the preprocessor macro to define for this architecture. */
638 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
647 /* Available values for -mfpu=. */
649 static const struct fpu_desc all_fpus
[] =
651 {"fpa", FPUTYPE_FPA
},
652 {"fpe2", FPUTYPE_FPA_EMU2
},
653 {"fpe3", FPUTYPE_FPA_EMU2
},
654 {"maverick", FPUTYPE_MAVERICK
},
659 /* Floating point models used by the different hardware.
660 See fputype in arm.h. */
662 static const enum fputype fp_model_for_fpu
[] =
664 /* No FP hardware. */
665 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
666 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
667 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
668 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
669 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
670 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
677 enum float_abi_type abi_type
;
681 /* Available values for -mfloat-abi=. */
683 static const struct float_abi all_float_abis
[] =
685 {"soft", ARM_FLOAT_ABI_SOFT
},
686 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
687 {"hard", ARM_FLOAT_ABI_HARD
}
694 enum arm_abi_type abi_type
;
698 /* Available values for -mabi=. */
700 static const struct abi_name arm_all_abis
[] =
702 {"apcs-gnu", ARM_ABI_APCS
},
703 {"atpcs", ARM_ABI_ATPCS
},
704 {"aapcs", ARM_ABI_AAPCS
},
705 {"iwmmxt", ARM_ABI_IWMMXT
},
706 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
709 /* Supported TLS relocations. */
719 /* Emit an insn that's a simple single-set. Both the operands must be known
722 emit_set_insn (rtx x
, rtx y
)
724 return emit_insn (gen_rtx_SET (VOIDmode
, x
, y
));
727 /* Return the number of bits set in VALUE. */
729 bit_count (unsigned long value
)
731 unsigned long count
= 0;
736 value
&= value
- 1; /* Clear the least-significant set bit. */
742 /* Set up library functions unique to ARM. */
745 arm_init_libfuncs (void)
747 /* There are no special library functions unless we are using the
752 /* The functions below are described in Section 4 of the "Run-Time
753 ABI for the ARM architecture", Version 1.0. */
755 /* Double-precision floating-point arithmetic. Table 2. */
756 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
757 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
758 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
759 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
760 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
762 /* Double-precision comparisons. Table 3. */
763 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
764 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
765 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
766 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
767 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
768 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
769 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
771 /* Single-precision floating-point arithmetic. Table 4. */
772 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
773 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
774 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
775 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
776 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
778 /* Single-precision comparisons. Table 5. */
779 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
780 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
781 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
782 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
783 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
784 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
785 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
787 /* Floating-point to integer conversions. Table 6. */
788 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
789 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
790 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
791 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
792 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
793 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
794 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
795 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
797 /* Conversions between floating types. Table 7. */
798 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
799 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
801 /* Integer to floating-point conversions. Table 8. */
802 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
803 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
804 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
805 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
806 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
807 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
808 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
809 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
811 /* Long long. Table 9. */
812 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
813 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
814 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
815 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
816 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
817 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
818 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
819 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
821 /* Integer (32/32->32) division. \S 4.3.1. */
822 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
823 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
825 /* The divmod functions are designed so that they can be used for
826 plain division, even though they return both the quotient and the
827 remainder. The quotient is returned in the usual location (i.e.,
828 r0 for SImode, {r0, r1} for DImode), just as would be expected
829 for an ordinary division routine. Because the AAPCS calling
830 conventions specify that all of { r0, r1, r2, r3 } are
831 callee-saved registers, there is no need to tell the compiler
832 explicitly that those registers are clobbered by these
834 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
835 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
837 /* For SImode division the ABI provides div-without-mod routines,
839 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
840 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
842 /* We don't have mod libcalls. Fortunately gcc knows how to use the
843 divmod libcalls instead. */
844 set_optab_libfunc (smod_optab
, DImode
, NULL
);
845 set_optab_libfunc (umod_optab
, DImode
, NULL
);
846 set_optab_libfunc (smod_optab
, SImode
, NULL
);
847 set_optab_libfunc (umod_optab
, SImode
, NULL
);
850 /* Implement TARGET_HANDLE_OPTION. */
853 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
858 arm_select
[1].string
= arg
;
862 arm_select
[0].string
= arg
;
865 case OPT_mhard_float
:
866 target_float_abi_name
= "hard";
869 case OPT_msoft_float
:
870 target_float_abi_name
= "soft";
874 arm_select
[2].string
= arg
;
882 /* Fix up any incompatible options that the user has specified.
883 This has now turned into a maze. */
885 arm_override_options (void)
888 enum processor_type target_arch_cpu
= arm_none
;
890 /* Set up the flags based on the cpu/architecture selected by the user. */
891 for (i
= ARRAY_SIZE (arm_select
); i
--;)
893 struct arm_cpu_select
* ptr
= arm_select
+ i
;
895 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
897 const struct processors
* sel
;
899 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
900 if (streq (ptr
->string
, sel
->name
))
902 /* Set the architecture define. */
903 if (i
!= ARM_OPT_SET_TUNE
)
904 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
906 /* Determine the processor core for which we should
907 tune code-generation. */
908 if (/* -mcpu= is a sensible default. */
910 /* -mtune= overrides -mcpu= and -march=. */
911 || i
== ARM_OPT_SET_TUNE
)
912 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
914 /* Remember the CPU associated with this architecture.
915 If no other option is used to set the CPU type,
916 we'll use this to guess the most suitable tuning
918 if (i
== ARM_OPT_SET_ARCH
)
919 target_arch_cpu
= sel
->core
;
921 if (i
!= ARM_OPT_SET_TUNE
)
923 /* If we have been given an architecture and a processor
924 make sure that they are compatible. We only generate
925 a warning though, and we prefer the CPU over the
927 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
928 warning (0, "switch -mcpu=%s conflicts with -march= switch",
931 insn_flags
= sel
->flags
;
937 if (sel
->name
== NULL
)
938 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
942 /* Guess the tuning options from the architecture if necessary. */
943 if (arm_tune
== arm_none
)
944 arm_tune
= target_arch_cpu
;
946 /* If the user did not specify a processor, choose one for them. */
949 const struct processors
* sel
;
951 enum processor_type cpu
;
953 cpu
= TARGET_CPU_DEFAULT
;
956 #ifdef SUBTARGET_CPU_DEFAULT
957 /* Use the subtarget default CPU if none was specified by
959 cpu
= SUBTARGET_CPU_DEFAULT
;
961 /* Default to ARM6. */
965 sel
= &all_cores
[cpu
];
967 insn_flags
= sel
->flags
;
969 /* Now check to see if the user has specified some command line
970 switch that require certain abilities from the cpu. */
973 if (TARGET_INTERWORK
|| TARGET_THUMB
)
975 sought
|= (FL_THUMB
| FL_MODE32
);
977 /* There are no ARM processors that support both APCS-26 and
978 interworking. Therefore we force FL_MODE26 to be removed
979 from insn_flags here (if it was set), so that the search
980 below will always be able to find a compatible processor. */
981 insn_flags
&= ~FL_MODE26
;
984 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
986 /* Try to locate a CPU type that supports all of the abilities
987 of the default CPU, plus the extra abilities requested by
989 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
990 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
993 if (sel
->name
== NULL
)
995 unsigned current_bit_count
= 0;
996 const struct processors
* best_fit
= NULL
;
998 /* Ideally we would like to issue an error message here
999 saying that it was not possible to find a CPU compatible
1000 with the default CPU, but which also supports the command
1001 line options specified by the programmer, and so they
1002 ought to use the -mcpu=<name> command line option to
1003 override the default CPU type.
1005 If we cannot find a cpu that has both the
1006 characteristics of the default cpu and the given
1007 command line options we scan the array again looking
1008 for a best match. */
1009 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1010 if ((sel
->flags
& sought
) == sought
)
1014 count
= bit_count (sel
->flags
& insn_flags
);
1016 if (count
>= current_bit_count
)
1019 current_bit_count
= count
;
1023 gcc_assert (best_fit
);
1027 insn_flags
= sel
->flags
;
1029 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1030 arm_default_cpu
= (enum processor_type
) (sel
- all_cores
);
1031 if (arm_tune
== arm_none
)
1032 arm_tune
= arm_default_cpu
;
1035 /* The processor for which we should tune should now have been
1037 gcc_assert (arm_tune
!= arm_none
);
1039 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1041 targetm
.rtx_costs
= arm_size_rtx_costs
;
1043 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
1045 /* Make sure that the processor choice does not conflict with any of the
1046 other command line choices. */
1047 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
1049 warning (0, "target CPU does not support interworking" );
1050 target_flags
&= ~MASK_INTERWORK
;
1053 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1055 warning (0, "target CPU does not support THUMB instructions");
1056 target_flags
&= ~MASK_THUMB
;
1059 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1061 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1062 target_flags
&= ~MASK_APCS_FRAME
;
1065 /* Callee super interworking implies thumb interworking. Adding
1066 this to the flags here simplifies the logic elsewhere. */
1067 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1068 target_flags
|= MASK_INTERWORK
;
1070 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1071 from here where no function is being compiled currently. */
1072 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1073 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1075 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1076 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1078 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1079 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1081 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1083 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1084 target_flags
|= MASK_APCS_FRAME
;
1087 if (TARGET_POKE_FUNCTION_NAME
)
1088 target_flags
|= MASK_APCS_FRAME
;
1090 if (TARGET_APCS_REENT
&& flag_pic
)
1091 error ("-fpic and -mapcs-reent are incompatible");
1093 if (TARGET_APCS_REENT
)
1094 warning (0, "APCS reentrant code not supported. Ignored");
1096 /* If this target is normally configured to use APCS frames, warn if they
1097 are turned off and debugging is turned on. */
1099 && write_symbols
!= NO_DEBUG
1100 && !TARGET_APCS_FRAME
1101 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1102 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1104 /* If stack checking is disabled, we can use r10 as the PIC register,
1105 which keeps r9 available. */
1106 if (flag_pic
&& TARGET_SINGLE_PIC_BASE
)
1107 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1109 if (TARGET_APCS_FLOAT
)
1110 warning (0, "passing floating point arguments in fp regs not yet supported");
1112 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1113 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1114 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1115 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1116 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1117 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1118 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1119 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1120 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1121 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1123 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1124 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1125 thumb_code
= (TARGET_ARM
== 0);
1126 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1127 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1128 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1130 /* V5 code we generate is completely interworking capable, so we turn off
1131 TARGET_INTERWORK here to avoid many tests later on. */
1133 /* XXX However, we must pass the right pre-processor defines to CPP
1134 or GLD can get confused. This is a hack. */
1135 if (TARGET_INTERWORK
)
1136 arm_cpp_interwork
= 1;
1139 target_flags
&= ~MASK_INTERWORK
;
1141 if (target_abi_name
)
1143 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1145 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1147 arm_abi
= arm_all_abis
[i
].abi_type
;
1151 if (i
== ARRAY_SIZE (arm_all_abis
))
1152 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1155 arm_abi
= ARM_DEFAULT_ABI
;
1157 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1158 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1160 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1161 error ("iwmmxt abi requires an iwmmxt capable cpu");
1163 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1164 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1166 if (streq (target_fpe_name
, "2"))
1167 target_fpu_name
= "fpe2";
1168 else if (streq (target_fpe_name
, "3"))
1169 target_fpu_name
= "fpe3";
1171 error ("invalid floating point emulation option: -mfpe=%s",
1174 if (target_fpu_name
!= NULL
)
1176 /* The user specified a FPU. */
1177 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1179 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1181 arm_fpu_arch
= all_fpus
[i
].fpu
;
1182 arm_fpu_tune
= arm_fpu_arch
;
1183 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1187 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1188 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1192 #ifdef FPUTYPE_DEFAULT
1193 /* Use the default if it is specified for this platform. */
1194 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1195 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1197 /* Pick one based on CPU type. */
1198 /* ??? Some targets assume FPA is the default.
1199 if ((insn_flags & FL_VFP) != 0)
1200 arm_fpu_arch = FPUTYPE_VFP;
1203 if (arm_arch_cirrus
)
1204 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1206 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1208 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1209 arm_fpu_tune
= FPUTYPE_FPA
;
1211 arm_fpu_tune
= arm_fpu_arch
;
1212 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1213 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1216 if (target_float_abi_name
!= NULL
)
1218 /* The user specified a FP ABI. */
1219 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1221 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1223 arm_float_abi
= all_float_abis
[i
].abi_type
;
1227 if (i
== ARRAY_SIZE (all_float_abis
))
1228 error ("invalid floating point abi: -mfloat-abi=%s",
1229 target_float_abi_name
);
1232 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1234 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1235 sorry ("-mfloat-abi=hard and VFP");
1237 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1238 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1239 will ever exist. GCC makes no attempt to support this combination. */
1240 if (TARGET_IWMMXT
&& !TARGET_SOFT_FLOAT
)
1241 sorry ("iWMMXt and hardware floating point");
1243 /* If soft-float is specified then don't use FPU. */
1244 if (TARGET_SOFT_FLOAT
)
1245 arm_fpu_arch
= FPUTYPE_NONE
;
1247 /* For arm2/3 there is no need to do any scheduling if there is only
1248 a floating point emulator, or we are doing software floating-point. */
1249 if ((TARGET_SOFT_FLOAT
1250 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1251 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1252 && (tune_flags
& FL_MODE32
) == 0)
1253 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1255 if (target_thread_switch
)
1257 if (strcmp (target_thread_switch
, "soft") == 0)
1258 target_thread_pointer
= TP_SOFT
;
1259 else if (strcmp (target_thread_switch
, "auto") == 0)
1260 target_thread_pointer
= TP_AUTO
;
1261 else if (strcmp (target_thread_switch
, "cp15") == 0)
1262 target_thread_pointer
= TP_CP15
;
1264 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1267 /* Use the cp15 method if it is available. */
1268 if (target_thread_pointer
== TP_AUTO
)
1270 if (arm_arch6k
&& !TARGET_THUMB
)
1271 target_thread_pointer
= TP_CP15
;
1273 target_thread_pointer
= TP_SOFT
;
1276 if (TARGET_HARD_TP
&& TARGET_THUMB
)
1277 error ("can not use -mtp=cp15 with -mthumb");
1279 /* Override the default structure alignment for AAPCS ABI. */
1280 if (TARGET_AAPCS_BASED
)
1281 arm_structure_size_boundary
= 8;
1283 if (structure_size_string
!= NULL
)
1285 int size
= strtol (structure_size_string
, NULL
, 0);
1287 if (size
== 8 || size
== 32
1288 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1289 arm_structure_size_boundary
= size
;
1291 warning (0, "structure size boundary can only be set to %s",
1292 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1295 if (arm_pic_register_string
!= NULL
)
1297 int pic_register
= decode_reg_name (arm_pic_register_string
);
1300 warning (0, "-mpic-register= is useless without -fpic");
1302 /* Prevent the user from choosing an obviously stupid PIC register. */
1303 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1304 || pic_register
== HARD_FRAME_POINTER_REGNUM
1305 || pic_register
== STACK_POINTER_REGNUM
1306 || pic_register
>= PC_REGNUM
)
1307 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1309 arm_pic_register
= pic_register
;
1312 if (TARGET_THUMB
&& flag_schedule_insns
)
1314 /* Don't warn since it's on by default in -O2. */
1315 flag_schedule_insns
= 0;
1320 arm_constant_limit
= 1;
1322 /* If optimizing for size, bump the number of instructions that we
1323 are prepared to conditionally execute (even on a StrongARM). */
1324 max_insns_skipped
= 6;
1328 /* For processors with load scheduling, it never costs more than
1329 2 cycles to load a constant, and the load scheduler may well
1330 reduce that to 1. */
1332 arm_constant_limit
= 1;
1334 /* On XScale the longer latency of a load makes it more difficult
1335 to achieve a good schedule, so it's faster to synthesize
1336 constants that can be done in two insns. */
1337 if (arm_tune_xscale
)
1338 arm_constant_limit
= 2;
1340 /* StrongARM has early execution of branches, so a sequence
1341 that is worth skipping is shorter. */
1342 if (arm_tune_strongarm
)
1343 max_insns_skipped
= 3;
1346 /* Register global variables with the garbage collector. */
1347 arm_add_gc_roots ();
1351 arm_add_gc_roots (void)
1353 gcc_obstack_init(&minipool_obstack
);
1354 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1357 /* A table of known ARM exception types.
1358 For use with the interrupt function attribute. */
1362 const char *const arg
;
1363 const unsigned long return_value
;
1367 static const isr_attribute_arg isr_attribute_args
[] =
1369 { "IRQ", ARM_FT_ISR
},
1370 { "irq", ARM_FT_ISR
},
1371 { "FIQ", ARM_FT_FIQ
},
1372 { "fiq", ARM_FT_FIQ
},
1373 { "ABORT", ARM_FT_ISR
},
1374 { "abort", ARM_FT_ISR
},
1375 { "ABORT", ARM_FT_ISR
},
1376 { "abort", ARM_FT_ISR
},
1377 { "UNDEF", ARM_FT_EXCEPTION
},
1378 { "undef", ARM_FT_EXCEPTION
},
1379 { "SWI", ARM_FT_EXCEPTION
},
1380 { "swi", ARM_FT_EXCEPTION
},
1381 { NULL
, ARM_FT_NORMAL
}
1384 /* Returns the (interrupt) function type of the current
1385 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1387 static unsigned long
1388 arm_isr_value (tree argument
)
1390 const isr_attribute_arg
* ptr
;
1393 /* No argument - default to IRQ. */
1394 if (argument
== NULL_TREE
)
1397 /* Get the value of the argument. */
1398 if (TREE_VALUE (argument
) == NULL_TREE
1399 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1400 return ARM_FT_UNKNOWN
;
1402 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1404 /* Check it against the list of known arguments. */
1405 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1406 if (streq (arg
, ptr
->arg
))
1407 return ptr
->return_value
;
1409 /* An unrecognized interrupt type. */
1410 return ARM_FT_UNKNOWN
;
1413 /* Computes the type of the current function. */
1415 static unsigned long
1416 arm_compute_func_type (void)
1418 unsigned long type
= ARM_FT_UNKNOWN
;
1422 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1424 /* Decide if the current function is volatile. Such functions
1425 never return, and many memory cycles can be saved by not storing
1426 register values that will never be needed again. This optimization
1427 was added to speed up context switching in a kernel application. */
1429 && (TREE_NOTHROW (current_function_decl
)
1430 || !(flag_unwind_tables
1431 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
)))
1432 && TREE_THIS_VOLATILE (current_function_decl
))
1433 type
|= ARM_FT_VOLATILE
;
1435 if (cfun
->static_chain_decl
!= NULL
)
1436 type
|= ARM_FT_NESTED
;
1438 attr
= DECL_ATTRIBUTES (current_function_decl
);
1440 a
= lookup_attribute ("naked", attr
);
1442 type
|= ARM_FT_NAKED
;
1444 a
= lookup_attribute ("isr", attr
);
1446 a
= lookup_attribute ("interrupt", attr
);
1449 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1451 type
|= arm_isr_value (TREE_VALUE (a
));
1456 /* Returns the type of the current function. */
1459 arm_current_func_type (void)
1461 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1462 cfun
->machine
->func_type
= arm_compute_func_type ();
1464 return cfun
->machine
->func_type
;
1467 /* Return 1 if it is possible to return using a single instruction.
1468 If SIBLING is non-null, this is a test for a return before a sibling
1469 call. SIBLING is the call insn, so we can examine its register usage. */
1472 use_return_insn (int iscond
, rtx sibling
)
1475 unsigned int func_type
;
1476 unsigned long saved_int_regs
;
1477 unsigned HOST_WIDE_INT stack_adjust
;
1478 arm_stack_offsets
*offsets
;
1480 /* Never use a return instruction before reload has run. */
1481 if (!reload_completed
)
1484 func_type
= arm_current_func_type ();
1486 /* Naked functions and volatile functions need special
1488 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1491 /* So do interrupt functions that use the frame pointer. */
1492 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1495 offsets
= arm_get_frame_offsets ();
1496 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1498 /* As do variadic functions. */
1499 if (current_function_pretend_args_size
1500 || cfun
->machine
->uses_anonymous_args
1501 /* Or if the function calls __builtin_eh_return () */
1502 || current_function_calls_eh_return
1503 /* Or if the function calls alloca */
1504 || current_function_calls_alloca
1505 /* Or if there is a stack adjustment. However, if the stack pointer
1506 is saved on the stack, we can use a pre-incrementing stack load. */
1507 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1510 saved_int_regs
= arm_compute_save_reg_mask ();
1512 /* Unfortunately, the insn
1514 ldmib sp, {..., sp, ...}
1516 triggers a bug on most SA-110 based devices, such that the stack
1517 pointer won't be correctly restored if the instruction takes a
1518 page fault. We work around this problem by popping r3 along with
1519 the other registers, since that is never slower than executing
1520 another instruction.
1522 We test for !arm_arch5 here, because code for any architecture
1523 less than this could potentially be run on one of the buggy
1525 if (stack_adjust
== 4 && !arm_arch5
)
1527 /* Validate that r3 is a call-clobbered register (always true in
1528 the default abi) ... */
1529 if (!call_used_regs
[3])
1532 /* ... that it isn't being used for a return value ... */
1533 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1536 /* ... or for a tail-call argument ... */
1539 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1541 if (find_regno_fusage (sibling
, USE
, 3))
1545 /* ... and that there are no call-saved registers in r0-r2
1546 (always true in the default ABI). */
1547 if (saved_int_regs
& 0x7)
1551 /* Can't be done if interworking with Thumb, and any registers have been
1553 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1556 /* On StrongARM, conditional returns are expensive if they aren't
1557 taken and multiple registers have been stacked. */
1558 if (iscond
&& arm_tune_strongarm
)
1560 /* Conditional return when just the LR is stored is a simple
1561 conditional-load instruction, that's not expensive. */
1562 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1566 && arm_pic_register
!= INVALID_REGNUM
1567 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1571 /* If there are saved registers but the LR isn't saved, then we need
1572 two instructions for the return. */
1573 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1576 /* Can't be done if any of the FPA regs are pushed,
1577 since this also requires an insn. */
1578 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1579 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1580 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1583 /* Likewise VFP regs. */
1584 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1585 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1586 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1589 if (TARGET_REALLY_IWMMXT
)
1590 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1591 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1597 /* Return TRUE if int I is a valid immediate ARM constant. */
1600 const_ok_for_arm (HOST_WIDE_INT i
)
1604 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1605 be all zero, or all one. */
1606 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1607 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1608 != ((~(unsigned HOST_WIDE_INT
) 0)
1609 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1612 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1614 /* Fast return for 0 and small values. We must do this for zero, since
1615 the code below can't handle that one case. */
1616 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1619 /* Get the number of trailing zeros, rounded down to the nearest even
1621 lowbit
= (ffs ((int) i
) - 1) & ~1;
1623 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1625 else if (lowbit
<= 4
1626 && ((i
& ~0xc000003f) == 0
1627 || (i
& ~0xf000000f) == 0
1628 || (i
& ~0xfc000003) == 0))
1634 /* Return true if I is a valid constant for the operation CODE. */
1636 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1638 if (const_ok_for_arm (i
))
1644 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1646 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1652 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1659 /* Emit a sequence of insns to handle a large constant.
1660 CODE is the code of the operation required, it can be any of SET, PLUS,
1661 IOR, AND, XOR, MINUS;
1662 MODE is the mode in which the operation is being performed;
1663 VAL is the integer to operate on;
1664 SOURCE is the other operand (a register, or a null-pointer for SET);
1665 SUBTARGETS means it is safe to create scratch registers if that will
1666 either produce a simpler sequence, or we will want to cse the values.
1667 Return value is the number of insns emitted. */
1670 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1671 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1675 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1676 cond
= COND_EXEC_TEST (PATTERN (insn
));
1680 if (subtargets
|| code
== SET
1681 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1682 && REGNO (target
) != REGNO (source
)))
1684 /* After arm_reorg has been called, we can't fix up expensive
1685 constants by pushing them into memory so we must synthesize
1686 them in-line, regardless of the cost. This is only likely to
1687 be more costly on chips that have load delay slots and we are
1688 compiling without running the scheduler (so no splitting
1689 occurred before the final instruction emission).
1691 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1693 if (!after_arm_reorg
1695 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1697 > arm_constant_limit
+ (code
!= SET
)))
1701 /* Currently SET is the only monadic value for CODE, all
1702 the rest are diadic. */
1703 emit_set_insn (target
, GEN_INT (val
));
1708 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1710 emit_set_insn (temp
, GEN_INT (val
));
1711 /* For MINUS, the value is subtracted from, since we never
1712 have subtraction of a constant. */
1714 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
1716 emit_set_insn (target
,
1717 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
1723 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1728 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1730 HOST_WIDE_INT temp1
;
1738 if (remainder
& (3 << (i
- 2)))
1743 temp1
= remainder
& ((0x0ff << end
)
1744 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1745 remainder
&= ~temp1
;
1750 } while (remainder
);
1754 /* Emit an instruction with the indicated PATTERN. If COND is
1755 non-NULL, conditionalize the execution of the instruction on COND
1759 emit_constant_insn (rtx cond
, rtx pattern
)
1762 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1763 emit_insn (pattern
);
1766 /* As above, but extra parameter GENERATE which, if clear, suppresses
1770 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1771 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1776 int can_negate_initial
= 0;
1779 int num_bits_set
= 0;
1780 int set_sign_bit_copies
= 0;
1781 int clear_sign_bit_copies
= 0;
1782 int clear_zero_bit_copies
= 0;
1783 int set_zero_bit_copies
= 0;
1785 unsigned HOST_WIDE_INT temp1
, temp2
;
1786 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1788 /* Find out which operations are safe for a given CODE. Also do a quick
1789 check for degenerate cases; these can occur when DImode operations
1801 can_negate_initial
= 1;
1805 if (remainder
== 0xffffffff)
1808 emit_constant_insn (cond
,
1809 gen_rtx_SET (VOIDmode
, target
,
1810 GEN_INT (ARM_SIGN_EXTEND (val
))));
1815 if (reload_completed
&& rtx_equal_p (target
, source
))
1818 emit_constant_insn (cond
,
1819 gen_rtx_SET (VOIDmode
, target
, source
));
1828 emit_constant_insn (cond
,
1829 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1832 if (remainder
== 0xffffffff)
1834 if (reload_completed
&& rtx_equal_p (target
, source
))
1837 emit_constant_insn (cond
,
1838 gen_rtx_SET (VOIDmode
, target
, source
));
1847 if (reload_completed
&& rtx_equal_p (target
, source
))
1850 emit_constant_insn (cond
,
1851 gen_rtx_SET (VOIDmode
, target
, source
));
1855 /* We don't know how to handle other cases yet. */
1856 gcc_assert (remainder
== 0xffffffff);
1859 emit_constant_insn (cond
,
1860 gen_rtx_SET (VOIDmode
, target
,
1861 gen_rtx_NOT (mode
, source
)));
1865 /* We treat MINUS as (val - source), since (source - val) is always
1866 passed as (source + (-val)). */
1870 emit_constant_insn (cond
,
1871 gen_rtx_SET (VOIDmode
, target
,
1872 gen_rtx_NEG (mode
, source
)));
1875 if (const_ok_for_arm (val
))
1878 emit_constant_insn (cond
,
1879 gen_rtx_SET (VOIDmode
, target
,
1880 gen_rtx_MINUS (mode
, GEN_INT (val
),
1892 /* If we can do it in one insn get out quickly. */
1893 if (const_ok_for_arm (val
)
1894 || (can_negate_initial
&& const_ok_for_arm (-val
))
1895 || (can_invert
&& const_ok_for_arm (~val
)))
1898 emit_constant_insn (cond
,
1899 gen_rtx_SET (VOIDmode
, target
,
1901 ? gen_rtx_fmt_ee (code
, mode
, source
,
1907 /* Calculate a few attributes that may be useful for specific
1909 for (i
= 31; i
>= 0; i
--)
1911 if ((remainder
& (1 << i
)) == 0)
1912 clear_sign_bit_copies
++;
1917 for (i
= 31; i
>= 0; i
--)
1919 if ((remainder
& (1 << i
)) != 0)
1920 set_sign_bit_copies
++;
1925 for (i
= 0; i
<= 31; i
++)
1927 if ((remainder
& (1 << i
)) == 0)
1928 clear_zero_bit_copies
++;
1933 for (i
= 0; i
<= 31; i
++)
1935 if ((remainder
& (1 << i
)) != 0)
1936 set_zero_bit_copies
++;
1944 /* See if we can do this by sign_extending a constant that is known
1945 to be negative. This is a good, way of doing it, since the shift
1946 may well merge into a subsequent insn. */
1947 if (set_sign_bit_copies
> 1)
1949 if (const_ok_for_arm
1950 (temp1
= ARM_SIGN_EXTEND (remainder
1951 << (set_sign_bit_copies
- 1))))
1955 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1956 emit_constant_insn (cond
,
1957 gen_rtx_SET (VOIDmode
, new_src
,
1959 emit_constant_insn (cond
,
1960 gen_ashrsi3 (target
, new_src
,
1961 GEN_INT (set_sign_bit_copies
- 1)));
1965 /* For an inverted constant, we will need to set the low bits,
1966 these will be shifted out of harm's way. */
1967 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1968 if (const_ok_for_arm (~temp1
))
1972 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1973 emit_constant_insn (cond
,
1974 gen_rtx_SET (VOIDmode
, new_src
,
1976 emit_constant_insn (cond
,
1977 gen_ashrsi3 (target
, new_src
,
1978 GEN_INT (set_sign_bit_copies
- 1)));
1984 /* See if we can calculate the value as the difference between two
1985 valid immediates. */
1986 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
1988 int topshift
= clear_sign_bit_copies
& ~1;
1990 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
1991 & (0xff000000 >> topshift
));
1993 /* If temp1 is zero, then that means the 9 most significant
1994 bits of remainder were 1 and we've caused it to overflow.
1995 When topshift is 0 we don't need to do anything since we
1996 can borrow from 'bit 32'. */
1997 if (temp1
== 0 && topshift
!= 0)
1998 temp1
= 0x80000000 >> (topshift
- 1);
2000 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
2002 if (const_ok_for_arm (temp2
))
2006 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2007 emit_constant_insn (cond
,
2008 gen_rtx_SET (VOIDmode
, new_src
,
2010 emit_constant_insn (cond
,
2011 gen_addsi3 (target
, new_src
,
2019 /* See if we can generate this by setting the bottom (or the top)
2020 16 bits, and then shifting these into the other half of the
2021 word. We only look for the simplest cases, to do more would cost
2022 too much. Be careful, however, not to generate this when the
2023 alternative would take fewer insns. */
2024 if (val
& 0xffff0000)
2026 temp1
= remainder
& 0xffff0000;
2027 temp2
= remainder
& 0x0000ffff;
2029 /* Overlaps outside this range are best done using other methods. */
2030 for (i
= 9; i
< 24; i
++)
2032 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2033 && !const_ok_for_arm (temp2
))
2035 rtx new_src
= (subtargets
2036 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2038 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2039 source
, subtargets
, generate
);
2047 gen_rtx_ASHIFT (mode
, source
,
2054 /* Don't duplicate cases already considered. */
2055 for (i
= 17; i
< 24; i
++)
2057 if (((temp1
| (temp1
>> i
)) == remainder
)
2058 && !const_ok_for_arm (temp1
))
2060 rtx new_src
= (subtargets
2061 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2063 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2064 source
, subtargets
, generate
);
2069 gen_rtx_SET (VOIDmode
, target
,
2072 gen_rtx_LSHIFTRT (mode
, source
,
2083 /* If we have IOR or XOR, and the constant can be loaded in a
2084 single instruction, and we can find a temporary to put it in,
2085 then this can be done in two instructions instead of 3-4. */
2087 /* TARGET can't be NULL if SUBTARGETS is 0 */
2088 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2090 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2094 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2096 emit_constant_insn (cond
,
2097 gen_rtx_SET (VOIDmode
, sub
,
2099 emit_constant_insn (cond
,
2100 gen_rtx_SET (VOIDmode
, target
,
2101 gen_rtx_fmt_ee (code
, mode
,
2111 if (set_sign_bit_copies
> 8
2112 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2116 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2117 rtx shift
= GEN_INT (set_sign_bit_copies
);
2121 gen_rtx_SET (VOIDmode
, sub
,
2123 gen_rtx_ASHIFT (mode
,
2128 gen_rtx_SET (VOIDmode
, target
,
2130 gen_rtx_LSHIFTRT (mode
, sub
,
2136 if (set_zero_bit_copies
> 8
2137 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2141 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2142 rtx shift
= GEN_INT (set_zero_bit_copies
);
2146 gen_rtx_SET (VOIDmode
, sub
,
2148 gen_rtx_LSHIFTRT (mode
,
2153 gen_rtx_SET (VOIDmode
, target
,
2155 gen_rtx_ASHIFT (mode
, sub
,
2161 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2165 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2166 emit_constant_insn (cond
,
2167 gen_rtx_SET (VOIDmode
, sub
,
2168 gen_rtx_NOT (mode
, source
)));
2171 sub
= gen_reg_rtx (mode
);
2172 emit_constant_insn (cond
,
2173 gen_rtx_SET (VOIDmode
, sub
,
2174 gen_rtx_AND (mode
, source
,
2176 emit_constant_insn (cond
,
2177 gen_rtx_SET (VOIDmode
, target
,
2178 gen_rtx_NOT (mode
, sub
)));
2185 /* See if two shifts will do 2 or more insn's worth of work. */
2186 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2188 HOST_WIDE_INT shift_mask
= ((0xffffffff
2189 << (32 - clear_sign_bit_copies
))
2192 if ((remainder
| shift_mask
) != 0xffffffff)
2196 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2197 insns
= arm_gen_constant (AND
, mode
, cond
,
2198 remainder
| shift_mask
,
2199 new_src
, source
, subtargets
, 1);
2204 rtx targ
= subtargets
? NULL_RTX
: target
;
2205 insns
= arm_gen_constant (AND
, mode
, cond
,
2206 remainder
| shift_mask
,
2207 targ
, source
, subtargets
, 0);
2213 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2214 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2216 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2217 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2223 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2225 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2227 if ((remainder
| shift_mask
) != 0xffffffff)
2231 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2233 insns
= arm_gen_constant (AND
, mode
, cond
,
2234 remainder
| shift_mask
,
2235 new_src
, source
, subtargets
, 1);
2240 rtx targ
= subtargets
? NULL_RTX
: target
;
2242 insns
= arm_gen_constant (AND
, mode
, cond
,
2243 remainder
| shift_mask
,
2244 targ
, source
, subtargets
, 0);
2250 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2251 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2253 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2254 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2266 for (i
= 0; i
< 32; i
++)
2267 if (remainder
& (1 << i
))
2270 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2271 remainder
= (~remainder
) & 0xffffffff;
2272 else if (code
== PLUS
&& num_bits_set
> 16)
2273 remainder
= (-remainder
) & 0xffffffff;
2280 /* Now try and find a way of doing the job in either two or three
2282 We start by looking for the largest block of zeros that are aligned on
2283 a 2-bit boundary, we then fill up the temps, wrapping around to the
2284 top of the word when we drop off the bottom.
2285 In the worst case this code should produce no more than four insns. */
2288 int best_consecutive_zeros
= 0;
2290 for (i
= 0; i
< 32; i
+= 2)
2292 int consecutive_zeros
= 0;
2294 if (!(remainder
& (3 << i
)))
2296 while ((i
< 32) && !(remainder
& (3 << i
)))
2298 consecutive_zeros
+= 2;
2301 if (consecutive_zeros
> best_consecutive_zeros
)
2303 best_consecutive_zeros
= consecutive_zeros
;
2304 best_start
= i
- consecutive_zeros
;
2310 /* So long as it won't require any more insns to do so, it's
2311 desirable to emit a small constant (in bits 0...9) in the last
2312 insn. This way there is more chance that it can be combined with
2313 a later addressing insn to form a pre-indexed load or store
2314 operation. Consider:
2316 *((volatile int *)0xe0000100) = 1;
2317 *((volatile int *)0xe0000110) = 2;
2319 We want this to wind up as:
2323 str rB, [rA, #0x100]
2325 str rB, [rA, #0x110]
2327 rather than having to synthesize both large constants from scratch.
2329 Therefore, we calculate how many insns would be required to emit
2330 the constant starting from `best_start', and also starting from
2331 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2332 yield a shorter sequence, we may as well use zero. */
2334 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2335 && (count_insns_for_constant (remainder
, 0) <=
2336 count_insns_for_constant (remainder
, best_start
)))
2339 /* Now start emitting the insns. */
2347 if (remainder
& (3 << (i
- 2)))
2352 temp1
= remainder
& ((0x0ff << end
)
2353 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2354 remainder
&= ~temp1
;
2358 rtx new_src
, temp1_rtx
;
2360 if (code
== SET
|| code
== MINUS
)
2362 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2363 if (can_invert
&& code
!= MINUS
)
2368 if (remainder
&& subtargets
)
2369 new_src
= gen_reg_rtx (mode
);
2374 else if (can_negate
)
2378 temp1
= trunc_int_for_mode (temp1
, mode
);
2379 temp1_rtx
= GEN_INT (temp1
);
2383 else if (code
== MINUS
)
2384 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2386 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2388 emit_constant_insn (cond
,
2389 gen_rtx_SET (VOIDmode
, new_src
,
2399 else if (code
== MINUS
)
2413 /* Canonicalize a comparison so that we are more likely to recognize it.
2414 This can be done for a few constant compares, where we can make the
2415 immediate value easier to load. */
2418 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2421 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2422 unsigned HOST_WIDE_INT maxval
;
2423 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2434 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2436 *op1
= GEN_INT (i
+ 1);
2437 return code
== GT
? GE
: LT
;
2444 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2446 *op1
= GEN_INT (i
- 1);
2447 return code
== GE
? GT
: LE
;
2453 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2454 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2456 *op1
= GEN_INT (i
+ 1);
2457 return code
== GTU
? GEU
: LTU
;
2464 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2466 *op1
= GEN_INT (i
- 1);
2467 return code
== GEU
? GTU
: LEU
;
2479 /* Define how to find the value returned by a function. */
2482 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2484 enum machine_mode mode
;
2485 int unsignedp ATTRIBUTE_UNUSED
;
2486 rtx r ATTRIBUTE_UNUSED
;
2488 mode
= TYPE_MODE (type
);
2489 /* Promote integer types. */
2490 if (INTEGRAL_TYPE_P (type
))
2491 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2493 /* Promotes small structs returned in a register to full-word size
2494 for big-endian AAPCS. */
2495 if (arm_return_in_msb (type
))
2497 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2498 if (size
% UNITS_PER_WORD
!= 0)
2500 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2501 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2505 return LIBCALL_VALUE(mode
);
2508 /* Determine the amount of memory needed to store the possible return
2509 registers of an untyped call. */
2511 arm_apply_result_size (void)
2517 if (TARGET_HARD_FLOAT_ABI
)
2521 if (TARGET_MAVERICK
)
2524 if (TARGET_IWMMXT_ABI
)
2531 /* Decide whether a type should be returned in memory (true)
2532 or in a register (false). This is called by the macro
2533 RETURN_IN_MEMORY. */
2535 arm_return_in_memory (tree type
)
2539 if (!AGGREGATE_TYPE_P (type
) &&
2540 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2541 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2542 /* All simple types are returned in registers.
2543 For AAPCS, complex types are treated the same as aggregates. */
2546 size
= int_size_in_bytes (type
);
2548 if (arm_abi
!= ARM_ABI_APCS
)
2550 /* ATPCS and later return aggregate types in memory only if they are
2551 larger than a word (or are variable size). */
2552 return (size
< 0 || size
> UNITS_PER_WORD
);
2555 /* To maximize backwards compatibility with previous versions of gcc,
2556 return vectors up to 4 words in registers. */
2557 if (TREE_CODE (type
) == VECTOR_TYPE
)
2558 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2560 /* For the arm-wince targets we choose to be compatible with Microsoft's
2561 ARM and Thumb compilers, which always return aggregates in memory. */
2563 /* All structures/unions bigger than one word are returned in memory.
2564 Also catch the case where int_size_in_bytes returns -1. In this case
2565 the aggregate is either huge or of variable size, and in either case
2566 we will want to return it via memory and not in a register. */
2567 if (size
< 0 || size
> UNITS_PER_WORD
)
2570 if (TREE_CODE (type
) == RECORD_TYPE
)
2574 /* For a struct the APCS says that we only return in a register
2575 if the type is 'integer like' and every addressable element
2576 has an offset of zero. For practical purposes this means
2577 that the structure can have at most one non bit-field element
2578 and that this element must be the first one in the structure. */
2580 /* Find the first field, ignoring non FIELD_DECL things which will
2581 have been created by C++. */
2582 for (field
= TYPE_FIELDS (type
);
2583 field
&& TREE_CODE (field
) != FIELD_DECL
;
2584 field
= TREE_CHAIN (field
))
2588 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2590 /* Check that the first field is valid for returning in a register. */
2592 /* ... Floats are not allowed */
2593 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2596 /* ... Aggregates that are not themselves valid for returning in
2597 a register are not allowed. */
2598 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2601 /* Now check the remaining fields, if any. Only bitfields are allowed,
2602 since they are not addressable. */
2603 for (field
= TREE_CHAIN (field
);
2605 field
= TREE_CHAIN (field
))
2607 if (TREE_CODE (field
) != FIELD_DECL
)
2610 if (!DECL_BIT_FIELD_TYPE (field
))
2617 if (TREE_CODE (type
) == UNION_TYPE
)
2621 /* Unions can be returned in registers if every element is
2622 integral, or can be returned in an integer register. */
2623 for (field
= TYPE_FIELDS (type
);
2625 field
= TREE_CHAIN (field
))
2627 if (TREE_CODE (field
) != FIELD_DECL
)
2630 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2633 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2639 #endif /* not ARM_WINCE */
2641 /* Return all other types in memory. */
2645 /* Indicate whether or not words of a double are in big-endian order. */
2648 arm_float_words_big_endian (void)
2650 if (TARGET_MAVERICK
)
2653 /* For FPA, float words are always big-endian. For VFP, floats words
2654 follow the memory system mode. */
2662 return (TARGET_BIG_END
? 1 : 0);
2667 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2668 for a call to a function whose data type is FNTYPE.
2669 For a library call, FNTYPE is NULL. */
2671 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2672 rtx libname ATTRIBUTE_UNUSED
,
2673 tree fndecl ATTRIBUTE_UNUSED
)
2675 /* On the ARM, the offset starts at 0. */
2677 pcum
->iwmmxt_nregs
= 0;
2678 pcum
->can_split
= true;
2680 pcum
->call_cookie
= CALL_NORMAL
;
2682 if (TARGET_LONG_CALLS
)
2683 pcum
->call_cookie
= CALL_LONG
;
2685 /* Check for long call/short call attributes. The attributes
2686 override any command line option. */
2689 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2690 pcum
->call_cookie
= CALL_SHORT
;
2691 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2692 pcum
->call_cookie
= CALL_LONG
;
2695 /* Varargs vectors are treated the same as long long.
2696 named_count avoids having to change the way arm handles 'named' */
2697 pcum
->named_count
= 0;
2700 if (TARGET_REALLY_IWMMXT
&& fntype
)
2704 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2706 fn_arg
= TREE_CHAIN (fn_arg
))
2707 pcum
->named_count
+= 1;
2709 if (! pcum
->named_count
)
2710 pcum
->named_count
= INT_MAX
;
2715 /* Return true if mode/type need doubleword alignment. */
2717 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2719 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2720 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2724 /* Determine where to put an argument to a function.
2725 Value is zero to push the argument on the stack,
2726 or a hard register in which to store the argument.
2728 MODE is the argument's machine mode.
2729 TYPE is the data type of the argument (as a tree).
2730 This is null for libcalls where that information may
2732 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2733 the preceding args and about the function being called.
2734 NAMED is nonzero if this argument is a named parameter
2735 (otherwise it is an extra parameter matching an ellipsis). */
2738 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2739 tree type
, int named
)
2743 /* Varargs vectors are treated the same as long long.
2744 named_count avoids having to change the way arm handles 'named' */
2745 if (TARGET_IWMMXT_ABI
2746 && arm_vector_mode_supported_p (mode
)
2747 && pcum
->named_count
> pcum
->nargs
+ 1)
2749 if (pcum
->iwmmxt_nregs
<= 9)
2750 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2753 pcum
->can_split
= false;
2758 /* Put doubleword aligned quantities in even register pairs. */
2760 && ARM_DOUBLEWORD_ALIGN
2761 && arm_needs_doubleword_align (mode
, type
))
2764 if (mode
== VOIDmode
)
2765 /* Compute operand 2 of the call insn. */
2766 return GEN_INT (pcum
->call_cookie
);
2768 /* Only allow splitting an arg between regs and memory if all preceding
2769 args were allocated to regs. For args passed by reference we only count
2770 the reference pointer. */
2771 if (pcum
->can_split
)
2774 nregs
= ARM_NUM_REGS2 (mode
, type
);
2776 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2779 return gen_rtx_REG (mode
, pcum
->nregs
);
2783 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2784 tree type
, bool named ATTRIBUTE_UNUSED
)
2786 int nregs
= pcum
->nregs
;
2788 if (arm_vector_mode_supported_p (mode
))
2791 if (NUM_ARG_REGS
> nregs
2792 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2794 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2799 /* Variable sized types are passed by reference. This is a GCC
2800 extension to the ARM ABI. */
2803 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2804 enum machine_mode mode ATTRIBUTE_UNUSED
,
2805 tree type
, bool named ATTRIBUTE_UNUSED
)
2807 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2810 /* Encode the current state of the #pragma [no_]long_calls. */
2813 OFF
, /* No #pragma [no_]long_calls is in effect. */
2814 LONG
, /* #pragma long_calls is in effect. */
2815 SHORT
/* #pragma no_long_calls is in effect. */
2818 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2821 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2823 arm_pragma_long_calls
= LONG
;
2827 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2829 arm_pragma_long_calls
= SHORT
;
2833 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2835 arm_pragma_long_calls
= OFF
;
2838 /* Table of machine attributes. */
2839 const struct attribute_spec arm_attribute_table
[] =
2841 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2842 /* Function calls made to this symbol must be done indirectly, because
2843 it may lie outside of the 26 bit addressing range of a normal function
2845 { "long_call", 0, 0, false, true, true, NULL
},
2846 /* Whereas these functions are always known to reside within the 26 bit
2847 addressing range. */
2848 { "short_call", 0, 0, false, true, true, NULL
},
2849 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2850 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2851 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2852 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2854 /* ARM/PE has three new attributes:
2856 dllexport - for exporting a function/variable that will live in a dll
2857 dllimport - for importing a function/variable from a dll
2859 Microsoft allows multiple declspecs in one __declspec, separating
2860 them with spaces. We do NOT support this. Instead, use __declspec
2863 { "dllimport", 0, 0, true, false, false, NULL
},
2864 { "dllexport", 0, 0, true, false, false, NULL
},
2865 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2866 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2867 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2868 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2869 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2871 { NULL
, 0, 0, false, false, false, NULL
}
2874 /* Handle an attribute requiring a FUNCTION_DECL;
2875 arguments as in struct attribute_spec.handler. */
2877 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2878 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2880 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2882 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2883 IDENTIFIER_POINTER (name
));
2884 *no_add_attrs
= true;
2890 /* Handle an "interrupt" or "isr" attribute;
2891 arguments as in struct attribute_spec.handler. */
2893 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2898 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2900 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2901 IDENTIFIER_POINTER (name
));
2902 *no_add_attrs
= true;
2904 /* FIXME: the argument if any is checked for type attributes;
2905 should it be checked for decl ones? */
2909 if (TREE_CODE (*node
) == FUNCTION_TYPE
2910 || TREE_CODE (*node
) == METHOD_TYPE
)
2912 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2914 warning (OPT_Wattributes
, "%qs attribute ignored",
2915 IDENTIFIER_POINTER (name
));
2916 *no_add_attrs
= true;
2919 else if (TREE_CODE (*node
) == POINTER_TYPE
2920 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2921 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2922 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2924 *node
= build_variant_type_copy (*node
);
2925 TREE_TYPE (*node
) = build_type_attribute_variant
2927 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2928 *no_add_attrs
= true;
2932 /* Possibly pass this attribute on from the type to a decl. */
2933 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2934 | (int) ATTR_FLAG_FUNCTION_NEXT
2935 | (int) ATTR_FLAG_ARRAY_NEXT
))
2937 *no_add_attrs
= true;
2938 return tree_cons (name
, args
, NULL_TREE
);
2942 warning (OPT_Wattributes
, "%qs attribute ignored",
2943 IDENTIFIER_POINTER (name
));
2951 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2952 /* Handle the "notshared" attribute. This attribute is another way of
2953 requesting hidden visibility. ARM's compiler supports
2954 "__declspec(notshared)"; we support the same thing via an
2958 arm_handle_notshared_attribute (tree
*node
,
2959 tree name ATTRIBUTE_UNUSED
,
2960 tree args ATTRIBUTE_UNUSED
,
2961 int flags ATTRIBUTE_UNUSED
,
2964 tree decl
= TYPE_NAME (*node
);
2968 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2969 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2970 *no_add_attrs
= false;
2976 /* Return 0 if the attributes for two types are incompatible, 1 if they
2977 are compatible, and 2 if they are nearly compatible (which causes a
2978 warning to be generated). */
2980 arm_comp_type_attributes (tree type1
, tree type2
)
2984 /* Check for mismatch of non-default calling convention. */
2985 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2988 /* Check for mismatched call attributes. */
2989 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2990 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2991 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2992 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2994 /* Only bother to check if an attribute is defined. */
2995 if (l1
| l2
| s1
| s2
)
2997 /* If one type has an attribute, the other must have the same attribute. */
2998 if ((l1
!= l2
) || (s1
!= s2
))
3001 /* Disallow mixed attributes. */
3002 if ((l1
& s2
) || (l2
& s1
))
3006 /* Check for mismatched ISR attribute. */
3007 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
3009 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
3010 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
3012 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
3019 /* Encode long_call or short_call attribute by prefixing
3020 symbol name in DECL with a special character FLAG. */
3022 arm_encode_call_attribute (tree decl
, int flag
)
3024 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
3025 int len
= strlen (str
);
3028 /* Do not allow weak functions to be treated as short call. */
3029 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
3032 newstr
= alloca (len
+ 2);
3034 strcpy (newstr
+ 1, str
);
3036 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
3037 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
3040 /* Assigns default attributes to newly defined type. This is used to
3041 set short_call/long_call attributes for function types of
3042 functions defined inside corresponding #pragma scopes. */
3044 arm_set_default_type_attributes (tree type
)
3046 /* Add __attribute__ ((long_call)) to all functions, when
3047 inside #pragma long_calls or __attribute__ ((short_call)),
3048 when inside #pragma no_long_calls. */
3049 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
3051 tree type_attr_list
, attr_name
;
3052 type_attr_list
= TYPE_ATTRIBUTES (type
);
3054 if (arm_pragma_long_calls
== LONG
)
3055 attr_name
= get_identifier ("long_call");
3056 else if (arm_pragma_long_calls
== SHORT
)
3057 attr_name
= get_identifier ("short_call");
3061 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
3062 TYPE_ATTRIBUTES (type
) = type_attr_list
;
3066 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3067 defined within the current compilation unit. If this cannot be
3068 determined, then 0 is returned. */
3070 current_file_function_operand (rtx sym_ref
)
3072 /* This is a bit of a fib. A function will have a short call flag
3073 applied to its name if it has the short call attribute, or it has
3074 already been defined within the current compilation unit. */
3075 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
3078 /* The current function is always defined within the current compilation
3079 unit. If it s a weak definition however, then this may not be the real
3080 definition of the function, and so we have to say no. */
3081 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
3082 && !DECL_WEAK (current_function_decl
))
3085 /* We cannot make the determination - default to returning 0. */
3089 /* Return nonzero if a 32 bit "long_call" should be generated for
3090 this call. We generate a long_call if the function:
3092 a. has an __attribute__((long call))
3093 or b. is within the scope of a #pragma long_calls
3094 or c. the -mlong-calls command line switch has been specified
3096 1. -ffunction-sections is in effect
3097 or 2. the current function has __attribute__ ((section))
3098 or 3. the target function has __attribute__ ((section))
3100 However we do not generate a long call if the function:
3102 d. has an __attribute__ ((short_call))
3103 or e. is inside the scope of a #pragma no_long_calls
3104 or f. is defined within the current compilation unit.
3106 This function will be called by C fragments contained in the machine
3107 description file. SYM_REF and CALL_COOKIE correspond to the matched
3108 rtl operands. CALL_SYMBOL is used to distinguish between
3109 two different callers of the function. It is set to 1 in the
3110 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3111 and "call_value" patterns. This is because of the difference in the
3112 SYM_REFs passed by these patterns. */
3114 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3118 if (GET_CODE (sym_ref
) != MEM
)
3121 sym_ref
= XEXP (sym_ref
, 0);
3124 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3127 if (call_cookie
& CALL_SHORT
)
3130 if (TARGET_LONG_CALLS
)
3132 if (flag_function_sections
3133 || DECL_SECTION_NAME (current_function_decl
))
3134 /* c.3 is handled by the definition of the
3135 ARM_DECLARE_FUNCTION_SIZE macro. */
3139 if (current_file_function_operand (sym_ref
))
3142 return (call_cookie
& CALL_LONG
)
3143 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3144 || TARGET_LONG_CALLS
;
3147 /* Return nonzero if it is ok to make a tail-call to DECL. */
3149 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3151 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3153 if (cfun
->machine
->sibcall_blocked
)
3156 /* Never tailcall something for which we have no decl, or if we
3157 are in Thumb mode. */
3158 if (decl
== NULL
|| TARGET_THUMB
)
3161 /* Get the calling method. */
3162 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3163 call_type
= CALL_SHORT
;
3164 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3165 call_type
= CALL_LONG
;
3167 /* Cannot tail-call to long calls, since these are out of range of
3168 a branch instruction. However, if not compiling PIC, we know
3169 we can reach the symbol if it is in this compilation unit. */
3170 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3173 /* If we are interworking and the function is not declared static
3174 then we can't tail-call it unless we know that it exists in this
3175 compilation unit (since it might be a Thumb routine). */
3176 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3179 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3180 if (IS_INTERRUPT (arm_current_func_type ()))
3183 /* Everything else is ok. */
3188 /* Addressing mode support functions. */
3190 /* Return nonzero if X is a legitimate immediate operand when compiling
3191 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3193 legitimate_pic_operand_p (rtx x
)
3195 if (GET_CODE (x
) == SYMBOL_REF
3196 || (GET_CODE (x
) == CONST
3197 && GET_CODE (XEXP (x
, 0)) == PLUS
3198 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
3205 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3207 if (GET_CODE (orig
) == SYMBOL_REF
3208 || GET_CODE (orig
) == LABEL_REF
)
3210 #ifndef AOF_ASSEMBLER
3211 rtx pic_ref
, address
;
3216 /* If this function doesn't have a pic register, create one now.
3217 A lot of the logic here is made obscure by the fact that this
3218 routine gets called as part of the rtx cost estimation
3219 process. We don't want those calls to affect any assumptions
3220 about the real function; and further, we can't call
3221 entry_of_function() until we start the real expansion
3223 if (!current_function_uses_pic_offset_table
)
3225 gcc_assert (!no_new_pseudos
);
3226 if (arm_pic_register
!= INVALID_REGNUM
)
3228 cfun
->machine
->pic_reg
= gen_rtx_REG (Pmode
, arm_pic_register
);
3230 /* Play games to avoid marking the function as needing pic
3231 if we are being called as part of the cost-estimation
3233 if (current_ir_type () != IR_GIMPLE
)
3234 current_function_uses_pic_offset_table
= 1;
3240 cfun
->machine
->pic_reg
= gen_reg_rtx (Pmode
);
3242 /* Play games to avoid marking the function as needing pic
3243 if we are being called as part of the cost-estimation
3245 if (current_ir_type () != IR_GIMPLE
)
3247 current_function_uses_pic_offset_table
= 1;
3250 arm_load_pic_register (0UL);
3254 emit_insn_after (seq
, entry_of_function ());
3261 gcc_assert (!no_new_pseudos
);
3262 reg
= gen_reg_rtx (Pmode
);
3267 #ifdef AOF_ASSEMBLER
3268 /* The AOF assembler can generate relocations for these directly, and
3269 understands that the PIC register has to be added into the offset. */
3270 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3273 address
= gen_reg_rtx (Pmode
);
3278 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3280 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3282 if ((GET_CODE (orig
) == LABEL_REF
3283 || (GET_CODE (orig
) == SYMBOL_REF
&&
3284 SYMBOL_REF_LOCAL_P (orig
)))
3286 pic_ref
= gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
, address
);
3289 pic_ref
= gen_const_mem (Pmode
,
3290 gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
,
3294 insn
= emit_move_insn (reg
, pic_ref
);
3296 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3298 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3302 else if (GET_CODE (orig
) == CONST
)
3306 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3307 && XEXP (XEXP (orig
, 0), 0) == cfun
->machine
->pic_reg
)
3310 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
3311 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
3316 gcc_assert (!no_new_pseudos
);
3317 reg
= gen_reg_rtx (Pmode
);
3320 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3322 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3323 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3324 base
== reg
? 0 : reg
);
3326 if (GET_CODE (offset
) == CONST_INT
)
3328 /* The base register doesn't really matter, we only want to
3329 test the index for the appropriate mode. */
3330 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3332 gcc_assert (!no_new_pseudos
);
3333 offset
= force_reg (Pmode
, offset
);
3336 if (GET_CODE (offset
) == CONST_INT
)
3337 return plus_constant (base
, INTVAL (offset
));
3340 if (GET_MODE_SIZE (mode
) > 4
3341 && (GET_MODE_CLASS (mode
) == MODE_INT
3342 || TARGET_SOFT_FLOAT
))
3344 emit_insn (gen_addsi3 (reg
, base
, offset
));
3348 return gen_rtx_PLUS (Pmode
, base
, offset
);
3355 /* Find a spare low register to use during the prolog of a function. */
3358 thumb_find_work_register (unsigned long pushed_regs_mask
)
3362 /* Check the argument registers first as these are call-used. The
3363 register allocation order means that sometimes r3 might be used
3364 but earlier argument registers might not, so check them all. */
3365 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3366 if (!regs_ever_live
[reg
])
3369 /* Before going on to check the call-saved registers we can try a couple
3370 more ways of deducing that r3 is available. The first is when we are
3371 pushing anonymous arguments onto the stack and we have less than 4
3372 registers worth of fixed arguments(*). In this case r3 will be part of
3373 the variable argument list and so we can be sure that it will be
3374 pushed right at the start of the function. Hence it will be available
3375 for the rest of the prologue.
3376 (*): ie current_function_pretend_args_size is greater than 0. */
3377 if (cfun
->machine
->uses_anonymous_args
3378 && current_function_pretend_args_size
> 0)
3379 return LAST_ARG_REGNUM
;
3381 /* The other case is when we have fixed arguments but less than 4 registers
3382 worth. In this case r3 might be used in the body of the function, but
3383 it is not being used to convey an argument into the function. In theory
3384 we could just check current_function_args_size to see how many bytes are
3385 being passed in argument registers, but it seems that it is unreliable.
3386 Sometimes it will have the value 0 when in fact arguments are being
3387 passed. (See testcase execute/20021111-1.c for an example). So we also
3388 check the args_info.nregs field as well. The problem with this field is
3389 that it makes no allowances for arguments that are passed to the
3390 function but which are not used. Hence we could miss an opportunity
3391 when a function has an unused argument in r3. But it is better to be
3392 safe than to be sorry. */
3393 if (! cfun
->machine
->uses_anonymous_args
3394 && current_function_args_size
>= 0
3395 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3396 && cfun
->args_info
.nregs
< 4)
3397 return LAST_ARG_REGNUM
;
3399 /* Otherwise look for a call-saved register that is going to be pushed. */
3400 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3401 if (pushed_regs_mask
& (1 << reg
))
3404 /* Something went wrong - thumb_compute_save_reg_mask()
3405 should have arranged for a suitable register to be pushed. */
3409 static GTY(()) int pic_labelno
;
3411 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3415 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3417 #ifndef AOF_ASSEMBLER
3418 rtx l1
, labelno
, pic_tmp
, pic_tmp2
, pic_rtx
;
3419 rtx global_offset_table
;
3421 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3424 gcc_assert (flag_pic
);
3426 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3427 in the code stream. */
3429 labelno
= GEN_INT (pic_labelno
++);
3430 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3431 l1
= gen_rtx_CONST (VOIDmode
, l1
);
3433 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3434 /* On the ARM the PC register contains 'dot + 8' at the time of the
3435 addition, on the Thumb it is 'dot + 4'. */
3436 pic_tmp
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
3438 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3439 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3441 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3443 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3447 emit_insn (gen_pic_load_addr_arm (cfun
->machine
->pic_reg
, pic_rtx
));
3448 emit_insn (gen_pic_add_dot_plus_eight (cfun
->machine
->pic_reg
,
3449 cfun
->machine
->pic_reg
, labelno
));
3453 if (arm_pic_register
!= INVALID_REGNUM
3454 && REGNO (cfun
->machine
->pic_reg
) > LAST_LO_REGNUM
)
3456 /* We will have pushed the pic register, so we should always be
3457 able to find a work register. */
3458 pic_tmp
= gen_rtx_REG (SImode
,
3459 thumb_find_work_register (saved_regs
));
3460 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3461 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3464 emit_insn (gen_pic_load_addr_thumb (cfun
->machine
->pic_reg
, pic_rtx
));
3465 emit_insn (gen_pic_add_dot_plus_four (cfun
->machine
->pic_reg
,
3466 cfun
->machine
->pic_reg
, labelno
));
3469 /* Need to emit this whether or not we obey regdecls,
3470 since setjmp/longjmp can cause life info to screw up. */
3471 emit_insn (gen_rtx_USE (VOIDmode
, cfun
->machine
->pic_reg
));
3472 #endif /* AOF_ASSEMBLER */
3476 /* Return nonzero if X is valid as an ARM state addressing register. */
3478 arm_address_register_rtx_p (rtx x
, int strict_p
)
3482 if (GET_CODE (x
) != REG
)
3488 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3490 return (regno
<= LAST_ARM_REGNUM
3491 || regno
>= FIRST_PSEUDO_REGISTER
3492 || regno
== FRAME_POINTER_REGNUM
3493 || regno
== ARG_POINTER_REGNUM
);
3496 /* Return TRUE if this rtx is the difference of a symbol and a label,
3497 and will reduce to a PC-relative relocation in the object file.
3498 Expressions like this can be left alone when generating PIC, rather
3499 than forced through the GOT. */
3501 pcrel_constant_p (rtx x
)
3503 if (GET_CODE (x
) == MINUS
)
3504 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
3509 /* Return nonzero if X is a valid ARM state address operand. */
3511 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3515 enum rtx_code code
= GET_CODE (x
);
3517 if (arm_address_register_rtx_p (x
, strict_p
))
3520 use_ldrd
= (TARGET_LDRD
3522 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3524 if (code
== POST_INC
|| code
== PRE_DEC
3525 || ((code
== PRE_INC
|| code
== POST_DEC
)
3526 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3527 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3529 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3530 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3531 && GET_CODE (XEXP (x
, 1)) == PLUS
3532 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3534 rtx addend
= XEXP (XEXP (x
, 1), 1);
3536 /* Don't allow ldrd post increment by register because it's hard
3537 to fixup invalid register choices. */
3539 && GET_CODE (x
) == POST_MODIFY
3540 && GET_CODE (addend
) == REG
)
3543 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3544 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3547 /* After reload constants split into minipools will have addresses
3548 from a LABEL_REF. */
3549 else if (reload_completed
3550 && (code
== LABEL_REF
3552 && GET_CODE (XEXP (x
, 0)) == PLUS
3553 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3554 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3557 else if (mode
== TImode
)
3560 else if (code
== PLUS
)
3562 rtx xop0
= XEXP (x
, 0);
3563 rtx xop1
= XEXP (x
, 1);
3565 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3566 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3567 || (arm_address_register_rtx_p (xop1
, strict_p
)
3568 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3572 /* Reload currently can't handle MINUS, so disable this for now */
3573 else if (GET_CODE (x
) == MINUS
)
3575 rtx xop0
= XEXP (x
, 0);
3576 rtx xop1
= XEXP (x
, 1);
3578 return (arm_address_register_rtx_p (xop0
, strict_p
)
3579 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3583 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3584 && code
== SYMBOL_REF
3585 && CONSTANT_POOL_ADDRESS_P (x
)
3587 && symbol_mentioned_p (get_pool_constant (x
))
3588 && ! pcrel_constant_p (get_pool_constant (x
))))
3594 /* Return nonzero if INDEX is valid for an address index operand in
3597 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3600 HOST_WIDE_INT range
;
3601 enum rtx_code code
= GET_CODE (index
);
3603 /* Standard coprocessor addressing modes. */
3604 if (TARGET_HARD_FLOAT
3605 && (TARGET_FPA
|| TARGET_MAVERICK
)
3606 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3607 || (TARGET_MAVERICK
&& mode
== DImode
)))
3608 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3609 && INTVAL (index
) > -1024
3610 && (INTVAL (index
) & 3) == 0);
3612 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3613 return (code
== CONST_INT
3614 && INTVAL (index
) < 1024
3615 && INTVAL (index
) > -1024
3616 && (INTVAL (index
) & 3) == 0);
3618 if (arm_address_register_rtx_p (index
, strict_p
)
3619 && (GET_MODE_SIZE (mode
) <= 4))
3622 if (mode
== DImode
|| mode
== DFmode
)
3624 if (code
== CONST_INT
)
3626 HOST_WIDE_INT val
= INTVAL (index
);
3629 return val
> -256 && val
< 256;
3631 return val
> -4096 && val
< 4092;
3634 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3637 if (GET_MODE_SIZE (mode
) <= 4
3640 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3644 rtx xiop0
= XEXP (index
, 0);
3645 rtx xiop1
= XEXP (index
, 1);
3647 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3648 && power_of_two_operand (xiop1
, SImode
))
3649 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3650 && power_of_two_operand (xiop0
, SImode
)));
3652 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3653 || code
== ASHIFT
|| code
== ROTATERT
)
3655 rtx op
= XEXP (index
, 1);
3657 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3658 && GET_CODE (op
) == CONST_INT
3660 && INTVAL (op
) <= 31);
3664 /* For ARM v4 we may be doing a sign-extend operation during the
3668 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3674 range
= (mode
== HImode
) ? 4095 : 4096;
3676 return (code
== CONST_INT
3677 && INTVAL (index
) < range
3678 && INTVAL (index
) > -range
);
3681 /* Return nonzero if X is valid as a Thumb state base register. */
3683 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3687 if (GET_CODE (x
) != REG
)
3693 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3695 return (regno
<= LAST_LO_REGNUM
3696 || regno
> LAST_VIRTUAL_REGISTER
3697 || regno
== FRAME_POINTER_REGNUM
3698 || (GET_MODE_SIZE (mode
) >= 4
3699 && (regno
== STACK_POINTER_REGNUM
3700 || regno
>= FIRST_PSEUDO_REGISTER
3701 || x
== hard_frame_pointer_rtx
3702 || x
== arg_pointer_rtx
)));
3705 /* Return nonzero if x is a legitimate index register. This is the case
3706 for any base register that can access a QImode object. */
3708 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3710 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3713 /* Return nonzero if x is a legitimate Thumb-state address.
3715 The AP may be eliminated to either the SP or the FP, so we use the
3716 least common denominator, e.g. SImode, and offsets from 0 to 64.
3718 ??? Verify whether the above is the right approach.
3720 ??? Also, the FP may be eliminated to the SP, so perhaps that
3721 needs special handling also.
3723 ??? Look at how the mips16 port solves this problem. It probably uses
3724 better ways to solve some of these problems.
3726 Although it is not incorrect, we don't accept QImode and HImode
3727 addresses based on the frame pointer or arg pointer until the
3728 reload pass starts. This is so that eliminating such addresses
3729 into stack based ones won't produce impossible code. */
3731 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3733 /* ??? Not clear if this is right. Experiment. */
3734 if (GET_MODE_SIZE (mode
) < 4
3735 && !(reload_in_progress
|| reload_completed
)
3736 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3737 || reg_mentioned_p (arg_pointer_rtx
, x
)
3738 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3739 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3740 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3741 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3744 /* Accept any base register. SP only in SImode or larger. */
3745 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3748 /* This is PC relative data before arm_reorg runs. */
3749 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3750 && GET_CODE (x
) == SYMBOL_REF
3751 && CONSTANT_POOL_ADDRESS_P (x
) && !flag_pic
)
3754 /* This is PC relative data after arm_reorg runs. */
3755 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3756 && (GET_CODE (x
) == LABEL_REF
3757 || (GET_CODE (x
) == CONST
3758 && GET_CODE (XEXP (x
, 0)) == PLUS
3759 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3760 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3763 /* Post-inc indexing only supported for SImode and larger. */
3764 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3765 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3768 else if (GET_CODE (x
) == PLUS
)
3770 /* REG+REG address can be any two index registers. */
3771 /* We disallow FRAME+REG addressing since we know that FRAME
3772 will be replaced with STACK, and SP relative addressing only
3773 permits SP+OFFSET. */
3774 if (GET_MODE_SIZE (mode
) <= 4
3775 && XEXP (x
, 0) != frame_pointer_rtx
3776 && XEXP (x
, 1) != frame_pointer_rtx
3777 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3778 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3781 /* REG+const has 5-7 bit offset for non-SP registers. */
3782 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3783 || XEXP (x
, 0) == arg_pointer_rtx
)
3784 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3785 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3788 /* REG+const has 10 bit offset for SP, but only SImode and
3789 larger is supported. */
3790 /* ??? Should probably check for DI/DFmode overflow here
3791 just like GO_IF_LEGITIMATE_OFFSET does. */
3792 else if (GET_CODE (XEXP (x
, 0)) == REG
3793 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3794 && GET_MODE_SIZE (mode
) >= 4
3795 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3796 && INTVAL (XEXP (x
, 1)) >= 0
3797 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3798 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3801 else if (GET_CODE (XEXP (x
, 0)) == REG
3802 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3803 && GET_MODE_SIZE (mode
) >= 4
3804 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3805 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3809 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3810 && GET_MODE_SIZE (mode
) == 4
3811 && GET_CODE (x
) == SYMBOL_REF
3812 && CONSTANT_POOL_ADDRESS_P (x
)
3814 && symbol_mentioned_p (get_pool_constant (x
))
3815 && ! pcrel_constant_p (get_pool_constant (x
))))
3821 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3822 instruction of mode MODE. */
3824 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3826 switch (GET_MODE_SIZE (mode
))
3829 return val
>= 0 && val
< 32;
3832 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3836 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3841 /* Build the SYMBOL_REF for __tls_get_addr. */
3843 static GTY(()) rtx tls_get_addr_libfunc
;
3846 get_tls_get_addr (void)
3848 if (!tls_get_addr_libfunc
)
3849 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
3850 return tls_get_addr_libfunc
;
3854 arm_load_tp (rtx target
)
3857 target
= gen_reg_rtx (SImode
);
3861 /* Can return in any reg. */
3862 emit_insn (gen_load_tp_hard (target
));
3866 /* Always returned in r0. Immediately copy the result into a pseudo,
3867 otherwise other uses of r0 (e.g. setting up function arguments) may
3868 clobber the value. */
3872 emit_insn (gen_load_tp_soft ());
3874 tmp
= gen_rtx_REG (SImode
, 0);
3875 emit_move_insn (target
, tmp
);
3881 load_tls_operand (rtx x
, rtx reg
)
3885 if (reg
== NULL_RTX
)
3886 reg
= gen_reg_rtx (SImode
);
3888 tmp
= gen_rtx_CONST (SImode
, x
);
3890 emit_move_insn (reg
, tmp
);
3896 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
3898 rtx insns
, label
, labelno
, sum
;
3902 labelno
= GEN_INT (pic_labelno
++);
3903 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3904 label
= gen_rtx_CONST (VOIDmode
, label
);
3906 sum
= gen_rtx_UNSPEC (Pmode
,
3907 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
3908 GEN_INT (TARGET_ARM
? 8 : 4)),
3910 reg
= load_tls_operand (sum
, reg
);
3913 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
3915 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3917 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
3918 Pmode
, 1, reg
, Pmode
);
3920 insns
= get_insns ();
3927 legitimize_tls_address (rtx x
, rtx reg
)
3929 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
3930 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
3934 case TLS_MODEL_GLOBAL_DYNAMIC
:
3935 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
3936 dest
= gen_reg_rtx (Pmode
);
3937 emit_libcall_block (insns
, dest
, ret
, x
);
3940 case TLS_MODEL_LOCAL_DYNAMIC
:
3941 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
3943 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3944 share the LDM result with other LD model accesses. */
3945 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
3947 dest
= gen_reg_rtx (Pmode
);
3948 emit_libcall_block (insns
, dest
, ret
, eqv
);
3950 /* Load the addend. */
3951 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
3953 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
3954 return gen_rtx_PLUS (Pmode
, dest
, addend
);
3956 case TLS_MODEL_INITIAL_EXEC
:
3957 labelno
= GEN_INT (pic_labelno
++);
3958 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3959 label
= gen_rtx_CONST (VOIDmode
, label
);
3960 sum
= gen_rtx_UNSPEC (Pmode
,
3961 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
3962 GEN_INT (TARGET_ARM
? 8 : 4)),
3964 reg
= load_tls_operand (sum
, reg
);
3967 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
3970 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3971 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
3974 tp
= arm_load_tp (NULL_RTX
);
3976 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3978 case TLS_MODEL_LOCAL_EXEC
:
3979 tp
= arm_load_tp (NULL_RTX
);
3981 reg
= gen_rtx_UNSPEC (Pmode
,
3982 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
3984 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
3986 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3993 /* Try machine-dependent ways of modifying an illegitimate address
3994 to be legitimate. If we find one, return the new, valid address. */
3996 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3998 if (arm_tls_symbol_p (x
))
3999 return legitimize_tls_address (x
, NULL_RTX
);
4001 if (GET_CODE (x
) == PLUS
)
4003 rtx xop0
= XEXP (x
, 0);
4004 rtx xop1
= XEXP (x
, 1);
4006 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
4007 xop0
= force_reg (SImode
, xop0
);
4009 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
4010 xop1
= force_reg (SImode
, xop1
);
4012 if (ARM_BASE_REGISTER_RTX_P (xop0
)
4013 && GET_CODE (xop1
) == CONST_INT
)
4015 HOST_WIDE_INT n
, low_n
;
4019 /* VFP addressing modes actually allow greater offsets, but for
4020 now we just stick with the lowest common denominator. */
4022 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
4034 low_n
= ((mode
) == TImode
? 0
4035 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
4039 base_reg
= gen_reg_rtx (SImode
);
4040 val
= force_operand (plus_constant (xop0
, n
), NULL_RTX
);
4041 emit_move_insn (base_reg
, val
);
4042 x
= plus_constant (base_reg
, low_n
);
4044 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4045 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4048 /* XXX We don't allow MINUS any more -- see comment in
4049 arm_legitimate_address_p (). */
4050 else if (GET_CODE (x
) == MINUS
)
4052 rtx xop0
= XEXP (x
, 0);
4053 rtx xop1
= XEXP (x
, 1);
4055 if (CONSTANT_P (xop0
))
4056 xop0
= force_reg (SImode
, xop0
);
4058 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
4059 xop1
= force_reg (SImode
, xop1
);
4061 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4062 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
4065 /* Make sure to take full advantage of the pre-indexed addressing mode
4066 with absolute addresses which often allows for the base register to
4067 be factorized for multiple adjacent memory references, and it might
4068 even allows for the mini pool to be avoided entirely. */
4069 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
4072 HOST_WIDE_INT mask
, base
, index
;
4075 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4076 use a 8 bit index. So let's use a 12 bit index for SImode only and
4077 hope that arm_gen_constant will enable ldrb to use more bits. */
4078 bits
= (mode
== SImode
) ? 12 : 8;
4079 mask
= (1 << bits
) - 1;
4080 base
= INTVAL (x
) & ~mask
;
4081 index
= INTVAL (x
) & mask
;
4082 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
4084 /* It'll most probably be more efficient to generate the base
4085 with more bits set and use a negative index instead. */
4089 base_reg
= force_reg (SImode
, GEN_INT (base
));
4090 x
= plus_constant (base_reg
, index
);
4095 /* We need to find and carefully transform any SYMBOL and LABEL
4096 references; so go back to the original address expression. */
4097 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4099 if (new_x
!= orig_x
)
4107 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4108 to be legitimate. If we find one, return the new, valid address. */
4110 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4112 if (arm_tls_symbol_p (x
))
4113 return legitimize_tls_address (x
, NULL_RTX
);
4115 if (GET_CODE (x
) == PLUS
4116 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4117 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
4118 || INTVAL (XEXP (x
, 1)) < 0))
4120 rtx xop0
= XEXP (x
, 0);
4121 rtx xop1
= XEXP (x
, 1);
4122 HOST_WIDE_INT offset
= INTVAL (xop1
);
4124 /* Try and fold the offset into a biasing of the base register and
4125 then offsetting that. Don't do this when optimizing for space
4126 since it can cause too many CSEs. */
4127 if (optimize_size
&& offset
>= 0
4128 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
4130 HOST_WIDE_INT delta
;
4133 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
4134 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
4135 delta
= 31 * GET_MODE_SIZE (mode
);
4137 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
4139 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
4141 x
= plus_constant (xop0
, delta
);
4143 else if (offset
< 0 && offset
> -256)
4144 /* Small negative offsets are best done with a subtract before the
4145 dereference, forcing these into a register normally takes two
4147 x
= force_operand (x
, NULL_RTX
);
4150 /* For the remaining cases, force the constant into a register. */
4151 xop1
= force_reg (SImode
, xop1
);
4152 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4155 else if (GET_CODE (x
) == PLUS
4156 && s_register_operand (XEXP (x
, 1), SImode
)
4157 && !s_register_operand (XEXP (x
, 0), SImode
))
4159 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
4161 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
4166 /* We need to find and carefully transform any SYMBOL and LABEL
4167 references; so go back to the original address expression. */
4168 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4170 if (new_x
!= orig_x
)
4178 thumb_legitimize_reload_address (rtx
*x_p
,
4179 enum machine_mode mode
,
4180 int opnum
, int type
,
4181 int ind_levels ATTRIBUTE_UNUSED
)
4185 if (GET_CODE (x
) == PLUS
4186 && GET_MODE_SIZE (mode
) < 4
4187 && REG_P (XEXP (x
, 0))
4188 && XEXP (x
, 0) == stack_pointer_rtx
4189 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4190 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4195 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4196 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4200 /* If both registers are hi-regs, then it's better to reload the
4201 entire expression rather than each register individually. That
4202 only requires one reload register rather than two. */
4203 if (GET_CODE (x
) == PLUS
4204 && REG_P (XEXP (x
, 0))
4205 && REG_P (XEXP (x
, 1))
4206 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
4207 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
4212 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4213 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4220 /* Test for various thread-local symbols. */
4222 /* Return TRUE if X is a thread-local symbol. */
4225 arm_tls_symbol_p (rtx x
)
4227 if (! TARGET_HAVE_TLS
)
4230 if (GET_CODE (x
) != SYMBOL_REF
)
4233 return SYMBOL_REF_TLS_MODEL (x
) != 0;
4236 /* Helper for arm_tls_referenced_p. */
4239 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4241 if (GET_CODE (*x
) == SYMBOL_REF
)
4242 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
4244 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4245 TLS offsets, not real symbol references. */
4246 if (GET_CODE (*x
) == UNSPEC
4247 && XINT (*x
, 1) == UNSPEC_TLS
)
4253 /* Return TRUE if X contains any TLS symbol references. */
4256 arm_tls_referenced_p (rtx x
)
4258 if (! TARGET_HAVE_TLS
)
4261 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
4264 #define REG_OR_SUBREG_REG(X) \
4265 (GET_CODE (X) == REG \
4266 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4268 #define REG_OR_SUBREG_RTX(X) \
4269 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4271 #ifndef COSTS_N_INSNS
4272 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4275 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4277 enum machine_mode mode
= GET_MODE (x
);
4290 return COSTS_N_INSNS (1);
4293 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4296 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
4303 return COSTS_N_INSNS (2) + cycles
;
4305 return COSTS_N_INSNS (1) + 16;
4308 return (COSTS_N_INSNS (1)
4309 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
4310 + GET_CODE (SET_DEST (x
)) == MEM
));
4315 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
4317 if (thumb_shiftable_const (INTVAL (x
)))
4318 return COSTS_N_INSNS (2);
4319 return COSTS_N_INSNS (3);
4321 else if ((outer
== PLUS
|| outer
== COMPARE
)
4322 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
4324 else if (outer
== AND
4325 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
4326 return COSTS_N_INSNS (1);
4327 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
4328 || outer
== LSHIFTRT
)
4330 return COSTS_N_INSNS (2);
4336 return COSTS_N_INSNS (3);
4354 /* XXX another guess. */
4355 /* Memory costs quite a lot for the first word, but subsequent words
4356 load at the equivalent of a single insn each. */
4357 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4358 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4363 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4368 /* XXX still guessing. */
4369 switch (GET_MODE (XEXP (x
, 0)))
4372 return (1 + (mode
== DImode
? 4 : 0)
4373 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4376 return (4 + (mode
== DImode
? 4 : 0)
4377 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4380 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4392 /* Worker routine for arm_rtx_costs. */
4394 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4396 enum machine_mode mode
= GET_MODE (x
);
4397 enum rtx_code subcode
;
4403 /* Memory costs quite a lot for the first word, but subsequent words
4404 load at the equivalent of a single insn each. */
4405 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4406 + (GET_CODE (x
) == SYMBOL_REF
4407 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4413 return optimize_size
? COSTS_N_INSNS (2) : 100;
4416 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4423 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4425 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4426 + ((GET_CODE (XEXP (x
, 0)) == REG
4427 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4428 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4430 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4431 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4432 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4434 + ((GET_CODE (XEXP (x
, 1)) == REG
4435 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4436 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4437 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4442 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4443 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4444 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4445 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4448 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4449 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4450 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4451 && arm_const_double_rtx (XEXP (x
, 1))))
4453 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4454 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4455 && arm_const_double_rtx (XEXP (x
, 0))))
4458 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4459 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4460 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4461 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4462 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4463 || subcode
== ROTATE
|| subcode
== ROTATERT
4465 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4466 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4467 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4468 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4469 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4470 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4471 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4476 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4478 extra_cost
= rtx_cost (XEXP (x
, 0), code
);
4479 if (!REG_OR_SUBREG_REG (XEXP (x
, 1)))
4480 extra_cost
+= 4 * ARM_NUM_REGS (mode
);
4484 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4485 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4486 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4487 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4488 && arm_const_double_rtx (XEXP (x
, 1))))
4492 case AND
: case XOR
: case IOR
:
4495 /* Normally the frame registers will be spilt into reg+const during
4496 reload, so it is a bad idea to combine them with other instructions,
4497 since then they might not be moved outside of loops. As a compromise
4498 we allow integration with ops that have a constant as their second
4500 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4501 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4502 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4503 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4504 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4508 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4509 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4510 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4511 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4514 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4515 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4516 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4517 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4518 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4521 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4522 return (1 + extra_cost
4523 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4524 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4525 || subcode
== ROTATE
|| subcode
== ROTATERT
4527 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4528 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4529 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4530 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4531 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4532 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4538 /* This should have been handled by the CPU specific routines. */
4542 if (arm_arch3m
&& mode
== SImode
4543 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4544 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4545 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4546 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4547 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4548 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4553 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4554 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4558 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4560 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4563 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4571 return 4 + (mode
== DImode
? 4 : 0);
4574 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4575 return (4 + (mode
== DImode
? 4 : 0)
4576 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4579 switch (GET_MODE (XEXP (x
, 0)))
4582 return (1 + (mode
== DImode
? 4 : 0)
4583 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4586 return (4 + (mode
== DImode
? 4 : 0)
4587 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4590 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4605 if (const_ok_for_arm (INTVAL (x
)))
4606 return outer
== SET
? 2 : -1;
4607 else if (outer
== AND
4608 && const_ok_for_arm (~INTVAL (x
)))
4610 else if ((outer
== COMPARE
4611 || outer
== PLUS
|| outer
== MINUS
)
4612 && const_ok_for_arm (-INTVAL (x
)))
4623 if (arm_const_double_rtx (x
))
4624 return outer
== SET
? 2 : -1;
4625 else if ((outer
== COMPARE
|| outer
== PLUS
)
4626 && neg_const_double_rtx_ok_for_fpa (x
))
4635 /* RTX costs when optimizing for size. */
4637 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4639 enum machine_mode mode
= GET_MODE (x
);
4643 /* XXX TBD. For now, use the standard costs. */
4644 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4651 /* A memory access costs 1 insn if the mode is small, or the address is
4652 a single register, otherwise it costs one insn per word. */
4653 if (REG_P (XEXP (x
, 0)))
4654 *total
= COSTS_N_INSNS (1);
4656 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4663 /* Needs a libcall, so it costs about this. */
4664 *total
= COSTS_N_INSNS (2);
4668 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4670 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4678 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4680 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4683 else if (mode
== SImode
)
4685 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4686 /* Slightly disparage register shifts, but not by much. */
4687 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4688 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4692 /* Needs a libcall. */
4693 *total
= COSTS_N_INSNS (2);
4697 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4699 *total
= COSTS_N_INSNS (1);
4705 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4706 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4708 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4709 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4710 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4711 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4712 || subcode1
== ASHIFTRT
)
4714 /* It's just the cost of the two operands. */
4719 *total
= COSTS_N_INSNS (1);
4723 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4727 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4729 *total
= COSTS_N_INSNS (1);
4734 case AND
: case XOR
: case IOR
:
4737 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4739 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4740 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4741 || (code
== AND
&& subcode
== NOT
))
4743 /* It's just the cost of the two operands. */
4749 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4753 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4757 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4758 *total
= COSTS_N_INSNS (1);
4761 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4770 if (cc_register (XEXP (x
, 0), VOIDmode
))
4773 *total
= COSTS_N_INSNS (1);
4777 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4778 *total
= COSTS_N_INSNS (1);
4780 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4785 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4787 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4788 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4791 *total
+= COSTS_N_INSNS (1);
4796 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4798 switch (GET_MODE (XEXP (x
, 0)))
4801 *total
+= COSTS_N_INSNS (1);
4805 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4811 *total
+= COSTS_N_INSNS (2);
4816 *total
+= COSTS_N_INSNS (1);
4821 if (const_ok_for_arm (INTVAL (x
)))
4822 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4823 else if (const_ok_for_arm (~INTVAL (x
)))
4824 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4825 else if (const_ok_for_arm (-INTVAL (x
)))
4827 if (outer_code
== COMPARE
|| outer_code
== PLUS
4828 || outer_code
== MINUS
)
4831 *total
= COSTS_N_INSNS (1);
4834 *total
= COSTS_N_INSNS (2);
4840 *total
= COSTS_N_INSNS (2);
4844 *total
= COSTS_N_INSNS (4);
4848 if (mode
!= VOIDmode
)
4849 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4851 *total
= COSTS_N_INSNS (4); /* How knows? */
4856 /* RTX costs for cores with a slow MUL implementation. */
4859 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4861 enum machine_mode mode
= GET_MODE (x
);
4865 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4872 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4879 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4881 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4882 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4883 int cost
, const_ok
= const_ok_for_arm (i
);
4884 int j
, booth_unit_size
;
4886 /* Tune as appropriate. */
4887 cost
= const_ok
? 4 : 8;
4888 booth_unit_size
= 2;
4889 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4891 i
>>= booth_unit_size
;
4899 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4900 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4904 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4910 /* RTX cost for cores with a fast multiply unit (M variants). */
4913 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4915 enum machine_mode mode
= GET_MODE (x
);
4919 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4926 /* There is no point basing this on the tuning, since it is always the
4927 fast variant if it exists at all. */
4929 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4930 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4931 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4938 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4945 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4947 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4948 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4949 int cost
, const_ok
= const_ok_for_arm (i
);
4950 int j
, booth_unit_size
;
4952 /* Tune as appropriate. */
4953 cost
= const_ok
? 4 : 8;
4954 booth_unit_size
= 8;
4955 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4957 i
>>= booth_unit_size
;
4965 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4966 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4970 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4976 /* RTX cost for XScale CPUs. */
4979 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4981 enum machine_mode mode
= GET_MODE (x
);
4985 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4992 /* There is no point basing this on the tuning, since it is always the
4993 fast variant if it exists at all. */
4995 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4996 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4997 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5004 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5011 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5013 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
5014 & (unsigned HOST_WIDE_INT
) 0xffffffff);
5015 int cost
, const_ok
= const_ok_for_arm (i
);
5016 unsigned HOST_WIDE_INT masked_const
;
5018 /* The cost will be related to two insns.
5019 First a load of the constant (MOV or LDR), then a multiply. */
5022 cost
+= 1; /* LDR is probably more expensive because
5023 of longer result latency. */
5024 masked_const
= i
& 0xffff8000;
5025 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
5027 masked_const
= i
& 0xf8000000;
5028 if (masked_const
== 0 || masked_const
== 0xf8000000)
5037 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
5038 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
5042 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5043 will stall until the multiplication is complete. */
5044 if (GET_CODE (XEXP (x
, 0)) == MULT
)
5045 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
5047 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5051 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5057 /* RTX costs for 9e (and later) cores. */
5060 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5062 enum machine_mode mode
= GET_MODE (x
);
5071 *total
= COSTS_N_INSNS (3);
5075 *total
= thumb_rtx_costs (x
, code
, outer_code
);
5083 /* There is no point basing this on the tuning, since it is always the
5084 fast variant if it exists at all. */
5086 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5087 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5088 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5095 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5112 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
5113 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
5117 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5121 /* All address computations that can be done are free, but rtx cost returns
5122 the same for practically all of them. So we weight the different types
5123 of address here in the order (most pref first):
5124 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5126 arm_arm_address_cost (rtx x
)
5128 enum rtx_code c
= GET_CODE (x
);
5130 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
5132 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
5135 if (c
== PLUS
|| c
== MINUS
)
5137 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5140 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
5150 arm_thumb_address_cost (rtx x
)
5152 enum rtx_code c
= GET_CODE (x
);
5157 && GET_CODE (XEXP (x
, 0)) == REG
5158 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5165 arm_address_cost (rtx x
)
5167 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
5171 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
5175 /* Some true dependencies can have a higher cost depending
5176 on precisely how certain input operands are used. */
5178 && REG_NOTE_KIND (link
) == 0
5179 && recog_memoized (insn
) >= 0
5180 && recog_memoized (dep
) >= 0)
5182 int shift_opnum
= get_attr_shift (insn
);
5183 enum attr_type attr_type
= get_attr_type (dep
);
5185 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5186 operand for INSN. If we have a shifted input operand and the
5187 instruction we depend on is another ALU instruction, then we may
5188 have to account for an additional stall. */
5189 if (shift_opnum
!= 0
5190 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
5192 rtx shifted_operand
;
5195 /* Get the shifted operand. */
5196 extract_insn (insn
);
5197 shifted_operand
= recog_data
.operand
[shift_opnum
];
5199 /* Iterate over all the operands in DEP. If we write an operand
5200 that overlaps with SHIFTED_OPERAND, then we have increase the
5201 cost of this dependency. */
5203 preprocess_constraints ();
5204 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5206 /* We can ignore strict inputs. */
5207 if (recog_data
.operand_type
[opno
] == OP_IN
)
5210 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
5217 /* XXX This is not strictly true for the FPA. */
5218 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
5219 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
5222 /* Call insns don't incur a stall, even if they follow a load. */
5223 if (REG_NOTE_KIND (link
) == 0
5224 && GET_CODE (insn
) == CALL_INSN
)
5227 if ((i_pat
= single_set (insn
)) != NULL
5228 && GET_CODE (SET_SRC (i_pat
)) == MEM
5229 && (d_pat
= single_set (dep
)) != NULL
5230 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
5232 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
5233 /* This is a load after a store, there is no conflict if the load reads
5234 from a cached area. Assume that loads from the stack, and from the
5235 constant pool are cached, and that others will miss. This is a
5238 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
5239 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
5240 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
5241 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
5248 static int fp_consts_inited
= 0;
5250 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5251 static const char * const strings_fp
[8] =
5254 "4", "5", "0.5", "10"
5257 static REAL_VALUE_TYPE values_fp
[8];
5260 init_fp_table (void)
5266 fp_consts_inited
= 1;
5268 fp_consts_inited
= 8;
5270 for (i
= 0; i
< fp_consts_inited
; i
++)
5272 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
5277 /* Return TRUE if rtx X is a valid immediate FP constant. */
5279 arm_const_double_rtx (rtx x
)
5284 if (!fp_consts_inited
)
5287 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5288 if (REAL_VALUE_MINUS_ZERO (r
))
5291 for (i
= 0; i
< fp_consts_inited
; i
++)
5292 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5298 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5300 neg_const_double_rtx_ok_for_fpa (rtx x
)
5305 if (!fp_consts_inited
)
5308 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5309 r
= REAL_VALUE_NEGATE (r
);
5310 if (REAL_VALUE_MINUS_ZERO (r
))
5313 for (i
= 0; i
< 8; i
++)
5314 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5320 /* Predicates for `match_operand' and `match_operator'. */
5322 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5324 cirrus_memory_offset (rtx op
)
5326 /* Reject eliminable registers. */
5327 if (! (reload_in_progress
|| reload_completed
)
5328 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5329 || reg_mentioned_p (arg_pointer_rtx
, op
)
5330 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5331 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5332 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5333 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5336 if (GET_CODE (op
) == MEM
)
5342 /* Match: (mem (reg)). */
5343 if (GET_CODE (ind
) == REG
)
5349 if (GET_CODE (ind
) == PLUS
5350 && GET_CODE (XEXP (ind
, 0)) == REG
5351 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5352 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
5359 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5360 WB if true if writeback address modes are allowed. */
5363 arm_coproc_mem_operand (rtx op
, bool wb
)
5367 /* Reject eliminable registers. */
5368 if (! (reload_in_progress
|| reload_completed
)
5369 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5370 || reg_mentioned_p (arg_pointer_rtx
, op
)
5371 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5372 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5373 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5374 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5377 /* Constants are converted into offsets from labels. */
5378 if (GET_CODE (op
) != MEM
)
5383 if (reload_completed
5384 && (GET_CODE (ind
) == LABEL_REF
5385 || (GET_CODE (ind
) == CONST
5386 && GET_CODE (XEXP (ind
, 0)) == PLUS
5387 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5388 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5391 /* Match: (mem (reg)). */
5392 if (GET_CODE (ind
) == REG
)
5393 return arm_address_register_rtx_p (ind
, 0);
5395 /* Autoincremment addressing modes. */
5397 && (GET_CODE (ind
) == PRE_INC
5398 || GET_CODE (ind
) == POST_INC
5399 || GET_CODE (ind
) == PRE_DEC
5400 || GET_CODE (ind
) == POST_DEC
))
5401 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5404 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5405 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5406 && GET_CODE (XEXP (ind
, 1)) == PLUS
5407 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5408 ind
= XEXP (ind
, 1);
5413 if (GET_CODE (ind
) == PLUS
5414 && GET_CODE (XEXP (ind
, 0)) == REG
5415 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5416 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5417 && INTVAL (XEXP (ind
, 1)) > -1024
5418 && INTVAL (XEXP (ind
, 1)) < 1024
5419 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5425 /* Return true if X is a register that will be eliminated later on. */
5427 arm_eliminable_register (rtx x
)
5429 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5430 || REGNO (x
) == ARG_POINTER_REGNUM
5431 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5432 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5435 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5436 VFP registers. Otherwise return NO_REGS. */
5439 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5441 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5444 return GENERAL_REGS
;
5447 /* Values which must be returned in the most-significant end of the return
5451 arm_return_in_msb (tree valtype
)
5453 return (TARGET_AAPCS_BASED
5455 && (AGGREGATE_TYPE_P (valtype
)
5456 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5459 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5460 Use by the Cirrus Maverick code which has to workaround
5461 a hardware bug triggered by such instructions. */
5463 arm_memory_load_p (rtx insn
)
5465 rtx body
, lhs
, rhs
;;
5467 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5470 body
= PATTERN (insn
);
5472 if (GET_CODE (body
) != SET
)
5475 lhs
= XEXP (body
, 0);
5476 rhs
= XEXP (body
, 1);
5478 lhs
= REG_OR_SUBREG_RTX (lhs
);
5480 /* If the destination is not a general purpose
5481 register we do not have to worry. */
5482 if (GET_CODE (lhs
) != REG
5483 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5486 /* As well as loads from memory we also have to react
5487 to loads of invalid constants which will be turned
5488 into loads from the minipool. */
5489 return (GET_CODE (rhs
) == MEM
5490 || GET_CODE (rhs
) == SYMBOL_REF
5491 || note_invalid_constants (insn
, -1, false));
5494 /* Return TRUE if INSN is a Cirrus instruction. */
5496 arm_cirrus_insn_p (rtx insn
)
5498 enum attr_cirrus attr
;
5500 /* get_attr cannot accept USE or CLOBBER. */
5502 || GET_CODE (insn
) != INSN
5503 || GET_CODE (PATTERN (insn
)) == USE
5504 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5507 attr
= get_attr_cirrus (insn
);
5509 return attr
!= CIRRUS_NOT
;
5512 /* Cirrus reorg for invalid instruction combinations. */
5514 cirrus_reorg (rtx first
)
5516 enum attr_cirrus attr
;
5517 rtx body
= PATTERN (first
);
5521 /* Any branch must be followed by 2 non Cirrus instructions. */
5522 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5525 t
= next_nonnote_insn (first
);
5527 if (arm_cirrus_insn_p (t
))
5530 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5534 emit_insn_after (gen_nop (), first
);
5539 /* (float (blah)) is in parallel with a clobber. */
5540 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5541 body
= XVECEXP (body
, 0, 0);
5543 if (GET_CODE (body
) == SET
)
5545 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5547 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5548 be followed by a non Cirrus insn. */
5549 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5551 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5552 emit_insn_after (gen_nop (), first
);
5556 else if (arm_memory_load_p (first
))
5558 unsigned int arm_regno
;
5560 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5561 ldr/cfmv64hr combination where the Rd field is the same
5562 in both instructions must be split with a non Cirrus
5569 /* Get Arm register number for ldr insn. */
5570 if (GET_CODE (lhs
) == REG
)
5571 arm_regno
= REGNO (lhs
);
5574 gcc_assert (GET_CODE (rhs
) == REG
);
5575 arm_regno
= REGNO (rhs
);
5579 first
= next_nonnote_insn (first
);
5581 if (! arm_cirrus_insn_p (first
))
5584 body
= PATTERN (first
);
5586 /* (float (blah)) is in parallel with a clobber. */
5587 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5588 body
= XVECEXP (body
, 0, 0);
5590 if (GET_CODE (body
) == FLOAT
)
5591 body
= XEXP (body
, 0);
5593 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5594 && GET_CODE (XEXP (body
, 1)) == REG
5595 && arm_regno
== REGNO (XEXP (body
, 1)))
5596 emit_insn_after (gen_nop (), first
);
5602 /* get_attr cannot accept USE or CLOBBER. */
5604 || GET_CODE (first
) != INSN
5605 || GET_CODE (PATTERN (first
)) == USE
5606 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5609 attr
= get_attr_cirrus (first
);
5611 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5612 must be followed by a non-coprocessor instruction. */
5613 if (attr
== CIRRUS_COMPARE
)
5617 t
= next_nonnote_insn (first
);
5619 if (arm_cirrus_insn_p (t
))
5622 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5626 emit_insn_after (gen_nop (), first
);
5632 /* Return TRUE if X references a SYMBOL_REF. */
5634 symbol_mentioned_p (rtx x
)
5639 if (GET_CODE (x
) == SYMBOL_REF
)
5642 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5643 are constant offsets, not symbols. */
5644 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5647 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5649 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5655 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5656 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5659 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5666 /* Return TRUE if X references a LABEL_REF. */
5668 label_mentioned_p (rtx x
)
5673 if (GET_CODE (x
) == LABEL_REF
)
5676 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5677 instruction, but they are constant offsets, not symbols. */
5678 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5681 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5682 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5688 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5689 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5692 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5700 tls_mentioned_p (rtx x
)
5702 switch (GET_CODE (x
))
5705 return tls_mentioned_p (XEXP (x
, 0));
5708 if (XINT (x
, 1) == UNSPEC_TLS
)
5716 /* Must not copy a SET whose source operand is PC-relative. */
5719 arm_cannot_copy_insn_p (rtx insn
)
5721 rtx pat
= PATTERN (insn
);
5723 if (GET_CODE (pat
) == PARALLEL
5724 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
)
5726 rtx rhs
= SET_SRC (XVECEXP (pat
, 0, 0));
5728 if (GET_CODE (rhs
) == UNSPEC
5729 && XINT (rhs
, 1) == UNSPEC_PIC_BASE
)
5732 if (GET_CODE (rhs
) == MEM
5733 && GET_CODE (XEXP (rhs
, 0)) == UNSPEC
5734 && XINT (XEXP (rhs
, 0), 1) == UNSPEC_PIC_BASE
)
5744 enum rtx_code code
= GET_CODE (x
);
5761 /* Return 1 if memory locations are adjacent. */
5763 adjacent_mem_locations (rtx a
, rtx b
)
5765 /* We don't guarantee to preserve the order of these memory refs. */
5766 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5769 if ((GET_CODE (XEXP (a
, 0)) == REG
5770 || (GET_CODE (XEXP (a
, 0)) == PLUS
5771 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5772 && (GET_CODE (XEXP (b
, 0)) == REG
5773 || (GET_CODE (XEXP (b
, 0)) == PLUS
5774 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5776 HOST_WIDE_INT val0
= 0, val1
= 0;
5780 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5782 reg0
= XEXP (XEXP (a
, 0), 0);
5783 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5788 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5790 reg1
= XEXP (XEXP (b
, 0), 0);
5791 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5796 /* Don't accept any offset that will require multiple
5797 instructions to handle, since this would cause the
5798 arith_adjacentmem pattern to output an overlong sequence. */
5799 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5802 /* Don't allow an eliminable register: register elimination can make
5803 the offset too large. */
5804 if (arm_eliminable_register (reg0
))
5807 val_diff
= val1
- val0
;
5811 /* If the target has load delay slots, then there's no benefit
5812 to using an ldm instruction unless the offset is zero and
5813 we are optimizing for size. */
5814 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5815 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5816 && (val_diff
== 4 || val_diff
== -4));
5819 return ((REGNO (reg0
) == REGNO (reg1
))
5820 && (val_diff
== 4 || val_diff
== -4));
5827 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5828 HOST_WIDE_INT
*load_offset
)
5830 int unsorted_regs
[4];
5831 HOST_WIDE_INT unsorted_offsets
[4];
5836 /* Can only handle 2, 3, or 4 insns at present,
5837 though could be easily extended if required. */
5838 gcc_assert (nops
>= 2 && nops
<= 4);
5840 /* Loop over the operands and check that the memory references are
5841 suitable (i.e. immediate offsets from the same base register). At
5842 the same time, extract the target register, and the memory
5844 for (i
= 0; i
< nops
; i
++)
5849 /* Convert a subreg of a mem into the mem itself. */
5850 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5851 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5853 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5855 /* Don't reorder volatile memory references; it doesn't seem worth
5856 looking for the case where the order is ok anyway. */
5857 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5860 offset
= const0_rtx
;
5862 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5863 || (GET_CODE (reg
) == SUBREG
5864 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5865 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5866 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5868 || (GET_CODE (reg
) == SUBREG
5869 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5870 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5875 base_reg
= REGNO (reg
);
5876 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5877 ? REGNO (operands
[i
])
5878 : REGNO (SUBREG_REG (operands
[i
])));
5883 if (base_reg
!= (int) REGNO (reg
))
5884 /* Not addressed from the same base register. */
5887 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5888 ? REGNO (operands
[i
])
5889 : REGNO (SUBREG_REG (operands
[i
])));
5890 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5894 /* If it isn't an integer register, or if it overwrites the
5895 base register but isn't the last insn in the list, then
5896 we can't do this. */
5897 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5898 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5901 unsorted_offsets
[i
] = INTVAL (offset
);
5904 /* Not a suitable memory address. */
5908 /* All the useful information has now been extracted from the
5909 operands into unsorted_regs and unsorted_offsets; additionally,
5910 order[0] has been set to the lowest numbered register in the
5911 list. Sort the registers into order, and check that the memory
5912 offsets are ascending and adjacent. */
5914 for (i
= 1; i
< nops
; i
++)
5918 order
[i
] = order
[i
- 1];
5919 for (j
= 0; j
< nops
; j
++)
5920 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5921 && (order
[i
] == order
[i
- 1]
5922 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5925 /* Have we found a suitable register? if not, one must be used more
5927 if (order
[i
] == order
[i
- 1])
5930 /* Is the memory address adjacent and ascending? */
5931 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5939 for (i
= 0; i
< nops
; i
++)
5940 regs
[i
] = unsorted_regs
[order
[i
]];
5942 *load_offset
= unsorted_offsets
[order
[0]];
5945 if (unsorted_offsets
[order
[0]] == 0)
5946 return 1; /* ldmia */
5948 if (unsorted_offsets
[order
[0]] == 4)
5949 return 2; /* ldmib */
5951 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5952 return 3; /* ldmda */
5954 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5955 return 4; /* ldmdb */
5957 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5958 if the offset isn't small enough. The reason 2 ldrs are faster
5959 is because these ARMs are able to do more than one cache access
5960 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5961 whilst the ARM8 has a double bandwidth cache. This means that
5962 these cores can do both an instruction fetch and a data fetch in
5963 a single cycle, so the trick of calculating the address into a
5964 scratch register (one of the result regs) and then doing a load
5965 multiple actually becomes slower (and no smaller in code size).
5966 That is the transformation
5968 ldr rd1, [rbase + offset]
5969 ldr rd2, [rbase + offset + 4]
5973 add rd1, rbase, offset
5974 ldmia rd1, {rd1, rd2}
5976 produces worse code -- '3 cycles + any stalls on rd2' instead of
5977 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5978 access per cycle, the first sequence could never complete in less
5979 than 6 cycles, whereas the ldm sequence would only take 5 and
5980 would make better use of sequential accesses if not hitting the
5983 We cheat here and test 'arm_ld_sched' which we currently know to
5984 only be true for the ARM8, ARM9 and StrongARM. If this ever
5985 changes, then the test below needs to be reworked. */
5986 if (nops
== 2 && arm_ld_sched
)
5989 /* Can't do it without setting up the offset, only do this if it takes
5990 no more than one insn. */
5991 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5992 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5996 emit_ldm_seq (rtx
*operands
, int nops
)
6000 HOST_WIDE_INT offset
;
6004 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6007 strcpy (buf
, "ldm%?ia\t");
6011 strcpy (buf
, "ldm%?ib\t");
6015 strcpy (buf
, "ldm%?da\t");
6019 strcpy (buf
, "ldm%?db\t");
6024 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6025 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6028 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6029 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6031 output_asm_insn (buf
, operands
);
6033 strcpy (buf
, "ldm%?ia\t");
6040 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6041 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6043 for (i
= 1; i
< nops
; i
++)
6044 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6045 reg_names
[regs
[i
]]);
6047 strcat (buf
, "}\t%@ phole ldm");
6049 output_asm_insn (buf
, operands
);
6054 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
6055 HOST_WIDE_INT
* load_offset
)
6057 int unsorted_regs
[4];
6058 HOST_WIDE_INT unsorted_offsets
[4];
6063 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6064 extended if required. */
6065 gcc_assert (nops
>= 2 && nops
<= 4);
6067 /* Loop over the operands and check that the memory references are
6068 suitable (i.e. immediate offsets from the same base register). At
6069 the same time, extract the target register, and the memory
6071 for (i
= 0; i
< nops
; i
++)
6076 /* Convert a subreg of a mem into the mem itself. */
6077 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
6078 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
6080 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6082 /* Don't reorder volatile memory references; it doesn't seem worth
6083 looking for the case where the order is ok anyway. */
6084 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6087 offset
= const0_rtx
;
6089 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6090 || (GET_CODE (reg
) == SUBREG
6091 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6092 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6093 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6095 || (GET_CODE (reg
) == SUBREG
6096 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6097 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6102 base_reg
= REGNO (reg
);
6103 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6104 ? REGNO (operands
[i
])
6105 : REGNO (SUBREG_REG (operands
[i
])));
6110 if (base_reg
!= (int) REGNO (reg
))
6111 /* Not addressed from the same base register. */
6114 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6115 ? REGNO (operands
[i
])
6116 : REGNO (SUBREG_REG (operands
[i
])));
6117 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6121 /* If it isn't an integer register, then we can't do this. */
6122 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
6125 unsorted_offsets
[i
] = INTVAL (offset
);
6128 /* Not a suitable memory address. */
6132 /* All the useful information has now been extracted from the
6133 operands into unsorted_regs and unsorted_offsets; additionally,
6134 order[0] has been set to the lowest numbered register in the
6135 list. Sort the registers into order, and check that the memory
6136 offsets are ascending and adjacent. */
6138 for (i
= 1; i
< nops
; i
++)
6142 order
[i
] = order
[i
- 1];
6143 for (j
= 0; j
< nops
; j
++)
6144 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6145 && (order
[i
] == order
[i
- 1]
6146 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6149 /* Have we found a suitable register? if not, one must be used more
6151 if (order
[i
] == order
[i
- 1])
6154 /* Is the memory address adjacent and ascending? */
6155 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6163 for (i
= 0; i
< nops
; i
++)
6164 regs
[i
] = unsorted_regs
[order
[i
]];
6166 *load_offset
= unsorted_offsets
[order
[0]];
6169 if (unsorted_offsets
[order
[0]] == 0)
6170 return 1; /* stmia */
6172 if (unsorted_offsets
[order
[0]] == 4)
6173 return 2; /* stmib */
6175 if (unsorted_offsets
[order
[nops
- 1]] == 0)
6176 return 3; /* stmda */
6178 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6179 return 4; /* stmdb */
6185 emit_stm_seq (rtx
*operands
, int nops
)
6189 HOST_WIDE_INT offset
;
6193 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6196 strcpy (buf
, "stm%?ia\t");
6200 strcpy (buf
, "stm%?ib\t");
6204 strcpy (buf
, "stm%?da\t");
6208 strcpy (buf
, "stm%?db\t");
6215 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6216 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6218 for (i
= 1; i
< nops
; i
++)
6219 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6220 reg_names
[regs
[i
]]);
6222 strcat (buf
, "}\t%@ phole stm");
6224 output_asm_insn (buf
, operands
);
6228 /* Routines for use in generating RTL. */
6231 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
6232 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6234 HOST_WIDE_INT offset
= *offsetp
;
6237 int sign
= up
? 1 : -1;
6240 /* XScale has load-store double instructions, but they have stricter
6241 alignment requirements than load-store multiple, so we cannot
6244 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6245 the pipeline until completion.
6253 An ldr instruction takes 1-3 cycles, but does not block the
6262 Best case ldr will always win. However, the more ldr instructions
6263 we issue, the less likely we are to be able to schedule them well.
6264 Using ldr instructions also increases code size.
6266 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6267 for counts of 3 or 4 regs. */
6268 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6274 for (i
= 0; i
< count
; i
++)
6276 addr
= plus_constant (from
, i
* 4 * sign
);
6277 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6278 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
6284 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
6294 result
= gen_rtx_PARALLEL (VOIDmode
,
6295 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6298 XVECEXP (result
, 0, 0)
6299 = gen_rtx_SET (VOIDmode
, from
, plus_constant (from
, count
* 4 * sign
));
6304 for (j
= 0; i
< count
; i
++, j
++)
6306 addr
= plus_constant (from
, j
* 4 * sign
);
6307 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6308 XVECEXP (result
, 0, i
)
6309 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
6320 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
6321 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6323 HOST_WIDE_INT offset
= *offsetp
;
6326 int sign
= up
? 1 : -1;
6329 /* See arm_gen_load_multiple for discussion of
6330 the pros/cons of ldm/stm usage for XScale. */
6331 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6337 for (i
= 0; i
< count
; i
++)
6339 addr
= plus_constant (to
, i
* 4 * sign
);
6340 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6341 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6347 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6357 result
= gen_rtx_PARALLEL (VOIDmode
,
6358 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6361 XVECEXP (result
, 0, 0)
6362 = gen_rtx_SET (VOIDmode
, to
,
6363 plus_constant (to
, count
* 4 * sign
));
6368 for (j
= 0; i
< count
; i
++, j
++)
6370 addr
= plus_constant (to
, j
* 4 * sign
);
6371 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6372 XVECEXP (result
, 0, i
)
6373 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6384 arm_gen_movmemqi (rtx
*operands
)
6386 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6387 HOST_WIDE_INT srcoffset
, dstoffset
;
6389 rtx src
, dst
, srcbase
, dstbase
;
6390 rtx part_bytes_reg
= NULL
;
6393 if (GET_CODE (operands
[2]) != CONST_INT
6394 || GET_CODE (operands
[3]) != CONST_INT
6395 || INTVAL (operands
[2]) > 64
6396 || INTVAL (operands
[3]) & 3)
6399 dstbase
= operands
[0];
6400 srcbase
= operands
[1];
6402 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
6403 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
6405 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6406 out_words_to_go
= INTVAL (operands
[2]) / 4;
6407 last_bytes
= INTVAL (operands
[2]) & 3;
6408 dstoffset
= srcoffset
= 0;
6410 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6411 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6413 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6415 if (in_words_to_go
> 4)
6416 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6417 srcbase
, &srcoffset
));
6419 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6420 FALSE
, srcbase
, &srcoffset
));
6422 if (out_words_to_go
)
6424 if (out_words_to_go
> 4)
6425 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6426 dstbase
, &dstoffset
));
6427 else if (out_words_to_go
!= 1)
6428 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6432 dstbase
, &dstoffset
));
6435 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6436 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6437 if (last_bytes
!= 0)
6439 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6445 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6446 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6449 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6450 if (out_words_to_go
)
6454 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6455 sreg
= copy_to_reg (mem
);
6457 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6458 emit_move_insn (mem
, sreg
);
6461 gcc_assert (!in_words_to_go
); /* Sanity check */
6466 gcc_assert (in_words_to_go
> 0);
6468 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6469 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6472 gcc_assert (!last_bytes
|| part_bytes_reg
);
6474 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6476 rtx tmp
= gen_reg_rtx (SImode
);
6478 /* The bytes we want are in the top end of the word. */
6479 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6480 GEN_INT (8 * (4 - last_bytes
))));
6481 part_bytes_reg
= tmp
;
6485 mem
= adjust_automodify_address (dstbase
, QImode
,
6486 plus_constant (dst
, last_bytes
- 1),
6487 dstoffset
+ last_bytes
- 1);
6488 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6492 tmp
= gen_reg_rtx (SImode
);
6493 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6494 part_bytes_reg
= tmp
;
6503 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6504 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6508 rtx tmp
= gen_reg_rtx (SImode
);
6509 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6510 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6511 part_bytes_reg
= tmp
;
6518 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6519 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6526 /* Select a dominance comparison mode if possible for a test of the general
6527 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6528 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6529 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6530 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6531 In all cases OP will be either EQ or NE, but we don't need to know which
6532 here. If we are unable to support a dominance comparison we return
6533 CC mode. This will then fail to match for the RTL expressions that
6534 generate this call. */
6536 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6538 enum rtx_code cond1
, cond2
;
6541 /* Currently we will probably get the wrong result if the individual
6542 comparisons are not simple. This also ensures that it is safe to
6543 reverse a comparison if necessary. */
6544 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6546 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6550 /* The if_then_else variant of this tests the second condition if the
6551 first passes, but is true if the first fails. Reverse the first
6552 condition to get a true "inclusive-or" expression. */
6553 if (cond_or
== DOM_CC_NX_OR_Y
)
6554 cond1
= reverse_condition (cond1
);
6556 /* If the comparisons are not equal, and one doesn't dominate the other,
6557 then we can't do this. */
6559 && !comparison_dominates_p (cond1
, cond2
)
6560 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6565 enum rtx_code temp
= cond1
;
6573 if (cond_or
== DOM_CC_X_AND_Y
)
6578 case EQ
: return CC_DEQmode
;
6579 case LE
: return CC_DLEmode
;
6580 case LEU
: return CC_DLEUmode
;
6581 case GE
: return CC_DGEmode
;
6582 case GEU
: return CC_DGEUmode
;
6583 default: gcc_unreachable ();
6587 if (cond_or
== DOM_CC_X_AND_Y
)
6603 if (cond_or
== DOM_CC_X_AND_Y
)
6619 if (cond_or
== DOM_CC_X_AND_Y
)
6635 if (cond_or
== DOM_CC_X_AND_Y
)
6650 /* The remaining cases only occur when both comparisons are the
6653 gcc_assert (cond1
== cond2
);
6657 gcc_assert (cond1
== cond2
);
6661 gcc_assert (cond1
== cond2
);
6665 gcc_assert (cond1
== cond2
);
6669 gcc_assert (cond1
== cond2
);
6678 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6680 /* All floating point compares return CCFP if it is an equality
6681 comparison, and CCFPE otherwise. */
6682 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6702 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6711 /* A compare with a shifted operand. Because of canonicalization, the
6712 comparison will have to be swapped when we emit the assembler. */
6713 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6714 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6715 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6716 || GET_CODE (x
) == ROTATERT
))
6719 /* This operation is performed swapped, but since we only rely on the Z
6720 flag we don't need an additional mode. */
6721 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6722 && GET_CODE (x
) == NEG
6723 && (op
== EQ
|| op
== NE
))
6726 /* This is a special case that is used by combine to allow a
6727 comparison of a shifted byte load to be split into a zero-extend
6728 followed by a comparison of the shifted integer (only valid for
6729 equalities and unsigned inequalities). */
6730 if (GET_MODE (x
) == SImode
6731 && GET_CODE (x
) == ASHIFT
6732 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6733 && GET_CODE (XEXP (x
, 0)) == SUBREG
6734 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6735 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6736 && (op
== EQ
|| op
== NE
6737 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6738 && GET_CODE (y
) == CONST_INT
)
6741 /* A construct for a conditional compare, if the false arm contains
6742 0, then both conditions must be true, otherwise either condition
6743 must be true. Not all conditions are possible, so CCmode is
6744 returned if it can't be done. */
6745 if (GET_CODE (x
) == IF_THEN_ELSE
6746 && (XEXP (x
, 2) == const0_rtx
6747 || XEXP (x
, 2) == const1_rtx
)
6748 && COMPARISON_P (XEXP (x
, 0))
6749 && COMPARISON_P (XEXP (x
, 1)))
6750 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6751 INTVAL (XEXP (x
, 2)));
6753 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6754 if (GET_CODE (x
) == AND
6755 && COMPARISON_P (XEXP (x
, 0))
6756 && COMPARISON_P (XEXP (x
, 1)))
6757 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6760 if (GET_CODE (x
) == IOR
6761 && COMPARISON_P (XEXP (x
, 0))
6762 && COMPARISON_P (XEXP (x
, 1)))
6763 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6766 /* An operation (on Thumb) where we want to test for a single bit.
6767 This is done by shifting that bit up into the top bit of a
6768 scratch register; we can then branch on the sign bit. */
6770 && GET_MODE (x
) == SImode
6771 && (op
== EQ
|| op
== NE
)
6772 && GET_CODE (x
) == ZERO_EXTRACT
6773 && XEXP (x
, 1) == const1_rtx
)
6776 /* An operation that sets the condition codes as a side-effect, the
6777 V flag is not set correctly, so we can only use comparisons where
6778 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6780 if (GET_MODE (x
) == SImode
6782 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6783 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6784 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6785 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6786 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6787 || GET_CODE (x
) == LSHIFTRT
6788 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6789 || GET_CODE (x
) == ROTATERT
6790 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6793 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6796 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6797 && GET_CODE (x
) == PLUS
6798 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6804 /* X and Y are two things to compare using CODE. Emit the compare insn and
6805 return the rtx for register 0 in the proper mode. FP means this is a
6806 floating point compare: I don't think that it is needed on the arm. */
6808 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6810 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6811 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6813 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
6818 /* Generate a sequence of insns that will generate the correct return
6819 address mask depending on the physical architecture that the program
6822 arm_gen_return_addr_mask (void)
6824 rtx reg
= gen_reg_rtx (Pmode
);
6826 emit_insn (gen_return_addr_mask (reg
));
6831 arm_reload_in_hi (rtx
*operands
)
6833 rtx ref
= operands
[1];
6835 HOST_WIDE_INT offset
= 0;
6837 if (GET_CODE (ref
) == SUBREG
)
6839 offset
= SUBREG_BYTE (ref
);
6840 ref
= SUBREG_REG (ref
);
6843 if (GET_CODE (ref
) == REG
)
6845 /* We have a pseudo which has been spilt onto the stack; there
6846 are two cases here: the first where there is a simple
6847 stack-slot replacement and a second where the stack-slot is
6848 out of range, or is used as a subreg. */
6849 if (reg_equiv_mem
[REGNO (ref
)])
6851 ref
= reg_equiv_mem
[REGNO (ref
)];
6852 base
= find_replacement (&XEXP (ref
, 0));
6855 /* The slot is out of range, or was dressed up in a SUBREG. */
6856 base
= reg_equiv_address
[REGNO (ref
)];
6859 base
= find_replacement (&XEXP (ref
, 0));
6861 /* Handle the case where the address is too complex to be offset by 1. */
6862 if (GET_CODE (base
) == MINUS
6863 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6865 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6867 emit_set_insn (base_plus
, base
);
6870 else if (GET_CODE (base
) == PLUS
)
6872 /* The addend must be CONST_INT, or we would have dealt with it above. */
6873 HOST_WIDE_INT hi
, lo
;
6875 offset
+= INTVAL (XEXP (base
, 1));
6876 base
= XEXP (base
, 0);
6878 /* Rework the address into a legal sequence of insns. */
6879 /* Valid range for lo is -4095 -> 4095 */
6882 : -((-offset
) & 0xfff));
6884 /* Corner case, if lo is the max offset then we would be out of range
6885 once we have added the additional 1 below, so bump the msb into the
6886 pre-loading insn(s). */
6890 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6891 ^ (HOST_WIDE_INT
) 0x80000000)
6892 - (HOST_WIDE_INT
) 0x80000000);
6894 gcc_assert (hi
+ lo
== offset
);
6898 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6900 /* Get the base address; addsi3 knows how to handle constants
6901 that require more than one insn. */
6902 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6908 /* Operands[2] may overlap operands[0] (though it won't overlap
6909 operands[1]), that's why we asked for a DImode reg -- so we can
6910 use the bit that does not overlap. */
6911 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6912 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6914 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6916 emit_insn (gen_zero_extendqisi2 (scratch
,
6917 gen_rtx_MEM (QImode
,
6918 plus_constant (base
,
6920 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6921 gen_rtx_MEM (QImode
,
6922 plus_constant (base
,
6924 if (!BYTES_BIG_ENDIAN
)
6925 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6926 gen_rtx_IOR (SImode
,
6929 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6933 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6934 gen_rtx_IOR (SImode
,
6935 gen_rtx_ASHIFT (SImode
, scratch
,
6937 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
6940 /* Handle storing a half-word to memory during reload by synthesizing as two
6941 byte stores. Take care not to clobber the input values until after we
6942 have moved them somewhere safe. This code assumes that if the DImode
6943 scratch in operands[2] overlaps either the input value or output address
6944 in some way, then that value must die in this insn (we absolutely need
6945 two scratch registers for some corner cases). */
6947 arm_reload_out_hi (rtx
*operands
)
6949 rtx ref
= operands
[0];
6950 rtx outval
= operands
[1];
6952 HOST_WIDE_INT offset
= 0;
6954 if (GET_CODE (ref
) == SUBREG
)
6956 offset
= SUBREG_BYTE (ref
);
6957 ref
= SUBREG_REG (ref
);
6960 if (GET_CODE (ref
) == REG
)
6962 /* We have a pseudo which has been spilt onto the stack; there
6963 are two cases here: the first where there is a simple
6964 stack-slot replacement and a second where the stack-slot is
6965 out of range, or is used as a subreg. */
6966 if (reg_equiv_mem
[REGNO (ref
)])
6968 ref
= reg_equiv_mem
[REGNO (ref
)];
6969 base
= find_replacement (&XEXP (ref
, 0));
6972 /* The slot is out of range, or was dressed up in a SUBREG. */
6973 base
= reg_equiv_address
[REGNO (ref
)];
6976 base
= find_replacement (&XEXP (ref
, 0));
6978 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6980 /* Handle the case where the address is too complex to be offset by 1. */
6981 if (GET_CODE (base
) == MINUS
6982 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6984 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6986 /* Be careful not to destroy OUTVAL. */
6987 if (reg_overlap_mentioned_p (base_plus
, outval
))
6989 /* Updating base_plus might destroy outval, see if we can
6990 swap the scratch and base_plus. */
6991 if (!reg_overlap_mentioned_p (scratch
, outval
))
6994 scratch
= base_plus
;
6999 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
7001 /* Be conservative and copy OUTVAL into the scratch now,
7002 this should only be necessary if outval is a subreg
7003 of something larger than a word. */
7004 /* XXX Might this clobber base? I can't see how it can,
7005 since scratch is known to overlap with OUTVAL, and
7006 must be wider than a word. */
7007 emit_insn (gen_movhi (scratch_hi
, outval
));
7008 outval
= scratch_hi
;
7012 emit_set_insn (base_plus
, base
);
7015 else if (GET_CODE (base
) == PLUS
)
7017 /* The addend must be CONST_INT, or we would have dealt with it above. */
7018 HOST_WIDE_INT hi
, lo
;
7020 offset
+= INTVAL (XEXP (base
, 1));
7021 base
= XEXP (base
, 0);
7023 /* Rework the address into a legal sequence of insns. */
7024 /* Valid range for lo is -4095 -> 4095 */
7027 : -((-offset
) & 0xfff));
7029 /* Corner case, if lo is the max offset then we would be out of range
7030 once we have added the additional 1 below, so bump the msb into the
7031 pre-loading insn(s). */
7035 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
7036 ^ (HOST_WIDE_INT
) 0x80000000)
7037 - (HOST_WIDE_INT
) 0x80000000);
7039 gcc_assert (hi
+ lo
== offset
);
7043 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7045 /* Be careful not to destroy OUTVAL. */
7046 if (reg_overlap_mentioned_p (base_plus
, outval
))
7048 /* Updating base_plus might destroy outval, see if we
7049 can swap the scratch and base_plus. */
7050 if (!reg_overlap_mentioned_p (scratch
, outval
))
7053 scratch
= base_plus
;
7058 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
7060 /* Be conservative and copy outval into scratch now,
7061 this should only be necessary if outval is a
7062 subreg of something larger than a word. */
7063 /* XXX Might this clobber base? I can't see how it
7064 can, since scratch is known to overlap with
7066 emit_insn (gen_movhi (scratch_hi
, outval
));
7067 outval
= scratch_hi
;
7071 /* Get the base address; addsi3 knows how to handle constants
7072 that require more than one insn. */
7073 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
7079 if (BYTES_BIG_ENDIAN
)
7081 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7082 plus_constant (base
, offset
+ 1)),
7083 gen_lowpart (QImode
, outval
)));
7084 emit_insn (gen_lshrsi3 (scratch
,
7085 gen_rtx_SUBREG (SImode
, outval
, 0),
7087 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7088 gen_lowpart (QImode
, scratch
)));
7092 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7093 gen_lowpart (QImode
, outval
)));
7094 emit_insn (gen_lshrsi3 (scratch
,
7095 gen_rtx_SUBREG (SImode
, outval
, 0),
7097 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7098 plus_constant (base
, offset
+ 1)),
7099 gen_lowpart (QImode
, scratch
)));
7103 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7104 (padded to the size of a word) should be passed in a register. */
7107 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
7109 if (TARGET_AAPCS_BASED
)
7110 return must_pass_in_stack_var_size (mode
, type
);
7112 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7116 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7117 Return true if an argument passed on the stack should be padded upwards,
7118 i.e. if the least-significant byte has useful data.
7119 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7120 aggregate types are placed in the lowest memory address. */
7123 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
7125 if (!TARGET_AAPCS_BASED
)
7126 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
7128 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
7135 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7136 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7137 byte of the register has useful data, and return the opposite if the
7138 most significant byte does.
7139 For AAPCS, small aggregates and small complex types are always padded
7143 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
7144 tree type
, int first ATTRIBUTE_UNUSED
)
7146 if (TARGET_AAPCS_BASED
7148 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
7149 && int_size_in_bytes (type
) <= 4)
7152 /* Otherwise, use default padding. */
7153 return !BYTES_BIG_ENDIAN
;
7157 /* Print a symbolic form of X to the debug file, F. */
7159 arm_print_value (FILE *f
, rtx x
)
7161 switch (GET_CODE (x
))
7164 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
7168 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
7176 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
7178 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
7179 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
7187 fprintf (f
, "\"%s\"", XSTR (x
, 0));
7191 fprintf (f
, "`%s'", XSTR (x
, 0));
7195 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
7199 arm_print_value (f
, XEXP (x
, 0));
7203 arm_print_value (f
, XEXP (x
, 0));
7205 arm_print_value (f
, XEXP (x
, 1));
7213 fprintf (f
, "????");
7218 /* Routines for manipulation of the constant pool. */
7220 /* Arm instructions cannot load a large constant directly into a
7221 register; they have to come from a pc relative load. The constant
7222 must therefore be placed in the addressable range of the pc
7223 relative load. Depending on the precise pc relative load
7224 instruction the range is somewhere between 256 bytes and 4k. This
7225 means that we often have to dump a constant inside a function, and
7226 generate code to branch around it.
7228 It is important to minimize this, since the branches will slow
7229 things down and make the code larger.
7231 Normally we can hide the table after an existing unconditional
7232 branch so that there is no interruption of the flow, but in the
7233 worst case the code looks like this:
7251 We fix this by performing a scan after scheduling, which notices
7252 which instructions need to have their operands fetched from the
7253 constant table and builds the table.
7255 The algorithm starts by building a table of all the constants that
7256 need fixing up and all the natural barriers in the function (places
7257 where a constant table can be dropped without breaking the flow).
7258 For each fixup we note how far the pc-relative replacement will be
7259 able to reach and the offset of the instruction into the function.
7261 Having built the table we then group the fixes together to form
7262 tables that are as large as possible (subject to addressing
7263 constraints) and emit each table of constants after the last
7264 barrier that is within range of all the instructions in the group.
7265 If a group does not contain a barrier, then we forcibly create one
7266 by inserting a jump instruction into the flow. Once the table has
7267 been inserted, the insns are then modified to reference the
7268 relevant entry in the pool.
7270 Possible enhancements to the algorithm (not implemented) are:
7272 1) For some processors and object formats, there may be benefit in
7273 aligning the pools to the start of cache lines; this alignment
7274 would need to be taken into account when calculating addressability
7277 /* These typedefs are located at the start of this file, so that
7278 they can be used in the prototypes there. This comment is to
7279 remind readers of that fact so that the following structures
7280 can be understood more easily.
7282 typedef struct minipool_node Mnode;
7283 typedef struct minipool_fixup Mfix; */
7285 struct minipool_node
7287 /* Doubly linked chain of entries. */
7290 /* The maximum offset into the code that this entry can be placed. While
7291 pushing fixes for forward references, all entries are sorted in order
7292 of increasing max_address. */
7293 HOST_WIDE_INT max_address
;
7294 /* Similarly for an entry inserted for a backwards ref. */
7295 HOST_WIDE_INT min_address
;
7296 /* The number of fixes referencing this entry. This can become zero
7297 if we "unpush" an entry. In this case we ignore the entry when we
7298 come to emit the code. */
7300 /* The offset from the start of the minipool. */
7301 HOST_WIDE_INT offset
;
7302 /* The value in table. */
7304 /* The mode of value. */
7305 enum machine_mode mode
;
7306 /* The size of the value. With iWMMXt enabled
7307 sizes > 4 also imply an alignment of 8-bytes. */
7311 struct minipool_fixup
7315 HOST_WIDE_INT address
;
7317 enum machine_mode mode
;
7321 HOST_WIDE_INT forwards
;
7322 HOST_WIDE_INT backwards
;
7325 /* Fixes less than a word need padding out to a word boundary. */
7326 #define MINIPOOL_FIX_SIZE(mode) \
7327 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7329 static Mnode
* minipool_vector_head
;
7330 static Mnode
* minipool_vector_tail
;
7331 static rtx minipool_vector_label
;
7332 static int minipool_pad
;
7334 /* The linked list of all minipool fixes required for this function. */
7335 Mfix
* minipool_fix_head
;
7336 Mfix
* minipool_fix_tail
;
7337 /* The fix entry for the current minipool, once it has been placed. */
7338 Mfix
* minipool_barrier
;
7340 /* Determines if INSN is the start of a jump table. Returns the end
7341 of the TABLE or NULL_RTX. */
7343 is_jump_table (rtx insn
)
7347 if (GET_CODE (insn
) == JUMP_INSN
7348 && JUMP_LABEL (insn
) != NULL
7349 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
7350 == next_real_insn (insn
))
7352 && GET_CODE (table
) == JUMP_INSN
7353 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
7354 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
7360 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7361 #define JUMP_TABLES_IN_TEXT_SECTION 0
7364 static HOST_WIDE_INT
7365 get_jump_table_size (rtx insn
)
7367 /* ADDR_VECs only take room if read-only data does into the text
7369 if (JUMP_TABLES_IN_TEXT_SECTION
|| readonly_data_section
== text_section
)
7371 rtx body
= PATTERN (insn
);
7372 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7374 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
7380 /* Move a minipool fix MP from its current location to before MAX_MP.
7381 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7382 constraints may need updating. */
7384 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7385 HOST_WIDE_INT max_address
)
7387 /* The code below assumes these are different. */
7388 gcc_assert (mp
!= max_mp
);
7392 if (max_address
< mp
->max_address
)
7393 mp
->max_address
= max_address
;
7397 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7398 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7400 mp
->max_address
= max_address
;
7402 /* Unlink MP from its current position. Since max_mp is non-null,
7403 mp->prev must be non-null. */
7404 mp
->prev
->next
= mp
->next
;
7405 if (mp
->next
!= NULL
)
7406 mp
->next
->prev
= mp
->prev
;
7408 minipool_vector_tail
= mp
->prev
;
7410 /* Re-insert it before MAX_MP. */
7412 mp
->prev
= max_mp
->prev
;
7415 if (mp
->prev
!= NULL
)
7416 mp
->prev
->next
= mp
;
7418 minipool_vector_head
= mp
;
7421 /* Save the new entry. */
7424 /* Scan over the preceding entries and adjust their addresses as
7426 while (mp
->prev
!= NULL
7427 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7429 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7436 /* Add a constant to the minipool for a forward reference. Returns the
7437 node added or NULL if the constant will not fit in this pool. */
7439 add_minipool_forward_ref (Mfix
*fix
)
7441 /* If set, max_mp is the first pool_entry that has a lower
7442 constraint than the one we are trying to add. */
7443 Mnode
* max_mp
= NULL
;
7444 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
- minipool_pad
;
7447 /* If the minipool starts before the end of FIX->INSN then this FIX
7448 can not be placed into the current pool. Furthermore, adding the
7449 new constant pool entry may cause the pool to start FIX_SIZE bytes
7451 if (minipool_vector_head
&&
7452 (fix
->address
+ get_attr_length (fix
->insn
)
7453 >= minipool_vector_head
->max_address
- fix
->fix_size
))
7456 /* Scan the pool to see if a constant with the same value has
7457 already been added. While we are doing this, also note the
7458 location where we must insert the constant if it doesn't already
7460 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7462 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7463 && fix
->mode
== mp
->mode
7464 && (GET_CODE (fix
->value
) != CODE_LABEL
7465 || (CODE_LABEL_NUMBER (fix
->value
)
7466 == CODE_LABEL_NUMBER (mp
->value
)))
7467 && rtx_equal_p (fix
->value
, mp
->value
))
7469 /* More than one fix references this entry. */
7471 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7474 /* Note the insertion point if necessary. */
7476 && mp
->max_address
> max_address
)
7479 /* If we are inserting an 8-bytes aligned quantity and
7480 we have not already found an insertion point, then
7481 make sure that all such 8-byte aligned quantities are
7482 placed at the start of the pool. */
7483 if (ARM_DOUBLEWORD_ALIGN
7485 && fix
->fix_size
== 8
7486 && mp
->fix_size
!= 8)
7489 max_address
= mp
->max_address
;
7493 /* The value is not currently in the minipool, so we need to create
7494 a new entry for it. If MAX_MP is NULL, the entry will be put on
7495 the end of the list since the placement is less constrained than
7496 any existing entry. Otherwise, we insert the new fix before
7497 MAX_MP and, if necessary, adjust the constraints on the other
7500 mp
->fix_size
= fix
->fix_size
;
7501 mp
->mode
= fix
->mode
;
7502 mp
->value
= fix
->value
;
7504 /* Not yet required for a backwards ref. */
7505 mp
->min_address
= -65536;
7509 mp
->max_address
= max_address
;
7511 mp
->prev
= minipool_vector_tail
;
7513 if (mp
->prev
== NULL
)
7515 minipool_vector_head
= mp
;
7516 minipool_vector_label
= gen_label_rtx ();
7519 mp
->prev
->next
= mp
;
7521 minipool_vector_tail
= mp
;
7525 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7526 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7528 mp
->max_address
= max_address
;
7531 mp
->prev
= max_mp
->prev
;
7533 if (mp
->prev
!= NULL
)
7534 mp
->prev
->next
= mp
;
7536 minipool_vector_head
= mp
;
7539 /* Save the new entry. */
7542 /* Scan over the preceding entries and adjust their addresses as
7544 while (mp
->prev
!= NULL
7545 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7547 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7555 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7556 HOST_WIDE_INT min_address
)
7558 HOST_WIDE_INT offset
;
7560 /* The code below assumes these are different. */
7561 gcc_assert (mp
!= min_mp
);
7565 if (min_address
> mp
->min_address
)
7566 mp
->min_address
= min_address
;
7570 /* We will adjust this below if it is too loose. */
7571 mp
->min_address
= min_address
;
7573 /* Unlink MP from its current position. Since min_mp is non-null,
7574 mp->next must be non-null. */
7575 mp
->next
->prev
= mp
->prev
;
7576 if (mp
->prev
!= NULL
)
7577 mp
->prev
->next
= mp
->next
;
7579 minipool_vector_head
= mp
->next
;
7581 /* Reinsert it after MIN_MP. */
7583 mp
->next
= min_mp
->next
;
7585 if (mp
->next
!= NULL
)
7586 mp
->next
->prev
= mp
;
7588 minipool_vector_tail
= mp
;
7594 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7596 mp
->offset
= offset
;
7597 if (mp
->refcount
> 0)
7598 offset
+= mp
->fix_size
;
7600 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7601 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7607 /* Add a constant to the minipool for a backward reference. Returns the
7608 node added or NULL if the constant will not fit in this pool.
7610 Note that the code for insertion for a backwards reference can be
7611 somewhat confusing because the calculated offsets for each fix do
7612 not take into account the size of the pool (which is still under
7615 add_minipool_backward_ref (Mfix
*fix
)
7617 /* If set, min_mp is the last pool_entry that has a lower constraint
7618 than the one we are trying to add. */
7619 Mnode
*min_mp
= NULL
;
7620 /* This can be negative, since it is only a constraint. */
7621 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7624 /* If we can't reach the current pool from this insn, or if we can't
7625 insert this entry at the end of the pool without pushing other
7626 fixes out of range, then we don't try. This ensures that we
7627 can't fail later on. */
7628 if (min_address
>= minipool_barrier
->address
7629 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7630 >= minipool_barrier
->address
))
7633 /* Scan the pool to see if a constant with the same value has
7634 already been added. While we are doing this, also note the
7635 location where we must insert the constant if it doesn't already
7637 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7639 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7640 && fix
->mode
== mp
->mode
7641 && (GET_CODE (fix
->value
) != CODE_LABEL
7642 || (CODE_LABEL_NUMBER (fix
->value
)
7643 == CODE_LABEL_NUMBER (mp
->value
)))
7644 && rtx_equal_p (fix
->value
, mp
->value
)
7645 /* Check that there is enough slack to move this entry to the
7646 end of the table (this is conservative). */
7648 > (minipool_barrier
->address
7649 + minipool_vector_tail
->offset
7650 + minipool_vector_tail
->fix_size
)))
7653 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7657 mp
->min_address
+= fix
->fix_size
;
7660 /* Note the insertion point if necessary. */
7661 if (mp
->min_address
< min_address
)
7663 /* For now, we do not allow the insertion of 8-byte alignment
7664 requiring nodes anywhere but at the start of the pool. */
7665 if (ARM_DOUBLEWORD_ALIGN
7666 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7671 else if (mp
->max_address
7672 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7674 /* Inserting before this entry would push the fix beyond
7675 its maximum address (which can happen if we have
7676 re-located a forwards fix); force the new fix to come
7679 min_address
= mp
->min_address
+ fix
->fix_size
;
7681 /* If we are inserting an 8-bytes aligned quantity and
7682 we have not already found an insertion point, then
7683 make sure that all such 8-byte aligned quantities are
7684 placed at the start of the pool. */
7685 else if (ARM_DOUBLEWORD_ALIGN
7687 && fix
->fix_size
== 8
7688 && mp
->fix_size
< 8)
7691 min_address
= mp
->min_address
+ fix
->fix_size
;
7696 /* We need to create a new entry. */
7698 mp
->fix_size
= fix
->fix_size
;
7699 mp
->mode
= fix
->mode
;
7700 mp
->value
= fix
->value
;
7702 mp
->max_address
= minipool_barrier
->address
+ 65536;
7704 mp
->min_address
= min_address
;
7709 mp
->next
= minipool_vector_head
;
7711 if (mp
->next
== NULL
)
7713 minipool_vector_tail
= mp
;
7714 minipool_vector_label
= gen_label_rtx ();
7717 mp
->next
->prev
= mp
;
7719 minipool_vector_head
= mp
;
7723 mp
->next
= min_mp
->next
;
7727 if (mp
->next
!= NULL
)
7728 mp
->next
->prev
= mp
;
7730 minipool_vector_tail
= mp
;
7733 /* Save the new entry. */
7741 /* Scan over the following entries and adjust their offsets. */
7742 while (mp
->next
!= NULL
)
7744 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7745 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7748 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7750 mp
->next
->offset
= mp
->offset
;
7759 assign_minipool_offsets (Mfix
*barrier
)
7761 HOST_WIDE_INT offset
= 0;
7764 minipool_barrier
= barrier
;
7766 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7768 mp
->offset
= offset
;
7770 if (mp
->refcount
> 0)
7771 offset
+= mp
->fix_size
;
7775 /* Output the literal table */
7777 dump_minipool (rtx scan
)
7783 if (ARM_DOUBLEWORD_ALIGN
)
7784 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7785 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7793 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7794 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7796 scan
= emit_label_after (gen_label_rtx (), scan
);
7797 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7798 scan
= emit_label_after (minipool_vector_label
, scan
);
7800 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7802 if (mp
->refcount
> 0)
7807 ";; Offset %u, min %ld, max %ld ",
7808 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7809 (unsigned long) mp
->max_address
);
7810 arm_print_value (dump_file
, mp
->value
);
7811 fputc ('\n', dump_file
);
7814 switch (mp
->fix_size
)
7816 #ifdef HAVE_consttable_1
7818 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7822 #ifdef HAVE_consttable_2
7824 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7828 #ifdef HAVE_consttable_4
7830 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7834 #ifdef HAVE_consttable_8
7836 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7849 minipool_vector_head
= minipool_vector_tail
= NULL
;
7850 scan
= emit_insn_after (gen_consttable_end (), scan
);
7851 scan
= emit_barrier_after (scan
);
7854 /* Return the cost of forcibly inserting a barrier after INSN. */
7856 arm_barrier_cost (rtx insn
)
7858 /* Basing the location of the pool on the loop depth is preferable,
7859 but at the moment, the basic block information seems to be
7860 corrupt by this stage of the compilation. */
7862 rtx next
= next_nonnote_insn (insn
);
7864 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7867 switch (GET_CODE (insn
))
7870 /* It will always be better to place the table before the label, rather
7879 return base_cost
- 10;
7882 return base_cost
+ 10;
7886 /* Find the best place in the insn stream in the range
7887 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7888 Create the barrier by inserting a jump and add a new fix entry for
7891 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7893 HOST_WIDE_INT count
= 0;
7895 rtx from
= fix
->insn
;
7896 /* The instruction after which we will insert the jump. */
7897 rtx selected
= NULL
;
7899 /* The address at which the jump instruction will be placed. */
7900 HOST_WIDE_INT selected_address
;
7902 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7903 rtx label
= gen_label_rtx ();
7905 selected_cost
= arm_barrier_cost (from
);
7906 selected_address
= fix
->address
;
7908 while (from
&& count
< max_count
)
7913 /* This code shouldn't have been called if there was a natural barrier
7915 gcc_assert (GET_CODE (from
) != BARRIER
);
7917 /* Count the length of this insn. */
7918 count
+= get_attr_length (from
);
7920 /* If there is a jump table, add its length. */
7921 tmp
= is_jump_table (from
);
7924 count
+= get_jump_table_size (tmp
);
7926 /* Jump tables aren't in a basic block, so base the cost on
7927 the dispatch insn. If we select this location, we will
7928 still put the pool after the table. */
7929 new_cost
= arm_barrier_cost (from
);
7931 if (count
< max_count
7932 && (!selected
|| new_cost
<= selected_cost
))
7935 selected_cost
= new_cost
;
7936 selected_address
= fix
->address
+ count
;
7939 /* Continue after the dispatch table. */
7940 from
= NEXT_INSN (tmp
);
7944 new_cost
= arm_barrier_cost (from
);
7946 if (count
< max_count
7947 && (!selected
|| new_cost
<= selected_cost
))
7950 selected_cost
= new_cost
;
7951 selected_address
= fix
->address
+ count
;
7954 from
= NEXT_INSN (from
);
7957 /* Make sure that we found a place to insert the jump. */
7958 gcc_assert (selected
);
7960 /* Create a new JUMP_INSN that branches around a barrier. */
7961 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7962 JUMP_LABEL (from
) = label
;
7963 barrier
= emit_barrier_after (from
);
7964 emit_label_after (label
, barrier
);
7966 /* Create a minipool barrier entry for the new barrier. */
7967 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7968 new_fix
->insn
= barrier
;
7969 new_fix
->address
= selected_address
;
7970 new_fix
->next
= fix
->next
;
7971 fix
->next
= new_fix
;
7976 /* Record that there is a natural barrier in the insn stream at
7979 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7981 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7984 fix
->address
= address
;
7987 if (minipool_fix_head
!= NULL
)
7988 minipool_fix_tail
->next
= fix
;
7990 minipool_fix_head
= fix
;
7992 minipool_fix_tail
= fix
;
7995 /* Record INSN, which will need fixing up to load a value from the
7996 minipool. ADDRESS is the offset of the insn since the start of the
7997 function; LOC is a pointer to the part of the insn which requires
7998 fixing; VALUE is the constant that must be loaded, which is of type
8001 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
8002 enum machine_mode mode
, rtx value
)
8004 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
8006 #ifdef AOF_ASSEMBLER
8007 /* PIC symbol references need to be converted into offsets into the
8009 /* XXX This shouldn't be done here. */
8010 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
8011 value
= aof_pic_entry (value
);
8012 #endif /* AOF_ASSEMBLER */
8015 fix
->address
= address
;
8018 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
8020 fix
->forwards
= get_attr_pool_range (insn
);
8021 fix
->backwards
= get_attr_neg_pool_range (insn
);
8022 fix
->minipool
= NULL
;
8024 /* If an insn doesn't have a range defined for it, then it isn't
8025 expecting to be reworked by this code. Better to stop now than
8026 to generate duff assembly code. */
8027 gcc_assert (fix
->forwards
|| fix
->backwards
);
8029 /* If an entry requires 8-byte alignment then assume all constant pools
8030 require 4 bytes of padding. Trying to do this later on a per-pool
8031 basis is awkward because existing pool entries have to be modified. */
8032 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
8038 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8039 GET_MODE_NAME (mode
),
8040 INSN_UID (insn
), (unsigned long) address
,
8041 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
8042 arm_print_value (dump_file
, fix
->value
);
8043 fprintf (dump_file
, "\n");
8046 /* Add it to the chain of fixes. */
8049 if (minipool_fix_head
!= NULL
)
8050 minipool_fix_tail
->next
= fix
;
8052 minipool_fix_head
= fix
;
8054 minipool_fix_tail
= fix
;
8057 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8058 Returns the number of insns needed, or 99 if we don't know how to
8061 arm_const_double_inline_cost (rtx val
)
8063 rtx lowpart
, highpart
;
8064 enum machine_mode mode
;
8066 mode
= GET_MODE (val
);
8068 if (mode
== VOIDmode
)
8071 gcc_assert (GET_MODE_SIZE (mode
) == 8);
8073 lowpart
= gen_lowpart (SImode
, val
);
8074 highpart
= gen_highpart_mode (SImode
, mode
, val
);
8076 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
8077 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
8079 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
8080 NULL_RTX
, NULL_RTX
, 0, 0)
8081 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
8082 NULL_RTX
, NULL_RTX
, 0, 0));
8085 /* Return true if it is worthwhile to split a 64-bit constant into two
8086 32-bit operations. This is the case if optimizing for size, or
8087 if we have load delay slots, or if one 32-bit part can be done with
8088 a single data operation. */
8090 arm_const_double_by_parts (rtx val
)
8092 enum machine_mode mode
= GET_MODE (val
);
8095 if (optimize_size
|| arm_ld_sched
)
8098 if (mode
== VOIDmode
)
8101 part
= gen_highpart_mode (SImode
, mode
, val
);
8103 gcc_assert (GET_CODE (part
) == CONST_INT
);
8105 if (const_ok_for_arm (INTVAL (part
))
8106 || const_ok_for_arm (~INTVAL (part
)))
8109 part
= gen_lowpart (SImode
, val
);
8111 gcc_assert (GET_CODE (part
) == CONST_INT
);
8113 if (const_ok_for_arm (INTVAL (part
))
8114 || const_ok_for_arm (~INTVAL (part
)))
8120 /* Scan INSN and note any of its operands that need fixing.
8121 If DO_PUSHES is false we do not actually push any of the fixups
8122 needed. The function returns TRUE if any fixups were needed/pushed.
8123 This is used by arm_memory_load_p() which needs to know about loads
8124 of constants that will be converted into minipool loads. */
8126 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
8128 bool result
= false;
8131 extract_insn (insn
);
8133 if (!constrain_operands (1))
8134 fatal_insn_not_found (insn
);
8136 if (recog_data
.n_alternatives
== 0)
8139 /* Fill in recog_op_alt with information about the constraints of
8141 preprocess_constraints ();
8143 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8145 /* Things we need to fix can only occur in inputs. */
8146 if (recog_data
.operand_type
[opno
] != OP_IN
)
8149 /* If this alternative is a memory reference, then any mention
8150 of constants in this alternative is really to fool reload
8151 into allowing us to accept one there. We need to fix them up
8152 now so that we output the right code. */
8153 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
8155 rtx op
= recog_data
.operand
[opno
];
8157 if (CONSTANT_P (op
))
8160 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
8161 recog_data
.operand_mode
[opno
], op
);
8164 else if (GET_CODE (op
) == MEM
8165 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
8166 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
8170 rtx cop
= avoid_constant_pool_reference (op
);
8172 /* Casting the address of something to a mode narrower
8173 than a word can cause avoid_constant_pool_reference()
8174 to return the pool reference itself. That's no good to
8175 us here. Lets just hope that we can use the
8176 constant pool value directly. */
8178 cop
= get_pool_constant (XEXP (op
, 0));
8180 push_minipool_fix (insn
, address
,
8181 recog_data
.operand_loc
[opno
],
8182 recog_data
.operand_mode
[opno
], cop
);
8193 /* Gcc puts the pool in the wrong place for ARM, since we can only
8194 load addresses a limited distance around the pc. We do some
8195 special munging to move the constant pool values to the correct
8196 point in the code. */
8201 HOST_WIDE_INT address
= 0;
8204 minipool_fix_head
= minipool_fix_tail
= NULL
;
8206 /* The first insn must always be a note, or the code below won't
8207 scan it properly. */
8208 insn
= get_insns ();
8209 gcc_assert (GET_CODE (insn
) == NOTE
);
8212 /* Scan all the insns and record the operands that will need fixing. */
8213 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
8215 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8216 && (arm_cirrus_insn_p (insn
)
8217 || GET_CODE (insn
) == JUMP_INSN
8218 || arm_memory_load_p (insn
)))
8219 cirrus_reorg (insn
);
8221 if (GET_CODE (insn
) == BARRIER
)
8222 push_minipool_barrier (insn
, address
);
8223 else if (INSN_P (insn
))
8227 note_invalid_constants (insn
, address
, true);
8228 address
+= get_attr_length (insn
);
8230 /* If the insn is a vector jump, add the size of the table
8231 and skip the table. */
8232 if ((table
= is_jump_table (insn
)) != NULL
)
8234 address
+= get_jump_table_size (table
);
8240 fix
= minipool_fix_head
;
8242 /* Now scan the fixups and perform the required changes. */
8247 Mfix
* last_added_fix
;
8248 Mfix
* last_barrier
= NULL
;
8251 /* Skip any further barriers before the next fix. */
8252 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
8255 /* No more fixes. */
8259 last_added_fix
= NULL
;
8261 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
8263 if (GET_CODE (ftmp
->insn
) == BARRIER
)
8265 if (ftmp
->address
>= minipool_vector_head
->max_address
)
8268 last_barrier
= ftmp
;
8270 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
8273 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
8276 /* If we found a barrier, drop back to that; any fixes that we
8277 could have reached but come after the barrier will now go in
8278 the next mini-pool. */
8279 if (last_barrier
!= NULL
)
8281 /* Reduce the refcount for those fixes that won't go into this
8283 for (fdel
= last_barrier
->next
;
8284 fdel
&& fdel
!= ftmp
;
8287 fdel
->minipool
->refcount
--;
8288 fdel
->minipool
= NULL
;
8291 ftmp
= last_barrier
;
8295 /* ftmp is first fix that we can't fit into this pool and
8296 there no natural barriers that we could use. Insert a
8297 new barrier in the code somewhere between the previous
8298 fix and this one, and arrange to jump around it. */
8299 HOST_WIDE_INT max_address
;
8301 /* The last item on the list of fixes must be a barrier, so
8302 we can never run off the end of the list of fixes without
8303 last_barrier being set. */
8306 max_address
= minipool_vector_head
->max_address
;
8307 /* Check that there isn't another fix that is in range that
8308 we couldn't fit into this pool because the pool was
8309 already too large: we need to put the pool before such an
8310 instruction. The pool itself may come just after the
8311 fix because create_fix_barrier also allows space for a
8312 jump instruction. */
8313 if (ftmp
->address
< max_address
)
8314 max_address
= ftmp
->address
+ 1;
8316 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
8319 assign_minipool_offsets (last_barrier
);
8323 if (GET_CODE (ftmp
->insn
) != BARRIER
8324 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
8331 /* Scan over the fixes we have identified for this pool, fixing them
8332 up and adding the constants to the pool itself. */
8333 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
8334 this_fix
= this_fix
->next
)
8335 if (GET_CODE (this_fix
->insn
) != BARRIER
)
8338 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
8339 minipool_vector_label
),
8340 this_fix
->minipool
->offset
);
8341 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
8344 dump_minipool (last_barrier
->insn
);
8348 /* From now on we must synthesize any constants that we can't handle
8349 directly. This can happen if the RTL gets split during final
8350 instruction generation. */
8351 after_arm_reorg
= 1;
8353 /* Free the minipool memory. */
8354 obstack_free (&minipool_obstack
, minipool_startobj
);
8357 /* Routines to output assembly language. */
8359 /* If the rtx is the correct value then return the string of the number.
8360 In this way we can ensure that valid double constants are generated even
8361 when cross compiling. */
8363 fp_immediate_constant (rtx x
)
8368 if (!fp_consts_inited
)
8371 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8372 for (i
= 0; i
< 8; i
++)
8373 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8374 return strings_fp
[i
];
8379 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8381 fp_const_from_val (REAL_VALUE_TYPE
*r
)
8385 if (!fp_consts_inited
)
8388 for (i
= 0; i
< 8; i
++)
8389 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
8390 return strings_fp
[i
];
8395 /* Output the operands of a LDM/STM instruction to STREAM.
8396 MASK is the ARM register set mask of which only bits 0-15 are important.
8397 REG is the base register, either the frame pointer or the stack pointer,
8398 INSTR is the possibly suffixed load or store instruction. */
8401 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
8405 bool not_first
= FALSE
;
8407 fputc ('\t', stream
);
8408 asm_fprintf (stream
, instr
, reg
);
8409 fputs (", {", stream
);
8411 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8412 if (mask
& (1 << i
))
8415 fprintf (stream
, ", ");
8417 asm_fprintf (stream
, "%r", i
);
8421 fprintf (stream
, "}\n");
8425 /* Output a FLDMX instruction to STREAM.
8426 BASE if the register containing the address.
8427 REG and COUNT specify the register range.
8428 Extra registers may be added to avoid hardware bugs. */
8431 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
8435 /* Workaround ARM10 VFPr1 bug. */
8436 if (count
== 2 && !arm_arch6
)
8443 fputc ('\t', stream
);
8444 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
8446 for (i
= reg
; i
< reg
+ count
; i
++)
8449 fputs (", ", stream
);
8450 asm_fprintf (stream
, "d%d", i
);
8452 fputs ("}\n", stream
);
8457 /* Output the assembly for a store multiple. */
8460 vfp_output_fstmx (rtx
* operands
)
8467 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8468 p
= strlen (pattern
);
8470 gcc_assert (GET_CODE (operands
[1]) == REG
);
8472 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8473 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8475 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8477 strcpy (&pattern
[p
], "}");
8479 output_asm_insn (pattern
, operands
);
8484 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8485 number of bytes pushed. */
8488 vfp_emit_fstmx (int base_reg
, int count
)
8495 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8496 register pairs are stored by a store multiple insn. We avoid this
8497 by pushing an extra pair. */
8498 if (count
== 2 && !arm_arch6
)
8500 if (base_reg
== LAST_VFP_REGNUM
- 3)
8505 /* ??? The frame layout is implementation defined. We describe
8506 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8507 We really need some way of representing the whole block so that the
8508 unwinder can figure it out at runtime. */
8509 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8510 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8512 reg
= gen_rtx_REG (DFmode
, base_reg
);
8516 = gen_rtx_SET (VOIDmode
,
8517 gen_frame_mem (BLKmode
,
8518 gen_rtx_PRE_DEC (BLKmode
,
8519 stack_pointer_rtx
)),
8520 gen_rtx_UNSPEC (BLKmode
,
8524 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8525 plus_constant (stack_pointer_rtx
, -(count
* 8 + 4)));
8526 RTX_FRAME_RELATED_P (tmp
) = 1;
8527 XVECEXP (dwarf
, 0, 0) = tmp
;
8529 tmp
= gen_rtx_SET (VOIDmode
,
8530 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8532 RTX_FRAME_RELATED_P (tmp
) = 1;
8533 XVECEXP (dwarf
, 0, 1) = tmp
;
8535 for (i
= 1; i
< count
; i
++)
8537 reg
= gen_rtx_REG (DFmode
, base_reg
);
8539 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8541 tmp
= gen_rtx_SET (VOIDmode
,
8542 gen_frame_mem (DFmode
,
8543 plus_constant (stack_pointer_rtx
,
8546 RTX_FRAME_RELATED_P (tmp
) = 1;
8547 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8550 par
= emit_insn (par
);
8551 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8553 RTX_FRAME_RELATED_P (par
) = 1;
8555 return count
* 8 + 4;
8559 /* Output a 'call' insn. */
8561 output_call (rtx
*operands
)
8563 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8565 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8566 if (REGNO (operands
[0]) == LR_REGNUM
)
8568 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8569 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8572 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8574 if (TARGET_INTERWORK
|| arm_arch4t
)
8575 output_asm_insn ("bx%?\t%0", operands
);
8577 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8582 /* Output a 'call' insn that is a reference in memory. */
8584 output_call_mem (rtx
*operands
)
8586 if (TARGET_INTERWORK
&& !arm_arch5
)
8588 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8589 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8590 output_asm_insn ("bx%?\t%|ip", operands
);
8592 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8594 /* LR is used in the memory address. We load the address in the
8595 first instruction. It's safe to use IP as the target of the
8596 load since the call will kill it anyway. */
8597 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8599 output_asm_insn ("blx%?\t%|ip", operands
);
8602 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8604 output_asm_insn ("bx%?\t%|ip", operands
);
8606 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8611 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8612 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8619 /* Output a move from arm registers to an fpa registers.
8620 OPERANDS[0] is an fpa register.
8621 OPERANDS[1] is the first registers of an arm register pair. */
8623 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8625 int arm_reg0
= REGNO (operands
[1]);
8628 gcc_assert (arm_reg0
!= IP_REGNUM
);
8630 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8631 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8632 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8634 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8635 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8640 /* Output a move from an fpa register to arm registers.
8641 OPERANDS[0] is the first registers of an arm register pair.
8642 OPERANDS[1] is an fpa register. */
8644 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8646 int arm_reg0
= REGNO (operands
[0]);
8649 gcc_assert (arm_reg0
!= IP_REGNUM
);
8651 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8652 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8653 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8655 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8656 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8660 /* Output a move from arm registers to arm registers of a long double
8661 OPERANDS[0] is the destination.
8662 OPERANDS[1] is the source. */
8664 output_mov_long_double_arm_from_arm (rtx
*operands
)
8666 /* We have to be careful here because the two might overlap. */
8667 int dest_start
= REGNO (operands
[0]);
8668 int src_start
= REGNO (operands
[1]);
8672 if (dest_start
< src_start
)
8674 for (i
= 0; i
< 3; i
++)
8676 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8677 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8678 output_asm_insn ("mov%?\t%0, %1", ops
);
8683 for (i
= 2; i
>= 0; i
--)
8685 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8686 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8687 output_asm_insn ("mov%?\t%0, %1", ops
);
8695 /* Output a move from arm registers to an fpa registers.
8696 OPERANDS[0] is an fpa register.
8697 OPERANDS[1] is the first registers of an arm register pair. */
8699 output_mov_double_fpa_from_arm (rtx
*operands
)
8701 int arm_reg0
= REGNO (operands
[1]);
8704 gcc_assert (arm_reg0
!= IP_REGNUM
);
8706 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8707 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8708 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8709 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8713 /* Output a move from an fpa register to arm registers.
8714 OPERANDS[0] is the first registers of an arm register pair.
8715 OPERANDS[1] is an fpa register. */
8717 output_mov_double_arm_from_fpa (rtx
*operands
)
8719 int arm_reg0
= REGNO (operands
[0]);
8722 gcc_assert (arm_reg0
!= IP_REGNUM
);
8724 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8725 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8726 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8727 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8731 /* Output a move between double words.
8732 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8733 or MEM<-REG and all MEMs must be offsettable addresses. */
8735 output_move_double (rtx
*operands
)
8737 enum rtx_code code0
= GET_CODE (operands
[0]);
8738 enum rtx_code code1
= GET_CODE (operands
[1]);
8743 int reg0
= REGNO (operands
[0]);
8745 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8747 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
8749 switch (GET_CODE (XEXP (operands
[1], 0)))
8752 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8756 gcc_assert (TARGET_LDRD
);
8757 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8761 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8765 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8769 gcc_assert (TARGET_LDRD
);
8770 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8775 otherops
[0] = operands
[0];
8776 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8777 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8779 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8781 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8783 /* Registers overlap so split out the increment. */
8784 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8785 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8788 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8792 /* We only allow constant increments, so this is safe. */
8793 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8799 output_asm_insn ("adr%?\t%0, %1", operands
);
8800 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8804 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8805 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8807 otherops
[0] = operands
[0];
8808 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8809 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8811 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8813 if (GET_CODE (otherops
[2]) == CONST_INT
)
8815 switch ((int) INTVAL (otherops
[2]))
8818 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8821 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8824 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8829 && (GET_CODE (otherops
[2]) == REG
8830 || (GET_CODE (otherops
[2]) == CONST_INT
8831 && INTVAL (otherops
[2]) > -256
8832 && INTVAL (otherops
[2]) < 256)))
8834 if (reg_overlap_mentioned_p (otherops
[0],
8837 /* Swap base and index registers over to
8838 avoid a conflict. */
8839 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8840 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8842 /* If both registers conflict, it will usually
8843 have been fixed by a splitter. */
8844 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8846 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8847 output_asm_insn ("ldr%?d\t%0, [%1]",
8851 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops
);
8855 if (GET_CODE (otherops
[2]) == CONST_INT
)
8857 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8858 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8860 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8863 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8866 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8868 return "ldm%?ia\t%0, %M0";
8872 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8873 /* Take care of overlapping base/data reg. */
8874 if (reg_mentioned_p (operands
[0], operands
[1]))
8876 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8877 output_asm_insn ("ldr%?\t%0, %1", operands
);
8881 output_asm_insn ("ldr%?\t%0, %1", operands
);
8882 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8889 /* Constraints should ensure this. */
8890 gcc_assert (code0
== MEM
&& code1
== REG
);
8891 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
8893 switch (GET_CODE (XEXP (operands
[0], 0)))
8896 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8900 gcc_assert (TARGET_LDRD
);
8901 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8905 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8909 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8913 gcc_assert (TARGET_LDRD
);
8914 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8919 otherops
[0] = operands
[1];
8920 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8921 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8923 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8924 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8926 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8930 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8931 if (GET_CODE (otherops
[2]) == CONST_INT
)
8933 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8936 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8940 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8944 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8949 && (GET_CODE (otherops
[2]) == REG
8950 || (GET_CODE (otherops
[2]) == CONST_INT
8951 && INTVAL (otherops
[2]) > -256
8952 && INTVAL (otherops
[2]) < 256)))
8954 otherops
[0] = operands
[1];
8955 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8956 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8962 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8963 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8964 output_asm_insn ("str%?\t%1, %0", operands
);
8965 output_asm_insn ("str%?\t%1, %0", otherops
);
8972 /* Output an ADD r, s, #n where n may be too big for one instruction.
8973 If adding zero to one register, output nothing. */
8975 output_add_immediate (rtx
*operands
)
8977 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8979 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8982 output_multi_immediate (operands
,
8983 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8986 output_multi_immediate (operands
,
8987 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8994 /* Output a multiple immediate operation.
8995 OPERANDS is the vector of operands referred to in the output patterns.
8996 INSTR1 is the output pattern to use for the first constant.
8997 INSTR2 is the output pattern to use for subsequent constants.
8998 IMMED_OP is the index of the constant slot in OPERANDS.
8999 N is the constant value. */
9001 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
9002 int immed_op
, HOST_WIDE_INT n
)
9004 #if HOST_BITS_PER_WIDE_INT > 32
9010 /* Quick and easy output. */
9011 operands
[immed_op
] = const0_rtx
;
9012 output_asm_insn (instr1
, operands
);
9017 const char * instr
= instr1
;
9019 /* Note that n is never zero here (which would give no output). */
9020 for (i
= 0; i
< 32; i
+= 2)
9024 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
9025 output_asm_insn (instr
, operands
);
9035 /* Return the appropriate ARM instruction for the operation code.
9036 The returned result should not be overwritten. OP is the rtx of the
9037 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9040 arithmetic_instr (rtx op
, int shift_first_arg
)
9042 switch (GET_CODE (op
))
9048 return shift_first_arg
? "rsb" : "sub";
9064 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9065 for the operation code. The returned result should not be overwritten.
9066 OP is the rtx code of the shift.
9067 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9070 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
9073 enum rtx_code code
= GET_CODE (op
);
9075 switch (GET_CODE (XEXP (op
, 1)))
9083 *amountp
= INTVAL (XEXP (op
, 1));
9105 gcc_assert (*amountp
!= -1);
9106 *amountp
= 32 - *amountp
;
9115 /* We never have to worry about the amount being other than a
9116 power of 2, since this case can never be reloaded from a reg. */
9117 gcc_assert (*amountp
!= -1);
9118 *amountp
= int_log2 (*amountp
);
9127 /* This is not 100% correct, but follows from the desire to merge
9128 multiplication by a power of 2 with the recognizer for a
9129 shift. >=32 is not a valid shift for "asl", so we must try and
9130 output a shift that produces the correct arithmetical result.
9131 Using lsr #32 is identical except for the fact that the carry bit
9132 is not set correctly if we set the flags; but we never use the
9133 carry bit from such an operation, so we can ignore that. */
9134 if (code
== ROTATERT
)
9135 /* Rotate is just modulo 32. */
9137 else if (*amountp
!= (*amountp
& 31))
9144 /* Shifts of 0 are no-ops. */
9152 /* Obtain the shift from the POWER of two. */
9154 static HOST_WIDE_INT
9155 int_log2 (HOST_WIDE_INT power
)
9157 HOST_WIDE_INT shift
= 0;
9159 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
9161 gcc_assert (shift
<= 31);
9168 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9169 because /bin/as is horribly restrictive. The judgement about
9170 whether or not each character is 'printable' (and can be output as
9171 is) or not (and must be printed with an octal escape) must be made
9172 with reference to the *host* character set -- the situation is
9173 similar to that discussed in the comments above pp_c_char in
9174 c-pretty-print.c. */
9176 #define MAX_ASCII_LEN 51
9179 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
9184 fputs ("\t.ascii\t\"", stream
);
9186 for (i
= 0; i
< len
; i
++)
9190 if (len_so_far
>= MAX_ASCII_LEN
)
9192 fputs ("\"\n\t.ascii\t\"", stream
);
9198 if (c
== '\\' || c
== '\"')
9200 putc ('\\', stream
);
9208 fprintf (stream
, "\\%03o", c
);
9213 fputs ("\"\n", stream
);
9216 /* Compute the register save mask for registers 0 through 12
9217 inclusive. This code is used by arm_compute_save_reg_mask. */
9219 static unsigned long
9220 arm_compute_save_reg0_reg12_mask (void)
9222 unsigned long func_type
= arm_current_func_type ();
9223 unsigned long save_reg_mask
= 0;
9226 if (IS_INTERRUPT (func_type
))
9228 unsigned int max_reg
;
9229 /* Interrupt functions must not corrupt any registers,
9230 even call clobbered ones. If this is a leaf function
9231 we can just examine the registers used by the RTL, but
9232 otherwise we have to assume that whatever function is
9233 called might clobber anything, and so we have to save
9234 all the call-clobbered registers as well. */
9235 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9236 /* FIQ handlers have registers r8 - r12 banked, so
9237 we only need to check r0 - r7, Normal ISRs only
9238 bank r14 and r15, so we must check up to r12.
9239 r13 is the stack pointer which is always preserved,
9240 so we do not need to consider it here. */
9245 for (reg
= 0; reg
<= max_reg
; reg
++)
9246 if (regs_ever_live
[reg
]
9247 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9248 save_reg_mask
|= (1 << reg
);
9250 /* Also save the pic base register if necessary. */
9252 && !TARGET_SINGLE_PIC_BASE
9253 && arm_pic_register
!= INVALID_REGNUM
9254 && current_function_uses_pic_offset_table
)
9255 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9259 /* In the normal case we only need to save those registers
9260 which are call saved and which are used by this function. */
9261 for (reg
= 0; reg
<= 10; reg
++)
9262 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9263 save_reg_mask
|= (1 << reg
);
9265 /* Handle the frame pointer as a special case. */
9266 if (! TARGET_APCS_FRAME
9267 && ! frame_pointer_needed
9268 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9269 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9270 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9272 /* If we aren't loading the PIC register,
9273 don't stack it even though it may be live. */
9275 && !TARGET_SINGLE_PIC_BASE
9276 && arm_pic_register
!= INVALID_REGNUM
9277 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
9278 || current_function_uses_pic_offset_table
))
9279 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9282 /* Save registers so the exception handler can modify them. */
9283 if (current_function_calls_eh_return
)
9289 reg
= EH_RETURN_DATA_REGNO (i
);
9290 if (reg
== INVALID_REGNUM
)
9292 save_reg_mask
|= 1 << reg
;
9296 return save_reg_mask
;
9299 /* Compute a bit mask of which registers need to be
9300 saved on the stack for the current function. */
9302 static unsigned long
9303 arm_compute_save_reg_mask (void)
9305 unsigned int save_reg_mask
= 0;
9306 unsigned long func_type
= arm_current_func_type ();
9308 if (IS_NAKED (func_type
))
9309 /* This should never really happen. */
9312 /* If we are creating a stack frame, then we must save the frame pointer,
9313 IP (which will hold the old stack pointer), LR and the PC. */
9314 if (frame_pointer_needed
)
9316 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9321 /* Volatile functions do not return, so there
9322 is no need to save any other registers. */
9323 if (IS_VOLATILE (func_type
))
9324 return save_reg_mask
;
9326 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9328 /* Decide if we need to save the link register.
9329 Interrupt routines have their own banked link register,
9330 so they never need to save it.
9331 Otherwise if we do not use the link register we do not need to save
9332 it. If we are pushing other registers onto the stack however, we
9333 can save an instruction in the epilogue by pushing the link register
9334 now and then popping it back into the PC. This incurs extra memory
9335 accesses though, so we only do it when optimizing for size, and only
9336 if we know that we will not need a fancy return sequence. */
9337 if (regs_ever_live
[LR_REGNUM
]
9340 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9341 && !current_function_calls_eh_return
))
9342 save_reg_mask
|= 1 << LR_REGNUM
;
9344 if (cfun
->machine
->lr_save_eliminated
)
9345 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9347 if (TARGET_REALLY_IWMMXT
9348 && ((bit_count (save_reg_mask
)
9349 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9353 /* The total number of registers that are going to be pushed
9354 onto the stack is odd. We need to ensure that the stack
9355 is 64-bit aligned before we start to save iWMMXt registers,
9356 and also before we start to create locals. (A local variable
9357 might be a double or long long which we will load/store using
9358 an iWMMXt instruction). Therefore we need to push another
9359 ARM register, so that the stack will be 64-bit aligned. We
9360 try to avoid using the arg registers (r0 -r3) as they might be
9361 used to pass values in a tail call. */
9362 for (reg
= 4; reg
<= 12; reg
++)
9363 if ((save_reg_mask
& (1 << reg
)) == 0)
9367 save_reg_mask
|= (1 << reg
);
9370 cfun
->machine
->sibcall_blocked
= 1;
9371 save_reg_mask
|= (1 << 3);
9375 return save_reg_mask
;
9379 /* Compute a bit mask of which registers need to be
9380 saved on the stack for the current function. */
9381 static unsigned long
9382 thumb_compute_save_reg_mask (void)
9388 for (reg
= 0; reg
< 12; reg
++)
9389 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9393 && !TARGET_SINGLE_PIC_BASE
9394 && arm_pic_register
!= INVALID_REGNUM
9395 && current_function_uses_pic_offset_table
)
9396 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9398 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9399 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
9400 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
9402 /* LR will also be pushed if any lo regs are pushed. */
9403 if (mask
& 0xff || thumb_force_lr_save ())
9404 mask
|= (1 << LR_REGNUM
);
9406 /* Make sure we have a low work register if we need one.
9407 We will need one if we are going to push a high register,
9408 but we are not currently intending to push a low register. */
9409 if ((mask
& 0xff) == 0
9410 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9412 /* Use thumb_find_work_register to choose which register
9413 we will use. If the register is live then we will
9414 have to push it. Use LAST_LO_REGNUM as our fallback
9415 choice for the register to select. */
9416 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9418 if (! call_used_regs
[reg
])
9426 /* Return the number of bytes required to save VFP registers. */
9428 arm_get_vfp_saved_size (void)
9435 /* Space for saved VFP registers. */
9436 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9439 for (regno
= FIRST_VFP_REGNUM
;
9440 regno
< LAST_VFP_REGNUM
;
9443 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9444 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9448 /* Workaround ARM10 VFPr1 bug. */
9449 if (count
== 2 && !arm_arch6
)
9451 saved
+= count
* 8 + 4;
9460 if (count
== 2 && !arm_arch6
)
9462 saved
+= count
* 8 + 4;
9469 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9470 everything bar the final return instruction. */
9472 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9474 char conditional
[10];
9477 unsigned long live_regs_mask
;
9478 unsigned long func_type
;
9479 arm_stack_offsets
*offsets
;
9481 func_type
= arm_current_func_type ();
9483 if (IS_NAKED (func_type
))
9486 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9488 /* If this function was declared non-returning, and we have
9489 found a tail call, then we have to trust that the called
9490 function won't return. */
9495 /* Otherwise, trap an attempted return by aborting. */
9497 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9499 assemble_external_libcall (ops
[1]);
9500 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9506 gcc_assert (!current_function_calls_alloca
|| really_return
);
9508 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9510 return_used_this_function
= 1;
9512 live_regs_mask
= arm_compute_save_reg_mask ();
9516 const char * return_reg
;
9518 /* If we do not have any special requirements for function exit
9519 (e.g. interworking, or ISR) then we can load the return address
9520 directly into the PC. Otherwise we must load it into LR. */
9522 && ! TARGET_INTERWORK
)
9523 return_reg
= reg_names
[PC_REGNUM
];
9525 return_reg
= reg_names
[LR_REGNUM
];
9527 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9529 /* There are three possible reasons for the IP register
9530 being saved. 1) a stack frame was created, in which case
9531 IP contains the old stack pointer, or 2) an ISR routine
9532 corrupted it, or 3) it was saved to align the stack on
9533 iWMMXt. In case 1, restore IP into SP, otherwise just
9535 if (frame_pointer_needed
)
9537 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9538 live_regs_mask
|= (1 << SP_REGNUM
);
9541 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9544 /* On some ARM architectures it is faster to use LDR rather than
9545 LDM to load a single register. On other architectures, the
9546 cost is the same. In 26 bit mode, or for exception handlers,
9547 we have to use LDM to load the PC so that the CPSR is also
9549 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9550 if (live_regs_mask
== (1U << reg
))
9553 if (reg
<= LAST_ARM_REGNUM
9554 && (reg
!= LR_REGNUM
9556 || ! IS_INTERRUPT (func_type
)))
9558 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9559 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9566 /* Generate the load multiple instruction to restore the
9567 registers. Note we can get here, even if
9568 frame_pointer_needed is true, but only if sp already
9569 points to the base of the saved core registers. */
9570 if (live_regs_mask
& (1 << SP_REGNUM
))
9572 unsigned HOST_WIDE_INT stack_adjust
;
9574 offsets
= arm_get_frame_offsets ();
9575 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9576 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
9578 if (stack_adjust
&& arm_arch5
)
9579 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9582 /* If we can't use ldmib (SA110 bug),
9583 then try to pop r3 instead. */
9585 live_regs_mask
|= 1 << 3;
9586 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9590 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9592 p
= instr
+ strlen (instr
);
9594 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9595 if (live_regs_mask
& (1 << reg
))
9597 int l
= strlen (reg_names
[reg
]);
9603 memcpy (p
, ", ", 2);
9607 memcpy (p
, "%|", 2);
9608 memcpy (p
+ 2, reg_names
[reg
], l
);
9612 if (live_regs_mask
& (1 << LR_REGNUM
))
9614 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9615 /* If returning from an interrupt, restore the CPSR. */
9616 if (IS_INTERRUPT (func_type
))
9623 output_asm_insn (instr
, & operand
);
9625 /* See if we need to generate an extra instruction to
9626 perform the actual function return. */
9628 && func_type
!= ARM_FT_INTERWORKED
9629 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9631 /* The return has already been handled
9632 by loading the LR into the PC. */
9639 switch ((int) ARM_FUNC_TYPE (func_type
))
9643 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9646 case ARM_FT_INTERWORKED
:
9647 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9650 case ARM_FT_EXCEPTION
:
9651 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9655 /* Use bx if it's available. */
9656 if (arm_arch5
|| arm_arch4t
)
9657 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9659 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9663 output_asm_insn (instr
, & operand
);
9669 /* Write the function name into the code section, directly preceding
9670 the function prologue.
9672 Code will be output similar to this:
9674 .ascii "arm_poke_function_name", 0
9677 .word 0xff000000 + (t1 - t0)
9678 arm_poke_function_name
9680 stmfd sp!, {fp, ip, lr, pc}
9683 When performing a stack backtrace, code can inspect the value
9684 of 'pc' stored at 'fp' + 0. If the trace function then looks
9685 at location pc - 12 and the top 8 bits are set, then we know
9686 that there is a function name embedded immediately preceding this
9687 location and has length ((pc[-3]) & 0xff000000).
9689 We assume that pc is declared as a pointer to an unsigned long.
9691 It is of no benefit to output the function name if we are assembling
9692 a leaf function. These function types will not contain a stack
9693 backtrace structure, therefore it is not possible to determine the
9696 arm_poke_function_name (FILE *stream
, const char *name
)
9698 unsigned long alignlength
;
9699 unsigned long length
;
9702 length
= strlen (name
) + 1;
9703 alignlength
= ROUND_UP_WORD (length
);
9705 ASM_OUTPUT_ASCII (stream
, name
, length
);
9706 ASM_OUTPUT_ALIGN (stream
, 2);
9707 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9708 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9711 /* Place some comments into the assembler stream
9712 describing the current function. */
9714 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9716 unsigned long func_type
;
9720 thumb_output_function_prologue (f
, frame_size
);
9725 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
9727 func_type
= arm_current_func_type ();
9729 switch ((int) ARM_FUNC_TYPE (func_type
))
9734 case ARM_FT_INTERWORKED
:
9735 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9738 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9741 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9743 case ARM_FT_EXCEPTION
:
9744 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9748 if (IS_NAKED (func_type
))
9749 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9751 if (IS_VOLATILE (func_type
))
9752 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9754 if (IS_NESTED (func_type
))
9755 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9757 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9758 current_function_args_size
,
9759 current_function_pretend_args_size
, frame_size
);
9761 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9762 frame_pointer_needed
,
9763 cfun
->machine
->uses_anonymous_args
);
9765 if (cfun
->machine
->lr_save_eliminated
)
9766 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9768 if (current_function_calls_eh_return
)
9769 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9771 #ifdef AOF_ASSEMBLER
9773 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9776 return_used_this_function
= 0;
9780 arm_output_epilogue (rtx sibling
)
9783 unsigned long saved_regs_mask
;
9784 unsigned long func_type
;
9785 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9786 frame that is $fp + 4 for a non-variadic function. */
9787 int floats_offset
= 0;
9789 FILE * f
= asm_out_file
;
9790 unsigned int lrm_count
= 0;
9791 int really_return
= (sibling
== NULL
);
9793 arm_stack_offsets
*offsets
;
9795 /* If we have already generated the return instruction
9796 then it is futile to generate anything else. */
9797 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9800 func_type
= arm_current_func_type ();
9802 if (IS_NAKED (func_type
))
9803 /* Naked functions don't have epilogues. */
9806 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9810 /* A volatile function should never return. Call abort. */
9811 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9812 assemble_external_libcall (op
);
9813 output_asm_insn ("bl\t%a0", &op
);
9818 /* If we are throwing an exception, then we really must be doing a
9819 return, so we can't tail-call. */
9820 gcc_assert (!current_function_calls_eh_return
|| really_return
);
9822 offsets
= arm_get_frame_offsets ();
9823 saved_regs_mask
= arm_compute_save_reg_mask ();
9826 lrm_count
= bit_count (saved_regs_mask
);
9828 floats_offset
= offsets
->saved_args
;
9829 /* Compute how far away the floats will be. */
9830 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9831 if (saved_regs_mask
& (1 << reg
))
9834 if (frame_pointer_needed
)
9836 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9837 int vfp_offset
= offsets
->frame
;
9839 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9841 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9842 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9844 floats_offset
+= 12;
9845 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9846 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9851 start_reg
= LAST_FPA_REGNUM
;
9853 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9855 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9857 floats_offset
+= 12;
9859 /* We can't unstack more than four registers at once. */
9860 if (start_reg
- reg
== 3)
9862 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9863 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9864 start_reg
= reg
- 1;
9869 if (reg
!= start_reg
)
9870 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9871 reg
+ 1, start_reg
- reg
,
9872 FP_REGNUM
, floats_offset
- vfp_offset
);
9873 start_reg
= reg
- 1;
9877 /* Just in case the last register checked also needs unstacking. */
9878 if (reg
!= start_reg
)
9879 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9880 reg
+ 1, start_reg
- reg
,
9881 FP_REGNUM
, floats_offset
- vfp_offset
);
9884 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9888 /* The fldmx insn does not have base+offset addressing modes,
9889 so we use IP to hold the address. */
9890 saved_size
= arm_get_vfp_saved_size ();
9894 floats_offset
+= saved_size
;
9895 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9896 FP_REGNUM
, floats_offset
- vfp_offset
);
9898 start_reg
= FIRST_VFP_REGNUM
;
9899 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9901 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9902 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9904 if (start_reg
!= reg
)
9905 arm_output_fldmx (f
, IP_REGNUM
,
9906 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9907 (reg
- start_reg
) / 2);
9908 start_reg
= reg
+ 2;
9911 if (start_reg
!= reg
)
9912 arm_output_fldmx (f
, IP_REGNUM
,
9913 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9914 (reg
- start_reg
) / 2);
9919 /* The frame pointer is guaranteed to be non-double-word aligned.
9920 This is because it is set to (old_stack_pointer - 4) and the
9921 old_stack_pointer was double word aligned. Thus the offset to
9922 the iWMMXt registers to be loaded must also be non-double-word
9923 sized, so that the resultant address *is* double-word aligned.
9924 We can ignore floats_offset since that was already included in
9925 the live_regs_mask. */
9926 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9928 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9929 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9931 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9932 reg
, FP_REGNUM
, lrm_count
* 4);
9937 /* saved_regs_mask should contain the IP, which at the time of stack
9938 frame generation actually contains the old stack pointer. So a
9939 quick way to unwind the stack is just pop the IP register directly
9940 into the stack pointer. */
9941 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
9942 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9943 saved_regs_mask
|= (1 << SP_REGNUM
);
9945 /* There are two registers left in saved_regs_mask - LR and PC. We
9946 only need to restore the LR register (the return address), but to
9947 save time we can load it directly into the PC, unless we need a
9948 special function exit sequence, or we are not really returning. */
9950 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9951 && !current_function_calls_eh_return
)
9952 /* Delete the LR from the register mask, so that the LR on
9953 the stack is loaded into the PC in the register mask. */
9954 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9956 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9958 /* We must use SP as the base register, because SP is one of the
9959 registers being restored. If an interrupt or page fault
9960 happens in the ldm instruction, the SP might or might not
9961 have been restored. That would be bad, as then SP will no
9962 longer indicate the safe area of stack, and we can get stack
9963 corruption. Using SP as the base register means that it will
9964 be reset correctly to the original value, should an interrupt
9965 occur. If the stack pointer already points at the right
9966 place, then omit the subtraction. */
9967 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9968 || current_function_calls_alloca
)
9969 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9970 4 * bit_count (saved_regs_mask
));
9971 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9973 if (IS_INTERRUPT (func_type
))
9974 /* Interrupt handlers will have pushed the
9975 IP onto the stack, so restore it now. */
9976 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9980 /* Restore stack pointer if necessary. */
9981 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9983 operands
[0] = operands
[1] = stack_pointer_rtx
;
9984 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9985 output_add_immediate (operands
);
9988 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9990 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9991 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9992 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9997 start_reg
= FIRST_FPA_REGNUM
;
9999 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
10001 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10003 if (reg
- start_reg
== 3)
10005 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
10006 start_reg
, SP_REGNUM
);
10007 start_reg
= reg
+ 1;
10012 if (reg
!= start_reg
)
10013 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
10014 start_reg
, reg
- start_reg
,
10017 start_reg
= reg
+ 1;
10021 /* Just in case the last register checked also needs unstacking. */
10022 if (reg
!= start_reg
)
10023 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
10024 start_reg
, reg
- start_reg
, SP_REGNUM
);
10027 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10029 start_reg
= FIRST_VFP_REGNUM
;
10030 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10032 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10033 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10035 if (start_reg
!= reg
)
10036 arm_output_fldmx (f
, SP_REGNUM
,
10037 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10038 (reg
- start_reg
) / 2);
10039 start_reg
= reg
+ 2;
10042 if (start_reg
!= reg
)
10043 arm_output_fldmx (f
, SP_REGNUM
,
10044 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10045 (reg
- start_reg
) / 2);
10048 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
10049 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10050 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
10052 /* If we can, restore the LR into the PC. */
10053 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
10055 && current_function_pretend_args_size
== 0
10056 && saved_regs_mask
& (1 << LR_REGNUM
)
10057 && !current_function_calls_eh_return
)
10059 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
10060 saved_regs_mask
|= (1 << PC_REGNUM
);
10063 /* Load the registers off the stack. If we only have one register
10064 to load use the LDR instruction - it is faster. */
10065 if (saved_regs_mask
== (1 << LR_REGNUM
))
10067 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
10069 else if (saved_regs_mask
)
10071 if (saved_regs_mask
& (1 << SP_REGNUM
))
10072 /* Note - write back to the stack register is not enabled
10073 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10074 in the list of registers and if we add writeback the
10075 instruction becomes UNPREDICTABLE. */
10076 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
10078 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
10081 if (current_function_pretend_args_size
)
10083 /* Unwind the pre-pushed regs. */
10084 operands
[0] = operands
[1] = stack_pointer_rtx
;
10085 operands
[2] = GEN_INT (current_function_pretend_args_size
);
10086 output_add_immediate (operands
);
10090 /* We may have already restored PC directly from the stack. */
10091 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
10094 /* Stack adjustment for exception handler. */
10095 if (current_function_calls_eh_return
)
10096 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
10097 ARM_EH_STACKADJ_REGNUM
);
10099 /* Generate the return instruction. */
10100 switch ((int) ARM_FUNC_TYPE (func_type
))
10104 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
10107 case ARM_FT_EXCEPTION
:
10108 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10111 case ARM_FT_INTERWORKED
:
10112 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10116 if (arm_arch5
|| arm_arch4t
)
10117 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10119 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10127 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10128 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
10130 arm_stack_offsets
*offsets
;
10136 /* Emit any call-via-reg trampolines that are needed for v4t support
10137 of call_reg and call_value_reg type insns. */
10138 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
10140 rtx label
= cfun
->machine
->call_via
[regno
];
10144 switch_to_section (function_section (current_function_decl
));
10145 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10146 CODE_LABEL_NUMBER (label
));
10147 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
10151 /* ??? Probably not safe to set this here, since it assumes that a
10152 function will be emitted as assembly immediately after we generate
10153 RTL for it. This does not happen for inline functions. */
10154 return_used_this_function
= 0;
10158 /* We need to take into account any stack-frame rounding. */
10159 offsets
= arm_get_frame_offsets ();
10161 gcc_assert (!use_return_insn (FALSE
, NULL
)
10162 || !return_used_this_function
10163 || offsets
->saved_regs
== offsets
->outgoing_args
10164 || frame_pointer_needed
);
10166 /* Reset the ARM-specific per-function variables. */
10167 after_arm_reorg
= 0;
10171 /* Generate and emit an insn that we will recognize as a push_multi.
10172 Unfortunately, since this insn does not reflect very well the actual
10173 semantics of the operation, we need to annotate the insn for the benefit
10174 of DWARF2 frame unwind information. */
10176 emit_multi_reg_push (unsigned long mask
)
10179 int num_dwarf_regs
;
10183 int dwarf_par_index
;
10186 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10187 if (mask
& (1 << i
))
10190 gcc_assert (num_regs
&& num_regs
<= 16);
10192 /* We don't record the PC in the dwarf frame information. */
10193 num_dwarf_regs
= num_regs
;
10194 if (mask
& (1 << PC_REGNUM
))
10197 /* For the body of the insn we are going to generate an UNSPEC in
10198 parallel with several USEs. This allows the insn to be recognized
10199 by the push_multi pattern in the arm.md file. The insn looks
10200 something like this:
10203 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10204 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10205 (use (reg:SI 11 fp))
10206 (use (reg:SI 12 ip))
10207 (use (reg:SI 14 lr))
10208 (use (reg:SI 15 pc))
10211 For the frame note however, we try to be more explicit and actually
10212 show each register being stored into the stack frame, plus a (single)
10213 decrement of the stack pointer. We do it this way in order to be
10214 friendly to the stack unwinding code, which only wants to see a single
10215 stack decrement per instruction. The RTL we generate for the note looks
10216 something like this:
10219 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10220 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10221 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10222 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10223 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10226 This sequence is used both by the code to support stack unwinding for
10227 exceptions handlers and the code to generate dwarf2 frame debugging. */
10229 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10230 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10231 dwarf_par_index
= 1;
10233 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10235 if (mask
& (1 << i
))
10237 reg
= gen_rtx_REG (SImode
, i
);
10239 XVECEXP (par
, 0, 0)
10240 = gen_rtx_SET (VOIDmode
,
10241 gen_frame_mem (BLKmode
,
10242 gen_rtx_PRE_DEC (BLKmode
,
10243 stack_pointer_rtx
)),
10244 gen_rtx_UNSPEC (BLKmode
,
10245 gen_rtvec (1, reg
),
10246 UNSPEC_PUSH_MULT
));
10248 if (i
!= PC_REGNUM
)
10250 tmp
= gen_rtx_SET (VOIDmode
,
10251 gen_frame_mem (SImode
, stack_pointer_rtx
),
10253 RTX_FRAME_RELATED_P (tmp
) = 1;
10254 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10262 for (j
= 1, i
++; j
< num_regs
; i
++)
10264 if (mask
& (1 << i
))
10266 reg
= gen_rtx_REG (SImode
, i
);
10268 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10270 if (i
!= PC_REGNUM
)
10273 = gen_rtx_SET (VOIDmode
,
10274 gen_frame_mem (SImode
,
10275 plus_constant (stack_pointer_rtx
,
10278 RTX_FRAME_RELATED_P (tmp
) = 1;
10279 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10286 par
= emit_insn (par
);
10288 tmp
= gen_rtx_SET (VOIDmode
,
10290 plus_constant (stack_pointer_rtx
, -4 * num_regs
));
10291 RTX_FRAME_RELATED_P (tmp
) = 1;
10292 XVECEXP (dwarf
, 0, 0) = tmp
;
10294 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10299 /* Calculate the size of the return value that is passed in registers. */
10301 arm_size_return_regs (void)
10303 enum machine_mode mode
;
10305 if (current_function_return_rtx
!= 0)
10306 mode
= GET_MODE (current_function_return_rtx
);
10308 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10310 return GET_MODE_SIZE (mode
);
10314 emit_sfm (int base_reg
, int count
)
10321 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10322 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10324 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10326 XVECEXP (par
, 0, 0)
10327 = gen_rtx_SET (VOIDmode
,
10328 gen_frame_mem (BLKmode
,
10329 gen_rtx_PRE_DEC (BLKmode
,
10330 stack_pointer_rtx
)),
10331 gen_rtx_UNSPEC (BLKmode
,
10332 gen_rtvec (1, reg
),
10333 UNSPEC_PUSH_MULT
));
10334 tmp
= gen_rtx_SET (VOIDmode
,
10335 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
10336 RTX_FRAME_RELATED_P (tmp
) = 1;
10337 XVECEXP (dwarf
, 0, 1) = tmp
;
10339 for (i
= 1; i
< count
; i
++)
10341 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10342 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10344 tmp
= gen_rtx_SET (VOIDmode
,
10345 gen_frame_mem (XFmode
,
10346 plus_constant (stack_pointer_rtx
,
10349 RTX_FRAME_RELATED_P (tmp
) = 1;
10350 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10353 tmp
= gen_rtx_SET (VOIDmode
,
10355 plus_constant (stack_pointer_rtx
, -12 * count
));
10357 RTX_FRAME_RELATED_P (tmp
) = 1;
10358 XVECEXP (dwarf
, 0, 0) = tmp
;
10360 par
= emit_insn (par
);
10361 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10367 /* Return true if the current function needs to save/restore LR. */
10370 thumb_force_lr_save (void)
10372 return !cfun
->machine
->lr_save_eliminated
10373 && (!leaf_function_p ()
10374 || thumb_far_jump_used_p ()
10375 || regs_ever_live
[LR_REGNUM
]);
10379 /* Compute the distance from register FROM to register TO.
10380 These can be the arg pointer (26), the soft frame pointer (25),
10381 the stack pointer (13) or the hard frame pointer (11).
10382 In thumb mode r7 is used as the soft frame pointer, if needed.
10383 Typical stack layout looks like this:
10385 old stack pointer -> | |
10388 | | saved arguments for
10389 | | vararg functions
10392 hard FP & arg pointer -> | | \
10400 soft frame pointer -> | | /
10405 locals base pointer -> | | /
10410 current stack pointer -> | | /
10413 For a given function some or all of these stack components
10414 may not be needed, giving rise to the possibility of
10415 eliminating some of the registers.
10417 The values returned by this function must reflect the behavior
10418 of arm_expand_prologue() and arm_compute_save_reg_mask().
10420 The sign of the number returned reflects the direction of stack
10421 growth, so the values are positive for all eliminations except
10422 from the soft frame pointer to the hard frame pointer.
10424 SFP may point just inside the local variables block to ensure correct
10428 /* Calculate stack offsets. These are used to calculate register elimination
10429 offsets and in prologue/epilogue code. */
10431 static arm_stack_offsets
*
10432 arm_get_frame_offsets (void)
10434 struct arm_stack_offsets
*offsets
;
10435 unsigned long func_type
;
10438 HOST_WIDE_INT frame_size
;
10440 offsets
= &cfun
->machine
->stack_offsets
;
10442 /* We need to know if we are a leaf function. Unfortunately, it
10443 is possible to be called after start_sequence has been called,
10444 which causes get_insns to return the insns for the sequence,
10445 not the function, which will cause leaf_function_p to return
10446 the incorrect result.
10448 to know about leaf functions once reload has completed, and the
10449 frame size cannot be changed after that time, so we can safely
10450 use the cached value. */
10452 if (reload_completed
)
10455 /* Initially this is the size of the local variables. It will translated
10456 into an offset once we have determined the size of preceding data. */
10457 frame_size
= ROUND_UP_WORD (get_frame_size ());
10459 leaf
= leaf_function_p ();
10461 /* Space for variadic functions. */
10462 offsets
->saved_args
= current_function_pretend_args_size
;
10464 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10468 unsigned int regno
;
10470 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10472 /* We know that SP will be doubleword aligned on entry, and we must
10473 preserve that condition at any subroutine call. We also require the
10474 soft frame pointer to be doubleword aligned. */
10476 if (TARGET_REALLY_IWMMXT
)
10478 /* Check for the call-saved iWMMXt registers. */
10479 for (regno
= FIRST_IWMMXT_REGNUM
;
10480 regno
<= LAST_IWMMXT_REGNUM
;
10482 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10486 func_type
= arm_current_func_type ();
10487 if (! IS_VOLATILE (func_type
))
10489 /* Space for saved FPA registers. */
10490 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10491 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10494 /* Space for saved VFP registers. */
10495 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10496 saved
+= arm_get_vfp_saved_size ();
10499 else /* TARGET_THUMB */
10501 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10502 if (TARGET_BACKTRACE
)
10506 /* Saved registers include the stack frame. */
10507 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10508 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10509 /* A leaf function does not need any stack alignment if it has nothing
10511 if (leaf
&& frame_size
== 0)
10513 offsets
->outgoing_args
= offsets
->soft_frame
;
10517 /* Ensure SFP has the correct alignment. */
10518 if (ARM_DOUBLEWORD_ALIGN
10519 && (offsets
->soft_frame
& 7))
10520 offsets
->soft_frame
+= 4;
10522 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
10523 offsets
->outgoing_args
= (offsets
->locals_base
10524 + current_function_outgoing_args_size
);
10526 if (ARM_DOUBLEWORD_ALIGN
)
10528 /* Ensure SP remains doubleword aligned. */
10529 if (offsets
->outgoing_args
& 7)
10530 offsets
->outgoing_args
+= 4;
10531 gcc_assert (!(offsets
->outgoing_args
& 7));
10538 /* Calculate the relative offsets for the different stack pointers. Positive
10539 offsets are in the direction of stack growth. */
10542 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10544 arm_stack_offsets
*offsets
;
10546 offsets
= arm_get_frame_offsets ();
10548 /* OK, now we have enough information to compute the distances.
10549 There must be an entry in these switch tables for each pair
10550 of registers in ELIMINABLE_REGS, even if some of the entries
10551 seem to be redundant or useless. */
10554 case ARG_POINTER_REGNUM
:
10557 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10560 case FRAME_POINTER_REGNUM
:
10561 /* This is the reverse of the soft frame pointer
10562 to hard frame pointer elimination below. */
10563 return offsets
->soft_frame
- offsets
->saved_args
;
10565 case ARM_HARD_FRAME_POINTER_REGNUM
:
10566 /* If there is no stack frame then the hard
10567 frame pointer and the arg pointer coincide. */
10568 if (offsets
->frame
== offsets
->saved_regs
)
10570 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10571 return (frame_pointer_needed
10572 && cfun
->static_chain_decl
!= NULL
10573 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10575 case STACK_POINTER_REGNUM
:
10576 /* If nothing has been pushed on the stack at all
10577 then this will return -4. This *is* correct! */
10578 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10581 gcc_unreachable ();
10583 gcc_unreachable ();
10585 case FRAME_POINTER_REGNUM
:
10588 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10591 case ARM_HARD_FRAME_POINTER_REGNUM
:
10592 /* The hard frame pointer points to the top entry in the
10593 stack frame. The soft frame pointer to the bottom entry
10594 in the stack frame. If there is no stack frame at all,
10595 then they are identical. */
10597 return offsets
->frame
- offsets
->soft_frame
;
10599 case STACK_POINTER_REGNUM
:
10600 return offsets
->outgoing_args
- offsets
->soft_frame
;
10603 gcc_unreachable ();
10605 gcc_unreachable ();
10608 /* You cannot eliminate from the stack pointer.
10609 In theory you could eliminate from the hard frame
10610 pointer to the stack pointer, but this will never
10611 happen, since if a stack frame is not needed the
10612 hard frame pointer will never be used. */
10613 gcc_unreachable ();
10618 /* Generate the prologue instructions for entry into an ARM function. */
10620 arm_expand_prologue (void)
10626 unsigned long live_regs_mask
;
10627 unsigned long func_type
;
10629 int saved_pretend_args
= 0;
10630 int saved_regs
= 0;
10631 unsigned HOST_WIDE_INT args_to_push
;
10632 arm_stack_offsets
*offsets
;
10634 func_type
= arm_current_func_type ();
10636 /* Naked functions don't have prologues. */
10637 if (IS_NAKED (func_type
))
10640 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10641 args_to_push
= current_function_pretend_args_size
;
10643 /* Compute which register we will have to save onto the stack. */
10644 live_regs_mask
= arm_compute_save_reg_mask ();
10646 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10648 if (frame_pointer_needed
)
10650 if (IS_INTERRUPT (func_type
))
10652 /* Interrupt functions must not corrupt any registers.
10653 Creating a frame pointer however, corrupts the IP
10654 register, so we must push it first. */
10655 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10657 /* Do not set RTX_FRAME_RELATED_P on this insn.
10658 The dwarf stack unwinding code only wants to see one
10659 stack decrement per function, and this is not it. If
10660 this instruction is labeled as being part of the frame
10661 creation sequence then dwarf2out_frame_debug_expr will
10662 die when it encounters the assignment of IP to FP
10663 later on, since the use of SP here establishes SP as
10664 the CFA register and not IP.
10666 Anyway this instruction is not really part of the stack
10667 frame creation although it is part of the prologue. */
10669 else if (IS_NESTED (func_type
))
10671 /* The Static chain register is the same as the IP register
10672 used as a scratch register during stack frame creation.
10673 To get around this need to find somewhere to store IP
10674 whilst the frame is being created. We try the following
10677 1. The last argument register.
10678 2. A slot on the stack above the frame. (This only
10679 works if the function is not a varargs function).
10680 3. Register r3, after pushing the argument registers
10683 Note - we only need to tell the dwarf2 backend about the SP
10684 adjustment in the second variant; the static chain register
10685 doesn't need to be unwound, as it doesn't contain a value
10686 inherited from the caller. */
10688 if (regs_ever_live
[3] == 0)
10689 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
10690 else if (args_to_push
== 0)
10694 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10695 insn
= emit_set_insn (gen_frame_mem (SImode
, insn
), ip_rtx
);
10698 /* Just tell the dwarf backend that we adjusted SP. */
10699 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10700 plus_constant (stack_pointer_rtx
,
10702 RTX_FRAME_RELATED_P (insn
) = 1;
10703 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10704 dwarf
, REG_NOTES (insn
));
10708 /* Store the args on the stack. */
10709 if (cfun
->machine
->uses_anonymous_args
)
10710 insn
= emit_multi_reg_push
10711 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10714 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10715 GEN_INT (- args_to_push
)));
10717 RTX_FRAME_RELATED_P (insn
) = 1;
10719 saved_pretend_args
= 1;
10720 fp_offset
= args_to_push
;
10723 /* Now reuse r3 to preserve IP. */
10724 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
10728 insn
= emit_set_insn (ip_rtx
,
10729 plus_constant (stack_pointer_rtx
, fp_offset
));
10730 RTX_FRAME_RELATED_P (insn
) = 1;
10735 /* Push the argument registers, or reserve space for them. */
10736 if (cfun
->machine
->uses_anonymous_args
)
10737 insn
= emit_multi_reg_push
10738 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10741 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10742 GEN_INT (- args_to_push
)));
10743 RTX_FRAME_RELATED_P (insn
) = 1;
10746 /* If this is an interrupt service routine, and the link register
10747 is going to be pushed, and we are not creating a stack frame,
10748 (which would involve an extra push of IP and a pop in the epilogue)
10749 subtracting four from LR now will mean that the function return
10750 can be done with a single instruction. */
10751 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10752 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10753 && ! frame_pointer_needed
)
10755 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
10757 emit_set_insn (lr
, plus_constant (lr
, -4));
10760 if (live_regs_mask
)
10762 insn
= emit_multi_reg_push (live_regs_mask
);
10763 saved_regs
+= bit_count (live_regs_mask
) * 4;
10764 RTX_FRAME_RELATED_P (insn
) = 1;
10768 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10769 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10771 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10772 insn
= gen_frame_mem (V2SImode
, insn
);
10773 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
10774 RTX_FRAME_RELATED_P (insn
) = 1;
10778 if (! IS_VOLATILE (func_type
))
10782 /* Save any floating point call-saved registers used by this
10784 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10786 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10787 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10789 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10790 insn
= gen_frame_mem (XFmode
, insn
);
10791 insn
= emit_set_insn (insn
, gen_rtx_REG (XFmode
, reg
));
10792 RTX_FRAME_RELATED_P (insn
) = 1;
10798 start_reg
= LAST_FPA_REGNUM
;
10800 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10802 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10804 if (start_reg
- reg
== 3)
10806 insn
= emit_sfm (reg
, 4);
10807 RTX_FRAME_RELATED_P (insn
) = 1;
10809 start_reg
= reg
- 1;
10814 if (start_reg
!= reg
)
10816 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10817 RTX_FRAME_RELATED_P (insn
) = 1;
10818 saved_regs
+= (start_reg
- reg
) * 12;
10820 start_reg
= reg
- 1;
10824 if (start_reg
!= reg
)
10826 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10827 saved_regs
+= (start_reg
- reg
) * 12;
10828 RTX_FRAME_RELATED_P (insn
) = 1;
10831 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10833 start_reg
= FIRST_VFP_REGNUM
;
10835 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10837 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10838 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10840 if (start_reg
!= reg
)
10841 saved_regs
+= vfp_emit_fstmx (start_reg
,
10842 (reg
- start_reg
) / 2);
10843 start_reg
= reg
+ 2;
10846 if (start_reg
!= reg
)
10847 saved_regs
+= vfp_emit_fstmx (start_reg
,
10848 (reg
- start_reg
) / 2);
10852 if (frame_pointer_needed
)
10854 /* Create the new frame pointer. */
10855 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10856 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10857 RTX_FRAME_RELATED_P (insn
) = 1;
10859 if (IS_NESTED (func_type
))
10861 /* Recover the static chain register. */
10862 if (regs_ever_live
[3] == 0
10863 || saved_pretend_args
)
10864 insn
= gen_rtx_REG (SImode
, 3);
10865 else /* if (current_function_pretend_args_size == 0) */
10867 insn
= plus_constant (hard_frame_pointer_rtx
, 4);
10868 insn
= gen_frame_mem (SImode
, insn
);
10871 emit_set_insn (ip_rtx
, insn
);
10872 /* Add a USE to stop propagate_one_insn() from barfing. */
10873 emit_insn (gen_prologue_use (ip_rtx
));
10877 offsets
= arm_get_frame_offsets ();
10878 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10880 /* This add can produce multiple insns for a large constant, so we
10881 need to get tricky. */
10882 rtx last
= get_last_insn ();
10884 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10885 - offsets
->outgoing_args
);
10887 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10891 last
= last
? NEXT_INSN (last
) : get_insns ();
10892 RTX_FRAME_RELATED_P (last
) = 1;
10894 while (last
!= insn
);
10896 /* If the frame pointer is needed, emit a special barrier that
10897 will prevent the scheduler from moving stores to the frame
10898 before the stack adjustment. */
10899 if (frame_pointer_needed
)
10900 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10901 hard_frame_pointer_rtx
));
10905 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
10906 arm_load_pic_register (0UL);
10908 /* If we are profiling, make sure no instructions are scheduled before
10909 the call to mcount. Similarly if the user has requested no
10910 scheduling in the prolog. Similarly if we want non-call exceptions
10911 using the EABI unwinder, to prevent faulting instructions from being
10912 swapped with a stack adjustment. */
10913 if (current_function_profile
|| !TARGET_SCHED_PROLOG
10914 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
10915 emit_insn (gen_blockage ());
10917 /* If the link register is being kept alive, with the return address in it,
10918 then make sure that it does not get reused by the ce2 pass. */
10919 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10921 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10922 cfun
->machine
->lr_save_eliminated
= 1;
10926 /* If CODE is 'd', then the X is a condition operand and the instruction
10927 should only be executed if the condition is true.
10928 if CODE is 'D', then the X is a condition operand and the instruction
10929 should only be executed if the condition is false: however, if the mode
10930 of the comparison is CCFPEmode, then always execute the instruction -- we
10931 do this because in these circumstances !GE does not necessarily imply LT;
10932 in these cases the instruction pattern will take care to make sure that
10933 an instruction containing %d will follow, thereby undoing the effects of
10934 doing this instruction unconditionally.
10935 If CODE is 'N' then X is a floating point operand that must be negated
10937 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10938 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10940 arm_print_operand (FILE *stream
, rtx x
, int code
)
10945 fputs (ASM_COMMENT_START
, stream
);
10949 fputs (user_label_prefix
, stream
);
10953 fputs (REGISTER_PREFIX
, stream
);
10957 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10961 output_operand_lossage ("predicated Thumb instruction");
10964 if (current_insn_predicate
!= NULL
)
10966 output_operand_lossage
10967 ("predicated instruction in conditional sequence");
10971 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10973 else if (current_insn_predicate
)
10975 enum arm_cond_code code
;
10979 output_operand_lossage ("predicated Thumb instruction");
10983 code
= get_arm_condition_code (current_insn_predicate
);
10984 fputs (arm_condition_codes
[code
], stream
);
10991 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10992 r
= REAL_VALUE_NEGATE (r
);
10993 fprintf (stream
, "%s", fp_const_from_val (&r
));
10998 if (GET_CODE (x
) == CONST_INT
)
11001 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
11002 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
11006 putc ('~', stream
);
11007 output_addr_const (stream
, x
);
11012 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
11015 /* Truncate Cirrus shift counts. */
11017 if (GET_CODE (x
) == CONST_INT
)
11019 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
11022 arm_print_operand (stream
, x
, 0);
11026 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
11034 if (!shift_operator (x
, SImode
))
11036 output_operand_lossage ("invalid shift operand");
11040 shift
= shift_op (x
, &val
);
11044 fprintf (stream
, ", %s ", shift
);
11046 arm_print_operand (stream
, XEXP (x
, 1), 0);
11048 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
11053 /* An explanation of the 'Q', 'R' and 'H' register operands:
11055 In a pair of registers containing a DI or DF value the 'Q'
11056 operand returns the register number of the register containing
11057 the least significant part of the value. The 'R' operand returns
11058 the register number of the register containing the most
11059 significant part of the value.
11061 The 'H' operand returns the higher of the two register numbers.
11062 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11063 same as the 'Q' operand, since the most significant part of the
11064 value is held in the lower number register. The reverse is true
11065 on systems where WORDS_BIG_ENDIAN is false.
11067 The purpose of these operands is to distinguish between cases
11068 where the endian-ness of the values is important (for example
11069 when they are added together), and cases where the endian-ness
11070 is irrelevant, but the order of register operations is important.
11071 For example when loading a value from memory into a register
11072 pair, the endian-ness does not matter. Provided that the value
11073 from the lower memory address is put into the lower numbered
11074 register, and the value from the higher address is put into the
11075 higher numbered register, the load will work regardless of whether
11076 the value being loaded is big-wordian or little-wordian. The
11077 order of the two register loads can matter however, if the address
11078 of the memory location is actually held in one of the registers
11079 being overwritten by the load. */
11081 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11083 output_operand_lossage ("invalid operand for code '%c'", code
);
11087 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
11091 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11093 output_operand_lossage ("invalid operand for code '%c'", code
);
11097 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
11101 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11103 output_operand_lossage ("invalid operand for code '%c'", code
);
11107 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
11111 asm_fprintf (stream
, "%r",
11112 GET_CODE (XEXP (x
, 0)) == REG
11113 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
11117 asm_fprintf (stream
, "{%r-%r}",
11119 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
11123 /* CONST_TRUE_RTX means always -- that's the default. */
11124 if (x
== const_true_rtx
)
11127 if (!COMPARISON_P (x
))
11129 output_operand_lossage ("invalid operand for code '%c'", code
);
11133 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
11138 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11139 want to do that. */
11140 if (x
== const_true_rtx
)
11142 output_operand_lossage ("instruction never exectued");
11145 if (!COMPARISON_P (x
))
11147 output_operand_lossage ("invalid operand for code '%c'", code
);
11151 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
11152 (get_arm_condition_code (x
))],
11156 /* Cirrus registers can be accessed in a variety of ways:
11157 single floating point (f)
11158 double floating point (d)
11160 64bit integer (dx). */
11161 case 'W': /* Cirrus register in F mode. */
11162 case 'X': /* Cirrus register in D mode. */
11163 case 'Y': /* Cirrus register in FX mode. */
11164 case 'Z': /* Cirrus register in DX mode. */
11165 gcc_assert (GET_CODE (x
) == REG
11166 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
11168 fprintf (stream
, "mv%s%s",
11170 : code
== 'X' ? "d"
11171 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
11175 /* Print cirrus register in the mode specified by the register's mode. */
11178 int mode
= GET_MODE (x
);
11180 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
11182 output_operand_lossage ("invalid operand for code '%c'", code
);
11186 fprintf (stream
, "mv%s%s",
11187 mode
== DFmode
? "d"
11188 : mode
== SImode
? "fx"
11189 : mode
== DImode
? "dx"
11190 : "f", reg_names
[REGNO (x
)] + 2);
11196 if (GET_CODE (x
) != REG
11197 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
11198 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
11199 /* Bad value for wCG register number. */
11201 output_operand_lossage ("invalid operand for code '%c'", code
);
11206 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
11209 /* Print an iWMMXt control register name. */
11211 if (GET_CODE (x
) != CONST_INT
11213 || INTVAL (x
) >= 16)
11214 /* Bad value for wC register number. */
11216 output_operand_lossage ("invalid operand for code '%c'", code
);
11222 static const char * wc_reg_names
[16] =
11224 "wCID", "wCon", "wCSSF", "wCASF",
11225 "wC4", "wC5", "wC6", "wC7",
11226 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11227 "wC12", "wC13", "wC14", "wC15"
11230 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
11234 /* Print a VFP double precision register name. */
11237 int mode
= GET_MODE (x
);
11240 if (mode
!= DImode
&& mode
!= DFmode
)
11242 output_operand_lossage ("invalid operand for code '%c'", code
);
11246 if (GET_CODE (x
) != REG
11247 || !IS_VFP_REGNUM (REGNO (x
)))
11249 output_operand_lossage ("invalid operand for code '%c'", code
);
11253 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
11256 output_operand_lossage ("invalid operand for code '%c'", code
);
11260 fprintf (stream
, "d%d", num
>> 1);
11267 output_operand_lossage ("missing operand");
11271 switch (GET_CODE (x
))
11274 asm_fprintf (stream
, "%r", REGNO (x
));
11278 output_memory_reference_mode
= GET_MODE (x
);
11279 output_address (XEXP (x
, 0));
11283 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11287 gcc_assert (GET_CODE (x
) != NEG
);
11288 fputc ('#', stream
);
11289 output_addr_const (stream
, x
);
11295 #ifndef AOF_ASSEMBLER
11296 /* Target hook for assembling integer objects. The ARM version needs to
11297 handle word-sized values specially. */
11299 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11301 if (size
== UNITS_PER_WORD
&& aligned_p
)
11303 fputs ("\t.word\t", asm_out_file
);
11304 output_addr_const (asm_out_file
, x
);
11306 /* Mark symbols as position independent. We only do this in the
11307 .text segment, not in the .data segment. */
11308 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
11309 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
11311 if (GET_CODE (x
) == SYMBOL_REF
11312 && (CONSTANT_POOL_ADDRESS_P (x
)
11313 || SYMBOL_REF_LOCAL_P (x
)))
11314 fputs ("(GOTOFF)", asm_out_file
);
11315 else if (GET_CODE (x
) == LABEL_REF
)
11316 fputs ("(GOTOFF)", asm_out_file
);
11318 fputs ("(GOT)", asm_out_file
);
11320 fputc ('\n', asm_out_file
);
11324 if (arm_vector_mode_supported_p (GET_MODE (x
)))
11328 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
11330 units
= CONST_VECTOR_NUNITS (x
);
11332 switch (GET_MODE (x
))
11334 case V2SImode
: size
= 4; break;
11335 case V4HImode
: size
= 2; break;
11336 case V8QImode
: size
= 1; break;
11338 gcc_unreachable ();
11341 for (i
= 0; i
< units
; i
++)
11345 elt
= CONST_VECTOR_ELT (x
, i
);
11347 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11353 return default_assemble_integer (x
, size
, aligned_p
);
11357 /* Add a function to the list of static constructors. */
11360 arm_elf_asm_constructor (rtx symbol
, int priority
)
11364 if (!TARGET_AAPCS_BASED
)
11366 default_named_section_asm_out_constructor (symbol
, priority
);
11370 /* Put these in the .init_array section, using a special relocation. */
11371 if (priority
!= DEFAULT_INIT_PRIORITY
)
11374 sprintf (buf
, ".init_array.%.5u", priority
);
11375 s
= get_section (buf
, SECTION_WRITE
, NULL_TREE
);
11380 switch_to_section (s
);
11381 assemble_align (POINTER_SIZE
);
11382 fputs ("\t.word\t", asm_out_file
);
11383 output_addr_const (asm_out_file
, symbol
);
11384 fputs ("(target1)\n", asm_out_file
);
11388 /* A finite state machine takes care of noticing whether or not instructions
11389 can be conditionally executed, and thus decrease execution time and code
11390 size by deleting branch instructions. The fsm is controlled by
11391 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11393 /* The state of the fsm controlling condition codes are:
11394 0: normal, do nothing special
11395 1: make ASM_OUTPUT_OPCODE not output this instruction
11396 2: make ASM_OUTPUT_OPCODE not output this instruction
11397 3: make instructions conditional
11398 4: make instructions conditional
11400 State transitions (state->state by whom under condition):
11401 0 -> 1 final_prescan_insn if the `target' is a label
11402 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11403 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11404 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11405 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11406 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11407 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11408 (the target insn is arm_target_insn).
11410 If the jump clobbers the conditions then we use states 2 and 4.
11412 A similar thing can be done with conditional return insns.
11414 XXX In case the `target' is an unconditional branch, this conditionalising
11415 of the instructions always reduces code size, but not always execution
11416 time. But then, I want to reduce the code size to somewhere near what
11417 /bin/cc produces. */
11419 /* Returns the index of the ARM condition code string in
11420 `arm_condition_codes'. COMPARISON should be an rtx like
11421 `(eq (...) (...))'. */
11422 static enum arm_cond_code
11423 get_arm_condition_code (rtx comparison
)
11425 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11427 enum rtx_code comp_code
= GET_CODE (comparison
);
11429 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11430 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11431 XEXP (comparison
, 1));
11435 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11436 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11437 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11438 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11439 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11440 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11441 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11442 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11443 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11444 case CC_DLTUmode
: code
= ARM_CC
;
11447 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
11449 if (comp_code
== EQ
)
11450 return ARM_INVERSE_CONDITION_CODE (code
);
11456 case NE
: return ARM_NE
;
11457 case EQ
: return ARM_EQ
;
11458 case GE
: return ARM_PL
;
11459 case LT
: return ARM_MI
;
11460 default: gcc_unreachable ();
11466 case NE
: return ARM_NE
;
11467 case EQ
: return ARM_EQ
;
11468 default: gcc_unreachable ();
11474 case NE
: return ARM_MI
;
11475 case EQ
: return ARM_PL
;
11476 default: gcc_unreachable ();
11481 /* These encodings assume that AC=1 in the FPA system control
11482 byte. This allows us to handle all cases except UNEQ and
11486 case GE
: return ARM_GE
;
11487 case GT
: return ARM_GT
;
11488 case LE
: return ARM_LS
;
11489 case LT
: return ARM_MI
;
11490 case NE
: return ARM_NE
;
11491 case EQ
: return ARM_EQ
;
11492 case ORDERED
: return ARM_VC
;
11493 case UNORDERED
: return ARM_VS
;
11494 case UNLT
: return ARM_LT
;
11495 case UNLE
: return ARM_LE
;
11496 case UNGT
: return ARM_HI
;
11497 case UNGE
: return ARM_PL
;
11498 /* UNEQ and LTGT do not have a representation. */
11499 case UNEQ
: /* Fall through. */
11500 case LTGT
: /* Fall through. */
11501 default: gcc_unreachable ();
11507 case NE
: return ARM_NE
;
11508 case EQ
: return ARM_EQ
;
11509 case GE
: return ARM_LE
;
11510 case GT
: return ARM_LT
;
11511 case LE
: return ARM_GE
;
11512 case LT
: return ARM_GT
;
11513 case GEU
: return ARM_LS
;
11514 case GTU
: return ARM_CC
;
11515 case LEU
: return ARM_CS
;
11516 case LTU
: return ARM_HI
;
11517 default: gcc_unreachable ();
11523 case LTU
: return ARM_CS
;
11524 case GEU
: return ARM_CC
;
11525 default: gcc_unreachable ();
11531 case NE
: return ARM_NE
;
11532 case EQ
: return ARM_EQ
;
11533 case GE
: return ARM_GE
;
11534 case GT
: return ARM_GT
;
11535 case LE
: return ARM_LE
;
11536 case LT
: return ARM_LT
;
11537 case GEU
: return ARM_CS
;
11538 case GTU
: return ARM_HI
;
11539 case LEU
: return ARM_LS
;
11540 case LTU
: return ARM_CC
;
11541 default: gcc_unreachable ();
11544 default: gcc_unreachable ();
11549 arm_final_prescan_insn (rtx insn
)
11551 /* BODY will hold the body of INSN. */
11552 rtx body
= PATTERN (insn
);
11554 /* This will be 1 if trying to repeat the trick, and things need to be
11555 reversed if it appears to fail. */
11558 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11559 taken are clobbered, even if the rtl suggests otherwise. It also
11560 means that we have to grub around within the jump expression to find
11561 out what the conditions are when the jump isn't taken. */
11562 int jump_clobbers
= 0;
11564 /* If we start with a return insn, we only succeed if we find another one. */
11565 int seeking_return
= 0;
11567 /* START_INSN will hold the insn from where we start looking. This is the
11568 first insn after the following code_label if REVERSE is true. */
11569 rtx start_insn
= insn
;
11571 /* If in state 4, check if the target branch is reached, in order to
11572 change back to state 0. */
11573 if (arm_ccfsm_state
== 4)
11575 if (insn
== arm_target_insn
)
11577 arm_target_insn
= NULL
;
11578 arm_ccfsm_state
= 0;
11583 /* If in state 3, it is possible to repeat the trick, if this insn is an
11584 unconditional branch to a label, and immediately following this branch
11585 is the previous target label which is only used once, and the label this
11586 branch jumps to is not too far off. */
11587 if (arm_ccfsm_state
== 3)
11589 if (simplejump_p (insn
))
11591 start_insn
= next_nonnote_insn (start_insn
);
11592 if (GET_CODE (start_insn
) == BARRIER
)
11594 /* XXX Isn't this always a barrier? */
11595 start_insn
= next_nonnote_insn (start_insn
);
11597 if (GET_CODE (start_insn
) == CODE_LABEL
11598 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11599 && LABEL_NUSES (start_insn
) == 1)
11604 else if (GET_CODE (body
) == RETURN
)
11606 start_insn
= next_nonnote_insn (start_insn
);
11607 if (GET_CODE (start_insn
) == BARRIER
)
11608 start_insn
= next_nonnote_insn (start_insn
);
11609 if (GET_CODE (start_insn
) == CODE_LABEL
11610 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11611 && LABEL_NUSES (start_insn
) == 1)
11614 seeking_return
= 1;
11623 gcc_assert (!arm_ccfsm_state
|| reverse
);
11624 if (GET_CODE (insn
) != JUMP_INSN
)
11627 /* This jump might be paralleled with a clobber of the condition codes
11628 the jump should always come first */
11629 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11630 body
= XVECEXP (body
, 0, 0);
11633 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11634 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11637 int fail
= FALSE
, succeed
= FALSE
;
11638 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11639 int then_not_else
= TRUE
;
11640 rtx this_insn
= start_insn
, label
= 0;
11642 /* If the jump cannot be done with one instruction, we cannot
11643 conditionally execute the instruction in the inverse case. */
11644 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11650 /* Register the insn jumped to. */
11653 if (!seeking_return
)
11654 label
= XEXP (SET_SRC (body
), 0);
11656 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11657 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11658 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11660 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11661 then_not_else
= FALSE
;
11663 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11664 seeking_return
= 1;
11665 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11667 seeking_return
= 1;
11668 then_not_else
= FALSE
;
11671 gcc_unreachable ();
11673 /* See how many insns this branch skips, and what kind of insns. If all
11674 insns are okay, and the label or unconditional branch to the same
11675 label is not too far away, succeed. */
11676 for (insns_skipped
= 0;
11677 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11681 this_insn
= next_nonnote_insn (this_insn
);
11685 switch (GET_CODE (this_insn
))
11688 /* Succeed if it is the target label, otherwise fail since
11689 control falls in from somewhere else. */
11690 if (this_insn
== label
)
11694 arm_ccfsm_state
= 2;
11695 this_insn
= next_nonnote_insn (this_insn
);
11698 arm_ccfsm_state
= 1;
11706 /* Succeed if the following insn is the target label.
11708 If return insns are used then the last insn in a function
11709 will be a barrier. */
11710 this_insn
= next_nonnote_insn (this_insn
);
11711 if (this_insn
&& this_insn
== label
)
11715 arm_ccfsm_state
= 2;
11716 this_insn
= next_nonnote_insn (this_insn
);
11719 arm_ccfsm_state
= 1;
11727 /* The AAPCS says that conditional calls should not be
11728 used since they make interworking inefficient (the
11729 linker can't transform BL<cond> into BLX). That's
11730 only a problem if the machine has BLX. */
11737 /* Succeed if the following insn is the target label, or
11738 if the following two insns are a barrier and the
11740 this_insn
= next_nonnote_insn (this_insn
);
11741 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11742 this_insn
= next_nonnote_insn (this_insn
);
11744 if (this_insn
&& this_insn
== label
11745 && insns_skipped
< max_insns_skipped
)
11749 arm_ccfsm_state
= 2;
11750 this_insn
= next_nonnote_insn (this_insn
);
11753 arm_ccfsm_state
= 1;
11761 /* If this is an unconditional branch to the same label, succeed.
11762 If it is to another label, do nothing. If it is conditional,
11764 /* XXX Probably, the tests for SET and the PC are
11767 scanbody
= PATTERN (this_insn
);
11768 if (GET_CODE (scanbody
) == SET
11769 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11771 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11772 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11774 arm_ccfsm_state
= 2;
11777 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11780 /* Fail if a conditional return is undesirable (e.g. on a
11781 StrongARM), but still allow this if optimizing for size. */
11782 else if (GET_CODE (scanbody
) == RETURN
11783 && !use_return_insn (TRUE
, NULL
)
11786 else if (GET_CODE (scanbody
) == RETURN
11789 arm_ccfsm_state
= 2;
11792 else if (GET_CODE (scanbody
) == PARALLEL
)
11794 switch (get_attr_conds (this_insn
))
11804 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11809 /* Instructions using or affecting the condition codes make it
11811 scanbody
= PATTERN (this_insn
);
11812 if (!(GET_CODE (scanbody
) == SET
11813 || GET_CODE (scanbody
) == PARALLEL
)
11814 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11817 /* A conditional cirrus instruction must be followed by
11818 a non Cirrus instruction. However, since we
11819 conditionalize instructions in this function and by
11820 the time we get here we can't add instructions
11821 (nops), because shorten_branches() has already been
11822 called, we will disable conditionalizing Cirrus
11823 instructions to be safe. */
11824 if (GET_CODE (scanbody
) != USE
11825 && GET_CODE (scanbody
) != CLOBBER
11826 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11836 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11837 arm_target_label
= CODE_LABEL_NUMBER (label
);
11840 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
11842 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11844 this_insn
= next_nonnote_insn (this_insn
);
11845 gcc_assert (!this_insn
11846 || (GET_CODE (this_insn
) != BARRIER
11847 && GET_CODE (this_insn
) != CODE_LABEL
));
11851 /* Oh, dear! we ran off the end.. give up. */
11852 recog (PATTERN (insn
), insn
, NULL
);
11853 arm_ccfsm_state
= 0;
11854 arm_target_insn
= NULL
;
11857 arm_target_insn
= this_insn
;
11861 gcc_assert (!reverse
);
11863 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11865 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11866 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11867 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11868 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11872 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11875 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11879 if (reverse
|| then_not_else
)
11880 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11883 /* Restore recog_data (getting the attributes of other insns can
11884 destroy this array, but final.c assumes that it remains intact
11885 across this call; since the insn has been recognized already we
11886 call recog direct). */
11887 recog (PATTERN (insn
), insn
, NULL
);
11891 /* Returns true if REGNO is a valid register
11892 for holding a quantity of type MODE. */
11894 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11896 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11897 return (regno
== CC_REGNUM
11898 || (TARGET_HARD_FLOAT
&& TARGET_VFP
11899 && regno
== VFPCC_REGNUM
));
11902 /* For the Thumb we only allow values bigger than SImode in
11903 registers 0 - 6, so that there is always a second low
11904 register available to hold the upper part of the value.
11905 We probably we ought to ensure that the register is the
11906 start of an even numbered register pair. */
11907 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11909 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
11910 && IS_CIRRUS_REGNUM (regno
))
11911 /* We have outlawed SI values in Cirrus registers because they
11912 reside in the lower 32 bits, but SF values reside in the
11913 upper 32 bits. This causes gcc all sorts of grief. We can't
11914 even split the registers into pairs because Cirrus SI values
11915 get sign extended to 64bits-- aldyh. */
11916 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11918 if (TARGET_HARD_FLOAT
&& TARGET_VFP
11919 && IS_VFP_REGNUM (regno
))
11921 if (mode
== SFmode
|| mode
== SImode
)
11924 /* DFmode values are only valid in even register pairs. */
11925 if (mode
== DFmode
)
11926 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11930 if (TARGET_REALLY_IWMMXT
)
11932 if (IS_IWMMXT_GR_REGNUM (regno
))
11933 return mode
== SImode
;
11935 if (IS_IWMMXT_REGNUM (regno
))
11936 return VALID_IWMMXT_REG_MODE (mode
);
11939 /* We allow any value to be stored in the general registers.
11940 Restrict doubleword quantities to even register pairs so that we can
11942 if (regno
<= LAST_ARM_REGNUM
)
11943 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11945 if (regno
== FRAME_POINTER_REGNUM
11946 || regno
== ARG_POINTER_REGNUM
)
11947 /* We only allow integers in the fake hard registers. */
11948 return GET_MODE_CLASS (mode
) == MODE_INT
;
11950 /* The only registers left are the FPA registers
11951 which we only allow to hold FP values. */
11952 return (TARGET_HARD_FLOAT
&& TARGET_FPA
11953 && GET_MODE_CLASS (mode
) == MODE_FLOAT
11954 && regno
>= FIRST_FPA_REGNUM
11955 && regno
<= LAST_FPA_REGNUM
);
11959 arm_regno_class (int regno
)
11963 if (regno
== STACK_POINTER_REGNUM
)
11965 if (regno
== CC_REGNUM
)
11972 if ( regno
<= LAST_ARM_REGNUM
11973 || regno
== FRAME_POINTER_REGNUM
11974 || regno
== ARG_POINTER_REGNUM
)
11975 return GENERAL_REGS
;
11977 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11980 if (IS_CIRRUS_REGNUM (regno
))
11981 return CIRRUS_REGS
;
11983 if (IS_VFP_REGNUM (regno
))
11986 if (IS_IWMMXT_REGNUM (regno
))
11987 return IWMMXT_REGS
;
11989 if (IS_IWMMXT_GR_REGNUM (regno
))
11990 return IWMMXT_GR_REGS
;
11995 /* Handle a special case when computing the offset
11996 of an argument from the frame pointer. */
11998 arm_debugger_arg_offset (int value
, rtx addr
)
12002 /* We are only interested if dbxout_parms() failed to compute the offset. */
12006 /* We can only cope with the case where the address is held in a register. */
12007 if (GET_CODE (addr
) != REG
)
12010 /* If we are using the frame pointer to point at the argument, then
12011 an offset of 0 is correct. */
12012 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
12015 /* If we are using the stack pointer to point at the
12016 argument, then an offset of 0 is correct. */
12017 if ((TARGET_THUMB
|| !frame_pointer_needed
)
12018 && REGNO (addr
) == SP_REGNUM
)
12021 /* Oh dear. The argument is pointed to by a register rather
12022 than being held in a register, or being stored at a known
12023 offset from the frame pointer. Since GDB only understands
12024 those two kinds of argument we must translate the address
12025 held in the register into an offset from the frame pointer.
12026 We do this by searching through the insns for the function
12027 looking to see where this register gets its value. If the
12028 register is initialized from the frame pointer plus an offset
12029 then we are in luck and we can continue, otherwise we give up.
12031 This code is exercised by producing debugging information
12032 for a function with arguments like this:
12034 double func (double a, double b, int c, double d) {return d;}
12036 Without this code the stab for parameter 'd' will be set to
12037 an offset of 0 from the frame pointer, rather than 8. */
12039 /* The if() statement says:
12041 If the insn is a normal instruction
12042 and if the insn is setting the value in a register
12043 and if the register being set is the register holding the address of the argument
12044 and if the address is computing by an addition
12045 that involves adding to a register
12046 which is the frame pointer
12051 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12053 if ( GET_CODE (insn
) == INSN
12054 && GET_CODE (PATTERN (insn
)) == SET
12055 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
12056 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
12057 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
12058 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12059 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
12062 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
12071 warning (0, "unable to compute real location of stacked parameter");
12072 value
= 8; /* XXX magic hack */
12078 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12081 if ((MASK) & insn_flags) \
12082 add_builtin_function ((NAME), (TYPE), (CODE), \
12083 BUILT_IN_MD, NULL, NULL_TREE); \
12087 struct builtin_description
12089 const unsigned int mask
;
12090 const enum insn_code icode
;
12091 const char * const name
;
12092 const enum arm_builtins code
;
12093 const enum rtx_code comparison
;
12094 const unsigned int flag
;
12097 static const struct builtin_description bdesc_2arg
[] =
12099 #define IWMMXT_BUILTIN(code, string, builtin) \
12100 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12101 ARM_BUILTIN_##builtin, 0, 0 },
12103 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
12104 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
12105 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
12106 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
12107 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
12108 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
12109 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
12110 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
12111 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
12112 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
12113 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
12114 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
12115 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
12116 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
12117 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
12118 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
12119 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
12120 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
12121 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
12122 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
12123 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
12124 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
12125 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
12126 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
12127 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
12128 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
12129 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
12130 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
12131 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
12132 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
12133 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
12134 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
12135 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
12136 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
12137 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
12138 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
12139 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
12140 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
12141 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
12142 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
12143 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
12144 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
12145 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
12146 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
12147 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
12148 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
12149 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
12150 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
12151 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
12152 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
12153 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
12154 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
12155 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
12156 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
12157 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
12158 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
12159 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
12160 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
12162 #define IWMMXT_BUILTIN2(code, builtin) \
12163 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12165 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
12166 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
12167 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
12168 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
12169 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
12170 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
12171 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
12172 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
12173 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
12174 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
12175 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
12176 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
12177 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
12178 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
12179 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
12180 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
12181 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
12182 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
12183 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
12184 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
12185 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
12186 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
12187 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
12188 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
12189 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
12190 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
12191 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
12192 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
12193 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
12194 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
12195 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
12196 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
12199 static const struct builtin_description bdesc_1arg
[] =
12201 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
12202 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
12203 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
12204 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
12205 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
12206 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
12207 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
12208 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
12209 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
12210 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
12211 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
12212 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
12213 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
12214 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
12215 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
12216 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
12217 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
12218 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
12221 /* Set up all the iWMMXt builtins. This is
12222 not called if TARGET_IWMMXT is zero. */
12225 arm_init_iwmmxt_builtins (void)
12227 const struct builtin_description
* d
;
12229 tree endlink
= void_list_node
;
12231 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12232 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12233 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12236 = build_function_type (integer_type_node
,
12237 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
12238 tree v8qi_ftype_v8qi_v8qi_int
12239 = build_function_type (V8QI_type_node
,
12240 tree_cons (NULL_TREE
, V8QI_type_node
,
12241 tree_cons (NULL_TREE
, V8QI_type_node
,
12242 tree_cons (NULL_TREE
,
12245 tree v4hi_ftype_v4hi_int
12246 = build_function_type (V4HI_type_node
,
12247 tree_cons (NULL_TREE
, V4HI_type_node
,
12248 tree_cons (NULL_TREE
, integer_type_node
,
12250 tree v2si_ftype_v2si_int
12251 = build_function_type (V2SI_type_node
,
12252 tree_cons (NULL_TREE
, V2SI_type_node
,
12253 tree_cons (NULL_TREE
, integer_type_node
,
12255 tree v2si_ftype_di_di
12256 = build_function_type (V2SI_type_node
,
12257 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12258 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12260 tree di_ftype_di_int
12261 = build_function_type (long_long_integer_type_node
,
12262 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12263 tree_cons (NULL_TREE
, integer_type_node
,
12265 tree di_ftype_di_int_int
12266 = build_function_type (long_long_integer_type_node
,
12267 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12268 tree_cons (NULL_TREE
, integer_type_node
,
12269 tree_cons (NULL_TREE
,
12272 tree int_ftype_v8qi
12273 = build_function_type (integer_type_node
,
12274 tree_cons (NULL_TREE
, V8QI_type_node
,
12276 tree int_ftype_v4hi
12277 = build_function_type (integer_type_node
,
12278 tree_cons (NULL_TREE
, V4HI_type_node
,
12280 tree int_ftype_v2si
12281 = build_function_type (integer_type_node
,
12282 tree_cons (NULL_TREE
, V2SI_type_node
,
12284 tree int_ftype_v8qi_int
12285 = build_function_type (integer_type_node
,
12286 tree_cons (NULL_TREE
, V8QI_type_node
,
12287 tree_cons (NULL_TREE
, integer_type_node
,
12289 tree int_ftype_v4hi_int
12290 = build_function_type (integer_type_node
,
12291 tree_cons (NULL_TREE
, V4HI_type_node
,
12292 tree_cons (NULL_TREE
, integer_type_node
,
12294 tree int_ftype_v2si_int
12295 = build_function_type (integer_type_node
,
12296 tree_cons (NULL_TREE
, V2SI_type_node
,
12297 tree_cons (NULL_TREE
, integer_type_node
,
12299 tree v8qi_ftype_v8qi_int_int
12300 = build_function_type (V8QI_type_node
,
12301 tree_cons (NULL_TREE
, V8QI_type_node
,
12302 tree_cons (NULL_TREE
, integer_type_node
,
12303 tree_cons (NULL_TREE
,
12306 tree v4hi_ftype_v4hi_int_int
12307 = build_function_type (V4HI_type_node
,
12308 tree_cons (NULL_TREE
, V4HI_type_node
,
12309 tree_cons (NULL_TREE
, integer_type_node
,
12310 tree_cons (NULL_TREE
,
12313 tree v2si_ftype_v2si_int_int
12314 = build_function_type (V2SI_type_node
,
12315 tree_cons (NULL_TREE
, V2SI_type_node
,
12316 tree_cons (NULL_TREE
, integer_type_node
,
12317 tree_cons (NULL_TREE
,
12320 /* Miscellaneous. */
12321 tree v8qi_ftype_v4hi_v4hi
12322 = build_function_type (V8QI_type_node
,
12323 tree_cons (NULL_TREE
, V4HI_type_node
,
12324 tree_cons (NULL_TREE
, V4HI_type_node
,
12326 tree v4hi_ftype_v2si_v2si
12327 = build_function_type (V4HI_type_node
,
12328 tree_cons (NULL_TREE
, V2SI_type_node
,
12329 tree_cons (NULL_TREE
, V2SI_type_node
,
12331 tree v2si_ftype_v4hi_v4hi
12332 = build_function_type (V2SI_type_node
,
12333 tree_cons (NULL_TREE
, V4HI_type_node
,
12334 tree_cons (NULL_TREE
, V4HI_type_node
,
12336 tree v2si_ftype_v8qi_v8qi
12337 = build_function_type (V2SI_type_node
,
12338 tree_cons (NULL_TREE
, V8QI_type_node
,
12339 tree_cons (NULL_TREE
, V8QI_type_node
,
12341 tree v4hi_ftype_v4hi_di
12342 = build_function_type (V4HI_type_node
,
12343 tree_cons (NULL_TREE
, V4HI_type_node
,
12344 tree_cons (NULL_TREE
,
12345 long_long_integer_type_node
,
12347 tree v2si_ftype_v2si_di
12348 = build_function_type (V2SI_type_node
,
12349 tree_cons (NULL_TREE
, V2SI_type_node
,
12350 tree_cons (NULL_TREE
,
12351 long_long_integer_type_node
,
12353 tree void_ftype_int_int
12354 = build_function_type (void_type_node
,
12355 tree_cons (NULL_TREE
, integer_type_node
,
12356 tree_cons (NULL_TREE
, integer_type_node
,
12359 = build_function_type (long_long_unsigned_type_node
, endlink
);
12361 = build_function_type (long_long_integer_type_node
,
12362 tree_cons (NULL_TREE
, V8QI_type_node
,
12365 = build_function_type (long_long_integer_type_node
,
12366 tree_cons (NULL_TREE
, V4HI_type_node
,
12369 = build_function_type (long_long_integer_type_node
,
12370 tree_cons (NULL_TREE
, V2SI_type_node
,
12372 tree v2si_ftype_v4hi
12373 = build_function_type (V2SI_type_node
,
12374 tree_cons (NULL_TREE
, V4HI_type_node
,
12376 tree v4hi_ftype_v8qi
12377 = build_function_type (V4HI_type_node
,
12378 tree_cons (NULL_TREE
, V8QI_type_node
,
12381 tree di_ftype_di_v4hi_v4hi
12382 = build_function_type (long_long_unsigned_type_node
,
12383 tree_cons (NULL_TREE
,
12384 long_long_unsigned_type_node
,
12385 tree_cons (NULL_TREE
, V4HI_type_node
,
12386 tree_cons (NULL_TREE
,
12390 tree di_ftype_v4hi_v4hi
12391 = build_function_type (long_long_unsigned_type_node
,
12392 tree_cons (NULL_TREE
, V4HI_type_node
,
12393 tree_cons (NULL_TREE
, V4HI_type_node
,
12396 /* Normal vector binops. */
12397 tree v8qi_ftype_v8qi_v8qi
12398 = build_function_type (V8QI_type_node
,
12399 tree_cons (NULL_TREE
, V8QI_type_node
,
12400 tree_cons (NULL_TREE
, V8QI_type_node
,
12402 tree v4hi_ftype_v4hi_v4hi
12403 = build_function_type (V4HI_type_node
,
12404 tree_cons (NULL_TREE
, V4HI_type_node
,
12405 tree_cons (NULL_TREE
, V4HI_type_node
,
12407 tree v2si_ftype_v2si_v2si
12408 = build_function_type (V2SI_type_node
,
12409 tree_cons (NULL_TREE
, V2SI_type_node
,
12410 tree_cons (NULL_TREE
, V2SI_type_node
,
12412 tree di_ftype_di_di
12413 = build_function_type (long_long_unsigned_type_node
,
12414 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
12415 tree_cons (NULL_TREE
,
12416 long_long_unsigned_type_node
,
12419 /* Add all builtins that are more or less simple operations on two
12421 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12423 /* Use one of the operands; the target can have a different mode for
12424 mask-generating compares. */
12425 enum machine_mode mode
;
12431 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12436 type
= v8qi_ftype_v8qi_v8qi
;
12439 type
= v4hi_ftype_v4hi_v4hi
;
12442 type
= v2si_ftype_v2si_v2si
;
12445 type
= di_ftype_di_di
;
12449 gcc_unreachable ();
12452 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12455 /* Add the remaining MMX insns with somewhat more complicated types. */
12456 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12457 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12458 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12460 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12461 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12462 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12463 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12464 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12465 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12467 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12468 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12469 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12470 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12471 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12472 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12474 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12475 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12476 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12477 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12478 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12479 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12481 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12482 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12483 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12484 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12485 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12486 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12488 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12490 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12491 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12492 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12493 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12495 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12496 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12497 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12498 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12499 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12500 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12501 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12502 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12503 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12505 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12506 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12507 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12509 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12510 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12511 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12513 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12514 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12515 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12516 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12517 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12518 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12520 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12521 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12522 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12523 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12524 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12525 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12526 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12527 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12528 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12529 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12530 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12531 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12533 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12534 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12535 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12536 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12538 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12539 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12540 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12541 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12542 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12543 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12544 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12548 arm_init_tls_builtins (void)
12551 tree nothrow
= tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
12552 tree const_nothrow
= tree_cons (get_identifier ("const"), NULL
, nothrow
);
12554 ftype
= build_function_type (ptr_type_node
, void_list_node
);
12555 add_builtin_function ("__builtin_thread_pointer", ftype
,
12556 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
12557 NULL
, const_nothrow
);
12561 arm_init_builtins (void)
12563 arm_init_tls_builtins ();
12565 if (TARGET_REALLY_IWMMXT
)
12566 arm_init_iwmmxt_builtins ();
12569 /* Errors in the source file can cause expand_expr to return const0_rtx
12570 where we expect a vector. To avoid crashing, use one of the vector
12571 clear instructions. */
12574 safe_vector_operand (rtx x
, enum machine_mode mode
)
12576 if (x
!= const0_rtx
)
12578 x
= gen_reg_rtx (mode
);
12580 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12581 : gen_rtx_SUBREG (DImode
, x
, 0)));
12585 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12588 arm_expand_binop_builtin (enum insn_code icode
,
12589 tree arglist
, rtx target
)
12592 tree arg0
= TREE_VALUE (arglist
);
12593 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12594 rtx op0
= expand_normal (arg0
);
12595 rtx op1
= expand_normal (arg1
);
12596 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12597 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12598 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12600 if (VECTOR_MODE_P (mode0
))
12601 op0
= safe_vector_operand (op0
, mode0
);
12602 if (VECTOR_MODE_P (mode1
))
12603 op1
= safe_vector_operand (op1
, mode1
);
12606 || GET_MODE (target
) != tmode
12607 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12608 target
= gen_reg_rtx (tmode
);
12610 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
12612 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12613 op0
= copy_to_mode_reg (mode0
, op0
);
12614 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12615 op1
= copy_to_mode_reg (mode1
, op1
);
12617 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12624 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12627 arm_expand_unop_builtin (enum insn_code icode
,
12628 tree arglist
, rtx target
, int do_load
)
12631 tree arg0
= TREE_VALUE (arglist
);
12632 rtx op0
= expand_normal (arg0
);
12633 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12634 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12637 || GET_MODE (target
) != tmode
12638 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12639 target
= gen_reg_rtx (tmode
);
12641 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12644 if (VECTOR_MODE_P (mode0
))
12645 op0
= safe_vector_operand (op0
, mode0
);
12647 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12648 op0
= copy_to_mode_reg (mode0
, op0
);
12651 pat
= GEN_FCN (icode
) (target
, op0
);
12658 /* Expand an expression EXP that calls a built-in function,
12659 with result going to TARGET if that's convenient
12660 (and in mode MODE if that's convenient).
12661 SUBTARGET may be used as the target for computing one of EXP's operands.
12662 IGNORE is nonzero if the value is to be ignored. */
12665 arm_expand_builtin (tree exp
,
12667 rtx subtarget ATTRIBUTE_UNUSED
,
12668 enum machine_mode mode ATTRIBUTE_UNUSED
,
12669 int ignore ATTRIBUTE_UNUSED
)
12671 const struct builtin_description
* d
;
12672 enum insn_code icode
;
12673 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12674 tree arglist
= TREE_OPERAND (exp
, 1);
12682 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12684 enum machine_mode tmode
;
12685 enum machine_mode mode0
;
12686 enum machine_mode mode1
;
12687 enum machine_mode mode2
;
12691 case ARM_BUILTIN_TEXTRMSB
:
12692 case ARM_BUILTIN_TEXTRMUB
:
12693 case ARM_BUILTIN_TEXTRMSH
:
12694 case ARM_BUILTIN_TEXTRMUH
:
12695 case ARM_BUILTIN_TEXTRMSW
:
12696 case ARM_BUILTIN_TEXTRMUW
:
12697 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12698 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12699 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12700 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12701 : CODE_FOR_iwmmxt_textrmw
);
12703 arg0
= TREE_VALUE (arglist
);
12704 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12705 op0
= expand_normal (arg0
);
12706 op1
= expand_normal (arg1
);
12707 tmode
= insn_data
[icode
].operand
[0].mode
;
12708 mode0
= insn_data
[icode
].operand
[1].mode
;
12709 mode1
= insn_data
[icode
].operand
[2].mode
;
12711 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12712 op0
= copy_to_mode_reg (mode0
, op0
);
12713 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12715 /* @@@ better error message */
12716 error ("selector must be an immediate");
12717 return gen_reg_rtx (tmode
);
12720 || GET_MODE (target
) != tmode
12721 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12722 target
= gen_reg_rtx (tmode
);
12723 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12729 case ARM_BUILTIN_TINSRB
:
12730 case ARM_BUILTIN_TINSRH
:
12731 case ARM_BUILTIN_TINSRW
:
12732 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12733 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12734 : CODE_FOR_iwmmxt_tinsrw
);
12735 arg0
= TREE_VALUE (arglist
);
12736 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12737 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12738 op0
= expand_normal (arg0
);
12739 op1
= expand_normal (arg1
);
12740 op2
= expand_normal (arg2
);
12741 tmode
= insn_data
[icode
].operand
[0].mode
;
12742 mode0
= insn_data
[icode
].operand
[1].mode
;
12743 mode1
= insn_data
[icode
].operand
[2].mode
;
12744 mode2
= insn_data
[icode
].operand
[3].mode
;
12746 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12747 op0
= copy_to_mode_reg (mode0
, op0
);
12748 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12749 op1
= copy_to_mode_reg (mode1
, op1
);
12750 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12752 /* @@@ better error message */
12753 error ("selector must be an immediate");
12757 || GET_MODE (target
) != tmode
12758 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12759 target
= gen_reg_rtx (tmode
);
12760 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12766 case ARM_BUILTIN_SETWCX
:
12767 arg0
= TREE_VALUE (arglist
);
12768 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12769 op0
= force_reg (SImode
, expand_normal (arg0
));
12770 op1
= expand_normal (arg1
);
12771 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12774 case ARM_BUILTIN_GETWCX
:
12775 arg0
= TREE_VALUE (arglist
);
12776 op0
= expand_normal (arg0
);
12777 target
= gen_reg_rtx (SImode
);
12778 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12781 case ARM_BUILTIN_WSHUFH
:
12782 icode
= CODE_FOR_iwmmxt_wshufh
;
12783 arg0
= TREE_VALUE (arglist
);
12784 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12785 op0
= expand_normal (arg0
);
12786 op1
= expand_normal (arg1
);
12787 tmode
= insn_data
[icode
].operand
[0].mode
;
12788 mode1
= insn_data
[icode
].operand
[1].mode
;
12789 mode2
= insn_data
[icode
].operand
[2].mode
;
12791 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12792 op0
= copy_to_mode_reg (mode1
, op0
);
12793 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12795 /* @@@ better error message */
12796 error ("mask must be an immediate");
12800 || GET_MODE (target
) != tmode
12801 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12802 target
= gen_reg_rtx (tmode
);
12803 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12809 case ARM_BUILTIN_WSADB
:
12810 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12811 case ARM_BUILTIN_WSADH
:
12812 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12813 case ARM_BUILTIN_WSADBZ
:
12814 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12815 case ARM_BUILTIN_WSADHZ
:
12816 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12818 /* Several three-argument builtins. */
12819 case ARM_BUILTIN_WMACS
:
12820 case ARM_BUILTIN_WMACU
:
12821 case ARM_BUILTIN_WALIGN
:
12822 case ARM_BUILTIN_TMIA
:
12823 case ARM_BUILTIN_TMIAPH
:
12824 case ARM_BUILTIN_TMIATT
:
12825 case ARM_BUILTIN_TMIATB
:
12826 case ARM_BUILTIN_TMIABT
:
12827 case ARM_BUILTIN_TMIABB
:
12828 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12829 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12830 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12831 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12832 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12833 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12834 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12835 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12836 : CODE_FOR_iwmmxt_walign
);
12837 arg0
= TREE_VALUE (arglist
);
12838 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12839 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12840 op0
= expand_normal (arg0
);
12841 op1
= expand_normal (arg1
);
12842 op2
= expand_normal (arg2
);
12843 tmode
= insn_data
[icode
].operand
[0].mode
;
12844 mode0
= insn_data
[icode
].operand
[1].mode
;
12845 mode1
= insn_data
[icode
].operand
[2].mode
;
12846 mode2
= insn_data
[icode
].operand
[3].mode
;
12848 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12849 op0
= copy_to_mode_reg (mode0
, op0
);
12850 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12851 op1
= copy_to_mode_reg (mode1
, op1
);
12852 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12853 op2
= copy_to_mode_reg (mode2
, op2
);
12855 || GET_MODE (target
) != tmode
12856 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12857 target
= gen_reg_rtx (tmode
);
12858 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12864 case ARM_BUILTIN_WZERO
:
12865 target
= gen_reg_rtx (DImode
);
12866 emit_insn (gen_iwmmxt_clrdi (target
));
12869 case ARM_BUILTIN_THREAD_POINTER
:
12870 return arm_load_tp (target
);
12876 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12877 if (d
->code
== (const enum arm_builtins
) fcode
)
12878 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12880 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12881 if (d
->code
== (const enum arm_builtins
) fcode
)
12882 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12884 /* @@@ Should really do something sensible here. */
12888 /* Return the number (counting from 0) of
12889 the least significant set bit in MASK. */
12892 number_of_first_bit_set (unsigned mask
)
12897 (mask
& (1 << bit
)) == 0;
12904 /* Emit code to push or pop registers to or from the stack. F is the
12905 assembly file. MASK is the registers to push or pop. PUSH is
12906 nonzero if we should push, and zero if we should pop. For debugging
12907 output, if pushing, adjust CFA_OFFSET by the amount of space added
12908 to the stack. REAL_REGS should have the same number of bits set as
12909 MASK, and will be used instead (in the same order) to describe which
12910 registers were saved - this is used to mark the save slots when we
12911 push high registers after moving them to low registers. */
12913 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12914 unsigned long real_regs
)
12917 int lo_mask
= mask
& 0xFF;
12918 int pushed_words
= 0;
12922 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12924 /* Special case. Do not generate a POP PC statement here, do it in
12926 thumb_exit (f
, -1);
12930 if (ARM_EABI_UNWIND_TABLES
&& push
)
12932 fprintf (f
, "\t.save\t{");
12933 for (regno
= 0; regno
< 15; regno
++)
12935 if (real_regs
& (1 << regno
))
12937 if (real_regs
& ((1 << regno
) -1))
12939 asm_fprintf (f
, "%r", regno
);
12942 fprintf (f
, "}\n");
12945 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12947 /* Look at the low registers first. */
12948 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12952 asm_fprintf (f
, "%r", regno
);
12954 if ((lo_mask
& ~1) != 0)
12961 if (push
&& (mask
& (1 << LR_REGNUM
)))
12963 /* Catch pushing the LR. */
12967 asm_fprintf (f
, "%r", LR_REGNUM
);
12971 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12973 /* Catch popping the PC. */
12974 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12975 || current_function_calls_eh_return
)
12977 /* The PC is never poped directly, instead
12978 it is popped into r3 and then BX is used. */
12979 fprintf (f
, "}\n");
12981 thumb_exit (f
, -1);
12990 asm_fprintf (f
, "%r", PC_REGNUM
);
12994 fprintf (f
, "}\n");
12996 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12998 char *l
= dwarf2out_cfi_label ();
12999 int pushed_mask
= real_regs
;
13001 *cfa_offset
+= pushed_words
* 4;
13002 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
13005 pushed_mask
= real_regs
;
13006 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
13008 if (pushed_mask
& 1)
13009 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
13014 /* Generate code to return from a thumb function.
13015 If 'reg_containing_return_addr' is -1, then the return address is
13016 actually on the stack, at the stack pointer. */
13018 thumb_exit (FILE *f
, int reg_containing_return_addr
)
13020 unsigned regs_available_for_popping
;
13021 unsigned regs_to_pop
;
13023 unsigned available
;
13027 int restore_a4
= FALSE
;
13029 /* Compute the registers we need to pop. */
13033 if (reg_containing_return_addr
== -1)
13035 regs_to_pop
|= 1 << LR_REGNUM
;
13039 if (TARGET_BACKTRACE
)
13041 /* Restore the (ARM) frame pointer and stack pointer. */
13042 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
13046 /* If there is nothing to pop then just emit the BX instruction and
13048 if (pops_needed
== 0)
13050 if (current_function_calls_eh_return
)
13051 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13053 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13056 /* Otherwise if we are not supporting interworking and we have not created
13057 a backtrace structure and the function was not entered in ARM mode then
13058 just pop the return address straight into the PC. */
13059 else if (!TARGET_INTERWORK
13060 && !TARGET_BACKTRACE
13061 && !is_called_in_ARM_mode (current_function_decl
)
13062 && !current_function_calls_eh_return
)
13064 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
13068 /* Find out how many of the (return) argument registers we can corrupt. */
13069 regs_available_for_popping
= 0;
13071 /* If returning via __builtin_eh_return, the bottom three registers
13072 all contain information needed for the return. */
13073 if (current_function_calls_eh_return
)
13077 /* If we can deduce the registers used from the function's
13078 return value. This is more reliable that examining
13079 regs_ever_live[] because that will be set if the register is
13080 ever used in the function, not just if the register is used
13081 to hold a return value. */
13083 if (current_function_return_rtx
!= 0)
13084 mode
= GET_MODE (current_function_return_rtx
);
13086 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13088 size
= GET_MODE_SIZE (mode
);
13092 /* In a void function we can use any argument register.
13093 In a function that returns a structure on the stack
13094 we can use the second and third argument registers. */
13095 if (mode
== VOIDmode
)
13096 regs_available_for_popping
=
13097 (1 << ARG_REGISTER (1))
13098 | (1 << ARG_REGISTER (2))
13099 | (1 << ARG_REGISTER (3));
13101 regs_available_for_popping
=
13102 (1 << ARG_REGISTER (2))
13103 | (1 << ARG_REGISTER (3));
13105 else if (size
<= 4)
13106 regs_available_for_popping
=
13107 (1 << ARG_REGISTER (2))
13108 | (1 << ARG_REGISTER (3));
13109 else if (size
<= 8)
13110 regs_available_for_popping
=
13111 (1 << ARG_REGISTER (3));
13114 /* Match registers to be popped with registers into which we pop them. */
13115 for (available
= regs_available_for_popping
,
13116 required
= regs_to_pop
;
13117 required
!= 0 && available
!= 0;
13118 available
&= ~(available
& - available
),
13119 required
&= ~(required
& - required
))
13122 /* If we have any popping registers left over, remove them. */
13124 regs_available_for_popping
&= ~available
;
13126 /* Otherwise if we need another popping register we can use
13127 the fourth argument register. */
13128 else if (pops_needed
)
13130 /* If we have not found any free argument registers and
13131 reg a4 contains the return address, we must move it. */
13132 if (regs_available_for_popping
== 0
13133 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
13135 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13136 reg_containing_return_addr
= LR_REGNUM
;
13138 else if (size
> 12)
13140 /* Register a4 is being used to hold part of the return value,
13141 but we have dire need of a free, low register. */
13144 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
13147 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
13149 /* The fourth argument register is available. */
13150 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
13156 /* Pop as many registers as we can. */
13157 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13158 regs_available_for_popping
);
13160 /* Process the registers we popped. */
13161 if (reg_containing_return_addr
== -1)
13163 /* The return address was popped into the lowest numbered register. */
13164 regs_to_pop
&= ~(1 << LR_REGNUM
);
13166 reg_containing_return_addr
=
13167 number_of_first_bit_set (regs_available_for_popping
);
13169 /* Remove this register for the mask of available registers, so that
13170 the return address will not be corrupted by further pops. */
13171 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
13174 /* If we popped other registers then handle them here. */
13175 if (regs_available_for_popping
)
13179 /* Work out which register currently contains the frame pointer. */
13180 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13182 /* Move it into the correct place. */
13183 asm_fprintf (f
, "\tmov\t%r, %r\n",
13184 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
13186 /* (Temporarily) remove it from the mask of popped registers. */
13187 regs_available_for_popping
&= ~(1 << frame_pointer
);
13188 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
13190 if (regs_available_for_popping
)
13194 /* We popped the stack pointer as well,
13195 find the register that contains it. */
13196 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13198 /* Move it into the stack register. */
13199 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
13201 /* At this point we have popped all necessary registers, so
13202 do not worry about restoring regs_available_for_popping
13203 to its correct value:
13205 assert (pops_needed == 0)
13206 assert (regs_available_for_popping == (1 << frame_pointer))
13207 assert (regs_to_pop == (1 << STACK_POINTER)) */
13211 /* Since we have just move the popped value into the frame
13212 pointer, the popping register is available for reuse, and
13213 we know that we still have the stack pointer left to pop. */
13214 regs_available_for_popping
|= (1 << frame_pointer
);
13218 /* If we still have registers left on the stack, but we no longer have
13219 any registers into which we can pop them, then we must move the return
13220 address into the link register and make available the register that
13222 if (regs_available_for_popping
== 0 && pops_needed
> 0)
13224 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
13226 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
13227 reg_containing_return_addr
);
13229 reg_containing_return_addr
= LR_REGNUM
;
13232 /* If we have registers left on the stack then pop some more.
13233 We know that at most we will want to pop FP and SP. */
13234 if (pops_needed
> 0)
13239 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13240 regs_available_for_popping
);
13242 /* We have popped either FP or SP.
13243 Move whichever one it is into the correct register. */
13244 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13245 move_to
= number_of_first_bit_set (regs_to_pop
);
13247 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
13249 regs_to_pop
&= ~(1 << move_to
);
13254 /* If we still have not popped everything then we must have only
13255 had one register available to us and we are now popping the SP. */
13256 if (pops_needed
> 0)
13260 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13261 regs_available_for_popping
);
13263 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13265 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
13267 assert (regs_to_pop == (1 << STACK_POINTER))
13268 assert (pops_needed == 1)
13272 /* If necessary restore the a4 register. */
13275 if (reg_containing_return_addr
!= LR_REGNUM
)
13277 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13278 reg_containing_return_addr
= LR_REGNUM
;
13281 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13284 if (current_function_calls_eh_return
)
13285 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13287 /* Return to caller. */
13288 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13293 thumb_final_prescan_insn (rtx insn
)
13295 if (flag_print_asm_name
)
13296 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
13297 INSN_ADDRESSES (INSN_UID (insn
)));
13301 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
13303 unsigned HOST_WIDE_INT mask
= 0xff;
13306 if (val
== 0) /* XXX */
13309 for (i
= 0; i
< 25; i
++)
13310 if ((val
& (mask
<< i
)) == val
)
13316 /* Returns nonzero if the current function contains,
13317 or might contain a far jump. */
13319 thumb_far_jump_used_p (void)
13323 /* This test is only important for leaf functions. */
13324 /* assert (!leaf_function_p ()); */
13326 /* If we have already decided that far jumps may be used,
13327 do not bother checking again, and always return true even if
13328 it turns out that they are not being used. Once we have made
13329 the decision that far jumps are present (and that hence the link
13330 register will be pushed onto the stack) we cannot go back on it. */
13331 if (cfun
->machine
->far_jump_used
)
13334 /* If this function is not being called from the prologue/epilogue
13335 generation code then it must be being called from the
13336 INITIAL_ELIMINATION_OFFSET macro. */
13337 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
13339 /* In this case we know that we are being asked about the elimination
13340 of the arg pointer register. If that register is not being used,
13341 then there are no arguments on the stack, and we do not have to
13342 worry that a far jump might force the prologue to push the link
13343 register, changing the stack offsets. In this case we can just
13344 return false, since the presence of far jumps in the function will
13345 not affect stack offsets.
13347 If the arg pointer is live (or if it was live, but has now been
13348 eliminated and so set to dead) then we do have to test to see if
13349 the function might contain a far jump. This test can lead to some
13350 false negatives, since before reload is completed, then length of
13351 branch instructions is not known, so gcc defaults to returning their
13352 longest length, which in turn sets the far jump attribute to true.
13354 A false negative will not result in bad code being generated, but it
13355 will result in a needless push and pop of the link register. We
13356 hope that this does not occur too often.
13358 If we need doubleword stack alignment this could affect the other
13359 elimination offsets so we can't risk getting it wrong. */
13360 if (regs_ever_live
[ARG_POINTER_REGNUM
])
13361 cfun
->machine
->arg_pointer_live
= 1;
13362 else if (!cfun
->machine
->arg_pointer_live
)
13366 /* Check to see if the function contains a branch
13367 insn with the far jump attribute set. */
13368 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13370 if (GET_CODE (insn
) == JUMP_INSN
13371 /* Ignore tablejump patterns. */
13372 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
13373 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
13374 && get_attr_far_jump (insn
) == FAR_JUMP_YES
13377 /* Record the fact that we have decided that
13378 the function does use far jumps. */
13379 cfun
->machine
->far_jump_used
= 1;
13387 /* Return nonzero if FUNC must be entered in ARM mode. */
13389 is_called_in_ARM_mode (tree func
)
13391 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
13393 /* Ignore the problem about functions whose address is taken. */
13394 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
13398 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
13404 /* The bits which aren't usefully expanded as rtl. */
13406 thumb_unexpanded_epilogue (void)
13409 unsigned long live_regs_mask
= 0;
13410 int high_regs_pushed
= 0;
13411 int had_to_push_lr
;
13414 if (return_used_this_function
)
13417 if (IS_NAKED (arm_current_func_type ()))
13420 live_regs_mask
= thumb_compute_save_reg_mask ();
13421 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13423 /* If we can deduce the registers used from the function's return value.
13424 This is more reliable that examining regs_ever_live[] because that
13425 will be set if the register is ever used in the function, not just if
13426 the register is used to hold a return value. */
13427 size
= arm_size_return_regs ();
13429 /* The prolog may have pushed some high registers to use as
13430 work registers. e.g. the testsuite file:
13431 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13432 compiles to produce:
13433 push {r4, r5, r6, r7, lr}
13437 as part of the prolog. We have to undo that pushing here. */
13439 if (high_regs_pushed
)
13441 unsigned long mask
= live_regs_mask
& 0xff;
13444 /* The available low registers depend on the size of the value we are
13452 /* Oh dear! We have no low registers into which we can pop
13455 ("no low registers available for popping high registers");
13457 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13458 if (live_regs_mask
& (1 << next_hi_reg
))
13461 while (high_regs_pushed
)
13463 /* Find lo register(s) into which the high register(s) can
13465 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13467 if (mask
& (1 << regno
))
13468 high_regs_pushed
--;
13469 if (high_regs_pushed
== 0)
13473 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13475 /* Pop the values into the low register(s). */
13476 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13478 /* Move the value(s) into the high registers. */
13479 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13481 if (mask
& (1 << regno
))
13483 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13486 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13487 if (live_regs_mask
& (1 << next_hi_reg
))
13492 live_regs_mask
&= ~0x0f00;
13495 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13496 live_regs_mask
&= 0xff;
13498 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13500 /* Pop the return address into the PC. */
13501 if (had_to_push_lr
)
13502 live_regs_mask
|= 1 << PC_REGNUM
;
13504 /* Either no argument registers were pushed or a backtrace
13505 structure was created which includes an adjusted stack
13506 pointer, so just pop everything. */
13507 if (live_regs_mask
)
13508 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13511 /* We have either just popped the return address into the
13512 PC or it is was kept in LR for the entire function. */
13513 if (!had_to_push_lr
)
13514 thumb_exit (asm_out_file
, LR_REGNUM
);
13518 /* Pop everything but the return address. */
13519 if (live_regs_mask
)
13520 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13523 if (had_to_push_lr
)
13527 /* We have no free low regs, so save one. */
13528 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13532 /* Get the return address into a temporary register. */
13533 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13534 1 << LAST_ARG_REGNUM
);
13538 /* Move the return address to lr. */
13539 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13541 /* Restore the low register. */
13542 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13547 regno
= LAST_ARG_REGNUM
;
13552 /* Remove the argument registers that were pushed onto the stack. */
13553 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13554 SP_REGNUM
, SP_REGNUM
,
13555 current_function_pretend_args_size
);
13557 thumb_exit (asm_out_file
, regno
);
13563 /* Functions to save and restore machine-specific function data. */
13564 static struct machine_function
*
13565 arm_init_machine_status (void)
13567 struct machine_function
*machine
;
13568 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13570 #if ARM_FT_UNKNOWN != 0
13571 machine
->func_type
= ARM_FT_UNKNOWN
;
13576 /* Return an RTX indicating where the return address to the
13577 calling function can be found. */
13579 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13584 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13587 /* Do anything needed before RTL is emitted for each function. */
13589 arm_init_expanders (void)
13591 /* Arrange to initialize and mark the machine per-function status. */
13592 init_machine_status
= arm_init_machine_status
;
13594 /* This is to stop the combine pass optimizing away the alignment
13595 adjustment of va_arg. */
13596 /* ??? It is claimed that this should not be necessary. */
13598 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13602 /* Like arm_compute_initial_elimination offset. Simpler because there
13603 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13604 to point at the base of the local variables after static stack
13605 space for a function has been allocated. */
13608 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13610 arm_stack_offsets
*offsets
;
13612 offsets
= arm_get_frame_offsets ();
13616 case ARG_POINTER_REGNUM
:
13619 case STACK_POINTER_REGNUM
:
13620 return offsets
->outgoing_args
- offsets
->saved_args
;
13622 case FRAME_POINTER_REGNUM
:
13623 return offsets
->soft_frame
- offsets
->saved_args
;
13625 case ARM_HARD_FRAME_POINTER_REGNUM
:
13626 return offsets
->saved_regs
- offsets
->saved_args
;
13628 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13629 return offsets
->locals_base
- offsets
->saved_args
;
13632 gcc_unreachable ();
13636 case FRAME_POINTER_REGNUM
:
13639 case STACK_POINTER_REGNUM
:
13640 return offsets
->outgoing_args
- offsets
->soft_frame
;
13642 case ARM_HARD_FRAME_POINTER_REGNUM
:
13643 return offsets
->saved_regs
- offsets
->soft_frame
;
13645 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13646 return offsets
->locals_base
- offsets
->soft_frame
;
13649 gcc_unreachable ();
13654 gcc_unreachable ();
13659 /* Generate the rest of a function's prologue. */
13661 thumb_expand_prologue (void)
13665 HOST_WIDE_INT amount
;
13666 arm_stack_offsets
*offsets
;
13667 unsigned long func_type
;
13669 unsigned long live_regs_mask
;
13671 func_type
= arm_current_func_type ();
13673 /* Naked functions don't have prologues. */
13674 if (IS_NAKED (func_type
))
13677 if (IS_INTERRUPT (func_type
))
13679 error ("interrupt Service Routines cannot be coded in Thumb mode");
13683 live_regs_mask
= thumb_compute_save_reg_mask ();
13684 /* Load the pic register before setting the frame pointer,
13685 so we can use r7 as a temporary work register. */
13686 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
13687 arm_load_pic_register (live_regs_mask
);
13689 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13690 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
13691 stack_pointer_rtx
);
13693 offsets
= arm_get_frame_offsets ();
13694 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13699 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13700 GEN_INT (- amount
)));
13701 RTX_FRAME_RELATED_P (insn
) = 1;
13707 /* The stack decrement is too big for an immediate value in a single
13708 insn. In theory we could issue multiple subtracts, but after
13709 three of them it becomes more space efficient to place the full
13710 value in the constant pool and load into a register. (Also the
13711 ARM debugger really likes to see only one stack decrement per
13712 function). So instead we look for a scratch register into which
13713 we can load the decrement, and then we subtract this from the
13714 stack pointer. Unfortunately on the thumb the only available
13715 scratch registers are the argument registers, and we cannot use
13716 these as they may hold arguments to the function. Instead we
13717 attempt to locate a call preserved register which is used by this
13718 function. If we can find one, then we know that it will have
13719 been pushed at the start of the prologue and so we can corrupt
13721 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13722 if (live_regs_mask
& (1 << regno
)
13723 && !(frame_pointer_needed
13724 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13727 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13729 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13731 /* Choose an arbitrary, non-argument low register. */
13732 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13734 /* Save it by copying it into a high, scratch register. */
13735 emit_insn (gen_movsi (spare
, reg
));
13736 /* Add a USE to stop propagate_one_insn() from barfing. */
13737 emit_insn (gen_prologue_use (spare
));
13739 /* Decrement the stack. */
13740 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13741 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13742 stack_pointer_rtx
, reg
));
13743 RTX_FRAME_RELATED_P (insn
) = 1;
13744 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13745 plus_constant (stack_pointer_rtx
,
13747 RTX_FRAME_RELATED_P (dwarf
) = 1;
13749 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13752 /* Restore the low register's original value. */
13753 emit_insn (gen_movsi (reg
, spare
));
13755 /* Emit a USE of the restored scratch register, so that flow
13756 analysis will not consider the restore redundant. The
13757 register won't be used again in this function and isn't
13758 restored by the epilogue. */
13759 emit_insn (gen_prologue_use (reg
));
13763 reg
= gen_rtx_REG (SImode
, regno
);
13765 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13767 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13768 stack_pointer_rtx
, reg
));
13769 RTX_FRAME_RELATED_P (insn
) = 1;
13770 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13771 plus_constant (stack_pointer_rtx
,
13773 RTX_FRAME_RELATED_P (dwarf
) = 1;
13775 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13781 if (frame_pointer_needed
)
13783 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
13786 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13787 stack_pointer_rtx
, GEN_INT (amount
)));
13790 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
13791 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13792 hard_frame_pointer_rtx
,
13793 stack_pointer_rtx
));
13794 dwarf
= gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
13795 plus_constant (stack_pointer_rtx
, amount
));
13796 RTX_FRAME_RELATED_P (dwarf
) = 1;
13797 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13801 RTX_FRAME_RELATED_P (insn
) = 1;
13804 /* If we are profiling, make sure no instructions are scheduled before
13805 the call to mcount. Similarly if the user has requested no
13806 scheduling in the prolog. Similarly if we want non-call exceptions
13807 using the EABI unwinder, to prevent faulting instructions from being
13808 swapped with a stack adjustment. */
13809 if (current_function_profile
|| !TARGET_SCHED_PROLOG
13810 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
13811 emit_insn (gen_blockage ());
13813 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13814 if (live_regs_mask
& 0xff)
13815 cfun
->machine
->lr_save_eliminated
= 0;
13817 /* If the link register is being kept alive, with the return address in it,
13818 then make sure that it does not get reused by the ce2 pass. */
13819 if (cfun
->machine
->lr_save_eliminated
)
13820 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13825 thumb_expand_epilogue (void)
13827 HOST_WIDE_INT amount
;
13828 arm_stack_offsets
*offsets
;
13831 /* Naked functions don't have prologues. */
13832 if (IS_NAKED (arm_current_func_type ()))
13835 offsets
= arm_get_frame_offsets ();
13836 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13838 if (frame_pointer_needed
)
13840 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13841 amount
= offsets
->locals_base
- offsets
->saved_regs
;
13847 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13848 GEN_INT (amount
)));
13851 /* r3 is always free in the epilogue. */
13852 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13854 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13855 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13859 /* Emit a USE (stack_pointer_rtx), so that
13860 the stack adjustment will not be deleted. */
13861 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13863 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13864 emit_insn (gen_blockage ());
13866 /* Emit a clobber for each insn that will be restored in the epilogue,
13867 so that flow2 will get register lifetimes correct. */
13868 for (regno
= 0; regno
< 13; regno
++)
13869 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13870 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13872 if (! regs_ever_live
[LR_REGNUM
])
13873 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13877 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13879 unsigned long live_regs_mask
= 0;
13880 unsigned long l_mask
;
13881 unsigned high_regs_pushed
= 0;
13882 int cfa_offset
= 0;
13885 if (IS_NAKED (arm_current_func_type ()))
13888 if (is_called_in_ARM_mode (current_function_decl
))
13892 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
13893 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
13895 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13897 /* Generate code sequence to switch us into Thumb mode. */
13898 /* The .code 32 directive has already been emitted by
13899 ASM_DECLARE_FUNCTION_NAME. */
13900 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13901 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13903 /* Generate a label, so that the debugger will notice the
13904 change in instruction sets. This label is also used by
13905 the assembler to bypass the ARM code when this function
13906 is called from a Thumb encoded function elsewhere in the
13907 same file. Hence the definition of STUB_NAME here must
13908 agree with the definition in gas/config/tc-arm.c. */
13910 #define STUB_NAME ".real_start_of"
13912 fprintf (f
, "\t.code\t16\n");
13914 if (arm_dllexport_name_p (name
))
13915 name
= arm_strip_name_encoding (name
);
13917 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13918 fprintf (f
, "\t.thumb_func\n");
13919 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13922 if (current_function_pretend_args_size
)
13924 /* Output unwind directive for the stack adjustment. */
13925 if (ARM_EABI_UNWIND_TABLES
)
13926 fprintf (f
, "\t.pad #%d\n",
13927 current_function_pretend_args_size
);
13929 if (cfun
->machine
->uses_anonymous_args
)
13933 fprintf (f
, "\tpush\t{");
13935 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13937 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13938 regno
<= LAST_ARG_REGNUM
;
13940 asm_fprintf (f
, "%r%s", regno
,
13941 regno
== LAST_ARG_REGNUM
? "" : ", ");
13943 fprintf (f
, "}\n");
13946 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13947 SP_REGNUM
, SP_REGNUM
,
13948 current_function_pretend_args_size
);
13950 /* We don't need to record the stores for unwinding (would it
13951 help the debugger any if we did?), but record the change in
13952 the stack pointer. */
13953 if (dwarf2out_do_frame ())
13955 char *l
= dwarf2out_cfi_label ();
13957 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13958 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13962 /* Get the registers we are going to push. */
13963 live_regs_mask
= thumb_compute_save_reg_mask ();
13964 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13965 l_mask
= live_regs_mask
& 0x40ff;
13966 /* Then count how many other high registers will need to be pushed. */
13967 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13969 if (TARGET_BACKTRACE
)
13972 unsigned work_register
;
13974 /* We have been asked to create a stack backtrace structure.
13975 The code looks like this:
13979 0 sub SP, #16 Reserve space for 4 registers.
13980 2 push {R7} Push low registers.
13981 4 add R7, SP, #20 Get the stack pointer before the push.
13982 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13983 8 mov R7, PC Get hold of the start of this code plus 12.
13984 10 str R7, [SP, #16] Store it.
13985 12 mov R7, FP Get hold of the current frame pointer.
13986 14 str R7, [SP, #4] Store it.
13987 16 mov R7, LR Get hold of the current return address.
13988 18 str R7, [SP, #12] Store it.
13989 20 add R7, SP, #16 Point at the start of the backtrace structure.
13990 22 mov FP, R7 Put this value into the frame pointer. */
13992 work_register
= thumb_find_work_register (live_regs_mask
);
13994 if (ARM_EABI_UNWIND_TABLES
)
13995 asm_fprintf (f
, "\t.pad #16\n");
13998 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13999 SP_REGNUM
, SP_REGNUM
);
14001 if (dwarf2out_do_frame ())
14003 char *l
= dwarf2out_cfi_label ();
14005 cfa_offset
= cfa_offset
+ 16;
14006 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
14011 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
14012 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
14017 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
14018 offset
+ 16 + current_function_pretend_args_size
);
14020 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14023 /* Make sure that the instruction fetching the PC is in the right place
14024 to calculate "start of backtrace creation code + 12". */
14027 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
14028 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14030 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
14031 ARM_HARD_FRAME_POINTER_REGNUM
);
14032 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14037 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
14038 ARM_HARD_FRAME_POINTER_REGNUM
);
14039 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14041 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
14042 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14046 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
14047 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14049 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
14051 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
14052 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
14054 /* Optimization: If we are not pushing any low registers but we are going
14055 to push some high registers then delay our first push. This will just
14056 be a push of LR and we can combine it with the push of the first high
14058 else if ((l_mask
& 0xff) != 0
14059 || (high_regs_pushed
== 0 && l_mask
))
14060 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
14062 if (high_regs_pushed
)
14064 unsigned pushable_regs
;
14065 unsigned next_hi_reg
;
14067 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
14068 if (live_regs_mask
& (1 << next_hi_reg
))
14071 pushable_regs
= l_mask
& 0xff;
14073 if (pushable_regs
== 0)
14074 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
14076 while (high_regs_pushed
> 0)
14078 unsigned long real_regs_mask
= 0;
14080 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
14082 if (pushable_regs
& (1 << regno
))
14084 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
14086 high_regs_pushed
--;
14087 real_regs_mask
|= (1 << next_hi_reg
);
14089 if (high_regs_pushed
)
14091 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
14093 if (live_regs_mask
& (1 << next_hi_reg
))
14098 pushable_regs
&= ~((1 << regno
) - 1);
14104 /* If we had to find a work register and we have not yet
14105 saved the LR then add it to the list of regs to push. */
14106 if (l_mask
== (1 << LR_REGNUM
))
14108 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
14110 real_regs_mask
| (1 << LR_REGNUM
));
14114 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
14119 /* Handle the case of a double word load into a low register from
14120 a computed memory address. The computed address may involve a
14121 register which is overwritten by the load. */
14123 thumb_load_double_from_address (rtx
*operands
)
14131 gcc_assert (GET_CODE (operands
[0]) == REG
);
14132 gcc_assert (GET_CODE (operands
[1]) == MEM
);
14134 /* Get the memory address. */
14135 addr
= XEXP (operands
[1], 0);
14137 /* Work out how the memory address is computed. */
14138 switch (GET_CODE (addr
))
14141 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14143 if (REGNO (operands
[0]) == REGNO (addr
))
14145 output_asm_insn ("ldr\t%H0, %2", operands
);
14146 output_asm_insn ("ldr\t%0, %1", operands
);
14150 output_asm_insn ("ldr\t%0, %1", operands
);
14151 output_asm_insn ("ldr\t%H0, %2", operands
);
14156 /* Compute <address> + 4 for the high order load. */
14157 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14159 output_asm_insn ("ldr\t%0, %1", operands
);
14160 output_asm_insn ("ldr\t%H0, %2", operands
);
14164 arg1
= XEXP (addr
, 0);
14165 arg2
= XEXP (addr
, 1);
14167 if (CONSTANT_P (arg1
))
14168 base
= arg2
, offset
= arg1
;
14170 base
= arg1
, offset
= arg2
;
14172 gcc_assert (GET_CODE (base
) == REG
);
14174 /* Catch the case of <address> = <reg> + <reg> */
14175 if (GET_CODE (offset
) == REG
)
14177 int reg_offset
= REGNO (offset
);
14178 int reg_base
= REGNO (base
);
14179 int reg_dest
= REGNO (operands
[0]);
14181 /* Add the base and offset registers together into the
14182 higher destination register. */
14183 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
14184 reg_dest
+ 1, reg_base
, reg_offset
);
14186 /* Load the lower destination register from the address in
14187 the higher destination register. */
14188 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
14189 reg_dest
, reg_dest
+ 1);
14191 /* Load the higher destination register from its own address
14193 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
14194 reg_dest
+ 1, reg_dest
+ 1);
14198 /* Compute <address> + 4 for the high order load. */
14199 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14201 /* If the computed address is held in the low order register
14202 then load the high order register first, otherwise always
14203 load the low order register first. */
14204 if (REGNO (operands
[0]) == REGNO (base
))
14206 output_asm_insn ("ldr\t%H0, %2", operands
);
14207 output_asm_insn ("ldr\t%0, %1", operands
);
14211 output_asm_insn ("ldr\t%0, %1", operands
);
14212 output_asm_insn ("ldr\t%H0, %2", operands
);
14218 /* With no registers to worry about we can just load the value
14220 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14222 output_asm_insn ("ldr\t%H0, %2", operands
);
14223 output_asm_insn ("ldr\t%0, %1", operands
);
14227 gcc_unreachable ();
14234 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
14241 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14244 operands
[4] = operands
[5];
14247 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
14248 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
14252 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14255 operands
[4] = operands
[5];
14258 if (REGNO (operands
[5]) > REGNO (operands
[6]))
14261 operands
[5] = operands
[6];
14264 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14267 operands
[4] = operands
[5];
14271 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
14272 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
14276 gcc_unreachable ();
14282 /* Output a call-via instruction for thumb state. */
14284 thumb_call_via_reg (rtx reg
)
14286 int regno
= REGNO (reg
);
14289 gcc_assert (regno
< LR_REGNUM
);
14291 /* If we are in the normal text section we can use a single instance
14292 per compilation unit. If we are doing function sections, then we need
14293 an entry per section, since we can't rely on reachability. */
14294 if (in_section
== text_section
)
14296 thumb_call_reg_needed
= 1;
14298 if (thumb_call_via_label
[regno
] == NULL
)
14299 thumb_call_via_label
[regno
] = gen_label_rtx ();
14300 labelp
= thumb_call_via_label
+ regno
;
14304 if (cfun
->machine
->call_via
[regno
] == NULL
)
14305 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
14306 labelp
= cfun
->machine
->call_via
+ regno
;
14309 output_asm_insn ("bl\t%a0", labelp
);
14313 /* Routines for generating rtl. */
14315 thumb_expand_movmemqi (rtx
*operands
)
14317 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
14318 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
14319 HOST_WIDE_INT len
= INTVAL (operands
[2]);
14320 HOST_WIDE_INT offset
= 0;
14324 emit_insn (gen_movmem12b (out
, in
, out
, in
));
14330 emit_insn (gen_movmem8b (out
, in
, out
, in
));
14336 rtx reg
= gen_reg_rtx (SImode
);
14337 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
14338 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
14345 rtx reg
= gen_reg_rtx (HImode
);
14346 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
14347 plus_constant (in
, offset
))));
14348 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
14356 rtx reg
= gen_reg_rtx (QImode
);
14357 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
14358 plus_constant (in
, offset
))));
14359 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
14365 thumb_reload_out_hi (rtx
*operands
)
14367 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
14370 /* Handle reading a half-word from memory during reload. */
14372 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
14374 gcc_unreachable ();
14377 /* Return the length of a function name prefix
14378 that starts with the character 'c'. */
14380 arm_get_strip_length (int c
)
14384 ARM_NAME_ENCODING_LENGTHS
14389 /* Return a pointer to a function's name with any
14390 and all prefix encodings stripped from it. */
14392 arm_strip_name_encoding (const char *name
)
14396 while ((skip
= arm_get_strip_length (* name
)))
14402 /* If there is a '*' anywhere in the name's prefix, then
14403 emit the stripped name verbatim, otherwise prepend an
14404 underscore if leading underscores are being used. */
14406 arm_asm_output_labelref (FILE *stream
, const char *name
)
14411 while ((skip
= arm_get_strip_length (* name
)))
14413 verbatim
|= (*name
== '*');
14418 fputs (name
, stream
);
14420 asm_fprintf (stream
, "%U%s", name
);
14424 arm_file_start (void)
14430 const char *fpu_name
;
14431 if (arm_select
[0].string
)
14432 asm_fprintf (asm_out_file
, "\t.cpu %s\n", arm_select
[0].string
);
14433 else if (arm_select
[1].string
)
14434 asm_fprintf (asm_out_file
, "\t.arch %s\n", arm_select
[1].string
);
14436 asm_fprintf (asm_out_file
, "\t.cpu %s\n",
14437 all_cores
[arm_default_cpu
].name
);
14439 if (TARGET_SOFT_FLOAT
)
14442 fpu_name
= "softvfp";
14444 fpu_name
= "softfpa";
14448 switch (arm_fpu_arch
)
14453 case FPUTYPE_FPA_EMU2
:
14456 case FPUTYPE_FPA_EMU3
:
14459 case FPUTYPE_MAVERICK
:
14460 fpu_name
= "maverick";
14463 if (TARGET_HARD_FLOAT
)
14464 asm_fprintf (asm_out_file
, "\t.eabi_attribute 27, 3\n");
14465 if (TARGET_HARD_FLOAT_ABI
)
14466 asm_fprintf (asm_out_file
, "\t.eabi_attribute 28, 1\n");
14473 asm_fprintf (asm_out_file
, "\t.fpu %s\n", fpu_name
);
14475 /* Some of these attributes only apply when the corresponding features
14476 are used. However we don't have any easy way of figuring this out.
14477 Conservatively record the setting that would have been used. */
14479 /* Tag_ABI_PCS_wchar_t. */
14480 asm_fprintf (asm_out_file
, "\t.eabi_attribute 18, %d\n",
14481 (int)WCHAR_TYPE_SIZE
/ BITS_PER_UNIT
);
14483 /* Tag_ABI_FP_rounding. */
14484 if (flag_rounding_math
)
14485 asm_fprintf (asm_out_file
, "\t.eabi_attribute 19, 1\n");
14486 if (!flag_unsafe_math_optimizations
)
14488 /* Tag_ABI_FP_denomal. */
14489 asm_fprintf (asm_out_file
, "\t.eabi_attribute 20, 1\n");
14490 /* Tag_ABI_FP_exceptions. */
14491 asm_fprintf (asm_out_file
, "\t.eabi_attribute 21, 1\n");
14493 /* Tag_ABI_FP_user_exceptions. */
14494 if (flag_signaling_nans
)
14495 asm_fprintf (asm_out_file
, "\t.eabi_attribute 22, 1\n");
14496 /* Tag_ABI_FP_number_model. */
14497 asm_fprintf (asm_out_file
, "\t.eabi_attribute 23, %d\n",
14498 flag_finite_math_only
? 1 : 3);
14500 /* Tag_ABI_align8_needed. */
14501 asm_fprintf (asm_out_file
, "\t.eabi_attribute 24, 1\n");
14502 /* Tag_ABI_align8_preserved. */
14503 asm_fprintf (asm_out_file
, "\t.eabi_attribute 25, 1\n");
14504 /* Tag_ABI_enum_size. */
14505 asm_fprintf (asm_out_file
, "\t.eabi_attribute 26, %d\n",
14506 flag_short_enums
? 1 : 2);
14508 /* Tag_ABI_optimization_goals. */
14511 else if (optimize
>= 2)
14517 asm_fprintf (asm_out_file
, "\t.eabi_attribute 30, %d\n", val
);
14519 default_file_start();
14523 arm_file_end (void)
14527 if (NEED_INDICATE_EXEC_STACK
)
14528 /* Add .note.GNU-stack. */
14529 file_end_indicate_exec_stack ();
14531 if (! thumb_call_reg_needed
)
14534 switch_to_section (text_section
);
14535 asm_fprintf (asm_out_file
, "\t.code 16\n");
14536 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
14538 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
14540 rtx label
= thumb_call_via_label
[regno
];
14544 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14545 CODE_LABEL_NUMBER (label
));
14546 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14553 #ifdef AOF_ASSEMBLER
14554 /* Special functions only needed when producing AOF syntax assembler. */
14558 struct pic_chain
* next
;
14559 const char * symname
;
14562 static struct pic_chain
* aof_pic_chain
= NULL
;
14565 aof_pic_entry (rtx x
)
14567 struct pic_chain
** chainp
;
14570 if (aof_pic_label
== NULL_RTX
)
14572 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14575 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14576 offset
+= 4, chainp
= &(*chainp
)->next
)
14577 if ((*chainp
)->symname
== XSTR (x
, 0))
14578 return plus_constant (aof_pic_label
, offset
);
14580 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14581 (*chainp
)->next
= NULL
;
14582 (*chainp
)->symname
= XSTR (x
, 0);
14583 return plus_constant (aof_pic_label
, offset
);
14587 aof_dump_pic_table (FILE *f
)
14589 struct pic_chain
* chain
;
14591 if (aof_pic_chain
== NULL
)
14594 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14595 PIC_OFFSET_TABLE_REGNUM
,
14596 PIC_OFFSET_TABLE_REGNUM
);
14597 fputs ("|x$adcons|\n", f
);
14599 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14601 fputs ("\tDCD\t", f
);
14602 assemble_name (f
, chain
->symname
);
14607 int arm_text_section_count
= 1;
14609 /* A get_unnamed_section callback for switching to the text section. */
14612 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
14614 fprintf (asm_out_file
, "\tAREA |C$$code%d|, CODE, READONLY",
14615 arm_text_section_count
++);
14617 fprintf (asm_out_file
, ", PIC, REENTRANT");
14618 fprintf (asm_out_file
, "\n");
14621 static int arm_data_section_count
= 1;
14623 /* A get_unnamed_section callback for switching to the data section. */
14626 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
14628 fprintf (asm_out_file
, "\tAREA |C$$data%d|, DATA\n",
14629 arm_data_section_count
++);
14632 /* Implement TARGET_ASM_INIT_SECTIONS.
14634 AOF Assembler syntax is a nightmare when it comes to areas, since once
14635 we change from one area to another, we can't go back again. Instead,
14636 we must create a new area with the same attributes and add the new output
14637 to that. Unfortunately, there is nothing we can do here to guarantee that
14638 two areas with the same attributes will be linked adjacently in the
14639 resulting executable, so we have to be careful not to do pc-relative
14640 addressing across such boundaries. */
14643 aof_asm_init_sections (void)
14645 text_section
= get_unnamed_section (SECTION_CODE
,
14646 aof_output_text_section_asm_op
, NULL
);
14647 data_section
= get_unnamed_section (SECTION_WRITE
,
14648 aof_output_data_section_asm_op
, NULL
);
14649 readonly_data_section
= text_section
;
14653 zero_init_section (void)
14655 static int zero_init_count
= 1;
14657 fprintf (asm_out_file
, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count
++);
14661 /* The AOF assembler is religiously strict about declarations of
14662 imported and exported symbols, so that it is impossible to declare
14663 a function as imported near the beginning of the file, and then to
14664 export it later on. It is, however, possible to delay the decision
14665 until all the functions in the file have been compiled. To get
14666 around this, we maintain a list of the imports and exports, and
14667 delete from it any that are subsequently defined. At the end of
14668 compilation we spit the remainder of the list out before the END
14673 struct import
* next
;
14677 static struct import
* imports_list
= NULL
;
14680 aof_add_import (const char *name
)
14682 struct import
* new;
14684 for (new = imports_list
; new; new = new->next
)
14685 if (new->name
== name
)
14688 new = (struct import
*) xmalloc (sizeof (struct import
));
14689 new->next
= imports_list
;
14690 imports_list
= new;
14695 aof_delete_import (const char *name
)
14697 struct import
** old
;
14699 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14701 if ((*old
)->name
== name
)
14703 *old
= (*old
)->next
;
14709 int arm_main_function
= 0;
14712 aof_dump_imports (FILE *f
)
14714 /* The AOF assembler needs this to cause the startup code to be extracted
14715 from the library. Brining in __main causes the whole thing to work
14717 if (arm_main_function
)
14719 switch_to_section (text_section
);
14720 fputs ("\tIMPORT __main\n", f
);
14721 fputs ("\tDCD __main\n", f
);
14724 /* Now dump the remaining imports. */
14725 while (imports_list
)
14727 fprintf (f
, "\tIMPORT\t");
14728 assemble_name (f
, imports_list
->name
);
14730 imports_list
= imports_list
->next
;
14735 aof_globalize_label (FILE *stream
, const char *name
)
14737 default_globalize_label (stream
, name
);
14738 if (! strcmp (name
, "main"))
14739 arm_main_function
= 1;
14743 aof_file_start (void)
14745 fputs ("__r0\tRN\t0\n", asm_out_file
);
14746 fputs ("__a1\tRN\t0\n", asm_out_file
);
14747 fputs ("__a2\tRN\t1\n", asm_out_file
);
14748 fputs ("__a3\tRN\t2\n", asm_out_file
);
14749 fputs ("__a4\tRN\t3\n", asm_out_file
);
14750 fputs ("__v1\tRN\t4\n", asm_out_file
);
14751 fputs ("__v2\tRN\t5\n", asm_out_file
);
14752 fputs ("__v3\tRN\t6\n", asm_out_file
);
14753 fputs ("__v4\tRN\t7\n", asm_out_file
);
14754 fputs ("__v5\tRN\t8\n", asm_out_file
);
14755 fputs ("__v6\tRN\t9\n", asm_out_file
);
14756 fputs ("__sl\tRN\t10\n", asm_out_file
);
14757 fputs ("__fp\tRN\t11\n", asm_out_file
);
14758 fputs ("__ip\tRN\t12\n", asm_out_file
);
14759 fputs ("__sp\tRN\t13\n", asm_out_file
);
14760 fputs ("__lr\tRN\t14\n", asm_out_file
);
14761 fputs ("__pc\tRN\t15\n", asm_out_file
);
14762 fputs ("__f0\tFN\t0\n", asm_out_file
);
14763 fputs ("__f1\tFN\t1\n", asm_out_file
);
14764 fputs ("__f2\tFN\t2\n", asm_out_file
);
14765 fputs ("__f3\tFN\t3\n", asm_out_file
);
14766 fputs ("__f4\tFN\t4\n", asm_out_file
);
14767 fputs ("__f5\tFN\t5\n", asm_out_file
);
14768 fputs ("__f6\tFN\t6\n", asm_out_file
);
14769 fputs ("__f7\tFN\t7\n", asm_out_file
);
14770 switch_to_section (text_section
);
14774 aof_file_end (void)
14777 aof_dump_pic_table (asm_out_file
);
14779 aof_dump_imports (asm_out_file
);
14780 fputs ("\tEND\n", asm_out_file
);
14782 #endif /* AOF_ASSEMBLER */
14785 /* Symbols in the text segment can be accessed without indirecting via the
14786 constant pool; it may take an extra binary operation, but this is still
14787 faster than indirecting via memory. Don't do this when not optimizing,
14788 since we won't be calculating al of the offsets necessary to do this
14792 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14794 /* This doesn't work with AOF syntax, since the string table may be in
14795 a different AREA. */
14796 #ifndef AOF_ASSEMBLER
14797 if (optimize
> 0 && TREE_CONSTANT (decl
))
14798 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14801 /* If we are referencing a function that is weak then encode a long call
14802 flag in the function name, otherwise if the function is static or
14803 or known to be defined in this file then encode a short call flag. */
14804 if (first
&& DECL_P (decl
))
14806 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14807 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14808 else if (! TREE_PUBLIC (decl
))
14809 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14812 default_encode_section_info (decl
, rtl
, first
);
14814 #endif /* !ARM_PE */
14817 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14819 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14820 && !strcmp (prefix
, "L"))
14822 arm_ccfsm_state
= 0;
14823 arm_target_insn
= NULL
;
14825 default_internal_label (stream
, prefix
, labelno
);
14828 /* Output code to add DELTA to the first argument, and then jump
14829 to FUNCTION. Used for C++ multiple inheritance. */
14831 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14832 HOST_WIDE_INT delta
,
14833 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14836 static int thunk_label
= 0;
14839 int mi_delta
= delta
;
14840 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14842 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14845 mi_delta
= - mi_delta
;
14848 int labelno
= thunk_label
++;
14849 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14850 fputs ("\tldr\tr12, ", file
);
14851 assemble_name (file
, label
);
14852 fputc ('\n', file
);
14855 /* If we are generating PIC, the ldr instruction below loads
14856 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
14857 the address of the add + 8, so we have:
14859 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
14862 Note that we have "+ 1" because some versions of GNU ld
14863 don't set the low bit of the result for R_ARM_REL32
14864 relocations against thumb function symbols. */
14865 ASM_GENERATE_INTERNAL_LABEL (labelpc
, "LTHUNKPC", labelno
);
14866 assemble_name (file
, labelpc
);
14867 fputs (":\n", file
);
14868 fputs ("\tadd\tr12, pc, r12\n", file
);
14871 while (mi_delta
!= 0)
14873 if ((mi_delta
& (3 << shift
)) == 0)
14877 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14878 mi_op
, this_regno
, this_regno
,
14879 mi_delta
& (0xff << shift
));
14880 mi_delta
&= ~(0xff << shift
);
14886 fprintf (file
, "\tbx\tr12\n");
14887 ASM_OUTPUT_ALIGN (file
, 2);
14888 assemble_name (file
, label
);
14889 fputs (":\n", file
);
14892 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
14893 rtx tem
= XEXP (DECL_RTL (function
), 0);
14894 tem
= gen_rtx_PLUS (GET_MODE (tem
), tem
, GEN_INT (-7));
14895 tem
= gen_rtx_MINUS (GET_MODE (tem
),
14897 gen_rtx_SYMBOL_REF (Pmode
,
14898 ggc_strdup (labelpc
)));
14899 assemble_integer (tem
, 4, BITS_PER_WORD
, 1);
14902 /* Output ".word .LTHUNKn". */
14903 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14907 fputs ("\tb\t", file
);
14908 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14909 if (NEED_PLT_RELOC
)
14910 fputs ("(PLT)", file
);
14911 fputc ('\n', file
);
14916 arm_emit_vector_const (FILE *file
, rtx x
)
14919 const char * pattern
;
14921 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
14923 switch (GET_MODE (x
))
14925 case V2SImode
: pattern
= "%08x"; break;
14926 case V4HImode
: pattern
= "%04x"; break;
14927 case V8QImode
: pattern
= "%02x"; break;
14928 default: gcc_unreachable ();
14931 fprintf (file
, "0x");
14932 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14936 element
= CONST_VECTOR_ELT (x
, i
);
14937 fprintf (file
, pattern
, INTVAL (element
));
14944 arm_output_load_gr (rtx
*operands
)
14951 if (GET_CODE (operands
[1]) != MEM
14952 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14953 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14954 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14955 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14956 return "wldrw%?\t%0, %1";
14958 /* Fix up an out-of-range load of a GR register. */
14959 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14960 wcgr
= operands
[0];
14962 output_asm_insn ("ldr%?\t%0, %1", operands
);
14964 operands
[0] = wcgr
;
14966 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14967 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14972 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14974 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14975 named arg and all anonymous args onto the stack.
14976 XXX I know the prologue shouldn't be pushing registers, but it is faster
14980 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14981 enum machine_mode mode ATTRIBUTE_UNUSED
,
14982 tree type ATTRIBUTE_UNUSED
,
14984 int second_time ATTRIBUTE_UNUSED
)
14986 cfun
->machine
->uses_anonymous_args
= 1;
14987 if (cum
->nregs
< NUM_ARG_REGS
)
14988 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14991 /* Return nonzero if the CONSUMER instruction (a store) does not need
14992 PRODUCER's value to calculate the address. */
14995 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14997 rtx value
= PATTERN (producer
);
14998 rtx addr
= PATTERN (consumer
);
15000 if (GET_CODE (value
) == COND_EXEC
)
15001 value
= COND_EXEC_CODE (value
);
15002 if (GET_CODE (value
) == PARALLEL
)
15003 value
= XVECEXP (value
, 0, 0);
15004 value
= XEXP (value
, 0);
15005 if (GET_CODE (addr
) == COND_EXEC
)
15006 addr
= COND_EXEC_CODE (addr
);
15007 if (GET_CODE (addr
) == PARALLEL
)
15008 addr
= XVECEXP (addr
, 0, 0);
15009 addr
= XEXP (addr
, 0);
15011 return !reg_overlap_mentioned_p (value
, addr
);
15014 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15015 have an early register shift value or amount dependency on the
15016 result of PRODUCER. */
15019 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
15021 rtx value
= PATTERN (producer
);
15022 rtx op
= PATTERN (consumer
);
15025 if (GET_CODE (value
) == COND_EXEC
)
15026 value
= COND_EXEC_CODE (value
);
15027 if (GET_CODE (value
) == PARALLEL
)
15028 value
= XVECEXP (value
, 0, 0);
15029 value
= XEXP (value
, 0);
15030 if (GET_CODE (op
) == COND_EXEC
)
15031 op
= COND_EXEC_CODE (op
);
15032 if (GET_CODE (op
) == PARALLEL
)
15033 op
= XVECEXP (op
, 0, 0);
15036 early_op
= XEXP (op
, 0);
15037 /* This is either an actual independent shift, or a shift applied to
15038 the first operand of another operation. We want the whole shift
15040 if (GET_CODE (early_op
) == REG
)
15043 return !reg_overlap_mentioned_p (value
, early_op
);
15046 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15047 have an early register shift value dependency on the result of
15051 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
15053 rtx value
= PATTERN (producer
);
15054 rtx op
= PATTERN (consumer
);
15057 if (GET_CODE (value
) == COND_EXEC
)
15058 value
= COND_EXEC_CODE (value
);
15059 if (GET_CODE (value
) == PARALLEL
)
15060 value
= XVECEXP (value
, 0, 0);
15061 value
= XEXP (value
, 0);
15062 if (GET_CODE (op
) == COND_EXEC
)
15063 op
= COND_EXEC_CODE (op
);
15064 if (GET_CODE (op
) == PARALLEL
)
15065 op
= XVECEXP (op
, 0, 0);
15068 early_op
= XEXP (op
, 0);
15070 /* This is either an actual independent shift, or a shift applied to
15071 the first operand of another operation. We want the value being
15072 shifted, in either case. */
15073 if (GET_CODE (early_op
) != REG
)
15074 early_op
= XEXP (early_op
, 0);
15076 return !reg_overlap_mentioned_p (value
, early_op
);
15079 /* Return nonzero if the CONSUMER (a mul or mac op) does not
15080 have an early register mult dependency on the result of
15084 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
15086 rtx value
= PATTERN (producer
);
15087 rtx op
= PATTERN (consumer
);
15089 if (GET_CODE (value
) == COND_EXEC
)
15090 value
= COND_EXEC_CODE (value
);
15091 if (GET_CODE (value
) == PARALLEL
)
15092 value
= XVECEXP (value
, 0, 0);
15093 value
= XEXP (value
, 0);
15094 if (GET_CODE (op
) == COND_EXEC
)
15095 op
= COND_EXEC_CODE (op
);
15096 if (GET_CODE (op
) == PARALLEL
)
15097 op
= XVECEXP (op
, 0, 0);
15100 return (GET_CODE (op
) == PLUS
15101 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
15105 /* We can't rely on the caller doing the proper promotion when
15106 using APCS or ATPCS. */
15109 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
15111 return !TARGET_AAPCS_BASED
;
15115 /* AAPCS based ABIs use short enums by default. */
15118 arm_default_short_enums (void)
15120 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
15124 /* AAPCS requires that anonymous bitfields affect structure alignment. */
15127 arm_align_anon_bitfield (void)
15129 return TARGET_AAPCS_BASED
;
15133 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
15136 arm_cxx_guard_type (void)
15138 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
15142 /* The EABI says test the least significant bit of a guard variable. */
15145 arm_cxx_guard_mask_bit (void)
15147 return TARGET_AAPCS_BASED
;
15151 /* The EABI specifies that all array cookies are 8 bytes long. */
15154 arm_get_cookie_size (tree type
)
15158 if (!TARGET_AAPCS_BASED
)
15159 return default_cxx_get_cookie_size (type
);
15161 size
= build_int_cst (sizetype
, 8);
15166 /* The EABI says that array cookies should also contain the element size. */
15169 arm_cookie_has_size (void)
15171 return TARGET_AAPCS_BASED
;
15175 /* The EABI says constructors and destructors should return a pointer to
15176 the object constructed/destroyed. */
15179 arm_cxx_cdtor_returns_this (void)
15181 return TARGET_AAPCS_BASED
;
15184 /* The EABI says that an inline function may never be the key
15188 arm_cxx_key_method_may_be_inline (void)
15190 return !TARGET_AAPCS_BASED
;
15194 arm_cxx_determine_class_data_visibility (tree decl
)
15196 if (!TARGET_AAPCS_BASED
)
15199 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
15200 is exported. However, on systems without dynamic vague linkage,
15201 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
15202 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
15203 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
15205 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
15206 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
15210 arm_cxx_class_data_always_comdat (void)
15212 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
15213 vague linkage if the class has no key function. */
15214 return !TARGET_AAPCS_BASED
;
15218 /* The EABI says __aeabi_atexit should be used to register static
15222 arm_cxx_use_aeabi_atexit (void)
15224 return TARGET_AAPCS_BASED
;
15229 arm_set_return_address (rtx source
, rtx scratch
)
15231 arm_stack_offsets
*offsets
;
15232 HOST_WIDE_INT delta
;
15234 unsigned long saved_regs
;
15236 saved_regs
= arm_compute_save_reg_mask ();
15238 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
15239 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15242 if (frame_pointer_needed
)
15243 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
15246 /* LR will be the first saved register. */
15247 offsets
= arm_get_frame_offsets ();
15248 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
15253 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
15254 GEN_INT (delta
& ~4095)));
15259 addr
= stack_pointer_rtx
;
15261 addr
= plus_constant (addr
, delta
);
15263 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15269 thumb_set_return_address (rtx source
, rtx scratch
)
15271 arm_stack_offsets
*offsets
;
15272 HOST_WIDE_INT delta
;
15275 unsigned long mask
;
15277 emit_insn (gen_rtx_USE (VOIDmode
, source
));
15279 mask
= thumb_compute_save_reg_mask ();
15280 if (mask
& (1 << LR_REGNUM
))
15282 offsets
= arm_get_frame_offsets ();
15284 /* Find the saved regs. */
15285 if (frame_pointer_needed
)
15287 delta
= offsets
->soft_frame
- offsets
->saved_args
;
15288 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
15292 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
15295 /* Allow for the stack frame. */
15296 if (TARGET_BACKTRACE
)
15298 /* The link register is always the first saved register. */
15301 /* Construct the address. */
15302 addr
= gen_rtx_REG (SImode
, reg
);
15303 if ((reg
!= SP_REGNUM
&& delta
>= 128)
15306 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
15307 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
15311 addr
= plus_constant (addr
, delta
);
15313 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15316 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15319 /* Implements target hook vector_mode_supported_p. */
15321 arm_vector_mode_supported_p (enum machine_mode mode
)
15323 if ((mode
== V2SImode
)
15324 || (mode
== V4HImode
)
15325 || (mode
== V8QImode
))
15331 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
15332 ARM insns and therefore guarantee that the shift count is modulo 256.
15333 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
15334 guarantee no particular behavior for out-of-range counts. */
15336 static unsigned HOST_WIDE_INT
15337 arm_shift_truncation_mask (enum machine_mode mode
)
15339 return mode
== SImode
? 255 : 0;
15343 /* Map internal gcc register numbers to DWARF2 register numbers. */
15346 arm_dbx_register_number (unsigned int regno
)
15351 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
15352 compatibility. The EABI defines them as registers 96-103. */
15353 if (IS_FPA_REGNUM (regno
))
15354 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
15356 if (IS_VFP_REGNUM (regno
))
15357 return 64 + regno
- FIRST_VFP_REGNUM
;
15359 if (IS_IWMMXT_GR_REGNUM (regno
))
15360 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
15362 if (IS_IWMMXT_REGNUM (regno
))
15363 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
15365 gcc_unreachable ();
15369 #ifdef TARGET_UNWIND_INFO
15370 /* Emit unwind directives for a store-multiple instruction. This should
15371 only ever be generated by the function prologue code, so we expect it
15372 to have a particular form. */
15375 arm_unwind_emit_stm (FILE * asm_out_file
, rtx p
)
15378 HOST_WIDE_INT offset
;
15379 HOST_WIDE_INT nregs
;
15385 /* First insn will adjust the stack pointer. */
15386 e
= XVECEXP (p
, 0, 0);
15387 if (GET_CODE (e
) != SET
15388 || GET_CODE (XEXP (e
, 0)) != REG
15389 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15390 || GET_CODE (XEXP (e
, 1)) != PLUS
)
15393 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
15394 nregs
= XVECLEN (p
, 0) - 1;
15396 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
15399 /* The function prologue may also push pc, but not annotate it as it is
15400 never restored. We turn this into a stack pointer adjustment. */
15401 if (nregs
* 4 == offset
- 4)
15403 fprintf (asm_out_file
, "\t.pad #4\n");
15408 else if (IS_VFP_REGNUM (reg
))
15410 /* FPA register saves use an additional word. */
15414 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
15416 /* FPA registers are done differently. */
15417 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
15421 /* Unknown register type. */
15424 /* If the stack increment doesn't match the size of the saved registers,
15425 something has gone horribly wrong. */
15426 if (offset
!= nregs
* reg_size
)
15429 fprintf (asm_out_file
, "\t.save {");
15433 /* The remaining insns will describe the stores. */
15434 for (i
= 1; i
<= nregs
; i
++)
15436 /* Expect (set (mem <addr>) (reg)).
15437 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
15438 e
= XVECEXP (p
, 0, i
);
15439 if (GET_CODE (e
) != SET
15440 || GET_CODE (XEXP (e
, 0)) != MEM
15441 || GET_CODE (XEXP (e
, 1)) != REG
)
15444 reg
= REGNO (XEXP (e
, 1));
15449 fprintf (asm_out_file
, ", ");
15450 /* We can't use %r for vfp because we need to use the
15451 double precision register names. */
15452 if (IS_VFP_REGNUM (reg
))
15453 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
15455 asm_fprintf (asm_out_file
, "%r", reg
);
15457 #ifdef ENABLE_CHECKING
15458 /* Check that the addresses are consecutive. */
15459 e
= XEXP (XEXP (e
, 0), 0);
15460 if (GET_CODE (e
) == PLUS
)
15462 offset
+= reg_size
;
15463 if (GET_CODE (XEXP (e
, 0)) != REG
15464 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15465 || GET_CODE (XEXP (e
, 1)) != CONST_INT
15466 || offset
!= INTVAL (XEXP (e
, 1)))
15470 || GET_CODE (e
) != REG
15471 || REGNO (e
) != SP_REGNUM
)
15475 fprintf (asm_out_file
, "}\n");
15478 /* Emit unwind directives for a SET. */
15481 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
15488 switch (GET_CODE (e0
))
15491 /* Pushing a single register. */
15492 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
15493 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
15494 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
15497 asm_fprintf (asm_out_file
, "\t.save ");
15498 if (IS_VFP_REGNUM (REGNO (e1
)))
15499 asm_fprintf(asm_out_file
, "{d%d}\n",
15500 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
15502 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
15506 if (REGNO (e0
) == SP_REGNUM
)
15508 /* A stack increment. */
15509 if (GET_CODE (e1
) != PLUS
15510 || GET_CODE (XEXP (e1
, 0)) != REG
15511 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
15512 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15515 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
15516 -INTVAL (XEXP (e1
, 1)));
15518 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
15520 HOST_WIDE_INT offset
;
15523 if (GET_CODE (e1
) == PLUS
)
15525 if (GET_CODE (XEXP (e1
, 0)) != REG
15526 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15528 reg
= REGNO (XEXP (e1
, 0));
15529 offset
= INTVAL (XEXP (e1
, 1));
15530 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
15531 HARD_FRAME_POINTER_REGNUM
, reg
,
15532 INTVAL (XEXP (e1
, 1)));
15534 else if (GET_CODE (e1
) == REG
)
15537 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
15538 HARD_FRAME_POINTER_REGNUM
, reg
);
15543 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
15545 /* Move from sp to reg. */
15546 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
15548 else if (GET_CODE (e1
) == PLUS
15549 && GET_CODE (XEXP (e1
, 0)) == REG
15550 && REGNO (XEXP (e1
, 0)) == SP_REGNUM
15551 && GET_CODE (XEXP (e1
, 1)) == CONST_INT
)
15553 /* Set reg to offset from sp. */
15554 asm_fprintf (asm_out_file
, "\t.movsp %r, #%d\n",
15555 REGNO (e0
), (int)INTVAL(XEXP (e1
, 1)));
15567 /* Emit unwind directives for the given insn. */
15570 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
15574 if (!ARM_EABI_UNWIND_TABLES
)
15577 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
15580 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
15582 pat
= XEXP (pat
, 0);
15584 pat
= PATTERN (insn
);
15586 switch (GET_CODE (pat
))
15589 arm_unwind_emit_set (asm_out_file
, pat
);
15593 /* Store multiple. */
15594 arm_unwind_emit_stm (asm_out_file
, pat
);
15603 /* Output a reference from a function exception table to the type_info
15604 object X. The EABI specifies that the symbol should be relocated by
15605 an R_ARM_TARGET2 relocation. */
15608 arm_output_ttype (rtx x
)
15610 fputs ("\t.word\t", asm_out_file
);
15611 output_addr_const (asm_out_file
, x
);
15612 /* Use special relocations for symbol references. */
15613 if (GET_CODE (x
) != CONST_INT
)
15614 fputs ("(TARGET2)", asm_out_file
);
15615 fputc ('\n', asm_out_file
);
15619 #endif /* TARGET_UNWIND_INFO */
15622 /* Output unwind directives for the start/end of a function. */
15625 arm_output_fn_unwind (FILE * f
, bool prologue
)
15627 if (!ARM_EABI_UNWIND_TABLES
)
15631 fputs ("\t.fnstart\n", f
);
15633 fputs ("\t.fnend\n", f
);
15637 arm_emit_tls_decoration (FILE *fp
, rtx x
)
15639 enum tls_reloc reloc
;
15642 val
= XVECEXP (x
, 0, 0);
15643 reloc
= INTVAL (XVECEXP (x
, 0, 1));
15645 output_addr_const (fp
, val
);
15650 fputs ("(tlsgd)", fp
);
15653 fputs ("(tlsldm)", fp
);
15656 fputs ("(tlsldo)", fp
);
15659 fputs ("(gottpoff)", fp
);
15662 fputs ("(tpoff)", fp
);
15665 gcc_unreachable ();
15673 fputs (" + (. - ", fp
);
15674 output_addr_const (fp
, XVECEXP (x
, 0, 2));
15676 output_addr_const (fp
, XVECEXP (x
, 0, 3));
15687 arm_output_addr_const_extra (FILE *fp
, rtx x
)
15689 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
15690 return arm_emit_tls_decoration (fp
, x
);
15691 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
15694 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
15696 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
15697 assemble_name_raw (fp
, label
);
15701 else if (GET_CODE (x
) == CONST_VECTOR
)
15702 return arm_emit_vector_const (fp
, x
);
15707 #include "gt-arm.h"