1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Recalculating spilled pseudo values (rematerialization);
41 o Changing spilled pseudos to stack memory or their equivalences;
42 o Allocation stack memory changes the address displacement and
43 new iteration is needed.
45 Here is block diagram of LRA passes:
47 ------------------------
48 --------------- | Undo inheritance for | ---------------
49 | Memory-memory | | spilled pseudos, | | New (and old) |
50 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
51 --------------- | the same hard regs, | | assignment |
52 Start | | and optional reloads | ---------------
53 | | ------------------------ ^
54 V | ---------------- |
55 ----------- V | Update virtual | |
56 | Remove |----> ------------>| register | |
57 | scratches | ^ | displacements | |
58 ----------- | ---------------- |
61 | ------------ pseudos -------------------
62 | |Constraints:| or insns | Inheritance/split |
63 | | RTL |--------->| transformations |
64 | | transfor- | | in EBB scope |
65 | substi- | mations | -------------------
66 | tutions ------------
69 | Spilled pseudo | -------------------
70 | to memory |<----| Rematerialization |
71 | substitution | -------------------
75 -------------------------
76 | Hard regs substitution, |
77 | devirtalization, and |------> Finish
78 | restoring scratches got |
80 -------------------------
82 To speed up the process:
83 o We process only insns affected by changes on previous
85 o We don't use DFA-infrastructure because it results in much slower
86 compiler speed than a special IR described below does;
87 o We use a special insn representation for quick access to insn
88 info which is always *synchronized* with the current RTL;
89 o Insn IR is minimized by memory. It is divided on three parts:
90 o one specific for each insn in RTL (only operand locations);
91 o one common for all insns in RTL with the same insn code
92 (different operand attributes from machine descriptions);
93 o one oriented for maintenance of live info (list of pseudos).
95 o all insns where the pseudo is referenced;
96 o live info (conflicting hard regs, live ranges, # of
98 o data used for assigning (preferred hard regs, costs etc).
100 This file contains LRA driver, LRA utility functions and data, and
101 code for dealing with scratches. */
105 #include "coretypes.h"
107 #include "hard-reg-set.h"
111 #include "insn-config.h"
112 #include "insn-codes.h"
115 #include "addresses.h"
118 #include "hash-set.h"
120 #include "machmode.h"
122 #include "function.h"
124 #include "wide-int.h"
130 #include "dominance.h"
133 #include "cfgbuild.h"
134 #include "basic-block.h"
136 #include "tree-pass.h"
143 /* Dump bitmap SET with TITLE and BB INDEX. */
145 lra_dump_bitmap_with_title (const char *title
, bitmap set
, int index
)
150 static const int max_nums_on_line
= 10;
152 if (bitmap_empty_p (set
))
154 fprintf (lra_dump_file
, " %s %d:", title
, index
);
155 fprintf (lra_dump_file
, "\n");
156 count
= max_nums_on_line
+ 1;
157 EXECUTE_IF_SET_IN_BITMAP (set
, 0, i
, bi
)
159 if (count
> max_nums_on_line
)
161 fprintf (lra_dump_file
, "\n ");
164 fprintf (lra_dump_file
, " %4u", i
);
167 fprintf (lra_dump_file
, "\n");
170 /* Hard registers currently not available for allocation. It can
171 changed after some hard registers become not eliminable. */
172 HARD_REG_SET lra_no_alloc_regs
;
174 static int get_new_reg_value (void);
175 static void expand_reg_info (void);
176 static void invalidate_insn_recog_data (int);
177 static int get_insn_freq (rtx_insn
*);
178 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t
,
181 /* Expand all regno related info needed for LRA. */
183 expand_reg_data (int old
)
187 ira_expand_reg_equiv ();
188 for (int i
= (int) max_reg_num () - 1; i
>= old
; i
--)
189 lra_change_class (i
, ALL_REGS
, " Set", true);
192 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
193 or of VOIDmode, use MD_MODE for the new reg. Initialize its
194 register class to RCLASS. Print message about assigning class
195 RCLASS containing new register name TITLE unless it is NULL. Use
196 attributes of ORIGINAL if it is a register. The created register
197 will have unique held value. */
199 lra_create_new_reg_with_unique_value (machine_mode md_mode
, rtx original
,
200 enum reg_class rclass
, const char *title
)
205 if (original
== NULL_RTX
|| (mode
= GET_MODE (original
)) == VOIDmode
)
207 lra_assert (mode
!= VOIDmode
);
208 new_reg
= gen_reg_rtx (mode
);
209 if (original
== NULL_RTX
|| ! REG_P (original
))
211 if (lra_dump_file
!= NULL
)
212 fprintf (lra_dump_file
, " Creating newreg=%i", REGNO (new_reg
));
216 if (ORIGINAL_REGNO (original
) >= FIRST_PSEUDO_REGISTER
)
217 ORIGINAL_REGNO (new_reg
) = ORIGINAL_REGNO (original
);
218 REG_USERVAR_P (new_reg
) = REG_USERVAR_P (original
);
219 REG_POINTER (new_reg
) = REG_POINTER (original
);
220 REG_ATTRS (new_reg
) = REG_ATTRS (original
);
221 if (lra_dump_file
!= NULL
)
222 fprintf (lra_dump_file
, " Creating newreg=%i from oldreg=%i",
223 REGNO (new_reg
), REGNO (original
));
225 if (lra_dump_file
!= NULL
)
228 fprintf (lra_dump_file
, ", assigning class %s to%s%s r%d",
229 reg_class_names
[rclass
], *title
== '\0' ? "" : " ",
230 title
, REGNO (new_reg
));
231 fprintf (lra_dump_file
, "\n");
233 expand_reg_data (max_reg_num ());
234 setup_reg_classes (REGNO (new_reg
), rclass
, NO_REGS
, rclass
);
238 /* Analogous to the previous function but also inherits value of
241 lra_create_new_reg (machine_mode md_mode
, rtx original
,
242 enum reg_class rclass
, const char *title
)
247 = lra_create_new_reg_with_unique_value (md_mode
, original
, rclass
, title
);
248 if (original
!= NULL_RTX
&& REG_P (original
))
249 lra_assign_reg_val (REGNO (original
), REGNO (new_reg
));
253 /* Set up for REGNO unique hold value. */
255 lra_set_regno_unique_value (int regno
)
257 lra_reg_info
[regno
].val
= get_new_reg_value ();
260 /* Invalidate INSN related info used by LRA. The info should never be
263 lra_invalidate_insn_data (rtx_insn
*insn
)
265 lra_invalidate_insn_regno_info (insn
);
266 invalidate_insn_recog_data (INSN_UID (insn
));
269 /* Mark INSN deleted and invalidate the insn related info used by
272 lra_set_insn_deleted (rtx_insn
*insn
)
274 lra_invalidate_insn_data (insn
);
275 SET_INSN_DELETED (insn
);
278 /* Delete an unneeded INSN and any previous insns who sole purpose is
279 loading data that is dead in INSN. */
281 lra_delete_dead_insn (rtx_insn
*insn
)
283 rtx_insn
*prev
= prev_real_insn (insn
);
286 /* If the previous insn sets a register that dies in our insn,
288 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
289 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
290 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
291 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
292 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
293 lra_delete_dead_insn (prev
);
295 lra_set_insn_deleted (insn
);
298 /* Emit insn x = y + z. Return NULL if we failed to do it.
299 Otherwise, return the insn. We don't use gen_add3_insn as it might
302 emit_add3_insn (rtx x
, rtx y
, rtx z
)
306 last
= get_last_insn ();
308 if (have_addptr3_insn (x
, y
, z
))
310 rtx insn
= gen_addptr3_insn (x
, y
, z
);
312 /* If the target provides an "addptr" pattern it hopefully does
313 for a reason. So falling back to the normal add would be
315 lra_assert (insn
!= NULL_RTX
);
320 rtx_insn
*insn
= emit_insn (gen_rtx_SET (VOIDmode
, x
,
321 gen_rtx_PLUS (GET_MODE (y
), y
, z
)));
322 if (recog_memoized (insn
) < 0)
324 delete_insns_since (last
);
330 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
333 emit_add2_insn (rtx x
, rtx y
)
337 insn
= emit_add3_insn (x
, x
, y
);
338 if (insn
== NULL_RTX
)
340 insn
= gen_add2_insn (x
, y
);
341 if (insn
!= NULL_RTX
)
347 /* Target checks operands through operand predicates to recognize an
348 insn. We should have a special precaution to generate add insns
349 which are frequent results of elimination.
351 Emit insns for x = y + z. X can be used to store intermediate
352 values and should be not in Y and Z when we use X to store an
353 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
354 + disp] where base and index are registers, disp and scale are
355 constants. Y should contain base if it is present, Z should
356 contain disp if any. index[*scale] can be part of Y or Z. */
358 lra_emit_add (rtx x
, rtx y
, rtx z
)
362 rtx a1
, a2
, base
, index
, disp
, scale
, index_scale
;
365 rtx add3_insn
= emit_add3_insn (x
, y
, z
);
366 old
= max_reg_num ();
367 if (add3_insn
!= NULL
)
371 disp
= a2
= NULL_RTX
;
372 if (GET_CODE (y
) == PLUS
)
386 index_scale
= scale
= NULL_RTX
;
387 if (GET_CODE (a1
) == MULT
)
390 index
= XEXP (a1
, 0);
391 scale
= XEXP (a1
, 1);
394 else if (a2
!= NULL_RTX
&& GET_CODE (a2
) == MULT
)
397 index
= XEXP (a2
, 0);
398 scale
= XEXP (a2
, 1);
406 if (! (REG_P (base
) || GET_CODE (base
) == SUBREG
)
407 || (index
!= NULL_RTX
408 && ! (REG_P (index
) || GET_CODE (index
) == SUBREG
))
409 || (disp
!= NULL_RTX
&& ! CONSTANT_P (disp
))
410 || (scale
!= NULL_RTX
&& ! CONSTANT_P (scale
)))
412 /* Probably we have no 3 op add. Last chance is to use 2-op
413 add insn. To succeed, don't move Z to X as an address
414 segment always comes in Y. Otherwise, we might fail when
415 adding the address segment to register. */
416 lra_assert (x
!= y
&& x
!= z
);
417 emit_move_insn (x
, y
);
418 rtx insn
= emit_add2_insn (x
, z
);
419 lra_assert (insn
!= NULL_RTX
);
423 if (index_scale
== NULL_RTX
)
425 if (disp
== NULL_RTX
)
427 /* Generate x = index_scale; x = x + base. */
428 lra_assert (index_scale
!= NULL_RTX
&& base
!= NULL_RTX
);
429 emit_move_insn (x
, index_scale
);
430 rtx insn
= emit_add2_insn (x
, base
);
431 lra_assert (insn
!= NULL_RTX
);
433 else if (scale
== NULL_RTX
)
435 /* Try x = base + disp. */
436 lra_assert (base
!= NULL_RTX
);
437 last
= get_last_insn ();
438 rtx_insn
*move_insn
=
439 emit_move_insn (x
, gen_rtx_PLUS (GET_MODE (base
), base
, disp
));
440 if (recog_memoized (move_insn
) < 0)
442 delete_insns_since (last
);
443 /* Generate x = disp; x = x + base. */
444 emit_move_insn (x
, disp
);
445 rtx add2_insn
= emit_add2_insn (x
, base
);
446 lra_assert (add2_insn
!= NULL_RTX
);
448 /* Generate x = x + index. */
449 if (index
!= NULL_RTX
)
451 rtx insn
= emit_add2_insn (x
, index
);
452 lra_assert (insn
!= NULL_RTX
);
457 /* Try x = index_scale; x = x + disp; x = x + base. */
458 last
= get_last_insn ();
459 rtx_insn
*move_insn
= emit_move_insn (x
, index_scale
);
461 if (recog_memoized (move_insn
) >= 0)
463 rtx insn
= emit_add2_insn (x
, disp
);
464 if (insn
!= NULL_RTX
)
466 insn
= emit_add2_insn (x
, disp
);
467 if (insn
!= NULL_RTX
)
473 delete_insns_since (last
);
474 /* Generate x = disp; x = x + base; x = x + index_scale. */
475 emit_move_insn (x
, disp
);
476 rtx insn
= emit_add2_insn (x
, base
);
477 lra_assert (insn
!= NULL_RTX
);
478 insn
= emit_add2_insn (x
, index_scale
);
479 lra_assert (insn
!= NULL_RTX
);
484 /* Functions emit_... can create pseudos -- so expand the pseudo
486 if (old
!= max_reg_num ())
487 expand_reg_data (old
);
490 /* The number of emitted reload insns so far. */
491 int lra_curr_reload_num
;
493 /* Emit x := y, processing special case when y = u + v or y = u + v *
494 scale + w through emit_add (Y can be an address which is base +
495 index reg * scale + displacement in general case). X may be used
496 as intermediate result therefore it should be not in Y. */
498 lra_emit_move (rtx x
, rtx y
)
502 if (GET_CODE (y
) != PLUS
)
504 if (rtx_equal_p (x
, y
))
506 old
= max_reg_num ();
507 emit_move_insn (x
, y
);
509 lra_reg_info
[ORIGINAL_REGNO (x
)].last_reload
= ++lra_curr_reload_num
;
510 /* Function emit_move can create pseudos -- so expand the pseudo
512 if (old
!= max_reg_num ())
513 expand_reg_data (old
);
516 lra_emit_add (x
, XEXP (y
, 0), XEXP (y
, 1));
519 /* Update insn operands which are duplication of operands whose
520 numbers are in array of NOPS (with end marker -1). The insn is
521 represented by its LRA internal representation ID. */
523 lra_update_dups (lra_insn_recog_data_t id
, signed char *nops
)
526 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
528 for (i
= 0; i
< static_id
->n_dups
; i
++)
529 for (j
= 0; (nop
= nops
[j
]) >= 0; j
++)
530 if (static_id
->dup_num
[i
] == nop
)
531 *id
->dup_loc
[i
] = *id
->operand_loc
[nop
];
536 /* This page contains code dealing with info about registers in the
539 /* Pools for insn reg info. */
540 static alloc_pool insn_reg_pool
;
542 /* Initiate pool for insn reg info. */
544 init_insn_regs (void)
547 = create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg
), 100);
550 /* Create LRA insn related info about a reference to REGNO in INSN with
551 TYPE (in/out/inout), biggest reference mode MODE, flag that it is
552 reference through subreg (SUBREG_P), flag that is early clobbered
553 in the insn (EARLY_CLOBBER), and reference to the next insn reg
555 static struct lra_insn_reg
*
556 new_insn_reg (rtx_insn
*insn
, int regno
, enum op_type type
,
558 bool subreg_p
, bool early_clobber
, struct lra_insn_reg
*next
)
560 struct lra_insn_reg
*ir
;
562 ir
= (struct lra_insn_reg
*) pool_alloc (insn_reg_pool
);
564 ir
->biggest_mode
= mode
;
565 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (lra_reg_info
[regno
].biggest_mode
)
566 && NONDEBUG_INSN_P (insn
))
567 lra_reg_info
[regno
].biggest_mode
= mode
;
568 ir
->subreg_p
= subreg_p
;
569 ir
->early_clobber
= early_clobber
;
575 /* Free insn reg info IR. */
577 free_insn_reg (struct lra_insn_reg
*ir
)
579 pool_free (insn_reg_pool
, ir
);
582 /* Free insn reg info list IR. */
584 free_insn_regs (struct lra_insn_reg
*ir
)
586 struct lra_insn_reg
*next_ir
;
588 for (; ir
!= NULL
; ir
= next_ir
)
595 /* Finish pool for insn reg info. */
597 finish_insn_regs (void)
599 free_alloc_pool (insn_reg_pool
);
604 /* This page contains code dealing LRA insn info (or in other words
605 LRA internal insn representation). */
607 /* Map INSN_CODE -> the static insn data. This info is valid during
608 all translation unit. */
609 struct lra_static_insn_data
*insn_code_data
[LAST_INSN_CODE
];
611 /* Debug insns are represented as a special insn with one input
612 operand which is RTL expression in var_location. */
614 /* The following data are used as static insn operand data for all
615 debug insns. If structure lra_operand_data is changed, the
616 initializer should be changed too. */
617 static struct lra_operand_data debug_operand_data
=
619 NULL
, /* alternative */
620 VOIDmode
, /* We are not interesting in the operand mode. */
625 /* The following data are used as static insn data for all debug
626 insns. If structure lra_static_insn_data is changed, the
627 initializer should be changed too. */
628 static struct lra_static_insn_data debug_insn_static_data
=
631 0, /* Duplication operands #. */
632 -1, /* Commutative operand #. */
633 1, /* Operands #. There is only one operand which is debug RTL
635 0, /* Duplications #. */
636 0, /* Alternatives #. We are not interesting in alternatives
637 because we does not proceed debug_insns for reloads. */
638 NULL
, /* Hard registers referenced in machine description. */
639 NULL
/* Descriptions of operands in alternatives. */
642 /* Called once per compiler work to initialize some LRA data related
645 init_insn_code_data_once (void)
647 memset (insn_code_data
, 0, sizeof (insn_code_data
));
650 /* Called once per compiler work to finalize some LRA data related to
653 finish_insn_code_data_once (void)
657 for (i
= 0; i
< LAST_INSN_CODE
; i
++)
659 if (insn_code_data
[i
] != NULL
)
660 free (insn_code_data
[i
]);
664 /* Return static insn data, allocate and setup if necessary. Although
665 dup_num is static data (it depends only on icode), to set it up we
666 need to extract insn first. So recog_data should be valid for
667 normal insn (ICODE >= 0) before the call. */
668 static struct lra_static_insn_data
*
669 get_static_insn_data (int icode
, int nop
, int ndup
, int nalt
)
671 struct lra_static_insn_data
*data
;
674 lra_assert (icode
< LAST_INSN_CODE
);
675 if (icode
>= 0 && (data
= insn_code_data
[icode
]) != NULL
)
677 lra_assert (nop
>= 0 && ndup
>= 0 && nalt
>= 0);
678 n_bytes
= sizeof (struct lra_static_insn_data
)
679 + sizeof (struct lra_operand_data
) * nop
680 + sizeof (int) * ndup
;
681 data
= XNEWVAR (struct lra_static_insn_data
, n_bytes
);
682 data
->operand_alternative
= NULL
;
683 data
->n_operands
= nop
;
685 data
->n_alternatives
= nalt
;
686 data
->operand
= ((struct lra_operand_data
*)
687 ((char *) data
+ sizeof (struct lra_static_insn_data
)));
688 data
->dup_num
= ((int *) ((char *) data
->operand
689 + sizeof (struct lra_operand_data
) * nop
));
694 insn_code_data
[icode
] = data
;
695 for (i
= 0; i
< nop
; i
++)
697 data
->operand
[i
].constraint
698 = insn_data
[icode
].operand
[i
].constraint
;
699 data
->operand
[i
].mode
= insn_data
[icode
].operand
[i
].mode
;
700 data
->operand
[i
].strict_low
= insn_data
[icode
].operand
[i
].strict_low
;
701 data
->operand
[i
].is_operator
702 = insn_data
[icode
].operand
[i
].is_operator
;
703 data
->operand
[i
].type
704 = (data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
705 : data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
707 data
->operand
[i
].is_address
= false;
709 for (i
= 0; i
< ndup
; i
++)
710 data
->dup_num
[i
] = recog_data
.dup_num
[i
];
715 /* The current length of the following array. */
716 int lra_insn_recog_data_len
;
718 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
719 lra_insn_recog_data_t
*lra_insn_recog_data
;
721 /* Initialize LRA data about insns. */
723 init_insn_recog_data (void)
725 lra_insn_recog_data_len
= 0;
726 lra_insn_recog_data
= NULL
;
730 /* Expand, if necessary, LRA data about insns. */
732 check_and_expand_insn_recog_data (int index
)
736 if (lra_insn_recog_data_len
> index
)
738 old
= lra_insn_recog_data_len
;
739 lra_insn_recog_data_len
= index
* 3 / 2 + 1;
740 lra_insn_recog_data
= XRESIZEVEC (lra_insn_recog_data_t
,
742 lra_insn_recog_data_len
);
743 for (i
= old
; i
< lra_insn_recog_data_len
; i
++)
744 lra_insn_recog_data
[i
] = NULL
;
747 /* Finish LRA DATA about insn. */
749 free_insn_recog_data (lra_insn_recog_data_t data
)
751 if (data
->operand_loc
!= NULL
)
752 free (data
->operand_loc
);
753 if (data
->dup_loc
!= NULL
)
754 free (data
->dup_loc
);
755 if (data
->arg_hard_regs
!= NULL
)
756 free (data
->arg_hard_regs
);
757 if (data
->icode
< 0 && NONDEBUG_INSN_P (data
->insn
))
759 if (data
->insn_static_data
->operand_alternative
!= NULL
)
760 free (const_cast <operand_alternative
*>
761 (data
->insn_static_data
->operand_alternative
));
762 free_insn_regs (data
->insn_static_data
->hard_regs
);
763 free (data
->insn_static_data
);
765 free_insn_regs (data
->regs
);
770 /* Finish LRA data about all insns. */
772 finish_insn_recog_data (void)
775 lra_insn_recog_data_t data
;
777 for (i
= 0; i
< lra_insn_recog_data_len
; i
++)
778 if ((data
= lra_insn_recog_data
[i
]) != NULL
)
779 free_insn_recog_data (data
);
781 free (lra_insn_recog_data
);
784 /* Setup info about operands in alternatives of LRA DATA of insn. */
786 setup_operand_alternative (lra_insn_recog_data_t data
,
787 const operand_alternative
*op_alt
)
790 int icode
= data
->icode
;
791 struct lra_static_insn_data
*static_data
= data
->insn_static_data
;
793 static_data
->commutative
= -1;
794 nop
= static_data
->n_operands
;
795 nalt
= static_data
->n_alternatives
;
796 static_data
->operand_alternative
= op_alt
;
797 for (i
= 0; i
< nop
; i
++)
799 static_data
->operand
[i
].early_clobber
= false;
800 static_data
->operand
[i
].is_address
= false;
801 if (static_data
->operand
[i
].constraint
[0] == '%')
803 /* We currently only support one commutative pair of operands. */
804 if (static_data
->commutative
< 0)
805 static_data
->commutative
= i
;
807 lra_assert (icode
< 0); /* Asm */
808 /* The last operand should not be marked commutative. */
809 lra_assert (i
!= nop
- 1);
812 for (j
= 0; j
< nalt
; j
++)
813 for (i
= 0; i
< nop
; i
++, op_alt
++)
815 static_data
->operand
[i
].early_clobber
|= op_alt
->earlyclobber
;
816 static_data
->operand
[i
].is_address
|= op_alt
->is_address
;
820 /* Recursively process X and collect info about registers, which are
821 not the insn operands, in X with TYPE (in/out/inout) and flag that
822 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
823 to LIST. X is a part of insn given by DATA. Return the result
825 static struct lra_insn_reg
*
826 collect_non_operand_hard_regs (rtx
*x
, lra_insn_recog_data_t data
,
827 struct lra_insn_reg
*list
,
828 enum op_type type
, bool early_clobber
)
830 int i
, j
, regno
, last
;
833 struct lra_insn_reg
*curr
;
835 enum rtx_code code
= GET_CODE (op
);
836 const char *fmt
= GET_RTX_FORMAT (code
);
838 for (i
= 0; i
< data
->insn_static_data
->n_operands
; i
++)
839 if (x
== data
->operand_loc
[i
])
840 /* It is an operand loc. Stop here. */
842 for (i
= 0; i
< data
->insn_static_data
->n_dups
; i
++)
843 if (x
== data
->dup_loc
[i
])
844 /* It is a dup loc. Stop here. */
846 mode
= GET_MODE (op
);
850 op
= SUBREG_REG (op
);
851 code
= GET_CODE (op
);
852 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (op
)))
854 mode
= GET_MODE (op
);
855 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
861 if ((regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
)
863 /* Process all regs even unallocatable ones as we need info
864 about all regs for rematerialization pass. */
865 for (last
= regno
+ hard_regno_nregs
[regno
][mode
];
869 for (curr
= list
; curr
!= NULL
; curr
= curr
->next
)
870 if (curr
->regno
== regno
&& curr
->subreg_p
== subreg_p
871 && curr
->biggest_mode
== mode
)
873 if (curr
->type
!= type
)
874 curr
->type
= OP_INOUT
;
875 if (curr
->early_clobber
!= early_clobber
)
876 curr
->early_clobber
= true;
881 /* This is a new hard regno or the info can not be
882 integrated into the found structure. */
886 /* This clobber is to inform popping floating
888 && ! (FIRST_STACK_REG
<= regno
889 && regno
<= LAST_STACK_REG
));
891 list
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
892 early_clobber
, list
);
900 list
= collect_non_operand_hard_regs (&SET_DEST (op
), data
,
901 list
, OP_OUT
, false);
902 list
= collect_non_operand_hard_regs (&SET_SRC (op
), data
,
906 /* We treat clobber of non-operand hard registers as early
907 clobber (the behavior is expected from asm). */
908 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
911 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
912 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
913 list
, OP_INOUT
, false);
915 case PRE_MODIFY
: case POST_MODIFY
:
916 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
917 list
, OP_INOUT
, false);
918 list
= collect_non_operand_hard_regs (&XEXP (op
, 1), data
,
922 fmt
= GET_RTX_FORMAT (code
);
923 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
926 list
= collect_non_operand_hard_regs (&XEXP (op
, i
), data
,
928 else if (fmt
[i
] == 'E')
929 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
930 list
= collect_non_operand_hard_regs (&XVECEXP (op
, i
, j
), data
,
937 /* Set up and return info about INSN. Set up the info if it is not set up
939 lra_insn_recog_data_t
940 lra_set_insn_recog_data (rtx_insn
*insn
)
942 lra_insn_recog_data_t data
;
945 unsigned int uid
= INSN_UID (insn
);
946 struct lra_static_insn_data
*insn_static_data
;
948 check_and_expand_insn_recog_data (uid
);
949 if (DEBUG_INSN_P (insn
))
953 icode
= INSN_CODE (insn
);
955 /* It might be a new simple insn which is not recognized yet. */
956 INSN_CODE (insn
) = icode
= recog_memoized (insn
);
958 data
= XNEW (struct lra_insn_recog_data
);
959 lra_insn_recog_data
[uid
] = data
;
961 data
->used_insn_alternative
= -1;
964 if (DEBUG_INSN_P (insn
))
966 data
->insn_static_data
= &debug_insn_static_data
;
967 data
->dup_loc
= NULL
;
968 data
->arg_hard_regs
= NULL
;
969 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
970 data
->operand_loc
= XNEWVEC (rtx
*, 1);
971 data
->operand_loc
[0] = &INSN_VAR_LOCATION_LOC (insn
);
977 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
978 const char *constraints
[MAX_RECOG_OPERANDS
];
980 nop
= asm_noperands (PATTERN (insn
));
981 data
->operand_loc
= data
->dup_loc
= NULL
;
985 /* It is a special insn like USE or CLOBBER. We should
986 recognize any regular insn otherwise LRA can do nothing
988 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
989 || GET_CODE (PATTERN (insn
)) == CLOBBER
990 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
991 data
->insn_static_data
= insn_static_data
992 = get_static_insn_data (-1, 0, 0, nalt
);
996 /* expand_asm_operands makes sure there aren't too many
998 lra_assert (nop
<= MAX_RECOG_OPERANDS
);
1000 data
->operand_loc
= XNEWVEC (rtx
*, nop
);
1001 /* Now get the operand values and constraints out of the
1003 decode_asm_operands (PATTERN (insn
), NULL
,
1005 constraints
, operand_mode
, NULL
);
1008 const char *p
= recog_data
.constraints
[0];
1010 for (p
= constraints
[0]; *p
; p
++)
1013 data
->insn_static_data
= insn_static_data
1014 = get_static_insn_data (-1, nop
, 0, nalt
);
1015 for (i
= 0; i
< nop
; i
++)
1017 insn_static_data
->operand
[i
].mode
= operand_mode
[i
];
1018 insn_static_data
->operand
[i
].constraint
= constraints
[i
];
1019 insn_static_data
->operand
[i
].strict_low
= false;
1020 insn_static_data
->operand
[i
].is_operator
= false;
1021 insn_static_data
->operand
[i
].is_address
= false;
1024 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1025 insn_static_data
->operand
[i
].type
1026 = (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1027 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1029 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
1032 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
,
1034 preprocess_constraints (nop
, nalt
, constraints
, op_alt
);
1035 setup_operand_alternative (data
, op_alt
);
1040 insn_extract (insn
);
1041 data
->insn_static_data
= insn_static_data
1042 = get_static_insn_data (icode
, insn_data
[icode
].n_operands
,
1043 insn_data
[icode
].n_dups
,
1044 insn_data
[icode
].n_alternatives
);
1045 n
= insn_static_data
->n_operands
;
1050 locs
= XNEWVEC (rtx
*, n
);
1051 memcpy (locs
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1053 data
->operand_loc
= locs
;
1054 n
= insn_static_data
->n_dups
;
1059 locs
= XNEWVEC (rtx
*, n
);
1060 memcpy (locs
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1062 data
->dup_loc
= locs
;
1063 data
->preferred_alternatives
= get_preferred_alternatives (insn
);
1064 const operand_alternative
*op_alt
= preprocess_insn_constraints (icode
);
1065 if (!insn_static_data
->operand_alternative
)
1066 setup_operand_alternative (data
, op_alt
);
1067 else if (op_alt
!= insn_static_data
->operand_alternative
)
1068 insn_static_data
->operand_alternative
= op_alt
;
1070 if (GET_CODE (PATTERN (insn
)) == CLOBBER
|| GET_CODE (PATTERN (insn
)) == USE
)
1071 insn_static_data
->hard_regs
= NULL
;
1073 insn_static_data
->hard_regs
1074 = collect_non_operand_hard_regs (&PATTERN (insn
), data
,
1075 NULL
, OP_IN
, false);
1076 data
->arg_hard_regs
= NULL
;
1080 int n_hard_regs
, regno
, arg_hard_regs
[FIRST_PSEUDO_REGISTER
];
1083 /* Finding implicit hard register usage. We believe it will be
1084 not changed whatever transformations are used. Call insns
1085 are such example. */
1086 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1088 link
= XEXP (link
, 1))
1089 if (GET_CODE (XEXP (link
, 0)) == USE
1090 && REG_P (XEXP (XEXP (link
, 0), 0)))
1092 regno
= REGNO (XEXP (XEXP (link
, 0), 0));
1093 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
1094 /* It is an argument register. */
1095 for (i
= (hard_regno_nregs
1096 [regno
][GET_MODE (XEXP (XEXP (link
, 0), 0))]) - 1;
1099 arg_hard_regs
[n_hard_regs
++] = regno
+ i
;
1101 if (n_hard_regs
!= 0)
1103 arg_hard_regs
[n_hard_regs
++] = -1;
1104 data
->arg_hard_regs
= XNEWVEC (int, n_hard_regs
);
1105 memcpy (data
->arg_hard_regs
, arg_hard_regs
,
1106 sizeof (int) * n_hard_regs
);
1109 /* Some output operand can be recognized only from the context not
1110 from the constraints which are empty in this case. Call insn may
1111 contain a hard register in set destination with empty constraint
1112 and extract_insn treats them as an input. */
1113 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1117 struct lra_operand_data
*operand
= &insn_static_data
->operand
[i
];
1119 /* ??? Should we treat 'X' the same way. It looks to me that
1120 'X' means anything and empty constraint means we do not
1122 if (operand
->type
!= OP_IN
|| *operand
->constraint
!= '\0'
1123 || operand
->is_operator
)
1125 pat
= PATTERN (insn
);
1126 if (GET_CODE (pat
) == SET
)
1128 if (data
->operand_loc
[i
] != &SET_DEST (pat
))
1131 else if (GET_CODE (pat
) == PARALLEL
)
1133 for (j
= XVECLEN (pat
, 0) - 1; j
>= 0; j
--)
1135 set
= XVECEXP (PATTERN (insn
), 0, j
);
1136 if (GET_CODE (set
) == SET
1137 && &SET_DEST (set
) == data
->operand_loc
[i
])
1145 operand
->type
= OP_OUT
;
1150 /* Return info about insn give by UID. The info should be already set
1152 static lra_insn_recog_data_t
1153 get_insn_recog_data_by_uid (int uid
)
1155 lra_insn_recog_data_t data
;
1157 data
= lra_insn_recog_data
[uid
];
1158 lra_assert (data
!= NULL
);
1162 /* Invalidate all info about insn given by its UID. */
1164 invalidate_insn_recog_data (int uid
)
1166 lra_insn_recog_data_t data
;
1168 data
= lra_insn_recog_data
[uid
];
1169 lra_assert (data
!= NULL
);
1170 free_insn_recog_data (data
);
1171 lra_insn_recog_data
[uid
] = NULL
;
1174 /* Update all the insn info about INSN. It is usually called when
1175 something in the insn was changed. Return the updated info. */
1176 lra_insn_recog_data_t
1177 lra_update_insn_recog_data (rtx_insn
*insn
)
1179 lra_insn_recog_data_t data
;
1181 unsigned int uid
= INSN_UID (insn
);
1182 struct lra_static_insn_data
*insn_static_data
;
1183 HOST_WIDE_INT sp_offset
= 0;
1185 check_and_expand_insn_recog_data (uid
);
1186 if ((data
= lra_insn_recog_data
[uid
]) != NULL
1187 && data
->icode
!= INSN_CODE (insn
))
1189 sp_offset
= data
->sp_offset
;
1190 invalidate_insn_data_regno_info (data
, insn
, get_insn_freq (insn
));
1191 invalidate_insn_recog_data (uid
);
1196 data
= lra_get_insn_recog_data (insn
);
1197 /* Initiate or restore SP offset. */
1198 data
->sp_offset
= sp_offset
;
1201 insn_static_data
= data
->insn_static_data
;
1202 data
->used_insn_alternative
= -1;
1203 if (DEBUG_INSN_P (insn
))
1205 if (data
->icode
< 0)
1208 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1209 const char *constraints
[MAX_RECOG_OPERANDS
];
1211 nop
= asm_noperands (PATTERN (insn
));
1214 lra_assert (nop
== data
->insn_static_data
->n_operands
);
1215 /* Now get the operand values and constraints out of the
1217 decode_asm_operands (PATTERN (insn
), NULL
,
1219 constraints
, operand_mode
, NULL
);
1220 #ifdef ENABLE_CHECKING
1224 for (i
= 0; i
< nop
; i
++)
1226 (insn_static_data
->operand
[i
].mode
== operand_mode
[i
]
1227 && insn_static_data
->operand
[i
].constraint
== constraints
[i
]
1228 && ! insn_static_data
->operand
[i
].is_operator
);
1232 #ifdef ENABLE_CHECKING
1236 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1238 (insn_static_data
->operand
[i
].type
1239 == (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1240 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1247 insn_extract (insn
);
1248 n
= insn_static_data
->n_operands
;
1250 memcpy (data
->operand_loc
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1251 n
= insn_static_data
->n_dups
;
1253 memcpy (data
->dup_loc
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1254 lra_assert (check_bool_attrs (insn
));
1259 /* Set up that INSN is using alternative ALT now. */
1261 lra_set_used_insn_alternative (rtx_insn
*insn
, int alt
)
1263 lra_insn_recog_data_t data
;
1265 data
= lra_get_insn_recog_data (insn
);
1266 data
->used_insn_alternative
= alt
;
1269 /* Set up that insn with UID is using alternative ALT now. The insn
1270 info should be already set up. */
1272 lra_set_used_insn_alternative_by_uid (int uid
, int alt
)
1274 lra_insn_recog_data_t data
;
1276 check_and_expand_insn_recog_data (uid
);
1277 data
= lra_insn_recog_data
[uid
];
1278 lra_assert (data
!= NULL
);
1279 data
->used_insn_alternative
= alt
;
1284 /* This page contains code dealing with common register info and
1287 /* The size of the following array. */
1288 static int reg_info_size
;
1289 /* Common info about each register. */
1290 struct lra_reg
*lra_reg_info
;
1292 /* Last register value. */
1293 static int last_reg_value
;
1295 /* Return new register value. */
1297 get_new_reg_value (void)
1299 return ++last_reg_value
;
1302 /* Pools for copies. */
1303 static alloc_pool copy_pool
;
1305 /* Vec referring to pseudo copies. */
1306 static vec
<lra_copy_t
> copy_vec
;
1308 /* Initialize I-th element of lra_reg_info. */
1310 initialize_lra_reg_info_element (int i
)
1312 bitmap_initialize (&lra_reg_info
[i
].insn_bitmap
, ®_obstack
);
1314 lra_reg_info
[i
].no_stack_p
= false;
1316 CLEAR_HARD_REG_SET (lra_reg_info
[i
].conflict_hard_regs
);
1317 CLEAR_HARD_REG_SET (lra_reg_info
[i
].actual_call_used_reg_set
);
1318 lra_reg_info
[i
].preferred_hard_regno1
= -1;
1319 lra_reg_info
[i
].preferred_hard_regno2
= -1;
1320 lra_reg_info
[i
].preferred_hard_regno_profit1
= 0;
1321 lra_reg_info
[i
].preferred_hard_regno_profit2
= 0;
1322 lra_reg_info
[i
].biggest_mode
= VOIDmode
;
1323 lra_reg_info
[i
].live_ranges
= NULL
;
1324 lra_reg_info
[i
].nrefs
= lra_reg_info
[i
].freq
= 0;
1325 lra_reg_info
[i
].last_reload
= 0;
1326 lra_reg_info
[i
].restore_regno
= -1;
1327 lra_reg_info
[i
].val
= get_new_reg_value ();
1328 lra_reg_info
[i
].offset
= 0;
1329 lra_reg_info
[i
].copies
= NULL
;
1332 /* Initialize common reg info and copies. */
1334 init_reg_info (void)
1339 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1340 lra_reg_info
= XNEWVEC (struct lra_reg
, reg_info_size
);
1341 for (i
= 0; i
< reg_info_size
; i
++)
1342 initialize_lra_reg_info_element (i
);
1344 = create_alloc_pool ("lra copies", sizeof (struct lra_copy
), 100);
1345 copy_vec
.create (100);
1349 /* Finish common reg info and copies. */
1351 finish_reg_info (void)
1355 for (i
= 0; i
< reg_info_size
; i
++)
1356 bitmap_clear (&lra_reg_info
[i
].insn_bitmap
);
1357 free (lra_reg_info
);
1359 free_alloc_pool (copy_pool
);
1360 copy_vec
.release ();
1363 /* Expand common reg info if it is necessary. */
1365 expand_reg_info (void)
1367 int i
, old
= reg_info_size
;
1369 if (reg_info_size
> max_reg_num ())
1371 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1372 lra_reg_info
= XRESIZEVEC (struct lra_reg
, lra_reg_info
, reg_info_size
);
1373 for (i
= old
; i
< reg_info_size
; i
++)
1374 initialize_lra_reg_info_element (i
);
1377 /* Free all copies. */
1379 lra_free_copies (void)
1383 while (copy_vec
.length () != 0)
1385 cp
= copy_vec
.pop ();
1386 lra_reg_info
[cp
->regno1
].copies
= lra_reg_info
[cp
->regno2
].copies
= NULL
;
1387 pool_free (copy_pool
, cp
);
1391 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1392 frequency is FREQ. */
1394 lra_create_copy (int regno1
, int regno2
, int freq
)
1399 lra_assert (regno1
!= regno2
);
1400 regno1_dest_p
= true;
1401 if (regno1
> regno2
)
1405 regno1_dest_p
= false;
1409 cp
= (lra_copy_t
) pool_alloc (copy_pool
);
1410 copy_vec
.safe_push (cp
);
1411 cp
->regno1_dest_p
= regno1_dest_p
;
1413 cp
->regno1
= regno1
;
1414 cp
->regno2
= regno2
;
1415 cp
->regno1_next
= lra_reg_info
[regno1
].copies
;
1416 lra_reg_info
[regno1
].copies
= cp
;
1417 cp
->regno2_next
= lra_reg_info
[regno2
].copies
;
1418 lra_reg_info
[regno2
].copies
= cp
;
1419 if (lra_dump_file
!= NULL
)
1420 fprintf (lra_dump_file
, " Creating copy r%d%sr%d@%d\n",
1421 regno1
, regno1_dest_p
? "<-" : "->", regno2
, freq
);
1424 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1427 lra_get_copy (int n
)
1429 if (n
>= (int) copy_vec
.length ())
1436 /* This page contains code dealing with info about registers in
1439 /* Process X of insn UID recursively and add info (operand type is
1440 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1441 about registers in X to the insn DATA. */
1443 add_regs_to_insn_regno_info (lra_insn_recog_data_t data
, rtx x
, int uid
,
1444 enum op_type type
, bool early_clobber
)
1451 struct lra_insn_reg
*curr
;
1453 code
= GET_CODE (x
);
1454 mode
= GET_MODE (x
);
1456 if (GET_CODE (x
) == SUBREG
)
1459 code
= GET_CODE (x
);
1460 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
)))
1462 mode
= GET_MODE (x
);
1463 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
1470 /* Process all regs even unallocatable ones as we need info about
1471 all regs for rematerialization pass. */
1473 if (bitmap_set_bit (&lra_reg_info
[regno
].insn_bitmap
, uid
))
1475 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
1476 early_clobber
, data
->regs
);
1481 for (curr
= data
->regs
; curr
!= NULL
; curr
= curr
->next
)
1482 if (curr
->regno
== regno
)
1484 if (curr
->subreg_p
!= subreg_p
|| curr
->biggest_mode
!= mode
)
1485 /* The info can not be integrated into the found
1487 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
,
1488 subreg_p
, early_clobber
,
1492 if (curr
->type
!= type
)
1493 curr
->type
= OP_INOUT
;
1494 if (curr
->early_clobber
!= early_clobber
)
1495 curr
->early_clobber
= true;
1506 add_regs_to_insn_regno_info (data
, SET_DEST (x
), uid
, OP_OUT
, false);
1507 add_regs_to_insn_regno_info (data
, SET_SRC (x
), uid
, OP_IN
, false);
1510 /* We treat clobber of non-operand hard registers as early
1511 clobber (the behavior is expected from asm). */
1512 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_OUT
, true);
1514 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1515 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1517 case PRE_MODIFY
: case POST_MODIFY
:
1518 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1519 add_regs_to_insn_regno_info (data
, XEXP (x
, 1), uid
, OP_IN
, false);
1522 if ((code
!= PARALLEL
&& code
!= EXPR_LIST
) || type
!= OP_OUT
)
1523 /* Some targets place small structures in registers for return
1524 values of functions, and those registers are wrapped in
1525 PARALLEL that we may see as the destination of a SET. Here
1528 (call_insn 13 12 14 2 (set (parallel:BLK [
1529 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1531 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1532 (const_int 8 [0x8]))
1534 (call (mem:QI (symbol_ref:DI (... */
1536 fmt
= GET_RTX_FORMAT (code
);
1537 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1540 add_regs_to_insn_regno_info (data
, XEXP (x
, i
), uid
, type
, false);
1541 else if (fmt
[i
] == 'E')
1543 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1544 add_regs_to_insn_regno_info (data
, XVECEXP (x
, i
, j
), uid
,
1551 /* Return execution frequency of INSN. */
1553 get_insn_freq (rtx_insn
*insn
)
1555 basic_block bb
= BLOCK_FOR_INSN (insn
);
1557 gcc_checking_assert (bb
!= NULL
);
1558 return REG_FREQ_FROM_BB (bb
);
1561 /* Invalidate all reg info of INSN with DATA and execution frequency
1562 FREQ. Update common info about the invalidated registers. */
1564 invalidate_insn_data_regno_info (lra_insn_recog_data_t data
, rtx_insn
*insn
,
1570 struct lra_insn_reg
*ir
, *next_ir
;
1572 uid
= INSN_UID (insn
);
1573 debug_p
= DEBUG_INSN_P (insn
);
1574 for (ir
= data
->regs
; ir
!= NULL
; ir
= next_ir
)
1579 bitmap_clear_bit (&lra_reg_info
[i
].insn_bitmap
, uid
);
1580 if (i
>= FIRST_PSEUDO_REGISTER
&& ! debug_p
)
1582 lra_reg_info
[i
].nrefs
--;
1583 lra_reg_info
[i
].freq
-= freq
;
1584 lra_assert (lra_reg_info
[i
].nrefs
>= 0 && lra_reg_info
[i
].freq
>= 0);
1590 /* Invalidate all reg info of INSN. Update common info about the
1591 invalidated registers. */
1593 lra_invalidate_insn_regno_info (rtx_insn
*insn
)
1595 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn
), insn
,
1596 get_insn_freq (insn
));
1599 /* Update common reg info from reg info of insn given by its DATA and
1600 execution frequency FREQ. */
1602 setup_insn_reg_info (lra_insn_recog_data_t data
, int freq
)
1605 struct lra_insn_reg
*ir
;
1607 for (ir
= data
->regs
; ir
!= NULL
; ir
= ir
->next
)
1608 if ((i
= ir
->regno
) >= FIRST_PSEUDO_REGISTER
)
1610 lra_reg_info
[i
].nrefs
++;
1611 lra_reg_info
[i
].freq
+= freq
;
1615 /* Set up insn reg info of INSN. Update common reg info from reg info
1618 lra_update_insn_regno_info (rtx_insn
*insn
)
1621 lra_insn_recog_data_t data
;
1622 struct lra_static_insn_data
*static_data
;
1625 if (! INSN_P (insn
))
1627 data
= lra_get_insn_recog_data (insn
);
1628 static_data
= data
->insn_static_data
;
1629 freq
= get_insn_freq (insn
);
1630 invalidate_insn_data_regno_info (data
, insn
, freq
);
1631 uid
= INSN_UID (insn
);
1632 for (i
= static_data
->n_operands
- 1; i
>= 0; i
--)
1633 add_regs_to_insn_regno_info (data
, *data
->operand_loc
[i
], uid
,
1634 static_data
->operand
[i
].type
,
1635 static_data
->operand
[i
].early_clobber
);
1636 if ((code
= GET_CODE (PATTERN (insn
))) == CLOBBER
|| code
== USE
)
1637 add_regs_to_insn_regno_info (data
, XEXP (PATTERN (insn
), 0), uid
,
1638 code
== USE
? OP_IN
: OP_OUT
, false);
1639 if (NONDEBUG_INSN_P (insn
))
1640 setup_insn_reg_info (data
, freq
);
1643 /* Return reg info of insn given by it UID. */
1644 struct lra_insn_reg
*
1645 lra_get_insn_regs (int uid
)
1647 lra_insn_recog_data_t data
;
1649 data
= get_insn_recog_data_by_uid (uid
);
1655 /* This page contains code dealing with stack of the insns which
1656 should be processed by the next constraint pass. */
1658 /* Bitmap used to put an insn on the stack only in one exemplar. */
1659 static sbitmap lra_constraint_insn_stack_bitmap
;
1661 /* The stack itself. */
1662 vec
<rtx_insn
*> lra_constraint_insn_stack
;
1664 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1665 info for INSN, otherwise only update it if INSN is not already on the
1668 lra_push_insn_1 (rtx_insn
*insn
, bool always_update
)
1670 unsigned int uid
= INSN_UID (insn
);
1672 lra_update_insn_regno_info (insn
);
1673 if (uid
>= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap
))
1674 lra_constraint_insn_stack_bitmap
=
1675 sbitmap_resize (lra_constraint_insn_stack_bitmap
, 3 * uid
/ 2, 0);
1676 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap
, uid
))
1678 bitmap_set_bit (lra_constraint_insn_stack_bitmap
, uid
);
1679 if (! always_update
)
1680 lra_update_insn_regno_info (insn
);
1681 lra_constraint_insn_stack
.safe_push (insn
);
1684 /* Put INSN on the stack. */
1686 lra_push_insn (rtx_insn
*insn
)
1688 lra_push_insn_1 (insn
, false);
1691 /* Put INSN on the stack and update its reg info. */
1693 lra_push_insn_and_update_insn_regno_info (rtx_insn
*insn
)
1695 lra_push_insn_1 (insn
, true);
1698 /* Put insn with UID on the stack. */
1700 lra_push_insn_by_uid (unsigned int uid
)
1702 lra_push_insn (lra_insn_recog_data
[uid
]->insn
);
1705 /* Take the last-inserted insns off the stack and return it. */
1709 rtx_insn
*insn
= lra_constraint_insn_stack
.pop ();
1710 bitmap_clear_bit (lra_constraint_insn_stack_bitmap
, INSN_UID (insn
));
1714 /* Return the current size of the insn stack. */
1716 lra_insn_stack_length (void)
1718 return lra_constraint_insn_stack
.length ();
1721 /* Push insns FROM to TO (excluding it) going in reverse order. */
1723 push_insns (rtx_insn
*from
, rtx_insn
*to
)
1727 if (from
== NULL_RTX
)
1729 for (insn
= from
; insn
!= to
; insn
= PREV_INSN (insn
))
1731 lra_push_insn (insn
);
1734 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
1735 taken from the next BB insn after LAST or zero if there in such
1738 setup_sp_offset (rtx_insn
*from
, rtx_insn
*last
)
1740 rtx_insn
*before
= next_nonnote_insn_bb (last
);
1741 HOST_WIDE_INT offset
= (before
== NULL_RTX
|| ! INSN_P (before
)
1742 ? 0 : lra_get_insn_recog_data (before
)->sp_offset
);
1744 for (rtx_insn
*insn
= from
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
1745 lra_get_insn_recog_data (insn
)->sp_offset
= offset
;
1748 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1749 insns onto the stack. Print about emitting the insns with
1752 lra_process_new_insns (rtx_insn
*insn
, rtx_insn
*before
, rtx_insn
*after
,
1757 if (before
== NULL_RTX
&& after
== NULL_RTX
)
1759 if (lra_dump_file
!= NULL
)
1761 dump_insn_slim (lra_dump_file
, insn
);
1762 if (before
!= NULL_RTX
)
1764 fprintf (lra_dump_file
," %s before:\n", title
);
1765 dump_rtl_slim (lra_dump_file
, before
, NULL
, -1, 0);
1767 if (after
!= NULL_RTX
)
1769 fprintf (lra_dump_file
, " %s after:\n", title
);
1770 dump_rtl_slim (lra_dump_file
, after
, NULL
, -1, 0);
1772 fprintf (lra_dump_file
, "\n");
1774 if (before
!= NULL_RTX
)
1776 emit_insn_before (before
, insn
);
1777 push_insns (PREV_INSN (insn
), PREV_INSN (before
));
1778 setup_sp_offset (before
, PREV_INSN (insn
));
1780 if (after
!= NULL_RTX
)
1782 for (last
= after
; NEXT_INSN (last
) != NULL_RTX
; last
= NEXT_INSN (last
))
1784 emit_insn_after (after
, insn
);
1785 push_insns (last
, insn
);
1786 setup_sp_offset (after
, last
);
1792 /* Replace all references to register OLD_REGNO in *LOC with pseudo
1793 register NEW_REG. Return true if any change was made. */
1795 lra_substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
1798 bool result
= false;
1806 code
= GET_CODE (x
);
1807 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
1809 machine_mode mode
= GET_MODE (*loc
);
1810 machine_mode inner_mode
= GET_MODE (new_reg
);
1812 if (mode
!= inner_mode
1813 && ! (CONST_INT_P (new_reg
) && SCALAR_INT_MODE_P (mode
)))
1815 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
1816 || ! SCALAR_INT_MODE_P (inner_mode
))
1817 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
1819 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
1825 /* Scan all the operand sub-expressions. */
1826 fmt
= GET_RTX_FORMAT (code
);
1827 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1831 if (lra_substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
1834 else if (fmt
[i
] == 'E')
1836 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1837 if (lra_substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
1844 /* Call lra_substitute_pseudo within an insn. This won't update the insn ptr,
1845 just the contents of the insn. */
1847 lra_substitute_pseudo_within_insn (rtx_insn
*insn
, int old_regno
, rtx new_reg
)
1850 return lra_substitute_pseudo (&loc
, old_regno
, new_reg
);
1855 /* This page contains code dealing with scratches (changing them onto
1856 pseudos and restoring them from the pseudos).
1858 We change scratches into pseudos at the beginning of LRA to
1859 simplify dealing with them (conflicts, hard register assignments).
1861 If the pseudo denoting scratch was spilled it means that we do need
1862 a hard register for it. Such pseudos are transformed back to
1863 scratches at the end of LRA. */
1865 /* Description of location of a former scratch operand. */
1868 rtx_insn
*insn
; /* Insn where the scratch was. */
1869 int nop
; /* Number of the operand which was a scratch. */
1872 typedef struct sloc
*sloc_t
;
1874 /* Locations of the former scratches. */
1875 static vec
<sloc_t
> scratches
;
1877 /* Bitmap of scratch regnos. */
1878 static bitmap_head scratch_bitmap
;
1880 /* Bitmap of scratch operands. */
1881 static bitmap_head scratch_operand_bitmap
;
1883 /* Return true if pseudo REGNO is made of SCRATCH. */
1885 lra_former_scratch_p (int regno
)
1887 return bitmap_bit_p (&scratch_bitmap
, regno
);
1890 /* Return true if the operand NOP of INSN is a former scratch. */
1892 lra_former_scratch_operand_p (rtx_insn
*insn
, int nop
)
1894 return bitmap_bit_p (&scratch_operand_bitmap
,
1895 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
) != 0;
1898 /* Change scratches onto pseudos and save their location. */
1900 remove_scratches (void)
1903 bool insn_changed_p
;
1908 lra_insn_recog_data_t id
;
1909 struct lra_static_insn_data
*static_id
;
1911 scratches
.create (get_max_uid ());
1912 bitmap_initialize (&scratch_bitmap
, ®_obstack
);
1913 bitmap_initialize (&scratch_operand_bitmap
, ®_obstack
);
1914 FOR_EACH_BB_FN (bb
, cfun
)
1915 FOR_BB_INSNS (bb
, insn
)
1918 id
= lra_get_insn_recog_data (insn
);
1919 static_id
= id
->insn_static_data
;
1920 insn_changed_p
= false;
1921 for (i
= 0; i
< static_id
->n_operands
; i
++)
1922 if (GET_CODE (*id
->operand_loc
[i
]) == SCRATCH
1923 && GET_MODE (*id
->operand_loc
[i
]) != VOIDmode
)
1925 insn_changed_p
= true;
1926 *id
->operand_loc
[i
] = reg
1927 = lra_create_new_reg (static_id
->operand
[i
].mode
,
1928 *id
->operand_loc
[i
], ALL_REGS
, NULL
);
1929 add_reg_note (insn
, REG_UNUSED
, reg
);
1930 lra_update_dup (id
, i
);
1931 loc
= XNEW (struct sloc
);
1934 scratches
.safe_push (loc
);
1935 bitmap_set_bit (&scratch_bitmap
, REGNO (*id
->operand_loc
[i
]));
1936 bitmap_set_bit (&scratch_operand_bitmap
,
1937 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ i
);
1938 if (lra_dump_file
!= NULL
)
1939 fprintf (lra_dump_file
,
1940 "Removing SCRATCH in insn #%u (nop %d)\n",
1941 INSN_UID (insn
), i
);
1944 /* Because we might use DF right after caller-saves sub-pass
1945 we need to keep DF info up to date. */
1946 df_insn_rescan (insn
);
1950 /* Changes pseudos created by function remove_scratches onto scratches. */
1952 restore_scratches (void)
1957 rtx_insn
*last
= NULL
;
1958 lra_insn_recog_data_t id
= NULL
;
1960 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
1962 if (last
!= loc
->insn
)
1965 id
= lra_get_insn_recog_data (last
);
1967 if (REG_P (*id
->operand_loc
[loc
->nop
])
1968 && ((regno
= REGNO (*id
->operand_loc
[loc
->nop
]))
1969 >= FIRST_PSEUDO_REGISTER
)
1970 && lra_get_regno_hard_regno (regno
) < 0)
1972 /* It should be only case when scratch register with chosen
1973 constraint 'X' did not get memory or hard register. */
1974 lra_assert (lra_former_scratch_p (regno
));
1975 *id
->operand_loc
[loc
->nop
]
1976 = gen_rtx_SCRATCH (GET_MODE (*id
->operand_loc
[loc
->nop
]));
1977 lra_update_dup (id
, loc
->nop
);
1978 if (lra_dump_file
!= NULL
)
1979 fprintf (lra_dump_file
, "Restoring SCRATCH in insn #%u(nop %d)\n",
1980 INSN_UID (loc
->insn
), loc
->nop
);
1983 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
1985 scratches
.release ();
1986 bitmap_clear (&scratch_bitmap
);
1987 bitmap_clear (&scratch_operand_bitmap
);
1992 #ifdef ENABLE_CHECKING
1994 /* Function checks RTL for correctness. If FINAL_P is true, it is
1995 done at the end of LRA and the check is more rigorous. */
1997 check_rtl (bool final_p
)
2002 lra_assert (! final_p
|| reload_completed
);
2003 FOR_EACH_BB_FN (bb
, cfun
)
2004 FOR_BB_INSNS (bb
, insn
)
2005 if (NONDEBUG_INSN_P (insn
)
2006 && GET_CODE (PATTERN (insn
)) != USE
2007 && GET_CODE (PATTERN (insn
)) != CLOBBER
2008 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
2012 #ifdef ENABLED_CHECKING
2013 extract_constrain_insn (insn
);
2017 /* LRA code is based on assumption that all addresses can be
2018 correctly decomposed. LRA can generate reloads for
2019 decomposable addresses. The decomposition code checks the
2020 correctness of the addresses. So we don't need to check
2021 the addresses here. Don't call insn_invalid_p here, it can
2022 change the code at this stage. */
2023 if (recog_memoized (insn
) < 0 && asm_noperands (PATTERN (insn
)) < 0)
2024 fatal_insn_not_found (insn
);
2027 #endif /* #ifdef ENABLE_CHECKING */
2029 /* Determine if the current function has an exception receiver block
2030 that reaches the exit block via non-exceptional edges */
2032 has_nonexceptional_receiver (void)
2036 basic_block
*tos
, *worklist
, bb
;
2038 /* If we're not optimizing, then just err on the safe side. */
2042 /* First determine which blocks can reach exit via normal paths. */
2043 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
2045 FOR_EACH_BB_FN (bb
, cfun
)
2046 bb
->flags
&= ~BB_REACHABLE
;
2048 /* Place the exit block on our worklist. */
2049 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
2050 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
2052 /* Iterate: find everything reachable from what we've already seen. */
2053 while (tos
!= worklist
)
2057 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
2058 if (e
->flags
& EDGE_ABNORMAL
)
2065 basic_block src
= e
->src
;
2067 if (!(src
->flags
& BB_REACHABLE
))
2069 src
->flags
|= BB_REACHABLE
;
2075 /* No exceptional block reached exit unexceptionally. */
2081 /* Process recursively X of INSN and add REG_INC notes if necessary. */
2083 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
2085 enum rtx_code code
= GET_CODE (x
);
2089 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
2091 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
2095 /* Scan all X sub-expressions. */
2096 fmt
= GET_RTX_FORMAT (code
);
2097 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2100 add_auto_inc_notes (insn
, XEXP (x
, i
));
2101 else if (fmt
[i
] == 'E')
2102 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2103 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
2109 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2110 We change pseudos by hard registers without notification of DF and
2111 that can make the notes obsolete. DF-infrastructure does not deal
2112 with REG_INC notes -- so we should regenerate them here. */
2114 update_inc_notes (void)
2120 FOR_EACH_BB_FN (bb
, cfun
)
2121 FOR_BB_INSNS (bb
, insn
)
2122 if (NONDEBUG_INSN_P (insn
))
2124 pnote
= ®_NOTES (insn
);
2127 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
2128 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
2129 || REG_NOTE_KIND (*pnote
) == REG_INC
)
2130 *pnote
= XEXP (*pnote
, 1);
2132 pnote
= &XEXP (*pnote
, 1);
2135 add_auto_inc_notes (insn
, PATTERN (insn
));
2140 /* Set to 1 while in lra. */
2141 int lra_in_progress
;
2143 /* Start of pseudo regnos before the LRA. */
2144 int lra_new_regno_start
;
2146 /* Start of reload pseudo regnos before the new spill pass. */
2147 int lra_constraint_new_regno_start
;
2149 /* Inheritance pseudo regnos before the new spill pass. */
2150 bitmap_head lra_inheritance_pseudos
;
2152 /* Split regnos before the new spill pass. */
2153 bitmap_head lra_split_regs
;
2155 /* Reload pseudo regnos before the new assignmnet pass which still can
2156 be spilled after the assinment pass as memory is also accepted in
2157 insns for the reload pseudos. */
2158 bitmap_head lra_optional_reload_pseudos
;
2160 /* Pseudo regnos used for subreg reloads before the new assignment
2161 pass. Such pseudos still can be spilled after the assinment
2163 bitmap_head lra_subreg_reload_pseudos
;
2165 /* File used for output of LRA debug information. */
2166 FILE *lra_dump_file
;
2168 /* True if we should try spill into registers of different classes
2169 instead of memory. */
2170 bool lra_reg_spill_p
;
2172 /* Set up value LRA_REG_SPILL_P. */
2174 setup_reg_spill_flag (void)
2178 if (targetm
.spill_class
!= NULL
)
2179 for (cl
= 0; cl
< (int) LIM_REG_CLASSES
; cl
++)
2180 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
2181 if (targetm
.spill_class ((enum reg_class
) cl
,
2182 (machine_mode
) mode
) != NO_REGS
)
2184 lra_reg_spill_p
= true;
2187 lra_reg_spill_p
= false;
2190 /* True if the current function is too big to use regular algorithms
2191 in LRA. In other words, we should use simpler and faster algorithms
2192 in LRA. It also means we should not worry about generation code
2193 for caller saves. The value is set up in IRA. */
2196 /* Major LRA entry function. F is a file should be used to dump LRA
2202 bool live_p
, scratch_p
, inserted_p
;
2206 timevar_push (TV_LRA
);
2208 /* Make sure that the last insn is a note. Some subsequent passes
2210 emit_note (NOTE_INSN_DELETED
);
2212 COPY_HARD_REG_SET (lra_no_alloc_regs
, ira_no_alloc_regs
);
2217 init_insn_recog_data ();
2219 #ifdef ENABLE_CHECKING
2220 /* Some quick check on RTL generated by previous passes. */
2224 lra_in_progress
= 1;
2226 lra_live_range_iter
= lra_coalesce_iter
= lra_constraint_iter
= 0;
2227 lra_assignment_iter
= lra_assignment_iter_after_spill
= 0;
2228 lra_inheritance_iter
= lra_undo_inheritance_iter
= 0;
2230 setup_reg_spill_flag ();
2232 /* Function remove_scratches can creates new pseudos for clobbers --
2233 so set up lra_constraint_new_regno_start before its call to
2234 permit changing reg classes for pseudos created by this
2236 lra_constraint_new_regno_start
= lra_new_regno_start
= max_reg_num ();
2237 remove_scratches ();
2238 scratch_p
= lra_constraint_new_regno_start
!= max_reg_num ();
2240 /* A function that has a non-local label that can reach the exit
2241 block via non-exceptional paths must save all call-saved
2243 if (cfun
->has_nonlocal_label
&& has_nonexceptional_receiver ())
2244 crtl
->saves_all_registers
= 1;
2246 if (crtl
->saves_all_registers
)
2247 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2248 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
2249 df_set_regs_ever_live (i
, true);
2251 /* We don't DF from now and avoid its using because it is to
2252 expensive when a lot of RTL changes are made. */
2253 df_set_flags (DF_NO_INSN_RESCAN
);
2254 lra_constraint_insn_stack
.create (get_max_uid ());
2255 lra_constraint_insn_stack_bitmap
= sbitmap_alloc (get_max_uid ());
2256 bitmap_clear (lra_constraint_insn_stack_bitmap
);
2257 lra_live_ranges_init ();
2258 lra_constraints_init ();
2259 lra_curr_reload_num
= 0;
2260 push_insns (get_last_insn (), NULL
);
2261 /* It is needed for the 1st coalescing. */
2262 bitmap_initialize (&lra_inheritance_pseudos
, ®_obstack
);
2263 bitmap_initialize (&lra_split_regs
, ®_obstack
);
2264 bitmap_initialize (&lra_optional_reload_pseudos
, ®_obstack
);
2265 bitmap_initialize (&lra_subreg_reload_pseudos
, ®_obstack
);
2267 if (get_frame_size () != 0 && crtl
->stack_alignment_needed
)
2268 /* If we have a stack frame, we must align it now. The stack size
2269 may be a part of the offset computation for register
2271 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
2277 /* We should try to assign hard registers to scratches even
2278 if there were no RTL transformations in
2280 if (! lra_constraints (lra_constraint_iter
== 0)
2281 && (lra_constraint_iter
> 1
2282 || (! scratch_p
&& ! caller_save_needed
)))
2284 /* Constraint transformations may result in that eliminable
2285 hard regs become uneliminable and pseudos which use them
2286 should be spilled. It is better to do it before pseudo
2289 For example, rs6000 can make
2290 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2291 to use a constant pool. */
2292 lra_eliminate (false, false);
2293 /* Do inheritance only for regular algorithms. */
2299 lra_clear_live_ranges ();
2300 /* As a side-effect of lra_create_live_ranges, we calculate
2301 actual_call_used_reg_set, which is needed during
2303 lra_create_live_ranges (true, true);
2309 lra_clear_live_ranges ();
2310 /* We need live ranges for lra_assign -- so build them. But
2311 don't remove dead insns or change global live info as we
2312 can undo inheritance transformations after inheritance
2313 pseudo assigning. */
2314 lra_create_live_ranges (true, false);
2316 /* If we don't spill non-reload and non-inheritance pseudos,
2317 there is no sense to run memory-memory move coalescing.
2318 If inheritance pseudos were spilled, the memory-memory
2319 moves involving them will be removed by pass undoing
2325 bool spill_p
= !lra_assign ();
2327 if (lra_undo_inheritance ())
2333 lra_create_live_ranges (true, true);
2336 if (lra_coalesce ())
2340 lra_clear_live_ranges ();
2343 /* Don't clear optional reloads bitmap until all constraints are
2344 satisfied as we need to differ them from regular reloads. */
2345 bitmap_clear (&lra_optional_reload_pseudos
);
2346 bitmap_clear (&lra_subreg_reload_pseudos
);
2347 bitmap_clear (&lra_inheritance_pseudos
);
2348 bitmap_clear (&lra_split_regs
);
2351 /* We need full live info for spilling pseudos into
2352 registers instead of memory. */
2353 lra_create_live_ranges (lra_reg_spill_p
, true);
2356 /* We should check necessity for spilling here as the above live
2357 range pass can remove spilled pseudos. */
2358 if (! lra_need_for_spills_p ())
2360 /* Now we know what pseudos should be spilled. Try to
2361 rematerialize them first. */
2364 /* We need full live info -- see the comment above. */
2365 lra_create_live_ranges (lra_reg_spill_p
, true);
2367 if (! lra_need_for_spills_p ())
2371 /* Assignment of stack slots changes elimination offsets for
2372 some eliminations. So update the offsets here. */
2373 lra_eliminate (false, false);
2374 lra_constraint_new_regno_start
= max_reg_num ();
2375 lra_assignment_iter_after_spill
= 0;
2377 restore_scratches ();
2378 lra_eliminate (true, false);
2379 lra_final_code_change ();
2380 lra_in_progress
= 0;
2382 lra_clear_live_ranges ();
2383 lra_live_ranges_finish ();
2384 lra_constraints_finish ();
2386 sbitmap_free (lra_constraint_insn_stack_bitmap
);
2387 lra_constraint_insn_stack
.release ();
2388 finish_insn_recog_data ();
2389 regstat_free_n_sets_and_refs ();
2391 reload_completed
= 1;
2392 update_inc_notes ();
2394 inserted_p
= fixup_abnormal_edges ();
2396 /* We've possibly turned single trapping insn into multiple ones. */
2397 if (cfun
->can_throw_non_call_exceptions
)
2400 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2401 bitmap_ones (blocks
);
2402 find_many_sub_basic_blocks (blocks
);
2403 sbitmap_free (blocks
);
2407 commit_edge_insertions ();
2409 /* Replacing pseudos with their memory equivalents might have
2410 created shared rtx. Subsequent passes would get confused
2411 by this, so unshare everything here. */
2412 unshare_all_rtl_again (get_insns ());
2414 #ifdef ENABLE_CHECKING
2418 timevar_pop (TV_LRA
);
2421 /* Called once per compiler to initialize LRA data once. */
2423 lra_init_once (void)
2425 init_insn_code_data_once ();
2428 /* Called once per compiler to finish LRA data which are initialize
2431 lra_finish_once (void)
2433 finish_insn_code_data_once ();